60463 lines
4.1 MiB
60463 lines
4.1 MiB
; --------------------------------------------------------------------------------
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; @Title: TMS570LS0xx On-Chip Peripherals
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; @Props: Released
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; @Author: MKR, BCA, MRO
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; @Changelog: 2013-03-13 MKR
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; 2019-03-29 MRO
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; @Manufacturer: TI - Texas Instruments
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; @Doc: tms570ls0332.pdf (Rev. SPNS186C, 2015-06-30)
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; tms570ls0232.pdf (Rev. SPNS242A, 2015-06-30)
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; tms570ls0714.pdf (Rev. SPNS226E, 2016-11-01)
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; tms570ls0914.pdf (Rev. SPNS225D, 2016-11-01)
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; spnz603b.pdf (Rev. SPNU603B, 2018-03)
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; spnz607a.pdf (Rev. SPNU607A, 2018-03)
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; spnz189.pdf (Rev. SPNZ189, 2012-09)
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; spnu517.pdf (Rev. SPNU517, 2012-09)
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; @Core: Cortex-R4, Cortex-R4F
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; @Chip: TMS570LS0232, TMS570LS0714-PGE, TMS570LS0714-PZ, TMS570LS0914-PGE
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; TMS570LS0914-PZ
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; @Copyright: (C) 1989-2019 Lauterbach GmbH, licensed for use with TRACE32(R) only
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; --------------------------------------------------------------------------------
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; $Id: pertms570ls0xx.per 10401 2019-04-03 16:34:46Z mkolodziejczyk $
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; Known problems
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; MODULE REGISTER DESCRIPTION
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; EPWM TBSTS CTRMAX misleading description (eventfld with read-only access)
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config 16. 8.
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sif (CORENAME()=="CORTEXR4F")
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tree "Core Registers (Cortex-R4F)"
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AUTOINDENT.PUSH
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AUTOINDENT.OFF
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width 0x8
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; --------------------------------------------------------------------------------
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; Identification registers
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; --------------------------------------------------------------------------------
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tree "ID Registers"
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rgroup c15:0x0--0x0
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line.long 0x0 "MIDR,Main ID Register"
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hexmask.long.byte 0x0 24.--31. 0x1 " IMPL ,Implementer code"
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bitfld.long 0x0 20.--23. " VAR ,Variant" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x0 16.--19. " ARCH , Architecture" "Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,ARMv7"
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textline " "
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hexmask.long.word 0x0 4.--15. 0x1 " PART ,Primary Part Number"
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bitfld.long 0x0 0.--3. " REV ,Revision Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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rgroup c15:0x100--0x100
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line.long 0x0 "CTR,Cache Type Register"
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bitfld.long 0x0 29.--31. " FORMAT ,Format" "Not ARMv7,Not ARMv7,Not ARMv7,Not ARMv7,ARMv7,Not ARMv7,Not ARMv7,Not ARMv7"
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bitfld.long 0x0 16.--19. " DMINLINE ,D-Cache Minimum Line Size" "1 word,2 words,4 words,8 words,16 words,32 words,64 words,128 words,256 words,512 words,1024 words,2048 words,4096 words,8192 words,16384 words,32768 words"
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bitfld.long 0x0 14.--15. " L1POLICY ,L1 Instruction cache policy" "Reserved,ASID,Virtual,Physical"
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textline " "
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bitfld.long 0x0 0.--3. " IMINLINE ,I-Cache Minimum Line Size" "1 word,2 words,4 words,8 words,16 words,32 words,64 words,128 words,256 words,512 words,1024 words,2048 words,4096 words,8192 words,16384 words,32768 words"
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rgroup c15:0x200--0x200
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line.long 0x0 "TCMSR,Tighly-Coupled Memory Status Register"
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bitfld.long 0x0 16.--19. " DTCMS ,Data Banks" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x0 0.--3. " ITCMS ,Instruction Banks" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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rgroup c15:0x400--0x400
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line.long 0x0 "MPUIR,MPU type register"
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hexmask.long.byte 0x00 8.--15. 1. " REGNUM ,Number of regions"
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bitfld.long 0x00 0. " TYPE ,Type of MPU regions" "Unified,Seperated"
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rgroup c15:0x500--0x500
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line.long 0x0 "MPIDR,Multiprocessor Affinity Register"
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hexmask.long.byte 0x00 16.--23. 1. " AFFL2 ,Affitnity Level 2"
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hexmask.long.byte 0x00 8.--15. 1. " AFFL1 ,Affitnity Level 1"
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hexmask.long.byte 0x00 0.--7. 1. " AFFL0 ,Affitnity Level 0"
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textline " "
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rgroup c15:0x0410++0x00
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line.long 0x00 "MMFR0,Memory Model Feature Register 0"
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bitfld.long 0x00 28.--31. " IT ,Instruction Type Support" "Reserved,Reserved,Reserved,Supported,?..."
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bitfld.long 0x00 24.--27. " FCSE ,Fast Context Switch Memory Mappings Support" "Reserved,Supported,?..."
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textline " "
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bitfld.long 0x00 20.--23. " ACR ,Auxiliary Control Register Support" "Reserved,Supported,?..."
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bitfld.long 0x00 16.--19. " TCM ,TCM and Associated DMA Support" "Not supported,?..."
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textline " "
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bitfld.long 0x00 12.--15. " CC_PLEA ,Cache Coherency With PLE Agent/Shared Memory Support" "Not supported,?..."
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bitfld.long 0x00 8.--11. " CC_CPUA ,Cache Coherency Support With CPU Agent/Shared Memory Support" "Not supported,?..."
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textline " "
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bitfld.long 0x00 4.--7. " PMSA ,Physical Memory System Architecture (PMSA) Support" "Not supported,?..."
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bitfld.long 0x00 0.--3. " VMSA ,Virtual Memory System Architecture (VMSA) Support" "Reserved,Reserved,Reserved,Supported,?..."
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rgroup c15:0x0510++0x00
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line.long 0x00 "MMFR1,Memory Model Feature Register 1"
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bitfld.long 0x00 28.--31. " BTB ,Branch Target Buffer Support" "Reserved,Reserved,Not required,?..."
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bitfld.long 0x00 24.--27. " L1TCO ,Test and Clean Operations on Data Cache/Harvard/Unified Architecture Support" "Not supported,?..."
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textline " "
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bitfld.long 0x00 20.--23. " L1UCMO ,L1 Cache/All Maintenance Operations/Unified Architecture Support" "Not supported,?..."
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bitfld.long 0x00 16.--19. " L1HCMO ,L1 Cache/All Maintenance Operations/Harvard Architecture Support" "Supported,?..."
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textline " "
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bitfld.long 0x00 12.--15. " L1UCLMOSW ,L1 Cache Line Maintenance Operations by Set and Way/Unified Architecture Support" "Not supported,?..."
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bitfld.long 0x00 8.--11. " L1HCLMOSW ,L1 Cache Line Maintenance Operations by Set and Way/Harvard Architecture Support" "Supported,?..."
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textline " "
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bitfld.long 0x00 4.--7. " L1UCLMOMVA ,L1 Cache Line Maintenance Operations by MVA/Unified Architecture Support" "Not supported,?..."
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bitfld.long 0x00 0.--3. " L1HCLMOMVA ,L1 Cache Line Maintenance Operations by MVA/Harvard Architecture" "Supported,?..."
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rgroup c15:0x0610++0x00
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line.long 0x00 "MMFR2,Memory Model Feature Register 2"
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bitfld.long 0x00 28.--31. " HAF ,Hardware Access Flag Support" "Not supported,?..."
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bitfld.long 0x00 24.--27. " WFI ,Wait for Interrupt Stalling Support" "Reserved,Supported,?..."
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textline " "
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bitfld.long 0x00 20.--23. " MBF ,Memory Barrier Operations Support" "Reserved,Reserved,Supported,?..."
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bitfld.long 0x00 16.--19. " UTLBMO ,TLB Maintenance Operations/Unified Architecture Support" "Not supported,?..."
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textline " "
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bitfld.long 0x00 12.--15. " HTLBMO ,TLB Maintenance Operations/Harvard Architecture Support" "Reserved,Reserved,Supported,?..."
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bitfld.long 0x00 8.--11. " HL1CMRO ,Cache Maintenance Range Operations/Harvard Architecture Support" "Not supported,?..."
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textline " "
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bitfld.long 0x00 4.--7. " HL1BPCRO ,Background Prefetch Cache Range Operations/Harvard Architecture Support" "Not supported,?..."
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bitfld.long 0x00 0.--3. " HL1FPCRO ,Foreground Prefetch Cache Range Operations/Harvard Architecture Support" "Not supported,?..."
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rgroup c15:0x0710++0x00
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line.long 0x00 "MMFR3,Memory Model Feature Register 3"
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bitfld.long 0x00 4.--7. " HCMOSW ,Invalidate Cache by Set and Way/Clean by Set and Way/Invalidate and Clean by Set and Way Support" "Reserved,Supported,?..."
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bitfld.long 0x00 0.--3. " HCMOMVA ,Invalidate Cache by MVA/Clean by MVA/Invalidate and Clean by MVA/Invalidate All Support" "Reserved,Supported,?..."
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rgroup c15:0x0020++0x00
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line.long 0x00 "ISAR0,Instruction Set Attribute Register 0"
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bitfld.long 0x00 24.--27. " DIVI ,Divide Instructions Support" "Not supported,?..."
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bitfld.long 0x00 20.--23. " DEBI ,Debug Instructions Support" "Reserved,Supported,?..."
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textline " "
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bitfld.long 0x00 16.--19. " CI ,Coprocessor Instructions Support" "Not supported,?..."
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bitfld.long 0x00 12.--15. " CBI ,Combined Compare and Branch Instructions Support" "Reserved,Supported,?..."
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textline " "
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bitfld.long 0x00 8.--11. " BI ,Bitfield Instructions Support" "Reserved,Supported,?..."
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bitfld.long 0x00 4.--7. " BCI ,Bit Counting Instructions Support" "Reserved,Supported,?..."
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textline " "
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bitfld.long 0x00 0.--3. " AI ,Atomic Load and Store Instructions Support" "Reserved,Supported,?..."
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rgroup c15:0x0120++0x00
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line.long 0x00 "ISAR1,Instruction Set Attribute Register 1"
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bitfld.long 0x00 28.--31. " JI ,Jazelle Instructions Support" "Reserved,Supported,?..."
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bitfld.long 0x00 24.--27. " INTI ,Instructions That Branch Between ARM and Thumb Code Support" "Reserved,Reserved,Supported,?..."
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textline " "
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bitfld.long 0x00 20.--23. " IMMI ,Immediate Instructions Support" "Reserved,Supported,?..."
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bitfld.long 0x00 16.--19. " ITEI ,If Then Instructions Support" "Reserved,Supported,?..."
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textline " "
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bitfld.long 0x00 12.--15. " EXTI ,Sign or Zero Extend Instructions Support" "Reserved,Reserved,Supported,?..."
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bitfld.long 0x00 8.--11. " E2I ,Exception 2 Instructions Support" "Reserved,Supported,?..."
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textline " "
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bitfld.long 0x00 4.--7. " E1I ,Exception 1 Instructions Support" "Reserved,Supported,?..."
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bitfld.long 0x00 0.--3. " ENDI ,Endianness Control Instructions Support" "Reserved,Supported,?..."
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rgroup c15:0x0220++0x00
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line.long 0x00 "ISAR2,Instruction Set Attribute Register 2"
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bitfld.long 0x00 28.--31. " RI ,Reversal Instructions Support" "Reserved,Reserved,Supported,?..."
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bitfld.long 0x00 24.--27. " PSRI ,PSR Instructions Support" "Reserved,Supported,?..."
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textline " "
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bitfld.long 0x00 20.--23. " UMI ,Advanced Unsigned Multiply Instructions Support" "Reserved,Reserved,Supported,?..."
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bitfld.long 0x00 16.--19. " SMI ,Advanced Signed Multiply Instructions Support" "Reserved,Reserved,Reserved,Supported,?..."
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textline " "
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bitfld.long 0x00 12.--15. " MI ,Multiply Instructions Support" "Reserved,Reserved,Supported,?..."
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bitfld.long 0x00 8.--11. " II ,Multi-Access Interruptible Instructions Support" "Supported,?..."
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textline " "
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bitfld.long 0x00 4.--7. " MHI ,Memory Hint Instructions Support" "Reserved,Reserved,Reserved,Supported,?..."
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bitfld.long 0x00 0.--3. " LSI ,Load and Store Instructions Support" "Reserved,Supported,?..."
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rgroup c15:0x0320++0x00
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line.long 0x00 "ISAR3,Instruction Set Attribute Register 3"
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bitfld.long 0x00 28.--31. " T2E ,Thumb-2 Extensions Support" "Reserved,Supported,?..."
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bitfld.long 0x00 24.--27. " NOPI ,True NOP Instructions Support" "Reserved,Supported,?..."
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textline " "
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bitfld.long 0x00 20.--23. " TCI ,Thumb Copy Instructions Support" "Reserved,Supported,?..."
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bitfld.long 0x00 16.--19. " TBI ,Table Branch Instructions Support" "Reserved,Reserved,Supported,?..."
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textline " "
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bitfld.long 0x00 12.--15. " SPI ,Synchronization Primitive Instructions Support" "Reserved,Reserved,Supported,?..."
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bitfld.long 0x00 8.--11. " SWII ,SWI Instructions Support" "Reserved,Supported,?..."
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textline " "
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bitfld.long 0x00 4.--7. " SIMDI ,Single Instruction Multiple Data (SIMD) Instructions Support" "Reserved,Reserved,Reserved,Supported,?..."
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bitfld.long 0x00 0.--3. " SI ,Saturate Instructions Support" "Reserved,Supported,?..."
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rgroup c15:0x0420++0x00
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line.long 0x00 "ISAR4,Instruction Set Attribute Register 4"
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bitfld.long 0x00 20.--23. " EI ,Exclusive Instructions Support" "Reserved,Supported,?..."
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bitfld.long 0x00 16.--19. " BI ,Barrier Instructions Support" "Reserved,Supported,?..."
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textline " "
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bitfld.long 0x00 12.--15. " SMII ,SMI Instructions Support" "Reserved,Supported,?..."
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bitfld.long 0x00 8.--11. " WBI ,Write-Back Instructions Support" "Reserved,Supported,?..."
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textline " "
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bitfld.long 0x00 4.--7. " WSI ,With-Shift Instructions Support" "Reserved,Reserved,Reserved,Reserved,Supported,?..."
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bitfld.long 0x00 0.--3. " UI ,Unprivileged Instructions Support" "Reserved,Reserved,Supported,?..."
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rgroup c15:0x0520++0x00
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line.long 0x00 "ISAR5,Instruction Set Attribute Registers 5 (Reserved)"
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rgroup c15:0x0620++0x00
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line.long 0x00 "ISAR6,Instruction Set Attribute Registers 6 (Reserved)"
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rgroup c15:0x0720++0x00
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line.long 0x00 "ISAR7,Instruction Set Attribute Registers 7 (Reserved)"
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rgroup c15:0x0010++0x00
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line.long 0x00 "ID_PFR0,Processor Feature Register 0"
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bitfld.long 0x00 12.--15. " STATE3 ,Thumb-2 Execution Environment (Thumb-2EE) Support" "Reserved,Supported,?..."
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bitfld.long 0x00 8.--11. " STATE2 ,Java Extension Interface Support" "Not supported,?..."
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bitfld.long 0x00 4.--7. " STATE1 ,Thumb Encoding Supported by the Processor Type" "Reserved,Reserved,Reserved,Supported,?..."
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textline " "
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bitfld.long 0x00 0.--3. " STATE0 ,ARM Instruction Set Support" "Reserved,Supported,?..."
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rgroup c15:0x0110++0x00
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line.long 0x00 "ID_PFR1,Processor Feature Register 1"
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bitfld.long 0x00 8.--11. " MPM ,Microcontroller Programmer's Model Support" "Supported,?..."
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bitfld.long 0x00 4.--7. " SE ,Security Extensions Architecture v1 Support" "Reserved,Supported,?..."
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bitfld.long 0x00 0.--3. " PM ,Standard ARMv4 Programmer's Model Support" "Reserved,Supported,?..."
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textline " "
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rgroup c15:0x0210++0x00
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line.long 0x00 "ID_DFR0,Debug Feature Register 0"
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bitfld.long 0x00 20.--23. " MDM_MM ,Microcontroller Debug Model Support" "Not supported,?..."
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bitfld.long 0x00 16.--19. " TDM_MM ,Trace Debug Model (Memory-Mapped) Support" "Reserved,Supported,?..."
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bitfld.long 0x00 12.--15. " TDM_CB ,Coprocessor-Based Trace Debug Model Support" "Not supported,?..."
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textline " "
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bitfld.long 0x00 8.--11. " CDM_MM ,Memory-Mapped Debug Model Support" "Reserved,Reserved,Reserved,Reserved,Supported,?..."
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bitfld.long 0x00 4.--7. " SDM_CB ,Secure Debug Model (Coprocessor) Support" "Not supported,?..."
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bitfld.long 0x00 0.--3. " CDM_CB ,Coprocessor Debug Model Support" "Not supported,?..."
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rgroup c15:0x0310++0x00
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line.long 0x00 "ID_AFR0,Auxiliary Feature Register 0"
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tree.end
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width 0x8
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tree "System Control and Configuration"
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group c15:0x1--0x1
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line.long 0x0 "SCTLR,Control Register"
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bitfld.long 0x0 31. " IE ,Instruction endianness" "Little,Big"
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bitfld.long 0x0 30. " TE ,Thumb exception enable" "ARM,Thumb"
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bitfld.long 0x0 29. " AFE ,Access Flag Enable" "Disable,Enable"
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bitfld.long 0x0 28. " TRE ,TEX remap enable" "Disable,Enable"
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bitfld.long 0x0 27. " NMFI ,Nonmaskable Fast Interrupt enable" "Disable,Enable"
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textline " "
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bitfld.long 0x0 25. " EE ,Exception endianess" "Little,Big"
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bitfld.long 0x0 24. " VE ,Vector Enable" "Disable,Vectored"
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bitfld.long 0x0 21. " FI ,Fast Interrupts enable" "Disable,Enable"
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bitfld.long 0x0 19. " DZ ,Divide by Zero exception bit" "Disable,Enable"
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bitfld.long 0x0 14. " RR ,Round-Robin bit" "Random,RRobin"
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bitfld.long 0x0 13. " V ,Base Location of Exception Registers" "0x00000000,0xFFFF0000"
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textline " "
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bitfld.long 0x0 12. " I ,Instruction Cache Enable" "Disable,Enable"
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bitfld.long 0x0 11. " Z ,Branch Prediction Enable" "Disable,Enable"
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bitfld.long 0x0 2. " C ,Enable data cache" "Disable,Enable"
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bitfld.long 0x0 1. " A ,Strict Alignment" "Disable,Enable"
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bitfld.long 0x0 0. " M ,MPU Enable" "Disable,Enable"
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textline " "
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group c15:0x101--0x101
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line.long 0x0 "ACTLR,Auxiliary Control Register"
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bitfld.long 0x00 31. " DICDI ,Disable Case C dual issue control" "Enable,Disable"
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bitfld.long 0x00 30. " DIB2DI ,Disable Case B2 dual issue control" "Enable,Disable"
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bitfld.long 0x00 29. " DIB1DI ,Disable Case B1 dual issue control" "Enable,Disable"
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textline " "
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bitfld.long 0x00 28. " DIADI ,Disable Case A dual issue control" "Enable,Disable"
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bitfld.long 0x00 27. " B1TCMPCEN ,B1TCM parity or ECC check enable" "Disable,Enable"
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bitfld.long 0x00 26. " B0TCMPCEN ,B1TCM parity or ECC check enable" "Disable,Enable"
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textline " "
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bitfld.long 0x00 25. " ATCMPCEN ,B1TCM parity or ECC check enable" "Disable,Enable"
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bitfld.long 0x00 24. " AXISCEN ,AXI slave cache access enable" "Disable,Enable"
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bitfld.long 0x00 23. " AXISCUEN ,AXI slave cache User mode access enable" "Disable,Enable"
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textline " "
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bitfld.long 0x00 22. " DILSM ,Disable LIL on load/store multiples" "Disable,Enable"
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bitfld.long 0x00 21. " DEOLP ,Disable end of loop prediction" "Disable,Enable"
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bitfld.long 0x00 20. " DBHE ,Disable BH extension" "Enable,Disable"
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textline " "
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bitfld.long 0x00 19. " FRCDIS ,Fetch rate control disable" "Enable,Disable"
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bitfld.long 0x00 17. " RSDIS ,Return stack disable" "Enable,Disable"
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bitfld.long 0x00 15.--16. " BP ,Control of the branch prediction policy" "Normal,Taken,Not taken,?..."
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textline " "
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bitfld.long 0x00 14. " DBWR ,Disable write_burst on AXI master" "Enable,Disable"
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bitfld.long 0x00 13. " DSWT ,Disable should_wait on AXI master" "Enable,Disable"
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bitfld.long 0x00 12. " ERPEG ,Enable random parity error generation" "Disable,Enable"
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textline " "
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bitfld.long 0x00 11. " DOLT ,Disable outstanding line fill on AXI master" "Enable,Disable"
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bitfld.long 0x00 10. " FORA ,Force outer read allocate (ORA) for outer write allocate (OWA) regions" "Not forced,Forced"
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bitfld.long 0x00 9. " FWT ,Force write-through (WT) for write-back (WB) regions" "Not forced,Forced"
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textline " "
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bitfld.long 0x00 8. " FDSnS ,Force D-side to not-shared when MPU is off" "Not forced,Forced"
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bitfld.long 0x00 7. " sMOV ,sMOV disabled" "Enabled,Disabled"
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bitfld.long 0x0 6. " DILS ,Disable low interrupt latency on all load/store instructions" "Enable,Disable"
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textline " "
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bitfld.long 0x00 5. " DA ,DA Disable abort on cache parity error" "Enable,Disable"
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bitfld.long 0x00 4. " EHR ,Enable hardware recovery from cache parity errors" "Disable,Enable"
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bitfld.long 0x00 2. " I1TCMECEN ,Instruction 1 TCM error check enable" "Disable,Enable"
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textline " "
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bitfld.long 0x00 1. " I0TCMECEN ,Instruction 1 TCM error check enable" "Disable,Enable"
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bitfld.long 0x00 0. " ITCMECEN ,Instruction TCM error check enable" "Disable,Enable"
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textline " "
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group c15:0x0f--0x0f
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line.long 0x0 "SACTLR,Secondary Auxiliary Control Register"
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bitfld.long 0x00 22. " DCHE ,Disable hard-error support in the caches" "Enable,Disable"
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bitfld.long 0x00 21. " DR2B ,Enable random 2-bit error genration in cache RAMs" "Disable,Enable"
|
|
bitfld.long 0x00 20. " DF6DI ,F6 dual issue control" "Enable,Disable"
|
|
textline " "
|
|
bitfld.long 0x00 19. " DF2DI ,F2 dual issue control" "Enable,Disable"
|
|
bitfld.long 0x00 18. " DDI ,F1/F3/F4 dual issue control" "Enable,Disable"
|
|
bitfld.long 0x00 17. " DOODPFP ,Out-of-order Double Precision Floating-point control" "Enable,Disable"
|
|
textline " "
|
|
bitfld.long 0x00 16. " DOOFMACS ,Out-of-order FMACS control" "Enable,Disable"
|
|
bitfld.long 0x00 13. " IXC ,Floating-point inexact exception output mask" "Mask,Propagate"
|
|
bitfld.long 0x00 12. " OFC ,Floating-point overflow exception output mask" "Mask,Propagate"
|
|
textline " "
|
|
bitfld.long 0x00 11. " UFC ,Floating-point underflow exception output mask" "Mask,Propagate"
|
|
bitfld.long 0x00 10. " IOC ,Floating-point invalid operation exception output mask" "Mask,Propagate"
|
|
bitfld.long 0x00 9. " DZC ,Floating-point divide-by-zero exception output mask" "Mask,Propagate"
|
|
textline " "
|
|
bitfld.long 0x00 8. " IDC ,Floating-point input denormal exception output mask" "Mask,Propagate"
|
|
bitfld.long 0x00 3. " BTCMECC ,Correction for internal ECC logic on BTCM ports" "Enable,Disable"
|
|
bitfld.long 0x00 2. " ATCMECC ,Correction for internal ECC logic on ATCM port" "Enable,Disable"
|
|
textline " "
|
|
bitfld.long 0x00 1. " BTCMRMW ,Enable 64-bit stores on BTCMs" "Disable,Enable"
|
|
bitfld.long 0x00 0. " ATCMRMW ,Enable 64-bit stores on ATCM" "Disable,Enable"
|
|
textline " "
|
|
group c15:0x201--0x201
|
|
line.long 0x0 "CPACR,Coprocessor Access Control Register"
|
|
bitfld.long 0x0 26.--27. " CP13 ,Coprocesor access control" "Denied,Privileged,Reserved,Full"
|
|
bitfld.long 0x0 24.--25. " CP12 ,Coprocesor access control" "Denied,Privileged,Reserved,Full"
|
|
textline " "
|
|
bitfld.long 0x0 22.--23. " CP11 ,Coprocesor access control" "Denied,Privileged,Reserved,Full"
|
|
bitfld.long 0x0 20.--21. " CP10 ,Coprocesor access control" "Denied,Privileged,Reserved,Full"
|
|
textline " "
|
|
bitfld.long 0x0 18.--19. " CP9 ,Coprocesor access control" "Denied,Privileged,Reserved,Full"
|
|
bitfld.long 0x0 16.--17. " CP8 ,Coprocesor access control" "Denied,Privileged,Reserved,Full"
|
|
textline " "
|
|
bitfld.long 0x0 14.--15. " CP7 ,Coprocesor access control" "Denied,Privileged,Reserved,Full"
|
|
bitfld.long 0x0 12.--13. " CP6 ,Coprocesor access control" "Denied,Privileged,Reserved,Full"
|
|
textline " "
|
|
bitfld.long 0x0 10.--11. " CP5 ,Coprocesor access control" "Denied,Privileged,Reserved,Full"
|
|
bitfld.long 0x0 8.--9. " CP4 ,Coprocesor access control" "Denied,Privileged,Reserved,Full"
|
|
textline " "
|
|
bitfld.long 0x0 6.--7. " CP3 ,Coprocesor access control" "Denied,Privileged,Reserved,Full"
|
|
bitfld.long 0x0 4.--5. " CP2 ,Coprocesor access control" "Denied,Privileged,Reserved,Full"
|
|
textline " "
|
|
bitfld.long 0x0 2.--3. " CP1 ,Coprocesor access control" "Denied,Privileged,Reserved,Full"
|
|
bitfld.long 0x0 0.--1. " CP0 ,Coprocesor access control" "Denied,Privileged,Reserved,Full"
|
|
textline " "
|
|
group.long c15:0x0b--0x0b
|
|
line.long 0x00 "SPC,Slave Port Control"
|
|
bitfld.long 0x00 1. " PRIV ,Privilege access only" "User/Privilege,Privilege only"
|
|
bitfld.long 0x00 0. " AXISLEN ,AXI slave port disable" "Enabled,Disabled"
|
|
tree.end
|
|
width 0x8
|
|
tree "MPU Control and Configuration"
|
|
group c15:0x0001--0x0001
|
|
line.long 0x0 "SCTLR,Control Register"
|
|
bitfld.long 0x0 31. " IE ,Instruction endianness" "Little,Big"
|
|
bitfld.long 0x0 30. " TE ,Thumb exception enable" "ARM,Thumb"
|
|
bitfld.long 0x0 29. " AFE ,Access Flag Enable" "Disable,Enable"
|
|
bitfld.long 0x0 28. " TRE ,TEX remap enable" "Disable,Enable"
|
|
bitfld.long 0x0 27. " NMFI ,Nonmaskable Fast Interrupt enable" "Disable,Enable"
|
|
textline " "
|
|
bitfld.long 0x0 25. " EE ,Exception endianess" "Little,Big"
|
|
bitfld.long 0x0 24. " VE ,Vector Enable" "Disable,Vectored"
|
|
bitfld.long 0x0 21. " FI ,Fast Interrupts enable" "Disable,Enable"
|
|
bitfld.long 0x0 19. " DZ ,Divide by Zero exception bit" "Disable,Enable"
|
|
bitfld.long 0x0 14. " RR ,Round-Robin bit" "Random,RRobin"
|
|
bitfld.long 0x0 13. " V ,Base Location of Exception Registers" "0x00000000,0xFFFF0000"
|
|
textline " "
|
|
bitfld.long 0x0 12. " I ,Instruction Cache Enable" "Disable,Enable"
|
|
bitfld.long 0x0 11. " Z ,Branch Prediction Enable" "Disable,Enable"
|
|
bitfld.long 0x0 2. " C ,Enable data cache" "Disable,Enable"
|
|
bitfld.long 0x0 1. " A ,Strict Alignment" "Disable,Enable"
|
|
bitfld.long 0x0 0. " M ,MPU Enable" "Disable,Enable"
|
|
textline " "
|
|
group.long c15:0x0005++0x00
|
|
line.long 0x00 "DFSR,Data Fault Status Register"
|
|
bitfld.long 0x00 12. " EXT ,External Abort Qualifier" "DECERR,SLVERR"
|
|
bitfld.long 0x00 11. " RW ,Access Caused an Abort Type" "Read,Write"
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " DOMAIN ,Domain Accessed When a Data Fault Occurs" "D0,D1,D2,D3,D4,D5,D6,D7,D8,D9,D10,D11,D12,D13,D14,D15"
|
|
bitfld.long 0x00 0.--3. 10. " STATUS ,Generated Exception Type" "Reserved,Alignment,Debug,Access/section,Instruction,Translation/section,Access/page,Translation/page,Nontranslation/synchronous external,Domain/section,Reserved,Domain/page,L1/external,Permission/section,L2/external,Permission/page,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Asynchronous external,?..."
|
|
group.long c15:0x0015++0x00
|
|
line.long 0x00 "ADFSR,Auxiliary Data Fault Status Register"
|
|
group.long c15:0x0006++0x00
|
|
line.long 0x00 "DFAR,Data Fault Address Register"
|
|
group.long c15:0x0105++0x00
|
|
line.long 0x00 "IFSR,Instruction Fault Status Register"
|
|
bitfld.long 0x00 12. " EXT ,External Abort Qualifier" "DECERR,SLVERR"
|
|
bitfld.long 0x00 0.--3. 10. " STATUS ,Generated Exception Type" "Reserved,Alignment,Debug,Access/section,Instruction,Translation/section,Access/page,Translation/page,Nontranslation/synchronous external,Domain/section,Reserved,Domain/page,L1/external,Permission/section,L2/external,Permission/page,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Asynchronous external,?..."
|
|
group.long c15:0x0115++0x00
|
|
line.long 0x00 "AIFSR,Auxiliary Instruction Fault Status Register"
|
|
group.long c15:0x0206++0x00
|
|
line.long 0x00 "IFAR,Instruction Fault Address Register"
|
|
textline " "
|
|
group c15:0x0016++0x00
|
|
line.long 0x00 "RBAR,Region Base Address Register"
|
|
hexmask.long 0x00 5.--31. 0x20 " BA ,Base address"
|
|
group c15:0x0216++0x00
|
|
line.long 0x00 "RSER,Region Size and Enable Register"
|
|
bitfld.long 0x00 15. " SD ,Subregion 7 disable" "-,D"
|
|
bitfld.long 0x00 14. " ,Subregion 6 disable" "-,D"
|
|
bitfld.long 0x00 13. " ,Subregion 5 disable" "-,D"
|
|
bitfld.long 0x00 12. " ,Subregion 4 disable" "-,D"
|
|
bitfld.long 0x00 11. " ,Subregion 3 disable" "-,D"
|
|
bitfld.long 0x00 10. " ,Subregion 2 disable" "-,D"
|
|
bitfld.long 0x00 9. " ,Subregion 1 disable" "-,D"
|
|
bitfld.long 0x00 8. " ,Subregion 0 disable" "-,D"
|
|
bitfld.long 0x00 1.--5. " RS ,Region size" "Unpredictable,Unpredictable,Unpredictable,Unpredictable,32 bytes,64 bytes,128 bytes,256 bytes,512 bytes,1KB,2KB,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB"
|
|
bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled"
|
|
group c15:0x0416++0x00
|
|
line.long 0x00 "RACR,Region Access Control Register"
|
|
bitfld.long 0x00 12. " XN ,Execute never" "-,NoExec"
|
|
bitfld.long 0x00 2. " S ,Share" "No,Yes"
|
|
bitfld.long 0x00 8.--10. " AP ,Access permission" "None,Privileged,User read-only,Full,Reserved,Privileged read,Read-only,Reserved"
|
|
bitfld.long 0x00 0.--1. 3.--5. " TYPE ,Region type" "Strongly-ordered,Shareable Device,Outer and Inner write-through/no write-allocate,Outer and Inner write-back/no write-allocate,Outer and Inner Non-cacheable,00101,00110,Outer and Inner write-back/write-allocate,Non-shareable Device,01001,01010,01011,01100,01101,01110,01111,O:Non-cacheable I:Non-cacheable,O:Non-cacheable I:Write-back/write-allocate,O:Non-cacheable I:Write-through/no write-allocate,O:Non-cacheable I:Write-back/no write-allocate,O:Write-back/write-allocate I:Non-cacheable,O:Write-back/write-allocate I:Write-back/write-allocate,O:Write-back/write-allocate I:Write-through/no write-allocate,O:Write-back/write-allocate I:Write-back/no write-allocate,O:Write-through/no write-allocate I:Non-cacheable,O:Write-through/no write-allocate I:Write-back/write-allocate,O:Write-through/no write-allocate I:Write-through/no write-allocate,O:Write-through/no write-allocate I:Write-back/no write-allocate,O:Write-back/no write-allocate I:Non-cacheable,O:Write-back/no write-allocate I:Write-back/write-allocate,O:Write-back/no write-allocate I:Write-through/no write-allocate,O:Write-back/no write-allocate I:Write-back/no write-allocate"
|
|
group c15:0x0026++0x00
|
|
line.long 0x00 "MRNR,Memory Region Number Register"
|
|
bitfld.long 0x00 0.--3. " REGION ,Defines the group of registers to be accessed" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
group c15:0x010d++0x00
|
|
line.long 0x00 "CIDR,Context ID Register"
|
|
group.long c15:0x20d++0x00
|
|
line.long 0x00 "TIDRURW,User read/write Thread and Process ID Register"
|
|
group.long c15:0x30d++0x00
|
|
line.long 0x00 "TIDRURO,User read only Thread and Process ID Register"
|
|
group.long c15:0x40d++0x00
|
|
line.long 0x00 "TIDRPRW,Privileged Only Thread and Process ID Register"
|
|
tree "MPU regions"
|
|
group c15:0x0016++0x00
|
|
saveout c15:0x26 %l 0x0
|
|
line.long 0x00 "RBAR0,Region Base Address Register 0"
|
|
hexmask.long 0x00 5.--31. 0x20 " BA ,Base address"
|
|
group c15:0x0216++0x00
|
|
saveout c15:0x26 %l 0x0
|
|
line.long 0x00 "RSER0,Region Size and Enable Register 0"
|
|
bitfld.long 0x00 15. " SD ,Subregion 7 disable" "-,D"
|
|
bitfld.long 0x00 14. " ,Subregion 6 disable" "-,D"
|
|
bitfld.long 0x00 13. " ,Subregion 5 disable" "-,D"
|
|
bitfld.long 0x00 12. " ,Subregion 4 disable" "-,D"
|
|
bitfld.long 0x00 11. " ,Subregion 3 disable" "-,D"
|
|
bitfld.long 0x00 10. " ,Subregion 2 disable" "-,D"
|
|
bitfld.long 0x00 9. " ,Subregion 1 disable" "-,D"
|
|
bitfld.long 0x00 8. " ,Subregion 0 disable" "-,D"
|
|
bitfld.long 0x00 1.--5. " RS ,Region size" "Unpredictable,Unpredictable,Unpredictable,Unpredictable,32 bytes,64 bytes,128 bytes,256 bytes,512 bytes,1KB,2KB,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB"
|
|
bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled"
|
|
group c15:0x0416++0x00
|
|
saveout c15:0x26 %l 0x0
|
|
line.long 0x00 "RACR0,Region Access Control Register 0"
|
|
bitfld.long 0x00 12. " XN ,Execute never" "-,NoExec"
|
|
bitfld.long 0x00 2. " S ,Share" "No,Yes"
|
|
bitfld.long 0x00 8.--10. " AP ,Access permission" "None,Privileged,User read-only,Full,Reserved,Privileged read,Read-only,Reserved"
|
|
bitfld.long 0x00 0.--1. 3.--5. " type ,Region type" "Strongly-ordered,Shareable Device,Outer and Inner write-through/no write-allocate,Outer and Inner write-back/no write-allocate,Outer and Inner Non-cacheable,00101,00110,Outer and Inner write-back/write-allocate,Non-shareable Device,01001,01010,01011,01100,01101,01110,01111,O:Non-cacheable I:Non-cacheable,O:Non-cacheable I:Write-back/write-allocate,O:Non-cacheable I:Write-through/no write-allocate,O:Non-cacheable I:Write-back/no write-allocate,O:Write-back/write-allocate I:Non-cacheable,O:Write-back/write-allocate I:Write-back/write-allocate,O:Write-back/write-allocate I:Write-through/no write-allocate,O:Write-back/write-allocate I:Write-back/no write-allocate,O:Write-through/no write-allocate I:Non-cacheable,O:Write-through/no write-allocate I:Write-back/write-allocate,O:Write-through/no write-allocate I:Write-through/no write-allocate,O:Write-through/no write-allocate I:Write-back/no write-allocate,O:Write-back/no write-allocate I:Non-cacheable,O:Write-back/no write-allocate I:Write-back/write-allocate,O:Write-back/no write-allocate I:Write-through/no write-allocate,O:Write-back/no write-allocate I:Write-back/no write-allocate"
|
|
textline " "
|
|
group c15:0x0016++0x00
|
|
saveout c15:0x26 %l 0x1
|
|
line.long 0x00 "RBAR1,Region Base Address Register 1"
|
|
hexmask.long 0x00 5.--31. 0x20 " BA ,Base address"
|
|
group c15:0x0216++0x00
|
|
saveout c15:0x26 %l 0x1
|
|
line.long 0x00 "RSER1,Region Size and Enable Register 1"
|
|
bitfld.long 0x00 15. " SD ,Subregion 7 disable" "-,D"
|
|
bitfld.long 0x00 14. " ,Subregion 6 disable" "-,D"
|
|
bitfld.long 0x00 13. " ,Subregion 5 disable" "-,D"
|
|
bitfld.long 0x00 12. " ,Subregion 4 disable" "-,D"
|
|
bitfld.long 0x00 11. " ,Subregion 3 disable" "-,D"
|
|
bitfld.long 0x00 10. " ,Subregion 2 disable" "-,D"
|
|
bitfld.long 0x00 9. " ,Subregion 1 disable" "-,D"
|
|
bitfld.long 0x00 8. " ,Subregion 0 disable" "-,D"
|
|
bitfld.long 0x00 1.--5. " RS ,Region size" "Unpredictable,Unpredictable,Unpredictable,Unpredictable,32 bytes,64 bytes,128 bytes,256 bytes,512 bytes,1KB,2KB,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB"
|
|
bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled"
|
|
group c15:0x0416++0x00
|
|
saveout c15:0x26 %l 0x1
|
|
line.long 0x00 "RACR1,Region Access Control Register 1"
|
|
bitfld.long 0x00 12. " XN ,Execute never" "-,NoExec"
|
|
bitfld.long 0x00 2. " S ,Share" "No,Yes"
|
|
bitfld.long 0x00 8.--10. " AP ,Access permission" "None,Privileged,User read-only,Full,Reserved,Privileged read,Read-only,Reserved"
|
|
bitfld.long 0x00 0.--1. 3.--5. " type ,Region type" "Strongly-ordered,Shareable Device,Outer and Inner write-through/no write-allocate,Outer and Inner write-back/no write-allocate,Outer and Inner Non-cacheable,00101,00110,Outer and Inner write-back/write-allocate,Non-shareable Device,01001,01010,01011,01100,01101,01110,01111,O:Non-cacheable I:Non-cacheable,O:Non-cacheable I:Write-back/write-allocate,O:Non-cacheable I:Write-through/no write-allocate,O:Non-cacheable I:Write-back/no write-allocate,O:Write-back/write-allocate I:Non-cacheable,O:Write-back/write-allocate I:Write-back/write-allocate,O:Write-back/write-allocate I:Write-through/no write-allocate,O:Write-back/write-allocate I:Write-back/no write-allocate,O:Write-through/no write-allocate I:Non-cacheable,O:Write-through/no write-allocate I:Write-back/write-allocate,O:Write-through/no write-allocate I:Write-through/no write-allocate,O:Write-through/no write-allocate I:Write-back/no write-allocate,O:Write-back/no write-allocate I:Non-cacheable,O:Write-back/no write-allocate I:Write-back/write-allocate,O:Write-back/no write-allocate I:Write-through/no write-allocate,O:Write-back/no write-allocate I:Write-back/no write-allocate"
|
|
textline " "
|
|
group c15:0x0016++0x00
|
|
saveout c15:0x26 %l 0x2
|
|
line.long 0x00 "RBAR2,Region Base Address Register 2"
|
|
hexmask.long 0x00 5.--31. 0x20 " BA ,Base address"
|
|
group c15:0x0216++0x00
|
|
saveout c15:0x26 %l 0x2
|
|
line.long 0x00 "RSER2,Region Size and Enable Register 2"
|
|
bitfld.long 0x00 15. " SD ,Subregion 7 disable" "-,D"
|
|
bitfld.long 0x00 14. " ,Subregion 6 disable" "-,D"
|
|
bitfld.long 0x00 13. " ,Subregion 5 disable" "-,D"
|
|
bitfld.long 0x00 12. " ,Subregion 4 disable" "-,D"
|
|
bitfld.long 0x00 11. " ,Subregion 3 disable" "-,D"
|
|
bitfld.long 0x00 10. " ,Subregion 2 disable" "-,D"
|
|
bitfld.long 0x00 9. " ,Subregion 1 disable" "-,D"
|
|
bitfld.long 0x00 8. " ,Subregion 0 disable" "-,D"
|
|
bitfld.long 0x00 1.--5. " RS ,Region size" "Unpredictable,Unpredictable,Unpredictable,Unpredictable,32 bytes,64 bytes,128 bytes,256 bytes,512 bytes,1KB,2KB,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB"
|
|
bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled"
|
|
group c15:0x0416++0x00
|
|
saveout c15:0x26 %l 0x2
|
|
line.long 0x00 "RACR2,Region Access Control Register 2"
|
|
bitfld.long 0x00 12. " XN ,Execute never" "-,NoExec"
|
|
bitfld.long 0x00 2. " S ,Share" "No,Yes"
|
|
bitfld.long 0x00 8.--10. " AP ,Access permission" "None,Privileged,User read-only,Full,Reserved,Privileged read,Read-only,Reserved"
|
|
bitfld.long 0x00 0.--1. 3.--5. " type ,Region type" "Strongly-ordered,Shareable Device,Outer and Inner write-through/no write-allocate,Outer and Inner write-back/no write-allocate,Outer and Inner Non-cacheable,00101,00110,Outer and Inner write-back/write-allocate,Non-shareable Device,01001,01010,01011,01100,01101,01110,01111,O:Non-cacheable I:Non-cacheable,O:Non-cacheable I:Write-back/write-allocate,O:Non-cacheable I:Write-through/no write-allocate,O:Non-cacheable I:Write-back/no write-allocate,O:Write-back/write-allocate I:Non-cacheable,O:Write-back/write-allocate I:Write-back/write-allocate,O:Write-back/write-allocate I:Write-through/no write-allocate,O:Write-back/write-allocate I:Write-back/no write-allocate,O:Write-through/no write-allocate I:Non-cacheable,O:Write-through/no write-allocate I:Write-back/write-allocate,O:Write-through/no write-allocate I:Write-through/no write-allocate,O:Write-through/no write-allocate I:Write-back/no write-allocate,O:Write-back/no write-allocate I:Non-cacheable,O:Write-back/no write-allocate I:Write-back/write-allocate,O:Write-back/no write-allocate I:Write-through/no write-allocate,O:Write-back/no write-allocate I:Write-back/no write-allocate"
|
|
textline " "
|
|
group c15:0x0016++0x00
|
|
saveout c15:0x26 %l 0x3
|
|
line.long 0x00 "RBAR3,Region Base Address Register 3"
|
|
hexmask.long 0x00 5.--31. 0x20 " BA ,Base address"
|
|
group c15:0x0216++0x00
|
|
saveout c15:0x26 %l 0x3
|
|
line.long 0x00 "RSER3,Region Size and Enable Register 3"
|
|
bitfld.long 0x00 15. " SD ,Subregion 7 disable" "-,D"
|
|
bitfld.long 0x00 14. " ,Subregion 6 disable" "-,D"
|
|
bitfld.long 0x00 13. " ,Subregion 5 disable" "-,D"
|
|
bitfld.long 0x00 12. " ,Subregion 4 disable" "-,D"
|
|
bitfld.long 0x00 11. " ,Subregion 3 disable" "-,D"
|
|
bitfld.long 0x00 10. " ,Subregion 2 disable" "-,D"
|
|
bitfld.long 0x00 9. " ,Subregion 1 disable" "-,D"
|
|
bitfld.long 0x00 8. " ,Subregion 0 disable" "-,D"
|
|
bitfld.long 0x00 1.--5. " RS ,Region size" "Unpredictable,Unpredictable,Unpredictable,Unpredictable,32 bytes,64 bytes,128 bytes,256 bytes,512 bytes,1KB,2KB,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB"
|
|
bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled"
|
|
group c15:0x0416++0x00
|
|
saveout c15:0x26 %l 0x3
|
|
line.long 0x00 "RACR3,Region Access Control Register 3"
|
|
bitfld.long 0x00 12. " XN ,Execute never" "-,NoExec"
|
|
bitfld.long 0x00 2. " S ,Share" "No,Yes"
|
|
bitfld.long 0x00 8.--10. " AP ,Access permission" "None,Privileged,User read-only,Full,Reserved,Privileged read,Read-only,Reserved"
|
|
bitfld.long 0x00 0.--1. 3.--5. " type ,Region type" "Strongly-ordered,Shareable Device,Outer and Inner write-through/no write-allocate,Outer and Inner write-back/no write-allocate,Outer and Inner Non-cacheable,00101,00110,Outer and Inner write-back/write-allocate,Non-shareable Device,01001,01010,01011,01100,01101,01110,01111,O:Non-cacheable I:Non-cacheable,O:Non-cacheable I:Write-back/write-allocate,O:Non-cacheable I:Write-through/no write-allocate,O:Non-cacheable I:Write-back/no write-allocate,O:Write-back/write-allocate I:Non-cacheable,O:Write-back/write-allocate I:Write-back/write-allocate,O:Write-back/write-allocate I:Write-through/no write-allocate,O:Write-back/write-allocate I:Write-back/no write-allocate,O:Write-through/no write-allocate I:Non-cacheable,O:Write-through/no write-allocate I:Write-back/write-allocate,O:Write-through/no write-allocate I:Write-through/no write-allocate,O:Write-through/no write-allocate I:Write-back/no write-allocate,O:Write-back/no write-allocate I:Non-cacheable,O:Write-back/no write-allocate I:Write-back/write-allocate,O:Write-back/no write-allocate I:Write-through/no write-allocate,O:Write-back/no write-allocate I:Write-back/no write-allocate"
|
|
textline " "
|
|
group c15:0x0016++0x00
|
|
saveout c15:0x26 %l 0x4
|
|
line.long 0x00 "RBAR4,Region Base Address Register 4"
|
|
hexmask.long 0x00 5.--31. 0x20 " BA ,Base address"
|
|
group c15:0x0216++0x00
|
|
saveout c15:0x26 %l 0x4
|
|
line.long 0x00 "RSER4,Region Size and Enable Register 4"
|
|
bitfld.long 0x00 15. " SD ,Subregion 7 disable" "-,D"
|
|
bitfld.long 0x00 14. " ,Subregion 6 disable" "-,D"
|
|
bitfld.long 0x00 13. " ,Subregion 5 disable" "-,D"
|
|
bitfld.long 0x00 12. " ,Subregion 4 disable" "-,D"
|
|
bitfld.long 0x00 11. " ,Subregion 3 disable" "-,D"
|
|
bitfld.long 0x00 10. " ,Subregion 2 disable" "-,D"
|
|
bitfld.long 0x00 9. " ,Subregion 1 disable" "-,D"
|
|
bitfld.long 0x00 8. " ,Subregion 0 disable" "-,D"
|
|
bitfld.long 0x00 1.--5. " RS ,Region size" "Unpredictable,Unpredictable,Unpredictable,Unpredictable,32 bytes,64 bytes,128 bytes,256 bytes,512 bytes,1KB,2KB,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB"
|
|
bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled"
|
|
group c15:0x0416++0x00
|
|
saveout c15:0x26 %l 0x4
|
|
line.long 0x00 "RACR4,Region Access Control Register 4"
|
|
bitfld.long 0x00 12. " XN ,Execute never" "-,NoExec"
|
|
bitfld.long 0x00 2. " S ,Share" "No,Yes"
|
|
bitfld.long 0x00 8.--10. " AP ,Access permission" "None,Privileged,User read-only,Full,Reserved,Privileged read,Read-only,Reserved"
|
|
bitfld.long 0x00 0.--1. 3.--5. " type ,Region type" "Strongly-ordered,Shareable Device,Outer and Inner write-through/no write-allocate,Outer and Inner write-back/no write-allocate,Outer and Inner Non-cacheable,00101,00110,Outer and Inner write-back/write-allocate,Non-shareable Device,01001,01010,01011,01100,01101,01110,01111,O:Non-cacheable I:Non-cacheable,O:Non-cacheable I:Write-back/write-allocate,O:Non-cacheable I:Write-through/no write-allocate,O:Non-cacheable I:Write-back/no write-allocate,O:Write-back/write-allocate I:Non-cacheable,O:Write-back/write-allocate I:Write-back/write-allocate,O:Write-back/write-allocate I:Write-through/no write-allocate,O:Write-back/write-allocate I:Write-back/no write-allocate,O:Write-through/no write-allocate I:Non-cacheable,O:Write-through/no write-allocate I:Write-back/write-allocate,O:Write-through/no write-allocate I:Write-through/no write-allocate,O:Write-through/no write-allocate I:Write-back/no write-allocate,O:Write-back/no write-allocate I:Non-cacheable,O:Write-back/no write-allocate I:Write-back/write-allocate,O:Write-back/no write-allocate I:Write-through/no write-allocate,O:Write-back/no write-allocate I:Write-back/no write-allocate"
|
|
textline " "
|
|
group c15:0x0016++0x00
|
|
saveout c15:0x26 %l 0x5
|
|
line.long 0x00 "RBAR5,Region Base Address Register 5"
|
|
hexmask.long 0x00 5.--31. 0x20 " BA ,Base address"
|
|
group c15:0x0216++0x00
|
|
saveout c15:0x26 %l 0x5
|
|
line.long 0x00 "RSER5,Region Size and Enable Register 5"
|
|
bitfld.long 0x00 15. " SD ,Subregion 7 disable" "-,D"
|
|
bitfld.long 0x00 14. " ,Subregion 6 disable" "-,D"
|
|
bitfld.long 0x00 13. " ,Subregion 5 disable" "-,D"
|
|
bitfld.long 0x00 12. " ,Subregion 4 disable" "-,D"
|
|
bitfld.long 0x00 11. " ,Subregion 3 disable" "-,D"
|
|
bitfld.long 0x00 10. " ,Subregion 2 disable" "-,D"
|
|
bitfld.long 0x00 9. " ,Subregion 1 disable" "-,D"
|
|
bitfld.long 0x00 8. " ,Subregion 0 disable" "-,D"
|
|
bitfld.long 0x00 1.--5. " RS ,Region size" "Unpredictable,Unpredictable,Unpredictable,Unpredictable,32 bytes,64 bytes,128 bytes,256 bytes,512 bytes,1KB,2KB,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB"
|
|
bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled"
|
|
group c15:0x0416++0x00
|
|
saveout c15:0x26 %l 0x5
|
|
line.long 0x00 "RACR5,Region Access Control Register 5"
|
|
bitfld.long 0x00 12. " XN ,Execute never" "-,NoExec"
|
|
bitfld.long 0x00 2. " S ,Share" "No,Yes"
|
|
bitfld.long 0x00 8.--10. " AP ,Access permission" "None,Privileged,User read-only,Full,Reserved,Privileged read,Read-only,Reserved"
|
|
bitfld.long 0x00 0.--1. 3.--5. " type ,Region type" "Strongly-ordered,Shareable Device,Outer and Inner write-through/no write-allocate,Outer and Inner write-back/no write-allocate,Outer and Inner Non-cacheable,00101,00110,Outer and Inner write-back/write-allocate,Non-shareable Device,01001,01010,01011,01100,01101,01110,01111,O:Non-cacheable I:Non-cacheable,O:Non-cacheable I:Write-back/write-allocate,O:Non-cacheable I:Write-through/no write-allocate,O:Non-cacheable I:Write-back/no write-allocate,O:Write-back/write-allocate I:Non-cacheable,O:Write-back/write-allocate I:Write-back/write-allocate,O:Write-back/write-allocate I:Write-through/no write-allocate,O:Write-back/write-allocate I:Write-back/no write-allocate,O:Write-through/no write-allocate I:Non-cacheable,O:Write-through/no write-allocate I:Write-back/write-allocate,O:Write-through/no write-allocate I:Write-through/no write-allocate,O:Write-through/no write-allocate I:Write-back/no write-allocate,O:Write-back/no write-allocate I:Non-cacheable,O:Write-back/no write-allocate I:Write-back/write-allocate,O:Write-back/no write-allocate I:Write-through/no write-allocate,O:Write-back/no write-allocate I:Write-back/no write-allocate"
|
|
textline " "
|
|
group c15:0x0016++0x00
|
|
saveout c15:0x26 %l 0x6
|
|
line.long 0x00 "RBAR6,Region Base Address Register 6"
|
|
hexmask.long 0x00 5.--31. 0x20 " BA ,Base address"
|
|
group c15:0x0216++0x00
|
|
saveout c15:0x26 %l 0x6
|
|
line.long 0x00 "RSER6,Region Size and Enable Register 6"
|
|
bitfld.long 0x00 15. " SD ,Subregion 7 disable" "-,D"
|
|
bitfld.long 0x00 14. " ,Subregion 6 disable" "-,D"
|
|
bitfld.long 0x00 13. " ,Subregion 5 disable" "-,D"
|
|
bitfld.long 0x00 12. " ,Subregion 4 disable" "-,D"
|
|
bitfld.long 0x00 11. " ,Subregion 3 disable" "-,D"
|
|
bitfld.long 0x00 10. " ,Subregion 2 disable" "-,D"
|
|
bitfld.long 0x00 9. " ,Subregion 1 disable" "-,D"
|
|
bitfld.long 0x00 8. " ,Subregion 0 disable" "-,D"
|
|
bitfld.long 0x00 1.--5. " RS ,Region size" "Unpredictable,Unpredictable,Unpredictable,Unpredictable,32 bytes,64 bytes,128 bytes,256 bytes,512 bytes,1KB,2KB,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB"
|
|
bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled"
|
|
group c15:0x0416++0x00
|
|
saveout c15:0x26 %l 0x6
|
|
line.long 0x00 "RACR6,Region Access Control Register 6"
|
|
bitfld.long 0x00 12. " XN ,Execute never" "-,NoExec"
|
|
bitfld.long 0x00 2. " S ,Share" "No,Yes"
|
|
bitfld.long 0x00 8.--10. " AP ,Access permission" "None,Privileged,User read-only,Full,Reserved,Privileged read,Read-only,Reserved"
|
|
bitfld.long 0x00 0.--1. 3.--5. " type ,Region type" "Strongly-ordered,Shareable Device,Outer and Inner write-through/no write-allocate,Outer and Inner write-back/no write-allocate,Outer and Inner Non-cacheable,00101,00110,Outer and Inner write-back/write-allocate,Non-shareable Device,01001,01010,01011,01100,01101,01110,01111,O:Non-cacheable I:Non-cacheable,O:Non-cacheable I:Write-back/write-allocate,O:Non-cacheable I:Write-through/no write-allocate,O:Non-cacheable I:Write-back/no write-allocate,O:Write-back/write-allocate I:Non-cacheable,O:Write-back/write-allocate I:Write-back/write-allocate,O:Write-back/write-allocate I:Write-through/no write-allocate,O:Write-back/write-allocate I:Write-back/no write-allocate,O:Write-through/no write-allocate I:Non-cacheable,O:Write-through/no write-allocate I:Write-back/write-allocate,O:Write-through/no write-allocate I:Write-through/no write-allocate,O:Write-through/no write-allocate I:Write-back/no write-allocate,O:Write-back/no write-allocate I:Non-cacheable,O:Write-back/no write-allocate I:Write-back/write-allocate,O:Write-back/no write-allocate I:Write-through/no write-allocate,O:Write-back/no write-allocate I:Write-back/no write-allocate"
|
|
textline " "
|
|
group c15:0x0016++0x00
|
|
saveout c15:0x26 %l 0x7
|
|
line.long 0x00 "RBAR7,Region Base Address Register 7"
|
|
hexmask.long 0x00 5.--31. 0x20 " BA ,Base address"
|
|
group c15:0x0216++0x00
|
|
saveout c15:0x26 %l 0x7
|
|
line.long 0x00 "RSER7,Region Size and Enable Register 7"
|
|
bitfld.long 0x00 15. " SD ,Subregion 7 disable" "-,D"
|
|
bitfld.long 0x00 14. " ,Subregion 6 disable" "-,D"
|
|
bitfld.long 0x00 13. " ,Subregion 5 disable" "-,D"
|
|
bitfld.long 0x00 12. " ,Subregion 4 disable" "-,D"
|
|
bitfld.long 0x00 11. " ,Subregion 3 disable" "-,D"
|
|
bitfld.long 0x00 10. " ,Subregion 2 disable" "-,D"
|
|
bitfld.long 0x00 9. " ,Subregion 1 disable" "-,D"
|
|
bitfld.long 0x00 8. " ,Subregion 0 disable" "-,D"
|
|
bitfld.long 0x00 1.--5. " RS ,Region size" "Unpredictable,Unpredictable,Unpredictable,Unpredictable,32 bytes,64 bytes,128 bytes,256 bytes,512 bytes,1KB,2KB,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB"
|
|
bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled"
|
|
group c15:0x0416++0x00
|
|
saveout c15:0x26 %l 0x7
|
|
line.long 0x00 "RACR7,Region Access Control Register 7"
|
|
bitfld.long 0x00 12. " XN ,Execute never" "-,NoExec"
|
|
bitfld.long 0x00 2. " S ,Share" "No,Yes"
|
|
bitfld.long 0x00 8.--10. " AP ,Access permission" "None,Privileged,User read-only,Full,Reserved,Privileged read,Read-only,Reserved"
|
|
bitfld.long 0x00 0.--1. 3.--5. " type ,Region type" "Strongly-ordered,Shareable Device,Outer and Inner write-through/no write-allocate,Outer and Inner write-back/no write-allocate,Outer and Inner Non-cacheable,00101,00110,Outer and Inner write-back/write-allocate,Non-shareable Device,01001,01010,01011,01100,01101,01110,01111,O:Non-cacheable I:Non-cacheable,O:Non-cacheable I:Write-back/write-allocate,O:Non-cacheable I:Write-through/no write-allocate,O:Non-cacheable I:Write-back/no write-allocate,O:Write-back/write-allocate I:Non-cacheable,O:Write-back/write-allocate I:Write-back/write-allocate,O:Write-back/write-allocate I:Write-through/no write-allocate,O:Write-back/write-allocate I:Write-back/no write-allocate,O:Write-through/no write-allocate I:Non-cacheable,O:Write-through/no write-allocate I:Write-back/write-allocate,O:Write-through/no write-allocate I:Write-through/no write-allocate,O:Write-through/no write-allocate I:Write-back/no write-allocate,O:Write-back/no write-allocate I:Non-cacheable,O:Write-back/no write-allocate I:Write-back/write-allocate,O:Write-back/no write-allocate I:Write-through/no write-allocate,O:Write-back/no write-allocate I:Write-back/no write-allocate"
|
|
textline " "
|
|
group c15:0x0016++0x00
|
|
saveout c15:0x26 %l 0x8
|
|
line.long 0x00 "RBAR8,Region Base Address Register 8"
|
|
hexmask.long 0x00 5.--31. 0x20 " BA ,Base address"
|
|
group c15:0x0216++0x00
|
|
saveout c15:0x26 %l 0x8
|
|
line.long 0x00 "RSER8,Region Size and Enable Register 8"
|
|
bitfld.long 0x00 15. " SD ,Subregion 7 disable" "-,D"
|
|
bitfld.long 0x00 14. " ,Subregion 6 disable" "-,D"
|
|
bitfld.long 0x00 13. " ,Subregion 5 disable" "-,D"
|
|
bitfld.long 0x00 12. " ,Subregion 4 disable" "-,D"
|
|
bitfld.long 0x00 11. " ,Subregion 3 disable" "-,D"
|
|
bitfld.long 0x00 10. " ,Subregion 2 disable" "-,D"
|
|
bitfld.long 0x00 9. " ,Subregion 1 disable" "-,D"
|
|
bitfld.long 0x00 8. " ,Subregion 0 disable" "-,D"
|
|
bitfld.long 0x00 1.--5. " RS ,Region size" "Unpredictable,Unpredictable,Unpredictable,Unpredictable,32 bytes,64 bytes,128 bytes,256 bytes,512 bytes,1KB,2KB,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB"
|
|
bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled"
|
|
group c15:0x0416++0x00
|
|
saveout c15:0x26 %l 0x8
|
|
line.long 0x00 "RACR8,Region Access Control Register 8"
|
|
bitfld.long 0x00 12. " XN ,Execute never" "-,NoExec"
|
|
bitfld.long 0x00 2. " S ,Share" "No,Yes"
|
|
bitfld.long 0x00 8.--10. " AP ,Access permission" "None,Privileged,User read-only,Full,Reserved,Privileged read,Read-only,Reserved"
|
|
bitfld.long 0x00 0.--1. 3.--5. " type ,Region type" "Strongly-ordered,Shareable Device,Outer and Inner write-through/no write-allocate,Outer and Inner write-back/no write-allocate,Outer and Inner Non-cacheable,00101,00110,Outer and Inner write-back/write-allocate,Non-shareable Device,01001,01010,01011,01100,01101,01110,01111,O:Non-cacheable I:Non-cacheable,O:Non-cacheable I:Write-back/write-allocate,O:Non-cacheable I:Write-through/no write-allocate,O:Non-cacheable I:Write-back/no write-allocate,O:Write-back/write-allocate I:Non-cacheable,O:Write-back/write-allocate I:Write-back/write-allocate,O:Write-back/write-allocate I:Write-through/no write-allocate,O:Write-back/write-allocate I:Write-back/no write-allocate,O:Write-through/no write-allocate I:Non-cacheable,O:Write-through/no write-allocate I:Write-back/write-allocate,O:Write-through/no write-allocate I:Write-through/no write-allocate,O:Write-through/no write-allocate I:Write-back/no write-allocate,O:Write-back/no write-allocate I:Non-cacheable,O:Write-back/no write-allocate I:Write-back/write-allocate,O:Write-back/no write-allocate I:Write-through/no write-allocate,O:Write-back/no write-allocate I:Write-back/no write-allocate"
|
|
textline " "
|
|
group c15:0x0016++0x00
|
|
saveout c15:0x26 %l 0x9
|
|
line.long 0x00 "RBAR9,Region Base Address Register 9"
|
|
hexmask.long 0x00 5.--31. 0x20 " BA ,Base address"
|
|
group c15:0x0216++0x00
|
|
saveout c15:0x26 %l 0x9
|
|
line.long 0x00 "RSER9,Region Size and Enable Register 9"
|
|
bitfld.long 0x00 15. " SD ,Subregion 7 disable" "-,D"
|
|
bitfld.long 0x00 14. " ,Subregion 6 disable" "-,D"
|
|
bitfld.long 0x00 13. " ,Subregion 5 disable" "-,D"
|
|
bitfld.long 0x00 12. " ,Subregion 4 disable" "-,D"
|
|
bitfld.long 0x00 11. " ,Subregion 3 disable" "-,D"
|
|
bitfld.long 0x00 10. " ,Subregion 2 disable" "-,D"
|
|
bitfld.long 0x00 9. " ,Subregion 1 disable" "-,D"
|
|
bitfld.long 0x00 8. " ,Subregion 0 disable" "-,D"
|
|
bitfld.long 0x00 1.--5. " RS ,Region size" "Unpredictable,Unpredictable,Unpredictable,Unpredictable,32 bytes,64 bytes,128 bytes,256 bytes,512 bytes,1KB,2KB,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB"
|
|
bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled"
|
|
group c15:0x0416++0x00
|
|
saveout c15:0x26 %l 0x9
|
|
line.long 0x00 "RACR9,Region Access Control Register 9"
|
|
bitfld.long 0x00 12. " XN ,Execute never" "-,NoExec"
|
|
bitfld.long 0x00 2. " S ,Share" "No,Yes"
|
|
bitfld.long 0x00 8.--10. " AP ,Access permission" "None,Privileged,User read-only,Full,Reserved,Privileged read,Read-only,Reserved"
|
|
bitfld.long 0x00 0.--1. 3.--5. " type ,Region type" "Strongly-ordered,Shareable Device,Outer and Inner write-through/no write-allocate,Outer and Inner write-back/no write-allocate,Outer and Inner Non-cacheable,00101,00110,Outer and Inner write-back/write-allocate,Non-shareable Device,01001,01010,01011,01100,01101,01110,01111,O:Non-cacheable I:Non-cacheable,O:Non-cacheable I:Write-back/write-allocate,O:Non-cacheable I:Write-through/no write-allocate,O:Non-cacheable I:Write-back/no write-allocate,O:Write-back/write-allocate I:Non-cacheable,O:Write-back/write-allocate I:Write-back/write-allocate,O:Write-back/write-allocate I:Write-through/no write-allocate,O:Write-back/write-allocate I:Write-back/no write-allocate,O:Write-through/no write-allocate I:Non-cacheable,O:Write-through/no write-allocate I:Write-back/write-allocate,O:Write-through/no write-allocate I:Write-through/no write-allocate,O:Write-through/no write-allocate I:Write-back/no write-allocate,O:Write-back/no write-allocate I:Non-cacheable,O:Write-back/no write-allocate I:Write-back/write-allocate,O:Write-back/no write-allocate I:Write-through/no write-allocate,O:Write-back/no write-allocate I:Write-back/no write-allocate"
|
|
textline " "
|
|
group c15:0x0016++0x00
|
|
saveout c15:0x26 %l 0xA
|
|
line.long 0x00 "RBAR10,Region Base Address Register 10"
|
|
hexmask.long 0x00 5.--31. 0x20 " BA ,Base address"
|
|
group c15:0x0216++0x00
|
|
saveout c15:0x26 %l 0xA
|
|
line.long 0x00 "RSER10,Region Size and Enable Register 10"
|
|
bitfld.long 0x00 15. " SD ,Subregion 7 disable" "-,D"
|
|
bitfld.long 0x00 14. " ,Subregion 6 disable" "-,D"
|
|
bitfld.long 0x00 13. " ,Subregion 5 disable" "-,D"
|
|
bitfld.long 0x00 12. " ,Subregion 4 disable" "-,D"
|
|
bitfld.long 0x00 11. " ,Subregion 3 disable" "-,D"
|
|
bitfld.long 0x00 10. " ,Subregion 2 disable" "-,D"
|
|
bitfld.long 0x00 9. " ,Subregion 1 disable" "-,D"
|
|
bitfld.long 0x00 8. " ,Subregion 0 disable" "-,D"
|
|
bitfld.long 0x00 1.--5. " RS ,Region size" "Unpredictable,Unpredictable,Unpredictable,Unpredictable,32 bytes,64 bytes,128 bytes,256 bytes,512 bytes,1KB,2KB,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB"
|
|
bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled"
|
|
group c15:0x0416++0x00
|
|
saveout c15:0x26 %l 0xA
|
|
line.long 0x00 "RACR10,Region Access Control Register 10"
|
|
bitfld.long 0x00 12. " XN ,Execute never" "-,NoExec"
|
|
bitfld.long 0x00 2. " S ,Share" "No,Yes"
|
|
bitfld.long 0x00 8.--10. " AP ,Access permission" "None,Privileged,User read-only,Full,Reserved,Privileged read,Read-only,Reserved"
|
|
bitfld.long 0x00 0.--1. 3.--5. " type ,Region type" "Strongly-ordered,Shareable Device,Outer and Inner write-through/no write-allocate,Outer and Inner write-back/no write-allocate,Outer and Inner Non-cacheable,00101,00110,Outer and Inner write-back/write-allocate,Non-shareable Device,01001,01010,01011,01100,01101,01110,01111,O:Non-cacheable I:Non-cacheable,O:Non-cacheable I:Write-back/write-allocate,O:Non-cacheable I:Write-through/no write-allocate,O:Non-cacheable I:Write-back/no write-allocate,O:Write-back/write-allocate I:Non-cacheable,O:Write-back/write-allocate I:Write-back/write-allocate,O:Write-back/write-allocate I:Write-through/no write-allocate,O:Write-back/write-allocate I:Write-back/no write-allocate,O:Write-through/no write-allocate I:Non-cacheable,O:Write-through/no write-allocate I:Write-back/write-allocate,O:Write-through/no write-allocate I:Write-through/no write-allocate,O:Write-through/no write-allocate I:Write-back/no write-allocate,O:Write-back/no write-allocate I:Non-cacheable,O:Write-back/no write-allocate I:Write-back/write-allocate,O:Write-back/no write-allocate I:Write-through/no write-allocate,O:Write-back/no write-allocate I:Write-back/no write-allocate"
|
|
textline " "
|
|
group c15:0x0016++0x00
|
|
saveout c15:0x26 %l 0xB
|
|
line.long 0x00 "RBAR11,Region Base Address Register 11"
|
|
hexmask.long 0x00 5.--31. 0x20 " BA ,Base address"
|
|
group c15:0x0216++0x00
|
|
saveout c15:0x26 %l 0xB
|
|
line.long 0x00 "RSER11,Region Size and Enable Register 11"
|
|
bitfld.long 0x00 15. " SD ,Subregion 7 disable" "-,D"
|
|
bitfld.long 0x00 14. " ,Subregion 6 disable" "-,D"
|
|
bitfld.long 0x00 13. " ,Subregion 5 disable" "-,D"
|
|
bitfld.long 0x00 12. " ,Subregion 4 disable" "-,D"
|
|
bitfld.long 0x00 11. " ,Subregion 3 disable" "-,D"
|
|
bitfld.long 0x00 10. " ,Subregion 2 disable" "-,D"
|
|
bitfld.long 0x00 9. " ,Subregion 1 disable" "-,D"
|
|
bitfld.long 0x00 8. " ,Subregion 0 disable" "-,D"
|
|
bitfld.long 0x00 1.--5. " RS ,Region size" "Unpredictable,Unpredictable,Unpredictable,Unpredictable,32 bytes,64 bytes,128 bytes,256 bytes,512 bytes,1KB,2KB,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB"
|
|
bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled"
|
|
group c15:0x0416++0x00
|
|
saveout c15:0x26 %l 0xB
|
|
line.long 0x00 "RACR11,Region Access Control Register 11"
|
|
bitfld.long 0x00 12. " XN ,Execute never" "-,NoExec"
|
|
bitfld.long 0x00 2. " S ,Share" "No,Yes"
|
|
bitfld.long 0x00 8.--10. " AP ,Access permission" "None,Privileged,User read-only,Full,Reserved,Privileged read,Read-only,Reserved"
|
|
bitfld.long 0x00 0.--1. 3.--5. " type ,Region type" "Strongly-ordered,Shareable Device,Outer and Inner write-through/no write-allocate,Outer and Inner write-back/no write-allocate,Outer and Inner Non-cacheable,00101,00110,Outer and Inner write-back/write-allocate,Non-shareable Device,01001,01010,01011,01100,01101,01110,01111,O:Non-cacheable I:Non-cacheable,O:Non-cacheable I:Write-back/write-allocate,O:Non-cacheable I:Write-through/no write-allocate,O:Non-cacheable I:Write-back/no write-allocate,O:Write-back/write-allocate I:Non-cacheable,O:Write-back/write-allocate I:Write-back/write-allocate,O:Write-back/write-allocate I:Write-through/no write-allocate,O:Write-back/write-allocate I:Write-back/no write-allocate,O:Write-through/no write-allocate I:Non-cacheable,O:Write-through/no write-allocate I:Write-back/write-allocate,O:Write-through/no write-allocate I:Write-through/no write-allocate,O:Write-through/no write-allocate I:Write-back/no write-allocate,O:Write-back/no write-allocate I:Non-cacheable,O:Write-back/no write-allocate I:Write-back/write-allocate,O:Write-back/no write-allocate I:Write-through/no write-allocate,O:Write-back/no write-allocate I:Write-back/no write-allocate"
|
|
textline " "
|
|
tree.end
|
|
tree.end
|
|
width 0x9
|
|
tree "TCM Control and Configuration"
|
|
rgroup.long c15:0x200++0x00
|
|
line.long 0x00 "TCMTR,TCM Type Register"
|
|
bitfld.long 0x00 16.--18. " BTCM ,Number of BTCMs implemented" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--2. " ATCM ,Number of ATCMs implemented" "0,1,2,3,4,5,6,7"
|
|
group.long c15:0x019++0x00
|
|
line.long 0x00 "BTCMRR,BTCM Region Register"
|
|
hexmask.long 0x00 12.--31. 0x1000 " BA ,Base address (physical address)"
|
|
bitfld.long 0x00 2.--6. " SIZE ,Size of instruction TCM on reads" "None,Reserved,Reserved,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,?..."
|
|
bitfld.long 0x00 0. " EN ,Enable instruction TCM" "Disabled,Enabled"
|
|
group.long c15:0x119++0x00
|
|
line.long 0x00 "ATCMRR,ATCM Region Register"
|
|
hexmask.long 0x00 12.--31. 0x1000 " BA ,Base address (physical address)"
|
|
bitfld.long 0x00 2.--6. " SIZE ,Size of instruction TCM on reads" "None,Reserved,Reserved,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,?..."
|
|
bitfld.long 0x00 0. " EN ,Enable instruction TCM" "Disabled,Enabled"
|
|
rgroup.long c15:0x29++0x00
|
|
line.long 0x00 "TCMSEL,TCM Selection Register"
|
|
tree.end
|
|
width 0xC
|
|
tree "Cache Control and Configuration"
|
|
rgroup.long c15:0x1100--0x1100
|
|
line.long 0x0 "CLIDR,Cache Level ID Register"
|
|
bitfld.long 0x00 27.--29. " LoU ,Level of Unification" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 24.--26. " LoC ,Level of Coherency" "Level 1,Level 2,Level 3,Level 4,Level 5,Level 6,Level 7,Level 8"
|
|
textline " "
|
|
bitfld.long 0x00 21.--23. " CL8 ,Cache Level (CL) 8" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 18.--20. " CL7 ,Cache Level (CL) 7" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 15.--17. " CL6 ,Cache Level (CL) 6" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 12.--14. " CL5 ,Cache Level (CL) 5" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 9.--11. " CL4 ,Cache Level (CL) 4" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 6.--8. " CL3 ,Cache Level (CL) 3" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 3.--5. " CL2 ,Cache Level (CL) 2" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--2. " CL1 ,Cache Level (CL) 1" "0,1,2,3,4,5,6,7"
|
|
rgroup.long c15:0x1000++0x00
|
|
line.long 0x00 "CCSIDR,Cache Size ID Register"
|
|
bitfld.long 0x00 31. " WT ,Write-Through" "Not supported,Supported"
|
|
bitfld.long 0x00 30. " WB ,Write-Back" "Not supported,Supported"
|
|
textline " "
|
|
bitfld.long 0x00 29. " RA ,Read-Allocate" "Not supported,Supported"
|
|
bitfld.long 0x00 28. " WA ,Write-Allocate" "Not supported,Supported"
|
|
textline " "
|
|
hexmask.long.word 0x00 13.--27. 1. " NUMSETS ,Number of sets"
|
|
hexmask.long.word 0x00 3.--12. 1. " ASSOCIATIVITY ,Associativity"
|
|
textline " "
|
|
bitfld.long 0x00 0.--2. " LINESIZE ,Number of words in each cache line" "0,1,2,3,4,5,6,7"
|
|
group.long c15:0x2000--0x2000
|
|
line.long 0x0 "CSSELR,Cache Size Selection Register"
|
|
bitfld.long 0x00 1.--3. " Level ,Cache level to select" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0. " InD ,Instruction or data or unified cache to use" "Data/unified,Instruction"
|
|
group.long c15:0x03f++0x00
|
|
line.long 0x00 "CFLR,Correctable Fault Location Register"
|
|
bitfld.long 0x00 26.--29. " WAY ,Way of the error" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 24.--25. " SIDE ,Source of the error" "0,1,2,3"
|
|
textline " "
|
|
hexmask.long.word 0x00 5.--13. 1. " INDEX ,index of the location where the error occurred"
|
|
bitfld.long 0x00 0.--1. " TYPE ,Type of access that caused the error" "Instruction cache,Data cache,Reserved,ACP"
|
|
rgroup.long c15:0x0ef++0x0
|
|
line.long 0x00 "CSOR,Cache Size Override Register"
|
|
bitfld.long 0x00 4.--6. " Dcache ,Validation data cache size" "Not presented,Reserved,Reserved,4k,8k,16k,32k,64k"
|
|
bitfld.long 0x00 0.--2. " Icache ,Validation instruction cache size" "Not presented,Reserved,Reserved,4k,8k,16k,32k,64k"
|
|
tree.end
|
|
width 8.
|
|
tree "System Performance Monitor"
|
|
group c15:0xC9--0xC9
|
|
line.long 0x0 "PMNC,Performance Monitor Control Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " IMP ,Implementer code"
|
|
hexmask.long.byte 0x00 16.--23. 1. " IDCODE ,Identification code"
|
|
bitfld.long 0x00 11.--15. " N ,Number of counters implemented" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 5. " DP ,Disable CCNT when prohibited" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " X ,Export Enabled" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " D ,Clock Divider" "Every cycle,64th cycle"
|
|
bitfld.long 0x00 2. " C ,Clock Counter Reset" "No action,Reset"
|
|
bitfld.long 0x00 1. " P ,Performance Counter Reset" "No action,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 0. " E ,Counters Enable" "Disabled,Enabled"
|
|
group c15:0x1C9--0x1C9
|
|
line.long 0x0 "CNTENS,Count Enable Set Register"
|
|
eventfld.long 0x00 31. " C ,CCNT Enabled / Enable / Disable CCNT" "Disabled,Enabled"
|
|
eventfld.long 0x00 3. " P3 ,PMN3 Enabled / Enable / Disable counter" "Disabled,Enabled"
|
|
eventfld.long 0x00 2. " P2 ,PMN2 Enabled / Enable / Disable counter" "Disabled,Enabled"
|
|
eventfld.long 0x00 1. " P1 ,PMN1 Enabled / Enable / Disable counter" "Disabled,Enabled"
|
|
eventfld.long 0x00 0. " P0 ,PMN0 Enabled / Enable / Disable counter" "Disabled,Enabled"
|
|
group c15:0x2C9--0x2C9
|
|
line.long 0x0 "CNTENC,Count Enable Clear Register"
|
|
eventfld.long 0x00 31. " C ,CCNT Enabled / Enable / Disable CCNT" "Disabled,Enabled"
|
|
eventfld.long 0x00 3. " P3 ,PMN3 Enabled / Enable / Disable counter" "Disabled,Enabled"
|
|
eventfld.long 0x00 2. " P2 ,PMN2 Enabled / Enable / Disable counter" "Disabled,Enabled"
|
|
eventfld.long 0x00 1. " P1 ,PMN1 Enabled / Enable / Disable counter" "Disabled,Enabled"
|
|
eventfld.long 0x00 0. " P0 ,PMN0 Enabled / Enable / Disable counter" "Disabled,Enabled"
|
|
group c15:0x3C9--0x3C9
|
|
line.long 0x0 "FLAG,Overflow Flag Status Register"
|
|
eventfld.long 0x00 31. " C ,CCNT overflowed" "No overflow,Overflow"
|
|
eventfld.long 0x00 3. " P3 ,PMN3 overflowed" "No overflow,Overflow"
|
|
eventfld.long 0x00 2. " P2 ,PMN2 overflowed" "No overflow,Overflow"
|
|
eventfld.long 0x00 1. " P1 ,PMN1 overflowed" "No overflow,Overflow"
|
|
eventfld.long 0x00 0. " P0 ,PMN0 overflowed" "No overflow,Overflow"
|
|
group c15:0x4C9--0x4C9
|
|
line.long 0x0 "SWINCR,Software Increment Register"
|
|
eventfld.long 0x00 3. " P3 ,Increment PMN3" "No action,Increment"
|
|
eventfld.long 0x00 2. " P2 ,Increment PMN2" "No action,Increment"
|
|
eventfld.long 0x00 1. " P1 ,Increment PMN1" "No action,Increment"
|
|
eventfld.long 0x00 0. " P0 ,Increment PMN0" "No action,Increment"
|
|
group c15:0x5C9--0x5C9
|
|
line.long 0x0 "PMNXSEL,Performance Counter Selection Register"
|
|
bitfld.long 0x00 0.--4. " SEL ,Selection value" "CNT0,CNT1,CNT2,CNT3,?..."
|
|
group c15:0xD9--0xD9
|
|
line.long 0x0 "CCNT,Cycle Count Register"
|
|
group c15:0x01d9++0x00
|
|
line.long 0x00 "ESR,Event Selection Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SEL ,Event Selection"
|
|
group c15:0x02d9++0x00
|
|
line.long 0x00 "PMCR,Performance Monitor Count Register"
|
|
group c15:0x01d9++0x00
|
|
saveout c15:0x5C9 %l 0x0
|
|
line.long 0x00 "ESR0,Event Selection Register 0"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SEL ,Event Selection"
|
|
group c15:0x02d9++0x00
|
|
saveout c15:0x5C9 %l 0x0
|
|
line.long 0x00 "PMCR0,Performance Monitor Count Register 0"
|
|
hexmask.long 0x00 0.--31. 1. " PMC ,Performance Monitor Count"
|
|
group c15:0x01d9++0x00
|
|
saveout c15:0x5C9 %l 0x1
|
|
line.long 0x00 "ESR1,Event Selection Register 1"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SEL ,Event Selection"
|
|
group c15:0x02d9++0x00
|
|
saveout c15:0x5C9 %l 0x1
|
|
line.long 0x00 "PMCR1,Performance Monitor Count Register 1"
|
|
hexmask.long 0x00 0.--31. 1. " PMC ,Performance Monitor Count"
|
|
group c15:0x01d9++0x00
|
|
saveout c15:0x5C9 %l 0x2
|
|
line.long 0x00 "ESR2,Event Selection Register 2"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SEL ,Event Selection"
|
|
group c15:0x02d9++0x00
|
|
saveout c15:0x5C9 %l 0x2
|
|
line.long 0x00 "PMCR2,Performance Monitor Count Register 2"
|
|
hexmask.long 0x00 0.--31. 1. " PMC ,Performance Monitor Count"
|
|
group c15:0xE9--0xE9
|
|
line.long 0x0 "USEREN,User Enable Register"
|
|
bitfld.long 0x00 0. " EN ,User Mode Enable" "Disabled,Enabled"
|
|
group c15:0x1E9--0x1E9
|
|
line.long 0x0 "INTENS,Interrupt Enable Set Register"
|
|
eventfld.long 0x00 31. " C ,Interrupt on CCNT Overflow Enabled / Enable / Disable Interrupt" "Disabled,Enabled"
|
|
eventfld.long 0x00 3. " P3 ,Interrupt on PMN3 Overflow Enabled / Enable / Disable Interrupt" "Disabled,Enabled"
|
|
eventfld.long 0x00 2. " P2 ,Interrupt on PMN2 Overflow Enabled / Enable / Disable Interrupt" "Disabled,Enabled"
|
|
eventfld.long 0x00 1. " P1 ,Interrupt on PMN1 Overflow Enabled / Enable / Disable Interrupt" "Disabled,Enabled"
|
|
eventfld.long 0x00 0. " P0 ,Interrupt on PMN0 Overflow Enabled / Enable / Disable Interrupt" "Disabled,Enabled"
|
|
group c15:0x2E9--0x2E9
|
|
line.long 0x0 "INTENC,Interrupt Enable Clear Register"
|
|
eventfld.long 0x00 31. " C ,Interrupt on CCNT Overflow Enabled / Enable / Disable Interrupt" "Disabled,Enabled"
|
|
eventfld.long 0x00 3. " P3 ,Interrupt on PMN3 Overflow Enabled / Enable / Disable Interrupt" "Disabled,Enabled"
|
|
eventfld.long 0x00 2. " P2 ,Interrupt on PMN2 Overflow Enabled / Enable / Disable Interrupt" "Disabled,Enabled"
|
|
eventfld.long 0x00 1. " P1 ,Interrupt on PMN1 Overflow Enabled / Enable / Disable Interrupt" "Disabled,Enabled"
|
|
eventfld.long 0x00 0. " P0 ,Interrupt on PMN0 Overflow Enabled / Enable / Disable Interrupt" "Disabled,Enabled"
|
|
tree.end
|
|
width 8.
|
|
tree "Debug Registers"
|
|
width 11.
|
|
tree "Processor Identifier Registers"
|
|
rgroup c14:0x340--0x340
|
|
line.long 0x00 "MIDR,Main ID Register"
|
|
hexmask.long.byte 0x0 24.--31. 0x1 " IMPL ,Implementer code"
|
|
hexmask.long.byte 0x0 20.--23. 0x1 " SPECREV ,Variant number"
|
|
textline " "
|
|
hexmask.long.byte 0x0 16.--19. 0x1 " ARCH , Architecture"
|
|
hexmask.long.word 0x0 4.--15. 0x1 " PARTNUM ,Part Number"
|
|
textline " "
|
|
hexmask.long.byte 0x0 0.--3. 0x1 " REV ,Layout Revision"
|
|
rgroup c14:0x341--0x341
|
|
line.long 0x00 "CACHETYPE,Cache Type Register"
|
|
bitfld.long 0x00 16.--19. " DMINLINE ,Words of Smallest Line Length in L1 or L2 Data Cache Number" "Reserved,Reserved,Reserved,Reserved,16x32-bit words,?..."
|
|
bitfld.long 0x00 14.--15. " L1_IPOLICY ,VIPT Instruction Cache Support" "Reserved,Reserved,Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " IMINLINE ,Words of Smallest Line Length in L1 or L2 Instruction Cache Number" "Reserved,Reserved,Reserved,Reserved,16x32-bit words,?..."
|
|
rgroup c14:0x343--0x343
|
|
line.long 0x00 "TLBTYPE,TLB Type Register"
|
|
hexmask.long.byte 0x0 16.--23. 0x1 " ILSIZE ,Specifies the number of instruction TLB lockable entries"
|
|
hexmask.long.byte 0x0 8.--15. 0x1 " DLSIZE ,Specifies the number of unified or data TLB lockable entries"
|
|
textline " "
|
|
bitfld.long 0x0 0. " U ,Unified or separate instruction TLBs" "Unified,Separate"
|
|
rgroup c14:0x348--0x348
|
|
line.long 0x00 "ID_PFR0,Processor Feature Register 0"
|
|
bitfld.long 0x00 12.--15. " STATE3 ,Thumb-2 Execution Environment (Thumb-2EE) Support" "Reserved,Supported,?..."
|
|
bitfld.long 0x00 8.--11. " STATE2 ,Java Extension Interface Support" "Not supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " STATE1 ,Thumb Encoding Supported by the Processor Type" "Reserved,Reserved,Reserved,Supported,?..."
|
|
bitfld.long 0x00 0.--3. " STATE0 ,ARM Instruction Set Support" "Reserved,Supported,?..."
|
|
rgroup c14:0x349--0x349
|
|
line.long 0x00 "ID_PFR1,Processor Feature Register 1"
|
|
bitfld.long 0x00 8.--11. " MPM ,Microcontroller Programmer's Model Support" "Supported,?..."
|
|
bitfld.long 0x00 4.--7. " SE ,Security Extensions Architecture v1 Support" "Reserved,Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " PM ,Standard ARMv4 Programmer's Model Support" "Reserved,Supported,?..."
|
|
rgroup c14:0x34a--0x34a
|
|
line.long 0x00 "ID_DFR0,Debug Feature Register 0"
|
|
bitfld.long 0x00 20.--23. " MDM_MM ,Microcontroller Debug Model Support" "Not supported,?..."
|
|
bitfld.long 0x00 16.--19. " TDM_MM ,Trace Debug Model (Memory-Mapped) Support" "Reserved,Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 12.--15. " TDM_CB ,Coprocessor-Based Trace Debug Model Support" "Not supported,?..."
|
|
bitfld.long 0x00 8.--11. " CDM_MM ,Memory-Mapped Debug Model Support" "Reserved,Reserved,Reserved,Reserved,Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " SDM_CB ,Secure Debug Model (Coprocessor) Support" "Not supported,?..."
|
|
bitfld.long 0x00 0.--3. " CDM_CB ,Coprocessor Debug Model Support" "Not supported,?..."
|
|
rgroup c14:0x34b--0x34b
|
|
line.long 0x00 "ID_AFR0,Auxiliary Feature Register 0"
|
|
hexmask.long 0x00 0.--31. 1. " AF ,Auxiliary Feature"
|
|
rgroup c14:0x34c--0x34c
|
|
line.long 0x00 "ID_MMFR0,Processor Feature Register 0"
|
|
bitfld.long 0x00 28.--31. " IT ,Instruction Type Support" "Reserved,Reserved,Reserved,Supported,?..."
|
|
bitfld.long 0x00 24.--27. " FCSE ,Fast Context Switch Memory Mappings Support" "Reserved,Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 20.--23. " ACR ,Auxiliary Control Register Support" "Reserved,Supported,?..."
|
|
bitfld.long 0x00 16.--19. " TCM ,TCM and Associated DMA Support" "Not supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 12.--15. " CC_PLEA ,Cache Coherency With PLE Agent/Shared Memory Support" "Not supported,?..."
|
|
bitfld.long 0x00 8.--11. " CC_CPUA ,Cache Coherency Support With CPU Agent/Shared Memory Support" "Not supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " PMSA ,Physical Memory System Architecture (PMSA) Support" "Not supported,?..."
|
|
bitfld.long 0x00 0.--3. " VMSA ,Virtual Memory System Architecture (VMSA) Support" "Reserved,Reserved,Reserved,Supported,?..."
|
|
rgroup c14:0x34d--0x34d
|
|
line.long 0x00 "ID_MMFR1,Processor Feature Register 1"
|
|
bitfld.long 0x00 28.--31. " BTB ,Branch Target Buffer Support" "Reserved,Reserved,Not required,?..."
|
|
bitfld.long 0x00 24.--27. " L1TCO ,Test and Clean Operations on Data Cache/Harvard/Unified Architecture Support" "Not supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 20.--23. " L1UCMO ,L1 Cache/All Maintenance Operations/Unified Architecture Support" "Not supported,?..."
|
|
bitfld.long 0x00 16.--19. " L1HCMO ,L1 Cache/All Maintenance Operations/Harvard Architecture Support" "Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 12.--15. " L1UCLMOSW ,L1 Cache Line Maintenance Operations by Set and Way/Unified Architecture Support" "Not supported,?..."
|
|
bitfld.long 0x00 8.--11. " L1HCLMOSW ,L1 Cache Line Maintenance Operations by Set and Way/Harvard Architecture Support" "Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " L1UCLMOMVA ,L1 Cache Line Maintenance Operations by MVA/Unified Architecture Support" "Not supported,?..."
|
|
bitfld.long 0x00 0.--3. " L1HCLMOMVA ,L1 Cache Line Maintenance Operations by MVA/Harvard Architecture" "Supported,?..."
|
|
rgroup c14:0x34e--0x34e
|
|
line.long 0x00 "ID_MMFR2,Processor Feature Register 2"
|
|
bitfld.long 0x00 28.--31. " HAF ,Hardware Access Flag Support" "Not supported,?..."
|
|
bitfld.long 0x00 24.--27. " WFI ,Wait for Interrupt Stalling Support" "Reserved,Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 20.--23. " MBF ,Memory Barrier Operations Support" "Reserved,Reserved,Supported,?..."
|
|
bitfld.long 0x00 16.--19. " UTLBMO ,TLB Maintenance Operations/Unified Architecture Support" "Not supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 12.--15. " HTLBMO ,TLB Maintenance Operations/Harvard Architecture Support" "Reserved,Reserved,Supported,?..."
|
|
bitfld.long 0x00 8.--11. " HL1CMRO ,Cache Maintenance Range Operations/Harvard Architecture Support" "Not supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " HL1BPCRO ,Background Prefetch Cache Range Operations/Harvard Architecture Support" "Not supported,?..."
|
|
bitfld.long 0x00 0.--3. " HL1FPCRO ,Foreground Prefetch Cache Range Operations/Harvard Architecture Support" "Not supported,?..."
|
|
rgroup c14:0x34f--0x34f
|
|
line.long 0x00 "ID_MMFR3,Processor Feature Register 3"
|
|
bitfld.long 0x00 4.--7. " HCMOSW ,Invalidate Cache by Set and Way/Clean by Set and Way/Invalidate and Clean by Set and Way Support" "Reserved,Supported,?..."
|
|
bitfld.long 0x00 0.--3. " HCMOMVA ,Invalidate Cache by MVA/Clean by MVA/Invalidate and Clean by MVA/Invalidate All Support" "Reserved,Supported,?..."
|
|
rgroup c14:0x350--0x350
|
|
line.long 0x00 "ID_ISAR0,ISA Feature Register 0"
|
|
bitfld.long 0x00 24.--27. " DIVI ,Divide Instructions Support" "Not supported,?..."
|
|
bitfld.long 0x00 20.--23. " DEBI ,Debug Instructions Support" "Reserved,Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. " CI ,Coprocessor Instructions Support" "Not supported,?..."
|
|
bitfld.long 0x00 12.--15. " CBI ,Combined Compare and Branch Instructions Support" "Reserved,Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 8.--11. " BI ,Bitfield Instructions Support" "Reserved,Supported,?..."
|
|
bitfld.long 0x00 4.--7. " BCI ,Bit Counting Instructions Support" "Reserved,Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " AI ,Atomic Load and Store Instructions Support" "Reserved,Supported,?..."
|
|
rgroup c14:0x351--0x351
|
|
line.long 0x00 "ID_ISAR1,ISA Feature Register 1"
|
|
bitfld.long 0x00 28.--31. " JI ,Jazelle Instructions Support" "Reserved,Supported,?..."
|
|
bitfld.long 0x00 24.--27. " INTI ,Instructions That Branch Between ARM and Thumb Code Support" "Reserved,Reserved,Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 20.--23. " IMMI ,Immediate Instructions Support" "Reserved,Supported,?..."
|
|
bitfld.long 0x00 16.--19. " ITEI ,If Then Instructions Support" "Reserved,Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 12.--15. " EXTI ,Sign or Zero Extend Instructions Support" "Reserved,Reserved,Supported,?..."
|
|
bitfld.long 0x00 8.--11. " E2I ,Exception 2 Instructions Support" "Reserved,Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " E1I ,Exception 1 Instructions Support" "Reserved,Supported,?..."
|
|
bitfld.long 0x00 0.--3. " ENDI ,Endianness Control Instructions Support" "Reserved,Supported,?..."
|
|
rgroup c14:0x352--0x352
|
|
line.long 0x00 "ID_ISAR2,ISA Feature Register 2"
|
|
bitfld.long 0x00 28.--31. " RI ,Reversal Instructions Support" "Reserved,Reserved,Supported,?..."
|
|
bitfld.long 0x00 24.--27. " PSRI ,PSR Instructions Support" "Reserved,Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 20.--23. " UMI ,Advanced Unsigned Multiply Instructions Support" "Reserved,Reserved,Supported,?..."
|
|
bitfld.long 0x00 16.--19. " SMI ,Advanced Signed Multiply Instructions Support" "Reserved,Reserved,Reserved,Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 12.--15. " MI ,Multiply Instructions Support" "Reserved,Reserved,Supported,?..."
|
|
bitfld.long 0x00 8.--11. " II ,Multi-Access Interruptible Instructions Support" "Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " MHI ,Memory Hint Instructions Support" "Reserved,Reserved,Reserved,Supported,?..."
|
|
bitfld.long 0x00 0.--3. " LSI ,Load and Store Instructions Support" "Reserved,Supported,?..."
|
|
rgroup c14:0x353--0x353
|
|
line.long 0x00 "ID_ISAR3,ISA Feature Register 3"
|
|
bitfld.long 0x00 28.--31. " T2E ,Thumb-2 Extensions Support" "Reserved,Supported,?..."
|
|
bitfld.long 0x00 24.--27. " NOPI ,True NOP Instructions Support" "Reserved,Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 20.--23. " TCI ,Thumb Copy Instructions Support" "Reserved,Supported,?..."
|
|
bitfld.long 0x00 16.--19. " TBI ,Table Branch Instructions Support" "Reserved,Reserved,Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 12.--15. " SPI ,Synchronization Primitive Instructions Support" "Reserved,Reserved,Supported,?..."
|
|
bitfld.long 0x00 8.--11. " SWII ,SWI Instructions Support" "Reserved,Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " SIMDI ,Single Instruction Multiple Data (SIMD) Instructions Support" "Reserved,Reserved,Reserved,Supported,?..."
|
|
bitfld.long 0x00 0.--3. " SI ,Saturate Instructions Support" "Reserved,Supported,?..."
|
|
rgroup c14:0x354--0x354
|
|
line.long 0x00 "ID_ISAR4,ISA Feature Register 4"
|
|
bitfld.long 0x00 20.--23. " EI ,Exclusive Instructions Support" "Reserved,Supported,?..."
|
|
bitfld.long 0x00 16.--19. " BI ,Barrier Instructions Support" "Reserved,Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 12.--15. " SMII ,SMI Instructions Support" "Reserved,Supported,?..."
|
|
bitfld.long 0x00 8.--11. " WBI ,Write-Back Instructions Support" "Reserved,Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " WSI ,With-Shift Instructions Support" "Reserved,Reserved,Reserved,Reserved,Supported,?..."
|
|
bitfld.long 0x00 0.--3. " UI ,Unprivileged Instructions Support" "Reserved,Reserved,Supported,?..."
|
|
rgroup c14:0x355--0x355
|
|
line.long 0x00 "ID_ISAR5,ISA Feature Register 5"
|
|
tree.end
|
|
tree "Coresight Management Registers"
|
|
width 0xC
|
|
textline " "
|
|
group c14:0x03bd++0x00
|
|
line.long 0x00 "ITCTRL_IOC,Integration Internal Output Control Register"
|
|
bitfld.long 0x00 5. " I_DBGTRIGGER ,Internal DBGTRIGGER" "0,1"
|
|
bitfld.long 0x00 4. " I_DBGRESTARTED ,Internal DBGRESTARTED" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. " I_NPMUIRQ ,Internal nPMUIRQ" "0,1"
|
|
bitfld.long 0x00 2. " InternalCOMMTX ,Internal COMMTX" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 1. " I_COMMRX ,Internal COMMRX" "0,1"
|
|
bitfld.long 0x00 0. " I_DBGACK ,Internal DBGACK" "0,1"
|
|
group c14:0x03be++0x00
|
|
line.long 0x00 "ITCTRL_EOC,Integration External Output Control Register"
|
|
bitfld.long 0x00 7. " NDMAEXTERRIQ ,External nDMAEXTERRIRQ" "0,1"
|
|
bitfld.long 0x00 6. " NDMASIRQ ,External nDMASIRQ" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 5. " NDMAIRQ ,External nDMAIRQ" "0,1"
|
|
bitfld.long 0x00 4. " NPMUIRQ ,External nPMUIRQ" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. " STANDBYWFI ,External STANDBYWFI" "0,1"
|
|
bitfld.long 0x00 2. " COMMTX ,External COMMTX" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 1. " COMMRX ,External COMMRX" "0,1"
|
|
bitfld.long 0x00 0. " DBGACK ,External DBGACK" "0,1"
|
|
rgroup c14:0x03bf++0x00
|
|
line.long 0x00 "ITCTRL_IS,Integration Input Status Register"
|
|
bitfld.long 0x00 11. " CTI_DBGRESTART ,CTI Debug Restart" "0,1"
|
|
bitfld.long 0x00 10. " CTI_EDBGRQ ,CTI Debug Request" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 9. " CTI_PMUEXTIN[1] ,CTI PMUEXTIN[1] Signal" "0,1"
|
|
bitfld.long 0x00 8. " CTI_PMUEXTIN[0] ,CTI PMUEXTIN[0] Signal" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 2. " NFIQ ,nFIQ Input" "0,1"
|
|
bitfld.long 0x00 1. " NIRQ ,nIRQ Input" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 0. " EDBGRQ ,EDBGRQ Input" "0,1"
|
|
group c14:0x3c0--0x3c0
|
|
line.long 0x0 "ITCTRL,Integration Mode Control Register"
|
|
bitfld.long 0x0 0. " IME ,Integration Mode Enable" "Disabled,Enabled"
|
|
group c14:0x3e8--0x3e8
|
|
line.long 0x0 "CLAIMSET,Claim Tag Set Register"
|
|
bitfld.long 0x0 7. " CT7 ,Claim Tag 7" "No Effect,Set"
|
|
bitfld.long 0x0 6. " CT6 ,Claim Tag 6" "No Effect,Set"
|
|
textline " "
|
|
bitfld.long 0x0 5. " CT5 ,Claim Tag 5" "No Effect,Set"
|
|
bitfld.long 0x0 4. " CT4 ,Claim Tag 4" "No Effect,Set"
|
|
textline " "
|
|
bitfld.long 0x0 3. " CT3 ,Claim Tag 3" "No Effect,Set"
|
|
bitfld.long 0x0 2. " CT2 ,Claim Tag 2" "No Effect,Set"
|
|
textline " "
|
|
bitfld.long 0x0 1. " CT1 ,Claim Tag 1" "No Effect,Set"
|
|
bitfld.long 0x0 0. " CT0 ,Claim Tag 0" "No Effect,Set"
|
|
group c14:0x3e9--0x3e9
|
|
line.long 0x0 "CLAIMCLR,Claim Tag Clear Register"
|
|
bitfld.long 0x0 7. " CT7 ,Claim Tag 7" "No Effect,Cleared"
|
|
bitfld.long 0x0 6. " CT6 ,Claim Tag 6" "No Effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x0 5. " CT5 ,Claim Tag 5" "No Effect,Cleared"
|
|
bitfld.long 0x0 4. " CT4 ,Claim Tag 4" "No Effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x0 3. " CT3 ,Claim Tag 3" "No Effect,Cleared"
|
|
bitfld.long 0x0 2. " CT2 ,Claim Tag 2" "No Effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x0 1. " CT1 ,Claim Tag 1" "No Effect,Cleared"
|
|
bitfld.long 0x0 0. " CT0 ,Claim Tag 0" "No Effect,Cleared"
|
|
wgroup c14:0x3ec--0x3ec
|
|
line.long 0x0 "LAR,Lock Access Register"
|
|
hexmask.long.long 0x0 0.--31. 1. " LACK ,Lock Access Control Key"
|
|
rgroup c14:0x3ed--0x3ed
|
|
line.long 0x0 "LSR,Lock Status Register"
|
|
bitfld.long 0x0 2. " 32ACND ,32-bit Access Needed" "Needed,Not needed"
|
|
bitfld.long 0x0 1. " WLCK ,Writes Lock" "Permitted,Ignored"
|
|
textline " "
|
|
bitfld.long 0x0 0. " LI ,Lock Implementation" "Lock ignored,Unlock required"
|
|
rgroup c14:0x3ee--0x3ee
|
|
line.long 0x0 "AUTHSTATUS,Authentication Status Register"
|
|
bitfld.long 0x0 7. " SNIDFI ,Secure Non-invasive Debug Features Implemented" "Not Implemented,Implemented"
|
|
bitfld.long 0x0 6. " SNIDE ,Secure Non-invasive Debug Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 5. " SIDFI ,Secure Invasive Debug Feauter Implemented" "Not Implemented,Implemented"
|
|
bitfld.long 0x0 4. " SIDE ,Secure Invasive Debug Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 3. " NSNIDFI ,Non-secure Non-invasive Debug Feature Implemented" "Not Implemented,Implemented"
|
|
bitfld.long 0x0 2. " NSNIDE ,Non-secure Non-invasive Debug Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 1. " NSIDFI ,Non-secure Invasive Debug Implemented" "Not Implemented,Implemented"
|
|
bitfld.long 0x0 0. " NSIDE ,Non-secure Invasive Debug Enable" "Disabled,Enabled"
|
|
hgroup c14:0x3f2--0x3f2
|
|
hide.long 0x0 "DEVID,Device Identifier (RESERVED)"
|
|
rgroup c14:0x3f3--0x3f3
|
|
line.long 0x0 "DEVTYPE,Device Type"
|
|
hexmask.long.byte 0x00 4.--7. 1. " SUBTYPE ,Subtype"
|
|
hexmask.long.byte 0x00 0.--3. 1. " MAIN_CLASS ,Main class"
|
|
rgroup c14:0x3f8--0x3f8
|
|
line.long 0x0 "PID0,Peripherial ID0"
|
|
hexmask.long.byte 0x0 0.--7. 1. " PN ,Part Number [7:0]"
|
|
rgroup c14:0x3f9--0x3f9
|
|
line.long 0x0 "PID1,Peripherial ID1"
|
|
hexmask.long.byte 0x0 4.--7. 1. " JEP106 ,JEP106 Identity Code [3:0]"
|
|
hexmask.long.byte 0x0 0.--3. 1. " PN ,Part Number [11:8]"
|
|
rgroup c14:0x3fa--0x3fa
|
|
line.long 0x0 "PID2,Peripherial ID2"
|
|
hexmask.long.byte 0x0 4.--7. 1. " REV ,Revision"
|
|
hexmask.long.byte 0x0 0.--2. 1. " JEP106 ,JEP106 Identity Code [6:4]"
|
|
rgroup c14:0x3fb--0x3fb
|
|
line.long 0x0 "PID3,Peripherial ID3"
|
|
hexmask.long.byte 0x0 4.--7. 1. " REVA ,RevAnd"
|
|
hexmask.long.byte 0x0 0.--3. 1. " CMOD ,Customer Modified"
|
|
rgroup c14:0x3f4--0x3f4
|
|
line.long 0x0 "PID4,Peripherial ID4"
|
|
bitfld.long 0x0 4.--7. " 4KBC ,Number of 4KB Blocks Occupied" "1,2,4,8,16,32,64,128,256,512,1024,2048,4096,8192,16384,32768"
|
|
bitfld.long 0x0 0.--3. " JEP106 ,JEP106 Continuation Code" "0000,0001,0010,0011,0100,0101,0110,0111,1000,1001,1010,1011,1100,1101,1110,1111"
|
|
rgroup c14:0x3fc--0x3fc
|
|
line.long 0x0 "COMPONENTID0,Component ID0"
|
|
hexmask.long.byte 0x0 0.--7. 1. " PRBL ,Preamble"
|
|
rgroup c14:0x3fd--0x3fd
|
|
line.long 0x0 "COMPONENTID1,Component ID1"
|
|
hexmask.long.byte 0x0 4.--7. 1. " CCLASS ,Component Class (CoreSight Component)"
|
|
hexmask.long.byte 0x0 0.--3. 1. " PRBL ,Preamble"
|
|
rgroup c14:0x3fe--0x3fe
|
|
line.long 0x0 "COMPONENTID2,Component ID2"
|
|
hexmask.long.byte 0x0 0.--7. 1. " PRBL ,Preamble"
|
|
rgroup c14:0x3ff--0x3ff
|
|
line.long 0x0 "COMPONENTID3,Component ID3"
|
|
hexmask.long.byte 0x0 0.--7. 1. " PRBL ,Preamble"
|
|
tree.end
|
|
textline " "
|
|
width 0x7
|
|
rgroup c14:0x000--0x000
|
|
line.long 0x0 "DIDR,Debug ID Register"
|
|
bitfld.long 0x0 28.--31. " WRP ,Number of Watchpoint Register Pairs" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16"
|
|
bitfld.long 0x0 24.--27. " BRP ,Number of Breakpoint Register Pairs" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16"
|
|
bitfld.long 0x0 20.--23. " CTX_CMP ,Number of BRPs with Context ID Comparison Capability" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16"
|
|
textline " "
|
|
bitfld.long 0x0 16.--19. " VERSION ,Debug Architecture Version" "Reserved,ARMv6,ARMv6.1,ARMv7,?..."
|
|
textline " "
|
|
bitfld.long 0x0 13. " PCSAMPLE ,PC Sample register implemented" "Low,High"
|
|
bitfld.long 0x0 12. " SECURITY ,Security Extensions implemented" "Not implemented,Implemented"
|
|
textline " "
|
|
bitfld.long 0x0 4.--7. " VARIANT ,Implementation-defined Variant Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x0 0.--3. " REVISION ,Implementation-defined Revision Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group c14:0x22--0x22
|
|
line.long 0x0 "DSCR,Debug Status and Control Register"
|
|
bitfld.long 0x0 30. " DTRRXFULL ,The DTRRX Full Flag" "Empty,Full"
|
|
bitfld.long 0x0 29. " DTRTXfull ,The DTRTX Full Flag" "Empty,Full"
|
|
textline " "
|
|
bitfld.long 0x00 27. " DTRRXFULL_L ,The DTRRX Full Flag 1" "Empty,Full"
|
|
bitfld.long 0x00 26. " DTRTXFULL_L ,The DTRTX Full Flag 1" "Empty,Full"
|
|
textline " "
|
|
bitfld.long 0x0 25. " SPA ,Sticky Pipeline Advance" "No effect,Instruction retired"
|
|
bitfld.long 0x0 24. " IC ,Instruction Complete" "Executing,Not executing"
|
|
textline " "
|
|
bitfld.long 0x0 20.--21. " DTR ,DTR Access Mode" "Non-blocking,Stall,Fast,?..."
|
|
bitfld.long 0x0 19. " NSWS ,Imprecise Data Aborts discarded" "Not discarded,Discarded"
|
|
textline " "
|
|
bitfld.long 0x0 18. " NS ,Non-secure World Status" "Secured,Not secured"
|
|
bitfld.long 0x0 17. " NSPNIDEN ,Secure Non-invasive Debug Disabled" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x0 16. " NSPIDEN ,Secure Invasive Debug Disabled" "Enabled,Disabled"
|
|
bitfld.long 0x0 15. " MONITOR ,Monitor Debug-mode enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 14. " HDEN ,Halting Debug-mode enable" "Disabled,Enabled"
|
|
bitfld.long 0x0 13. " EXECUTE ,Execute instruction enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 12. " COMMS ,User mode access to Comms Channel disable" "Enabled,Disabled"
|
|
bitfld.long 0x0 11. " INTDIS ,Disable Interrupts" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x0 10. " DBGACK ,Force Debug Acknowledge" "Not forced,Forced"
|
|
bitfld.long 0x0 8. " UEXT ,Sticky Undefined Exception" "No exception,Exception"
|
|
textline " "
|
|
bitfld.long 0x0 7. " IABORT ,Sticky Imprecise Abort" "Not aborted,Aborted"
|
|
bitfld.long 0x0 6. " PABORT ,Sticky Precise Abort" "Not aborted,Aborted"
|
|
textline " "
|
|
bitfld.long 0x0 2.--5. " MOE ,Method of Debug Entry" "Debug Entry,Breakpoint,Imprecise Watchpoint,BKPT instruction,External debug,Vector catch,Reserved,Reserved,OS Unlock,?..."
|
|
bitfld.long 0x0 1. " RESTARTED ,Core Restarted" "Debug not exited,Debug exited"
|
|
textline " "
|
|
bitfld.long 0x0 0. " HALTED ,Core Halted" "Normal state,Debug state"
|
|
if (((data.long(c14:0x00))&0x01000)==0x00000)
|
|
group c14:0x007--0x007
|
|
line.long 0x0 "VCR,Vector Catch Register"
|
|
bitfld.long 0x0 7. " FIQ ,Vector Catch Enable FIQ" "Disabled,Enabled"
|
|
bitfld.long 0x0 6. " IRQ ,Vector Catch Enable IRQ" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 4. " DABORT ,Vector Catch Enable Data Abort" "Disabled,Enabled"
|
|
bitfld.long 0x0 3. " PABORT ,Vector Catch Enable Prefetch Abort" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 2. " SWI ,Vector Catch Enable SWI" "Disabled,Enabled"
|
|
bitfld.long 0x0 1. " UNDEF ,Vector Catch Enable Undefined Instruction" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 0. " RESET ,Vector Catch Enable Reset" "Disabled,Enabled"
|
|
else
|
|
group c14:0x007--0x007
|
|
line.long 0x0 "VCR,Vector Catch Register"
|
|
bitfld.long 0x0 31. " FIQN ,Vector Catch Enable FIQ (Non-secure)" "Disabled,Enabled"
|
|
bitfld.long 0x0 30. " IRQN ,Vector Catch Enable IRQ (Non-secure)" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 28. " DABORTN ,Vector Catch Enable Data Abort (Non-secure)" "Disabled,Enabled"
|
|
bitfld.long 0x0 27. " PABORTN ,Vector Catch Enable Prefetch abort (Non-secure)" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 26. " SWIN ,Vector Catch Enable SWI (Non-secure)" "Disabled,Enabled"
|
|
bitfld.long 0x0 25. " UNDEFS ,Vector Catch Enable Undefined (Non-secure)" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 15. " FIQS ,Vector Catch Enable FIQ (Secure)" "Disabled,Enabled"
|
|
bitfld.long 0x0 14. " IRQS ,Vector Catch Enable IRQ (Secure)" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 12. " DABORTS ,Vector Catch Enable Data Abort (Secure)" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " PABORTS ,Vector Catch Enable Prefetch abort (Secure)" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 10. " SMI ,Vector Catch Enable SMI (Secure)" "Disabled,Enabled"
|
|
bitfld.long 0x0 7. " FIQ ,Vector Catch Enable FIQ" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 6. " IRQ ,Vector Catch Enable IRQ" "Disabled,Enabled"
|
|
bitfld.long 0x0 4. " DABORT0 ,Vector Catch Enable Data Abort" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 3. " PABORT ,Vector Catch Enable Prefetch Abort" "Disabled,Enabled"
|
|
bitfld.long 0x0 2. " SWI ,Vector Catch Enable SWI" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 1. " UNDEF ,Vector Catch Enable Undefined Instruction" "Disabled,Enabled"
|
|
bitfld.long 0x0 0. " RESET ,Vector Catch Enable Reset" "Disabled,Enabled"
|
|
endif
|
|
hgroup c14:0x020--0x020
|
|
hide.long 0x0 "DTRRX,Target -> Host Data Transfer Register"
|
|
in
|
|
group c14:0x023--0x023
|
|
line.long 0x0 "DTRTX,Host -> Target Data Transfer Register"
|
|
hexmask.long 0x00 0.--31. 1. " HTD ,Host -> target data"
|
|
group c14:0x09++0x00
|
|
line.long 0x00 "ECR,Event Catch Register"
|
|
bitfld.long 0x00 0. " OSUC ,OS Unlock Catch" "Disabled,Enabled"
|
|
group c14:0x0a++0x00
|
|
line.long 0x00 "DSCCR,Debug State Cache Control Register"
|
|
bitfld.long 0x00 2. " NWT ,Not Write-Through" "Forced,Normal"
|
|
bitfld.long 0x00 0. " DUCL ,Data and Unified Cache Linefill" "Disabled,Normal"
|
|
wgroup c14:0x21++0x00
|
|
line.long 0x00 "ITR,Instruction Transfer Register"
|
|
hexmask.long 0x00 0.--31. 1. " Data ,ARM Instruction for the Processor in Debug State Execute"
|
|
wgroup c14:0x24++0x00
|
|
line.long 0x00 "DRCR,Debug Run Control Register"
|
|
bitfld.long 0x00 3. " CSPA ,Clear Sticky Pipeline Advance" "Not cleared,Cleared"
|
|
bitfld.long 0x00 2. " CSE ,Clear Sticky Exceptions" "Not cleared,Cleared"
|
|
textline " "
|
|
bitfld.long 0x00 1. " RR ,Restart Request" "Not requested,Requested"
|
|
bitfld.long 0x00 0. " HR ,Halt Request" "Not requested,Requested"
|
|
wgroup c14:0xc0++0x00
|
|
line.long 0x00 "OSLAR,Operating System Lock Access Register"
|
|
hexmask.long 0x00 0.--31. 1. " OSLA ,OS Lock Access"
|
|
rgroup c14:0xc1++0x00
|
|
line.long 0x00 "OSLSR,Operating System Lock Status Register"
|
|
bitfld.long 0x00 2. " 32_BA ,32-Bit Access" "Not required,Required"
|
|
bitfld.long 0x00 1. " LB ,Locked Bit" "Not locked,Locked"
|
|
bitfld.long 0x00 0. " LIB ,Lock Implemented Bit" "Not implemented,Implemented"
|
|
group c14:0xc2++0x00
|
|
line.long 0x00 "OSSRR,Operating System Save and Restore Register"
|
|
hexmask.long 0x00 0.--31. 1. " OSSR ,OS Save and Restore"
|
|
group c14:0xc4++0x00
|
|
line.long 0x00 "PRCR,Device Power-Down and Reset Control Register"
|
|
bitfld.long 0x00 2. " HIR ,Hold Internal Reset" "Not held,Held"
|
|
bitfld.long 0x00 1. " FIR ,Force Internal Reset" "Not forced,Forced"
|
|
bitfld.long 0x00 0. " NPD ,No Power-Down" "DBGNOPWRDWN low,DBGNOPWRDWN high"
|
|
hgroup c14:0xc5++0x00
|
|
hide.long 0x00 "PRSR,Device Power-Down and Reset Status Register"
|
|
in
|
|
tree.end
|
|
tree "Breakpoint Registers"
|
|
group c14:0x40++0x00
|
|
line.long 0x00 "BVR0,Breakpoint Value Register 0"
|
|
hexmask.long 0x00 0.--31. 1. " BV0 ,Breakpoint Value 0"
|
|
group c14:0x50++0x00
|
|
line.long 0x00 "BCR0,Breakpoint Control Register 0"
|
|
bitfld.long 0x00 24.--28. " BAM ,Breakpoint Address Mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF"
|
|
bitfld.long 0x00 20.--22. " M ,BVR Meaning" "IVA match,Linked IVA match,Reserved,Reserved,IVA mismatch,Linked IVA mismatch,?..."
|
|
bitfld.long 0x00 16.--19. " LBRP ,Linked BRP Number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15"
|
|
bitfld.long 0x00 14.--15. " SWAC ,Secure World Access Control" "Both,Nonsecure,Secure,?..."
|
|
textline " "
|
|
bitfld.long 0x0 8. " BAS ,Byte 3 address select" "0,1"
|
|
bitfld.long 0x0 7. ",Byte 2 address select" "0,1"
|
|
bitfld.long 0x0 6. ",Byte 1 address select" "0,1"
|
|
bitfld.long 0x0 5. ",Byte 0 address select" "0,1"
|
|
bitfld.long 0x00 1.--2. " S ,Supervisor Access Control" "User/system/supervisor,Privileged,User,Any"
|
|
bitfld.long 0x00 0. " B ,Breakpoint Enable" "Disabled,Enabled"
|
|
group c14:0x41++0x00
|
|
line.long 0x00 "BVR1,Breakpoint Value Register 1"
|
|
hexmask.long 0x00 0.--31. 1. " BV1 ,Breakpoint Value 1"
|
|
group c14:0x51++0x00
|
|
line.long 0x00 "BCR1,Breakpoint Control Register 1"
|
|
bitfld.long 0x00 24.--28. " BAM ,Breakpoint Address Mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF"
|
|
bitfld.long 0x00 20.--22. " M ,BVR Meaning" "IVA match,Linked IVA match,Reserved,Reserved,IVA mismatch,Linked IVA mismatch,?..."
|
|
bitfld.long 0x00 16.--19. " LBRP ,Linked BRP Number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15"
|
|
bitfld.long 0x00 14.--15. " SWAC ,Secure World Access Control" "Both,Nonsecure,Secure,?..."
|
|
textline " "
|
|
bitfld.long 0x0 8. " BAS ,Byte 3 address select" "0,1"
|
|
bitfld.long 0x0 7. ",Byte 2 address select" "0,1"
|
|
bitfld.long 0x0 6. ",Byte 1 address select" "0,1"
|
|
bitfld.long 0x0 5. ",Byte 0 address select" "0,1"
|
|
bitfld.long 0x00 1.--2. " S ,Supervisor Access Control" "User/system/supervisor,Privileged,User,Any"
|
|
bitfld.long 0x00 0. " B ,Breakpoint Enable" "Disabled,Enabled"
|
|
group c14:0x42++0x00
|
|
line.long 0x00 "BVR2,Breakpoint Value Register 2"
|
|
hexmask.long 0x00 0.--31. 1. " BV2 ,Breakpoint Value 2"
|
|
group c14:0x52++0x00
|
|
line.long 0x00 "BCR2,Breakpoint Control Register 2"
|
|
bitfld.long 0x00 24.--28. " BAM ,Breakpoint Address Mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF"
|
|
bitfld.long 0x00 20.--22. " M ,BVR Meaning" "IVA match,Linked IVA match,Reserved,Reserved,IVA mismatch,Linked IVA mismatch,?..."
|
|
bitfld.long 0x00 16.--19. " LBRP ,Linked BRP Number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15"
|
|
bitfld.long 0x00 14.--15. " SWAC ,Secure World Access Control" "Both,Nonsecure,Secure,?..."
|
|
textline " "
|
|
bitfld.long 0x0 8. " BAS ,Byte 3 address select" "0,1"
|
|
bitfld.long 0x0 7. ",Byte 2 address select" "0,1"
|
|
bitfld.long 0x0 6. ",Byte 1 address select" "0,1"
|
|
bitfld.long 0x0 5. ",Byte 0 address select" "0,1"
|
|
bitfld.long 0x00 1.--2. " S ,Supervisor Access Control" "User/system/supervisor,Privileged,User,Any"
|
|
bitfld.long 0x00 0. " B ,Breakpoint Enable" "Disabled,Enabled"
|
|
group c14:0x43++0x00
|
|
line.long 0x00 "BVR3,Breakpoint Value Register 3"
|
|
hexmask.long 0x00 0.--31. 1. " BV3 ,Breakpoint Value 3"
|
|
group c14:0x53++0x00
|
|
line.long 0x00 "BCR3,Breakpoint Control Register 3"
|
|
bitfld.long 0x00 24.--28. " BAM ,Breakpoint Address Mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF"
|
|
bitfld.long 0x00 20.--22. " M ,BVR Meaning" "IVA match,Linked IVA match,Reserved,Reserved,IVA mismatch,Linked IVA mismatch,?..."
|
|
bitfld.long 0x00 16.--19. " LBRP ,Linked BRP Number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15"
|
|
bitfld.long 0x00 14.--15. " SWAC ,Secure World Access Control" "Both,Nonsecure,Secure,?..."
|
|
textline " "
|
|
bitfld.long 0x0 8. " BAS ,Byte 3 address select" "0,1"
|
|
bitfld.long 0x0 7. ",Byte 2 address select" "0,1"
|
|
bitfld.long 0x0 6. ",Byte 1 address select" "0,1"
|
|
bitfld.long 0x0 5. ",Byte 0 address select" "0,1"
|
|
bitfld.long 0x00 1.--2. " S ,Supervisor Access Control" "User/system/supervisor,Privileged,User,Any"
|
|
bitfld.long 0x00 0. " B ,Breakpoint Enable" "Disabled,Enabled"
|
|
group c14:0x44++0x00
|
|
line.long 0x00 "BVR4,Breakpoint Value Register 4"
|
|
hexmask.long 0x00 0.--31. 1. " BV4 ,Breakpoint Value 4"
|
|
group c14:0x54++0x00
|
|
line.long 0x00 "BCR4,Breakpoint Control Register 4"
|
|
bitfld.long 0x00 24.--28. " BAM ,Breakpoint Address Mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF"
|
|
bitfld.long 0x00 20.--22. " M ,BVR Meaning" "IVA match,Linked IVA match,Unlinked ID,Linked ID,IVA mismatch,Linked IVA mismatch,?..."
|
|
bitfld.long 0x00 16.--19. " LBRP ,Linked BRP Number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15"
|
|
bitfld.long 0x00 14.--15. " SWAC ,Secure World Access Control" "Both,Nonsecure,Secure,?..."
|
|
textline " "
|
|
bitfld.long 0x0 8. " BAS ,Byte 3 address select" "0,1"
|
|
bitfld.long 0x0 7. ",Byte 2 address select" "0,1"
|
|
bitfld.long 0x0 6. ",Byte 1 address select" "0,1"
|
|
bitfld.long 0x0 5. ",Byte 0 address select" "0,1"
|
|
bitfld.long 0x00 1.--2. " S ,Supervisor Access Control" "User/system/supervisor,Privileged,User,Any"
|
|
bitfld.long 0x00 0. " B ,Breakpoint Enable" "Disabled,Enabled"
|
|
group c14:0x45++0x00
|
|
line.long 0x00 "BVR5,Breakpoint Value Register 5"
|
|
hexmask.long 0x00 0.--31. 1. " BV5 ,Breakpoint Value 5"
|
|
group c14:0x55++0x00
|
|
line.long 0x00 "BCR5,Breakpoint Control Register 5"
|
|
bitfld.long 0x00 24.--28. " BAM ,Breakpoint Address Mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF"
|
|
bitfld.long 0x00 20.--22. " M ,BVR Meaning" "IVA match,Linked IVA match,Unlinked ID,Linked ID,IVA mismatch,Linked IVA mismatch,?..."
|
|
bitfld.long 0x00 16.--19. " LBRP ,Linked BRP Number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15"
|
|
bitfld.long 0x00 14.--15. " SWAC ,Secure World Access Control" "Both,Nonsecure,Secure,?..."
|
|
textline " "
|
|
bitfld.long 0x0 8. " BAS ,Byte 3 address select" "0,1"
|
|
bitfld.long 0x0 7. ",Byte 2 address select" "0,1"
|
|
bitfld.long 0x0 6. ",Byte 1 address select" "0,1"
|
|
bitfld.long 0x0 5. ",Byte 0 address select" "0,1"
|
|
bitfld.long 0x00 1.--2. " S ,Supervisor Access Control" "User/system/supervisor,Privileged,User,Any"
|
|
bitfld.long 0x00 0. " B ,Breakpoint Enable" "Disabled,Enabled"
|
|
group c14:0x46++0x00
|
|
line.long 0x00 "BVR6,Breakpoint Value Register 6"
|
|
hexmask.long 0x00 0.--31. 1. " BV6 ,Breakpoint Value 6"
|
|
group c14:0x56++0x00
|
|
line.long 0x00 "BCR6,Breakpoint Control Register 6"
|
|
bitfld.long 0x00 24.--28. " BAM ,Breakpoint Address Mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF"
|
|
bitfld.long 0x00 20.--22. " M ,BVR Meaning" "IVA match,Linked IVA match,Unlinked ID,Linked ID,IVA mismatch,Linked IVA mismatch,?..."
|
|
bitfld.long 0x00 16.--19. " LBRP ,Linked BRP Number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15"
|
|
bitfld.long 0x00 14.--15. " SWAC ,Secure World Access Control" "Both,Nonsecure,Secure,?..."
|
|
textline " "
|
|
bitfld.long 0x0 8. " BAS ,Byte 3 address select" "0,1"
|
|
bitfld.long 0x0 7. ",Byte 2 address select" "0,1"
|
|
bitfld.long 0x0 6. ",Byte 1 address select" "0,1"
|
|
bitfld.long 0x0 5. ",Byte 0 address select" "0,1"
|
|
bitfld.long 0x00 1.--2. " S ,Supervisor Access Control" "User/system/supervisor,Privileged,User,Any"
|
|
bitfld.long 0x00 0. " B ,Breakpoint Enable" "Disabled,Enabled"
|
|
group c14:0x47++0x00
|
|
line.long 0x00 "BVR7,Breakpoint Value Register 7"
|
|
hexmask.long 0x00 0.--31. 1. " BV7 ,Breakpoint Value 7"
|
|
group c14:0x57++0x00
|
|
line.long 0x00 "BCR7,Breakpoint Control Register 7"
|
|
bitfld.long 0x00 24.--28. " BAM ,Breakpoint Address Mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF"
|
|
bitfld.long 0x00 20.--22. " M ,BVR Meaning" "IVA match,Linked IVA match,Unlinked ID,Linked ID,IVA mismatch,Linked IVA mismatch,?..."
|
|
bitfld.long 0x00 16.--19. " LBRP ,Linked BRP Number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15"
|
|
bitfld.long 0x00 14.--15. " SWAC ,Secure World Access Control" "Both,Nonsecure,Secure,?..."
|
|
textline " "
|
|
bitfld.long 0x0 8. " BAS ,Byte 3 address select" "0,1"
|
|
bitfld.long 0x0 7. ",Byte 2 address select" "0,1"
|
|
bitfld.long 0x0 6. ",Byte 1 address select" "0,1"
|
|
bitfld.long 0x0 5. ",Byte 0 address select" "0,1"
|
|
bitfld.long 0x00 1.--2. " S ,Supervisor Access Control" "User/system/supervisor,Privileged,User,Any"
|
|
bitfld.long 0x00 0. " B ,Breakpoint Enable" "Disabled,Enabled"
|
|
tree.end
|
|
tree "Watchpoint Control Registers"
|
|
group c14:0x60++0x00
|
|
line.long 0x00 "WVR0,Watchpoint Value Register 0"
|
|
hexmask.long 0x00 2.--31. 0x04 " WA0 ,Watchpoint Address 0"
|
|
group c14:0x70--0x70
|
|
line.long 0x0 "WCR0,Watchpoint Control Register 0"
|
|
bitfld.long 0x0 24.--28. " WAM ,Watchpoint address mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF"
|
|
bitfld.long 0x0 20. " EL ,Enable Linking" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 16.--19. " LBN ,Linked BRP number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15"
|
|
bitfld.long 0x0 14.--15. " SWAC ,Secure world access control" "Non-secure & Secure,Non-secure,Secure,?..."
|
|
textline " "
|
|
bitfld.long 0x0 12. " BAS ,Byte 7 address select" "0,1"
|
|
bitfld.long 0x0 11. ",Byte 6 address select" "0,1"
|
|
bitfld.long 0x0 10. ",Byte 5 address select" "0,1"
|
|
bitfld.long 0x0 9. ",Byte 4 address select" "0,1"
|
|
bitfld.long 0x0 8. ",Byte 3 address select" "0,1"
|
|
bitfld.long 0x0 7. ",Byte 2 address select" "0,1"
|
|
bitfld.long 0x0 6. ",Byte 1 address select" "0,1"
|
|
bitfld.long 0x0 5. ",Byte 0 address select" "0,1"
|
|
textline " "
|
|
bitfld.long 0x0 3.--4. " RD/WR ,Load/Store access control" "Reserved,Load,Store,Any"
|
|
bitfld.long 0x0 1.--2. " PAC ,Privileged access control" "Reserved,Privileged,USR,Any"
|
|
textline " "
|
|
bitfld.long 0x0 0. " WE ,Watchpoint enable" "Disabled,Enabled"
|
|
group c14:0x61++0x00
|
|
line.long 0x00 "WVR1,Watchpoint Value Register 1"
|
|
hexmask.long 0x00 2.--31. 0x04 " WA1 ,Watchpoint Address 1"
|
|
group c14:0x71--0x71
|
|
line.long 0x0 "WCR1,Watchpoint Control Register 1"
|
|
bitfld.long 0x0 24.--28. " WAM ,Watchpoint address mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF"
|
|
bitfld.long 0x0 20. " EL ,Enable Linking" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 16.--19. " LBN ,Linked BRP number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15"
|
|
bitfld.long 0x0 14.--15. " SWAC ,Secure world access control" "Non-secure & Secure,Non-secure,Secure,?..."
|
|
textline " "
|
|
bitfld.long 0x0 12. " BAS ,Byte 7 address select" "0,1"
|
|
bitfld.long 0x0 11. ",Byte 6 address select" "0,1"
|
|
bitfld.long 0x0 10. ",Byte 5 address select" "0,1"
|
|
bitfld.long 0x0 9. ",Byte 4 address select" "0,1"
|
|
bitfld.long 0x0 8. ",Byte 3 address select" "0,1"
|
|
bitfld.long 0x0 7. ",Byte 2 address select" "0,1"
|
|
bitfld.long 0x0 6. ",Byte 1 address select" "0,1"
|
|
bitfld.long 0x0 5. ",Byte 0 address select" "0,1"
|
|
textline " "
|
|
bitfld.long 0x0 3.--4. " RD/WR ,Load/Store access control" "Reserved,Load,Store,Any"
|
|
bitfld.long 0x0 1.--2. " PAC ,Privileged access control" "Reserved,Privileged,USR,Any"
|
|
textline " "
|
|
bitfld.long 0x0 0. " WE ,Watchpoint enable" "Disabled,Enabled"
|
|
group c14:0x62++0x00
|
|
line.long 0x00 "WVR2,Watchpoint Value Register 2"
|
|
hexmask.long 0x00 2.--31. 0x04 " WA2 ,Watchpoint Address 2"
|
|
group c14:0x72--0x72
|
|
line.long 0x0 "WCR2,Watchpoint Control Register 2"
|
|
bitfld.long 0x0 24.--28. " WAM ,Watchpoint address mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF"
|
|
bitfld.long 0x0 20. " EL ,Enable Linking" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 16.--19. " LBN ,Linked BRP number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15"
|
|
bitfld.long 0x0 14.--15. " SWAC ,Secure world access control" "Non-secure & Secure,Non-secure,Secure,?..."
|
|
textline " "
|
|
bitfld.long 0x0 12. " BAS ,Byte 7 address select" "0,1"
|
|
bitfld.long 0x0 11. ",Byte 6 address select" "0,1"
|
|
bitfld.long 0x0 10. ",Byte 5 address select" "0,1"
|
|
bitfld.long 0x0 9. ",Byte 4 address select" "0,1"
|
|
bitfld.long 0x0 8. ",Byte 3 address select" "0,1"
|
|
bitfld.long 0x0 7. ",Byte 2 address select" "0,1"
|
|
bitfld.long 0x0 6. ",Byte 1 address select" "0,1"
|
|
bitfld.long 0x0 5. ",Byte 0 address select" "0,1"
|
|
textline " "
|
|
bitfld.long 0x0 3.--4. " RD/WR ,Load/Store access control" "Reserved,Load,Store,Any"
|
|
bitfld.long 0x0 1.--2. " PAC ,Privileged access control" "Reserved,Privileged,USR,Any"
|
|
textline " "
|
|
bitfld.long 0x0 0. " WE ,Watchpoint enable" "Disabled,Enabled"
|
|
group c14:0x63++0x00
|
|
line.long 0x00 "WVR3,Watchpoint Value Register 3"
|
|
hexmask.long 0x00 2.--31. 0x04 " WA3 ,Watchpoint Address 3"
|
|
group c14:0x73--0x73
|
|
line.long 0x0 "WCR3,Watchpoint Control Register 3"
|
|
bitfld.long 0x0 24.--28. " WAM ,Watchpoint address mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF"
|
|
bitfld.long 0x0 20. " EL ,Enable Linking" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 16.--19. " LBN ,Linked BRP number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15"
|
|
bitfld.long 0x0 14.--15. " SWAC ,Secure world access control" "Non-secure & Secure,Non-secure,Secure,?..."
|
|
textline " "
|
|
bitfld.long 0x0 12. " BAS ,Byte 7 address select" "0,1"
|
|
bitfld.long 0x0 11. ",Byte 6 address select" "0,1"
|
|
bitfld.long 0x0 10. ",Byte 5 address select" "0,1"
|
|
bitfld.long 0x0 9. ",Byte 4 address select" "0,1"
|
|
bitfld.long 0x0 8. ",Byte 3 address select" "0,1"
|
|
bitfld.long 0x0 7. ",Byte 2 address select" "0,1"
|
|
bitfld.long 0x0 6. ",Byte 1 address select" "0,1"
|
|
bitfld.long 0x0 5. ",Byte 0 address select" "0,1"
|
|
textline " "
|
|
bitfld.long 0x0 3.--4. " RD/WR ,Load/Store access control" "Reserved,Load,Store,Any"
|
|
bitfld.long 0x0 1.--2. " PAC ,Privileged access control" "Reserved,Privileged,USR,Any"
|
|
textline " "
|
|
bitfld.long 0x0 0. " WE ,Watchpoint enable" "Disabled,Enabled"
|
|
group c14:0x64++0x00
|
|
line.long 0x00 "WVR4,Watchpoint Value Register 4"
|
|
hexmask.long 0x00 2.--31. 0x04 " WA4 ,Watchpoint Address 4"
|
|
group c14:0x74--0x74
|
|
line.long 0x0 "WCR4,Watchpoint Control Register 4"
|
|
bitfld.long 0x0 24.--28. " WAM ,Watchpoint address mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF"
|
|
bitfld.long 0x0 20. " EL ,Enable Linking" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 16.--19. " LBN ,Linked BRP number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15"
|
|
bitfld.long 0x0 14.--15. " SWAC ,Secure world access control" "Non-secure & Secure,Non-secure,Secure,?..."
|
|
textline " "
|
|
bitfld.long 0x0 12. " BAS ,Byte 7 address select" "0,1"
|
|
bitfld.long 0x0 11. ",Byte 6 address select" "0,1"
|
|
bitfld.long 0x0 10. ",Byte 5 address select" "0,1"
|
|
bitfld.long 0x0 9. ",Byte 4 address select" "0,1"
|
|
bitfld.long 0x0 8. ",Byte 3 address select" "0,1"
|
|
bitfld.long 0x0 7. ",Byte 2 address select" "0,1"
|
|
bitfld.long 0x0 6. ",Byte 1 address select" "0,1"
|
|
bitfld.long 0x0 5. ",Byte 0 address select" "0,1"
|
|
textline " "
|
|
bitfld.long 0x0 3.--4. " RD/WR ,Load/Store access control" "Reserved,Load,Store,Any"
|
|
bitfld.long 0x0 1.--2. " PAC ,Privileged access control" "Reserved,Privileged,USR,Any"
|
|
textline " "
|
|
bitfld.long 0x0 0. " WE ,Watchpoint enable" "Disabled,Enabled"
|
|
group c14:0x65++0x00
|
|
line.long 0x00 "WVR5,Watchpoint Value Register 5"
|
|
hexmask.long 0x00 2.--31. 0x04 " WA5 ,Watchpoint Address 5"
|
|
group c14:0x75--0x75
|
|
line.long 0x0 "WCR5,Watchpoint Control Register 5"
|
|
bitfld.long 0x0 24.--28. " WAM ,Watchpoint address mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF"
|
|
bitfld.long 0x0 20. " EL ,Enable Linking" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 16.--19. " LBN ,Linked BRP number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15"
|
|
bitfld.long 0x0 14.--15. " SWAC ,Secure world access control" "Non-secure & Secure,Non-secure,Secure,?..."
|
|
textline " "
|
|
bitfld.long 0x0 12. " BAS ,Byte 7 address select" "0,1"
|
|
bitfld.long 0x0 11. ",Byte 6 address select" "0,1"
|
|
bitfld.long 0x0 10. ",Byte 5 address select" "0,1"
|
|
bitfld.long 0x0 9. ",Byte 4 address select" "0,1"
|
|
bitfld.long 0x0 8. ",Byte 3 address select" "0,1"
|
|
bitfld.long 0x0 7. ",Byte 2 address select" "0,1"
|
|
bitfld.long 0x0 6. ",Byte 1 address select" "0,1"
|
|
bitfld.long 0x0 5. ",Byte 0 address select" "0,1"
|
|
textline " "
|
|
bitfld.long 0x0 3.--4. " RD/WR ,Load/Store access control" "Reserved,Load,Store,Any"
|
|
bitfld.long 0x0 1.--2. " PAC ,Privileged access control" "Reserved,Privileged,USR,Any"
|
|
textline " "
|
|
bitfld.long 0x0 0. " WE ,Watchpoint enable" "Disabled,Enabled"
|
|
group c14:0x66++0x00
|
|
line.long 0x00 "WVR6,Watchpoint Value Register 6"
|
|
hexmask.long 0x00 2.--31. 0x04 " WA6 ,Watchpoint Address 6"
|
|
group c14:0x76--0x76
|
|
line.long 0x0 "WCR6,Watchpoint Control Register 6"
|
|
bitfld.long 0x0 24.--28. " WAM ,Watchpoint address mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF"
|
|
bitfld.long 0x0 20. " EL ,Enable Linking" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 16.--19. " LBN ,Linked BRP number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15"
|
|
bitfld.long 0x0 14.--15. " SWAC ,Secure world access control" "Non-secure & Secure,Non-secure,Secure,?..."
|
|
textline " "
|
|
bitfld.long 0x0 12. " BAS ,Byte 7 address select" "0,1"
|
|
bitfld.long 0x0 11. ",Byte 6 address select" "0,1"
|
|
bitfld.long 0x0 10. ",Byte 5 address select" "0,1"
|
|
bitfld.long 0x0 9. ",Byte 4 address select" "0,1"
|
|
bitfld.long 0x0 8. ",Byte 3 address select" "0,1"
|
|
bitfld.long 0x0 7. ",Byte 2 address select" "0,1"
|
|
bitfld.long 0x0 6. ",Byte 1 address select" "0,1"
|
|
bitfld.long 0x0 5. ",Byte 0 address select" "0,1"
|
|
textline " "
|
|
bitfld.long 0x0 3.--4. " RD/WR ,Load/Store access control" "Reserved,Load,Store,Any"
|
|
bitfld.long 0x0 1.--2. " PAC ,Privileged access control" "Reserved,Privileged,USR,Any"
|
|
textline " "
|
|
bitfld.long 0x0 0. " WE ,Watchpoint enable" "Disabled,Enabled"
|
|
group c14:0x67++0x00
|
|
line.long 0x00 "WVR7,Watchpoint Value Register 7"
|
|
hexmask.long 0x00 2.--31. 0x04 " WA7 ,Watchpoint Address 7"
|
|
group c14:0x77--0x77
|
|
line.long 0x0 "WCR7,Watchpoint Control Register 7"
|
|
bitfld.long 0x0 24.--28. " WAM ,Watchpoint address mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF"
|
|
bitfld.long 0x0 20. " EL ,Enable Linking" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 16.--19. " LBN ,Linked BRP number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15"
|
|
bitfld.long 0x0 14.--15. " SWAC ,Secure world access control" "Non-secure & Secure,Non-secure,Secure,?..."
|
|
textline " "
|
|
bitfld.long 0x0 12. " BAS ,Byte 7 address select" "0,1"
|
|
bitfld.long 0x0 11. ",Byte 6 address select" "0,1"
|
|
bitfld.long 0x0 10. ",Byte 5 address select" "0,1"
|
|
bitfld.long 0x0 9. ",Byte 4 address select" "0,1"
|
|
bitfld.long 0x0 8. ",Byte 3 address select" "0,1"
|
|
bitfld.long 0x0 7. ",Byte 2 address select" "0,1"
|
|
bitfld.long 0x0 6. ",Byte 1 address select" "0,1"
|
|
bitfld.long 0x0 5. ",Byte 0 address select" "0,1"
|
|
textline " "
|
|
bitfld.long 0x0 3.--4. " RD/WR ,Load/Store access control" "Reserved,Load,Store,Any"
|
|
bitfld.long 0x0 1.--2. " PAC ,Privileged access control" "Reserved,Privileged,USR,Any"
|
|
textline " "
|
|
bitfld.long 0x0 0. " WE ,Watchpoint enable" "Disabled,Enabled"
|
|
group c14:0x006--0x006
|
|
line.long 0x0 "WFAR,Watchpoint Fault Address Register"
|
|
hexmask.long.long 0x00 1.--31. 0x02 " WFAR ,Address of the watchpointed instruction"
|
|
tree.end
|
|
AUTOINDENT.POP
|
|
tree.end
|
|
elif (CORENAME()=="CORTEXR4")
|
|
tree "Core Registers (Cortex-R4)"
|
|
AUTOINDENT.PUSH
|
|
AUTOINDENT.OFF
|
|
width 0x8
|
|
; --------------------------------------------------------------------------------
|
|
; Identification registers
|
|
; --------------------------------------------------------------------------------
|
|
tree "ID Registers"
|
|
rgroup c15:0x0--0x0
|
|
line.long 0x0 "MIDR,Main ID Register"
|
|
hexmask.long.byte 0x0 24.--31. 0x1 " IMPL ,Implementer code"
|
|
bitfld.long 0x0 20.--23. " VAR ,Variant" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x0 16.--19. " ARCH , Architecture" "Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,ARMv7"
|
|
textline " "
|
|
hexmask.long.word 0x0 4.--15. 0x1 " PART ,Primary Part Number"
|
|
bitfld.long 0x0 0.--3. " REV ,Revision Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rgroup c15:0x100--0x100
|
|
line.long 0x0 "CTR,Cache Type Register"
|
|
bitfld.long 0x0 29.--31. " FORMAT ,Format" "Not ARMv7,Not ARMv7,Not ARMv7,Not ARMv7,ARMv7,Not ARMv7,Not ARMv7,Not ARMv7"
|
|
bitfld.long 0x0 16.--19. " DMINLINE ,D-Cache Minimum Line Size" "1 word,2 words,4 words,8 words,16 words,32 words,64 words,128 words,256 words,512 words,1024 words,2048 words,4096 words,8192 words,16384 words,32768 words"
|
|
bitfld.long 0x0 14.--15. " L1POLICY ,L1 Instruction cache policy" "Reserved,ASID,Virtual,Physical"
|
|
textline " "
|
|
bitfld.long 0x0 0.--3. " IMINLINE ,I-Cache Minimum Line Size" "1 word,2 words,4 words,8 words,16 words,32 words,64 words,128 words,256 words,512 words,1024 words,2048 words,4096 words,8192 words,16384 words,32768 words"
|
|
rgroup c15:0x200--0x200
|
|
line.long 0x0 "TCMSR,Tighly-Coupled Memory Status Register"
|
|
bitfld.long 0x0 16.--19. " DTCMS ,Data Banks" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x0 0.--3. " ITCMS ,Instruction Banks" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rgroup c15:0x400--0x400
|
|
line.long 0x0 "MPUIR,MPU type register"
|
|
hexmask.long.byte 0x00 8.--15. 1. " REGNUM ,Number of regions"
|
|
bitfld.long 0x00 0. " TYPE ,Type of MPU regions" "Unified,Seperated"
|
|
rgroup c15:0x500--0x500
|
|
line.long 0x0 "MPIDR,Multiprocessor Affinity Register"
|
|
hexmask.long.byte 0x00 16.--23. 1. " AFFL2 ,Affitnity Level 2"
|
|
hexmask.long.byte 0x00 8.--15. 1. " AFFL1 ,Affitnity Level 1"
|
|
hexmask.long.byte 0x00 0.--7. 1. " AFFL0 ,Affitnity Level 0"
|
|
textline " "
|
|
rgroup c15:0x0410++0x00
|
|
line.long 0x00 "MMFR0,Memory Model Feature Register 0"
|
|
bitfld.long 0x00 28.--31. " IT ,Instruction Type Support" "Reserved,Reserved,Reserved,Supported,?..."
|
|
bitfld.long 0x00 24.--27. " FCSE ,Fast Context Switch Memory Mappings Support" "Reserved,Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 20.--23. " ACR ,Auxiliary Control Register Support" "Reserved,Supported,?..."
|
|
bitfld.long 0x00 16.--19. " TCM ,TCM and Associated DMA Support" "Not supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 12.--15. " CC_PLEA ,Cache Coherency With PLE Agent/Shared Memory Support" "Not supported,?..."
|
|
bitfld.long 0x00 8.--11. " CC_CPUA ,Cache Coherency Support With CPU Agent/Shared Memory Support" "Not supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " PMSA ,Physical Memory System Architecture (PMSA) Support" "Not supported,?..."
|
|
bitfld.long 0x00 0.--3. " VMSA ,Virtual Memory System Architecture (VMSA) Support" "Reserved,Reserved,Reserved,Supported,?..."
|
|
rgroup c15:0x0510++0x00
|
|
line.long 0x00 "MMFR1,Memory Model Feature Register 1"
|
|
bitfld.long 0x00 28.--31. " BTB ,Branch Target Buffer Support" "Reserved,Reserved,Not required,?..."
|
|
bitfld.long 0x00 24.--27. " L1TCO ,Test and Clean Operations on Data Cache/Harvard/Unified Architecture Support" "Not supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 20.--23. " L1UCMO ,L1 Cache/All Maintenance Operations/Unified Architecture Support" "Not supported,?..."
|
|
bitfld.long 0x00 16.--19. " L1HCMO ,L1 Cache/All Maintenance Operations/Harvard Architecture Support" "Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 12.--15. " L1UCLMOSW ,L1 Cache Line Maintenance Operations by Set and Way/Unified Architecture Support" "Not supported,?..."
|
|
bitfld.long 0x00 8.--11. " L1HCLMOSW ,L1 Cache Line Maintenance Operations by Set and Way/Harvard Architecture Support" "Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " L1UCLMOMVA ,L1 Cache Line Maintenance Operations by MVA/Unified Architecture Support" "Not supported,?..."
|
|
bitfld.long 0x00 0.--3. " L1HCLMOMVA ,L1 Cache Line Maintenance Operations by MVA/Harvard Architecture" "Supported,?..."
|
|
rgroup c15:0x0610++0x00
|
|
line.long 0x00 "MMFR2,Memory Model Feature Register 2"
|
|
bitfld.long 0x00 28.--31. " HAF ,Hardware Access Flag Support" "Not supported,?..."
|
|
bitfld.long 0x00 24.--27. " WFI ,Wait for Interrupt Stalling Support" "Reserved,Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 20.--23. " MBF ,Memory Barrier Operations Support" "Reserved,Reserved,Supported,?..."
|
|
bitfld.long 0x00 16.--19. " UTLBMO ,TLB Maintenance Operations/Unified Architecture Support" "Not supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 12.--15. " HTLBMO ,TLB Maintenance Operations/Harvard Architecture Support" "Reserved,Reserved,Supported,?..."
|
|
bitfld.long 0x00 8.--11. " HL1CMRO ,Cache Maintenance Range Operations/Harvard Architecture Support" "Not supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " HL1BPCRO ,Background Prefetch Cache Range Operations/Harvard Architecture Support" "Not supported,?..."
|
|
bitfld.long 0x00 0.--3. " HL1FPCRO ,Foreground Prefetch Cache Range Operations/Harvard Architecture Support" "Not supported,?..."
|
|
rgroup c15:0x0710++0x00
|
|
line.long 0x00 "MMFR3,Memory Model Feature Register 3"
|
|
bitfld.long 0x00 4.--7. " HCMOSW ,Invalidate Cache by Set and Way/Clean by Set and Way/Invalidate and Clean by Set and Way Support" "Reserved,Supported,?..."
|
|
bitfld.long 0x00 0.--3. " HCMOMVA ,Invalidate Cache by MVA/Clean by MVA/Invalidate and Clean by MVA/Invalidate All Support" "Reserved,Supported,?..."
|
|
rgroup c15:0x0020++0x00
|
|
line.long 0x00 "ISAR0,Instruction Set Attribute Register 0"
|
|
bitfld.long 0x00 24.--27. " DIVI ,Divide Instructions Support" "Not supported,?..."
|
|
bitfld.long 0x00 20.--23. " DEBI ,Debug Instructions Support" "Reserved,Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. " CI ,Coprocessor Instructions Support" "Not supported,?..."
|
|
bitfld.long 0x00 12.--15. " CBI ,Combined Compare and Branch Instructions Support" "Reserved,Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 8.--11. " BI ,Bitfield Instructions Support" "Reserved,Supported,?..."
|
|
bitfld.long 0x00 4.--7. " BCI ,Bit Counting Instructions Support" "Reserved,Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " AI ,Atomic Load and Store Instructions Support" "Reserved,Supported,?..."
|
|
rgroup c15:0x0120++0x00
|
|
line.long 0x00 "ISAR1,Instruction Set Attribute Register 1"
|
|
bitfld.long 0x00 28.--31. " JI ,Jazelle Instructions Support" "Reserved,Supported,?..."
|
|
bitfld.long 0x00 24.--27. " INTI ,Instructions That Branch Between ARM and Thumb Code Support" "Reserved,Reserved,Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 20.--23. " IMMI ,Immediate Instructions Support" "Reserved,Supported,?..."
|
|
bitfld.long 0x00 16.--19. " ITEI ,If Then Instructions Support" "Reserved,Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 12.--15. " EXTI ,Sign or Zero Extend Instructions Support" "Reserved,Reserved,Supported,?..."
|
|
bitfld.long 0x00 8.--11. " E2I ,Exception 2 Instructions Support" "Reserved,Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " E1I ,Exception 1 Instructions Support" "Reserved,Supported,?..."
|
|
bitfld.long 0x00 0.--3. " ENDI ,Endianness Control Instructions Support" "Reserved,Supported,?..."
|
|
rgroup c15:0x0220++0x00
|
|
line.long 0x00 "ISAR2,Instruction Set Attribute Register 2"
|
|
bitfld.long 0x00 28.--31. " RI ,Reversal Instructions Support" "Reserved,Reserved,Supported,?..."
|
|
bitfld.long 0x00 24.--27. " PSRI ,PSR Instructions Support" "Reserved,Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 20.--23. " UMI ,Advanced Unsigned Multiply Instructions Support" "Reserved,Reserved,Supported,?..."
|
|
bitfld.long 0x00 16.--19. " SMI ,Advanced Signed Multiply Instructions Support" "Reserved,Reserved,Reserved,Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 12.--15. " MI ,Multiply Instructions Support" "Reserved,Reserved,Supported,?..."
|
|
bitfld.long 0x00 8.--11. " II ,Multi-Access Interruptible Instructions Support" "Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " MHI ,Memory Hint Instructions Support" "Reserved,Reserved,Reserved,Supported,?..."
|
|
bitfld.long 0x00 0.--3. " LSI ,Load and Store Instructions Support" "Reserved,Supported,?..."
|
|
rgroup c15:0x0320++0x00
|
|
line.long 0x00 "ISAR3,Instruction Set Attribute Register 3"
|
|
bitfld.long 0x00 28.--31. " T2E ,Thumb-2 Extensions Support" "Reserved,Supported,?..."
|
|
bitfld.long 0x00 24.--27. " NOPI ,True NOP Instructions Support" "Reserved,Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 20.--23. " TCI ,Thumb Copy Instructions Support" "Reserved,Supported,?..."
|
|
bitfld.long 0x00 16.--19. " TBI ,Table Branch Instructions Support" "Reserved,Reserved,Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 12.--15. " SPI ,Synchronization Primitive Instructions Support" "Reserved,Reserved,Supported,?..."
|
|
bitfld.long 0x00 8.--11. " SWII ,SWI Instructions Support" "Reserved,Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " SIMDI ,Single Instruction Multiple Data (SIMD) Instructions Support" "Reserved,Reserved,Reserved,Supported,?..."
|
|
bitfld.long 0x00 0.--3. " SI ,Saturate Instructions Support" "Reserved,Supported,?..."
|
|
rgroup c15:0x0420++0x00
|
|
line.long 0x00 "ISAR4,Instruction Set Attribute Register 4"
|
|
bitfld.long 0x00 20.--23. " EI ,Exclusive Instructions Support" "Reserved,Supported,?..."
|
|
bitfld.long 0x00 16.--19. " BI ,Barrier Instructions Support" "Reserved,Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 12.--15. " SMII ,SMI Instructions Support" "Reserved,Supported,?..."
|
|
bitfld.long 0x00 8.--11. " WBI ,Write-Back Instructions Support" "Reserved,Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " WSI ,With-Shift Instructions Support" "Reserved,Reserved,Reserved,Reserved,Supported,?..."
|
|
bitfld.long 0x00 0.--3. " UI ,Unprivileged Instructions Support" "Reserved,Reserved,Supported,?..."
|
|
rgroup c15:0x0520++0x00
|
|
line.long 0x00 "ISAR5,Instruction Set Attribute Registers 5 (Reserved)"
|
|
rgroup c15:0x0620++0x00
|
|
line.long 0x00 "ISAR6,Instruction Set Attribute Registers 6 (Reserved)"
|
|
rgroup c15:0x0720++0x00
|
|
line.long 0x00 "ISAR7,Instruction Set Attribute Registers 7 (Reserved)"
|
|
rgroup c15:0x0010++0x00
|
|
line.long 0x00 "ID_PFR0,Processor Feature Register 0"
|
|
bitfld.long 0x00 12.--15. " STATE3 ,Thumb-2 Execution Environment (Thumb-2EE) Support" "Reserved,Supported,?..."
|
|
bitfld.long 0x00 8.--11. " STATE2 ,Java Extension Interface Support" "Not supported,?..."
|
|
bitfld.long 0x00 4.--7. " STATE1 ,Thumb Encoding Supported by the Processor Type" "Reserved,Reserved,Reserved,Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " STATE0 ,ARM Instruction Set Support" "Reserved,Supported,?..."
|
|
rgroup c15:0x0110++0x00
|
|
line.long 0x00 "ID_PFR1,Processor Feature Register 1"
|
|
bitfld.long 0x00 8.--11. " MPM ,Microcontroller Programmer's Model Support" "Supported,?..."
|
|
bitfld.long 0x00 4.--7. " SE ,Security Extensions Architecture v1 Support" "Reserved,Supported,?..."
|
|
bitfld.long 0x00 0.--3. " PM ,Standard ARMv4 Programmer's Model Support" "Reserved,Supported,?..."
|
|
textline " "
|
|
rgroup c15:0x0210++0x00
|
|
line.long 0x00 "ID_DFR0,Debug Feature Register 0"
|
|
bitfld.long 0x00 20.--23. " MDM_MM ,Microcontroller Debug Model Support" "Not supported,?..."
|
|
bitfld.long 0x00 16.--19. " TDM_MM ,Trace Debug Model (Memory-Mapped) Support" "Reserved,Supported,?..."
|
|
bitfld.long 0x00 12.--15. " TDM_CB ,Coprocessor-Based Trace Debug Model Support" "Not supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 8.--11. " CDM_MM ,Memory-Mapped Debug Model Support" "Reserved,Reserved,Reserved,Reserved,Supported,?..."
|
|
bitfld.long 0x00 4.--7. " SDM_CB ,Secure Debug Model (Coprocessor) Support" "Not supported,?..."
|
|
bitfld.long 0x00 0.--3. " CDM_CB ,Coprocessor Debug Model Support" "Not supported,?..."
|
|
rgroup c15:0x0310++0x00
|
|
line.long 0x00 "ID_AFR0,Auxiliary Feature Register 0"
|
|
tree.end
|
|
width 0x8
|
|
tree "System Control and Configuration"
|
|
group c15:0x1--0x1
|
|
line.long 0x0 "SCTLR,Control Register"
|
|
bitfld.long 0x0 31. " IE ,Instruction endianness" "Little,Big"
|
|
bitfld.long 0x0 30. " TE ,Thumb exception enable" "ARM,Thumb"
|
|
bitfld.long 0x0 29. " AFE ,Access Flag Enable" "Disable,Enable"
|
|
bitfld.long 0x0 28. " TRE ,TEX remap enable" "Disable,Enable"
|
|
bitfld.long 0x0 27. " NMFI ,Nonmaskable Fast Interrupt enable" "Disable,Enable"
|
|
textline " "
|
|
bitfld.long 0x0 25. " EE ,Exception endianess" "Little,Big"
|
|
bitfld.long 0x0 24. " VE ,Vector Enable" "Disable,Vectored"
|
|
bitfld.long 0x0 21. " FI ,Fast Interrupts enable" "Disable,Enable"
|
|
bitfld.long 0x0 19. " DZ ,Divide by Zero exception bit" "Disable,Enable"
|
|
bitfld.long 0x0 14. " RR ,Round-Robin bit" "Random,RRobin"
|
|
bitfld.long 0x0 13. " V ,Base Location of Exception Registers" "0x00000000,0xFFFF0000"
|
|
textline " "
|
|
bitfld.long 0x0 12. " I ,Instruction Cache Enable" "Disable,Enable"
|
|
bitfld.long 0x0 11. " Z ,Branch Prediction Enable" "Disable,Enable"
|
|
bitfld.long 0x0 2. " C ,Enable data cache" "Disable,Enable"
|
|
bitfld.long 0x0 1. " A ,Strict Alignment" "Disable,Enable"
|
|
bitfld.long 0x0 0. " M ,MPU Enable" "Disable,Enable"
|
|
textline " "
|
|
group c15:0x101--0x101
|
|
line.long 0x0 "ACTLR,Auxiliary Control Register"
|
|
bitfld.long 0x00 31. " DICDI ,Disable Case C dual issue control" "Enable,Disable"
|
|
bitfld.long 0x00 30. " DIB2DI ,Disable Case B2 dual issue control" "Enable,Disable"
|
|
bitfld.long 0x00 29. " DIB1DI ,Disable Case B1 dual issue control" "Enable,Disable"
|
|
textline " "
|
|
bitfld.long 0x00 28. " DIADI ,Disable Case A dual issue control" "Enable,Disable"
|
|
bitfld.long 0x00 27. " B1TCMPCEN ,B1TCM parity or ECC check enable" "Disable,Enable"
|
|
bitfld.long 0x00 26. " B0TCMPCEN ,B1TCM parity or ECC check enable" "Disable,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ATCMPCEN ,B1TCM parity or ECC check enable" "Disable,Enable"
|
|
bitfld.long 0x00 24. " AXISCEN ,AXI slave cache access enable" "Disable,Enable"
|
|
bitfld.long 0x00 23. " AXISCUEN ,AXI slave cache User mode access enable" "Disable,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 22. " DILSM ,Disable LIL on load/store multiples" "Disable,Enable"
|
|
bitfld.long 0x00 21. " DEOLP ,Disable end of loop prediction" "Disable,Enable"
|
|
bitfld.long 0x00 20. " DBHE ,Disable BH extension" "Enable,Disable"
|
|
textline " "
|
|
bitfld.long 0x00 19. " FRCDIS ,Fetch rate control disable" "Enable,Disable"
|
|
bitfld.long 0x00 17. " RSDIS ,Return stack disable" "Enable,Disable"
|
|
bitfld.long 0x00 15.--16. " BP ,Control of the branch prediction policy" "Normal,Taken,Not taken,?..."
|
|
textline " "
|
|
bitfld.long 0x00 14. " DBWR ,Disable write_burst on AXI master" "Enable,Disable"
|
|
bitfld.long 0x00 13. " DSWT ,Disable should_wait on AXI master" "Enable,Disable"
|
|
bitfld.long 0x00 12. " ERPEG ,Enable random parity error generation" "Disable,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 11. " DOLT ,Disable outstanding line fill on AXI master" "Enable,Disable"
|
|
bitfld.long 0x00 10. " FORA ,Force outer read allocate (ORA) for outer write allocate (OWA) regions" "Not forced,Forced"
|
|
bitfld.long 0x00 9. " FWT ,Force write-through (WT) for write-back (WB) regions" "Not forced,Forced"
|
|
textline " "
|
|
bitfld.long 0x00 8. " FDSnS ,Force D-side to not-shared when MPU is off" "Not forced,Forced"
|
|
bitfld.long 0x00 7. " sMOV ,sMOV disabled" "Enabled,Disabled"
|
|
bitfld.long 0x0 6. " DILS ,Disable low interrupt latency on all load/store instructions" "Enable,Disable"
|
|
textline " "
|
|
bitfld.long 0x00 5. " DA ,DA Disable abort on cache parity error" "Enable,Disable"
|
|
bitfld.long 0x00 4. " EHR ,Enable hardware recovery from cache parity errors" "Disable,Enable"
|
|
bitfld.long 0x00 2. " I1TCMECEN ,Instruction 1 TCM error check enable" "Disable,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 1. " I0TCMECEN ,Instruction 1 TCM error check enable" "Disable,Enable"
|
|
bitfld.long 0x00 0. " ITCMECEN ,Instruction TCM error check enable" "Disable,Enable"
|
|
textline " "
|
|
group c15:0x0f--0x0f
|
|
line.long 0x0 "SACTLR,Secondary Auxiliary Control Register"
|
|
bitfld.long 0x00 22. " DCHE ,Disable hard-error support in the caches" "Enable,Disable"
|
|
bitfld.long 0x00 21. " DR2B ,Enable random 2-bit error genration in cache RAMs" "Disable,Enable"
|
|
bitfld.long 0x00 20. " DF6DI ,F6 dual issue control" "Enable,Disable"
|
|
textline " "
|
|
bitfld.long 0x00 19. " DF2DI ,F2 dual issue control" "Enable,Disable"
|
|
bitfld.long 0x00 18. " DDI ,F1/F3/F4 dual issue control" "Enable,Disable"
|
|
bitfld.long 0x00 17. " DOODPFP ,Out-of-order Double Precision Floating-point control" "Enable,Disable"
|
|
textline " "
|
|
bitfld.long 0x00 16. " DOOFMACS ,Out-of-order FMACS control" "Enable,Disable"
|
|
bitfld.long 0x00 13. " IXC ,Floating-point inexact exception output mask" "Mask,Propagate"
|
|
bitfld.long 0x00 12. " OFC ,Floating-point overflow exception output mask" "Mask,Propagate"
|
|
textline " "
|
|
bitfld.long 0x00 11. " UFC ,Floating-point underflow exception output mask" "Mask,Propagate"
|
|
bitfld.long 0x00 10. " IOC ,Floating-point invalid operation exception output mask" "Mask,Propagate"
|
|
bitfld.long 0x00 9. " DZC ,Floating-point divide-by-zero exception output mask" "Mask,Propagate"
|
|
textline " "
|
|
bitfld.long 0x00 8. " IDC ,Floating-point input denormal exception output mask" "Mask,Propagate"
|
|
bitfld.long 0x00 3. " BTCMECC ,Correction for internal ECC logic on BTCM ports" "Enable,Disable"
|
|
bitfld.long 0x00 2. " ATCMECC ,Correction for internal ECC logic on ATCM port" "Enable,Disable"
|
|
textline " "
|
|
bitfld.long 0x00 1. " BTCMRMW ,Enable 64-bit stores on BTCMs" "Disable,Enable"
|
|
bitfld.long 0x00 0. " ATCMRMW ,Enable 64-bit stores on ATCM" "Disable,Enable"
|
|
textline " "
|
|
group c15:0x201--0x201
|
|
line.long 0x0 "CPACR,Coprocessor Access Control Register"
|
|
bitfld.long 0x0 26.--27. " CP13 ,Coprocesor access control" "Denied,Privileged,Reserved,Full"
|
|
bitfld.long 0x0 24.--25. " CP12 ,Coprocesor access control" "Denied,Privileged,Reserved,Full"
|
|
textline " "
|
|
bitfld.long 0x0 22.--23. " CP11 ,Coprocesor access control" "Denied,Privileged,Reserved,Full"
|
|
bitfld.long 0x0 20.--21. " CP10 ,Coprocesor access control" "Denied,Privileged,Reserved,Full"
|
|
textline " "
|
|
bitfld.long 0x0 18.--19. " CP9 ,Coprocesor access control" "Denied,Privileged,Reserved,Full"
|
|
bitfld.long 0x0 16.--17. " CP8 ,Coprocesor access control" "Denied,Privileged,Reserved,Full"
|
|
textline " "
|
|
bitfld.long 0x0 14.--15. " CP7 ,Coprocesor access control" "Denied,Privileged,Reserved,Full"
|
|
bitfld.long 0x0 12.--13. " CP6 ,Coprocesor access control" "Denied,Privileged,Reserved,Full"
|
|
textline " "
|
|
bitfld.long 0x0 10.--11. " CP5 ,Coprocesor access control" "Denied,Privileged,Reserved,Full"
|
|
bitfld.long 0x0 8.--9. " CP4 ,Coprocesor access control" "Denied,Privileged,Reserved,Full"
|
|
textline " "
|
|
bitfld.long 0x0 6.--7. " CP3 ,Coprocesor access control" "Denied,Privileged,Reserved,Full"
|
|
bitfld.long 0x0 4.--5. " CP2 ,Coprocesor access control" "Denied,Privileged,Reserved,Full"
|
|
textline " "
|
|
bitfld.long 0x0 2.--3. " CP1 ,Coprocesor access control" "Denied,Privileged,Reserved,Full"
|
|
bitfld.long 0x0 0.--1. " CP0 ,Coprocesor access control" "Denied,Privileged,Reserved,Full"
|
|
textline " "
|
|
group.long c15:0x0b--0x0b
|
|
line.long 0x00 "SPC,Slave Port Control"
|
|
bitfld.long 0x00 1. " PRIV ,Privilege access only" "User/Privilege,Privilege only"
|
|
bitfld.long 0x00 0. " AXISLEN ,AXI slave port disable" "Enabled,Disabled"
|
|
tree.end
|
|
width 0x8
|
|
tree "MPU Control and Configuration"
|
|
group c15:0x0001--0x0001
|
|
line.long 0x0 "SCTLR,Control Register"
|
|
bitfld.long 0x0 31. " IE ,Instruction endianness" "Little,Big"
|
|
bitfld.long 0x0 30. " TE ,Thumb exception enable" "ARM,Thumb"
|
|
bitfld.long 0x0 29. " AFE ,Access Flag Enable" "Disable,Enable"
|
|
bitfld.long 0x0 28. " TRE ,TEX remap enable" "Disable,Enable"
|
|
bitfld.long 0x0 27. " NMFI ,Nonmaskable Fast Interrupt enable" "Disable,Enable"
|
|
textline " "
|
|
bitfld.long 0x0 25. " EE ,Exception endianess" "Little,Big"
|
|
bitfld.long 0x0 24. " VE ,Vector Enable" "Disable,Vectored"
|
|
bitfld.long 0x0 21. " FI ,Fast Interrupts enable" "Disable,Enable"
|
|
bitfld.long 0x0 19. " DZ ,Divide by Zero exception bit" "Disable,Enable"
|
|
bitfld.long 0x0 14. " RR ,Round-Robin bit" "Random,RRobin"
|
|
bitfld.long 0x0 13. " V ,Base Location of Exception Registers" "0x00000000,0xFFFF0000"
|
|
textline " "
|
|
bitfld.long 0x0 12. " I ,Instruction Cache Enable" "Disable,Enable"
|
|
bitfld.long 0x0 11. " Z ,Branch Prediction Enable" "Disable,Enable"
|
|
bitfld.long 0x0 2. " C ,Enable data cache" "Disable,Enable"
|
|
bitfld.long 0x0 1. " A ,Strict Alignment" "Disable,Enable"
|
|
bitfld.long 0x0 0. " M ,MPU Enable" "Disable,Enable"
|
|
textline " "
|
|
group.long c15:0x0005++0x00
|
|
line.long 0x00 "DFSR,Data Fault Status Register"
|
|
bitfld.long 0x00 12. " EXT ,External Abort Qualifier" "DECERR,SLVERR"
|
|
bitfld.long 0x00 11. " RW ,Access Caused an Abort Type" "Read,Write"
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " DOMAIN ,Domain Accessed When a Data Fault Occurs" "D0,D1,D2,D3,D4,D5,D6,D7,D8,D9,D10,D11,D12,D13,D14,D15"
|
|
bitfld.long 0x00 0.--3. 10. " STATUS ,Generated Exception Type" "Reserved,Alignment,Debug,Access/section,Instruction,Translation/section,Access/page,Translation/page,Nontranslation/synchronous external,Domain/section,Reserved,Domain/page,L1/external,Permission/section,L2/external,Permission/page,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Asynchronous external,?..."
|
|
group.long c15:0x0015++0x00
|
|
line.long 0x00 "ADFSR,Auxiliary Data Fault Status Register"
|
|
group.long c15:0x0006++0x00
|
|
line.long 0x00 "DFAR,Data Fault Address Register"
|
|
group.long c15:0x0105++0x00
|
|
line.long 0x00 "IFSR,Instruction Fault Status Register"
|
|
bitfld.long 0x00 12. " EXT ,External Abort Qualifier" "DECERR,SLVERR"
|
|
bitfld.long 0x00 0.--3. 10. " STATUS ,Generated Exception Type" "Reserved,Alignment,Debug,Access/section,Instruction,Translation/section,Access/page,Translation/page,Nontranslation/synchronous external,Domain/section,Reserved,Domain/page,L1/external,Permission/section,L2/external,Permission/page,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Asynchronous external,?..."
|
|
group.long c15:0x0115++0x00
|
|
line.long 0x00 "AIFSR,Auxiliary Instruction Fault Status Register"
|
|
group.long c15:0x0206++0x00
|
|
line.long 0x00 "IFAR,Instruction Fault Address Register"
|
|
textline " "
|
|
group c15:0x0016++0x00
|
|
line.long 0x00 "RBAR,Region Base Address Register"
|
|
hexmask.long 0x00 5.--31. 0x20 " BA ,Base address"
|
|
group c15:0x0216++0x00
|
|
line.long 0x00 "RSER,Region Size and Enable Register"
|
|
bitfld.long 0x00 15. " SD ,Subregion 7 disable" "-,D"
|
|
bitfld.long 0x00 14. " ,Subregion 6 disable" "-,D"
|
|
bitfld.long 0x00 13. " ,Subregion 5 disable" "-,D"
|
|
bitfld.long 0x00 12. " ,Subregion 4 disable" "-,D"
|
|
bitfld.long 0x00 11. " ,Subregion 3 disable" "-,D"
|
|
bitfld.long 0x00 10. " ,Subregion 2 disable" "-,D"
|
|
bitfld.long 0x00 9. " ,Subregion 1 disable" "-,D"
|
|
bitfld.long 0x00 8. " ,Subregion 0 disable" "-,D"
|
|
bitfld.long 0x00 1.--5. " RS ,Region size" "Unpredictable,Unpredictable,Unpredictable,Unpredictable,32 bytes,64 bytes,128 bytes,256 bytes,512 bytes,1KB,2KB,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB"
|
|
bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled"
|
|
group c15:0x0416++0x00
|
|
line.long 0x00 "RACR,Region Access Control Register"
|
|
bitfld.long 0x00 12. " XN ,Execute never" "-,NoExec"
|
|
bitfld.long 0x00 2. " S ,Share" "No,Yes"
|
|
bitfld.long 0x00 8.--10. " AP ,Access permission" "None,Privileged,User read-only,Full,Reserved,Privileged read,Read-only,Reserved"
|
|
bitfld.long 0x00 0.--1. 3.--5. " TYPE ,Region type" "Strongly-ordered,Shareable Device,Outer and Inner write-through/no write-allocate,Outer and Inner write-back/no write-allocate,Outer and Inner Non-cacheable,00101,00110,Outer and Inner write-back/write-allocate,Non-shareable Device,01001,01010,01011,01100,01101,01110,01111,O:Non-cacheable I:Non-cacheable,O:Non-cacheable I:Write-back/write-allocate,O:Non-cacheable I:Write-through/no write-allocate,O:Non-cacheable I:Write-back/no write-allocate,O:Write-back/write-allocate I:Non-cacheable,O:Write-back/write-allocate I:Write-back/write-allocate,O:Write-back/write-allocate I:Write-through/no write-allocate,O:Write-back/write-allocate I:Write-back/no write-allocate,O:Write-through/no write-allocate I:Non-cacheable,O:Write-through/no write-allocate I:Write-back/write-allocate,O:Write-through/no write-allocate I:Write-through/no write-allocate,O:Write-through/no write-allocate I:Write-back/no write-allocate,O:Write-back/no write-allocate I:Non-cacheable,O:Write-back/no write-allocate I:Write-back/write-allocate,O:Write-back/no write-allocate I:Write-through/no write-allocate,O:Write-back/no write-allocate I:Write-back/no write-allocate"
|
|
group c15:0x0026++0x00
|
|
line.long 0x00 "MRNR,Memory Region Number Register"
|
|
bitfld.long 0x00 0.--3. " REGION ,Defines the group of registers to be accessed" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
group c15:0x010d++0x00
|
|
line.long 0x00 "CIDR,Context ID Register"
|
|
group.long c15:0x20d++0x00
|
|
line.long 0x00 "TIDRURW,User read/write Thread and Process ID Register"
|
|
group.long c15:0x30d++0x00
|
|
line.long 0x00 "TIDRURO,User read only Thread and Process ID Register"
|
|
group.long c15:0x40d++0x00
|
|
line.long 0x00 "TIDRPRW,Privileged Only Thread and Process ID Register"
|
|
tree "MPU regions"
|
|
group c15:0x0016++0x00
|
|
saveout c15:0x26 %l 0x0
|
|
line.long 0x00 "RBAR0,Region Base Address Register 0"
|
|
hexmask.long 0x00 5.--31. 0x20 " BA ,Base address"
|
|
group c15:0x0216++0x00
|
|
saveout c15:0x26 %l 0x0
|
|
line.long 0x00 "RSER0,Region Size and Enable Register 0"
|
|
bitfld.long 0x00 15. " SD ,Subregion 7 disable" "-,D"
|
|
bitfld.long 0x00 14. " ,Subregion 6 disable" "-,D"
|
|
bitfld.long 0x00 13. " ,Subregion 5 disable" "-,D"
|
|
bitfld.long 0x00 12. " ,Subregion 4 disable" "-,D"
|
|
bitfld.long 0x00 11. " ,Subregion 3 disable" "-,D"
|
|
bitfld.long 0x00 10. " ,Subregion 2 disable" "-,D"
|
|
bitfld.long 0x00 9. " ,Subregion 1 disable" "-,D"
|
|
bitfld.long 0x00 8. " ,Subregion 0 disable" "-,D"
|
|
bitfld.long 0x00 1.--5. " RS ,Region size" "Unpredictable,Unpredictable,Unpredictable,Unpredictable,32 bytes,64 bytes,128 bytes,256 bytes,512 bytes,1KB,2KB,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB"
|
|
bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled"
|
|
group c15:0x0416++0x00
|
|
saveout c15:0x26 %l 0x0
|
|
line.long 0x00 "RACR0,Region Access Control Register 0"
|
|
bitfld.long 0x00 12. " XN ,Execute never" "-,NoExec"
|
|
bitfld.long 0x00 2. " S ,Share" "No,Yes"
|
|
bitfld.long 0x00 8.--10. " AP ,Access permission" "None,Privileged,User read-only,Full,Reserved,Privileged read,Read-only,Reserved"
|
|
bitfld.long 0x00 0.--1. 3.--5. " type ,Region type" "Strongly-ordered,Shareable Device,Outer and Inner write-through/no write-allocate,Outer and Inner write-back/no write-allocate,Outer and Inner Non-cacheable,00101,00110,Outer and Inner write-back/write-allocate,Non-shareable Device,01001,01010,01011,01100,01101,01110,01111,O:Non-cacheable I:Non-cacheable,O:Non-cacheable I:Write-back/write-allocate,O:Non-cacheable I:Write-through/no write-allocate,O:Non-cacheable I:Write-back/no write-allocate,O:Write-back/write-allocate I:Non-cacheable,O:Write-back/write-allocate I:Write-back/write-allocate,O:Write-back/write-allocate I:Write-through/no write-allocate,O:Write-back/write-allocate I:Write-back/no write-allocate,O:Write-through/no write-allocate I:Non-cacheable,O:Write-through/no write-allocate I:Write-back/write-allocate,O:Write-through/no write-allocate I:Write-through/no write-allocate,O:Write-through/no write-allocate I:Write-back/no write-allocate,O:Write-back/no write-allocate I:Non-cacheable,O:Write-back/no write-allocate I:Write-back/write-allocate,O:Write-back/no write-allocate I:Write-through/no write-allocate,O:Write-back/no write-allocate I:Write-back/no write-allocate"
|
|
textline " "
|
|
group c15:0x0016++0x00
|
|
saveout c15:0x26 %l 0x1
|
|
line.long 0x00 "RBAR1,Region Base Address Register 1"
|
|
hexmask.long 0x00 5.--31. 0x20 " BA ,Base address"
|
|
group c15:0x0216++0x00
|
|
saveout c15:0x26 %l 0x1
|
|
line.long 0x00 "RSER1,Region Size and Enable Register 1"
|
|
bitfld.long 0x00 15. " SD ,Subregion 7 disable" "-,D"
|
|
bitfld.long 0x00 14. " ,Subregion 6 disable" "-,D"
|
|
bitfld.long 0x00 13. " ,Subregion 5 disable" "-,D"
|
|
bitfld.long 0x00 12. " ,Subregion 4 disable" "-,D"
|
|
bitfld.long 0x00 11. " ,Subregion 3 disable" "-,D"
|
|
bitfld.long 0x00 10. " ,Subregion 2 disable" "-,D"
|
|
bitfld.long 0x00 9. " ,Subregion 1 disable" "-,D"
|
|
bitfld.long 0x00 8. " ,Subregion 0 disable" "-,D"
|
|
bitfld.long 0x00 1.--5. " RS ,Region size" "Unpredictable,Unpredictable,Unpredictable,Unpredictable,32 bytes,64 bytes,128 bytes,256 bytes,512 bytes,1KB,2KB,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB"
|
|
bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled"
|
|
group c15:0x0416++0x00
|
|
saveout c15:0x26 %l 0x1
|
|
line.long 0x00 "RACR1,Region Access Control Register 1"
|
|
bitfld.long 0x00 12. " XN ,Execute never" "-,NoExec"
|
|
bitfld.long 0x00 2. " S ,Share" "No,Yes"
|
|
bitfld.long 0x00 8.--10. " AP ,Access permission" "None,Privileged,User read-only,Full,Reserved,Privileged read,Read-only,Reserved"
|
|
bitfld.long 0x00 0.--1. 3.--5. " type ,Region type" "Strongly-ordered,Shareable Device,Outer and Inner write-through/no write-allocate,Outer and Inner write-back/no write-allocate,Outer and Inner Non-cacheable,00101,00110,Outer and Inner write-back/write-allocate,Non-shareable Device,01001,01010,01011,01100,01101,01110,01111,O:Non-cacheable I:Non-cacheable,O:Non-cacheable I:Write-back/write-allocate,O:Non-cacheable I:Write-through/no write-allocate,O:Non-cacheable I:Write-back/no write-allocate,O:Write-back/write-allocate I:Non-cacheable,O:Write-back/write-allocate I:Write-back/write-allocate,O:Write-back/write-allocate I:Write-through/no write-allocate,O:Write-back/write-allocate I:Write-back/no write-allocate,O:Write-through/no write-allocate I:Non-cacheable,O:Write-through/no write-allocate I:Write-back/write-allocate,O:Write-through/no write-allocate I:Write-through/no write-allocate,O:Write-through/no write-allocate I:Write-back/no write-allocate,O:Write-back/no write-allocate I:Non-cacheable,O:Write-back/no write-allocate I:Write-back/write-allocate,O:Write-back/no write-allocate I:Write-through/no write-allocate,O:Write-back/no write-allocate I:Write-back/no write-allocate"
|
|
textline " "
|
|
group c15:0x0016++0x00
|
|
saveout c15:0x26 %l 0x2
|
|
line.long 0x00 "RBAR2,Region Base Address Register 2"
|
|
hexmask.long 0x00 5.--31. 0x20 " BA ,Base address"
|
|
group c15:0x0216++0x00
|
|
saveout c15:0x26 %l 0x2
|
|
line.long 0x00 "RSER2,Region Size and Enable Register 2"
|
|
bitfld.long 0x00 15. " SD ,Subregion 7 disable" "-,D"
|
|
bitfld.long 0x00 14. " ,Subregion 6 disable" "-,D"
|
|
bitfld.long 0x00 13. " ,Subregion 5 disable" "-,D"
|
|
bitfld.long 0x00 12. " ,Subregion 4 disable" "-,D"
|
|
bitfld.long 0x00 11. " ,Subregion 3 disable" "-,D"
|
|
bitfld.long 0x00 10. " ,Subregion 2 disable" "-,D"
|
|
bitfld.long 0x00 9. " ,Subregion 1 disable" "-,D"
|
|
bitfld.long 0x00 8. " ,Subregion 0 disable" "-,D"
|
|
bitfld.long 0x00 1.--5. " RS ,Region size" "Unpredictable,Unpredictable,Unpredictable,Unpredictable,32 bytes,64 bytes,128 bytes,256 bytes,512 bytes,1KB,2KB,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB"
|
|
bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled"
|
|
group c15:0x0416++0x00
|
|
saveout c15:0x26 %l 0x2
|
|
line.long 0x00 "RACR2,Region Access Control Register 2"
|
|
bitfld.long 0x00 12. " XN ,Execute never" "-,NoExec"
|
|
bitfld.long 0x00 2. " S ,Share" "No,Yes"
|
|
bitfld.long 0x00 8.--10. " AP ,Access permission" "None,Privileged,User read-only,Full,Reserved,Privileged read,Read-only,Reserved"
|
|
bitfld.long 0x00 0.--1. 3.--5. " type ,Region type" "Strongly-ordered,Shareable Device,Outer and Inner write-through/no write-allocate,Outer and Inner write-back/no write-allocate,Outer and Inner Non-cacheable,00101,00110,Outer and Inner write-back/write-allocate,Non-shareable Device,01001,01010,01011,01100,01101,01110,01111,O:Non-cacheable I:Non-cacheable,O:Non-cacheable I:Write-back/write-allocate,O:Non-cacheable I:Write-through/no write-allocate,O:Non-cacheable I:Write-back/no write-allocate,O:Write-back/write-allocate I:Non-cacheable,O:Write-back/write-allocate I:Write-back/write-allocate,O:Write-back/write-allocate I:Write-through/no write-allocate,O:Write-back/write-allocate I:Write-back/no write-allocate,O:Write-through/no write-allocate I:Non-cacheable,O:Write-through/no write-allocate I:Write-back/write-allocate,O:Write-through/no write-allocate I:Write-through/no write-allocate,O:Write-through/no write-allocate I:Write-back/no write-allocate,O:Write-back/no write-allocate I:Non-cacheable,O:Write-back/no write-allocate I:Write-back/write-allocate,O:Write-back/no write-allocate I:Write-through/no write-allocate,O:Write-back/no write-allocate I:Write-back/no write-allocate"
|
|
textline " "
|
|
group c15:0x0016++0x00
|
|
saveout c15:0x26 %l 0x3
|
|
line.long 0x00 "RBAR3,Region Base Address Register 3"
|
|
hexmask.long 0x00 5.--31. 0x20 " BA ,Base address"
|
|
group c15:0x0216++0x00
|
|
saveout c15:0x26 %l 0x3
|
|
line.long 0x00 "RSER3,Region Size and Enable Register 3"
|
|
bitfld.long 0x00 15. " SD ,Subregion 7 disable" "-,D"
|
|
bitfld.long 0x00 14. " ,Subregion 6 disable" "-,D"
|
|
bitfld.long 0x00 13. " ,Subregion 5 disable" "-,D"
|
|
bitfld.long 0x00 12. " ,Subregion 4 disable" "-,D"
|
|
bitfld.long 0x00 11. " ,Subregion 3 disable" "-,D"
|
|
bitfld.long 0x00 10. " ,Subregion 2 disable" "-,D"
|
|
bitfld.long 0x00 9. " ,Subregion 1 disable" "-,D"
|
|
bitfld.long 0x00 8. " ,Subregion 0 disable" "-,D"
|
|
bitfld.long 0x00 1.--5. " RS ,Region size" "Unpredictable,Unpredictable,Unpredictable,Unpredictable,32 bytes,64 bytes,128 bytes,256 bytes,512 bytes,1KB,2KB,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB"
|
|
bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled"
|
|
group c15:0x0416++0x00
|
|
saveout c15:0x26 %l 0x3
|
|
line.long 0x00 "RACR3,Region Access Control Register 3"
|
|
bitfld.long 0x00 12. " XN ,Execute never" "-,NoExec"
|
|
bitfld.long 0x00 2. " S ,Share" "No,Yes"
|
|
bitfld.long 0x00 8.--10. " AP ,Access permission" "None,Privileged,User read-only,Full,Reserved,Privileged read,Read-only,Reserved"
|
|
bitfld.long 0x00 0.--1. 3.--5. " type ,Region type" "Strongly-ordered,Shareable Device,Outer and Inner write-through/no write-allocate,Outer and Inner write-back/no write-allocate,Outer and Inner Non-cacheable,00101,00110,Outer and Inner write-back/write-allocate,Non-shareable Device,01001,01010,01011,01100,01101,01110,01111,O:Non-cacheable I:Non-cacheable,O:Non-cacheable I:Write-back/write-allocate,O:Non-cacheable I:Write-through/no write-allocate,O:Non-cacheable I:Write-back/no write-allocate,O:Write-back/write-allocate I:Non-cacheable,O:Write-back/write-allocate I:Write-back/write-allocate,O:Write-back/write-allocate I:Write-through/no write-allocate,O:Write-back/write-allocate I:Write-back/no write-allocate,O:Write-through/no write-allocate I:Non-cacheable,O:Write-through/no write-allocate I:Write-back/write-allocate,O:Write-through/no write-allocate I:Write-through/no write-allocate,O:Write-through/no write-allocate I:Write-back/no write-allocate,O:Write-back/no write-allocate I:Non-cacheable,O:Write-back/no write-allocate I:Write-back/write-allocate,O:Write-back/no write-allocate I:Write-through/no write-allocate,O:Write-back/no write-allocate I:Write-back/no write-allocate"
|
|
textline " "
|
|
group c15:0x0016++0x00
|
|
saveout c15:0x26 %l 0x4
|
|
line.long 0x00 "RBAR4,Region Base Address Register 4"
|
|
hexmask.long 0x00 5.--31. 0x20 " BA ,Base address"
|
|
group c15:0x0216++0x00
|
|
saveout c15:0x26 %l 0x4
|
|
line.long 0x00 "RSER4,Region Size and Enable Register 4"
|
|
bitfld.long 0x00 15. " SD ,Subregion 7 disable" "-,D"
|
|
bitfld.long 0x00 14. " ,Subregion 6 disable" "-,D"
|
|
bitfld.long 0x00 13. " ,Subregion 5 disable" "-,D"
|
|
bitfld.long 0x00 12. " ,Subregion 4 disable" "-,D"
|
|
bitfld.long 0x00 11. " ,Subregion 3 disable" "-,D"
|
|
bitfld.long 0x00 10. " ,Subregion 2 disable" "-,D"
|
|
bitfld.long 0x00 9. " ,Subregion 1 disable" "-,D"
|
|
bitfld.long 0x00 8. " ,Subregion 0 disable" "-,D"
|
|
bitfld.long 0x00 1.--5. " RS ,Region size" "Unpredictable,Unpredictable,Unpredictable,Unpredictable,32 bytes,64 bytes,128 bytes,256 bytes,512 bytes,1KB,2KB,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB"
|
|
bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled"
|
|
group c15:0x0416++0x00
|
|
saveout c15:0x26 %l 0x4
|
|
line.long 0x00 "RACR4,Region Access Control Register 4"
|
|
bitfld.long 0x00 12. " XN ,Execute never" "-,NoExec"
|
|
bitfld.long 0x00 2. " S ,Share" "No,Yes"
|
|
bitfld.long 0x00 8.--10. " AP ,Access permission" "None,Privileged,User read-only,Full,Reserved,Privileged read,Read-only,Reserved"
|
|
bitfld.long 0x00 0.--1. 3.--5. " type ,Region type" "Strongly-ordered,Shareable Device,Outer and Inner write-through/no write-allocate,Outer and Inner write-back/no write-allocate,Outer and Inner Non-cacheable,00101,00110,Outer and Inner write-back/write-allocate,Non-shareable Device,01001,01010,01011,01100,01101,01110,01111,O:Non-cacheable I:Non-cacheable,O:Non-cacheable I:Write-back/write-allocate,O:Non-cacheable I:Write-through/no write-allocate,O:Non-cacheable I:Write-back/no write-allocate,O:Write-back/write-allocate I:Non-cacheable,O:Write-back/write-allocate I:Write-back/write-allocate,O:Write-back/write-allocate I:Write-through/no write-allocate,O:Write-back/write-allocate I:Write-back/no write-allocate,O:Write-through/no write-allocate I:Non-cacheable,O:Write-through/no write-allocate I:Write-back/write-allocate,O:Write-through/no write-allocate I:Write-through/no write-allocate,O:Write-through/no write-allocate I:Write-back/no write-allocate,O:Write-back/no write-allocate I:Non-cacheable,O:Write-back/no write-allocate I:Write-back/write-allocate,O:Write-back/no write-allocate I:Write-through/no write-allocate,O:Write-back/no write-allocate I:Write-back/no write-allocate"
|
|
textline " "
|
|
group c15:0x0016++0x00
|
|
saveout c15:0x26 %l 0x5
|
|
line.long 0x00 "RBAR5,Region Base Address Register 5"
|
|
hexmask.long 0x00 5.--31. 0x20 " BA ,Base address"
|
|
group c15:0x0216++0x00
|
|
saveout c15:0x26 %l 0x5
|
|
line.long 0x00 "RSER5,Region Size and Enable Register 5"
|
|
bitfld.long 0x00 15. " SD ,Subregion 7 disable" "-,D"
|
|
bitfld.long 0x00 14. " ,Subregion 6 disable" "-,D"
|
|
bitfld.long 0x00 13. " ,Subregion 5 disable" "-,D"
|
|
bitfld.long 0x00 12. " ,Subregion 4 disable" "-,D"
|
|
bitfld.long 0x00 11. " ,Subregion 3 disable" "-,D"
|
|
bitfld.long 0x00 10. " ,Subregion 2 disable" "-,D"
|
|
bitfld.long 0x00 9. " ,Subregion 1 disable" "-,D"
|
|
bitfld.long 0x00 8. " ,Subregion 0 disable" "-,D"
|
|
bitfld.long 0x00 1.--5. " RS ,Region size" "Unpredictable,Unpredictable,Unpredictable,Unpredictable,32 bytes,64 bytes,128 bytes,256 bytes,512 bytes,1KB,2KB,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB"
|
|
bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled"
|
|
group c15:0x0416++0x00
|
|
saveout c15:0x26 %l 0x5
|
|
line.long 0x00 "RACR5,Region Access Control Register 5"
|
|
bitfld.long 0x00 12. " XN ,Execute never" "-,NoExec"
|
|
bitfld.long 0x00 2. " S ,Share" "No,Yes"
|
|
bitfld.long 0x00 8.--10. " AP ,Access permission" "None,Privileged,User read-only,Full,Reserved,Privileged read,Read-only,Reserved"
|
|
bitfld.long 0x00 0.--1. 3.--5. " type ,Region type" "Strongly-ordered,Shareable Device,Outer and Inner write-through/no write-allocate,Outer and Inner write-back/no write-allocate,Outer and Inner Non-cacheable,00101,00110,Outer and Inner write-back/write-allocate,Non-shareable Device,01001,01010,01011,01100,01101,01110,01111,O:Non-cacheable I:Non-cacheable,O:Non-cacheable I:Write-back/write-allocate,O:Non-cacheable I:Write-through/no write-allocate,O:Non-cacheable I:Write-back/no write-allocate,O:Write-back/write-allocate I:Non-cacheable,O:Write-back/write-allocate I:Write-back/write-allocate,O:Write-back/write-allocate I:Write-through/no write-allocate,O:Write-back/write-allocate I:Write-back/no write-allocate,O:Write-through/no write-allocate I:Non-cacheable,O:Write-through/no write-allocate I:Write-back/write-allocate,O:Write-through/no write-allocate I:Write-through/no write-allocate,O:Write-through/no write-allocate I:Write-back/no write-allocate,O:Write-back/no write-allocate I:Non-cacheable,O:Write-back/no write-allocate I:Write-back/write-allocate,O:Write-back/no write-allocate I:Write-through/no write-allocate,O:Write-back/no write-allocate I:Write-back/no write-allocate"
|
|
textline " "
|
|
group c15:0x0016++0x00
|
|
saveout c15:0x26 %l 0x6
|
|
line.long 0x00 "RBAR6,Region Base Address Register 6"
|
|
hexmask.long 0x00 5.--31. 0x20 " BA ,Base address"
|
|
group c15:0x0216++0x00
|
|
saveout c15:0x26 %l 0x6
|
|
line.long 0x00 "RSER6,Region Size and Enable Register 6"
|
|
bitfld.long 0x00 15. " SD ,Subregion 7 disable" "-,D"
|
|
bitfld.long 0x00 14. " ,Subregion 6 disable" "-,D"
|
|
bitfld.long 0x00 13. " ,Subregion 5 disable" "-,D"
|
|
bitfld.long 0x00 12. " ,Subregion 4 disable" "-,D"
|
|
bitfld.long 0x00 11. " ,Subregion 3 disable" "-,D"
|
|
bitfld.long 0x00 10. " ,Subregion 2 disable" "-,D"
|
|
bitfld.long 0x00 9. " ,Subregion 1 disable" "-,D"
|
|
bitfld.long 0x00 8. " ,Subregion 0 disable" "-,D"
|
|
bitfld.long 0x00 1.--5. " RS ,Region size" "Unpredictable,Unpredictable,Unpredictable,Unpredictable,32 bytes,64 bytes,128 bytes,256 bytes,512 bytes,1KB,2KB,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB"
|
|
bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled"
|
|
group c15:0x0416++0x00
|
|
saveout c15:0x26 %l 0x6
|
|
line.long 0x00 "RACR6,Region Access Control Register 6"
|
|
bitfld.long 0x00 12. " XN ,Execute never" "-,NoExec"
|
|
bitfld.long 0x00 2. " S ,Share" "No,Yes"
|
|
bitfld.long 0x00 8.--10. " AP ,Access permission" "None,Privileged,User read-only,Full,Reserved,Privileged read,Read-only,Reserved"
|
|
bitfld.long 0x00 0.--1. 3.--5. " type ,Region type" "Strongly-ordered,Shareable Device,Outer and Inner write-through/no write-allocate,Outer and Inner write-back/no write-allocate,Outer and Inner Non-cacheable,00101,00110,Outer and Inner write-back/write-allocate,Non-shareable Device,01001,01010,01011,01100,01101,01110,01111,O:Non-cacheable I:Non-cacheable,O:Non-cacheable I:Write-back/write-allocate,O:Non-cacheable I:Write-through/no write-allocate,O:Non-cacheable I:Write-back/no write-allocate,O:Write-back/write-allocate I:Non-cacheable,O:Write-back/write-allocate I:Write-back/write-allocate,O:Write-back/write-allocate I:Write-through/no write-allocate,O:Write-back/write-allocate I:Write-back/no write-allocate,O:Write-through/no write-allocate I:Non-cacheable,O:Write-through/no write-allocate I:Write-back/write-allocate,O:Write-through/no write-allocate I:Write-through/no write-allocate,O:Write-through/no write-allocate I:Write-back/no write-allocate,O:Write-back/no write-allocate I:Non-cacheable,O:Write-back/no write-allocate I:Write-back/write-allocate,O:Write-back/no write-allocate I:Write-through/no write-allocate,O:Write-back/no write-allocate I:Write-back/no write-allocate"
|
|
textline " "
|
|
group c15:0x0016++0x00
|
|
saveout c15:0x26 %l 0x7
|
|
line.long 0x00 "RBAR7,Region Base Address Register 7"
|
|
hexmask.long 0x00 5.--31. 0x20 " BA ,Base address"
|
|
group c15:0x0216++0x00
|
|
saveout c15:0x26 %l 0x7
|
|
line.long 0x00 "RSER7,Region Size and Enable Register 7"
|
|
bitfld.long 0x00 15. " SD ,Subregion 7 disable" "-,D"
|
|
bitfld.long 0x00 14. " ,Subregion 6 disable" "-,D"
|
|
bitfld.long 0x00 13. " ,Subregion 5 disable" "-,D"
|
|
bitfld.long 0x00 12. " ,Subregion 4 disable" "-,D"
|
|
bitfld.long 0x00 11. " ,Subregion 3 disable" "-,D"
|
|
bitfld.long 0x00 10. " ,Subregion 2 disable" "-,D"
|
|
bitfld.long 0x00 9. " ,Subregion 1 disable" "-,D"
|
|
bitfld.long 0x00 8. " ,Subregion 0 disable" "-,D"
|
|
bitfld.long 0x00 1.--5. " RS ,Region size" "Unpredictable,Unpredictable,Unpredictable,Unpredictable,32 bytes,64 bytes,128 bytes,256 bytes,512 bytes,1KB,2KB,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB"
|
|
bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled"
|
|
group c15:0x0416++0x00
|
|
saveout c15:0x26 %l 0x7
|
|
line.long 0x00 "RACR7,Region Access Control Register 7"
|
|
bitfld.long 0x00 12. " XN ,Execute never" "-,NoExec"
|
|
bitfld.long 0x00 2. " S ,Share" "No,Yes"
|
|
bitfld.long 0x00 8.--10. " AP ,Access permission" "None,Privileged,User read-only,Full,Reserved,Privileged read,Read-only,Reserved"
|
|
bitfld.long 0x00 0.--1. 3.--5. " type ,Region type" "Strongly-ordered,Shareable Device,Outer and Inner write-through/no write-allocate,Outer and Inner write-back/no write-allocate,Outer and Inner Non-cacheable,00101,00110,Outer and Inner write-back/write-allocate,Non-shareable Device,01001,01010,01011,01100,01101,01110,01111,O:Non-cacheable I:Non-cacheable,O:Non-cacheable I:Write-back/write-allocate,O:Non-cacheable I:Write-through/no write-allocate,O:Non-cacheable I:Write-back/no write-allocate,O:Write-back/write-allocate I:Non-cacheable,O:Write-back/write-allocate I:Write-back/write-allocate,O:Write-back/write-allocate I:Write-through/no write-allocate,O:Write-back/write-allocate I:Write-back/no write-allocate,O:Write-through/no write-allocate I:Non-cacheable,O:Write-through/no write-allocate I:Write-back/write-allocate,O:Write-through/no write-allocate I:Write-through/no write-allocate,O:Write-through/no write-allocate I:Write-back/no write-allocate,O:Write-back/no write-allocate I:Non-cacheable,O:Write-back/no write-allocate I:Write-back/write-allocate,O:Write-back/no write-allocate I:Write-through/no write-allocate,O:Write-back/no write-allocate I:Write-back/no write-allocate"
|
|
textline " "
|
|
group c15:0x0016++0x00
|
|
saveout c15:0x26 %l 0x8
|
|
line.long 0x00 "RBAR8,Region Base Address Register 8"
|
|
hexmask.long 0x00 5.--31. 0x20 " BA ,Base address"
|
|
group c15:0x0216++0x00
|
|
saveout c15:0x26 %l 0x8
|
|
line.long 0x00 "RSER8,Region Size and Enable Register 8"
|
|
bitfld.long 0x00 15. " SD ,Subregion 7 disable" "-,D"
|
|
bitfld.long 0x00 14. " ,Subregion 6 disable" "-,D"
|
|
bitfld.long 0x00 13. " ,Subregion 5 disable" "-,D"
|
|
bitfld.long 0x00 12. " ,Subregion 4 disable" "-,D"
|
|
bitfld.long 0x00 11. " ,Subregion 3 disable" "-,D"
|
|
bitfld.long 0x00 10. " ,Subregion 2 disable" "-,D"
|
|
bitfld.long 0x00 9. " ,Subregion 1 disable" "-,D"
|
|
bitfld.long 0x00 8. " ,Subregion 0 disable" "-,D"
|
|
bitfld.long 0x00 1.--5. " RS ,Region size" "Unpredictable,Unpredictable,Unpredictable,Unpredictable,32 bytes,64 bytes,128 bytes,256 bytes,512 bytes,1KB,2KB,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB"
|
|
bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled"
|
|
group c15:0x0416++0x00
|
|
saveout c15:0x26 %l 0x8
|
|
line.long 0x00 "RACR8,Region Access Control Register 8"
|
|
bitfld.long 0x00 12. " XN ,Execute never" "-,NoExec"
|
|
bitfld.long 0x00 2. " S ,Share" "No,Yes"
|
|
bitfld.long 0x00 8.--10. " AP ,Access permission" "None,Privileged,User read-only,Full,Reserved,Privileged read,Read-only,Reserved"
|
|
bitfld.long 0x00 0.--1. 3.--5. " type ,Region type" "Strongly-ordered,Shareable Device,Outer and Inner write-through/no write-allocate,Outer and Inner write-back/no write-allocate,Outer and Inner Non-cacheable,00101,00110,Outer and Inner write-back/write-allocate,Non-shareable Device,01001,01010,01011,01100,01101,01110,01111,O:Non-cacheable I:Non-cacheable,O:Non-cacheable I:Write-back/write-allocate,O:Non-cacheable I:Write-through/no write-allocate,O:Non-cacheable I:Write-back/no write-allocate,O:Write-back/write-allocate I:Non-cacheable,O:Write-back/write-allocate I:Write-back/write-allocate,O:Write-back/write-allocate I:Write-through/no write-allocate,O:Write-back/write-allocate I:Write-back/no write-allocate,O:Write-through/no write-allocate I:Non-cacheable,O:Write-through/no write-allocate I:Write-back/write-allocate,O:Write-through/no write-allocate I:Write-through/no write-allocate,O:Write-through/no write-allocate I:Write-back/no write-allocate,O:Write-back/no write-allocate I:Non-cacheable,O:Write-back/no write-allocate I:Write-back/write-allocate,O:Write-back/no write-allocate I:Write-through/no write-allocate,O:Write-back/no write-allocate I:Write-back/no write-allocate"
|
|
textline " "
|
|
group c15:0x0016++0x00
|
|
saveout c15:0x26 %l 0x9
|
|
line.long 0x00 "RBAR9,Region Base Address Register 9"
|
|
hexmask.long 0x00 5.--31. 0x20 " BA ,Base address"
|
|
group c15:0x0216++0x00
|
|
saveout c15:0x26 %l 0x9
|
|
line.long 0x00 "RSER9,Region Size and Enable Register 9"
|
|
bitfld.long 0x00 15. " SD ,Subregion 7 disable" "-,D"
|
|
bitfld.long 0x00 14. " ,Subregion 6 disable" "-,D"
|
|
bitfld.long 0x00 13. " ,Subregion 5 disable" "-,D"
|
|
bitfld.long 0x00 12. " ,Subregion 4 disable" "-,D"
|
|
bitfld.long 0x00 11. " ,Subregion 3 disable" "-,D"
|
|
bitfld.long 0x00 10. " ,Subregion 2 disable" "-,D"
|
|
bitfld.long 0x00 9. " ,Subregion 1 disable" "-,D"
|
|
bitfld.long 0x00 8. " ,Subregion 0 disable" "-,D"
|
|
bitfld.long 0x00 1.--5. " RS ,Region size" "Unpredictable,Unpredictable,Unpredictable,Unpredictable,32 bytes,64 bytes,128 bytes,256 bytes,512 bytes,1KB,2KB,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB"
|
|
bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled"
|
|
group c15:0x0416++0x00
|
|
saveout c15:0x26 %l 0x9
|
|
line.long 0x00 "RACR9,Region Access Control Register 9"
|
|
bitfld.long 0x00 12. " XN ,Execute never" "-,NoExec"
|
|
bitfld.long 0x00 2. " S ,Share" "No,Yes"
|
|
bitfld.long 0x00 8.--10. " AP ,Access permission" "None,Privileged,User read-only,Full,Reserved,Privileged read,Read-only,Reserved"
|
|
bitfld.long 0x00 0.--1. 3.--5. " type ,Region type" "Strongly-ordered,Shareable Device,Outer and Inner write-through/no write-allocate,Outer and Inner write-back/no write-allocate,Outer and Inner Non-cacheable,00101,00110,Outer and Inner write-back/write-allocate,Non-shareable Device,01001,01010,01011,01100,01101,01110,01111,O:Non-cacheable I:Non-cacheable,O:Non-cacheable I:Write-back/write-allocate,O:Non-cacheable I:Write-through/no write-allocate,O:Non-cacheable I:Write-back/no write-allocate,O:Write-back/write-allocate I:Non-cacheable,O:Write-back/write-allocate I:Write-back/write-allocate,O:Write-back/write-allocate I:Write-through/no write-allocate,O:Write-back/write-allocate I:Write-back/no write-allocate,O:Write-through/no write-allocate I:Non-cacheable,O:Write-through/no write-allocate I:Write-back/write-allocate,O:Write-through/no write-allocate I:Write-through/no write-allocate,O:Write-through/no write-allocate I:Write-back/no write-allocate,O:Write-back/no write-allocate I:Non-cacheable,O:Write-back/no write-allocate I:Write-back/write-allocate,O:Write-back/no write-allocate I:Write-through/no write-allocate,O:Write-back/no write-allocate I:Write-back/no write-allocate"
|
|
textline " "
|
|
group c15:0x0016++0x00
|
|
saveout c15:0x26 %l 0xA
|
|
line.long 0x00 "RBAR10,Region Base Address Register 10"
|
|
hexmask.long 0x00 5.--31. 0x20 " BA ,Base address"
|
|
group c15:0x0216++0x00
|
|
saveout c15:0x26 %l 0xA
|
|
line.long 0x00 "RSER10,Region Size and Enable Register 10"
|
|
bitfld.long 0x00 15. " SD ,Subregion 7 disable" "-,D"
|
|
bitfld.long 0x00 14. " ,Subregion 6 disable" "-,D"
|
|
bitfld.long 0x00 13. " ,Subregion 5 disable" "-,D"
|
|
bitfld.long 0x00 12. " ,Subregion 4 disable" "-,D"
|
|
bitfld.long 0x00 11. " ,Subregion 3 disable" "-,D"
|
|
bitfld.long 0x00 10. " ,Subregion 2 disable" "-,D"
|
|
bitfld.long 0x00 9. " ,Subregion 1 disable" "-,D"
|
|
bitfld.long 0x00 8. " ,Subregion 0 disable" "-,D"
|
|
bitfld.long 0x00 1.--5. " RS ,Region size" "Unpredictable,Unpredictable,Unpredictable,Unpredictable,32 bytes,64 bytes,128 bytes,256 bytes,512 bytes,1KB,2KB,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB"
|
|
bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled"
|
|
group c15:0x0416++0x00
|
|
saveout c15:0x26 %l 0xA
|
|
line.long 0x00 "RACR10,Region Access Control Register 10"
|
|
bitfld.long 0x00 12. " XN ,Execute never" "-,NoExec"
|
|
bitfld.long 0x00 2. " S ,Share" "No,Yes"
|
|
bitfld.long 0x00 8.--10. " AP ,Access permission" "None,Privileged,User read-only,Full,Reserved,Privileged read,Read-only,Reserved"
|
|
bitfld.long 0x00 0.--1. 3.--5. " type ,Region type" "Strongly-ordered,Shareable Device,Outer and Inner write-through/no write-allocate,Outer and Inner write-back/no write-allocate,Outer and Inner Non-cacheable,00101,00110,Outer and Inner write-back/write-allocate,Non-shareable Device,01001,01010,01011,01100,01101,01110,01111,O:Non-cacheable I:Non-cacheable,O:Non-cacheable I:Write-back/write-allocate,O:Non-cacheable I:Write-through/no write-allocate,O:Non-cacheable I:Write-back/no write-allocate,O:Write-back/write-allocate I:Non-cacheable,O:Write-back/write-allocate I:Write-back/write-allocate,O:Write-back/write-allocate I:Write-through/no write-allocate,O:Write-back/write-allocate I:Write-back/no write-allocate,O:Write-through/no write-allocate I:Non-cacheable,O:Write-through/no write-allocate I:Write-back/write-allocate,O:Write-through/no write-allocate I:Write-through/no write-allocate,O:Write-through/no write-allocate I:Write-back/no write-allocate,O:Write-back/no write-allocate I:Non-cacheable,O:Write-back/no write-allocate I:Write-back/write-allocate,O:Write-back/no write-allocate I:Write-through/no write-allocate,O:Write-back/no write-allocate I:Write-back/no write-allocate"
|
|
textline " "
|
|
group c15:0x0016++0x00
|
|
saveout c15:0x26 %l 0xB
|
|
line.long 0x00 "RBAR11,Region Base Address Register 11"
|
|
hexmask.long 0x00 5.--31. 0x20 " BA ,Base address"
|
|
group c15:0x0216++0x00
|
|
saveout c15:0x26 %l 0xB
|
|
line.long 0x00 "RSER11,Region Size and Enable Register 11"
|
|
bitfld.long 0x00 15. " SD ,Subregion 7 disable" "-,D"
|
|
bitfld.long 0x00 14. " ,Subregion 6 disable" "-,D"
|
|
bitfld.long 0x00 13. " ,Subregion 5 disable" "-,D"
|
|
bitfld.long 0x00 12. " ,Subregion 4 disable" "-,D"
|
|
bitfld.long 0x00 11. " ,Subregion 3 disable" "-,D"
|
|
bitfld.long 0x00 10. " ,Subregion 2 disable" "-,D"
|
|
bitfld.long 0x00 9. " ,Subregion 1 disable" "-,D"
|
|
bitfld.long 0x00 8. " ,Subregion 0 disable" "-,D"
|
|
bitfld.long 0x00 1.--5. " RS ,Region size" "Unpredictable,Unpredictable,Unpredictable,Unpredictable,32 bytes,64 bytes,128 bytes,256 bytes,512 bytes,1KB,2KB,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB"
|
|
bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled"
|
|
group c15:0x0416++0x00
|
|
saveout c15:0x26 %l 0xB
|
|
line.long 0x00 "RACR11,Region Access Control Register 11"
|
|
bitfld.long 0x00 12. " XN ,Execute never" "-,NoExec"
|
|
bitfld.long 0x00 2. " S ,Share" "No,Yes"
|
|
bitfld.long 0x00 8.--10. " AP ,Access permission" "None,Privileged,User read-only,Full,Reserved,Privileged read,Read-only,Reserved"
|
|
bitfld.long 0x00 0.--1. 3.--5. " type ,Region type" "Strongly-ordered,Shareable Device,Outer and Inner write-through/no write-allocate,Outer and Inner write-back/no write-allocate,Outer and Inner Non-cacheable,00101,00110,Outer and Inner write-back/write-allocate,Non-shareable Device,01001,01010,01011,01100,01101,01110,01111,O:Non-cacheable I:Non-cacheable,O:Non-cacheable I:Write-back/write-allocate,O:Non-cacheable I:Write-through/no write-allocate,O:Non-cacheable I:Write-back/no write-allocate,O:Write-back/write-allocate I:Non-cacheable,O:Write-back/write-allocate I:Write-back/write-allocate,O:Write-back/write-allocate I:Write-through/no write-allocate,O:Write-back/write-allocate I:Write-back/no write-allocate,O:Write-through/no write-allocate I:Non-cacheable,O:Write-through/no write-allocate I:Write-back/write-allocate,O:Write-through/no write-allocate I:Write-through/no write-allocate,O:Write-through/no write-allocate I:Write-back/no write-allocate,O:Write-back/no write-allocate I:Non-cacheable,O:Write-back/no write-allocate I:Write-back/write-allocate,O:Write-back/no write-allocate I:Write-through/no write-allocate,O:Write-back/no write-allocate I:Write-back/no write-allocate"
|
|
textline " "
|
|
tree.end
|
|
tree.end
|
|
width 0x9
|
|
tree "TCM Control and Configuration"
|
|
rgroup.long c15:0x200++0x00
|
|
line.long 0x00 "TCMTR,TCM Type Register"
|
|
bitfld.long 0x00 16.--18. " BTCM ,Number of BTCMs implemented" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--2. " ATCM ,Number of ATCMs implemented" "0,1,2,3,4,5,6,7"
|
|
group.long c15:0x019++0x00
|
|
line.long 0x00 "BTCMRR,BTCM Region Register"
|
|
hexmask.long 0x00 12.--31. 0x1000 " BA ,Base address (physical address)"
|
|
bitfld.long 0x00 2.--6. " SIZE ,Size of instruction TCM on reads" "None,Reserved,Reserved,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,?..."
|
|
bitfld.long 0x00 0. " EN ,Enable instruction TCM" "Disabled,Enabled"
|
|
group.long c15:0x119++0x00
|
|
line.long 0x00 "ATCMRR,ATCM Region Register"
|
|
hexmask.long 0x00 12.--31. 0x1000 " BA ,Base address (physical address)"
|
|
bitfld.long 0x00 2.--6. " SIZE ,Size of instruction TCM on reads" "None,Reserved,Reserved,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,?..."
|
|
bitfld.long 0x00 0. " EN ,Enable instruction TCM" "Disabled,Enabled"
|
|
rgroup.long c15:0x29++0x00
|
|
line.long 0x00 "TCMSEL,TCM Selection Register"
|
|
tree.end
|
|
width 0xC
|
|
tree "Cache Control and Configuration"
|
|
rgroup.long c15:0x1100--0x1100
|
|
line.long 0x0 "CLIDR,Cache Level ID Register"
|
|
bitfld.long 0x00 27.--29. " LoU ,Level of Unification" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 24.--26. " LoC ,Level of Coherency" "Level 1,Level 2,Level 3,Level 4,Level 5,Level 6,Level 7,Level 8"
|
|
textline " "
|
|
bitfld.long 0x00 21.--23. " CL8 ,Cache Level (CL) 8" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 18.--20. " CL7 ,Cache Level (CL) 7" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 15.--17. " CL6 ,Cache Level (CL) 6" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 12.--14. " CL5 ,Cache Level (CL) 5" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 9.--11. " CL4 ,Cache Level (CL) 4" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 6.--8. " CL3 ,Cache Level (CL) 3" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 3.--5. " CL2 ,Cache Level (CL) 2" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--2. " CL1 ,Cache Level (CL) 1" "0,1,2,3,4,5,6,7"
|
|
rgroup.long c15:0x1000++0x00
|
|
line.long 0x00 "CCSIDR,Cache Size ID Register"
|
|
bitfld.long 0x00 31. " WT ,Write-Through" "Not supported,Supported"
|
|
bitfld.long 0x00 30. " WB ,Write-Back" "Not supported,Supported"
|
|
textline " "
|
|
bitfld.long 0x00 29. " RA ,Read-Allocate" "Not supported,Supported"
|
|
bitfld.long 0x00 28. " WA ,Write-Allocate" "Not supported,Supported"
|
|
textline " "
|
|
hexmask.long.word 0x00 13.--27. 1. " NUMSETS ,Number of sets"
|
|
hexmask.long.word 0x00 3.--12. 1. " ASSOCIATIVITY ,Associativity"
|
|
textline " "
|
|
bitfld.long 0x00 0.--2. " LINESIZE ,Number of words in each cache line" "0,1,2,3,4,5,6,7"
|
|
group.long c15:0x2000--0x2000
|
|
line.long 0x0 "CSSELR,Cache Size Selection Register"
|
|
bitfld.long 0x00 1.--3. " Level ,Cache level to select" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0. " InD ,Instruction or data or unified cache to use" "Data/unified,Instruction"
|
|
group.long c15:0x03f++0x00
|
|
line.long 0x00 "CFLR,Correctable Fault Location Register"
|
|
bitfld.long 0x00 26.--29. " WAY ,Way of the error" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 24.--25. " SIDE ,Source of the error" "0,1,2,3"
|
|
textline " "
|
|
hexmask.long.word 0x00 5.--13. 1. " INDEX ,index of the location where the error occurred"
|
|
bitfld.long 0x00 0.--1. " TYPE ,Type of access that caused the error" "Instruction cache,Data cache,Reserved,ACP"
|
|
rgroup.long c15:0x0ef++0x0
|
|
line.long 0x00 "CSOR,Cache Size Override Register"
|
|
bitfld.long 0x00 4.--6. " Dcache ,Validation data cache size" "Not presented,Reserved,Reserved,4k,8k,16k,32k,64k"
|
|
bitfld.long 0x00 0.--2. " Icache ,Validation instruction cache size" "Not presented,Reserved,Reserved,4k,8k,16k,32k,64k"
|
|
tree.end
|
|
width 8.
|
|
tree "System Performance Monitor"
|
|
group c15:0xC9--0xC9
|
|
line.long 0x0 "PMNC,Performance Monitor Control Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " IMP ,Implementer code"
|
|
hexmask.long.byte 0x00 16.--23. 1. " IDCODE ,Identification code"
|
|
bitfld.long 0x00 11.--15. " N ,Number of counters implemented" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 5. " DP ,Disable CCNT when prohibited" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " X ,Export Enabled" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " D ,Clock Divider" "Every cycle,64th cycle"
|
|
bitfld.long 0x00 2. " C ,Clock Counter Reset" "No action,Reset"
|
|
bitfld.long 0x00 1. " P ,Performance Counter Reset" "No action,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 0. " E ,Counters Enable" "Disabled,Enabled"
|
|
group c15:0x1C9--0x1C9
|
|
line.long 0x0 "CNTENS,Count Enable Set Register"
|
|
eventfld.long 0x00 31. " C ,CCNT Enabled / Enable / Disable CCNT" "Disabled,Enabled"
|
|
eventfld.long 0x00 3. " P3 ,PMN3 Enabled / Enable / Disable counter" "Disabled,Enabled"
|
|
eventfld.long 0x00 2. " P2 ,PMN2 Enabled / Enable / Disable counter" "Disabled,Enabled"
|
|
eventfld.long 0x00 1. " P1 ,PMN1 Enabled / Enable / Disable counter" "Disabled,Enabled"
|
|
eventfld.long 0x00 0. " P0 ,PMN0 Enabled / Enable / Disable counter" "Disabled,Enabled"
|
|
group c15:0x2C9--0x2C9
|
|
line.long 0x0 "CNTENC,Count Enable Clear Register"
|
|
eventfld.long 0x00 31. " C ,CCNT Enabled / Enable / Disable CCNT" "Disabled,Enabled"
|
|
eventfld.long 0x00 3. " P3 ,PMN3 Enabled / Enable / Disable counter" "Disabled,Enabled"
|
|
eventfld.long 0x00 2. " P2 ,PMN2 Enabled / Enable / Disable counter" "Disabled,Enabled"
|
|
eventfld.long 0x00 1. " P1 ,PMN1 Enabled / Enable / Disable counter" "Disabled,Enabled"
|
|
eventfld.long 0x00 0. " P0 ,PMN0 Enabled / Enable / Disable counter" "Disabled,Enabled"
|
|
group c15:0x3C9--0x3C9
|
|
line.long 0x0 "FLAG,Overflow Flag Status Register"
|
|
eventfld.long 0x00 31. " C ,CCNT overflowed" "No overflow,Overflow"
|
|
eventfld.long 0x00 3. " P3 ,PMN3 overflowed" "No overflow,Overflow"
|
|
eventfld.long 0x00 2. " P2 ,PMN2 overflowed" "No overflow,Overflow"
|
|
eventfld.long 0x00 1. " P1 ,PMN1 overflowed" "No overflow,Overflow"
|
|
eventfld.long 0x00 0. " P0 ,PMN0 overflowed" "No overflow,Overflow"
|
|
group c15:0x4C9--0x4C9
|
|
line.long 0x0 "SWINCR,Software Increment Register"
|
|
eventfld.long 0x00 3. " P3 ,Increment PMN3" "No action,Increment"
|
|
eventfld.long 0x00 2. " P2 ,Increment PMN2" "No action,Increment"
|
|
eventfld.long 0x00 1. " P1 ,Increment PMN1" "No action,Increment"
|
|
eventfld.long 0x00 0. " P0 ,Increment PMN0" "No action,Increment"
|
|
group c15:0x5C9--0x5C9
|
|
line.long 0x0 "PMNXSEL,Performance Counter Selection Register"
|
|
bitfld.long 0x00 0.--4. " SEL ,Selection value" "CNT0,CNT1,CNT2,CNT3,?..."
|
|
group c15:0xD9--0xD9
|
|
line.long 0x0 "CCNT,Cycle Count Register"
|
|
group c15:0x01d9++0x00
|
|
line.long 0x00 "ESR,Event Selection Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SEL ,Event Selection"
|
|
group c15:0x02d9++0x00
|
|
line.long 0x00 "PMCR,Performance Monitor Count Register"
|
|
group c15:0x01d9++0x00
|
|
saveout c15:0x5C9 %l 0x0
|
|
line.long 0x00 "ESR0,Event Selection Register 0"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SEL ,Event Selection"
|
|
group c15:0x02d9++0x00
|
|
saveout c15:0x5C9 %l 0x0
|
|
line.long 0x00 "PMCR0,Performance Monitor Count Register 0"
|
|
hexmask.long 0x00 0.--31. 1. " PMC ,Performance Monitor Count"
|
|
group c15:0x01d9++0x00
|
|
saveout c15:0x5C9 %l 0x1
|
|
line.long 0x00 "ESR1,Event Selection Register 1"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SEL ,Event Selection"
|
|
group c15:0x02d9++0x00
|
|
saveout c15:0x5C9 %l 0x1
|
|
line.long 0x00 "PMCR1,Performance Monitor Count Register 1"
|
|
hexmask.long 0x00 0.--31. 1. " PMC ,Performance Monitor Count"
|
|
group c15:0x01d9++0x00
|
|
saveout c15:0x5C9 %l 0x2
|
|
line.long 0x00 "ESR2,Event Selection Register 2"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SEL ,Event Selection"
|
|
group c15:0x02d9++0x00
|
|
saveout c15:0x5C9 %l 0x2
|
|
line.long 0x00 "PMCR2,Performance Monitor Count Register 2"
|
|
hexmask.long 0x00 0.--31. 1. " PMC ,Performance Monitor Count"
|
|
group c15:0xE9--0xE9
|
|
line.long 0x0 "USEREN,User Enable Register"
|
|
bitfld.long 0x00 0. " EN ,User Mode Enable" "Disabled,Enabled"
|
|
group c15:0x1E9--0x1E9
|
|
line.long 0x0 "INTENS,Interrupt Enable Set Register"
|
|
eventfld.long 0x00 31. " C ,Interrupt on CCNT Overflow Enabled / Enable / Disable Interrupt" "Disabled,Enabled"
|
|
eventfld.long 0x00 3. " P3 ,Interrupt on PMN3 Overflow Enabled / Enable / Disable Interrupt" "Disabled,Enabled"
|
|
eventfld.long 0x00 2. " P2 ,Interrupt on PMN2 Overflow Enabled / Enable / Disable Interrupt" "Disabled,Enabled"
|
|
eventfld.long 0x00 1. " P1 ,Interrupt on PMN1 Overflow Enabled / Enable / Disable Interrupt" "Disabled,Enabled"
|
|
eventfld.long 0x00 0. " P0 ,Interrupt on PMN0 Overflow Enabled / Enable / Disable Interrupt" "Disabled,Enabled"
|
|
group c15:0x2E9--0x2E9
|
|
line.long 0x0 "INTENC,Interrupt Enable Clear Register"
|
|
eventfld.long 0x00 31. " C ,Interrupt on CCNT Overflow Enabled / Enable / Disable Interrupt" "Disabled,Enabled"
|
|
eventfld.long 0x00 3. " P3 ,Interrupt on PMN3 Overflow Enabled / Enable / Disable Interrupt" "Disabled,Enabled"
|
|
eventfld.long 0x00 2. " P2 ,Interrupt on PMN2 Overflow Enabled / Enable / Disable Interrupt" "Disabled,Enabled"
|
|
eventfld.long 0x00 1. " P1 ,Interrupt on PMN1 Overflow Enabled / Enable / Disable Interrupt" "Disabled,Enabled"
|
|
eventfld.long 0x00 0. " P0 ,Interrupt on PMN0 Overflow Enabled / Enable / Disable Interrupt" "Disabled,Enabled"
|
|
tree.end
|
|
width 8.
|
|
tree "Debug Registers"
|
|
width 11.
|
|
tree "Processor Identifier Registers"
|
|
rgroup c14:0x340--0x340
|
|
line.long 0x00 "MIDR,Main ID Register"
|
|
hexmask.long.byte 0x0 24.--31. 0x1 " IMPL ,Implementer code"
|
|
hexmask.long.byte 0x0 20.--23. 0x1 " SPECREV ,Variant number"
|
|
textline " "
|
|
hexmask.long.byte 0x0 16.--19. 0x1 " ARCH , Architecture"
|
|
hexmask.long.word 0x0 4.--15. 0x1 " PARTNUM ,Part Number"
|
|
textline " "
|
|
hexmask.long.byte 0x0 0.--3. 0x1 " REV ,Layout Revision"
|
|
rgroup c14:0x341--0x341
|
|
line.long 0x00 "CACHETYPE,Cache Type Register"
|
|
bitfld.long 0x00 16.--19. " DMINLINE ,Words of Smallest Line Length in L1 or L2 Data Cache Number" "Reserved,Reserved,Reserved,Reserved,16x32-bit words,?..."
|
|
bitfld.long 0x00 14.--15. " L1_IPOLICY ,VIPT Instruction Cache Support" "Reserved,Reserved,Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " IMINLINE ,Words of Smallest Line Length in L1 or L2 Instruction Cache Number" "Reserved,Reserved,Reserved,Reserved,16x32-bit words,?..."
|
|
rgroup c14:0x343--0x343
|
|
line.long 0x00 "TLBTYPE,TLB Type Register"
|
|
hexmask.long.byte 0x0 16.--23. 0x1 " ILSIZE ,Specifies the number of instruction TLB lockable entries"
|
|
hexmask.long.byte 0x0 8.--15. 0x1 " DLSIZE ,Specifies the number of unified or data TLB lockable entries"
|
|
textline " "
|
|
bitfld.long 0x0 0. " U ,Unified or separate instruction TLBs" "Unified,Separate"
|
|
rgroup c14:0x348--0x348
|
|
line.long 0x00 "ID_PFR0,Processor Feature Register 0"
|
|
bitfld.long 0x00 12.--15. " STATE3 ,Thumb-2 Execution Environment (Thumb-2EE) Support" "Reserved,Supported,?..."
|
|
bitfld.long 0x00 8.--11. " STATE2 ,Java Extension Interface Support" "Not supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " STATE1 ,Thumb Encoding Supported by the Processor Type" "Reserved,Reserved,Reserved,Supported,?..."
|
|
bitfld.long 0x00 0.--3. " STATE0 ,ARM Instruction Set Support" "Reserved,Supported,?..."
|
|
rgroup c14:0x349--0x349
|
|
line.long 0x00 "ID_PFR1,Processor Feature Register 1"
|
|
bitfld.long 0x00 8.--11. " MPM ,Microcontroller Programmer's Model Support" "Supported,?..."
|
|
bitfld.long 0x00 4.--7. " SE ,Security Extensions Architecture v1 Support" "Reserved,Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " PM ,Standard ARMv4 Programmer's Model Support" "Reserved,Supported,?..."
|
|
rgroup c14:0x34a--0x34a
|
|
line.long 0x00 "ID_DFR0,Debug Feature Register 0"
|
|
bitfld.long 0x00 20.--23. " MDM_MM ,Microcontroller Debug Model Support" "Not supported,?..."
|
|
bitfld.long 0x00 16.--19. " TDM_MM ,Trace Debug Model (Memory-Mapped) Support" "Reserved,Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 12.--15. " TDM_CB ,Coprocessor-Based Trace Debug Model Support" "Not supported,?..."
|
|
bitfld.long 0x00 8.--11. " CDM_MM ,Memory-Mapped Debug Model Support" "Reserved,Reserved,Reserved,Reserved,Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " SDM_CB ,Secure Debug Model (Coprocessor) Support" "Not supported,?..."
|
|
bitfld.long 0x00 0.--3. " CDM_CB ,Coprocessor Debug Model Support" "Not supported,?..."
|
|
rgroup c14:0x34b--0x34b
|
|
line.long 0x00 "ID_AFR0,Auxiliary Feature Register 0"
|
|
hexmask.long 0x00 0.--31. 1. " AF ,Auxiliary Feature"
|
|
rgroup c14:0x34c--0x34c
|
|
line.long 0x00 "ID_MMFR0,Processor Feature Register 0"
|
|
bitfld.long 0x00 28.--31. " IT ,Instruction Type Support" "Reserved,Reserved,Reserved,Supported,?..."
|
|
bitfld.long 0x00 24.--27. " FCSE ,Fast Context Switch Memory Mappings Support" "Reserved,Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 20.--23. " ACR ,Auxiliary Control Register Support" "Reserved,Supported,?..."
|
|
bitfld.long 0x00 16.--19. " TCM ,TCM and Associated DMA Support" "Not supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 12.--15. " CC_PLEA ,Cache Coherency With PLE Agent/Shared Memory Support" "Not supported,?..."
|
|
bitfld.long 0x00 8.--11. " CC_CPUA ,Cache Coherency Support With CPU Agent/Shared Memory Support" "Not supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " PMSA ,Physical Memory System Architecture (PMSA) Support" "Not supported,?..."
|
|
bitfld.long 0x00 0.--3. " VMSA ,Virtual Memory System Architecture (VMSA) Support" "Reserved,Reserved,Reserved,Supported,?..."
|
|
rgroup c14:0x34d--0x34d
|
|
line.long 0x00 "ID_MMFR1,Processor Feature Register 1"
|
|
bitfld.long 0x00 28.--31. " BTB ,Branch Target Buffer Support" "Reserved,Reserved,Not required,?..."
|
|
bitfld.long 0x00 24.--27. " L1TCO ,Test and Clean Operations on Data Cache/Harvard/Unified Architecture Support" "Not supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 20.--23. " L1UCMO ,L1 Cache/All Maintenance Operations/Unified Architecture Support" "Not supported,?..."
|
|
bitfld.long 0x00 16.--19. " L1HCMO ,L1 Cache/All Maintenance Operations/Harvard Architecture Support" "Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 12.--15. " L1UCLMOSW ,L1 Cache Line Maintenance Operations by Set and Way/Unified Architecture Support" "Not supported,?..."
|
|
bitfld.long 0x00 8.--11. " L1HCLMOSW ,L1 Cache Line Maintenance Operations by Set and Way/Harvard Architecture Support" "Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " L1UCLMOMVA ,L1 Cache Line Maintenance Operations by MVA/Unified Architecture Support" "Not supported,?..."
|
|
bitfld.long 0x00 0.--3. " L1HCLMOMVA ,L1 Cache Line Maintenance Operations by MVA/Harvard Architecture" "Supported,?..."
|
|
rgroup c14:0x34e--0x34e
|
|
line.long 0x00 "ID_MMFR2,Processor Feature Register 2"
|
|
bitfld.long 0x00 28.--31. " HAF ,Hardware Access Flag Support" "Not supported,?..."
|
|
bitfld.long 0x00 24.--27. " WFI ,Wait for Interrupt Stalling Support" "Reserved,Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 20.--23. " MBF ,Memory Barrier Operations Support" "Reserved,Reserved,Supported,?..."
|
|
bitfld.long 0x00 16.--19. " UTLBMO ,TLB Maintenance Operations/Unified Architecture Support" "Not supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 12.--15. " HTLBMO ,TLB Maintenance Operations/Harvard Architecture Support" "Reserved,Reserved,Supported,?..."
|
|
bitfld.long 0x00 8.--11. " HL1CMRO ,Cache Maintenance Range Operations/Harvard Architecture Support" "Not supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " HL1BPCRO ,Background Prefetch Cache Range Operations/Harvard Architecture Support" "Not supported,?..."
|
|
bitfld.long 0x00 0.--3. " HL1FPCRO ,Foreground Prefetch Cache Range Operations/Harvard Architecture Support" "Not supported,?..."
|
|
rgroup c14:0x34f--0x34f
|
|
line.long 0x00 "ID_MMFR3,Processor Feature Register 3"
|
|
bitfld.long 0x00 4.--7. " HCMOSW ,Invalidate Cache by Set and Way/Clean by Set and Way/Invalidate and Clean by Set and Way Support" "Reserved,Supported,?..."
|
|
bitfld.long 0x00 0.--3. " HCMOMVA ,Invalidate Cache by MVA/Clean by MVA/Invalidate and Clean by MVA/Invalidate All Support" "Reserved,Supported,?..."
|
|
rgroup c14:0x350--0x350
|
|
line.long 0x00 "ID_ISAR0,ISA Feature Register 0"
|
|
bitfld.long 0x00 24.--27. " DIVI ,Divide Instructions Support" "Not supported,?..."
|
|
bitfld.long 0x00 20.--23. " DEBI ,Debug Instructions Support" "Reserved,Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. " CI ,Coprocessor Instructions Support" "Not supported,?..."
|
|
bitfld.long 0x00 12.--15. " CBI ,Combined Compare and Branch Instructions Support" "Reserved,Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 8.--11. " BI ,Bitfield Instructions Support" "Reserved,Supported,?..."
|
|
bitfld.long 0x00 4.--7. " BCI ,Bit Counting Instructions Support" "Reserved,Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " AI ,Atomic Load and Store Instructions Support" "Reserved,Supported,?..."
|
|
rgroup c14:0x351--0x351
|
|
line.long 0x00 "ID_ISAR1,ISA Feature Register 1"
|
|
bitfld.long 0x00 28.--31. " JI ,Jazelle Instructions Support" "Reserved,Supported,?..."
|
|
bitfld.long 0x00 24.--27. " INTI ,Instructions That Branch Between ARM and Thumb Code Support" "Reserved,Reserved,Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 20.--23. " IMMI ,Immediate Instructions Support" "Reserved,Supported,?..."
|
|
bitfld.long 0x00 16.--19. " ITEI ,If Then Instructions Support" "Reserved,Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 12.--15. " EXTI ,Sign or Zero Extend Instructions Support" "Reserved,Reserved,Supported,?..."
|
|
bitfld.long 0x00 8.--11. " E2I ,Exception 2 Instructions Support" "Reserved,Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " E1I ,Exception 1 Instructions Support" "Reserved,Supported,?..."
|
|
bitfld.long 0x00 0.--3. " ENDI ,Endianness Control Instructions Support" "Reserved,Supported,?..."
|
|
rgroup c14:0x352--0x352
|
|
line.long 0x00 "ID_ISAR2,ISA Feature Register 2"
|
|
bitfld.long 0x00 28.--31. " RI ,Reversal Instructions Support" "Reserved,Reserved,Supported,?..."
|
|
bitfld.long 0x00 24.--27. " PSRI ,PSR Instructions Support" "Reserved,Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 20.--23. " UMI ,Advanced Unsigned Multiply Instructions Support" "Reserved,Reserved,Supported,?..."
|
|
bitfld.long 0x00 16.--19. " SMI ,Advanced Signed Multiply Instructions Support" "Reserved,Reserved,Reserved,Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 12.--15. " MI ,Multiply Instructions Support" "Reserved,Reserved,Supported,?..."
|
|
bitfld.long 0x00 8.--11. " II ,Multi-Access Interruptible Instructions Support" "Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " MHI ,Memory Hint Instructions Support" "Reserved,Reserved,Reserved,Supported,?..."
|
|
bitfld.long 0x00 0.--3. " LSI ,Load and Store Instructions Support" "Reserved,Supported,?..."
|
|
rgroup c14:0x353--0x353
|
|
line.long 0x00 "ID_ISAR3,ISA Feature Register 3"
|
|
bitfld.long 0x00 28.--31. " T2E ,Thumb-2 Extensions Support" "Reserved,Supported,?..."
|
|
bitfld.long 0x00 24.--27. " NOPI ,True NOP Instructions Support" "Reserved,Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 20.--23. " TCI ,Thumb Copy Instructions Support" "Reserved,Supported,?..."
|
|
bitfld.long 0x00 16.--19. " TBI ,Table Branch Instructions Support" "Reserved,Reserved,Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 12.--15. " SPI ,Synchronization Primitive Instructions Support" "Reserved,Reserved,Supported,?..."
|
|
bitfld.long 0x00 8.--11. " SWII ,SWI Instructions Support" "Reserved,Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " SIMDI ,Single Instruction Multiple Data (SIMD) Instructions Support" "Reserved,Reserved,Reserved,Supported,?..."
|
|
bitfld.long 0x00 0.--3. " SI ,Saturate Instructions Support" "Reserved,Supported,?..."
|
|
rgroup c14:0x354--0x354
|
|
line.long 0x00 "ID_ISAR4,ISA Feature Register 4"
|
|
bitfld.long 0x00 20.--23. " EI ,Exclusive Instructions Support" "Reserved,Supported,?..."
|
|
bitfld.long 0x00 16.--19. " BI ,Barrier Instructions Support" "Reserved,Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 12.--15. " SMII ,SMI Instructions Support" "Reserved,Supported,?..."
|
|
bitfld.long 0x00 8.--11. " WBI ,Write-Back Instructions Support" "Reserved,Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " WSI ,With-Shift Instructions Support" "Reserved,Reserved,Reserved,Reserved,Supported,?..."
|
|
bitfld.long 0x00 0.--3. " UI ,Unprivileged Instructions Support" "Reserved,Reserved,Supported,?..."
|
|
rgroup c14:0x355--0x355
|
|
line.long 0x00 "ID_ISAR5,ISA Feature Register 5"
|
|
tree.end
|
|
tree "Coresight Management Registers"
|
|
width 0xC
|
|
textline " "
|
|
group c14:0x03bd++0x00
|
|
line.long 0x00 "ITCTRL_IOC,Integration Internal Output Control Register"
|
|
bitfld.long 0x00 5. " I_DBGTRIGGER ,Internal DBGTRIGGER" "0,1"
|
|
bitfld.long 0x00 4. " I_DBGRESTARTED ,Internal DBGRESTARTED" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. " I_NPMUIRQ ,Internal nPMUIRQ" "0,1"
|
|
bitfld.long 0x00 2. " InternalCOMMTX ,Internal COMMTX" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 1. " I_COMMRX ,Internal COMMRX" "0,1"
|
|
bitfld.long 0x00 0. " I_DBGACK ,Internal DBGACK" "0,1"
|
|
group c14:0x03be++0x00
|
|
line.long 0x00 "ITCTRL_EOC,Integration External Output Control Register"
|
|
bitfld.long 0x00 7. " NDMAEXTERRIQ ,External nDMAEXTERRIRQ" "0,1"
|
|
bitfld.long 0x00 6. " NDMASIRQ ,External nDMASIRQ" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 5. " NDMAIRQ ,External nDMAIRQ" "0,1"
|
|
bitfld.long 0x00 4. " NPMUIRQ ,External nPMUIRQ" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. " STANDBYWFI ,External STANDBYWFI" "0,1"
|
|
bitfld.long 0x00 2. " COMMTX ,External COMMTX" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 1. " COMMRX ,External COMMRX" "0,1"
|
|
bitfld.long 0x00 0. " DBGACK ,External DBGACK" "0,1"
|
|
rgroup c14:0x03bf++0x00
|
|
line.long 0x00 "ITCTRL_IS,Integration Input Status Register"
|
|
bitfld.long 0x00 11. " CTI_DBGRESTART ,CTI Debug Restart" "0,1"
|
|
bitfld.long 0x00 10. " CTI_EDBGRQ ,CTI Debug Request" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 9. " CTI_PMUEXTIN[1] ,CTI PMUEXTIN[1] Signal" "0,1"
|
|
bitfld.long 0x00 8. " CTI_PMUEXTIN[0] ,CTI PMUEXTIN[0] Signal" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 2. " NFIQ ,nFIQ Input" "0,1"
|
|
bitfld.long 0x00 1. " NIRQ ,nIRQ Input" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 0. " EDBGRQ ,EDBGRQ Input" "0,1"
|
|
group c14:0x3c0--0x3c0
|
|
line.long 0x0 "ITCTRL,Integration Mode Control Register"
|
|
bitfld.long 0x0 0. " IME ,Integration Mode Enable" "Disabled,Enabled"
|
|
group c14:0x3e8--0x3e8
|
|
line.long 0x0 "CLAIMSET,Claim Tag Set Register"
|
|
bitfld.long 0x0 7. " CT7 ,Claim Tag 7" "No Effect,Set"
|
|
bitfld.long 0x0 6. " CT6 ,Claim Tag 6" "No Effect,Set"
|
|
textline " "
|
|
bitfld.long 0x0 5. " CT5 ,Claim Tag 5" "No Effect,Set"
|
|
bitfld.long 0x0 4. " CT4 ,Claim Tag 4" "No Effect,Set"
|
|
textline " "
|
|
bitfld.long 0x0 3. " CT3 ,Claim Tag 3" "No Effect,Set"
|
|
bitfld.long 0x0 2. " CT2 ,Claim Tag 2" "No Effect,Set"
|
|
textline " "
|
|
bitfld.long 0x0 1. " CT1 ,Claim Tag 1" "No Effect,Set"
|
|
bitfld.long 0x0 0. " CT0 ,Claim Tag 0" "No Effect,Set"
|
|
group c14:0x3e9--0x3e9
|
|
line.long 0x0 "CLAIMCLR,Claim Tag Clear Register"
|
|
bitfld.long 0x0 7. " CT7 ,Claim Tag 7" "No Effect,Cleared"
|
|
bitfld.long 0x0 6. " CT6 ,Claim Tag 6" "No Effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x0 5. " CT5 ,Claim Tag 5" "No Effect,Cleared"
|
|
bitfld.long 0x0 4. " CT4 ,Claim Tag 4" "No Effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x0 3. " CT3 ,Claim Tag 3" "No Effect,Cleared"
|
|
bitfld.long 0x0 2. " CT2 ,Claim Tag 2" "No Effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x0 1. " CT1 ,Claim Tag 1" "No Effect,Cleared"
|
|
bitfld.long 0x0 0. " CT0 ,Claim Tag 0" "No Effect,Cleared"
|
|
wgroup c14:0x3ec--0x3ec
|
|
line.long 0x0 "LAR,Lock Access Register"
|
|
hexmask.long.long 0x0 0.--31. 1. " LACK ,Lock Access Control Key"
|
|
rgroup c14:0x3ed--0x3ed
|
|
line.long 0x0 "LSR,Lock Status Register"
|
|
bitfld.long 0x0 2. " 32ACND ,32-bit Access Needed" "Needed,Not needed"
|
|
bitfld.long 0x0 1. " WLCK ,Writes Lock" "Permitted,Ignored"
|
|
textline " "
|
|
bitfld.long 0x0 0. " LI ,Lock Implementation" "Lock ignored,Unlock required"
|
|
rgroup c14:0x3ee--0x3ee
|
|
line.long 0x0 "AUTHSTATUS,Authentication Status Register"
|
|
bitfld.long 0x0 7. " SNIDFI ,Secure Non-invasive Debug Features Implemented" "Not Implemented,Implemented"
|
|
bitfld.long 0x0 6. " SNIDE ,Secure Non-invasive Debug Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 5. " SIDFI ,Secure Invasive Debug Feauter Implemented" "Not Implemented,Implemented"
|
|
bitfld.long 0x0 4. " SIDE ,Secure Invasive Debug Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 3. " NSNIDFI ,Non-secure Non-invasive Debug Feature Implemented" "Not Implemented,Implemented"
|
|
bitfld.long 0x0 2. " NSNIDE ,Non-secure Non-invasive Debug Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 1. " NSIDFI ,Non-secure Invasive Debug Implemented" "Not Implemented,Implemented"
|
|
bitfld.long 0x0 0. " NSIDE ,Non-secure Invasive Debug Enable" "Disabled,Enabled"
|
|
hgroup c14:0x3f2--0x3f2
|
|
hide.long 0x0 "DEVID,Device Identifier (RESERVED)"
|
|
rgroup c14:0x3f3--0x3f3
|
|
line.long 0x0 "DEVTYPE,Device Type"
|
|
hexmask.long.byte 0x00 4.--7. 1. " SUBTYPE ,Subtype"
|
|
hexmask.long.byte 0x00 0.--3. 1. " MAIN_CLASS ,Main class"
|
|
rgroup c14:0x3f8--0x3f8
|
|
line.long 0x0 "PID0,Peripherial ID0"
|
|
hexmask.long.byte 0x0 0.--7. 1. " PN ,Part Number [7:0]"
|
|
rgroup c14:0x3f9--0x3f9
|
|
line.long 0x0 "PID1,Peripherial ID1"
|
|
hexmask.long.byte 0x0 4.--7. 1. " JEP106 ,JEP106 Identity Code [3:0]"
|
|
hexmask.long.byte 0x0 0.--3. 1. " PN ,Part Number [11:8]"
|
|
rgroup c14:0x3fa--0x3fa
|
|
line.long 0x0 "PID2,Peripherial ID2"
|
|
hexmask.long.byte 0x0 4.--7. 1. " REV ,Revision"
|
|
hexmask.long.byte 0x0 0.--2. 1. " JEP106 ,JEP106 Identity Code [6:4]"
|
|
rgroup c14:0x3fb--0x3fb
|
|
line.long 0x0 "PID3,Peripherial ID3"
|
|
hexmask.long.byte 0x0 4.--7. 1. " REVA ,RevAnd"
|
|
hexmask.long.byte 0x0 0.--3. 1. " CMOD ,Customer Modified"
|
|
rgroup c14:0x3f4--0x3f4
|
|
line.long 0x0 "PID4,Peripherial ID4"
|
|
bitfld.long 0x0 4.--7. " 4KBC ,Number of 4KB Blocks Occupied" "1,2,4,8,16,32,64,128,256,512,1024,2048,4096,8192,16384,32768"
|
|
bitfld.long 0x0 0.--3. " JEP106 ,JEP106 Continuation Code" "0000,0001,0010,0011,0100,0101,0110,0111,1000,1001,1010,1011,1100,1101,1110,1111"
|
|
rgroup c14:0x3fc--0x3fc
|
|
line.long 0x0 "COMPONENTID0,Component ID0"
|
|
hexmask.long.byte 0x0 0.--7. 1. " PRBL ,Preamble"
|
|
rgroup c14:0x3fd--0x3fd
|
|
line.long 0x0 "COMPONENTID1,Component ID1"
|
|
hexmask.long.byte 0x0 4.--7. 1. " CCLASS ,Component Class (CoreSight Component)"
|
|
hexmask.long.byte 0x0 0.--3. 1. " PRBL ,Preamble"
|
|
rgroup c14:0x3fe--0x3fe
|
|
line.long 0x0 "COMPONENTID2,Component ID2"
|
|
hexmask.long.byte 0x0 0.--7. 1. " PRBL ,Preamble"
|
|
rgroup c14:0x3ff--0x3ff
|
|
line.long 0x0 "COMPONENTID3,Component ID3"
|
|
hexmask.long.byte 0x0 0.--7. 1. " PRBL ,Preamble"
|
|
tree.end
|
|
textline " "
|
|
width 0x7
|
|
rgroup c14:0x000--0x000
|
|
line.long 0x0 "DIDR,Debug ID Register"
|
|
bitfld.long 0x0 28.--31. " WRP ,Number of Watchpoint Register Pairs" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16"
|
|
bitfld.long 0x0 24.--27. " BRP ,Number of Breakpoint Register Pairs" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16"
|
|
bitfld.long 0x0 20.--23. " CTX_CMP ,Number of BRPs with Context ID Comparison Capability" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16"
|
|
textline " "
|
|
bitfld.long 0x0 16.--19. " VERSION ,Debug Architecture Version" "Reserved,ARMv6,ARMv6.1,ARMv7,?..."
|
|
textline " "
|
|
bitfld.long 0x0 13. " PCSAMPLE ,PC Sample register implemented" "Low,High"
|
|
bitfld.long 0x0 12. " SECURITY ,Security Extensions implemented" "Not implemented,Implemented"
|
|
textline " "
|
|
bitfld.long 0x0 4.--7. " VARIANT ,Implementation-defined Variant Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x0 0.--3. " REVISION ,Implementation-defined Revision Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group c14:0x22--0x22
|
|
line.long 0x0 "DSCR,Debug Status and Control Register"
|
|
bitfld.long 0x0 30. " DTRRXFULL ,The DTRRX Full Flag" "Empty,Full"
|
|
bitfld.long 0x0 29. " DTRTXfull ,The DTRTX Full Flag" "Empty,Full"
|
|
textline " "
|
|
bitfld.long 0x00 27. " DTRRXFULL_L ,The DTRRX Full Flag 1" "Empty,Full"
|
|
bitfld.long 0x00 26. " DTRTXFULL_L ,The DTRTX Full Flag 1" "Empty,Full"
|
|
textline " "
|
|
bitfld.long 0x0 25. " SPA ,Sticky Pipeline Advance" "No effect,Instruction retired"
|
|
bitfld.long 0x0 24. " IC ,Instruction Complete" "Executing,Not executing"
|
|
textline " "
|
|
bitfld.long 0x0 20.--21. " DTR ,DTR Access Mode" "Non-blocking,Stall,Fast,?..."
|
|
bitfld.long 0x0 19. " NSWS ,Imprecise Data Aborts discarded" "Not discarded,Discarded"
|
|
textline " "
|
|
bitfld.long 0x0 18. " NS ,Non-secure World Status" "Secured,Not secured"
|
|
bitfld.long 0x0 17. " NSPNIDEN ,Secure Non-invasive Debug Disabled" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x0 16. " NSPIDEN ,Secure Invasive Debug Disabled" "Enabled,Disabled"
|
|
bitfld.long 0x0 15. " MONITOR ,Monitor Debug-mode enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 14. " HDEN ,Halting Debug-mode enable" "Disabled,Enabled"
|
|
bitfld.long 0x0 13. " EXECUTE ,Execute instruction enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 12. " COMMS ,User mode access to Comms Channel disable" "Enabled,Disabled"
|
|
bitfld.long 0x0 11. " INTDIS ,Disable Interrupts" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x0 10. " DBGACK ,Force Debug Acknowledge" "Not forced,Forced"
|
|
bitfld.long 0x0 8. " UEXT ,Sticky Undefined Exception" "No exception,Exception"
|
|
textline " "
|
|
bitfld.long 0x0 7. " IABORT ,Sticky Imprecise Abort" "Not aborted,Aborted"
|
|
bitfld.long 0x0 6. " PABORT ,Sticky Precise Abort" "Not aborted,Aborted"
|
|
textline " "
|
|
bitfld.long 0x0 2.--5. " MOE ,Method of Debug Entry" "Debug Entry,Breakpoint,Imprecise Watchpoint,BKPT instruction,External debug,Vector catch,Reserved,Reserved,OS Unlock,?..."
|
|
bitfld.long 0x0 1. " RESTARTED ,Core Restarted" "Debug not exited,Debug exited"
|
|
textline " "
|
|
bitfld.long 0x0 0. " HALTED ,Core Halted" "Normal state,Debug state"
|
|
if (((data.long(c14:0x00))&0x01000)==0x00000)
|
|
group c14:0x007--0x007
|
|
line.long 0x0 "VCR,Vector Catch Register"
|
|
bitfld.long 0x0 7. " FIQ ,Vector Catch Enable FIQ" "Disabled,Enabled"
|
|
bitfld.long 0x0 6. " IRQ ,Vector Catch Enable IRQ" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 4. " DABORT ,Vector Catch Enable Data Abort" "Disabled,Enabled"
|
|
bitfld.long 0x0 3. " PABORT ,Vector Catch Enable Prefetch Abort" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 2. " SWI ,Vector Catch Enable SWI" "Disabled,Enabled"
|
|
bitfld.long 0x0 1. " UNDEF ,Vector Catch Enable Undefined Instruction" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 0. " RESET ,Vector Catch Enable Reset" "Disabled,Enabled"
|
|
else
|
|
group c14:0x007--0x007
|
|
line.long 0x0 "VCR,Vector Catch Register"
|
|
bitfld.long 0x0 31. " FIQN ,Vector Catch Enable FIQ (Non-secure)" "Disabled,Enabled"
|
|
bitfld.long 0x0 30. " IRQN ,Vector Catch Enable IRQ (Non-secure)" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 28. " DABORTN ,Vector Catch Enable Data Abort (Non-secure)" "Disabled,Enabled"
|
|
bitfld.long 0x0 27. " PABORTN ,Vector Catch Enable Prefetch abort (Non-secure)" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 26. " SWIN ,Vector Catch Enable SWI (Non-secure)" "Disabled,Enabled"
|
|
bitfld.long 0x0 25. " UNDEFS ,Vector Catch Enable Undefined (Non-secure)" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 15. " FIQS ,Vector Catch Enable FIQ (Secure)" "Disabled,Enabled"
|
|
bitfld.long 0x0 14. " IRQS ,Vector Catch Enable IRQ (Secure)" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 12. " DABORTS ,Vector Catch Enable Data Abort (Secure)" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " PABORTS ,Vector Catch Enable Prefetch abort (Secure)" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 10. " SMI ,Vector Catch Enable SMI (Secure)" "Disabled,Enabled"
|
|
bitfld.long 0x0 7. " FIQ ,Vector Catch Enable FIQ" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 6. " IRQ ,Vector Catch Enable IRQ" "Disabled,Enabled"
|
|
bitfld.long 0x0 4. " DABORT0 ,Vector Catch Enable Data Abort" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 3. " PABORT ,Vector Catch Enable Prefetch Abort" "Disabled,Enabled"
|
|
bitfld.long 0x0 2. " SWI ,Vector Catch Enable SWI" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 1. " UNDEF ,Vector Catch Enable Undefined Instruction" "Disabled,Enabled"
|
|
bitfld.long 0x0 0. " RESET ,Vector Catch Enable Reset" "Disabled,Enabled"
|
|
endif
|
|
hgroup c14:0x020--0x020
|
|
hide.long 0x0 "DTRRX,Target -> Host Data Transfer Register"
|
|
in
|
|
group c14:0x023--0x023
|
|
line.long 0x0 "DTRTX,Host -> Target Data Transfer Register"
|
|
hexmask.long 0x00 0.--31. 1. " HTD ,Host -> target data"
|
|
group c14:0x09++0x00
|
|
line.long 0x00 "ECR,Event Catch Register"
|
|
bitfld.long 0x00 0. " OSUC ,OS Unlock Catch" "Disabled,Enabled"
|
|
group c14:0x0a++0x00
|
|
line.long 0x00 "DSCCR,Debug State Cache Control Register"
|
|
bitfld.long 0x00 2. " NWT ,Not Write-Through" "Forced,Normal"
|
|
bitfld.long 0x00 0. " DUCL ,Data and Unified Cache Linefill" "Disabled,Normal"
|
|
wgroup c14:0x21++0x00
|
|
line.long 0x00 "ITR,Instruction Transfer Register"
|
|
hexmask.long 0x00 0.--31. 1. " Data ,ARM Instruction for the Processor in Debug State Execute"
|
|
wgroup c14:0x24++0x00
|
|
line.long 0x00 "DRCR,Debug Run Control Register"
|
|
bitfld.long 0x00 3. " CSPA ,Clear Sticky Pipeline Advance" "Not cleared,Cleared"
|
|
bitfld.long 0x00 2. " CSE ,Clear Sticky Exceptions" "Not cleared,Cleared"
|
|
textline " "
|
|
bitfld.long 0x00 1. " RR ,Restart Request" "Not requested,Requested"
|
|
bitfld.long 0x00 0. " HR ,Halt Request" "Not requested,Requested"
|
|
wgroup c14:0xc0++0x00
|
|
line.long 0x00 "OSLAR,Operating System Lock Access Register"
|
|
hexmask.long 0x00 0.--31. 1. " OSLA ,OS Lock Access"
|
|
rgroup c14:0xc1++0x00
|
|
line.long 0x00 "OSLSR,Operating System Lock Status Register"
|
|
bitfld.long 0x00 2. " 32_BA ,32-Bit Access" "Not required,Required"
|
|
bitfld.long 0x00 1. " LB ,Locked Bit" "Not locked,Locked"
|
|
bitfld.long 0x00 0. " LIB ,Lock Implemented Bit" "Not implemented,Implemented"
|
|
group c14:0xc2++0x00
|
|
line.long 0x00 "OSSRR,Operating System Save and Restore Register"
|
|
hexmask.long 0x00 0.--31. 1. " OSSR ,OS Save and Restore"
|
|
group c14:0xc4++0x00
|
|
line.long 0x00 "PRCR,Device Power-Down and Reset Control Register"
|
|
bitfld.long 0x00 2. " HIR ,Hold Internal Reset" "Not held,Held"
|
|
bitfld.long 0x00 1. " FIR ,Force Internal Reset" "Not forced,Forced"
|
|
bitfld.long 0x00 0. " NPD ,No Power-Down" "DBGNOPWRDWN low,DBGNOPWRDWN high"
|
|
hgroup c14:0xc5++0x00
|
|
hide.long 0x00 "PRSR,Device Power-Down and Reset Status Register"
|
|
in
|
|
tree.end
|
|
tree "Breakpoint Registers"
|
|
group c14:0x40++0x00
|
|
line.long 0x00 "BVR0,Breakpoint Value Register 0"
|
|
hexmask.long 0x00 0.--31. 1. " BV0 ,Breakpoint Value 0"
|
|
group c14:0x50++0x00
|
|
line.long 0x00 "BCR0,Breakpoint Control Register 0"
|
|
bitfld.long 0x00 24.--28. " BAM ,Breakpoint Address Mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF"
|
|
bitfld.long 0x00 20.--22. " M ,BVR Meaning" "IVA match,Linked IVA match,Reserved,Reserved,IVA mismatch,Linked IVA mismatch,?..."
|
|
bitfld.long 0x00 16.--19. " LBRP ,Linked BRP Number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15"
|
|
bitfld.long 0x00 14.--15. " SWAC ,Secure World Access Control" "Both,Nonsecure,Secure,?..."
|
|
textline " "
|
|
bitfld.long 0x0 8. " BAS ,Byte 3 address select" "0,1"
|
|
bitfld.long 0x0 7. ",Byte 2 address select" "0,1"
|
|
bitfld.long 0x0 6. ",Byte 1 address select" "0,1"
|
|
bitfld.long 0x0 5. ",Byte 0 address select" "0,1"
|
|
bitfld.long 0x00 1.--2. " S ,Supervisor Access Control" "User/system/supervisor,Privileged,User,Any"
|
|
bitfld.long 0x00 0. " B ,Breakpoint Enable" "Disabled,Enabled"
|
|
group c14:0x41++0x00
|
|
line.long 0x00 "BVR1,Breakpoint Value Register 1"
|
|
hexmask.long 0x00 0.--31. 1. " BV1 ,Breakpoint Value 1"
|
|
group c14:0x51++0x00
|
|
line.long 0x00 "BCR1,Breakpoint Control Register 1"
|
|
bitfld.long 0x00 24.--28. " BAM ,Breakpoint Address Mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF"
|
|
bitfld.long 0x00 20.--22. " M ,BVR Meaning" "IVA match,Linked IVA match,Reserved,Reserved,IVA mismatch,Linked IVA mismatch,?..."
|
|
bitfld.long 0x00 16.--19. " LBRP ,Linked BRP Number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15"
|
|
bitfld.long 0x00 14.--15. " SWAC ,Secure World Access Control" "Both,Nonsecure,Secure,?..."
|
|
textline " "
|
|
bitfld.long 0x0 8. " BAS ,Byte 3 address select" "0,1"
|
|
bitfld.long 0x0 7. ",Byte 2 address select" "0,1"
|
|
bitfld.long 0x0 6. ",Byte 1 address select" "0,1"
|
|
bitfld.long 0x0 5. ",Byte 0 address select" "0,1"
|
|
bitfld.long 0x00 1.--2. " S ,Supervisor Access Control" "User/system/supervisor,Privileged,User,Any"
|
|
bitfld.long 0x00 0. " B ,Breakpoint Enable" "Disabled,Enabled"
|
|
group c14:0x42++0x00
|
|
line.long 0x00 "BVR2,Breakpoint Value Register 2"
|
|
hexmask.long 0x00 0.--31. 1. " BV2 ,Breakpoint Value 2"
|
|
group c14:0x52++0x00
|
|
line.long 0x00 "BCR2,Breakpoint Control Register 2"
|
|
bitfld.long 0x00 24.--28. " BAM ,Breakpoint Address Mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF"
|
|
bitfld.long 0x00 20.--22. " M ,BVR Meaning" "IVA match,Linked IVA match,Reserved,Reserved,IVA mismatch,Linked IVA mismatch,?..."
|
|
bitfld.long 0x00 16.--19. " LBRP ,Linked BRP Number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15"
|
|
bitfld.long 0x00 14.--15. " SWAC ,Secure World Access Control" "Both,Nonsecure,Secure,?..."
|
|
textline " "
|
|
bitfld.long 0x0 8. " BAS ,Byte 3 address select" "0,1"
|
|
bitfld.long 0x0 7. ",Byte 2 address select" "0,1"
|
|
bitfld.long 0x0 6. ",Byte 1 address select" "0,1"
|
|
bitfld.long 0x0 5. ",Byte 0 address select" "0,1"
|
|
bitfld.long 0x00 1.--2. " S ,Supervisor Access Control" "User/system/supervisor,Privileged,User,Any"
|
|
bitfld.long 0x00 0. " B ,Breakpoint Enable" "Disabled,Enabled"
|
|
group c14:0x43++0x00
|
|
line.long 0x00 "BVR3,Breakpoint Value Register 3"
|
|
hexmask.long 0x00 0.--31. 1. " BV3 ,Breakpoint Value 3"
|
|
group c14:0x53++0x00
|
|
line.long 0x00 "BCR3,Breakpoint Control Register 3"
|
|
bitfld.long 0x00 24.--28. " BAM ,Breakpoint Address Mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF"
|
|
bitfld.long 0x00 20.--22. " M ,BVR Meaning" "IVA match,Linked IVA match,Reserved,Reserved,IVA mismatch,Linked IVA mismatch,?..."
|
|
bitfld.long 0x00 16.--19. " LBRP ,Linked BRP Number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15"
|
|
bitfld.long 0x00 14.--15. " SWAC ,Secure World Access Control" "Both,Nonsecure,Secure,?..."
|
|
textline " "
|
|
bitfld.long 0x0 8. " BAS ,Byte 3 address select" "0,1"
|
|
bitfld.long 0x0 7. ",Byte 2 address select" "0,1"
|
|
bitfld.long 0x0 6. ",Byte 1 address select" "0,1"
|
|
bitfld.long 0x0 5. ",Byte 0 address select" "0,1"
|
|
bitfld.long 0x00 1.--2. " S ,Supervisor Access Control" "User/system/supervisor,Privileged,User,Any"
|
|
bitfld.long 0x00 0. " B ,Breakpoint Enable" "Disabled,Enabled"
|
|
group c14:0x44++0x00
|
|
line.long 0x00 "BVR4,Breakpoint Value Register 4"
|
|
hexmask.long 0x00 0.--31. 1. " BV4 ,Breakpoint Value 4"
|
|
group c14:0x54++0x00
|
|
line.long 0x00 "BCR4,Breakpoint Control Register 4"
|
|
bitfld.long 0x00 24.--28. " BAM ,Breakpoint Address Mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF"
|
|
bitfld.long 0x00 20.--22. " M ,BVR Meaning" "IVA match,Linked IVA match,Unlinked ID,Linked ID,IVA mismatch,Linked IVA mismatch,?..."
|
|
bitfld.long 0x00 16.--19. " LBRP ,Linked BRP Number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15"
|
|
bitfld.long 0x00 14.--15. " SWAC ,Secure World Access Control" "Both,Nonsecure,Secure,?..."
|
|
textline " "
|
|
bitfld.long 0x0 8. " BAS ,Byte 3 address select" "0,1"
|
|
bitfld.long 0x0 7. ",Byte 2 address select" "0,1"
|
|
bitfld.long 0x0 6. ",Byte 1 address select" "0,1"
|
|
bitfld.long 0x0 5. ",Byte 0 address select" "0,1"
|
|
bitfld.long 0x00 1.--2. " S ,Supervisor Access Control" "User/system/supervisor,Privileged,User,Any"
|
|
bitfld.long 0x00 0. " B ,Breakpoint Enable" "Disabled,Enabled"
|
|
group c14:0x45++0x00
|
|
line.long 0x00 "BVR5,Breakpoint Value Register 5"
|
|
hexmask.long 0x00 0.--31. 1. " BV5 ,Breakpoint Value 5"
|
|
group c14:0x55++0x00
|
|
line.long 0x00 "BCR5,Breakpoint Control Register 5"
|
|
bitfld.long 0x00 24.--28. " BAM ,Breakpoint Address Mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF"
|
|
bitfld.long 0x00 20.--22. " M ,BVR Meaning" "IVA match,Linked IVA match,Unlinked ID,Linked ID,IVA mismatch,Linked IVA mismatch,?..."
|
|
bitfld.long 0x00 16.--19. " LBRP ,Linked BRP Number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15"
|
|
bitfld.long 0x00 14.--15. " SWAC ,Secure World Access Control" "Both,Nonsecure,Secure,?..."
|
|
textline " "
|
|
bitfld.long 0x0 8. " BAS ,Byte 3 address select" "0,1"
|
|
bitfld.long 0x0 7. ",Byte 2 address select" "0,1"
|
|
bitfld.long 0x0 6. ",Byte 1 address select" "0,1"
|
|
bitfld.long 0x0 5. ",Byte 0 address select" "0,1"
|
|
bitfld.long 0x00 1.--2. " S ,Supervisor Access Control" "User/system/supervisor,Privileged,User,Any"
|
|
bitfld.long 0x00 0. " B ,Breakpoint Enable" "Disabled,Enabled"
|
|
group c14:0x46++0x00
|
|
line.long 0x00 "BVR6,Breakpoint Value Register 6"
|
|
hexmask.long 0x00 0.--31. 1. " BV6 ,Breakpoint Value 6"
|
|
group c14:0x56++0x00
|
|
line.long 0x00 "BCR6,Breakpoint Control Register 6"
|
|
bitfld.long 0x00 24.--28. " BAM ,Breakpoint Address Mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF"
|
|
bitfld.long 0x00 20.--22. " M ,BVR Meaning" "IVA match,Linked IVA match,Unlinked ID,Linked ID,IVA mismatch,Linked IVA mismatch,?..."
|
|
bitfld.long 0x00 16.--19. " LBRP ,Linked BRP Number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15"
|
|
bitfld.long 0x00 14.--15. " SWAC ,Secure World Access Control" "Both,Nonsecure,Secure,?..."
|
|
textline " "
|
|
bitfld.long 0x0 8. " BAS ,Byte 3 address select" "0,1"
|
|
bitfld.long 0x0 7. ",Byte 2 address select" "0,1"
|
|
bitfld.long 0x0 6. ",Byte 1 address select" "0,1"
|
|
bitfld.long 0x0 5. ",Byte 0 address select" "0,1"
|
|
bitfld.long 0x00 1.--2. " S ,Supervisor Access Control" "User/system/supervisor,Privileged,User,Any"
|
|
bitfld.long 0x00 0. " B ,Breakpoint Enable" "Disabled,Enabled"
|
|
group c14:0x47++0x00
|
|
line.long 0x00 "BVR7,Breakpoint Value Register 7"
|
|
hexmask.long 0x00 0.--31. 1. " BV7 ,Breakpoint Value 7"
|
|
group c14:0x57++0x00
|
|
line.long 0x00 "BCR7,Breakpoint Control Register 7"
|
|
bitfld.long 0x00 24.--28. " BAM ,Breakpoint Address Mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF"
|
|
bitfld.long 0x00 20.--22. " M ,BVR Meaning" "IVA match,Linked IVA match,Unlinked ID,Linked ID,IVA mismatch,Linked IVA mismatch,?..."
|
|
bitfld.long 0x00 16.--19. " LBRP ,Linked BRP Number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15"
|
|
bitfld.long 0x00 14.--15. " SWAC ,Secure World Access Control" "Both,Nonsecure,Secure,?..."
|
|
textline " "
|
|
bitfld.long 0x0 8. " BAS ,Byte 3 address select" "0,1"
|
|
bitfld.long 0x0 7. ",Byte 2 address select" "0,1"
|
|
bitfld.long 0x0 6. ",Byte 1 address select" "0,1"
|
|
bitfld.long 0x0 5. ",Byte 0 address select" "0,1"
|
|
bitfld.long 0x00 1.--2. " S ,Supervisor Access Control" "User/system/supervisor,Privileged,User,Any"
|
|
bitfld.long 0x00 0. " B ,Breakpoint Enable" "Disabled,Enabled"
|
|
tree.end
|
|
tree "Watchpoint Control Registers"
|
|
group c14:0x60++0x00
|
|
line.long 0x00 "WVR0,Watchpoint Value Register 0"
|
|
hexmask.long 0x00 2.--31. 0x04 " WA0 ,Watchpoint Address 0"
|
|
group c14:0x70--0x70
|
|
line.long 0x0 "WCR0,Watchpoint Control Register 0"
|
|
bitfld.long 0x0 24.--28. " WAM ,Watchpoint address mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF"
|
|
bitfld.long 0x0 20. " EL ,Enable Linking" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 16.--19. " LBN ,Linked BRP number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15"
|
|
bitfld.long 0x0 14.--15. " SWAC ,Secure world access control" "Non-secure & Secure,Non-secure,Secure,?..."
|
|
textline " "
|
|
bitfld.long 0x0 12. " BAS ,Byte 7 address select" "0,1"
|
|
bitfld.long 0x0 11. ",Byte 6 address select" "0,1"
|
|
bitfld.long 0x0 10. ",Byte 5 address select" "0,1"
|
|
bitfld.long 0x0 9. ",Byte 4 address select" "0,1"
|
|
bitfld.long 0x0 8. ",Byte 3 address select" "0,1"
|
|
bitfld.long 0x0 7. ",Byte 2 address select" "0,1"
|
|
bitfld.long 0x0 6. ",Byte 1 address select" "0,1"
|
|
bitfld.long 0x0 5. ",Byte 0 address select" "0,1"
|
|
textline " "
|
|
bitfld.long 0x0 3.--4. " RD/WR ,Load/Store access control" "Reserved,Load,Store,Any"
|
|
bitfld.long 0x0 1.--2. " PAC ,Privileged access control" "Reserved,Privileged,USR,Any"
|
|
textline " "
|
|
bitfld.long 0x0 0. " WE ,Watchpoint enable" "Disabled,Enabled"
|
|
group c14:0x61++0x00
|
|
line.long 0x00 "WVR1,Watchpoint Value Register 1"
|
|
hexmask.long 0x00 2.--31. 0x04 " WA1 ,Watchpoint Address 1"
|
|
group c14:0x71--0x71
|
|
line.long 0x0 "WCR1,Watchpoint Control Register 1"
|
|
bitfld.long 0x0 24.--28. " WAM ,Watchpoint address mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF"
|
|
bitfld.long 0x0 20. " EL ,Enable Linking" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 16.--19. " LBN ,Linked BRP number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15"
|
|
bitfld.long 0x0 14.--15. " SWAC ,Secure world access control" "Non-secure & Secure,Non-secure,Secure,?..."
|
|
textline " "
|
|
bitfld.long 0x0 12. " BAS ,Byte 7 address select" "0,1"
|
|
bitfld.long 0x0 11. ",Byte 6 address select" "0,1"
|
|
bitfld.long 0x0 10. ",Byte 5 address select" "0,1"
|
|
bitfld.long 0x0 9. ",Byte 4 address select" "0,1"
|
|
bitfld.long 0x0 8. ",Byte 3 address select" "0,1"
|
|
bitfld.long 0x0 7. ",Byte 2 address select" "0,1"
|
|
bitfld.long 0x0 6. ",Byte 1 address select" "0,1"
|
|
bitfld.long 0x0 5. ",Byte 0 address select" "0,1"
|
|
textline " "
|
|
bitfld.long 0x0 3.--4. " RD/WR ,Load/Store access control" "Reserved,Load,Store,Any"
|
|
bitfld.long 0x0 1.--2. " PAC ,Privileged access control" "Reserved,Privileged,USR,Any"
|
|
textline " "
|
|
bitfld.long 0x0 0. " WE ,Watchpoint enable" "Disabled,Enabled"
|
|
group c14:0x62++0x00
|
|
line.long 0x00 "WVR2,Watchpoint Value Register 2"
|
|
hexmask.long 0x00 2.--31. 0x04 " WA2 ,Watchpoint Address 2"
|
|
group c14:0x72--0x72
|
|
line.long 0x0 "WCR2,Watchpoint Control Register 2"
|
|
bitfld.long 0x0 24.--28. " WAM ,Watchpoint address mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF"
|
|
bitfld.long 0x0 20. " EL ,Enable Linking" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 16.--19. " LBN ,Linked BRP number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15"
|
|
bitfld.long 0x0 14.--15. " SWAC ,Secure world access control" "Non-secure & Secure,Non-secure,Secure,?..."
|
|
textline " "
|
|
bitfld.long 0x0 12. " BAS ,Byte 7 address select" "0,1"
|
|
bitfld.long 0x0 11. ",Byte 6 address select" "0,1"
|
|
bitfld.long 0x0 10. ",Byte 5 address select" "0,1"
|
|
bitfld.long 0x0 9. ",Byte 4 address select" "0,1"
|
|
bitfld.long 0x0 8. ",Byte 3 address select" "0,1"
|
|
bitfld.long 0x0 7. ",Byte 2 address select" "0,1"
|
|
bitfld.long 0x0 6. ",Byte 1 address select" "0,1"
|
|
bitfld.long 0x0 5. ",Byte 0 address select" "0,1"
|
|
textline " "
|
|
bitfld.long 0x0 3.--4. " RD/WR ,Load/Store access control" "Reserved,Load,Store,Any"
|
|
bitfld.long 0x0 1.--2. " PAC ,Privileged access control" "Reserved,Privileged,USR,Any"
|
|
textline " "
|
|
bitfld.long 0x0 0. " WE ,Watchpoint enable" "Disabled,Enabled"
|
|
group c14:0x63++0x00
|
|
line.long 0x00 "WVR3,Watchpoint Value Register 3"
|
|
hexmask.long 0x00 2.--31. 0x04 " WA3 ,Watchpoint Address 3"
|
|
group c14:0x73--0x73
|
|
line.long 0x0 "WCR3,Watchpoint Control Register 3"
|
|
bitfld.long 0x0 24.--28. " WAM ,Watchpoint address mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF"
|
|
bitfld.long 0x0 20. " EL ,Enable Linking" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 16.--19. " LBN ,Linked BRP number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15"
|
|
bitfld.long 0x0 14.--15. " SWAC ,Secure world access control" "Non-secure & Secure,Non-secure,Secure,?..."
|
|
textline " "
|
|
bitfld.long 0x0 12. " BAS ,Byte 7 address select" "0,1"
|
|
bitfld.long 0x0 11. ",Byte 6 address select" "0,1"
|
|
bitfld.long 0x0 10. ",Byte 5 address select" "0,1"
|
|
bitfld.long 0x0 9. ",Byte 4 address select" "0,1"
|
|
bitfld.long 0x0 8. ",Byte 3 address select" "0,1"
|
|
bitfld.long 0x0 7. ",Byte 2 address select" "0,1"
|
|
bitfld.long 0x0 6. ",Byte 1 address select" "0,1"
|
|
bitfld.long 0x0 5. ",Byte 0 address select" "0,1"
|
|
textline " "
|
|
bitfld.long 0x0 3.--4. " RD/WR ,Load/Store access control" "Reserved,Load,Store,Any"
|
|
bitfld.long 0x0 1.--2. " PAC ,Privileged access control" "Reserved,Privileged,USR,Any"
|
|
textline " "
|
|
bitfld.long 0x0 0. " WE ,Watchpoint enable" "Disabled,Enabled"
|
|
group c14:0x64++0x00
|
|
line.long 0x00 "WVR4,Watchpoint Value Register 4"
|
|
hexmask.long 0x00 2.--31. 0x04 " WA4 ,Watchpoint Address 4"
|
|
group c14:0x74--0x74
|
|
line.long 0x0 "WCR4,Watchpoint Control Register 4"
|
|
bitfld.long 0x0 24.--28. " WAM ,Watchpoint address mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF"
|
|
bitfld.long 0x0 20. " EL ,Enable Linking" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 16.--19. " LBN ,Linked BRP number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15"
|
|
bitfld.long 0x0 14.--15. " SWAC ,Secure world access control" "Non-secure & Secure,Non-secure,Secure,?..."
|
|
textline " "
|
|
bitfld.long 0x0 12. " BAS ,Byte 7 address select" "0,1"
|
|
bitfld.long 0x0 11. ",Byte 6 address select" "0,1"
|
|
bitfld.long 0x0 10. ",Byte 5 address select" "0,1"
|
|
bitfld.long 0x0 9. ",Byte 4 address select" "0,1"
|
|
bitfld.long 0x0 8. ",Byte 3 address select" "0,1"
|
|
bitfld.long 0x0 7. ",Byte 2 address select" "0,1"
|
|
bitfld.long 0x0 6. ",Byte 1 address select" "0,1"
|
|
bitfld.long 0x0 5. ",Byte 0 address select" "0,1"
|
|
textline " "
|
|
bitfld.long 0x0 3.--4. " RD/WR ,Load/Store access control" "Reserved,Load,Store,Any"
|
|
bitfld.long 0x0 1.--2. " PAC ,Privileged access control" "Reserved,Privileged,USR,Any"
|
|
textline " "
|
|
bitfld.long 0x0 0. " WE ,Watchpoint enable" "Disabled,Enabled"
|
|
group c14:0x65++0x00
|
|
line.long 0x00 "WVR5,Watchpoint Value Register 5"
|
|
hexmask.long 0x00 2.--31. 0x04 " WA5 ,Watchpoint Address 5"
|
|
group c14:0x75--0x75
|
|
line.long 0x0 "WCR5,Watchpoint Control Register 5"
|
|
bitfld.long 0x0 24.--28. " WAM ,Watchpoint address mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF"
|
|
bitfld.long 0x0 20. " EL ,Enable Linking" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 16.--19. " LBN ,Linked BRP number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15"
|
|
bitfld.long 0x0 14.--15. " SWAC ,Secure world access control" "Non-secure & Secure,Non-secure,Secure,?..."
|
|
textline " "
|
|
bitfld.long 0x0 12. " BAS ,Byte 7 address select" "0,1"
|
|
bitfld.long 0x0 11. ",Byte 6 address select" "0,1"
|
|
bitfld.long 0x0 10. ",Byte 5 address select" "0,1"
|
|
bitfld.long 0x0 9. ",Byte 4 address select" "0,1"
|
|
bitfld.long 0x0 8. ",Byte 3 address select" "0,1"
|
|
bitfld.long 0x0 7. ",Byte 2 address select" "0,1"
|
|
bitfld.long 0x0 6. ",Byte 1 address select" "0,1"
|
|
bitfld.long 0x0 5. ",Byte 0 address select" "0,1"
|
|
textline " "
|
|
bitfld.long 0x0 3.--4. " RD/WR ,Load/Store access control" "Reserved,Load,Store,Any"
|
|
bitfld.long 0x0 1.--2. " PAC ,Privileged access control" "Reserved,Privileged,USR,Any"
|
|
textline " "
|
|
bitfld.long 0x0 0. " WE ,Watchpoint enable" "Disabled,Enabled"
|
|
group c14:0x66++0x00
|
|
line.long 0x00 "WVR6,Watchpoint Value Register 6"
|
|
hexmask.long 0x00 2.--31. 0x04 " WA6 ,Watchpoint Address 6"
|
|
group c14:0x76--0x76
|
|
line.long 0x0 "WCR6,Watchpoint Control Register 6"
|
|
bitfld.long 0x0 24.--28. " WAM ,Watchpoint address mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF"
|
|
bitfld.long 0x0 20. " EL ,Enable Linking" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 16.--19. " LBN ,Linked BRP number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15"
|
|
bitfld.long 0x0 14.--15. " SWAC ,Secure world access control" "Non-secure & Secure,Non-secure,Secure,?..."
|
|
textline " "
|
|
bitfld.long 0x0 12. " BAS ,Byte 7 address select" "0,1"
|
|
bitfld.long 0x0 11. ",Byte 6 address select" "0,1"
|
|
bitfld.long 0x0 10. ",Byte 5 address select" "0,1"
|
|
bitfld.long 0x0 9. ",Byte 4 address select" "0,1"
|
|
bitfld.long 0x0 8. ",Byte 3 address select" "0,1"
|
|
bitfld.long 0x0 7. ",Byte 2 address select" "0,1"
|
|
bitfld.long 0x0 6. ",Byte 1 address select" "0,1"
|
|
bitfld.long 0x0 5. ",Byte 0 address select" "0,1"
|
|
textline " "
|
|
bitfld.long 0x0 3.--4. " RD/WR ,Load/Store access control" "Reserved,Load,Store,Any"
|
|
bitfld.long 0x0 1.--2. " PAC ,Privileged access control" "Reserved,Privileged,USR,Any"
|
|
textline " "
|
|
bitfld.long 0x0 0. " WE ,Watchpoint enable" "Disabled,Enabled"
|
|
group c14:0x67++0x00
|
|
line.long 0x00 "WVR7,Watchpoint Value Register 7"
|
|
hexmask.long 0x00 2.--31. 0x04 " WA7 ,Watchpoint Address 7"
|
|
group c14:0x77--0x77
|
|
line.long 0x0 "WCR7,Watchpoint Control Register 7"
|
|
bitfld.long 0x0 24.--28. " WAM ,Watchpoint address mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF"
|
|
bitfld.long 0x0 20. " EL ,Enable Linking" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 16.--19. " LBN ,Linked BRP number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15"
|
|
bitfld.long 0x0 14.--15. " SWAC ,Secure world access control" "Non-secure & Secure,Non-secure,Secure,?..."
|
|
textline " "
|
|
bitfld.long 0x0 12. " BAS ,Byte 7 address select" "0,1"
|
|
bitfld.long 0x0 11. ",Byte 6 address select" "0,1"
|
|
bitfld.long 0x0 10. ",Byte 5 address select" "0,1"
|
|
bitfld.long 0x0 9. ",Byte 4 address select" "0,1"
|
|
bitfld.long 0x0 8. ",Byte 3 address select" "0,1"
|
|
bitfld.long 0x0 7. ",Byte 2 address select" "0,1"
|
|
bitfld.long 0x0 6. ",Byte 1 address select" "0,1"
|
|
bitfld.long 0x0 5. ",Byte 0 address select" "0,1"
|
|
textline " "
|
|
bitfld.long 0x0 3.--4. " RD/WR ,Load/Store access control" "Reserved,Load,Store,Any"
|
|
bitfld.long 0x0 1.--2. " PAC ,Privileged access control" "Reserved,Privileged,USR,Any"
|
|
textline " "
|
|
bitfld.long 0x0 0. " WE ,Watchpoint enable" "Disabled,Enabled"
|
|
group c14:0x006--0x006
|
|
line.long 0x0 "WFAR,Watchpoint Fault Address Register"
|
|
hexmask.long.long 0x00 1.--31. 0x02 " WFAR ,Address of the watchpointed instruction"
|
|
tree.end
|
|
AUTOINDENT.POP
|
|
tree.end
|
|
endif
|
|
tree "SYS (System and Peripheral Control Registers)"
|
|
tree "SYS1 (Primary System Registers)"
|
|
base ad:0xFFFFFF00
|
|
sif (cpuis("TMS570LS09*")||cpuis("TMS570LS07*")||cpuis("TMS570LS0232"))
|
|
sif (cpuis("TMS570LS09*")||cpuis("TMS570LS07*")||cpuis("TMS570LS0232"))
|
|
endian.be
|
|
endif
|
|
width 16.
|
|
tree "System Pin Control Registers"
|
|
group.long 0x00++0x07
|
|
line.long 0x00 "SYSPC1,SYS Pin Control Register 1"
|
|
bitfld.long 0x00 0. " ECPCLK_FUN ,ECPCLK function" "GIO,ECPCLK"
|
|
line.long 0x04 "SYSPC2,SYS Pin Control Register 2"
|
|
bitfld.long 0x04 0. " ECPCLK_DIR ,ECPCLK data direction" "Input,Output"
|
|
rgroup.long 0x08++0x03
|
|
line.long 0x00 "SYSPC3,SYS Pin Control Register 3"
|
|
bitfld.long 0x00 0. " ECPCLK_DIN ,ECPCLK data in" "Low,High"
|
|
sif (cpuis("TMS570LS09*")||cpuis("TMS570LS07*")||cpuis("TMS570LS0232")||cpuis("TMS570LS3137-EP"))
|
|
if ((((per.l.be(ad:0xFFFFFF00))&0x01)==0x00)&&(((per.l.be((ad:0xFFFFFF00+0x04)))&0x01)==0x01))
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "SYSPC4,SYS Pin Control Register 4"
|
|
bitfld.long 0x00 0. " ECPCLK_DOUT ,ECPCLK data out write" "Low,High"
|
|
else
|
|
hgroup.long 0x0C++0x03
|
|
hide.long 0x00 "SYSPC4,SYS Pin Control Register 4"
|
|
endif
|
|
if ((((per.l.be(ad:0xFFFFFF00))&0x01)==0x00)&&(((per.l.be((ad:0xFFFFFF00+0x04)))&0x01)==0x01))
|
|
group.long 0x10++0x07
|
|
line.long 0x00 "SYSPC5,SYS Pin Control Register 5"
|
|
bitfld.long 0x00 0. " ECPCLK_SET ,ECPCLK data out set" "Low,High"
|
|
line.long 0x04 "SYSPC6,SYS Pin Control Register 6"
|
|
bitfld.long 0x04 0. " ECPCLK_CLR ,ECPCLK data out clear" "Low,High"
|
|
else
|
|
hgroup.long 0x10++0x03
|
|
hide.long 0x0 "SYSPC5,SYS Pin Control Register 5"
|
|
hgroup.long 0x14++0x03
|
|
hide.long 0x0 "SYSPC6,SYS Pin Control Register 6"
|
|
endif
|
|
if (((per.l.be(ad:0xFFFFFF00))&0x01)==0x00)
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "SYSPC7,SYS Pin Control Register 7"
|
|
bitfld.long 0x00 0. " ECPCLK_ODE ,ECPCLK open drain enable" "Push/pull,Open drain"
|
|
else
|
|
hgroup.long 0x18++0x03
|
|
hide.long 0x00 "SYSPC7,SYS Pin Control Register 7"
|
|
endif
|
|
if ((((per.l.be(ad:0xFFFFFF00))&0x01)==0x00)&&(((per.l.be((ad:0xFFFFFF00+0x04)))&0x01)==0x00))
|
|
group.long 0x1C++0x07
|
|
line.long 0x00 "SYSPC8,SYS Pin Control Register 8"
|
|
bitfld.long 0x00 0. " ECPCLK_PUE ,ECPCLK pull up enable" "Active,Inactive"
|
|
line.long 0x04 "SYSPC9,SYS Pin Control Register 9"
|
|
bitfld.long 0x04 0. " ECPCLK_PS ,ECPCLK pull up/pull down select" "Down,Up"
|
|
else
|
|
hgroup.long 0x1C++0x03
|
|
hide.long 0x00 "SYSPC8,SYS Pin Control Register 8"
|
|
hgroup.long 0x20++0x03
|
|
hide.long 0x0 "SYSPC9,SYS Pin Control Register 9"
|
|
endif
|
|
else
|
|
if ((((per.l(ad:0xFFFFFF00))&0x01)==0x00)&&(((per.l((ad:0xFFFFFF00+0x04)))&0x01)==0x01))
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "SYSPC4,SYS Pin Control Register 4"
|
|
bitfld.long 0x00 0. " ECPCLK_DOUT ,ECPCLK data out write" "Low,High"
|
|
else
|
|
hgroup.long 0x0C++0x03
|
|
hide.long 0x00 "SYSPC4,SYS Pin Control Register 4"
|
|
endif
|
|
if ((((per.l(ad:0xFFFFFF00))&0x01)==0x00)&&(((per.l((ad:0xFFFFFF00+0x04)))&0x01)==0x01))
|
|
group.long 0x10++0x07
|
|
line.long 0x00 "SYSPC5,SYS Pin Control Register 5"
|
|
bitfld.long 0x00 0. " ECPCLK_SET ,ECPCLK data out set" "Low,High"
|
|
line.long 0x04 "SYSPC6,SYS Pin Control Register 6"
|
|
bitfld.long 0x04 0. " ECPCLK_CLR ,ECPCLK data out clear" "Low,High"
|
|
else
|
|
hgroup.long 0x10++0x03
|
|
hide.long 0x00 "SYSPC5,SYS Pin Control Register 5"
|
|
hgroup.long 0x14++0x03
|
|
hide.long 0x00 "SYSPC6,SYS Pin Control Register 6"
|
|
endif
|
|
if (((per.l(ad:0xFFFFFF00))&0x01)==0x00)
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "SYSPC7,SYS Pin Control Register 7"
|
|
bitfld.long 0x00 0. " ECPCLK_ODE ,ECPCLK open drain enable" "Push/pull,Open drain"
|
|
else
|
|
hgroup.long 0x18++0x03
|
|
hide.long 0x00 "SYSPC7,SYS Pin Control Register 7"
|
|
endif
|
|
if ((((per.l(ad:0xFFFFFF00))&0x01)==0x00)&&(((per.l((ad:0xFFFFFF00+0x04)))&0x01)==0x00))
|
|
group.long 0x1C++0x07
|
|
line.long 0x00 "SYSPC8,SYS Pin Control Register 8"
|
|
bitfld.long 0x00 0. " ECPCLK_PUE ,ECPCLK pull up enable" "Active,Inactive"
|
|
line.long 0x04 "SYSPC9,SYS Pin Control Register 9"
|
|
bitfld.long 0x04 0. " ECPCLK_PS ,ECPCLK pull up/pull down select" "Down,Up"
|
|
else
|
|
hgroup.long 0x1C++0x03
|
|
hide.long 0x0 "SYSPC8,SYS Pin Control Register 8"
|
|
hgroup.long 0x20++0x03
|
|
hide.long 0x0 "SYSPC9,SYS Pin Control Register 9"
|
|
endif
|
|
endif
|
|
tree.end
|
|
width 15.
|
|
tree "System Clock Source/Domain Disable Registers"
|
|
sif (cpuis("TMS570LS09*")||cpuis("TMS570LS07*")||cpuis("TMS570LS0232")||cpuis("TMS570LS3137-EP"))
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "CSDIS_SET/CLR,Clock Source Disable Set/Clear Register"
|
|
sif (cpuis("TMS570LS09*")||cpuis("TMS570LS07*")||cpuis("TMS570LS3137-EP"))
|
|
setclrfld.long 0x00 7. 0x04 7. 0x08 7. " CLKSR7_OFF ,Clock source 7 (EXTCLKIN2) disable" "No,Yes"
|
|
newline
|
|
endif
|
|
setclrfld.long 0x00 5. 0x04 5. 0x08 5. " CLKSR5_OFF ,Clock source 5 (High-frequency LPO (Low-power oscillator) clock) disable" "No,Yes"
|
|
setclrfld.long 0x00 4. 0x04 4. 0x08 4. " CLKSR4_OFF ,Clock source 4 (Low-frequency LPO (Low-power oscillator) clock) disable" "No,Yes"
|
|
setclrfld.long 0x00 3. 0x04 3. 0x08 3. " CLKSR3_OFF ,Clock source 3 (EXTCLKIN) disable" "No,Yes"
|
|
newline
|
|
setclrfld.long 0x00 1. 0x04 1. 0x08 1. " CLKSR1_OFF ,Clock source 1 (PLL1) disable" "No,Yes"
|
|
setclrfld.long 0x00 0. 0x04 0. 0x08 0. " CLKSR0_OFF ,Clock source 0 (Oscillator) disable" "No,Yes"
|
|
group.long 0x3C++0x03
|
|
line.long 0x00 "CDDIS_SET/CLR,Clock Domain Disable Set/Clear Register"
|
|
sif !cpuis("TMS570LS3137-EP")
|
|
setclrfld.long 0x00 9. 0x04 9. 0x08 9. " VCLK4OFF ,VCLK4 domain disable" "No,Yes"
|
|
newline
|
|
else
|
|
setclrfld.long 0x00 11. 0x04 11. 0x08 11. " VCLK4OFF ,VCLK4 domain disable" "No,Yes"
|
|
setclrfld.long 0x00 8. 0x04 8. 0x08 8. " VCLK3OFF ,VCLK3 domain disable" "No,Yes"
|
|
newline
|
|
endif
|
|
setclrfld.long 0x00 6. 0x4 6. 0x8 6. " RTICLK1OFF ,RTICLK1 domain disable" "No,Yes"
|
|
newline
|
|
sif cpuis("TMS570LS3137-EP")
|
|
setclrfld.long 0x00 5. 0x04 5. 0x08 5. " VCLKA2OFF ,VCLKA2 domain disable" "No,Yes"
|
|
newline
|
|
endif
|
|
setclrfld.long 0x00 4. 0x4 4. 0x8 4. " VCLKA1OFF ,VCLKA1 domain disable" "No,Yes"
|
|
setclrfld.long 0x00 3. 0x4 3. 0x8 3. " VCLK2OFF ,VCLK2 domain disable" "No,Yes"
|
|
newline
|
|
setclrfld.long 0x00 2. 0x4 2. 0x8 2. " VCLKPOFF ,VCLKP domain disable" "No,Yes"
|
|
setclrfld.long 0x00 1. 0x4 1. 0x8 1. " HCLKOFF ,HCLK domain disable" "No,Yes"
|
|
newline
|
|
setclrfld.long 0x00 0. 0x4 0. 0x8 0. " GCLKOFF ,GCLK domain disable" "No,Yes"
|
|
else
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "CSDIS_SET/CLR,Clock Source Disable Set/Clear Register"
|
|
setclrfld.long 0x00 6. 0x04 6. 0x08 6. " CLKSR6_OFF ,Clock source 6 (PLL2 (FPLL)) off" "Enabled,Disabled"
|
|
setclrfld.long 0x00 5. 0x04 5. 0x08 5. " CLKSR5_OFF ,Clock source 5 (LPO high frequency clock) off" "Enabled,Disabled"
|
|
setclrfld.long 0x00 4. 0x04 4. 0x08 4. " CLKSR4_OFF ,Clock source 4 (LPO low frequency clock) off" "Enabled,Disabled"
|
|
newline
|
|
setclrfld.long 0x00 1. 0x04 1. 0x08 1. " CLKSR1_OFF ,Clock source 1 (PLL1 (FMzPLL)) off" "Enabled,Disabled"
|
|
setclrfld.long 0x00 0. 0x04 0. 0x08 0. " CLKSR0_OFF ,Clock source 0 (Oscillator) off" "Enabled,Disabled"
|
|
group.long 0x3C++0x03
|
|
line.long 0x00 "CDDIS_SET/CLR,Clock Domain Disable Set/Clear Register"
|
|
setclrfld.long 0x00 6. 0x4 6. 0x8 6. " RTICLK1OFF ,RTICLK1 domain off" "Enabled,Disabled"
|
|
setclrfld.long 0x00 5. 0x4 5. 0x8 5. " VCLKA2OFF ,VCLKA2 domain off" "Enabled,Disabled"
|
|
setclrfld.long 0x00 4. 0x4 4. 0x8 4. " VCLKA1OFF ,VCLKA1 domain off" "Enabled,Disabled"
|
|
newline
|
|
setclrfld.long 0x00 3. 0x4 3. 0x8 3. " VCLK2OFF ,VCLK2 domain off" "Enabled,Disabled"
|
|
setclrfld.long 0x00 2. 0x4 2. 0x8 2. " VCLKPOFF ,VCLKP domain off" "Enabled,Disabled"
|
|
setclrfld.long 0x00 1. 0x4 1. 0x8 1. " HCLKOFF ,HCLK domain off" "Enabled,Disabled"
|
|
newline
|
|
setclrfld.long 0x00 0. 0x4 0. 0x8 0. " GCLKOFF ,GCLK domain off" "Enabled,Disabled"
|
|
endif
|
|
tree.end
|
|
newline
|
|
width 13.
|
|
group.long 0x48++0x0B
|
|
line.long 0x0 "GHVSRC,GCLK/HCLK/VCLK and VCLK2 Source Register"
|
|
sif (cpuis("TMS570LS09*")||cpuis("TMS570LS07*")||cpuis("TMS570LS3137-EP"))
|
|
bitfld.long 0x00 24.--27. " GHVWAKE ,GCLK/HCLK/VCLK/VCLK2 source on wakeup" "Source 0,Source 1,,Source 3,Source 4,Source 5,,Source 7,?..."
|
|
bitfld.long 0x00 16.--19. " HVLPM ,HCLK/VCLK/VCLK2 source on wakeup (GCLK turned off)" "Source 0,Source 1,,Source 3,Source 4,Source 5,,Source 7,?..."
|
|
bitfld.long 0x00 0.--3. " GHVSRC ,GCLK/HCLK/VCLK/VCLK2 current source" "Source 0,Source 1,,Source 3,Source 4,Source 5,,Source 7,?..."
|
|
elif cpuis("TMS570LS0232")
|
|
bitfld.long 0x00 24.--27. " GHVWAKE ,GCLK/HCLK/VCLK/VCLK2 source on wakeup" "Source 0,Source 1,,Source 3,Source 4,Source 5,?..."
|
|
bitfld.long 0x00 16.--19. " HVLPM ,HCLK/VCLK/VCLK2 source on wakeup (GCLK turned off)" "Source 0,Source 1,,Source 3,Source 4,Source 5,?..."
|
|
bitfld.long 0x00 0.--3. " GHVSRC ,GCLK/HCLK/VCLK/VCLK2 current source" "Source 0,Source 1,,Source 3,Source 4,Source 5,?..."
|
|
else
|
|
bitfld.long 0x00 24.--27. " GHVWAKE ,GCLK/HCLK/VCLK/VCLK2 source on wakeup" "Source 0,Source 1,Source 2,Source 3,Source 4,Source 5,Source 6,Source 7,?..."
|
|
bitfld.long 0x00 16.--19. " HVLPM ,HCLK/VCLK/VCLK2 source on wakeup (GCLK turned off)" "Source 0,Source 1,Source 2,Source 3,Source 4,Source 5,Source 6,Source 7,?..."
|
|
bitfld.long 0x00 0.--3. " GHVSRC ,GCLK/HCLK/VCLK/VCLK2 current source" "Source 0,Source 1,Source 2,Source 3,Source 4,Source 5,Source 6,Source 7,?..."
|
|
endif
|
|
line.long 0x04 "VCLKASRC,Peripheral Asynchronous Clock Source Register"
|
|
sif (cpuis("TMS570LS09*")||cpuis("TMS570LS07*"))
|
|
bitfld.long 0x04 0.--3. " VCLKA1S ,Peripheral asynchronous clock 1 source" "Source 0,Source 1,,Source 3,Source 4,Source 5,,Source 7,VCLK,VCLK,VCLK,VCLK,VCLK,VCLK,VCLK,VCLK"
|
|
elif cpuis("TMS570LS0232")
|
|
bitfld.long 0x04 0.--3. " VCLKA1S ,Peripheral asynchronous clock 1 source" "Source 0,Source 1,,Source 3,Source 4,Source 5,,,VCLK,VCLK,VCLK,VCLK,VCLK,VCLK,VCLK,VCLK"
|
|
else
|
|
bitfld.long 0x04 8.--11. " VCLKA2S ,Peripheral asynchronous clock 2 source" "Source 0,Source 1,Source 2,Source 3,Source 4,Source 5,Source 6,Source 7,VCLK,VCLK,VCLK,VCLK,VCLK,VCLK,VCLK,VCLK"
|
|
bitfld.long 0x04 0.--3. " VCLKA1S ,Peripheral asynchronous clock 1 source" "Source 0,Source 1,Source 2,Source 3,Source 4,Source 5,Source 6,Source 7,VCLK,VCLK,VCLK,VCLK,VCLK,VCLK,VCLK,VCLK"
|
|
endif
|
|
line.long 0x08 "RCLKSRC,RTI Clock Source Register"
|
|
sif (cpuis("TMS570LS09*")||cpuis("TMS570LS07*"))
|
|
bitfld.long 0x08 8.--9. " RTI1DIV ,RTI clock 1 divider" "RTICLK1,RTICLK1/2,RTICLK1/4,RTICLK1/8"
|
|
bitfld.long 0x08 0.--3. " RTI1SRC ,RTI clock 1 source" "Source 0,Source 1,,Source 3,Source 4,Source 5,,Source 7,VCLK,VCLK,VCLK,VCLK,VCLK,VCLK,VCLK,VCLK"
|
|
elif cpuis("TMS570LS0232")
|
|
bitfld.long 0x08 8.--9. " RTI1DIV ,RTI clock 1 divider" "RTICLK1,RTICLK1/2,RTICLK1/4,RTICLK1/8"
|
|
bitfld.long 0x08 0.--3. " RTI1SRC ,RTI clock 1 source" "Source 0,Source 1,,Source 3,Source 4,Source 5,,,VCLK,VCLK,VCLK,VCLK,VCLK,VCLK,VCLK,VCLK"
|
|
else
|
|
bitfld.long 0x08 8.--9. " RTI1DIV ,RTI clock 1 divider" "RTICLK1,RTICLK1/2,RTICLK1/4,RTICLK1/8"
|
|
bitfld.long 0x08 0.--3. " RTI1SRC ,RTI clock 1 source" "Source 0,Source 1,Source 2,Source 3,Source 4,Source 5,Source 6,Source 7,VCLK,VCLK,VCLK,VCLK,VCLK,VCLK,VCLK,VCLK"
|
|
endif
|
|
rgroup.long 0x54++0x03
|
|
line.long 0x0 "CSVSTAT,Clock Source Valid Status Register"
|
|
sif (cpuis("TMS570LS09*")||cpuis("TMS570LS07*")||cpuis("TMS570LS3137-EP"))
|
|
bitfld.long 0x00 7. " CLKSR7V ,Clock source 7 valid" "Not valid,Valid"
|
|
bitfld.long 0x00 5. " CLKSR5V ,Clock source 5 valid" "Not valid,Valid"
|
|
bitfld.long 0x00 4. " CLKSR4V ,Clock source 4 valid" "Not valid,Valid"
|
|
newline
|
|
bitfld.long 0x00 3. " CLKSR3V ,Clock source 3 valid" "Not valid,Valid"
|
|
bitfld.long 0x00 1. " CLKSR1V ,Clock source 1 valid" "Not valid,Valid"
|
|
bitfld.long 0x00 0. " CLKSR0V ,Clock source 0 valid" "Not valid,Valid"
|
|
elif cpuis("TMS570LS0232")
|
|
bitfld.long 0x00 5. " CLKSR5V ,Clock source 5 valid" "Not valid,Valid"
|
|
bitfld.long 0x00 4. " CLKSR4V ,Clock source 4 valid" "Not valid,Valid"
|
|
bitfld.long 0x00 3. " CLKSR3V ,Clock source 3 valid" "Not valid,Valid"
|
|
newline
|
|
bitfld.long 0x00 1. " CLKSR1V ,Clock source 1 valid" "Not valid,Valid"
|
|
bitfld.long 0x00 0. " CLKSR0V ,Clock source 0 valid" "Not valid,Valid"
|
|
else
|
|
bitfld.long 0x00 7. " CLKSR7V ,Clock source 7 valid" "Not valid,Valid"
|
|
bitfld.long 0x00 6. " CLKSR6V ,Clock source 6 valid" "Not valid,Valid"
|
|
bitfld.long 0x00 5. " CLKSR5V ,Clock source 5 valid" "Not valid,Valid"
|
|
newline
|
|
bitfld.long 0x00 4. " CLKSR4V ,Clock source 4 valid" "Not valid,Valid"
|
|
bitfld.long 0x00 3. " CLKSR3V ,Clock source 3 valid" "Not valid,Valid"
|
|
bitfld.long 0x00 2. " CLKSR2V ,Clock source 2 valid" "Not valid,Valid"
|
|
newline
|
|
bitfld.long 0x00 1. " CLKSR1V ,Clock source 1 valid" "Not valid,Valid"
|
|
bitfld.long 0x00 0. " CLKSR0V ,Clock source 0 valid" "Not valid,Valid"
|
|
endif
|
|
group.long 0x58++0x0B
|
|
line.long 0x0 "MSTGCR,Memory Self-Test Global Control Register"
|
|
sif (!cpuis("TMS570LS0232"))
|
|
hexmask.long.byte 0x00 16.--23. 1. " MBIST_ALGSEL ,Selects different algorithm for MBIST"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 8.--9. " ROM_DIV ,ROM clock source prescaler divider" "HCLK,HCLK/2,HCLK/4,HCLK/8"
|
|
bitfld.long 0x00 0.--3. " MSTGENA ,Memory self-test controller global enable key" "Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Enabled,Disabled,Disabled,Disabled,Disabled,Disabled"
|
|
newline
|
|
line.long 0x04 "MINITGCR,Memory Hardware Initialization Global Control Register"
|
|
bitfld.long 0x04 0.--3. " MINITGENA ,Memory hardware initialization global enable key" "Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Enabled,Disabled,Disabled,Disabled,Disabled,Disabled"
|
|
line.long 0x08 "MSINENA,MBIST Controller/Memory Initialization Enable Register"
|
|
bitfld.long 0x08 31. " MSIENA[31] ,MBIST controller/memory initialization enable 31" "Disabled,Enabled"
|
|
bitfld.long 0x08 30. " [30] ,MBIST controller/memory initialization enable 30" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x08 29. " [29] ,MBIST controller/memory initialization enable 29" "Disabled,Enabled"
|
|
bitfld.long 0x08 28. " [28] ,MBIST controller/memory initialization enable 28" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x08 27. " [27] ,MBIST controller/memory initialization enable 27" "Disabled,Enabled"
|
|
bitfld.long 0x08 26. " [26] ,MBIST controller/memory initialization enable 26" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x08 25. " [25] ,MBIST controller/memory initialization enable 25" "Disabled,Enabled"
|
|
bitfld.long 0x08 24. " [24] ,MBIST controller/memory initialization enable 24" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x08 23. " [23] ,MBIST controller/memory initialization enable 23" "Disabled,Enabled"
|
|
bitfld.long 0x08 22. " [22] ,MBIST controller/memory initialization enable 22" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x08 21. " [21] ,MBIST controller/memory initialization enable 21" "Disabled,Enabled"
|
|
bitfld.long 0x08 20. " [20] ,MBIST controller/memory initialization enable 20" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x08 19. " [19] ,MBIST controller/memory initialization enable 19" "Disabled,Enabled"
|
|
bitfld.long 0x08 18. " [18] ,MBIST controller/memory initialization enable 18" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x08 17. " [17] ,MBIST controller/memory initialization enable 17" "Disabled,Enabled"
|
|
bitfld.long 0x08 16. " [16] ,MBIST controller/memory initialization enable 16" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x08 15. " [15] ,MBIST controller/memory initialization enable 15" "Disabled,Enabled"
|
|
bitfld.long 0x08 14. " [14] ,MBIST controller/memory initialization enable 14" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x08 13. " [13] ,MBIST controller/memory initialization enable 13" "Disabled,Enabled"
|
|
bitfld.long 0x08 12. " [12] ,MBIST controller/memory initialization enable 12" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x08 11. " [11] ,MBIST controller/memory initialization enable 11" "Disabled,Enabled"
|
|
bitfld.long 0x08 10. " [10] ,MBIST controller/memory initialization enable 10" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x08 9. " [9] ,MBIST controller/memory initialization enable 9" "Disabled,Enabled"
|
|
bitfld.long 0x08 8. " [8] ,MBIST controller/memory initialization enable 8" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x08 7. " [7] ,MBIST controller/memory initialization enable 7" "Disabled,Enabled"
|
|
bitfld.long 0x08 6. " [6] ,MBIST controller/memory initialization enable 6" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x08 5. " [5] ,MBIST controller/memory initialization enable 5" "Disabled,Enabled"
|
|
bitfld.long 0x08 4. " [4] ,MBIST controller/memory initialization enable 4" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x08 3. " [3] ,MBIST controller/memory initialization enable 3" "Disabled,Enabled"
|
|
bitfld.long 0x08 2. " [2] ,MBIST controller/memory initialization enable 2" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x08 1. " [1] ,MBIST controller/memory initialization enable 1" "Disabled,Enabled"
|
|
bitfld.long 0x08 0. " [0] ,MBIST controller/memory initialization enable 0" "Disabled,Enabled"
|
|
sif (cpuis("TMS570LS09*")||cpuis("TMS570LS07*")||cpuis("TMS570LS0232"))
|
|
group.long 0x64++0x03
|
|
line.long 0x00 "MSTFAIL,Memory Self-Test Fail Status Register"
|
|
bitfld.long 0x00 31. " MSTF[31] ,Memory self-test fail status 31 bit" "Not failed,Failed"
|
|
bitfld.long 0x00 30. " [30] ,Memory self-test fail status 30 bit" "Not failed,Failed"
|
|
newline
|
|
bitfld.long 0x00 29. " [29] ,Memory self-test fail status 29 bit" "Not failed,Failed"
|
|
bitfld.long 0x00 28. " [28] ,Memory self-test fail status 28 bit" "Not failed,Failed"
|
|
newline
|
|
bitfld.long 0x00 27. " [27] ,Memory self-test fail status 27 bit" "Not failed,Failed"
|
|
bitfld.long 0x00 26. " [26] ,Memory self-test fail status 26 bit" "Not failed,Failed"
|
|
newline
|
|
bitfld.long 0x00 25. " [25] ,Memory self-test fail status 25 bit" "Not failed,Failed"
|
|
bitfld.long 0x00 24. " [24] ,Memory self-test fail status 24 bit" "Not failed,Failed"
|
|
newline
|
|
bitfld.long 0x00 23. " [23] ,Memory self-test fail status 23 bit" "Not failed,Failed"
|
|
bitfld.long 0x00 22. " [22] ,Memory self-test fail status 22 bit" "Not failed,Failed"
|
|
newline
|
|
bitfld.long 0x00 21. " [21] ,Memory self-test fail status 21 bit" "Not failed,Failed"
|
|
bitfld.long 0x00 20. " [20] ,Memory self-test fail status 20 bit" "Not failed,Failed"
|
|
newline
|
|
bitfld.long 0x00 19. " [19] ,Memory self-test fail status 19 bit" "Not failed,Failed"
|
|
bitfld.long 0x00 18. " [18] ,Memory self-test fail status 18 bit" "Not failed,Failed"
|
|
newline
|
|
bitfld.long 0x00 17. " [17] ,Memory self-test fail status 17 bit" "Not failed,Failed"
|
|
bitfld.long 0x00 16. " [16] ,Memory self-test fail status 16 bit" "Not failed,Failed"
|
|
newline
|
|
bitfld.long 0x00 15. " [15] ,Memory self-test fail status 15 bit" "Not failed,Failed"
|
|
bitfld.long 0x00 14. " [14] ,Memory self-test fail status 14 bit" "Not failed,Failed"
|
|
newline
|
|
bitfld.long 0x00 13. " [13] ,Memory self-test fail status 13 bit" "Not failed,Failed"
|
|
bitfld.long 0x00 12. " [12] ,Memory self-test fail status 12 bit" "Not failed,Failed"
|
|
newline
|
|
bitfld.long 0x00 11. " [11] ,Memory self-test fail status 11 bit" "Not failed,Failed"
|
|
bitfld.long 0x00 10. " [10] ,Memory self-test fail status 10 bit" "Not failed,Failed"
|
|
newline
|
|
bitfld.long 0x00 9. " [9] ,Memory self-test fail status 9 bit" "Not failed,Failed"
|
|
bitfld.long 0x00 8. " [8] ,Memory self-test fail status 8 bit" "Not failed,Failed"
|
|
newline
|
|
bitfld.long 0x00 7. " [7] ,Memory self-test fail status 7 bit" "Not failed,Failed"
|
|
bitfld.long 0x00 6. " [6] ,Memory self-test fail status 6 bit" "Not failed,Failed"
|
|
newline
|
|
bitfld.long 0x00 5. " [5] ,Memory self-test fail status 5 bit" "Not failed,Failed"
|
|
bitfld.long 0x00 4. " [4] ,Memory self-test fail status 4 bit" "Not failed,Failed"
|
|
newline
|
|
bitfld.long 0x00 3. " [3] ,Memory self-test fail status 3 bit" "Not failed,Failed"
|
|
bitfld.long 0x00 2. " [2] ,Memory self-test fail status 2 bit" "Not failed,Failed"
|
|
newline
|
|
bitfld.long 0x00 1. " [1] ,Memory self-test fail status 1 bit" "Not failed,Failed"
|
|
bitfld.long 0x00 0. " [0] ,Memory self-test fail status 0 bit" "Not failed,Failed"
|
|
endif
|
|
group.long 0x68++0x0F
|
|
line.long 0x00 "MSTCGSTAT,MSTC Global Status Register"
|
|
sif (cpuis("TMS570LS09*")||cpuis("TMS570LS07*")||cpuis("TMS570LS0232")||cpuis("TMS570LS3137-EP"))
|
|
eventfld.long 0x00 8. " MINIDONE ,Memory hardware initialization test run complete status" "Not completed,Completed"
|
|
newline
|
|
else
|
|
bitfld.long 0x00 8. " MINIDONE ,Memory hardware initialization test run complete status" "Not completed,Completed"
|
|
newline
|
|
endif
|
|
eventfld.long 0x00 0. " MSTDONE ,Memory self-test run complete status" "Not completed,Completed"
|
|
line.long 0x04 "MINISTAT,Memory Hardware Initialization Status Register"
|
|
eventfld.long 0x04 31. " MIDONE[31] ,Memory hardware initialization status 31" "Not completed,Completed"
|
|
eventfld.long 0x04 30. " [30] ,Memory hardware initialization status 30" "Not completed,Completed"
|
|
newline
|
|
eventfld.long 0x04 29. " [29] ,Memory hardware initialization status 29" "Not completed,Completed"
|
|
eventfld.long 0x04 28. " [28] ,Memory hardware initialization status 28" "Not completed,Completed"
|
|
newline
|
|
eventfld.long 0x04 27. " [27] ,Memory hardware initialization status 27" "Not completed,Completed"
|
|
eventfld.long 0x04 26. " [26] ,Memory hardware initialization status 26" "Not completed,Completed"
|
|
newline
|
|
eventfld.long 0x04 25. " [25] ,Memory hardware initialization status 25" "Not completed,Completed"
|
|
eventfld.long 0x04 24. " [24] ,Memory hardware initialization status 24" "Not completed,Completed"
|
|
newline
|
|
eventfld.long 0x04 23. " [23] ,Memory hardware initialization status 23" "Not completed,Completed"
|
|
eventfld.long 0x04 22. " [22] ,Memory hardware initialization status 22" "Not completed,Completed"
|
|
newline
|
|
eventfld.long 0x04 21. " [21] ,Memory hardware initialization status 21" "Not completed,Completed"
|
|
eventfld.long 0x04 20. " [20] ,Memory hardware initialization status 20" "Not completed,Completed"
|
|
newline
|
|
eventfld.long 0x04 19. " [19] ,Memory hardware initialization status 19" "Not completed,Completed"
|
|
eventfld.long 0x04 18. " [18] ,Memory hardware initialization status 18" "Not completed,Completed"
|
|
newline
|
|
eventfld.long 0x04 17. " [17] ,Memory hardware initialization status 17" "Not completed,Completed"
|
|
eventfld.long 0x04 16. " [16] ,Memory hardware initialization status 16" "Not completed,Completed"
|
|
newline
|
|
eventfld.long 0x04 15. " [15] ,Memory hardware initialization status 15" "Not completed,Completed"
|
|
eventfld.long 0x04 14. " [14] ,Memory hardware initialization status 14" "Not completed,Completed"
|
|
newline
|
|
eventfld.long 0x04 13. " [13] ,Memory hardware initialization status 13" "Not completed,Completed"
|
|
eventfld.long 0x04 12. " [12] ,Memory hardware initialization status 12" "Not completed,Completed"
|
|
newline
|
|
eventfld.long 0x04 11. " [11] ,Memory hardware initialization status 11" "Not completed,Completed"
|
|
eventfld.long 0x04 10. " [10] ,Memory hardware initialization status 10" "Not completed,Completed"
|
|
newline
|
|
eventfld.long 0x04 9. " [9] ,Memory hardware initialization status 9" "Not completed,Completed"
|
|
eventfld.long 0x04 8. " [8] ,Memory hardware initialization status 8" "Not completed,Completed"
|
|
newline
|
|
eventfld.long 0x04 7. " [7] ,Memory hardware initialization status 7" "Not completed,Completed"
|
|
eventfld.long 0x04 6. " [6] ,Memory hardware initialization status 6" "Not completed,Completed"
|
|
newline
|
|
eventfld.long 0x04 5. " [5] ,Memory hardware initialization status 5" "Not completed,Completed"
|
|
eventfld.long 0x04 4. " [4] ,Memory hardware initialization status 4" "Not completed,Completed"
|
|
newline
|
|
eventfld.long 0x04 3. " [3] ,Memory hardware initialization status 3" "Not completed,Completed"
|
|
eventfld.long 0x04 2. " [2] ,Memory hardware initialization status 2" "Not completed,Completed"
|
|
newline
|
|
eventfld.long 0x04 1. " [1] ,Memory hardware initialization status 1" "Not completed,Completed"
|
|
eventfld.long 0x04 0. " [0] ,Memory hardware initialization status 0" "Not completed,Completed"
|
|
newline
|
|
line.long 0x08 "PLLCTL1,PLL Control Register 1"
|
|
bitfld.long 0x08 31. " ROS ,Reset on PLL cycle slip" "No reset,Reset"
|
|
newline
|
|
sif (cpuis("TMS570LS09*")||cpuis("TMS570LS07*")||cpuis("TMS570LS0232")||cpuis("TMS570LS3137-EP"))
|
|
bitfld.long 0x08 29.--30. " MASK_SLIP ,Mask detection of PLL slip" "Enabled,Enabled,Disabled,Enabled"
|
|
newline
|
|
else
|
|
bitfld.long 0x08 29.--30. " BPOS ,Bypass on PLL Slip" "Enabled,Enabled,Disabled,Enabled"
|
|
newline
|
|
endif
|
|
bitfld.long 0x08 24.--28. " PLLDIV ,PLL output clock divider" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32"
|
|
bitfld.long 0x08 23. " ROF ,Reset on oscillator fail" "No reset,Reset"
|
|
newline
|
|
bitfld.long 0x08 16.--21. " REFCLKDIV ,Reference clock divider" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64"
|
|
hexmask.long.word 0x08 0.--15. 1. " PLLMUL ,PLL multiplication factor"
|
|
line.long 0x0C "PLLCTL2,PLL Control Register 2"
|
|
bitfld.long 0x0C 31. " FMENA ,Frequency modulation enable" "Disabled,Enabled"
|
|
hexmask.long.word 0x0C 22.--30. 1. " SPREADINGRATE ,Spreadingrate"
|
|
newline
|
|
sif (cpuis("TMS570LS09*")||cpuis("TMS570LS07*")||cpuis("TMS570LS0232")||cpuis("TMS570LS3137-EP"))
|
|
hexmask.long.word 0x0C 12.--20. 1. " MULMOD ,Multiplier correction when frequency modulation is enabled"
|
|
newline
|
|
else
|
|
hexmask.long.word 0x0C 12.--20. 1. " BWADJ ,Bandwidth adjustment"
|
|
newline
|
|
endif
|
|
bitfld.long 0x0C 9.--11. " ODPLL ,Internal PLL output divider" "/1,/2,/3,/4,/5,/6,/7,/8"
|
|
hexmask.long.word 0x0C 0.--8. 1. " SPR_AMOUNT ,Spreading amount"
|
|
sif (cpuis("TMS570LS09*")||cpuis("TMS570LS07*")||cpuis("TMS570LS0232")||cpuis("TMS570LS3137-EP"))
|
|
group.long 0x78++0x03
|
|
line.long 0x00 "SYSPC10,SYS Pin Control Register 10"
|
|
bitfld.long 0x00 0. " ECLK_SLEW ,ECLK slew control" "Fast mode,Slow mode"
|
|
endif
|
|
rgroup.long 0x7C++0x07
|
|
line.long 0x00 "DIEIDL,Die Identification Register Lower Word"
|
|
sif (!cpuis("TMS570LS09*")&&!cpuis("TMS570LS07*")&&!cpuis("TMS570LS0232"))
|
|
hexmask.long.word 0x00 22.--31. 1. " LOT# ,Lower 10 Bits"
|
|
hexmask.long.byte 0x00 16.--21. 1. " WAFER# ,Wafer number"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. " Y_WAFER_COORDINATE ,Y Wafer coordinate"
|
|
hexmask.long.byte 0x00 0.--7. 1. " X_WAFER_COORDINATE ,X Wafer coordinate"
|
|
else
|
|
hexmask.long.byte 0x00 24.--31. 1. " WAFER# ,Wafer number"
|
|
hexmask.long.word 0x00 12.--23. 1. " Y_WAFER_COORDINATE ,Y Wafer coordinate"
|
|
newline
|
|
hexmask.long.word 0x00 0.--11. 1. " X_WAFER_COORDINATE ,X Wafer coordinate"
|
|
endif
|
|
line.long 0x04 "DIEIDH,Die Identification Register Upper Word"
|
|
sif (!cpuis("TMS570LS09*")&&!cpuis("TMS570LS07*")&&!cpuis("TMS570LS0232"))
|
|
hexmask.long.word 0x04 0.--13. 1. " LOT# ,Upper 10 Bits"
|
|
newline
|
|
else
|
|
hexmask.long.tbyte 0x04 0.--23. 1. " LOT# ,Device lot number"
|
|
endif
|
|
newline
|
|
group.long 0x88++0x07
|
|
line.long 0x0 "LPOMONCTL,LPO/Clock Monitor Control Register"
|
|
bitfld.long 0x00 24. " BIAS_ENABLE ,Bias enable" "Disabled,Enabled"
|
|
sif (cpuis("TMS570LS09*")||cpuis("TMS570LS07*")||cpuis("TMS570LS0232")||cpuis("TMS570LS3137-EP"))
|
|
newline
|
|
rbitfld.long 0x00 16. " OSCFRQCONFIGCNT ,Configures the counter based on OSC frequency" "Freq<=20MHz,Freq>20MHz&&<=80MHz"
|
|
endif
|
|
sif (cpuis("TMS570LS09*")||cpuis("TMS570LS07*")||cpuis("TMS570LS0232"))
|
|
newline
|
|
bitfld.long 0x00 8.--12. " HFTRIM ,High frequency oscillator trim value" "29.52%,34.24%,38.85%,43.45%,47.99%,52.55%,57.02%,61.46%,65.92%,70.17%,74.55%,78.92%,83.17%,87.43%,91.75%,95.89%,100%,104.09%,108.17%,112.32%,116.41%,120.67%,124.42%,128.38%,132.24%,136.15%,140.15%,143.94%,148.02%,151.80%,155.50%,159.35%"
|
|
bitfld.long 0x00 0.--4. " LFTRIM ,Low frequency oscillator trim value" "20.67%,25.76%,30.84%,35.90%,40.93%,45.95%,50.97%,55.91%,60.86%,65.78%,70.75%,75.63%,80.61%,85.39%,90.23%,95.11%,100%,104.84%,109.51%,114.31%,119.01%,123.75%,128.62%,133.31%,138.03%,142.75%,147.32%,152.02%,156.63%,161.38%,165.90%,170.42%"
|
|
elif cpuis("TMS570LS3137-EP")
|
|
newline
|
|
bitfld.long 0x00 8.--12. " HFTRIM ,High frequency oscillator trim value" "29.52,34.24,38.85,43.45,47.99,52.55,57.02,61.46,65.92,70.17,74.55,78.92,83.17,87.43,91.75,95.89,100.00,104.09,108.17,112.32,116.41,120.67,124.42,128.38,132.24,136.15,140.15,143.94,148.02,151.80,155.50,159.35"
|
|
bitfld.long 0x00 0.--4. " LFTRIM ,Low frequency oscillator trim value" "20.67,25.76,30.84,35.90,40.93,45.95,50.97,55.91,60.86,65.78,70.75,75.63,80.61,85.39,90.23,95.11,100.00,104.84,109.51,114.31,119.01,123.75,128.62,133.31,138.03,142.75,147.32,152.02,156.63,161.38,165.90,170.42"
|
|
else
|
|
newline
|
|
bitfld.long 0x00 8.--11. " HFTRIM ,High frequency oscillator trim value" "50 %,56.25 %,62.5 %,68.75 %,75 %,81.25 %,87.5 %,,100 %,106.25 %,112.5 %,118.75 %,125 %,131.25%,137.5 %,143.75 %"
|
|
bitfld.long 0x00 0.--3. " LFTRIM ,Low frequency oscillator trim value" "50 %,56.25 %,62.5 %,68.75 %,75 %,81.25 %,87.5 %,,100 %,106.25 %,112.5 %,118.75 %,125 %,131.25%,137.5 %,143.75 %"
|
|
endif
|
|
line.long 0x04 "CLKTEST,Clock Test Register"
|
|
bitfld.long 0x04 26. " ALTLIMPCLOCKENABLE ,Alternate limp clock enable" "10-MHz LPO,ALTLIMPCLOCK"
|
|
bitfld.long 0x04 25. " RANGEDETCTRL ,Range detection control" "Disabled,Enabled"
|
|
newline
|
|
sif (cpuis("TMS570LS0232"))
|
|
bitfld.long 0x04 24. " RANGEDETENABLE ,Range detection enable select" "Hardware,CLKTEST[RANGEDETCTRL]"
|
|
newline
|
|
else
|
|
bitfld.long 0x04 24. " RANGEDETENSSEL ,Range detection enable select" "Hardware,CLKTEST[RANGEDETCTRL]"
|
|
newline
|
|
endif
|
|
bitfld.long 0x04 16.--19. " CLK_TEST_EN ,Clock test enable" "Disabled,Disabled,Disabled,Disabled,Disabled,Enabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled"
|
|
sif cpuis("TMS570LS0232")
|
|
newline
|
|
bitfld.long 0x04 8.--11. " SEL_N2HET_PIN ,N2HET[2] pin clock source valid, clock source select" "Oscillator,PLL1,,,,High-frequency LPO,,,Low-frequency LPO,Oscillator,Oscillator,Oscillator,Oscillator,,,Oscillator"
|
|
bitfld.long 0x04 0.--4. " SEL_ECP_PIN ,ECLK pin clock source select" "Oscillator,PLL,,EXTCLKIN1,Low-frequency LPO,High-frequency LPO,,EXTCLKIN2,GCLK,RTI Base,,VCLKA1,,,,,,HCLK1,VCLK1,VCLK2,,VCLK4,?..."
|
|
elif cpuis("TMS570LS09*")||cpuis("TMS570LS07*")||cpuis("TMS570LS3137-EP")
|
|
newline
|
|
bitfld.long 0x04 8.--11. " SEL_GIO_PIN ,GIOB[0] pin clock source valid, clock source select" "Oscillator,PLL1,,,,High-frequency LPO,,,Low-frequency LPO,Oscillator,Oscillator,Oscillator,Oscillator,Oscillator,Oscillator,Oscillator"
|
|
newline
|
|
sif cpuis("TMS570LS3137-EP")
|
|
bitfld.long 0x04 0.--3. " SEL_ECP_PIN ,ECLK pin clock source select" "Oscillator,PLL1,,EXTCLKIN1,LFLPO,HFLPO,PLL2,EXTCLKIN2,GCLK,RTI,,VCLKA1,VCLKA2,,VCLKA4,?..."
|
|
newline
|
|
else
|
|
bitfld.long 0x04 0.--3. " SEL_ECP_PIN ,ECLK pin clock source select" "Oscillator,PLL,,,Low-frequency LPO,High-frequency LPO,,,GCLK,RTI Base,,VCLKA1,,,,Flash HD Pump Oscillator"
|
|
newline
|
|
endif
|
|
else
|
|
bitfld.long 0x04 0.--3. " SEL_ECP_PIN ,Clock at ECP pin select" "Oscillator,PLL,Not Implemented,External,LPO low,LPO high,Not Implemented,Not Implemented,GCLKMCLK,RTICLK1SRC,Not Implemented,VCLK1,VCLK2,?..."
|
|
endif
|
|
newline
|
|
sif cpuis("TMS570LS0232")||cpuis("TMS570LS3137-EP")
|
|
group.long 0x90++0x07
|
|
line.long 0x00 "DFTCTRLREG,DFT Control Register"
|
|
bitfld.long 0x00 12.--13. 8.--9. " DFTWRITE/DFTREAD ,DFT logic access" "Stress mode,,,,,Slow mode,,,,,Fast mode,,,,,Screen mode"
|
|
bitfld.long 0x00 0.--3. " TEST_MODE_KEY ,Test mode key" "Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Enabled,Disabled,Disabled,Disabled,Disabled,Disabled"
|
|
newline
|
|
line.long 0x04 "DFTCTRLREG2,DFT Control Register 2"
|
|
bitfld.long 0x04 31. " IMPDF[27] ,DFT Implementation defined bit 27" "Disabled,Enabled"
|
|
bitfld.long 0x04 30. " [26] ,DFT Implementation defined bit 26" "Disabled,Enabled"
|
|
bitfld.long 0x04 29. " [25] ,DFT Implementation defined bit 25" "Disabled,Enabled"
|
|
bitfld.long 0x04 28. " [24] ,DFT Implementation defined bit 24" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x04 27. " [23] ,DFT Implementation defined bit 23" "Disabled,Enabled"
|
|
bitfld.long 0x04 26. " [22] ,DFT Implementation defined bit 22" "Disabled,Enabled"
|
|
bitfld.long 0x04 25. " [21] ,DFT Implementation defined bit 21" "Disabled,Enabled"
|
|
bitfld.long 0x04 24. " [20] ,DFT Implementation defined bit 20" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x04 23. " [19] ,DFT Implementation defined bit 19" "Disabled,Enabled"
|
|
bitfld.long 0x04 22. " [18] ,DFT Implementation defined bit 18" "Disabled,Enabled"
|
|
bitfld.long 0x04 21. " [17] ,DFT Implementation defined bit 17" "Disabled,Enabled"
|
|
bitfld.long 0x04 20. " [16] ,DFT Implementation defined bit 16" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x04 19. " [15] ,DFT Implementation defined bit 15" "Disabled,Enabled"
|
|
bitfld.long 0x04 18. " [14] ,DFT Implementation defined bit 14" "Disabled,Enabled"
|
|
bitfld.long 0x04 17. " [13] ,DFT Implementation defined bit 13" "Disabled,Enabled"
|
|
bitfld.long 0x04 16. " [12] ,DFT Implementation defined bit 12" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x04 15. " [11] ,DFT Implementation defined bit 11" "Disabled,Enabled"
|
|
bitfld.long 0x04 14. " [10] ,DFT Implementation defined bit 10" "Disabled,Enabled"
|
|
bitfld.long 0x04 13. " [9] ,DFT Implementation defined bit 9" "Disabled,Enabled"
|
|
bitfld.long 0x04 12. " [8] ,DFT Implementation defined bit 8" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x04 11. " [7] ,DFT Implementation defined bit 7" "Disabled,Enabled"
|
|
bitfld.long 0x04 10. " [6] ,DFT Implementation defined bit 6" "Disabled,Enabled"
|
|
bitfld.long 0x04 9. " [5] ,DFT Implementation defined bit 5" "Disabled,Enabled"
|
|
bitfld.long 0x04 8. " [4] ,DFT Implementation defined bit 4" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x04 7. " [3] ,DFT Implementation defined bit 3" "Disabled,Enabled"
|
|
bitfld.long 0x04 6. " [2] ,DFT Implementation defined bit 2" "Disabled,Enabled"
|
|
bitfld.long 0x04 5. " [1] ,DFT Implementation defined bit 1" "Disabled,Enabled"
|
|
bitfld.long 0x04 4. " [0] ,DFT Implementation defined bit 0" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x04 0.--3. " TEST_MODE_KEY ,Test mode key" "Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Enabled,Disabled,Disabled,Disabled,Disabled,Disabled"
|
|
endif
|
|
newline
|
|
sif (cpuis("TMS570LS09*")||cpuis("TMS570LS07*")||cpuis("TMS570LS0232")||cpuis("TMS570LS3137-EP"))
|
|
group.long 0xA0++0x03
|
|
line.long 0x00 "GPREG1,General Purpose Register"
|
|
sif cpuis("TMS570LS3137-EP")
|
|
bitfld.long 0x00 31. " EMIF_FUNC , Enable EMIF functions to be output" "Disabled,Enabled"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 20.--25. " PLL1_FBSLIP_FILTER_COUNT ,FBSLIP down counter programmed value" "Disabled,Every slip recognized,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x00 16.--19. " PLL1_FBSLIP_FILTER_KEY ,Enable the FBSLIP filtering" "Enabled,Enabled,Enabled,Enabled,Enabled,Disabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,?..."
|
|
newline
|
|
sif !cpuis("TMS570LS0232")
|
|
sif cpuis("TMS570LS3137-EP")
|
|
bitfld.long 0x00 15. " OUTPUT_BUFFER_LOW_EMI_MODE[9] ,Signal RTP output buffer low emi mode disable" "No,Yes"
|
|
bitfld.long 0x00 14. " [8] ,Signal ADEVT output buffer low emi mode disable" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 13. " [7] ,Signal nERROR output buffer low emi mode disable" "No,Yes"
|
|
newline
|
|
else
|
|
bitfld.long 0x00 13. " OUTPUT_BUFFER_LOW_EMI_MODE[7] ,Signal nERROR output buffer low emi mode disable" "No,Yes"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 12. " [6] ,MiBSPI1 output buffer low emi mode disable" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 11. " [5] ,Signal RTCK output buffer low emi mode disable" "No,Yes"
|
|
bitfld.long 0x00 10. " [4] ,Signal TDO output buffer low emi mode disable" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 8. " [3] ,Signal TMS output buffer low emi mode disable" "No,Yes"
|
|
bitfld.long 0x00 4. " [2] ,MiBSPI5 output buffer low emi mode disable" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 2. " [1] ,MiBSPI3 output buffer low emi mode disable" "No,Yes"
|
|
bitfld.long 0x00 0. " [0] ,MiBSPI1 output buffer low emi mode disable" "No,Yes"
|
|
endif
|
|
endif
|
|
hgroup.long 0xA8++0x03
|
|
hide.long 0x00 "IMPFASTS,Imprecise Fault Status Register"
|
|
in
|
|
rgroup.long 0xAC++0x03
|
|
line.long 0x00 "IMPFTADD,Imprecise Fault Write Address Register"
|
|
width 7.
|
|
tree "System Software Interrupt Request Registers"
|
|
group.long 0xB0++0x0F
|
|
line.long 0x00 "SSIR1,System Software Interrupt Request 1 Register"
|
|
hexmask.long.byte 0x00 8.--15. 1. " SSKEY1 ,System software interrupt request key"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSDATA1 ,System software interrupt data"
|
|
line.long 0x04 "SSIR2,System Software Interrupt Request 2 Register"
|
|
hexmask.long.byte 0x04 8.--15. 1. " SSKEY2 ,System software interrupt 2 request key"
|
|
hexmask.long.byte 0x04 0.--7. 1. " SSDATA2 ,System software interrupt 2 data"
|
|
line.long 0x08 "SSIR3,System Software Interrupt Request 3 Register"
|
|
hexmask.long.byte 0x08 8.--15. 1. " SSKEY3 ,System software interrupt 3 request key"
|
|
hexmask.long.byte 0x08 0.--7. 1. " SSDATA3 ,System software interrupt 3 data"
|
|
line.long 0x0C "SSIR4,System Software Interrupt Request 4 Register"
|
|
hexmask.long.byte 0x0C 8.--15. 1. " SSKEY4 ,System software interrupt 3 request key"
|
|
hexmask.long.byte 0x0C 0.--7. 1. " SSDATA4 ,System software interrupt 4 data"
|
|
tree.end
|
|
newline
|
|
width 10.
|
|
group.long 0xC0++0x07
|
|
line.long 0x00 "RAMGCR,RAM Control Register"
|
|
bitfld.long 0x00 16.--19. " RAM_DFT_EN ,Functional mode RAM DFT port enable key" "Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Enabled,Disabled,Disabled,Disabled,Disabled,Disabled"
|
|
bitfld.long 0x00 2. " WST_AENA0 ,eSRAM0 data phase wait state enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " WST_DENA0 ,eSRAM0 data phase wait state enable" "Disabled,Enabled"
|
|
line.long 0x04 "BMMCR1,Bus Matrix Module Control Register 1"
|
|
bitfld.long 0x04 0.--3. " MEMSW ,Memory swap bit key" ",,,,,Swapped,,,,,Default,?..."
|
|
sif (!cpuis("TMS570LS09*")&&!cpuis("TMS570LS07*")&&!cpuis("TMS570LS0232")&&!cpuis("TMS570LS3137-EP"))
|
|
group.long 0xC8++0x03
|
|
line.long 0x0 "BMMCR2,Bus Matrix Module Control Register 2"
|
|
bitfld.long 0x00 7. " PRTY_PBM ,PBM Arbitration Priority" "Fixed,Round robin"
|
|
bitfld.long 0x00 6. " PRTY_HPI ,HPI Arbitration Priority" "Fixed,Round robin"
|
|
bitfld.long 0x00 5. " PRTY_RAM3 ,eSRAM3 Arbitration Priority" "Fixed,Round robin"
|
|
bitfld.long 0x00 4. " PRTY_RAM2 ,eSRAM2 Arbitration Priority" "Fixed,Round robin"
|
|
newline
|
|
bitfld.long 0x00 3. " PRTY_CRC ,CRC Arbitration Priority" "Fixed,Round robin"
|
|
bitfld.long 0x00 2. " PRTY_PRG ,Peripheral Bridge Arbitration Priority" "Fixed,Round robin"
|
|
bitfld.long 0x00 1. " PRTY_FLASH ,eSRAM1 Arbitration Priority" "Fixed,Round robin"
|
|
bitfld.long 0x00 0. " PRTY_RAM0 ,eSRAM0 Arbitration Priority" "Fixed,Round robin"
|
|
endif
|
|
sif (cpuis("TMS570LS09*")||cpuis("TMS570LS07*")||cpuis("TMS570LS0232")||cpuis("TMS570LS3137-EP"))
|
|
group.long 0xCC++0x03
|
|
line.long 0x00 "CPURSTCR,CPU Reset Control Register"
|
|
bitfld.long 0x00 0. " CPU_RESET ,CPU reset" "No reset,Reset"
|
|
else
|
|
group.long 0xCC++0x03
|
|
line.long 0x00 "MMUGCR,MMU Global Control Register"
|
|
bitfld.long 0x00 0. " CPU_RESET ,Memory Protection Mode Enable" "MMU/MPU,MPU"
|
|
endif
|
|
group.long 0xD0++0x07
|
|
line.long 0x0 "CLKCNTL,Clock Control Register"
|
|
sif (cpuis("TMS570LS0232"))
|
|
bitfld.long 0x00 24.--27. " VCLKR2 ,VBUS clock 2 ratio" "HCLK,HCLK/2,?..."
|
|
bitfld.long 0x00 16.--19. " VCLKR ,VBUS clock ratio" "HCLK,HCLK/2,?..."
|
|
newline
|
|
else
|
|
bitfld.long 0x00 24.--27. " VCLKR2 ,VBUS clock 2 ratio" "HCLK,HCLK/2,HCLK/3,HCLK/4,HCLK/5,HCLK/6,HCLK/7,HCLK/8,HCLK/9,HCLK/10,HCLK/11,HCLK/12,HCLK/13,HCLK/14,HCLK/15,HCLK/16"
|
|
bitfld.long 0x00 16.--19. " VCLKR ,VBUS clock ratio" "HCLK,HCLK/2,HCLK/3,HCLK/4,HCLK/5,HCLK/6,HCLK/7,HCLK/8,HCLK/9,HCLK/10,HCLK/11,HCLK/12,HCLK/13,HCLK/14,HCLK/15,HCLK/16"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 8. " PENA ,Peripheral enable" "Reset,No reset"
|
|
line.long 0x04 "ECPCNTL,ECP Control Register"
|
|
bitfld.long 0x04 24. " ECPSSEL ,ECP clock source select for ECP module" "Oscillator,VCLK"
|
|
bitfld.long 0x04 23. " ECPCOS ,ECP continue on suspend" "Suspended,Continue"
|
|
newline
|
|
sif (cpuis("TMS570LS09*")||cpuis("TMS570LS07*")||cpuis("TMS570LS0232")||cpuis("TMS570LS3137-EP"))
|
|
bitfld.long 0x04 16.--17. " ECPINSEL ,ECP input clock source" "Tied low,HCLK,External clock,Tied low"
|
|
newline
|
|
endif
|
|
hexmask.long.word 0x04 0.--15. 1. " ECPDIV ,ECP divider value"
|
|
group.long 0xDC++0x0B
|
|
line.long 0x00 "DEVCR1,DEV Parity Control Register 1"
|
|
bitfld.long 0x00 0.--3. " DEVPARSEL ,Device parity select bit key" ",,,,,Even,,,,,Odd,?..."
|
|
line.long 0x04 "SYSECR,System Exception Control Register"
|
|
bitfld.long 0x04 14.--15. " RESET ,Software reset" "Reset,No reset,Reset,Reset"
|
|
line.long 0x08 "SYSESR,System Exception Status Register"
|
|
eventfld.long 0x08 15. " PORST ,Power-on reset" "No reset,Reset"
|
|
eventfld.long 0x08 14. " OSCRST ,Oscillator failure/PLL cycle slip reset" "No reset,Reset"
|
|
eventfld.long 0x08 13. " WDRST ,Watchdog reset flag" "No reset,Reset"
|
|
newline
|
|
eventfld.long 0x08 5. " CPURST ,CPU reset flag" "No reset,Reset"
|
|
eventfld.long 0x08 4. " SWRST ,Software reset flag" "No reset,Reset"
|
|
eventfld.long 0x08 3. " EXTRST ,External reset flag" "No reset,Reset"
|
|
sif (!cpuis("TMS570LS09*")&&!cpuis("TMS570LS07*")&&!cpuis("TMS570LS0232")&&!cpuis("TMS570LS3137-EP"))
|
|
newline
|
|
eventfld.long 0x08 0. " MPMODE ,Current memory protection unit" "Disabled,Enabled"
|
|
endif
|
|
newline
|
|
sif (cpuis("TMS570LS09*")||cpuis("TMS570LS07*")||cpuis("TMS570LS0232"))
|
|
group.long 0xE8++0x03
|
|
line.long 0x00 "SYSTASR,System Test Abort Status Register"
|
|
bitfld.long 0x00 0.--4. " EFUSE_ABORT ,Test abort status flag" "Last op completed,Timed out,Auto-load machine started|Not enough FuseROM data,Auto-load machine started|Wrong signature returned,Auto-load machine started|Not able/allowed to complete op,?..."
|
|
newline
|
|
endif
|
|
group.long 0xEC++0x07
|
|
line.long 0x00 "GLBSTAT,Global Status Register"
|
|
eventfld.long 0x00 9. " FBSLIP ,Over cycle slip detection of PLL" "Not detected,Detected"
|
|
eventfld.long 0x00 8. " RFSLIP ,Under cycle slip detection of PLL" "Not detected,Detected"
|
|
eventfld.long 0x00 0. " OSCFAIL ,Oscillator fail flag" "Not failed,Failed"
|
|
line.long 0x04 "DEVID,Device Identification Register"
|
|
sif (cpuis("TMS570LS09*")||cpuis("TMS570LS07*")||cpuis("TMS570LS0232")||cpuis("TMS570LS3137-EP"))
|
|
rbitfld.long 0x04 31. " CP15 ,CPU coprocessor 15 presence" "No CP15,CP15"
|
|
hexmask.long.word 0x04 17.--30. 1. " ID ,Device ID"
|
|
rbitfld.long 0x04 13.--16. " TECH ,Device manufacture process technology" "C05,F05,C035,F035,C021,F021,?..."
|
|
newline
|
|
rbitfld.long 0x04 12. " I/O ,Input/Output voltage" "3.3 V,5 V"
|
|
rbitfld.long 0x04 11. " PPAR ,Peripheral parity" "No parity,Parity"
|
|
rbitfld.long 0x04 9.--10. " FLASH_ECC ,Program memory parity present" "Not protected,Single bit,ECC,?..."
|
|
newline
|
|
rbitfld.long 0x04 8. " RAM_ECC ,RAM ECC" "No ECC,ECC"
|
|
hexmask.long.byte 0x04 3.--7. 1. " VERSION ,Version"
|
|
hexmask.long.byte 0x04 0.--2. 1. " PLATFORM_ID ,The TMSx70 platform ID"
|
|
else
|
|
bitfld.long 0x04 31. " CP15 ,CP15 CPU" "No CP15,CP15"
|
|
hexmask.long.word 0x04 17.--30. 1. " ID ,Device ID"
|
|
bitfld.long 0x04 13.--16. " TECH ,Device manufacture process technology" "C05,F05,C035,F035,?..."
|
|
newline
|
|
bitfld.long 0x04 12. " I/O ,Input/Output voltage" "3.3 V,5 V"
|
|
bitfld.long 0x04 11. " PPAR ,Peripheral parity" "No parity,Parity"
|
|
bitfld.long 0x04 9.--10. " PROGRAM_PARITY ,Program memory parity present" "Not protected,Single bit,ECC,?..."
|
|
newline
|
|
bitfld.long 0x04 8. " RECC ,RAM ECC" "No ECC,ECC"
|
|
hexmask.long.byte 0x04 3.--7. 1. " VERSION ,Version"
|
|
hexmask.long.byte 0x04 0.--2. 1. " PLATFORM_ID ,The TMSx70 platform ID"
|
|
endif
|
|
hgroup.long 0xF4++0x03
|
|
hide.long 0x00 "SSIVEC,Software Interrupt Vector Register"
|
|
in
|
|
group.long 0xF8++0x03
|
|
line.long 0x00 "SSIF,System Software Interrupt Flag Register"
|
|
eventfld.long 0x00 3. " SSI_FLAG4 ,System software interrupt flag 4" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 2. " SSI_FLAG3 ,System software interrupt flag 3" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 1. " SSI_FLAG2 ,System software interrupt flag 2" "No interrupt,Interrupt"
|
|
newline
|
|
eventfld.long 0x00 0. " SSI_FLAG1 ,System software interrupt flag 1" "No interrupt,Interrupt"
|
|
sif (cpuis("TMS570LS09*")||cpuis("TMS570LS07*")||cpuis("TMS570LS0232"))
|
|
endian.le
|
|
endif
|
|
width 0x0B
|
|
else
|
|
width 9.
|
|
tree "System Pin Control Registers"
|
|
group.long 0x00++0x7
|
|
line.long 0x0 "SYSPC1,SYS Pin Control Register 1"
|
|
bitfld.long 0x00 0. " ECPCLKFUN ,ECPCLK Function" "GIO,ECPCLK"
|
|
line.long 0x04 "SYSPC2,SYS Pin Control Register 2"
|
|
bitfld.long 0x04 0. " ECPCLKDIR ,ECPCLK Data Direction" "Input,Output"
|
|
rgroup.long 0x08++0x3
|
|
line.long 0x0 "SYSPC3,SYS Pin Control Register 3"
|
|
bitfld.long 0x00 0. " ECPCLKDIN ,ECPCLK Data In" "Low,High"
|
|
sif (cpuis("RM48L950*"))
|
|
if ((((d.l(ad:0xFFFFFF00))&0x01000000)==0x00)&&(((d.l(ad:0xFFFFFF00+0x04))&0x01000000)==0x01000000))
|
|
group.long 0x0C++0x3
|
|
line.long 0x0 "SYSPC4,SYS Pin Control Register 4"
|
|
bitfld.long 0x00 0. " ECPCLKDOUT ,ECPCLK Data Out Write" "Low,High"
|
|
elif (((d.l(ad:0xFFFFFF00))&0x01000000)==0x00)
|
|
rgroup.long 0x0C++0x3
|
|
line.long 0x0 "SYSPC4,SYS Pin Control Register 4"
|
|
bitfld.long 0x00 0. " ECPCLKDOUT ,ECPCLK Data Out Write" "Low,High"
|
|
else
|
|
hgroup.long 0x0C++0x3
|
|
hide.long 0x0 "SYSPC4,SYS Pin Control Register 4"
|
|
endif
|
|
else
|
|
if ((((d.l(ad:0xFFFFFF00))&0x01)==0x00)&&(((d.l(ad:0xFFFFFF00+0x04))&0x01)==0x01))
|
|
group.long 0x0C++0x3
|
|
line.long 0x0 "SYSPC4,SYS Pin Control Register 4"
|
|
bitfld.long 0x00 0. " ECPCLKDOUT ,ECPCLK Data Out Write" "Low,High"
|
|
elif (((d.l(ad:0xFFFFFF00))&0x01)==0x00)
|
|
rgroup.long 0x0C++0x3
|
|
line.long 0x0 "SYSPC4,SYS Pin Control Register 4"
|
|
bitfld.long 0x00 0. " ECPCLKDOUT ,ECPCLK Data Out Write" "Low,High"
|
|
else
|
|
hgroup.long 0x0C++0x3
|
|
hide.long 0x0 "SYSPC4,SYS Pin Control Register 4"
|
|
endif
|
|
endif
|
|
sif (cpuis("RM48L950*"))
|
|
if ((((d.l(ad:0xFFFFFF00))&0x01000000)==0x00)&&(((d.l(ad:0xFFFFFF00+0x04))&0x01000000)==0x01000000))
|
|
group.long 0x10++0x7
|
|
line.long 0x0 "SYSPC5,SYS Pin Control Register 5"
|
|
bitfld.long 0x00 0. " ECPCLKSET ,ECPCLK Data Out Set" "Low,High"
|
|
line.long 0x04 "SYSPC6,SYS Pin Control Register 6"
|
|
bitfld.long 0x04 0. " ECPCLKCLR ,ECPCLK Data Out clear" "Low,High"
|
|
else
|
|
hgroup.long 0x10++0x7
|
|
hide.long 0x00 "SYSPC5,SYS Pin Control Register 5"
|
|
hide.long 0x04 "SYSPC6,SYS Pin Control Register 6"
|
|
endif
|
|
else
|
|
if ((((d.l(ad:0xFFFFFF00))&0x01)==0x00)&&(((d.l(ad:0xFFFFFF00+0x04))&0x01)==0x01))
|
|
group.long 0x10++0x7
|
|
line.long 0x0 "SYSPC5,SYS Pin Control Register 5"
|
|
bitfld.long 0x00 0. " ECPCLKSET ,ECPCLK Data Out Set" "Low,High"
|
|
line.long 0x04 "SYSPC6,SYS Pin Control Register 6"
|
|
bitfld.long 0x04 0. " ECPCLKCLR ,ECPCLK Data Out clear" "Low,High"
|
|
else
|
|
hgroup.long 0x10++0x7
|
|
hide.long 0x00 "SYSPC5,SYS Pin Control Register 5"
|
|
hide.long 0x04 "SYSPC6,SYS Pin Control Register 6"
|
|
endif
|
|
endif
|
|
sif (cpuis("RM48L950*"))
|
|
if (((d.l(ad:0xFFFFFF00))&0x01000000)==0x00)
|
|
group.long 0x18++0x3
|
|
line.long 0x0 "SYSPC7,SYS Pin Control Register 7"
|
|
bitfld.long 0x00 0. " ECPCLKODE ,ECPCLK Open Drain Enable" "Push/pull,Open drain"
|
|
else
|
|
hgroup.long 0x18++0x3
|
|
hide.long 0x0 "SYSPC7,SYS Pin Control Register 7"
|
|
endif
|
|
else
|
|
if (((d.l(ad:0xFFFFFF00))&0x01)==0x00)
|
|
group.long 0x18++0x3
|
|
line.long 0x0 "SYSPC7,SYS Pin Control Register 7"
|
|
bitfld.long 0x00 0. " ECPCLKODE ,ECPCLK Open Drain Enable" "Push/pull,Open drain"
|
|
else
|
|
hgroup.long 0x18++0x3
|
|
hide.long 0x0 "SYSPC7,SYS Pin Control Register 7"
|
|
endif
|
|
endif
|
|
sif (cpuis("RM48L950*"))
|
|
if ((((d.l(ad:0xFFFFFF00))&0x01000000)==0x00)&&(((d.l(ad:0xFFFFFF00+0x04))&0x01000000)==0x00))
|
|
group.long 0x1C++0x3
|
|
line.long 0x0 "SYSPC8,SYS Pin Control Register 8"
|
|
bitfld.long 0x00 0. " ECPCLKPULDIS ,ECPCLK Pull Disable" "Active,Inactive"
|
|
else
|
|
hgroup.long 0x1C++0x3
|
|
hide.long 0x0 "SYSPC8,SYS Pin Control Register 8"
|
|
endif
|
|
else
|
|
if ((((d.l(ad:0xFFFFFF00))&0x01)==0x00)&&(((d.l(ad:0xFFFFFF00+0x04))&0x01)==0x00))
|
|
group.long 0x1C++0x3
|
|
line.long 0x0 "SYSPC8,SYS Pin Control Register 8"
|
|
bitfld.long 0x00 0. " ECPCLKPULDIS ,ECPCLK Pull Disable" "Active,Inactive"
|
|
else
|
|
hgroup.long 0x1C++0x3
|
|
hide.long 0x0 "SYSPC8,SYS Pin Control Register 8"
|
|
endif
|
|
endif
|
|
sif (cpuis("RM48L950*"))
|
|
if ((((d.l(ad:0xFFFFFF00))&0x01000000)==0x00)&&(((d.l(ad:0xFFFFFF00+0x04))&0x01000000)==0x00)&&(((d.l(ad:0xFFFFFF00+0x1C))&0x01000000)==0x00))
|
|
group.long 0x20++0x3
|
|
line.long 0x0 "SYSPC9,SYS Pin Control Register 9"
|
|
bitfld.long 0x00 0. " ECPCLKPSEL ,ECPCLK Pull Up/Pull Down Select" "Down,Up"
|
|
else
|
|
hgroup.long 0x20++0x3
|
|
hide.long 0x0 "SYSPC9,SYS Pin Control Register 9"
|
|
endif
|
|
else
|
|
if ((((d.l(ad:0xFFFFFF00))&0x01)==0x00)&&(((d.l(ad:0xFFFFFF00+0x04))&0x01)==0x00)&&(((d.l(ad:0xFFFFFF00+0x1C))&0x01)==0x00))
|
|
group.long 0x20++0x3
|
|
line.long 0x0 "SYSPC9,SYS Pin Control Register 9"
|
|
bitfld.long 0x00 0. " ECPCLKPSEL ,ECPCLK Pull Up/Pull Down Select" "Down,Up"
|
|
else
|
|
hgroup.long 0x20++0x3
|
|
hide.long 0x0 "SYSPC9,SYS Pin Control Register 9"
|
|
endif
|
|
endif
|
|
sif (cpu()!=("TMS570LS0332")&&cpu()!=("TMS570LS0432")&&!cpuis("TMS570LS1114*")&&!cpuis("TMS570LS1115*")&&!cpuis("TMS570LS1224*")&&!cpuis("TMS570LS1225*")&&!cpuis("TMS570LS1227*"))
|
|
group.long 0x78++0x3
|
|
line.long 0x0 "SYSPC10,SYS Pin Control Register 10"
|
|
bitfld.long 0x00 0. " ECPCLK_SLEW ,ECPCLK Slew Control" "Fast,Slow"
|
|
endif
|
|
tree.end
|
|
tree "System SSW PLL BIST Control Registers"
|
|
sif !(cpu()==("TMS570LS2124-PGE")||cpu()==("TMS570LS2124-ZWT")||cpu()==("TMS570LS2125-PGE")||cpu()==("TMS570LS2125-ZWT")||(cpu()=="TMS570LS2126")||(cpu()=="TMS570LS2127")||cpu()==("TMS570LS2134-PGE")||cpu()==("TMS570LS2134-ZWT")||cpu()==("TMS570LS2135-PGE")||cpu()==("TMS570LS2135-ZWT")||(cpu()=="TMS570LS2136")||(cpu()=="TMS570LS2137")||cpu()==("TMS570LS3134-PGE")||cpu()==("TMS570LS3134-ZWT")||cpu()==("TMS570LS3135-PGE")||cpu()==("TMS570LS3135-ZWT")||(cpu()=="TMS570LS3136")||(cpu()=="TMS570LS3137-PGE")||(cpu()=="TMS570LS3137-ZWT")||(cpu()=="TMS570LS30336")||(cpu()=="RM48L950")||cpu()=="RM48L952-PGE"||cpu()=="RM48L952-ZWT"||cpu()=="RM48L950-PGE"||cpu()=="RM48L950-ZWT"||cpu()=="RM48L940-ZWT"||cpu()=="RM48L940-PGE"||cpu()=="RM48L930-ZWT"||cpu()=="RM48L930-PGE"||cpu()=="RM48L750-ZWT"||cpu()=="RM48L750-PGE"||cpu()=="RM48L740-ZWT"||cpu()=="RM48L740-PGE"||cpu()=="RM48L730-ZWT"||cpu()=="RM48L730-PGE"||cpu()=="RM48L550-PGE"||cpu()=="RM48L540-ZWT"||cpu()=="RM48L540-PGE"||cpu()=="RM48L530-ZWT"||cpu()=="RM48L530-PGE"||cpu()=="RM46L852-PGE"||cpu()=="RM46L852-ZWT"||cpu()=="RM46L850-PGE"||cpu()=="RM46L850-ZWT"||cpu()=="RM46L840-ZWT"||cpu()=="RM46L840-PGE"||cpu()=="RM46L830-ZWT"||cpu()=="RM46L830-PGE"||cpu()=="RM46L450-ZWT"||cpu()=="RM46L450-PGE"||cpu()=="RM46L440-ZWT"||cpu()=="RM46L440-PGE"||cpu()=="RM46L430-ZWT"||cpu()=="RM46L430-PGE"||cpu()=="RM42L432"||cpu()=="RM48L550-ZWT"||cpu()==("TMS570LS0332")||cpu()==("TMS570LS0432")||!cpuis("TMS570LS1114*")||!cpuis("TMS570LS1115*")||!cpuis("TMS570LS1224*")||!cpuis("TMS570LS1225*")||!cpuis("TMS570LS1227*"))
|
|
group.long 0x24++0x3
|
|
line.long 0x0 "SSWPLL1,SSW PLL BIST Control Register 1"
|
|
hexmask.long.byte 0x00 8.--15. 1. " CAPTURE_WINDOW_INDEX ,Window capture index"
|
|
bitfld.long 0x00 6. " COUNTER_READ_READY ,Counter Read Ready" "Not ready,Ready"
|
|
textline " "
|
|
bitfld.long 0x00 5. " COUNTER_RESET ,Counter Reset" "No reset,Reset"
|
|
bitfld.long 0x00 4. " COUNTER_EN ,Counter Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1.--3. " TAP_COUNTER_DIS[3:1] ,TAP Counter Disable" "Bit 16,Bit 18,Bit 20,Bit 22,Bit 24,Bit 26,Bit 28,Bit 30"
|
|
bitfld.long 0x00 0. " EXT_COUNTER_EN ,Modulation Depth/Frequency Measurement mode" "Modulation Dept,Frequency"
|
|
rgroup.long 0x28++0x3
|
|
line.long 0x0 "SSWPLL2,SSW PLL BIST Control Register 2"
|
|
rgroup.long 0x2C++0x3
|
|
line.long 0x0 "SSWPLL3,SSW PLL BIST Control Register 3"
|
|
endif
|
|
tree.end
|
|
width 7.
|
|
tree "System Clock Source/Domain Disable Registers"
|
|
group.long 0x30++0x3
|
|
line.long 0x0 "CSDIS,Clock Source Disable Register"
|
|
sif (cpu()!=("TMS570LS0332")&&cpu()!=("TMS570LS0432"))
|
|
setclrfld.long 0x00 7. 0x04 7. 0x08 7. " CLKSR7_OFF_set/clr ,Clock Source 7 (External Clock In 2) Off" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x00 6. 0x04 6. 0x08 6. " CLKSR6_OFF_set/clr ,Clock Source 6 (PLL2) Off" "Enabled,Disabled"
|
|
endif
|
|
setclrfld.long 0x00 5. 0x04 5. 0x08 5. " CLKSR5_OFF_set/clr ,Clock Source 5 (LPO High Frequency Clock) Off" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x00 4. 0x04 4. 0x08 4. " CLKSR4_OFF_set/clr ,Clock Source 4 (LPO Low Frequency Clock) Off" "Enabled,Disabled"
|
|
setclrfld.long 0x00 3. 0x04 3. 0x08 3. " CLKSR3_OFF_set/clr ,Clock Source 3 (External Clock In) Off" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x04 1. 0x08 1. " CLKSR1_OFF_set/clr ,Clock Source 1 (PLL1) Off" "Enabled,Disabled"
|
|
setclrfld.long 0x00 0. 0x04 0. 0x08 0. " CLKSR0_OFF_set/clr ,Clock Source 0 (Oscillator) Off" "Enabled,Disabled"
|
|
group.long 0x3C++0x3
|
|
line.long 0x0 "CDDIS,Clock Domain Disable Register"
|
|
sif (cpu()!=("TMS570LS0332")&&cpu()!=("TMS570LS0432"))
|
|
setclrfld.long 0x00 11. 0x4 11. 0x8 11. " VCLKA4OFF_set/clr ,VCLKA4 Domain Off" "Enabled,Disabled"
|
|
setclrfld.long 0x00 10. 0x4 10. 0x8 10. " VCLKA3OFF_set/clr ,VCLKA3 Domain Off" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x00 8. 0x4 8. 0x8 8. " VCLK3OFF_set/clr ,VCLK3 Domain Off" "Enabled,Disabled"
|
|
else
|
|
setclrfld.long 0x00 9. 0x4 9. 0x8 9. " VCLK_EQEP_OFF_set/clr ,VCLK_EQEP_OFF domain off" "Enabled,Disabled"
|
|
endif
|
|
setclrfld.long 0x00 6. 0x4 6. 0x8 6. " RTICLK1OFF_set/clr ,RTICLK1 Domain Off" "Enabled,Disabled"
|
|
textline " "
|
|
sif (cpu()!=("TMS570LS0332")&&cpu()!=("TMS570LS0432"))
|
|
setclrfld.long 0x00 5. 0x4 5. 0x8 5. " VCLKA2OFF_set/clr ,VCLKA2 Domain Off" "Enabled,Disabled"
|
|
endif
|
|
setclrfld.long 0x00 4. 0x4 4. 0x8 4. " VCLKA1OFF_set/clr ,VCLKA1 Domain Off" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x00 3. 0x4 3. 0x8 3. " VCLK2OFF_set/clr ,VCLK2 Domain Off" "Enabled,Disabled"
|
|
setclrfld.long 0x00 2. 0x4 2. 0x8 2. " VCLKPOFF_set/clr ,VCLKP Domain Off" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x4 1. 0x8 1. " HCLKOFF_set/clr ,HCLK Domain Off" "Enabled,Disabled"
|
|
setclrfld.long 0x00 0. 0x4 0. 0x8 0. " GCLKOFF_set/clr ,GCLK Domain Off" "Enabled,Disabled"
|
|
tree.end
|
|
width 13.
|
|
group.long 0x48++0x3
|
|
line.long 0x0 "GHVSRC,GCLK/HCLK/VCLK and VCLK2 Source Register"
|
|
sif (cpu()==("TMS570LS0332")||cpu()==("TMS570LS0432"))
|
|
bitfld.long 0x00 24.--27. " GHVWAKE[3:0] ,GCLK/HCLK/VCLK/VCLK2/VCLK3/VCLK4 Source on Wakeup" "Source 0,Source 1,Reserved,Source 3,Source 4,Source 5,?..."
|
|
bitfld.long 0x00 16.--19. " HVLPM[3:0] ,HCLK/VCLK/VCLK2/VCLK3/VCLK4 Source on Wakeup (GCLK Turned Off)" "Source 0,Source 1,Reserved,Source 3,Source 4,Source 5,?..."
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " GHVSRC[3:0] ,GCLK/HCLK/VCLK/VCLK2/VCLK3/VCLK4 Current Source" "Source 0,Source 1,Reserved,Source 3,Source 4,Source 5,?..."
|
|
elif (cpuis("TMS570LS1114*")||cpuis("TMS570LS1115*")||cpuis("TMS570LS1224*")||cpuis("TMS570LS1225*")||cpuis("TMS570LS1227*"))
|
|
bitfld.long 0x00 24.--27. " GHVWAKE[3:0] ,GCLK/HCLK/VCLK/VCLK2/VCLK3/VCLK4 Source on Wakeup" "Source 0,Source 1,Reserved,Source 3,Source 4,Source 5,Source 6,Source 7,?..."
|
|
bitfld.long 0x00 16.--19. " HVLPM[3:0] ,HCLK/VCLK/VCLK2/VCLK3/VCLK4 Source on Wakeup (GCLK Turned Off)" "Source 0,Source 1,Reserved,Source 3,Source 4,Source 5,Source 6,Source 7,?..."
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " GHVSRC[3:0] ,GCLK/HCLK/VCLK/VCLK2/VCLK3/VCLK4 Current Source" "Source 0,Source 1,Reserved,Source 3,Source 4,Source 5,Source 6,Source 7,?..."
|
|
else
|
|
bitfld.long 0x00 24.--27. " GHVWAKE[3:0] ,GCLK/HCLK/VCLK/VCLK2/VCLK3/VCLK4 Source on Wakeup" "Source 0,Source 1,Source 2,Source 3,Source 4,Source 5,Source 6,Source 7,?..."
|
|
bitfld.long 0x00 16.--19. " HVLPM[3:0] ,HCLK/VCLK/VCLK2/VCLK3/VCLK4 Source on Wakeup (GCLK Turned Off)" "Source 0,Source 1,Source 2,Source 3,Source 4,Source 5,Source 6,Source 7,?..."
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " GHVSRC[3:0] ,GCLK/HCLK/VCLK/VCLK2/VCLK3/VCLK4 Current Source" "Source 0,Source 1,Source 2,Source 3,Source 4,Source 5,Source 6,Source 7,?..."
|
|
endif
|
|
group.long 0x4C++0x3
|
|
line.long 0x0 "VCLKASRC,Peripheral Asynchronous Clock Source Register"
|
|
sif (cpu()==("TMS570LS0332")||cpu()==("TMS570LS0432"))
|
|
bitfld.long 0x00 0.--3. " VCLKA1S[3:0] ,Peripheral Asynchronous Clock 1 Source" "Source 0,Source 1,Reserved,Source 3,Source 4,Source 5Reserved,Reserved,VCLK,VCLK,VCLK,VCLK,VCLK,VCLK,VCLK,VCLK,?..."
|
|
elif (cpuis("TMS570LS1114*")||cpuis("TMS570LS1115*")||cpuis("TMS570LS1224*")||cpuis("TMS570LS1225*")||cpuis("TMS570LS1227*"))
|
|
bitfld.long 0x00 8.--11. " VCLKA2S[3:0] ,Peripheral Asynchronous Clock 2 Source" "Source 0,Source 1,Reserved,Source 3,Source 4,Source 5,Source 6,Source 7,VCLK,VCLK,VCLK,VCLK,VCLK,VCLK,VCLK,VCLK"
|
|
bitfld.long 0x00 0.--3. " VCLKA1S[3:0] ,Peripheral Asynchronous Clock 1 Source" "Source 0,Source 1,Reserved,Source 3,Source 4,Source 5,Source 6,Source 7,VCLK,VCLK,VCLK,VCLK,VCLK,VCLK,VCLK,VCLK"
|
|
else
|
|
bitfld.long 0x00 8.--11. " VCLKA2S[3:0] ,Peripheral Asynchronous Clock 2 Source" "Source 0,Source 1,Source 2,Source 3,Source 4,Source 5,Source 6,Source 7,VCLK,VCLK,VCLK,VCLK,VCLK,VCLK,VCLK,VCLK"
|
|
bitfld.long 0x00 0.--3. " VCLKA1S[3:0] ,Peripheral Asynchronous Clock 1 Source" "Source 0,Source 1,Source 2,Source 3,Source 4,Source 5,Source 6,Source 7,VCLK,VCLK,VCLK,VCLK,VCLK,VCLK,VCLK,VCLK"
|
|
endif
|
|
group.long 0x50++0x3
|
|
line.long 0x0 "RCLKSRC,RTI Clock Source Register"
|
|
bitfld.long 0x00 8.--9. " RTI1DIV[1:0] ,RTI Clock 1 Divider" "RTICLK1,RTICLK1/2,RTICLK1/4,RTICLK1/8"
|
|
sif (cpu()==("TMS570LS0332")||cpu()==("TMS570LS0432"))
|
|
bitfld.long 0x00 0.--3. " RTI1SRC[3:0] ,RTI Clock 1 Source" "Source 0,Source 1,Reserved,Source 3,Source 4,Source 5,Reserved,Reserved,VCLK,VCLK,VCLK,VCLK,VCLK,VCLK,VCLK,VCLK"
|
|
elif (cpuis("TMS570LS1114*")||cpuis("TMS570LS1115*")||cpuis("TMS570LS1224*")||cpuis("TMS570LS1225*")||cpuis("TMS570LS1227*"))
|
|
bitfld.long 0x00 0.--3. " RTI1SRC[3:0] ,RTI Clock 1 Source" "Source 0,Source 1,Reserved,Source 3,Source 4,Source 5,Source 6,Source 7,VCLK,VCLK,VCLK,VCLK,VCLK,VCLK,VCLK,VCLK"
|
|
else
|
|
bitfld.long 0x00 0.--3. " RTI1SRC[3:0] ,RTI Clock 1 Source" "Source 0,Source 1,Source 2,Source 3,Source 4,Source 5,Source 6,Source 7,VCLK,VCLK,VCLK,VCLK,VCLK,VCLK,VCLK,VCLK"
|
|
endif
|
|
width 13.
|
|
rgroup.long 0x54++0x3
|
|
line.long 0x0 "CSVSTAT,Clock Source Valid Status Register"
|
|
sif (cpu()!=("TMS570LS0332")&&cpu()!=("TMS570LS0432"))
|
|
bitfld.long 0x00 7. " CLKSR7V ,Clock Source 7 Valid" "Not valid,Valid"
|
|
bitfld.long 0x00 6. " CLKSR6V ,Clock Source 6 Valid" "Not valid,Valid"
|
|
endif
|
|
bitfld.long 0x00 5. " CLKSR5V ,Clock Source 5 Valid" "Not valid,Valid"
|
|
textline " "
|
|
bitfld.long 0x00 4. " CLKSR4V ,Clock Source 4 Valid" "Not valid,Valid"
|
|
bitfld.long 0x00 3. " CLKSR3V ,Clock Source 3 Valid" "Not valid,Valid"
|
|
textline " "
|
|
bitfld.long 0x00 1. " CLKSR1V ,Clock Source 1 Valid" "Not valid,Valid"
|
|
bitfld.long 0x00 0. " CLKSR0V ,Clock Source 0 Valid" "Not valid,Valid"
|
|
group.long 0x58++0x3
|
|
line.long 0x0 "MSTGCR,Memory Self-Test Global Control Register"
|
|
sif (cpu()!=("TMS570LS0332")&&cpu()!=("TMS570LS0432"))
|
|
hexmask.long.byte 0x00 16.--23. 1. " MBIST_ALGSEL ,Selects Different Algorithm for MBIST"
|
|
bitfld.long 0x00 8.--9. " ROM_DIV[1:0] ,ROM Clock Source Prescaler Divider" "HCLK,HCLK/2,HCLK/4,HCLK/8"
|
|
endif
|
|
bitfld.long 0x00 0.--3. " MSTGENA[3:0] ,Memory Self-Test Controller Global Enable Key" "Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Enabled,Disabled,Disabled,Disabled,Disabled,Disabled"
|
|
group.long 0x5C++0x3
|
|
line.long 0x0 "MINITGCR,Memory Hardware Initialization Global Control Register"
|
|
bitfld.long 0x00 0.--3. " MINITGENA[3:0] ,Memory Hardware Initialization Global Enable Key" "Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Enabled,Disabled,Disabled,Disabled,Disabled,Disabled"
|
|
group.long 0x60++0x3
|
|
line.long 0x0 "MSINENA,MBIST Controller/Memory Initialization Enable Register"
|
|
bitfld.long 0x00 31. " MSIENA31 ,MBIST Controller/Memory Initialization Enable 31" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " MSIENA30 ,MBIST Controller/Memory Initialization Enable 30" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " MSIENA29 ,MBIST Controller/Memory Initialization Enable 29" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 28. " MSIENA28 ,MBIST Controller/Memory Initialization Enable 28" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " MSIENA27 ,MBIST Controller/Memory Initialization Enable 27" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " MSIENA26 ,MBIST Controller/Memory Initialization Enable 26" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 25. " MSIENA25 ,MBIST Controller/Memory Initialization Enable 25" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " MSIENA24 ,MBIST Controller/Memory Initialization Enable 24" "Disabled,Enabled"
|
|
bitfld.long 0x00 23. " MSIENA23 ,MBIST Controller/Memory Initialization Enable 23" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 22. " MSIENA22 ,MBIST Controller/Memory Initialization Enable 22" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " MSIENA21 ,MBIST Controller/Memory Initialization Enable 21" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " MSIENA20 ,MBIST Controller/Memory Initialization Enable 20" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19. " MSIENA19 ,MBIST Controller/Memory Initialization Enable 19" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " MSIENA18 ,MBIST Controller/Memory Initialization Enable 18" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " MSIENA17 ,MBIST Controller/Memory Initialization Enable 17" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " MSIENA16 ,MBIST Controller/Memory Initialization Enable 16" "Disabled,Enabled"
|
|
bitfld.long 0x00 15. " MSIENA15 ,MBIST Controller/Memory Initialization Enable 15" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " MSIENA14 ,MBIST Controller/Memory Initialization Enable 14" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " MSIENA13 ,MBIST Controller/Memory Initialization Enable 13" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " MSIENA12 ,MBIST Controller/Memory Initialization Enable 12" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " MSIENA11 ,MBIST Controller/Memory Initialization Enable 11" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 10. " MSIENA10 ,MBIST Controller/Memory Initialization Enable 10" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " MSIENA9 ,MBIST Controller/Memory Initialization Enable 9" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " MSIENA8 ,MBIST Controller/Memory Initialization Enable 8" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " MSIENA7 ,MBIST Controller/Memory Initialization Enable 7" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " MSIENA6 ,MBIST Controller/Memory Initialization Enable 6" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " MSIENA5 ,MBIST Controller/Memory Initialization Enable 5" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " MSIENA4 ,MBIST Controller/Memory Initialization Enable 4" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " MSIENA3 ,MBIST Controller/Memory Initialization Enable 3" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " MSIENA2 ,MBIST Controller/Memory Initialization Enable 2" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " MSIENA1 ,MBIST Controller/Memory Initialization Enable 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " MSIENA0 ,MBIST Controller/Memory Initialization Enable 0" "Disabled,Enabled"
|
|
group.long 0x64++0x3
|
|
line.long 0x0 "MSTFAIL,Memory Self-Test Fail Status Register"
|
|
eventfld.long 0x00 31. " MSTF31 ,Memory Self-Test Fail Status 31" "Not failed,Failed"
|
|
eventfld.long 0x00 30. " MSTF30 ,Memory Self-Test Fail Status 30" "Not failed,Failed"
|
|
eventfld.long 0x00 29. " MSTF29 ,Memory Self-Test Fail Status 29" "Not failed,Failed"
|
|
textline " "
|
|
eventfld.long 0x00 28. " MSTF28 ,Memory Self-Test Fail Status 28" "Not failed,Failed"
|
|
eventfld.long 0x00 27. " MSTF27 ,Memory Self-Test Fail Status 27" "Not failed,Failed"
|
|
eventfld.long 0x00 26. " MSTF26 ,Memory Self-Test Fail Status 26" "Not failed,Failed"
|
|
textline " "
|
|
eventfld.long 0x00 25. " MSTF25 ,Memory Self-Test Fail Status 25" "Not failed,Failed"
|
|
eventfld.long 0x00 24. " MSTF24 ,Memory Self-Test Fail Status 24" "Not failed,Failed"
|
|
eventfld.long 0x00 23. " MSTF23 ,Memory Self-Test Fail Status 23" "Not failed,Failed"
|
|
textline " "
|
|
eventfld.long 0x00 22. " MSTF22 ,Memory Self-Test Fail Status 22" "Not failed,Failed"
|
|
eventfld.long 0x00 21. " MSTF21 ,Memory Self-Test Fail Status 21" "Not failed,Failed"
|
|
eventfld.long 0x00 20. " MSTF20 ,Memory Self-Test Fail Status 20" "Not failed,Failed"
|
|
textline " "
|
|
eventfld.long 0x00 19. " MSTF19 ,Memory Self-Test Fail Status 19" "Not failed,Failed"
|
|
eventfld.long 0x00 18. " MSTF18 ,Memory Self-Test Fail Status 18" "Not failed,Failed"
|
|
eventfld.long 0x00 17. " MSTF17 ,Memory Self-Test Fail Status 17" "Not failed,Failed"
|
|
textline " "
|
|
eventfld.long 0x00 16. " MSTF16 ,Memory Self-Test Fail Status 16" "Not failed,Failed"
|
|
eventfld.long 0x00 15. " MSTF15 ,Memory Self-Test Fail Status 15" "Not failed,Failed"
|
|
eventfld.long 0x00 14. " MSTF14 ,Memory Self-Test Fail Status 14" "Not failed,Failed"
|
|
textline " "
|
|
eventfld.long 0x00 13. " MSTF13 ,Memory Self-Test Fail Status 13" "Not failed,Failed"
|
|
eventfld.long 0x00 12. " MSTF12 ,Memory Self-Test Fail Status 12" "Not failed,Failed"
|
|
eventfld.long 0x00 11. " MSTF11 ,Memory Self-Test Fail Status 11" "Not failed,Failed"
|
|
textline " "
|
|
eventfld.long 0x00 10. " MSTF10 ,Memory Self-Test Fail Status 10" "Not failed,Failed"
|
|
eventfld.long 0x00 9. " MSTF9 ,Memory Self-Test Fail Status 9" "Not failed,Failed"
|
|
eventfld.long 0x00 8. " MSTF8 ,Memory Self-Test Fail Status 8" "Not failed,Failed"
|
|
textline " "
|
|
eventfld.long 0x00 7. " MSTF7 ,Memory Self-Test Fail Status 7" "Not failed,Failed"
|
|
eventfld.long 0x00 6. " MSTF6 ,Memory Self-Test Fail Status 6" "Not failed,Failed"
|
|
eventfld.long 0x00 5. " MSTF5 ,Memory Self-Test Fail Status 5" "Not failed,Failed"
|
|
textline " "
|
|
eventfld.long 0x00 4. " MSTF4 ,Memory Self-Test Fail Status 4" "Not failed,Failed"
|
|
eventfld.long 0x00 3. " MSTF3 ,Memory Self-Test Fail Status 3" "Not failed,Failed"
|
|
eventfld.long 0x00 2. " MSTF2 ,Memory Self-Test Fail Status 2" "Not failed,Failed"
|
|
textline " "
|
|
eventfld.long 0x00 1. " MSTF1 ,Memory Self-Test Fail Status 1" "Not failed,Failed"
|
|
eventfld.long 0x00 0. " MSTF0 ,Memory Self-Test Fail Status 0" "Not failed,Failed"
|
|
group.long 0x68++0x3
|
|
line.long 0x0 "MSTCGSTAT,MSTC Global Status Register"
|
|
eventfld.long 0x00 8. " MINIDONE ,Memory Hardware Initililization Test Run Complete Status" "Not completed,Completed"
|
|
eventfld.long 0x00 0. " MSTDONE ,Memory Self-Test Run Complete Status" "Not completed,Completed"
|
|
group.long 0x6C++0x3
|
|
line.long 0x0 "MINISTAT,Memory Hardware Initialization Status Register"
|
|
eventfld.long 0x00 31. " MIDONE31 ,Memory Hardware Initialization Status 31" "Not completed,Completed"
|
|
eventfld.long 0x00 30. " MIDONE30 ,Memory Hardware Initialization Status 30" "Not completed,Completed"
|
|
textline " "
|
|
eventfld.long 0x00 29. " MIDONE29 ,Memory Hardware Initialization Status 29" "Not completed,Completed"
|
|
eventfld.long 0x00 28. " MIDONE28 ,Memory Hardware Initialization Status 28" "Not completed,Completed"
|
|
textline " "
|
|
eventfld.long 0x00 27. " MIDONE27 ,Memory Hardware Initialization Status 27" "Not completed,Completed"
|
|
eventfld.long 0x00 26. " MIDONE26 ,Memory Hardware Initialization Status 26" "Not completed,Completed"
|
|
textline " "
|
|
eventfld.long 0x00 25. " MIDONE25 ,Memory Hardware Initialization Status 25" "Not completed,Completed"
|
|
eventfld.long 0x00 24. " MIDONE24 ,Memory Hardware Initialization Status 24" "Not completed,Completed"
|
|
textline " "
|
|
eventfld.long 0x00 23. " MIDONE23 ,Memory Hardware Initialization Status 23" "Not completed,Completed"
|
|
eventfld.long 0x00 22. " MIDONE22 ,Memory Hardware Initialization Status 22" "Not completed,Completed"
|
|
textline " "
|
|
eventfld.long 0x00 21. " MIDONE21 ,Memory Hardware Initialization Status 21" "Not completed,Completed"
|
|
eventfld.long 0x00 20. " MIDONE20 ,Memory Hardware Initialization Status 20" "Not completed,Completed"
|
|
textline " "
|
|
eventfld.long 0x00 19. " MIDONE19 ,Memory Hardware Initialization Status 19" "Not completed,Completed"
|
|
eventfld.long 0x00 18. " MIDONE18 ,Memory Hardware Initialization Status 18" "Not completed,Completed"
|
|
textline " "
|
|
eventfld.long 0x00 17. " MIDONE17 ,Memory Hardware Initialization Status 17" "Not completed,Completed"
|
|
eventfld.long 0x00 16. " MIDONE16 ,Memory Hardware Initialization Status 16" "Not completed,Completed"
|
|
textline " "
|
|
eventfld.long 0x00 15. " MIDONE15 ,Memory Hardware Initialization Status 15" "Not completed,Completed"
|
|
eventfld.long 0x00 14. " MIDONE14 ,Memory Hardware Initialization Status 14" "Not completed,Completed"
|
|
textline " "
|
|
eventfld.long 0x00 13. " MIDONE13 ,Memory Hardware Initialization Status 13" "Not completed,Completed"
|
|
eventfld.long 0x00 12. " MIDONE12 ,Memory Hardware Initialization Status 12" "Not completed,Completed"
|
|
textline " "
|
|
eventfld.long 0x00 11. " MIDONE11 ,Memory Hardware Initialization Status 11" "Not completed,Completed"
|
|
eventfld.long 0x00 10. " MIDONE10 ,Memory Hardware Initialization Status 10" "Not completed,Completed"
|
|
textline " "
|
|
eventfld.long 0x00 9. " MIDONE9 ,Memory Hardware Initialization Status 9" "Not completed,Completed"
|
|
eventfld.long 0x00 8. " MIDONE8 ,Memory Hardware Initialization Status 8" "Not completed,Completed"
|
|
textline " "
|
|
eventfld.long 0x00 7. " MIDONE7 ,Memory Hardware Initialization Status 7" "Not completed,Completed"
|
|
eventfld.long 0x00 6. " MIDONE6 ,Memory Hardware Initialization Status 6" "Not completed,Completed"
|
|
textline " "
|
|
eventfld.long 0x00 5. " MIDONE5 ,Memory Hardware Initialization Status 5" "Not completed,Completed"
|
|
eventfld.long 0x00 4. " MIDONE4 ,Memory Hardware Initialization Status 4" "Not completed,Completed"
|
|
textline " "
|
|
eventfld.long 0x00 3. " MIDONE3 ,Memory Hardware Initialization Status 3" "Not completed,Completed"
|
|
eventfld.long 0x00 2. " MIDONE2 ,Memory Hardware Initialization Status 2" "Not completed,Completed"
|
|
textline " "
|
|
eventfld.long 0x00 1. " MIDONE1 ,Memory Hardware Initialization Status 1" "Not completed,Completed"
|
|
eventfld.long 0x00 0. " MIDONE0 ,Memory Hardware Initialization Status 0" "Not completed,Completed"
|
|
width 13.
|
|
group.long 0x70++0x3
|
|
line.long 0x0 "PLLCTL1,PLL Control Register 1"
|
|
bitfld.long 0x00 31. " ROS ,Reset on PLL Cycle Slip" "No reset,Reset"
|
|
bitfld.long 0x00 29.--30. " MASK_SLIP ,Mask detection of PLL slip" "Enabled,Enabled,Disabled,Enabled"
|
|
bitfld.long 0x00 24.--28. " PLLDIV ,PLL Output Clock Divider" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32"
|
|
textline " "
|
|
bitfld.long 0x00 23. " ROF ,Reset on Oscillator Fail" "No reset,Reset"
|
|
bitfld.long 0x00 16.--21. " REFCLKDIV ,Reference Clock Divider" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64"
|
|
hexmask.long.word 0x00 0.--15. 1. " PLLMUL ,PLL Multiplication Factor"
|
|
group.long 0x74++0x3
|
|
line.long 0x0 "PLLCTL2,PLL Control Register 2"
|
|
bitfld.long 0x00 31. " FMENA ,Frequency Modulation Enable" "Disabled,Enabled"
|
|
hexmask.long.word 0x00 22.--30. 1. " SPREADINGRATE ,Spreadingrate"
|
|
hexmask.long.word 0x00 12.--20. 1. " MULMOD ,Multiplier Correction when Frequency Modulation is enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9.--11. " ODPLL ,Internal PLL Output Divider" "/1,/2,/3,/4,/5,/6,/7,/8"
|
|
hexmask.long.word 0x00 0.--8. 1. " SPR_AMOUNT ,Spreading Amount"
|
|
rgroup.long 0x7C++0x3
|
|
line.long 0x0 "DIEIDL,Die Identification Register Lower Word"
|
|
hexmask.long.word 0x00 22.--31. 1. " LOT ,Lower 10 bits of the device lot number"
|
|
bitfld.long 0x00 16.--21. " WAFER ,Wafer number of the device" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " Y_WAFER ,Y wafer coordinate of the device"
|
|
hexmask.long.byte 0x00 0.--7. 1. " X_WAFER ,X wafer coordinate of the device"
|
|
rgroup.long 0x80++0x3
|
|
line.long 0x0 "DIEIDH,Die Identification Register Upper Word"
|
|
hexmask.long.word 0x00 0.--13. 1. " LOT ,Upper 14 bits of the device lot number"
|
|
width 13.
|
|
group.long 0x88++0x3
|
|
line.long 0x0 "LPOMONCTL,LPO/Clock Monitor Control Register"
|
|
bitfld.long 0x00 24. " BIAS_ENABLE ,Bias Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " OSCFRQCONFIGCNT ,Configures the counter based on OSC frequency" "<= 20MHz,> 20MHz & <= 80MHz"
|
|
textline " "
|
|
sif (cpu()!=("TMS570LS0332")&&cpu()!=("TMS570LS0432"))
|
|
bitfld.long 0x00 8.--12. " HFTRIM[4-0] ,High frequency oscillator trim value" "29.52%,34.24%,38.85%,43.45%,47.99%,52.55%,57.02%,61.46%,65.92%,70.17%,74.55%,78.92%,83.17%,87.43%,91.75%,95.89%,100.00%,104.09%,108.17%,112.32%,116.41%,120.67%,124.42%,128.38%,132.24%,136.15%,140.15%,143.94%,148.02%,151.80%,155.50%,159.35%"
|
|
bitfld.long 0x00 0.--4. " LFTRIM[4-0] ,Low frequency oscillator trim value" "20.67%,25.76%,30.84%,35.90%,40.93%,45.95%,50.97%,55.91%,60.86%,65.78%,70.75%,75.63%,80.61%,85.39%,90.23%,95.11%,100.00%,104.84%,109.51%,114.31%,119.01%,123.75%,128.62%,133.31%,138.03%,142.75%,147.32%,152.02%,156.63%,161.38%,165.90%,170.42%"
|
|
else
|
|
bitfld.long 0x00 8.--11. " HFTRIM[3-0] ,High frequency oscillator trim value" "29.52%,38.85%,47.99%,57.02%,65.92%,74.55%,83.17%,91.75%,100.00%,108.17%,116.41%,124.42%,132.24%,140.15%,148.02%,155.50%"
|
|
bitfld.long 0x00 0.--3. " LFTRIM[3-0] ,Low frequency oscillator trim value" "20.67%,30.84%,40.93%,50.97%,60.86%,70.75%,80.61%,90.23%,100.00%,109.51%,119.01%,128.62%,138.03%,147.32%,156.63%,165.90%"
|
|
endif
|
|
width 13.
|
|
group.long 0x8C++0x3
|
|
line.long 0x0 "CLKTEST,Clock Test Register"
|
|
bitfld.long 0x00 26. " ALTLIMPCLOCKENABLE ,Alternate Limp Clock Enable" "10-MHz LPO,ALTLIMPCLOCK"
|
|
textline " "
|
|
bitfld.long 0x00 25. " RANGEDETCTRL ,Range Detection Control" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 24. " RANGEDETENSSEL ,Range Detection Enable Select" "Hardware,CLKTEST[RANGEDETCTRL]"
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. " CLK_TEST_EN[3:0] ,Clock Test Enable" "Disabled,Disabled,Disabled,Disabled,Disabled,Enabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled"
|
|
textline " "
|
|
sif (cpu()=="RM48L952-PGE"||cpu()=="RM48L952-ZWT"||cpu()=="RM48L950-PGE"||cpu()=="RM48L950-ZWT"||cpu()=="RM48L940-ZWT"||cpu()=="RM48L940-PGE"||cpu()=="RM48L930-ZWT"||cpu()=="RM48L930-PGE"||cpu()=="RM48L750-ZWT"||cpu()=="RM48L750-PGE"||cpu()=="RM48L740-ZWT"||cpu()=="RM48L740-PGE"||cpu()=="RM48L730-ZWT"||cpu()=="RM48L730-PGE"||cpu()=="RM48L550-PGE"||cpu()=="RM48L540-ZWT"||cpu()=="RM48L540-PGE"||cpu()=="RM48L530-ZWT"||cpu()=="RM48L530-PGE"||cpu()=="RM46L852-PGE"||cpu()=="RM46L852-ZWT"||cpu()=="RM46L850-PGE"||cpu()=="RM46L850-ZWT"||cpu()=="RM46L840-ZWT"||cpu()=="RM46L840-PGE"||cpu()=="RM46L830-ZWT"||cpu()=="RM46L830-PGE"||cpu()=="RM46L450-ZWT"||cpu()=="RM46L450-PGE"||cpu()=="RM46L440-ZWT"||cpu()=="RM46L440-PGE"||cpu()=="RM46L430-ZWT"||cpu()=="RM46L430-PGE"||cpu()=="RM48L550-ZWT"||!cpuis("TMS570LS1114*")||!cpuis("TMS570LS1115*")||!cpuis("TMS570LS1224*")||!cpuis("TMS570LS1225*")||!cpuis("TMS570LS1227*"))
|
|
bitfld.long 0x00 8.--11. " SEL_GIO_PIN[3:0] ,Clock Source Valid Signal/Clock Source at Functional GIO Pin Select" "Oscillator,PLL,Reserved,Reserved,Reserved,High frequency clock LPO,Secondary PLL,Reserved,Low frequency clock LPO,Oscillator,Oscillator,Oscillator,Oscillator,Oscillator,Oscillator,Oscillator"
|
|
elif (cpu()=="RM42L432")
|
|
bitfld.long 0x00 8.--11. " SEL_N2HET_PIN[3:0] ,N2HET[2] pin clock source valid/select" "Oscillator,PLL,Reserved,Reserved,Reserved,High frequency clock LPO,Secondary PLL,Reserved,Low frequency clock LPO,Oscillator,Oscillator,Oscillator,Oscillator,Oscillator,Oscillator,Oscillator"
|
|
elif (cpu()==("TMS570LS0332")||cpu()==("TMS570LS0432"))
|
|
bitfld.long 0x00 8.--11. " SEL_N2HET_PIN[3:0] ,N2HET[2] pin clock source valid/select" "Oscillator,PLL,Reserved,Reserved,Reserved,High frequency clock LPO,Reserved,Reserved,Low frequency clock LPO,Oscillator,Oscillator,Oscillator,Oscillator,Oscillator,Oscillator,Oscillator"
|
|
else
|
|
bitfld.long 0x00 8.--11. " SEL_GIO_PIN[3:0] ,Clock Source Valid Signal/Clock Source at Functional GIO Pin Select" "Source 0,Source 1,Source 2,Source 3,Source 4,Source 5,Source 6,Source 7,Source 4/pin,?..."
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " SEL_ECP_PIN[3:0] ,Clock at ECP Pin Select" "Oscillator,PLL,Reserved,EXTCLKIN1,LPO low,LPO high,Secondary PLL,EXCLKIN2,GCLK,RTI Base,Reserved,VCLKA1,VCLKA2,VCLKA3_S,VCLKA4,Flash HD Pump Oscillator"
|
|
width 13.
|
|
group.long 0x90++0x3
|
|
line.long 0x0 "DFTCTRLREG,DFT Control Register"
|
|
bitfld.long 0x00 12.--13. " DFTWRITE ,DFT Logic Access Mode" "Stress/Slow,Stress/Fast,Screen/Slow,Screen/Fast"
|
|
bitfld.long 0x00 8.--9. " DFTREAD ,DFT Logic Access" "Stress/Slow,Stress/Fast,Screen/Slow,Screen/Fast"
|
|
bitfld.long 0x00 0.--3. " TEST_MODE_KEY ,Test Mode Key" "Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Enabled,Disabled,Disabled,Disabled,Disabled,Disabled"
|
|
group.long 0x94++0x3
|
|
line.long 0x0 "DFTCTRLREG2,DFT Control Register"
|
|
bitfld.long 0x00 31. " IMPDF[27] ,DFT Implementation Defined Bit[27]" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " IMPDF[26] ,DFT Implementation Defined Bit[26]" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " IMPDF[25] ,DFT Implementation Defined Bit[25]" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 28. " IMPDF[24] ,DFT Implementation Defined Bit[24]" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " IMPDF[23] ,DFT Implementation Defined Bit[23]" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " IMPDF[22] ,DFT Implementation Defined Bit[22]" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 25. " IMPDF[21] ,DFT Implementation Defined Bit[21]" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " IMPDF[20] ,DFT Implementation Defined Bit[20]" "Disabled,Enabled"
|
|
bitfld.long 0x00 23. " IMPDF[19] ,DFT Implementation Defined Bit[19]" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 22. " IMPDF[18] ,DFT Implementation Defined Bit[18]" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " IMPDF[17] ,DFT Implementation Defined Bit[17]" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " IMPDF[16] ,DFT Implementation Defined Bit[16]" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19. " IMPDF[15] ,DFT Implementation Defined Bit[15]" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " IMPDF[14] ,DFT Implementation Defined Bit[14]" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " IMPDF[13] ,DFT Implementation Defined Bit[13]" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " IMPDF[12] ,DFT Implementation Defined Bit[12]" "Disabled,Enabled"
|
|
bitfld.long 0x00 15. " IMPDF[11] ,DFT Implementation Defined Bit[11]" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " IMPDF[10] ,DFT Implementation Defined Bit[10]" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " IMPDF[9] ,DFT Implementation Defined Bit[9]" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " IMPDF[8] ,DFT Implementation Defined Bit[8]" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " IMPDF[7] ,DFT Implementation Defined Bit[7]" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 10. " IMPDF[6] ,DFT Implementation Defined Bit[6]" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " IMPDF[5] ,DFT Implementation Defined Bit[5]" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " IMPDF[4] ,DFT Implementation Defined Bit[4]" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " IMPDF[3] ,DFT Implementation Defined Bit[3]" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " IMPDF[2] ,DFT Implementation Defined Bit[2]" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " IMPDF[1] ,DFT Implementation Defined Bit[1]" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " IMPDF[0] ,DFT Implementation Defined Bit[0]" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--3. " TEST_MODE_KEY ,Test Mode Key (Internal TI Use Only)" "Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Enabled,Disabled,Disabled,Disabled,Disabled,Disabled"
|
|
width 13.
|
|
group.long 0xA0++0x3
|
|
line.long 0x0 "GPREG1,General Purpose Register 1"
|
|
bitfld.long 0x00 20.--25. " PLL1_FBSLIP_FILTER_COUNT ,FBSLIP down counter programmed value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. " PLL1_RFSLIP_FILTER_KEY ,Configures the system response when a FBSLIP is indicated by the PLL macro" "Reserved,Reserved,Reserved,Reserved,Reserved,Bypassed,Reserved,Reserved,Reserved,Reserved,One-stage synchronization,Reserved,Reserved,Reserved,Reserved,Two-stage synchronization"
|
|
sif (cpu()!=("TMS570LS0332")&&cpu()!=("TMS570LS0432"))
|
|
sif (!cpuis("TMS570LS1114*")&&!cpuis("TMS570LS1115*")&&!cpuis("TMS570LS1224*")&&!cpuis("TMS570LS1225*")&&!cpuis("TMS570LS1227*"))
|
|
textline " "
|
|
bitfld.long 0x00 15. " OUTPUT_BUFFER_LOW_EMI_MODE[15] ,EMI mode for RTP enable" "Enabled,Disabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 14. " OUTPUT_BUFFER_LOW_EMI_MODE[14] ,EMI mode for ADEVT enable" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " OUTPUT_BUFFER_LOW_EMI_MODE[13] ,EMI mode for nERROR enable" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 12. " OUTPUT_BUFFER_LOW_EMI_MODE[12] ,EMI mode for TEST enable" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " OUTPUT_BUFFER_LOW_EMI_MODE[11] ,EMI mode for RTCK enable" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 10. " OUTPUT_BUFFER_LOW_EMI_MODE[10] ,EMI mode for TD0 enable" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " OUTPUT_BUFFER_LOW_EMI_MODE[9] ,EMI mode for TDI enable" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 8. " OUTPUT_BUFFER_LOW_EMI_MODE[8] ,EMI mode for TMS enable" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " OUTPUT_BUFFER_LOW_EMI_MODE[7] ,EMI mode for ETM enable" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 6. " OUTPUT_BUFFER_LOW_EMI_MODE[6] ,EMI mode for EMIF enable" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " OUTPUT_BUFFER_LOW_EMI_MODE[5] ,EMI mode for FlexRay enable" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " OUTPUT_BUFFER_LOW_EMI_MODE[4] ,EMI mode for MiBSPI5 enable" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " OUTPUT_BUFFER_LOW_EMI_MODE[3] ,EMI mode for SPI4 enable" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " OUTPUT_BUFFER_LOW_EMI_MODE[2] ,EMI mode for MiBSPI3 enable" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " OUTPUT_BUFFER_LOW_EMI_MODE[1] ,EMI mode for SPI2 enable" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " OUTPUT_BUFFER_LOW_EMI_MODE[0] ,EMI mode for MiBSPI1 enable" "Enabled,Disabled"
|
|
endif
|
|
hgroup.long 0xA8++0x3
|
|
hide.long 0x0 "IMPFASTS,Imprecise Fault Status Register"
|
|
in
|
|
rgroup.long 0xAC++0x3
|
|
line.long 0x0 "IMPFTADD,Imprecise Fault Write Address Register"
|
|
width 14.
|
|
tree "System Software Interrupt Request Registers"
|
|
group.long 0xB0++0x3
|
|
line.long 0x0 "SSIR1,System Software Interrupt Request 1 Register"
|
|
hexmask.long.byte 0x00 8.--15. 1. " SSKEY1[7:0] ,System Software Interrupt Request Key"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSDATA1[7:0] ,System Software Interrupt Data"
|
|
group.long 0xB4++0x3
|
|
line.long 0x0 "SSIR2,System Software Interrupt Request 2 Register"
|
|
hexmask.long.byte 0x00 8.--15. 1. " SSKEY2[7:0] ,System Software Interrupt 2 Request Key"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSDATA2[7:0] ,System Software Interrupt 2 Data"
|
|
group.long 0xB8++0x3
|
|
line.long 0x0 "SSIR3,System Software Interrupt Request 3 Register"
|
|
hexmask.long.byte 0x00 8.--15. 1. " SSKEY3[7:0] ,System Software Interrupt 3 Request Key"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSDATA3[7:0] ,System Software Interrupt 3 Data"
|
|
group.long 0xBC++0x3
|
|
line.long 0x0 "SSIR4,System Software Interrupt Request 4 Register"
|
|
hexmask.long.byte 0x00 8.--15. 1. " SSKEY4[7:0] ,System Software Interrupt 3 Request Key"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SSDATA4[7:0] ,System Software Interrupt 4 Data"
|
|
tree.end
|
|
width 10.
|
|
group.long 0xC0++0x3
|
|
line.long 0x0 "RAMGCR,RAM Control Register"
|
|
bitfld.long 0x00 16.--19. " RAM_DFT_EN[3:0] ,Functional Mode RAM DFT Port Enable Key" "Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Enabled,Disabled,Disabled,Disabled,Disabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " WST_AENA0 ,eSRAM0 Data Phase Wait State Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " WST_DENA0 ,eSRAM0 Data Phase Wait State Enable" "Disabled,Enabled"
|
|
group.long 0xC4++0x3
|
|
line.long 0x0 "BMMCR1,Bus Matrix Module Control Register1"
|
|
bitfld.long 0x00 0.--3. " MEMSW[3:0] ,Memory Swap Bit Key" "Reserved,Reserved,Reserved,Reserved,Reserved,Swapped,Reserved,Reserved,Reserved,Reserved,Default,?..."
|
|
sif (cpu()!="RM48L952-PGE"&&cpu()!="RM48L952-ZWT"&&cpu()!="RM48L950-PGE"&&cpu()!="RM48L950-ZWT"&&cpu()!="RM48L940-ZWT"&&cpu()!="RM48L940-PGE"&&cpu()!="RM48L930-ZWT"&&cpu()!="RM48L930-PGE"&&cpu()!="RM48L750-ZWT"&&cpu()!="RM48L750-PGE"&&cpu()!="RM48L740-ZWT"&&cpu()!="RM48L740-PGE"&&cpu()!="RM48L730-ZWT"&&cpu()!="RM48L730-PGE"&&cpu()!="RM48L550-PGE"&&cpu()!="RM48L540-ZWT"&&cpu()!="RM48L540-PGE"&&cpu()!="RM48L530-ZWT"&&cpu()!="RM48L530-PGE"&&cpu()!="RM46L852-PGE"&&cpu()!="RM46L852-ZWT"&&cpu()!="RM46L850-PGE"&&cpu()!="RM46L850-ZWT"&&cpu()!="RM46L840-ZWT"&&cpu()!="RM46L840-PGE"&&cpu()!="RM46L830-ZWT"&&cpu()!="RM46L830-PGE"&&cpu()!="RM46L450-ZWT"&&cpu()!="RM46L450-PGE"&&cpu()!="RM46L440-ZWT"&&cpu()!="RM46L440-PGE"&&cpu()!="RM46L430-ZWT"&&cpu()!="RM46L430-PGE"&&cpu()!="RM42L432"&&cpu()!="RM48L550-ZWT"&&cpu()!=("TMS570LS0332")&&cpu()!=("TMS570LS0432")&&!cpuis("TMS570LS1114*")&&!cpuis("TMS570LS1115*")&&!cpuis("TMS570LS1224*")&&!cpuis("TMS570LS1225*")&&!cpuis("TMS570LS1227*"))
|
|
group.long 0xC8++0x3
|
|
line.long 0x0 "BMMCR2,Bus Matrix Module Control Register2"
|
|
endif
|
|
group.long 0xCC++0x3
|
|
line.long 0x0 "CPURSTCR,CPU Reset Control Register"
|
|
bitfld.long 0x00 0. " CPU_RESET ,Cpu reset" "No reset,Reset"
|
|
group.long 0xD0++0x3
|
|
line.long 0x0 "CLKCNTL,Clock Control Register"
|
|
bitfld.long 0x00 24.--27. " VCLKR2[3:0] ,VBUS Clock 2 Ratio" "HCLK,HCLK/2,HCLK/3,HCLK/4,HCLK/5,HCLK/6,HCLK/7,HCLK/8,HCLK/9,HCLK/10,HCLK/11,HCLK/12,HCLK/13,HCLK/14,HCLK/15,HCLK/16"
|
|
bitfld.long 0x00 16.--19. " VCLKR[3:0] ,VBUS Clock Ratio" "HCLK,HCLK/2,HCLK/3,HCLK/4,HCLK/5,HCLK/6,HCLK/7,HCLK/8,HCLK/9,HCLK/10,HCLK/11,HCLK/12,HCLK/13,HCLK/14,HCLK/15,HCLK/16"
|
|
bitfld.long 0x00 8. " PENA ,Peripheral Enable" "Reset,No reset"
|
|
group.long 0xD4++0x3
|
|
line.long 0x0 "ECPCNTRL,ECP Control Register"
|
|
bitfld.long 0x00 24. " ECPSSEL ,ECP Source Clock Select for ECP Module" "Oscillator,VCLK"
|
|
bitfld.long 0x00 23. " ECPCOS ,ECP Continue on Suspend" "Suspended,Continue"
|
|
bitfld.long 0x00 16.--17. " ECPINSEL ,Select ECP Input Clock Source" "Tied Low,HCLK,External,Tied Low"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--15. 1. " ECPDIV[15:0] ,ECP Divider Value"
|
|
group.long 0xDC++0x3
|
|
line.long 0x0 "DEVCR1,DEV Parity Control Register1"
|
|
bitfld.long 0x00 0.--3. " DEVPARSEL ,Device Parity Select Bit Key" "Reserved,Reserved,Reserved,Reserved,Reserved,Even,Reserved,Reserved,Reserved,Reserved,Odd,?..."
|
|
group.long 0xE0++0x3
|
|
line.long 0x0 "SYSECR,System Exception Control Register"
|
|
bitfld.long 0x00 14.--15. " RESET[1:0] ,Software Reset" "Reset,No reset,Reset,Reset"
|
|
width 10.
|
|
group.long 0xE4++0x3
|
|
line.long 0x0 "SYSESR,System Exception Status Register"
|
|
eventfld.long 0x00 15. " PORST ,Power-Up Reset" "No reset,Reset"
|
|
eventfld.long 0x00 14. " OSCRST ,Oscillator Failure/PLL Cycle Slip Reset" "No reset,Reset"
|
|
eventfld.long 0x00 13. " WDRST ,Watchdog Reset Flag" "No reset,Reset"
|
|
textline " "
|
|
eventfld.long 0x00 5. " CPURST ,CPU Reset Flag" "No reset,Reset"
|
|
eventfld.long 0x00 4. " SWRST ,Software Reset Flag" "No reset,Reset"
|
|
eventfld.long 0x00 3. " EXTRST ,External Reset Flag" "No reset,Reset"
|
|
textline " "
|
|
eventfld.long 0x00 0. " MPMODE ,This indicates the current memory protection unit (MPU) mode" "Disabled,Enabled"
|
|
group.long 0xE8++0x3
|
|
line.long 0x0 "SYSTASR,System Test Abort Status Register"
|
|
bitfld.long 0x00 0.--4. " EFUSE_ABORT[4:0] ,Test Abort Status Flag" "Read: Last operation,Read: Controller times out,Read: Autoload/Not find FuseROM,Read: Autoload/Scan chain,Read: Autoload/Not completed operation,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Write: Cleared"
|
|
width 10.
|
|
group.long 0xEC++0x3
|
|
line.long 0x0 "GLBSTAT,Global Status Register"
|
|
eventfld.long 0x00 9. " FBSLIP ,Over Cycle Slip Detection of PLL" "Not detected,Detected"
|
|
eventfld.long 0x00 8. " RFSLIP ,Under Cycle Slip Detection of PLL" "Not detected,Detected"
|
|
eventfld.long 0x00 0. " OSCFAIL ,Oscillator Fail Flag" "Not failed,Failed"
|
|
rgroup.long 0xF0++0x3
|
|
line.long 0x0 "DEVID,Device Identification Register"
|
|
bitfld.long 0x00 31. " CP15 ,CP15 CPU" "CP15,No CP15"
|
|
hexmask.long.word 0x00 17.--30. 1. " UNIQUE_ID ,Device ID"
|
|
bitfld.long 0x00 13.--16. " TECH ,Device Manufacture Process Technology" "C05,F05,C035,F035,C021,F021,?..."
|
|
textline " "
|
|
bitfld.long 0x00 12. " I/O_VOLTAGE ,Input/Output Voltage" "3.3 V,5 V"
|
|
bitfld.long 0x00 11. " PERIPHERAL_PARITY ,Peripheral Parity" "No parity,Parity"
|
|
bitfld.long 0x00 9.--10. " FLASH_ECC ,Program Memory Parity Present" "Not protected,Single bit,ECC,?..."
|
|
textline " "
|
|
bitfld.long 0x00 8. " RAM_RECC ,RAM ECC" "No ECC,ECC"
|
|
hexmask.long.byte 0x00 3.--7. 1. " VERSION ,Version"
|
|
hexmask.long.byte 0x00 0.--2. 1. " PLATFORM_ID ,The TMS570Px Platform ID"
|
|
hgroup.long 0xF4++0x3
|
|
hide.long 0x0 "SSIVEC,Software Interrupt Vector Register"
|
|
in
|
|
width 10.
|
|
group.long 0xF8++0x3
|
|
line.long 0x0 "SSIF,System Software Interrupt Flag Register"
|
|
eventfld.long 0x00 3. " SSI_FLAG4 ,System Software Interrupt Flag 4" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 2. " SSI_FLAG43 ,System Software Interrupt Flag 3" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 1. " SSI_FLAG42 ,System Software Interrupt Flag 2" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 0. " SSI_FLAG41 ,System Software Interrupt Flag 1" "No interrupt,Interrupt"
|
|
width 11.
|
|
endif
|
|
tree.end
|
|
tree "SYS2 (Secondary System Registers)"
|
|
base ad:0xFFFFE100
|
|
sif (cpuis("TMS570LS09*")||cpuis("TMS570LS07*")||cpuis("TMS570LS0232"))
|
|
endian.be
|
|
endif
|
|
width 15.
|
|
sif (cpu()!="RM42L432"&&cpu()!=("TMS570LS0332")&&cpu()!=("TMS570LS0432")&&!cpuis("TMS570LS09*")&&!cpuis("TMS570LS07*")&&!cpuis("TMS570LS0232"))
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "PLLCTL3,PLL Control Register 3"
|
|
bitfld.long 0x00 29.--31. " ODPLL2 ,Internal PLL output divider" "/1,/2,/3,/4,/5,/6,/7,/8"
|
|
bitfld.long 0x00 24.--28. " PLLDIV2 ,PLL#2 output clock divider" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32"
|
|
newline
|
|
bitfld.long 0x00 16.--21. " REFCLKDIV2 ,Reference clock divider" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64"
|
|
hexmask.long.word 0x00 0.--15. 1. " PLL_MUL2 ,PLL multiplication"
|
|
endif
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "STCLKDIV,CPU Logic BIST Clock Divider"
|
|
bitfld.long 0x00 24.--26. " CLKDIV ,Clock divider/prescaler for CPU clock during logic BIST" "/1,/2,/3,/4,/5,/6,/7,/8"
|
|
sif !cpuis("RM48L952-PGE")&&!cpuis("RM48L952-ZWT")&&!cpuis("RM48L952-PGE")&&!cpuis("RM48L952-ZWT")&&!cpuis("RM48L950-PGE")&&!cpuis("RM48L950-ZWT")&&!cpuis("RM48L940-ZWT")&&!cpuis("RM48L940-PGE")&&!cpuis("RM48L930-ZWT")&&!cpuis("RM48L930-PGE")&&!cpuis("RM48L750-ZWT")&&!cpuis("RM48L750-PGE")&&!cpuis("RM48L740-ZWT")&&!cpuis("RM48L740-PGE")&&!cpuis("RM48L730-ZWT")&&!cpuis("RM48L730-PGE")&&!cpuis("RM48L550-PGE")&&!cpuis("RM48L540-ZWT")&&!cpuis("RM48L540-PGE")&&!cpuis("RM48L530-ZWT")&&!cpuis("RM48L530-PGE")&&!cpuis("RM48L550-ZWT")&&!cpuis("RM42L432")&&!cpuis("TMS570LS0332")&&!cpuis("TMS570LS0432")&&!cpuis("TMS570LS1114*")&&!cpuis("TMS570LS1115*")&&!cpuis("TMS570LS1224*")&&!cpuis("TMS570LS1225*")&&!cpuis("TMS570LS1227*")&&!cpuis("TMS570LS0232")&&!cpuis("TMS570LS3137-EP")
|
|
sif cpuis("RM46L852-PGE")||cpuis("RM46L852-ZWT")||cpuis("RM46L850-PGE")||cpuis("RM46L850-ZWT")||cpuis("RM46L840-ZWT")||cpuis("RM46L840-PGE")||cpuis("RM46L830-ZWT")||cpuis("RM46L830-PGE")||cpuis("RM46L450-ZWT")||cpuis("RM46L450-PGE")||cpuis("RM46L440-ZWT")||cpuis("RM46L440-PGE")||cpuis("RM46L430-ZWT")||cpuis("RM46L430-PGE")||cpuis("TMS570LS09*")||cpuis("TMS570LS07*")
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "ECPCNTL,ECP Control Register 1"
|
|
bitfld.long 0x00 24. " ECPSSEL ,Allows the selection between VCLK and OSCIN as the clock source for ECLK2" "VCLK,OSCIN"
|
|
bitfld.long 0x00 23. " ECPCOS ,ECP continue on suspend" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 16.--17. " ECPINSEL ,Select ECP input clock source" "Tied Low,HCLK,External clock,Tied Low"
|
|
hexmask.long.word 0x00 0.--15. 1. " ECPDIV ,ECP divider value"
|
|
else
|
|
group.long 0x0C++0xB
|
|
line.long 0x00 "CLKHB_GLBREG,Clock Hibernate Mode Global Enable Register"
|
|
line.long 0x04 "CLKHB_RTIDREG,Clocked Hibernate RTI Domain Control Register"
|
|
line.long 0x08 "HBCD_STAT,Hibernate Clock Domain Status Register"
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "CLKTRMI1,Clock Trim 1 Register"
|
|
endif
|
|
endif
|
|
sif !cpuis("TMS570LS0232")
|
|
sif (cpu()!="RM42L432"||cpu()!=("TMS570LS0332")&&cpu()!=("TMS570LS0432"))
|
|
group.long 0x3C++0x03
|
|
line.long 0x00 "CLK2CNTRL,Clock 2 Control Register"
|
|
sif (cpuis("TMS570LS09*")||cpuis("TMS570LS07*"))
|
|
bitfld.long 0x00 8.--11. " VCLK4R ,VBUS clock4 ratio" "HCLK,HCLK/2,HCLK/3,HCLK/4,HCLK/5,HCLK/6,HCLK/7,HCLK/8,HCLK/9,HCLK/10,HCLK/11,HCLK/12,HCLK/13,HCLK/14,HCLK/15,HCLK/16"
|
|
else
|
|
bitfld.long 0x00 0.--3. " VCLK3R ,VBUS clock3 ratio" "HCLK,HCLK/2,HCLK/3,HCLK/4,HCLK/5,HCLK/6,HCLK/7,HCLK/8,HCLK/9,HCLK/10,HCLK/11,HCLK/12,HCLK/13,HCLK/14,HCLK/15,HCLK/16"
|
|
endif
|
|
sif (!cpuis("TMS570LS09*")&&!cpuis("TMS570LS07*"))
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "VCLKACON1,Peripheral Asynchronous Clock Configuration 1 Register"
|
|
bitfld.long 0x00 24.--26. " VCLKA4R ,Clock divider for the VCLKA4 source" "VCLKA4,VCLKA4/2,VCLKA4/3,VCLKA4/4,VCLKA4/5,VCLKA4/6,VCLKA4/7,VCLKA4/8"
|
|
bitfld.long 0x00 20. " VCLKA4_DIV_CDDIS ,Disable the VCLKA4 divider output" "No,Yes"
|
|
newline
|
|
sif (cpu()==("TMS570LS0332")||cpu()==("TMS570LS0432")||cpuis("TMS570LS1114*")||cpuis("TMS570LS1115*")||cpuis("TMS570LS1224*")||cpuis("TMS570LS1225*")||cpuis("TMS570LS1227*"))
|
|
bitfld.long 0x00 16.--19. " VCLKA4S ,Peripheral asynchronous clock4 source" "Source 0,Source 1,,Source 3,Source 4,Source 5,Source 6,Source 7,VCLK,VCLK,VCLK,VCLK,VCLK,VCLK,VCLK,VCLK"
|
|
newline
|
|
else
|
|
bitfld.long 0x00 16.--19. " VCLKA4S ,Peripheral asynchronous clock4 source" "Source 0,Source 1,Source 2,Source 3,Source 4,Source 5,Source 6,Source 7,VCLK,VCLK,VCLK,VCLK,VCLK,VCLK,VCLK,VCLK"
|
|
newline
|
|
endif
|
|
sif !cpuis("TMS570LS3137-EP")
|
|
bitfld.long 0x00 8.--10. " VCLKA3R ,Clock divider for the VCLKA3 source" "VCLKA3,VCLKA3/2,VCLKA3/3,VCLKA3/4,VCLKA3/5,VCLKA3/6,VCLKA3/7,VCLKA3/8"
|
|
bitfld.long 0x00 4. " VCLKA3_DIV_CDDIS ,Disable the VCLKA3 divider output" "No,Yes"
|
|
newline
|
|
sif (cpu()==("TMS570LS0332")||cpu()==("TMS570LS0432")||cpuis("TMS570LS1114*")||cpuis("TMS570LS1115*")||cpuis("TMS570LS1224*")||cpuis("TMS570LS1225*")||cpuis("TMS570LS1227*"))
|
|
bitfld.long 0x00 0.--3. " VCLKA3S ,Peripheral asynchronous clock3 source" "Source 0,Source 1,,Source 3,Source 4,Source 5,Source 6,Source 7,VCLK,VCLK,VCLK,VCLK,VCLK,VCLK,VCLK,VCLK"
|
|
else
|
|
bitfld.long 0x00 0.--3. " VCLKA3S ,Peripheral asynchronous clock3 source" "Source 0,Source 1,Source 2,Source 3,Source 4,Source 5,Source 6,Source 7,VCLK,VCLK,VCLK,VCLK,VCLK,VCLK,VCLK,VCLK"
|
|
endif
|
|
endif
|
|
endif
|
|
endif
|
|
endif
|
|
group.long 0x70++0x03
|
|
line.long 0x00 "CLKSLIP,Clock Slip Register"
|
|
sif (cpuis("TMS570LS09*")||cpuis("TMS570LS07*")||cpuis("TMS570LS0232"))
|
|
bitfld.long 0x00 8.--13. " PLL1_SLIP_FILTER_COUNT ,Configure the count for the filtered PLL slip" "Disabled,Every slip recognized,At least 2 HF LPO cycles,At least 3 HF LPO cycles,At least 4 HF LPO cycles,At least 5 HF LPO cycles,At least 6 HF LPO cycles,At least 7 HF LPO cycles,At least 8 HF LPO cycles,At least 9 HF LPO cycles,At least 10 HF LPO cycles,At least 11 HF LPO cycles,At least 12 HF LPO cycles,At least 13 HF LPO cycles,At least 14 HF LPO cycles,At least 15 HF LPO cycles,At least 16 HF LPO cycles,At least 17 HF LPO cycles,At least 18 HF LPO cycles,At least 19 HF LPO cycles,At least 20 HF LPO cycles,At least 21 HF LPO cycles,At least 22 HF LPO cycles,At least 23 HF LPO cycles,At least 24 HF LPO cycles,At least 25 HF LPO cycles,At least 26 HF LPO cycles,At least 27 HF LPO cycles,At least 28 HF LPO cycles,At least 29 HF LPO cycles,At least 30 HF LPO cycles,At least 31 HF LPO cycles,At least 32 HF LPO cycles,At least 33 HF LPO cycles,At least 34 HF LPO cycles,At least 35 HF LPO cycles,At least 36 HF LPO cycles,At least 37 HF LPO cycles,At least 38 HF LPO cycles,At least 39 HF LPO cycles,At least 40 HF LPO cycles,At least 41 HF LPO cycles,At least 42 HF LPO cycles,At least 43 HF LPO cycles,At least 44 HF LPO cycles,At least 45 HF LPO cycles,At least 46 HF LPO cycles,At least 47 HF LPO cycles,At least 48 HF LPO cycles,At least 49 HF LPO cycles,At least 50 HF LPO cycles,At least 51 HF LPO cycles,At least 52 HF LPO cycles,At least 53 HF LPO cycles,At least 54 HF LPO cycles,At least 55 HF LPO cycles,At least 56 HF LPO cycles,At least 57 HF LPO cycles,At least 58 HF LPO cycles,At least 59 HF LPO cycles,At least 60 HF LPO cycles,At least 61 HF LPO cycles,At least 62 HF LPO cycles,At least 63 HF LPO cycles"
|
|
newline
|
|
else
|
|
bitfld.long 0x00 8.--13. " PLL1_SLIP_FILTER_COUNT ,Configure the count for the filtered PLL slip" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 0.--3. " PLL1_SLIP_FILTER_KEY ,Enable the PLL filtering" "Enabled,Enabled,Enabled,Enabled,Enabled,Disabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,?..."
|
|
group.long 0xEC++0x03
|
|
line.long 0x00 "EFC_CTLREG,EFUSE Controller Control Register"
|
|
bitfld.long 0x00 0.--3. " EFC_INSTR_WEN ,Enable user write of 4 EFUSE controller instructions" "Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Enabled,Disabled,Disabled,Disabled,Disabled,Disabled"
|
|
rgroup.long 0xF0++0x0F
|
|
line.long 0x00 "DIEIDL_REG0,Die Identification Register Lower Word"
|
|
sif (cpuis("TMS570LS09*")||cpuis("TMS570LS07*")||cpuis("TMS570LS0232")||cpuis("TMS570LS3137-EP"))
|
|
hexmask.long.byte 0x00 24.--31. 1. " WAFER# ,Wafer number of the device"
|
|
hexmask.long.word 0x00 12.--23. 1. " Y_WAFER_COORDINATE ,Y wafer coordinate of the device"
|
|
hexmask.long.word 0x00 0.--11. 1. " X_WAFER_COORDINATE ,X wafer coordinate of the device"
|
|
endif
|
|
line.long 0x04 "DIEIDH_REG1,Die Identification Register Upper Word"
|
|
sif (cpuis("TMS570LS09*")||cpuis("TMS570LS07*")||cpuis("TMS570LS0232")||cpuis("TMS570LS3137-EP"))
|
|
hexmask.long.tbyte 0x04 0.--23. 1. " LOT# ,Device lot number"
|
|
endif
|
|
line.long 0x08 "DIEIDH_REG2,Die Identification Register Lower Word"
|
|
line.long 0x0C "DIEIDH_REG3,Die Identification Register Upper Word"
|
|
sif (cpuis("TMS570LS09*")||cpuis("TMS570LS07*")||cpuis("TMS570LS0232"))
|
|
endian.le
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
tree "PCR (Peripheral Central Resource)"
|
|
base ad:0xFFFFE000
|
|
sif (cpuis("TMS570LS09*")||cpuis("TMS570LS07*")||cpuis("TMS570LS0232"))
|
|
endian.be
|
|
endif
|
|
width 17.
|
|
tree "PCR Protection Registers"
|
|
tree "PCR Memory Protection Registers"
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "PMPROTSET/CLR_0,Set/Clear Register To Protect PCS Frames 0 To 31"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x10 31. " PCS31PROT ,Peripheral memory frame protection 31" "Not protected,Protected"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x10 30. " PCS30PROT ,Peripheral memory frame protection 30" "Not protected,Protected"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x10 29. " PCS29PROT ,Peripheral memory frame protection 29" "Not protected,Protected"
|
|
textline " "
|
|
setclrfld.long 0x00 28. 0x00 28. 0x10 28. " PCS28PROT ,Peripheral memory frame protection 28" "Not protected,Protected"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x10 27. " PCS27PROT ,Peripheral memory frame protection 27" "Not protected,Protected"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x10 26. " PCS26PROT ,Peripheral memory frame protection 26" "Not protected,Protected"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x10 25. " PCS25PROT ,Peripheral memory frame protection 25" "Not protected,Protected"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x10 24. " PCS24PROT ,Peripheral memory frame protection 24" "Not protected,Protected"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x10 23. " PCS23PROT ,Peripheral memory frame protection 23" "Not protected,Protected"
|
|
textline " "
|
|
setclrfld.long 0x00 22. 0x00 22. 0x10 22. " PCS22PROT ,Peripheral memory frame protection 22" "Not protected,Protected"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x10 21. " PCS21PROT ,Peripheral memory frame protection 21" "Not protected,Protected"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x10 20. " PCS20PROT ,Peripheral memory frame protection 20" "Not protected,Protected"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x10 19. " PCS19PROT ,Peripheral memory frame protection 19" "Not protected,Protected"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x10 18. " PCS18PROT ,Peripheral memory frame protection 18" "Not protected,Protected"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x10 17. " PCS17PROT ,Peripheral memory frame protection 17" "Not protected,Protected"
|
|
textline " "
|
|
setclrfld.long 0x00 16. 0x00 16. 0x10 16. " PCS16PROT ,Peripheral memory frame protection 16" "Not protected,Protected"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x10 15. " PCS15PROT ,Peripheral memory frame protection 15" "Not protected,Protected"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x10 14. " PCS14PROT ,Peripheral memory frame protection 14" "Not protected,Protected"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x10 13. " PCS13PROT ,Peripheral memory frame protection 13" "Not protected,Protected"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x10 12. " PCS12PROT ,Peripheral memory frame protection 12" "Not protected,Protected"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x10 11. " PCS11PROT ,Peripheral memory frame protection 11" "Not protected,Protected"
|
|
textline " "
|
|
setclrfld.long 0x00 10. 0x00 10. 0x10 10. " PCS10PROT ,Peripheral memory frame protection 10" "Not protected,Protected"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x10 9. " PCS9PROT ,Peripheral memory frame protection 9" "Not protected,Protected"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x10 8. " PCS8PROT ,Peripheral memory frame protection 8" "Not protected,Protected"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x10 7. " PCS7PROT ,Peripheral memory frame protection 7" "Not protected,Protected"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x10 6. " PCS6PROT ,Peripheral memory frame protection 6" "Not protected,Protected"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x10 5. " PCS5PROT ,Peripheral memory frame protection 5" "Not protected,Protected"
|
|
textline " "
|
|
setclrfld.long 0x00 4. 0x00 4. 0x10 4. " PCS4PROT ,Peripheral memory frame protection 4" "Not protected,Protected"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x10 3. " PCS3PROT ,Peripheral memory frame protection 3" "Not protected,Protected"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x10 2. " PCS2PROT ,Peripheral memory frame protection 2" "Not protected,Protected"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x10 1. " PCS1PROT ,Peripheral memory frame protection 1" "Not protected,Protected"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x10 0. " PCS0PROT ,Peripheral memory frame protection 0" "Not protected,Protected"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "PMPROTSET/CLR_1,Set/Clear Register To Protect PCS Frames 32 To 64"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x10 31. " PCS63PROT ,Peripheral memory frame protection 63" "Not protected,Protected"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x10 30. " PCS62PROT ,Peripheral memory frame protection 62" "Not protected,Protected"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x10 29. " PCS61PROT ,Peripheral memory frame protection 61" "Not protected,Protected"
|
|
textline " "
|
|
setclrfld.long 0x00 28. 0x00 28. 0x10 28. " PCS60PROT ,Peripheral memory frame protection 60" "Not protected,Protected"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x10 27. " PCS59PROT ,Peripheral memory frame protection 59" "Not protected,Protected"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x10 26. " PCS58PROT ,Peripheral memory frame protection 58" "Not protected,Protected"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x10 25. " PCS57PROT ,Peripheral memory frame protection 57" "Not protected,Protected"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x10 24. " PCS56PROT ,Peripheral memory frame protection 56" "Not protected,Protected"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x10 23. " PCS55PROT ,Peripheral memory frame protection 55" "Not protected,Protected"
|
|
textline " "
|
|
setclrfld.long 0x00 22. 0x00 22. 0x10 22. " PCS54PROT ,Peripheral memory frame protection 54" "Not protected,Protected"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x10 21. " PCS53PROT ,Peripheral memory frame protection 53" "Not protected,Protected"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x10 20. " PCS52PROT ,Peripheral memory frame protection 52" "Not protected,Protected"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x10 19. " PCS51PROT ,Peripheral memory frame protection 51" "Not protected,Protected"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x10 18. " PCS50PROT ,Peripheral memory frame protection 50" "Not protected,Protected"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x10 17. " PCS49PROT ,Peripheral memory frame protection 49" "Not protected,Protected"
|
|
textline " "
|
|
setclrfld.long 0x00 16. 0x00 16. 0x10 16. " PCS48PROT ,Peripheral memory frame protection 48" "Not protected,Protected"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x10 15. " PCS47PROT ,Peripheral memory frame protection 47" "Not protected,Protected"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x10 14. " PCS46PROT ,Peripheral memory frame protection 46" "Not protected,Protected"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x10 13. " PCS45PROT ,Peripheral memory frame protection 45" "Not protected,Protected"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x10 12. " PCS44PROT ,Peripheral memory frame protection 44" "Not protected,Protected"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x10 11. " PCS43PROT ,Peripheral memory frame protection 43" "Not protected,Protected"
|
|
textline " "
|
|
setclrfld.long 0x00 10. 0x00 10. 0x10 10. " PCS42PROT ,Peripheral memory frame protection 42" "Not protected,Protected"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x10 9. " PCS41PROT ,Peripheral memory frame protection 41" "Not protected,Protected"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x10 8. " PCS40PROT ,Peripheral memory frame protection 40" "Not protected,Protected"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x10 7. " PCS39PROT ,Peripheral memory frame protection 39" "Not protected,Protected"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x10 6. " PCS38PROT ,Peripheral memory frame protection 38" "Not protected,Protected"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x10 5. " PCS37PROT ,Peripheral memory frame protection 37" "Not protected,Protected"
|
|
textline " "
|
|
setclrfld.long 0x00 4. 0x00 4. 0x10 4. " PCS36PROT ,Peripheral memory frame protection 36" "Not protected,Protected"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x10 3. " PCS35PROT ,Peripheral memory frame protection 35" "Not protected,Protected"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x10 2. " PCS34PROT ,Peripheral memory frame protection 34" "Not protected,Protected"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x10 1. " PCS33PROT ,Peripheral memory frame protection 33" "Not protected,Protected"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x10 0. " PCS32PROT ,Peripheral memory frame protection 32" "Not protected,Protected"
|
|
tree.end
|
|
textline " "
|
|
width 16.
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "PPROTSET/CLR_0,Set/Clear Register To Protect The 32 Quadrants Of PS0 To PS7"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x20 31. " PCS7QUAD3PROT ,Peripheral select 7 quadrant 3 protection" "Not protected,Protected"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x20 30. " PCS7QUAD2PROT ,Peripheral select 7 quadrant 2 protection" "Not protected,Protected"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x20 29. " PCS7QUAD1PROT ,Peripheral select 7 quadrant 1 protection" "Not protected,Protected"
|
|
textline " "
|
|
setclrfld.long 0x00 28. 0x00 28. 0x20 28. " PCS7QUAD0PROT ,Peripheral select 7 quadrant 0 protection" "Not protected,Protected"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x20 27. " PCS6QUAD3PROT ,Peripheral select 6 quadrant 3 protection" "Not protected,Protected"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x20 26. " PCS6QUAD2PROT ,Peripheral select 6 quadrant 2 protection" "Not protected,Protected"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x20 25. " PCS6QUAD1PROT ,Peripheral select 6 quadrant 1 protection" "Not protected,Protected"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x20 24. " PCS6QUAD0PROT ,Peripheral select 6 quadrant 0 protection" "Not protected,Protected"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x20 23. " PCS5QUAD3PROT ,Peripheral select 5 quadrant 3 protection" "Not protected,Protected"
|
|
textline " "
|
|
setclrfld.long 0x00 22. 0x00 22. 0x20 22. " PCS5QUAD2PROT ,Peripheral select 5 quadrant 2 protection" "Not protected,Protected"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x20 21. " PCS5QUAD1PROT ,Peripheral select 5 quadrant 1 protection" "Not protected,Protected"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x20 20. " PCS5QUAD0PROT ,Peripheral select 5 quadrant 0 protection" "Not protected,Protected"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x20 19. " PCS4QUAD3PROT ,Peripheral select 4 quadrant 3 protection" "Not protected,Protected"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x20 18. " PCS4QUAD2PROT ,Peripheral select 4 quadrant 2 protection" "Not protected,Protected"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x20 17. " PCS4QUAD1PROT ,Peripheral select 4 quadrant 1 protection" "Not protected,Protected"
|
|
textline " "
|
|
setclrfld.long 0x00 16. 0x00 16. 0x20 16. " PCS4QUAD0PROT ,Peripheral select 4 quadrant 0 protection" "Not protected,Protected"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x20 15. " PCS3QUAD3PROT ,Peripheral select 3 quadrant 3 protection" "Not protected,Protected"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x20 14. " PCS3QUAD2PROT ,Peripheral select 3 quadrant 2 protection" "Not protected,Protected"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x20 13. " PCS3QUAD1PROT ,Peripheral select 3 quadrant 1 protection" "Not protected,Protected"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x20 12. " PCS3QUAD0PROT ,Peripheral select 3 quadrant 0 protection" "Not protected,Protected"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x20 11. " PCS2QUAD3PROT ,Peripheral select 2 quadrant 3 protection" "Not protected,Protected"
|
|
textline " "
|
|
setclrfld.long 0x00 10. 0x00 10. 0x20 10. " PCS2QUAD2PROT ,Peripheral select 2 quadrant 2 protection" "Not protected,Protected"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x20 9. " PCS2QUAD1PROT ,Peripheral select 2 quadrant 1 protection" "Not protected,Protected"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x20 8. " PCS2QUAD0PROT ,Peripheral select 2 quadrant 0 protection" "Not protected,Protected"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x20 7. " PCS1QUAD3PROT ,Peripheral select 1 quadrant 3 protection" "Not protected,Protected"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x20 6. " PCS1QUAD2PROT ,Peripheral select 1 quadrant 2 protection" "Not protected,Protected"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x20 5. " PCS1QUAD1PROT ,Peripheral select 1 quadrant 1 protection" "Not protected,Protected"
|
|
textline " "
|
|
setclrfld.long 0x00 4. 0x00 4. 0x20 4. " PCS1QUAD0PROT ,Peripheral select 1 quadrant 0 protection" "Not protected,Protected"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x20 3. " PCS0QUAD3PROT ,Peripheral select 0 quadrant 3 protection" "Not protected,Protected"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x20 2. " PCS0QUAD2PROT ,Peripheral select 0 quadrant 2 protection" "Not protected,Protected"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x20 1. " PCS0QUAD1PROT ,Peripheral select 0 quadrant 1 protection" "Not protected,Protected"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x20 0. " PCS0QUAD0PROT ,Peripheral select 0 quadrant 0 protection" "Not protected,Protected"
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "PPROTSET/CLR_1,Set/Clear Register To Protect The 32 Quadrants Of PS8 To PS15"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x20 31. " PCS15QUAD3PROT ,Peripheral select 15 quadrant 3 protection" "Not protected,Protected"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x20 30. " PCS15QUAD2PROT ,Peripheral select 15 quadrant 2 protection" "Not protected,Protected"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x20 29. " PCS15QUAD1PROT ,Peripheral select 15 quadrant 1 protection" "Not protected,Protected"
|
|
textline " "
|
|
setclrfld.long 0x00 28. 0x00 28. 0x20 28. " PCS15QUAD0PROT ,Peripheral select 15 quadrant 0 protection" "Not protected,Protected"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x20 27. " PCS14QUAD3PROT ,Peripheral select 14 quadrant 3 protection" "Not protected,Protected"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x20 26. " PCS14QUAD2PROT ,Peripheral select 14 quadrant 2 protection" "Not protected,Protected"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x20 25. " PCS14QUAD1PROT ,Peripheral select 14 quadrant 1 protection" "Not protected,Protected"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x20 24. " PCS14QUAD0PROT ,Peripheral select 14 quadrant 0 protection" "Not protected,Protected"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x20 23. " PCS13QUAD3PROT ,Peripheral select 13 quadrant 3 protection" "Not protected,Protected"
|
|
textline " "
|
|
setclrfld.long 0x00 22. 0x00 22. 0x20 22. " PCS13QUAD2PROT ,Peripheral select 13 quadrant 2 protection" "Not protected,Protected"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x20 21. " PCS13QUAD1PROT ,Peripheral select 13 quadrant 1 protection" "Not protected,Protected"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x20 20. " PCS13QUAD0PROT ,Peripheral select 13 quadrant 0 protection" "Not protected,Protected"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x20 19. " PCS12QUAD3PROT ,Peripheral select 12 quadrant 3 protection" "Not protected,Protected"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x20 18. " PCS12QUAD2PROT ,Peripheral select 12 quadrant 2 protection" "Not protected,Protected"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x20 17. " PCS12QUAD1PROT ,Peripheral select 12 quadrant 1 protection" "Not protected,Protected"
|
|
textline " "
|
|
setclrfld.long 0x00 16. 0x00 16. 0x20 16. " PCS12QUAD0PROT ,Peripheral select 12 quadrant 0 protection" "Not protected,Protected"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x20 15. " PCS11QUAD3PROT ,Peripheral select 11 quadrant 3 protection" "Not protected,Protected"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x20 14. " PCS11QUAD2PROT ,Peripheral select 11 quadrant 2 protection" "Not protected,Protected"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x20 13. " PCS11QUAD1PROT ,Peripheral select 11 quadrant 1 protection" "Not protected,Protected"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x20 12. " PCS11QUAD0PROT ,Peripheral select 11 quadrant 0 protection" "Not protected,Protected"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x20 11. " PCS10QUAD3PROT ,Peripheral select 10 quadrant 3 protection" "Not protected,Protected"
|
|
textline " "
|
|
setclrfld.long 0x00 10. 0x00 10. 0x20 10. " PCS10QUAD2PROT ,Peripheral select 10 quadrant 2 protection" "Not protected,Protected"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x20 9. " PCS10QUAD1PROT ,Peripheral select 10 quadrant 1 protection" "Not protected,Protected"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x20 8. " PCS10QUAD0PROT ,Peripheral select 10 quadrant 0 protection" "Not protected,Protected"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x20 7. " PCS9QUAD3PROT ,Peripheral select 9 quadrant 3 protection" "Not protected,Protected"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x20 6. " PCS9QUAD2PROT ,Peripheral select 9 quadrant 2 protection" "Not protected,Protected"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x20 5. " PCS9QUAD1PROT ,Peripheral select 9 quadrant 1 protection" "Not protected,Protected"
|
|
textline " "
|
|
setclrfld.long 0x00 4. 0x00 4. 0x20 4. " PCS9QUAD0PROT ,Peripheral select 9 quadrant 0 protection" "Not protected,Protected"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x20 3. " PCS8QUAD3PROT ,Peripheral select 8 quadrant 3 protection" "Not protected,Protected"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x20 2. " PCS8QUAD2PROT ,Peripheral select 8 quadrant 2 protection" "Not protected,Protected"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x20 1. " PCS8QUAD1PROT ,Peripheral select 8 quadrant 1 protection" "Not protected,Protected"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x20 0. " PCS8QUAD0PROT ,Peripheral select 8 quadrant 0 protection" "Not protected,Protected"
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "PPROTSET/CLR_2,Set/Clear Register To Protect The 32 Quadrants Of PS16 To PS23"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x20 31. " PCS23QUAD3PROT ,Peripheral select 23 quadrant 3 protection" "Not protected,Protected"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x20 30. " PCS23QUAD2PROT ,Peripheral select 23 quadrant 2 protection" "Not protected,Protected"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x20 29. " PCS23QUAD1PROT ,Peripheral select 23 quadrant 1 protection" "Not protected,Protected"
|
|
textline " "
|
|
setclrfld.long 0x00 28. 0x00 28. 0x20 28. " PCS23QUAD0PROT ,Peripheral select 23 quadrant 0 protection" "Not protected,Protected"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x20 27. " PCS22QUAD3PROT ,Peripheral select 22 quadrant 3 protection" "Not protected,Protected"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x20 26. " PCS22QUAD2PROT ,Peripheral select 22 quadrant 2 protection" "Not protected,Protected"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x20 25. " PCS22QUAD1PROT ,Peripheral select 22 quadrant 1 protection" "Not protected,Protected"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x20 24. " PCS22QUAD0PROT ,Peripheral select 22 quadrant 0 protection" "Not protected,Protected"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x20 23. " PCS21QUAD3PROT ,Peripheral select 21 quadrant 3 protection" "Not protected,Protected"
|
|
textline " "
|
|
setclrfld.long 0x00 22. 0x00 22. 0x20 22. " PCS21QUAD2PROT ,Peripheral select 21 quadrant 2 protection" "Not protected,Protected"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x20 21. " PCS21QUAD1PROT ,Peripheral select 21 quadrant 1 protection" "Not protected,Protected"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x20 20. " PCS21QUAD0PROT ,Peripheral select 21 quadrant 0 protection" "Not protected,Protected"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x20 19. " PCS20QUAD3PROT ,Peripheral select 20 quadrant 3 protection" "Not protected,Protected"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x20 18. " PCS20QUAD2PROT ,Peripheral select 20 quadrant 2 protection" "Not protected,Protected"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x20 17. " PCS20QUAD1PROT ,Peripheral select 20 quadrant 1 protection" "Not protected,Protected"
|
|
textline " "
|
|
setclrfld.long 0x00 16. 0x00 16. 0x20 16. " PCS20QUAD0PROT ,Peripheral select 20 quadrant 0 protection" "Not protected,Protected"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x20 15. " PCS19QUAD3PROT ,Peripheral select 19 quadrant 3 protection" "Not protected,Protected"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x20 14. " PCS19QUAD2PROT ,Peripheral select 19 quadrant 2 protection" "Not protected,Protected"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x20 13. " PCS19QUAD1PROT ,Peripheral select 19 quadrant 1 protection" "Not protected,Protected"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x20 12. " PCS19QUAD0PROT ,Peripheral select 19 quadrant 0 protection" "Not protected,Protected"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x20 11. " PCS18QUAD3PROT ,Peripheral select 18 quadrant 3 protection" "Not protected,Protected"
|
|
textline " "
|
|
setclrfld.long 0x00 10. 0x00 10. 0x20 10. " PCS18QUAD2PROT ,Peripheral select 18 quadrant 2 protection" "Not protected,Protected"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x20 9. " PCS18QUAD1PROT ,Peripheral select 18 quadrant 1 protection" "Not protected,Protected"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x20 8. " PCS18QUAD0PROT ,Peripheral select 18 quadrant 0 protection" "Not protected,Protected"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x20 7. " PCS17QUAD3PROT ,Peripheral select 17 quadrant 3 protection" "Not protected,Protected"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x20 6. " PCS17QUAD2PROT ,Peripheral select 17 quadrant 2 protection" "Not protected,Protected"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x20 5. " PCS17QUAD1PROT ,Peripheral select 17 quadrant 1 protection" "Not protected,Protected"
|
|
textline " "
|
|
setclrfld.long 0x00 4. 0x00 4. 0x20 4. " PCS17QUAD0PROT ,Peripheral select 17 quadrant 0 protection" "Not protected,Protected"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x20 3. " PCS16QUAD3PROT ,Peripheral select 16 quadrant 3 protection" "Not protected,Protected"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x20 2. " PCS16QUAD2PROT ,Peripheral select 16 quadrant 2 protection" "Not protected,Protected"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x20 1. " PCS16QUAD1PROT ,Peripheral select 16 quadrant 1 protection" "Not protected,Protected"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x20 0. " PCS16QUAD0PROT ,Peripheral select 16 quadrant 0 protection" "Not protected,Protected"
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "PPROTSET/CLR_3,Set/Clear Register To Protect The 32 Quadrants Of PS24 To PS31"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x20 31. " PCS31QUAD3PROT ,Peripheral select 31 quadrant 3 protection" "Not protected,Protected"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x20 30. " PCS31QUAD2PROT ,Peripheral select 31 quadrant 2 protection" "Not protected,Protected"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x20 29. " PCS31QUAD1PROT ,Peripheral select 31 quadrant 1 protection" "Not protected,Protected"
|
|
textline " "
|
|
setclrfld.long 0x00 28. 0x00 28. 0x20 28. " PCS31QUAD0PROT ,Peripheral select 31 quadrant 0 protection" "Not protected,Protected"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x20 27. " PCS30QUAD3PROT ,Peripheral select 30 quadrant 3 protection" "Not protected,Protected"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x20 26. " PCS30QUAD2PROT ,Peripheral select 30 quadrant 2 protection" "Not protected,Protected"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x20 25. " PCS30QUAD1PROT ,Peripheral select 30 quadrant 1 protection" "Not protected,Protected"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x20 24. " PCS30QUAD0PROT ,Peripheral select 30 quadrant 0 protection" "Not protected,Protected"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x20 23. " PCS29QUAD3PROT ,Peripheral select 29 quadrant 3 protection" "Not protected,Protected"
|
|
textline " "
|
|
setclrfld.long 0x00 22. 0x00 22. 0x20 22. " PCS29QUAD2PROT ,Peripheral select 29 quadrant 2 protection" "Not protected,Protected"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x20 21. " PCS29QUAD1PROT ,Peripheral select 29 quadrant 1 protection" "Not protected,Protected"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x20 20. " PCS29QUAD0PROT ,Peripheral select 29 quadrant 0 protection" "Not protected,Protected"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x20 19. " PCS28QUAD3PROT ,Peripheral select 28 quadrant 3 protection" "Not protected,Protected"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x20 18. " PCS28QUAD2PROT ,Peripheral select 28 quadrant 2 protection" "Not protected,Protected"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x20 17. " PCS28QUAD1PROT ,Peripheral select 28 quadrant 1 protection" "Not protected,Protected"
|
|
textline " "
|
|
setclrfld.long 0x00 16. 0x00 16. 0x20 16. " PCS28QUAD0PROT ,Peripheral select 28 quadrant 0 protection" "Not protected,Protected"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x20 15. " PCS27QUAD3PROT ,Peripheral select 27 quadrant 3 protection" "Not protected,Protected"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x20 14. " PCS27QUAD2PROT ,Peripheral select 27 quadrant 2 protection" "Not protected,Protected"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x20 13. " PCS27QUAD1PROT ,Peripheral select 27 quadrant 1 protection" "Not protected,Protected"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x20 12. " PCS27QUAD0PROT ,Peripheral select 27 quadrant 0 protection" "Not protected,Protected"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x20 11. " PCS26QUAD3PROT ,Peripheral select 26 quadrant 3 protection" "Not protected,Protected"
|
|
textline " "
|
|
setclrfld.long 0x00 10. 0x00 10. 0x20 10. " PCS26QUAD2PROT ,Peripheral select 26 quadrant 2 protection" "Not protected,Protected"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x20 9. " PCS26QUAD1PROT ,Peripheral select 26 quadrant 1 protection" "Not protected,Protected"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x20 8. " PCS26QUAD0PROT ,Peripheral select 26 quadrant 0 protection" "Not protected,Protected"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x20 7. " PCS25QUAD3PROT ,Peripheral select 25 quadrant 3 protection" "Not protected,Protected"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x20 6. " PCS25QUAD2PROT ,Peripheral select 25 quadrant 2 protection" "Not protected,Protected"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x20 5. " PCS25QUAD1PROT ,Peripheral select 25 quadrant 1 protection" "Not protected,Protected"
|
|
textline " "
|
|
setclrfld.long 0x00 4. 0x00 4. 0x20 4. " PCS25QUAD0PROT ,Peripheral select 25 quadrant 0 protection" "Not protected,Protected"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x20 3. " PCS24QUAD3PROT ,Peripheral select 24 quadrant 3 protection" "Not protected,Protected"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x20 2. " PCS24QUAD2PROT ,Peripheral select 24 quadrant 2 protection" "Not protected,Protected"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x20 1. " PCS24QUAD1PROT ,Peripheral select 24 quadrant 1 protection" "Not protected,Protected"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x20 0. " PCS24QUAD0PROT ,Peripheral select 24 quadrant 0 protection" "Not protected,Protected"
|
|
tree.end
|
|
width 20.
|
|
tree "PCR Power Down Registers"
|
|
tree "PCR Memory Power Down Registers"
|
|
group.long 0x60++0x03
|
|
line.long 0x00 "PCSPWRDWNSET/CLR_0,Peripheral Memory Power-Down Set/Clear Register 0"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x10 31. " PCS31PWRDWN ,Peripheral memory power down enable 31" "No power down,Power down"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x10 30. " PCS30PWRDWN ,Peripheral memory power down enable 30" "No power down,Power down"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x10 29. " PCS29PWRDWN ,Peripheral memory power down enable 29" "No power down,Power down"
|
|
textline " "
|
|
setclrfld.long 0x00 28. 0x00 28. 0x10 28. " PCS28PWRDWN ,Peripheral memory power down enable 28" "No power down,Power down"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x10 27. " PCS27PWRDWN ,Peripheral memory power down enable 27" "No power down,Power down"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x10 26. " PCS26PWRDWN ,Peripheral memory power down enable 26" "No power down,Power down"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x10 25. " PCS25PWRDWN ,Peripheral memory power down enable 25" "No power down,Power down"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x10 24. " PCS24PWRDWN ,Peripheral memory power down enable 24" "No power down,Power down"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x10 23. " PCS23PWRDWN ,Peripheral memory power down enable 23" "No power down,Power down"
|
|
textline " "
|
|
setclrfld.long 0x00 22. 0x00 22. 0x10 22. " PCS22PWRDWN ,Peripheral memory power down enable 22" "No power down,Power down"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x10 21. " PCS21PWRDWN ,Peripheral memory power down enable 21" "No power down,Power down"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x10 20. " PCS20PWRDWN ,Peripheral memory power down enable 20" "No power down,Power down"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x10 19. " PCS19PWRDWN ,Peripheral memory power down enable 19" "No power down,Power down"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x10 18. " PCS18PWRDWN ,Peripheral memory power down enable 18" "No power down,Power down"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x10 17. " PCS17PWRDWN ,Peripheral memory power down enable 17" "No power down,Power down"
|
|
textline " "
|
|
setclrfld.long 0x00 16. 0x00 16. 0x10 16. " PCS16PWRDWN ,Peripheral memory power down enable 16" "No power down,Power down"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x10 15. " PCS15PWRDWN ,Peripheral memory power down enable 15" "No power down,Power down"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x10 14. " PCS14PWRDWN ,Peripheral memory power down enable 14" "No power down,Power down"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x10 13. " PCS13PWRDWN ,Peripheral memory power down enable 13" "No power down,Power down"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x10 12. " PCS12PWRDWN ,Peripheral memory power down enable 12" "No power down,Power down"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x10 11. " PCS11PWRDWN ,Peripheral memory power down enable 11" "No power down,Power down"
|
|
textline " "
|
|
setclrfld.long 0x00 10. 0x00 10. 0x10 10. " PCS10PWRDWN ,Peripheral memory power down enable 10" "No power down,Power down"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x10 9. " PCS9PWRDWN ,Peripheral memory power down enable 9" "No power down,Power down"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x10 8. " PCS8PWRDWN ,Peripheral memory power down enable 8" "No power down,Power down"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x10 7. " PCS7PWRDWN ,Peripheral memory power down enable 7" "No power down,Power down"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x10 6. " PCS6PWRDWN ,Peripheral memory power down enable 6" "No power down,Power down"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x10 5. " PCS5PWRDWN ,Peripheral memory power down enable 5" "No power down,Power down"
|
|
textline " "
|
|
setclrfld.long 0x00 4. 0x00 4. 0x10 4. " PCS4PWRDWN ,Peripheral memory power down enable 4" "No power down,Power down"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x10 3. " PCS3PWRDWN ,Peripheral memory power down enable 3" "No power down,Power down"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x10 2. " PCS2PWRDWN ,Peripheral memory power down enable 2" "No power down,Power down"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x10 1. " PCS1PWRDWN ,Peripheral memory power down enable 1" "No power down,Power down"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x10 0. " PCS0PWRDWN ,Peripheral memory power down enable 0" "No power down,Power down"
|
|
group.long 0x64++0x03
|
|
line.long 0x00 "PCSPWRDWNSET/CLR_1,Peripheral Memory Power-Down Set/Clear Register 1"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x10 31. " PCS63PWRDWN ,Peripheral memory power down enable 63" "No power down,Power down"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x10 30. " PCS62PWRDWN ,Peripheral memory power down enable 62" "No power down,Power down"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x10 29. " PCS61PWRDWN ,Peripheral memory power down enable 61" "No power down,Power down"
|
|
textline " "
|
|
setclrfld.long 0x00 28. 0x00 28. 0x10 28. " PCS60PWRDWN ,Peripheral memory power down enable 60" "No power down,Power down"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x10 27. " PCS59PWRDWN ,Peripheral memory power down enable 59" "No power down,Power down"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x10 26. " PCS58PWRDWN ,Peripheral memory power down enable 58" "No power down,Power down"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x10 25. " PCS57PWRDWN ,Peripheral memory power down enable 57" "No power down,Power down"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x10 24. " PCS56PWRDWN ,Peripheral memory power down enable 56" "No power down,Power down"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x10 23. " PCS55PWRDWN ,Peripheral memory power down enable 55" "No power down,Power down"
|
|
textline " "
|
|
setclrfld.long 0x00 22. 0x00 22. 0x10 22. " PCS54PWRDWN ,Peripheral memory power down enable 54" "No power down,Power down"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x10 21. " PC531PWRDWN ,Peripheral memory power down enable 53" "No power down,Power down"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x10 20. " PCS52PWRDWN ,Peripheral memory power down enable 52" "No power down,Power down"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x10 19. " PCS51PWRDWN ,Peripheral memory power down enable 51" "No power down,Power down"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x10 18. " PCS50PWRDWN ,Peripheral memory power down enable 50" "No power down,Power down"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x10 17. " PCS49PWRDWN ,Peripheral memory power down enable 49" "No power down,Power down"
|
|
textline " "
|
|
setclrfld.long 0x00 16. 0x00 16. 0x10 16. " PCS48PWRDWN ,Peripheral memory power down enable 48" "No power down,Power down"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x10 15. " PCS47PWRDWN ,Peripheral memory power down enable 47" "No power down,Power down"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x10 14. " PCS46PWRDWN ,Peripheral memory power down enable 46" "No power down,Power down"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x10 13. " PCS45PWRDWN ,Peripheral memory power down enable 45" "No power down,Power down"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x10 12. " PCS44PWRDWN ,Peripheral memory power down enable 44" "No power down,Power down"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x10 11. " PCS43PWRDWN ,Peripheral memory power down enable 43" "No power down,Power down"
|
|
textline " "
|
|
setclrfld.long 0x00 10. 0x00 10. 0x10 10. " PCS42PWRDWN ,Peripheral memory power down enable 42" "No power down,Power down"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x10 9. " PCS41PWRDWN ,Peripheral memory power down enable 41" "No power down,Power down"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x10 8. " PCS40PWRDWN ,Peripheral memory power down enable 40" "No power down,Power down"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x10 7. " PCS39PWRDWN ,Peripheral memory power down enable 39" "No power down,Power down"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x10 6. " PCS38PWRDWN ,Peripheral memory power down enable 38" "No power down,Power down"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x10 5. " PCS37PWRDWN ,Peripheral memory power down enable 37" "No power down,Power down"
|
|
textline " "
|
|
setclrfld.long 0x00 4. 0x00 4. 0x10 4. " PCS36PWRDWN ,Peripheral memory power down enable 36" "No power down,Power down"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x10 3. " PCS35PWRDWN ,Peripheral memory power down enable 35" "No power down,Power down"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x10 2. " PCS34PWRDWN ,Peripheral memory power down enable 34" "No power down,Power down"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x10 1. " PCS33PWRDWN ,Peripheral memory power down enable 33" "No power down,Power down"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x10 0. " PCS32PWRDWN ,Peripheral memory power down enable 32" "No power down,Power down"
|
|
tree.end
|
|
textline " "
|
|
group.long 0x80++0x03
|
|
line.long 0x00 "PSPWRDWNSET/CLR_0,Peripheral Power-Down Set/Clear Register 0"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x20 31. " PS7QUAD3PWRDWN ,Peripheral select 7 quadrant 3 clock power down enable" "No power down,Power down"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x20 30. " PS7QUAD2PWRDWN ,Peripheral select 7 quadrant 2 clock power down enable" "No power down,Power down"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x20 29. " PS7QUAD1PWRDWN ,Peripheral select 7 quadrant 1 clock power down enable" "No power down,Power down"
|
|
textline " "
|
|
setclrfld.long 0x00 28. 0x00 28. 0x20 28. " PS7QUAD0PWRDWN ,Peripheral select 7 quadrant 0 clock power down enable" "No power down,Power down"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x20 27. " PS6QUAD3PWRDWN ,Peripheral select 6 quadrant 3 clock power down enable" "No power down,Power down"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x20 26. " PS6QUAD2PWRDWN ,Peripheral select 6 quadrant 2 clock power down enable" "No power down,Power down"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x20 25. " PS6QUAD1PWRDWN ,Peripheral select 6 quadrant 1 clock power down enable" "No power down,Power down"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x20 24. " PS6QUAD0PWRDWN ,Peripheral select 6 quadrant 0 clock power down enable" "No power down,Power down"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x20 23. " PS5QUAD3PWRDWN ,Peripheral select 5 quadrant 3 clock power down enable" "No power down,Power down"
|
|
textline " "
|
|
setclrfld.long 0x00 22. 0x00 22. 0x20 22. " PS5QUAD2PWRDWN ,Peripheral select 5 quadrant 2 clock power down enable" "No power down,Power down"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x20 21. " PS5QUAD1PWRDWN ,Peripheral select 5 quadrant 1 clock power down enable" "No power down,Power down"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x20 20. " PS5QUAD0PWRDWN ,Peripheral select 5 quadrant 0 clock power down enable" "No power down,Power down"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x20 19. " PS4QUAD3PWRDWN ,Peripheral select 4 quadrant 3 clock power down enable" "No power down,Power down"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x20 18. " PS4QUAD2PWRDWN ,Peripheral select 4 quadrant 2 clock power down enable" "No power down,Power down"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x20 17. " PS4QUAD1PWRDWN ,Peripheral select 4 quadrant 1 clock power down enable" "No power down,Power down"
|
|
textline " "
|
|
setclrfld.long 0x00 16. 0x00 16. 0x20 16. " PS4QUAD0PWRDWN ,Peripheral select 4 quadrant 0 clock power down enable" "No power down,Power down"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x20 15. " PS3QUAD3PWRDWN ,Peripheral select 3 quadrant 3 clock power down enable" "No power down,Power down"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x20 14. " PS3QUAD2PWRDWN ,Peripheral select 3 quadrant 2 clock power down enable" "No power down,Power down"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x20 13. " PS3QUAD1PWRDWN ,Peripheral select 3 quadrant 1 clock power down enable" "No power down,Power down"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x20 12. " PS3QUAD0PWRDWN ,Peripheral select 3 quadrant 0 clock power down enable" "No power down,Power down"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x20 11. " PS2QUAD3PWRDWN ,Peripheral select 2 quadrant 3 clock power down enable" "No power down,Power down"
|
|
textline " "
|
|
setclrfld.long 0x00 10. 0x00 10. 0x20 10. " PS2QUAD2PWRDWN ,Peripheral select 2 quadrant 2 clock power down enable" "No power down,Power down"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x20 9. " PS2QUAD1PWRDWN ,Peripheral select 2 quadrant 1 clock power down enable" "No power down,Power down"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x20 8. " PS2QUAD0PWRDWN ,Peripheral select 2 quadrant 0 clock power down enable" "No power down,Power down"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x20 7. " PS1QUAD3PWRDWN ,Peripheral select 1 quadrant 3 clock power down enable" "No power down,Power down"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x20 6. " PS1QUAD2PWRDWN ,Peripheral select 1 quadrant 2 clock power down enable" "No power down,Power down"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x20 5. " PS1QUAD1PWRDWN ,Peripheral select 1 quadrant 1 clock power down enable" "No power down,Power down"
|
|
textline " "
|
|
setclrfld.long 0x00 4. 0x00 4. 0x20 4. " PS1QUAD0PWRDWN ,Peripheral select 1 quadrant 0 clock power down enable" "No power down,Power down"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x20 3. " PS0QUAD3PWRDWN ,Peripheral select 0 quadrant 3 clock power down enable" "No power down,Power down"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x20 2. " PS0QUAD2PWRDWN ,Peripheral select 0 quadrant 2 clock power down enable" "No power down,Power down"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x20 1. " PS0QUAD1PWRDWN ,Peripheral select 0 quadrant 1 clock power down enable" "No power down,Power down"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x20 0. " PS0QUAD0PWRDWN ,Peripheral select 0 quadrant 0 clock power down enable" "No power down,Power down"
|
|
group.long 0x84++0x03
|
|
line.long 0x00 "PSPWRDWNSET/CLR_1,Peripheral Power-Down Set/Clear Register 1"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x20 31. " PS15QUAD3PWRDWN ,Peripheral select 15 quadrant 3 clock power down enable" "No power down,Power down"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x20 30. " PS15QUAD2PWRDWN ,Peripheral select 15 quadrant 2 clock power down enable" "No power down,Power down"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x20 29. " PS15QUAD1PWRDWN ,Peripheral select 15 quadrant 1 clock power down enable" "No power down,Power down"
|
|
textline " "
|
|
setclrfld.long 0x00 28. 0x00 28. 0x20 28. " PS15QUAD0PWRDWN ,Peripheral select 15 quadrant 0 clock power down enable" "No power down,Power down"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x20 27. " PS14QUAD3PWRDWN ,Peripheral select 14 quadrant 3 clock power down enable" "No power down,Power down"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x20 26. " PS14QUAD2PWRDWN ,Peripheral select 14 quadrant 2 clock power down enable" "No power down,Power down"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x20 25. " PS14QUAD1PWRDWN ,Peripheral select 14 quadrant 1 clock power down enable" "No power down,Power down"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x20 24. " PS14QUAD0PWRDWN ,Peripheral select 14 quadrant 0 clock power down enable" "No power down,Power down"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x20 23. " PS13QUAD3PWRDWN ,Peripheral select 13 quadrant 3 clock power down enable" "No power down,Power down"
|
|
textline " "
|
|
setclrfld.long 0x00 22. 0x00 22. 0x20 22. " PS13QUAD2PWRDWN ,Peripheral select 13 quadrant 2 clock power down enable" "No power down,Power down"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x20 21. " PS13QUAD1PWRDWN ,Peripheral select 13 quadrant 1 clock power down enable" "No power down,Power down"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x20 20. " PS13QUAD0PWRDWN ,Peripheral select 13 quadrant 0 clock power down enable" "No power down,Power down"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x20 19. " PS12QUAD3PWRDWN ,Peripheral select 12 quadrant 3 clock power down enable" "No power down,Power down"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x20 18. " PS12QUAD2PWRDWN ,Peripheral select 12 quadrant 2 clock power down enable" "No power down,Power down"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x20 17. " PS12QUAD1PWRDWN ,Peripheral select 12 quadrant 1 clock power down enable" "No power down,Power down"
|
|
textline " "
|
|
setclrfld.long 0x00 16. 0x00 16. 0x20 16. " PS12QUAD0PWRDWN ,Peripheral select 12 quadrant 0 clock power down enable" "No power down,Power down"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x20 15. " PS11QUAD3PWRDWN ,Peripheral select 11 quadrant 3 clock power down enable" "No power down,Power down"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x20 14. " PS11QUAD2PWRDWN ,Peripheral select 11 quadrant 2 clock power down enable" "No power down,Power down"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x20 13. " PS11QUAD1PWRDWN ,Peripheral select 11 quadrant 1 clock power down enable" "No power down,Power down"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x20 12. " PS11QUAD0PWRDWN ,Peripheral select 11 quadrant 0 clock power down enable" "No power down,Power down"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x20 11. " PS10QUAD3PWRDWN ,Peripheral select 10 quadrant 3 clock power down enable" "No power down,Power down"
|
|
textline " "
|
|
setclrfld.long 0x00 10. 0x00 10. 0x20 10. " PS10QUAD2PWRDWN ,Peripheral select 10 quadrant 2 clock power down enable" "No power down,Power down"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x20 9. " PS10QUAD1PWRDWN ,Peripheral select 10 quadrant 1 clock power down enable" "No power down,Power down"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x20 8. " PS10QUAD0PWRDWN ,Peripheral select 10 quadrant 0 clock power down enable" "No power down,Power down"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x20 7. " PS9QUAD3PWRDWN ,Peripheral select 9 quadrant 3 clock power down enable" "No power down,Power down"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x20 6. " PS9QUAD2PWRDWN ,Peripheral select 9 quadrant 2 clock power down enable" "No power down,Power down"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x20 5. " PS9QUAD1PWRDWN ,Peripheral select 9 quadrant 1 clock power down enable" "No power down,Power down"
|
|
textline " "
|
|
setclrfld.long 0x00 4. 0x00 4. 0x20 4. " PS9QUAD0PWRDWN ,Peripheral select 9 quadrant 0 clock power down enable" "No power down,Power down"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x20 3. " PS8QUAD3PWRDWN ,Peripheral select 8 quadrant 3 clock power down enable" "No power down,Power down"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x20 2. " PS8QUAD2PWRDWN ,Peripheral select 8 quadrant 2 clock power down enable" "No power down,Power down"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x20 1. " PS8QUAD1PWRDWN ,Peripheral select 8 quadrant 1 clock power down enable" "No power down,Power down"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x20 0. " PS8QUAD0PWRDWN ,Peripheral select 8 quadrant 0 clock power down enable" "No power down,Power down"
|
|
group.long 0x88++0x03
|
|
line.long 0x00 "PSPWRDWNSET/CLR_2,Peripheral Power-Down Set/Clear Register 2"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x20 31. " PS23QUAD3PWRDWN ,Peripheral select 23 quadrant 3 clock power down enable" "No power down,Power down"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x20 30. " PS23QUAD2PWRDWN ,Peripheral select 23 quadrant 2 clock power down enable" "No power down,Power down"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x20 29. " PS23QUAD1PWRDWN ,Peripheral select 23 quadrant 1 clock power down enable" "No power down,Power down"
|
|
textline " "
|
|
setclrfld.long 0x00 28. 0x00 28. 0x20 28. " PS23QUAD0PWRDWN ,Peripheral select 23 quadrant 0 clock power down enable" "No power down,Power down"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x20 27. " PS22QUAD3PWRDWN ,Peripheral select 22 quadrant 3 clock power down enable" "No power down,Power down"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x20 26. " PS22QUAD2PWRDWN ,Peripheral select 22 quadrant 2 clock power down enable" "No power down,Power down"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x20 25. " PS22QUAD1PWRDWN ,Peripheral select 22 quadrant 1 clock power down enable" "No power down,Power down"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x20 24. " PS22QUAD0PWRDWN ,Peripheral select 22 quadrant 0 clock power down enable" "No power down,Power down"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x20 23. " PS21QUAD3PWRDWN ,Peripheral select 21 quadrant 3 clock power down enable" "No power down,Power down"
|
|
textline " "
|
|
setclrfld.long 0x00 22. 0x00 22. 0x20 22. " PS21QUAD2PWRDWN ,Peripheral select 21 quadrant 2 clock power down enable" "No power down,Power down"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x20 21. " PS21QUAD1PWRDWN ,Peripheral select 21 quadrant 1 clock power down enable" "No power down,Power down"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x20 20. " PS21QUAD0PWRDWN ,Peripheral select 21 quadrant 0 clock power down enable" "No power down,Power down"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x20 19. " PS20QUAD3PWRDWN ,Peripheral select 20 quadrant 3 clock power down enable" "No power down,Power down"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x20 18. " PS20QUAD2PWRDWN ,Peripheral select 20 quadrant 2 clock power down enable" "No power down,Power down"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x20 17. " PS20QUAD1PWRDWN ,Peripheral select 20 quadrant 1 clock power down enable" "No power down,Power down"
|
|
textline " "
|
|
setclrfld.long 0x00 16. 0x00 16. 0x20 16. " PS20QUAD0PWRDWN ,Peripheral select 20 quadrant 0 clock power down enable" "No power down,Power down"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x20 15. " PS19QUAD3PWRDWN ,Peripheral select 19 quadrant 3 clock power down enable" "No power down,Power down"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x20 14. " PS19QUAD2PWRDWN ,Peripheral select 19 quadrant 2 clock power down enable" "No power down,Power down"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x20 13. " PS19QUAD1PWRDWN ,Peripheral select 19 quadrant 1 clock power down enable" "No power down,Power down"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x20 12. " PS19QUAD0PWRDWN ,Peripheral select 19 quadrant 0 clock power down enable" "No power down,Power down"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x20 11. " PS18QUAD3PWRDWN ,Peripheral select 18 quadrant 3 clock power down enable" "No power down,Power down"
|
|
textline " "
|
|
setclrfld.long 0x00 10. 0x00 10. 0x20 10. " PS18QUAD2PWRDWN ,Peripheral select 18 quadrant 2 clock power down enable" "No power down,Power down"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x20 9. " PS18QUAD1PWRDWN ,Peripheral select 18 quadrant 1 clock power down enable" "No power down,Power down"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x20 8. " PS18QUAD0PWRDWN ,Peripheral select 18 quadrant 0 clock power down enable" "No power down,Power down"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x20 7. " PS17QUAD3PWRDWN ,Peripheral select 17 quadrant 3 clock power down enable" "No power down,Power down"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x20 6. " PS17QUAD2PWRDWN ,Peripheral select 17 quadrant 2 clock power down enable" "No power down,Power down"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x20 5. " PS17QUAD1PWRDWN ,Peripheral select 17 quadrant 1 clock power down enable" "No power down,Power down"
|
|
textline " "
|
|
setclrfld.long 0x00 4. 0x00 4. 0x20 4. " PS17QUAD0PWRDWN ,Peripheral select 17 quadrant 0 clock power down enable" "No power down,Power down"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x20 3. " PS16QUAD3PWRDWN ,Peripheral select 16 quadrant 3 clock power down enable" "No power down,Power down"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x20 2. " PS16QUAD2PWRDWN ,Peripheral select 16 quadrant 2 clock power down enable" "No power down,Power down"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x20 1. " PS16QUAD1PWRDWN ,Peripheral select 16 quadrant 1 clock power down enable" "No power down,Power down"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x20 0. " PS16QUAD0PWRDWN ,Peripheral select 16 quadrant 0 clock power down enable" "No power down,Power down"
|
|
group.long 0x8C++0x03
|
|
line.long 0x00 "PSPWRDWNSET/CLR_3,Peripheral Power-Down Set/Clear Register 3"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x20 31. " PS31QUAD3PWRDWN ,Peripheral select 31 quadrant 3 clock power down enable" "No power down,Power down"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x20 30. " PS31QUAD2PWRDWN ,Peripheral select 31 quadrant 2 clock power down enable" "No power down,Power down"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x20 29. " PS31QUAD1PWRDWN ,Peripheral select 31 quadrant 1 clock power down enable" "No power down,Power down"
|
|
textline " "
|
|
setclrfld.long 0x00 28. 0x00 28. 0x20 28. " PS31QUAD0PWRDWN ,Peripheral select 31 quadrant 0 clock power down enable" "No power down,Power down"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x20 27. " PS30QUAD3PWRDWN ,Peripheral select 30 quadrant 3 clock power down enable" "No power down,Power down"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x20 26. " PS30QUAD2PWRDWN ,Peripheral select 30 quadrant 2 clock power down enable" "No power down,Power down"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x20 25. " PS30QUAD1PWRDWN ,Peripheral select 30 quadrant 1 clock power down enable" "No power down,Power down"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x20 24. " PS30QUAD0PWRDWN ,Peripheral select 30 quadrant 0 clock power down enable" "No power down,Power down"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x20 23. " PS29QUAD3PWRDWN ,Peripheral select 29 quadrant 3 clock power down enable" "No power down,Power down"
|
|
textline " "
|
|
setclrfld.long 0x00 22. 0x00 22. 0x20 22. " PS29QUAD2PWRDWN ,Peripheral select 29 quadrant 2 clock power down enable" "No power down,Power down"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x20 21. " PS29QUAD1PWRDWN ,Peripheral select 29 quadrant 1 clock power down enable" "No power down,Power down"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x20 20. " PS29QUAD0PWRDWN ,Peripheral select 29 quadrant 0 clock power down enable" "No power down,Power down"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x20 19. " PS28QUAD3PWRDWN ,Peripheral select 28 quadrant 3 clock power down enable" "No power down,Power down"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x20 18. " PS28QUAD2PWRDWN ,Peripheral select 28 quadrant 2 clock power down enable" "No power down,Power down"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x20 17. " PS28QUAD1PWRDWN ,Peripheral select 28 quadrant 1 clock power down enable" "No power down,Power down"
|
|
textline " "
|
|
setclrfld.long 0x00 16. 0x00 16. 0x20 16. " PS28QUAD0PWRDWN ,Peripheral select 28 quadrant 0 clock power down enable" "No power down,Power down"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x20 15. " PS27QUAD3PWRDWN ,Peripheral select 27 quadrant 3 clock power down enable" "No power down,Power down"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x20 14. " PS27QUAD2PWRDWN ,Peripheral select 27 quadrant 2 clock power down enable" "No power down,Power down"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x20 13. " PS27QUAD1PWRDWN ,Peripheral select 27 quadrant 1 clock power down enable" "No power down,Power down"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x20 12. " PS27QUAD0PWRDWN ,Peripheral select 27 quadrant 0 clock power down enable" "No power down,Power down"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x20 11. " PS26QUAD3PWRDWN ,Peripheral select 26 quadrant 3 clock power down enable" "No power down,Power down"
|
|
textline " "
|
|
setclrfld.long 0x00 10. 0x00 10. 0x20 10. " PS26QUAD2PWRDWN ,Peripheral select 26 quadrant 2 clock power down enable" "No power down,Power down"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x20 9. " PS26QUAD1PWRDWN ,Peripheral select 26 quadrant 1 clock power down enable" "No power down,Power down"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x20 8. " PS26QUAD0PWRDWN ,Peripheral select 26 quadrant 0 clock power down enable" "No power down,Power down"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x20 7. " PS25QUAD3PWRDWN ,Peripheral select 25 quadrant 3 clock power down enable" "No power down,Power down"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x20 6. " PS25QUAD2PWRDWN ,Peripheral select 25 quadrant 2 clock power down enable" "No power down,Power down"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x20 5. " PS25QUAD1PWRDWN ,Peripheral select 25 quadrant 1 clock power down enable" "No power down,Power down"
|
|
textline " "
|
|
setclrfld.long 0x00 4. 0x00 4. 0x20 4. " PS25QUAD0PWRDWN ,Peripheral select 25 quadrant 0 clock power down enable" "No power down,Power down"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x20 3. " PS24QUAD3PWRDWN ,Peripheral select 24 quadrant 3 clock power down enable" "No power down,Power down"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x20 2. " PS24QUAD2PWRDWN ,Peripheral select 24 quadrant 2 clock power down enable" "No power down,Power down"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x20 1. " PS24QUAD1PWRDWN ,Peripheral select 24 quadrant 1 clock power down enable" "No power down,Power down"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x20 0. " PS24QUAD0PWRDWN ,Peripheral select 24 quadrant 0 clock power down enable" "No power down,Power down"
|
|
tree.end
|
|
sif (cpuis("TMS570LS09*")||cpuis("TMS570LS07*")||cpuis("TMS570LS0232"))
|
|
endian.le
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
tree.end
|
|
sif (cpuis("TMS570LS09*")||cpuis("TMS570LS07*"))
|
|
tree "PMM (Power Management Module)"
|
|
base ad:0xFFFF0000
|
|
sif cpuis("TMS570LS09*")||cpuis("TMS570LS07*")||cpuis("TMS570LS0232")
|
|
endian.be
|
|
endif
|
|
width 19.
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "LOGICPDPWRCTRL0,Logic Power Domain Control Register 0"
|
|
bitfld.long 0x00 24.--27. " LOGICPDON[0] ,Power domain PD2 state" "Active,Active,Active,Active,Active,Active,Active,Active,Active,,Off,Active,Active,Active,Active,Active"
|
|
bitfld.long 0x00 16.--19. " [1] ,Power domain PD3 state" "Active,Active,Active,Active,Active,Active,Active,Active,Active,,Off,Active,Active,Active,Active,Active"
|
|
newline
|
|
bitfld.long 0x00 8.--11. " [2] ,Power domain PD4 state" "Active,Active,Active,Active,Active,Active,Active,Active,Active,,Off,Active,Active,Active,Active,Active"
|
|
bitfld.long 0x00 0.--3. " [3] ,Power domain PD5 state" "Active,Active,Active,Active,Active,Active,Active,Active,Active,,Off,Active,Active,Active,Active,Active"
|
|
sif (!cpuis("TMS570LS09*")&&!cpuis("TMS570LS07*")&&!cpuis("TMS570LS3137-EP"))
|
|
group.long 0x04++0x0B
|
|
line.long 0x00 "LOGICPDCTRL1,Logic Power Domain Control Register"
|
|
line.long 0x04 "LOGICPDCTRL2,Logic Power Domain Control Register"
|
|
line.long 0x08 "LOGICPDCTRL3,Logic Power Domain Control Register"
|
|
endif
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "MEMPDPWRCTRL0,Memory Power Domain Control Register 0"
|
|
bitfld.long 0x00 24.--27. " MEMPDON[0] ,Power domain RAM_PD1 state" "Active,Active,Active,Active,Active,Active,Active,Active,Active,,Off,Active,Active,Active,Active,Active"
|
|
bitfld.long 0x00 16.--19. " [1] ,Power domain RAM_PD2 state" "Active,Active,Active,Active,Active,Active,Active,Active,Active,,Off,Active,Active,Active,Active,Active"
|
|
sif (!cpuis("TMS570LS09*")&&!cpuis("TMS570LS07*"))
|
|
newline
|
|
bitfld.long 0x00 8.--11. " [2] ,Power domain RAM_PD3 state" "Active,Active,Active,Active,Active,Active,Active,Active,Active,,Off,Active,Active,Active,Active,Active"
|
|
endif
|
|
sif (!cpuis("TMS570LS09*")&&!cpuis("TMS570LS07*")&&!cpuis("TMS570LS3137-EP"))
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "MEMPDCTRL1,Memory Power Domain Control Register"
|
|
endif
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "PDCLK_DIS_SET/CLR,Power Domain Clock Disable Set/Clear Register"
|
|
setclrfld.long 0x00 3. 0x04 3. 0x08 3. " PDCLK_DIS[3] ,Clocks to logic power domain PD5 disable" "No,Yes"
|
|
setclrfld.long 0x00 2. 0x04 2. 0x08 2. " [2] ,Clocks to logic power domain PD4 disable" "No,Yes"
|
|
newline
|
|
setclrfld.long 0x00 1. 0x04 1. 0x08 1. " [1] ,Clocks to logic power domain PD3 disable" "No,Yes"
|
|
setclrfld.long 0x00 0. 0x04 0. 0x08 0. " [0] ,Clocks to logic power domain PD2 disable" "No,Yes"
|
|
sif (!cpuis("TMS570LS09*")&&!cpuis("TMS570LS07*")&&!cpuis("TMS570LS3137-EP"))
|
|
group.long 0x30++0x0B
|
|
line.long 0x00 "ISOEXTEND,Isolation Extension Register"
|
|
line.long 0x04 "ISOEXTENDSET,Isolation Extension SET Register"
|
|
line.long 0x08 "ISOEXTENDCLR,Isolation Extension CLEAR Register"
|
|
endif
|
|
rgroup.long 0x40++0x03
|
|
line.long 0x00 "LOGICPDPWRSTAT0 ,Logic Power Domain Status Register 0 "
|
|
bitfld.long 0x00 24. " LOGIC_IN_TRANS0 ,Logic in transition status for power domain PD2" "Active/Off,Power-down/up"
|
|
bitfld.long 0x00 16. " MEM_IN_TRANS0 ,Memory in transition status for power domain PD2" "Active/Off,Power-down/up"
|
|
newline
|
|
bitfld.long 0x00 8. " DOMAIN_ON0 ,Current state of power domain PD2" "Off,Active"
|
|
bitfld.long 0x00 0.--1. " LOGICPDPWR_STAT0 ,Logic power domain PD2 power state" "Off,Idle,,Active"
|
|
rgroup.long 0x44++0x03
|
|
line.long 0x00 "LOGICPDPWRSTAT1 ,Logic Power Domain Status Register 1 "
|
|
bitfld.long 0x00 24. " LOGIC_IN_TRANS1 ,Logic in transition status for power domain PD3" "Active/Off,Power-down/up"
|
|
bitfld.long 0x00 16. " MEM_IN_TRANS1 ,Memory in transition status for power domain PD3" "Active/Off,Power-down/up"
|
|
newline
|
|
bitfld.long 0x00 8. " DOMAIN_ON1 ,Current state of power domain PD3" "Off,Active"
|
|
bitfld.long 0x00 0.--1. " LOGICPDPWR_STAT1 ,Logic power domain PD3 power state" "Off,Idle,,Active"
|
|
rgroup.long 0x48++0x03
|
|
line.long 0x00 "LOGICPDPWRSTAT2 ,Logic Power Domain Status Register 2 "
|
|
bitfld.long 0x00 24. " LOGIC_IN_TRANS2 ,Logic in transition status for power domain PD4" "Active/Off,Power-down/up"
|
|
bitfld.long 0x00 16. " MEM_IN_TRANS2 ,Memory in transition status for power domain PD4" "Active/Off,Power-down/up"
|
|
newline
|
|
bitfld.long 0x00 8. " DOMAIN_ON2 ,Current state of power domain PD4" "Off,Active"
|
|
bitfld.long 0x00 0.--1. " LOGICPDPWR_STAT2 ,Logic power domain PD4 power state" "Off,Idle,,Active"
|
|
rgroup.long 0x4C++0x03
|
|
line.long 0x00 "LOGICPDPWRSTAT3 ,Logic Power Domain Status Register 3 "
|
|
bitfld.long 0x00 24. " LOGIC_IN_TRANS3 ,Logic in transition status for power domain PD5" "Active/Off,Power-down/up"
|
|
bitfld.long 0x00 16. " MEM_IN_TRANS3 ,Memory in transition status for power domain PD5" "Active/Off,Power-down/up"
|
|
newline
|
|
bitfld.long 0x00 8. " DOMAIN_ON3 ,Current state of power domain PD5" "Off,Active"
|
|
bitfld.long 0x00 0.--1. " LOGICPDPWR_STAT3 ,Logic power domain PD5 power state" "Off,Idle,,Active"
|
|
sif (!cpuis("TMS570LS09*")&&!cpuis("TMS570LS07*")&&!cpuis("TMS570LS3137-EP"))
|
|
group.long 0x50++0x2F
|
|
line.long 0x00 "LOGICPDPWRSTAT4,Logic Power Domain Power Status Register"
|
|
line.long 0x04 "LOGICPDPWRSTAT5,Logic Power Domain Power Status Register"
|
|
line.long 0x08 "LOGICPDPWRSTAT6,Logic Power Domain Power Status Register"
|
|
line.long 0x0C "LOGICPDPWRSTAT7,Logic Power Domain Power Status Register"
|
|
line.long 0x10 "LOGICPDPWRSTAT8,Logic Power Domain Power Status Register"
|
|
line.long 0x14 "LOGICPDPWRSTAT9,Logic Power Domain Power Status Register"
|
|
line.long 0x18 "LOGICPDPWRSTAT10,Logic Power Domain Power Status Register"
|
|
line.long 0x1C "LOGICPDPWRSTAT11,Logic Power Domain Power Status Register"
|
|
line.long 0x20 "LOGICPDPWRSTAT12,Logic Power Domain Power Status Register"
|
|
line.long 0x24 "LOGICPDPWRSTAT13,Logic Power Domain Power Status Register"
|
|
line.long 0x28 "LOGICPDPWRSTAT14,Logic Power Domain Power Status Register"
|
|
line.long 0x2C "LOGICPDPWRSTAT15,Logic Power Domain Power Status Register"
|
|
endif
|
|
sif (cpuis("TMS570LS09*")||cpuis("TMS570LS07*"))
|
|
rgroup.long 0x80++0x03
|
|
line.long 0x00 "MEMPDPWRSTAT0 ,Memory Power Domain Status Register 0 "
|
|
bitfld.long 0x00 24. " LOGIC_IN_TRANS0 ,Logic in transition status for power domain RAM_PD1" "Active/Off,Power-down/up"
|
|
bitfld.long 0x00 16. " MEM_IN_TRANS0 ,Memory in transition status for power domain RAM_PD1" "Active/Off,Power-down/up"
|
|
newline
|
|
bitfld.long 0x00 8. " DOMAIN_ON0 ,Current state of power domain RAM_PD1" "Off,Active"
|
|
bitfld.long 0x00 0.--1. " MEMPDPWRSTAT0 ,Memory power domain RAM_PD1 power state" "Off,Idle,,Active"
|
|
rgroup.long 0x84++0x03
|
|
line.long 0x00 "MEMPDPWRSTAT1 ,Memory Power Domain Status Register 1 "
|
|
bitfld.long 0x00 24. " LOGIC_IN_TRANS1 ,Logic in transition status for power domain RAM_PD2" "Active/Off,Power-down/up"
|
|
bitfld.long 0x00 16. " MEM_IN_TRANS1 ,Memory in transition status for power domain RAM_PD2" "Active/Off,Power-down/up"
|
|
newline
|
|
bitfld.long 0x00 8. " DOMAIN_ON1 ,Current state of power domain RAM_PD2" "Off,Active"
|
|
bitfld.long 0x00 0.--1. " MEMPDPWRSTAT1 ,Memory power domain RAM_PD2 power state" "Off,Idle,,Active"
|
|
else
|
|
rgroup.long 0x80++0x03
|
|
line.long 0x00 "MEMPDPWRSTAT0 ,Memory Power Domain Status 0 "
|
|
bitfld.long 0x00 24. " LOGIC_IN_TRANS0 ,Logic in transition status for power domain RAM_PD1" "Active/Off,Power-down/up"
|
|
bitfld.long 0x00 16. " MEM_IN_TRANS0 ,Memory in transition status for power domain RAM_PD1" "Active/Off,Power-down/up"
|
|
bitfld.long 0x00 8. " DOMAIN_ON0 ,Current state of power domain RAM_PD1" "Off,Active"
|
|
newline
|
|
sif cpuis("TMS570LS3137-EP")
|
|
bitfld.long 0x00 0.--1. " MEMPDPWRSTAT0 ,Memory power domain RAM_PD1 power state" "Off,,,Active"
|
|
else
|
|
bitfld.long 0x00 0.--1. " MEMPDPWRSTAT0 ,Memory power domain RAM_PD1 power state" "Off,Idle,,Active"
|
|
endif
|
|
rgroup.long 0x84++0x03
|
|
line.long 0x00 "MEMPDPWRSTAT1 ,Memory Power Domain Status 1 "
|
|
bitfld.long 0x00 24. " LOGIC_IN_TRANS1 ,Logic in transition status for power domain RAM_PD2" "Active/Off,Power-down/up"
|
|
bitfld.long 0x00 16. " MEM_IN_TRANS1 ,Memory in transition status for power domain RAM_PD2" "Active/Off,Power-down/up"
|
|
bitfld.long 0x00 8. " DOMAIN_ON1 ,Current state of power domain RAM_PD2" "Off,Active"
|
|
newline
|
|
sif cpuis("TMS570LS3137-EP")
|
|
bitfld.long 0x00 0.--1. " MEMPDPWRSTAT1 ,Memory power domain RAM_PD2 power state" "Off,,,Active"
|
|
else
|
|
bitfld.long 0x00 0.--1. " MEMPDPWRSTAT1 ,Memory power domain RAM_PD2 power state" "Off,Idle,,Active"
|
|
endif
|
|
rgroup.long 0x88++0x03
|
|
line.long 0x00 "MEMPDPWRSTAT2 ,Memory Power Domain Status 2 "
|
|
bitfld.long 0x00 24. " LOGIC_IN_TRANS2 ,Logic in transition status for power domain RAM_PD3" "Active/Off,Power-down/up"
|
|
bitfld.long 0x00 16. " MEM_IN_TRANS2 ,Memory in transition status for power domain RAM_PD3" "Active/Off,Power-down/up"
|
|
bitfld.long 0x00 8. " DOMAIN_ON2 ,Current state of power domain RAM_PD3" "Off,Active"
|
|
newline
|
|
sif cpuis("TMS570LS3137-EP")
|
|
bitfld.long 0x00 0.--1. " MEMPDPWRSTAT2 ,Memory power domain RAM_PD3 power state" "Off,,,Active"
|
|
else
|
|
bitfld.long 0x00 0.--1. " MEMPDPWRSTAT2 ,Memory power domain RAM_PD3 power state" "Off,Idle,,Active"
|
|
endif
|
|
endif
|
|
sif (!cpuis("TMS570LS09*")&&!cpuis("TMS570LS07*")&&!cpuis("TMS570LS3137-EP"))
|
|
group.long 0x8C++0x13
|
|
line.long 0x00 "MEMPWRSTAT3,Memory Power Domain Power Status Register"
|
|
line.long 0x04 "MEMPWRSTAT4,Memory Power Domain Power Status Register"
|
|
line.long 0x08 "MEMPWRSTAT5,Memory Power Domain Power Status Register"
|
|
line.long 0x0C "MEMPWRSTAT6,Memory Power Domain Power Status Register"
|
|
line.long 0x10 "MEMPWRSTAT7,Memory Power Domain Power Status Register"
|
|
endif
|
|
group.long 0xA0++0x03
|
|
line.long 0x00 "GLOBALCTRL1,Global Control Register 1"
|
|
bitfld.long 0x00 8. " PMCTRL_PWRDN ,PMC/PSCON power down" "Not powered down,Powered down"
|
|
bitfld.long 0x00 0. " AUTO_CLK_WAKE_ENA ,Automatic clock enable on wake up" "Disabled,Enabled"
|
|
sif (!cpuis("TMS570LS09*")&&!cpuis("TMS570LS07*")&&!cpuis("TMS570LS3137-EP"))
|
|
group.long 0xA4++0x03
|
|
line.long 0x00 "GLOBALCTRL2,Global Control Register 2"
|
|
endif
|
|
rgroup.long 0xA8++0x03
|
|
line.long 0x00 "GLOBALSTAT,Global Status Register"
|
|
bitfld.long 0x00 0. " PMCTRL_IDLE ,State of PMC and all PSCONs" "Not idle,Idle"
|
|
group.long 0xAC++0x17
|
|
line.long 0x00 "PRCKEYREG,PSCON Diagnostic Compare Key Register"
|
|
sif (cpuis("TMS570LS09*")||cpuis("TMS570LS07*"))
|
|
bitfld.long 0x00 0.--3. " MKEY ,Diagnostic PSCON mode key" "Lock step,,,,,,Self-test,,,Error forcing,,,,,,Self-test error forcing"
|
|
else
|
|
bitfld.long 0x00 0.--3. " MKEY ,Diagnostic PSCON mode key" "Lock step,Lock step,Lock step,Lock step,Lock step,Lock step,Self-test,Lock step,Lock step,Error Forcing,Lock step,Lock step,Lock step,Lock step,Lock step,Self-test Error Forcing"
|
|
endif
|
|
newline
|
|
line.long 0x04 "LPDDCSTAT1,Logic PD PSCON Diagnostic Compare Status Register 1"
|
|
sif (cpuis("TMS570LS09*")||cpuis("TMS570LS07*")||cpuis("TMS570LS3137-EP"))
|
|
eventfld.long 0x04 19. " LCMPE[3] ,Logic power domain compare error for PD5" "No error,Error"
|
|
eventfld.long 0x04 18. " [2] ,Logic power domain compare error for PD4" "No error,Error"
|
|
newline
|
|
eventfld.long 0x04 17. " [1] ,Logic power domain compare error for PD3" "No error,Error"
|
|
eventfld.long 0x04 16. " [0] ,Logic power domain compare error for PD2" "No error,Error"
|
|
newline
|
|
rbitfld.long 0x04 3. " LSTC[3] ,Logic power domain self-test complete for PD5" "Not completed,Completed"
|
|
rbitfld.long 0x04 2. " [2] ,Logic power domain self-test complete for PD4" "Not completed,Completed"
|
|
newline
|
|
rbitfld.long 0x04 1. " [1] ,Logic power domain self-test complete for PD3" "Not completed,Completed"
|
|
rbitfld.long 0x04 0. " [0] ,Logic power domain self-test complete for PD2" "Not completed,Completed"
|
|
else
|
|
eventfld.long 0x04 19. " LCMPE[3] ,Logic power domain compare error for PD5" "No error,Error"
|
|
eventfld.long 0x04 18. " [2] ,Logic power domain compare error for PD4" "No error,Error"
|
|
newline
|
|
eventfld.long 0x04 17. " [1] ,Logic power domain compare error for PD3" "No error,Error"
|
|
eventfld.long 0x04 16. " [0] ,Logic power domain compare error for PD2" "No error,Error"
|
|
newline
|
|
bitfld.long 0x04 3. " LSTC[3] ,Logic power domain self-test complete for PD5" "Not completed,Completed"
|
|
bitfld.long 0x04 2. " [2] ,Logic power domain self-test complete for PD4" "Not completed,Completed"
|
|
newline
|
|
bitfld.long 0x04 1. " [1] ,Logic power domain self-test complete for PD3" "Not completed,Completed"
|
|
bitfld.long 0x04 0. " [0] ,Logic power domain self-test complete for PD2" "Not completed,Completed"
|
|
endif
|
|
line.long 0x08 "LPDDCSTAT2,Logic PD PSCON Diagnostic Compare Status Register 2"
|
|
sif (cpuis("TMS570LS09*")||cpuis("TMS570LS07*")||cpuis("TMS570LS3137-EP"))
|
|
rbitfld.long 0x08 19. " LSTET[3] ,Logic power domain self-test error type for PD5" "During match test,During mismatch test"
|
|
rbitfld.long 0x08 18. " [2] ,Logic power domain self-test error type for PD4" "During match test,During mismatch test"
|
|
newline
|
|
rbitfld.long 0x08 17. " [1] ,Logic power domain self-test error type for PD3" "During match test,During mismatch test"
|
|
rbitfld.long 0x08 16. " [0] ,Logic power domain self-test error type for PD2" "During match test,During mismatch test"
|
|
newline
|
|
rbitfld.long 0x08 3. " LSTE[3] ,Logic power domain self-test error for PD5" "No error,Error"
|
|
rbitfld.long 0x08 2. " [2] ,Logic power domain self-test error for PD4" "No error,Error"
|
|
newline
|
|
rbitfld.long 0x08 1. " [1] ,Logic power domain self-test error for PD3" "No error,Error"
|
|
rbitfld.long 0x08 0. " [0] ,Logic power domain self-test error for PD2" "No error,Error"
|
|
else
|
|
bitfld.long 0x08 19. " LSTET[3] ,Logic power domain self-test error type for PD5" "During match test,During mismatch test"
|
|
bitfld.long 0x08 18. " LSTET[2] ,Logic power domain self-test error type for PD4" "During match test,During mismatch test"
|
|
newline
|
|
bitfld.long 0x08 17. " LSTET[1] ,Logic power domain self-test error type for PD3" "During match test,During mismatch test"
|
|
bitfld.long 0x08 16. " LSTET[0] ,Logic power domain self-test error type for PD2" "During match test,During mismatch test"
|
|
newline
|
|
bitfld.long 0x08 3. " LSTE[3] ,Logic power domain self-test error for PD5" "No error,Error"
|
|
bitfld.long 0x08 2. " LSTE[2] ,Logic power domain self-test error for PD4" "No error,Error"
|
|
newline
|
|
bitfld.long 0x08 1. " LSTE[1] ,Logic power domain self-test error for PD3" "No error,Error"
|
|
bitfld.long 0x08 0. " LSTE[0] ,Logic power domain self-test error for PD2" "No error,Error"
|
|
endif
|
|
line.long 0x0C "MPDDCSTAT1,Memory PD PSCON Diagnostic Compare Status Register 1"
|
|
sif cpuis("TMS570LS3137-EP")
|
|
eventfld.long 0x0C 18. " MCMPE2 ,Memory power domain compare error for RAM_PD3" "No error,Error"
|
|
newline
|
|
elif !cpuis("TMS570LS09*")&&!cpuis("TMS570LS07*")
|
|
bitfld.long 0x0C 18. " MCMPE2 ,Memory power domain compare error for RAM_PD3" "No error,Error"
|
|
newline
|
|
endif
|
|
sif (cpuis("TMS570LS09*")||cpuis("TMS570LS07*")||cpuis("TMS570LS3137-EP"))
|
|
eventfld.long 0x0C 17. " [1] ,Memory power domain compare error for RAM_PD2" "No error,Error"
|
|
eventfld.long 0x0C 16. " [0] ,Memory power domain compare error for RAM_PD1" "No error,Error"
|
|
newline
|
|
else
|
|
bitfld.long 0x0C 17. " MCMPE1 ,Memory power domain compare error for RAM_PD2" "No error,Error"
|
|
bitfld.long 0x0C 16. " MCMPE0 ,Memory power domain compare error for RAM_PD1" "No error,Error"
|
|
newline
|
|
endif
|
|
sif cpuis("TMS570LS3137-EP")
|
|
rbitfld.long 0x0C 2. " MSTC2 ,Memory power domain self-test complete for RAM_PD3" "Not completed,Completed"
|
|
newline
|
|
elif (!cpuis("TMS570LS09*")&&!cpuis("TMS570LS07*"))
|
|
bitfld.long 0x0C 2. " MSTC2 ,Memory power domain self-test complete for RAM_PD3" "Not completed,Completed"
|
|
newline
|
|
endif
|
|
sif (cpuis("TMS570LS09*")||cpuis("TMS570LS07*")||cpuis("TMS570LS3137-EP"))
|
|
rbitfld.long 0x0C 1. " [1] ,Memory power domain self-test complete for RAM_PD2" "Not completed,Completed"
|
|
rbitfld.long 0x0C 0. " [0] ,Memory power domain self-test complete for RAM_PD1" "Not completed,Completed"
|
|
else
|
|
bitfld.long 0x0C 1. " MSTC1 ,Memory power domain self-test complete for RAM_PD2" "Not completed,Completed"
|
|
bitfld.long 0x0C 0. " MSTC0 ,Memory power domain self-test complete for RAM_PD1" "Not completed,Completed"
|
|
endif
|
|
line.long 0x10 "MPDDCSTAT2,Memory PD PSCON Diagnostic Compare Status Register 2"
|
|
sif cpuis("TMS570LS3137-EP")
|
|
rbitfld.long 0x10 18. " MSTET2 ,Memory power domain self-test error type for RAM_PD3" "During match test,During mismatch test"
|
|
newline
|
|
endif
|
|
sif (cpuis("TMS570LS09*")||cpuis("TMS570LS07*")||cpuis("TMS570LS3137-EP"))
|
|
rbitfld.long 0x10 17. " [1] ,Memory power domain self-test error type for RAM_PD2" "During match test,During mismatch test"
|
|
rbitfld.long 0x10 16. " [0] ,Memory power domain self-test error type for RAM_PD1" "During match test,During mismatch test"
|
|
newline
|
|
else
|
|
bitfld.long 0x10 18. " MSTET2 ,Memory power domain self-test error type for RAM_PD3" "During match test,During mismatch test"
|
|
bitfld.long 0x10 17. " MSTET1 ,Memory power domain self-test error type for RAM_PD2" "During match test,During mismatch test"
|
|
bitfld.long 0x10 16. " MSTET0 ,Memory power domain self-test error type for RAM_PD1" "During match test,During mismatch test"
|
|
newline
|
|
endif
|
|
sif cpuis("TMS570LS3137-EP")
|
|
rbitfld.long 0x10 2. " MSTE2 ,Memory power domain self-test error for RAM_PD3" "No error,Error"
|
|
newline
|
|
endif
|
|
sif (cpuis("TMS570LS09*")||cpuis("TMS570LS07*")||cpuis("TMS570LS3137-EP"))
|
|
rbitfld.long 0x10 1. " [1] ,Memory power domain self-test error for RAM_PD2" "No error,Error"
|
|
rbitfld.long 0x10 0. " [0] ,Memory power domain self-test error for RAM_PD1" "No error,Error"
|
|
newline
|
|
else
|
|
bitfld.long 0x10 2. " MSTE2 ,Memory power domain self-test error for RAM_PD3" "No error,Error"
|
|
bitfld.long 0x10 1. " MSTE1 ,Memory power domain self-test error for RAM_PD2" "No error,Error"
|
|
bitfld.long 0x10 0. " MSTE0 ,Memory power domain self-test error for RAM_PD1" "No error,Error"
|
|
newline
|
|
endif
|
|
line.long 0x14 "ISODIAGSTAT,Isolation Diagnostic Status Register"
|
|
sif (cpuis("TMS570LS09*")||cpuis("TMS570LS07*")||cpuis("TMS570LS3137-EP"))
|
|
rbitfld.long 0x14 3. " ISO_DIAG3 ,Isolation diagnostic for PD5 disable" "No,Yes"
|
|
rbitfld.long 0x14 2. " [2] ,Isolation diagnostic for PD4 disable" "No,Yes"
|
|
newline
|
|
rbitfld.long 0x14 1. " [1] ,Isolation diagnostic for PD3 disable" "No,Yes"
|
|
rbitfld.long 0x14 0. " [0] ,Isolation diagnostic for PD2 disable" "No,Yes"
|
|
else
|
|
bitfld.long 0x14 3. " ISO_DIAG3 ,Isolation diagnostic for PD5 enable" "Enabled,Disabled"
|
|
bitfld.long 0x14 2. " ISO_DIAG2 ,Isolation diagnostic for PD4 enable" "Enabled,Disabled"
|
|
newline
|
|
bitfld.long 0x14 1. " ISO_DIAG1 ,Isolation diagnostic for PD3 enable" "Enabled,Disabled"
|
|
bitfld.long 0x14 0. " ISO_DIAG0 ,Isolation diagnostic for PD2 enable" "Enabled,Disabled"
|
|
endif
|
|
sif cpuis("TMS570LS09*")||cpuis("TMS570LS07*")||cpuis("TMS570LS0232")
|
|
endian.le
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
endif
|
|
tree "IOMM (I/O Multiplexing and Control Module)"
|
|
base ad:0xFFFFEA00
|
|
sif (cpuis("TMS570LS09*")||cpuis("TMS570LS07*")||cpuis("TMS570LS0232"))
|
|
endian.be
|
|
endif
|
|
width 32.
|
|
rgroup.long 0x00++0x03
|
|
line.long 0x00 "REVISION_REG,Module Revision Register"
|
|
bitfld.long 0x00 30.--31. " REV_SCHEME ,Revision scheme" "0,1,2,3"
|
|
hexmask.long.word 0x00 16.--27. 1. " REV_MODULE ,Module id"
|
|
bitfld.long 0x00 11.--15. " REV_RTL ,RTL revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
bitfld.long 0x00 8.--10. " REV_MAJOR ,Major revision" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 6.--7. " REV_CUSTOM ,Custom revision" "0,1,2,3"
|
|
bitfld.long 0x00 0.--5. " REV_MINOR ,Minor revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
sif cpuis("TMS570LS09*")||cpuis("TMS570LS07*")
|
|
rgroup.long 0x20++0x03
|
|
line.long 0x00 "ENDIAN_REG,Endianness Register"
|
|
bitfld.long 0x00 0. " ENDIAN ,Device endianness" "Little endian,Big endian"
|
|
else
|
|
rgroup.long 0x20++0x03
|
|
line.long 0x00 "BOOT_REG,Boot Mode Register"
|
|
bitfld.long 0x00 0. " ENDIAN ,Device endianness" "Little endian,Big endian"
|
|
endif
|
|
group.long 0x38++0x07
|
|
line.long 0x00 "KICK_REG0,Kicker Register 0"
|
|
line.long 0x04 "KICK_REG1,Kicker Register 1"
|
|
group.long 0xE0++0x07
|
|
line.long 0x00 "ERR_RAW_STATUS_REG,Error Raw Status/Set Register"
|
|
bitfld.long 0x00 1. " ADDR_ERR ,Addressing error status and error signaling enable" "No error,Error"
|
|
bitfld.long 0x00 0. " PROT_ERR ,Protection error status and error signaling enable" "No error,Error"
|
|
line.long 0x04 "ERR_ENABLED_STATUS_REG_SET/CLR,Error Enabled Set/Clear Register"
|
|
setclrfld.long 0x04 1. 0x08 1. 0x0C 1. " ADDR_ERR ,Addressing error signaling enable status and status clear" "Disabled,Enabled"
|
|
setclrfld.long 0x04 0. 0x08 0. 0x0C 0. " PROT_ERR ,Protection error signaling enable status and status clear" "Disabled,Enabled"
|
|
group.long 0xF4++0x03
|
|
line.long 0x00 "FAULT_ADDRESS_REG,Fault Address Register"
|
|
sif (cpuis("TMS570LS09*")||cpuis("TMS570LS07*")||cpuis("TMS570LS0232"))
|
|
hexmask.long.word 0x00 0.--8. 0x01 " FAULT_ADDR ,Fault address"
|
|
endif
|
|
rgroup.long 0xF8++0x03
|
|
line.long 0x00 "FAULT_STATUS_REG,Fault Status Register"
|
|
bitfld.long 0x00 24.--27. " FAULT_ID ,Faulting transaction ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.byte 0x00 16.--23. 1. " FAULT_MSTID ,Id of master that initiated the faulting transaction"
|
|
bitfld.long 0x00 9.--12. " FAULT_PRIVID ,Faulting privilege Id" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
sif (cpu()!=("TMS570LS0332")&&cpu()!=("TMS570LS0432")&&!cpuis("TMS570LS09*")&&!cpuis("TMS570LS07*"))
|
|
bitfld.long 0x00 7. " FAULT_NS ,Fault: Non-secure access detected" "Not detected,Detected"
|
|
endif
|
|
sif (cpuis("TMS570LS09*")||cpuis("TMS570LS07*")||cpuis("TMS570LS0232"))
|
|
newline
|
|
bitfld.long 0x00 0.--5. " FAULT_TYPE ,Type of fault detected" "No fault,User execute fault,User write fault,,User read fault,,,,Supervisor execute fault,,,,,,,,Supervisor write fault,,,,,,,,,,,,,,,,Supervisor read fault,?..."
|
|
else
|
|
newline
|
|
bitfld.long 0x00 0.--5. " FAULT_TYPE ,Type of fault detected" "No fault,User execute fault,User write fault,User read fault,Supervisor execute fault,,,,Supervisor write fault,,,,,,,,,,,,,,,,,,,,,,,,Supervisor read fault,?..."
|
|
endif
|
|
group.long 0xFC++0x03
|
|
line.long 0x00 "FAULT_CLEAR_REG,Fault Clear Register"
|
|
bitfld.long 0x00 0. " FAULT_CLEAR ,Fault clear" "Not cleared,Cleared"
|
|
width 10.
|
|
tree "Output Pin Multiplexing Control Registers"
|
|
sif !cpuis("TMS570LS09*")&&!cpuis("TMS570LS07*")
|
|
group.long 0x110++0x1B
|
|
line.long 0x00 "PINMMR0,PINMMR0 Control Register"
|
|
sif (cpu()==("TMS570LS0332")||cpu()==("TMS570LS0432"))
|
|
bitfld.long 0x00 10. " GIOA[8] ,GIOA[8]" "Disabled,Enabled"
|
|
else
|
|
bitfld.long 0x00 10. " GIOA[0] ,GIOA[0]" "Disabled,Enabled"
|
|
endif
|
|
bitfld.long 0x00 9. " SPI3NCS[3] ,SPI3nCS[3]" "Disabled,Enabled"
|
|
line.long 0x04 "PINMMR1,PINMMR1 Control Register"
|
|
bitfld.long 0x04 25. " SPI2NCS[2] ,SPI2nCS[2]" "Disabled,Enabled"
|
|
bitfld.long 0x04 24. " GIOA[4] ,GIOA[4]" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x04 17. " SPI2NCS[3] ,SPI2nCS[3]" "Disabled,Enabled"
|
|
bitfld.long 0x04 16. " GIOA[3] ,GIOA[3]" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x04 9. " SPI3NCS[1] ,SPI3nCS[1]" "Disabled,Enabled"
|
|
bitfld.long 0x04 8. " GIOA[2] ,GIOA[2]" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x04 1. " SPI3NCS[2] ,SPI3nCS[2]" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " GIOA[1] ,GIOA[1]" "Disabled,Enabled"
|
|
line.long 0x08 "PINMMR2,PINMMR2 Control Register"
|
|
bitfld.long 0x08 17. " N2HET[29] ,N2HET[29]" "Disabled,Enabled"
|
|
bitfld.long 0x08 16. " GIOA[7] ,GIOA[7]" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x08 10. " N2HET[31] ,N2HET[31]" "Disabled,Enabled"
|
|
bitfld.long 0x08 9. " SPI2NCS[1] ,SPI2nCS[1]" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x08 8. " GIOA[6] ,GIOA[6]" "Disabled,Enabled"
|
|
bitfld.long 0x08 1. " EXTCLKIN ,EXTCLKIN" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x08 0. " GIOA[5] ,GIOA[5]" "Disabled,Enabled"
|
|
line.long 0x0C "PINMMR3,PINMMR3 Control Register"
|
|
bitfld.long 0x0C 25. " EQEPB ,EQEPB" "Disabled,Enabled"
|
|
bitfld.long 0x0C 24. " SPI3NENA ,SPI3nENA" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x0C 17. " EQEPA ,EQEPA" "Disabled,Enabled"
|
|
bitfld.long 0x0C 16. " SPI3CLK ,SPI3CLK" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x0C 2. " N2HET[19] ,N2HET[19]" "Disabled,Enabled"
|
|
bitfld.long 0x0C 1. " N2HET[20] ,N2HET[20]" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x0C 0. " MIBSPI1NCS[2] ,MIBSPI1nCS[2]" "Disabled,Enabled"
|
|
line.long 0x10 "PINMMR4,PINMMR4 Control Register"
|
|
bitfld.long 0x10 17. " N2HET[28] ,N2HET[28]" "Disabled,Enabled"
|
|
bitfld.long 0x10 16. " ADEVT ,ADEVT" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x10 9. " N2HET[26] ,N2HET[26]" "Disabled,Enabled"
|
|
bitfld.long 0x10 8. " MIBSPI1NCS[3] ,MIBSPI1nCS[3]" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x10 1. " EQEPI ,EQEPI" "Disabled,Enabled"
|
|
bitfld.long 0x10 0. " SPI3NCS[0] ,SPI3nCS[0]" "Disabled,Enabled"
|
|
line.long 0x14 "PINMMR5,PINMMR5 Control Register"
|
|
sif cpuis("TMS570LS0232")
|
|
bitfld.long 0x14 10. " N2HET[30] ,N2HET[30]" "Disabled,Enabled"
|
|
newline
|
|
endif
|
|
bitfld.long 0x14 9. " N2HET[23] ,N2HET[23]" "Disabled,Enabled"
|
|
bitfld.long 0x14 8. " MIBSPI1NENA ,MIBSPI1NENA" "Disabled,Enabled"
|
|
line.long 0x18 "PINMMR6,PINMMR6 Control Register"
|
|
sif cpuis("TMS570LS0232")
|
|
bitfld.long 0x18 10. " N2HET[17] ,N2HET[17]" "Disabled,Enabled"
|
|
newline
|
|
endif
|
|
bitfld.long 0x18 9. " EQEPS ,EQEPS" "Disabled,Enabled"
|
|
bitfld.long 0x18 8. " MIBSPI1NCS[1] ,MIBSPI1nCS[1]" "Disabled,Enabled"
|
|
else
|
|
sif (cpu()=="TMS570LS0714-PGE"||cpu()=="TMS570LS0914-PGE")
|
|
group.long 0xB10++0x3B
|
|
line.long 0x00 "PINMMR0,PINMMR0 Control Register"
|
|
bitfld.long 0x00 27. " NTZ2 ,NTZ2" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " N2HET1[27] ,N2HET1[27]" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 25. " I2C_SDA ,I2C_SDA" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " MIBSPI3NCS[2] ,MIBSPI3NCS[2]" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 19. " NTZ1 ,nTZ1 " "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " N2HET1[29] ,N2HET1[29] " "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 17. " I2C_SCL ,I2C_SCL" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " MIBSPI3NCS[3] ,MIBSPI3NCS[3]" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 8. " GIOA[0] ,GIOA[0]" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " GIOB[3] ,GIOB[3] " "Disabled,Enabled"
|
|
line.long 0x04 "PINMMR1,PINMMR1 Control Register"
|
|
bitfld.long 0x04 13. " EPWM1SYNCO ,EPWM1SYNCO " "Disabled,Enabled"
|
|
bitfld.long 0x04 10. " N2HET2[18] ,N2HET2[18] " "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x04 9. " MIBSPI3NCS[4] ,MIBSPI3NCS[4] " "Disabled,Enabled"
|
|
bitfld.long 0x04 8. " N2HET1[11] ,N2HET1[11] " "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x04 0. " GIOA[1] ,GIOA[1] " "Disabled,Enabled"
|
|
line.long 0x08 "PINMMR2,PINMMR2 Control Register"
|
|
bitfld.long 0x08 26. " EPWM1A ,EPWM1A " "Disabled,Enabled"
|
|
bitfld.long 0x08 25. " EXTCLKIN1 ,EXTCLKIN1 " "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x08 24. " GIOA[5] ,GIOA[5] " "Disabled,Enabled"
|
|
bitfld.long 0x08 4. " EQEP2I ,EQEP2I " "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x08 3. " N2HET2[0] ,N2HET2[0] " "Disabled,Enabled"
|
|
bitfld.long 0x08 0. " GIOA[2] ,GIOA[2]" "Disabled,Enabled"
|
|
line.long 0x0C "PINMMR3,PINMMR3 Control Register"
|
|
bitfld.long 0x0C 18. " EPWM1B ,EPWM1B " "Disabled,Enabled"
|
|
bitfld.long 0x0C 17. " N2HET2[4] ,N2HET2[4] " "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x0C 16. " GIOA[6] ,GIOA[6] " "Disabled,Enabled"
|
|
bitfld.long 0x0C 8. " N2HET1[22] ,N2HET1[22] " "Disabled,Enabled"
|
|
line.long 0x10 "PINMMR4,PINMMR4 Control Register"
|
|
bitfld.long 0x10 29. " EQEP2B ,EQEP2B " "Disabled,Enabled"
|
|
bitfld.long 0x10 28. " N2HET2[10] ,N2HET2[10] " "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x10 25. " SPI4NCS[0] ,SPI4NCS[0] " "Disabled,Enabled"
|
|
bitfld.long 0x10 24. " N2HET1[03] ,N2HET1[03] " "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x10 21. " EQEP2A ,EQEP2A " "Disabled,Enabled"
|
|
bitfld.long 0x10 20. " N2HET2[8] ,N2HET2[8] " "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x10 17. " SPI4NENA ,SPI4NENA " "Disabled,Enabled"
|
|
bitfld.long 0x10 16. " N2HET1[01] ,N2HET1[01] " "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x10 2. " EPWM2A ,EPWM2A " "Disabled,Enabled"
|
|
bitfld.long 0x10 1. " N2HET2[6] ,N2HET2[6] " "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x10 0. " GIOA[7] ,GIOA[7] " "Disabled,Enabled"
|
|
line.long 0x14 "PINMMR5,PINMMR5 Control Register"
|
|
bitfld.long 0x14 19. " EPWM3B ,EPWM3B " "Disabled,Enabled"
|
|
bitfld.long 0x14 18. " N2HET2[12] ,N2HET2[12] " "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x14 17. " SPI4SOMI ,SPI4SOMI " "Disabled,Enabled"
|
|
bitfld.long 0x14 16. " N2HET1[05] ,N2HET1[05] " "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x14 10. " EPWM3A ,EPWM3A " "Disabled,Enabled"
|
|
bitfld.long 0x14 9. " SPI4SIMO ,SPI4SIMO " "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x14 8. " N2HET1[02] ,N2HET1[02] " "Disabled,Enabled"
|
|
bitfld.long 0x14 2. " EPWM2B ,EPWM2B " "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x14 1. " SPI4CLK ,SPI4CLK " "Disabled,Enabled"
|
|
bitfld.long 0x14 0. " N2HET1[0] ,N2HET1[0] " "Disabled,Enabled"
|
|
line.long 0x18 "PINMMR6,PINMMR6 Control Register"
|
|
bitfld.long 0x18 20. " EPWM7A ,EPWM7A " "Disabled,Enabled"
|
|
bitfld.long 0x18 17. " N2HET2[16] ,N2HET2[16] " "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x18 16. " N2HET1[09] ,N2HET1[09] " "Disabled,Enabled"
|
|
bitfld.long 0x18 4. " EPWM7B ,EPWM7B " "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x18 3. " N2HET2[14] ,N2HET2[14] " "Disabled,Enabled"
|
|
bitfld.long 0x18 0. " N2HET1[07] ,N2HET1[07] " "Disabled,Enabled"
|
|
line.long 0x1C "PINMMR7,PINMMR7 Control Register"
|
|
bitfld.long 0x1C 18. " EPWM5A ,EPWM5A " "Disabled,Enabled"
|
|
bitfld.long 0x1C 17. " SCIRX ,SCIRX " "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x1C 16. " N2HET1[06] ,N2HET1[06] " "Disabled,Enabled"
|
|
bitfld.long 0x1C 9. " N2HET1[25] ,N2HET1[25] " "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x1C 8. " MIBSPI3NCS[1] ,MIBSPI3NCS[1] " "Disabled,Enabled"
|
|
line.long 0x20 "PINMMR8,PINMMR8 Control Register"
|
|
bitfld.long 0x20 18. " ECAP1 ,ECAP1 " "Disabled,Enabled"
|
|
bitfld.long 0x20 17. " MIBSPI1NCS[4] ,MIBSPI1NCS[4] " "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x20 16. " N2HET1[15] ,N2HET1[15] " "Disabled,Enabled"
|
|
bitfld.long 0x20 9. " N2HET1[19] ,N2HET1[19] " "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x20 8. " MIBSPI1NCS[2] ,MIBSPI1NCS[2] " "Disabled,Enabled"
|
|
bitfld.long 0x20 2. " EPWM5B ,EPWM5B " "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x20 1. " SCITX ,SCITX " "Disabled,Enabled"
|
|
bitfld.long 0x20 0. " N2HET1[13] ,N2HET1[13] " "Disabled,Enabled"
|
|
line.long 0x24 "PINMMR9,PINMMR9 Control Register"
|
|
bitfld.long 0x24 19. " EQEP1I ,EQEP1I " "Disabled,Enabled"
|
|
bitfld.long 0x24 18. " GIOB[2] ,GIOB[2] " "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x24 17. " AD2EVT ,AD2EVT " "Disabled,Enabled"
|
|
bitfld.long 0x24 16. " MIBSPI1NCS[2] ,MIBSPI1NCS[2] " "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x24 11. " EQEP1B ,EQEP1B " "Disabled,Enabled"
|
|
bitfld.long 0x24 10. " N2HET1[31] ,N2HET1[31] " "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x24 9. " MIBSPI3NCS[5] ,MIBSPI3NCS[5] " "Disabled,Enabled"
|
|
bitfld.long 0x24 8. " MIBSPI3NENA ,MIBSPI1NCS[2] " "Disabled,Enabled"
|
|
line.long 0x28 "PINMMR10,PINMMR10 Control Register"
|
|
bitfld.long 0x28 0. " AD1EVT ,AD1EVT " "Disabled,Enabled"
|
|
line.long 0x2C "PINMMR11,PINMMR11 Control Register"
|
|
bitfld.long 0x2C 25. " MIBSPI1NCS[5] ,MIBSPI1NCS[5] " "Disabled,Enabled"
|
|
bitfld.long 0x2C 24. " N2HET1[24] ,N2HET1[24] " "Disabled,Enabled"
|
|
line.long 0x30 "PINMMR12,PINMMR12 Control Register"
|
|
bitfld.long 0x30 29. " ECAP5 ,ECAP5 " "Disabled,Enabled"
|
|
bitfld.long 0x30 28. " MIBSPI5SOMI[1] ,MIBSPI5SOMI[1] " "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x30 24. " MIBSPI5NENA ,MIBSPI5NENA " "Disabled,Enabled"
|
|
bitfld.long 0x30 20. " ECAP4 ,ECAP4 " "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x30 17. " N2HET1[23] ,N2HET1[23] " "Disabled,Enabled"
|
|
bitfld.long 0x30 16. " MIBSPI1NENA ,MIBSPI1NENA " "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x30 0. " N2HET1[26] ,N2HET1[26] " "Disabled,Enabled"
|
|
line.long 0x34 "PINMMR13,PINMMR13 Control Register"
|
|
bitfld.long 0x34 28. " ECAP6 ,ECAP6 " "Disabled,Enabled"
|
|
bitfld.long 0x34 25. " MIBSPI1SOMI[1] ,MIBSPI1SOMI[1] " "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x34 24. " MIBSPI1NCS[0] ,MIBSPI1NCS[0] " "Disabled,Enabled"
|
|
bitfld.long 0x34 16. " MIBSPI5CLK ,MIBSPI5CLK " "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x34 12. " MIBSPI5SOMI[2] ,MIBSPI5SOMI[2] " "Disabled,Enabled"
|
|
bitfld.long 0x34 8. " MIBSPI5CLK ,MIBSPI5CLK " "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x34 0. " MIBSPI5SOMI[0] ,MIBSPI5SOMI[0] " "Disabled,Enabled"
|
|
line.long 0x38 "PINMMR14,PINMMR14 Control Register"
|
|
bitfld.long 0x38 8. " N2HET1[28] ,MIBSPI1SIMO[1] " "Disabled,Enabled"
|
|
bitfld.long 0x38 1. " MIBSPI1SIMO[1] ,MIBSPI1SIMO[1] " "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x38 0. " N2HET1[08] ,N2HET1[08] " "Disabled,Enabled"
|
|
group.long 0xB54++0x13
|
|
line.long 0x00 "PINMMR17,PINMMR17 Control Register"
|
|
bitfld.long 0x00 16. " N2HET1[12] ,N2HET1[12] " "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " NTZ3 ,nTZ3 " "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 0. " N2HET1[10] ,N2HET1[10] " "Disabled,Enabled"
|
|
line.long 0x04 "PINMMR18,PINMMR18 Control Register"
|
|
bitfld.long 0x04 24. " GIOB[0] ,GIOB[0] " "Disabled,Enabled"
|
|
bitfld.long 0x04 8. " N2HET1[14] ,N2HET1[14] " "Disabled,Enabled"
|
|
line.long 0x08 "PINMMR19,PINMMR19 Control Register"
|
|
bitfld.long 0x08 11. " EQEP2S ,EQEP2S " "Disabled,Enabled"
|
|
bitfld.long 0x08 8. " N2HET1[30] ,N2HET1[30] " "Disabled,Enabled"
|
|
line.long 0x0C "PINMMR20,PINMMR20 Control Register"
|
|
bitfld.long 0x0C 20. " EQEP1S ,EQEP1S " "Disabled,Enabled"
|
|
bitfld.long 0x0C 17. " N2HET1[17] ,N2HET1[17] " "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x0C 16. " MIBSPI1NCS[1] ,MIBSPI1NCS[1] " "Disabled,Enabled"
|
|
line.long 0x10 "PINMMR21,PINMMR21 Control Register"
|
|
bitfld.long 0x10 8. " GIOB[1] ,GIOB[1] " "Disabled,Enabled"
|
|
group.long 0xB70++0x0F
|
|
line.long 0x00 "PINMMR24,PINMMR24 Control Register"
|
|
bitfld.long 0x00 24. " N2HET1[19] ,N2HET1[19]" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " N2HET1[17] ,N2HET1[17]" "Disabled,Enabled"
|
|
line.long 0x04 "PINMMR25,PINMMR25 Control Register"
|
|
bitfld.long 0x04 24. " N2HET1[27] ,N2HET1[27]" "Disabled,Enabled"
|
|
bitfld.long 0x04 16. " N2HET1[25] ,N2HET1[25]" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x04 8. " N2HET1[23] ,N2HET1[23]" "Disabled,Enabled"
|
|
line.long 0x08 "PINMMR26,PINMMR26 Control Register"
|
|
bitfld.long 0x08 8. " N2HET1[31] ,N2HET1[31]" "Disabled,Enabled"
|
|
bitfld.long 0x08 0. " N2HET1[29] ,N2HET1[29]" "Disabled,Enabled"
|
|
line.long 0x0C "PINMMR27,PINMMR27 Control Register"
|
|
bitfld.long 0x0C 2. " EPWM4A ,EPWM4A " "Disabled,Enabled"
|
|
bitfld.long 0x0C 0. " MIBSPI5NCS[0] ,MIBSPI5NCS[0] " "Disabled,Enabled"
|
|
group.long 0xB84++0x03
|
|
line.long 0x00 "PINMMR29,PINMMR29 Control Register"
|
|
bitfld.long 0x00 16. " GIOB[2] ,GIOB[2]" "Disabled,Enabled"
|
|
group.long 0xB94++0x07
|
|
line.long 0x00 "PINMMR33,PINMMR33 Control Register"
|
|
bitfld.long 0x00 26. " EQEP1A ,EQEP1A " "Disabled,Enabled"
|
|
bitfld.long 0x00 25. " AWM1_EXT_SEL[1] ,AWM1_EXT_SEL[1] " "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 24. " MIBSPI3CLK ,MIBSPI3CLK " "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " ECAP3 ,ECAP3 " "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 17. " AWM1_EXT_SEL[0] ,AWM1_EXT_SEL[0] " "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " MIBSPI3SIMO ,MIBSPI3CLK " "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 10. " ECAP2 ,ECAP2 " "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " AWM1_EXT_ENA ,AWM1_EXT_ENA " "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 8. " MIBSPI3SOMI ,MIBSPI3SOMI " "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " EPWM4B ,EPWM4B " "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 0. " N2HET1[04] ,N2HET1[04] " "Disabled,Enabled"
|
|
line.long 0x04 "PINMMR34,PINMMR34 Control Register"
|
|
bitfld.long 0x04 17. " EPWM6B ,EPWM6B " "Disabled,Enabled"
|
|
bitfld.long 0x04 16. " N2HET1[20] ,N2HET1[20] " "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x04 9. " EPWM6A ,EPWM6A " "Disabled,Enabled"
|
|
bitfld.long 0x04 8. " N2HET1[18] ,N2HET1[18] " "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x04 2. " EPWM1SYNCO ,EPWM1SYNCO " "Disabled,Enabled"
|
|
bitfld.long 0x04 1. " EPWM1SYNCI ,EPWM1SYNCI " "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x04 0. " N2HET1[16] ,N2HET1[16] " "Disabled,Enabled"
|
|
else
|
|
group.long 0xB14++0x13
|
|
line.long 0x00 "PINMMR1,PINMMR1 Control Register"
|
|
bitfld.long 0x00 0. " GIOA[1]/INT[1] ,GIOA[1]/INT[1]" "Disabled,Enabled"
|
|
line.long 0x04 "PINMMR2,PINMMR2 Control Register"
|
|
bitfld.long 0x04 26. " EPWM1A ,EPWM1A " "Disabled,Enabled"
|
|
bitfld.long 0x04 25. " EXTCLKIN1 ,EXTCLKIN1 " "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x04 24. " GIOA[5]/INT[5] ,GIOA[5]/INT[5] " "Disabled,Enabled"
|
|
bitfld.long 0x04 4. " EQEP2I ,EQEP2I " "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x04 3. " N2HET2[0] ,N2HET2[0] " "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " GIOA[2]/INT[2] ,GIOA[2]/INT[2]" "Disabled,Enabled"
|
|
line.long 0x08 "PINMMR3,PINMMR3 Control Register"
|
|
bitfld.long 0x08 18. " EPWM1B ,EPWM1B " "Disabled,Enabled"
|
|
bitfld.long 0x08 17. " N2HET2[4] ,N2HET2[4] " "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x08 16. " GIOA[6]/INT[6] ,GIOA[6]/INT[6] " "Disabled,Enabled"
|
|
line.long 0x0C "PINMMR4,PINMMR4 Control Register"
|
|
bitfld.long 0x0C 2. " EPWM2A ,EPWM2A " "Disabled,Enabled"
|
|
bitfld.long 0x0C 1. " N2HET2[6] ,N2HET2[6] " "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x0C 0. " GIOA[7]/INT[7] ,GIOA[7]/INT[7] " "Disabled,Enabled"
|
|
line.long 0x10 "PINMMR5,PINMMR5 Control Register"
|
|
bitfld.long 0x10 10. " EPWM3A ,EPWM3A " "Disabled,Enabled"
|
|
bitfld.long 0x10 9. " SPI4SIMO ,SPI4SIMO " "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x10 8. " N2HET1[02] ,N2HET1[02] " "Disabled,Enabled"
|
|
bitfld.long 0x10 2. " EPWM2B ,EPWM2B " "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x10 1. " SPI4CLK ,SPI4CLK " "Disabled,Enabled"
|
|
bitfld.long 0x10 0. " N2HET1[0] ,N2HET1[0] " "Disabled,Enabled"
|
|
group.long 0xB2C++0x0B
|
|
line.long 0x00 "PINMMR7,PINMMR7 Control Register"
|
|
bitfld.long 0x00 18. " EPWM5A ,EPWM5A " "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SCIRX ,SCIRX " "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 16. " N2HET1[06] ,N2HET1[06] " "Disabled,Enabled"
|
|
line.long 0x04 "PINMMR8,PINMMR8 Control Register"
|
|
bitfld.long 0x04 9. " N2HET1[19] ,N2HET1[19] " "Disabled,Enabled"
|
|
bitfld.long 0x04 8. " MIBSPI1NCS[2] ,MIBSPI1NCS[2] " "Disabled,Enabled"
|
|
line.long 0x08 "PINMMR9,PINMMR9 Control Register"
|
|
bitfld.long 0x08 19. " EQEP1I ,EQEP1I " "Disabled,Enabled"
|
|
bitfld.long 0x08 18. " GIOB[2] ,GIOB[2] " "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x08 17. " AD2EVT ,AD2EVT " "Disabled,Enabled"
|
|
bitfld.long 0x08 16. " MIBSPI3NCS[0] ,MIBSPI3NCS[0] " "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x08 11. " EQEP1B ,EQEP1B " "Disabled,Enabled"
|
|
bitfld.long 0x08 10. " N2HET1[31] ,N2HET1[31] " "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x08 9. " MIBSPI3NCS[5] ,MIBSPI3NCS[5] " "Disabled,Enabled"
|
|
bitfld.long 0x08 8. " MIBSPI3NENA ,MIBSPI3NCS[0] " "Disabled,Enabled"
|
|
group.long 0xB3C++0x0F
|
|
line.long 0x00 "PINMMR11,PINMMR11 Control Register"
|
|
bitfld.long 0x00 25. " MIBSPI1NCS[5] ,MIBSPI1NCS[5] " "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " N2HET1[24] ,N2HET1[24] " "Disabled,Enabled"
|
|
line.long 0x04 "PINMMR12,PINMMR12 Control Register"
|
|
bitfld.long 0x04 20. " ECAP4 ,ECAP4 " "Disabled,Enabled"
|
|
bitfld.long 0x04 17. " N2HET1[23] ,N2HET1[23] " "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x04 16. " MIBSPI1NENA ,MIBSPI1NCS[2] " "Disabled,Enabled"
|
|
line.long 0x08 "PINMMR13,PINMMR13 Control Register"
|
|
bitfld.long 0x08 28. " ECAP6 ,ECAP6 " "Disabled,Enabled"
|
|
bitfld.long 0x08 25. " MIBSPI1SOMI[1] ,MIBSPI1SOMI[1] " "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x08 24. " MIBSPI1NCS[0] ,MIBSPI1NCS[0] " "Disabled,Enabled"
|
|
line.long 0x0C "PINMMR14,PINMMR14 Control Register"
|
|
bitfld.long 0x0C 1. " MIBSPI1SIMO[1] ,MIBSPI1SIMO[1] " "Disabled,Enabled"
|
|
bitfld.long 0x0C 0. " N2HET1[08] ,N2HET1[08] " "Disabled,Enabled"
|
|
group.long 0xB54++0x03
|
|
line.long 0x00 "PINMMR17,PINMMR17 Control Register"
|
|
bitfld.long 0x00 4. " NTZ3 ,nTZ3 " "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " N2HET1[10] ,N2HET1[10] " "Disabled,Enabled"
|
|
group.long 0xB60++0x03
|
|
line.long 0x00 "PINMMR20,PINMMR20 Control Register"
|
|
bitfld.long 0x00 20. " EQEP1S ,EQEP1S " "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " N2HET1[17] ,N2HET1[17] " "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 16. " MIBSPI1NCS[1] ,MIBSPI1NCS[1] " "Disabled,Enabled"
|
|
group.long 0xB70++0x0B
|
|
line.long 0x00 "PINMMR24,PINMMR24 Control Register"
|
|
bitfld.long 0x00 24. " N2HET1[19] ,N2HET1[19]" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " N2HET1[17] ,N2HET1[17]" "Disabled,Enabled"
|
|
line.long 0x04 "PINMMR25,PINMMR25 Control Register"
|
|
bitfld.long 0x04 8. " N2HET1[23] ,N2HET1[23]" "Disabled,Enabled"
|
|
line.long 0x08 "PINMMR26,PINMMR26 Control Register"
|
|
bitfld.long 0x08 8. " N2HET1[31] ,N2HET1[31]" "Disabled,Enabled"
|
|
group.long 0xB84++0x03
|
|
line.long 0x00 "PINMMR29,PINMMR29 Control Register"
|
|
bitfld.long 0x00 16. " GIOB[2] ,GIOB[2]" "Disabled,Enabled"
|
|
group.long 0xB94++0x07
|
|
line.long 0x00 "PINMMR33,PINMMR33 Control Register"
|
|
bitfld.long 0x00 26. " EQEP1A ,EQEP1A " "Disabled,Enabled"
|
|
bitfld.long 0x00 25. " AWM1_EXT_SEL[1] ,AWM1_EXT_SEL[1] " "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 24. " MIBSPI3CLK ,MIBSPI3CLK " "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " ECAP3 ,ECAP3 " "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 17. " AWM1_EXT_SEL[0] ,AWM1_EXT_SEL[0] " "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " MIBSPI3SIMO[0] ,MIBSPI3SIMO[0] " "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 10. " ECAP2 ,ECAP2 " "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " AWM1_EXT_ENA ,AWM1_EXT_ENA " "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 8. " MIBSPI3SOMI[0] ,MIBSPI3SOMI[0] " "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " EPWM4B ,EPWM4B " "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 0. " N2HET1[04] ,N2HET1[04] " "Disabled,Enabled"
|
|
line.long 0x04 "PINMMR34,PINMMR34 Control Register"
|
|
bitfld.long 0x04 9. " EPWM6A ,EPWM6A " "Disabled,Enabled"
|
|
bitfld.long 0x04 8. " N2HET1[18] ,N2HET1[18] " "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x04 2. " EPWM1SYNCO ,EPWM1SYNCO " "Disabled,Enabled"
|
|
bitfld.long 0x04 1. " EPWM1SYNCI ,EPWM1SYNCI " "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x04 0. " N2HET1[16] ,N2HET1[16] " "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
tree.end
|
|
sif (cpuis("TMS570LS09*")||cpuis("TMS570LS07*")||cpuis("TMS570LS0232"))
|
|
endian.le
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
tree "F021 (Flash Module Controller)"
|
|
base ad:0xFFF87000
|
|
sif (cpuis("TMS570LS09*")||cpuis("TMS570LS07*")||cpuis("TMS570LS0232"))
|
|
endian.be
|
|
endif
|
|
width 16.
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "FRDCNTL,Flash Option Control Register"
|
|
bitfld.long 0x00 8.--11. " RWAIT ,Random read wait state" "0 cycles,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles"
|
|
bitfld.long 0x00 4. " ASWSTEN ,Address setup wait state enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " ENPIPE ,Enable pipeline mode" "Disabled,Enabled"
|
|
group.long 0x08++0x0B
|
|
line.long 0x00 "FEDACCTRL1,Flash Error Detection and Correction Control Register 1"
|
|
bitfld.long 0x00 24. " SUSP_IGNR ,Suspend ignore" "Not ignored,Ignored"
|
|
newline
|
|
sif (cpuis("TMS570LS09*")||cpuis("TMS570LS07*")||cpuis("TMS570LS0232"))
|
|
bitfld.long 0x00 16.--19. " EDACMODE ,Error correction mode for the main flash banks" "Correctable errors,Correctable errors,Correctable errors,Correctable errors,Correctable errors,Uncorrectable errors,Correctable errors,Correctable errors,Correctable errors,Correctable errors,Correctable errors,Correctable errors,Correctable errors,Correctable errors,Correctable errors,Correctable errors"
|
|
newline
|
|
else
|
|
bitfld.long 0x00 16.--19. " EDACMODE ,Error correction mode" "Correction mode,Correction mode,Correction mode,Correction mode,Correction mode,Detection mode,Correction mode,Correction mode,Correction mode,Correction mode,Correction mode,Correction mode,Correction mode,Correction mode,Correction mode,Correction mode"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 10. " EOFEN ,Error on one fail enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " EZFEN ,Event on zeros fail enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " EPEN ,Error profiling enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 0.--3. " EDACEN ,Error detection and correction enable" "Enabled,Enabled,Enabled,Enabled,Enabled,Disabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled"
|
|
line.long 0x04 "FEDACCTRL2,Flash Error Correction and Correction Control Register 2"
|
|
hexmask.long.word 0x04 0.--15. 1. " SEC_THRESHOLD ,Single error correction threshold"
|
|
line.long 0x08 "FCOR_ERR_CNT,Flash Correctable Error Count Register"
|
|
hexmask.long.word 0x08 0.--15. 1. " FERRCNT ,Single error correction count"
|
|
rgroup.long 0x14++0x07
|
|
line.long 0x00 "FCOR_ERR_ADD,Flash Correctable Error Address Register"
|
|
hexmask.long 0x00 3.--31. 0x08 " COR_ERR_ADD ,Correctable error address"
|
|
hexmask.long.byte 0x00 0.--2. 0x01 " B_OFF ,Byte offset"
|
|
line.long 0x04 "FCOR_ERR_POS,Flash Correctable Error Position Register"
|
|
bitfld.long 0x04 9. " BUS2 ,Bus 2 error" "Main flash,OTP read"
|
|
bitfld.long 0x04 8. " TYPE ,Error type" "64 data bits,8 check bits"
|
|
hexmask.long.byte 0x04 0.--7. 1. " ERR_POS ,The bit address of the single bit error"
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "FEDACSTATUS,Flash Error Detection and Correction Status Register"
|
|
eventfld.long 0x00 24. " FSM_DONE ,Flash state machine done" "Not occurred,Occurred"
|
|
eventfld.long 0x00 19. " COMB2_MAL_G ,Bus 2 compare malfunction flag" "Not occurred,Occurred"
|
|
eventfld.long 0x00 18. " ECC_B2_MAL_ERR ,Bus 2 ECC malfunction error flag" "Not occurred,Occurred"
|
|
newline
|
|
eventfld.long 0x00 17. " B2_UNC_ERR ,Bus 2 uncorrectable error" "Not occurred,Occurred"
|
|
eventfld.long 0x00 16. " B2_COR_ERR ,Bus 2 correctable error" "Not occurred,Occurred"
|
|
eventfld.long 0x00 12. " D_UNC_ERR ,Diagnostic uncorrectable error" "Not occurred,Occurred"
|
|
newline
|
|
eventfld.long 0x00 11. " ADD_TAG_ERR ,Address tag register error flag" "Not occurred,Occurred"
|
|
eventfld.long 0x00 10. " ADD_PAR_ERR ,Address parity error" "Not occurred,Occurred"
|
|
eventfld.long 0x00 8. " B1_UNC_ERR ,Bus 1 uncorrectable error flag" "Not occurred,Occurred"
|
|
newline
|
|
eventfld.long 0x00 3. " D_CORR_ERR ,Diagnostic correctable error status flag" "Not occurred,Occurred"
|
|
eventfld.long 0x00 2. " ERR_ONE_FLG ,Error on one fail status flag" "Not occurred,Occurred"
|
|
eventfld.long 0x00 1. " ERR_ZERO_FLG ,Error on zero fail status flag" "Not occurred,Occurred"
|
|
newline
|
|
eventfld.long 0x00 0. " ERR_PRF_FLG ,Error profiling status flag" "Not occurred,Occurred"
|
|
rgroup.long 0x20++0x03
|
|
line.long 0x00 "FUNC_ERR_ADD,Flash Uncorrectable Error Address Register"
|
|
hexmask.long 0x00 3.--31. 0x08 " UNC_ERR_ADD ,Un-correctable error address"
|
|
hexmask.long.byte 0x00 0.--2. 0x01 " B_OFF ,Byte offset"
|
|
newline
|
|
sif (cpuis("TMS570LS09*")||cpuis("TMS570LS07*")||cpuis("TMS570LS0232"))
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "FEDACSDIS,Flash Error Detection and Correction Sector Disable Register"
|
|
bitfld.long 0x0 29.--31. " BANKID1_INVERSE ,Inverted bank number 1" "Bank 7,?..."
|
|
sif cpuis("TMS570LS0232")
|
|
newline
|
|
bitfld.long 0x0 24.--27. " SECTORID1_INVERSE ,Inverted sector number 1" ",,,,,,,,,,,,Sector 3,Sector 2,Sector 1,Sector 0"
|
|
else
|
|
newline
|
|
bitfld.long 0x0 24.--27. " SECTORID1_INVERSE ,Inverted sector number 1" "Sector 15,Sector 14,Sector 13,Sector 12,Sector 11,Sector 10,Sector 9,Sector 8,Sector 7,Sector 6,Sector 5,Sector 4,Sector 3,Sector 2,Sector 1,Sector 0"
|
|
endif
|
|
bitfld.long 0x0 21.--23. " BANKID1 ,Bank number 1" ",,,,,,,Bank 7"
|
|
sif cpuis("TMS570LS0232")
|
|
newline
|
|
bitfld.long 0x0 16.--19. " SECTORID1 ,Sector number 1" "Sector 0,Sector 1,Sector 2,Sector 3,?..."
|
|
else
|
|
newline
|
|
bitfld.long 0x0 16.--19. " SECTORID1 ,Sector number 1" "Sector 0,Sector 1,Sector 2,Sector 3,Sector 4,Sector 5,Sector 6,Sector 7,Sector 8,Sector 9,Sector 10,Sector 11,Sector 12,Sector 13,Sector 14,Sector 15"
|
|
endif
|
|
bitfld.long 0x0 13.--15. " BANKID0_INVERSE ,Inverted bank number 0" "Bank 7,?..."
|
|
sif cpuis("TMS570LS0232")
|
|
newline
|
|
bitfld.long 0x0 8.--11. " SECTORID0_INVERSE ,Inverted sector number 0" ",,,,,,,,,,,,Sector 3,Sector 2,Sector 1,Sector 0"
|
|
else
|
|
newline
|
|
bitfld.long 0x0 8.--11. " SECTORID0_INVERSE ,Inverted sector number 0" "Sector 15,Sector 14,Sector 13,Sector 12,Sector 11,Sector 10,Sector 9,Sector 8,Sector 7,Sector 6,Sector 5,Sector 4,Sector 3,Sector 2,Sector 1,Sector 0"
|
|
endif
|
|
bitfld.long 0x0 5.--7. " BANKID0 ,Bank number 0" "Bank 0,Bank 1,Bank 2,Bank 3,?..."
|
|
sif cpuis("TMS570LS0232")
|
|
newline
|
|
bitfld.long 0x0 0.--3. " SECTORID0 ,Sector number 0" "Sector 0,Sector 1,Sector 2,Sector 3,?..."
|
|
else
|
|
newline
|
|
bitfld.long 0x0 0.--3. " SECTORID0 ,Sector number 0" "Sector 0,Sector 1,Sector 2,Sector 3,Sector 4,Sector 5,Sector 6,Sector 7,Sector 8,Sector 9,Sector 10,Sector 11,Sector 12,Sector 13,Sector 14,Sector 15"
|
|
endif
|
|
else
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "FEDACSDIS,Flash Error Detection and Correction Sector Disable Register"
|
|
bitfld.long 0x0 29.--31. " BANKID1_INVERSE ,Inverted bank number 1" ",,,,Bank 3,Bank 2,Bank 1,Bank 0"
|
|
bitfld.long 0x0 24.--27. " SECTORID1_INVERSE ,Inverted sector number 1" ",,,,,,,,,,,,Sector 3,Sector 2,Sector 1,Sector 0"
|
|
bitfld.long 0x0 21.--23. " BANKID1 ,Bank number 1" "Bank 0,Bank 1,Bank 2,Bank 3,?..."
|
|
newline
|
|
bitfld.long 0x0 16.--19. " SECTORID1 ,Sector number 1" "Sector 0,Sector 1,Sector 2,Sector 3,?..."
|
|
bitfld.long 0x0 13.--15. " BANKID0_INVERSE ,Inverted bank number 0" ",,,,Bank 3,Bank 2,Bank 1,Bank 0"
|
|
bitfld.long 0x0 8.--11. " SECTORID0_INVERSE ,Inverted sector number 0" ",,,,,,Sector 9,Sector 8,Sector 7,Sector 6,Sector 5,Sector 4,Sector 3,Sector 2,Sector 1,Sector 0"
|
|
newline
|
|
bitfld.long 0x0 5.--7. " BANKID0 ,Bank number 0" "Bank 0,Bank 1,Bank 2,Bank 3,?..."
|
|
bitfld.long 0x0 0.--3. " SECTORID0 ,Sector number 0" "Sector 0,Sector 1,Sector 2,Sector 3,Sector 4,Sector 5,Sector 6,Sector 7,Sector 8,Sector 9,?..."
|
|
endif
|
|
newline
|
|
sif (cpuis("TMS570LS09*")||cpuis("TMS570LS07*")||cpuis("TMS570LS0232"))
|
|
if (((per.l.be(ad:0xFFF87000+0x6C))&0xF0007)==0x50005)
|
|
group.long 0x28++0x07
|
|
line.long 0x00 "FPRIM_ADD_TAG,Primary Address Tag Register"
|
|
hexmask.long 0x00 4.--31. 0x10 " PRIM_ADD_TAG ,Primary address tag register"
|
|
line.long 0x04 "FDUP_ADD_TAG,Duplicate Address Tag Register"
|
|
hexmask.long 0x04 4.--31. 0x10 " DUP_ADD_TAG ,Primary address tag register"
|
|
else
|
|
rgroup.long 0x28++0x07
|
|
line.long 0x00 "FPRIM_ADD_TAG,Primary Address Tag Register"
|
|
hexmask.long 0x00 4.--31. 0x10 " PRIM_ADD_TAG ,Primary address tag register"
|
|
line.long 0x04 "FDUP_ADD_TAG,Duplicate Address Tag Register"
|
|
hexmask.long 0x04 4.--31. 0x10 " DUP_ADD_TAG ,Primary address tag register"
|
|
endif
|
|
else
|
|
group.long 0x28++0x07
|
|
line.long 0x00 "FPRIM_ADD_TAG,Primary Address Tag Register"
|
|
hexmask.long 0x00 4.--31. 0x10 " PRIM_ADD_TAG ,Primary address tag register"
|
|
line.long 0x04 "FDUP_ADD_TAG,Duplicate Address Tag Register"
|
|
hexmask.long 0x04 4.--31. 0x10 " DUP_ADD_TAG ,Primary address tag register"
|
|
endif
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "FBPROT,Flash Bank Protection Register"
|
|
sif (cpuis("TMS570LS09*")||cpuis("TMS570LS07*")||cpuis("TMS570LS0232"))
|
|
bitfld.long 0x00 0. " PROTL1DIS ,Level 1 protection disabled" "No,Yes"
|
|
else
|
|
bitfld.long 0x00 0. " PROTL1DIS ,Level 1 protection disabled" "Disabled,Enabled"
|
|
endif
|
|
newline
|
|
sif (cpuis("TMS570LS09*")||cpuis("TMS570LS07*")||cpuis("TMS570LS0232"))
|
|
if (((per.l.be(ad:0xFFF87000+0x30))&0x01)==0x01)
|
|
group.long 0x34++0x03
|
|
line.long 0x00 "FBSE,Flash Bank Sector Enable Register"
|
|
bitfld.long 0x00 15. " BSE[15] ,Bank sector enable 15" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " [14] ,Bank sector enable 14" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " [13] ,Bank sector enable 13" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 12. " [12] ,Bank sector enable 12" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " [11] ,Bank sector enable 11" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " [10] ,Bank sector enable 10" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 9. " [9] ,Bank sector enable 9" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " [8] ,Bank sector enable 8" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " [7] ,Bank sector enable 7" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 6. " [6] ,Bank sector enable 6" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " [5] ,Bank sector enable 5" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " [4] ,Bank sector enable 4" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 3. " [3] ,Bank sector enable 3" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " [2] ,Bank sector enable 2" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " [1] ,Bank sector enable 1" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 0. " [0] ,Bank sector enable 0" "Disabled,Enabled"
|
|
else
|
|
rgroup.long 0x34++0x03
|
|
line.long 0x00 "FBSE,Flash Bank Sector Enable Register"
|
|
bitfld.long 0x00 15. " BSE[15] ,Bank sector enable 15" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " [14] ,Bank sector enable 14" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " [13] ,Bank sector enable 13" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 12. " [12] ,Bank sector enable 12" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " [11] ,Bank sector enable 11" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " [10] ,Bank sector enable 10" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 9. " [9] ,Bank sector enable 9" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " [8] ,Bank sector enable 8" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " [7] ,Bank sector enable 7" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 6. " [6] ,Bank sector enable 6" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " [5] ,Bank sector enable 5" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " [4] ,Bank sector enable 4" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 3. " [3] ,Bank sector enable 3" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " [2] ,Bank sector enable 2" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " [1] ,Bank sector enable 1" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 0. " [0] ,Bank sector enable 0" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
group.long 0x34++0x03
|
|
line.long 0x00 "FBSE,Flash Bank Sector Enable Register"
|
|
bitfld.long 0x00 15. " BSE[15] ,Bank sector enable 15" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " [14] ,Bank sector enable 14" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " [13] ,Bank sector enable 13" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 12. " [12] ,Bank sector enable 12" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " [11] ,Bank sector enable 11" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " [10] ,Bank sector enable 10" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 9. " [9] ,Bank sector enable 9" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " [8] ,Bank sector enable 8" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " [7] ,Bank sector enable 7" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 6. " [6] ,Bank sector enable 6" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " [5] ,Bank sector enable 5" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " [4] ,Bank sector enable 4" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 3. " [3] ,Bank sector enable 3" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " [2] ,Bank sector enable 2" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " [1] ,Bank sector enable 1" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 0. " [0] ,Bank sector enable 0" "Disabled,Enabled"
|
|
endif
|
|
group.long 0x38++0x03
|
|
line.long 0x00 "FBBUSY,Flash Bank Busy Register"
|
|
sif (cpuis("TMS570LS09*")||cpuis("TMS570LS07*")||cpuis("TMS570LS0232"))
|
|
bitfld.long 0x00 7. " BUSY[7] ,Bank 7 busy" "Not busy,Busy"
|
|
bitfld.long 0x00 6. " [6] ,Bank 6 busy" "Not busy,Busy"
|
|
bitfld.long 0x00 5. " [5] ,Bank 5 busy" "Not busy,Busy"
|
|
newline
|
|
bitfld.long 0x00 4. " [4] ,Bank 4 busy" "Not busy,Busy"
|
|
bitfld.long 0x00 3. " [3] ,Bank 3 busy" "Not busy,Busy"
|
|
bitfld.long 0x00 2. " [2] ,Bank 2 busy" "Not busy,Busy"
|
|
newline
|
|
bitfld.long 0x00 1. " [1] ,Bank 1 busy" "Not busy,Busy"
|
|
bitfld.long 0x00 0. " [0] ,Bank 0 busy" "Not busy,Busy"
|
|
newline
|
|
else
|
|
hexmask.long.byte 0x00 0.--7. 1. " BUSY ,Bank busy"
|
|
endif
|
|
sif (cpuis("TMS570LS09*")||cpuis("TMS570LS07*")||cpuis("TMS570LS0232"))
|
|
if (((per.l.be(ad:0xFFF87000+0x30))&0x01)==0x01)
|
|
group.long 0x3C++0x03
|
|
line.long 0x00 "FBAC,Flash Bank Access Control Register"
|
|
bitfld.long 0x00 23. " OTPPROTDIS[7] ,OTP sector protection disable 7" "No,Yes"
|
|
bitfld.long 0x00 22. " [6] ,OTP sector protection disable 6" "No,Yes"
|
|
bitfld.long 0x00 21. " [5] ,OTP sector protection disable 5" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 20. " [4] ,OTP sector protection disable 4" "No,Yes"
|
|
bitfld.long 0x00 19. " [3] ,OTP sector protection disable 3" "No,Yes"
|
|
bitfld.long 0x00 18. " [2] ,OTP sector protection disable 2" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 17. " [1] ,OTP sector protection disable 1" "No,Yes"
|
|
bitfld.long 0x00 16. " [0] ,OTP sector protection disable 0" "No,Yes"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. " BAGP ,Bank active grace period"
|
|
hexmask.long.byte 0x00 0.--7. 1. " VREADST ,VREAD setup"
|
|
else
|
|
group.long 0x3C++0x03
|
|
line.long 0x00 "FBAC,Flash Bank Access Control Register"
|
|
rbitfld.long 0x00 23. " OTPPROTDIS[7] ,OTP sector protection disable 7" "No,Yes"
|
|
rbitfld.long 0x00 22. " [6] ,OTP sector protection disable 6" "No,Yes"
|
|
rbitfld.long 0x00 21. " [5] ,OTP sector protection disable 5" "No,Yes"
|
|
newline
|
|
rbitfld.long 0x00 20. " [4] ,OTP sector protection disable 4" "No,Yes"
|
|
rbitfld.long 0x00 19. " [3] ,OTP sector protection disable 3" "No,Yes"
|
|
rbitfld.long 0x00 18. " [2] ,OTP sector protection disable 2" "No,Yes"
|
|
newline
|
|
rbitfld.long 0x00 17. " [1] ,OTP sector protection disable 1" "No,Yes"
|
|
rbitfld.long 0x00 16. " [0] ,OTP sector protection disable 0" "No,Yes"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. " BAGP ,Bank active grace period"
|
|
hexmask.long.byte 0x00 0.--7. 1. " VREADST ,VREAD setup"
|
|
endif
|
|
else
|
|
group.long 0x3C++0x03
|
|
line.long 0x00 "FBAC,Flash Bank Access Control Register"
|
|
bitfld.long 0x00 23. " OTPPROTDIS[7] ,OTP sector protection disable 7" "No,Yes"
|
|
bitfld.long 0x00 22. " [6] ,OTP sector protection disable 6" "No,Yes"
|
|
bitfld.long 0x00 21. " [5] ,OTP sector protection disable 5" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 20. " [4] ,OTP sector protection disable 4" "No,Yes"
|
|
bitfld.long 0x00 19. " [3] ,OTP sector protection disable 3" "No,Yes"
|
|
bitfld.long 0x00 18. " [2] ,OTP sector protection disable 2" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 17. " [1] ,OTP sector protection disable 1" "No,Yes"
|
|
bitfld.long 0x00 16. " [0] ,OTP sector protection disable 0" "No,Yes"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. " BAGP ,Bank active grace period"
|
|
hexmask.long.byte 0x00 0.--7. 1. " VREADST ,VREAD setup"
|
|
endif
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "FBFALLBACK,Flash Bank Fallback Power Register"
|
|
bitfld.long 0x00 14.--15. " BANKPWR7 ,Bank 7 fall back power mode" "Sleep,Standby,,Active"
|
|
bitfld.long 0x00 2.--3. " BANKPWR1 ,Bank 1 fall back power mode" "Sleep,Standby,,Active"
|
|
bitfld.long 0x00 0.--1. " BANKPWR0 ,Bank 0 fall back power mode" "Sleep,Standby,,Active"
|
|
rgroup.long 0x44++0x03
|
|
line.long 0x00 "FBPRDY,Flash Bank/Pump Ready Register"
|
|
sif (cpuis("TMS570LS09*")||cpuis("TMS570LS07*")||cpuis("TMS570LS0232"))
|
|
bitfld.long 0x00 23. " BANKBUSY[7] ,Bank 7 busy" "Not Busy,Busy"
|
|
bitfld.long 0x00 16. " [0] ,Bank 0 busy" "Not Busy,Busy"
|
|
newline
|
|
else
|
|
bitfld.long 0x00 23. " BANKBUSY[7] ,Bank busy 3" "Not Busy,Busy"
|
|
bitfld.long 0x00 22. " [6] ,Bank busy 2" "Not Busy,Busy"
|
|
bitfld.long 0x00 21. " [5] ,Bank busy 1" "Not Busy,Busy"
|
|
newline
|
|
bitfld.long 0x00 20. " [4] ,Bank busy 0" "Not Busy,Busy"
|
|
bitfld.long 0x00 19. " [3] ,Bank busy 3" "Not Busy,Busy"
|
|
bitfld.long 0x00 18. " [2] ,Bank busy 2" "Not Busy,Busy"
|
|
newline
|
|
bitfld.long 0x00 17. " [1] ,Bank busy 1" "Not Busy,Busy"
|
|
bitfld.long 0x00 16. " [0] ,Bank busy 0" "Not Busy,Busy"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 15. " PUMPRDY ,Pump ready" "Not ready,Ready"
|
|
sif (cpuis("TMS570LS09*")||cpuis("TMS570LS07*")||cpuis("TMS570LS0232"))
|
|
newline
|
|
bitfld.long 0x00 7. " BANKRDY[7] ,Bank 7 ready" "Not ready,Ready"
|
|
bitfld.long 0x00 0. " [0] ,Bank 0 ready" "Not ready,Ready"
|
|
else
|
|
newline
|
|
bitfld.long 0x00 7. " BANKRDY[7] ,Bank ready 3" "Not ready,Ready"
|
|
bitfld.long 0x00 6. " [6] ,Bank ready 2" "Not ready,Ready"
|
|
bitfld.long 0x00 5. " [5] ,Bank ready 1" "Not ready,Ready"
|
|
newline
|
|
bitfld.long 0x00 4. " [4] ,Bank ready 0" "Not ready,Ready"
|
|
bitfld.long 0x00 3. " [3] ,Bank ready 3" "Not ready,Ready"
|
|
bitfld.long 0x00 2. " [2] ,Bank ready 2" "Not ready,Ready"
|
|
newline
|
|
bitfld.long 0x00 1. " [1] ,Bank ready 1" "Not ready,Ready"
|
|
bitfld.long 0x00 0. " [0] ,Bank ready 0" "Not ready,Ready"
|
|
endif
|
|
newline
|
|
group.long 0x48++0x0B
|
|
line.long 0x00 "FPAC1,Flash Pump Access Control Register 1"
|
|
hexmask.long.word 0x00 16.--26. 1. " PSLEEP ,Pump sleep"
|
|
bitfld.long 0x00 0. " PUMPPWR ,Flash charge pump fall back power mode" "Sleep,Active"
|
|
line.long 0x04 "FPAC2,Flash Pump Access Control Register 2"
|
|
hexmask.long.word 0x04 0.--15. 1. " PAGP ,Pump active grace period"
|
|
line.long 0x08 "FMAC,Flash Module Access Control Register"
|
|
sif (cpuis("TMS570LS09*")||cpuis("TMS570LS07*")||cpuis("TMS570LS0232"))
|
|
bitfld.long 0x08 0.--2. " BANK ,Bank enable" "Bank 0,,,,,,,Bank 7"
|
|
else
|
|
bitfld.long 0x08 0.--2. " BANK ,Bank enable" "Bank 0,Bank 1,Bank 2,Bank 3,?..."
|
|
endif
|
|
rgroup.long 0x54++0x03
|
|
line.long 0x00 "FMSTAT,Flash Module Status Register"
|
|
bitfld.long 0x00 14. " ILA ,Illegal address" "Not detected,Detected"
|
|
bitfld.long 0x00 12. " PGV ,Program verify" "Not detected,Detected"
|
|
bitfld.long 0x00 10. " EV ,Erase verify" "Not detected,Detected"
|
|
newline
|
|
bitfld.long 0x00 8. " BUSY ,Busy" "Not detected,Detected"
|
|
bitfld.long 0x00 7. " ERS ,Erase active" "Not detected,Detected"
|
|
bitfld.long 0x00 6. " PGM ,Program active" "Not detected,Detected"
|
|
newline
|
|
bitfld.long 0x00 5. " INVDAT ,Invalid data" "Not detected,Detected"
|
|
bitfld.long 0x00 4. " CSTAT ,Command status" "Not detected,Detected"
|
|
bitfld.long 0x00 3. " VOLTSTAT ,Core voltage status" "Not detected,Detected"
|
|
newline
|
|
bitfld.long 0x00 2. " ESUSP ,Erase suspended" "Not detected,Detected"
|
|
bitfld.long 0x00 1. " PSUSP ,Program suspended" "Not detected,Detected"
|
|
bitfld.long 0x00 0. " SLOCK ,Sector lock status" "Not detected,Detected"
|
|
newline
|
|
group.long 0x58++0x0B
|
|
line.long 0x00 "FEMU_DMSW,EEPROM Emulation Data MSW Register"
|
|
line.long 0x04 "FEMU_DLSW,EEPROM Emulation Data LSW Register"
|
|
line.long 0x08 "FEMU_ECC,EEPROM Emulation ECC Register"
|
|
hexmask.long.byte 0x08 0.--7. 1. " EMU_ECC ,Emulation ECC"
|
|
sif (!cpuis("TMS570LS09*")&&!cpuis("TMS570LS07*")&&!cpuis("TMS570LS0232"))
|
|
group.long 0x64++0x03
|
|
line.long 0x00 "FLOCK,Flash Lock Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " ENCOM ,Enable writes to FEDACCTRL1"
|
|
endif
|
|
group.long 0x68++0x17
|
|
line.long 0x00 "FEMU_ADDR,EEPROM Emulation Address Register"
|
|
hexmask.long.tbyte 0x00 3.--21. 0x08 " FEMU_ADDR ,EEPROM emulation address"
|
|
line.long 0x04 "FDIAGCTRL,Diagnostic Control Register"
|
|
bitfld.long 0x04 24. " DIAG_TRIG ,Diagnostic trigger" "Not triggered,Triggered"
|
|
sif (cpuis("TMS570LS09*")||cpuis("TMS570LS07*")||cpuis("TMS570LS0232"))
|
|
newline
|
|
bitfld.long 0x04 16.--19. " DIAG_EN_KEY ,Diagnostic enable key" "Disabled,Disabled,Disabled,Disabled,Disabled,Enabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled"
|
|
else
|
|
newline
|
|
bitfld.long 0x04 16.--19. " DIAG_EN_KEY ,Diagnostic enable key" "Disabled,Disabled,Disabled,Disabled,Disabled,Enabled,Disabled,Disabled,?..."
|
|
endif
|
|
newline
|
|
bitfld.long 0x04 12.--14. " DIAG_ECC_SEL ,Diagnostic SECDED select" "SECDED0,SECDED1,SECDED2,SECDED3,BUS2 SECDED,FEE SECDED,?..."
|
|
bitfld.long 0x04 8.--9. " DIAG_BUF_SEL ,Diagnostic buffer select" "Instruction buffer 0,Data buffer 0,Instruction buffer 1,Data buffer 1"
|
|
newline
|
|
bitfld.long 0x04 0.--2. " DIAGMODE ,Diagnostic mode" "Disabled,ECC corr,ECC syndrome,ECC test 1,ECC test 2,Address tag,,ECC Data Corr"
|
|
line.long 0x08 "FRAW_DATAH,Uncorrected Raw Data High Register"
|
|
line.long 0x0C "FRAW_DATAL,Uncorrected Raw Data Low Register"
|
|
line.long 0x10 "FRAW_ECC,Uncorrected Raw ECC Register"
|
|
sif (cpuis("TMS570LS09*")||cpuis("TMS570LS07*")||cpuis("TMS570LS0232"))
|
|
eventfld.long 0x10 8. " PIPE_BUF ,Error came from pipeline buffer hit" "No error,Error"
|
|
newline
|
|
else
|
|
bitfld.long 0x10 8. " PIPE_BUF ,Error came from pipeline buffer hit" "No error,Error"
|
|
newline
|
|
endif
|
|
hexmask.long.byte 0x10 0.--7. 1. " RAW_ECC ,Uncorrected raw ECC"
|
|
line.long 0x14 "FPAR_OVR,Parity Override Register"
|
|
bitfld.long 0x14 16. " BNK_INV_PAR ,Buffer invert parity" "SYS_ODD_PARITY,Inverted"
|
|
bitfld.long 0x14 12.--15. " BUS_PAR_DIS ,Disable bus parity" "Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Disabled,Enabled,Enabled,Enabled,Enabled,Enabled"
|
|
newline
|
|
bitfld.long 0x14 9.--11. " PAR_OVR_KEY ,PAR_OVR_KEY" "DEVCR1,DEVCR1,DEVCR1,DEVCR1,DEVCR1,ADD/DAT_INV_PAR,DEVCR1,DEVCR1"
|
|
bitfld.long 0x14 8. " ADD_INV_PAR ,Address odd parity" "Inverted,Not inverted"
|
|
newline
|
|
hexmask.long.byte 0x14 0.--7. 1. " DAT_INV_PAR ,Data odd parity"
|
|
newline
|
|
sif (cpuis("TMS570LS09*")||cpuis("TMS570LS07*")||cpuis("TMS570LS0232"))
|
|
group.long 0xC0++0x03
|
|
line.long 0x00 "FEDACSDIS2,Flash Error Detection and Correction Sector Disable Register 2"
|
|
bitfld.long 0x0 29.--31. " BANKID3_INVERSE ,Inverted bank number 3" "Bank 7,?..."
|
|
sif cpuis("TMS570LS0232")
|
|
newline
|
|
bitfld.long 0x0 24.--27. " SECTORID3_INVERSE ,Inverted sector number 3" ",,,,,,,,,,,,Sector 3,Sector 2,Sector 1,Sector 0"
|
|
else
|
|
newline
|
|
bitfld.long 0x0 24.--27. " SECTORID3_INVERSE ,Inverted sector number 3" "Sector 15,Sector 14,Sector 13,Sector 12,Sector 11,Sector 10,Sector 9,Sector 8,Sector 7,Sector 6,Sector 5,Sector 4,Sector 3,Sector 2,Sector 1,Sector 0"
|
|
endif
|
|
bitfld.long 0x0 21.--23. " BANKID3 ,Bank number 3" ",,,,,,,Bank 7"
|
|
sif cpuis("TMS570LS0232")
|
|
newline
|
|
bitfld.long 0x0 16.--19. " SECTORID3 ,Sector number 3" "Sector 0,Sector 1,Sector 2,Sector 3,?..."
|
|
else
|
|
newline
|
|
bitfld.long 0x0 16.--19. " SECTORID3 ,Sector number 3" "Sector 0,Sector 1,Sector 2,Sector 3,Sector 4,Sector 5,Sector 6,Sector 7,Sector 8,Sector 9,Sector 10,Sector 11,Sector 12,Sector 13,Sector 14,Sector 15"
|
|
endif
|
|
bitfld.long 0x0 13.--15. " BANKID2_INVERSE ,Inverted bank number 2" "Bank 7,?..."
|
|
sif cpuis("TMS570LS0232")
|
|
newline
|
|
bitfld.long 0x0 8.--11. " SECTORID2_INVERSE ,Inverted sector number 2" ",,,,,,,,,,,,Sector 3,Sector 2,Sector 1,Sector 0"
|
|
else
|
|
newline
|
|
bitfld.long 0x0 8.--11. " SECTORID2_INVERSE ,Inverted sector number 2" "Sector 15,Sector 14,Sector 13,Sector 12,Sector 11,Sector 10,Sector 9,Sector 8,Sector 7,Sector 6,Sector 5,Sector 4,Sector 3,Sector 2,Sector 1,Sector 0"
|
|
endif
|
|
bitfld.long 0x0 5.--7. " BANKID2 ,Bank number 2" "Bank 0,Bank 1,Bank 2,Bank 3,?..."
|
|
sif cpuis("TMS570LS0232")
|
|
newline
|
|
bitfld.long 0x0 0.--3. " SECTORID2 ,Sector number 2" "Sector 0,Sector 1,Sector 2,Sector 3,?..."
|
|
else
|
|
newline
|
|
bitfld.long 0x0 0.--3. " SECTORID2 ,Sector number 2" "Sector 0,Sector 1,Sector 2,Sector 3,Sector 4,Sector 5,Sector 6,Sector 7,Sector 8,Sector 9,Sector 10,Sector 11,Sector 12,Sector 13,Sector 14,Sector 15"
|
|
endif
|
|
else
|
|
group.long 0xC0++0x03
|
|
line.long 0x00 "FEDACSDIS2,Flash Error Detection and Correction Sector Disable Register 2"
|
|
bitfld.long 0x00 29.--31. " BANKID3_INVERSE ,Inverted bank number 3" ",,,,Bank 3,Bank 2,Bank 1,Bank 0"
|
|
bitfld.long 0x00 24.--27. " SECTORID3_INVERSE ,Inverted sector number 3" ",,,,,,,,,,,,Sector 3,Sector 2,Sector 1,Sector 0"
|
|
newline
|
|
bitfld.long 0x00 21.--23. " BANKID3 ,Bank number 3" "Bank 0,Bank 1,Bank 2,Bank 3,?..."
|
|
bitfld.long 0x00 16.--19. " SECTORID3 ,Sector number 3" "Sector 0,Sector 1,Sector 2,Sector 3,?..."
|
|
newline
|
|
bitfld.long 0x00 13.--15. " BANKID2_INVERSE ,Inverted bank number 2" ",,,,Bank 3,Bank 2,Bank 1,Bank 0"
|
|
bitfld.long 0x00 8.--11. " SECTORID2_INVERSE ,Inverted sector number 2" ",,,,,,,,,,,,Sector 3,Sector 2,Sector 1,Sector 0"
|
|
newline
|
|
bitfld.long 0x00 5.--7. " BANKID2 ,Bank number 2" "Bank 0,Bank 1,Bank 2,Bank 3,?..."
|
|
bitfld.long 0x00 0.--3. " SECTORID2 ,Sector number 2" "Sector 0,Sector 1,Sector 2,Sector 3,?..."
|
|
endif
|
|
newline
|
|
group.long 0x288++0x03
|
|
line.long 0x00 "FSM_WR_ENA,FSM Register Write Enable"
|
|
bitfld.long 0x00 0.--2. " WR_ENA ,Flash state machine write enable" "Disabled,Disabled,Disabled,Disabled,Disabled,Enabled,Disabled,Disabled"
|
|
group.long 0x2A4++0x03
|
|
line.long 0x00 "FSM_SECTOR,FSM Sector Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " SECT_ERASED ,Sectors erased"
|
|
group.long 0x2B8++0x03
|
|
line.long 0x00 "EEPROM_CONFIG,EEPROM Emulation Configuration Register"
|
|
bitfld.long 0x00 16.--19. " EWAIT ,EEPROM wait state counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 8. " AUTOSUSP_EN ,Auto suspend enable" "Disabled,Enabled"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--7. 1. " AUTOSTART_GRACE ,Auto-suspend startup grace period"
|
|
group.long 0x308++0x0B
|
|
line.long 0x00 "EE_CTRL1,EEPROM Emulation Error Detection and Correction Control Register 1"
|
|
bitfld.long 0x00 16.--19. " EE_EDACMODE ,Error correction mode" "Single-bit errors,Single-bit errors,Single-bit errors,Single-bit errors,Single-bit errors,Detection only,Single-bit errors,Single-bit errors,Single-bit errors,Single-bit errors,Single-bit errors,Single-bit errors,Single-bit errors,Single-bit errors,Single-bit errors,Single-bit errors"
|
|
bitfld.long 0x00 10. " EE_EOFEN ,EEPROM emulation event on a correctable one's fail enable bit" "No ESM,ESM"
|
|
newline
|
|
bitfld.long 0x00 9. " EE_EZFEN ,EEPROM emulation event on a correctable zero's fail enable bit" "No ESM,ESM"
|
|
bitfld.long 0x00 8. " EE_EPEN ,EEPROM emulation error profiling enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 5. " EE_ALL1_OK ,EEPROM emulation all one condition valid" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " EE_ALL0_OK ,EEPROM emulation all zero condition valid" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 0.--3. " EE_EDACEN ,EEPROM emulation error detection and correction enable" "Enabled,Enabled,Enabled,Enabled,Enabled,Disabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled"
|
|
line.long 0x04 "EE_CTRL2,EEPROM Emulation Error Correction and Correction Control Register 2"
|
|
hexmask.long.word 0x04 0.--15. 1. " EE_SEC_THRESHOLD ,EEPROM emulation single error correction threshold"
|
|
line.long 0x08 "EE_COR_ERR_CNT,EEPROM Emulation Correctable Error Count Register"
|
|
hexmask.long.word 0x08 0.--15. 1. " EE_ERRCNT ,Single error correction count"
|
|
rgroup.long 0x314++0x0F
|
|
line.long 0x00 "EE_COR_ERR_ADD,EEPROM Emulation Correctable Error Address Register"
|
|
hexmask.long 0x00 3.--31. 0x08 " COR_ERR_ADD ,Correctable error address"
|
|
bitfld.long 0x00 0.--2. " B_OFF ,Byte offset" "0,1,2,3,4,5,6,7"
|
|
line.long 0x04 "EE_COR_ERR_POS,EEPROM Emulation Correctable Error Position Register"
|
|
bitfld.long 0x04 8. " TYPE ,Error type" "64 data bits,8 check bits"
|
|
hexmask.long.byte 0x04 0.--7. 1. " EE_ERR_POS ,The bit address of the single bit error"
|
|
line.long 0x08 "EE_STATUS,EEPROM Emulation Error Status Register"
|
|
bitfld.long 0x08 12. " EE_D_UNC_ERR ,Diagnostic mode uncorrectable error status flag" "No error,Error"
|
|
bitfld.long 0x08 8. " EE_UNC_ERR ,EEPROM emulation uncorrectable error flag" "No error,Error"
|
|
newline
|
|
bitfld.long 0x08 6. " EE_CMG ,EEPROM emulation compare malfunction good" "No error,Error"
|
|
bitfld.long 0x08 4. " EE_CME ,EEPROM emulation compare malfunction error" "0,1"
|
|
newline
|
|
bitfld.long 0x08 3. " EE_D_COR_ERR ,Diagnostic correctable error flag" "No error,Error"
|
|
bitfld.long 0x08 2. " EE_ERR_ONE_FLG ,Error on one fail error flag" "No error,Error"
|
|
newline
|
|
bitfld.long 0x08 1. " EE_ERR_ZERO_FLG ,Error on zero fail error flag" "No error,Error"
|
|
bitfld.long 0x08 0. " EE_ERR_PRF_FLG ,Error profiling error flag" "No error,Error"
|
|
line.long 0x0C "EE_UNC_ERR_ADD,EEPROM Emulation Uncorrectable Error Address Register"
|
|
sif (cpuis("TMS570LS09*")||cpuis("TMS570LS07*")||cpuis("TMS570LS0232"))
|
|
hexmask.long 0x0C 3.--31. 0x08 " UNC_ERR_ADD ,Uncorrectable error address"
|
|
hexmask.long.byte 0x0C 0.--2. 0x01 " B_OFF ,Byte offset"
|
|
else
|
|
hexmask.long 0x0C 3.--31. 0x08 " COR_ERR_ADD ,Correctable error address"
|
|
bitfld.long 0x0C 0.--2. " B_OFF ,Byte offset" "0,1,2,3,4,5,6,7"
|
|
endif
|
|
rgroup.long 0x400++0x03
|
|
line.long 0x00 "FCFG_BANK,Flash Bank Configuration Register"
|
|
hexmask.long.word 0x00 20.--31. 1. " EE_BANK_WIDTH ,Bank 7 width"
|
|
hexmask.long.word 0x00 4.--15. 1. " MAIN_BANK_WIDTH ,Width of main flash banks"
|
|
sif (cpuis("TMS570LS09*")||cpuis("TMS570LS07*")||cpuis("TMS570LS0232"))
|
|
endian.le
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
tree.open "TCRAM (Tightly-Coupled RAM)"
|
|
tree "RAM ECC Even"
|
|
base ad:0xFFFFF800
|
|
sif (cpuis("TMS570LS09*")||cpuis("TMS570LS07*")||cpuis("TMS570LS0232"))
|
|
endian.be
|
|
endif
|
|
width 17.
|
|
group.long 0x00++0x13
|
|
line.long 0x00 "RAMCTRL,Module Control Register"
|
|
sif cpuis("TMS570LS09*")||cpuis("TMS570LS07*")
|
|
bitfld.long 0x00 30. " EMU_TRACE_DIS ,Emulation mode trace disable" "No,Yes"
|
|
newline
|
|
endif
|
|
sif cpuis("TMS570LS09*")||cpuis("TMS570LS07*")||cpuis("TMS570LS0232")
|
|
bitfld.long 0x00 24.--27. " ADDR_PARITY_OVERRIDE ,Address parity override" "Not inverted,Not inverted,Not inverted,Not inverted,Not inverted,Not inverted,Not inverted,Not inverted,Not inverted,Not inverted,Not inverted,Not inverted,Not inverted,Inverted,Not inverted,Not inverted"
|
|
newline
|
|
else
|
|
bitfld.long 0x00 24.--27. " ADDR_PARITY_OVERRIDE ,Address parity override" "Not inverted,Not inverted,Not inverted,Not inverted,Not inverted,Not inverted,Not inverted,Not inverted,Not inverted,Not inverted,Inverted,Not inverted,Not inverted,Not inverted,Not inverted,Not inverted"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 16.--19. " ADDR_PARITY_DISABLE ,Address parity detect" "Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Disabled,Enabled,Enabled,Enabled,Enabled,Enabled"
|
|
bitfld.long 0x00 8. " ECC_WR_EN ,ECC write enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 0.--3. " ECC_DETECT_EN ,ECC detect enable" "Enabled,Enabled,Enabled,Enabled,Enabled,Disabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled"
|
|
line.long 0x04 "RAMTHRESHOLD,TCRAM Module Single-Bit Error Correction Threshold Register"
|
|
hexmask.long.word 0x04 0.--15. 1. " THRESHOLD ,Single-bit error threshold count"
|
|
line.long 0x08 "RAMOCCUR,TCRAM Module Single-Bit Error Occurrences Counter Register"
|
|
hexmask.long.word 0x08 0.--15. 1. " SINGLE_ERROR_OCCURRENCES ,Single-bit error correction occurrences"
|
|
line.long 0x0C "RAMINTCTRL,TCRAM Module Interrupt Control Register"
|
|
bitfld.long 0x0C 0. " SERR_EN ,Single-bit error correction interrupt enable" "Disabled,Enabled"
|
|
line.long 0x10 "RAMERRSTATUS,Error Status Register"
|
|
eventfld.long 0x10 9. " WADDR_PAR_FAIL ,Write address parity failure" "No failure,Failure"
|
|
eventfld.long 0x10 8. " RADDR_PAR_FAIL ,Read address parity failure" "No failure,Failure"
|
|
newline
|
|
eventfld.long 0x10 5. " DERR ,Multi-bit error" "No error,Error"
|
|
eventfld.long 0x10 4. " ADDR_COMP_LOGIC_FAIL ,Address decode logic element failed" "No failure,Failure"
|
|
newline
|
|
eventfld.long 0x10 2. " ADDR_DEC_FAIL ,Address decode failed" "No failure,Failure"
|
|
eventfld.long 0x10 0. " SERR ,Single error status" "No error,Error"
|
|
rgroup.long 0x14++0x03
|
|
line.long 0x00 "RAMSERRADDR,TCRAM Module Single-Bit Error Address Register"
|
|
hexmask.long.tbyte 0x00 3.--17. 0x08 " SINGLE_ERROR_ADDRESS ,Bits 17-3 of the address for which the Cortex-R4 CPU detects a single-bit error"
|
|
rgroup.long 0x1C++0x03
|
|
line.long 0x00 "RAMUERRADDR,TCRAM Module Uncorrectable Error Address Register"
|
|
hexmask.long.tbyte 0x00 3.--22. 0x08 " UNCORRECTABLE_ERROR_ADDRESS ,Uncorrectable error or an ERROR ADDRESS address parity error"
|
|
sif (cpuis("TMS570LS09*")||cpuis("TMS570LS07*")||cpuis("TMS570LS0232"))
|
|
if (((per.l.be(ad:0xFFFFF800+0x30))&0x0A)==0x0A)
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "RAMTEST,TCRAM Module Test Mode Control Register"
|
|
bitfld.long 0x00 8. " TRIGGER ,Test trigger" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 6.--7. " TEST_MODE ,Test mode" ",Inequality check is done,Equality check is done,?..."
|
|
bitfld.long 0x00 0.--3. " TEST_ENABLE ,Test enable" "Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Enabled,Disabled,Disabled,Disabled,Disabled,Disabled"
|
|
else
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "RAMTEST,TCRAM Module Test Mode Control Register"
|
|
bitfld.long 0x00 6.--7. " TEST_MODE ,Test mode" ",Inequality check is done,Equality check is done,?..."
|
|
bitfld.long 0x00 0.--3. " TEST_ENABLE ,Test enable" "Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Enabled,Disabled,Disabled,Disabled,Disabled,Disabled"
|
|
endif
|
|
group.long 0x38++0x03
|
|
line.long 0x00 "RAMADDRDECVECT,TCRAM RAM Address Decode Vector Test Register"
|
|
bitfld.long 0x00 26. " ECC_SELECT ,ECC select" "Not selected,Selected"
|
|
hexmask.long.word 0x00 0.--15. 1. " RAM_CHIP_SELECT ,RAM chip select"
|
|
rgroup.long 0x3C++0x03
|
|
line.long 0x00 "RAMPERRADDR,TCRAM Module Parity Error Address Register"
|
|
hexmask.long.tbyte 0x00 3.--22. 0x08 " ADDRESS_PARITY_ERROR_ADDRESS ,Parity error address"
|
|
else
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "RAMTEST,L2RAMW Module Test Mode Control Register"
|
|
bitfld.long 0x00 8. " TRIGGER ,Test trigger" "0,1"
|
|
bitfld.long 0x00 6.--7. " TEST_MODE ,Test mode" ",Inequality check is done,Equality check is done,?..."
|
|
newline
|
|
bitfld.long 0x00 0.--3. " TEST_ENABLE ,Test enable" "Disabled,Disabled,Disabled,Disabled,Disabled,Enabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled"
|
|
group.long 0x38++0x03
|
|
line.long 0x00 "RAMADDRDEC_VECT,L2RAMW RAM Address Decode Vector Test Register"
|
|
bitfld.long 0x00 26. " DESV ,Diagnostic ECC select vector" "Not selected,Selected"
|
|
hexmask.long.word 0x00 0.--15. 1. " RAM_CHIP_SELECT ,RAM chip select"
|
|
rgroup.long 0x3C++0x03
|
|
line.long 0x00 "RAMPERRADDR,TCRAM Module Parity Error Address Register"
|
|
hexmask.long.tbyte 0x00 3.--22. 0x08 " ADDRESS_PARITY_ERROR_ADDRESS ,Parity error address"
|
|
endif
|
|
sif cpuis("TMS570LS09*")||cpuis("TMS570LS07*")
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "INIT_DOMAIN,INIT DOMAIN Register"
|
|
bitfld.long 0x00 7. " AUTO_MEM_INIT_ENABLE[7] ,Enable auto-memory initialization for power domain 7" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " [6] ,Enable auto-memory initialization for power domain 6" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 5. " [5] ,Enable auto-memory initialization for power domain 5" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " [4] ,Enable auto-memory initialization for power domain 4" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 3. " [3] ,Enable auto-memory initialization for power domain 3" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " [2] ,Enable auto-memory initialization for power domain 2" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 1. " [1] ,Enable auto-memory initialization for power domain 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,Enable auto-memory initialization for power domain 0" "Disabled,Enabled"
|
|
endif
|
|
sif (cpuis("TMS570LS09*")||cpuis("TMS570LS07*")||cpuis("TMS570LS0232"))
|
|
endian.le
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
tree "RAM ECC Odd"
|
|
base ad:0xFFFFF900
|
|
sif (cpuis("TMS570LS09*")||cpuis("TMS570LS07*")||cpuis("TMS570LS0232"))
|
|
endian.be
|
|
endif
|
|
width 17.
|
|
group.long 0x00++0x13
|
|
line.long 0x00 "RAMCTRL,Module Control Register"
|
|
sif cpuis("TMS570LS09*")||cpuis("TMS570LS07*")
|
|
bitfld.long 0x00 30. " EMU_TRACE_DIS ,Emulation mode trace disable" "No,Yes"
|
|
newline
|
|
endif
|
|
sif cpuis("TMS570LS09*")||cpuis("TMS570LS07*")||cpuis("TMS570LS0232")
|
|
bitfld.long 0x00 24.--27. " ADDR_PARITY_OVERRIDE ,Address parity override" "Not inverted,Not inverted,Not inverted,Not inverted,Not inverted,Not inverted,Not inverted,Not inverted,Not inverted,Not inverted,Not inverted,Not inverted,Not inverted,Inverted,Not inverted,Not inverted"
|
|
newline
|
|
else
|
|
bitfld.long 0x00 24.--27. " ADDR_PARITY_OVERRIDE ,Address parity override" "Not inverted,Not inverted,Not inverted,Not inverted,Not inverted,Not inverted,Not inverted,Not inverted,Not inverted,Not inverted,Inverted,Not inverted,Not inverted,Not inverted,Not inverted,Not inverted"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 16.--19. " ADDR_PARITY_DISABLE ,Address parity detect" "Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Disabled,Enabled,Enabled,Enabled,Enabled,Enabled"
|
|
bitfld.long 0x00 8. " ECC_WR_EN ,ECC write enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 0.--3. " ECC_DETECT_EN ,ECC detect enable" "Enabled,Enabled,Enabled,Enabled,Enabled,Disabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled"
|
|
line.long 0x04 "RAMTHRESHOLD,TCRAM Module Single-Bit Error Correction Threshold Register"
|
|
hexmask.long.word 0x04 0.--15. 1. " THRESHOLD ,Single-bit error threshold count"
|
|
line.long 0x08 "RAMOCCUR,TCRAM Module Single-Bit Error Occurrences Counter Register"
|
|
hexmask.long.word 0x08 0.--15. 1. " SINGLE_ERROR_OCCURRENCES ,Single-bit error correction occurrences"
|
|
line.long 0x0C "RAMINTCTRL,TCRAM Module Interrupt Control Register"
|
|
bitfld.long 0x0C 0. " SERR_EN ,Single-bit error correction interrupt enable" "Disabled,Enabled"
|
|
line.long 0x10 "RAMERRSTATUS,Error Status Register"
|
|
eventfld.long 0x10 9. " WADDR_PAR_FAIL ,Write address parity failure" "No failure,Failure"
|
|
eventfld.long 0x10 8. " RADDR_PAR_FAIL ,Read address parity failure" "No failure,Failure"
|
|
newline
|
|
eventfld.long 0x10 5. " DERR ,Multi-bit error" "No error,Error"
|
|
eventfld.long 0x10 4. " ADDR_COMP_LOGIC_FAIL ,Address decode logic element failed" "No failure,Failure"
|
|
newline
|
|
eventfld.long 0x10 2. " ADDR_DEC_FAIL ,Address decode failed" "No failure,Failure"
|
|
eventfld.long 0x10 0. " SERR ,Single error status" "No error,Error"
|
|
rgroup.long 0x14++0x03
|
|
line.long 0x00 "RAMSERRADDR,TCRAM Module Single-Bit Error Address Register"
|
|
hexmask.long.tbyte 0x00 3.--17. 0x08 " SINGLE_ERROR_ADDRESS ,Bits 17-3 of the address for which the Cortex-R4 CPU detects a single-bit error"
|
|
rgroup.long 0x1C++0x03
|
|
line.long 0x00 "RAMUERRADDR,TCRAM Module Uncorrectable Error Address Register"
|
|
hexmask.long.tbyte 0x00 3.--22. 0x08 " UNCORRECTABLE_ERROR_ADDRESS ,Uncorrectable error or an ERROR ADDRESS address parity error"
|
|
sif (cpuis("TMS570LS09*")||cpuis("TMS570LS07*")||cpuis("TMS570LS0232"))
|
|
if (((per.l.be(ad:0xFFFFF800+0x30))&0x0A)==0x0A)
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "RAMTEST,TCRAM Module Test Mode Control Register"
|
|
bitfld.long 0x00 8. " TRIGGER ,Test trigger" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 6.--7. " TEST_MODE ,Test mode" ",Inequality check is done,Equality check is done,?..."
|
|
bitfld.long 0x00 0.--3. " TEST_ENABLE ,Test enable" "Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Enabled,Disabled,Disabled,Disabled,Disabled,Disabled"
|
|
else
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "RAMTEST,TCRAM Module Test Mode Control Register"
|
|
bitfld.long 0x00 6.--7. " TEST_MODE ,Test mode" ",Inequality check is done,Equality check is done,?..."
|
|
bitfld.long 0x00 0.--3. " TEST_ENABLE ,Test enable" "Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Enabled,Disabled,Disabled,Disabled,Disabled,Disabled"
|
|
endif
|
|
group.long 0x38++0x03
|
|
line.long 0x00 "RAMADDRDECVECT,TCRAM RAM Address Decode Vector Test Register"
|
|
bitfld.long 0x00 26. " ECC_SELECT ,ECC select" "Not selected,Selected"
|
|
hexmask.long.word 0x00 0.--15. 1. " RAM_CHIP_SELECT ,RAM chip select"
|
|
rgroup.long 0x3C++0x03
|
|
line.long 0x00 "RAMPERRADDR,TCRAM Module Parity Error Address Register"
|
|
hexmask.long.tbyte 0x00 3.--22. 0x08 " ADDRESS_PARITY_ERROR_ADDRESS ,Parity error address"
|
|
else
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "RAMTEST,L2RAMW Module Test Mode Control Register"
|
|
bitfld.long 0x00 8. " TRIGGER ,Test trigger" "0,1"
|
|
bitfld.long 0x00 6.--7. " TEST_MODE ,Test mode" ",Inequality check is done,Equality check is done,?..."
|
|
newline
|
|
bitfld.long 0x00 0.--3. " TEST_ENABLE ,Test enable" "Disabled,Disabled,Disabled,Disabled,Disabled,Enabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled"
|
|
group.long 0x38++0x03
|
|
line.long 0x00 "RAMADDRDEC_VECT,L2RAMW RAM Address Decode Vector Test Register"
|
|
bitfld.long 0x00 26. " DESV ,Diagnostic ECC select vector" "Not selected,Selected"
|
|
hexmask.long.word 0x00 0.--15. 1. " RAM_CHIP_SELECT ,RAM chip select"
|
|
rgroup.long 0x3C++0x03
|
|
line.long 0x00 "RAMPERRADDR,TCRAM Module Parity Error Address Register"
|
|
hexmask.long.tbyte 0x00 3.--22. 0x08 " ADDRESS_PARITY_ERROR_ADDRESS ,Parity error address"
|
|
endif
|
|
sif cpuis("TMS570LS09*")||cpuis("TMS570LS07*")
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "INIT_DOMAIN,INIT DOMAIN Register"
|
|
bitfld.long 0x00 7. " AUTO_MEM_INIT_ENABLE[7] ,Enable auto-memory initialization for power domain 7" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " [6] ,Enable auto-memory initialization for power domain 6" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 5. " [5] ,Enable auto-memory initialization for power domain 5" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " [4] ,Enable auto-memory initialization for power domain 4" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 3. " [3] ,Enable auto-memory initialization for power domain 3" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " [2] ,Enable auto-memory initialization for power domain 2" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 1. " [1] ,Enable auto-memory initialization for power domain 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,Enable auto-memory initialization for power domain 0" "Disabled,Enabled"
|
|
endif
|
|
sif (cpuis("TMS570LS09*")||cpuis("TMS570LS07*")||cpuis("TMS570LS0232"))
|
|
endian.le
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
tree.end
|
|
tree "PBIST (Programmable Built-In Self-Test)"
|
|
base ad:0xFFFFE400
|
|
sif (cpuis("TMS570LS09*")||cpuis("TMS570LS07*")||cpuis("TMS570LS0232"))
|
|
endian.be
|
|
endif
|
|
width 9.
|
|
group.long 0x160++0x07
|
|
line.long 0x00 "RAMT,RAM Configuration Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " RGS ,Ram group select"
|
|
hexmask.long.byte 0x00 16.--23. 1. " RDS ,Return data select"
|
|
hexmask.long.byte 0x00 8.--15. 1. " DWR ,Data width register"
|
|
newline
|
|
bitfld.long 0x00 6.--7. " SMS ,Sense margin select register" "0,1,2,3"
|
|
bitfld.long 0x00 2.--5. " PLS ,Pipeline latency select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--1. " RLS ,RAM latency select" "0,1,2,3"
|
|
line.long 0x04 "DLR,Datalogger Register"
|
|
bitfld.long 0x04 4. " DLR4 ,Allow the host processor to configure the PBIST controller" "Not allowed,Allowed"
|
|
bitfld.long 0x04 2. " DLR2 ,Enable PBIST controller to execute test algorithms that are stored in the PBIST ROM" "Disabled,Enabled"
|
|
sif cpuis("TMS570LS0232")
|
|
group.long 0x16C++0x03
|
|
line.long 0x00 "PCR,Program Control Register"
|
|
bitfld.long 0x00 0.--4. " STR ,PBIST controller mode" ",Start/Time stamp mode restart,Resume/Emulation read,,Stop,,,,Step/Step for emulation mode,,Check MISR mode,?..."
|
|
endif
|
|
group.long 0x180++0x0B
|
|
line.long 0x00 "PACT,PBIST Activate/Clock Enable Register"
|
|
sif (!cpuis("TMS570LS09*")&&!cpuis("TMS570LS07*")&&!cpuis("TMS570LS0232"))
|
|
bitfld.long 0x00 1. " PACT1 ,PBIST activate" "Not activated,Activated"
|
|
newline
|
|
endif
|
|
sif (cpuis("TMS570LS09*")||cpuis("TMS570LS07*")||cpuis("TMS570LS0232"))
|
|
bitfld.long 0x00 0. " PACT0 ,PBIST internal clocks enable" "Disabled,Enabled"
|
|
else
|
|
bitfld.long 0x00 0. " PACT0 ,ROM clock enable register" "Disabled,Enabled"
|
|
endif
|
|
line.long 0x04 "PBISTID,PBIST ID Register"
|
|
hexmask.long.byte 0x04 0.--7. 1. " PBIST_ID ,Unique ID assigned to each PBIST controller in a device with multiple PBIST controllers"
|
|
line.long 0x08 "OVER,Override Register"
|
|
bitfld.long 0x08 0. " OVER0 ,RINFO override bit" "No override,Override"
|
|
rgroup.long 0x190++0x03
|
|
line.long 0x00 "FSRF0,Fail Status Fail Register 0"
|
|
bitfld.long 0x00 0. " FSRF0 ,Fail status 0" "Not occurred,Occurred"
|
|
sif (!cpuis("TMS570LS09*")&&!cpuis("TMS570LS07*")&&!cpuis("TMS570LS0232"))
|
|
rgroup.long 0x194++0x03
|
|
line.long 0x00 "FSRF1,Fail Status Fail Register 1"
|
|
bitfld.long 0x00 0. " FSRF1 ,Fail status 1" "Not occurred,Occurred"
|
|
endif
|
|
rgroup.long 0x198++0x13
|
|
line.long 0x00 "FSRC0,Fail Status Count 0 Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " FSRC0 ,Number of failures on port 0"
|
|
line.long 0x04 "FSRC1,Fail Status Count 1 Register"
|
|
hexmask.long.byte 0x04 0.--7. 1. " FSRC1 ,Number of failures on port 1"
|
|
line.long 0x08 "FSRA0,Fail Status Address 0 Registers"
|
|
hexmask.long.word 0x08 0.--15. 1. " FSRA0 ,Address of the first failure"
|
|
line.long 0x0C "FSRA1,Fail Status Address 1 Registers"
|
|
hexmask.long.word 0x0C 0.--15. 1. " FSRA1 ,Address of the first failure"
|
|
line.long 0x10 "FSRDL0,Fail Status Data Register 0"
|
|
sif (cpuis("TMS570LS09*")||cpuis("TMS570LS07*")||cpuis("TMS570LS0232"))
|
|
rgroup.long 0x1B0++0x03
|
|
line.long 0x00 "FSRDL1,Fail Status Data Register 1"
|
|
else
|
|
rgroup.long 0x1AC++0x03
|
|
line.long 0x00 "FSRDL1,Fail Status Data Register 1"
|
|
endif
|
|
group.long 0x1C0++0x07
|
|
line.long 0x00 "ROM,ROM Mask Register"
|
|
bitfld.long 0x00 0.--1. " ROM ,ROM mask" "No information,RAM group,Algorithm,Algorithm & RAM"
|
|
newline
|
|
line.long 0x04 "ALGO,ROM Algorithm Mask Register"
|
|
sif (cpuis("TMS570LS09*")||cpuis("TMS570LS07*")||cpuis("TMS570LS0232"))
|
|
bitfld.long 0x04 31. " ALGO_[31] ,Algorithm powerup_invpowerup - single_port" "Not selected,Selected"
|
|
bitfld.long 0x04 30. " [30] ,Algorithm powerup_invpowerup - two_port" "Not selected,Selected"
|
|
bitfld.long 0x04 29. " [29] ,Algorithm iddqrowstripe - single_port" "Not selected,Selected"
|
|
newline
|
|
bitfld.long 0x04 28. " [28] ,Algorithm iddqrowstripe - two_port" "Not selected,Selected"
|
|
bitfld.long 0x04 27. " [27] ,Algorithm iddqrowstripe - single_port" "Not selected,Selected"
|
|
bitfld.long 0x04 26. " [26] ,Algorithm iddqrowstripe - two_port" "Not selected,Selected"
|
|
newline
|
|
bitfld.long 0x04 25. " [25] ,Algorithm retention - single_port" "Not selected,Selected"
|
|
bitfld.long 0x04 24. " [24] ,Algorithm retention - two_port" "Not selected,Selected"
|
|
bitfld.long 0x04 23. " [23] ,Algorithm iddq - single_port" "Not selected,Selected"
|
|
newline
|
|
bitfld.long 0x04 22. " [22] ,Algorithm iddq - two_port" "Not selected,Selected"
|
|
bitfld.long 0x04 21. " [21] ,Algorithm retention - single_port" "Not selected,Selected"
|
|
bitfld.long 0x04 20. " [20] ,Algorithm retention - two_port" "Not selected,Selected"
|
|
newline
|
|
bitfld.long 0x04 19. " [19] ,Algorithm iddq - single_port" "Not selected,Selected"
|
|
bitfld.long 0x04 18. " [18] ,Algorithm iddq - two_port" "Not selected,Selected"
|
|
bitfld.long 0x04 17. " [17] ,Algorithm flip10 - single_port" "Not selected,Selected"
|
|
newline
|
|
bitfld.long 0x04 16. " [16] ,Algorithm flip10 - two_port" "Not selected,Selected"
|
|
bitfld.long 0x04 15. " [15] ,Algorithm pmos_open_slice2 - two_port" "Not selected,Selected"
|
|
bitfld.long 0x04 14. " [14] ,Algorithm pmos_open_slice1 - two_port" "Not selected,Selected"
|
|
newline
|
|
bitfld.long 0x04 13. " [13] ,Algorithm pmos_open - two_port" "Not selected,Selected"
|
|
bitfld.long 0x04 12. " [12] ,Algorithm pmos_open - two_port" "Not selected,Selected"
|
|
bitfld.long 0x04 11. " [11] ,Algorithm dtxn2 - single_port" "Not selected,Selected"
|
|
newline
|
|
bitfld.long 0x04 10. " [10] ,Algorithm dtxn2 - two_port" "Not selected,Selected"
|
|
bitfld.long 0x04 9. " [9] ,Algorithm precharge - single_port" "Not selected,Selected"
|
|
bitfld.long 0x04 8. " [8] ,Algorithm precharge - two_port" "Not selected,Selected"
|
|
newline
|
|
bitfld.long 0x04 7. " [7] ,Algorithm mapcolumn - single_port" "Not selected,Selected"
|
|
bitfld.long 0x04 6. " [6] ,Algorithm mapcolumn - two_port" "Not selected,Selected"
|
|
bitfld.long 0x04 5. " [5] ,Algorithm down2 - single_port" "Not selected,Selected"
|
|
newline
|
|
bitfld.long 0x04 4. " [4] ,Algorithm down2 - two_port" "Not selected,Selected"
|
|
newline
|
|
else
|
|
bitfld.long 0x04 24. " ALGO_[24] ,Algorithm pmos_open_slice2 - two_port" "Not selected,Selected"
|
|
bitfld.long 0x04 23. " [23] ,Algorithm pmos_open__slice1 - two_port" "Not selected,Selected"
|
|
bitfld.long 0x04 22. " [22] ,Algorithm pmos_open_slice1 - single_port" "Not selected,Selected"
|
|
newline
|
|
bitfld.long 0x04 21. " [21] ,Algorithm dtxn2 - two_port" "Not selected,Selected"
|
|
bitfld.long 0x04 20. " [20] ,Algorithm dtxn2 - single_port" "Not selected,Selected"
|
|
bitfld.long 0x04 19. " [19] ,Algorithm flip10 - two_port" "Not selected,Selected"
|
|
newline
|
|
bitfld.long 0x04 18. " [18] ,Algorithm flip10 - single_port" "Not selected,Selected"
|
|
bitfld.long 0x04 17. " [17] ,Algorithm precharge - two_port" "Not selected,Selected"
|
|
bitfld.long 0x04 16. " [16] ,Algorithm precharge - single_port" "Not selected,Selected"
|
|
newline
|
|
bitfld.long 0x04 15. " [15] ,Algorithm mapcolumn - two_port" "Not selected,Selected"
|
|
bitfld.long 0x04 14. " [14] ,Algorithm mapcolumn - single_port" "Not selected,Selected"
|
|
bitfld.long 0x04 13. " [13] ,Algorithm march_disturb_dec - two_port" "Not selected,Selected"
|
|
newline
|
|
bitfld.long 0x04 12. " [12] ,Algorithm march_disturb_dec - single_port" "Not selected,Selected"
|
|
bitfld.long 0x04 11. " [11] ,Algorithm march_disturb_inc - two_port" "Not selected,Selected"
|
|
bitfld.long 0x04 10. " [10] ,Algorithm march_disturb_inc - single_port" "Not selected,Selected"
|
|
newline
|
|
bitfld.long 0x04 9. " [9] ,Algorithm march_distur_dec - two_port" "Not selected,Selected"
|
|
bitfld.long 0x04 8. " [8] ,Algorithm march_disturb_dec - single_port" "Not selected,Selected"
|
|
bitfld.long 0x04 7. " [7] ,Algorithm march_disturb_inc - two_port" "Not selected,Selected"
|
|
newline
|
|
bitfld.long 0x04 6. " [6] ,Algorithm march_disturb_inc - single_port" "Not selected,Selected"
|
|
bitfld.long 0x04 5. " [5] ,Algorithm down2 - two_port" "Not selected,Selected"
|
|
bitfld.long 0x04 4. " [4] ,Algorithm down2 - single_port" "Not selected,Selected"
|
|
newline
|
|
endif
|
|
bitfld.long 0x04 3. " [3] ,Algorithm march13n - single_port" "Not selected,Selected"
|
|
bitfld.long 0x04 2. " [2] ,Algorithm march13n - two_port" "Not selected,Selected"
|
|
bitfld.long 0x04 1. " [1] ,Algorithm triple_read_fast_read - ROM" "Not selected,Selected"
|
|
newline
|
|
bitfld.long 0x04 0. " [0] ,Algorithm triple_read_slow_read - ROM" "Not selected,Selected"
|
|
newline
|
|
sif (cpuis("TMS570LS09*")||cpuis("TMS570LS07*")||cpuis("TMS570LS0232"))
|
|
if (((per.l.be(ad:0xFFFFE400+0x188))&0x01)==0x00)
|
|
group.long 0x1C8++0x03
|
|
line.long 0x00 "RINFOL,RAM Info Mask Lower Register"
|
|
sif cpuis("TMS570LS09*")||cpuis("TMS570LS07*")
|
|
bitfld.long 0x00 20. " ESRAM5 ,Ram group 21 select" "Not selected,Selected"
|
|
bitfld.long 0x00 19. " HET_TU2 ,Ram group 20 select" "Not selected,Selected"
|
|
newline
|
|
bitfld.long 0x00 18. " N2HET2 ,Ram group 19 select" "Not selected,Selected"
|
|
bitfld.long 0x00 17. " MIBADC2 ,Ram group 18 select" "Not selected,Selected"
|
|
newline
|
|
bitfld.long 0x00 13. " HET_TU1 ,Ram group 14 select" "Not selected,Selected"
|
|
bitfld.long 0x00 12. " N2HET1 ,Ram group 13 select" "Not selected,Selected"
|
|
newline
|
|
bitfld.long 0x00 11. " DMA ,Ram group 12 select" "Not selected,Selected"
|
|
bitfld.long 0x00 10. " MIBADC1 ,Ram group 11 select" "Not selected,Selected"
|
|
newline
|
|
else
|
|
bitfld.long 0x00 13. " HET_TU ,Ram group 14 select" "Not selected,Selected"
|
|
bitfld.long 0x00 12. " N2HET ,Ram group 13 select" "Not selected,Selected"
|
|
newline
|
|
bitfld.long 0x00 10. " MIBADC ,Ram group 11 select" "Not selected,Selected"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 9. " VIM ,Ram group 10 select" "Not selected,Selected"
|
|
newline
|
|
sif cpuis("TMS570LS09*")||cpuis("TMS570LS07*")
|
|
bitfld.long 0x00 8. " MIBSPI5 ,Ram group 9 select" "Not selected,Selected"
|
|
bitfld.long 0x00 7. " MIBSPI3 ,Ram group 8 select" "Not selected,Selected"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 6. " MIBSPI1 ,Ram group 7 select" "Not selected,Selected"
|
|
bitfld.long 0x00 5. " ESRAM1 ,Ram group 6 select" "Not selected,Selected"
|
|
newline
|
|
sif cpuis("TMS570LS09*")||cpuis("TMS570LS07*")
|
|
bitfld.long 0x00 4. " DCAN3 ,Ram group 5 select" "Not selected,Selected"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 3. " DCAN2 ,Ram group 4 select" "Not selected,Selected"
|
|
bitfld.long 0x00 2. " DCAN1 ,Ram group 3 select" "Not selected,Selected"
|
|
newline
|
|
bitfld.long 0x00 1. " STC_ROM ,Ram group 2 select" "Not selected,Selected"
|
|
bitfld.long 0x00 0. " PBIST_ROM ,Ram group 1 select" "Not selected,Selected"
|
|
else
|
|
hgroup.long 0x1C8++0x03
|
|
hide.long 0x00 "RINFOL,RAM Info Mask Lower Register"
|
|
endif
|
|
else
|
|
group.long 0x1C8++0x03
|
|
line.long 0x00 "RINFOL,RAM Info Mask Lower Register"
|
|
bitfld.long 0x00 31. " R5_DCACHE ,RAM group select" "Not selected,Selected"
|
|
bitfld.long 0x00 30. " R5_ICACHE ,RAM group select" "Not selected,Selected"
|
|
newline
|
|
bitfld.long 0x00 29. " L2RAMW ,RAM group select" "Not selected,Selected"
|
|
bitfld.long 0x00 28. " L2RAMW ,RAM group select" "Not selected,Selected"
|
|
newline
|
|
bitfld.long 0x00 27. " CPGMAC_STAT_FIFO ,RAM group select" "Not selected,Selected"
|
|
bitfld.long 0x00 26. " CPGMAC_STATE_RXA_DDR ,RAM group select" "Not selected,Selected"
|
|
newline
|
|
bitfld.long 0x00 25. " FRAY_INBUF_OUTBUF ,RAM group select" "Not selected,Selected"
|
|
bitfld.long 0x00 24. " FTU ,RAM group select" "Not selected,Selected"
|
|
newline
|
|
bitfld.long 0x00 23. " N2HET2 ,RAM group select" "Not selected,Selected"
|
|
bitfld.long 0x00 22. " MIBSPI5 ,RAM group select" "Not selected,Selected"
|
|
newline
|
|
bitfld.long 0x00 21. " MIBSPI4 ,RAM group select" "Not selected,Selected"
|
|
bitfld.long 0x00 20. " HTU2 ,RAM group select" "Not selected,Selected"
|
|
newline
|
|
bitfld.long 0x00 19. " DCAN4 ,RAM group select" "Not selected,Selected"
|
|
bitfld.long 0x00 18. " DCAN3 ,RAM group select" "Not selected,Selected"
|
|
newline
|
|
bitfld.long 0x00 17. " AWM2 ,RAM group select" "Not selected,Selected"
|
|
bitfld.long 0x00 16. " ATB ,RAM group select" "Not selected,Selected"
|
|
newline
|
|
bitfld.long 0x00 15. " RTP ,RAM group select" "Not selected,Selected"
|
|
bitfld.long 0x00 13. " VIM ,RAM group select" "Not selected,Selected"
|
|
newline
|
|
bitfld.long 0x00 12. " N2HET1 ,RAM group select" "Not selected,Selected"
|
|
bitfld.long 0x00 11. " MIBSPI3 ,RAM group select" "Not selected,Selected"
|
|
newline
|
|
bitfld.long 0x00 10. " MIBSPI2 ,RAM group select" "Not selected,Selected"
|
|
bitfld.long 0x00 9. " MIBSPI1 ,RAM group select" "Not selected,Selected"
|
|
newline
|
|
bitfld.long 0x00 8. " HTU1 ,RAM group select" "Not selected,Selected"
|
|
bitfld.long 0x00 7. " DMA ,RAM group select" "Not selected,Selected"
|
|
newline
|
|
bitfld.long 0x00 6. " DCAN2 ,RAM group select" "Not selected,Selected"
|
|
bitfld.long 0x00 5. " DCAN1 ,RAM group select" "Not selected,Selected"
|
|
newline
|
|
bitfld.long 0x00 4. " AWM1 ,RAM group select" "Not selected,Selected"
|
|
bitfld.long 0x00 3. " STC2_ROM_N2HET ,RAM group select" "Not selected,Selected"
|
|
newline
|
|
bitfld.long 0x00 2. " STC1_2_ROM_R5 ,RAM group select" "Not selected,Selected"
|
|
bitfld.long 0x00 1. " STC1_1_ROM_R5 ,RAM group select" "Not selected,Selected"
|
|
newline
|
|
bitfld.long 0x00 0. " PBIST_ROM ,RAM group select" "Not selected,Selected"
|
|
endif
|
|
sif (!cpuis("TMS570LS09*")&&!cpuis("TMS570LS07*")&&!cpuis("TMS570LS0232"))
|
|
newline
|
|
group.long 0x1CC++0x03
|
|
line.long 0x00 "RINFOU,RAM Info Mask Upper Register"
|
|
bitfld.long 0x00 4. " R5_DCACHE_DIRTY ,RAM group select" "Not selected,Selected"
|
|
bitfld.long 0x00 3. " CPGMAC_CPPI ,RAM group select" "Not selected,Selected"
|
|
newline
|
|
bitfld.long 0x00 2. " FRAY_TRBUF_MSGRA_M ,RAM group select" "Not selected,Selected"
|
|
endif
|
|
sif (cpuis("TMS570LS09*")||cpuis("TMS570LS07*")||cpuis("TMS570LS0232"))
|
|
endian.le
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
tree "STC (Self-Test Controller)"
|
|
base ad:0xFFFFE600
|
|
sif (cpuis("TMS570LS09*")||cpuis("TMS570LS07*")||cpuis("TMS570LS0232"))
|
|
endian.be
|
|
endif
|
|
width 7.
|
|
group.long 0x00++0x0B
|
|
line.long 0x0 "GCR0,STC Global Control Register 0"
|
|
hexmask.long.word 0x00 16.--31. 1. " INTCOUNT ,Number of intervals of selftest run"
|
|
bitfld.long 0x00 0. " RS_CNT ,Restart or continue" "Continue,Restart"
|
|
line.long 0x04 "GCR1,STC Global Control Register 1"
|
|
bitfld.long 0x04 0.--3. " STC_ENA ,Self test run enable key" "Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Enabled,Disabled,Disabled,Disabled,Disabled,Disabled"
|
|
line.long 0x08 "TPR,Self-Test Run Timeout Counter Preload Register"
|
|
sif (cpuis("TMS570LS09*")||cpuis("TMS570LS07*")||cpuis("TMS570LS0232"))
|
|
rgroup.long 0x0C++0x03
|
|
line.long 0x00 "CADDR,STC Current ROM Address Register"
|
|
else
|
|
rgroup.long 0x0C++0x03
|
|
line.long 0x00 "ADDR1,STC Current ROM Address Register - CORE1"
|
|
endif
|
|
rgroup.long 0x10++0x03
|
|
line.long 0x00 "CICR,Current Interval Count Register"
|
|
sif (cpuis("TMS570LS09*")||cpuis("TMS570LS07*")||cpuis("TMS570LS0232"))
|
|
hexmask.long.word 0x00 0.--15. 1. " N ,Interval number"
|
|
else
|
|
hexmask.long.word 0x00 0.--15. 1. " CORE1_ICOUNT ,Interval number for Core1"
|
|
endif
|
|
sif (cpuis("TMS570LS09*")||cpuis("TMS570LS07*")||cpuis("TMS570LS0232"))
|
|
group.long 0x14++0x07
|
|
line.long 0x00 "GSTAT,Self-Test Global Status Register"
|
|
bitfld.long 0x00 1. " TEST_FAIL ,Test fail" "Not failed,Failed"
|
|
bitfld.long 0x00 0. " TEST_DONE ,Test done" "Not completed,Completed"
|
|
line.long 0x04 "FSTAT,Self-Test Fail Status Register"
|
|
bitfld.long 0x04 2. " TO_ERR ,Timeout error" "Not Occurred,Occurred"
|
|
bitfld.long 0x04 1. " CPU2_FAIL ,CPU2 failure info" "No mismatch,Mismatch"
|
|
bitfld.long 0x04 0. " CPU1_FAIL ,CPU1 failure info" "No mismatch,Mismatch"
|
|
else
|
|
rgroup.long 0x14++0x07
|
|
line.long 0x00 "GSTAT,Self-Test Global Status Register"
|
|
bitfld.long 0x00 1. " TEST_FAIL ,Test fail" "Not failed,Failed"
|
|
bitfld.long 0x00 0. " TEST_DONE ,Test done" "Not completed,Completed"
|
|
line.long 0x04 "FSTAT,Self-Test Fail Status Register"
|
|
bitfld.long 0x04 2. " TO_ERR ,Timeout error" "Not Occurred,Occurred"
|
|
bitfld.long 0x04 1. " CPU2_FAIL ,CPU2 failure info" "No mismatch,Mismatch"
|
|
bitfld.long 0x04 0. " CPU1_FAIL ,CPU1 failure info" "No mismatch,Mismatch"
|
|
endif
|
|
newline
|
|
width 16.
|
|
sif (cpu()!=("TMS570LS0332")&&cpu()!=("TMS570LS0432"))
|
|
rgroup.long 0x1C++0x0F
|
|
line.long 0x00 "CORE1_CURMISR3,CORE1 Current MISR Register"
|
|
line.long 0x04 "CORE1_CURMISR2,CORE1 Current MISR Register"
|
|
line.long 0x08 "CORE1_CURMISR1,CORE1 Current MISR Register"
|
|
line.long 0x0C "CORE1_CURMISR0,CORE1 Current MISR Register"
|
|
rgroup.long 0x2C++0x0F
|
|
line.long 0x00 "CORE2_CURMISR3,CORE2 Current MISR Register"
|
|
line.long 0x04 "CORE2_CURMISR2,CORE2 Current MISR Register"
|
|
line.long 0x08 "CORE2_CURMISR1,CORE2 Current MISR Register"
|
|
line.long 0x0C "CORE2_CURMISR0,CORE2 Current MISR Register"
|
|
else
|
|
rgroup.long 0x1C++0x0F
|
|
line.long 0x00 "CPU1_CURMISR3,CORE1 Current MISR Register"
|
|
line.long 0x04 "CPU1_CURMISR2,CORE1 Current MISR Register"
|
|
line.long 0x08 "CPU1_CURMISR1,CORE1 Current MISR Register"
|
|
line.long 0x0C "CPU1_CURMISR0,CORE1 Current MISR Register"
|
|
rgroup.long 0x2C++0x0F
|
|
line.long 0x00 "CPU2_CURMISR3,CORE2 Current MISR Register"
|
|
line.long 0x04 "CPU2_CURMISR2,CORE2 Current MISR Register"
|
|
line.long 0x08 "CPU2_CURMISR1,CORE2 Current MISR Register"
|
|
line.long 0x0C "CPU2_CURMISR0,CORE2 Current MISR Register"
|
|
endif
|
|
newline
|
|
width 7.
|
|
group.long 0x3C++0x03
|
|
line.long 0x00 "SCSCR,Signature Compare Self-Check Register"
|
|
bitfld.long 0x00 4. " FAULT_INS ,Insert stuck-at fault inside CPU" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--3. " SELF_CHECK_KEY ,Signature compare logic self-check enable key" "Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Enabled,Disabled,Disabled,Disabled,Disabled,Disabled"
|
|
sif (cpuis("TMS570LS09*")||cpuis("TMS570LS07*")||cpuis("TMS570LS0232"))
|
|
endian.le
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
tree "CCM-R4 (CPU Compare Module for Cortex-R4)"
|
|
base ad:0xFFFFF600
|
|
sif (cpuis("TMS570LS09*")||cpuis("TMS570LS07*")||cpuis("TMS570LS0232"))
|
|
endian.be
|
|
endif
|
|
width 9.
|
|
group.long 0x00++0x7
|
|
line.long 0x00 "CCMSR,CCM-R4F Status Register"
|
|
eventfld.long 0x00 16. " CMPE ,CPU output signals compare error" "No error,Error"
|
|
rbitfld.long 0x00 8. " STC ,CPU output compare diagnostic self-test complete" "Not completed,Completed"
|
|
rbitfld.long 0x00 1. " STET ,Self-test error type" "Match test fail,Mismatch test fail"
|
|
rbitfld.long 0x00 0. " STE ,CPU output compare diagnostic status" "No error,Error"
|
|
line.long 0x04 "CCMKEYR,CCM-R4 Key Register"
|
|
bitfld.long 0x04 0.--3. " MKEY ,Mode key" "Lockstep,,,,,,Self-test,,,Error forcing,,,,,,Self-test error forcing"
|
|
sif (cpuis("TMS570LS09*")||cpuis("TMS570LS07*")||cpuis("TMS570LS0232"))
|
|
endian.le
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
tree "PLL (Phase-Locked Loop)"
|
|
base ad:0xFFFFE100
|
|
sif (cpuis("TMS570LS09*")||cpuis("TMS570LS07*")||cpuis("TMS570LS0232"))
|
|
endian.be
|
|
endif
|
|
width 15.
|
|
sif (cpuis("RM57L843-ZWT")||cpuis("TMS570LS09*")||cpuis("TMS570LS07*")||cpuis("TMS570LS0232")||cpuis("TMS570LS3137-EP"))
|
|
group.long 0x1E30++0x03
|
|
line.long 0x00 "CSDIS_SET/CLR,Clock Source Disable Set/Clear Register"
|
|
sif !cpuis("TMS570LS0232")
|
|
setclrfld.long 0x00 7. 0x04 7. 0x08 7. " CLKSR7_OFF ,Clock source 7 (External clock in 2) disable" "No,Yes"
|
|
newline
|
|
endif
|
|
sif !cpuis("TMS570LS09*")&&!cpuis("TMS570LS07*")&&!cpuis("TMS570LS0232")
|
|
setclrfld.long 0x00 6. 0x04 6. 0x08 6. " CLKSR6_OFF ,Clock source 6 (Pll2) disable" "No,Yes"
|
|
newline
|
|
endif
|
|
setclrfld.long 0x00 5. 0x04 5. 0x08 5. " CLKSR5_OFF ,Clock source 5 (LPO high frequency clock) disable" "No,Yes"
|
|
setclrfld.long 0x00 4. 0x04 4. 0x08 4. " CLKSR4_OFF ,Clock source 4 (LPO low frequency clock) disable" "No,Yes"
|
|
setclrfld.long 0x00 3. 0x04 3. 0x08 3. " CLKSR3_OFF ,Clock source 3 (External clock in) disable" "No,Yes"
|
|
newline
|
|
setclrfld.long 0x00 1. 0x04 1. 0x08 1. " CLKSR1_OFF ,Clock source 1 (PLL1) disable" "No,Yes"
|
|
setclrfld.long 0x00 0. 0x04 0. 0x08 0. " CLKSR0_OFF ,Clock source 0 (Oscillator) disable" "No,Yes"
|
|
rgroup.long 0x1E54++0x03
|
|
line.long 0x00 "CSVSTAT,Clock Source Valid Status Register"
|
|
sif !cpuis("TMS570LS0232")
|
|
bitfld.long 0x00 7. " CLKSR7V ,Clock source 7 valid" "Not valid,Valid"
|
|
newline
|
|
endif
|
|
sif !cpuis("TMS570LS09*")&&!cpuis("TMS570LS07*")&&!cpuis("TMS570LS0232")
|
|
bitfld.long 0x00 6. " CLKSR6V ,Clock source 6 valid" "Not valid,Valid"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 5. " CLKSR5V ,Clock source 5 valid" "Not valid,Valid"
|
|
bitfld.long 0x00 4. " CLKSR4V ,Clock source 4 valid" "Not valid,Valid"
|
|
bitfld.long 0x00 3. " CLKSR3V ,Clock source 3 valid" "Not valid,Valid"
|
|
newline
|
|
bitfld.long 0x00 1. " CLKSR1V ,Clock source 1 valid" "Not valid,Valid"
|
|
bitfld.long 0x00 0. " CLKSR0V ,Clock source 0 valid" "Not valid,Valid"
|
|
endif
|
|
group.long 0x1E70++0x07
|
|
line.long 0x00 "PLLCTL1,PLL Control 1 Register"
|
|
bitfld.long 0x00 31. " ROS ,Reset on PLL slip" "No reset,Reset"
|
|
sif (cpuis("TMS570LS09*")||cpuis("TMS570LS07*")||cpuis("TMS570LS0232")||cpuis("TMS570LS3137-EP"))
|
|
bitfld.long 0x00 29.--30. " MASK_SLIP ,Bypass of PLL slip" "Bypassed,Bypassed,Not bypassed,Bypassed"
|
|
else
|
|
bitfld.long 0x00 29.--30. " BPOS ,Bypass of PLL slip" "Bypassed,Bypassed,Not bypassed,Bypassed"
|
|
endif
|
|
bitfld.long 0x00 24.--28. " PLLDIV ,PLL output clock divider" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32"
|
|
newline
|
|
bitfld.long 0x00 23. " ROF ,Reset on oscillator fail" "No reset,Reset"
|
|
sif (cpuis("TMS570LS09*")||cpuis("TMS570LS07*")||cpuis("TMS570LS0232")||cpuis("TMS570LS3137-EP"))
|
|
bitfld.long 0x00 16.--21. " REFCLKDIV ,Reference clock divider" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/50,/61,/62,/63,/64"
|
|
newline
|
|
else
|
|
bitfld.long 0x00 16.--21. " REFCLKDIV ,Reference clock divider" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/50,/61,/62,/63,?..."
|
|
newline
|
|
endif
|
|
hexmask.long.word 0x00 0.--15. 1. " PLLMUL ,PLL multiplication factor"
|
|
line.long 0x04 "PLLCTL2,PLL Control 2 Register"
|
|
bitfld.long 0x04 31. " FMENA ,Frequency modulation enable" "Disabled,Enabled"
|
|
hexmask.long.word 0x04 22.--30. 1. " SPREADINGRATE ,Spreading rate"
|
|
hexmask.long.word 0x04 12.--20. 1. " MULMOD ,Multiplier correction"
|
|
newline
|
|
bitfld.long 0x04 9.--11. " ODPLL ,Internal PLL output divider" "/1,/2,/3,/4,/5,/6,/7,/8"
|
|
hexmask.long.word 0x04 0.--8. 1. " SPR_AMOUNT ,Spreading amount"
|
|
sif (cpu()!=("TMS570LS0332")&&cpu()!=("TMS570LS0432"))&&!cpuis("TMS570LS09*")&&!cpuis("TMS570LS07*")&&!cpuis("TMS570LS0232")
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "PLLCTL3,PLL Control 3 Register"
|
|
sif cpuis("TMS570LS3137-EP")
|
|
bitfld.long 0x00 29.--31. " ODPLL2 ,Internal PLL output divider" "/1,/2,/3,/4,/5,/6,/7,/8"
|
|
bitfld.long 0x00 24.--28. " PLLDIV2 ,PLL output clock divider" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32"
|
|
else
|
|
bitfld.long 0x00 29.--31. " ODPLL ,Internal PLL output divider" "/1,/2,/3,/4,/5,/6,/7,/8"
|
|
bitfld.long 0x00 24.--28. " PLLDIV ,PLL output clock divider" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32"
|
|
endif
|
|
sif !cpuis("TMS570LS3137-EP")
|
|
bitfld.long 0x00 16.--21. " REFCLKDIV ,Reference clock divider" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/50,/61,/62,/63,?..."
|
|
else
|
|
bitfld.long 0x00 16.--21. " REFCLKDIV2 ,Reference clock divider" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/50,/61,/62,/63,/64"
|
|
endif
|
|
newline
|
|
sif cpuis("TMS570LS3137-EP")
|
|
hexmask.long.word 0x00 0.--15. 1. " PLLMUL2 ,PLL multiplication factor"
|
|
else
|
|
hexmask.long.word 0x00 0.--15. 1. " PLLMUL ,PLL multiplication factor"
|
|
endif
|
|
group.long 0x70++0x03
|
|
line.long 0x00 "CLKSLIP,PLL Clock Slip Control Register"
|
|
bitfld.long 0x00 8.--13. " PLL1_RFSLIP_FILTER_COUNT ,Number of HFLPO cycles to be recognized by RFSLIP as a slip" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x00 0.--3. " PLL1_RFSLIP_FILTER_KEY ,PLL1 RFSLIP filtering enable key" "Enabled,Enabled,Enabled,Enabled,Enabled,Disabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,?..."
|
|
group.long 0x1EA0++0x03
|
|
line.long 0x00 "GPREG1,General Purpose Register 1"
|
|
sif cpuis("TMS570LS3137-EP")
|
|
bitfld.long 0x00 31. " EMIF_FUNC ,EMIF functions" "Disabled,Enabled"
|
|
endif
|
|
newline
|
|
bitfld.long 0x00 20.--25. " PLL1_FBSLIP_FILTER_COUNT ,Number of HFLPO cycles to be recognized by FBSLIP as a slip" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x00 16.--19. " PLL1_FBSLIP_FILTER_KEY ,PLL1 FBSLIP filtering enable key" "Enabled,Enabled,Enabled,Enabled,Enabled,Disabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,?..."
|
|
sif cpuis("TMS570LS3137-EP")
|
|
newline
|
|
bitfld.long 0x00 15. " OUTPUT_BUFFER_LOW_EMI_MODE[15] ,Control field for the low-EMI mode of output buffer for RTP" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " [14] ,Control field for the low-EMI mode of output buffer for ADEVT" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " [13] ,Control field for the low-EMI mode of output buffer for nERROR" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 12. " [12] ,Control field for the low-EMI mode of output buffer for TEST" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " [11] ,Control field for the low-EMI mode of output buffer for RTCK" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " [10] ,Control field for the low-EMI mode of output buffer for TDO" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 9. " [9] ,Control field for the low-EMI mode of output buffer for TDI" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " [8] ,Control field for the low-EMI mode of output buffer for TMS" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " [7] ,Control field for the low-EMI mode of output buffer for ETM" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 6. " [6] ,Control field for the low-EMI mode of output buffer for EMIF" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " [5] ,Control field for the low-EMI mode of output buffer for FlexRay" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " [4] ,Control field for the low-EMI mode of output buffer for MiBSPI5" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 3. " [3] ,Control field for the low-EMI mode of output buffer for SPI4" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " [2] ,Control field for the low-EMI mode of output buffer for MiBSPI3" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " [1] ,Control field for the low-EMI mode of output buffer for SPI2" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 0. " [0] ,Control field for the low-EMI mode of output buffer for MiBSPI1" "Disabled,Enabled"
|
|
endif
|
|
sif (cpuis("RM57L843-ZWT")||cpuis("TMS570LS3137-EP"))
|
|
group.long 0x1EEC++0x03
|
|
line.long 0x00 "GLBSTAT,Global Status Register"
|
|
eventfld.long 0x00 9. " FBSLIP ,Over cycle slip detection of PLL" "Not detected,Detected"
|
|
eventfld.long 0x00 8. " RFSLIP ,Under cycle slip detection of PLL" "Not detected,Detected"
|
|
eventfld.long 0x00 0. " OSCFAIL ,Oscillator fail flag" "Not failed,Failed"
|
|
endif
|
|
elif (cpuis("TMS570LS09*")||cpuis("TMS570LS07*")||cpuis("TMS570LS0232"))
|
|
group.long 0x1EA0++0x03
|
|
line.long 0x00 "GPREG1,General Purpose Register"
|
|
bitfld.long 0x00 20.--25. " PLL1_FBSLIP_FILTER_COUNT ,FBSLIP down counter programmed value" "Disabled,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles,16 cycles,17 cycles,18 cycles,19 cycles,20 cycles,21 cycles,22 cycles,23 cycles,24 cycles,25 cycles,26 cycles,27 cycles,28 cycles,29 cycles,30 cycles,31 cycles,32 cycles,33 cycles,34 cycles,35 cycles,36 cycles,37 cycles,38 cycles,39 cycles,40 cycles,41 cycles,42 cycles,43 cycles,44 cycles,45 cycles,46 cycles,47 cycles,48 cycles,49 cycles,50 cycles,51 cycles,52 cycles,53 cycles,54 cycles,55 cycles,56 cycles,57 cycles,58 cycles,59 cycles,60 cycles,61 cycles,62 cycles,63 cycles"
|
|
bitfld.long 0x00 16.--19. " PLL1_FBSLIP_FILTER_KEY ,Enable the FBSLIP filtering" "Enabled,Enabled,Enabled,Enabled,Enabled,Disabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,?..."
|
|
sif cpuis("TMS570LS09*")||cpuis("TMS570LS07*")
|
|
newline
|
|
bitfld.long 0x00 13. " OUTPUT_BUFFER_LOW_EMI_MODE[6] ,Control field for the low-EMI mode (signal nERROR)" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " [5] ,Control field for the low-EMI mode (signal RTC)" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " [4] ,Control field for the low-EMI mode (signal TDO)" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 8. " [3] ,Control field for the low-EMI mode (signal TMS)" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " [2] ,Control field for the low-EMI mode (MiBSPI5)" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " [1] ,Control field for the low-EMI mode (MiBSPI3)" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 0. " [0] ,Control field for the low-EMI mode (MiBSPI1)" "Disabled,Enabled"
|
|
endif
|
|
group.long 0x1EEC++0x03
|
|
line.long 0x00 "GLBSTAT,Global Status Register"
|
|
eventfld.long 0x00 9. " FBSLIP ,Over cycle slip detection of PLL" "Not detected,Detected"
|
|
eventfld.long 0x00 8. " RFSLIP ,Under cycle slip detection of PLL" "Not detected,Detected"
|
|
eventfld.long 0x00 0. " OSCFAIL ,Oscillator fail flag" "Not failed,Failed"
|
|
group.long 0x70++0x03
|
|
line.long 0x00 "CLKSLIP,PLL Clock Slip Control Register"
|
|
bitfld.long 0x00 8.--13. " PLL1_SLIP_FILTER_COUNT ,Number of HFLPO cycles to be recognized by RFSLIP as a slip" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x00 0.--3. " PLL1_SLIP_FILTER_KEY ,PLL1 RFSLIP filtering enable key" "Enabled,Enabled,Enabled,Enabled,Enabled,Disabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,?..."
|
|
endif
|
|
sif (cpuis("TMS570LS09*")||cpuis("TMS570LS07*")||cpuis("TMS570LS0232")||cpuis("TMS570LS3137-EP"))
|
|
if (per.l.be(ad:0xFFFFE100+0x1E24)&0x01)==0x01
|
|
group.long 0x1E24++0x03
|
|
line.long 0x00 "SSWPLL1,PLL Modulation Depth Measurement Control Register"
|
|
hexmask.long.byte 0x00 8.--15. 1. " CAPTURE_WINDOW_INDEX ,Count clock edges if phase capture window value is equal"
|
|
rbitfld.long 0x00 6. " COUNTER_READ_READY ,Counter read ready" "Not ready,Ready"
|
|
bitfld.long 0x00 5. " COUNTER_RESET ,Counter reset" "No reset,Reset"
|
|
newline
|
|
bitfld.long 0x00 4. " COUNTER_EN ,Counter enable" "Disabled,Enabled"
|
|
textfld " "
|
|
bitfld.long 0x00 0. " EXT_COUNTER_EN ,Measurement mode" "Modulation depth,Frequency"
|
|
else
|
|
group.long 0x1E24++0x03
|
|
line.long 0x00 "SSWPLL1,PLL Modulation Depth Measurement Control Register"
|
|
hexmask.long.byte 0x00 8.--15. 1. " CAPTURE_WINDOW_INDEX ,Count clock edges if phase capture window value is equal"
|
|
rbitfld.long 0x00 6. " COUNTER_READ_READY ,Counter read ready" "Not ready,Ready"
|
|
bitfld.long 0x00 5. " COUNTER_RESET ,Counter reset" "No reset,Reset"
|
|
newline
|
|
bitfld.long 0x00 4. " COUNTER_EN ,Counter status" "Inactive,Active"
|
|
bitfld.long 0x00 1.--3. " TAP_COUNTER_DIS ,CLKOUT bit select" "CLKOUT[16],CLKOUT[18],CLKOUT[20],CLKOUT[22],CLKOUT[24],CLKOUT[26],CLKOUT[28],CLKOUT[30]"
|
|
bitfld.long 0x00 0. " EXT_COUNTER_EN ,Measurement mode" "Modulation depth,Frequency"
|
|
endif
|
|
else
|
|
if (per.l(ad:0xFFFFE100+0x1E24)&0x01)==0x01
|
|
group.long 0x1E24++0x03
|
|
line.long 0x00 "SSWPLL1,PLL Modulation Depth Measurement Control Register"
|
|
hexmask.long.byte 0x00 8.--15. 1. " CAPTURE_WINDOW_INDEX ,Count clock edges if phase capture window value is equal"
|
|
rbitfld.long 0x00 6. " COUNTER_READ_READY ,Counter read ready" "Not ready,Ready"
|
|
bitfld.long 0x00 5. " COUNTER_RESET ,Counter reset" "No reset,Reset"
|
|
newline
|
|
bitfld.long 0x00 4. " COUNTER_EN ,Counter enable" "Disabled,Enabled"
|
|
textfld " "
|
|
bitfld.long 0x00 0. " EXT_COUNTER_EN ,Measurement mode" "Modulation depth,Frequency"
|
|
else
|
|
group.long 0x1E24++0x03
|
|
line.long 0x00 "SSWPLL1,PLL Modulation Depth Measurement Control Register"
|
|
hexmask.long.byte 0x00 8.--15. 1. " CAPTURE_WINDOW_INDEX ,Count clock edges if phase capture window value is equal"
|
|
rbitfld.long 0x00 6. " COUNTER_READ_READY ,Counter read ready" "Not ready,Ready"
|
|
bitfld.long 0x00 5. " COUNTER_RESET ,Counter reset" "No reset,Reset"
|
|
newline
|
|
bitfld.long 0x00 4. " COUNTER_EN ,Counter status" "Inactive,Active"
|
|
bitfld.long 0x00 1.--3. " TAP_COUNTER_DIS ,CLKOUT bit select" "CLKOUT[16],CLKOUT[18],CLKOUT[20],CLKOUT[22],CLKOUT[24],CLKOUT[26],CLKOUT[28],CLKOUT[30]"
|
|
bitfld.long 0x00 0. " EXT_COUNTER_EN ,Measurement mode" "Modulation depth,Frequency"
|
|
endif
|
|
endif
|
|
rgroup.long 0x1E28++0x07
|
|
line.long 0x00 "SSWPLL2,SSW PLL BIST Control Register 2"
|
|
line.long 0x04 "SSWPLL3,SSW PLL BIST Control Register 3"
|
|
sif (cpuis("TMS570LS09*")||cpuis("TMS570LS07*")||cpuis("TMS570LS0232"))
|
|
endian.le
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
tree "LPOCLKDET (Low-Power Oscillator and Clock Detect)"
|
|
base ad:0xFFFFFF88
|
|
sif (cpuis("TMS570LS09*")||cpuis("TMS570LS07*")||cpuis("TMS570LS0232"))
|
|
endian.be
|
|
endif
|
|
width 11.
|
|
group.long 0x00++0x07
|
|
line.long 0x00 "LPOMONCTL,LPO/Clock Monitor Control Register"
|
|
bitfld.long 0x00 24. " BIAS_ENABLE ,Bias enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " OSCFRQCONFIGCNT ,OSC frequency based counter configuration" "OSC freq <= 20MHz,20MHz < OSC freq <= 80MHz"
|
|
newline
|
|
sif (cpuis("TMS570LS0332")||cpuis("TMS570LS0432"))
|
|
bitfld.long 0x00 8.--11. " HFTRIM ,High frequency oscillator trim value" "29.52%,38.85%,47.99%,57.02%,65.92%,74.55%,83.17%,91.75%,100%,108.17%,116.41%,124.42%,132.24%,140.15%,148.02%,155.50%"
|
|
bitfld.long 0x00 0.--3. " LFTRIM ,Low frequency oscillator trim value" "20.67%,30.84%,40.93%,50.97%,60.86%,70.75%,80.61%,90.23%,100%,109.51%,119.01%,128.62%,138.03%,147.32%,156.63%,165.90%"
|
|
else
|
|
bitfld.long 0x00 8.--12. " HFTRIM ,High frequency oscillator trim value" "29.52%,34.24%,38.85%,43.45%,47.99%,52.55%,57.02%,61.46%,65.92%,70.17%,74.55%,78.92%,83.17%,87.43%,91.75%,95.89%,100%,104.09%,108.17%,112.32%,116.41%,120.67%,124.42%,128.38%,132.24%,136.15%,140.15%,143.94%,148.02%,151.80%,155.50%,159.35%"
|
|
bitfld.long 0x00 0.--4. " LFTRIM ,Low frequency oscillator trim value" "20.67%,25.76%,30.84%,35.90%,40.93%,45.95%,50.97%,55.91%,60.86%,65.78%,70.75%,75.63%,80.61%,85.39%,90.23%,95.11%,100%,104.84%,109.51%,114.31%,119.01%,123.75%,128.62%,133.31%,138.03%,142.75%,147.32%,152.02%,156.63%,161.38%,165.90%,170.42%"
|
|
endif
|
|
line.long 0x04 "CLKTEST,Clock Test Register"
|
|
sif (cpuis("TMS570LS0332")||cpuis("TMS570LS0432"))||(cpuis("TMS570LS09*")||cpuis("TMS570LS07*")||cpuis("TMS570LS0232")||cpuis("TMS570LS3137-EP"))
|
|
bitfld.long 0x04 26. " ALTLIMPCLOCKENABLE ,Clock enable" "Disabled,Enabled"
|
|
else
|
|
bitfld.long 0x04 26. " TEST ,Bit used for test purposes" "0,1"
|
|
endif
|
|
newline
|
|
bitfld.long 0x04 25. " RANGEDETCTRL ,Range detection control" "Disabled,Enabled"
|
|
bitfld.long 0x04 24. " RANGEDETENASSEL ,Range detect enable select" "Clock monitor,RANGEDETCTRL"
|
|
newline
|
|
bitfld.long 0x04 16.--19. " CLK_TEST_EN ,Clock test enable" "Disabled,Disabled,Disabled,Disabled,Disabled,Enabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled"
|
|
sif (cpuis("TMS570LS0332")||cpuis("TMS570LS0432"))
|
|
newline
|
|
bitfld.long 0x04 8.--11. " SEL_GIO_PIN ,Select clock source or it's valid signal at functional GIO pin" "Oscillator valid status,Main PLL valid status,,,,HFLPO CLK10M valid status,,,LFLPO CLK80K valid status,Oscillator valid status,Oscillator valid status,Oscillator valid status,Oscillator valid status,Oscillator valid status,Oscillator valid status,Oscillator valid status"
|
|
bitfld.long 0x04 0.--3. " SEL_ECP_PIN ,Select clock at ECP pin" "Oscillator,PLL clock,,,LFLPO,HFLPO,,,GCLK,RTI Base,,VCLKA1,,,,Flash HDPO"
|
|
elif (cpuis("TMS570LS1114*")||cpuis("TMS570LS1115*")||cpuis("TMS570LS1224*")||cpuis("TMS570LS1225*")||cpuis("TMS570LS1227*"))
|
|
newline
|
|
bitfld.long 0x04 8.--11. " SEL_GIO_PIN ,Select clock source or it's valid signal at functional GIO pin" "Oscillator valid status,Main PLL valid status,,,,HFLPO valid status,PLL2 valid status,,LFLPO,Oscillator valid status,Oscillator valid status,Oscillator valid status,Oscillator valid status,,VCLKA4_S,Oscillator valid status"
|
|
bitfld.long 0x04 0.--3. " SEL_ECP_PIN ,Select clock at ECP pin" "Oscillator,PLL clock,,EXTCLKIN1,LFLPO,HFLPO,PLL2 clock,EXTCLKIN2,GCLK,RTI Base,,VCLKA1,VCLKA2,,VCLKA4_DIVR,?..."
|
|
elif cpuis("RM57L843-ZWT")
|
|
newline
|
|
bitfld.long 0x04 8.--11. " SEL_GIO_PIN ,Select clock source or it's valid signal at functional GIO pin" "Oscillator valid status,PLL clock status,,,,HFLPO valid status,SPLLFRCO valid status,,LFLPO valid status,Oscillator valid status,Oscillator valid status,Oscillator valid status,Oscillator valid status,Oscillator valid status,Oscillator valid status,Oscillator valid status"
|
|
bitfld.long 0x04 0.--3. " SEL_ECP_PIN ,Select clock at ECP pin" "Oscillator clock,PLL clock,,EXTCLKIN1,LFLPO,HFLPO,Secondary PLL,EXCLKIN2,GCLK,RTI Base,,VCLKA1,VCLKA2,VCLKA3_S,VCLKA4,Flash HDPO"
|
|
elif cpuis("TMS570LS0232")
|
|
newline
|
|
bitfld.long 0x04 8.--11. " SEL_N2HET_PIN ,Pin clock source valid or clock source select" "Oscillator valid status,PLL1 valid status,,,,HFLPO CLK10M valid status,,,LFLPO CLK80K valid status,Oscillator valid status,Oscillator valid status,Oscillator valid status,Oscillator valid status,Oscillator valid status,Oscillator valid status,Oscillator valid status"
|
|
bitfld.long 0x04 0.--3. " SEL_ECP_PIN ,ECLK pin clock source select" "Oscillator clock,PLL1 clock output,,,LFLPO CLK80K,HFLPO CLK10M,,,GCLK,RTI Base,,VCLKA1,,,,Flash HD pump oscillator"
|
|
elif cpuis("TMS570LS09*")||cpuis("TMS570LS07*")
|
|
newline
|
|
bitfld.long 0x04 8.--11. " SEL_GIO_PIN ,Pin clock source valid or clock source select" "Oscillator valid status,PLL1 valid status,,,,HFLPO clock valid status,,,LFLPO clock valid status,Oscillator valid status,Oscillator valid status,Oscillator valid status,Oscillator valid status,,,Oscillator valid status"
|
|
bitfld.long 0x04 0.--4. " SEL_ECP_PIN ,ECLK pin clock source select" "Oscillator clock,PLL1 free-running clock output,,EXTCLKIN1,LFLPO clock,HFLPO clock,,EXTCLKIN2,GCLK,RTI base,,VCLKA1,,,,,,HCLK1,VCLK1,VCLK2,,VCLK4,?..."
|
|
elif cpuis("TMS570LS3137-EP")
|
|
newline
|
|
bitfld.long 0x04 8.--11. " SEL_GIO_PIN ,GIOB[0] pin clock source valid/select" "Oscillator,PLL1,,,,HFLPO,PLL2,,LFLPO,?..."
|
|
bitfld.long 0x04 0.--3. " SEL_ECP_PIN ,ECLK pin clock source select" "Oscillator,PLL1,,EXTCLKIN1,LFLPO,HFLPO,PLL2,EXTCLKIN2,GCLK,RTI base,,VCLKA1,VCLKA2,,VCLKA4,?..."
|
|
else
|
|
newline
|
|
bitfld.long 0x04 8.--11. " SEL_GIO_PIN ,Select clock source or it's valid signal at functional GIO pin" "Oscillator Valid status,Main PLL Valid status,,,,HFLPO CLK10M Valid status,,,LFLPO CLK80K Valid status,Oscillator Valid status,Oscillator Valid status,Oscillator Valid status,Oscillator Valid status,,VCLKA4_S,Oscillator Valid status"
|
|
bitfld.long 0x04 0.--4. " SEL_ECP_PIN ,Select clock at ECP pin" "Oscillator,Main PLL free-running clock output,,EXTCLKIN1,LFLPO,HFLPO,Secondary PLL free-running clock output,EXTCLKIN2,GCLK,RTI1 Base,RTI2 Base,VCLKA1,VCLKA2,,VCLKA4,Flash HD Pump Oscillator,,HCLK,VCLK,VCLK2,VCLK3,,,EMAC Clock,?..."
|
|
endif
|
|
sif (cpuis("TMS570LS09*")||cpuis("TMS570LS07*")||cpuis("TMS570LS0232"))
|
|
endian.le
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
tree "DCC (Dual-Clock Comparator)"
|
|
base ad:0xFFFFEC00
|
|
sif (cpuis("TMS570LS09*")||cpuis("TMS570LS07*")||cpuis("TMS570LS0232"))
|
|
endian.be
|
|
endif
|
|
width 12.
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "GCTRL,Global Control Register"
|
|
bitfld.long 0x00 12.--15. " DONE_INT_ENA ,Done interrupt enable" "Enabled,Enabled,Enabled,Enabled,Enabled,Disabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled"
|
|
sif cpuis("TMS570LS3137-EP")
|
|
bitfld.long 0x00 8.--11. " SINGLE_SHOT ,Single-shot mode enable" "Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,CNT0_VALID0,CNT1,Disabled,Disabled,Disabled,Disabled"
|
|
else
|
|
bitfld.long 0x00 8.--11. " SINGLE_SHOT ,Single-shot mode enable" "Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Enabled,Enabled,Disabled,Disabled,Disabled,Disabled"
|
|
endif
|
|
bitfld.long 0x00 4.--7. " ERR_ENA ,Error interrupt enable" "Enabled,Enabled,Enabled,Enabled,Enabled,Disabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled"
|
|
bitfld.long 0x00 0.--3. " DCC_ENA ,DCC enable" "Enabled,Enabled,Enabled,Enabled,Enabled,Disabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled"
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "REV,Revision ID Register"
|
|
bitfld.long 0x00 30.--31. " SCHEME ,Scheme" "0,1,2,3"
|
|
newline
|
|
hexmask.long.word 0x00 16.--27. 1. " FUNC ,Functional release number"
|
|
newline
|
|
bitfld.long 0x00 11.--15. " RTL ,Design release number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
bitfld.long 0x00 8.--10. " MAJOR ,Major revision number" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 6.--7. " CUSTOM ,Custom version number" "0,1,2,3"
|
|
bitfld.long 0x00 0.--5. " MINOR ,Minor revision number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
group.long 0x08++0x0F
|
|
line.long 0x00 "CNTSEED0,DCC Counter 0 Seed Register"
|
|
hexmask.long.tbyte 0x00 0.--19. 1. " COUNT0_SEED ,Seed value for DCC counter 0"
|
|
line.long 0x04 "VALIDSEED0,Valid 0 Seed Value"
|
|
hexmask.long.word 0x04 0.--15. 1. " VALID0_SEED ,Seed value for DCC valid 0"
|
|
line.long 0x08 "CNTSEED1,DCC Counter 1 Seed Register"
|
|
hexmask.long.tbyte 0x08 0.--19. 1. " COUNT1_SEED ,Seed value for DCC counter 1"
|
|
line.long 0x0C "STAT,Status Register"
|
|
eventfld.long 0x0C 1. " DONE_FLG ,Single-shot sequence done flag" "Not done,Done"
|
|
eventfld.long 0x0C 0. " ERR_FLG ,Error flag" "No error,Error"
|
|
rgroup.long 0x18++0x07
|
|
line.long 0x00 "CNT0,DCC Counter 0 Value Register"
|
|
hexmask.long.tbyte 0x00 0.--19. 1. " COUNT0 ,Value of DCC counter 0"
|
|
line.long 0x04 "VALID0,Valid 0 Value Register"
|
|
hexmask.long.word 0x04 0.--15. 1. " VALID0 ,Current value for DCC valid 0"
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "CNT1,DCC Counter 1 Value Register"
|
|
hexmask.long.tbyte 0x00 0.--19. 1. " COUNT1 ,Value of DCC counter 1"
|
|
sif (cpuis("RM48L950")||cpuis("RM48L952-PGE")||cpuis("RM48L950-PGE")||cpuis("RM48L950-ZWT")||cpuis("RM48L940-ZWT")||cpuis("RM48L940-PGE")||cpuis("RM48L930-ZWT")||cpuis("RM48L930-PGE")||cpuis("RM48L750-ZWT")||cpuis("RM48L750-PGE")||cpuis("RM48L740-ZWT")||cpuis("RM48L740-PGE")||cpuis("RM48L730-ZWT")||cpuis("RM48L730-PGE")||cpuis("RM48L550-PGE")||cpuis("RM48L540-ZWT")||cpuis("RM48L540-PGE")||cpuis("RM48L530-ZWT")||cpuis("RM48L530-PGE")||cpuis("RM46L852-PGE")||cpuis("RM46L852-ZWT")||cpuis("RM46L850-PGE")||cpuis("RM46L850-ZWT")||cpuis("RM46L840-ZWT")||cpuis("RM46L840-PGE")||cpuis("RM46L830-ZWT")||cpuis("RM46L830-PGE")||cpuis("RM46L450-ZWT")||cpuis("RM46L450-PGE")||cpuis("RM46L440-ZWT")||cpuis("RM46L440-PGE")||cpuis("RM46L430-ZWT")||cpuis("RM46L430-PGE")||cpuis("RM42L432")||cpuis("TMS570LS0332")||cpuis("TMS570LS0432")||cpuis("TMS570LS1114*")||cpuis("TMS570LS1115*")||cpuis("TMS570LS1224*")||cpuis("TMS570LS1225*")||cpuis("TMS570LS1227*"))
|
|
if (((per.l(ad:0xFFFFEC00+0x24))&0xF00000)==0xA00000)
|
|
group.long 0x24++0x3
|
|
line.long 0x0 "CNT1CLKSRC,DCC Counter1 Clock Source Selection Register"
|
|
bitfld.long 0x00 12.--15. " KEY ,Key to enable clock source selection for Counter1" "Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Enabled,Disabled,Disabled,Disabled,Disabled,Disabled"
|
|
sif (cpuis("TMS570LS0332")||cpuis("TMS570LS0432"))
|
|
bitfld.long 0x00 0.--3. " CNT1_CLKSRC ,Clock Source for Counter1" "PLL Output,,LF LPO,HF LPO,HD pump,EXTCLKIN,,Ring,VCLK,VCLK,VCLK,VCLK,VCLK,VCLK,VCLK,VCLK"
|
|
elif (cpuis("TMS570LS1114*")||cpuis("TMS570LS1115*")||cpuis("TMS570LS1224*")||cpuis("TMS570LS1225*")||cpuis("TMS570LS1227*"))
|
|
bitfld.long 0x00 0.--3. " CNT1_CLKSRC ,Clock Source for Counter1" "PLL1 Output,PLL2 Output,LF LPO,HF LPO,,EXTCLKIN1,EXTCLKIN2,,VCLK,VCLK,VCLK,VCLK,VCLK,VCLK,VCLK,VCLK"
|
|
else
|
|
bitfld.long 0x00 0.--3. " CNT1_CLKSRC ,Clock Source for Counter1" "PLL1 Output,PLL2 Output,LF LPO,HF LPO,,EXTCLKIN1,EXTCLKIN2,,VCLK,VCLK,VCLK,VCLK,VCLK,VCLK,VCLK,VCLK"
|
|
endif
|
|
else
|
|
group.long 0x24++0x3
|
|
line.long 0x0 "CNT1CLKSRC,DCC Counter1 Clock Source Selection Register"
|
|
bitfld.long 0x00 12.--15. " KEY ,Key to enable clock source selection for Counter1" "Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Enabled,Disabled,Disabled,Disabled,Disabled,Disabled"
|
|
endif
|
|
elif (cpuis("TMS570LS09*")||cpuis("TMS570LS07*")||cpuis("TMS570LS0232")||cpuis("TMS570LS3137-EP"))
|
|
if (((per.l.be(ad:0xFFFFEC00+0x24))&0xF000)==0xA000)
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "CNT1CLKSRC,DCC Counter 1 Clock Source Selection Register"
|
|
bitfld.long 0x00 12.--15. " KEY ,Key to enable clock source selection for counter 1" "Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Enabled,Disabled,Disabled,Disabled,Disabled,Disabled"
|
|
sif (cpuis("TMS570LS0232"))
|
|
bitfld.long 0x00 0.--3. " CNT1_CLKSRC ,Clock source for counter 1" "PLL1 Output,,LF LPO,HF LPO,,EXTCLKIN,,,VCLK,VCLK,VCLK,VCLK,VCLK,VCLK,VCLK,VCLK"
|
|
elif (cpuis("TMS570LS3137-EP"))
|
|
bitfld.long 0x00 0.--3. " CNT1_CLKSRC ,Clock source for counter 1" "PLL Output,,LF LPO,HF LPO,Flash HD,EXTCLKIN1,,Ring oscillator,VCLK,VCLK,VCLK,VCLK,VCLK,VCLK,VCLK,VCLK"
|
|
elif cpuis("TMS570LS09*")||cpuis("TMS570LS07*")
|
|
bitfld.long 0x00 0.--3. " CNT1_CLKSRC ,Clock source for counter 1" "OSCIN,PLL1,,EXTCLKIN1,LFLPO,HFLPO,,EXTCLKIN2,?..."
|
|
endif
|
|
else
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "CNT1CLKSRC,DCC Counter 1 Clock Source Selection Register"
|
|
bitfld.long 0x00 12.--15. " KEY ,Key to enable clock source selection for counter 1" "Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Enabled,Disabled,Disabled,Disabled,Disabled,Disabled"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0xFFFFEC00+0x24))&0xF000)==0xA000)
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "CNT1CLKSRC,DCC Counter 1 Clock Source Selection Register"
|
|
bitfld.long 0x00 12.--15. " KEY ,Key to enable clock source selection for counter 1" "Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Enabled,Disabled,Disabled,Disabled,Disabled,Disabled"
|
|
newline
|
|
sif (cpuis("TMS570LS0332")||cpuis("TMS570LS0432"))
|
|
bitfld.long 0x00 0.--3. " CNT1_CLKSRC ,Clock source for counter 1" "PLL Output,,LF LPO,HF LPO,HD pump,EXTCLKIN,,Ring,VCLK,VCLK,VCLK,VCLK,VCLK,VCLK,VCLK,VCLK"
|
|
elif (cpuis("TMS570LS1114*")||cpuis("TMS570LS1115*")||cpuis("TMS570LS1224*")||cpuis("TMS570LS1225*")||cpuis("TMS570LS1227*"))
|
|
bitfld.long 0x00 0.--3. " CNT1_CLKSRC ,Clock source for counter 1" "PLL1 Output,PLL2 Output,LF LPO,HF LPO,,EXTCLKIN1,EXTCLKIN2,,VCLK,VCLK,VCLK,VCLK,VCLK,VCLK,VCLK,VCLK"
|
|
else
|
|
bitfld.long 0x00 0.--3. " CNT1_CLKSRC ,Clock source for counter 1" "PLL1 Output,PLL2 Output,LF LPO,HF LPO,,EXTCLKIN1,EXTCLKIN2,,VCLK,VCLK,VCLK,VCLK,VCLK,VCLK,VCLK,VCLK"
|
|
endif
|
|
else
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "CNT1CLKSRC,DCC Counter 1 Clock Source Selection Register"
|
|
bitfld.long 0x00 12.--15. " KEY ,Key to enable clock source selection for counter 1" "Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Enabled,Disabled,Disabled,Disabled,Disabled,Disabled"
|
|
endif
|
|
endif
|
|
sif (!cpuis("TMS570LS09*")&&!cpuis("TMS570LS07*")&&!cpuis("TMS570LS0232")&&!cpuis("TMS570LS3137-EP"))
|
|
sif (cpuis("RM48L950")||cpuis("RM48L952-PGE")||cpuis("RM48L952-ZWT")||cpuis("RM48L950-PGE")||cpuis("RM48L950-ZWT")||cpuis("RM48L940-ZWT")||cpuis("RM48L940-PGE")||cpuis("RM48L930-ZWT")||cpuis("RM48L930-PGE")||cpuis("RM48L750-ZWT")||cpuis("RM48L750-PGE")||cpuis("RM48L740-ZWT")||cpuis("RM48L740-PGE")||cpuis("RM48L730-ZWT")||cpuis("RM48L730-PGE")||cpuis("RM48L550-PGE")||cpuis("RM48L540-ZWT")||cpuis("RM48L540-PGE")||cpuis("RM48L530-ZWT")||cpuis("RM48L530-PGE")||cpuis("RM46L852-PGE")||cpuis("RM46L852-ZWT")||cpuis("RM46L850-PGE")||cpuis("RM46L850-ZWT")||cpuis("RM46L840-ZWT")||cpuis("RM46L840-PGE")||cpuis("RM46L830-ZWT")||cpuis("RM46L830-PGE")||cpuis("RM46L450-ZWT")||cpuis("RM46L450-PGE")||cpuis("RM46L440-ZWT")||cpuis("RM46L440-PGE")||cpuis("RM46L430-ZWT")||cpuis("RM46L430-PGE")||cpuis("RM42L432")||cpuis("TMS570LS1114*")||cpuis("TMS570LS1115*")||cpuis("TMS570LS1224*")||cpuis("TMS570LS1225*")||cpuis("TMS570LS1227*")||cpuis("TMS570LS0332")||cpuis("TMS570LS0432"))
|
|
if (((per.l(ad:0xFFFFEC00+0x24))&0xF00000)==0xA00000)
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "CNT1CLKSRC,DCC Counter 1 Clock Source Selection Register"
|
|
bitfld.long 0x00 12.--15. " KEY ,Key to enable clock source selection for counter 1" "Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Enabled,Disabled,Disabled,Disabled,Disabled,Disabled"
|
|
bitfld.long 0x00 0.--3. " CNT1_CLKSRC ,Clock source for counter 1" ",,,,,,,,VCLK,VCLK,VCLK,VCLK,VCLK,VCLK,VCLK,VCLK"
|
|
else
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "CNT1CLKSRC,DCC Counter 1 Clock Source Selection Register"
|
|
bitfld.long 0x00 12.--15. " KEY ,Key to enable clock source selection for counter 1" "Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Enabled,Disabled,Disabled,Disabled,Disabled,Disabled"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0xFFFFEC00+0x24))&0xF000)==0xA000)
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "CNT1CLKSRC,DCC Counter 1 Clock Source Selection Register"
|
|
bitfld.long 0x00 12.--15. " KEY ,Key to enable clock source selection for Counter1" "Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Enabled,Disabled,Disabled,Disabled,Disabled,Disabled"
|
|
bitfld.long 0x00 0.--3. " CNT1_CLKSRC ,Clock source for counter 1" ",,,,,,,,VCLK,VCLK,VCLK,VCLK,VCLK,VCLK,VCLK,VCLK"
|
|
else
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "CNT1CLKSRC,DCC Counter 1 Clock Source Selection Register"
|
|
bitfld.long 0x00 12.--15. " KEY ,Key to enable clock source selection for counter 1" "Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Enabled,Disabled,Disabled,Disabled,Disabled,Disabled"
|
|
endif
|
|
endif
|
|
endif
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "CNT0CLKSRC,DCC Counter0 Clock Source Selection Register"
|
|
sif cpuis("TMS570LS09*")||cpuis("TMS570LS07*")||cpuis("TMS570LS0232")||cpuis("TMS570LS3137-EP")||cpuis("RM48L950")||cpuis("RM48L952-PGE")||cpuis("RM48L952-ZWT")||cpuis("RM48L950-PGE")||cpuis("RM48L950-ZWT")||cpuis("RM48L940-ZWT")||cpuis("RM48L940-PGE")||cpuis("RM48L930-ZWT")||cpuis("RM48L930-PGE")||cpuis("RM48L750-ZWT")||cpuis("RM48L750-PGE")||cpuis("RM48L740-ZWT")||cpuis("RM48L740-PGE")||cpuis("RM48L730-ZWT")||cpuis("RM48L730-PGE")||cpuis("RM48L550-PGE")||cpuis("RM48L540-ZWT")||cpuis("RM48L540-PGE")||cpuis("RM48L530-ZWT")||cpuis("RM48L530-PGE")
|
|
bitfld.long 0x00 0.--3. " CNT0_CLKSRC ,Clock source for counter 0" "OSCIN,OSCIN,OSCIN,OSCIN,OSCIN,HF LPO,OSCIN,OSCIN,OSCIN,OSCIN,TCK,OSCIN,OSCIN,OSCIN,OSCIN,OSCIN"
|
|
else
|
|
bitfld.long 0x00 0.--3. " CNT0_CLKSRC ,Clock source for counter 0" "OSCIN,OSCIN,OSCIN,OSCIN,OSCIN,OSCIN,OSCIN,OSCIN,OSCIN,OSCIN,TCK,OSCIN,OSCIN,OSCIN,OSCIN,VCLK"
|
|
endif
|
|
sif (cpuis("TMS570LS09*")||cpuis("TMS570LS07*")||cpuis("TMS570LS0232"))
|
|
endian.le
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
tree "ESM (Error Signaling Module)"
|
|
base ad:0xFFFFF500
|
|
sif (cpuis("TMS570LS09*")||cpuis("TMS570LS07*")||cpuis("TMS570LS0232"))
|
|
endian.be
|
|
endif
|
|
width 17.
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "EEPAPR1_SET/CLR,Enable Error Pin Action/Response Set/Clear Register 1"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x04 31. " IEPSET[31] ,Set/Clear influence on error pin 31 - CCM-R4 - selftest" "No influence,Influence"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x04 30. " [30] ,Set/Clear influence on error pin 30 - DCC - error" "No influence,Influence"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x04 28. " [28] ,Set/Clear influence on error pin 28 - RAM odd bank (B1TCM)" "No influence,Influence"
|
|
newline
|
|
setclrfld.long 0x00 27. 0x00 27. 0x04 27. " [27] ,Set/Clear influence on error pin 27 - CPU - selftest" "No influence,Influence"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x04 26. " [26] ,Set/Clear influence on error pin 26 - RAM even bank (B0TCM)" "No influence,Influence"
|
|
sif cpuis("TMS570LS09*")||cpuis("TMS570LS07*")
|
|
newline
|
|
setclrfld.long 0x00 24. 0x00 24. 0x04 24. " [24] ,Set/Clear influence on error pin 24 - MibSPI5 - RAM parity error" "No influence,Influence"
|
|
endif
|
|
newline
|
|
setclrfld.long 0x00 23. 0x00 23. 0x04 23. " [23] ,Set/Clear influence on error pin 23 - DCAN2 - parity" "No influence,Influence"
|
|
sif cpuis("TMS570LS09*")||cpuis("TMS570LS07*")
|
|
newline
|
|
setclrfld.long 0x00 22. 0x00 22. 0x04 22. " [22] ,Set/Clear influence on error pin 22 - DCAN3 - RAM parity error" "No influence,Influence"
|
|
endif
|
|
newline
|
|
setclrfld.long 0x00 21. 0x00 21. 0x04 21. " [21] ,Set/Clear influence on error pin 21 - DCAN1 - parity" "No influence,Influence"
|
|
setclrfld.long 0x00 19. 0x00 19. 0x04 19. " [19] ,Set/Clear influence on error pin 19 - MibADC - parity" "No influence,Influence"
|
|
sif cpuis("TMS570LS09*")||cpuis("TMS570LS07*")
|
|
newline
|
|
setclrfld.long 0x00 18. 0x00 18. 0x04 18. " [18] ,Set/Clear influence on error pin 18 - MibSPI3 - RAM parity error" "No influence,Influence"
|
|
endif
|
|
newline
|
|
setclrfld.long 0x00 17. 0x00 17. 0x04 17. " [17] ,Set/Clear influence on error pin 17 - MibSPI1 - parity" "No influence,Influence"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x04 15. " [15] ,Set/Clear influence on error pin 15 - VIM RAM - parity" "No influence,Influence"
|
|
sif cpuis("TMS570LS09*")||cpuis("TMS570LS07*")
|
|
newline
|
|
setclrfld.long 0x00 13. 0x00 13. 0x04 13. " [13] ,Set/Clear influence on error pin 13 - DMA - error on DMA write access, imprecise error" "No influence,Influence"
|
|
endif
|
|
newline
|
|
setclrfld.long 0x00 11. 0x00 11. 0x04 11. " [11] ,Set/Clear influence on error pin 11 - clock monitor" "No influence,Influence"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x04 10. " [10] ,Set/Clear influence on error pin 10 - PLL - slip" "No influence,Influence"
|
|
sif cpuis("TMS570LS0232")
|
|
newline
|
|
setclrfld.long 0x00 9. 0x00 9. 0x04 9. " [9] ,Set/Clear influence on error pin 9 - HTU - MPU" "No influence,Influence"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x04 8. " [8] ,Set/Clear influence on error pin 8 - HTU - parity" "No influence,Influence"
|
|
elif cpuis("TMS570LS09*")||cpuis("TMS570LS07*")
|
|
newline
|
|
setclrfld.long 0x00 9. 0x00 9. 0x04 9. " [9] ,Set/Clear influence on error pin 9 - HET TU1/HET TU2 - MPU configuration violation" "No influence,Influence"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x04 8. " [8] ,Set/Clear influence on error pin 8 - HET TU1/HET TU2 - dual-control packet RAM parity error" "No influence,Influence"
|
|
else
|
|
newline
|
|
setclrfld.long 0x00 9. 0x00 9. 0x04 9. " [9] ,Set/Clear influence on error pin 9 - HET TU - MPU" "No influence,Influence"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x04 8. " [8] ,Set/Clear influence on error pin 8 - HET TU - parity" "No influence,Influence"
|
|
endif
|
|
newline
|
|
setclrfld.long 0x00 7. 0x00 7. 0x04 7. " [7] ,Set/Clear influence on error pin 7 - N2HET - parity" "No influence,Influence"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x04 6. " [6] ,Set/Clear influence on error pin 6 - FMC" "No influence,Influence"
|
|
sif cpuis("TMS570LS09*")||cpuis("TMS570LS07*")
|
|
newline
|
|
setclrfld.long 0x00 5. 0x00 5. 0x04 5. " [5] ,Set/Clear influence on error pin 5 - DMA - error on DMA read access, imprecise error" "No influence,Influence"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x04 3. " [3] ,Set/Clear influence on error pin 3 - DMA - control packet RAM parity error" "No influence,Influence"
|
|
newline
|
|
setclrfld.long 0x00 2. 0x00 2. 0x04 2. " [2] ,Set/Clear influence on error pin 2 - DMA - MPU configuration violation" "No influence,Influence"
|
|
setclrfld.long 0x00 1. 0x00 1. 0x04 1. " [1] ,Set/Clear influence on error pin 1 - MibADC2 - RAM parity error" "No influence,Influence"
|
|
endif
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "IESR1_SET/CLR,Interrupt Enable Set/Clear Register 1"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x04 31. " INTENSET[31] ,Set/Clear interrupt enable 31 - CCM-R4 - selftest" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x04 30. " [30] ,Set/Clear interrupt enable 30 - DCC - error" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x04 28. " [28] ,Set/Clear interrupt enable 28 - RAM odd bank (B1TCM)" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 27. 0x00 27. 0x04 27. " [27] ,Set/Clear interrupt enable 27 - CPU - selftest" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x04 26. " [26] ,Set/Clear interrupt enable 26 - RAM even bank (B0TCM)" "Disabled,Enabled"
|
|
sif cpuis("TMS570LS09*")||cpuis("TMS570LS07*")
|
|
newline
|
|
setclrfld.long 0x00 24. 0x00 24. 0x04 24. " [24] ,Set/Clear interrupt enable 24 - MibSPI5 - RAM parity error" "Disabled,Enabled"
|
|
endif
|
|
newline
|
|
setclrfld.long 0x00 23. 0x00 23. 0x04 23. " [23] ,Set/Clear interrupt enable 23 - DCAN2 - parity" "Disabled,Enabled"
|
|
sif cpuis("TMS570LS09*")||cpuis("TMS570LS07*")
|
|
newline
|
|
setclrfld.long 0x00 22. 0x00 22. 0x04 22. " [22] ,Set/Clear interrupt enable 22 - DCAN3 - RAM parity error" "Disabled,Enabled"
|
|
endif
|
|
newline
|
|
setclrfld.long 0x00 21. 0x00 21. 0x04 21. " [21] ,Set/Clear interrupt enable 21 - DCAN1 - parity" "Disabled,Enabled"
|
|
setclrfld.long 0x00 19. 0x00 19. 0x04 19. " [19] ,Set/Clear interrupt enable 19 - MibADC - parity" "Disabled,Enabled"
|
|
sif cpuis("TMS570LS09*")||cpuis("TMS570LS07*")
|
|
newline
|
|
setclrfld.long 0x00 18. 0x00 18. 0x04 18. " [18] ,Set/Clear interrupt enable 18 - MibSPI3 - RAM parity error" "Disabled,Enabled"
|
|
endif
|
|
newline
|
|
setclrfld.long 0x00 17. 0x00 17. 0x04 17. " [17] ,Set/Clear interrupt enable 17 - MibSPI1 - parity" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x04 15. " [15] ,Set/Clear interrupt enable 15 - VIM RAM - parity" "Disabled,Enabled"
|
|
sif cpuis("TMS570LS09*")||cpuis("TMS570LS07*")
|
|
newline
|
|
setclrfld.long 0x00 13. 0x00 13. 0x04 13. " [13] ,Set/Clear interrupt enable 13 - DMA - error on DMA write access, imprecise error" "Disabled,Enabled"
|
|
endif
|
|
newline
|
|
setclrfld.long 0x00 11. 0x00 11. 0x04 11. " [11] ,Set/Clear interrupt enable 11 - Clock Monitor - interrupt" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x04 10. " [10] ,Set/Clear interrupt enable 10 - PLL - Slip" "Disabled,Enabled"
|
|
sif cpuis("TMS570LS0232")
|
|
newline
|
|
setclrfld.long 0x00 9. 0x00 9. 0x04 9. " [9] ,Set/Clear interrupt enable 9 - HTU - MPU" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x04 8. " [8] ,Set/Clear interrupt enable 8 - HTU - parity" "Disabled,Enabled"
|
|
elif cpuis("TMS570LS09*")||cpuis("TMS570LS07*")
|
|
newline
|
|
setclrfld.long 0x00 9. 0x00 9. 0x04 9. " [9] ,Set/Clear interrupt enable 9 - HET TU1/HET TU2 - MPU configuration violation" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x04 8. " [8] ,Set/Clear interrupt enable 8 - HET TU1/HET TU2 - dual-control packet RAM parity error" "Disabled,Enabled"
|
|
else
|
|
newline
|
|
setclrfld.long 0x00 9. 0x00 9. 0x04 9. " [9] ,Set/Clear interrupt enable 9 - HET TU - MPU" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x04 8. " [8] ,Set/Clear interrupt enable 8 - HET TU - parity" "Disabled,Enabled"
|
|
endif
|
|
newline
|
|
setclrfld.long 0x00 7. 0x00 7. 0x04 7. " [7] ,Set/Clear interrupt enable 7 - N2HET - parity" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x04 6. " [6] ,Set/Clear interrupt enable 6 - FMC" "Disabled,Enabled"
|
|
sif cpuis("TMS570LS09*")||cpuis("TMS570LS07*")
|
|
newline
|
|
setclrfld.long 0x00 5. 0x00 5. 0x04 5. " [5] ,Set/Clear interrupt enable 5 - DMA - error on DMA read access, imprecise error" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x04 3. " [3] ,Set/Clear interrupt enable 3 - DMA - control packet RAM parity error" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x04 2. " [2] ,Set/Clear interrupt enable 2 - DMA - MPU configuration violation" "Disabled,Enabled"
|
|
setclrfld.long 0x00 1. 0x00 1. 0x04 1. " [1] ,Set/Clear interrupt enable 1 - MibADC2 - RAM parity error" "Disabled,Enabled"
|
|
endif
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "ILSR1_SET/CLR,Interrupt Level Set/Clear Register 1"
|
|
sif (cpuis("TMS570LS09*")||cpuis("TMS570LS07*")||cpuis("TMS570LS0232"))
|
|
setclrfld.long 0x00 31. 0x00 31. 0x04 31. " INTLVLSET[31] ,Set/Clear interrupt level pin 31 (CCM-R4 - selftest)" "Low,High"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x04 30. " [30] ,Set/Clear interrupt level pin 30 (DCC - error)" "Low,High"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x04 28. " [28] ,Set/Clear interrupt level pin 28 (RAM odd bank (B1TCM))" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 27. 0x00 27. 0x04 27. " [27] ,Set/Clear interrupt level pin 27 (CPU - selftest)" "Low,High"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x04 26. " [26] ,Set/Clear interrupt level pin 26 (RAM even bank (B0TCM))" "Low,High"
|
|
sif !cpuis("TMS570LS0232")
|
|
newline
|
|
setclrfld.long 0x00 24. 0x00 24. 0x04 24. " [24] ,Set/Clear interrupt level pin 24 (MibSPI5 - RAM parity error)" "Low,High"
|
|
endif
|
|
newline
|
|
setclrfld.long 0x00 23. 0x00 23. 0x04 23. " [23] ,Set/Clear interrupt level pin 23 (DCAN2 - parity)" "Low,High"
|
|
sif !cpuis("TMS570LS0232")
|
|
newline
|
|
setclrfld.long 0x00 22. 0x00 22. 0x04 22. " [22] ,Set/Clear interrupt level pin 22 (DCAN3 - RAM parity error)" "Low,High"
|
|
endif
|
|
newline
|
|
setclrfld.long 0x00 21. 0x00 21. 0x04 21. " [21] ,Set/Clear interrupt level pin 21 (DCAN1 - parity)" "Low,High"
|
|
setclrfld.long 0x00 19. 0x00 19. 0x04 19. " [19] ,Set/Clear interrupt level pin 19 (MibADC - parity)" "Low,High"
|
|
sif !cpuis("TMS570LS0232")
|
|
newline
|
|
setclrfld.long 0x00 18. 0x00 18. 0x04 18. " [18] ,Set/Clear interrupt level pin 18 (MibSPI3 - RAM parity error)" "Low,High"
|
|
endif
|
|
newline
|
|
setclrfld.long 0x00 17. 0x00 17. 0x04 17. " [17] ,Set/Clear interrupt level pin 17 (MibSPI1 - parity)" "Low,High"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x04 15. " [15] ,Set/Clear interrupt level pin 15 (VIM RAM - parity)" "Low,High"
|
|
sif !cpuis("TMS570LS0232")
|
|
newline
|
|
setclrfld.long 0x00 13. 0x00 13. 0x04 13. " [13] ,Set/Clear interrupt level pin 13 (DMA - error on DMA write access, imprecise error)" "Low,High"
|
|
endif
|
|
newline
|
|
setclrfld.long 0x00 11. 0x00 11. 0x04 11. " [11] ,Set/Clear interrupt level pin 11 (Clock monitor)" "Low,High"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x04 10. " [10] ,Set/Clear interrupt level pin 10 (PLL - Slip)" "Low,High"
|
|
sif cpuis("TMS570LS0232")
|
|
newline
|
|
setclrfld.long 0x00 9. 0x00 9. 0x04 9. " [9] ,Set/Clear interrupt level pin 9 (HTU - MPU)" "Low,High"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x04 8. " [8] ,Set/Clear interrupt level pin 8 (HTU - parity)" "Low,High"
|
|
else
|
|
newline
|
|
setclrfld.long 0x00 9. 0x00 9. 0x04 9. " [9] ,Set/Clear interrupt level pin 9 (HET TU1/HET TU2 - MPU configuration violation)" "Low,High"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x04 8. " [8] ,Set/Clear interrupt level pin 8 (HET TU1/HET TU2 - dual-control packet RAM parity error)" "Low,High"
|
|
endif
|
|
newline
|
|
setclrfld.long 0x00 7. 0x00 7. 0x04 7. " [7] ,Set/Clear interrupt level pin 7 (N2HET - parity)" "Low,High"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x04 6. " [6] ,Set/Clear interrupt level pin 6 (FMC)" "Low,High"
|
|
sif !cpuis("TMS570LS0232")
|
|
newline
|
|
setclrfld.long 0x00 5. 0x00 5. 0x04 5. " [5] ,Set/Clear interrupt level pin 5 (DMA - error on DMA read access, imprecise error)" "Low,High"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x04 3. " [3] ,Set/Clear interrupt level pin 3 (DMA - control packet RAM parity error)" "Low,High"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x04 2. " [2] ,Set/Clear interrupt level pin 2 (DMA - MPU configuration violation)" "Low,High"
|
|
setclrfld.long 0x00 1. 0x00 1. 0x04 1. " [1] ,Set/Clear interrupt level pin 1 (MibADC2 - RAM parity error)" "Low,High"
|
|
endif
|
|
else
|
|
setclrfld.long 0x00 31. 0x00 31. 0x04 31. " INTLVLSET[31] ,Set/Clear interrupt level 31" "Low,High"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x04 30. " [30] ,Set/Clear interrupt level 30" "Low,High"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x04 29. " [29] ,Set/Clear interrupt level 29" "Low,High"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x04 28. " [28] ,Set/Clear interrupt level 28" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 27. 0x00 27. 0x04 27. " [27] ,Set/Clear interrupt level 27" "Low,High"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x04 26. " [26] ,Set/Clear interrupt level 26" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 25. 0x00 25. 0x04 25. " [25] ,Set/Clear interrupt level 25" "Low,High"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x04 24. " [24] ,Set/Clear interrupt level 24" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 23. 0x00 23. 0x04 23. " [23] ,Set/Clear interrupt level 23" "Low,High"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x04 22. " [22] ,Set/Clear interrupt level 22" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 21. 0x00 21. 0x04 21. " [21] ,Set/Clear interrupt level 21" "Low,High"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x04 20. " [20] ,Set/Clear interrupt level 20" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 19. 0x00 19. 0x04 19. " [19] ,Set/Clear interrupt level 19" "Low,High"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x04 18. " [18] ,Set/Clear interrupt level 18" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 17. 0x00 17. 0x04 17. " [17] ,Set/Clear interrupt level 17" "Low,High"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x04 16. " [16] ,Set/Clear interrupt level 16" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 15. 0x00 15. 0x04 15. " [15] ,Set/Clear interrupt level 15" "Low,High"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x04 14. " [14] ,Set/Clear interrupt level 14" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 13. 0x00 13. 0x04 13. " [13] ,Set/Clear interrupt level 13" "Low,High"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x04 12. " [12] ,Set/Clear interrupt level 12" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 11. 0x00 11. 0x04 11. " [11] ,Set/Clear interrupt level 11" "Low,High"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x04 10. " [10] ,Set/Clear interrupt level 10" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 9. 0x00 9. 0x04 9. " [9] ,Set/Clear interrupt level 9" "Low,High"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x04 8. " [8] ,Set/Clear interrupt level 8" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 7. 0x00 7. 0x04 7. " [7] ,Set/Clear interrupt level 7" "Low,High"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x04 6. " [6] ,Set/Clear interrupt level 6" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 5. 0x00 5. 0x04 5. " [5] ,Set/Clear interrupt level 5" "Low,High"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x04 4. " [4] ,Set/Clear interrupt level 4" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 3. 0x00 3. 0x04 3. " [3] ,Set/Clear interrupt level 3" "Low,High"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x04 2. " [2] ,Set/Clear interrupt level 2" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 1. 0x00 1. 0x04 1. " [1] ,Set/Clear interrupt level 1" "Low,High"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x04 0. " [0] ,Set/Clear interrupt level 0" "Low,High"
|
|
endif
|
|
group.long 0x18++0x0B
|
|
line.long 0x00 "SR1,Status Register 1"
|
|
sif (cpuis("TMS570LS09*")||cpuis("TMS570LS07*")||cpuis("TMS570LS0232"))
|
|
eventfld.long 0x00 31. " ESF[31] ,Error status flag pin 31 (CCM-R4 - selftest)" "No error,Error"
|
|
eventfld.long 0x00 30. " [30] ,Error status flag pin 30 (DCC - error)" "No error,Error"
|
|
newline
|
|
eventfld.long 0x00 28. " [28] ,Error status flag pin 28 (RAM odd bank (B1TCM))" "No error,Error"
|
|
eventfld.long 0x00 27. " [27] ,Error status flag pin 27 (CPU - selftest)" "No error,Error"
|
|
newline
|
|
eventfld.long 0x00 26. " [26] ,Error status flag pin 26 (RAM even bank (B0TCM))" "No error,Error"
|
|
sif !cpuis("TMS570LS0232")
|
|
newline
|
|
eventfld.long 0x00 24. " [24] ,Error status flag pin 24 (MibSPI5 - RAM parity error)" "No error,Error"
|
|
endif
|
|
newline
|
|
eventfld.long 0x00 23. " [23] ,Error status flag pin 23 (DCAN2 - parity)" "No error,Error"
|
|
sif !cpuis("TMS570LS0232")
|
|
newline
|
|
eventfld.long 0x00 22. " [22] ,Error status flag pin 22 (DCAN3 - RAM parity error)" "No error,Error"
|
|
endif
|
|
newline
|
|
eventfld.long 0x00 21. " [21] ,Error status flag pin 21 (DCAN1 - parity)" "No error,Error"
|
|
eventfld.long 0x00 19. " [19] ,Error status flag pin 19 (MibADC - parity)" "No error,Error"
|
|
sif !cpuis("TMS570LS0232")
|
|
newline
|
|
eventfld.long 0x00 18. " [18] ,Error status flag pin 18 (MibSPI3 - RAM parity error)" "No error,Error"
|
|
endif
|
|
newline
|
|
eventfld.long 0x00 17. " [17] ,Error status flag pin 17 (MibSPI1 - parity)" "No error,Error"
|
|
eventfld.long 0x00 15. " [15] ,Error status flag pin 15 (VIM RAM - parity)" "No error,Error"
|
|
sif !cpuis("TMS570LS0232")
|
|
newline
|
|
eventfld.long 0x00 13. " [13] ,Error status flag pin 13 (DMA - error on DMA write access, imprecise error)" "No error,Error"
|
|
endif
|
|
newline
|
|
eventfld.long 0x00 11. " [11] ,Error status flag pin 11 (Clock monitor)" "No error,Error"
|
|
eventfld.long 0x00 10. " [10] ,Error status flag pin 10 (PLL - Slip)" "No error,Error"
|
|
sif cpuis("TMS570LS0232")
|
|
newline
|
|
eventfld.long 0x00 9. " [9] ,Error status flag pin 9 (HTU - MPU)" "No error,Error"
|
|
eventfld.long 0x00 8. " [8] ,Error status flag pin 8 (HTU - parity)" "No error,Error"
|
|
else
|
|
newline
|
|
eventfld.long 0x00 9. " [9] ,Error status flag pin 9 (HET TU1/HET TU2 - MPU configuration violation)" "No error,Error"
|
|
eventfld.long 0x00 8. " [8] ,Error status flag pin 8 (HET TU1/HET TU2 - dual-control packet RAM parity error)" "No error,Error"
|
|
endif
|
|
newline
|
|
eventfld.long 0x00 7. " [7] ,Error status flag pin 7 (N2HET - parity)" "No error,Error"
|
|
eventfld.long 0x00 6. " [6] ,Error status flag pin 6 (FMC)" "No error,Error"
|
|
sif !cpuis("TMS570LS0232")
|
|
newline
|
|
eventfld.long 0x00 5. " [5] ,Error status flag pin 5 (DMA - error on DMA read access, imprecise error)" "No error,Error"
|
|
eventfld.long 0x00 3. " [3] ,Error status flag pin 3 (DMA - control packet RAM parity error)" "No error,Error"
|
|
newline
|
|
eventfld.long 0x00 2. " [2] ,Error status flag pin 2 (DMA - MPU configuration violation)" "No error,Error"
|
|
eventfld.long 0x00 1. " [1] ,Error status flag pin 1 (MibADC2 - RAM parity error)" "No error,Error"
|
|
endif
|
|
else
|
|
eventfld.long 0x00 31. " ESF[31] ,Error status flag 31" "No error,Error"
|
|
eventfld.long 0x00 30. " [30] ,Error status flag 30" "No error,Error"
|
|
newline
|
|
eventfld.long 0x00 29. " [29] ,Error status flag 29" "No error,Error"
|
|
eventfld.long 0x00 28. " [28] ,Error status flag 28" "No error,Error"
|
|
newline
|
|
eventfld.long 0x00 27. " [27] ,Error status flag 27" "No error,Error"
|
|
eventfld.long 0x00 26. " [26] ,Error status flag 26" "No error,Error"
|
|
newline
|
|
eventfld.long 0x00 25. " [25] ,Error status flag 25" "No error,Error"
|
|
eventfld.long 0x00 24. " [24] ,Error status flag 24" "No error,Error"
|
|
newline
|
|
eventfld.long 0x00 23. " [23] ,Error status flag 23" "No error,Error"
|
|
eventfld.long 0x00 22. " [22] ,Error status flag 22" "No error,Error"
|
|
newline
|
|
eventfld.long 0x00 21. " [21] ,Error status flag 21" "No error,Error"
|
|
eventfld.long 0x00 20. " [20] ,Error status flag 20" "No error,Error"
|
|
newline
|
|
eventfld.long 0x00 19. " [19] ,Error status flag 19" "No error,Error"
|
|
eventfld.long 0x00 18. " [18] ,Error status flag 18" "No error,Error"
|
|
newline
|
|
eventfld.long 0x00 17. " [17] ,Error status flag 17" "No error,Error"
|
|
eventfld.long 0x00 16. " [16] ,Error status flag 16" "No error,Error"
|
|
newline
|
|
eventfld.long 0x00 15. " [15] ,Error status flag 15" "No error,Error"
|
|
eventfld.long 0x00 14. " [14] ,Error status flag 14" "No error,Error"
|
|
newline
|
|
eventfld.long 0x00 13. " [13] ,Error status flag 13" "No error,Error"
|
|
eventfld.long 0x00 12. " [12] ,Error status flag 12" "No error,Error"
|
|
newline
|
|
eventfld.long 0x00 11. " [11] ,Error status flag 11" "No error,Error"
|
|
eventfld.long 0x00 10. " [10] ,Error status flag 10" "No error,Error"
|
|
newline
|
|
eventfld.long 0x00 9. " [9] ,Error status flag 9" "No error,Error"
|
|
eventfld.long 0x00 8. " [8] ,Error status flag 8" "No error,Error"
|
|
newline
|
|
eventfld.long 0x00 7. " [7] ,Error status flag 7" "No error,Error"
|
|
eventfld.long 0x00 6. " [6] ,Error status flag 6" "No error,Error"
|
|
newline
|
|
eventfld.long 0x00 5. " [5] ,Error status flag 5" "No error,Error"
|
|
eventfld.long 0x00 4. " [4] ,Error status flag 4" "No error,Error"
|
|
newline
|
|
eventfld.long 0x00 3. " [3] ,Error status flag 3" "No error,Error"
|
|
eventfld.long 0x00 2. " [2] ,Error status flag 2" "No error,Error"
|
|
newline
|
|
eventfld.long 0x00 1. " [1] ,Error status flag 1" "No error,Error"
|
|
eventfld.long 0x00 0. " [0] ,Error status flag 0" "No error,Error"
|
|
endif
|
|
line.long 0x04 "SR2,Status Register 2"
|
|
sif (cpuis("TMS570LS09*")||cpuis("TMS570LS07*")||cpuis("TMS570LS0232"))
|
|
eventfld.long 0x04 24. " ESF[24] ,Error status flag pin 24 (RTI_WWD_NMI)" "No error,Error"
|
|
eventfld.long 0x04 16. " [16] ,Error status flag pin 16 (TCM - ECC live lock detect)" "No error,Error"
|
|
newline
|
|
eventfld.long 0x04 12. " [12] ,Error status flag pin 12 (RAM odd bank (B1TCM) - address bus parity error )" "No error,Error"
|
|
eventfld.long 0x04 10. " [10] ,Error status flag pin 10 (RAM even bank (B0TCM) - address bus parity error)" "No error,Error"
|
|
newline
|
|
eventfld.long 0x04 8. " [8] ,Error status flag pin 8 (RAM odd bank (B1TCM) - uncorrectable error )" "No error,Error"
|
|
eventfld.long 0x04 6. " [6] ,Error status flag pin 6 (RAM even bank (B0TCM) - uncorrectable error)" "No error,Error"
|
|
newline
|
|
eventfld.long 0x04 4. " [4] ,Error status flag pin 4 (FMC - uncorrectable error (address parity on bus1 accesses))" "No error,Error"
|
|
eventfld.long 0x04 2. " [2] ,Error status flag pin 2 (CCMR4 - compare)" "No error,Error"
|
|
else
|
|
eventfld.long 0x04 31. " ESF[31] ,Error status flag 31" "No error,Error"
|
|
eventfld.long 0x04 30. " [30] ,Error status flag 30" "No error,Error"
|
|
newline
|
|
eventfld.long 0x04 29. " [29] ,Error status flag 29" "No error,Error"
|
|
eventfld.long 0x04 28. " [28] ,Error status flag 28" "No error,Error"
|
|
newline
|
|
eventfld.long 0x04 27. " [27] ,Error status flag 27" "No error,Error"
|
|
eventfld.long 0x04 26. " [26] ,Error status flag 26" "No error,Error"
|
|
newline
|
|
eventfld.long 0x04 25. " [25] ,Error status flag 25" "No error,Error"
|
|
eventfld.long 0x04 24. " [24] ,Error status flag 24" "No error,Error"
|
|
newline
|
|
eventfld.long 0x04 23. " [23] ,Error status flag 23" "No error,Error"
|
|
eventfld.long 0x04 22. " [22] ,Error status flag 22" "No error,Error"
|
|
newline
|
|
eventfld.long 0x04 21. " [21] ,Error status flag 21" "No error,Error"
|
|
eventfld.long 0x04 20. " [20] ,Error status flag 20" "No error,Error"
|
|
newline
|
|
eventfld.long 0x04 19. " [19] ,Error status flag 19" "No error,Error"
|
|
eventfld.long 0x04 18. " [18] ,Error status flag 18" "No error,Error"
|
|
newline
|
|
eventfld.long 0x04 17. " [17] ,Error status flag 17" "No error,Error"
|
|
eventfld.long 0x04 16. " [16] ,Error status flag 16" "No error,Error"
|
|
newline
|
|
eventfld.long 0x04 15. " [15] ,Error status flag 15" "No error,Error"
|
|
eventfld.long 0x04 14. " [14] ,Error status flag 14" "No error,Error"
|
|
newline
|
|
eventfld.long 0x04 13. " [13] ,Error status flag 13" "No error,Error"
|
|
eventfld.long 0x04 12. " [12] ,Error status flag 12" "No error,Error"
|
|
newline
|
|
eventfld.long 0x04 11. " [11] ,Error status flag 11" "No error,Error"
|
|
eventfld.long 0x04 10. " [10] ,Error status flag 10" "No error,Error"
|
|
newline
|
|
eventfld.long 0x04 9. " [9] ,Error status flag 9" "No error,Error"
|
|
eventfld.long 0x04 8. " [8] ,Error status flag 8" "No error,Error"
|
|
newline
|
|
eventfld.long 0x04 7. " [7] ,Error status flag 7" "No error,Error"
|
|
eventfld.long 0x04 6. " [6] ,Error status flag 6" "No error,Error"
|
|
newline
|
|
eventfld.long 0x04 5. " [5] ,Error status flag 5" "No error,Error"
|
|
eventfld.long 0x04 4. " [4] ,Error status flag 4" "No error,Error"
|
|
newline
|
|
eventfld.long 0x04 3. " [3] ,Error status flag 3" "No error,Error"
|
|
eventfld.long 0x04 2. " [2] ,Error status flag 2" "No error,Error"
|
|
newline
|
|
eventfld.long 0x04 1. " [1] ,Error status flag 1" "No error,Error"
|
|
eventfld.long 0x04 0. " [0] ,Error status flag 0" "No error,Error"
|
|
endif
|
|
line.long 0x08 "SR3,Status Register 3"
|
|
sif (cpuis("TMS570LS09*")||cpuis("TMS570LS07*")||cpuis("TMS570LS0232"))
|
|
eventfld.long 0x08 7. " ESF[7] ,Error status flag pin 7 (FMC)" "No error,Error"
|
|
eventfld.long 0x08 5. " [5] ,Error status flag pin 5 (RAM odd bank (B1TCM) - ECC uncorrectable error)" "No error,Error"
|
|
newline
|
|
eventfld.long 0x08 3. " [3] ,Error status flag pin 3 (RAM even bank (B0TCM) - ECC uncorrectable error)" "No error,Error"
|
|
eventfld.long 0x08 1. " [1] ,Error status flag pin 1 (eFuse Farm - autoload error)" "No error,Error"
|
|
else
|
|
eventfld.long 0x08 31. " ESF[31] ,Error status flag 31" "No error,Error"
|
|
eventfld.long 0x08 30. " [30] ,Error status flag 30" "No error,Error"
|
|
newline
|
|
eventfld.long 0x08 29. " [29] ,Error status flag 29" "No error,Error"
|
|
eventfld.long 0x08 28. " [28] ,Error status flag 28" "No error,Error"
|
|
newline
|
|
eventfld.long 0x08 27. " [27] ,Error status flag 27" "No error,Error"
|
|
eventfld.long 0x08 26. " [26] ,Error status flag 26" "No error,Error"
|
|
newline
|
|
eventfld.long 0x08 25. " [25] ,Error status flag 25" "No error,Error"
|
|
eventfld.long 0x08 24. " [24] ,Error status flag 24" "No error,Error"
|
|
newline
|
|
eventfld.long 0x08 23. " [23] ,Error status flag 23" "No error,Error"
|
|
eventfld.long 0x08 22. " [22] ,Error status flag 22" "No error,Error"
|
|
newline
|
|
eventfld.long 0x08 21. " [21] ,Error status flag 21" "No error,Error"
|
|
eventfld.long 0x08 20. " [20] ,Error status flag 20" "No error,Error"
|
|
newline
|
|
eventfld.long 0x08 19. " [19] ,Error status flag 19" "No error,Error"
|
|
eventfld.long 0x08 18. " [18] ,Error status flag 18" "No error,Error"
|
|
newline
|
|
eventfld.long 0x08 17. " [17] ,Error status flag 17" "No error,Error"
|
|
eventfld.long 0x08 16. " [16] ,Error status flag 16" "No error,Error"
|
|
newline
|
|
eventfld.long 0x08 15. " [15] ,Error status flag 15" "No error,Error"
|
|
eventfld.long 0x08 14. " [14] ,Error status flag 14" "No error,Error"
|
|
newline
|
|
eventfld.long 0x08 13. " [13] ,Error status flag 13" "No error,Error"
|
|
eventfld.long 0x08 12. " [12] ,Error status flag 12" "No error,Error"
|
|
newline
|
|
eventfld.long 0x08 11. " [11] ,Error status flag 11" "No error,Error"
|
|
eventfld.long 0x08 10. " [10] ,Error status flag 10" "No error,Error"
|
|
newline
|
|
eventfld.long 0x08 9. " [9] ,Error status flag 9" "No error,Error"
|
|
eventfld.long 0x08 8. " [8] ,Error status flag 8" "No error,Error"
|
|
newline
|
|
eventfld.long 0x08 7. " [7] ,Error status flag 7" "No error,Error"
|
|
eventfld.long 0x08 6. " [6] ,Error status flag 6" "No error,Error"
|
|
newline
|
|
eventfld.long 0x08 5. " [5] ,Error status flag 5" "No error,Error"
|
|
eventfld.long 0x08 4. " [4] ,Error status flag 4" "No error,Error"
|
|
newline
|
|
eventfld.long 0x08 3. " [3] ,Error status flag 3" "No error,Error"
|
|
eventfld.long 0x08 2. " [2] ,Error status flag 2" "No error,Error"
|
|
newline
|
|
eventfld.long 0x08 1. " [1] ,Error status flag 1" "No error,Error"
|
|
eventfld.long 0x08 0. " [0] ,Error status flag 0" "No error,Error"
|
|
endif
|
|
rgroup.long 0x24++0x0F
|
|
line.long 0x00 "EPSR,Error Pin Status Register"
|
|
bitfld.long 0x00 0. " EPSF ,Error pin status flag" "Active,Not active"
|
|
line.long 0x04 "IOFFHR,Interrupt Offset High Register"
|
|
hexmask.long.byte 0x04 0.--6. 1. " INTOFFH ,Offset high level interrupt"
|
|
line.long 0x08 "IOFFLR,Interrupt Offset Low Register"
|
|
hexmask.long.byte 0x08 0.--6. 1. " INTOFFL ,Offset low level interrupt"
|
|
line.long 0x0C "LTCR,Low-Time Counter Register"
|
|
hexmask.long.word 0x0C 0.--15. 1. " LTC ,Error pin low-time counter"
|
|
group.long 0x34++0x0F
|
|
line.long 0x00 "LTCPR,Low-Time Counter Preload Register"
|
|
bitfld.long 0x00 14.--15. " LTCP[15:14] ,Low-time counter pre-load value [15:14]" "0,1,2,3"
|
|
hexmask.long.word 0x00 0.--13. 1. " LTCP[13:0] ,Low-time counter pre-load value [13:0]"
|
|
line.long 0x04 "EKR,Error Key Register"
|
|
bitfld.long 0x04 0.--3. " EKEY ,Error key" "Normal,Normal,Normal,Normal,Normal,LTC,Normal,Normal,Normal,Normal,Forced error,Normal,Normal,Normal,Normal,Normal"
|
|
line.long 0x08 "SSR2,Status Shadow Register"
|
|
sif (cpuis("TMS570LS09*")||cpuis("TMS570LS07*")||cpuis("TMS570LS0232"))
|
|
eventfld.long 0x08 24. " ESF[24] ,Error status flag pin 24 (RTI_WWD_NMI)" "No error,Error"
|
|
eventfld.long 0x08 16. " [16] ,Error status flag pin 16 (TCM - ECC live lock detect)" "No error,Error"
|
|
newline
|
|
eventfld.long 0x08 12. " [12] ,Error status flag pin 12 (RAM odd bank (B1TCM) - address bus parity error )" "No error,Error"
|
|
eventfld.long 0x08 10. " [10] ,Error status flag pin 10 (RAM even bank (B0TCM) - address bus parity error)" "No error,Error"
|
|
newline
|
|
eventfld.long 0x08 8. " [8] ,Error status flag pin 8 (RAM odd bank (B1TCM) - uncorrectable error )" "No error,Error"
|
|
eventfld.long 0x08 6. " [6] ,Error status flag pin 6 (RAM even bank (B0TCM) - uncorrectable error)" "No error,Error"
|
|
newline
|
|
eventfld.long 0x08 4. " [4] ,Error status flag pin 4 (FMC - uncorrectable error (address parity on bus1 accesses))" "No error,Error"
|
|
eventfld.long 0x08 2. " [2] ,Error status flag pin 2 (CCMR4 - compare)" "No error,Error"
|
|
else
|
|
eventfld.long 0x08 31. " ESF[31] ,Error status flag 31" "No error,Error"
|
|
eventfld.long 0x08 30. " [30] ,Error status flag 30" "No error,Error"
|
|
newline
|
|
eventfld.long 0x08 29. " [29] ,Error status flag 29" "No error,Error"
|
|
eventfld.long 0x08 28. " [28] ,Error status flag 28" "No error,Error"
|
|
newline
|
|
eventfld.long 0x08 27. " [27] ,Error status flag 27" "No error,Error"
|
|
eventfld.long 0x08 26. " [26] ,Error status flag 26" "No error,Error"
|
|
newline
|
|
eventfld.long 0x08 25. " [25] ,Error status flag 25" "No error,Error"
|
|
eventfld.long 0x08 24. " [24] ,Error status flag 24" "No error,Error"
|
|
newline
|
|
eventfld.long 0x08 23. " [23] ,Error status flag 23" "No error,Error"
|
|
eventfld.long 0x08 22. " [22] ,Error status flag 22" "No error,Error"
|
|
newline
|
|
eventfld.long 0x08 21. " [21] ,Error status flag 21" "No error,Error"
|
|
eventfld.long 0x08 20. " [20] ,Error status flag 20" "No error,Error"
|
|
newline
|
|
eventfld.long 0x08 19. " [19] ,Error status flag 19" "No error,Error"
|
|
eventfld.long 0x08 18. " [18] ,Error status flag 18" "No error,Error"
|
|
newline
|
|
eventfld.long 0x08 17. " [17] ,Error status flag 17" "No error,Error"
|
|
eventfld.long 0x08 16. " [16] ,Error status flag 16" "No error,Error"
|
|
newline
|
|
eventfld.long 0x08 15. " [15] ,Error status flag 15" "No error,Error"
|
|
eventfld.long 0x08 14. " [14] ,Error status flag 14" "No error,Error"
|
|
newline
|
|
eventfld.long 0x08 13. " [13] ,Error status flag 13" "No error,Error"
|
|
eventfld.long 0x08 12. " [12] ,Error status flag 12" "No error,Error"
|
|
newline
|
|
eventfld.long 0x08 11. " [11] ,Error status flag 11" "No error,Error"
|
|
eventfld.long 0x08 10. " [10] ,Error status flag 10" "No error,Error"
|
|
newline
|
|
eventfld.long 0x08 9. " [9] ,Error status flag 9" "No error,Error"
|
|
eventfld.long 0x08 8. " [8] ,Error status flag 8" "No error,Error"
|
|
newline
|
|
eventfld.long 0x08 7. " [7] ,Error status flag 7" "No error,Error"
|
|
eventfld.long 0x08 6. " [6] ,Error status flag 6" "No error,Error"
|
|
newline
|
|
eventfld.long 0x08 5. " [5] ,Error status flag 5" "No error,Error"
|
|
eventfld.long 0x08 4. " [4] ,Error status flag 4" "No error,Error"
|
|
newline
|
|
eventfld.long 0x08 3. " [3] ,Error status flag 3" "No error,Error"
|
|
eventfld.long 0x08 2. " [2] ,Error status flag 2" "No error,Error"
|
|
newline
|
|
eventfld.long 0x08 1. " [1] ,Error status flag 1" "No error,Error"
|
|
eventfld.long 0x08 0. " [0] ,Error status flag 0" "No error,Error"
|
|
endif
|
|
line.long 0x0C "IEPSR4_SET/CLR,Influence Error Pin Set/Clear Register 4"
|
|
sif (cpuis("TMS570LS09*")||cpuis("TMS570LS07*")||cpuis("TMS570LS0232"))
|
|
sif cpuis("TMS570LS09*")||cpuis("TMS570LS07*")
|
|
setclrfld.long 0x0C 30. 0x0C 30. 0x10 30. " IEPSET[62] ,Set/Clear influence on error pin 62 (DCC2 - error)" "No influence,Influence"
|
|
newline
|
|
endif
|
|
setclrfld.long 0x0C 9. 0x0C 9. 0x10 9. " [41] ,Set/Clear influence on error pin 41 (eFuse farm - self test error)" "No influence,Influence"
|
|
setclrfld.long 0x0C 8. 0x0C 8. 0x10 8. " [40] ,Set/Clear influence on error pin 40 (eFuse farm)" "No influence,Influence"
|
|
sif cpuis("TMS570LS09*")||cpuis("TMS570LS07*")
|
|
newline
|
|
setclrfld.long 0x0C 7. 0x0C 7. 0x10 7. " [39] ,Set/Clear influence on error pin 39 (Power domain controller self-test error)" "No influence,Influence"
|
|
setclrfld.long 0x0C 6. 0x0C 6. 0x10 6. " [38] ,Set/Clear influence on error pin 38 (Power domain controller compare error)" "No influence,Influence"
|
|
endif
|
|
newline
|
|
setclrfld.long 0x0C 5. 0x0C 5. 0x10 5. " [37] ,Set/Clear influence on error pin 37 (IOMM - Mux configuration error)" "No influence,Influence"
|
|
setclrfld.long 0x0C 4. 0x0C 4. 0x10 4. " [36] ,Set/Clear influence on error pin 36 (FMC - uncorrectable error (EEPROM bank access))" "No influence,Influence"
|
|
newline
|
|
setclrfld.long 0x0C 3. 0x0C 3. 0x10 3. " [35] ,Set/Clear influence on error pin 35 (FMC - correctable error (EEPROM bank access))" "No influence,Influence"
|
|
sif cpuis("TMS570LS09*")||cpuis("TMS570LS07*")
|
|
newline
|
|
setclrfld.long 0x0C 2. 0x0C 2. 0x10 2. " [34] ,Set/Clear influence on error pin 34 (N2HET2 - RAM parity error)" "No influence,Influence"
|
|
endif
|
|
else
|
|
setclrfld.long 0x0C 31. 0x0C 31. 0x10 31. " IEPSET[63] ,Set/Clear influence on error pin 63" "No influence,Influence"
|
|
setclrfld.long 0x0C 30. 0x0C 30. 0x10 30. " [62] ,Set/Clear influence on error pin 62" "No influence,Influence"
|
|
newline
|
|
setclrfld.long 0x0C 29. 0x0C 29. 0x10 29. " [61] ,Set/Clear influence on error pin 61" "No influence,Influence"
|
|
setclrfld.long 0x0C 28. 0x0C 28. 0x10 28. " [60] ,Set/Clear influence on error pin 60" "No influence,Influence"
|
|
newline
|
|
setclrfld.long 0x0C 27. 0x0C 27. 0x10 27. " [59] ,Set/Clear influence on error pin 59" "No influence,Influence"
|
|
setclrfld.long 0x0C 26. 0x0C 26. 0x10 26. " [58] ,Set/Clear influence on error pin 58" "No influence,Influence"
|
|
newline
|
|
setclrfld.long 0x0C 25. 0x0C 25. 0x10 25. " [57] ,Set/Clear influence on error pin 57" "No influence,Influence"
|
|
setclrfld.long 0x0C 24. 0x0C 24. 0x10 24. " [56] ,Set/Clear influence on error pin 56" "No influence,Influence"
|
|
newline
|
|
setclrfld.long 0x0C 23. 0x0C 23. 0x10 23. " [55] ,Set/Clear influence on error pin 55" "No influence,Influence"
|
|
setclrfld.long 0x0C 22. 0x0C 22. 0x10 22. " [54] ,Set/Clear influence on error pin 54" "No influence,Influence"
|
|
newline
|
|
setclrfld.long 0x0C 21. 0x0C 21. 0x10 21. " [53] ,Set/Clear influence on error pin 53" "No influence,Influence"
|
|
setclrfld.long 0x0C 20. 0x0C 20. 0x10 20. " [52] ,Set/Clear influence on error pin 52" "No influence,Influence"
|
|
newline
|
|
setclrfld.long 0x0C 19. 0x0C 19. 0x10 19. " [51] ,Set/Clear influence on error pin 51" "No influence,Influence"
|
|
setclrfld.long 0x0C 18. 0x0C 18. 0x10 18. " [50] ,Set/Clear influence on error pin 50" "No influence,Influence"
|
|
newline
|
|
setclrfld.long 0x0C 17. 0x0C 17. 0x10 17. " [49] ,Set/Clear influence on error pin 49" "No influence,Influence"
|
|
setclrfld.long 0x0C 16. 0x0C 16. 0x10 16. " [48] ,Set/Clear influence on error pin 48" "No influence,Influence"
|
|
newline
|
|
setclrfld.long 0x0C 15. 0x0C 15. 0x10 15. " [47] ,Set/Clear influence on error pin 47" "No influence,Influence"
|
|
setclrfld.long 0x0C 14. 0x0C 14. 0x10 14. " [46] ,Set/Clear influence on error pin 46" "No influence,Influence"
|
|
newline
|
|
setclrfld.long 0x0C 13. 0x0C 13. 0x10 13. " [45] ,Set/Clear influence on error pin 45" "No influence,Influence"
|
|
setclrfld.long 0x0C 12. 0x0C 12. 0x10 12. " [44] ,Set/Clear influence on error pin 44" "No influence,Influence"
|
|
newline
|
|
setclrfld.long 0x0C 11. 0x0C 11. 0x10 11. " [43] ,Set/Clear influence on error pin 43" "No influence,Influence"
|
|
setclrfld.long 0x0C 10. 0x0C 10. 0x10 10. " [42] ,Set/Clear influence on error pin 42" "No influence,Influence"
|
|
newline
|
|
setclrfld.long 0x0C 9. 0x0C 9. 0x10 9. " [41] ,Set/Clear influence on error pin 41" "No influence,Influence"
|
|
setclrfld.long 0x0C 8. 0x0C 8. 0x10 8. " [40] ,Set/Clear influence on error pin 40" "No influence,Influence"
|
|
newline
|
|
setclrfld.long 0x0C 7. 0x0C 7. 0x10 7. " [39] ,Set/Clear influence on error pin 39" "No influence,Influence"
|
|
setclrfld.long 0x0C 6. 0x0C 6. 0x10 6. " [38] ,Set/Clear influence on error pin 38" "No influence,Influence"
|
|
newline
|
|
setclrfld.long 0x0C 5. 0x0C 5. 0x10 5. " [37] ,Set/Clear influence on error pin 37" "No influence,Influence"
|
|
setclrfld.long 0x0C 4. 0x0C 4. 0x10 4. " [36] ,Set/Clear influence on error pin 36" "No influence,Influence"
|
|
newline
|
|
setclrfld.long 0x0C 3. 0x0C 3. 0x10 3. " [35] ,Set/Clear influence on error pin 35" "No influence,Influence"
|
|
setclrfld.long 0x0C 2. 0x0C 2. 0x10 2. " [34] ,Set/Clear influence on error pin 34" "No influence,Influence"
|
|
newline
|
|
setclrfld.long 0x0C 1. 0x0C 1. 0x10 1. " [33] ,Set/Clear influence on error pin 33" "No influence,Influence"
|
|
setclrfld.long 0x0C 0. 0x0C 0. 0x10 0. " [32] ,Set/Clear influence on error pin 32" "No influence,Influence"
|
|
endif
|
|
group.long 0x48++0x03
|
|
line.long 0x00 "IESR4_SET/CLR,Interrupt Enable Set/Clear Register 4"
|
|
sif (cpuis("TMS570LS09*")||cpuis("TMS570LS07*")||cpuis("TMS570LS0232"))
|
|
sif cpuis("TMS570LS09*")||cpuis("TMS570LS07*")
|
|
setclrfld.long 0x00 30. 0x00 30. 0x04 30. " INTENSET[62] ,Set/Clear interrupt enable pin 62 (DCC2 - error)" "Disabled,Enabled"
|
|
newline
|
|
endif
|
|
setclrfld.long 0x00 9. 0x00 9. 0x04 9. " [41] ,Set/Clear interrupt enable pin 41 (eFuse farm - self test error)" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x04 8. " [40] ,Set/Clear interrupt enable pin 40 (eFuse farm)" "Disabled,Enabled"
|
|
sif cpuis("TMS570LS09*")||cpuis("TMS570LS07*")
|
|
newline
|
|
setclrfld.long 0x00 7. 0x00 7. 0x04 7. " [39] ,Set/Clear interrupt enable pin 39 (Power domain controller self-test error)" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x04 6. " [38] ,Set/Clear interrupt enable pin 38 (Power domain controller compare error)" "Disabled,Enabled"
|
|
endif
|
|
newline
|
|
setclrfld.long 0x00 5. 0x00 5. 0x04 5. " [37] ,Set/Clear interrupt enable pin 37 (IOMM - Mux configuration error)" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x04 4. " [36] ,Set/Clear interrupt enable pin 36 (FMC - uncorrectable error (EEPROM bank access))" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 3. 0x00 3. 0x04 3. " [35] ,Set/Clear interrupt enable pin 35 (FMC - correctable error (EEPROM bank access))" "Disabled,Enabled"
|
|
sif cpuis("TMS570LS09*")||cpuis("TMS570LS07*")
|
|
newline
|
|
setclrfld.long 0x00 2. 0x00 2. 0x04 2. " [34] ,Set/Clear interrupt enable pin 34 (N2HET2 - RAM parity error)" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
setclrfld.long 0x00 31. 0x00 31. 0x04 31. " INTENSET[63] ,Set/Clear interrupt enable pin 63" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x04 30. " [62] ,Set/Clear interrupt enable pin 62" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 29. 0x00 29. 0x04 29. " [61] ,Set/Clear interrupt enable pin 61" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x04 28. " [60] ,Set/Clear interrupt enable pin 60" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 27. 0x00 27. 0x04 27. " [59] ,Set/Clear interrupt enable pin 59" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x04 26. " [58] ,Set/Clear interrupt enable pin 58" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 25. 0x00 25. 0x04 25. " [57] ,Set/Clear interrupt enable pin 57" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x04 24. " [56] ,Set/Clear interrupt enable pin 56" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 23. 0x00 23. 0x04 23. " [55] ,Set/Clear interrupt enable pin 55" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x04 22. " [54] ,Set/Clear interrupt enable pin 54" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 21. 0x00 21. 0x04 21. " [53] ,Set/Clear interrupt enable pin 53" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x04 20. " [52] ,Set/Clear interrupt enable pin 52" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 19. 0x00 19. 0x04 19. " [51] ,Set/Clear interrupt enable pin 51" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x04 18. " [50] ,Set/Clear interrupt enable pin 50" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 17. 0x00 17. 0x04 17. " [49] ,Set/Clear interrupt enable pin 49" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x04 16. " [48] ,Set/Clear interrupt enable pin 48" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 15. 0x00 15. 0x04 15. " [47] ,Set/Clear interrupt enable pin 47" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x04 14. " [46] ,Set/Clear interrupt enable pin 46" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 13. 0x00 13. 0x04 13. " [45] ,Set/Clear interrupt enable pin 45" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x04 12. " [44] ,Set/Clear interrupt enable pin 44" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 11. 0x00 11. 0x04 11. " [43] ,Set/Clear interrupt enable pin 43" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x04 10. " [42] ,Set/Clear interrupt enable pin 42" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 9. 0x00 9. 0x04 9. " [41] ,Set/Clear interrupt enable pin 41" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x04 8. " [40] ,Set/Clear interrupt enable pin 40" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 7. 0x00 7. 0x04 7. " [39] ,Set/Clear interrupt enable pin 39" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x04 6. " [38] ,Set/Clear interrupt enable pin 38" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 5. 0x00 5. 0x04 5. " [37] ,Set/Clear interrupt enable pin 37" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x04 4. " [36] ,Set/Clear interrupt enable pin 36" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 3. 0x00 3. 0x04 3. " [35] ,Set/Clear interrupt enable pin 35" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x04 2. " [34] ,Set/Clear interrupt enable pin 34" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 1. 0x00 1. 0x04 1. " [33] ,Set/Clear interrupt enable pin 33" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x04 0. " [32] ,Set/Clear interrupt enable pin 32" "Disabled,Enabled"
|
|
endif
|
|
group.long 0x50++0x03
|
|
line.long 0x00 "ILSR4_SET/CLR,Interrupt Level Set/Clear Register 4"
|
|
sif (cpuis("TMS570LS09*")||cpuis("TMS570LS07*")||cpuis("TMS570LS0232"))
|
|
sif cpuis("TMS570LS09*")||cpuis("TMS570LS07*")
|
|
setclrfld.long 0x00 30. 0x00 30. 0x04 30. " INTLVLSET[62] ,Set/Clear interrupt level pin 62 (DCC2 - error)" "Low,High"
|
|
newline
|
|
endif
|
|
setclrfld.long 0x00 9. 0x00 9. 0x04 9. " [41] ,Set/Clear interrupt level pin 41 (eFuse farm - self test error)" "Low,High"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x04 8. " [40] ,Set/Clear interrupt level pin 40 (eFuse farm)" "Low,High"
|
|
sif cpuis("TMS570LS09*")||cpuis("TMS570LS07*")
|
|
newline
|
|
setclrfld.long 0x00 7. 0x00 7. 0x04 7. " [39] ,Set/Clear interrupt level pin 39 (Power domain controller self-test error)" "Low,High"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x04 6. " [38] ,Set/Clear interrupt level pin 38 (Power domain controller compare error)" "Low,High"
|
|
endif
|
|
newline
|
|
setclrfld.long 0x00 5. 0x00 5. 0x04 5. " [37] ,Set/Clear interrupt level pin 37 (IOMM - Mux configuration error)" "Low,High"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x04 4. " [36] ,Set/Clear interrupt level pin 36 (FMC - uncorrectable error (EEPROM bank access))" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 3. 0x00 3. 0x04 3. " [35] ,Set/Clear interrupt level pin 35 (FMC - correctable error (EEPROM bank access))" "Low,High"
|
|
sif cpuis("TMS570LS09*")||cpuis("TMS570LS07*")
|
|
newline
|
|
setclrfld.long 0x00 2. 0x00 2. 0x04 2. " [34] ,Set/Clear interrupt level pin 34 (N2HET2 - RAM parity error)" "Low,High"
|
|
endif
|
|
else
|
|
setclrfld.long 0x00 31. 0x00 31. 0x04 31. " INTLVLSET[63] ,Set/Clear interrupt level pin 63" "Low,High"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x04 30. " [62] ,Set/Clear interrupt level pin 62" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 29. 0x00 29. 0x04 29. " [61] ,Set/Clear interrupt level pin 61" "Low,High"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x04 28. " [60] ,Set/Clear interrupt level pin 60" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 27. 0x00 27. 0x04 27. " [59] ,Set/Clear interrupt level pin 59" "Low,High"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x04 26. " [58] ,Set/Clear interrupt level pin 58" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 25. 0x00 25. 0x04 25. " [57] ,Set/Clear interrupt level pin 57" "Low,High"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x04 24. " [56] ,Set/Clear interrupt level pin 56" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 23. 0x00 23. 0x04 23. " [55] ,Set/Clear interrupt level pin 55" "Low,High"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x04 22. " [54] ,Set/Clear interrupt level pin 54" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 21. 0x00 21. 0x04 21. " [53] ,Set/Clear interrupt level pin 53" "Low,High"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x04 20. " [52] ,Set/Clear interrupt level pin 52" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 19. 0x00 19. 0x04 19. " [51] ,Set/Clear interrupt level pin 51" "Low,High"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x04 18. " [50] ,Set/Clear interrupt level pin 50" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 17. 0x00 17. 0x04 17. " [49] ,Set/Clear interrupt level pin 49" "Low,High"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x04 16. " [48] ,Set/Clear interrupt level pin 48" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 15. 0x00 15. 0x04 15. " [47] ,Set/Clear interrupt level pin 47" "Low,High"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x04 14. " [46] ,Set/Clear interrupt level pin 46" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 13. 0x00 13. 0x04 13. " [45] ,Set/Clear interrupt level pin 45" "Low,High"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x04 12. " [44] ,Set/Clear interrupt level pin 44" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 11. 0x00 11. 0x04 11. " [43] ,Set/Clear interrupt level pin 43" "Low,High"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x04 10. " [42] ,Set/Clear interrupt level pin 42" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 9. 0x00 9. 0x04 9. " [41] ,Set/Clear interrupt level pin 41" "Low,High"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x04 8. " [40] ,Set/Clear interrupt level pin 40" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 7. 0x00 7. 0x04 7. " [39] ,Set/Clear interrupt level pin 39" "Low,High"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x04 6. " [38] ,Set/Clear interrupt level pin 38" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 5. 0x00 5. 0x04 5. " [37] ,Set/Clear interrupt level pin 37" "Low,High"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x04 4. " [36] ,Set/Clear interrupt level pin 36" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 3. 0x00 3. 0x04 3. " [35] ,Set/Clear interrupt level pin 35" "Low,High"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x04 2. " [34] ,Set/Clear interrupt level pin 34" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 1. 0x00 1. 0x04 1. " [33] ,Set/Clear interrupt level pin 33" "Low,High"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x04 0. " [32] ,Set/Clear interrupt level pin 32" "Low,High"
|
|
endif
|
|
group.long 0x58++0x03
|
|
line.long 0x0 "SR4_SET/CLR,Status Register 4"
|
|
sif (cpuis("TMS570LS09*")||cpuis("TMS570LS07*")||cpuis("TMS570LS0232"))
|
|
sif cpuis("TMS570LS09*")||cpuis("TMS570LS07*")
|
|
eventfld.long 0x00 30. " ESF[62] ,Error status flag pin 62 (DCC2 - error)" "No error,Error"
|
|
newline
|
|
endif
|
|
eventfld.long 0x00 9. " [41] ,Error status flag pin 41 (eFuse farm - self test error)" "No error,Error"
|
|
eventfld.long 0x00 8. " [40] ,Error status flag pin 40 (eFuse farm)" "No error,Error"
|
|
sif cpuis("TMS570LS09*")||cpuis("TMS570LS07*")
|
|
newline
|
|
eventfld.long 0x00 7. " [39] ,Error status flag pin 39 (Power domain controller self-test error)" "No error,Error"
|
|
eventfld.long 0x00 6. " [38] ,Error status flag pin 38 (Power domain controller compare error)" "No error,Error"
|
|
endif
|
|
newline
|
|
eventfld.long 0x00 5. " [37] ,Error status flag pin 37 (IOMM - Mux configuration error)" "Low,High"
|
|
eventfld.long 0x00 4. " [36] ,Error status flag pin 36 (FMC - uncorrectable error (EEPROM bank access))" "No error,Error"
|
|
newline
|
|
eventfld.long 0x00 3. " [35] ,Error status flag pin 35 (FMC - correctable error (EEPROM bank access))" "No error,Error"
|
|
sif cpuis("TMS570LS09*")||cpuis("TMS570LS07*")
|
|
newline
|
|
eventfld.long 0x00 2. " [34] ,Error status flag pin 34 (N2HET2 - RAM parity error)" "No error,Error"
|
|
endif
|
|
else
|
|
eventfld.long 0x00 31. " ESF[63] ,Error status flag 63" "No error,Error"
|
|
eventfld.long 0x00 30. " [62] ,Error status flag 62" "No error,Error"
|
|
newline
|
|
eventfld.long 0x00 29. " [61] ,Error status flag 61" "No error,Error"
|
|
eventfld.long 0x00 28. " [60] ,Error status flag 60" "No error,Error"
|
|
newline
|
|
eventfld.long 0x00 27. " [59] ,Error status flag 59" "No error,Error"
|
|
eventfld.long 0x00 26. " [58] ,Error status flag 58" "No error,Error"
|
|
newline
|
|
eventfld.long 0x00 25. " [57] ,Error status flag 57" "No error,Error"
|
|
eventfld.long 0x00 24. " [56] ,Error status flag 56" "No error,Error"
|
|
newline
|
|
eventfld.long 0x00 23. " [55] ,Error status flag 55" "No error,Error"
|
|
eventfld.long 0x00 22. " [54] ,Error status flag 54" "No error,Error"
|
|
newline
|
|
eventfld.long 0x00 21. " [53] ,Error status flag 53" "No error,Error"
|
|
eventfld.long 0x00 20. " [52] ,Error status flag 52" "No error,Error"
|
|
newline
|
|
eventfld.long 0x00 19. " [51] ,Error status flag 51" "No error,Error"
|
|
eventfld.long 0x00 18. " [50] ,Error status flag 50" "No error,Error"
|
|
newline
|
|
eventfld.long 0x00 17. " [49] ,Error status flag 49" "No error,Error"
|
|
eventfld.long 0x00 16. " [48] ,Error status flag 48" "No error,Error"
|
|
newline
|
|
eventfld.long 0x00 15. " [47] ,Error status flag 47" "No error,Error"
|
|
eventfld.long 0x00 14. " [46] ,Error status flag 46" "No error,Error"
|
|
newline
|
|
eventfld.long 0x00 13. " [45] ,Error status flag 45" "No error,Error"
|
|
eventfld.long 0x00 12. " [44] ,Error status flag 44" "No error,Error"
|
|
newline
|
|
eventfld.long 0x00 11. " [43] ,Error status flag 43" "No error,Error"
|
|
eventfld.long 0x00 10. " [42] ,Error status flag 42" "No error,Error"
|
|
newline
|
|
eventfld.long 0x00 9. " [41] ,Error status flag 41" "No error,Error"
|
|
eventfld.long 0x00 8. " [40] ,Error status flag 40" "No error,Error"
|
|
newline
|
|
eventfld.long 0x00 7. " [39] ,Error status flag 39" "No error,Error"
|
|
eventfld.long 0x00 6. " [38] ,Error status flag 38" "No error,Error"
|
|
newline
|
|
eventfld.long 0x00 5. " [37] ,Error status flag 37" "No error,Error"
|
|
eventfld.long 0x00 4. " [36] ,Error status flag 36" "No error,Error"
|
|
newline
|
|
eventfld.long 0x00 3. " [35] ,Error status flag 35" "No error,Error"
|
|
eventfld.long 0x00 2. " [34] ,Error status flag 34" "No error,Error"
|
|
newline
|
|
eventfld.long 0x00 1. " [33] ,Error status flag 33" "No error,Error"
|
|
eventfld.long 0x00 0. " [32] ,Error status flag 32" "No error,Error"
|
|
endif
|
|
sif (cpuis("TMS570LS09*")||cpuis("TMS570LS07*")||cpuis("TMS570LS0232"))
|
|
endian.le
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
tree "RTI (Real-Time Interrupt)"
|
|
base ad:0xFFFFFC00
|
|
sif cpuis("TMS570LS09*")||cpuis("TMS570LS07*")||cpuis("TMS570LS0232")
|
|
endian.be
|
|
endif
|
|
width 16.
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "GCTRL,Global Control Register"
|
|
sif (cpuis("TMS570LS1114*")||cpuis("TMS570LS1115*")||cpuis("TMS570LS1224*")||cpuis("TMS570LS1225*")||cpuis("TMS570LS1227*")||cpuis("TMS570LS3137-EP"))
|
|
bitfld.long 0x00 16.--19. " NTUSEL ,Select NTU signal" "NTU0,,,,,NTU1,,,,,NTU2,,,,,NTU3"
|
|
bitfld.long 0x00 15. " COS ,Continue on suspend" "Stopped,Running"
|
|
newline
|
|
else
|
|
sif (cpu()!="TMS470MF031")&&(cpu()!="TMS470MF042")&&(cpu()!="TMS470MF066"&&cpu()!=("TMS570LS0332")&&cpu()!=("TMS570LS0432"))&&!cpuis("TMS570LS09*")&&!cpuis("TMS570LS07*")&&!cpuis("TMS570LS0232")
|
|
bitfld.long 0x00 16.--17. " NTUSEL ,Select NTU signal" "NTU0,NTU1,?..."
|
|
bitfld.long 0x00 15. " COS ,Continue on suspend" "Stopped,Running"
|
|
newline
|
|
else
|
|
bitfld.long 0x00 15. " COS ,Continue on suspend" "Stopped,Running"
|
|
newline
|
|
endif
|
|
endif
|
|
bitfld.long 0x00 1. " CNT1EN ,Counter 1 enable" "Stopped,Started"
|
|
bitfld.long 0x00 0. " CNT0EN ,Counter 0 enable" "Stopped,Started"
|
|
sif (cpu()!="TMS470MF031")&&(cpu()!="TMS470MF042")&&(cpu()!="TMS470MF066"&&cpu()!=("TMS570LS0332")&&cpu()!=("TMS570LS0432"))&&!cpuis("TMS570LS0232")
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "TBCTRL,Timebase Control Register"
|
|
bitfld.long 0x00 1. " INC ,Increment free running counter" "Not incremented,Incremented"
|
|
sif cpuis("TMS570LS09*")||cpuis("TMS570LS07*")||cpuis("TMS570LS3137-EP")
|
|
newline
|
|
bitfld.long 0x00 0. " TBEXT ,Time base external" "Clocks FRC0,Not clocks FRC0"
|
|
else
|
|
newline
|
|
bitfld.long 0x00 0. " TBEXT ,Time base external" "UC0,NTU"
|
|
endif
|
|
endif
|
|
group.long 0x08++0x07
|
|
line.long 0x00 "CAPCTRL,Capture Control Register"
|
|
bitfld.long 0x00 1. " CAPCNTR1 ,Capture counter 1" "CES 0,CES 1"
|
|
bitfld.long 0x00 0. " CAPCNTR0 ,Capture counter 0" "CES 0,CES 1"
|
|
line.long 0x04 "COMPCTRL,Compare Control Register"
|
|
bitfld.long 0x04 12. " COMPSEL3 ,Compare select 3" "FRC0,FRC1"
|
|
bitfld.long 0x04 8. " COMPSEL2 ,Compare select 2" "FRC0,FRC1"
|
|
bitfld.long 0x04 4. " COMPSEL1 ,Compare select 1" "FRC0,FRC1"
|
|
newline
|
|
bitfld.long 0x04 0. " COMPSEL0 ,Compare select 0" "FRC0,FRC1"
|
|
sif cpuis("TMS570LS3137-EP")
|
|
hgroup.long 0x10++0x03
|
|
hide.long 0x00 "FRC0,Free Running Counter 0 Register"
|
|
in
|
|
else
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "FRC0,Free Running Counter 0 Register"
|
|
endif
|
|
group.long 0x14++0x07
|
|
line.long 0x00 "UC0,Up Counter 0 Register"
|
|
line.long 0x04 "CPUC0,Compare Up Counter 0 Register"
|
|
rgroup.long 0x20++0x07
|
|
line.long 0x00 "CAFRC0,Capture Free Running Counter 0 Register"
|
|
line.long 0x04 "CAUC0,Capture Up Counter 0 Register"
|
|
sif cpuis("TMS570LS3137-EP")
|
|
hgroup.long 0x30++0x03
|
|
hide.long 0x00 "FRC1,Free Running Counter 1 Register"
|
|
in
|
|
else
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "FRC1,Free Running Counter 1 Register"
|
|
endif
|
|
group.long 0x34++0x07
|
|
line.long 0x00 "UC1,Up Counter 1 Register"
|
|
line.long 0x04 "CPUC1,Compare Up Counter 1 Register"
|
|
rgroup.long 0x40++0x07
|
|
line.long 0x00 "CAFRC1,Capture Free Running Counter 1 Register"
|
|
line.long 0x04 "CAUC1,Capture Up Counter 1 Register"
|
|
group.long 0x50++0x1F
|
|
line.long 0x00 "COMP0,Compare 0 Register"
|
|
line.long 0x04 "UDCP0,Update Compare 0 Register"
|
|
line.long 0x08 "COMP1,Compare 1 Register"
|
|
line.long 0x0C "UDCP1,Update Compare 1 Register"
|
|
line.long 0x10 "COMP2,Compare 2 Register"
|
|
line.long 0x14 "UDCP2,Update Compare 2 Register"
|
|
line.long 0x18 "COMP3,Compare 3 Register"
|
|
line.long 0x1C "UDCP3,Update Compare 3 Register"
|
|
sif (cpu()!="TMS470MF031")&&(cpu()!="TMS470MF042")&&(cpu()!="TMS470MF066"&&cpu()!=("TMS570LS0332")&&cpu()!=("TMS570LS0432"))&&!cpuis("TMS570LS09*")&&!cpuis("TMS570LS07*")&&!cpuis("TMS570LS0232")
|
|
group.long 0x70++0x07
|
|
line.long 0x00 "TBLCOMP,External Clock Timebase Low Compare Register"
|
|
line.long 0x04 "TBHCOMP,External Clock Timebase High Compare Register"
|
|
endif
|
|
group.long 0x80++0x03
|
|
line.long 0x00 "SETINT_SET/CLR,Set/Clear Interrupt Register"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x04 18. " SETOVL1IN_SET/CLR ,Free running counter 1 overflow interrupt" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x04 17. " SETOVL0INT_SET/CLR ,Free running counter 0 overflow interrupt" "Disabled,Enabled"
|
|
sif (cpu()!="TMS470MF031")&&(cpu()!="TMS470MF042")&&(cpu()!="TMS470MF066")
|
|
newline
|
|
setclrfld.long 0x00 16. 0x00 16. 0x04 16. " SETTBINT_SET/CLR ,Timebase interrupt" "Disabled,Enabled"
|
|
sif (cpu()!=("TMS570LS0332")&&cpu()!=("TMS570LS0432"))&&!cpuis("TMS570LS0232")
|
|
newline
|
|
setclrfld.long 0x00 11. 0x00 11. 0x04 11. " SETDMA3_SET/CLR ,Compare DMA request 3" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x04 10. " SETDMA2_SET/CLR ,Compare DMA request 2" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x04 9. " SETDMA1_SET/CLR ,Compare DMA request 1" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 8. 0x00 8. 0x04 8. " SETDMA0_SET/CLR ,Compare DMA request 0" "Disabled,Enabled"
|
|
endif
|
|
newline
|
|
setclrfld.long 0x00 3. 0x00 3. 0x04 3. " SETINT3_SET/CLR ,Compare interrupt 3" "Disabled,Enabled"
|
|
else
|
|
newline
|
|
setclrfld.long 0x00 3. 0x00 3. 0x04 3. " SETINT3_SET/CLR ,Compare interrupt 3" "Disabled,Enabled"
|
|
endif
|
|
newline
|
|
setclrfld.long 0x00 2. 0x00 2. 0x04 2. " SETINT2_SET/CLR ,Compare interrupt 2" "Disabled,Enabled"
|
|
setclrfld.long 0x00 1. 0x00 1. 0x04 1. " SETINT1_SET/CLR ,Compare interrupt 1" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x04 0. " SETINT0_SET/CLR ,Compare interrupt 0" "Disabled,Enabled"
|
|
group.long 0x88++0x03
|
|
line.long 0x00 "INTFLAG,Interrupt Flag Register"
|
|
eventfld.long 0x00 18. " OVL1INT ,Free running counter 1 overflow interrupt flag" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 17. " OVL0INT ,Free running counter 0 overflow interrupt flag" "No interrupt,Interrupt"
|
|
sif (cpu()!="TMS470MF031")&&(cpu()!="TMS470MF042")&&(cpu()!="TMS470MF066")
|
|
newline
|
|
eventfld.long 0x00 16. " TBINT ,Timebase interrupt flag" "No interrupt,Interrupt"
|
|
endif
|
|
newline
|
|
eventfld.long 0x00 3. " INT3 ,Interrupt flag 3" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 2. " INT2 ,Interrupt flag 2" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 1. " INT1 ,Interrupt flag 1" "No interrupt,Interrupt"
|
|
newline
|
|
eventfld.long 0x00 0. " INT0 ,Interrupt flag 0" "No interrupt,Interrupt"
|
|
sif (cpu()!="TMS570PSFC61")
|
|
group.long 0x90++0x0F
|
|
line.long 0x00 "DWDCTRL,Digital Watchdog Control Register"
|
|
line.long 0x04 "DWDPRLD,Digital Watchdog Preload Register"
|
|
hexmask.long.word 0x04 0.--11. 1. " DWDPRLD ,Digital watchdog preload value"
|
|
line.long 0x08 "WDSTATUS,Watchdog Status Register"
|
|
sif (cpu()==("TMS570LC4357")||cpu()==("TMS570LS2126")||cpu()==("TMS570LS2127")||cpu()==("TMS570LS2136")||cpu()==("TMS570LS2137")||cpu()==("TMS570LS2125-PGE")||cpu()==("TMS570LS2125-ZWT")||cpu()==("TMS570LS2135-PGE")||cpu()==("TMS570LS2135-ZWT")||cpu()==("TMS570LS2124-PGE")||cpu()==("TMS570LS2124-ZWT")||cpu()==("TMS570LS2134-PGE")||cpu()==("TMS570LS2134-ZWT")||cpu()==("TMS570LS3134-PGE")||cpu()==("TMS570LS3134-ZWT")||cpu()==("TMS570LS3135-PGE")||cpu()==("TMS570LS3135-ZWT")||cpu()==("TMS570LS3136")||cpu()==("TMS570LS3137-PGE")||cpu()==("TMS570LS3137-ZWT")||cpu()==("TMS570LS30336")||cpuis("RM48L950*")||cpu()==("TMS570LS0332")||cpu()==("TMS570LS0432")||cpuis("TMS570LS1114*")||cpuis("TMS570LS1115*")||cpuis("TMS570LS1224*")||cpuis("TMS570LS1225*")||cpuis("TMS570LS1227*")||cpuis("TMS570LS3137-EP")||cpuis("TMS570LS09*")||cpuis("TMS570LS07*")||cpuis("TMS570LS0232"))
|
|
eventfld.long 0x08 5. " DWWD_ST ,Windowed watchdog status" "Not occurred,Occurred"
|
|
eventfld.long 0x08 4. " END_TIME_VIOL ,Windowed watchdog end time violation status" "Not occurred,Occurred"
|
|
eventfld.long 0x08 3. " START_TIME_VIOL ,Windowed watchdog start time violation status" "Not occurred,Occurred"
|
|
newline
|
|
eventfld.long 0x08 2. " KEYST ,Watchdog key status" "Not occurred,Occurred"
|
|
eventfld.long 0x08 1. " DWDST ,Digital watchdog status" "Not occurred,Occurred"
|
|
else
|
|
eventfld.long 0x08 2. " KEYST ,Watchdog key status" "Not occurred,Occurred"
|
|
eventfld.long 0x08 1. " DWDST ,Digital watchdog status" "Not occurred,Occurred"
|
|
sif (cpu()!="TMS470MF031")&&(cpu()!="TMS470MF042")&&(cpu()!="TMS470MF066")
|
|
eventfld.long 0x08 0. " AWDST ,Analog watchdog status" "Not occurred,Occurred"
|
|
endif
|
|
endif
|
|
line.long 0x0C "WDKEY,Watchdog Key Register"
|
|
hexmask.long.word 0x0C 0.--15. 1. " WDKEY ,Watchdog key"
|
|
rgroup.long 0xA0++0x03
|
|
line.long 0x00 "WDCNTR,Digital Watchdog Down Counter"
|
|
hexmask.long 0x00 0.--24. 1. " DWDCNTR ,Digital watchdog down counter"
|
|
endif
|
|
sif (cpu()==("TMS570LC4357")||cpu()==("TMS570LS2126")||cpu()==("TMS570LS2127")||cpu()==("TMS570LS2136")||cpu()==("TMS570LS2137")||cpu()==("TMS570LS2125-PGE")||cpu()==("TMS570LS2125-ZWT")||cpu()==("TMS570LS2135-PGE")||cpu()==("TMS570LS2135-ZWT")||cpu()==("TMS570LS2124-PGE")||cpu()==("TMS570LS2124-ZWT")||cpu()==("TMS570LS2134-PGE")||cpu()==("TMS570LS2134-ZWT")||cpu()==("TMS570LS3134-PGE")||cpu()==("TMS570LS3134-ZWT")||cpu()==("TMS570LS3135-PGE")||cpu()==("TMS570LS3135-ZWT")||cpu()==("TMS570LS3136")||cpu()==("TMS570LS3137-PGE")||cpu()==("TMS570LS3137-ZWT")||cpu()==("TMS570LS30336")||cpuis("RM48L950*")||cpu()==("TMS570LS0332")||cpu()==("TMS570LS0432")||cpuis("TMS570LS1114*")||cpuis("TMS570LS1115*")||cpuis("TMS570LS1224*")||cpuis("TMS570LS1225*")||cpuis("TMS570LS1227*")||cpuis("TMS570LS3137-EP")||cpuis("TMS570LS09*")||cpuis("TMS570LS07*")||cpuis("TMS570LS0232"))
|
|
group.long 0xA4++0x07
|
|
line.long 0x00 "WWDRXNCTRL,Digital Windowed Watchdog Reaction Control"
|
|
sif (cpuis("TMS570LS09*")||cpuis("TMS570LS07*")||cpuis("TMS570LS0232")||cpuis("TMS570LS3137-EP"))
|
|
bitfld.long 0x00 0.--3. " WWDRXN ,The DWWD reaction" "Reset,Reset,Reset,Reset,Reset,Reset,Reset,Reset,Reset,Reset,Interrupt,Reset,Reset,Reset,Reset,Reset"
|
|
else
|
|
bitfld.long 0x00 0.--3. " DWDST ,The DWWD reaction" "Reset,Reset,Reset,Reset,Reset,Reset,Reset,Reset,Reset,Reset,Interrupt,Reset,Reset,Reset,Reset,Reset"
|
|
endif
|
|
line.long 0x04 "WWDSIZECTRL,Digital Windowed Watchdog Window Size Control"
|
|
endif
|
|
sif cpuis("TMS570LS09*")||cpuis("TMS570LS07*")||cpuis("TMS570LS0232")||cpuis("TMS570LS3137-EP")
|
|
group.long 0xAC++0x13
|
|
line.long 0x00 "INTCLRENABLE,Compare Interrupt Clear Enable Register"
|
|
bitfld.long 0x00 24.--27. " INTCLRENABLE3 ,Auto-clear functionality on the compare 3 interrupt enable" "Enabled,Enabled,Enabled,Enabled,Enabled,Disabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled"
|
|
bitfld.long 0x00 16.--19. " INTCLRENABLE2 ,Auto-clear functionality on the compare 2 interrupt enable" "Enabled,Enabled,Enabled,Enabled,Enabled,Disabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled"
|
|
bitfld.long 0x00 8.--11. " INTCLRENABLE1 ,Auto-clear functionality on the compare 1 interrupt enable" "Enabled,Enabled,Enabled,Enabled,Enabled,Disabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 0.--3. " INTCLRENABLE0 ,Auto-clear functionality on the compare 0 interrupt enable" "Enabled,Enabled,Enabled,Enabled,Enabled,Disabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled"
|
|
line.long 0x04 "CMP0CLR,Compare 0 Clear Register"
|
|
line.long 0x08 "CMP1CLR,Compare 1 Clear Register"
|
|
line.long 0x0C "CMP2CLR,Compare 2 Clear Register"
|
|
line.long 0x10 "CMP3CLR,Compare 3 Clear Register"
|
|
endif
|
|
sif cpuis("TMS570LS09*")||cpuis("TMS570LS07*")||cpuis("TMS570LS0232")
|
|
endian.le
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
tree "CRC (Cyclic Redundancy Check Controller Module)"
|
|
base ad:0xFE000000
|
|
sif cpuis("TMS570LS0232")||cpuis("TMS570LS0714*")||cpuis("TMS570LS0914*")
|
|
endian.be
|
|
endif
|
|
width 20.
|
|
group.long 0x00++0x3
|
|
line.long 0x0 "CRC_CTRL0,CRC Global Control Register 0"
|
|
bitfld.long 0x00 8. " CH2_PSA_SWREST ,Channel 2 PSA Software Reset" "No reset,Reset"
|
|
bitfld.long 0x00 0. " CH1_PSA_SWREST ,Channel 1 PSA Software Reset" "No reset,Reset"
|
|
group.long 0x08++0x3
|
|
line.long 0x0 "CRC_CTRL1,CRC Global Control Register 1"
|
|
bitfld.long 0x00 0. " PWDN ,Power Down" "Not powered down,Powered down"
|
|
group.long 0x10++0x3
|
|
line.long 0x0 "CRC_CTRL2,CRC Global Control Register 2"
|
|
sif (cpu()==("TMS570LS0332")||cpu()==("TMS570LS0432"))
|
|
bitfld.long 0x00 8.--9. " CH2_MODE ,Channel 2 Mode" "Data capture,Auto,?..."
|
|
bitfld.long 0x00 4. " CH1_TRACEEN ,Channel 1 Data Trace Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--1. " CH1_MODE ,Channel 1 Mode" "Data capture,Auto,?..."
|
|
elif cpuis("TMS570LS0232")
|
|
bitfld.long 0x00 8.--9. " CH2_MODE ,Channel 2 Mode" "Data capture,,,Full-CPU"
|
|
bitfld.long 0x00 4. " CH1_TRACEEN ,Channel 1 Data Trace Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--1. " CH1_MODE ,Channel 1 Mode" "Data capture,,,Full-CPU"
|
|
elif cpuis("TMS570LS0714*")||cpuis("TMS570LS0914*")
|
|
bitfld.long 0x00 8.--9. " CH2_MODE ,Channel 2 mode" "Data capture,Auto,Semi-CPU,Full-CPU"
|
|
bitfld.long 0x00 4. " CH1_TRACEEN ,Channel 1 Data Trace Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--1. " CH1_MODE ,Channel 1 mode" "Data capture,Auto,Semi-CPU,Full-CPU"
|
|
else
|
|
bitfld.long 0x00 8.--9. " CH2_MODE ,Channel 2 Mode" "Data capture,Auto,,Full-CPU"
|
|
bitfld.long 0x00 4. " CH1_TRACEEN ,Channel 1 Data Trace Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--1. " CH1_MODE ,Channel 1 Mode" "Data capture,Auto,,Full-CPU"
|
|
endif
|
|
sif cpuis("TMS570LS0714*")||cpuis("TMS570LS0914*")
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "CRC_INTS,Write One To A Bit To Enable A Interrupt"
|
|
bitfld.long 0x00 12. " CH2_TIMEOUTENS ,Channel 2 timeout interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " CH2_UNDERENS ,Channel 2 underrun interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " CH2_OVERENS ,Channel 2 overrun interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " CH2_CRCFAILENS ,Channel 2 CRC fail interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " CH2_CCITEN ,Channel 2 compression complete interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 4. " CH1_TIMEOUTENS ,Channel 1 timeout interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " CH1_UNDERENS ,Channel 1 underrun interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " CH1_OVERENS ,Channel 1 overrun interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CH1_CRCFAILENS ,Channel 1 CRC fail interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CH1_CCITEN ,Channel 1 compression complete interrupt enable" "Disabled,Enabled"
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "CRC_INTR,Write One To A Bit To Disable A Interrupt"
|
|
bitfld.long 0x00 12. " CH2_TIMEOUTENR ,Channel 2 timeout interrupt disable" "No,Yes"
|
|
bitfld.long 0x00 11. " CH2_UNDERENR ,Channel 2 underrun interrupt disable" "No,Yes"
|
|
bitfld.long 0x00 10. " CH2_OVERENR ,Channel 2 overrun interrupt disable" "No,Yes"
|
|
bitfld.long 0x00 9. " CH2_CRCFAILENR ,Channel 2 CRC fail interrupt disable" "No,Yes"
|
|
bitfld.long 0x00 8. " CH2_CCITEN ,Channel 2 compression complete interrupt disable" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 4. " CH1_TIMEOUTENR ,Channel 1 timeout interrupt disable" "No,Yes"
|
|
bitfld.long 0x00 3. " CH1_UNDERENR ,Channel 1 underrun interrupt disable" "No,Yes"
|
|
bitfld.long 0x00 2. " CH1_OVERENR ,Channel 1 overrun interrupt disable" "No,Yes"
|
|
bitfld.long 0x00 1. " CH1_CRCFAILENR ,Channel 1 CRC fail interrupt disable" "No,Yes"
|
|
bitfld.long 0x00 0. " CH1_CCITEN ,Channel 1 compression complete interrupt disable" "No,Yes"
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "CRC_STATUS,CRC Interrupt Status Register"
|
|
eventfld.long 0x00 12. " CH2_TIMEOUT ,Channel 2 CRC timeout status flag" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 11. " CH2_UNDER ,Channel 2 CRC underrun status flag" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 10. " CH2_OVER ,Channel 2 CRC overrun status flag" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 9. " CH2_CRCFAIL ,Channel 2 CRC compare fail status flag" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 8. " CH2_CCIT ,Channel 2 CRC pattern compression complete status flag" "No interrupt,Interrupt"
|
|
newline
|
|
eventfld.long 0x00 4. " CH1_TIMEOUT ,Channel 1 CRC timeout status flag" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 3. " CH1_UNDER ,Channel 1 CRC underrun status flag" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 2. " CH1_OVER ,Channel 1 CRC overrun status flag" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 1. " CH1_CRCFAIL ,Channel 1 CRC compare fail status flag" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 0. " CH1_CCIT ,Channel 1 CRC pattern compression complete status flag" "No interrupt,Interrupt"
|
|
rgroup.long 0x30++0x03
|
|
line.long 0x00 "CRC_INT_OFFSET_REG,CRC Interrupt Offset Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " OFSTREG ,CRC interrupt offset"
|
|
rgroup.long 0x38++0x03
|
|
line.long 0x00 "CRC_BUSY,CRC Busy Register"
|
|
bitfld.long 0x00 8. " CH2_BUSY ,Channel 2 busy flag" "Not busy,Busy"
|
|
bitfld.long 0x00 0. " CH1_BUSY ,Channel 1 busy flag" "Not busy,Busy"
|
|
tree "CRC Channel 1 Registers"
|
|
group.long 0x40++0x07
|
|
line.long 0x00 "CRC_PCOUNT_REG1,CRC Pattern Counter Preload Register 1"
|
|
hexmask.long.tbyte 0x00 0.--19. 1. " CRC_PAT_COUNT1 ,Channel 1 pattern counter preload"
|
|
line.long 0x04 "CRC_SCOUNT_REG1,CRC Sector Counter Preload Register 1"
|
|
hexmask.long.word 0x04 0.--15. 1. " CRC_SEC_COUNT1 ,Channel 1 sector counter preload"
|
|
hgroup.long (0x40+0x08)++0x03
|
|
hide.long 0x00 "CRC_CURSEC_REG1,CRC Current Sector Register 1"
|
|
in
|
|
group.long (0x40+0x0C)++0x07
|
|
line.long 0x00 "CRC_WDTOPLD1,Watchdog Timeout Preload Register"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " CRC_WDTOPLD1 ,Channel 1 watchdog timeout counter preload"
|
|
line.long 0x04 "CRC_BCTOPLD1,CRC Channel 1 Block Complete Timeout Preload Register"
|
|
hexmask.long.tbyte 0x04 0.--23. 1. " CRC_BCTOPLD1 ,Channel 1 block complete timeout counter preload"
|
|
group.long (0x40+0x20)++0x0F
|
|
line.long 0x00 "PSA_SIGREGL1,Channel 1 PSA Signature Low Register"
|
|
line.long 0x04 "PSA_SIGREGH1,Channel 1 PSA Signature High Register"
|
|
line.long 0x08 "CRC_REGL1,Channel 1 CRC Value Low Register"
|
|
line.long 0x0C "CRC_REGH1,Channel 1 CRC Value High Register"
|
|
rgroup.long (0x40+0x30)++0x0F
|
|
line.long 0x00 "PSA_SECSIGREGL1,PSA Sector Signature Low Register 1"
|
|
line.long 0x04 "PSA_SECSIGREGH1,PSA Sector Signature High Register 1"
|
|
line.long 0x08 "RAW_DATAREGL1,Raw Data Low Register 1"
|
|
line.long 0x0C "RAW_DATAREGH1,Raw Data High Register 1"
|
|
tree.end
|
|
tree "CRC Channel 2 Registers"
|
|
group.long 0x80++0x07
|
|
line.long 0x00 "CRC_PCOUNT_REG2,CRC Pattern Counter Preload Register 2"
|
|
hexmask.long.tbyte 0x00 0.--19. 1. " CRC_PAT_COUNT2 ,Channel 2 pattern counter preload"
|
|
line.long 0x04 "CRC_SCOUNT_REG2,CRC Sector Counter Preload Register 2"
|
|
hexmask.long.word 0x04 0.--15. 1. " CRC_SEC_COUNT2 ,Channel 2 sector counter preload"
|
|
hgroup.long (0x80+0x08)++0x03
|
|
hide.long 0x00 "CRC_CURSEC_REG2,CRC Current Sector Register 2"
|
|
in
|
|
group.long (0x80+0x0C)++0x07
|
|
line.long 0x00 "CRC_WDTOPLD2,Watchdog Timeout Preload Register"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " CRC_WDTOPLD2 ,Channel 2 watchdog timeout counter preload"
|
|
line.long 0x04 "CRC_BCTOPLD2,CRC Channel 2 Block Complete Timeout Preload Register"
|
|
hexmask.long.tbyte 0x04 0.--23. 1. " CRC_BCTOPLD2 ,Channel 2 block complete timeout counter preload"
|
|
group.long (0x80+0x20)++0x0F
|
|
line.long 0x00 "PSA_SIGREGL2,Channel 2 PSA Signature Low Register"
|
|
line.long 0x04 "PSA_SIGREGH2,Channel 2 PSA Signature High Register"
|
|
line.long 0x08 "CRC_REGL2,Channel 2 CRC Value Low Register"
|
|
line.long 0x0C "CRC_REGH2,Channel 2 CRC Value High Register"
|
|
rgroup.long (0x80+0x30)++0x0F
|
|
line.long 0x00 "PSA_SECSIGREGL2,PSA Sector Signature Low Register 2"
|
|
line.long 0x04 "PSA_SECSIGREGH2,PSA Sector Signature High Register 2"
|
|
line.long 0x08 "RAW_DATAREGL2,Raw Data Low Register 2"
|
|
line.long 0x0C "RAW_DATAREGH2,Raw Data High Register 2"
|
|
tree.end
|
|
else
|
|
tree "CRC Channel 1 Registers"
|
|
group.long 0x60++0x07
|
|
line.long 0x00 "PSA_SIGREGL1,Channel 1 PSA Signature Low Register"
|
|
line.long 0x04 "PSA_SIGREGH1,Channel 1 PSA Signature High Register"
|
|
rgroup.long 0x78++0x07
|
|
line.long 0x00 "RAW_DATAREGL1,Raw Data Low Register 1"
|
|
line.long 0x04 "RAW_DATAREGH1,Raw Data High Register 1"
|
|
tree.end
|
|
tree "CRC Channel 2 Registers"
|
|
group.long 0x60++0x07
|
|
line.long 0x00 "PSA_SIGREGL2,Channel 2 PSA Signature Low Register"
|
|
line.long 0x04 "PSA_SIGREGH2,Channel 2 PSA Signature High Register"
|
|
rgroup.long 0x78++0x07
|
|
line.long 0x00 "RAW_DATAREGL2,Raw Data Low Register 2"
|
|
line.long 0x04 "RAW_DATAREGH2,Raw Data High Register 2"
|
|
tree.end
|
|
endif
|
|
newline
|
|
group.long 0x140++0x03
|
|
line.long 0x00 "CRC_TRACE_BUS_SEL, Data Bus Selection Register"
|
|
bitfld.long 0x00 2. " MEN , Enable/disables the tracing of Peripheral Bus Master" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " DTCMEN , Enable/disables the tracing of data TCM" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 0. " ITCMEN , Enable/disables the tracing of instruction TCM" "Disabled,Enabled"
|
|
sif cpuis("TMS570LS0232")||cpuis("TMS570LS0714*")||cpuis("TMS570LS0914*")
|
|
endian.le
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
tree "VIM (Vectored Interrupt Manager Module)"
|
|
base ad:0xFFFFFD00
|
|
sif cpuis("TMS570LS0232")||cpuis("TMS570LS0714*")||cpuis("TMS570LS0914*")
|
|
endian.be
|
|
endif
|
|
width 18.
|
|
base ad:0xFFFFFDEC
|
|
tree "Parity Registers"
|
|
group.long 0x00++0x07
|
|
line.long 0x00 "PARFLG, Interrupt Vector Table Parity Flag Register"
|
|
sif cpuis("TMS570LS0232")||cpuis("TMS570LS0714*")||cpuis("TMS570LS0914*")
|
|
eventfld.long 0x00 0. " PARFLG , Parity error has been found" "No error,Error"
|
|
else
|
|
bitfld.long 0x00 0. " PARFLG , Parity error has been found" "No error,Error"
|
|
endif
|
|
line.long 0x04 "PARCTL, Interrupt Vector Table Parity Control Register"
|
|
bitfld.long 0x04 8. " TEST , This bit maps the parity bits into the Interrupt Vector Table frame to make them accessible by the CPU" "Not mapped,Mapped"
|
|
bitfld.long 0x04 0.--3. " PARENA , VIM parity enable" "Enabled,Enabled,Enabled,Enabled,Enabled,Disabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled"
|
|
rgroup.long 0x08++0x03
|
|
line.long 0x00 "ADDERR, Address Parity Error Register"
|
|
sif cpuis("TMS570LS0232")||cpuis("TMS570LS0714*")||cpuis("TMS570LS0914*")
|
|
hexmask.long.tbyte 0x00 9.--31. 0x02 " IVTO ,Interrupt vector table offset"
|
|
newline
|
|
endif
|
|
hexmask.long.word 0x00 2.--8. 0x04 " ADDERR , Address parity error register"
|
|
bitfld.long 0x00 0.--1. " WORD_OFFSET , Word offset" "0,?..."
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "FBPARERR, Fall-Back Address Parity Error Register"
|
|
tree.end
|
|
base ad:0xFFFFFE00
|
|
tree "VIM Offset Vector Registers"
|
|
rgroup.long 0x00++0x7
|
|
line.long 0x0 "IRQINDEX,IRQ Index Offset Vector Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " IRQINDEX ,IRQ index vector"
|
|
line.long 0x4 "FIQINDEX,FIQ Index Offset Vector Register"
|
|
hexmask.long.byte 0x04 0.--7. 1. " FIQINDEX ,FIQ index offset vector"
|
|
tree.end
|
|
tree "FIQ/IRC Program Control Registers"
|
|
group.long 0x10++0xF
|
|
line.long 0x00 "FIRQPR0,Program Control Register 0"
|
|
bitfld.long 0x00 31. " FIRQPR[31] ,FIQ/IRQ Program control 31" "IRQ,FIQ"
|
|
bitfld.long 0x00 30. " [30] ,FIQ/IRQ Program control 30" "IRQ,FIQ"
|
|
bitfld.long 0x00 29. " [29] ,FIQ/IRQ Program control 29" "IRQ,FIQ"
|
|
bitfld.long 0x00 28. " [28] ,FIQ/IRQ Program control 28" "IRQ,FIQ"
|
|
newline
|
|
bitfld.long 0x00 27. " [27] ,FIQ/IRQ Program control 27" "IRQ,FIQ"
|
|
bitfld.long 0x00 26. " [26] ,FIQ/IRQ Program control 26" "IRQ,FIQ"
|
|
bitfld.long 0x00 25. " [25] ,FIQ/IRQ Program control 25" "IRQ,FIQ"
|
|
bitfld.long 0x00 24. " [24] ,FIQ/IRQ Program control 24" "IRQ,FIQ"
|
|
newline
|
|
bitfld.long 0x00 23. " [23] ,FIQ/IRQ Program control 23" "IRQ,FIQ"
|
|
bitfld.long 0x00 22. " [22] ,FIQ/IRQ Program control 22" "IRQ,FIQ"
|
|
bitfld.long 0x00 21. " [21] ,FIQ/IRQ Program control 21" "IRQ,FIQ"
|
|
bitfld.long 0x00 20. " [20] ,FIQ/IRQ Program control 20" "IRQ,FIQ"
|
|
newline
|
|
bitfld.long 0x00 19. " [19] ,FIQ/IRQ Program control 19" "IRQ,FIQ"
|
|
bitfld.long 0x00 18. " [18] ,FIQ/IRQ Program control 18" "IRQ,FIQ"
|
|
bitfld.long 0x00 17. " [17] ,FIQ/IRQ Program control 17" "IRQ,FIQ"
|
|
bitfld.long 0x00 16. " [16] ,FIQ/IRQ Program control 16" "IRQ,FIQ"
|
|
newline
|
|
bitfld.long 0x00 15. " [15] ,FIQ/IRQ Program control 15" "IRQ,FIQ"
|
|
bitfld.long 0x00 14. " [14] ,FIQ/IRQ Program control 14" "IRQ,FIQ"
|
|
bitfld.long 0x00 13. " [13] ,FIQ/IRQ Program control 13" "IRQ,FIQ"
|
|
bitfld.long 0x00 12. " [12] ,FIQ/IRQ Program control 12" "IRQ,FIQ"
|
|
newline
|
|
bitfld.long 0x00 11. " [11] ,FIQ/IRQ Program control 11" "IRQ,FIQ"
|
|
bitfld.long 0x00 10. " [10] ,FIQ/IRQ Program control 10" "IRQ,FIQ"
|
|
bitfld.long 0x00 9. " [9] ,FIQ/IRQ Program control 9" "IRQ,FIQ"
|
|
bitfld.long 0x00 8. " [8] ,FIQ/IRQ Program control 8" "IRQ,FIQ"
|
|
newline
|
|
bitfld.long 0x00 7. " [7] ,FIQ/IRQ Program control 7" "IRQ,FIQ"
|
|
bitfld.long 0x00 6. " [6] ,FIQ/IRQ Program control 6" "IRQ,FIQ"
|
|
bitfld.long 0x00 5. " [5] ,FIQ/IRQ Program control 5" "IRQ,FIQ"
|
|
bitfld.long 0x00 4. " [4] ,FIQ/IRQ Program control 4" "IRQ,FIQ"
|
|
newline
|
|
bitfld.long 0x00 3. " [3] ,FIQ/IRQ Program control 3" "IRQ,FIQ"
|
|
bitfld.long 0x00 2. " [2] ,FIQ/IRQ Program control 2" "IRQ,FIQ"
|
|
line.long 0x4 "FIRQPR1,Program Control Register 1"
|
|
bitfld.long 0x04 31. " FIRQPR[63] ,FIQ/IRQ Program control 63" "IRQ,FIQ"
|
|
bitfld.long 0x04 30. " [62] ,FIQ/IRQ Program control 62" "IRQ,FIQ"
|
|
bitfld.long 0x04 29. " [61] ,FIQ/IRQ Program control 61" "IRQ,FIQ"
|
|
bitfld.long 0x04 28. " [60] ,FIQ/IRQ Program control 60" "IRQ,FIQ"
|
|
newline
|
|
bitfld.long 0x04 27. " [59] ,FIQ/IRQ (Program control 59" "IRQ,FIQ"
|
|
bitfld.long 0x04 26. " [58] ,FIQ/IRQ Program control 58" "IRQ,FIQ"
|
|
bitfld.long 0x04 25. " [57] ,FIQ/IRQ Program control 57" "IRQ,FIQ"
|
|
bitfld.long 0x04 24. " [56] ,FIQ/IRQ Program control 56" "IRQ,FIQ"
|
|
newline
|
|
bitfld.long 0x04 23. " [55] ,FIQ/IRQ Program control 55" "IRQ,FIQ"
|
|
bitfld.long 0x04 22. " [54] ,FIQ/IRQ Program control 54" "IRQ,FIQ"
|
|
bitfld.long 0x04 21. " [53] ,FIQ/IRQ Program control 53" "IRQ,FIQ"
|
|
bitfld.long 0x04 20. " [52] ,FIQ/IRQ Program control 52" "IRQ,FIQ"
|
|
newline
|
|
bitfld.long 0x04 19. " [51] ,FIQ/IRQ Program control 51" "IRQ,FIQ"
|
|
bitfld.long 0x04 18. " [50] ,FIQ/IRQ Program control 50" "IRQ,FIQ"
|
|
bitfld.long 0x04 17. " [49] ,FIQ/IRQ Program control 49" "IRQ,FIQ"
|
|
bitfld.long 0x04 16. " [48] ,FIQ/IRQ Program control 48" "IRQ,FIQ"
|
|
newline
|
|
bitfld.long 0x04 15. " [47] ,FIQ/IRQ Program control 47" "IRQ,FIQ"
|
|
bitfld.long 0x04 14. " [46] ,FIQ/IRQ Program control 46" "IRQ,FIQ"
|
|
bitfld.long 0x04 13. " [45] ,FIQ/IRQ Program control 45" "IRQ,FIQ"
|
|
bitfld.long 0x04 12. " [44] ,FIQ/IRQ Program control 44" "IRQ,FIQ"
|
|
newline
|
|
bitfld.long 0x04 11. " [43] ,FIQ/IRQ Program control 43" "IRQ,FIQ"
|
|
bitfld.long 0x04 10. " [42] ,FIQ/IRQ Program control 42" "IRQ,FIQ"
|
|
bitfld.long 0x04 9. " [41] ,FIQ/IRQ Program control 41" "IRQ,FIQ"
|
|
bitfld.long 0x04 8. " [40] ,FIQ/IRQ Program control 40" "IRQ,FIQ"
|
|
newline
|
|
bitfld.long 0x04 7. " [39] ,FIQ/IRQ Program control 39" "IRQ,FIQ"
|
|
bitfld.long 0x04 6. " [38] ,FIQ/IRQ Program control 38" "IRQ,FIQ"
|
|
bitfld.long 0x04 5. " [37] ,FIQ/IRQ Program control 37" "IRQ,FIQ"
|
|
bitfld.long 0x04 4. " [36] ,FIQ/IRQ Program control 36" "IRQ,FIQ"
|
|
newline
|
|
bitfld.long 0x04 3. " [35] ,FIQ/IRQ Program control 35" "IRQ,FIQ"
|
|
bitfld.long 0x04 2. " [34] ,FIQ/IRQ Program control 34" "IRQ,FIQ"
|
|
bitfld.long 0x04 1. " [33] ,FIQ/IRQ Program control 33" "IRQ,FIQ"
|
|
bitfld.long 0x04 0. " [32] ,FIQ/IRQ Program control 32" "IRQ,FIQ"
|
|
line.long 0x08 "FIRQPR2,Program Control Register 2"
|
|
bitfld.long 0x08 31. " FIRQPR[95] ,FIQ/IRQ Program control 95" "IRQ,FIQ"
|
|
bitfld.long 0x08 30. " [94] ,FIQ/IRQ Program control 94" "IRQ,FIQ"
|
|
bitfld.long 0x08 29. " [93] ,FIQ/IRQ Program control 93" "IRQ,FIQ"
|
|
bitfld.long 0x08 28. " [92] ,FIQ/IRQ Program control 92" "IRQ,FIQ"
|
|
newline
|
|
bitfld.long 0x08 27. " [91] ,FIQ/IRQ Program control 91" "IRQ,FIQ"
|
|
bitfld.long 0x08 26. " [90] ,FIQ/IRQ Program control 90" "IRQ,FIQ"
|
|
bitfld.long 0x08 25. " [89] ,FIQ/IRQ Program control 89" "IRQ,FIQ"
|
|
bitfld.long 0x08 24. " [88] ,FIQ/IRQ Program control 88" "IRQ,FIQ"
|
|
newline
|
|
bitfld.long 0x08 23. " [87] ,FIQ/IRQ Program control 87" "IRQ,FIQ"
|
|
bitfld.long 0x08 22. " [86] ,FIQ/IRQ Program control 86" "IRQ,FIQ"
|
|
bitfld.long 0x08 21. " [85] ,FIQ/IRQ Program control 85" "IRQ,FIQ"
|
|
newline
|
|
sif cpuis("TMS570LS0232")||cpuis("TMS570LS0714*")||cpuis("TMS570LS0914*")
|
|
bitfld.long 0x08 20. " [84] ,FIQ/IRQ Program control 84" "IRQ,FIQ"
|
|
newline
|
|
endif
|
|
bitfld.long 0x08 19. " [83] ,FIQ/IRQ Program control 83" "IRQ,FIQ"
|
|
bitfld.long 0x08 18. " [82] ,FIQ/IRQ Program control 82" "IRQ,FIQ"
|
|
bitfld.long 0x08 17. " [81] ,FIQ/IRQ Program control 81" "IRQ,FIQ"
|
|
bitfld.long 0x08 16. " [80] ,FIQ/IRQ Program control 80" "IRQ,FIQ"
|
|
newline
|
|
bitfld.long 0x08 15. " [79] ,FIQ/IRQ Program control 79" "IRQ,FIQ"
|
|
bitfld.long 0x08 14. " [78] ,FIQ/IRQ Program control 78" "IRQ,FIQ"
|
|
bitfld.long 0x08 13. " [77] ,FIQ/IRQ Program control 77" "IRQ,FIQ"
|
|
bitfld.long 0x08 12. " [76] ,FIQ/IRQ Program control 76" "IRQ,FIQ"
|
|
newline
|
|
bitfld.long 0x08 11. " [75] ,FIQ/IRQ Program control 75" "IRQ,FIQ"
|
|
bitfld.long 0x08 10. " [74] ,FIQ/IRQ Program control 74" "IRQ,FIQ"
|
|
bitfld.long 0x08 9. " [73] ,FIQ/IRQ Program control 73" "IRQ,FIQ"
|
|
newline
|
|
sif cpuis("TMS570LS0232")||cpuis("TMS570LS0714*")||cpuis("TMS570LS0914*")
|
|
bitfld.long 0x08 8. " [72] ,FIQ/IRQ Program control 72" "IRQ,FIQ"
|
|
bitfld.long 0x08 7. " [71] ,FIQ/IRQ Program control 71" "IRQ,FIQ"
|
|
bitfld.long 0x08 6. " [70] ,FIQ/IRQ Program control 70" "IRQ,FIQ"
|
|
newline
|
|
bitfld.long 0x08 5. " [69] ,FIQ/IRQ Program control 69" "IRQ,FIQ"
|
|
bitfld.long 0x08 4. " [68] ,FIQ/IRQ Program control 68" "IRQ,FIQ"
|
|
bitfld.long 0x08 3. " [67] ,FIQ/IRQ Program control 67" "IRQ,FIQ"
|
|
newline
|
|
endif
|
|
bitfld.long 0x08 2. " [66] ,FIQ/IRQ Program control 66" "IRQ,FIQ"
|
|
bitfld.long 0x08 1. " [65] ,FIQ/IRQ Program control 65" "IRQ,FIQ"
|
|
bitfld.long 0x08 0. " [64] ,FIQ/IRQ Program control 64" "IRQ,FIQ"
|
|
sif cpuis("TMS570LS0714*")||cpuis("TMS570LS0914*")
|
|
line.long 0x0C "FIRQPR3,Program Control Register 3"
|
|
bitfld.long 0x0C 31. " FIRQPR[127] ,FIQ/IRQ Program control 127" "IRQ,FIQ"
|
|
bitfld.long 0x0C 30. " [126] ,FIQ/IRQ Program control 126" "IRQ,FIQ"
|
|
bitfld.long 0x0C 29. " [125] ,FIQ/IRQ Program control 125" "IRQ,FIQ"
|
|
bitfld.long 0x0C 28. " [124] ,FIQ/IRQ Program control 124" "IRQ,FIQ"
|
|
newline
|
|
bitfld.long 0x0C 27. " [123] ,FIQ/IRQ Program control 123" "IRQ,FIQ"
|
|
bitfld.long 0x0C 26. " [122] ,FIQ/IRQ Program control 122" "IRQ,FIQ"
|
|
bitfld.long 0x0C 25. " [121] ,FIQ/IRQ Program control 121" "IRQ,FIQ"
|
|
bitfld.long 0x0C 24. " [120] ,FIQ/IRQ Program control 120" "IRQ,FIQ"
|
|
newline
|
|
bitfld.long 0x0C 23. " [119] ,FIQ/IRQ Program control 119" "IRQ,FIQ"
|
|
bitfld.long 0x0C 22. " [118] ,FIQ/IRQ Program control 118" "IRQ,FIQ"
|
|
bitfld.long 0x0C 21. " [117] ,FIQ/IRQ Program control 117" "IRQ,FIQ"
|
|
bitfld.long 0x0C 20. " [116] ,FIQ/IRQ Program control 116" "IRQ,FIQ"
|
|
newline
|
|
bitfld.long 0x0C 19. " [115] ,FIQ/IRQ Program control 115" "IRQ,FIQ"
|
|
bitfld.long 0x0C 18. " [114] ,FIQ/IRQ Program control 114" "IRQ,FIQ"
|
|
bitfld.long 0x0C 17. " [113] ,FIQ/IRQ Program control 113" "IRQ,FIQ"
|
|
bitfld.long 0x0C 16. " [112] ,FIQ/IRQ Program control 112" "IRQ,FIQ"
|
|
newline
|
|
bitfld.long 0x0C 15. " [111] ,FIQ/IRQ Program control 111" "IRQ,FIQ"
|
|
bitfld.long 0x0C 14. " [110] ,FIQ/IRQ Program control 110" "IRQ,FIQ"
|
|
bitfld.long 0x0C 13. " [109] ,FIQ/IRQ Program control 109" "IRQ,FIQ"
|
|
bitfld.long 0x0C 12. " [108] ,FIQ/IRQ Program control 108" "IRQ,FIQ"
|
|
newline
|
|
bitfld.long 0x0C 11. " [107] ,FIQ/IRQ Program control 107" "IRQ,FIQ"
|
|
bitfld.long 0x0C 10. " [106] ,FIQ/IRQ Program control 106" "IRQ,FIQ"
|
|
bitfld.long 0x0C 9. " [105] ,FIQ/IRQ Program control 105" "IRQ,FIQ"
|
|
bitfld.long 0x0C 8. " [104] ,FIQ/IRQ Program control 104" "IRQ,FIQ"
|
|
newline
|
|
bitfld.long 0x0C 7. " [103] ,FIQ/IRQ Program control 103" "IRQ,FIQ"
|
|
bitfld.long 0x0C 6. " [102] ,FIQ/IRQ Program control 102" "IRQ,FIQ"
|
|
bitfld.long 0x0C 5. " [101] ,FIQ/IRQ Program control 101" "IRQ,FIQ"
|
|
bitfld.long 0x0C 4. " [100] ,FIQ/IRQ Program control 100" "IRQ,FIQ"
|
|
newline
|
|
bitfld.long 0x0C 3. " [99] ,FIQ/IRQ Program control 99" "IRQ,FIQ"
|
|
bitfld.long 0x0C 2. " [98] ,FIQ/IRQ Program control 98" "IRQ,FIQ"
|
|
bitfld.long 0x0C 1. " [97] ,FIQ/IRQ Program control 97" "IRQ,FIQ"
|
|
bitfld.long 0x0C 0. " [96] ,FIQ/IRQ Program control 96" "IRQ,FIQ"
|
|
endif
|
|
tree.end
|
|
tree "VIM Pending Interrupt Read Location Registers"
|
|
group.long 0x20++0x0F
|
|
line.long 0x0 "INTREQ0,Pending Interrupt Read Location 0"
|
|
bitfld.long 0x00 31. " INTREQ[31] ,Interrupt pending 31" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 30. " [30] ,Interrupt pending 30" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 29. " [29] ,Interrupt pending 29" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 28. " [28] ,Interrupt pending 28" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x00 27. " [27] ,Interrupt pending 27" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 26. " [26] ,Interrupt pending 26" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 25. " [25] ,Interrupt pending 25" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 24. " [24] ,Interrupt pending 24" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x00 23. " [23] ,Interrupt pending 23" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 22. " [22] ,Interrupt pending 22" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 21. " [21] ,Interrupt pending 21" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 20. " [20] ,Interrupt pending 20" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x00 19. " [19] ,Interrupt pending 19" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 18. " [18] ,Interrupt pending 18" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 17. " [17] ,Interrupt pending 17" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 16. " [16] ,Interrupt pending 16" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x00 15. " [15] ,Interrupt pending 15" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 14. " [14] ,Interrupt pending 14" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 13. " [13] ,Interrupt pending 13" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 12. " [12] ,Interrupt pending 12" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x00 11. " [11] ,Interrupt pending 11" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 10. " [10] ,Interrupt pending 10" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 9. " [9] ,Interrupt pending 9" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 8. " [8] ,Interrupt pending 8" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x00 7. " [7] ,Interrupt pending 7" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 6. " [6] ,Interrupt pending 6" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 5. " [5] ,Interrupt pending 5" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 4. " [4] ,Interrupt pending 4" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x00 3. " [3] ,Interrupt pending 3" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 2. " [2] ,Interrupt pending 2" "No interrupt,Interrupt"
|
|
newline
|
|
sif cpuis("TMS570LS0232")||cpuis("TMS570LS0714*")||cpuis("TMS570LS0914*")
|
|
bitfld.long 0x00 1. " [1] ,Interrupt pending 1" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 0. " [0] ,Interrupt pending 0" "No interrupt,Interrupt"
|
|
endif
|
|
line.long 0x04 "INTREQ1,Pending Interrupt Read Location 1"
|
|
bitfld.long 0x04 31. " INTREQ[63] ,Interrupt pending 63" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 30. " [62] ,Interrupt pending 62" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 29. " [61] ,Interrupt pending 61" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 28. " [60] ,Interrupt pending 60" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x04 27. " [59] ,Interrupt pending 59" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 26. " [58] ,Interrupt pending 58" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 25. " [57] ,Interrupt pending 57" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 24. " [56] ,Interrupt pending 56" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x04 23. " [55] ,Interrupt pending 55" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 22. " [54] ,Interrupt pending 54" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 21. " [53] ,Interrupt pending 53" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 20. " [52] ,Interrupt pending 52" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x04 19. " [51] ,Interrupt pending 51" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 18. " [50] ,Interrupt pending 50" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 17. " [49] ,Interrupt pending 49" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 16. " [48] ,Interrupt pending 48" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x04 15. " [47] ,Interrupt pending 47" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 14. " [46] ,Interrupt pending 46" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 13. " [45] ,Interrupt pending 45" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 12. " [44] ,Interrupt pending 44" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x04 11. " [43] ,Interrupt pending 43" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 10. " [42] ,Interrupt pending 42" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 9. " [41] ,Interrupt pending 41" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 8. " [40] ,Interrupt pending 40" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x04 7. " [39] ,Interrupt pending 39" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 5. " [37] ,Interrupt pending 37" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 4. " [36] ,Interrupt pending 36" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x04 3. " [35] ,Interrupt pending 35" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 2. " [34] ,Interrupt pending 34" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 1. " [33] ,Interrupt pending 33" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 0. " [32] ,Interrupt pending 32" "No interrupt,Interrupt"
|
|
line.long 0x08 "INTREQ2,Pending Interrupt Read Location 2"
|
|
bitfld.long 0x08 31. " INTREQ[95] ,Interrupt pending 95" "No interrupt,Interrupt"
|
|
bitfld.long 0x08 30. " [94] ,Interrupt pending 94" "No interrupt,Interrupt"
|
|
bitfld.long 0x08 29. " [93] ,Interrupt pending 93" "No interrupt,Interrupt"
|
|
bitfld.long 0x08 28. " [92] ,Interrupt pending 92" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x08 27. " [91] ,Interrupt pending 91" "No interrupt,Interrupt"
|
|
bitfld.long 0x08 26. " [90] ,Interrupt pending 90" "No interrupt,Interrupt"
|
|
bitfld.long 0x08 25. " [89] ,Interrupt pending 89" "No interrupt,Interrupt"
|
|
bitfld.long 0x08 24. " [88] ,Interrupt pending 88" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x08 23. " [87] ,Interrupt pending 87" "No interrupt,Interrupt"
|
|
bitfld.long 0x08 22. " [86] ,Interrupt pending 86" "No interrupt,Interrupt"
|
|
bitfld.long 0x08 21. " [85] ,Interrupt pending 85" "No interrupt,Interrupt"
|
|
newline
|
|
sif cpuis("TMS570LS0232")||cpuis("TMS570LS0714*")||cpuis("TMS570LS0914*")
|
|
bitfld.long 0x08 20. " [84] ,Interrupt pending 84" "No interrupt,Interrupt"
|
|
newline
|
|
endif
|
|
bitfld.long 0x08 19. " [83] ,Interrupt pending 83" "No interrupt,Interrupt"
|
|
bitfld.long 0x08 18. " [82] ,Interrupt pending 82" "No interrupt,Interrupt"
|
|
bitfld.long 0x08 17. " [81] ,Interrupt pending 81" "No interrupt,Interrupt"
|
|
bitfld.long 0x08 16. " [80] ,Interrupt pending 80" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x08 15. " [79] ,Interrupt pending 79" "No interrupt,Interrupt"
|
|
bitfld.long 0x08 14. " [78] ,Interrupt pending 78" "No interrupt,Interrupt"
|
|
bitfld.long 0x08 13. " [77] ,Interrupt pending 77" "No interrupt,Interrupt"
|
|
bitfld.long 0x08 12. " [76] ,Interrupt pending 76" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x08 11. " [75] ,Interrupt pending 75" "No interrupt,Interrupt"
|
|
bitfld.long 0x08 10. " [74] ,Interrupt pending 74" "No interrupt,Interrupt"
|
|
bitfld.long 0x08 9. " [73] ,Interrupt pending 73" "No interrupt,Interrupt"
|
|
newline
|
|
sif cpuis("TMS570LS0232")||cpuis("TMS570LS0714*")||cpuis("TMS570LS0914*")
|
|
bitfld.long 0x08 8. " [72] ,Interrupt pending 72" "No interrupt,Interrupt"
|
|
bitfld.long 0x08 7. " [71] ,Interrupt pending 71" "No interrupt,Interrupt"
|
|
bitfld.long 0x08 6. " [70] ,Interrupt pending 70" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x08 5. " [69] ,Interrupt pending 69" "No interrupt,Interrupt"
|
|
bitfld.long 0x08 4. " [68] ,Interrupt pending 68" "No interrupt,Interrupt"
|
|
bitfld.long 0x08 3. " [67] ,Interrupt pending 67" "No interrupt,Interrupt"
|
|
newline
|
|
endif
|
|
bitfld.long 0x08 2. " [66] ,Interrupt pending 66" "No interrupt,Interrupt"
|
|
bitfld.long 0x08 1. " [65] ,Interrupt pending 65" "No interrupt,Interrupt"
|
|
bitfld.long 0x08 0. " [64] ,Interrupt pending 64" "No interrupt,Interrupt"
|
|
sif cpuis("TMS570LS0714*")||cpuis("TMS570LS0914*")
|
|
line.long 0x0C "INTREQ3,Pending Interrupt Read Location 3"
|
|
bitfld.long 0x0C 31. " INTREQ[127] ,Interrupt pending 127" "No interrupt,Interrupt"
|
|
bitfld.long 0x0C 30. " [126] ,Interrupt pending 126" "No interrupt,Interrupt"
|
|
bitfld.long 0x0C 29. " [125] ,Interrupt pending 125" "No interrupt,Interrupt"
|
|
bitfld.long 0x0C 28. " [124] ,Interrupt pending 124" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x0C 27. " [123] ,Interrupt pending 123" "No interrupt,Interrupt"
|
|
bitfld.long 0x0C 26. " [122] ,Interrupt pending 122" "No interrupt,Interrupt"
|
|
bitfld.long 0x0C 25. " [121] ,Interrupt pending 121" "No interrupt,Interrupt"
|
|
bitfld.long 0x0C 24. " [120] ,Interrupt pending 120" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x0C 23. " [119] ,Interrupt pending 119" "No interrupt,Interrupt"
|
|
bitfld.long 0x0C 22. " [118] ,Interrupt pending 118" "No interrupt,Interrupt"
|
|
bitfld.long 0x0C 21. " [117] ,Interrupt pending 117" "No interrupt,Interrupt"
|
|
bitfld.long 0x0C 20. " [116] ,Interrupt pending 116" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x0C 19. " [115] ,Interrupt pending 115" "No interrupt,Interrupt"
|
|
bitfld.long 0x0C 18. " [114] ,Interrupt pending 114" "No interrupt,Interrupt"
|
|
bitfld.long 0x0C 17. " [113] ,Interrupt pending 113" "No interrupt,Interrupt"
|
|
bitfld.long 0x0C 16. " [112] ,Interrupt pending 112" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x0C 15. " [111] ,Interrupt pending 111" "No interrupt,Interrupt"
|
|
bitfld.long 0x0C 14. " [110] ,Interrupt pending 110" "No interrupt,Interrupt"
|
|
bitfld.long 0x0C 13. " [109] ,Interrupt pending 109" "No interrupt,Interrupt"
|
|
bitfld.long 0x0C 12. " [108] ,Interrupt pending 108" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x0C 11. " [107] ,Interrupt pending 107" "No interrupt,Interrupt"
|
|
bitfld.long 0x0C 10. " [106] ,Interrupt pending 106" "No interrupt,Interrupt"
|
|
bitfld.long 0x0C 9. " [105] ,Interrupt pending 105" "No interrupt,Interrupt"
|
|
bitfld.long 0x0C 8. " [104] ,Interrupt pending 104" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x0C 7. " [103] ,Interrupt pending 103" "No interrupt,Interrupt"
|
|
bitfld.long 0x0C 6. " [102] ,Interrupt pending 102" "No interrupt,Interrupt"
|
|
bitfld.long 0x0C 5. " [101] ,Interrupt pending 101" "No interrupt,Interrupt"
|
|
bitfld.long 0x0C 4. " [100] ,Interrupt pending 100" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x0C 3. " [99] ,Interrupt pending 99" "No interrupt,Interrupt"
|
|
bitfld.long 0x0C 2. " [98] ,Interrupt pending 98" "No interrupt,Interrupt"
|
|
bitfld.long 0x0C 1. " [97] ,Interrupt pending 97" "No interrupt,Interrupt"
|
|
bitfld.long 0x0C 0. " [96] ,Interrupt pending 96" "No interrupt,Interrupt"
|
|
endif
|
|
tree.end
|
|
tree "VIM Interrupt Mask Registers"
|
|
group.long 0x30++0x3
|
|
line.long 0x0 "REQENA0_SET/CLR,Interrupt Mask Set/Clear Register 0"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x10 31. " REQENASET[31] ,Request mask 31" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x10 30. " [30] ,Request mask 30" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x10 29. " [29] ,Request mask 29" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x10 28. " [28] ,Request mask 28" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 27. 0x00 27. 0x10 27. " [27] ,Request mask 27" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x10 26. " [26] ,Request mask 26" "Disabled,Enabled"
|
|
setclrfld.long 0x00 25. 0x00 25. 0x10 25. " [25] ,Request mask 25" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x10 24. " [24] ,Request mask 24" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 23. 0x00 23. 0x10 23. " [23] ,Request mask 23" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x10 22. " [22] ,Request mask 22" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x10 21. " [21] ,Request mask 21" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x10 20. " [20] ,Request mask 20" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 19. 0x00 19. 0x10 19. " [19] ,Request mask 19" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x10 18. " [18] ,Request mask 18" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x10 17. " [17] ,Request mask 17" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x10 16. " [16] ,Request mask 16" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 15. 0x00 15. 0x10 15. " [15] ,Request mask 15" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x10 14. " [14] ,Request mask 14" "Disabled,Enabled"
|
|
setclrfld.long 0x00 13. 0x00 13. 0x10 13. " [13] ,Request mask 13" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x10 12. " [12] ,Request mask 12" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 11. 0x00 11. 0x10 11. " [11] ,Request mask 11" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x10 10. " [10] ,Request mask 10" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x10 9. " [9] ,Request mask 9" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x10 8. " [8] ,Request mask 8" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 7. 0x00 7. 0x10 7. " [7] ,Request mask 7" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x10 6. " [6] ,Request mask 6" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x10 5. " [5] ,Request mask 5" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x10 4. " [4] ,Request mask 4" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 3. 0x00 3. 0x10 3. " [3] ,Request mask 3" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x10 2. " [2] ,Request mask 2" "Disabled,Enabled"
|
|
group.long 0x34++0x3
|
|
line.long 0x0 "REQENA1_SET/CLR,Interrupt Mask Set/Clear Register 1"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x10 31. " REQENASET[63] ,Request Mask 63" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x10 30. " [62] ,Request mask 62" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x10 29. " [61] ,Request mask 61" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x10 28. " [60] ,Request mask 60" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 27. 0x00 27. 0x10 27. " [59] ,Request mask 59" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x10 26. " [58] ,Request mask 58" "Disabled,Enabled"
|
|
setclrfld.long 0x00 25. 0x00 25. 0x10 25. " [57] ,Request mask 57" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x10 24. " [56] ,Request mask 56" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 23. 0x00 23. 0x10 23. " [55] ,Request mask 55" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x10 22. " [54] ,Request mask 54" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x10 21. " [53] ,Request mask 53" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x10 20. " [52] ,Request mask 52" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 19. 0x00 19. 0x10 19. " [51] ,Request mask 51" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x10 18. " [50] ,Request mask 50" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x10 17. " [49] ,Request mask 49" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x10 16. " [48] ,Request mask 48" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 15. 0x00 15. 0x10 15. " [47] ,Request mask 47" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x10 14. " [46] ,Request mask 46" "Disabled,Enabled"
|
|
setclrfld.long 0x00 13. 0x00 13. 0x10 13. " [45] ,Request mask 45" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x10 12. " [44] ,Request mask 44" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 11. 0x00 11. 0x10 11. " [43] ,Request mask 43" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x10 10. " [42] ,Request mask 42" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x10 9. " [41] ,Request mask 41" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x10 8. " [40] ,Request mask 40" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 7. 0x00 7. 0x10 7. " [39] ,Request mask 39" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x10 6. " [38] ,Request mask 38" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x10 5. " [37] ,Request mask 37" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x10 4. " [36] ,Request mask 36" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 3. 0x00 3. 0x10 3. " [35] ,Request mask 35" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x10 2. " [34] ,Request mask 34" "Disabled,Enabled"
|
|
setclrfld.long 0x00 1. 0x00 1. 0x10 1. " [33] ,Request mask 33" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x10 0. " [32] ,Request mask 32" "Disabled,Enabled"
|
|
group.long 0x38++0x3
|
|
line.long 0x0 "REQENA2_SET/CLR,Interrupt Mask Set/Clear Register 2"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x10 31. " REQENASET[95] ,Request mask 95" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x10 30. " [94] ,Request mask 94" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x10 29. " [93] ,Request mask 93" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x10 28. " [92] ,Request mask 92" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 27. 0x00 27. 0x10 27. " [91] ,Request mask 91" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x10 26. " [90] ,Request mask 90" "Disabled,Enabled"
|
|
setclrfld.long 0x00 25. 0x00 25. 0x10 25. " [89] ,Request mask 89" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x10 24. " [88] ,Request mask 88" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 23. 0x00 23. 0x10 23. " [87] ,Request mask 87" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x10 22. " [86] ,Request mask 86" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x10 21. " [85] ,Request mask 85" "Disabled,Enabled"
|
|
newline
|
|
sif cpuis("TMS570LS0232")||cpuis("TMS570LS0714*")||cpuis("TMS570LS0914*")
|
|
setclrfld.long 0x00 20. 0x00 20. 0x10 20. " [84] ,Request Mask 84" "Disabled,Enabled"
|
|
newline
|
|
endif
|
|
setclrfld.long 0x00 19. 0x00 19. 0x10 19. " [83] ,Request mask 83" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x10 18. " [82] ,Request mask 82" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x10 17. " [81] ,Request mask 81" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x10 16. " [80] ,Request mask 80" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 15. 0x00 15. 0x10 15. " [79] ,Request mask 79" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x10 14. " [78] ,Request mask 78" "Disabled,Enabled"
|
|
setclrfld.long 0x00 13. 0x00 13. 0x10 13. " [77] ,Request mask 77" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x10 12. " [76] ,Request mask 76" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 11. 0x00 11. 0x10 11. " [75] ,Request mask 75" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x10 10. " [74] ,Request mask 74" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x10 9. " [73] ,Request Mask 73" "Disabled,Enabled"
|
|
newline
|
|
sif cpuis("TMS570LS0232")||cpuis("TMS570LS0714*")||cpuis("TMS570LS0914*")
|
|
setclrfld.long 0x00 8. 0x00 8. 0x10 8. " [72] ,Request mask 72" "Disabled,Enabled"
|
|
setclrfld.long 0x00 7. 0x00 7. 0x10 7. " [71] ,Request mask 71" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x10 6. " [70] ,Request mask 70" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 5. 0x00 5. 0x10 5. " [69] ,Request mask 69" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x10 4. " [68] ,Request mask 68" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x10 3. " [67] ,Request mask 67" "Disabled,Enabled"
|
|
newline
|
|
endif
|
|
setclrfld.long 0x00 2. 0x00 2. 0x10 2. " [66] ,Request mask 66" "Disabled,Enabled"
|
|
setclrfld.long 0x00 1. 0x00 1. 0x10 1. " [65] ,Request mask 65" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x10 0. " [64] ,Request mask 64" "Disabled,Enabled"
|
|
sif cpuis("TMS570LS0714*")||cpuis("TMS570LS0914*")
|
|
group.long 0x3C++0x03
|
|
line.long 0x00 "REQENA3_SET/CLR,Interrupt Mask Set/Clear Register 3"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x10 31. " REQENASET[127] ,Request mask 127" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x10 30. " [126] ,Request mask 126" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x10 29. " [125] ,Request mask 125" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x10 28. " [124] ,Request mask 124" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 27. 0x00 27. 0x10 27. " [123] ,Request mask 123" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x10 26. " [122] ,Request mask 122" "Disabled,Enabled"
|
|
setclrfld.long 0x00 25. 0x00 25. 0x10 25. " [121] ,Request mask 121" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x10 24. " [120] ,Request mask 120" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 23. 0x00 23. 0x10 23. " [119] ,Request mask 119" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x10 22. " [118] ,Request mask 118" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x10 21. " [117] ,Request mask 117" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x10 20. " [116] ,Request mask 116" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 19. 0x00 19. 0x10 19. " [115] ,Request mask 115" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x10 18. " [114] ,Request mask 114" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x10 17. " [113] ,Request mask 113" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x10 16. " [112] ,Request mask 112" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 15. 0x00 15. 0x10 15. " [111] ,Request mask 111" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x10 14. " [110] ,Request mask 110" "Disabled,Enabled"
|
|
setclrfld.long 0x00 13. 0x00 13. 0x10 13. " [109] ,Request mask 109" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x10 12. " [108] ,Request mask 108" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 11. 0x00 11. 0x10 11. " [107] ,Request mask 107" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x10 10. " [106] ,Request mask 106" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x10 9. " [105] ,Request mask 105" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x10 8. " [104] ,Request mask 104" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 7. 0x00 7. 0x10 7. " [103] ,Request mask 103" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x10 6. " [102] ,Request mask 102" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x10 5. " [101] ,Request mask 101" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x10 4. " [100] ,Request mask 100" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 3. 0x00 3. 0x10 3. " [99] ,Request mask 99" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x10 2. " [98] ,Request mask 98" "Disabled,Enabled"
|
|
setclrfld.long 0x00 1. 0x00 1. 0x10 1. " [97] ,Request mask 97" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x10 0. " [96] ,Request mask 96" "Disabled,Enabled"
|
|
endif
|
|
tree.end
|
|
tree "VIM Wake Up Mask Registers"
|
|
group.long 0x50++0x3
|
|
line.long 0x0 "WAKEENA0_SET/CLR,Wake-up Mask Set/Clear Register 0"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x10 31. " WAKEMASK[31] ,Wake up mask 31" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x10 30. " [30] ,Wake up mask 30" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x10 29. " [29] ,Wake up mask 29" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x10 28. " [28] ,Wake up mask 28" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 27. 0x00 27. 0x10 27. " [27] ,Wake up mask 27" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x10 26. " [26] ,Wake up mask 26" "Disabled,Enabled"
|
|
setclrfld.long 0x00 25. 0x00 25. 0x10 25. " [25] ,Wake up mask 25" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x10 24. " [24] ,Wake up mask 24" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 23. 0x00 23. 0x10 23. " [23] ,Wake up mask 23" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x10 22. " [22] ,Wake up mask 22" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x10 21. " [21] ,Wake up mask 21" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x10 20. " [20] ,Wake up mask 20" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 19. 0x00 19. 0x10 19. " [19] ,Wake up mask 19" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x10 18. " [18] ,Wake up mask 18" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x10 17. " [17] ,Wake up mask 17" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x10 16. " [16] ,Wake up mask 16" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 15. 0x00 15. 0x10 15. " [15] ,Wake up mask 15" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x10 14. " [14] ,Wake up mask 14" "Disabled,Enabled"
|
|
setclrfld.long 0x00 13. 0x00 13. 0x10 13. " [13] ,Wake up mask 13" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x10 12. " [12] ,Wake up mask 12" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 11. 0x00 11. 0x10 11. " [11] ,Wake up mask 11" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x10 10. " [10] ,Wake up mask 10" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x10 9. " [9] ,Wake up mask 9" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x10 8. " [8] ,Wake up mask 8" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 7. 0x00 7. 0x10 7. " [7] ,Wake up mask 7" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x10 6. " [6] ,Wake up mask 6" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x10 5. " [5] ,Wake up mask 5" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x10 4. " [4] ,Wake up mask 4" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 3. 0x00 3. 0x10 3. " [3] ,Wake up mask 3" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x10 2. " [2] ,Wake up mask 2" "Disabled,Enabled"
|
|
setclrfld.long 0x00 1. 0x00 1. 0x10 1. " [1] ,Wake up mask 1" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x10 0. " [0] ,Wake up mask 0" "Disabled,Enabled"
|
|
group.long 0x54++0x3
|
|
line.long 0x0 "WAKEENA1_SET/CLR,Wake-up Mask Set/Clear Register 1"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x10 31. " WAKEMASK[63] ,Wake up mask 63" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x10 30. " [62] ,Wake up mask 62" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x10 29. " [61] ,Wake up mask 61" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x10 28. " [60] ,Wake up mask 60" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 27. 0x00 27. 0x10 27. " [59] ,Wake up mask 59" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x10 26. " [58] ,Wake up mask 58" "Disabled,Enabled"
|
|
setclrfld.long 0x00 25. 0x00 25. 0x10 25. " [57] ,Wake up mask 57" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x10 24. " [56] ,Wake up mask 56" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 23. 0x00 23. 0x10 23. " [55] ,Wake up mask 55" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x10 22. " [54] ,Wake up mask 54" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x10 21. " [53] ,Wake up mask 53" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x10 20. " [52] ,Wake up mask 52" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 19. 0x00 19. 0x10 19. " [51] ,Wake up mask 51" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x10 18. " [50] ,Wake up mask 50" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x10 17. " [49] ,Wake up mask 49" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x10 16. " [48] ,Wake up mask 48" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 15. 0x00 15. 0x10 15. " [47] ,Wake up mask 47" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x10 14. " [46] ,Wake up mask 46" "Disabled,Enabled"
|
|
setclrfld.long 0x00 13. 0x00 13. 0x10 13. " [45] ,Wake up mask 45" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x10 12. " [44] ,Wake up mask 44" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 11. 0x00 11. 0x10 11. " [43] ,Wake up mask 43" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x10 10. " [42] ,Wake up mask 42" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x10 9. " [41] ,Wake up mask 41" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x10 8. " [40] ,Wake up mask 40" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 7. 0x00 7. 0x10 7. " [39] ,Wake up mask 39" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x10 6. " [38] ,Wake up mask 38" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x10 5. " [37] ,Wake up mask 37" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x10 4. " [36] ,Wake up mask 36" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 3. 0x00 3. 0x10 3. " [35] ,Wake up mask 35" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x10 2. " [34] ,Wake up mask 34" "Disabled,Enabled"
|
|
setclrfld.long 0x00 1. 0x00 1. 0x10 1. " [33] ,Wake up mask 33" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x10 0. " [32] ,Wake up mask 32" "Disabled,Enabled"
|
|
group.long 0x58++0x03
|
|
line.long 0x0 "WAKEENA2_SET/CLR,Wake-up Mask Set/Clear Register 2"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x10 31. " WAKEMASK[95] ,Wake up mask 95" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x10 30. " [94] ,Wake up mask 94" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x10 29. " [93] ,Wake up mask 93" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x10 28. " [92] ,Wake up mask 92" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 27. 0x00 27. 0x10 27. " [91] ,Wake up mask 91" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x10 26. " [90] ,Wake up mask 90" "Disabled,Enabled"
|
|
setclrfld.long 0x00 25. 0x00 25. 0x10 25. " [89] ,Wake up mask 89" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x10 24. " [88] ,Wake up mask 88" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 23. 0x00 23. 0x10 23. " [87] ,Wake up mask 87" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x10 22. " [86] ,Wake up mask 86" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x10 21. " [85] ,Wake up mask 85" "Disabled,Enabled"
|
|
newline
|
|
sif cpuis("TMS570LS0232")||cpuis("TMS570LS0714*")||cpuis("TMS570LS0914*")
|
|
setclrfld.long 0x00 20. 0x00 20. 0x10 20. " [84] ,Request Mask 84" "Disabled,Enabled"
|
|
newline
|
|
endif
|
|
setclrfld.long 0x00 19. 0x00 19. 0x10 19. " [83] ,Wake up mask 83" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x10 18. " [82] ,Wake up mask 82" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x10 17. " [81] ,Wake up mask 81" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x10 16. " [80] ,Wake up mask 80" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 15. 0x00 15. 0x10 15. " [79] ,Wake up mask 79" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x10 14. " [78] ,Wake up mask 78" "Disabled,Enabled"
|
|
setclrfld.long 0x00 13. 0x00 13. 0x10 13. " [77] ,Wake up mask 77" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x10 12. " [76] ,Wake up mask 76" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 11. 0x00 11. 0x10 11. " [75] ,Wake up mask 75" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x10 10. " [74] ,Wake up mask 74" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x10 9. " [73] ,Wake up mask 73" "Disabled,Enabled"
|
|
newline
|
|
sif cpuis("TMS570LS0232")||cpuis("TMS570LS0714*")||cpuis("TMS570LS0914*")
|
|
setclrfld.long 0x00 8. 0x00 8. 0x10 8. " [72] ,Wake up mask 72" "Disabled,Enabled"
|
|
setclrfld.long 0x00 7. 0x00 7. 0x10 7. " [71] ,Wake up mask 71" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x10 6. " [70] ,Wake up mask 70" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 5. 0x00 5. 0x10 5. " [69] ,Wake up mask 69" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x10 4. " [68] ,Wake up mask 68" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x10 3. " [67] ,Wake up mask 67" "Disabled,Enabled"
|
|
newline
|
|
endif
|
|
setclrfld.long 0x00 2. 0x00 2. 0x10 2. " [66] ,Wake up mask 66" "Disabled,Enabled"
|
|
setclrfld.long 0x00 1. 0x00 1. 0x10 1. " [65] ,Wake up mask 65" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x10 0. " [64] ,Wake up mask 64" "Disabled,Enabled"
|
|
sif cpuis("TMS570LS0714*")||cpuis("TMS570LS0914*")
|
|
group.long 0x5C++0x3
|
|
line.long 0x00 "WAKEENA3_SET/CLR,Wake-up Mask Set/Clear Register 3"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x10 31. " WAKEMASK[127] ,Wake up mask 127" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x10 30. " [126] ,Wake up mask 126" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x10 29. " [125] ,Wake up mask 125" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x10 28. " [124] ,Wake up mask 124" "No interrupt,Interrupt"
|
|
newline
|
|
setclrfld.long 0x00 27. 0x00 27. 0x10 27. " [123] ,Wake up mask 123" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x10 26. " [122] ,Wake up mask 122" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 25. 0x00 25. 0x10 25. " [121] ,Wake up mask 121" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x10 24. " [120] ,Wake up mask 120" "No interrupt,Interrupt"
|
|
newline
|
|
setclrfld.long 0x00 23. 0x00 23. 0x10 23. " [119] ,Wake up mask 119" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x10 22. " [118] ,Wake up mask 118" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x10 21. " [117] ,Wake up mask 117" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x10 20. " [116] ,Wake up mask 116" "No interrupt,Interrupt"
|
|
newline
|
|
setclrfld.long 0x00 19. 0x00 19. 0x10 19. " [115] ,Wake up mask 115" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x10 18. " [114] ,Wake up mask 114" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x10 17. " [113] ,Wake up mask 113" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x10 16. " [112] ,Wake up mask 112" "No interrupt,Interrupt"
|
|
newline
|
|
setclrfld.long 0x00 15. 0x00 15. 0x10 15. " [111] ,Wake up mask 111" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x10 14. " [110] ,Wake up mask 110" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 13. 0x00 13. 0x10 13. " [109] ,Wake up mask 109" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x10 12. " [108] ,Wake up mask 108" "No interrupt,Interrupt"
|
|
newline
|
|
setclrfld.long 0x00 11. 0x00 11. 0x10 11. " [107] ,Wake up mask 107" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x10 10. " [106] ,Wake up mask 106" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x10 9. " [105] ,Wake up mask 105" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x10 8. " [104] ,Wake up mask 104" "No interrupt,Interrupt"
|
|
newline
|
|
setclrfld.long 0x00 7. 0x00 7. 0x10 7. " [103] ,Wake up mask 103" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x10 6. " [102] ,Wake up mask 102" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x10 5. " [101] ,Wake up mask 101" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x10 4. " [100] ,Wake up mask 100" "No interrupt,Interrupt"
|
|
newline
|
|
setclrfld.long 0x00 3. 0x00 3. 0x10 3. " [99] ,Wake up mask 99" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x10 2. " [98] ,Wake up mask 98" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 1. 0x00 1. 0x10 1. " [97] ,Wake up mask 97" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x10 0. " [96] ,Wake up mask 96" "No interrupt,Interrupt"
|
|
endif
|
|
tree.end
|
|
width 0x11
|
|
tree "VIM Interrupt Vector and VIM Event Registers"
|
|
rgroup.long 0x70++0x7
|
|
line.long 0x00 "IRQVECREG,IRQ Interrupt Vector Register"
|
|
line.long 0x04 "FIQVECREG,FIQ Interrupt Vector Register"
|
|
group.long 0x78++0x3
|
|
line.long 0x0 "CAPEVT,Capture Event register"
|
|
hexmask.long.byte 0x00 16.--22. 1. " CAPEVTSRC1 ,Capture Event Source 1 Mapping Control"
|
|
hexmask.long.byte 0x00 0.--6. 1. " CAPEVTSRC0 ,Capture Event Source 0 Mapping Control"
|
|
tree.end
|
|
tree "VIM Interrupt Control Registers"
|
|
group.long 0x80++0x03
|
|
line.long 0x00 "CHANCTRL0,VIM Interrupt Control Register 0"
|
|
hexmask.long.byte 0x00 24.--30. 1. " CHANMAP0 ,Interrupt CHAN0 Mapping Control"
|
|
hexmask.long.byte 0x00 16.--22. 1. " CHANMAP1 ,Interrupt CHAN1 Mapping Control"
|
|
hexmask.long.byte 0x00 8.--14. 1. " CHANMAP2 ,Interrupt CHAN2 Mapping Control"
|
|
hexmask.long.byte 0x00 0.--6. 1. " CHANMAP3 ,Interrupt CHAN3 Mapping Control"
|
|
group.long 0x84++0x03
|
|
line.long 0x00 "CHANCTRL1,VIM Interrupt Control Register 1"
|
|
hexmask.long.byte 0x00 24.--30. 1. " CHANMAP4 ,Interrupt CHAN4 Mapping Control"
|
|
hexmask.long.byte 0x00 16.--22. 1. " CHANMAP5 ,Interrupt CHAN5 Mapping Control"
|
|
hexmask.long.byte 0x00 8.--14. 1. " CHANMAP6 ,Interrupt CHAN6 Mapping Control"
|
|
hexmask.long.byte 0x00 0.--6. 1. " CHANMAP7 ,Interrupt CHAN7 Mapping Control"
|
|
group.long 0x88++0x03
|
|
line.long 0x00 "CHANCTRL2,VIM Interrupt Control Register 2"
|
|
hexmask.long.byte 0x00 24.--30. 1. " CHANMAP8 ,Interrupt CHAN8 Mapping Control"
|
|
hexmask.long.byte 0x00 16.--22. 1. " CHANMAP9 ,Interrupt CHAN9 Mapping Control"
|
|
hexmask.long.byte 0x00 8.--14. 1. " CHANMAP10 ,Interrupt CHAN10 Mapping Control"
|
|
hexmask.long.byte 0x00 0.--6. 1. " CHANMAP11 ,Interrupt CHAN11 Mapping Control"
|
|
group.long 0x8C++0x03
|
|
line.long 0x00 "CHANCTRL3,VIM Interrupt Control Register 3"
|
|
hexmask.long.byte 0x00 24.--30. 1. " CHANMAP12 ,Interrupt CHAN12 Mapping Control"
|
|
hexmask.long.byte 0x00 16.--22. 1. " CHANMAP13 ,Interrupt CHAN13 Mapping Control"
|
|
hexmask.long.byte 0x00 8.--14. 1. " CHANMAP14 ,Interrupt CHAN14 Mapping Control"
|
|
hexmask.long.byte 0x00 0.--6. 1. " CHANMAP15 ,Interrupt CHAN15 Mapping Control"
|
|
group.long 0x90++0x03
|
|
line.long 0x00 "CHANCTRL4,VIM Interrupt Control Register 4"
|
|
hexmask.long.byte 0x00 24.--30. 1. " CHANMAP16 ,Interrupt CHAN16 Mapping Control"
|
|
hexmask.long.byte 0x00 16.--22. 1. " CHANMAP17 ,Interrupt CHAN17 Mapping Control"
|
|
hexmask.long.byte 0x00 8.--14. 1. " CHANMAP18 ,Interrupt CHAN18 Mapping Control"
|
|
hexmask.long.byte 0x00 0.--6. 1. " CHANMAP19 ,Interrupt CHAN19 Mapping Control"
|
|
group.long 0x94++0x03
|
|
line.long 0x00 "CHANCTRL5,VIM Interrupt Control Register 5"
|
|
hexmask.long.byte 0x00 24.--30. 1. " CHANMAP20 ,Interrupt CHAN20 Mapping Control"
|
|
hexmask.long.byte 0x00 16.--22. 1. " CHANMAP21 ,Interrupt CHAN21 Mapping Control"
|
|
hexmask.long.byte 0x00 8.--14. 1. " CHANMAP22 ,Interrupt CHAN22 Mapping Control"
|
|
hexmask.long.byte 0x00 0.--6. 1. " CHANMAP23 ,Interrupt CHAN23 Mapping Control"
|
|
group.long 0x98++0x03
|
|
line.long 0x00 "CHANCTRL6,VIM Interrupt Control Register 6"
|
|
hexmask.long.byte 0x00 24.--30. 1. " CHANMAP24 ,Interrupt CHAN24 Mapping Control"
|
|
hexmask.long.byte 0x00 16.--22. 1. " CHANMAP25 ,Interrupt CHAN25 Mapping Control"
|
|
hexmask.long.byte 0x00 8.--14. 1. " CHANMAP26 ,Interrupt CHAN26 Mapping Control"
|
|
hexmask.long.byte 0x00 0.--6. 1. " CHANMAP27 ,Interrupt CHAN27 Mapping Control"
|
|
group.long 0x9C++0x03
|
|
line.long 0x00 "CHANCTRL7,VIM Interrupt Control Register 7"
|
|
hexmask.long.byte 0x00 24.--30. 1. " CHANMAP28 ,Interrupt CHAN28 Mapping Control"
|
|
hexmask.long.byte 0x00 16.--22. 1. " CHANMAP29 ,Interrupt CHAN29 Mapping Control"
|
|
hexmask.long.byte 0x00 8.--14. 1. " CHANMAP30 ,Interrupt CHAN30 Mapping Control"
|
|
hexmask.long.byte 0x00 0.--6. 1. " CHANMAP31 ,Interrupt CHAN31 Mapping Control"
|
|
group.long 0xA0++0x03
|
|
line.long 0x00 "CHANCTRL8,VIM Interrupt Control Register 8"
|
|
hexmask.long.byte 0x00 24.--30. 1. " CHANMAP32 ,Interrupt CHAN32 Mapping Control"
|
|
hexmask.long.byte 0x00 16.--22. 1. " CHANMAP33 ,Interrupt CHAN33 Mapping Control"
|
|
hexmask.long.byte 0x00 8.--14. 1. " CHANMAP34 ,Interrupt CHAN34 Mapping Control"
|
|
hexmask.long.byte 0x00 0.--6. 1. " CHANMAP35 ,Interrupt CHAN35 Mapping Control"
|
|
group.long 0xA4++0x03
|
|
line.long 0x00 "CHANCTRL9,VIM Interrupt Control Register 9"
|
|
hexmask.long.byte 0x00 24.--30. 1. " CHANMAP36 ,Interrupt CHAN36 Mapping Control"
|
|
hexmask.long.byte 0x00 16.--22. 1. " CHANMAP37 ,Interrupt CHAN37 Mapping Control"
|
|
hexmask.long.byte 0x00 8.--14. 1. " CHANMAP38 ,Interrupt CHAN38 Mapping Control"
|
|
hexmask.long.byte 0x00 0.--6. 1. " CHANMAP39 ,Interrupt CHAN39 Mapping Control"
|
|
group.long 0xA8++0x03
|
|
line.long 0x00 "CHANCTRL10,VIM Interrupt Control Register 10"
|
|
hexmask.long.byte 0x00 24.--30. 1. " CHANMAP40 ,Interrupt CHAN40 Mapping Control"
|
|
hexmask.long.byte 0x00 16.--22. 1. " CHANMAP41 ,Interrupt CHAN41 Mapping Control"
|
|
hexmask.long.byte 0x00 8.--14. 1. " CHANMAP42 ,Interrupt CHAN42 Mapping Control"
|
|
hexmask.long.byte 0x00 0.--6. 1. " CHANMAP43 ,Interrupt CHAN43 Mapping Control"
|
|
group.long 0xAC++0x03
|
|
line.long 0x00 "CHANCTRL11,VIM Interrupt Control Register 11"
|
|
hexmask.long.byte 0x00 24.--30. 1. " CHANMAP44 ,Interrupt CHAN44 Mapping Control"
|
|
hexmask.long.byte 0x00 16.--22. 1. " CHANMAP45 ,Interrupt CHAN45 Mapping Control"
|
|
hexmask.long.byte 0x00 8.--14. 1. " CHANMAP46 ,Interrupt CHAN46 Mapping Control"
|
|
hexmask.long.byte 0x00 0.--6. 1. " CHANMAP47 ,Interrupt CHAN47 Mapping Control"
|
|
group.long 0xB0++0x03
|
|
line.long 0x00 "CHANCTRL12,VIM Interrupt Control Register 12"
|
|
hexmask.long.byte 0x00 24.--30. 1. " CHANMAP48 ,Interrupt CHAN48 Mapping Control"
|
|
hexmask.long.byte 0x00 16.--22. 1. " CHANMAP49 ,Interrupt CHAN49 Mapping Control"
|
|
hexmask.long.byte 0x00 8.--14. 1. " CHANMAP50 ,Interrupt CHAN50 Mapping Control"
|
|
hexmask.long.byte 0x00 0.--6. 1. " CHANMAP51 ,Interrupt CHAN51 Mapping Control"
|
|
group.long 0xB4++0x03
|
|
line.long 0x00 "CHANCTRL13,VIM Interrupt Control Register 13"
|
|
hexmask.long.byte 0x00 24.--30. 1. " CHANMAP52 ,Interrupt CHAN52 Mapping Control"
|
|
hexmask.long.byte 0x00 16.--22. 1. " CHANMAP53 ,Interrupt CHAN53 Mapping Control"
|
|
hexmask.long.byte 0x00 8.--14. 1. " CHANMAP54 ,Interrupt CHAN54 Mapping Control"
|
|
hexmask.long.byte 0x00 0.--6. 1. " CHANMAP55 ,Interrupt CHAN55 Mapping Control"
|
|
group.long 0xB8++0x03
|
|
line.long 0x00 "CHANCTRL14,VIM Interrupt Control Register 14"
|
|
hexmask.long.byte 0x00 24.--30. 1. " CHANMAP56 ,Interrupt CHAN56 Mapping Control"
|
|
hexmask.long.byte 0x00 16.--22. 1. " CHANMAP57 ,Interrupt CHAN57 Mapping Control"
|
|
hexmask.long.byte 0x00 8.--14. 1. " CHANMAP58 ,Interrupt CHAN58 Mapping Control"
|
|
hexmask.long.byte 0x00 0.--6. 1. " CHANMAP59 ,Interrupt CHAN59 Mapping Control"
|
|
group.long 0xBC++0x03
|
|
line.long 0x00 "CHANCTRL15,VIM Interrupt Control Register 15"
|
|
hexmask.long.byte 0x00 24.--30. 1. " CHANMAP60 ,Interrupt CHAN60 Mapping Control"
|
|
hexmask.long.byte 0x00 16.--22. 1. " CHANMAP61 ,Interrupt CHAN61 Mapping Control"
|
|
hexmask.long.byte 0x00 8.--14. 1. " CHANMAP62 ,Interrupt CHAN62 Mapping Control"
|
|
hexmask.long.byte 0x00 0.--6. 1. " CHANMAP63 ,Interrupt CHAN63 Mapping Control"
|
|
group.long 0xC0++0x03
|
|
line.long 0x00 "CHANCTRL16,VIM Interrupt Control Register 16"
|
|
hexmask.long.byte 0x00 24.--30. 1. " CHANMAP64 ,Interrupt CHAN64 Mapping Control"
|
|
hexmask.long.byte 0x00 16.--22. 1. " CHANMAP65 ,Interrupt CHAN65 Mapping Control"
|
|
hexmask.long.byte 0x00 8.--14. 1. " CHANMAP66 ,Interrupt CHAN66 Mapping Control"
|
|
hexmask.long.byte 0x00 0.--6. 1. " CHANMAP67 ,Interrupt CHAN67 Mapping Control"
|
|
group.long 0xC4++0x03
|
|
line.long 0x00 "CHANCTRL17,VIM Interrupt Control Register 17"
|
|
hexmask.long.byte 0x00 24.--30. 1. " CHANMAP68 ,Interrupt CHAN68 Mapping Control"
|
|
hexmask.long.byte 0x00 16.--22. 1. " CHANMAP69 ,Interrupt CHAN69 Mapping Control"
|
|
hexmask.long.byte 0x00 8.--14. 1. " CHANMAP70 ,Interrupt CHAN70 Mapping Control"
|
|
hexmask.long.byte 0x00 0.--6. 1. " CHANMAP71 ,Interrupt CHAN71 Mapping Control"
|
|
group.long 0xC8++0x03
|
|
line.long 0x00 "CHANCTRL18,VIM Interrupt Control Register 18"
|
|
hexmask.long.byte 0x00 24.--30. 1. " CHANMAP72 ,Interrupt CHAN72 Mapping Control"
|
|
hexmask.long.byte 0x00 16.--22. 1. " CHANMAP73 ,Interrupt CHAN73 Mapping Control"
|
|
hexmask.long.byte 0x00 8.--14. 1. " CHANMAP74 ,Interrupt CHAN74 Mapping Control"
|
|
hexmask.long.byte 0x00 0.--6. 1. " CHANMAP75 ,Interrupt CHAN75 Mapping Control"
|
|
group.long 0xCC++0x03
|
|
line.long 0x00 "CHANCTRL19,VIM Interrupt Control Register 19"
|
|
hexmask.long.byte 0x00 24.--30. 1. " CHANMAP76 ,Interrupt CHAN76 Mapping Control"
|
|
hexmask.long.byte 0x00 16.--22. 1. " CHANMAP77 ,Interrupt CHAN77 Mapping Control"
|
|
hexmask.long.byte 0x00 8.--14. 1. " CHANMAP78 ,Interrupt CHAN78 Mapping Control"
|
|
hexmask.long.byte 0x00 0.--6. 1. " CHANMAP79 ,Interrupt CHAN79 Mapping Control"
|
|
group.long 0xD0++0x03
|
|
line.long 0x00 "CHANCTRL20,VIM Interrupt Control Register 20"
|
|
hexmask.long.byte 0x00 24.--30. 1. " CHANMAP80 ,Interrupt CHAN80 Mapping Control"
|
|
hexmask.long.byte 0x00 16.--22. 1. " CHANMAP81 ,Interrupt CHAN81 Mapping Control"
|
|
hexmask.long.byte 0x00 8.--14. 1. " CHANMAP82 ,Interrupt CHAN82 Mapping Control"
|
|
hexmask.long.byte 0x00 0.--6. 1. " CHANMAP83 ,Interrupt CHAN83 Mapping Control"
|
|
group.long 0xD4++0x03
|
|
line.long 0x00 "CHANCTRL21,VIM Interrupt Control Register 21"
|
|
hexmask.long.byte 0x00 24.--30. 1. " CHANMAP84 ,Interrupt CHAN84 Mapping Control"
|
|
hexmask.long.byte 0x00 16.--22. 1. " CHANMAP85 ,Interrupt CHAN85 Mapping Control"
|
|
hexmask.long.byte 0x00 8.--14. 1. " CHANMAP86 ,Interrupt CHAN86 Mapping Control"
|
|
hexmask.long.byte 0x00 0.--6. 1. " CHANMAP87 ,Interrupt CHAN87 Mapping Control"
|
|
group.long 0xD8++0x03
|
|
line.long 0x00 "CHANCTRL22,VIM Interrupt Control Register 22"
|
|
hexmask.long.byte 0x00 24.--30. 1. " CHANMAP88 ,Interrupt CHAN88 Mapping Control"
|
|
hexmask.long.byte 0x00 16.--22. 1. " CHANMAP89 ,Interrupt CHAN89 Mapping Control"
|
|
hexmask.long.byte 0x00 8.--14. 1. " CHANMAP90 ,Interrupt CHAN90 Mapping Control"
|
|
hexmask.long.byte 0x00 0.--6. 1. " CHANMAP91 ,Interrupt CHAN91 Mapping Control"
|
|
group.long 0xDC++0x03
|
|
line.long 0x00 "CHANCTRL23,VIM Interrupt Control Register 23"
|
|
hexmask.long.byte 0x00 24.--30. 1. " CHANMAP92 ,Interrupt CHAN92 Mapping Control"
|
|
hexmask.long.byte 0x00 16.--22. 1. " CHANMAP93 ,Interrupt CHAN93 Mapping Control"
|
|
hexmask.long.byte 0x00 8.--14. 1. " CHANMAP94 ,Interrupt CHAN94 Mapping Control"
|
|
hexmask.long.byte 0x00 0.--6. 1. " CHANMAP95 ,Interrupt CHAN95 Mapping Control"
|
|
sif cpuis("TMS570LS0714*")||cpuis("TMS570LS0914*")
|
|
group.long 0xE0++0x03
|
|
line.long 0x00 "CHANCTRL24,VIM Interrupt Control Register 24"
|
|
hexmask.long.byte 0x00 24.--30. 1. " CHANMAP96 ,Interrupt CHAN96 Mapping Control"
|
|
hexmask.long.byte 0x00 16.--22. 1. " CHANMAP97 ,Interrupt CHAN97 Mapping Control"
|
|
hexmask.long.byte 0x00 8.--14. 1. " CHANMAP98 ,Interrupt CHAN98 Mapping Control"
|
|
hexmask.long.byte 0x00 0.--6. 1. " CHANMAP99 ,Interrupt CHAN99 Mapping Control"
|
|
group.long 0xE4++0x03
|
|
line.long 0x00 "CHANCTRL25,VIM Interrupt Control Register 25"
|
|
hexmask.long.byte 0x00 24.--30. 1. " CHANMAP100 ,Interrupt CHAN100 Mapping Control"
|
|
hexmask.long.byte 0x00 16.--22. 1. " CHANMAP101 ,Interrupt CHAN101 Mapping Control"
|
|
hexmask.long.byte 0x00 8.--14. 1. " CHANMAP102 ,Interrupt CHAN102 Mapping Control"
|
|
hexmask.long.byte 0x00 0.--6. 1. " CHANMAP103 ,Interrupt CHAN103 Mapping Control"
|
|
group.long 0xE8++0x03
|
|
line.long 0x00 "CHANCTRL26,VIM Interrupt Control Register 26"
|
|
hexmask.long.byte 0x00 24.--30. 1. " CHANMAP104 ,Interrupt CHAN104 Mapping Control"
|
|
hexmask.long.byte 0x00 16.--22. 1. " CHANMAP105 ,Interrupt CHAN105 Mapping Control"
|
|
hexmask.long.byte 0x00 8.--14. 1. " CHANMAP106 ,Interrupt CHAN106 Mapping Control"
|
|
hexmask.long.byte 0x00 0.--6. 1. " CHANMAP107 ,Interrupt CHAN107 Mapping Control"
|
|
group.long 0xEC++0x03
|
|
line.long 0x00 "CHANCTRL27,VIM Interrupt Control Register 27"
|
|
hexmask.long.byte 0x00 24.--30. 1. " CHANMAP108 ,Interrupt CHAN108 Mapping Control"
|
|
hexmask.long.byte 0x00 16.--22. 1. " CHANMAP109 ,Interrupt CHAN109 Mapping Control"
|
|
hexmask.long.byte 0x00 8.--14. 1. " CHANMAP110 ,Interrupt CHAN110 Mapping Control"
|
|
hexmask.long.byte 0x00 0.--6. 1. " CHANMAP111 ,Interrupt CHAN111 Mapping Control"
|
|
group.long 0xF0++0x03
|
|
line.long 0x00 "CHANCTRL28,VIM Interrupt Control Register 28"
|
|
hexmask.long.byte 0x00 24.--30. 1. " CHANMAP112 ,Interrupt CHAN112 Mapping Control"
|
|
hexmask.long.byte 0x00 16.--22. 1. " CHANMAP113 ,Interrupt CHAN113 Mapping Control"
|
|
hexmask.long.byte 0x00 8.--14. 1. " CHANMAP114 ,Interrupt CHAN114 Mapping Control"
|
|
hexmask.long.byte 0x00 0.--6. 1. " CHANMAP115 ,Interrupt CHAN115 Mapping Control"
|
|
group.long 0xF4++0x03
|
|
line.long 0x00 "CHANCTRL29,VIM Interrupt Control Register 29"
|
|
hexmask.long.byte 0x00 24.--30. 1. " CHANMAP116 ,Interrupt CHAN116 Mapping Control"
|
|
hexmask.long.byte 0x00 16.--22. 1. " CHANMAP117 ,Interrupt CHAN117 Mapping Control"
|
|
hexmask.long.byte 0x00 8.--14. 1. " CHANMAP118 ,Interrupt CHAN118 Mapping Control"
|
|
hexmask.long.byte 0x00 0.--6. 1. " CHANMAP119 ,Interrupt CHAN119 Mapping Control"
|
|
group.long 0xF8++0x03
|
|
line.long 0x00 "CHANCTRL30,VIM Interrupt Control Register 30"
|
|
hexmask.long.byte 0x00 24.--30. 1. " CHANMAP120 ,Interrupt CHAN120 Mapping Control"
|
|
hexmask.long.byte 0x00 16.--22. 1. " CHANMAP121 ,Interrupt CHAN121 Mapping Control"
|
|
hexmask.long.byte 0x00 8.--14. 1. " CHANMAP122 ,Interrupt CHAN122 Mapping Control"
|
|
hexmask.long.byte 0x00 0.--6. 1. " CHANMAP123 ,Interrupt CHAN123 Mapping Control"
|
|
group.long 0xFC++0x03
|
|
line.long 0x00 "CHANCTRL31,VIM Interrupt Control Register 31"
|
|
hexmask.long.byte 0x00 24.--30. 1. " CHANMAP124 ,Interrupt CHAN124 Mapping Control"
|
|
hexmask.long.byte 0x00 16.--22. 1. " CHANMAP125 ,Interrupt CHAN125 Mapping Control"
|
|
hexmask.long.byte 0x00 8.--14. 1. " CHANMAP126 ,Interrupt CHAN126 Mapping Control"
|
|
hexmask.long.byte 0x00 0.--6. 1. " CHANMAP127 ,Interrupt CHAN127 Mapping Control"
|
|
endif
|
|
tree.end
|
|
sif cpuis("TMS570LS0232")||cpuis("TMS570LS0714*")||cpuis("TMS570LS0914*")
|
|
endian.le
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
sif cpuis("TMS570LS0714*")||cpuis("TMS570LS0914*")
|
|
tree "DMA (Direct Memory Access)"
|
|
base ad:0xFFFFF000
|
|
width 12.
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "GCTRL,Global Control Register"
|
|
bitfld.long 0x00 16. " DMA_EN ,DMA enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 14. " BUS_BUSY ,DMA external ahb bus status" "Not busy,Busy"
|
|
newline
|
|
bitfld.long 0x00 8.--9. " DEBUG_MODE ,Debug mode" "Suspend ignored,Block finished,Frame finished,Immediate stop"
|
|
bitfld.long 0x00 0. " DMA_RES ,DMA software reset" "No reset,Reset"
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "PEND,Channel Pending Register"
|
|
bitfld.long 0x00 15. " PEND[15] ,Channel pending bit 15" "Inactive,Pending"
|
|
bitfld.long 0x00 14. " [14] ,Channel pending bit 14" "Inactive,Pending"
|
|
bitfld.long 0x00 13. " [13] ,Channel pending bit 13" "Inactive,Pending"
|
|
bitfld.long 0x00 12. " [12] ,Channel pending bit 12" "Inactive,Pending"
|
|
newline
|
|
bitfld.long 0x00 11. " [11] ,Channel pending bit 11" "Inactive,Pending"
|
|
bitfld.long 0x00 10. " [10] ,Channel pending bit 10" "Inactive,Pending"
|
|
bitfld.long 0x00 9. " [9] ,Channel pending bit 9" "Inactive,Pending"
|
|
bitfld.long 0x00 8. " [8] ,Channel pending bit 8" "Inactive,Pending"
|
|
newline
|
|
bitfld.long 0x00 7. " [7] ,Channel pending bit 7" "Inactive,Pending"
|
|
bitfld.long 0x00 6. " [6] ,Channel pending bit 6" "Inactive,Pending"
|
|
bitfld.long 0x00 5. " [5] ,Channel pending bit 5" "Inactive,Pending"
|
|
bitfld.long 0x00 4. " [4] ,Channel pending bit 4" "Inactive,Pending"
|
|
newline
|
|
bitfld.long 0x00 3. " [3] ,Channel pending bit 3" "Inactive,Pending"
|
|
bitfld.long 0x00 2. " [2] ,Channel pending bit 2" "Inactive,Pending"
|
|
bitfld.long 0x00 1. " [1] ,Channel pending bit 1" "Inactive,Pending"
|
|
bitfld.long 0x00 0. " [0] ,Channel pending bit 0" "Inactive,Pending"
|
|
rgroup.long 0x0C++0x03
|
|
line.long 0x00 "DMASTAT,DMA Status Register"
|
|
bitfld.long 0x00 15. " STCH[15] ,Status of DMA channel 15" "Inactive,Active"
|
|
bitfld.long 0x00 14. " [14] ,Status of DMA channel 14" "Inactive,Active"
|
|
bitfld.long 0x00 13. " [13] ,Status of DMA channel 13" "Inactive,Active"
|
|
bitfld.long 0x00 12. " [12] ,Status of DMA channel 12" "Inactive,Active"
|
|
newline
|
|
bitfld.long 0x00 11. " [11] ,Status of DMA channel 11" "Inactive,Active"
|
|
bitfld.long 0x00 10. " [10] ,Status of DMA channel 10" "Inactive,Active"
|
|
bitfld.long 0x00 9. " [9] ,Status of DMA channel 9" "Inactive,Active"
|
|
bitfld.long 0x00 8. " [8] ,Status of DMA channel 8" "Inactive,Active"
|
|
newline
|
|
bitfld.long 0x00 7. " [7] ,Status of DMA channel 7" "Inactive,Active"
|
|
bitfld.long 0x00 6. " [6] ,Status of DMA channel 6" "Inactive,Active"
|
|
bitfld.long 0x00 5. " [5] ,Status of DMA channel 5" "Inactive,Active"
|
|
bitfld.long 0x00 4. " [4] ,Status of DMA channel 4" "Inactive,Active"
|
|
newline
|
|
bitfld.long 0x00 3. " [3] ,Status of DMA channel 3" "Inactive,Active"
|
|
bitfld.long 0x00 2. " [2] ,Status of DMA channel 2" "Inactive,Active"
|
|
bitfld.long 0x00 1. " [1] ,Status of DMA channel 1" "Inactive,Active"
|
|
bitfld.long 0x00 0. " [0] ,Status of DMA channel 0" "Inactive,Active"
|
|
tree "Channel Enable Status Registers"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "HWCHENAS,HW Channel Enable Set And Status Register"
|
|
bitfld.long 0x00 15. " HWCHENA[15] ,HW channel 15 enable status" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " [14] ,HW channel 14 enable status" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " [13] ,HW channel 13 enable status" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " [12] ,HW channel 12 enable status" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 11. " [11] ,HW channel 11 enable status" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " [10] ,HW channel 10 enable status" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " [9] ,HW channel 9 enable status" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " [8] ,HW channel 8 enable status" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 7. " [7] ,HW channel 7 enable status" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " [6] ,HW channel 6 enable status" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " [5] ,HW channel 5 enable status" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " [4] ,HW channel 4 enable status" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 3. " [3] ,HW channel 3 enable status" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " [2] ,HW channel 2 enable status" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " [1] ,HW channel 1 enable status" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,HW channel 0 enable status" "Disabled,Enabled"
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "HWCHENAR,HW Channel Enable Reset And Status Register"
|
|
bitfld.long 0x00 15. " HWCHDIS[15] ,HW channel 15 disable" "No,Yes"
|
|
bitfld.long 0x00 14. " [14] ,HW channel 14 disable" "No,Yes"
|
|
bitfld.long 0x00 13. " [13] ,HW channel 13 disable" "No,Yes"
|
|
bitfld.long 0x00 12. " [12] ,HW channel 12 disable" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 11. " [11] ,HW channel 11 disable" "No,Yes"
|
|
bitfld.long 0x00 10. " [10] ,HW channel 10 disable" "No,Yes"
|
|
bitfld.long 0x00 9. " [9] ,HW channel 9 disable" "No,Yes"
|
|
bitfld.long 0x00 8. " [8] ,HW channel 8 disable" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 7. " [7] ,HW channel 7 disable" "No,Yes"
|
|
bitfld.long 0x00 6. " [6] ,HW channel 6 disable" "No,Yes"
|
|
bitfld.long 0x00 5. " [5] ,HW channel 5 disable" "No,Yes"
|
|
bitfld.long 0x00 4. " [4] ,HW channel 4 disable" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 3. " [3] ,HW channel 3 disable" "No,Yes"
|
|
bitfld.long 0x00 2. " [2] ,HW channel 2 disable" "No,Yes"
|
|
bitfld.long 0x00 1. " [1] ,HW channel 1 disable" "No,Yes"
|
|
bitfld.long 0x00 0. " [0] ,HW channel 0 disable" "No,Yes"
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "SWCHENAS,SW Channel Enable Set And Status Register"
|
|
bitfld.long 0x00 15. " SWCHENA[15] ,SW channel 15 enable status" "Not triggered,Triggered"
|
|
bitfld.long 0x00 14. " [14] ,SW channel 14 enable status" "Not triggered,Triggered"
|
|
bitfld.long 0x00 13. " [13] ,SW channel 13 enable status" "Not triggered,Triggered"
|
|
bitfld.long 0x00 12. " [12] ,SW channel 12 enable status" "Not triggered,Triggered"
|
|
newline
|
|
bitfld.long 0x00 11. " [11] ,SW channel 11 enable status" "Not triggered,Triggered"
|
|
bitfld.long 0x00 10. " [10] ,SW channel 10 enable status" "Not triggered,Triggered"
|
|
bitfld.long 0x00 9. " [9] ,SW channel 9 enable status" "Not triggered,Triggered"
|
|
bitfld.long 0x00 8. " [8] ,SW channel 8 enable status" "Not triggered,Triggered"
|
|
newline
|
|
bitfld.long 0x00 7. " [7] ,SW channel 7 enable status" "Not triggered,Triggered"
|
|
bitfld.long 0x00 6. " [6] ,SW channel 6 enable status" "Not triggered,Triggered"
|
|
bitfld.long 0x00 5. " [5] ,SW channel 5 enable status" "Not triggered,Triggered"
|
|
bitfld.long 0x00 4. " [4] ,SW channel 4 enable status" "Not triggered,Triggered"
|
|
newline
|
|
bitfld.long 0x00 3. " [3] ,SW channel 3 enable status" "Not triggered,Triggered"
|
|
bitfld.long 0x00 2. " [2] ,SW channel 2 enable status" "Not triggered,Triggered"
|
|
bitfld.long 0x00 1. " [1] ,SW channel 1 enable status" "Not triggered,Triggered"
|
|
bitfld.long 0x00 0. " [0] ,SW channel 0 enable status" "Not triggered,Triggered"
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "SWCHENAR,SW Channel Enable Reset And Status Register"
|
|
bitfld.long 0x00 15. " SWCHDIS[15] ,SW channel 15 disable" "No,Yes"
|
|
bitfld.long 0x00 14. " [14] ,SW channel 14 disable" "No,Yes"
|
|
bitfld.long 0x00 13. " [13] ,SW channel 13 disable" "No,Yes"
|
|
bitfld.long 0x00 12. " [12] ,SW channel 12 disable" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 11. " [11] ,SW channel 11 disable" "No,Yes"
|
|
bitfld.long 0x00 10. " [10] ,SW channel 10 disable" "No,Yes"
|
|
bitfld.long 0x00 9. " [9] ,SW channel 9 disable" "No,Yes"
|
|
bitfld.long 0x00 8. " [8] ,SW channel 8 disable" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 7. " [7] ,SW channel 7 disable" "No,Yes"
|
|
bitfld.long 0x00 6. " [6] ,SW channel 6 disable" "No,Yes"
|
|
bitfld.long 0x00 5. " [5] ,SW channel 5 disable" "No,Yes"
|
|
bitfld.long 0x00 4. " [4] ,SW channel 4 disable" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 3. " [3] ,SW channel 3 disable" "No,Yes"
|
|
bitfld.long 0x00 2. " [2] ,SW channel 2 disable" "No,Yes"
|
|
bitfld.long 0x00 1. " [1] ,SW channel 1 disable" "No,Yes"
|
|
bitfld.long 0x00 0. " [0] ,SW channel 0 disable" "No,Yes"
|
|
tree.end
|
|
newline
|
|
group.long 0x34++0x03
|
|
line.long 0x00 "CHPRIOS,Channel Priority Set Register"
|
|
bitfld.long 0x00 15. " CPS[15] ,Channel priority 15 set" "Low,High"
|
|
bitfld.long 0x00 14. " [14] ,Channel priority 14 set" "Low,High"
|
|
bitfld.long 0x00 13. " [13] ,Channel priority 13 set" "Low,High"
|
|
bitfld.long 0x00 12. " [12] ,Channel priority 12 set" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 11. " [11] ,Channel priority 11 set" "Low,High"
|
|
bitfld.long 0x00 10. " [10] ,Channel priority 10 set" "Low,High"
|
|
bitfld.long 0x00 9. " [9] ,Channel priority 9 set" "Low,High"
|
|
bitfld.long 0x00 8. " [8] ,Channel priority 8 set" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 7. " [7] ,Channel priority 7 set" "Low,High"
|
|
bitfld.long 0x00 6. " [6] ,Channel priority 6 set" "Low,High"
|
|
bitfld.long 0x00 5. " [5] ,Channel priority 5 set" "Low,High"
|
|
bitfld.long 0x00 4. " [4] ,Channel priority 4 set" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 3. " [3] ,Channel priority 3 set" "Low,High"
|
|
bitfld.long 0x00 2. " [2] ,Channel priority 2 set" "Low,High"
|
|
bitfld.long 0x00 1. " [1] ,Channel priority 1 set" "Low,High"
|
|
bitfld.long 0x00 0. " [0] ,Channel priority 0 set" "Low,High"
|
|
group.long 0x3C++0x03
|
|
line.long 0x00 "CHPRIOR,Channel Priority Reset"
|
|
bitfld.long 0x00 15. " CPR[15] ,Channel priority 15" "No effect,Reset"
|
|
bitfld.long 0x00 14. " [14] ,Channel priority 14" "No effect,Reset"
|
|
bitfld.long 0x00 13. " [13] ,Channel priority 13" "No effect,Reset"
|
|
bitfld.long 0x00 12. " [12] ,Channel priority 12" "No effect,Reset"
|
|
newline
|
|
bitfld.long 0x00 11. " [11] ,Channel priority 11" "No effect,Reset"
|
|
bitfld.long 0x00 10. " [10] ,Channel priority 10" "No effect,Reset"
|
|
bitfld.long 0x00 9. " [9] ,Channel priority 9" "No effect,Reset"
|
|
bitfld.long 0x00 8. " [8] ,Channel priority 8" "No effect,Reset"
|
|
newline
|
|
bitfld.long 0x00 7. " [7] ,Channel priority 7" "No effect,Reset"
|
|
bitfld.long 0x00 6. " [6] ,Channel priority 6" "No effect,Reset"
|
|
bitfld.long 0x00 5. " [5] ,Channel priority 5" "No effect,Reset"
|
|
bitfld.long 0x00 4. " [4] ,Channel priority 4" "No effect,Reset"
|
|
newline
|
|
bitfld.long 0x00 3. " [3] ,Channel priority 3" "No effect,Reset"
|
|
bitfld.long 0x00 2. " [2] ,Channel priority 2" "No effect,Reset"
|
|
bitfld.long 0x00 1. " [1] ,Channel priority 1" "No effect,Reset"
|
|
bitfld.long 0x00 0. " [0] ,Channel priority 0" "No effect,Reset"
|
|
group.long 0x44++0x03
|
|
line.long 0x00 "GCHIENAS,Global Channel Interrupt Enable Set"
|
|
bitfld.long 0x00 15. " GCHIE[15] ,Global channel interrupt enable 15" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " [14] ,Global channel interrupt enable 14" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " [13] ,Global channel interrupt enable 13" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " [12] ,Global channel interrupt enable 12" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 11. " [11] ,Global channel interrupt enable 11" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " [10] ,Global channel interrupt enable 10" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " [9] ,Global channel interrupt enable 9" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " [8] ,Global channel interrupt enable 8" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 7. " [7] ,Global channel interrupt enable 7" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " [6] ,Global channel interrupt enable 6" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " [5] ,Global channel interrupt enable 5" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " [4] ,Global channel interrupt enable 4" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 3. " [3] ,Global channel interrupt enable 3" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " [2] ,Global channel interrupt enable 2" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " [1] ,Global channel interrupt enable 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,Global channel interrupt enable 0" "Disabled,Enabled"
|
|
group.long 0x4C++0x03
|
|
line.long 0x00 "GCHIENAR,Global Channel Interrupt Enable Reset"
|
|
bitfld.long 0x00 15. " GCHID[15] ,Global channel interrupt disable 15" "No effect,Reset"
|
|
bitfld.long 0x00 14. " [14] ,Global channel interrupt disable 14" "No effect,Reset"
|
|
bitfld.long 0x00 13. " [13] ,Global channel interrupt disable 13" "No effect,Reset"
|
|
bitfld.long 0x00 12. " [12] ,Global channel interrupt disable 12" "No effect,Reset"
|
|
newline
|
|
bitfld.long 0x00 11. " [11] ,Global channel interrupt disable 11" "No effect,Reset"
|
|
bitfld.long 0x00 10. " [10] ,Global channel interrupt disable 10" "No effect,Reset"
|
|
bitfld.long 0x00 9. " [9] ,Global channel interrupt disable 9" "No effect,Reset"
|
|
bitfld.long 0x00 8. " [8] ,Global channel interrupt disable 8" "No effect,Reset"
|
|
newline
|
|
bitfld.long 0x00 7. " [7] ,Global channel interrupt disable 7" "No effect,Reset"
|
|
bitfld.long 0x00 6. " [6] ,Global channel interrupt disable 6" "No effect,Reset"
|
|
bitfld.long 0x00 5. " [5] ,Global channel interrupt disable 5" "No effect,Reset"
|
|
bitfld.long 0x00 4. " [4] ,Global channel interrupt disable 4" "No effect,Reset"
|
|
newline
|
|
bitfld.long 0x00 3. " [3] ,Global channel interrupt disable 3" "No effect,Reset"
|
|
bitfld.long 0x00 2. " [2] ,Global channel interrupt disable 2" "No effect,Reset"
|
|
bitfld.long 0x00 1. " [1] ,Global channel interrupt disable 1" "No effect,Reset"
|
|
bitfld.long 0x00 0. " [0] ,Global channel interrupt disable 0" "No effect,Reset"
|
|
tree "DMA Request Assignment Registers"
|
|
group.long 0x54++0x0F
|
|
line.long 0x00 "DREQASI0,DMA Request Assignment Register 0"
|
|
bitfld.long 0x00 24.--29. " CH0ASI ,Channel 0 assignment" "Line 0,Line 1,Line 2,Line 3,Line 4,Line 5,Line 6,Line 7,Line 8,Line 9,Line 10,Line 11,Line 12,Line 13,Line 14,Line 15,Line 16,Line 17,Line 18,Line 19,Line 20,Line 21,Line 22,Line 23,Line 24,Line 25,Line 26,Line 27,Line 28,Line 29,Line 30,Line 31,?..."
|
|
bitfld.long 0x00 16.--21. " CH1ASI ,Channel 1 assignment" "Line 0,Line 1,Line 2,Line 3,Line 4,Line 5,Line 6,Line 7,Line 8,Line 9,Line 10,Line 11,Line 12,Line 13,Line 14,Line 15,Line 16,Line 17,Line 18,Line 19,Line 20,Line 21,Line 22,Line 23,Line 24,Line 25,Line 26,Line 27,Line 28,Line 29,Line 30,Line 31,?..."
|
|
bitfld.long 0x00 8.--13. " CH2ASI ,Channel 2 assignment" "Line 0,Line 1,Line 2,Line 3,Line 4,Line 5,Line 6,Line 7,Line 8,Line 9,Line 10,Line 11,Line 12,Line 13,Line 14,Line 15,Line 16,Line 17,Line 18,Line 19,Line 20,Line 21,Line 22,Line 23,Line 24,Line 25,Line 26,Line 27,Line 28,Line 29,Line 30,Line 31,?..."
|
|
bitfld.long 0x00 0.--5. " CH3ASI ,Channel 3 assignment" "Line 0,Line 1,Line 2,Line 3,Line 4,Line 5,Line 6,Line 7,Line 8,Line 9,Line 10,Line 11,Line 12,Line 13,Line 14,Line 15,Line 16,Line 17,Line 18,Line 19,Line 20,Line 21,Line 22,Line 23,Line 24,Line 25,Line 26,Line 27,Line 28,Line 29,Line 30,Line 31,?..."
|
|
line.long 0x04 "DREQASI1,DMA Request Assignment Register 1"
|
|
bitfld.long 0x04 24.--29. " CH04SI ,Channel 4 assignment" "Line 0,Line 1,Line 2,Line 3,Line 4,Line 5,Line 6,Line 7,Line 8,Line 9,Line 10,Line 11,Line 12,Line 13,Line 14,Line 15,Line 16,Line 17,Line 18,Line 19,Line 20,Line 21,Line 22,Line 23,Line 24,Line 25,Line 26,Line 27,Line 28,Line 29,Line 30,Line 31,?..."
|
|
bitfld.long 0x04 16.--21. " CH5ASI ,Channel 5 assignment" "Line 0,Line 1,Line 2,Line 3,Line 4,Line 5,Line 6,Line 7,Line 8,Line 9,Line 10,Line 11,Line 12,Line 13,Line 14,Line 15,Line 16,Line 17,Line 18,Line 19,Line 20,Line 21,Line 22,Line 23,Line 24,Line 25,Line 26,Line 27,Line 28,Line 29,Line 30,Line 31,?..."
|
|
bitfld.long 0x04 8.--13. " CH6ASI ,Channel 6 assignment" "Line 0,Line 1,Line 2,Line 3,Line 4,Line 5,Line 6,Line 7,Line 8,Line 9,Line 10,Line 11,Line 12,Line 13,Line 14,Line 15,Line 16,Line 17,Line 18,Line 19,Line 20,Line 21,Line 22,Line 23,Line 24,Line 25,Line 26,Line 27,Line 28,Line 29,Line 30,Line 31,?..."
|
|
bitfld.long 0x04 0.--5. " CH7ASI ,Channel 7 assignment" "Line 0,Line 1,Line 2,Line 3,Line 4,Line 5,Line 6,Line 7,Line 8,Line 9,Line 10,Line 11,Line 12,Line 13,Line 14,Line 15,Line 16,Line 17,Line 18,Line 19,Line 20,Line 21,Line 22,Line 23,Line 24,Line 25,Line 26,Line 27,Line 28,Line 29,Line 30,Line 31,?..."
|
|
line.long 0x08 "DREQASI2,DMA Request Assignment Register 2"
|
|
bitfld.long 0x08 24.--29. " CH8ASI ,Channel 8 assignment" "Line 0,Line 1,Line 2,Line 3,Line 4,Line 5,Line 6,Line 7,Line 8,Line 9,Line 10,Line 11,Line 12,Line 13,Line 14,Line 15,Line 16,Line 17,Line 18,Line 19,Line 20,Line 21,Line 22,Line 23,Line 24,Line 25,Line 26,Line 27,Line 28,Line 29,Line 30,Line 31,?..."
|
|
bitfld.long 0x08 16.--21. " CH9ASI ,Channel 9 assignment" "Line 0,Line 1,Line 2,Line 3,Line 4,Line 5,Line 6,Line 7,Line 8,Line 9,Line 10,Line 11,Line 12,Line 13,Line 14,Line 15,Line 16,Line 17,Line 18,Line 19,Line 20,Line 21,Line 22,Line 23,Line 24,Line 25,Line 26,Line 27,Line 28,Line 29,Line 30,Line 31,?..."
|
|
bitfld.long 0x08 8.--13. " CH10ASI ,Channel 10 assignment" "Line 0,Line 1,Line 2,Line 3,Line 4,Line 5,Line 6,Line 7,Line 8,Line 9,Line 10,Line 11,Line 12,Line 13,Line 14,Line 15,Line 16,Line 17,Line 18,Line 19,Line 20,Line 21,Line 22,Line 23,Line 24,Line 25,Line 26,Line 27,Line 28,Line 29,Line 30,Line 31,?..."
|
|
bitfld.long 0x08 0.--5. " CH11ASI ,Channel 11 assignment" "Line 0,Line 1,Line 2,Line 3,Line 4,Line 5,Line 6,Line 7,Line 8,Line 9,Line 10,Line 11,Line 12,Line 13,Line 14,Line 15,Line 16,Line 17,Line 18,Line 19,Line 20,Line 21,Line 22,Line 23,Line 24,Line 25,Line 26,Line 27,Line 28,Line 29,Line 30,Line 31,?..."
|
|
line.long 0x0C "DREQASI3,DMA Request Assignment Register 3"
|
|
bitfld.long 0x0C 24.--29. " CH12ASI ,Channel 12 assignment" "Line 0,Line 1,Line 2,Line 3,Line 4,Line 5,Line 6,Line 7,Line 8,Line 9,Line 10,Line 11,Line 12,Line 13,Line 14,Line 15,Line 16,Line 17,Line 18,Line 19,Line 20,Line 21,Line 22,Line 23,Line 24,Line 25,Line 26,Line 27,Line 28,Line 29,Line 30,Line 31,?..."
|
|
bitfld.long 0x0C 16.--21. " CH13ASI ,Channel 13 assignment" "Line 0,Line 1,Line 2,Line 3,Line 4,Line 5,Line 6,Line 7,Line 8,Line 9,Line 10,Line 11,Line 12,Line 13,Line 14,Line 15,Line 16,Line 17,Line 18,Line 19,Line 20,Line 21,Line 22,Line 23,Line 24,Line 25,Line 26,Line 27,Line 28,Line 29,Line 30,Line 31,?..."
|
|
bitfld.long 0x0C 8.--13. " CH14ASI ,Channel 14 assignment" "Line 0,Line 1,Line 2,Line 3,Line 4,Line 5,Line 6,Line 7,Line 8,Line 9,Line 10,Line 11,Line 12,Line 13,Line 14,Line 15,Line 16,Line 17,Line 18,Line 19,Line 20,Line 21,Line 22,Line 23,Line 24,Line 25,Line 26,Line 27,Line 28,Line 29,Line 30,Line 31,?..."
|
|
bitfld.long 0x0C 0.--5. " CH15ASI ,Channel 15 assignment" "Line 0,Line 1,Line 2,Line 3,Line 4,Line 5,Line 6,Line 7,Line 8,Line 9,Line 10,Line 11,Line 12,Line 13,Line 14,Line 15,Line 16,Line 17,Line 18,Line 19,Line 20,Line 21,Line 22,Line 23,Line 24,Line 25,Line 26,Line 27,Line 28,Line 29,Line 30,Line 31,?..."
|
|
tree.end
|
|
tree "Port Assignment Registers"
|
|
group.long 0x94++0x07
|
|
line.long 0x00 "PAR0,Port Assignment Register 0"
|
|
bitfld.long 0x00 28.--30. " CH0PA ,Port channel 0 assignment" ",,,,Port B,Port B,Port B,Port B"
|
|
bitfld.long 0x00 24.--26. " CH1PA ,Port channel 1 assignment" ",,,,Port B,Port B,Port B,Port B"
|
|
bitfld.long 0x00 20.--22. " CH2PA ,Port channel 2 assignment" ",,,,Port B,Port B,Port B,Port B"
|
|
bitfld.long 0x00 16.--18. " CH3PA ,Port channel 3 assignment" ",,,,Port B,Port B,Port B,Port B"
|
|
newline
|
|
bitfld.long 0x00 12.--14. " CH4PA ,Port channel 4 assignment" ",,,,Port B,Port B,Port B,Port B"
|
|
bitfld.long 0x00 8.--10. " CH5PA ,Port channel 5 assignment" ",,,,Port B,Port B,Port B,Port B"
|
|
bitfld.long 0x00 4.--6. " CH6PA ,Port channel 6 assignment" ",,,,Port B,Port B,Port B,Port B"
|
|
bitfld.long 0x00 0.--2. " CH7PA ,Port channel 7 assignment" ",,,,Port B,Port B,Port B,Port B"
|
|
line.long 0x04 "PAR1,Port Assignment Register 1"
|
|
bitfld.long 0x04 28.--30. " CH8PA ,Port channel 8 assignment" ",,,,Port B,Port B,Port B,Port B"
|
|
bitfld.long 0x04 24.--26. " CH9PA ,Port channel 9 assignment" ",,,,Port B,Port B,Port B,Port B"
|
|
bitfld.long 0x04 20.--22. " CH10PA ,Port channel 10 assignment" ",,,,Port B,Port B,Port B,Port B"
|
|
bitfld.long 0x04 16.--18. " CH11PA ,Port channel 11 assignment" ",,,,Port B,Port B,Port B,Port B"
|
|
newline
|
|
bitfld.long 0x04 12.--14. " CH12PA ,Port channel 12 assignment" ",,,,Port B,Port B,Port B,Port B"
|
|
bitfld.long 0x04 8.--10. " CH13PA ,Port channel 13 assignment" ",,,,Port B,Port B,Port B,Port B"
|
|
bitfld.long 0x04 4.--6. " CH14PA ,Port channel 14 assignment" ",,,,Port B,Port B,Port B,Port B"
|
|
bitfld.long 0x04 0.--2. " CH15PA ,Port channel 15 assignment" ",,,,Port B,Port B,Port B,Port B"
|
|
tree.end
|
|
tree "Interrupt Mapping Registers"
|
|
group.long 0xB4++0x03
|
|
line.long 0x00 "FTCMAP,FTC Interrupt Mapping Register"
|
|
bitfld.long 0x00 15. " FTCAB[15] ,Frame transfer complete interrupt of channel 15 to group A/B" "Group A,Group B"
|
|
bitfld.long 0x00 14. " [14] ,Frame transfer complete interrupt of channel 14 to group A/B" "Group A,Group B"
|
|
bitfld.long 0x00 13. " [13] ,Frame transfer complete interrupt of channel 13 to group A/B" "Group A,Group B"
|
|
bitfld.long 0x00 12. " [12] ,Frame transfer complete interrupt of channel 12 to group A/B" "Group A,Group B"
|
|
newline
|
|
bitfld.long 0x00 11. " [11] ,Frame transfer complete interrupt of channel 11 to group A/B" "Group A,Group B"
|
|
bitfld.long 0x00 10. " [10] ,Frame transfer complete interrupt of channel 10 to group A/B" "Group A,Group B"
|
|
bitfld.long 0x00 9. " [9] ,Frame transfer complete interrupt of channel 9 to group A/B" "Group A,Group B"
|
|
bitfld.long 0x00 8. " [8] ,Frame transfer complete interrupt of channel 8 to group A/B" "Group A,Group B"
|
|
newline
|
|
bitfld.long 0x00 7. " [7] ,Frame transfer complete interrupt of channel 7 to group A/B" "Group A,Group B"
|
|
bitfld.long 0x00 6. " [6] ,Frame transfer complete interrupt of channel 6 to group A/B" "Group A,Group B"
|
|
bitfld.long 0x00 5. " [5] ,Frame transfer complete interrupt of channel 5 to group A/B" "Group A,Group B"
|
|
bitfld.long 0x00 4. " [4] ,Frame transfer complete interrupt of channel 4 to group A/B" "Group A,Group B"
|
|
newline
|
|
bitfld.long 0x00 3. " [3] ,Frame transfer complete interrupt of channel 3 to group A/B" "Group A,Group B"
|
|
bitfld.long 0x00 2. " [2] ,Frame transfer complete interrupt of channel 2 to group A/B" "Group A,Group B"
|
|
bitfld.long 0x00 1. " [1] ,Frame transfer complete interrupt of channel 1 to group A/B" "Group A,Group B"
|
|
bitfld.long 0x00 0. " [0] ,Frame transfer complete interrupt of channel 0 to group A/B" "Group A,Group B"
|
|
group.long 0xBC++0x03
|
|
line.long 0x00 "LFSMAP,LFS Interrupt Mapping Register"
|
|
bitfld.long 0x00 15. " LFSAB[15] ,Last frame started interrupt of channel 15 to group A/B" "Group A,Group B"
|
|
bitfld.long 0x00 14. " [14] ,Last frame started interrupt of channel 14 to group A/B" "Group A,Group B"
|
|
bitfld.long 0x00 13. " [13] ,Last frame started interrupt of channel 13 to group A/B" "Group A,Group B"
|
|
bitfld.long 0x00 12. " [12] ,Last frame started interrupt of channel 12 to group A/B" "Group A,Group B"
|
|
newline
|
|
bitfld.long 0x00 11. " [11] ,Last frame started interrupt of channel 11 to group A/B" "Group A,Group B"
|
|
bitfld.long 0x00 10. " [10] ,Last frame started interrupt of channel 10 to group A/B" "Group A,Group B"
|
|
bitfld.long 0x00 9. " [9] ,Last frame started interrupt of channel 9 to group A/B" "Group A,Group B"
|
|
bitfld.long 0x00 8. " [8] ,Last frame started interrupt of channel 8 to group A/B" "Group A,Group B"
|
|
newline
|
|
bitfld.long 0x00 7. " [7] ,Last frame started interrupt of channel 7 to group A/B" "Group A,Group B"
|
|
bitfld.long 0x00 6. " [6] ,Last frame started interrupt of channel 6 to group A/B" "Group A,Group B"
|
|
bitfld.long 0x00 5. " [5] ,Last frame started interrupt of channel 5 to group A/B" "Group A,Group B"
|
|
bitfld.long 0x00 4. " [4] ,Last frame started interrupt of channel 4 to group A/B" "Group A,Group B"
|
|
newline
|
|
bitfld.long 0x00 3. " [3] ,Last frame started interrupt of channel 3 to group A/B" "Group A,Group B"
|
|
bitfld.long 0x00 2. " [2] ,Last frame started interrupt of channel 2 to group A/B" "Group A,Group B"
|
|
bitfld.long 0x00 1. " [1] ,Last frame started interrupt of channel 1 to group A/B" "Group A,Group B"
|
|
bitfld.long 0x00 0. " [0] ,Last frame started interrupt of channel 0 to group A/B" "Group A,Group B"
|
|
group.long 0xC4++0x03
|
|
line.long 0x00 "HBCMAP,HBC Interrupt Mapping Register"
|
|
bitfld.long 0x00 15. " HBCAB[15] ,Half Block complete interrupt of channel 15 to group A/B" "Group A,Group B"
|
|
bitfld.long 0x00 14. " [14] ,Half Block complete interrupt of channel 14 to group A/B" "Group A,Group B"
|
|
bitfld.long 0x00 13. " [13] ,Half Block complete interrupt of channel 13 to group A/B" "Group A,Group B"
|
|
bitfld.long 0x00 12. " [12] ,Half Block complete interrupt of channel 12 to group A/B" "Group A,Group B"
|
|
newline
|
|
bitfld.long 0x00 11. " [11] ,Half Block complete interrupt of channel 11 to group A/B" "Group A,Group B"
|
|
bitfld.long 0x00 10. " [10] ,Half Block complete interrupt of channel 10 to group A/B" "Group A,Group B"
|
|
bitfld.long 0x00 9. " [9] ,Half Block complete interrupt of channel 9 to group A/B" "Group A,Group B"
|
|
bitfld.long 0x00 8. " [8] ,Half Block complete interrupt of channel 8 to group A/B" "Group A,Group B"
|
|
newline
|
|
bitfld.long 0x00 7. " [7] ,Half Block complete interrupt of channel 7 to group A/B" "Group A,Group B"
|
|
bitfld.long 0x00 6. " [6] ,Half Block complete interrupt of channel 6 to group A/B" "Group A,Group B"
|
|
bitfld.long 0x00 5. " [5] ,Half Block complete interrupt of channel 5 to group A/B" "Group A,Group B"
|
|
bitfld.long 0x00 4. " [4] ,Half Block complete interrupt of channel 4 to group A/B" "Group A,Group B"
|
|
newline
|
|
bitfld.long 0x00 3. " [3] ,Half Block complete interrupt of channel 3 to group A/B" "Group A,Group B"
|
|
bitfld.long 0x00 2. " [2] ,Half Block complete interrupt of channel 2 to group A/B" "Group A,Group B"
|
|
bitfld.long 0x00 1. " [1] ,Half Block complete interrupt of channel 1 to group A/B" "Group A,Group B"
|
|
bitfld.long 0x00 0. " [0] ,Half Block complete interrupt of channel 0 to group A/B" "Group A,Group B"
|
|
group.long 0xCC++0x03
|
|
line.long 0x00 "BTCMAP,BTC Interrupt Mapping Register"
|
|
bitfld.long 0x00 15. " BTCAB[15] ,Block transfer complete interrupt of channel 15 to group A/B" "Group A,Group B"
|
|
bitfld.long 0x00 14. " [14] ,Block transfer complete interrupt of channel 14 to group A/B" "Group A,Group B"
|
|
bitfld.long 0x00 13. " [13] ,Block transfer complete interrupt of channel 13 to group A/B" "Group A,Group B"
|
|
bitfld.long 0x00 12. " [12] ,Block transfer complete interrupt of channel 12 to group A/B" "Group A,Group B"
|
|
newline
|
|
bitfld.long 0x00 11. " [11] ,Block transfer complete interrupt of channel 11 to group A/B" "Group A,Group B"
|
|
bitfld.long 0x00 10. " [10] ,Block transfer complete interrupt of channel 10 to group A/B" "Group A,Group B"
|
|
bitfld.long 0x00 9. " [9] ,Block transfer complete interrupt of channel 9 to group A/B" "Group A,Group B"
|
|
bitfld.long 0x00 8. " [8] ,Block transfer complete interrupt of channel 8 to group A/B" "Group A,Group B"
|
|
newline
|
|
bitfld.long 0x00 7. " [7] ,Block transfer complete interrupt of channel 7 to group A/B" "Group A,Group B"
|
|
bitfld.long 0x00 6. " [6] ,Block transfer complete interrupt of channel 6 to group A/B" "Group A,Group B"
|
|
bitfld.long 0x00 5. " [5] ,Block transfer complete interrupt of channel 5 to group A/B" "Group A,Group B"
|
|
bitfld.long 0x00 4. " [4] ,Block transfer complete interrupt of channel 4 to group A/B" "Group A,Group B"
|
|
newline
|
|
bitfld.long 0x00 3. " [3] ,Block transfer complete interrupt of channel 3 to group A/B" "Group A,Group B"
|
|
bitfld.long 0x00 2. " [2] ,Block transfer complete interrupt of channel 2 to group A/B" "Group A,Group B"
|
|
bitfld.long 0x00 1. " [1] ,Block transfer complete interrupt of channel 1 to group A/B" "Group A,Group B"
|
|
bitfld.long 0x00 0. " [0] ,Block transfer complete interrupt of channel 0 to group A/B" "Group A,Group B"
|
|
tree.end
|
|
tree "Interrupt Enable Registers"
|
|
group.long 0xDC++0x03
|
|
line.long 0x00 "FTCINTENAS,FTC Interrupt Enable Set"
|
|
bitfld.long 0x00 15. " FTCINTENA[15] ,Frame transfer complete interrupt enable 15" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " [14] ,Frame transfer complete interrupt enable 14" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " [13] ,Frame transfer complete interrupt enable 13" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " [12] ,Frame transfer complete interrupt enable 12" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 11. " [11] ,Frame transfer complete interrupt enable 11" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " [10] ,Frame transfer complete interrupt enable 10" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " [9] ,Frame transfer complete interrupt enable 9" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " [8] ,Frame transfer complete interrupt enable 8" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 7. " [7] ,Frame transfer complete interrupt enable 7" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " [6] ,Frame transfer complete interrupt enable 6" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " [5] ,Frame transfer complete interrupt enable 5" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " [4] ,Frame transfer complete interrupt enable 4" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 3. " [3] ,Frame transfer complete interrupt enable 3" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " [2] ,Frame transfer complete interrupt enable 2" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " [1] ,Frame transfer complete interrupt enable 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,Frame transfer complete interrupt enable 0" "Disabled,Enabled"
|
|
group.long 0xE4++0x03
|
|
line.long 0x00 "FTCINTENAR,FTC Interrupt Enable Reset"
|
|
bitfld.long 0x00 15. " FTCINTDIS[15] ,Frame transfer complete interrupt disable 15" "No effect,Reset"
|
|
bitfld.long 0x00 14. " [14] ,Frame transfer complete interrupt disable 14" "No effect,Reset"
|
|
bitfld.long 0x00 13. " [13] ,Frame transfer complete interrupt disable 13" "No effect,Reset"
|
|
bitfld.long 0x00 12. " [12] ,Frame transfer complete interrupt disable 12" "No effect,Reset"
|
|
newline
|
|
bitfld.long 0x00 11. " [11] ,Frame transfer complete interrupt disable 11" "No effect,Reset"
|
|
bitfld.long 0x00 10. " [10] ,Frame transfer complete interrupt disable 10" "No effect,Reset"
|
|
bitfld.long 0x00 9. " [9] ,Frame transfer complete interrupt disable 9" "No effect,Reset"
|
|
bitfld.long 0x00 8. " [8] ,Frame transfer complete interrupt disable 8" "No effect,Reset"
|
|
newline
|
|
bitfld.long 0x00 7. " [7] ,Frame transfer complete interrupt disable 7" "No effect,Reset"
|
|
bitfld.long 0x00 6. " [6] ,Frame transfer complete interrupt disable 6" "No effect,Reset"
|
|
bitfld.long 0x00 5. " [5] ,Frame transfer complete interrupt disable 5" "No effect,Reset"
|
|
bitfld.long 0x00 4. " [4] ,Frame transfer complete interrupt disable 4" "No effect,Reset"
|
|
newline
|
|
bitfld.long 0x00 3. " [3] ,Frame transfer complete interrupt disable 3" "No effect,Reset"
|
|
bitfld.long 0x00 2. " [2] ,Frame transfer complete interrupt disable 2" "No effect,Reset"
|
|
bitfld.long 0x00 1. " [1] ,Frame transfer complete interrupt disable 1" "No effect,Reset"
|
|
bitfld.long 0x00 0. " [0] ,Frame transfer complete interrupt disable 0" "No effect,Reset"
|
|
group.long 0xEC++0x03
|
|
line.long 0x00 "LFSINTENAS,LFS Interrupt Enable Set"
|
|
bitfld.long 0x00 15. " LFSINTENA[15] ,Last frame started interrupt enable 15" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " [14] ,Last frame started interrupt enable 14" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " [13] ,Last frame started interrupt enable 13" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " [12] ,Last frame started interrupt enable 12" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 11. " [11] ,Last frame started interrupt enable 11" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " [10] ,Last frame started interrupt enable 10" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " [9] ,Last frame started interrupt enable 9" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " [8] ,Last frame started interrupt enable 8" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 7. " [7] ,Last frame started interrupt enable 7" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " [6] ,Last frame started interrupt enable 6" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " [5] ,Last frame started interrupt enable 5" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " [4] ,Last frame started interrupt enable 4" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 3. " [3] ,Last frame started interrupt enable 3" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " [2] ,Last frame started interrupt enable 2" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " [1] ,Last frame started interrupt enable 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,Last frame started interrupt enable 0" "Disabled,Enabled"
|
|
group.long 0xF4++0x03
|
|
line.long 0x00 "LFSINTENAR,LFS Interrupt Enable Reset"
|
|
bitfld.long 0x00 15. " LFSINTDIS[15] ,Last frame started interrupt disable 15" "No effect,Reset"
|
|
bitfld.long 0x00 14. " [14] ,Last frame started interrupt disable 14" "No effect,Reset"
|
|
bitfld.long 0x00 13. " [13] ,Last frame started interrupt disable 13" "No effect,Reset"
|
|
bitfld.long 0x00 12. " [12] ,Last frame started interrupt disable 12" "No effect,Reset"
|
|
newline
|
|
bitfld.long 0x00 11. " [11] ,Last frame started interrupt disable 11" "No effect,Reset"
|
|
bitfld.long 0x00 10. " [10] ,Last frame started interrupt disable 10" "No effect,Reset"
|
|
bitfld.long 0x00 9. " [9] ,Last frame started interrupt disable 9" "No effect,Reset"
|
|
bitfld.long 0x00 8. " [8] ,Last frame started interrupt disable 8" "No effect,Reset"
|
|
newline
|
|
bitfld.long 0x00 7. " [7] ,Last frame started interrupt disable 7" "No effect,Reset"
|
|
bitfld.long 0x00 6. " [6] ,Last frame started interrupt disable 6" "No effect,Reset"
|
|
bitfld.long 0x00 5. " [5] ,Last frame started interrupt disable 5" "No effect,Reset"
|
|
bitfld.long 0x00 4. " [4] ,Last frame started interrupt disable 4" "No effect,Reset"
|
|
newline
|
|
bitfld.long 0x00 3. " [3] ,Last frame started interrupt disable 3" "No effect,Reset"
|
|
bitfld.long 0x00 2. " [2] ,Last frame started interrupt disable 2" "No effect,Reset"
|
|
bitfld.long 0x00 1. " [1] ,Last frame started interrupt disable 1" "No effect,Reset"
|
|
bitfld.long 0x00 0. " [0] ,Last frame started interrupt disable 0" "No effect,Reset"
|
|
group.long 0xFC++0x03
|
|
line.long 0x00 "HBCINTENAS,HBC Interrupt Enable Set"
|
|
bitfld.long 0x00 15. " HBCINTENA[15] ,Half block complete interrupt enable 15" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " [14] ,Half block complete interrupt enable 14" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " [13] ,Half block complete interrupt enable 13" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " [12] ,Half block complete interrupt enable 12" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 11. " [11] ,Half block complete interrupt enable 11" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " [10] ,Half block complete interrupt enable 10" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " [9] ,Half block complete interrupt enable 9" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " [8] ,Half block complete interrupt enable 8" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 7. " [7] ,Half block complete interrupt enable 7" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " [6] ,Half block complete interrupt enable 6" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " [5] ,Half block complete interrupt enable 5" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " [4] ,Half block complete interrupt enable 4" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 3. " [3] ,Half block complete interrupt enable 3" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " [2] ,Half block complete interrupt enable 2" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " [1] ,Half block complete interrupt enable 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,Half block complete interrupt enable 0" "Disabled,Enabled"
|
|
group.long 0x104++0x03
|
|
line.long 0x00 "HBCINTENAR,HBC Interrupt Enable Reset"
|
|
bitfld.long 0x00 15. " HBCINTDIS[15] ,Half block complete interrupt disable 15" "No effect,Reset"
|
|
bitfld.long 0x00 14. " [14] ,Half block complete interrupt disable 14" "No effect,Reset"
|
|
bitfld.long 0x00 13. " [13] ,Half block complete interrupt disable 13" "No effect,Reset"
|
|
bitfld.long 0x00 12. " [12] ,Half block complete interrupt disable 12" "No effect,Reset"
|
|
newline
|
|
bitfld.long 0x00 11. " [11] ,Half block complete interrupt disable 11" "No effect,Reset"
|
|
bitfld.long 0x00 10. " [10] ,Half block complete interrupt disable 10" "No effect,Reset"
|
|
bitfld.long 0x00 9. " [9] ,Half block complete interrupt disable 9" "No effect,Reset"
|
|
bitfld.long 0x00 8. " [8] ,Half block complete interrupt disable 8" "No effect,Reset"
|
|
newline
|
|
bitfld.long 0x00 7. " [7] ,Half block complete interrupt disable 7" "No effect,Reset"
|
|
bitfld.long 0x00 6. " [6] ,Half block complete interrupt disable 6" "No effect,Reset"
|
|
bitfld.long 0x00 5. " [5] ,Half block complete interrupt disable 5" "No effect,Reset"
|
|
bitfld.long 0x00 4. " [4] ,Half block complete interrupt disable 4" "No effect,Reset"
|
|
newline
|
|
bitfld.long 0x00 3. " [3] ,Half block complete interrupt disable 3" "No effect,Reset"
|
|
bitfld.long 0x00 2. " [2] ,Half block complete interrupt disable 2" "No effect,Reset"
|
|
bitfld.long 0x00 1. " [1] ,Half block complete interrupt disable 1" "No effect,Reset"
|
|
bitfld.long 0x00 0. " [0] ,Half block complete interrupt disable 0" "No effect,Reset"
|
|
group.long 0x10C++0x03
|
|
line.long 0x00 "BTCINTENAS,BTC Interrupt Enable Set"
|
|
bitfld.long 0x00 15. " BTCINTENA[15] ,Block transfer complete interrupt enable 15" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " [14] ,Block transfer complete interrupt enable 14" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " [13] ,Block transfer complete interrupt enable 13" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " [12] ,Block transfer complete interrupt enable 12" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 11. " [11] ,Block transfer complete interrupt enable 11" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " [10] ,Block transfer complete interrupt enable 10" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " [9] ,Block transfer complete interrupt enable 9" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " [8] ,Block transfer complete interrupt enable 8" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 7. " [7] ,Block transfer complete interrupt enable 7" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " [6] ,Block transfer complete interrupt enable 6" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " [5] ,Block transfer complete interrupt enable 5" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " [4] ,Block transfer complete interrupt enable 4" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 3. " [3] ,Block transfer complete interrupt enable 3" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " [2] ,Block transfer complete interrupt enable 2" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " [1] ,Block transfer complete interrupt enable 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,Block transfer complete interrupt enable 0" "Disabled,Enabled"
|
|
group.long 0x114++0x03
|
|
line.long 0x00 "BTCINTENAR,BTC Interrupt Enable Reset"
|
|
bitfld.long 0x00 15. " BTCINTDIS[15] ,Block transfer complete interrupt disable 15" "No effect,Reset"
|
|
bitfld.long 0x00 14. " [14] ,Block transfer complete interrupt disable 14" "No effect,Reset"
|
|
bitfld.long 0x00 13. " [13] ,Block transfer complete interrupt disable 13" "No effect,Reset"
|
|
bitfld.long 0x00 12. " [12] ,Block transfer complete interrupt disable 12" "No effect,Reset"
|
|
newline
|
|
bitfld.long 0x00 11. " [11] ,Block transfer complete interrupt disable 11" "No effect,Reset"
|
|
bitfld.long 0x00 10. " [10] ,Block transfer complete interrupt disable 10" "No effect,Reset"
|
|
bitfld.long 0x00 9. " [9] ,Block transfer complete interrupt disable 9" "No effect,Reset"
|
|
bitfld.long 0x00 8. " [8] ,Block transfer complete interrupt disable 8" "No effect,Reset"
|
|
newline
|
|
bitfld.long 0x00 7. " [7] ,Block transfer complete interrupt disable 7" "No effect,Reset"
|
|
bitfld.long 0x00 6. " [6] ,Block transfer complete interrupt disable 6" "No effect,Reset"
|
|
bitfld.long 0x00 5. " [5] ,Block transfer complete interrupt disable 5" "No effect,Reset"
|
|
bitfld.long 0x00 4. " [4] ,Block transfer complete interrupt disable 4" "No effect,Reset"
|
|
newline
|
|
bitfld.long 0x00 3. " [3] ,Block transfer complete interrupt disable 3" "No effect,Reset"
|
|
bitfld.long 0x00 2. " [2] ,Block transfer complete interrupt disable 2" "No effect,Reset"
|
|
bitfld.long 0x00 1. " [1] ,Block transfer complete interrupt disable 1" "No effect,Reset"
|
|
bitfld.long 0x00 0. " [0] ,Block transfer complete interrupt disable 0" "No effect,Reset"
|
|
tree.end
|
|
tree "Interrupt Flag Registers"
|
|
group.long 0x11C++0x03
|
|
line.long 0x00 "GINTFLAG,Global Interrupt Flag Register"
|
|
bitfld.long 0x00 15. " GINT[15] ,Global interrupt flag 15" "Not pending,Pending"
|
|
bitfld.long 0x00 14. " [14] ,Global interrupt flag 14" "Not pending,Pending"
|
|
bitfld.long 0x00 13. " [13] ,Global interrupt flag 13" "Not pending,Pending"
|
|
bitfld.long 0x00 12. " [12] ,Global interrupt flag 12" "Not pending,Pending"
|
|
newline
|
|
bitfld.long 0x00 11. " [11] ,Global interrupt flag 11" "Not pending,Pending"
|
|
bitfld.long 0x00 10. " [10] ,Global interrupt flag 10" "Not pending,Pending"
|
|
bitfld.long 0x00 9. " [9] ,Global interrupt flag 9" "Not pending,Pending"
|
|
bitfld.long 0x00 8. " [8] ,Global interrupt flag 8" "Not pending,Pending"
|
|
newline
|
|
bitfld.long 0x00 7. " [7] ,Global interrupt flag 7" "Not pending,Pending"
|
|
bitfld.long 0x00 6. " [6] ,Global interrupt flag 6" "Not pending,Pending"
|
|
bitfld.long 0x00 5. " [5] ,Global interrupt flag 5" "Not pending,Pending"
|
|
bitfld.long 0x00 4. " [4] ,Global interrupt flag 4" "Not pending,Pending"
|
|
newline
|
|
bitfld.long 0x00 3. " [3] ,Global interrupt flag 3" "Not pending,Pending"
|
|
bitfld.long 0x00 2. " [2] ,Global interrupt flag 2" "Not pending,Pending"
|
|
bitfld.long 0x00 1. " [1] ,Global interrupt flag 1" "Not pending,Pending"
|
|
bitfld.long 0x00 0. " [0] ,Global interrupt flag 0" "Not pending,Pending"
|
|
group.long 0x124++0x03
|
|
line.long 0x00 "FTCFLAG,FTC Interrupt Flag Register"
|
|
eventfld.long 0x00 15. " FTCI[15] ,Frame transfer complete flag 15" "Not pending,Pending"
|
|
eventfld.long 0x00 14. " [14] ,Frame transfer complete flag 14" "Not pending,Pending"
|
|
eventfld.long 0x00 13. " [13] ,Frame transfer complete flag 13" "Not pending,Pending"
|
|
eventfld.long 0x00 12. " [12] ,Frame transfer complete flag 12" "Not pending,Pending"
|
|
newline
|
|
eventfld.long 0x00 11. " [11] ,Frame transfer complete flag 11" "Not pending,Pending"
|
|
eventfld.long 0x00 10. " [10] ,Frame transfer complete flag 10" "Not pending,Pending"
|
|
eventfld.long 0x00 9. " [9] ,Frame transfer complete flag 9" "Not pending,Pending"
|
|
eventfld.long 0x00 8. " [8] ,Frame transfer complete flag 8" "Not pending,Pending"
|
|
newline
|
|
eventfld.long 0x00 7. " [7] ,Frame transfer complete flag 7" "Not pending,Pending"
|
|
eventfld.long 0x00 6. " [6] ,Frame transfer complete flag 6" "Not pending,Pending"
|
|
eventfld.long 0x00 5. " [5] ,Frame transfer complete flag 5" "Not pending,Pending"
|
|
eventfld.long 0x00 4. " [4] ,Frame transfer complete flag 4" "Not pending,Pending"
|
|
newline
|
|
eventfld.long 0x00 3. " [3] ,Frame transfer complete flag 3" "Not pending,Pending"
|
|
eventfld.long 0x00 2. " [2] ,Frame transfer complete flag 2" "Not pending,Pending"
|
|
eventfld.long 0x00 1. " [1] ,Frame transfer complete flag 1" "Not pending,Pending"
|
|
eventfld.long 0x00 0. " [0] ,Frame transfer complete flag 0" "Not pending,Pending"
|
|
group.long 0x12C++0x03
|
|
line.long 0x00 "LFSFLAG,LFS Interrupt Flag Register"
|
|
eventfld.long 0x00 15. " LFSI[15] ,Last frame transfer started flag 15" "Not pending,Pending"
|
|
eventfld.long 0x00 14. " [14] ,Last frame transfer started flag 14" "Not pending,Pending"
|
|
eventfld.long 0x00 13. " [13] ,Last frame transfer started flag 13" "Not pending,Pending"
|
|
eventfld.long 0x00 12. " [12] ,Last frame transfer started flag 12" "Not pending,Pending"
|
|
newline
|
|
eventfld.long 0x00 11. " [11] ,Last frame transfer started flag 11" "Not pending,Pending"
|
|
eventfld.long 0x00 10. " [10] ,Last frame transfer started flag 10" "Not pending,Pending"
|
|
eventfld.long 0x00 9. " [9] ,Last frame transfer started flag 9" "Not pending,Pending"
|
|
eventfld.long 0x00 8. " [8] ,Last frame transfer started flag 8" "Not pending,Pending"
|
|
newline
|
|
eventfld.long 0x00 7. " [7] ,Last frame transfer started flag 7" "Not pending,Pending"
|
|
eventfld.long 0x00 6. " [6] ,Last frame transfer started flag 6" "Not pending,Pending"
|
|
eventfld.long 0x00 5. " [5] ,Last frame transfer started flag 5" "Not pending,Pending"
|
|
eventfld.long 0x00 4. " [4] ,Last frame transfer started flag 4" "Not pending,Pending"
|
|
newline
|
|
eventfld.long 0x00 3. " [3] ,Last frame transfer started flag 3" "Not pending,Pending"
|
|
eventfld.long 0x00 2. " [2] ,Last frame transfer started flag 2" "Not pending,Pending"
|
|
eventfld.long 0x00 1. " [1] ,Last frame transfer started flag 1" "Not pending,Pending"
|
|
eventfld.long 0x00 0. " [0] ,Last frame transfer started flag 0" "Not pending,Pending"
|
|
group.long 0x134++0x03
|
|
line.long 0x00 "HBCFLAG,HBC Interrupt Flag Register"
|
|
eventfld.long 0x00 15. " HBCI[15] ,Half of block transfer complete flag 15" "Not pending,Pending"
|
|
eventfld.long 0x00 14. " [14] ,Half of block transfer complete flag 14" "Not pending,Pending"
|
|
eventfld.long 0x00 13. " [13] ,Half of block transfer complete flag 13" "Not pending,Pending"
|
|
eventfld.long 0x00 12. " [12] ,Half of block transfer complete flag 12" "Not pending,Pending"
|
|
newline
|
|
eventfld.long 0x00 11. " [11] ,Half of block transfer complete flag 11" "Not pending,Pending"
|
|
eventfld.long 0x00 10. " [10] ,Half of block transfer complete flag 10" "Not pending,Pending"
|
|
eventfld.long 0x00 9. " [9] ,Half of block transfer complete flag 9" "Not pending,Pending"
|
|
eventfld.long 0x00 8. " [8] ,Half of block transfer complete flag 8" "Not pending,Pending"
|
|
newline
|
|
eventfld.long 0x00 7. " [7] ,Half of block transfer complete flag 7" "Not pending,Pending"
|
|
eventfld.long 0x00 6. " [6] ,Half of block transfer complete flag 6" "Not pending,Pending"
|
|
eventfld.long 0x00 5. " [5] ,Half of block transfer complete flag 5" "Not pending,Pending"
|
|
eventfld.long 0x00 4. " [4] ,Half of block transfer complete flag 4" "Not pending,Pending"
|
|
newline
|
|
eventfld.long 0x00 3. " [3] ,Half of block transfer complete flag 3" "Not pending,Pending"
|
|
eventfld.long 0x00 2. " [2] ,Half of block transfer complete flag 2" "Not pending,Pending"
|
|
eventfld.long 0x00 1. " [1] ,Half of block transfer complete flag 1" "Not pending,Pending"
|
|
eventfld.long 0x00 0. " [0] ,Half of block transfer complete flag 0" "Not pending,Pending"
|
|
group.long 0x13C++0x03
|
|
line.long 0x00 "BTCFLAG,BER Interrupt Flag Register"
|
|
eventfld.long 0x00 15. " BTCI[15] ,Block transfer complete flag 15" "Not pending,Pending"
|
|
eventfld.long 0x00 14. " [14] ,Block transfer complete flag 14" "Not pending,Pending"
|
|
eventfld.long 0x00 13. " [13] ,Block transfer complete flag 13" "Not pending,Pending"
|
|
eventfld.long 0x00 12. " [12] ,Block transfer complete flag 12" "Not pending,Pending"
|
|
newline
|
|
eventfld.long 0x00 11. " [11] ,Block transfer complete flag 11" "Not pending,Pending"
|
|
eventfld.long 0x00 10. " [10] ,Block transfer complete flag 10" "Not pending,Pending"
|
|
eventfld.long 0x00 9. " [9] ,Block transfer complete flag 9" "Not pending,Pending"
|
|
eventfld.long 0x00 8. " [8] ,Block transfer complete flag 8" "Not pending,Pending"
|
|
newline
|
|
eventfld.long 0x00 7. " [7] ,Block transfer complete flag 7" "Not pending,Pending"
|
|
eventfld.long 0x00 6. " [6] ,Block transfer complete flag 6" "Not pending,Pending"
|
|
eventfld.long 0x00 5. " [5] ,Block transfer complete flag 5" "Not pending,Pending"
|
|
eventfld.long 0x00 4. " [4] ,Block transfer complete flag 4" "Not pending,Pending"
|
|
newline
|
|
eventfld.long 0x00 3. " [3] ,Block transfer complete flag 3" "Not pending,Pending"
|
|
eventfld.long 0x00 2. " [2] ,Block transfer complete flag 2" "Not pending,Pending"
|
|
eventfld.long 0x00 1. " [1] ,Block transfer complete flag 1" "Not pending,Pending"
|
|
eventfld.long 0x00 0. " [0] ,Block transfer complete flag 0" "Not pending,Pending"
|
|
hgroup.long 0x144++0x03
|
|
hide.long 0x00 "BERFLAG,BER Interrupt Flag Register"
|
|
tree.end
|
|
tree "Interrupt Channel Offset Registers"
|
|
hgroup.long 0x14C++0x03
|
|
hide.long 0x00 "FTCAOFFSET,FTCA Interrupt Channel Offset Register"
|
|
in
|
|
hgroup.long 0x150++0x03
|
|
hide.long 0x00 "LFSAOFFSET,LFSA Interrupt Channel Offset Register"
|
|
in
|
|
hgroup.long 0x154++0x03
|
|
hide.long 0x00 "HBCAOFFSET,HBCA Interrupt Channel Offset Register"
|
|
in
|
|
hgroup.long 0x158++0x03
|
|
hide.long 0x00 "BTCAOFFSET,BTCA Interrupt Channel Offset Register"
|
|
in
|
|
hgroup.long 0x160++0x03
|
|
hide.long 0x00 "FTCBOFFSET,FTCB Interrupt Channel Offset Register"
|
|
in
|
|
hgroup.long 0x164++0x03
|
|
hide.long 0x00 "LSFBOFFSET,LFSB Interrupt Channel Offset Register"
|
|
in
|
|
hgroup.long 0x168++0x03
|
|
hide.long 0x00 "HBCBOFFSET,HBCB Interrupt Channel Offset Register"
|
|
in
|
|
hgroup.long 0x16C++0x03
|
|
hide.long 0x00 "BTCBOFFSET,BTCB Interrupt Channel Offset Register"
|
|
in
|
|
tree.end
|
|
newline
|
|
group.long 0x178++0x13
|
|
line.long 0x00 "PTCRL,Port Control Register"
|
|
bitfld.long 0x00 24. " PENDB ,Port B transactions pending" "Not pending,Pending"
|
|
bitfld.long 0x00 18. " BYB ,Bypass FIFO B" "Not bypassed,Bypassed"
|
|
newline
|
|
bitfld.long 0x00 17. " PSFRHQPB ,Port B high priority queue priority scheme" "Fixed,Rotated"
|
|
bitfld.long 0x00 16. " PSFRLQPB ,Port B low priority queue priority scheme" "Fixed,Rotated"
|
|
line.long 0x04 "RTCTRL,Ram Test Control"
|
|
bitfld.long 0x04 0. " RTC ,RAM test control enable" "Disabled,Enabled"
|
|
line.long 0x08 "DCTRL,Debug Control"
|
|
bitfld.long 0x08 24.--28. " CHNUM ,Channel number" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,Channel 8,Channel 9,Channel 10,Channel 11,Channel 12,Channel 13,Channel 14,Channel 15,?..."
|
|
eventfld.long 0x08 16. " DMADBGS ,DMA debug status" "Not detected,Detected"
|
|
bitfld.long 0x08 0. " DBGEN ,Debug enable" "Disabled,Enabled"
|
|
line.long 0x0C "WPR,Watch Point Register"
|
|
line.long 0x10 "WMR,Watch Mask Register"
|
|
bitfld.long 0x10 31. " WM ,Watch mask 31" "0,1"
|
|
bitfld.long 0x10 30. ",Watch mask 30" "0,1"
|
|
bitfld.long 0x10 29. ",Watch mask 29" "0,1"
|
|
bitfld.long 0x10 28. ",Watch mask 28" "0,1"
|
|
bitfld.long 0x10 27. ",Watch mask 27" "0,1"
|
|
bitfld.long 0x10 26. ",Watch mask 26" "0,1"
|
|
bitfld.long 0x10 25. ",Watch mask 25" "0,1"
|
|
bitfld.long 0x10 24. ",Watch mask 24" "0,1"
|
|
bitfld.long 0x10 23. ",Watch mask 23" "0,1"
|
|
bitfld.long 0x10 22. ",Watch mask 22" "0,1"
|
|
bitfld.long 0x10 21. ",Watch mask 21" "0,1"
|
|
bitfld.long 0x10 20. ",Watch mask 20" "0,1"
|
|
bitfld.long 0x10 19. ",Watch mask 19" "0,1"
|
|
bitfld.long 0x10 18. ",Watch mask 18" "0,1"
|
|
bitfld.long 0x10 17. ",Watch mask 17" "0,1"
|
|
bitfld.long 0x10 16. ",Watch mask 16" "0,1"
|
|
bitfld.long 0x10 15. ",Watch mask 15" "0,1"
|
|
bitfld.long 0x10 14. ",Watch mask 14" "0,1"
|
|
bitfld.long 0x10 13. ",Watch mask 13" "0,1"
|
|
bitfld.long 0x10 12. ",Watch mask 12" "0,1"
|
|
bitfld.long 0x10 11. ",Watch mask 11" "0,1"
|
|
bitfld.long 0x10 10. ",Watch mask 10" "0,1"
|
|
bitfld.long 0x10 9. ",Watch mask 9" "0,1"
|
|
bitfld.long 0x10 8. ",Watch mask 8" "0,1"
|
|
bitfld.long 0x10 7. ",Watch mask 7" "0,1"
|
|
bitfld.long 0x10 6. ",Watch mask 6" "0,1"
|
|
bitfld.long 0x10 5. ",Watch mask 5" "0,1"
|
|
bitfld.long 0x10 4. ",Watch mask 4" "0,1"
|
|
bitfld.long 0x10 3. ",Watch mask 3" "0,1"
|
|
bitfld.long 0x10 2. ",Watch mask 2" "0,1"
|
|
bitfld.long 0x10 1. ",Watch mask 1" "0,1"
|
|
bitfld.long 0x10 0. ",Watch mask 0" "0,1"
|
|
tree "Active Channel Registers"
|
|
rgroup.long 0x198++0x0B
|
|
line.long 0x00 "PBACSADDR,Port B Active Channel Source Address Register"
|
|
line.long 0x04 "PBACDADDR,Port B Active Channel Destination Address Register"
|
|
line.long 0x08 "PBACTC,Port B Active Channel Transfer Count Register"
|
|
hexmask.long.word 0x08 16.--28. 1. " PBFTCOUNT ,Port B Active Channel Frame Count"
|
|
hexmask.long.word 0x08 0.--12. 1. " PBETCOUNT ,Port B Active Channel Element Count"
|
|
tree.end
|
|
newline
|
|
group.long 0x1A8++0x07
|
|
line.long 0x00 "DMAPCR,Parity Control Register"
|
|
bitfld.long 0x00 16. " ERRA ,Error action" "Unchanged,Disabled"
|
|
bitfld.long 0x00 8. " TEST ,Test" "Not mapped,Mapped"
|
|
bitfld.long 0x00 0.--3. " PARITY_ENA ,Parity error detection enable" "Enabled,Enabled,Enabled,Enabled,Enabled,Disabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled"
|
|
line.long 0x04 "DMAPAR,Parity Error Address Register"
|
|
eventfld.long 0x04 24. " EDFLG ,Parity error detection flag" "No error,Error"
|
|
hexmask.long.word 0x04 0.--11. 0x01 " ERROR_ADDRESS ,Error address"
|
|
tree "DMA Memory Protection Registers"
|
|
group.long 0x1B0++0x27
|
|
line.long 0x00 "DMAMPCTRL,Memory Protection Control Register"
|
|
bitfld.long 0x00 28. " INT3AB ,Interrupt assignment of region 3 to group A/B" "Group A,Group B"
|
|
bitfld.long 0x00 27. " INT3ENA ,Interrupt enable of region 3" "Disabled,Enabled"
|
|
bitfld.long 0x00 25.--26. " REG3AP ,Region 3 access permission" "R/W,Read,Write,Not allowed"
|
|
bitfld.long 0x00 24. " REG3ENA ,Region 3 enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 20. " INT2AB ,Interrupt assignment of region 2 to group A/B" "Group A,Group B"
|
|
bitfld.long 0x00 19. " INT2ENA ,Interrupt enable of region 2" "Disabled,Enabled"
|
|
bitfld.long 0x00 17.--18. " REG2AP ,Region 2 access permission" "R/W,Read,Write,Not allowed"
|
|
bitfld.long 0x00 16. " REG2ENA ,Region 2 enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 12. " INT1AB ,Interrupt assignment of region 1 to group A/B" "Group A,Group B"
|
|
bitfld.long 0x00 11. " INT1ENA ,Interrupt enable of region 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 9.--10. " REG1AP ,Region 1 access permission" "R/W,Read,Write,Not allowed"
|
|
bitfld.long 0x00 8. " REG1ENA ,Region 1 enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 4. " INT0AB ,Interrupt assignment of region 0 to group A/B" "Group A,Group B"
|
|
bitfld.long 0x00 3. " INT0ENA ,Interrupt enable of region 0" "Disabled,Enabled"
|
|
bitfld.long 0x00 1.--2. " REG0AP ,Region 0 access permission" "R/W,Read,Write,Not allowed"
|
|
bitfld.long 0x00 0. " REG0ENA ,Region 0 enable" "Disabled,Enabled"
|
|
line.long 0x04 "DMAMPST,Memory Protection Status Register"
|
|
eventfld.long 0x04 24. " REG3FT ,Region 3 fault" "Not detected,Detected"
|
|
eventfld.long 0x04 16. " REG2FT ,Region 2 fault" "Not detected,Detected"
|
|
eventfld.long 0x04 8. " REG1FT ,Region 1 fault" "Not detected,Detected"
|
|
eventfld.long 0x04 0. " REG0FT ,Region 0 fault" "Not detected,Detected"
|
|
line.long 0x08 "DMAPR0S,Defines Starting Address of Region 0"
|
|
line.long 0x0C "DMAPR0E,Defines end Address of Region 0"
|
|
line.long 0x10 "DMAPR1S,Defines Starting Address of Region 1"
|
|
line.long 0x14 "DMAPR1E,Defines end Address of Region 1"
|
|
line.long 0x18 "DMAPR2S,Defines Starting Address of Region 2"
|
|
line.long 0x1C "DMAPR2E,Defines end Address of Region 2"
|
|
line.long 0x20 "DMAPR3S,Defines Starting Address of Region 3"
|
|
line.long 0x24 "DMAPR3E,Defines end Address of Region 3"
|
|
tree.end
|
|
base ad:0xFFF80000
|
|
tree "Control Packet Registers"
|
|
tree.open "Primary Control Packet Registers"
|
|
tree "Primary Control Packet 0"
|
|
group.long (0x0)++0x0B
|
|
line.long 0x00 "ISADDR,Initial Source Address Register"
|
|
line.long 0x04 "IDADDR,Initial Destination Address Register"
|
|
line.long 0x08 "ITCOUNT,Initial Transfer Count Register"
|
|
hexmask.long.word 0x08 16.--28. 1. " IFTCOUNT ,Initial frame transfer count"
|
|
hexmask.long.word 0x08 0.--12. 1. " IETCOUNT ,Initial element transfer count"
|
|
group.long (0x0+0x10)++0x0B
|
|
line.long 0x00 "CHCTRL,Channel Control Register"
|
|
bitfld.long 0x00 16.--21. " CHAIN ,Next channel to be triggered" "No channel,Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,Channel 8,Channel 9,Channel 10,Channel 11,Channel 12,Channel 13,Channel 14,Channel 15,?..."
|
|
bitfld.long 0x00 14.--15. " RES ,Read element size" "8 bits,16 bits,32 bits,64 bits"
|
|
bitfld.long 0x00 12.--13. " WES ,Write element size" "8 bits,16 bits,32 bits,64 bits"
|
|
newline
|
|
bitfld.long 0x00 8. " TTYPE ,Transfer type" "Frame,Block"
|
|
bitfld.long 0x00 3.--4. " ADDMR ,Addressing mode read" "Constant,Post-increment,,Indexed"
|
|
newline
|
|
bitfld.long 0x00 1.--2. " ADDMW ,Addressing mode write" "Constant,Post-increment,,Indexed"
|
|
bitfld.long 0x00 0. " AIM ,Autoinitiation mode enable" "Disabled,Enabled"
|
|
line.long 0x04 "EIOFF,Element Index Offset Register"
|
|
hexmask.long.word 0x04 16.--28. 1. " EIDXD ,Destination address element index"
|
|
hexmask.long.word 0x04 0.--12. 1. " EIDXS ,Source address element index"
|
|
line.long 0x08 "FIOFF,Frame Index Offset Register"
|
|
hexmask.long.word 0x08 16.--28. 1. " FIDXD ,Destination address frame index"
|
|
hexmask.long.word 0x08 0.--12. 1. " FIDXS ,Source address frame index"
|
|
tree.end
|
|
tree "Primary Control Packet 1"
|
|
group.long (0x20)++0x0B
|
|
line.long 0x00 "ISADDR,Initial Source Address Register"
|
|
line.long 0x04 "IDADDR,Initial Destination Address Register"
|
|
line.long 0x08 "ITCOUNT,Initial Transfer Count Register"
|
|
hexmask.long.word 0x08 16.--28. 1. " IFTCOUNT ,Initial frame transfer count"
|
|
hexmask.long.word 0x08 0.--12. 1. " IETCOUNT ,Initial element transfer count"
|
|
group.long (0x20+0x10)++0x0B
|
|
line.long 0x00 "CHCTRL,Channel Control Register"
|
|
bitfld.long 0x00 16.--21. " CHAIN ,Next channel to be triggered" "No channel,Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,Channel 8,Channel 9,Channel 10,Channel 11,Channel 12,Channel 13,Channel 14,Channel 15,?..."
|
|
bitfld.long 0x00 14.--15. " RES ,Read element size" "8 bits,16 bits,32 bits,64 bits"
|
|
bitfld.long 0x00 12.--13. " WES ,Write element size" "8 bits,16 bits,32 bits,64 bits"
|
|
newline
|
|
bitfld.long 0x00 8. " TTYPE ,Transfer type" "Frame,Block"
|
|
bitfld.long 0x00 3.--4. " ADDMR ,Addressing mode read" "Constant,Post-increment,,Indexed"
|
|
newline
|
|
bitfld.long 0x00 1.--2. " ADDMW ,Addressing mode write" "Constant,Post-increment,,Indexed"
|
|
bitfld.long 0x00 0. " AIM ,Autoinitiation mode enable" "Disabled,Enabled"
|
|
line.long 0x04 "EIOFF,Element Index Offset Register"
|
|
hexmask.long.word 0x04 16.--28. 1. " EIDXD ,Destination address element index"
|
|
hexmask.long.word 0x04 0.--12. 1. " EIDXS ,Source address element index"
|
|
line.long 0x08 "FIOFF,Frame Index Offset Register"
|
|
hexmask.long.word 0x08 16.--28. 1. " FIDXD ,Destination address frame index"
|
|
hexmask.long.word 0x08 0.--12. 1. " FIDXS ,Source address frame index"
|
|
tree.end
|
|
tree "Primary Control Packet 2"
|
|
group.long (0x40)++0x0B
|
|
line.long 0x00 "ISADDR,Initial Source Address Register"
|
|
line.long 0x04 "IDADDR,Initial Destination Address Register"
|
|
line.long 0x08 "ITCOUNT,Initial Transfer Count Register"
|
|
hexmask.long.word 0x08 16.--28. 1. " IFTCOUNT ,Initial frame transfer count"
|
|
hexmask.long.word 0x08 0.--12. 1. " IETCOUNT ,Initial element transfer count"
|
|
group.long (0x40+0x10)++0x0B
|
|
line.long 0x00 "CHCTRL,Channel Control Register"
|
|
bitfld.long 0x00 16.--21. " CHAIN ,Next channel to be triggered" "No channel,Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,Channel 8,Channel 9,Channel 10,Channel 11,Channel 12,Channel 13,Channel 14,Channel 15,?..."
|
|
bitfld.long 0x00 14.--15. " RES ,Read element size" "8 bits,16 bits,32 bits,64 bits"
|
|
bitfld.long 0x00 12.--13. " WES ,Write element size" "8 bits,16 bits,32 bits,64 bits"
|
|
newline
|
|
bitfld.long 0x00 8. " TTYPE ,Transfer type" "Frame,Block"
|
|
bitfld.long 0x00 3.--4. " ADDMR ,Addressing mode read" "Constant,Post-increment,,Indexed"
|
|
newline
|
|
bitfld.long 0x00 1.--2. " ADDMW ,Addressing mode write" "Constant,Post-increment,,Indexed"
|
|
bitfld.long 0x00 0. " AIM ,Autoinitiation mode enable" "Disabled,Enabled"
|
|
line.long 0x04 "EIOFF,Element Index Offset Register"
|
|
hexmask.long.word 0x04 16.--28. 1. " EIDXD ,Destination address element index"
|
|
hexmask.long.word 0x04 0.--12. 1. " EIDXS ,Source address element index"
|
|
line.long 0x08 "FIOFF,Frame Index Offset Register"
|
|
hexmask.long.word 0x08 16.--28. 1. " FIDXD ,Destination address frame index"
|
|
hexmask.long.word 0x08 0.--12. 1. " FIDXS ,Source address frame index"
|
|
tree.end
|
|
tree "Primary Control Packet 3"
|
|
group.long (0x60)++0x0B
|
|
line.long 0x00 "ISADDR,Initial Source Address Register"
|
|
line.long 0x04 "IDADDR,Initial Destination Address Register"
|
|
line.long 0x08 "ITCOUNT,Initial Transfer Count Register"
|
|
hexmask.long.word 0x08 16.--28. 1. " IFTCOUNT ,Initial frame transfer count"
|
|
hexmask.long.word 0x08 0.--12. 1. " IETCOUNT ,Initial element transfer count"
|
|
group.long (0x60+0x10)++0x0B
|
|
line.long 0x00 "CHCTRL,Channel Control Register"
|
|
bitfld.long 0x00 16.--21. " CHAIN ,Next channel to be triggered" "No channel,Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,Channel 8,Channel 9,Channel 10,Channel 11,Channel 12,Channel 13,Channel 14,Channel 15,?..."
|
|
bitfld.long 0x00 14.--15. " RES ,Read element size" "8 bits,16 bits,32 bits,64 bits"
|
|
bitfld.long 0x00 12.--13. " WES ,Write element size" "8 bits,16 bits,32 bits,64 bits"
|
|
newline
|
|
bitfld.long 0x00 8. " TTYPE ,Transfer type" "Frame,Block"
|
|
bitfld.long 0x00 3.--4. " ADDMR ,Addressing mode read" "Constant,Post-increment,,Indexed"
|
|
newline
|
|
bitfld.long 0x00 1.--2. " ADDMW ,Addressing mode write" "Constant,Post-increment,,Indexed"
|
|
bitfld.long 0x00 0. " AIM ,Autoinitiation mode enable" "Disabled,Enabled"
|
|
line.long 0x04 "EIOFF,Element Index Offset Register"
|
|
hexmask.long.word 0x04 16.--28. 1. " EIDXD ,Destination address element index"
|
|
hexmask.long.word 0x04 0.--12. 1. " EIDXS ,Source address element index"
|
|
line.long 0x08 "FIOFF,Frame Index Offset Register"
|
|
hexmask.long.word 0x08 16.--28. 1. " FIDXD ,Destination address frame index"
|
|
hexmask.long.word 0x08 0.--12. 1. " FIDXS ,Source address frame index"
|
|
tree.end
|
|
tree "Primary Control Packet 4"
|
|
group.long (0x80)++0x0B
|
|
line.long 0x00 "ISADDR,Initial Source Address Register"
|
|
line.long 0x04 "IDADDR,Initial Destination Address Register"
|
|
line.long 0x08 "ITCOUNT,Initial Transfer Count Register"
|
|
hexmask.long.word 0x08 16.--28. 1. " IFTCOUNT ,Initial frame transfer count"
|
|
hexmask.long.word 0x08 0.--12. 1. " IETCOUNT ,Initial element transfer count"
|
|
group.long (0x80+0x10)++0x0B
|
|
line.long 0x00 "CHCTRL,Channel Control Register"
|
|
bitfld.long 0x00 16.--21. " CHAIN ,Next channel to be triggered" "No channel,Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,Channel 8,Channel 9,Channel 10,Channel 11,Channel 12,Channel 13,Channel 14,Channel 15,?..."
|
|
bitfld.long 0x00 14.--15. " RES ,Read element size" "8 bits,16 bits,32 bits,64 bits"
|
|
bitfld.long 0x00 12.--13. " WES ,Write element size" "8 bits,16 bits,32 bits,64 bits"
|
|
newline
|
|
bitfld.long 0x00 8. " TTYPE ,Transfer type" "Frame,Block"
|
|
bitfld.long 0x00 3.--4. " ADDMR ,Addressing mode read" "Constant,Post-increment,,Indexed"
|
|
newline
|
|
bitfld.long 0x00 1.--2. " ADDMW ,Addressing mode write" "Constant,Post-increment,,Indexed"
|
|
bitfld.long 0x00 0. " AIM ,Autoinitiation mode enable" "Disabled,Enabled"
|
|
line.long 0x04 "EIOFF,Element Index Offset Register"
|
|
hexmask.long.word 0x04 16.--28. 1. " EIDXD ,Destination address element index"
|
|
hexmask.long.word 0x04 0.--12. 1. " EIDXS ,Source address element index"
|
|
line.long 0x08 "FIOFF,Frame Index Offset Register"
|
|
hexmask.long.word 0x08 16.--28. 1. " FIDXD ,Destination address frame index"
|
|
hexmask.long.word 0x08 0.--12. 1. " FIDXS ,Source address frame index"
|
|
tree.end
|
|
tree "Primary Control Packet 5"
|
|
group.long (0xA0)++0x0B
|
|
line.long 0x00 "ISADDR,Initial Source Address Register"
|
|
line.long 0x04 "IDADDR,Initial Destination Address Register"
|
|
line.long 0x08 "ITCOUNT,Initial Transfer Count Register"
|
|
hexmask.long.word 0x08 16.--28. 1. " IFTCOUNT ,Initial frame transfer count"
|
|
hexmask.long.word 0x08 0.--12. 1. " IETCOUNT ,Initial element transfer count"
|
|
group.long (0xA0+0x10)++0x0B
|
|
line.long 0x00 "CHCTRL,Channel Control Register"
|
|
bitfld.long 0x00 16.--21. " CHAIN ,Next channel to be triggered" "No channel,Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,Channel 8,Channel 9,Channel 10,Channel 11,Channel 12,Channel 13,Channel 14,Channel 15,?..."
|
|
bitfld.long 0x00 14.--15. " RES ,Read element size" "8 bits,16 bits,32 bits,64 bits"
|
|
bitfld.long 0x00 12.--13. " WES ,Write element size" "8 bits,16 bits,32 bits,64 bits"
|
|
newline
|
|
bitfld.long 0x00 8. " TTYPE ,Transfer type" "Frame,Block"
|
|
bitfld.long 0x00 3.--4. " ADDMR ,Addressing mode read" "Constant,Post-increment,,Indexed"
|
|
newline
|
|
bitfld.long 0x00 1.--2. " ADDMW ,Addressing mode write" "Constant,Post-increment,,Indexed"
|
|
bitfld.long 0x00 0. " AIM ,Autoinitiation mode enable" "Disabled,Enabled"
|
|
line.long 0x04 "EIOFF,Element Index Offset Register"
|
|
hexmask.long.word 0x04 16.--28. 1. " EIDXD ,Destination address element index"
|
|
hexmask.long.word 0x04 0.--12. 1. " EIDXS ,Source address element index"
|
|
line.long 0x08 "FIOFF,Frame Index Offset Register"
|
|
hexmask.long.word 0x08 16.--28. 1. " FIDXD ,Destination address frame index"
|
|
hexmask.long.word 0x08 0.--12. 1. " FIDXS ,Source address frame index"
|
|
tree.end
|
|
tree "Primary Control Packet 6"
|
|
group.long (0xC0)++0x0B
|
|
line.long 0x00 "ISADDR,Initial Source Address Register"
|
|
line.long 0x04 "IDADDR,Initial Destination Address Register"
|
|
line.long 0x08 "ITCOUNT,Initial Transfer Count Register"
|
|
hexmask.long.word 0x08 16.--28. 1. " IFTCOUNT ,Initial frame transfer count"
|
|
hexmask.long.word 0x08 0.--12. 1. " IETCOUNT ,Initial element transfer count"
|
|
group.long (0xC0+0x10)++0x0B
|
|
line.long 0x00 "CHCTRL,Channel Control Register"
|
|
bitfld.long 0x00 16.--21. " CHAIN ,Next channel to be triggered" "No channel,Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,Channel 8,Channel 9,Channel 10,Channel 11,Channel 12,Channel 13,Channel 14,Channel 15,?..."
|
|
bitfld.long 0x00 14.--15. " RES ,Read element size" "8 bits,16 bits,32 bits,64 bits"
|
|
bitfld.long 0x00 12.--13. " WES ,Write element size" "8 bits,16 bits,32 bits,64 bits"
|
|
newline
|
|
bitfld.long 0x00 8. " TTYPE ,Transfer type" "Frame,Block"
|
|
bitfld.long 0x00 3.--4. " ADDMR ,Addressing mode read" "Constant,Post-increment,,Indexed"
|
|
newline
|
|
bitfld.long 0x00 1.--2. " ADDMW ,Addressing mode write" "Constant,Post-increment,,Indexed"
|
|
bitfld.long 0x00 0. " AIM ,Autoinitiation mode enable" "Disabled,Enabled"
|
|
line.long 0x04 "EIOFF,Element Index Offset Register"
|
|
hexmask.long.word 0x04 16.--28. 1. " EIDXD ,Destination address element index"
|
|
hexmask.long.word 0x04 0.--12. 1. " EIDXS ,Source address element index"
|
|
line.long 0x08 "FIOFF,Frame Index Offset Register"
|
|
hexmask.long.word 0x08 16.--28. 1. " FIDXD ,Destination address frame index"
|
|
hexmask.long.word 0x08 0.--12. 1. " FIDXS ,Source address frame index"
|
|
tree.end
|
|
tree "Primary Control Packet 7"
|
|
group.long (0xE0)++0x0B
|
|
line.long 0x00 "ISADDR,Initial Source Address Register"
|
|
line.long 0x04 "IDADDR,Initial Destination Address Register"
|
|
line.long 0x08 "ITCOUNT,Initial Transfer Count Register"
|
|
hexmask.long.word 0x08 16.--28. 1. " IFTCOUNT ,Initial frame transfer count"
|
|
hexmask.long.word 0x08 0.--12. 1. " IETCOUNT ,Initial element transfer count"
|
|
group.long (0xE0+0x10)++0x0B
|
|
line.long 0x00 "CHCTRL,Channel Control Register"
|
|
bitfld.long 0x00 16.--21. " CHAIN ,Next channel to be triggered" "No channel,Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,Channel 8,Channel 9,Channel 10,Channel 11,Channel 12,Channel 13,Channel 14,Channel 15,?..."
|
|
bitfld.long 0x00 14.--15. " RES ,Read element size" "8 bits,16 bits,32 bits,64 bits"
|
|
bitfld.long 0x00 12.--13. " WES ,Write element size" "8 bits,16 bits,32 bits,64 bits"
|
|
newline
|
|
bitfld.long 0x00 8. " TTYPE ,Transfer type" "Frame,Block"
|
|
bitfld.long 0x00 3.--4. " ADDMR ,Addressing mode read" "Constant,Post-increment,,Indexed"
|
|
newline
|
|
bitfld.long 0x00 1.--2. " ADDMW ,Addressing mode write" "Constant,Post-increment,,Indexed"
|
|
bitfld.long 0x00 0. " AIM ,Autoinitiation mode enable" "Disabled,Enabled"
|
|
line.long 0x04 "EIOFF,Element Index Offset Register"
|
|
hexmask.long.word 0x04 16.--28. 1. " EIDXD ,Destination address element index"
|
|
hexmask.long.word 0x04 0.--12. 1. " EIDXS ,Source address element index"
|
|
line.long 0x08 "FIOFF,Frame Index Offset Register"
|
|
hexmask.long.word 0x08 16.--28. 1. " FIDXD ,Destination address frame index"
|
|
hexmask.long.word 0x08 0.--12. 1. " FIDXS ,Source address frame index"
|
|
tree.end
|
|
tree "Primary Control Packet 8"
|
|
group.long (0x100)++0x0B
|
|
line.long 0x00 "ISADDR,Initial Source Address Register"
|
|
line.long 0x04 "IDADDR,Initial Destination Address Register"
|
|
line.long 0x08 "ITCOUNT,Initial Transfer Count Register"
|
|
hexmask.long.word 0x08 16.--28. 1. " IFTCOUNT ,Initial frame transfer count"
|
|
hexmask.long.word 0x08 0.--12. 1. " IETCOUNT ,Initial element transfer count"
|
|
group.long (0x100+0x10)++0x0B
|
|
line.long 0x00 "CHCTRL,Channel Control Register"
|
|
bitfld.long 0x00 16.--21. " CHAIN ,Next channel to be triggered" "No channel,Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,Channel 8,Channel 9,Channel 10,Channel 11,Channel 12,Channel 13,Channel 14,Channel 15,?..."
|
|
bitfld.long 0x00 14.--15. " RES ,Read element size" "8 bits,16 bits,32 bits,64 bits"
|
|
bitfld.long 0x00 12.--13. " WES ,Write element size" "8 bits,16 bits,32 bits,64 bits"
|
|
newline
|
|
bitfld.long 0x00 8. " TTYPE ,Transfer type" "Frame,Block"
|
|
bitfld.long 0x00 3.--4. " ADDMR ,Addressing mode read" "Constant,Post-increment,,Indexed"
|
|
newline
|
|
bitfld.long 0x00 1.--2. " ADDMW ,Addressing mode write" "Constant,Post-increment,,Indexed"
|
|
bitfld.long 0x00 0. " AIM ,Autoinitiation mode enable" "Disabled,Enabled"
|
|
line.long 0x04 "EIOFF,Element Index Offset Register"
|
|
hexmask.long.word 0x04 16.--28. 1. " EIDXD ,Destination address element index"
|
|
hexmask.long.word 0x04 0.--12. 1. " EIDXS ,Source address element index"
|
|
line.long 0x08 "FIOFF,Frame Index Offset Register"
|
|
hexmask.long.word 0x08 16.--28. 1. " FIDXD ,Destination address frame index"
|
|
hexmask.long.word 0x08 0.--12. 1. " FIDXS ,Source address frame index"
|
|
tree.end
|
|
tree "Primary Control Packet 9"
|
|
group.long (0x120)++0x0B
|
|
line.long 0x00 "ISADDR,Initial Source Address Register"
|
|
line.long 0x04 "IDADDR,Initial Destination Address Register"
|
|
line.long 0x08 "ITCOUNT,Initial Transfer Count Register"
|
|
hexmask.long.word 0x08 16.--28. 1. " IFTCOUNT ,Initial frame transfer count"
|
|
hexmask.long.word 0x08 0.--12. 1. " IETCOUNT ,Initial element transfer count"
|
|
group.long (0x120+0x10)++0x0B
|
|
line.long 0x00 "CHCTRL,Channel Control Register"
|
|
bitfld.long 0x00 16.--21. " CHAIN ,Next channel to be triggered" "No channel,Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,Channel 8,Channel 9,Channel 10,Channel 11,Channel 12,Channel 13,Channel 14,Channel 15,?..."
|
|
bitfld.long 0x00 14.--15. " RES ,Read element size" "8 bits,16 bits,32 bits,64 bits"
|
|
bitfld.long 0x00 12.--13. " WES ,Write element size" "8 bits,16 bits,32 bits,64 bits"
|
|
newline
|
|
bitfld.long 0x00 8. " TTYPE ,Transfer type" "Frame,Block"
|
|
bitfld.long 0x00 3.--4. " ADDMR ,Addressing mode read" "Constant,Post-increment,,Indexed"
|
|
newline
|
|
bitfld.long 0x00 1.--2. " ADDMW ,Addressing mode write" "Constant,Post-increment,,Indexed"
|
|
bitfld.long 0x00 0. " AIM ,Autoinitiation mode enable" "Disabled,Enabled"
|
|
line.long 0x04 "EIOFF,Element Index Offset Register"
|
|
hexmask.long.word 0x04 16.--28. 1. " EIDXD ,Destination address element index"
|
|
hexmask.long.word 0x04 0.--12. 1. " EIDXS ,Source address element index"
|
|
line.long 0x08 "FIOFF,Frame Index Offset Register"
|
|
hexmask.long.word 0x08 16.--28. 1. " FIDXD ,Destination address frame index"
|
|
hexmask.long.word 0x08 0.--12. 1. " FIDXS ,Source address frame index"
|
|
tree.end
|
|
tree "Primary Control Packet 10"
|
|
group.long (0x140)++0x0B
|
|
line.long 0x00 "ISADDR,Initial Source Address Register"
|
|
line.long 0x04 "IDADDR,Initial Destination Address Register"
|
|
line.long 0x08 "ITCOUNT,Initial Transfer Count Register"
|
|
hexmask.long.word 0x08 16.--28. 1. " IFTCOUNT ,Initial frame transfer count"
|
|
hexmask.long.word 0x08 0.--12. 1. " IETCOUNT ,Initial element transfer count"
|
|
group.long (0x140+0x10)++0x0B
|
|
line.long 0x00 "CHCTRL,Channel Control Register"
|
|
bitfld.long 0x00 16.--21. " CHAIN ,Next channel to be triggered" "No channel,Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,Channel 8,Channel 9,Channel 10,Channel 11,Channel 12,Channel 13,Channel 14,Channel 15,?..."
|
|
bitfld.long 0x00 14.--15. " RES ,Read element size" "8 bits,16 bits,32 bits,64 bits"
|
|
bitfld.long 0x00 12.--13. " WES ,Write element size" "8 bits,16 bits,32 bits,64 bits"
|
|
newline
|
|
bitfld.long 0x00 8. " TTYPE ,Transfer type" "Frame,Block"
|
|
bitfld.long 0x00 3.--4. " ADDMR ,Addressing mode read" "Constant,Post-increment,,Indexed"
|
|
newline
|
|
bitfld.long 0x00 1.--2. " ADDMW ,Addressing mode write" "Constant,Post-increment,,Indexed"
|
|
bitfld.long 0x00 0. " AIM ,Autoinitiation mode enable" "Disabled,Enabled"
|
|
line.long 0x04 "EIOFF,Element Index Offset Register"
|
|
hexmask.long.word 0x04 16.--28. 1. " EIDXD ,Destination address element index"
|
|
hexmask.long.word 0x04 0.--12. 1. " EIDXS ,Source address element index"
|
|
line.long 0x08 "FIOFF,Frame Index Offset Register"
|
|
hexmask.long.word 0x08 16.--28. 1. " FIDXD ,Destination address frame index"
|
|
hexmask.long.word 0x08 0.--12. 1. " FIDXS ,Source address frame index"
|
|
tree.end
|
|
tree "Primary Control Packet 11"
|
|
group.long (0x160)++0x0B
|
|
line.long 0x00 "ISADDR,Initial Source Address Register"
|
|
line.long 0x04 "IDADDR,Initial Destination Address Register"
|
|
line.long 0x08 "ITCOUNT,Initial Transfer Count Register"
|
|
hexmask.long.word 0x08 16.--28. 1. " IFTCOUNT ,Initial frame transfer count"
|
|
hexmask.long.word 0x08 0.--12. 1. " IETCOUNT ,Initial element transfer count"
|
|
group.long (0x160+0x10)++0x0B
|
|
line.long 0x00 "CHCTRL,Channel Control Register"
|
|
bitfld.long 0x00 16.--21. " CHAIN ,Next channel to be triggered" "No channel,Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,Channel 8,Channel 9,Channel 10,Channel 11,Channel 12,Channel 13,Channel 14,Channel 15,?..."
|
|
bitfld.long 0x00 14.--15. " RES ,Read element size" "8 bits,16 bits,32 bits,64 bits"
|
|
bitfld.long 0x00 12.--13. " WES ,Write element size" "8 bits,16 bits,32 bits,64 bits"
|
|
newline
|
|
bitfld.long 0x00 8. " TTYPE ,Transfer type" "Frame,Block"
|
|
bitfld.long 0x00 3.--4. " ADDMR ,Addressing mode read" "Constant,Post-increment,,Indexed"
|
|
newline
|
|
bitfld.long 0x00 1.--2. " ADDMW ,Addressing mode write" "Constant,Post-increment,,Indexed"
|
|
bitfld.long 0x00 0. " AIM ,Autoinitiation mode enable" "Disabled,Enabled"
|
|
line.long 0x04 "EIOFF,Element Index Offset Register"
|
|
hexmask.long.word 0x04 16.--28. 1. " EIDXD ,Destination address element index"
|
|
hexmask.long.word 0x04 0.--12. 1. " EIDXS ,Source address element index"
|
|
line.long 0x08 "FIOFF,Frame Index Offset Register"
|
|
hexmask.long.word 0x08 16.--28. 1. " FIDXD ,Destination address frame index"
|
|
hexmask.long.word 0x08 0.--12. 1. " FIDXS ,Source address frame index"
|
|
tree.end
|
|
tree "Primary Control Packet 12"
|
|
group.long (0x180)++0x0B
|
|
line.long 0x00 "ISADDR,Initial Source Address Register"
|
|
line.long 0x04 "IDADDR,Initial Destination Address Register"
|
|
line.long 0x08 "ITCOUNT,Initial Transfer Count Register"
|
|
hexmask.long.word 0x08 16.--28. 1. " IFTCOUNT ,Initial frame transfer count"
|
|
hexmask.long.word 0x08 0.--12. 1. " IETCOUNT ,Initial element transfer count"
|
|
group.long (0x180+0x10)++0x0B
|
|
line.long 0x00 "CHCTRL,Channel Control Register"
|
|
bitfld.long 0x00 16.--21. " CHAIN ,Next channel to be triggered" "No channel,Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,Channel 8,Channel 9,Channel 10,Channel 11,Channel 12,Channel 13,Channel 14,Channel 15,?..."
|
|
bitfld.long 0x00 14.--15. " RES ,Read element size" "8 bits,16 bits,32 bits,64 bits"
|
|
bitfld.long 0x00 12.--13. " WES ,Write element size" "8 bits,16 bits,32 bits,64 bits"
|
|
newline
|
|
bitfld.long 0x00 8. " TTYPE ,Transfer type" "Frame,Block"
|
|
bitfld.long 0x00 3.--4. " ADDMR ,Addressing mode read" "Constant,Post-increment,,Indexed"
|
|
newline
|
|
bitfld.long 0x00 1.--2. " ADDMW ,Addressing mode write" "Constant,Post-increment,,Indexed"
|
|
bitfld.long 0x00 0. " AIM ,Autoinitiation mode enable" "Disabled,Enabled"
|
|
line.long 0x04 "EIOFF,Element Index Offset Register"
|
|
hexmask.long.word 0x04 16.--28. 1. " EIDXD ,Destination address element index"
|
|
hexmask.long.word 0x04 0.--12. 1. " EIDXS ,Source address element index"
|
|
line.long 0x08 "FIOFF,Frame Index Offset Register"
|
|
hexmask.long.word 0x08 16.--28. 1. " FIDXD ,Destination address frame index"
|
|
hexmask.long.word 0x08 0.--12. 1. " FIDXS ,Source address frame index"
|
|
tree.end
|
|
tree "Primary Control Packet 13"
|
|
group.long (0x1A0)++0x0B
|
|
line.long 0x00 "ISADDR,Initial Source Address Register"
|
|
line.long 0x04 "IDADDR,Initial Destination Address Register"
|
|
line.long 0x08 "ITCOUNT,Initial Transfer Count Register"
|
|
hexmask.long.word 0x08 16.--28. 1. " IFTCOUNT ,Initial frame transfer count"
|
|
hexmask.long.word 0x08 0.--12. 1. " IETCOUNT ,Initial element transfer count"
|
|
group.long (0x1A0+0x10)++0x0B
|
|
line.long 0x00 "CHCTRL,Channel Control Register"
|
|
bitfld.long 0x00 16.--21. " CHAIN ,Next channel to be triggered" "No channel,Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,Channel 8,Channel 9,Channel 10,Channel 11,Channel 12,Channel 13,Channel 14,Channel 15,?..."
|
|
bitfld.long 0x00 14.--15. " RES ,Read element size" "8 bits,16 bits,32 bits,64 bits"
|
|
bitfld.long 0x00 12.--13. " WES ,Write element size" "8 bits,16 bits,32 bits,64 bits"
|
|
newline
|
|
bitfld.long 0x00 8. " TTYPE ,Transfer type" "Frame,Block"
|
|
bitfld.long 0x00 3.--4. " ADDMR ,Addressing mode read" "Constant,Post-increment,,Indexed"
|
|
newline
|
|
bitfld.long 0x00 1.--2. " ADDMW ,Addressing mode write" "Constant,Post-increment,,Indexed"
|
|
bitfld.long 0x00 0. " AIM ,Autoinitiation mode enable" "Disabled,Enabled"
|
|
line.long 0x04 "EIOFF,Element Index Offset Register"
|
|
hexmask.long.word 0x04 16.--28. 1. " EIDXD ,Destination address element index"
|
|
hexmask.long.word 0x04 0.--12. 1. " EIDXS ,Source address element index"
|
|
line.long 0x08 "FIOFF,Frame Index Offset Register"
|
|
hexmask.long.word 0x08 16.--28. 1. " FIDXD ,Destination address frame index"
|
|
hexmask.long.word 0x08 0.--12. 1. " FIDXS ,Source address frame index"
|
|
tree.end
|
|
tree "Primary Control Packet 14"
|
|
group.long (0x1C0)++0x0B
|
|
line.long 0x00 "ISADDR,Initial Source Address Register"
|
|
line.long 0x04 "IDADDR,Initial Destination Address Register"
|
|
line.long 0x08 "ITCOUNT,Initial Transfer Count Register"
|
|
hexmask.long.word 0x08 16.--28. 1. " IFTCOUNT ,Initial frame transfer count"
|
|
hexmask.long.word 0x08 0.--12. 1. " IETCOUNT ,Initial element transfer count"
|
|
group.long (0x1C0+0x10)++0x0B
|
|
line.long 0x00 "CHCTRL,Channel Control Register"
|
|
bitfld.long 0x00 16.--21. " CHAIN ,Next channel to be triggered" "No channel,Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,Channel 8,Channel 9,Channel 10,Channel 11,Channel 12,Channel 13,Channel 14,Channel 15,?..."
|
|
bitfld.long 0x00 14.--15. " RES ,Read element size" "8 bits,16 bits,32 bits,64 bits"
|
|
bitfld.long 0x00 12.--13. " WES ,Write element size" "8 bits,16 bits,32 bits,64 bits"
|
|
newline
|
|
bitfld.long 0x00 8. " TTYPE ,Transfer type" "Frame,Block"
|
|
bitfld.long 0x00 3.--4. " ADDMR ,Addressing mode read" "Constant,Post-increment,,Indexed"
|
|
newline
|
|
bitfld.long 0x00 1.--2. " ADDMW ,Addressing mode write" "Constant,Post-increment,,Indexed"
|
|
bitfld.long 0x00 0. " AIM ,Autoinitiation mode enable" "Disabled,Enabled"
|
|
line.long 0x04 "EIOFF,Element Index Offset Register"
|
|
hexmask.long.word 0x04 16.--28. 1. " EIDXD ,Destination address element index"
|
|
hexmask.long.word 0x04 0.--12. 1. " EIDXS ,Source address element index"
|
|
line.long 0x08 "FIOFF,Frame Index Offset Register"
|
|
hexmask.long.word 0x08 16.--28. 1. " FIDXD ,Destination address frame index"
|
|
hexmask.long.word 0x08 0.--12. 1. " FIDXS ,Source address frame index"
|
|
tree.end
|
|
tree "Primary Control Packet 15"
|
|
group.long (0x1E0)++0x0B
|
|
line.long 0x00 "ISADDR,Initial Source Address Register"
|
|
line.long 0x04 "IDADDR,Initial Destination Address Register"
|
|
line.long 0x08 "ITCOUNT,Initial Transfer Count Register"
|
|
hexmask.long.word 0x08 16.--28. 1. " IFTCOUNT ,Initial frame transfer count"
|
|
hexmask.long.word 0x08 0.--12. 1. " IETCOUNT ,Initial element transfer count"
|
|
group.long (0x1E0+0x10)++0x0B
|
|
line.long 0x00 "CHCTRL,Channel Control Register"
|
|
bitfld.long 0x00 16.--21. " CHAIN ,Next channel to be triggered" "No channel,Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,Channel 8,Channel 9,Channel 10,Channel 11,Channel 12,Channel 13,Channel 14,Channel 15,?..."
|
|
bitfld.long 0x00 14.--15. " RES ,Read element size" "8 bits,16 bits,32 bits,64 bits"
|
|
bitfld.long 0x00 12.--13. " WES ,Write element size" "8 bits,16 bits,32 bits,64 bits"
|
|
newline
|
|
bitfld.long 0x00 8. " TTYPE ,Transfer type" "Frame,Block"
|
|
bitfld.long 0x00 3.--4. " ADDMR ,Addressing mode read" "Constant,Post-increment,,Indexed"
|
|
newline
|
|
bitfld.long 0x00 1.--2. " ADDMW ,Addressing mode write" "Constant,Post-increment,,Indexed"
|
|
bitfld.long 0x00 0. " AIM ,Autoinitiation mode enable" "Disabled,Enabled"
|
|
line.long 0x04 "EIOFF,Element Index Offset Register"
|
|
hexmask.long.word 0x04 16.--28. 1. " EIDXD ,Destination address element index"
|
|
hexmask.long.word 0x04 0.--12. 1. " EIDXS ,Source address element index"
|
|
line.long 0x08 "FIOFF,Frame Index Offset Register"
|
|
hexmask.long.word 0x08 16.--28. 1. " FIDXD ,Destination address frame index"
|
|
hexmask.long.word 0x08 0.--12. 1. " FIDXS ,Source address frame index"
|
|
tree.end
|
|
tree.end
|
|
tree.open "Working Control Packet Registers"
|
|
tree "Working Control Packet 0"
|
|
rgroup.long 0x800++0x0B
|
|
line.long 0x00 "CSADDR,Current Source Address Register"
|
|
line.long 0x04 "CDADDR,Current Destination Address Register"
|
|
line.long 0x08 "CTCOUNT,Current Transfer Count Register"
|
|
hexmask.long.word 0x08 16.--28. 1. " CFTCOUNT ,Current frame transfer count"
|
|
hexmask.long.word 0x08 0.--12. 1. " CETCOUNT ,Current element transfer count"
|
|
tree.end
|
|
tree "Working Control Packet 1"
|
|
rgroup.long 0x810++0x0B
|
|
line.long 0x00 "CSADDR,Current Source Address Register"
|
|
line.long 0x04 "CDADDR,Current Destination Address Register"
|
|
line.long 0x08 "CTCOUNT,Current Transfer Count Register"
|
|
hexmask.long.word 0x08 16.--28. 1. " CFTCOUNT ,Current frame transfer count"
|
|
hexmask.long.word 0x08 0.--12. 1. " CETCOUNT ,Current element transfer count"
|
|
tree.end
|
|
tree "Working Control Packet 2"
|
|
rgroup.long 0x820++0x0B
|
|
line.long 0x00 "CSADDR,Current Source Address Register"
|
|
line.long 0x04 "CDADDR,Current Destination Address Register"
|
|
line.long 0x08 "CTCOUNT,Current Transfer Count Register"
|
|
hexmask.long.word 0x08 16.--28. 1. " CFTCOUNT ,Current frame transfer count"
|
|
hexmask.long.word 0x08 0.--12. 1. " CETCOUNT ,Current element transfer count"
|
|
tree.end
|
|
tree "Working Control Packet 3"
|
|
rgroup.long 0x830++0x0B
|
|
line.long 0x00 "CSADDR,Current Source Address Register"
|
|
line.long 0x04 "CDADDR,Current Destination Address Register"
|
|
line.long 0x08 "CTCOUNT,Current Transfer Count Register"
|
|
hexmask.long.word 0x08 16.--28. 1. " CFTCOUNT ,Current frame transfer count"
|
|
hexmask.long.word 0x08 0.--12. 1. " CETCOUNT ,Current element transfer count"
|
|
tree.end
|
|
tree "Working Control Packet 4"
|
|
rgroup.long 0x840++0x0B
|
|
line.long 0x00 "CSADDR,Current Source Address Register"
|
|
line.long 0x04 "CDADDR,Current Destination Address Register"
|
|
line.long 0x08 "CTCOUNT,Current Transfer Count Register"
|
|
hexmask.long.word 0x08 16.--28. 1. " CFTCOUNT ,Current frame transfer count"
|
|
hexmask.long.word 0x08 0.--12. 1. " CETCOUNT ,Current element transfer count"
|
|
tree.end
|
|
tree "Working Control Packet 5"
|
|
rgroup.long 0x850++0x0B
|
|
line.long 0x00 "CSADDR,Current Source Address Register"
|
|
line.long 0x04 "CDADDR,Current Destination Address Register"
|
|
line.long 0x08 "CTCOUNT,Current Transfer Count Register"
|
|
hexmask.long.word 0x08 16.--28. 1. " CFTCOUNT ,Current frame transfer count"
|
|
hexmask.long.word 0x08 0.--12. 1. " CETCOUNT ,Current element transfer count"
|
|
tree.end
|
|
tree "Working Control Packet 6"
|
|
rgroup.long 0x860++0x0B
|
|
line.long 0x00 "CSADDR,Current Source Address Register"
|
|
line.long 0x04 "CDADDR,Current Destination Address Register"
|
|
line.long 0x08 "CTCOUNT,Current Transfer Count Register"
|
|
hexmask.long.word 0x08 16.--28. 1. " CFTCOUNT ,Current frame transfer count"
|
|
hexmask.long.word 0x08 0.--12. 1. " CETCOUNT ,Current element transfer count"
|
|
tree.end
|
|
tree "Working Control Packet 7"
|
|
rgroup.long 0x870++0x0B
|
|
line.long 0x00 "CSADDR,Current Source Address Register"
|
|
line.long 0x04 "CDADDR,Current Destination Address Register"
|
|
line.long 0x08 "CTCOUNT,Current Transfer Count Register"
|
|
hexmask.long.word 0x08 16.--28. 1. " CFTCOUNT ,Current frame transfer count"
|
|
hexmask.long.word 0x08 0.--12. 1. " CETCOUNT ,Current element transfer count"
|
|
tree.end
|
|
tree "Working Control Packet 8"
|
|
rgroup.long 0x880++0x0B
|
|
line.long 0x00 "CSADDR,Current Source Address Register"
|
|
line.long 0x04 "CDADDR,Current Destination Address Register"
|
|
line.long 0x08 "CTCOUNT,Current Transfer Count Register"
|
|
hexmask.long.word 0x08 16.--28. 1. " CFTCOUNT ,Current frame transfer count"
|
|
hexmask.long.word 0x08 0.--12. 1. " CETCOUNT ,Current element transfer count"
|
|
tree.end
|
|
tree "Working Control Packet 9"
|
|
rgroup.long 0x890++0x0B
|
|
line.long 0x00 "CSADDR,Current Source Address Register"
|
|
line.long 0x04 "CDADDR,Current Destination Address Register"
|
|
line.long 0x08 "CTCOUNT,Current Transfer Count Register"
|
|
hexmask.long.word 0x08 16.--28. 1. " CFTCOUNT ,Current frame transfer count"
|
|
hexmask.long.word 0x08 0.--12. 1. " CETCOUNT ,Current element transfer count"
|
|
tree.end
|
|
tree "Working Control Packet 10"
|
|
rgroup.long 0x8A0++0x0B
|
|
line.long 0x00 "CSADDR,Current Source Address Register"
|
|
line.long 0x04 "CDADDR,Current Destination Address Register"
|
|
line.long 0x08 "CTCOUNT,Current Transfer Count Register"
|
|
hexmask.long.word 0x08 16.--28. 1. " CFTCOUNT ,Current frame transfer count"
|
|
hexmask.long.word 0x08 0.--12. 1. " CETCOUNT ,Current element transfer count"
|
|
tree.end
|
|
tree "Working Control Packet 11"
|
|
rgroup.long 0x8B0++0x0B
|
|
line.long 0x00 "CSADDR,Current Source Address Register"
|
|
line.long 0x04 "CDADDR,Current Destination Address Register"
|
|
line.long 0x08 "CTCOUNT,Current Transfer Count Register"
|
|
hexmask.long.word 0x08 16.--28. 1. " CFTCOUNT ,Current frame transfer count"
|
|
hexmask.long.word 0x08 0.--12. 1. " CETCOUNT ,Current element transfer count"
|
|
tree.end
|
|
tree "Working Control Packet 12"
|
|
rgroup.long 0x8C0++0x0B
|
|
line.long 0x00 "CSADDR,Current Source Address Register"
|
|
line.long 0x04 "CDADDR,Current Destination Address Register"
|
|
line.long 0x08 "CTCOUNT,Current Transfer Count Register"
|
|
hexmask.long.word 0x08 16.--28. 1. " CFTCOUNT ,Current frame transfer count"
|
|
hexmask.long.word 0x08 0.--12. 1. " CETCOUNT ,Current element transfer count"
|
|
tree.end
|
|
tree "Working Control Packet 13"
|
|
rgroup.long 0x8D0++0x0B
|
|
line.long 0x00 "CSADDR,Current Source Address Register"
|
|
line.long 0x04 "CDADDR,Current Destination Address Register"
|
|
line.long 0x08 "CTCOUNT,Current Transfer Count Register"
|
|
hexmask.long.word 0x08 16.--28. 1. " CFTCOUNT ,Current frame transfer count"
|
|
hexmask.long.word 0x08 0.--12. 1. " CETCOUNT ,Current element transfer count"
|
|
tree.end
|
|
tree "Working Control Packet 14"
|
|
rgroup.long 0x8E0++0x0B
|
|
line.long 0x00 "CSADDR,Current Source Address Register"
|
|
line.long 0x04 "CDADDR,Current Destination Address Register"
|
|
line.long 0x08 "CTCOUNT,Current Transfer Count Register"
|
|
hexmask.long.word 0x08 16.--28. 1. " CFTCOUNT ,Current frame transfer count"
|
|
hexmask.long.word 0x08 0.--12. 1. " CETCOUNT ,Current element transfer count"
|
|
tree.end
|
|
tree "Working Control Packet 15"
|
|
rgroup.long 0x8F0++0x0B
|
|
line.long 0x00 "CSADDR,Current Source Address Register"
|
|
line.long 0x04 "CDADDR,Current Destination Address Register"
|
|
line.long 0x08 "CTCOUNT,Current Transfer Count Register"
|
|
hexmask.long.word 0x08 16.--28. 1. " CFTCOUNT ,Current frame transfer count"
|
|
hexmask.long.word 0x08 0.--12. 1. " CETCOUNT ,Current element transfer count"
|
|
tree.end
|
|
tree.end
|
|
tree.end
|
|
endian.le
|
|
width 0x0B
|
|
tree.end
|
|
endif
|
|
sif cpuis("TMS570LS0714*")||cpuis("TMS570LS0914*")
|
|
tree.open "EPWM (Enhanced Pulse Width Modulator Module)"
|
|
tree "EPWM1"
|
|
base ad:0xFCF78C00
|
|
endian.be
|
|
width 14.
|
|
group.word 0x00++0x05
|
|
line.word 0x00 "TBSTS,Time-Base Status Register"
|
|
eventfld.word 0x00 2. " CTRMAX ,Time-base counter max latched status" "Not reached,Reached"
|
|
eventfld.word 0x00 1. " SYNCI ,Input synchronization latched status" "Not occurred,Occurred"
|
|
rbitfld.word 0x00 0. " CTRDIR ,Time-base counter direction status" "Counting down,Counting up"
|
|
line.word 0x02 "TBCTL,Time-Base Control Register"
|
|
bitfld.word 0x02 14.--15. " FREE_SOFT ,Emulation mode" "Stop after INC/DEC,Stop after cycle,Free run,Free run"
|
|
bitfld.word 0x02 13. " PHSDIR ,Phase direction" "Count down,Count up"
|
|
bitfld.word 0x02 10.--12. " CLKDIV ,Time-base clock prescale" "/1,/2,/4,/8,/16,/32,/64,/128"
|
|
newline
|
|
bitfld.word 0x02 7.--9. " HSPCLKDIV ,High speed time-base clock prescale" "/1,/2,/4,/6,/8,/10,/12,/14"
|
|
eventfld.word 0x02 6. " SWFSYNC ,Software forced synchronization pulse" "No effect,Forced"
|
|
bitfld.word 0x02 4.--5. " SYNCOSEL ,Synchronization output select" "EPWMxSYNC,CTR=zero,CTR=CMPB,Disabled"
|
|
newline
|
|
bitfld.word 0x02 3. " PRDLD ,Active period register load from shadow register usage" "Used,Not used"
|
|
bitfld.word 0x02 2. " PHSEN ,Counter register load from phase register enable" "Disabled,Enabled"
|
|
bitfld.word 0x02 0.--1. " CTRMODE ,Counter mode" "Up-count,Down-count,Up-down-count,Stop-freeze cnt"
|
|
line.word 0x04 "TBPHS,Time-Base Counter Phase Register"
|
|
group.word 0x08++0x05
|
|
line.word 0x00 "TBPRD,Time-Base Period Register"
|
|
line.word 0x02 "TBCTR,Time-Base Counter Register"
|
|
line.word 0x04 "CMPCTL,Counter-Compare Control Register"
|
|
rbitfld.word 0x04 9. " SHDWBFULL ,Counter-compare B shadow register full status flag" "Not full,Full"
|
|
rbitfld.word 0x04 8. " SHDWAFULL ,Counter-compare A shadow register full status flag" "Not full,Full"
|
|
bitfld.word 0x04 6. " SHDWBMODE ,Counter-compare B register operating mode" "Shadow,Immediate"
|
|
newline
|
|
bitfld.word 0x04 4. " SHDWAMODE ,Counter-compare A register operating mode" "Shadow,Immediate"
|
|
bitfld.word 0x04 2.--3. " LOADBMODE ,Active counter-compare B load from shadow select mode" "CTR=Zero,CTR=PRD,Both,Freeze"
|
|
bitfld.word 0x04 0.--1. " LOADBMODE ,Active counter-compare B load from shadow select mode" "CTR=Zero,CTR=PRD,Both,Freeze"
|
|
group.word 0x10++0x01
|
|
line.word 0x00 "CMPA,Compare A Register"
|
|
group.word 0x14++0x17
|
|
line.word 0x00 "AQCTLA,AQCTLA Register"
|
|
bitfld.word 0x00 10.--11. " CBD ,Action when the time-base counter = CMPB register and the counter is decrementing" "Disabled,Clear,Set,Toggle output"
|
|
bitfld.word 0x00 8.--9. " CBU ,Action when the time-base counter = CMPB register and the counter is incrementing" "Disabled,Clear,Set,Toggle output"
|
|
bitfld.word 0x00 6.--7. " CAD ,Action when the time-base counter = CMPA register and the counter is decrementing" "Disabled,Clear,Set,Toggle output"
|
|
newline
|
|
bitfld.word 0x00 4.--5. " CAU ,Action when the time-base counter = CMPA register and the counter is incrementing" "Disabled,Clear,Set,Toggle output"
|
|
bitfld.word 0x00 2.--3. " PRD ,Action when the counter = the period" "Disabled,Clear,Set,Toggle output"
|
|
bitfld.word 0x00 0.--1. " ZRO ,Action when the counter = zero" "Disabled,Clear,Set,Toggle output"
|
|
line.word 0x02 "CMPB,Compare B Register"
|
|
line.word 0x04 "AQSFRC,AQSFRC Register"
|
|
bitfld.word 0x04 6.--7. " RLDCSF ,AQCSFRC active register reload from shadow options" "CNT=0,CNT=period,CNT=0 or CNT=period,Load immediately"
|
|
eventfld.word 0x04 5. " OTSFB ,One-time software forced event on output B" "No effect,Forced"
|
|
bitfld.word 0x04 3.--4. " ACTSFB ,Action when one-time software force B is invoked" "Disabled,Clear,Set,Toggle"
|
|
newline
|
|
eventfld.word 0x04 2. " OTSFA ,One-time software forced event on output A" "No effect,Forced"
|
|
bitfld.word 0x04 0.--1. " ACTSFA ,Action when one-time software force A is invoked" "Disabled,Clear,Set,Toggle"
|
|
line.word 0x06 "AQCTLA,AQCTLA Register"
|
|
bitfld.word 0x06 10.--11. " CBD ,Action when the time-base counter = CMPB register and the counter is decrementing" "Disabled,Clear,Set,Toggle output"
|
|
bitfld.word 0x06 8.--9. " CBU ,Action when the time-base counter = CMPB register and the counter is incrementing" "Disabled,Clear,Set,Toggle output"
|
|
bitfld.word 0x06 6.--7. " CAD ,Action when the time-base counter = CMPA register and the counter is decrementing" "Disabled,Clear,Set,Toggle output"
|
|
newline
|
|
bitfld.word 0x06 4.--5. " CAU ,Action when the time-base counter = CMPA register and the counter is incrementing" "Disabled,Clear,Set,Toggle output"
|
|
bitfld.word 0x06 2.--3. " PRD ,Action when the counter = the period" "Disabled,Clear,Set,Toggle output"
|
|
bitfld.word 0x06 0.--1. " ZRO ,Action when the counter = zero" "Disabled,Clear,Set,Toggle output"
|
|
line.word 0x08 "DBCTL,Dead-Band Control Register"
|
|
bitfld.word 0x08 15. " HALFCYCLE ,Half cycle clocking enable" "Disabled,Enabled"
|
|
bitfld.word 0x08 4.--5. " IN_MODE ,Dead band input mode control (A In for edge / B In for edge)" "Both / -,Falling / Rising,Rising / Falling,- / Both"
|
|
newline
|
|
bitfld.word 0x08 2.--3. " POLSEL ,Active polarity select control" "High,Low complementary,High complementary,Low"
|
|
bitfld.word 0x08 0.--1. " OUT_MODE ,Dead band output mode control" "Bypass,Rising disabled,Falling disabled,- / Both"
|
|
line.word 0x0A "AQCSFRC,AQCSFRC register"
|
|
bitfld.word 0x0A 2.--3. " CSFB ,Continuous software force on output B" "Disabled,Forced low,Forced high,Disabled"
|
|
bitfld.word 0x0A 0.--1. " CSFA ,Continuous software force on output A" "Disabled,Forced low,Forced high,Disabled"
|
|
line.word 0x0C "DBFED,Falling Edge Delay Register"
|
|
hexmask.word 0x0C 0.--9. 1. " DEL ,Falling edge delay count"
|
|
line.word 0x0E "DBRED,Rising Edge Delay Register"
|
|
hexmask.word 0x0E 0.--9. 1. " DEL ,Rising edge delay count"
|
|
line.word 0x10 "TZDCSEL,Digital Compare Select Register"
|
|
bitfld.word 0x10 9.--11. " DCBEVT2 ,Digital compare output B event 2 selection (DCBL / DCBH)" "Event,Don't care / Low,Don't care / High,Low / Don't care,High / Don't care,High / Low,?..."
|
|
bitfld.word 0x10 6.--8. " DCBEVT1 ,Digital compare output B event 1 selection (DCBL / DCBH)" "Event,Don't care / Low,Don't care / High,Low / Don't care,High / Don't care,High / Low,?..."
|
|
newline
|
|
bitfld.word 0x10 3.--5. " DCAEVT2 ,Digital compare output A event 2 selection (DCAL / DCAH)" "Event,Don't care / Low,Don't care / High,Low / Don't care,High / Don't care,High / Low,?..."
|
|
bitfld.word 0x10 0.--2. " DCAEVT1 ,Digital compare output A event 1 selection (DCAL / DCAH)" "Event,Don't care / Low,Don't care / High,Low / Don't care,High / Don't care,High / Low,?..."
|
|
line.word 0x12 "TZSEL,Trip-Zone Select Register"
|
|
rbitfld.word 0x12 15. " DCBEVT1 ,Digital compare output B event 1 enable" "Disabled,Enabled"
|
|
rbitfld.word 0x12 14. " DCAEVT1 ,Digital compare output A event 1 enable" "Disabled,Enabled"
|
|
bitfld.word 0x12 13. " OSHT6 ,Trip-zone 6 (/TZ6) as one-shot trip enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.word 0x12 12. " OSHT5 ,Trip-zone 5 (/TZ5) as one-shot trip enable" "Disabled,Enabled"
|
|
bitfld.word 0x12 11. " OSHT4 ,Trip-zone 4 (/TZ4) as one-shot trip enable" "Disabled,Enabled"
|
|
bitfld.word 0x12 10. " OSHT3 ,Trip-zone 3 (/TZ3) as one-shot trip enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.word 0x12 9. " OSHT2 ,Trip-zone 2 (/TZ2) as one-shot trip enable" "Disabled,Enabled"
|
|
bitfld.word 0x12 8. " OSHT1 ,Trip-zone 1 (/TZ1) as one-shot trip enable" "Disabled,Enabled"
|
|
rbitfld.word 0x12 7. " DCBEVT2 ,Digital compare output B event 2 enable" "Disabled,Enabled"
|
|
newline
|
|
rbitfld.word 0x12 6. " DCAEVT2 ,Digital compare output A event 2 enable" "Disabled,Enabled"
|
|
bitfld.word 0x12 5. " CBC6 ,Trip-zone 6 (/TZ6) as CBC enable" "Disabled,Enabled"
|
|
bitfld.word 0x12 4. " CBC5 ,Trip-zone 5 (/TZ5) as CBC enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.word 0x12 3. " CBC4 ,Trip-zone 4 (/TZ4) as CBC enable" "Disabled,Enabled"
|
|
bitfld.word 0x12 2. " CBC3 ,Trip-zone 3 (/TZ3) as CBC enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.word 0x12 1. " CBC2 ,Trip-zone 2 (/TZ2) as CBC enable" "Disabled,Enabled"
|
|
bitfld.word 0x12 0. " CBC1 ,Trip-zone 1 (/TZ1) as CBC enable" "Disabled,Enabled"
|
|
line.word 0x14 "TZEINT,Trip-Zone Interrupt Register"
|
|
bitfld.word 0x14 6. " DCBEVT2 ,Digital comparator output B event 2 interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x14 5. " DCBEVT1 ,Digital comparator output B event 1 interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x14 4. " DCAEVT2 ,Digital comparator output A event 2 interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.word 0x14 3. " DCAEVT1 ,Digital comparator output A event 1 interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x14 2. " OST ,Trip-zone one-shot interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x14 1. " CBC ,Trip-zone cycle-by-cycle interrupt enable" "Disabled,Enabled"
|
|
line.word 0x16 "TZCTL,Trip-Zone Control Register"
|
|
bitfld.word 0x16 10.--11. " DCBEVT2 ,Digital compare output B event 2 action on EPWMxB" "High-impedance,Forced high,Forced low,Disabled"
|
|
bitfld.word 0x16 8.--9. " DCBEVT1 ,Digital compare output B event 1 action on EPWMxB" "High-impedance,Forced high,Forced low,Disabled"
|
|
bitfld.word 0x16 6.--7. " DCAEVT2 ,Digital compare output A event 2 action on EPWMxA" "High-impedance,Forced high,Forced low,Disabled"
|
|
newline
|
|
bitfld.word 0x16 4.--5. " DCAEVT1 ,Digital compare output A event 1 action on EPWMxA" "High-impedance,Forced high,Forced low,Disabled"
|
|
bitfld.word 0x16 2.--3. " TZB ,Action on trip-zone event for EPWMxB select" "High-impedance,Forced high,Forced low,Disabled"
|
|
bitfld.word 0x16 0.--1. " TZA ,Action on trip-zone event for EPWMxA select" "High-impedance,Forced high,Forced low,Disabled"
|
|
wgroup.word 0x2C++0x01
|
|
line.word 0x00 "TZCLR,Trip-Zone Clear Register"
|
|
bitfld.word 0x00 6. " DCBEVT2 ,Clear flag for digital compare output B event 2" "No effect,Clear"
|
|
bitfld.word 0x00 5. " DCBEVT1 ,Clear flag for digital compare output B event 1" "No effect,Clear"
|
|
bitfld.word 0x00 4. " DCAEVT2 ,Clear flag for digital compare output A event 2" "No effect,Clear"
|
|
newline
|
|
bitfld.word 0x00 3. " DCAEVT1 ,Clear flag for digital compare output A event 1" "No effect,Clear"
|
|
bitfld.word 0x00 2. " OST ,Clear flag for one-shot trip latch" "No effect,Clear"
|
|
newline
|
|
bitfld.word 0x00 1. " CBC ,Clear flag for cycle-by-cycle trip latch" "No effect,Clear"
|
|
bitfld.word 0x00 0. " INT ,Global interrupt clear flag" "No effect,Clear"
|
|
rgroup.word 0x2E++0x01
|
|
line.word 0x00 "TZFLG,Trip-Zone Flag Register"
|
|
bitfld.word 0x00 6. " DCBEVT2 ,Latched status flag for digital compare output B event 2" "No interrupt,Interrupt"
|
|
bitfld.word 0x00 5. " DCBEVT1 ,Latched status flag for digital compare output B event 1" "No interrupt,Interrupt"
|
|
bitfld.word 0x00 4. " DCAEVT2 ,Latched status flag for digital compare output A event 2" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.word 0x00 3. " DCAEVT1 ,Latched status flag for digital compare output A event 1" "No interrupt,Interrupt"
|
|
bitfld.word 0x00 2. " OST ,Latched status flag for one-shot trip latch" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.word 0x00 1. " CBC ,Latched status flag for cycle-by-cycle trip latch" "No interrupt,Interrupt"
|
|
bitfld.word 0x00 0. " INT ,Global interrupt latched status flag" "No interrupt,Interrupt"
|
|
group.word 0x30++0x03
|
|
line.word 0x00 "ETSEL,Event Select Register"
|
|
bitfld.word 0x00 15. " SOCBEN ,Enable the ADC start of conversion B pulse" "Disabled,Enabled"
|
|
bitfld.word 0x00 12.--14. " SOCBSEL ,Start of conversion B option select" "DCBEVT1,TBCTR=0,TBCTR=TBPRD,TBCTR=0 or TBCTR=TBPRD,TBCTR=CMPA for INC,TBCTR=CMPA for DEC,TBCTR=CMPB for INC,TBCTR=CMPB for DEC"
|
|
bitfld.word 0x00 11. " SOCAEN ,Enable the ADC start of conversion A pulse" "Disabled,Enabled"
|
|
newline
|
|
bitfld.word 0x00 8.--10. " SOCASEL ,Start of conversion A option select" "DCAEVT1,TBCTR=0,TBCTR=TBPRD,TBCTR=0 or TBCTR=TBPRD,TBCTR=CMPA for INC,TBCTR=CMPA for DEC,TBCTR=CMPB for INC,TBCTR=CMPB for DEC"
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bitfld.word 0x00 3. " INTEN ,Enable ePWM interrupt generation" "Disabled,Enabled"
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|
bitfld.word 0x00 0.--2. " INTSEL ,EPWM interrupt option select" ",TBCTR=0,TBCTR=TBPRD,TBCTR=0 or TBCTR=TBPRD,TBCTR=CMPA for INC,TBCTR=CMPA for DEC,TBCTR=CMPB for INC,TBCTR=CMPB for DEC"
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|
line.word 0x02 "TZFLG,Trip-Zone Flag Register"
|
|
bitfld.word 0x02 6. " DCBEVT2 ,Force flag for digital compare output B event 2" "No interrupt,Interrupt"
|
|
bitfld.word 0x02 5. " DCBEVT1 ,Force flag for digital compare output B event 1" "No interrupt,Interrupt"
|
|
bitfld.word 0x02 4. " DCAEVT2 ,Force flag for digital compare output A event 2" "No interrupt,Interrupt"
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|
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bitfld.word 0x02 3. " DCAEVT1 ,Force flag for digital compare output A event 1" "No interrupt,Interrupt"
|
|
bitfld.word 0x02 2. " OST ,Force flag for one-shot trip latch" "No interrupt,Interrupt"
|
|
bitfld.word 0x02 1. " CBC ,Force flag for cycle-by-cycle trip latch" "No interrupt,Interrupt"
|
|
group.word 0x34++0x01
|
|
line.word 0x00 "ET_SETCLR,Event Set/Clear Register"
|
|
setclrfld.word 0x00 3. 0x04 3. 0x06 3. " SOCB ,Latched ePWM ADC start of conversation B status flag" "No interrupt,Interrupt"
|
|
setclrfld.word 0x00 2. 0x04 2. 0x06 2. " SOCA ,Latched ePWM ADC start of conversation A status flag" "No interrupt,Interrupt"
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|
setclrfld.word 0x00 0. 0x04 0. 0x06 0. " INT ,Latched ePWM interrupt status flag" "No interrupt,Interrupt"
|
|
group.word 0x36++0x01
|
|
line.word 0x00 "ETPS,Event Period Select Register"
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|
rbitfld.word 0x00 14.--15. " SOCBCNT ,ePWM ADC start of conversion B event counter" "No events,1 event,2 events,3 events"
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bitfld.word 0x00 12.--13. " SOCBPRD ,ePWM ADC start of conversion B event period select" "Disabled,1st event,2nd event,3rd event"
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rbitfld.word 0x00 10.--11. " SOCACNT ,ePWM ADC start of conversion A event counter" "No events,1 event,2 events,3 events"
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bitfld.word 0x00 8.--9. " SOCAPRD ,ePWM ADC start of conversion A event period select" "Disabled,1st event,2nd event,3rd event"
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|
rbitfld.word 0x00 2.--3. " INTCNT ,ePWM interrupt event counter" "No events,1 event,2 events,3 events"
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|
bitfld.word 0x00 0.--1. " INTPRD ,ePWM interrupt period select" "Disabled,1st event,2nd event,3rd event"
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|
group.word 0x3E++0x01
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|
line.word 0x00 "PCCTL,PWM Chopping Control Register"
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|
bitfld.word 0x00 8.--10. " CHPDUTY ,Chopping clock duty cycle" "1/8,2/8,3/8,4/8,5/8,6/8,7/8,"
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bitfld.word 0x00 5.--7. " CHPFREQ ,Chopping clock frequency" "/1,/2,/3,/4,/5,/6,/7,/8"
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|
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bitfld.word 0x00 1.--4. " OSHTWTH ,One-shot pulse width" "1 x VCLK4 / 8,2 x VCLK4 / 8,3 x VCLK4 / 8,4 x VCLK4 / 8,5 x VCLK4 / 8,6 x VCLK4 / 8,7 x VCLK4 / 8,8 x VCLK4 / 8,9 x VCLK4 / 8,10 x VCLK4 / 8,11 x VCLK4 / 8,12 x VCLK4 / 8,13 x VCLK4 / 8,14 x VCLK4 / 8,15 x VCLK4 / 8,16 x VCLK4 / 8"
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bitfld.word 0x00 0. " CHPEN ,PWM-chopping enable" "Disabled,Enabled"
|
|
group.word 0x60++0x07
|
|
line.word 0x00 "DCACTL,DCA Control Register"
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bitfld.word 0x00 9. " EVT2FRC_SYNCSEL ,DCAEVT2 force synchronization signal select" "Synchronous,Asynchronous"
|
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bitfld.word 0x00 8. " EVT2SRCSEL ,DCAEVT2 source signal select" "DCAEVT2,DCEVTFILT"
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bitfld.word 0x00 3. " EVT1SYNCE ,DCAEVT1 SYNC enable" "Disabled,Enabled"
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bitfld.word 0x00 2. " EVT1SOCE ,DCAEVT1 SOC enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 1. " EVT1FRC_SYNCSEL ,DCAEVT1 force synchronization signal select" "Synchronous,Asynchronous"
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|
bitfld.word 0x00 0. " EVT1SRCSEL ,DCAEVT1 source signal select" "DCAEVT1,DCEVTFILT"
|
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line.word 0x02 "DCTRIPSEL,Digital Compare Select Register"
|
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bitfld.word 0x02 12.--15. " DCBLCOMPSEL ,Digital compare B low input select" "/TZ1,/TZ2,/TZ3,?..."
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bitfld.word 0x02 8.--11. " DCBHCOMPSEL ,Digital compare B high input select" "/TZ1,/TZ2,/TZ3,?..."
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bitfld.word 0x02 4.--7. " DCALCOMPSEL ,Digital compare A low input select" "/TZ1,/TZ2,/TZ3,?..."
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bitfld.word 0x02 0.--3. " DCAHCOMPSEL ,Digital compare A high input select" "/TZ1,/TZ2,/TZ3,?..."
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line.word 0x04 "DCFCTL,DC Control Register"
|
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bitfld.word 0x04 4.--5. " PULSESEL ,Pulse select for blanking and capture alignment" "TBCTR=TBPRD,TBCTR=0,?..."
|
|
bitfld.word 0x04 3. " BLANKINV ,Banking windows inversion" "Not inverted,Inverted"
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|
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bitfld.word 0x04 2. " BLANKE ,Blanking widow enable" "Disabled,Enabled"
|
|
bitfld.word 0x04 0.--1. " SRCSEL ,Filter block signal source select" "DCAEVT1,DCAEVT2,DCBEVT1,DCBEVT2"
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line.word 0x06 "DCBCTL,DCB Control Register"
|
|
bitfld.word 0x06 9. " EVT2FRC_SYNCSEL ,DCBEVT2 force synchronization signal select" "Synchronous,Asynchronous"
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bitfld.word 0x06 8. " EVT2SRCSEL ,DCBEVT2 source signal select" "DCBEVT2,DCEVTFILT"
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bitfld.word 0x06 3. " EVT1SYNCE ,DCBEVT1 SYNC enable" "Disabled,Enabled"
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bitfld.word 0x06 2. " EVT1SOCE ,DCBEVT1 SOC enable" "Disabled,Enabled"
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bitfld.word 0x06 1. " EVT1FRC_SYNCSEL ,DCBEVT1 force synchronization signal select" "Synchronous,Asynchronous"
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|
bitfld.word 0x06 0. " EVT1SRCSEL ,DCBEVT1 source signal select" "DCBEVT1,DCEVTFILT"
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rgroup.word 0x68++0x01
|
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line.word 0x00 "DCFOFFSET,Blanking Window Offset Register"
|
|
group.word 0x6A++0x01
|
|
line.word 0x00 "DCCAPCTL,DC Capture Control Register"
|
|
bitfld.word 0x00 1. " SHDWMODE ,TBCTR counter capture shadow select mode" "Enable shadow,Active"
|
|
bitfld.word 0x00 0. " CAPE ,TBCTR counter capture enable" "Disabled,Enabled"
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|
rgroup.word 0x6E++0x05
|
|
line.word 0x00 "DCFOFFSETCNT,Blanking Offset Counter Register"
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|
line.word 0x02 "DCCAP,Digital Compare Capture Register"
|
|
line.word 0x04 "DCFWINDOWCNT,DC Blanking Window Counter Register"
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hexmask.word.byte 0x04 0.--7. 1. " WINDOWCNT ,Blanking window counter"
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endian.le
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width 0x0B
|
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tree.end
|
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tree "EPWM2"
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base ad:0xFCF78D00
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endian.be
|
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width 14.
|
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group.word 0x00++0x05
|
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line.word 0x00 "TBSTS,Time-Base Status Register"
|
|
eventfld.word 0x00 2. " CTRMAX ,Time-base counter max latched status" "Not reached,Reached"
|
|
eventfld.word 0x00 1. " SYNCI ,Input synchronization latched status" "Not occurred,Occurred"
|
|
rbitfld.word 0x00 0. " CTRDIR ,Time-base counter direction status" "Counting down,Counting up"
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line.word 0x02 "TBCTL,Time-Base Control Register"
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bitfld.word 0x02 14.--15. " FREE_SOFT ,Emulation mode" "Stop after INC/DEC,Stop after cycle,Free run,Free run"
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bitfld.word 0x02 13. " PHSDIR ,Phase direction" "Count down,Count up"
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bitfld.word 0x02 10.--12. " CLKDIV ,Time-base clock prescale" "/1,/2,/4,/8,/16,/32,/64,/128"
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bitfld.word 0x02 7.--9. " HSPCLKDIV ,High speed time-base clock prescale" "/1,/2,/4,/6,/8,/10,/12,/14"
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eventfld.word 0x02 6. " SWFSYNC ,Software forced synchronization pulse" "No effect,Forced"
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bitfld.word 0x02 4.--5. " SYNCOSEL ,Synchronization output select" "EPWMxSYNC,CTR=zero,CTR=CMPB,Disabled"
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newline
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bitfld.word 0x02 3. " PRDLD ,Active period register load from shadow register usage" "Used,Not used"
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bitfld.word 0x02 2. " PHSEN ,Counter register load from phase register enable" "Disabled,Enabled"
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bitfld.word 0x02 0.--1. " CTRMODE ,Counter mode" "Up-count,Down-count,Up-down-count,Stop-freeze cnt"
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line.word 0x04 "TBPHS,Time-Base Counter Phase Register"
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group.word 0x08++0x05
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line.word 0x00 "TBPRD,Time-Base Period Register"
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line.word 0x02 "TBCTR,Time-Base Counter Register"
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line.word 0x04 "CMPCTL,Counter-Compare Control Register"
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rbitfld.word 0x04 9. " SHDWBFULL ,Counter-compare B shadow register full status flag" "Not full,Full"
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rbitfld.word 0x04 8. " SHDWAFULL ,Counter-compare A shadow register full status flag" "Not full,Full"
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bitfld.word 0x04 6. " SHDWBMODE ,Counter-compare B register operating mode" "Shadow,Immediate"
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bitfld.word 0x04 4. " SHDWAMODE ,Counter-compare A register operating mode" "Shadow,Immediate"
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bitfld.word 0x04 2.--3. " LOADBMODE ,Active counter-compare B load from shadow select mode" "CTR=Zero,CTR=PRD,Both,Freeze"
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bitfld.word 0x04 0.--1. " LOADBMODE ,Active counter-compare B load from shadow select mode" "CTR=Zero,CTR=PRD,Both,Freeze"
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group.word 0x10++0x01
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line.word 0x00 "CMPA,Compare A Register"
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group.word 0x14++0x17
|
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line.word 0x00 "AQCTLA,AQCTLA Register"
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bitfld.word 0x00 10.--11. " CBD ,Action when the time-base counter = CMPB register and the counter is decrementing" "Disabled,Clear,Set,Toggle output"
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bitfld.word 0x00 8.--9. " CBU ,Action when the time-base counter = CMPB register and the counter is incrementing" "Disabled,Clear,Set,Toggle output"
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bitfld.word 0x00 6.--7. " CAD ,Action when the time-base counter = CMPA register and the counter is decrementing" "Disabled,Clear,Set,Toggle output"
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newline
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bitfld.word 0x00 4.--5. " CAU ,Action when the time-base counter = CMPA register and the counter is incrementing" "Disabled,Clear,Set,Toggle output"
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bitfld.word 0x00 2.--3. " PRD ,Action when the counter = the period" "Disabled,Clear,Set,Toggle output"
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bitfld.word 0x00 0.--1. " ZRO ,Action when the counter = zero" "Disabled,Clear,Set,Toggle output"
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line.word 0x02 "CMPB,Compare B Register"
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line.word 0x04 "AQSFRC,AQSFRC Register"
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bitfld.word 0x04 6.--7. " RLDCSF ,AQCSFRC active register reload from shadow options" "CNT=0,CNT=period,CNT=0 or CNT=period,Load immediately"
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eventfld.word 0x04 5. " OTSFB ,One-time software forced event on output B" "No effect,Forced"
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bitfld.word 0x04 3.--4. " ACTSFB ,Action when one-time software force B is invoked" "Disabled,Clear,Set,Toggle"
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|
newline
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eventfld.word 0x04 2. " OTSFA ,One-time software forced event on output A" "No effect,Forced"
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bitfld.word 0x04 0.--1. " ACTSFA ,Action when one-time software force A is invoked" "Disabled,Clear,Set,Toggle"
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line.word 0x06 "AQCTLA,AQCTLA Register"
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bitfld.word 0x06 10.--11. " CBD ,Action when the time-base counter = CMPB register and the counter is decrementing" "Disabled,Clear,Set,Toggle output"
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bitfld.word 0x06 8.--9. " CBU ,Action when the time-base counter = CMPB register and the counter is incrementing" "Disabled,Clear,Set,Toggle output"
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bitfld.word 0x06 6.--7. " CAD ,Action when the time-base counter = CMPA register and the counter is decrementing" "Disabled,Clear,Set,Toggle output"
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newline
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bitfld.word 0x06 4.--5. " CAU ,Action when the time-base counter = CMPA register and the counter is incrementing" "Disabled,Clear,Set,Toggle output"
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bitfld.word 0x06 2.--3. " PRD ,Action when the counter = the period" "Disabled,Clear,Set,Toggle output"
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bitfld.word 0x06 0.--1. " ZRO ,Action when the counter = zero" "Disabled,Clear,Set,Toggle output"
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line.word 0x08 "DBCTL,Dead-Band Control Register"
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bitfld.word 0x08 15. " HALFCYCLE ,Half cycle clocking enable" "Disabled,Enabled"
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bitfld.word 0x08 4.--5. " IN_MODE ,Dead band input mode control (A In for edge / B In for edge)" "Both / -,Falling / Rising,Rising / Falling,- / Both"
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newline
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bitfld.word 0x08 2.--3. " POLSEL ,Active polarity select control" "High,Low complementary,High complementary,Low"
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bitfld.word 0x08 0.--1. " OUT_MODE ,Dead band output mode control" "Bypass,Rising disabled,Falling disabled,- / Both"
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line.word 0x0A "AQCSFRC,AQCSFRC register"
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bitfld.word 0x0A 2.--3. " CSFB ,Continuous software force on output B" "Disabled,Forced low,Forced high,Disabled"
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bitfld.word 0x0A 0.--1. " CSFA ,Continuous software force on output A" "Disabled,Forced low,Forced high,Disabled"
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line.word 0x0C "DBFED,Falling Edge Delay Register"
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hexmask.word 0x0C 0.--9. 1. " DEL ,Falling edge delay count"
|
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line.word 0x0E "DBRED,Rising Edge Delay Register"
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hexmask.word 0x0E 0.--9. 1. " DEL ,Rising edge delay count"
|
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line.word 0x10 "TZDCSEL,Digital Compare Select Register"
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bitfld.word 0x10 9.--11. " DCBEVT2 ,Digital compare output B event 2 selection (DCBL / DCBH)" "Event,Don't care / Low,Don't care / High,Low / Don't care,High / Don't care,High / Low,?..."
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bitfld.word 0x10 6.--8. " DCBEVT1 ,Digital compare output B event 1 selection (DCBL / DCBH)" "Event,Don't care / Low,Don't care / High,Low / Don't care,High / Don't care,High / Low,?..."
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newline
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bitfld.word 0x10 3.--5. " DCAEVT2 ,Digital compare output A event 2 selection (DCAL / DCAH)" "Event,Don't care / Low,Don't care / High,Low / Don't care,High / Don't care,High / Low,?..."
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bitfld.word 0x10 0.--2. " DCAEVT1 ,Digital compare output A event 1 selection (DCAL / DCAH)" "Event,Don't care / Low,Don't care / High,Low / Don't care,High / Don't care,High / Low,?..."
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line.word 0x12 "TZSEL,Trip-Zone Select Register"
|
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rbitfld.word 0x12 15. " DCBEVT1 ,Digital compare output B event 1 enable" "Disabled,Enabled"
|
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rbitfld.word 0x12 14. " DCAEVT1 ,Digital compare output A event 1 enable" "Disabled,Enabled"
|
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bitfld.word 0x12 13. " OSHT6 ,Trip-zone 6 (/TZ6) as one-shot trip enable" "Disabled,Enabled"
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|
newline
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bitfld.word 0x12 12. " OSHT5 ,Trip-zone 5 (/TZ5) as one-shot trip enable" "Disabled,Enabled"
|
|
bitfld.word 0x12 11. " OSHT4 ,Trip-zone 4 (/TZ4) as one-shot trip enable" "Disabled,Enabled"
|
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bitfld.word 0x12 10. " OSHT3 ,Trip-zone 3 (/TZ3) as one-shot trip enable" "Disabled,Enabled"
|
|
newline
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bitfld.word 0x12 9. " OSHT2 ,Trip-zone 2 (/TZ2) as one-shot trip enable" "Disabled,Enabled"
|
|
bitfld.word 0x12 8. " OSHT1 ,Trip-zone 1 (/TZ1) as one-shot trip enable" "Disabled,Enabled"
|
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rbitfld.word 0x12 7. " DCBEVT2 ,Digital compare output B event 2 enable" "Disabled,Enabled"
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|
newline
|
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rbitfld.word 0x12 6. " DCAEVT2 ,Digital compare output A event 2 enable" "Disabled,Enabled"
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bitfld.word 0x12 5. " CBC6 ,Trip-zone 6 (/TZ6) as CBC enable" "Disabled,Enabled"
|
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bitfld.word 0x12 4. " CBC5 ,Trip-zone 5 (/TZ5) as CBC enable" "Disabled,Enabled"
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|
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bitfld.word 0x12 3. " CBC4 ,Trip-zone 4 (/TZ4) as CBC enable" "Disabled,Enabled"
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|
bitfld.word 0x12 2. " CBC3 ,Trip-zone 3 (/TZ3) as CBC enable" "Disabled,Enabled"
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|
newline
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bitfld.word 0x12 1. " CBC2 ,Trip-zone 2 (/TZ2) as CBC enable" "Disabled,Enabled"
|
|
bitfld.word 0x12 0. " CBC1 ,Trip-zone 1 (/TZ1) as CBC enable" "Disabled,Enabled"
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line.word 0x14 "TZEINT,Trip-Zone Interrupt Register"
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bitfld.word 0x14 6. " DCBEVT2 ,Digital comparator output B event 2 interrupt enable" "Disabled,Enabled"
|
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bitfld.word 0x14 5. " DCBEVT1 ,Digital comparator output B event 1 interrupt enable" "Disabled,Enabled"
|
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bitfld.word 0x14 4. " DCAEVT2 ,Digital comparator output A event 2 interrupt enable" "Disabled,Enabled"
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|
newline
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bitfld.word 0x14 3. " DCAEVT1 ,Digital comparator output A event 1 interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x14 2. " OST ,Trip-zone one-shot interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x14 1. " CBC ,Trip-zone cycle-by-cycle interrupt enable" "Disabled,Enabled"
|
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line.word 0x16 "TZCTL,Trip-Zone Control Register"
|
|
bitfld.word 0x16 10.--11. " DCBEVT2 ,Digital compare output B event 2 action on EPWMxB" "High-impedance,Forced high,Forced low,Disabled"
|
|
bitfld.word 0x16 8.--9. " DCBEVT1 ,Digital compare output B event 1 action on EPWMxB" "High-impedance,Forced high,Forced low,Disabled"
|
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bitfld.word 0x16 6.--7. " DCAEVT2 ,Digital compare output A event 2 action on EPWMxA" "High-impedance,Forced high,Forced low,Disabled"
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|
newline
|
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bitfld.word 0x16 4.--5. " DCAEVT1 ,Digital compare output A event 1 action on EPWMxA" "High-impedance,Forced high,Forced low,Disabled"
|
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bitfld.word 0x16 2.--3. " TZB ,Action on trip-zone event for EPWMxB select" "High-impedance,Forced high,Forced low,Disabled"
|
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bitfld.word 0x16 0.--1. " TZA ,Action on trip-zone event for EPWMxA select" "High-impedance,Forced high,Forced low,Disabled"
|
|
wgroup.word 0x2C++0x01
|
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line.word 0x00 "TZCLR,Trip-Zone Clear Register"
|
|
bitfld.word 0x00 6. " DCBEVT2 ,Clear flag for digital compare output B event 2" "No effect,Clear"
|
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bitfld.word 0x00 5. " DCBEVT1 ,Clear flag for digital compare output B event 1" "No effect,Clear"
|
|
bitfld.word 0x00 4. " DCAEVT2 ,Clear flag for digital compare output A event 2" "No effect,Clear"
|
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newline
|
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bitfld.word 0x00 3. " DCAEVT1 ,Clear flag for digital compare output A event 1" "No effect,Clear"
|
|
bitfld.word 0x00 2. " OST ,Clear flag for one-shot trip latch" "No effect,Clear"
|
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newline
|
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bitfld.word 0x00 1. " CBC ,Clear flag for cycle-by-cycle trip latch" "No effect,Clear"
|
|
bitfld.word 0x00 0. " INT ,Global interrupt clear flag" "No effect,Clear"
|
|
rgroup.word 0x2E++0x01
|
|
line.word 0x00 "TZFLG,Trip-Zone Flag Register"
|
|
bitfld.word 0x00 6. " DCBEVT2 ,Latched status flag for digital compare output B event 2" "No interrupt,Interrupt"
|
|
bitfld.word 0x00 5. " DCBEVT1 ,Latched status flag for digital compare output B event 1" "No interrupt,Interrupt"
|
|
bitfld.word 0x00 4. " DCAEVT2 ,Latched status flag for digital compare output A event 2" "No interrupt,Interrupt"
|
|
newline
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bitfld.word 0x00 3. " DCAEVT1 ,Latched status flag for digital compare output A event 1" "No interrupt,Interrupt"
|
|
bitfld.word 0x00 2. " OST ,Latched status flag for one-shot trip latch" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.word 0x00 1. " CBC ,Latched status flag for cycle-by-cycle trip latch" "No interrupt,Interrupt"
|
|
bitfld.word 0x00 0. " INT ,Global interrupt latched status flag" "No interrupt,Interrupt"
|
|
group.word 0x30++0x03
|
|
line.word 0x00 "ETSEL,Event Select Register"
|
|
bitfld.word 0x00 15. " SOCBEN ,Enable the ADC start of conversion B pulse" "Disabled,Enabled"
|
|
bitfld.word 0x00 12.--14. " SOCBSEL ,Start of conversion B option select" "DCBEVT1,TBCTR=0,TBCTR=TBPRD,TBCTR=0 or TBCTR=TBPRD,TBCTR=CMPA for INC,TBCTR=CMPA for DEC,TBCTR=CMPB for INC,TBCTR=CMPB for DEC"
|
|
bitfld.word 0x00 11. " SOCAEN ,Enable the ADC start of conversion A pulse" "Disabled,Enabled"
|
|
newline
|
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bitfld.word 0x00 8.--10. " SOCASEL ,Start of conversion A option select" "DCAEVT1,TBCTR=0,TBCTR=TBPRD,TBCTR=0 or TBCTR=TBPRD,TBCTR=CMPA for INC,TBCTR=CMPA for DEC,TBCTR=CMPB for INC,TBCTR=CMPB for DEC"
|
|
bitfld.word 0x00 3. " INTEN ,Enable ePWM interrupt generation" "Disabled,Enabled"
|
|
bitfld.word 0x00 0.--2. " INTSEL ,EPWM interrupt option select" ",TBCTR=0,TBCTR=TBPRD,TBCTR=0 or TBCTR=TBPRD,TBCTR=CMPA for INC,TBCTR=CMPA for DEC,TBCTR=CMPB for INC,TBCTR=CMPB for DEC"
|
|
line.word 0x02 "TZFLG,Trip-Zone Flag Register"
|
|
bitfld.word 0x02 6. " DCBEVT2 ,Force flag for digital compare output B event 2" "No interrupt,Interrupt"
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|
bitfld.word 0x02 5. " DCBEVT1 ,Force flag for digital compare output B event 1" "No interrupt,Interrupt"
|
|
bitfld.word 0x02 4. " DCAEVT2 ,Force flag for digital compare output A event 2" "No interrupt,Interrupt"
|
|
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bitfld.word 0x02 3. " DCAEVT1 ,Force flag for digital compare output A event 1" "No interrupt,Interrupt"
|
|
bitfld.word 0x02 2. " OST ,Force flag for one-shot trip latch" "No interrupt,Interrupt"
|
|
bitfld.word 0x02 1. " CBC ,Force flag for cycle-by-cycle trip latch" "No interrupt,Interrupt"
|
|
group.word 0x34++0x01
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|
line.word 0x00 "ET_SETCLR,Event Set/Clear Register"
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|
setclrfld.word 0x00 3. 0x04 3. 0x06 3. " SOCB ,Latched ePWM ADC start of conversation B status flag" "No interrupt,Interrupt"
|
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setclrfld.word 0x00 2. 0x04 2. 0x06 2. " SOCA ,Latched ePWM ADC start of conversation A status flag" "No interrupt,Interrupt"
|
|
setclrfld.word 0x00 0. 0x04 0. 0x06 0. " INT ,Latched ePWM interrupt status flag" "No interrupt,Interrupt"
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|
group.word 0x36++0x01
|
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line.word 0x00 "ETPS,Event Period Select Register"
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|
rbitfld.word 0x00 14.--15. " SOCBCNT ,ePWM ADC start of conversion B event counter" "No events,1 event,2 events,3 events"
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|
bitfld.word 0x00 12.--13. " SOCBPRD ,ePWM ADC start of conversion B event period select" "Disabled,1st event,2nd event,3rd event"
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|
rbitfld.word 0x00 10.--11. " SOCACNT ,ePWM ADC start of conversion A event counter" "No events,1 event,2 events,3 events"
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|
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bitfld.word 0x00 8.--9. " SOCAPRD ,ePWM ADC start of conversion A event period select" "Disabled,1st event,2nd event,3rd event"
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|
rbitfld.word 0x00 2.--3. " INTCNT ,ePWM interrupt event counter" "No events,1 event,2 events,3 events"
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|
bitfld.word 0x00 0.--1. " INTPRD ,ePWM interrupt period select" "Disabled,1st event,2nd event,3rd event"
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|
group.word 0x3E++0x01
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line.word 0x00 "PCCTL,PWM Chopping Control Register"
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|
bitfld.word 0x00 8.--10. " CHPDUTY ,Chopping clock duty cycle" "1/8,2/8,3/8,4/8,5/8,6/8,7/8,"
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bitfld.word 0x00 5.--7. " CHPFREQ ,Chopping clock frequency" "/1,/2,/3,/4,/5,/6,/7,/8"
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|
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bitfld.word 0x00 1.--4. " OSHTWTH ,One-shot pulse width" "1 x VCLK4 / 8,2 x VCLK4 / 8,3 x VCLK4 / 8,4 x VCLK4 / 8,5 x VCLK4 / 8,6 x VCLK4 / 8,7 x VCLK4 / 8,8 x VCLK4 / 8,9 x VCLK4 / 8,10 x VCLK4 / 8,11 x VCLK4 / 8,12 x VCLK4 / 8,13 x VCLK4 / 8,14 x VCLK4 / 8,15 x VCLK4 / 8,16 x VCLK4 / 8"
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bitfld.word 0x00 0. " CHPEN ,PWM-chopping enable" "Disabled,Enabled"
|
|
group.word 0x60++0x07
|
|
line.word 0x00 "DCACTL,DCA Control Register"
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|
bitfld.word 0x00 9. " EVT2FRC_SYNCSEL ,DCAEVT2 force synchronization signal select" "Synchronous,Asynchronous"
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bitfld.word 0x00 8. " EVT2SRCSEL ,DCAEVT2 source signal select" "DCAEVT2,DCEVTFILT"
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|
bitfld.word 0x00 3. " EVT1SYNCE ,DCAEVT1 SYNC enable" "Disabled,Enabled"
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|
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bitfld.word 0x00 2. " EVT1SOCE ,DCAEVT1 SOC enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 1. " EVT1FRC_SYNCSEL ,DCAEVT1 force synchronization signal select" "Synchronous,Asynchronous"
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|
bitfld.word 0x00 0. " EVT1SRCSEL ,DCAEVT1 source signal select" "DCAEVT1,DCEVTFILT"
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line.word 0x02 "DCTRIPSEL,Digital Compare Select Register"
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bitfld.word 0x02 12.--15. " DCBLCOMPSEL ,Digital compare B low input select" "/TZ1,/TZ2,/TZ3,?..."
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bitfld.word 0x02 8.--11. " DCBHCOMPSEL ,Digital compare B high input select" "/TZ1,/TZ2,/TZ3,?..."
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bitfld.word 0x02 4.--7. " DCALCOMPSEL ,Digital compare A low input select" "/TZ1,/TZ2,/TZ3,?..."
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bitfld.word 0x02 0.--3. " DCAHCOMPSEL ,Digital compare A high input select" "/TZ1,/TZ2,/TZ3,?..."
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line.word 0x04 "DCFCTL,DC Control Register"
|
|
bitfld.word 0x04 4.--5. " PULSESEL ,Pulse select for blanking and capture alignment" "TBCTR=TBPRD,TBCTR=0,?..."
|
|
bitfld.word 0x04 3. " BLANKINV ,Banking windows inversion" "Not inverted,Inverted"
|
|
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bitfld.word 0x04 2. " BLANKE ,Blanking widow enable" "Disabled,Enabled"
|
|
bitfld.word 0x04 0.--1. " SRCSEL ,Filter block signal source select" "DCAEVT1,DCAEVT2,DCBEVT1,DCBEVT2"
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line.word 0x06 "DCBCTL,DCB Control Register"
|
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bitfld.word 0x06 9. " EVT2FRC_SYNCSEL ,DCBEVT2 force synchronization signal select" "Synchronous,Asynchronous"
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bitfld.word 0x06 8. " EVT2SRCSEL ,DCBEVT2 source signal select" "DCBEVT2,DCEVTFILT"
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bitfld.word 0x06 3. " EVT1SYNCE ,DCBEVT1 SYNC enable" "Disabled,Enabled"
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bitfld.word 0x06 2. " EVT1SOCE ,DCBEVT1 SOC enable" "Disabled,Enabled"
|
|
bitfld.word 0x06 1. " EVT1FRC_SYNCSEL ,DCBEVT1 force synchronization signal select" "Synchronous,Asynchronous"
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bitfld.word 0x06 0. " EVT1SRCSEL ,DCBEVT1 source signal select" "DCBEVT1,DCEVTFILT"
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|
rgroup.word 0x68++0x01
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line.word 0x00 "DCFOFFSET,Blanking Window Offset Register"
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group.word 0x6A++0x01
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line.word 0x00 "DCCAPCTL,DC Capture Control Register"
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|
bitfld.word 0x00 1. " SHDWMODE ,TBCTR counter capture shadow select mode" "Enable shadow,Active"
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|
bitfld.word 0x00 0. " CAPE ,TBCTR counter capture enable" "Disabled,Enabled"
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rgroup.word 0x6E++0x05
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line.word 0x00 "DCFOFFSETCNT,Blanking Offset Counter Register"
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line.word 0x02 "DCCAP,Digital Compare Capture Register"
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line.word 0x04 "DCFWINDOWCNT,DC Blanking Window Counter Register"
|
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hexmask.word.byte 0x04 0.--7. 1. " WINDOWCNT ,Blanking window counter"
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endian.le
|
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width 0x0B
|
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tree.end
|
|
tree "EPWM3"
|
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base ad:0xFCF78E00
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endian.be
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width 14.
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group.word 0x00++0x05
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line.word 0x00 "TBSTS,Time-Base Status Register"
|
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eventfld.word 0x00 2. " CTRMAX ,Time-base counter max latched status" "Not reached,Reached"
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eventfld.word 0x00 1. " SYNCI ,Input synchronization latched status" "Not occurred,Occurred"
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|
rbitfld.word 0x00 0. " CTRDIR ,Time-base counter direction status" "Counting down,Counting up"
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line.word 0x02 "TBCTL,Time-Base Control Register"
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bitfld.word 0x02 14.--15. " FREE_SOFT ,Emulation mode" "Stop after INC/DEC,Stop after cycle,Free run,Free run"
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bitfld.word 0x02 13. " PHSDIR ,Phase direction" "Count down,Count up"
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bitfld.word 0x02 10.--12. " CLKDIV ,Time-base clock prescale" "/1,/2,/4,/8,/16,/32,/64,/128"
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|
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bitfld.word 0x02 7.--9. " HSPCLKDIV ,High speed time-base clock prescale" "/1,/2,/4,/6,/8,/10,/12,/14"
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eventfld.word 0x02 6. " SWFSYNC ,Software forced synchronization pulse" "No effect,Forced"
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bitfld.word 0x02 4.--5. " SYNCOSEL ,Synchronization output select" "EPWMxSYNC,CTR=zero,CTR=CMPB,Disabled"
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bitfld.word 0x02 3. " PRDLD ,Active period register load from shadow register usage" "Used,Not used"
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bitfld.word 0x02 2. " PHSEN ,Counter register load from phase register enable" "Disabled,Enabled"
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bitfld.word 0x02 0.--1. " CTRMODE ,Counter mode" "Up-count,Down-count,Up-down-count,Stop-freeze cnt"
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line.word 0x04 "TBPHS,Time-Base Counter Phase Register"
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group.word 0x08++0x05
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line.word 0x00 "TBPRD,Time-Base Period Register"
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line.word 0x02 "TBCTR,Time-Base Counter Register"
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line.word 0x04 "CMPCTL,Counter-Compare Control Register"
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rbitfld.word 0x04 9. " SHDWBFULL ,Counter-compare B shadow register full status flag" "Not full,Full"
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rbitfld.word 0x04 8. " SHDWAFULL ,Counter-compare A shadow register full status flag" "Not full,Full"
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bitfld.word 0x04 6. " SHDWBMODE ,Counter-compare B register operating mode" "Shadow,Immediate"
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bitfld.word 0x04 4. " SHDWAMODE ,Counter-compare A register operating mode" "Shadow,Immediate"
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bitfld.word 0x04 2.--3. " LOADBMODE ,Active counter-compare B load from shadow select mode" "CTR=Zero,CTR=PRD,Both,Freeze"
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bitfld.word 0x04 0.--1. " LOADBMODE ,Active counter-compare B load from shadow select mode" "CTR=Zero,CTR=PRD,Both,Freeze"
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group.word 0x10++0x01
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line.word 0x00 "CMPA,Compare A Register"
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group.word 0x14++0x17
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line.word 0x00 "AQCTLA,AQCTLA Register"
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bitfld.word 0x00 10.--11. " CBD ,Action when the time-base counter = CMPB register and the counter is decrementing" "Disabled,Clear,Set,Toggle output"
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bitfld.word 0x00 8.--9. " CBU ,Action when the time-base counter = CMPB register and the counter is incrementing" "Disabled,Clear,Set,Toggle output"
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bitfld.word 0x00 6.--7. " CAD ,Action when the time-base counter = CMPA register and the counter is decrementing" "Disabled,Clear,Set,Toggle output"
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bitfld.word 0x00 4.--5. " CAU ,Action when the time-base counter = CMPA register and the counter is incrementing" "Disabled,Clear,Set,Toggle output"
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bitfld.word 0x00 2.--3. " PRD ,Action when the counter = the period" "Disabled,Clear,Set,Toggle output"
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bitfld.word 0x00 0.--1. " ZRO ,Action when the counter = zero" "Disabled,Clear,Set,Toggle output"
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line.word 0x02 "CMPB,Compare B Register"
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line.word 0x04 "AQSFRC,AQSFRC Register"
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bitfld.word 0x04 6.--7. " RLDCSF ,AQCSFRC active register reload from shadow options" "CNT=0,CNT=period,CNT=0 or CNT=period,Load immediately"
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eventfld.word 0x04 5. " OTSFB ,One-time software forced event on output B" "No effect,Forced"
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bitfld.word 0x04 3.--4. " ACTSFB ,Action when one-time software force B is invoked" "Disabled,Clear,Set,Toggle"
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newline
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eventfld.word 0x04 2. " OTSFA ,One-time software forced event on output A" "No effect,Forced"
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bitfld.word 0x04 0.--1. " ACTSFA ,Action when one-time software force A is invoked" "Disabled,Clear,Set,Toggle"
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line.word 0x06 "AQCTLA,AQCTLA Register"
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bitfld.word 0x06 10.--11. " CBD ,Action when the time-base counter = CMPB register and the counter is decrementing" "Disabled,Clear,Set,Toggle output"
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bitfld.word 0x06 8.--9. " CBU ,Action when the time-base counter = CMPB register and the counter is incrementing" "Disabled,Clear,Set,Toggle output"
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bitfld.word 0x06 6.--7. " CAD ,Action when the time-base counter = CMPA register and the counter is decrementing" "Disabled,Clear,Set,Toggle output"
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bitfld.word 0x06 4.--5. " CAU ,Action when the time-base counter = CMPA register and the counter is incrementing" "Disabled,Clear,Set,Toggle output"
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bitfld.word 0x06 2.--3. " PRD ,Action when the counter = the period" "Disabled,Clear,Set,Toggle output"
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bitfld.word 0x06 0.--1. " ZRO ,Action when the counter = zero" "Disabled,Clear,Set,Toggle output"
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line.word 0x08 "DBCTL,Dead-Band Control Register"
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bitfld.word 0x08 15. " HALFCYCLE ,Half cycle clocking enable" "Disabled,Enabled"
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bitfld.word 0x08 4.--5. " IN_MODE ,Dead band input mode control (A In for edge / B In for edge)" "Both / -,Falling / Rising,Rising / Falling,- / Both"
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newline
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bitfld.word 0x08 2.--3. " POLSEL ,Active polarity select control" "High,Low complementary,High complementary,Low"
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bitfld.word 0x08 0.--1. " OUT_MODE ,Dead band output mode control" "Bypass,Rising disabled,Falling disabled,- / Both"
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line.word 0x0A "AQCSFRC,AQCSFRC register"
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bitfld.word 0x0A 2.--3. " CSFB ,Continuous software force on output B" "Disabled,Forced low,Forced high,Disabled"
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bitfld.word 0x0A 0.--1. " CSFA ,Continuous software force on output A" "Disabled,Forced low,Forced high,Disabled"
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line.word 0x0C "DBFED,Falling Edge Delay Register"
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hexmask.word 0x0C 0.--9. 1. " DEL ,Falling edge delay count"
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line.word 0x0E "DBRED,Rising Edge Delay Register"
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hexmask.word 0x0E 0.--9. 1. " DEL ,Rising edge delay count"
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line.word 0x10 "TZDCSEL,Digital Compare Select Register"
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bitfld.word 0x10 9.--11. " DCBEVT2 ,Digital compare output B event 2 selection (DCBL / DCBH)" "Event,Don't care / Low,Don't care / High,Low / Don't care,High / Don't care,High / Low,?..."
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bitfld.word 0x10 6.--8. " DCBEVT1 ,Digital compare output B event 1 selection (DCBL / DCBH)" "Event,Don't care / Low,Don't care / High,Low / Don't care,High / Don't care,High / Low,?..."
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newline
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bitfld.word 0x10 3.--5. " DCAEVT2 ,Digital compare output A event 2 selection (DCAL / DCAH)" "Event,Don't care / Low,Don't care / High,Low / Don't care,High / Don't care,High / Low,?..."
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bitfld.word 0x10 0.--2. " DCAEVT1 ,Digital compare output A event 1 selection (DCAL / DCAH)" "Event,Don't care / Low,Don't care / High,Low / Don't care,High / Don't care,High / Low,?..."
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line.word 0x12 "TZSEL,Trip-Zone Select Register"
|
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rbitfld.word 0x12 15. " DCBEVT1 ,Digital compare output B event 1 enable" "Disabled,Enabled"
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rbitfld.word 0x12 14. " DCAEVT1 ,Digital compare output A event 1 enable" "Disabled,Enabled"
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bitfld.word 0x12 13. " OSHT6 ,Trip-zone 6 (/TZ6) as one-shot trip enable" "Disabled,Enabled"
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bitfld.word 0x12 12. " OSHT5 ,Trip-zone 5 (/TZ5) as one-shot trip enable" "Disabled,Enabled"
|
|
bitfld.word 0x12 11. " OSHT4 ,Trip-zone 4 (/TZ4) as one-shot trip enable" "Disabled,Enabled"
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bitfld.word 0x12 10. " OSHT3 ,Trip-zone 3 (/TZ3) as one-shot trip enable" "Disabled,Enabled"
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newline
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bitfld.word 0x12 9. " OSHT2 ,Trip-zone 2 (/TZ2) as one-shot trip enable" "Disabled,Enabled"
|
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bitfld.word 0x12 8. " OSHT1 ,Trip-zone 1 (/TZ1) as one-shot trip enable" "Disabled,Enabled"
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rbitfld.word 0x12 7. " DCBEVT2 ,Digital compare output B event 2 enable" "Disabled,Enabled"
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rbitfld.word 0x12 6. " DCAEVT2 ,Digital compare output A event 2 enable" "Disabled,Enabled"
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bitfld.word 0x12 5. " CBC6 ,Trip-zone 6 (/TZ6) as CBC enable" "Disabled,Enabled"
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bitfld.word 0x12 4. " CBC5 ,Trip-zone 5 (/TZ5) as CBC enable" "Disabled,Enabled"
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bitfld.word 0x12 3. " CBC4 ,Trip-zone 4 (/TZ4) as CBC enable" "Disabled,Enabled"
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bitfld.word 0x12 2. " CBC3 ,Trip-zone 3 (/TZ3) as CBC enable" "Disabled,Enabled"
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bitfld.word 0x12 1. " CBC2 ,Trip-zone 2 (/TZ2) as CBC enable" "Disabled,Enabled"
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bitfld.word 0x12 0. " CBC1 ,Trip-zone 1 (/TZ1) as CBC enable" "Disabled,Enabled"
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line.word 0x14 "TZEINT,Trip-Zone Interrupt Register"
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bitfld.word 0x14 6. " DCBEVT2 ,Digital comparator output B event 2 interrupt enable" "Disabled,Enabled"
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bitfld.word 0x14 5. " DCBEVT1 ,Digital comparator output B event 1 interrupt enable" "Disabled,Enabled"
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bitfld.word 0x14 4. " DCAEVT2 ,Digital comparator output A event 2 interrupt enable" "Disabled,Enabled"
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bitfld.word 0x14 3. " DCAEVT1 ,Digital comparator output A event 1 interrupt enable" "Disabled,Enabled"
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bitfld.word 0x14 2. " OST ,Trip-zone one-shot interrupt enable" "Disabled,Enabled"
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bitfld.word 0x14 1. " CBC ,Trip-zone cycle-by-cycle interrupt enable" "Disabled,Enabled"
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line.word 0x16 "TZCTL,Trip-Zone Control Register"
|
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bitfld.word 0x16 10.--11. " DCBEVT2 ,Digital compare output B event 2 action on EPWMxB" "High-impedance,Forced high,Forced low,Disabled"
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bitfld.word 0x16 8.--9. " DCBEVT1 ,Digital compare output B event 1 action on EPWMxB" "High-impedance,Forced high,Forced low,Disabled"
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bitfld.word 0x16 6.--7. " DCAEVT2 ,Digital compare output A event 2 action on EPWMxA" "High-impedance,Forced high,Forced low,Disabled"
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newline
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bitfld.word 0x16 4.--5. " DCAEVT1 ,Digital compare output A event 1 action on EPWMxA" "High-impedance,Forced high,Forced low,Disabled"
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bitfld.word 0x16 2.--3. " TZB ,Action on trip-zone event for EPWMxB select" "High-impedance,Forced high,Forced low,Disabled"
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bitfld.word 0x16 0.--1. " TZA ,Action on trip-zone event for EPWMxA select" "High-impedance,Forced high,Forced low,Disabled"
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wgroup.word 0x2C++0x01
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line.word 0x00 "TZCLR,Trip-Zone Clear Register"
|
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bitfld.word 0x00 6. " DCBEVT2 ,Clear flag for digital compare output B event 2" "No effect,Clear"
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bitfld.word 0x00 5. " DCBEVT1 ,Clear flag for digital compare output B event 1" "No effect,Clear"
|
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bitfld.word 0x00 4. " DCAEVT2 ,Clear flag for digital compare output A event 2" "No effect,Clear"
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bitfld.word 0x00 3. " DCAEVT1 ,Clear flag for digital compare output A event 1" "No effect,Clear"
|
|
bitfld.word 0x00 2. " OST ,Clear flag for one-shot trip latch" "No effect,Clear"
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bitfld.word 0x00 1. " CBC ,Clear flag for cycle-by-cycle trip latch" "No effect,Clear"
|
|
bitfld.word 0x00 0. " INT ,Global interrupt clear flag" "No effect,Clear"
|
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rgroup.word 0x2E++0x01
|
|
line.word 0x00 "TZFLG,Trip-Zone Flag Register"
|
|
bitfld.word 0x00 6. " DCBEVT2 ,Latched status flag for digital compare output B event 2" "No interrupt,Interrupt"
|
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bitfld.word 0x00 5. " DCBEVT1 ,Latched status flag for digital compare output B event 1" "No interrupt,Interrupt"
|
|
bitfld.word 0x00 4. " DCAEVT2 ,Latched status flag for digital compare output A event 2" "No interrupt,Interrupt"
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bitfld.word 0x00 3. " DCAEVT1 ,Latched status flag for digital compare output A event 1" "No interrupt,Interrupt"
|
|
bitfld.word 0x00 2. " OST ,Latched status flag for one-shot trip latch" "No interrupt,Interrupt"
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|
newline
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bitfld.word 0x00 1. " CBC ,Latched status flag for cycle-by-cycle trip latch" "No interrupt,Interrupt"
|
|
bitfld.word 0x00 0. " INT ,Global interrupt latched status flag" "No interrupt,Interrupt"
|
|
group.word 0x30++0x03
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line.word 0x00 "ETSEL,Event Select Register"
|
|
bitfld.word 0x00 15. " SOCBEN ,Enable the ADC start of conversion B pulse" "Disabled,Enabled"
|
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bitfld.word 0x00 12.--14. " SOCBSEL ,Start of conversion B option select" "DCBEVT1,TBCTR=0,TBCTR=TBPRD,TBCTR=0 or TBCTR=TBPRD,TBCTR=CMPA for INC,TBCTR=CMPA for DEC,TBCTR=CMPB for INC,TBCTR=CMPB for DEC"
|
|
bitfld.word 0x00 11. " SOCAEN ,Enable the ADC start of conversion A pulse" "Disabled,Enabled"
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|
newline
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bitfld.word 0x00 8.--10. " SOCASEL ,Start of conversion A option select" "DCAEVT1,TBCTR=0,TBCTR=TBPRD,TBCTR=0 or TBCTR=TBPRD,TBCTR=CMPA for INC,TBCTR=CMPA for DEC,TBCTR=CMPB for INC,TBCTR=CMPB for DEC"
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bitfld.word 0x00 3. " INTEN ,Enable ePWM interrupt generation" "Disabled,Enabled"
|
|
bitfld.word 0x00 0.--2. " INTSEL ,EPWM interrupt option select" ",TBCTR=0,TBCTR=TBPRD,TBCTR=0 or TBCTR=TBPRD,TBCTR=CMPA for INC,TBCTR=CMPA for DEC,TBCTR=CMPB for INC,TBCTR=CMPB for DEC"
|
|
line.word 0x02 "TZFLG,Trip-Zone Flag Register"
|
|
bitfld.word 0x02 6. " DCBEVT2 ,Force flag for digital compare output B event 2" "No interrupt,Interrupt"
|
|
bitfld.word 0x02 5. " DCBEVT1 ,Force flag for digital compare output B event 1" "No interrupt,Interrupt"
|
|
bitfld.word 0x02 4. " DCAEVT2 ,Force flag for digital compare output A event 2" "No interrupt,Interrupt"
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|
newline
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bitfld.word 0x02 3. " DCAEVT1 ,Force flag for digital compare output A event 1" "No interrupt,Interrupt"
|
|
bitfld.word 0x02 2. " OST ,Force flag for one-shot trip latch" "No interrupt,Interrupt"
|
|
bitfld.word 0x02 1. " CBC ,Force flag for cycle-by-cycle trip latch" "No interrupt,Interrupt"
|
|
group.word 0x34++0x01
|
|
line.word 0x00 "ET_SETCLR,Event Set/Clear Register"
|
|
setclrfld.word 0x00 3. 0x04 3. 0x06 3. " SOCB ,Latched ePWM ADC start of conversation B status flag" "No interrupt,Interrupt"
|
|
setclrfld.word 0x00 2. 0x04 2. 0x06 2. " SOCA ,Latched ePWM ADC start of conversation A status flag" "No interrupt,Interrupt"
|
|
setclrfld.word 0x00 0. 0x04 0. 0x06 0. " INT ,Latched ePWM interrupt status flag" "No interrupt,Interrupt"
|
|
group.word 0x36++0x01
|
|
line.word 0x00 "ETPS,Event Period Select Register"
|
|
rbitfld.word 0x00 14.--15. " SOCBCNT ,ePWM ADC start of conversion B event counter" "No events,1 event,2 events,3 events"
|
|
bitfld.word 0x00 12.--13. " SOCBPRD ,ePWM ADC start of conversion B event period select" "Disabled,1st event,2nd event,3rd event"
|
|
rbitfld.word 0x00 10.--11. " SOCACNT ,ePWM ADC start of conversion A event counter" "No events,1 event,2 events,3 events"
|
|
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bitfld.word 0x00 8.--9. " SOCAPRD ,ePWM ADC start of conversion A event period select" "Disabled,1st event,2nd event,3rd event"
|
|
rbitfld.word 0x00 2.--3. " INTCNT ,ePWM interrupt event counter" "No events,1 event,2 events,3 events"
|
|
bitfld.word 0x00 0.--1. " INTPRD ,ePWM interrupt period select" "Disabled,1st event,2nd event,3rd event"
|
|
group.word 0x3E++0x01
|
|
line.word 0x00 "PCCTL,PWM Chopping Control Register"
|
|
bitfld.word 0x00 8.--10. " CHPDUTY ,Chopping clock duty cycle" "1/8,2/8,3/8,4/8,5/8,6/8,7/8,"
|
|
bitfld.word 0x00 5.--7. " CHPFREQ ,Chopping clock frequency" "/1,/2,/3,/4,/5,/6,/7,/8"
|
|
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|
bitfld.word 0x00 1.--4. " OSHTWTH ,One-shot pulse width" "1 x VCLK4 / 8,2 x VCLK4 / 8,3 x VCLK4 / 8,4 x VCLK4 / 8,5 x VCLK4 / 8,6 x VCLK4 / 8,7 x VCLK4 / 8,8 x VCLK4 / 8,9 x VCLK4 / 8,10 x VCLK4 / 8,11 x VCLK4 / 8,12 x VCLK4 / 8,13 x VCLK4 / 8,14 x VCLK4 / 8,15 x VCLK4 / 8,16 x VCLK4 / 8"
|
|
bitfld.word 0x00 0. " CHPEN ,PWM-chopping enable" "Disabled,Enabled"
|
|
group.word 0x60++0x07
|
|
line.word 0x00 "DCACTL,DCA Control Register"
|
|
bitfld.word 0x00 9. " EVT2FRC_SYNCSEL ,DCAEVT2 force synchronization signal select" "Synchronous,Asynchronous"
|
|
bitfld.word 0x00 8. " EVT2SRCSEL ,DCAEVT2 source signal select" "DCAEVT2,DCEVTFILT"
|
|
bitfld.word 0x00 3. " EVT1SYNCE ,DCAEVT1 SYNC enable" "Disabled,Enabled"
|
|
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bitfld.word 0x00 2. " EVT1SOCE ,DCAEVT1 SOC enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 1. " EVT1FRC_SYNCSEL ,DCAEVT1 force synchronization signal select" "Synchronous,Asynchronous"
|
|
bitfld.word 0x00 0. " EVT1SRCSEL ,DCAEVT1 source signal select" "DCAEVT1,DCEVTFILT"
|
|
line.word 0x02 "DCTRIPSEL,Digital Compare Select Register"
|
|
bitfld.word 0x02 12.--15. " DCBLCOMPSEL ,Digital compare B low input select" "/TZ1,/TZ2,/TZ3,?..."
|
|
bitfld.word 0x02 8.--11. " DCBHCOMPSEL ,Digital compare B high input select" "/TZ1,/TZ2,/TZ3,?..."
|
|
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bitfld.word 0x02 4.--7. " DCALCOMPSEL ,Digital compare A low input select" "/TZ1,/TZ2,/TZ3,?..."
|
|
bitfld.word 0x02 0.--3. " DCAHCOMPSEL ,Digital compare A high input select" "/TZ1,/TZ2,/TZ3,?..."
|
|
line.word 0x04 "DCFCTL,DC Control Register"
|
|
bitfld.word 0x04 4.--5. " PULSESEL ,Pulse select for blanking and capture alignment" "TBCTR=TBPRD,TBCTR=0,?..."
|
|
bitfld.word 0x04 3. " BLANKINV ,Banking windows inversion" "Not inverted,Inverted"
|
|
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|
|
bitfld.word 0x04 2. " BLANKE ,Blanking widow enable" "Disabled,Enabled"
|
|
bitfld.word 0x04 0.--1. " SRCSEL ,Filter block signal source select" "DCAEVT1,DCAEVT2,DCBEVT1,DCBEVT2"
|
|
line.word 0x06 "DCBCTL,DCB Control Register"
|
|
bitfld.word 0x06 9. " EVT2FRC_SYNCSEL ,DCBEVT2 force synchronization signal select" "Synchronous,Asynchronous"
|
|
bitfld.word 0x06 8. " EVT2SRCSEL ,DCBEVT2 source signal select" "DCBEVT2,DCEVTFILT"
|
|
bitfld.word 0x06 3. " EVT1SYNCE ,DCBEVT1 SYNC enable" "Disabled,Enabled"
|
|
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|
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bitfld.word 0x06 2. " EVT1SOCE ,DCBEVT1 SOC enable" "Disabled,Enabled"
|
|
bitfld.word 0x06 1. " EVT1FRC_SYNCSEL ,DCBEVT1 force synchronization signal select" "Synchronous,Asynchronous"
|
|
bitfld.word 0x06 0. " EVT1SRCSEL ,DCBEVT1 source signal select" "DCBEVT1,DCEVTFILT"
|
|
rgroup.word 0x68++0x01
|
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line.word 0x00 "DCFOFFSET,Blanking Window Offset Register"
|
|
group.word 0x6A++0x01
|
|
line.word 0x00 "DCCAPCTL,DC Capture Control Register"
|
|
bitfld.word 0x00 1. " SHDWMODE ,TBCTR counter capture shadow select mode" "Enable shadow,Active"
|
|
bitfld.word 0x00 0. " CAPE ,TBCTR counter capture enable" "Disabled,Enabled"
|
|
rgroup.word 0x6E++0x05
|
|
line.word 0x00 "DCFOFFSETCNT,Blanking Offset Counter Register"
|
|
line.word 0x02 "DCCAP,Digital Compare Capture Register"
|
|
line.word 0x04 "DCFWINDOWCNT,DC Blanking Window Counter Register"
|
|
hexmask.word.byte 0x04 0.--7. 1. " WINDOWCNT ,Blanking window counter"
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|
endian.le
|
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width 0x0B
|
|
tree.end
|
|
tree "EPWM4"
|
|
base ad:0xFCF78F00
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endian.be
|
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width 14.
|
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group.word 0x00++0x05
|
|
line.word 0x00 "TBSTS,Time-Base Status Register"
|
|
eventfld.word 0x00 2. " CTRMAX ,Time-base counter max latched status" "Not reached,Reached"
|
|
eventfld.word 0x00 1. " SYNCI ,Input synchronization latched status" "Not occurred,Occurred"
|
|
rbitfld.word 0x00 0. " CTRDIR ,Time-base counter direction status" "Counting down,Counting up"
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|
line.word 0x02 "TBCTL,Time-Base Control Register"
|
|
bitfld.word 0x02 14.--15. " FREE_SOFT ,Emulation mode" "Stop after INC/DEC,Stop after cycle,Free run,Free run"
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bitfld.word 0x02 13. " PHSDIR ,Phase direction" "Count down,Count up"
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|
bitfld.word 0x02 10.--12. " CLKDIV ,Time-base clock prescale" "/1,/2,/4,/8,/16,/32,/64,/128"
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|
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bitfld.word 0x02 7.--9. " HSPCLKDIV ,High speed time-base clock prescale" "/1,/2,/4,/6,/8,/10,/12,/14"
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eventfld.word 0x02 6. " SWFSYNC ,Software forced synchronization pulse" "No effect,Forced"
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bitfld.word 0x02 4.--5. " SYNCOSEL ,Synchronization output select" "EPWMxSYNC,CTR=zero,CTR=CMPB,Disabled"
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|
newline
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bitfld.word 0x02 3. " PRDLD ,Active period register load from shadow register usage" "Used,Not used"
|
|
bitfld.word 0x02 2. " PHSEN ,Counter register load from phase register enable" "Disabled,Enabled"
|
|
bitfld.word 0x02 0.--1. " CTRMODE ,Counter mode" "Up-count,Down-count,Up-down-count,Stop-freeze cnt"
|
|
line.word 0x04 "TBPHS,Time-Base Counter Phase Register"
|
|
group.word 0x08++0x05
|
|
line.word 0x00 "TBPRD,Time-Base Period Register"
|
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line.word 0x02 "TBCTR,Time-Base Counter Register"
|
|
line.word 0x04 "CMPCTL,Counter-Compare Control Register"
|
|
rbitfld.word 0x04 9. " SHDWBFULL ,Counter-compare B shadow register full status flag" "Not full,Full"
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rbitfld.word 0x04 8. " SHDWAFULL ,Counter-compare A shadow register full status flag" "Not full,Full"
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|
bitfld.word 0x04 6. " SHDWBMODE ,Counter-compare B register operating mode" "Shadow,Immediate"
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|
newline
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bitfld.word 0x04 4. " SHDWAMODE ,Counter-compare A register operating mode" "Shadow,Immediate"
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|
bitfld.word 0x04 2.--3. " LOADBMODE ,Active counter-compare B load from shadow select mode" "CTR=Zero,CTR=PRD,Both,Freeze"
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|
bitfld.word 0x04 0.--1. " LOADBMODE ,Active counter-compare B load from shadow select mode" "CTR=Zero,CTR=PRD,Both,Freeze"
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group.word 0x10++0x01
|
|
line.word 0x00 "CMPA,Compare A Register"
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group.word 0x14++0x17
|
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line.word 0x00 "AQCTLA,AQCTLA Register"
|
|
bitfld.word 0x00 10.--11. " CBD ,Action when the time-base counter = CMPB register and the counter is decrementing" "Disabled,Clear,Set,Toggle output"
|
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bitfld.word 0x00 8.--9. " CBU ,Action when the time-base counter = CMPB register and the counter is incrementing" "Disabled,Clear,Set,Toggle output"
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bitfld.word 0x00 6.--7. " CAD ,Action when the time-base counter = CMPA register and the counter is decrementing" "Disabled,Clear,Set,Toggle output"
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|
newline
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bitfld.word 0x00 4.--5. " CAU ,Action when the time-base counter = CMPA register and the counter is incrementing" "Disabled,Clear,Set,Toggle output"
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bitfld.word 0x00 2.--3. " PRD ,Action when the counter = the period" "Disabled,Clear,Set,Toggle output"
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bitfld.word 0x00 0.--1. " ZRO ,Action when the counter = zero" "Disabled,Clear,Set,Toggle output"
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line.word 0x02 "CMPB,Compare B Register"
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line.word 0x04 "AQSFRC,AQSFRC Register"
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bitfld.word 0x04 6.--7. " RLDCSF ,AQCSFRC active register reload from shadow options" "CNT=0,CNT=period,CNT=0 or CNT=period,Load immediately"
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eventfld.word 0x04 5. " OTSFB ,One-time software forced event on output B" "No effect,Forced"
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bitfld.word 0x04 3.--4. " ACTSFB ,Action when one-time software force B is invoked" "Disabled,Clear,Set,Toggle"
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|
newline
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eventfld.word 0x04 2. " OTSFA ,One-time software forced event on output A" "No effect,Forced"
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|
bitfld.word 0x04 0.--1. " ACTSFA ,Action when one-time software force A is invoked" "Disabled,Clear,Set,Toggle"
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line.word 0x06 "AQCTLA,AQCTLA Register"
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bitfld.word 0x06 10.--11. " CBD ,Action when the time-base counter = CMPB register and the counter is decrementing" "Disabled,Clear,Set,Toggle output"
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bitfld.word 0x06 8.--9. " CBU ,Action when the time-base counter = CMPB register and the counter is incrementing" "Disabled,Clear,Set,Toggle output"
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bitfld.word 0x06 6.--7. " CAD ,Action when the time-base counter = CMPA register and the counter is decrementing" "Disabled,Clear,Set,Toggle output"
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|
newline
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bitfld.word 0x06 4.--5. " CAU ,Action when the time-base counter = CMPA register and the counter is incrementing" "Disabled,Clear,Set,Toggle output"
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bitfld.word 0x06 2.--3. " PRD ,Action when the counter = the period" "Disabled,Clear,Set,Toggle output"
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bitfld.word 0x06 0.--1. " ZRO ,Action when the counter = zero" "Disabled,Clear,Set,Toggle output"
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line.word 0x08 "DBCTL,Dead-Band Control Register"
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bitfld.word 0x08 15. " HALFCYCLE ,Half cycle clocking enable" "Disabled,Enabled"
|
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bitfld.word 0x08 4.--5. " IN_MODE ,Dead band input mode control (A In for edge / B In for edge)" "Both / -,Falling / Rising,Rising / Falling,- / Both"
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newline
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bitfld.word 0x08 2.--3. " POLSEL ,Active polarity select control" "High,Low complementary,High complementary,Low"
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bitfld.word 0x08 0.--1. " OUT_MODE ,Dead band output mode control" "Bypass,Rising disabled,Falling disabled,- / Both"
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line.word 0x0A "AQCSFRC,AQCSFRC register"
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bitfld.word 0x0A 2.--3. " CSFB ,Continuous software force on output B" "Disabled,Forced low,Forced high,Disabled"
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bitfld.word 0x0A 0.--1. " CSFA ,Continuous software force on output A" "Disabled,Forced low,Forced high,Disabled"
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line.word 0x0C "DBFED,Falling Edge Delay Register"
|
|
hexmask.word 0x0C 0.--9. 1. " DEL ,Falling edge delay count"
|
|
line.word 0x0E "DBRED,Rising Edge Delay Register"
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hexmask.word 0x0E 0.--9. 1. " DEL ,Rising edge delay count"
|
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line.word 0x10 "TZDCSEL,Digital Compare Select Register"
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bitfld.word 0x10 9.--11. " DCBEVT2 ,Digital compare output B event 2 selection (DCBL / DCBH)" "Event,Don't care / Low,Don't care / High,Low / Don't care,High / Don't care,High / Low,?..."
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bitfld.word 0x10 6.--8. " DCBEVT1 ,Digital compare output B event 1 selection (DCBL / DCBH)" "Event,Don't care / Low,Don't care / High,Low / Don't care,High / Don't care,High / Low,?..."
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newline
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bitfld.word 0x10 3.--5. " DCAEVT2 ,Digital compare output A event 2 selection (DCAL / DCAH)" "Event,Don't care / Low,Don't care / High,Low / Don't care,High / Don't care,High / Low,?..."
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bitfld.word 0x10 0.--2. " DCAEVT1 ,Digital compare output A event 1 selection (DCAL / DCAH)" "Event,Don't care / Low,Don't care / High,Low / Don't care,High / Don't care,High / Low,?..."
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line.word 0x12 "TZSEL,Trip-Zone Select Register"
|
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rbitfld.word 0x12 15. " DCBEVT1 ,Digital compare output B event 1 enable" "Disabled,Enabled"
|
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rbitfld.word 0x12 14. " DCAEVT1 ,Digital compare output A event 1 enable" "Disabled,Enabled"
|
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bitfld.word 0x12 13. " OSHT6 ,Trip-zone 6 (/TZ6) as one-shot trip enable" "Disabled,Enabled"
|
|
newline
|
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bitfld.word 0x12 12. " OSHT5 ,Trip-zone 5 (/TZ5) as one-shot trip enable" "Disabled,Enabled"
|
|
bitfld.word 0x12 11. " OSHT4 ,Trip-zone 4 (/TZ4) as one-shot trip enable" "Disabled,Enabled"
|
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bitfld.word 0x12 10. " OSHT3 ,Trip-zone 3 (/TZ3) as one-shot trip enable" "Disabled,Enabled"
|
|
newline
|
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bitfld.word 0x12 9. " OSHT2 ,Trip-zone 2 (/TZ2) as one-shot trip enable" "Disabled,Enabled"
|
|
bitfld.word 0x12 8. " OSHT1 ,Trip-zone 1 (/TZ1) as one-shot trip enable" "Disabled,Enabled"
|
|
rbitfld.word 0x12 7. " DCBEVT2 ,Digital compare output B event 2 enable" "Disabled,Enabled"
|
|
newline
|
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rbitfld.word 0x12 6. " DCAEVT2 ,Digital compare output A event 2 enable" "Disabled,Enabled"
|
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bitfld.word 0x12 5. " CBC6 ,Trip-zone 6 (/TZ6) as CBC enable" "Disabled,Enabled"
|
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bitfld.word 0x12 4. " CBC5 ,Trip-zone 5 (/TZ5) as CBC enable" "Disabled,Enabled"
|
|
newline
|
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bitfld.word 0x12 3. " CBC4 ,Trip-zone 4 (/TZ4) as CBC enable" "Disabled,Enabled"
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|
bitfld.word 0x12 2. " CBC3 ,Trip-zone 3 (/TZ3) as CBC enable" "Disabled,Enabled"
|
|
newline
|
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bitfld.word 0x12 1. " CBC2 ,Trip-zone 2 (/TZ2) as CBC enable" "Disabled,Enabled"
|
|
bitfld.word 0x12 0. " CBC1 ,Trip-zone 1 (/TZ1) as CBC enable" "Disabled,Enabled"
|
|
line.word 0x14 "TZEINT,Trip-Zone Interrupt Register"
|
|
bitfld.word 0x14 6. " DCBEVT2 ,Digital comparator output B event 2 interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x14 5. " DCBEVT1 ,Digital comparator output B event 1 interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x14 4. " DCAEVT2 ,Digital comparator output A event 2 interrupt enable" "Disabled,Enabled"
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|
newline
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bitfld.word 0x14 3. " DCAEVT1 ,Digital comparator output A event 1 interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x14 2. " OST ,Trip-zone one-shot interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x14 1. " CBC ,Trip-zone cycle-by-cycle interrupt enable" "Disabled,Enabled"
|
|
line.word 0x16 "TZCTL,Trip-Zone Control Register"
|
|
bitfld.word 0x16 10.--11. " DCBEVT2 ,Digital compare output B event 2 action on EPWMxB" "High-impedance,Forced high,Forced low,Disabled"
|
|
bitfld.word 0x16 8.--9. " DCBEVT1 ,Digital compare output B event 1 action on EPWMxB" "High-impedance,Forced high,Forced low,Disabled"
|
|
bitfld.word 0x16 6.--7. " DCAEVT2 ,Digital compare output A event 2 action on EPWMxA" "High-impedance,Forced high,Forced low,Disabled"
|
|
newline
|
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bitfld.word 0x16 4.--5. " DCAEVT1 ,Digital compare output A event 1 action on EPWMxA" "High-impedance,Forced high,Forced low,Disabled"
|
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bitfld.word 0x16 2.--3. " TZB ,Action on trip-zone event for EPWMxB select" "High-impedance,Forced high,Forced low,Disabled"
|
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bitfld.word 0x16 0.--1. " TZA ,Action on trip-zone event for EPWMxA select" "High-impedance,Forced high,Forced low,Disabled"
|
|
wgroup.word 0x2C++0x01
|
|
line.word 0x00 "TZCLR,Trip-Zone Clear Register"
|
|
bitfld.word 0x00 6. " DCBEVT2 ,Clear flag for digital compare output B event 2" "No effect,Clear"
|
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bitfld.word 0x00 5. " DCBEVT1 ,Clear flag for digital compare output B event 1" "No effect,Clear"
|
|
bitfld.word 0x00 4. " DCAEVT2 ,Clear flag for digital compare output A event 2" "No effect,Clear"
|
|
newline
|
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bitfld.word 0x00 3. " DCAEVT1 ,Clear flag for digital compare output A event 1" "No effect,Clear"
|
|
bitfld.word 0x00 2. " OST ,Clear flag for one-shot trip latch" "No effect,Clear"
|
|
newline
|
|
bitfld.word 0x00 1. " CBC ,Clear flag for cycle-by-cycle trip latch" "No effect,Clear"
|
|
bitfld.word 0x00 0. " INT ,Global interrupt clear flag" "No effect,Clear"
|
|
rgroup.word 0x2E++0x01
|
|
line.word 0x00 "TZFLG,Trip-Zone Flag Register"
|
|
bitfld.word 0x00 6. " DCBEVT2 ,Latched status flag for digital compare output B event 2" "No interrupt,Interrupt"
|
|
bitfld.word 0x00 5. " DCBEVT1 ,Latched status flag for digital compare output B event 1" "No interrupt,Interrupt"
|
|
bitfld.word 0x00 4. " DCAEVT2 ,Latched status flag for digital compare output A event 2" "No interrupt,Interrupt"
|
|
newline
|
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bitfld.word 0x00 3. " DCAEVT1 ,Latched status flag for digital compare output A event 1" "No interrupt,Interrupt"
|
|
bitfld.word 0x00 2. " OST ,Latched status flag for one-shot trip latch" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.word 0x00 1. " CBC ,Latched status flag for cycle-by-cycle trip latch" "No interrupt,Interrupt"
|
|
bitfld.word 0x00 0. " INT ,Global interrupt latched status flag" "No interrupt,Interrupt"
|
|
group.word 0x30++0x03
|
|
line.word 0x00 "ETSEL,Event Select Register"
|
|
bitfld.word 0x00 15. " SOCBEN ,Enable the ADC start of conversion B pulse" "Disabled,Enabled"
|
|
bitfld.word 0x00 12.--14. " SOCBSEL ,Start of conversion B option select" "DCBEVT1,TBCTR=0,TBCTR=TBPRD,TBCTR=0 or TBCTR=TBPRD,TBCTR=CMPA for INC,TBCTR=CMPA for DEC,TBCTR=CMPB for INC,TBCTR=CMPB for DEC"
|
|
bitfld.word 0x00 11. " SOCAEN ,Enable the ADC start of conversion A pulse" "Disabled,Enabled"
|
|
newline
|
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bitfld.word 0x00 8.--10. " SOCASEL ,Start of conversion A option select" "DCAEVT1,TBCTR=0,TBCTR=TBPRD,TBCTR=0 or TBCTR=TBPRD,TBCTR=CMPA for INC,TBCTR=CMPA for DEC,TBCTR=CMPB for INC,TBCTR=CMPB for DEC"
|
|
bitfld.word 0x00 3. " INTEN ,Enable ePWM interrupt generation" "Disabled,Enabled"
|
|
bitfld.word 0x00 0.--2. " INTSEL ,EPWM interrupt option select" ",TBCTR=0,TBCTR=TBPRD,TBCTR=0 or TBCTR=TBPRD,TBCTR=CMPA for INC,TBCTR=CMPA for DEC,TBCTR=CMPB for INC,TBCTR=CMPB for DEC"
|
|
line.word 0x02 "TZFLG,Trip-Zone Flag Register"
|
|
bitfld.word 0x02 6. " DCBEVT2 ,Force flag for digital compare output B event 2" "No interrupt,Interrupt"
|
|
bitfld.word 0x02 5. " DCBEVT1 ,Force flag for digital compare output B event 1" "No interrupt,Interrupt"
|
|
bitfld.word 0x02 4. " DCAEVT2 ,Force flag for digital compare output A event 2" "No interrupt,Interrupt"
|
|
newline
|
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bitfld.word 0x02 3. " DCAEVT1 ,Force flag for digital compare output A event 1" "No interrupt,Interrupt"
|
|
bitfld.word 0x02 2. " OST ,Force flag for one-shot trip latch" "No interrupt,Interrupt"
|
|
bitfld.word 0x02 1. " CBC ,Force flag for cycle-by-cycle trip latch" "No interrupt,Interrupt"
|
|
group.word 0x34++0x01
|
|
line.word 0x00 "ET_SETCLR,Event Set/Clear Register"
|
|
setclrfld.word 0x00 3. 0x04 3. 0x06 3. " SOCB ,Latched ePWM ADC start of conversation B status flag" "No interrupt,Interrupt"
|
|
setclrfld.word 0x00 2. 0x04 2. 0x06 2. " SOCA ,Latched ePWM ADC start of conversation A status flag" "No interrupt,Interrupt"
|
|
setclrfld.word 0x00 0. 0x04 0. 0x06 0. " INT ,Latched ePWM interrupt status flag" "No interrupt,Interrupt"
|
|
group.word 0x36++0x01
|
|
line.word 0x00 "ETPS,Event Period Select Register"
|
|
rbitfld.word 0x00 14.--15. " SOCBCNT ,ePWM ADC start of conversion B event counter" "No events,1 event,2 events,3 events"
|
|
bitfld.word 0x00 12.--13. " SOCBPRD ,ePWM ADC start of conversion B event period select" "Disabled,1st event,2nd event,3rd event"
|
|
rbitfld.word 0x00 10.--11. " SOCACNT ,ePWM ADC start of conversion A event counter" "No events,1 event,2 events,3 events"
|
|
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bitfld.word 0x00 8.--9. " SOCAPRD ,ePWM ADC start of conversion A event period select" "Disabled,1st event,2nd event,3rd event"
|
|
rbitfld.word 0x00 2.--3. " INTCNT ,ePWM interrupt event counter" "No events,1 event,2 events,3 events"
|
|
bitfld.word 0x00 0.--1. " INTPRD ,ePWM interrupt period select" "Disabled,1st event,2nd event,3rd event"
|
|
group.word 0x3E++0x01
|
|
line.word 0x00 "PCCTL,PWM Chopping Control Register"
|
|
bitfld.word 0x00 8.--10. " CHPDUTY ,Chopping clock duty cycle" "1/8,2/8,3/8,4/8,5/8,6/8,7/8,"
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bitfld.word 0x00 5.--7. " CHPFREQ ,Chopping clock frequency" "/1,/2,/3,/4,/5,/6,/7,/8"
|
|
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bitfld.word 0x00 1.--4. " OSHTWTH ,One-shot pulse width" "1 x VCLK4 / 8,2 x VCLK4 / 8,3 x VCLK4 / 8,4 x VCLK4 / 8,5 x VCLK4 / 8,6 x VCLK4 / 8,7 x VCLK4 / 8,8 x VCLK4 / 8,9 x VCLK4 / 8,10 x VCLK4 / 8,11 x VCLK4 / 8,12 x VCLK4 / 8,13 x VCLK4 / 8,14 x VCLK4 / 8,15 x VCLK4 / 8,16 x VCLK4 / 8"
|
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bitfld.word 0x00 0. " CHPEN ,PWM-chopping enable" "Disabled,Enabled"
|
|
group.word 0x60++0x07
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|
line.word 0x00 "DCACTL,DCA Control Register"
|
|
bitfld.word 0x00 9. " EVT2FRC_SYNCSEL ,DCAEVT2 force synchronization signal select" "Synchronous,Asynchronous"
|
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bitfld.word 0x00 8. " EVT2SRCSEL ,DCAEVT2 source signal select" "DCAEVT2,DCEVTFILT"
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|
bitfld.word 0x00 3. " EVT1SYNCE ,DCAEVT1 SYNC enable" "Disabled,Enabled"
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|
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bitfld.word 0x00 2. " EVT1SOCE ,DCAEVT1 SOC enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 1. " EVT1FRC_SYNCSEL ,DCAEVT1 force synchronization signal select" "Synchronous,Asynchronous"
|
|
bitfld.word 0x00 0. " EVT1SRCSEL ,DCAEVT1 source signal select" "DCAEVT1,DCEVTFILT"
|
|
line.word 0x02 "DCTRIPSEL,Digital Compare Select Register"
|
|
bitfld.word 0x02 12.--15. " DCBLCOMPSEL ,Digital compare B low input select" "/TZ1,/TZ2,/TZ3,?..."
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bitfld.word 0x02 8.--11. " DCBHCOMPSEL ,Digital compare B high input select" "/TZ1,/TZ2,/TZ3,?..."
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|
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bitfld.word 0x02 4.--7. " DCALCOMPSEL ,Digital compare A low input select" "/TZ1,/TZ2,/TZ3,?..."
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bitfld.word 0x02 0.--3. " DCAHCOMPSEL ,Digital compare A high input select" "/TZ1,/TZ2,/TZ3,?..."
|
|
line.word 0x04 "DCFCTL,DC Control Register"
|
|
bitfld.word 0x04 4.--5. " PULSESEL ,Pulse select for blanking and capture alignment" "TBCTR=TBPRD,TBCTR=0,?..."
|
|
bitfld.word 0x04 3. " BLANKINV ,Banking windows inversion" "Not inverted,Inverted"
|
|
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bitfld.word 0x04 2. " BLANKE ,Blanking widow enable" "Disabled,Enabled"
|
|
bitfld.word 0x04 0.--1. " SRCSEL ,Filter block signal source select" "DCAEVT1,DCAEVT2,DCBEVT1,DCBEVT2"
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|
line.word 0x06 "DCBCTL,DCB Control Register"
|
|
bitfld.word 0x06 9. " EVT2FRC_SYNCSEL ,DCBEVT2 force synchronization signal select" "Synchronous,Asynchronous"
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bitfld.word 0x06 8. " EVT2SRCSEL ,DCBEVT2 source signal select" "DCBEVT2,DCEVTFILT"
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|
bitfld.word 0x06 3. " EVT1SYNCE ,DCBEVT1 SYNC enable" "Disabled,Enabled"
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|
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bitfld.word 0x06 2. " EVT1SOCE ,DCBEVT1 SOC enable" "Disabled,Enabled"
|
|
bitfld.word 0x06 1. " EVT1FRC_SYNCSEL ,DCBEVT1 force synchronization signal select" "Synchronous,Asynchronous"
|
|
bitfld.word 0x06 0. " EVT1SRCSEL ,DCBEVT1 source signal select" "DCBEVT1,DCEVTFILT"
|
|
rgroup.word 0x68++0x01
|
|
line.word 0x00 "DCFOFFSET,Blanking Window Offset Register"
|
|
group.word 0x6A++0x01
|
|
line.word 0x00 "DCCAPCTL,DC Capture Control Register"
|
|
bitfld.word 0x00 1. " SHDWMODE ,TBCTR counter capture shadow select mode" "Enable shadow,Active"
|
|
bitfld.word 0x00 0. " CAPE ,TBCTR counter capture enable" "Disabled,Enabled"
|
|
rgroup.word 0x6E++0x05
|
|
line.word 0x00 "DCFOFFSETCNT,Blanking Offset Counter Register"
|
|
line.word 0x02 "DCCAP,Digital Compare Capture Register"
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line.word 0x04 "DCFWINDOWCNT,DC Blanking Window Counter Register"
|
|
hexmask.word.byte 0x04 0.--7. 1. " WINDOWCNT ,Blanking window counter"
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|
endian.le
|
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width 0x0B
|
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tree.end
|
|
tree "EPWM5"
|
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base ad:0xFCF79000
|
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endian.be
|
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width 14.
|
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group.word 0x00++0x05
|
|
line.word 0x00 "TBSTS,Time-Base Status Register"
|
|
eventfld.word 0x00 2. " CTRMAX ,Time-base counter max latched status" "Not reached,Reached"
|
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eventfld.word 0x00 1. " SYNCI ,Input synchronization latched status" "Not occurred,Occurred"
|
|
rbitfld.word 0x00 0. " CTRDIR ,Time-base counter direction status" "Counting down,Counting up"
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line.word 0x02 "TBCTL,Time-Base Control Register"
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bitfld.word 0x02 14.--15. " FREE_SOFT ,Emulation mode" "Stop after INC/DEC,Stop after cycle,Free run,Free run"
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bitfld.word 0x02 13. " PHSDIR ,Phase direction" "Count down,Count up"
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bitfld.word 0x02 10.--12. " CLKDIV ,Time-base clock prescale" "/1,/2,/4,/8,/16,/32,/64,/128"
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|
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bitfld.word 0x02 7.--9. " HSPCLKDIV ,High speed time-base clock prescale" "/1,/2,/4,/6,/8,/10,/12,/14"
|
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eventfld.word 0x02 6. " SWFSYNC ,Software forced synchronization pulse" "No effect,Forced"
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bitfld.word 0x02 4.--5. " SYNCOSEL ,Synchronization output select" "EPWMxSYNC,CTR=zero,CTR=CMPB,Disabled"
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bitfld.word 0x02 3. " PRDLD ,Active period register load from shadow register usage" "Used,Not used"
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|
bitfld.word 0x02 2. " PHSEN ,Counter register load from phase register enable" "Disabled,Enabled"
|
|
bitfld.word 0x02 0.--1. " CTRMODE ,Counter mode" "Up-count,Down-count,Up-down-count,Stop-freeze cnt"
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line.word 0x04 "TBPHS,Time-Base Counter Phase Register"
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group.word 0x08++0x05
|
|
line.word 0x00 "TBPRD,Time-Base Period Register"
|
|
line.word 0x02 "TBCTR,Time-Base Counter Register"
|
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line.word 0x04 "CMPCTL,Counter-Compare Control Register"
|
|
rbitfld.word 0x04 9. " SHDWBFULL ,Counter-compare B shadow register full status flag" "Not full,Full"
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|
rbitfld.word 0x04 8. " SHDWAFULL ,Counter-compare A shadow register full status flag" "Not full,Full"
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|
bitfld.word 0x04 6. " SHDWBMODE ,Counter-compare B register operating mode" "Shadow,Immediate"
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|
newline
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bitfld.word 0x04 4. " SHDWAMODE ,Counter-compare A register operating mode" "Shadow,Immediate"
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|
bitfld.word 0x04 2.--3. " LOADBMODE ,Active counter-compare B load from shadow select mode" "CTR=Zero,CTR=PRD,Both,Freeze"
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bitfld.word 0x04 0.--1. " LOADBMODE ,Active counter-compare B load from shadow select mode" "CTR=Zero,CTR=PRD,Both,Freeze"
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group.word 0x10++0x01
|
|
line.word 0x00 "CMPA,Compare A Register"
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group.word 0x14++0x17
|
|
line.word 0x00 "AQCTLA,AQCTLA Register"
|
|
bitfld.word 0x00 10.--11. " CBD ,Action when the time-base counter = CMPB register and the counter is decrementing" "Disabled,Clear,Set,Toggle output"
|
|
bitfld.word 0x00 8.--9. " CBU ,Action when the time-base counter = CMPB register and the counter is incrementing" "Disabled,Clear,Set,Toggle output"
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bitfld.word 0x00 6.--7. " CAD ,Action when the time-base counter = CMPA register and the counter is decrementing" "Disabled,Clear,Set,Toggle output"
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|
newline
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bitfld.word 0x00 4.--5. " CAU ,Action when the time-base counter = CMPA register and the counter is incrementing" "Disabled,Clear,Set,Toggle output"
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bitfld.word 0x00 2.--3. " PRD ,Action when the counter = the period" "Disabled,Clear,Set,Toggle output"
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bitfld.word 0x00 0.--1. " ZRO ,Action when the counter = zero" "Disabled,Clear,Set,Toggle output"
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line.word 0x02 "CMPB,Compare B Register"
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line.word 0x04 "AQSFRC,AQSFRC Register"
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bitfld.word 0x04 6.--7. " RLDCSF ,AQCSFRC active register reload from shadow options" "CNT=0,CNT=period,CNT=0 or CNT=period,Load immediately"
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eventfld.word 0x04 5. " OTSFB ,One-time software forced event on output B" "No effect,Forced"
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bitfld.word 0x04 3.--4. " ACTSFB ,Action when one-time software force B is invoked" "Disabled,Clear,Set,Toggle"
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|
newline
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eventfld.word 0x04 2. " OTSFA ,One-time software forced event on output A" "No effect,Forced"
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|
bitfld.word 0x04 0.--1. " ACTSFA ,Action when one-time software force A is invoked" "Disabled,Clear,Set,Toggle"
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line.word 0x06 "AQCTLA,AQCTLA Register"
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bitfld.word 0x06 10.--11. " CBD ,Action when the time-base counter = CMPB register and the counter is decrementing" "Disabled,Clear,Set,Toggle output"
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bitfld.word 0x06 8.--9. " CBU ,Action when the time-base counter = CMPB register and the counter is incrementing" "Disabled,Clear,Set,Toggle output"
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bitfld.word 0x06 6.--7. " CAD ,Action when the time-base counter = CMPA register and the counter is decrementing" "Disabled,Clear,Set,Toggle output"
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|
newline
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bitfld.word 0x06 4.--5. " CAU ,Action when the time-base counter = CMPA register and the counter is incrementing" "Disabled,Clear,Set,Toggle output"
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bitfld.word 0x06 2.--3. " PRD ,Action when the counter = the period" "Disabled,Clear,Set,Toggle output"
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bitfld.word 0x06 0.--1. " ZRO ,Action when the counter = zero" "Disabled,Clear,Set,Toggle output"
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line.word 0x08 "DBCTL,Dead-Band Control Register"
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bitfld.word 0x08 15. " HALFCYCLE ,Half cycle clocking enable" "Disabled,Enabled"
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bitfld.word 0x08 4.--5. " IN_MODE ,Dead band input mode control (A In for edge / B In for edge)" "Both / -,Falling / Rising,Rising / Falling,- / Both"
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newline
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bitfld.word 0x08 2.--3. " POLSEL ,Active polarity select control" "High,Low complementary,High complementary,Low"
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bitfld.word 0x08 0.--1. " OUT_MODE ,Dead band output mode control" "Bypass,Rising disabled,Falling disabled,- / Both"
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line.word 0x0A "AQCSFRC,AQCSFRC register"
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bitfld.word 0x0A 2.--3. " CSFB ,Continuous software force on output B" "Disabled,Forced low,Forced high,Disabled"
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bitfld.word 0x0A 0.--1. " CSFA ,Continuous software force on output A" "Disabled,Forced low,Forced high,Disabled"
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line.word 0x0C "DBFED,Falling Edge Delay Register"
|
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hexmask.word 0x0C 0.--9. 1. " DEL ,Falling edge delay count"
|
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line.word 0x0E "DBRED,Rising Edge Delay Register"
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hexmask.word 0x0E 0.--9. 1. " DEL ,Rising edge delay count"
|
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line.word 0x10 "TZDCSEL,Digital Compare Select Register"
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bitfld.word 0x10 9.--11. " DCBEVT2 ,Digital compare output B event 2 selection (DCBL / DCBH)" "Event,Don't care / Low,Don't care / High,Low / Don't care,High / Don't care,High / Low,?..."
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bitfld.word 0x10 6.--8. " DCBEVT1 ,Digital compare output B event 1 selection (DCBL / DCBH)" "Event,Don't care / Low,Don't care / High,Low / Don't care,High / Don't care,High / Low,?..."
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newline
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bitfld.word 0x10 3.--5. " DCAEVT2 ,Digital compare output A event 2 selection (DCAL / DCAH)" "Event,Don't care / Low,Don't care / High,Low / Don't care,High / Don't care,High / Low,?..."
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bitfld.word 0x10 0.--2. " DCAEVT1 ,Digital compare output A event 1 selection (DCAL / DCAH)" "Event,Don't care / Low,Don't care / High,Low / Don't care,High / Don't care,High / Low,?..."
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line.word 0x12 "TZSEL,Trip-Zone Select Register"
|
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rbitfld.word 0x12 15. " DCBEVT1 ,Digital compare output B event 1 enable" "Disabled,Enabled"
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rbitfld.word 0x12 14. " DCAEVT1 ,Digital compare output A event 1 enable" "Disabled,Enabled"
|
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bitfld.word 0x12 13. " OSHT6 ,Trip-zone 6 (/TZ6) as one-shot trip enable" "Disabled,Enabled"
|
|
newline
|
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bitfld.word 0x12 12. " OSHT5 ,Trip-zone 5 (/TZ5) as one-shot trip enable" "Disabled,Enabled"
|
|
bitfld.word 0x12 11. " OSHT4 ,Trip-zone 4 (/TZ4) as one-shot trip enable" "Disabled,Enabled"
|
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bitfld.word 0x12 10. " OSHT3 ,Trip-zone 3 (/TZ3) as one-shot trip enable" "Disabled,Enabled"
|
|
newline
|
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bitfld.word 0x12 9. " OSHT2 ,Trip-zone 2 (/TZ2) as one-shot trip enable" "Disabled,Enabled"
|
|
bitfld.word 0x12 8. " OSHT1 ,Trip-zone 1 (/TZ1) as one-shot trip enable" "Disabled,Enabled"
|
|
rbitfld.word 0x12 7. " DCBEVT2 ,Digital compare output B event 2 enable" "Disabled,Enabled"
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|
newline
|
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rbitfld.word 0x12 6. " DCAEVT2 ,Digital compare output A event 2 enable" "Disabled,Enabled"
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bitfld.word 0x12 5. " CBC6 ,Trip-zone 6 (/TZ6) as CBC enable" "Disabled,Enabled"
|
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bitfld.word 0x12 4. " CBC5 ,Trip-zone 5 (/TZ5) as CBC enable" "Disabled,Enabled"
|
|
newline
|
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bitfld.word 0x12 3. " CBC4 ,Trip-zone 4 (/TZ4) as CBC enable" "Disabled,Enabled"
|
|
bitfld.word 0x12 2. " CBC3 ,Trip-zone 3 (/TZ3) as CBC enable" "Disabled,Enabled"
|
|
newline
|
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bitfld.word 0x12 1. " CBC2 ,Trip-zone 2 (/TZ2) as CBC enable" "Disabled,Enabled"
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|
bitfld.word 0x12 0. " CBC1 ,Trip-zone 1 (/TZ1) as CBC enable" "Disabled,Enabled"
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line.word 0x14 "TZEINT,Trip-Zone Interrupt Register"
|
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bitfld.word 0x14 6. " DCBEVT2 ,Digital comparator output B event 2 interrupt enable" "Disabled,Enabled"
|
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bitfld.word 0x14 5. " DCBEVT1 ,Digital comparator output B event 1 interrupt enable" "Disabled,Enabled"
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bitfld.word 0x14 4. " DCAEVT2 ,Digital comparator output A event 2 interrupt enable" "Disabled,Enabled"
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|
newline
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bitfld.word 0x14 3. " DCAEVT1 ,Digital comparator output A event 1 interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x14 2. " OST ,Trip-zone one-shot interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x14 1. " CBC ,Trip-zone cycle-by-cycle interrupt enable" "Disabled,Enabled"
|
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line.word 0x16 "TZCTL,Trip-Zone Control Register"
|
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bitfld.word 0x16 10.--11. " DCBEVT2 ,Digital compare output B event 2 action on EPWMxB" "High-impedance,Forced high,Forced low,Disabled"
|
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bitfld.word 0x16 8.--9. " DCBEVT1 ,Digital compare output B event 1 action on EPWMxB" "High-impedance,Forced high,Forced low,Disabled"
|
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bitfld.word 0x16 6.--7. " DCAEVT2 ,Digital compare output A event 2 action on EPWMxA" "High-impedance,Forced high,Forced low,Disabled"
|
|
newline
|
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bitfld.word 0x16 4.--5. " DCAEVT1 ,Digital compare output A event 1 action on EPWMxA" "High-impedance,Forced high,Forced low,Disabled"
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bitfld.word 0x16 2.--3. " TZB ,Action on trip-zone event for EPWMxB select" "High-impedance,Forced high,Forced low,Disabled"
|
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bitfld.word 0x16 0.--1. " TZA ,Action on trip-zone event for EPWMxA select" "High-impedance,Forced high,Forced low,Disabled"
|
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wgroup.word 0x2C++0x01
|
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line.word 0x00 "TZCLR,Trip-Zone Clear Register"
|
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bitfld.word 0x00 6. " DCBEVT2 ,Clear flag for digital compare output B event 2" "No effect,Clear"
|
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bitfld.word 0x00 5. " DCBEVT1 ,Clear flag for digital compare output B event 1" "No effect,Clear"
|
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bitfld.word 0x00 4. " DCAEVT2 ,Clear flag for digital compare output A event 2" "No effect,Clear"
|
|
newline
|
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bitfld.word 0x00 3. " DCAEVT1 ,Clear flag for digital compare output A event 1" "No effect,Clear"
|
|
bitfld.word 0x00 2. " OST ,Clear flag for one-shot trip latch" "No effect,Clear"
|
|
newline
|
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bitfld.word 0x00 1. " CBC ,Clear flag for cycle-by-cycle trip latch" "No effect,Clear"
|
|
bitfld.word 0x00 0. " INT ,Global interrupt clear flag" "No effect,Clear"
|
|
rgroup.word 0x2E++0x01
|
|
line.word 0x00 "TZFLG,Trip-Zone Flag Register"
|
|
bitfld.word 0x00 6. " DCBEVT2 ,Latched status flag for digital compare output B event 2" "No interrupt,Interrupt"
|
|
bitfld.word 0x00 5. " DCBEVT1 ,Latched status flag for digital compare output B event 1" "No interrupt,Interrupt"
|
|
bitfld.word 0x00 4. " DCAEVT2 ,Latched status flag for digital compare output A event 2" "No interrupt,Interrupt"
|
|
newline
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bitfld.word 0x00 3. " DCAEVT1 ,Latched status flag for digital compare output A event 1" "No interrupt,Interrupt"
|
|
bitfld.word 0x00 2. " OST ,Latched status flag for one-shot trip latch" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.word 0x00 1. " CBC ,Latched status flag for cycle-by-cycle trip latch" "No interrupt,Interrupt"
|
|
bitfld.word 0x00 0. " INT ,Global interrupt latched status flag" "No interrupt,Interrupt"
|
|
group.word 0x30++0x03
|
|
line.word 0x00 "ETSEL,Event Select Register"
|
|
bitfld.word 0x00 15. " SOCBEN ,Enable the ADC start of conversion B pulse" "Disabled,Enabled"
|
|
bitfld.word 0x00 12.--14. " SOCBSEL ,Start of conversion B option select" "DCBEVT1,TBCTR=0,TBCTR=TBPRD,TBCTR=0 or TBCTR=TBPRD,TBCTR=CMPA for INC,TBCTR=CMPA for DEC,TBCTR=CMPB for INC,TBCTR=CMPB for DEC"
|
|
bitfld.word 0x00 11. " SOCAEN ,Enable the ADC start of conversion A pulse" "Disabled,Enabled"
|
|
newline
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bitfld.word 0x00 8.--10. " SOCASEL ,Start of conversion A option select" "DCAEVT1,TBCTR=0,TBCTR=TBPRD,TBCTR=0 or TBCTR=TBPRD,TBCTR=CMPA for INC,TBCTR=CMPA for DEC,TBCTR=CMPB for INC,TBCTR=CMPB for DEC"
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bitfld.word 0x00 3. " INTEN ,Enable ePWM interrupt generation" "Disabled,Enabled"
|
|
bitfld.word 0x00 0.--2. " INTSEL ,EPWM interrupt option select" ",TBCTR=0,TBCTR=TBPRD,TBCTR=0 or TBCTR=TBPRD,TBCTR=CMPA for INC,TBCTR=CMPA for DEC,TBCTR=CMPB for INC,TBCTR=CMPB for DEC"
|
|
line.word 0x02 "TZFLG,Trip-Zone Flag Register"
|
|
bitfld.word 0x02 6. " DCBEVT2 ,Force flag for digital compare output B event 2" "No interrupt,Interrupt"
|
|
bitfld.word 0x02 5. " DCBEVT1 ,Force flag for digital compare output B event 1" "No interrupt,Interrupt"
|
|
bitfld.word 0x02 4. " DCAEVT2 ,Force flag for digital compare output A event 2" "No interrupt,Interrupt"
|
|
newline
|
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bitfld.word 0x02 3. " DCAEVT1 ,Force flag for digital compare output A event 1" "No interrupt,Interrupt"
|
|
bitfld.word 0x02 2. " OST ,Force flag for one-shot trip latch" "No interrupt,Interrupt"
|
|
bitfld.word 0x02 1. " CBC ,Force flag for cycle-by-cycle trip latch" "No interrupt,Interrupt"
|
|
group.word 0x34++0x01
|
|
line.word 0x00 "ET_SETCLR,Event Set/Clear Register"
|
|
setclrfld.word 0x00 3. 0x04 3. 0x06 3. " SOCB ,Latched ePWM ADC start of conversation B status flag" "No interrupt,Interrupt"
|
|
setclrfld.word 0x00 2. 0x04 2. 0x06 2. " SOCA ,Latched ePWM ADC start of conversation A status flag" "No interrupt,Interrupt"
|
|
setclrfld.word 0x00 0. 0x04 0. 0x06 0. " INT ,Latched ePWM interrupt status flag" "No interrupt,Interrupt"
|
|
group.word 0x36++0x01
|
|
line.word 0x00 "ETPS,Event Period Select Register"
|
|
rbitfld.word 0x00 14.--15. " SOCBCNT ,ePWM ADC start of conversion B event counter" "No events,1 event,2 events,3 events"
|
|
bitfld.word 0x00 12.--13. " SOCBPRD ,ePWM ADC start of conversion B event period select" "Disabled,1st event,2nd event,3rd event"
|
|
rbitfld.word 0x00 10.--11. " SOCACNT ,ePWM ADC start of conversion A event counter" "No events,1 event,2 events,3 events"
|
|
newline
|
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bitfld.word 0x00 8.--9. " SOCAPRD ,ePWM ADC start of conversion A event period select" "Disabled,1st event,2nd event,3rd event"
|
|
rbitfld.word 0x00 2.--3. " INTCNT ,ePWM interrupt event counter" "No events,1 event,2 events,3 events"
|
|
bitfld.word 0x00 0.--1. " INTPRD ,ePWM interrupt period select" "Disabled,1st event,2nd event,3rd event"
|
|
group.word 0x3E++0x01
|
|
line.word 0x00 "PCCTL,PWM Chopping Control Register"
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|
bitfld.word 0x00 8.--10. " CHPDUTY ,Chopping clock duty cycle" "1/8,2/8,3/8,4/8,5/8,6/8,7/8,"
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|
bitfld.word 0x00 5.--7. " CHPFREQ ,Chopping clock frequency" "/1,/2,/3,/4,/5,/6,/7,/8"
|
|
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bitfld.word 0x00 1.--4. " OSHTWTH ,One-shot pulse width" "1 x VCLK4 / 8,2 x VCLK4 / 8,3 x VCLK4 / 8,4 x VCLK4 / 8,5 x VCLK4 / 8,6 x VCLK4 / 8,7 x VCLK4 / 8,8 x VCLK4 / 8,9 x VCLK4 / 8,10 x VCLK4 / 8,11 x VCLK4 / 8,12 x VCLK4 / 8,13 x VCLK4 / 8,14 x VCLK4 / 8,15 x VCLK4 / 8,16 x VCLK4 / 8"
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bitfld.word 0x00 0. " CHPEN ,PWM-chopping enable" "Disabled,Enabled"
|
|
group.word 0x60++0x07
|
|
line.word 0x00 "DCACTL,DCA Control Register"
|
|
bitfld.word 0x00 9. " EVT2FRC_SYNCSEL ,DCAEVT2 force synchronization signal select" "Synchronous,Asynchronous"
|
|
bitfld.word 0x00 8. " EVT2SRCSEL ,DCAEVT2 source signal select" "DCAEVT2,DCEVTFILT"
|
|
bitfld.word 0x00 3. " EVT1SYNCE ,DCAEVT1 SYNC enable" "Disabled,Enabled"
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|
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bitfld.word 0x00 2. " EVT1SOCE ,DCAEVT1 SOC enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 1. " EVT1FRC_SYNCSEL ,DCAEVT1 force synchronization signal select" "Synchronous,Asynchronous"
|
|
bitfld.word 0x00 0. " EVT1SRCSEL ,DCAEVT1 source signal select" "DCAEVT1,DCEVTFILT"
|
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line.word 0x02 "DCTRIPSEL,Digital Compare Select Register"
|
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bitfld.word 0x02 12.--15. " DCBLCOMPSEL ,Digital compare B low input select" "/TZ1,/TZ2,/TZ3,?..."
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bitfld.word 0x02 8.--11. " DCBHCOMPSEL ,Digital compare B high input select" "/TZ1,/TZ2,/TZ3,?..."
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|
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bitfld.word 0x02 4.--7. " DCALCOMPSEL ,Digital compare A low input select" "/TZ1,/TZ2,/TZ3,?..."
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bitfld.word 0x02 0.--3. " DCAHCOMPSEL ,Digital compare A high input select" "/TZ1,/TZ2,/TZ3,?..."
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line.word 0x04 "DCFCTL,DC Control Register"
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|
bitfld.word 0x04 4.--5. " PULSESEL ,Pulse select for blanking and capture alignment" "TBCTR=TBPRD,TBCTR=0,?..."
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|
bitfld.word 0x04 3. " BLANKINV ,Banking windows inversion" "Not inverted,Inverted"
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|
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bitfld.word 0x04 2. " BLANKE ,Blanking widow enable" "Disabled,Enabled"
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|
bitfld.word 0x04 0.--1. " SRCSEL ,Filter block signal source select" "DCAEVT1,DCAEVT2,DCBEVT1,DCBEVT2"
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line.word 0x06 "DCBCTL,DCB Control Register"
|
|
bitfld.word 0x06 9. " EVT2FRC_SYNCSEL ,DCBEVT2 force synchronization signal select" "Synchronous,Asynchronous"
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bitfld.word 0x06 8. " EVT2SRCSEL ,DCBEVT2 source signal select" "DCBEVT2,DCEVTFILT"
|
|
bitfld.word 0x06 3. " EVT1SYNCE ,DCBEVT1 SYNC enable" "Disabled,Enabled"
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|
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bitfld.word 0x06 2. " EVT1SOCE ,DCBEVT1 SOC enable" "Disabled,Enabled"
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|
bitfld.word 0x06 1. " EVT1FRC_SYNCSEL ,DCBEVT1 force synchronization signal select" "Synchronous,Asynchronous"
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|
bitfld.word 0x06 0. " EVT1SRCSEL ,DCBEVT1 source signal select" "DCBEVT1,DCEVTFILT"
|
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rgroup.word 0x68++0x01
|
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line.word 0x00 "DCFOFFSET,Blanking Window Offset Register"
|
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group.word 0x6A++0x01
|
|
line.word 0x00 "DCCAPCTL,DC Capture Control Register"
|
|
bitfld.word 0x00 1. " SHDWMODE ,TBCTR counter capture shadow select mode" "Enable shadow,Active"
|
|
bitfld.word 0x00 0. " CAPE ,TBCTR counter capture enable" "Disabled,Enabled"
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|
rgroup.word 0x6E++0x05
|
|
line.word 0x00 "DCFOFFSETCNT,Blanking Offset Counter Register"
|
|
line.word 0x02 "DCCAP,Digital Compare Capture Register"
|
|
line.word 0x04 "DCFWINDOWCNT,DC Blanking Window Counter Register"
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hexmask.word.byte 0x04 0.--7. 1. " WINDOWCNT ,Blanking window counter"
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endian.le
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width 0x0B
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tree.end
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tree "EPWM6"
|
|
base ad:0xFCF79100
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endian.be
|
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width 14.
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group.word 0x00++0x05
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line.word 0x00 "TBSTS,Time-Base Status Register"
|
|
eventfld.word 0x00 2. " CTRMAX ,Time-base counter max latched status" "Not reached,Reached"
|
|
eventfld.word 0x00 1. " SYNCI ,Input synchronization latched status" "Not occurred,Occurred"
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|
rbitfld.word 0x00 0. " CTRDIR ,Time-base counter direction status" "Counting down,Counting up"
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line.word 0x02 "TBCTL,Time-Base Control Register"
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bitfld.word 0x02 14.--15. " FREE_SOFT ,Emulation mode" "Stop after INC/DEC,Stop after cycle,Free run,Free run"
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bitfld.word 0x02 13. " PHSDIR ,Phase direction" "Count down,Count up"
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bitfld.word 0x02 10.--12. " CLKDIV ,Time-base clock prescale" "/1,/2,/4,/8,/16,/32,/64,/128"
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bitfld.word 0x02 7.--9. " HSPCLKDIV ,High speed time-base clock prescale" "/1,/2,/4,/6,/8,/10,/12,/14"
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eventfld.word 0x02 6. " SWFSYNC ,Software forced synchronization pulse" "No effect,Forced"
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bitfld.word 0x02 4.--5. " SYNCOSEL ,Synchronization output select" "EPWMxSYNC,CTR=zero,CTR=CMPB,Disabled"
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bitfld.word 0x02 3. " PRDLD ,Active period register load from shadow register usage" "Used,Not used"
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|
bitfld.word 0x02 2. " PHSEN ,Counter register load from phase register enable" "Disabled,Enabled"
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|
bitfld.word 0x02 0.--1. " CTRMODE ,Counter mode" "Up-count,Down-count,Up-down-count,Stop-freeze cnt"
|
|
line.word 0x04 "TBPHS,Time-Base Counter Phase Register"
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group.word 0x08++0x05
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line.word 0x00 "TBPRD,Time-Base Period Register"
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line.word 0x02 "TBCTR,Time-Base Counter Register"
|
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line.word 0x04 "CMPCTL,Counter-Compare Control Register"
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rbitfld.word 0x04 9. " SHDWBFULL ,Counter-compare B shadow register full status flag" "Not full,Full"
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rbitfld.word 0x04 8. " SHDWAFULL ,Counter-compare A shadow register full status flag" "Not full,Full"
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bitfld.word 0x04 6. " SHDWBMODE ,Counter-compare B register operating mode" "Shadow,Immediate"
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bitfld.word 0x04 4. " SHDWAMODE ,Counter-compare A register operating mode" "Shadow,Immediate"
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bitfld.word 0x04 2.--3. " LOADBMODE ,Active counter-compare B load from shadow select mode" "CTR=Zero,CTR=PRD,Both,Freeze"
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|
bitfld.word 0x04 0.--1. " LOADBMODE ,Active counter-compare B load from shadow select mode" "CTR=Zero,CTR=PRD,Both,Freeze"
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group.word 0x10++0x01
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line.word 0x00 "CMPA,Compare A Register"
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group.word 0x14++0x17
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line.word 0x00 "AQCTLA,AQCTLA Register"
|
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bitfld.word 0x00 10.--11. " CBD ,Action when the time-base counter = CMPB register and the counter is decrementing" "Disabled,Clear,Set,Toggle output"
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bitfld.word 0x00 8.--9. " CBU ,Action when the time-base counter = CMPB register and the counter is incrementing" "Disabled,Clear,Set,Toggle output"
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bitfld.word 0x00 6.--7. " CAD ,Action when the time-base counter = CMPA register and the counter is decrementing" "Disabled,Clear,Set,Toggle output"
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newline
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bitfld.word 0x00 4.--5. " CAU ,Action when the time-base counter = CMPA register and the counter is incrementing" "Disabled,Clear,Set,Toggle output"
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bitfld.word 0x00 2.--3. " PRD ,Action when the counter = the period" "Disabled,Clear,Set,Toggle output"
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bitfld.word 0x00 0.--1. " ZRO ,Action when the counter = zero" "Disabled,Clear,Set,Toggle output"
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line.word 0x02 "CMPB,Compare B Register"
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line.word 0x04 "AQSFRC,AQSFRC Register"
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bitfld.word 0x04 6.--7. " RLDCSF ,AQCSFRC active register reload from shadow options" "CNT=0,CNT=period,CNT=0 or CNT=period,Load immediately"
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eventfld.word 0x04 5. " OTSFB ,One-time software forced event on output B" "No effect,Forced"
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bitfld.word 0x04 3.--4. " ACTSFB ,Action when one-time software force B is invoked" "Disabled,Clear,Set,Toggle"
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|
newline
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eventfld.word 0x04 2. " OTSFA ,One-time software forced event on output A" "No effect,Forced"
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bitfld.word 0x04 0.--1. " ACTSFA ,Action when one-time software force A is invoked" "Disabled,Clear,Set,Toggle"
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line.word 0x06 "AQCTLA,AQCTLA Register"
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bitfld.word 0x06 10.--11. " CBD ,Action when the time-base counter = CMPB register and the counter is decrementing" "Disabled,Clear,Set,Toggle output"
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bitfld.word 0x06 8.--9. " CBU ,Action when the time-base counter = CMPB register and the counter is incrementing" "Disabled,Clear,Set,Toggle output"
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bitfld.word 0x06 6.--7. " CAD ,Action when the time-base counter = CMPA register and the counter is decrementing" "Disabled,Clear,Set,Toggle output"
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newline
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bitfld.word 0x06 4.--5. " CAU ,Action when the time-base counter = CMPA register and the counter is incrementing" "Disabled,Clear,Set,Toggle output"
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bitfld.word 0x06 2.--3. " PRD ,Action when the counter = the period" "Disabled,Clear,Set,Toggle output"
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bitfld.word 0x06 0.--1. " ZRO ,Action when the counter = zero" "Disabled,Clear,Set,Toggle output"
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line.word 0x08 "DBCTL,Dead-Band Control Register"
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bitfld.word 0x08 15. " HALFCYCLE ,Half cycle clocking enable" "Disabled,Enabled"
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bitfld.word 0x08 4.--5. " IN_MODE ,Dead band input mode control (A In for edge / B In for edge)" "Both / -,Falling / Rising,Rising / Falling,- / Both"
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newline
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bitfld.word 0x08 2.--3. " POLSEL ,Active polarity select control" "High,Low complementary,High complementary,Low"
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bitfld.word 0x08 0.--1. " OUT_MODE ,Dead band output mode control" "Bypass,Rising disabled,Falling disabled,- / Both"
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line.word 0x0A "AQCSFRC,AQCSFRC register"
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bitfld.word 0x0A 2.--3. " CSFB ,Continuous software force on output B" "Disabled,Forced low,Forced high,Disabled"
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bitfld.word 0x0A 0.--1. " CSFA ,Continuous software force on output A" "Disabled,Forced low,Forced high,Disabled"
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line.word 0x0C "DBFED,Falling Edge Delay Register"
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hexmask.word 0x0C 0.--9. 1. " DEL ,Falling edge delay count"
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line.word 0x0E "DBRED,Rising Edge Delay Register"
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hexmask.word 0x0E 0.--9. 1. " DEL ,Rising edge delay count"
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line.word 0x10 "TZDCSEL,Digital Compare Select Register"
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bitfld.word 0x10 9.--11. " DCBEVT2 ,Digital compare output B event 2 selection (DCBL / DCBH)" "Event,Don't care / Low,Don't care / High,Low / Don't care,High / Don't care,High / Low,?..."
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bitfld.word 0x10 6.--8. " DCBEVT1 ,Digital compare output B event 1 selection (DCBL / DCBH)" "Event,Don't care / Low,Don't care / High,Low / Don't care,High / Don't care,High / Low,?..."
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newline
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bitfld.word 0x10 3.--5. " DCAEVT2 ,Digital compare output A event 2 selection (DCAL / DCAH)" "Event,Don't care / Low,Don't care / High,Low / Don't care,High / Don't care,High / Low,?..."
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bitfld.word 0x10 0.--2. " DCAEVT1 ,Digital compare output A event 1 selection (DCAL / DCAH)" "Event,Don't care / Low,Don't care / High,Low / Don't care,High / Don't care,High / Low,?..."
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line.word 0x12 "TZSEL,Trip-Zone Select Register"
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rbitfld.word 0x12 15. " DCBEVT1 ,Digital compare output B event 1 enable" "Disabled,Enabled"
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rbitfld.word 0x12 14. " DCAEVT1 ,Digital compare output A event 1 enable" "Disabled,Enabled"
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bitfld.word 0x12 13. " OSHT6 ,Trip-zone 6 (/TZ6) as one-shot trip enable" "Disabled,Enabled"
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newline
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bitfld.word 0x12 12. " OSHT5 ,Trip-zone 5 (/TZ5) as one-shot trip enable" "Disabled,Enabled"
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bitfld.word 0x12 11. " OSHT4 ,Trip-zone 4 (/TZ4) as one-shot trip enable" "Disabled,Enabled"
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bitfld.word 0x12 10. " OSHT3 ,Trip-zone 3 (/TZ3) as one-shot trip enable" "Disabled,Enabled"
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newline
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bitfld.word 0x12 9. " OSHT2 ,Trip-zone 2 (/TZ2) as one-shot trip enable" "Disabled,Enabled"
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bitfld.word 0x12 8. " OSHT1 ,Trip-zone 1 (/TZ1) as one-shot trip enable" "Disabled,Enabled"
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rbitfld.word 0x12 7. " DCBEVT2 ,Digital compare output B event 2 enable" "Disabled,Enabled"
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newline
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rbitfld.word 0x12 6. " DCAEVT2 ,Digital compare output A event 2 enable" "Disabled,Enabled"
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bitfld.word 0x12 5. " CBC6 ,Trip-zone 6 (/TZ6) as CBC enable" "Disabled,Enabled"
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bitfld.word 0x12 4. " CBC5 ,Trip-zone 5 (/TZ5) as CBC enable" "Disabled,Enabled"
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newline
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bitfld.word 0x12 3. " CBC4 ,Trip-zone 4 (/TZ4) as CBC enable" "Disabled,Enabled"
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bitfld.word 0x12 2. " CBC3 ,Trip-zone 3 (/TZ3) as CBC enable" "Disabled,Enabled"
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newline
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bitfld.word 0x12 1. " CBC2 ,Trip-zone 2 (/TZ2) as CBC enable" "Disabled,Enabled"
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bitfld.word 0x12 0. " CBC1 ,Trip-zone 1 (/TZ1) as CBC enable" "Disabled,Enabled"
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line.word 0x14 "TZEINT,Trip-Zone Interrupt Register"
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bitfld.word 0x14 6. " DCBEVT2 ,Digital comparator output B event 2 interrupt enable" "Disabled,Enabled"
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bitfld.word 0x14 5. " DCBEVT1 ,Digital comparator output B event 1 interrupt enable" "Disabled,Enabled"
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bitfld.word 0x14 4. " DCAEVT2 ,Digital comparator output A event 2 interrupt enable" "Disabled,Enabled"
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newline
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bitfld.word 0x14 3. " DCAEVT1 ,Digital comparator output A event 1 interrupt enable" "Disabled,Enabled"
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bitfld.word 0x14 2. " OST ,Trip-zone one-shot interrupt enable" "Disabled,Enabled"
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bitfld.word 0x14 1. " CBC ,Trip-zone cycle-by-cycle interrupt enable" "Disabled,Enabled"
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line.word 0x16 "TZCTL,Trip-Zone Control Register"
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bitfld.word 0x16 10.--11. " DCBEVT2 ,Digital compare output B event 2 action on EPWMxB" "High-impedance,Forced high,Forced low,Disabled"
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bitfld.word 0x16 8.--9. " DCBEVT1 ,Digital compare output B event 1 action on EPWMxB" "High-impedance,Forced high,Forced low,Disabled"
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bitfld.word 0x16 6.--7. " DCAEVT2 ,Digital compare output A event 2 action on EPWMxA" "High-impedance,Forced high,Forced low,Disabled"
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newline
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bitfld.word 0x16 4.--5. " DCAEVT1 ,Digital compare output A event 1 action on EPWMxA" "High-impedance,Forced high,Forced low,Disabled"
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bitfld.word 0x16 2.--3. " TZB ,Action on trip-zone event for EPWMxB select" "High-impedance,Forced high,Forced low,Disabled"
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bitfld.word 0x16 0.--1. " TZA ,Action on trip-zone event for EPWMxA select" "High-impedance,Forced high,Forced low,Disabled"
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wgroup.word 0x2C++0x01
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line.word 0x00 "TZCLR,Trip-Zone Clear Register"
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bitfld.word 0x00 6. " DCBEVT2 ,Clear flag for digital compare output B event 2" "No effect,Clear"
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bitfld.word 0x00 5. " DCBEVT1 ,Clear flag for digital compare output B event 1" "No effect,Clear"
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bitfld.word 0x00 4. " DCAEVT2 ,Clear flag for digital compare output A event 2" "No effect,Clear"
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newline
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bitfld.word 0x00 3. " DCAEVT1 ,Clear flag for digital compare output A event 1" "No effect,Clear"
|
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bitfld.word 0x00 2. " OST ,Clear flag for one-shot trip latch" "No effect,Clear"
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newline
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bitfld.word 0x00 1. " CBC ,Clear flag for cycle-by-cycle trip latch" "No effect,Clear"
|
|
bitfld.word 0x00 0. " INT ,Global interrupt clear flag" "No effect,Clear"
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rgroup.word 0x2E++0x01
|
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line.word 0x00 "TZFLG,Trip-Zone Flag Register"
|
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bitfld.word 0x00 6. " DCBEVT2 ,Latched status flag for digital compare output B event 2" "No interrupt,Interrupt"
|
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bitfld.word 0x00 5. " DCBEVT1 ,Latched status flag for digital compare output B event 1" "No interrupt,Interrupt"
|
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bitfld.word 0x00 4. " DCAEVT2 ,Latched status flag for digital compare output A event 2" "No interrupt,Interrupt"
|
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newline
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bitfld.word 0x00 3. " DCAEVT1 ,Latched status flag for digital compare output A event 1" "No interrupt,Interrupt"
|
|
bitfld.word 0x00 2. " OST ,Latched status flag for one-shot trip latch" "No interrupt,Interrupt"
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|
newline
|
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bitfld.word 0x00 1. " CBC ,Latched status flag for cycle-by-cycle trip latch" "No interrupt,Interrupt"
|
|
bitfld.word 0x00 0. " INT ,Global interrupt latched status flag" "No interrupt,Interrupt"
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group.word 0x30++0x03
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line.word 0x00 "ETSEL,Event Select Register"
|
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bitfld.word 0x00 15. " SOCBEN ,Enable the ADC start of conversion B pulse" "Disabled,Enabled"
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bitfld.word 0x00 12.--14. " SOCBSEL ,Start of conversion B option select" "DCBEVT1,TBCTR=0,TBCTR=TBPRD,TBCTR=0 or TBCTR=TBPRD,TBCTR=CMPA for INC,TBCTR=CMPA for DEC,TBCTR=CMPB for INC,TBCTR=CMPB for DEC"
|
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bitfld.word 0x00 11. " SOCAEN ,Enable the ADC start of conversion A pulse" "Disabled,Enabled"
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|
newline
|
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bitfld.word 0x00 8.--10. " SOCASEL ,Start of conversion A option select" "DCAEVT1,TBCTR=0,TBCTR=TBPRD,TBCTR=0 or TBCTR=TBPRD,TBCTR=CMPA for INC,TBCTR=CMPA for DEC,TBCTR=CMPB for INC,TBCTR=CMPB for DEC"
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bitfld.word 0x00 3. " INTEN ,Enable ePWM interrupt generation" "Disabled,Enabled"
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bitfld.word 0x00 0.--2. " INTSEL ,EPWM interrupt option select" ",TBCTR=0,TBCTR=TBPRD,TBCTR=0 or TBCTR=TBPRD,TBCTR=CMPA for INC,TBCTR=CMPA for DEC,TBCTR=CMPB for INC,TBCTR=CMPB for DEC"
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line.word 0x02 "TZFLG,Trip-Zone Flag Register"
|
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bitfld.word 0x02 6. " DCBEVT2 ,Force flag for digital compare output B event 2" "No interrupt,Interrupt"
|
|
bitfld.word 0x02 5. " DCBEVT1 ,Force flag for digital compare output B event 1" "No interrupt,Interrupt"
|
|
bitfld.word 0x02 4. " DCAEVT2 ,Force flag for digital compare output A event 2" "No interrupt,Interrupt"
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|
newline
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bitfld.word 0x02 3. " DCAEVT1 ,Force flag for digital compare output A event 1" "No interrupt,Interrupt"
|
|
bitfld.word 0x02 2. " OST ,Force flag for one-shot trip latch" "No interrupt,Interrupt"
|
|
bitfld.word 0x02 1. " CBC ,Force flag for cycle-by-cycle trip latch" "No interrupt,Interrupt"
|
|
group.word 0x34++0x01
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|
line.word 0x00 "ET_SETCLR,Event Set/Clear Register"
|
|
setclrfld.word 0x00 3. 0x04 3. 0x06 3. " SOCB ,Latched ePWM ADC start of conversation B status flag" "No interrupt,Interrupt"
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|
setclrfld.word 0x00 2. 0x04 2. 0x06 2. " SOCA ,Latched ePWM ADC start of conversation A status flag" "No interrupt,Interrupt"
|
|
setclrfld.word 0x00 0. 0x04 0. 0x06 0. " INT ,Latched ePWM interrupt status flag" "No interrupt,Interrupt"
|
|
group.word 0x36++0x01
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|
line.word 0x00 "ETPS,Event Period Select Register"
|
|
rbitfld.word 0x00 14.--15. " SOCBCNT ,ePWM ADC start of conversion B event counter" "No events,1 event,2 events,3 events"
|
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bitfld.word 0x00 12.--13. " SOCBPRD ,ePWM ADC start of conversion B event period select" "Disabled,1st event,2nd event,3rd event"
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rbitfld.word 0x00 10.--11. " SOCACNT ,ePWM ADC start of conversion A event counter" "No events,1 event,2 events,3 events"
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newline
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bitfld.word 0x00 8.--9. " SOCAPRD ,ePWM ADC start of conversion A event period select" "Disabled,1st event,2nd event,3rd event"
|
|
rbitfld.word 0x00 2.--3. " INTCNT ,ePWM interrupt event counter" "No events,1 event,2 events,3 events"
|
|
bitfld.word 0x00 0.--1. " INTPRD ,ePWM interrupt period select" "Disabled,1st event,2nd event,3rd event"
|
|
group.word 0x3E++0x01
|
|
line.word 0x00 "PCCTL,PWM Chopping Control Register"
|
|
bitfld.word 0x00 8.--10. " CHPDUTY ,Chopping clock duty cycle" "1/8,2/8,3/8,4/8,5/8,6/8,7/8,"
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bitfld.word 0x00 5.--7. " CHPFREQ ,Chopping clock frequency" "/1,/2,/3,/4,/5,/6,/7,/8"
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|
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bitfld.word 0x00 1.--4. " OSHTWTH ,One-shot pulse width" "1 x VCLK4 / 8,2 x VCLK4 / 8,3 x VCLK4 / 8,4 x VCLK4 / 8,5 x VCLK4 / 8,6 x VCLK4 / 8,7 x VCLK4 / 8,8 x VCLK4 / 8,9 x VCLK4 / 8,10 x VCLK4 / 8,11 x VCLK4 / 8,12 x VCLK4 / 8,13 x VCLK4 / 8,14 x VCLK4 / 8,15 x VCLK4 / 8,16 x VCLK4 / 8"
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bitfld.word 0x00 0. " CHPEN ,PWM-chopping enable" "Disabled,Enabled"
|
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group.word 0x60++0x07
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line.word 0x00 "DCACTL,DCA Control Register"
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bitfld.word 0x00 9. " EVT2FRC_SYNCSEL ,DCAEVT2 force synchronization signal select" "Synchronous,Asynchronous"
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bitfld.word 0x00 8. " EVT2SRCSEL ,DCAEVT2 source signal select" "DCAEVT2,DCEVTFILT"
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bitfld.word 0x00 3. " EVT1SYNCE ,DCAEVT1 SYNC enable" "Disabled,Enabled"
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|
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bitfld.word 0x00 2. " EVT1SOCE ,DCAEVT1 SOC enable" "Disabled,Enabled"
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bitfld.word 0x00 1. " EVT1FRC_SYNCSEL ,DCAEVT1 force synchronization signal select" "Synchronous,Asynchronous"
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bitfld.word 0x00 0. " EVT1SRCSEL ,DCAEVT1 source signal select" "DCAEVT1,DCEVTFILT"
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line.word 0x02 "DCTRIPSEL,Digital Compare Select Register"
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bitfld.word 0x02 12.--15. " DCBLCOMPSEL ,Digital compare B low input select" "/TZ1,/TZ2,/TZ3,?..."
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bitfld.word 0x02 8.--11. " DCBHCOMPSEL ,Digital compare B high input select" "/TZ1,/TZ2,/TZ3,?..."
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bitfld.word 0x02 4.--7. " DCALCOMPSEL ,Digital compare A low input select" "/TZ1,/TZ2,/TZ3,?..."
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bitfld.word 0x02 0.--3. " DCAHCOMPSEL ,Digital compare A high input select" "/TZ1,/TZ2,/TZ3,?..."
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line.word 0x04 "DCFCTL,DC Control Register"
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bitfld.word 0x04 4.--5. " PULSESEL ,Pulse select for blanking and capture alignment" "TBCTR=TBPRD,TBCTR=0,?..."
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bitfld.word 0x04 3. " BLANKINV ,Banking windows inversion" "Not inverted,Inverted"
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|
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bitfld.word 0x04 2. " BLANKE ,Blanking widow enable" "Disabled,Enabled"
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bitfld.word 0x04 0.--1. " SRCSEL ,Filter block signal source select" "DCAEVT1,DCAEVT2,DCBEVT1,DCBEVT2"
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line.word 0x06 "DCBCTL,DCB Control Register"
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bitfld.word 0x06 9. " EVT2FRC_SYNCSEL ,DCBEVT2 force synchronization signal select" "Synchronous,Asynchronous"
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bitfld.word 0x06 8. " EVT2SRCSEL ,DCBEVT2 source signal select" "DCBEVT2,DCEVTFILT"
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bitfld.word 0x06 3. " EVT1SYNCE ,DCBEVT1 SYNC enable" "Disabled,Enabled"
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bitfld.word 0x06 2. " EVT1SOCE ,DCBEVT1 SOC enable" "Disabled,Enabled"
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bitfld.word 0x06 1. " EVT1FRC_SYNCSEL ,DCBEVT1 force synchronization signal select" "Synchronous,Asynchronous"
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bitfld.word 0x06 0. " EVT1SRCSEL ,DCBEVT1 source signal select" "DCBEVT1,DCEVTFILT"
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rgroup.word 0x68++0x01
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line.word 0x00 "DCFOFFSET,Blanking Window Offset Register"
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group.word 0x6A++0x01
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line.word 0x00 "DCCAPCTL,DC Capture Control Register"
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bitfld.word 0x00 1. " SHDWMODE ,TBCTR counter capture shadow select mode" "Enable shadow,Active"
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bitfld.word 0x00 0. " CAPE ,TBCTR counter capture enable" "Disabled,Enabled"
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rgroup.word 0x6E++0x05
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line.word 0x00 "DCFOFFSETCNT,Blanking Offset Counter Register"
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line.word 0x02 "DCCAP,Digital Compare Capture Register"
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line.word 0x04 "DCFWINDOWCNT,DC Blanking Window Counter Register"
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hexmask.word.byte 0x04 0.--7. 1. " WINDOWCNT ,Blanking window counter"
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endian.le
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width 0x0B
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tree.end
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tree "EPWM7"
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base ad:0xFCF79200
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endian.be
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width 14.
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group.word 0x00++0x05
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line.word 0x00 "TBSTS,Time-Base Status Register"
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eventfld.word 0x00 2. " CTRMAX ,Time-base counter max latched status" "Not reached,Reached"
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eventfld.word 0x00 1. " SYNCI ,Input synchronization latched status" "Not occurred,Occurred"
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rbitfld.word 0x00 0. " CTRDIR ,Time-base counter direction status" "Counting down,Counting up"
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line.word 0x02 "TBCTL,Time-Base Control Register"
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bitfld.word 0x02 14.--15. " FREE_SOFT ,Emulation mode" "Stop after INC/DEC,Stop after cycle,Free run,Free run"
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bitfld.word 0x02 13. " PHSDIR ,Phase direction" "Count down,Count up"
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bitfld.word 0x02 10.--12. " CLKDIV ,Time-base clock prescale" "/1,/2,/4,/8,/16,/32,/64,/128"
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bitfld.word 0x02 7.--9. " HSPCLKDIV ,High speed time-base clock prescale" "/1,/2,/4,/6,/8,/10,/12,/14"
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eventfld.word 0x02 6. " SWFSYNC ,Software forced synchronization pulse" "No effect,Forced"
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bitfld.word 0x02 4.--5. " SYNCOSEL ,Synchronization output select" "EPWMxSYNC,CTR=zero,CTR=CMPB,Disabled"
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bitfld.word 0x02 3. " PRDLD ,Active period register load from shadow register usage" "Used,Not used"
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bitfld.word 0x02 2. " PHSEN ,Counter register load from phase register enable" "Disabled,Enabled"
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bitfld.word 0x02 0.--1. " CTRMODE ,Counter mode" "Up-count,Down-count,Up-down-count,Stop-freeze cnt"
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line.word 0x04 "TBPHS,Time-Base Counter Phase Register"
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group.word 0x08++0x05
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line.word 0x00 "TBPRD,Time-Base Period Register"
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line.word 0x02 "TBCTR,Time-Base Counter Register"
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line.word 0x04 "CMPCTL,Counter-Compare Control Register"
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rbitfld.word 0x04 9. " SHDWBFULL ,Counter-compare B shadow register full status flag" "Not full,Full"
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rbitfld.word 0x04 8. " SHDWAFULL ,Counter-compare A shadow register full status flag" "Not full,Full"
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bitfld.word 0x04 6. " SHDWBMODE ,Counter-compare B register operating mode" "Shadow,Immediate"
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bitfld.word 0x04 4. " SHDWAMODE ,Counter-compare A register operating mode" "Shadow,Immediate"
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bitfld.word 0x04 2.--3. " LOADBMODE ,Active counter-compare B load from shadow select mode" "CTR=Zero,CTR=PRD,Both,Freeze"
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bitfld.word 0x04 0.--1. " LOADBMODE ,Active counter-compare B load from shadow select mode" "CTR=Zero,CTR=PRD,Both,Freeze"
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group.word 0x10++0x01
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line.word 0x00 "CMPA,Compare A Register"
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group.word 0x14++0x17
|
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line.word 0x00 "AQCTLA,AQCTLA Register"
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bitfld.word 0x00 10.--11. " CBD ,Action when the time-base counter = CMPB register and the counter is decrementing" "Disabled,Clear,Set,Toggle output"
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bitfld.word 0x00 8.--9. " CBU ,Action when the time-base counter = CMPB register and the counter is incrementing" "Disabled,Clear,Set,Toggle output"
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bitfld.word 0x00 6.--7. " CAD ,Action when the time-base counter = CMPA register and the counter is decrementing" "Disabled,Clear,Set,Toggle output"
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bitfld.word 0x00 4.--5. " CAU ,Action when the time-base counter = CMPA register and the counter is incrementing" "Disabled,Clear,Set,Toggle output"
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bitfld.word 0x00 2.--3. " PRD ,Action when the counter = the period" "Disabled,Clear,Set,Toggle output"
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bitfld.word 0x00 0.--1. " ZRO ,Action when the counter = zero" "Disabled,Clear,Set,Toggle output"
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line.word 0x02 "CMPB,Compare B Register"
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line.word 0x04 "AQSFRC,AQSFRC Register"
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bitfld.word 0x04 6.--7. " RLDCSF ,AQCSFRC active register reload from shadow options" "CNT=0,CNT=period,CNT=0 or CNT=period,Load immediately"
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eventfld.word 0x04 5. " OTSFB ,One-time software forced event on output B" "No effect,Forced"
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bitfld.word 0x04 3.--4. " ACTSFB ,Action when one-time software force B is invoked" "Disabled,Clear,Set,Toggle"
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newline
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eventfld.word 0x04 2. " OTSFA ,One-time software forced event on output A" "No effect,Forced"
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bitfld.word 0x04 0.--1. " ACTSFA ,Action when one-time software force A is invoked" "Disabled,Clear,Set,Toggle"
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line.word 0x06 "AQCTLA,AQCTLA Register"
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bitfld.word 0x06 10.--11. " CBD ,Action when the time-base counter = CMPB register and the counter is decrementing" "Disabled,Clear,Set,Toggle output"
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bitfld.word 0x06 8.--9. " CBU ,Action when the time-base counter = CMPB register and the counter is incrementing" "Disabled,Clear,Set,Toggle output"
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bitfld.word 0x06 6.--7. " CAD ,Action when the time-base counter = CMPA register and the counter is decrementing" "Disabled,Clear,Set,Toggle output"
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newline
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bitfld.word 0x06 4.--5. " CAU ,Action when the time-base counter = CMPA register and the counter is incrementing" "Disabled,Clear,Set,Toggle output"
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bitfld.word 0x06 2.--3. " PRD ,Action when the counter = the period" "Disabled,Clear,Set,Toggle output"
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bitfld.word 0x06 0.--1. " ZRO ,Action when the counter = zero" "Disabled,Clear,Set,Toggle output"
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line.word 0x08 "DBCTL,Dead-Band Control Register"
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bitfld.word 0x08 15. " HALFCYCLE ,Half cycle clocking enable" "Disabled,Enabled"
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bitfld.word 0x08 4.--5. " IN_MODE ,Dead band input mode control (A In for edge / B In for edge)" "Both / -,Falling / Rising,Rising / Falling,- / Both"
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newline
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bitfld.word 0x08 2.--3. " POLSEL ,Active polarity select control" "High,Low complementary,High complementary,Low"
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bitfld.word 0x08 0.--1. " OUT_MODE ,Dead band output mode control" "Bypass,Rising disabled,Falling disabled,- / Both"
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line.word 0x0A "AQCSFRC,AQCSFRC register"
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bitfld.word 0x0A 2.--3. " CSFB ,Continuous software force on output B" "Disabled,Forced low,Forced high,Disabled"
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bitfld.word 0x0A 0.--1. " CSFA ,Continuous software force on output A" "Disabled,Forced low,Forced high,Disabled"
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line.word 0x0C "DBFED,Falling Edge Delay Register"
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hexmask.word 0x0C 0.--9. 1. " DEL ,Falling edge delay count"
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line.word 0x0E "DBRED,Rising Edge Delay Register"
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hexmask.word 0x0E 0.--9. 1. " DEL ,Rising edge delay count"
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line.word 0x10 "TZDCSEL,Digital Compare Select Register"
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bitfld.word 0x10 9.--11. " DCBEVT2 ,Digital compare output B event 2 selection (DCBL / DCBH)" "Event,Don't care / Low,Don't care / High,Low / Don't care,High / Don't care,High / Low,?..."
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bitfld.word 0x10 6.--8. " DCBEVT1 ,Digital compare output B event 1 selection (DCBL / DCBH)" "Event,Don't care / Low,Don't care / High,Low / Don't care,High / Don't care,High / Low,?..."
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newline
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bitfld.word 0x10 3.--5. " DCAEVT2 ,Digital compare output A event 2 selection (DCAL / DCAH)" "Event,Don't care / Low,Don't care / High,Low / Don't care,High / Don't care,High / Low,?..."
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bitfld.word 0x10 0.--2. " DCAEVT1 ,Digital compare output A event 1 selection (DCAL / DCAH)" "Event,Don't care / Low,Don't care / High,Low / Don't care,High / Don't care,High / Low,?..."
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line.word 0x12 "TZSEL,Trip-Zone Select Register"
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rbitfld.word 0x12 15. " DCBEVT1 ,Digital compare output B event 1 enable" "Disabled,Enabled"
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rbitfld.word 0x12 14. " DCAEVT1 ,Digital compare output A event 1 enable" "Disabled,Enabled"
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bitfld.word 0x12 13. " OSHT6 ,Trip-zone 6 (/TZ6) as one-shot trip enable" "Disabled,Enabled"
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newline
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bitfld.word 0x12 12. " OSHT5 ,Trip-zone 5 (/TZ5) as one-shot trip enable" "Disabled,Enabled"
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bitfld.word 0x12 11. " OSHT4 ,Trip-zone 4 (/TZ4) as one-shot trip enable" "Disabled,Enabled"
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bitfld.word 0x12 10. " OSHT3 ,Trip-zone 3 (/TZ3) as one-shot trip enable" "Disabled,Enabled"
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newline
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bitfld.word 0x12 9. " OSHT2 ,Trip-zone 2 (/TZ2) as one-shot trip enable" "Disabled,Enabled"
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bitfld.word 0x12 8. " OSHT1 ,Trip-zone 1 (/TZ1) as one-shot trip enable" "Disabled,Enabled"
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rbitfld.word 0x12 7. " DCBEVT2 ,Digital compare output B event 2 enable" "Disabled,Enabled"
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newline
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rbitfld.word 0x12 6. " DCAEVT2 ,Digital compare output A event 2 enable" "Disabled,Enabled"
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bitfld.word 0x12 5. " CBC6 ,Trip-zone 6 (/TZ6) as CBC enable" "Disabled,Enabled"
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bitfld.word 0x12 4. " CBC5 ,Trip-zone 5 (/TZ5) as CBC enable" "Disabled,Enabled"
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bitfld.word 0x12 3. " CBC4 ,Trip-zone 4 (/TZ4) as CBC enable" "Disabled,Enabled"
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bitfld.word 0x12 2. " CBC3 ,Trip-zone 3 (/TZ3) as CBC enable" "Disabled,Enabled"
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newline
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bitfld.word 0x12 1. " CBC2 ,Trip-zone 2 (/TZ2) as CBC enable" "Disabled,Enabled"
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bitfld.word 0x12 0. " CBC1 ,Trip-zone 1 (/TZ1) as CBC enable" "Disabled,Enabled"
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line.word 0x14 "TZEINT,Trip-Zone Interrupt Register"
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bitfld.word 0x14 6. " DCBEVT2 ,Digital comparator output B event 2 interrupt enable" "Disabled,Enabled"
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bitfld.word 0x14 5. " DCBEVT1 ,Digital comparator output B event 1 interrupt enable" "Disabled,Enabled"
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bitfld.word 0x14 4. " DCAEVT2 ,Digital comparator output A event 2 interrupt enable" "Disabled,Enabled"
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newline
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bitfld.word 0x14 3. " DCAEVT1 ,Digital comparator output A event 1 interrupt enable" "Disabled,Enabled"
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bitfld.word 0x14 2. " OST ,Trip-zone one-shot interrupt enable" "Disabled,Enabled"
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bitfld.word 0x14 1. " CBC ,Trip-zone cycle-by-cycle interrupt enable" "Disabled,Enabled"
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line.word 0x16 "TZCTL,Trip-Zone Control Register"
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bitfld.word 0x16 10.--11. " DCBEVT2 ,Digital compare output B event 2 action on EPWMxB" "High-impedance,Forced high,Forced low,Disabled"
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bitfld.word 0x16 8.--9. " DCBEVT1 ,Digital compare output B event 1 action on EPWMxB" "High-impedance,Forced high,Forced low,Disabled"
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bitfld.word 0x16 6.--7. " DCAEVT2 ,Digital compare output A event 2 action on EPWMxA" "High-impedance,Forced high,Forced low,Disabled"
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newline
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bitfld.word 0x16 4.--5. " DCAEVT1 ,Digital compare output A event 1 action on EPWMxA" "High-impedance,Forced high,Forced low,Disabled"
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bitfld.word 0x16 2.--3. " TZB ,Action on trip-zone event for EPWMxB select" "High-impedance,Forced high,Forced low,Disabled"
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bitfld.word 0x16 0.--1. " TZA ,Action on trip-zone event for EPWMxA select" "High-impedance,Forced high,Forced low,Disabled"
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wgroup.word 0x2C++0x01
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line.word 0x00 "TZCLR,Trip-Zone Clear Register"
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bitfld.word 0x00 6. " DCBEVT2 ,Clear flag for digital compare output B event 2" "No effect,Clear"
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bitfld.word 0x00 5. " DCBEVT1 ,Clear flag for digital compare output B event 1" "No effect,Clear"
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bitfld.word 0x00 4. " DCAEVT2 ,Clear flag for digital compare output A event 2" "No effect,Clear"
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newline
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bitfld.word 0x00 3. " DCAEVT1 ,Clear flag for digital compare output A event 1" "No effect,Clear"
|
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bitfld.word 0x00 2. " OST ,Clear flag for one-shot trip latch" "No effect,Clear"
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bitfld.word 0x00 1. " CBC ,Clear flag for cycle-by-cycle trip latch" "No effect,Clear"
|
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bitfld.word 0x00 0. " INT ,Global interrupt clear flag" "No effect,Clear"
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rgroup.word 0x2E++0x01
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line.word 0x00 "TZFLG,Trip-Zone Flag Register"
|
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bitfld.word 0x00 6. " DCBEVT2 ,Latched status flag for digital compare output B event 2" "No interrupt,Interrupt"
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bitfld.word 0x00 5. " DCBEVT1 ,Latched status flag for digital compare output B event 1" "No interrupt,Interrupt"
|
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bitfld.word 0x00 4. " DCAEVT2 ,Latched status flag for digital compare output A event 2" "No interrupt,Interrupt"
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newline
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bitfld.word 0x00 3. " DCAEVT1 ,Latched status flag for digital compare output A event 1" "No interrupt,Interrupt"
|
|
bitfld.word 0x00 2. " OST ,Latched status flag for one-shot trip latch" "No interrupt,Interrupt"
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newline
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bitfld.word 0x00 1. " CBC ,Latched status flag for cycle-by-cycle trip latch" "No interrupt,Interrupt"
|
|
bitfld.word 0x00 0. " INT ,Global interrupt latched status flag" "No interrupt,Interrupt"
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group.word 0x30++0x03
|
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line.word 0x00 "ETSEL,Event Select Register"
|
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bitfld.word 0x00 15. " SOCBEN ,Enable the ADC start of conversion B pulse" "Disabled,Enabled"
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bitfld.word 0x00 12.--14. " SOCBSEL ,Start of conversion B option select" "DCBEVT1,TBCTR=0,TBCTR=TBPRD,TBCTR=0 or TBCTR=TBPRD,TBCTR=CMPA for INC,TBCTR=CMPA for DEC,TBCTR=CMPB for INC,TBCTR=CMPB for DEC"
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bitfld.word 0x00 11. " SOCAEN ,Enable the ADC start of conversion A pulse" "Disabled,Enabled"
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|
newline
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bitfld.word 0x00 8.--10. " SOCASEL ,Start of conversion A option select" "DCAEVT1,TBCTR=0,TBCTR=TBPRD,TBCTR=0 or TBCTR=TBPRD,TBCTR=CMPA for INC,TBCTR=CMPA for DEC,TBCTR=CMPB for INC,TBCTR=CMPB for DEC"
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bitfld.word 0x00 3. " INTEN ,Enable ePWM interrupt generation" "Disabled,Enabled"
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bitfld.word 0x00 0.--2. " INTSEL ,EPWM interrupt option select" ",TBCTR=0,TBCTR=TBPRD,TBCTR=0 or TBCTR=TBPRD,TBCTR=CMPA for INC,TBCTR=CMPA for DEC,TBCTR=CMPB for INC,TBCTR=CMPB for DEC"
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line.word 0x02 "TZFLG,Trip-Zone Flag Register"
|
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bitfld.word 0x02 6. " DCBEVT2 ,Force flag for digital compare output B event 2" "No interrupt,Interrupt"
|
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bitfld.word 0x02 5. " DCBEVT1 ,Force flag for digital compare output B event 1" "No interrupt,Interrupt"
|
|
bitfld.word 0x02 4. " DCAEVT2 ,Force flag for digital compare output A event 2" "No interrupt,Interrupt"
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|
newline
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bitfld.word 0x02 3. " DCAEVT1 ,Force flag for digital compare output A event 1" "No interrupt,Interrupt"
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|
bitfld.word 0x02 2. " OST ,Force flag for one-shot trip latch" "No interrupt,Interrupt"
|
|
bitfld.word 0x02 1. " CBC ,Force flag for cycle-by-cycle trip latch" "No interrupt,Interrupt"
|
|
group.word 0x34++0x01
|
|
line.word 0x00 "ET_SETCLR,Event Set/Clear Register"
|
|
setclrfld.word 0x00 3. 0x04 3. 0x06 3. " SOCB ,Latched ePWM ADC start of conversation B status flag" "No interrupt,Interrupt"
|
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setclrfld.word 0x00 2. 0x04 2. 0x06 2. " SOCA ,Latched ePWM ADC start of conversation A status flag" "No interrupt,Interrupt"
|
|
setclrfld.word 0x00 0. 0x04 0. 0x06 0. " INT ,Latched ePWM interrupt status flag" "No interrupt,Interrupt"
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|
group.word 0x36++0x01
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line.word 0x00 "ETPS,Event Period Select Register"
|
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rbitfld.word 0x00 14.--15. " SOCBCNT ,ePWM ADC start of conversion B event counter" "No events,1 event,2 events,3 events"
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bitfld.word 0x00 12.--13. " SOCBPRD ,ePWM ADC start of conversion B event period select" "Disabled,1st event,2nd event,3rd event"
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rbitfld.word 0x00 10.--11. " SOCACNT ,ePWM ADC start of conversion A event counter" "No events,1 event,2 events,3 events"
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newline
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bitfld.word 0x00 8.--9. " SOCAPRD ,ePWM ADC start of conversion A event period select" "Disabled,1st event,2nd event,3rd event"
|
|
rbitfld.word 0x00 2.--3. " INTCNT ,ePWM interrupt event counter" "No events,1 event,2 events,3 events"
|
|
bitfld.word 0x00 0.--1. " INTPRD ,ePWM interrupt period select" "Disabled,1st event,2nd event,3rd event"
|
|
group.word 0x3E++0x01
|
|
line.word 0x00 "PCCTL,PWM Chopping Control Register"
|
|
bitfld.word 0x00 8.--10. " CHPDUTY ,Chopping clock duty cycle" "1/8,2/8,3/8,4/8,5/8,6/8,7/8,"
|
|
bitfld.word 0x00 5.--7. " CHPFREQ ,Chopping clock frequency" "/1,/2,/3,/4,/5,/6,/7,/8"
|
|
newline
|
|
bitfld.word 0x00 1.--4. " OSHTWTH ,One-shot pulse width" "1 x VCLK4 / 8,2 x VCLK4 / 8,3 x VCLK4 / 8,4 x VCLK4 / 8,5 x VCLK4 / 8,6 x VCLK4 / 8,7 x VCLK4 / 8,8 x VCLK4 / 8,9 x VCLK4 / 8,10 x VCLK4 / 8,11 x VCLK4 / 8,12 x VCLK4 / 8,13 x VCLK4 / 8,14 x VCLK4 / 8,15 x VCLK4 / 8,16 x VCLK4 / 8"
|
|
bitfld.word 0x00 0. " CHPEN ,PWM-chopping enable" "Disabled,Enabled"
|
|
group.word 0x60++0x07
|
|
line.word 0x00 "DCACTL,DCA Control Register"
|
|
bitfld.word 0x00 9. " EVT2FRC_SYNCSEL ,DCAEVT2 force synchronization signal select" "Synchronous,Asynchronous"
|
|
bitfld.word 0x00 8. " EVT2SRCSEL ,DCAEVT2 source signal select" "DCAEVT2,DCEVTFILT"
|
|
bitfld.word 0x00 3. " EVT1SYNCE ,DCAEVT1 SYNC enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.word 0x00 2. " EVT1SOCE ,DCAEVT1 SOC enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 1. " EVT1FRC_SYNCSEL ,DCAEVT1 force synchronization signal select" "Synchronous,Asynchronous"
|
|
bitfld.word 0x00 0. " EVT1SRCSEL ,DCAEVT1 source signal select" "DCAEVT1,DCEVTFILT"
|
|
line.word 0x02 "DCTRIPSEL,Digital Compare Select Register"
|
|
bitfld.word 0x02 12.--15. " DCBLCOMPSEL ,Digital compare B low input select" "/TZ1,/TZ2,/TZ3,?..."
|
|
bitfld.word 0x02 8.--11. " DCBHCOMPSEL ,Digital compare B high input select" "/TZ1,/TZ2,/TZ3,?..."
|
|
newline
|
|
bitfld.word 0x02 4.--7. " DCALCOMPSEL ,Digital compare A low input select" "/TZ1,/TZ2,/TZ3,?..."
|
|
bitfld.word 0x02 0.--3. " DCAHCOMPSEL ,Digital compare A high input select" "/TZ1,/TZ2,/TZ3,?..."
|
|
line.word 0x04 "DCFCTL,DC Control Register"
|
|
bitfld.word 0x04 4.--5. " PULSESEL ,Pulse select for blanking and capture alignment" "TBCTR=TBPRD,TBCTR=0,?..."
|
|
bitfld.word 0x04 3. " BLANKINV ,Banking windows inversion" "Not inverted,Inverted"
|
|
newline
|
|
bitfld.word 0x04 2. " BLANKE ,Blanking widow enable" "Disabled,Enabled"
|
|
bitfld.word 0x04 0.--1. " SRCSEL ,Filter block signal source select" "DCAEVT1,DCAEVT2,DCBEVT1,DCBEVT2"
|
|
line.word 0x06 "DCBCTL,DCB Control Register"
|
|
bitfld.word 0x06 9. " EVT2FRC_SYNCSEL ,DCBEVT2 force synchronization signal select" "Synchronous,Asynchronous"
|
|
bitfld.word 0x06 8. " EVT2SRCSEL ,DCBEVT2 source signal select" "DCBEVT2,DCEVTFILT"
|
|
bitfld.word 0x06 3. " EVT1SYNCE ,DCBEVT1 SYNC enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.word 0x06 2. " EVT1SOCE ,DCBEVT1 SOC enable" "Disabled,Enabled"
|
|
bitfld.word 0x06 1. " EVT1FRC_SYNCSEL ,DCBEVT1 force synchronization signal select" "Synchronous,Asynchronous"
|
|
bitfld.word 0x06 0. " EVT1SRCSEL ,DCBEVT1 source signal select" "DCBEVT1,DCEVTFILT"
|
|
rgroup.word 0x68++0x01
|
|
line.word 0x00 "DCFOFFSET,Blanking Window Offset Register"
|
|
group.word 0x6A++0x01
|
|
line.word 0x00 "DCCAPCTL,DC Capture Control Register"
|
|
bitfld.word 0x00 1. " SHDWMODE ,TBCTR counter capture shadow select mode" "Enable shadow,Active"
|
|
bitfld.word 0x00 0. " CAPE ,TBCTR counter capture enable" "Disabled,Enabled"
|
|
rgroup.word 0x6E++0x05
|
|
line.word 0x00 "DCFOFFSETCNT,Blanking Offset Counter Register"
|
|
line.word 0x02 "DCCAP,Digital Compare Capture Register"
|
|
line.word 0x04 "DCFWINDOWCNT,DC Blanking Window Counter Register"
|
|
hexmask.word.byte 0x04 0.--7. 1. " WINDOWCNT ,Blanking window counter"
|
|
endian.le
|
|
width 0x0B
|
|
tree.end
|
|
tree.end
|
|
endif
|
|
sif cpuis("TMS570LS0714*")||cpuis("TMS570LS0914*")
|
|
tree.open "ECAP (Enhanced Capture Module)"
|
|
tree "ECAP1"
|
|
base ad:0xFCF79300
|
|
endian.be
|
|
width 15.
|
|
group.long 0x00++0x07
|
|
line.long 0x00 "TSCTR,Capture Time-Base Counter Register"
|
|
line.long 0x04 "CTRPHS,Counter Phase Value Register"
|
|
group.long 0x8++0x03
|
|
line.long 0x00 "CAP1,Capture register 1"
|
|
group.long 0xC++0x03
|
|
line.long 0x00 "CAP2,Capture register 2"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "CAP3,Capture register 3"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "CAP4,Capture register 4"
|
|
group.word 0x28++0x03
|
|
line.word 0x00 "ECCTL2,ECAP Control Register 2"
|
|
bitfld.word 0x00 10. " APWMPOL ,APWM output polarity select" "Active HIGH,Active LOW"
|
|
bitfld.word 0x00 9. " CAP_APWM ,CAP/APWM operating mode select" "Capture,APWM"
|
|
bitfld.word 0x00 8. " SWSYNC ,Software-focused counter synchronizing" "No effect,Forced TSCTR"
|
|
newline
|
|
bitfld.word 0x00 6.--7. " SYNCO_SEL ,Sync-out select" "Sync-in event,CTR = PRD event,Disabled,Disabled"
|
|
bitfld.word 0x00 5. " SYNCI_EN ,Counter sync-in select mode" "Disabled,Enabled"
|
|
bitfld.word 0x00 4. " TSCTRSTOP ,Time stamp counter stop control" "Stopped,Free-running"
|
|
newline
|
|
bitfld.word 0x00 3. " REARM ,One-shot re-arming control" "No effect,Enabled"
|
|
bitfld.word 0x00 1.--2. " STOP_WRAP ,Stop value for one-shot mode" "Event 1,Event 2,Event 3,Event 4"
|
|
bitfld.word 0x00 0. " CONT_ONESHT ,Continuous or one-shot mode control" "Continuous,One-shot"
|
|
line.word 0x02 "ECCTL1,ECAP Control Register 1"
|
|
bitfld.word 0x02 14.--15. " FREE_SOFT ,Emulation control effect on TSCTR counter" "Stopped,Run,Unaffected,Unaffected"
|
|
bitfld.word 0x02 9.--13. " PRESCALE ,Event filter prescale select" "No prescale,/2,/4,/6,/8,/10,/12,/14,/16,/18,/20,/22,/24,/26,/28,/30,/32,/34,/36,/38,/40,/42,/44,/46,/48,/50,/52,/54,/56,/58,/60,/62"
|
|
bitfld.word 0x02 8. " CAPLDEN ,Enable loading of CAP1-4 registers on a capture event" "Disabled,Enabled"
|
|
newline
|
|
bitfld.word 0x02 7. " CTRRST4 ,Counter reset on capture event 4" "No reset,Reset"
|
|
bitfld.word 0x02 6. " CAP4POL ,Capture event 4 polarity select" "Rising edge,Falling edge"
|
|
bitfld.word 0x02 5. " CTRRST3 ,Counter reset on capture event 3" "No reset,Reset"
|
|
newline
|
|
bitfld.word 0x02 4. " CAP3POL ,Capture event 3 polarity select" "Rising edge,Falling edge"
|
|
bitfld.word 0x02 3. " CTRRST2 ,Counter reset on capture event 2" "No reset,Reset"
|
|
bitfld.word 0x02 2. " CAP2POL ,Capture event 2 polarity select" "Rising edge,Falling edge"
|
|
newline
|
|
bitfld.word 0x02 1. " CTRRST1 ,Counter reset on capture event 1" "No reset,Reset"
|
|
bitfld.word 0x02 0. " CAP1POL ,Capture event 1 polarity select" "Rising edge,Falling edge"
|
|
rgroup.word 0x2C++0x01
|
|
line.word 0x00 "ECFLG,ECAP Flag Register"
|
|
bitfld.word 0x00 7. " CTR_CMP ,Counter compare equal status flag" "No event,Triggered"
|
|
bitfld.word 0x00 6. " CTR_PRD ,Counter equal period status flag" "No event,Triggered"
|
|
bitfld.word 0x00 5. " CTROVF ,Counter overflow status flag" "No event,Triggered"
|
|
newline
|
|
bitfld.word 0x00 4. " CEVT4 ,Capture event 4 status flag" "No event,Triggered"
|
|
bitfld.word 0x00 3. " CEVT3 ,Capture event 3 status flag" "No event,Triggered"
|
|
bitfld.word 0x00 2. " CEVT2 ,Capture event 2 status flag" "No event,Triggered"
|
|
newline
|
|
bitfld.word 0x00 1. " CEVT1 ,Capture event 1 status flag" "No event,Triggered"
|
|
bitfld.word 0x00 0. " INT ,Global interrupt status flag" "No event,Triggered"
|
|
group.word 0x2E++0x01
|
|
line.word 0x00 "ECEINT,ECAP Interrupt Enable Register"
|
|
bitfld.word 0x00 7. " CTR_CMP ,Counter equal compare interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 6. " CTR_PRD ,Counter equal period interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 5. " CTROVF ,Counter overflow interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.word 0x00 4. " CEVT4 ,Capture event 4 interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 3. " CEVT3 ,Capture event 3 interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.word 0x00 2. " CEVT2 ,Capture event 2 interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 1. " CEVT1 ,Capture event 1 interrupt enable" "Disabled,Enabled"
|
|
group.word 0x30++0x01
|
|
line.word 0x00 "ECFRC_SET/CLR,ECAP Force Counter Set/Clear Register"
|
|
setclrfld.word 0x00 7. 0x00 7. 0x02 7. " CTR_CMP ,Force counter equal compare interrupt" "No event,Forced"
|
|
setclrfld.word 0x00 6. 0x00 6. 0x02 6. " CTR_PRD ,Force counter equal period interrupt" "No event,Forced"
|
|
setclrfld.word 0x00 5. 0x00 5. 0x02 5. " CTROVF ,Force counter overflow interrupt" "No event,Forced"
|
|
newline
|
|
setclrfld.word 0x00 4. 0x00 4. 0x02 4. " CEVT4 ,Force capture event 4 interrupt" "No event,Forced"
|
|
setclrfld.word 0x00 3. 0x00 3. 0x02 3. " CEVT3 ,Force capture event 3 interrupt" "No event,Forced"
|
|
newline
|
|
setclrfld.word 0x00 2. 0x00 2. 0x02 2. " CEVT2 ,Force capture event 2 interrupt" "No event,Forced"
|
|
setclrfld.word 0x00 1. 0x00 1. 0x02 1. " CEVT1 ,Force capture event 1 interrupt" "No event,Forced"
|
|
endian.le
|
|
width 0x0B
|
|
tree.end
|
|
tree "ECAP2"
|
|
base ad:0xFCF79400
|
|
endian.be
|
|
width 15.
|
|
group.long 0x00++0x07
|
|
line.long 0x00 "TSCTR,Capture Time-Base Counter Register"
|
|
line.long 0x04 "CTRPHS,Counter Phase Value Register"
|
|
group.long 0x8++0x03
|
|
line.long 0x00 "CAP1,Capture register 1"
|
|
group.long 0xC++0x03
|
|
line.long 0x00 "CAP2,Capture register 2"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "CAP3,Capture register 3"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "CAP4,Capture register 4"
|
|
group.word 0x28++0x03
|
|
line.word 0x00 "ECCTL2,ECAP Control Register 2"
|
|
bitfld.word 0x00 10. " APWMPOL ,APWM output polarity select" "Active HIGH,Active LOW"
|
|
bitfld.word 0x00 9. " CAP_APWM ,CAP/APWM operating mode select" "Capture,APWM"
|
|
bitfld.word 0x00 8. " SWSYNC ,Software-focused counter synchronizing" "No effect,Forced TSCTR"
|
|
newline
|
|
bitfld.word 0x00 6.--7. " SYNCO_SEL ,Sync-out select" "Sync-in event,CTR = PRD event,Disabled,Disabled"
|
|
bitfld.word 0x00 5. " SYNCI_EN ,Counter sync-in select mode" "Disabled,Enabled"
|
|
bitfld.word 0x00 4. " TSCTRSTOP ,Time stamp counter stop control" "Stopped,Free-running"
|
|
newline
|
|
bitfld.word 0x00 3. " REARM ,One-shot re-arming control" "No effect,Enabled"
|
|
bitfld.word 0x00 1.--2. " STOP_WRAP ,Stop value for one-shot mode" "Event 1,Event 2,Event 3,Event 4"
|
|
bitfld.word 0x00 0. " CONT_ONESHT ,Continuous or one-shot mode control" "Continuous,One-shot"
|
|
line.word 0x02 "ECCTL1,ECAP Control Register 1"
|
|
bitfld.word 0x02 14.--15. " FREE_SOFT ,Emulation control effect on TSCTR counter" "Stopped,Run,Unaffected,Unaffected"
|
|
bitfld.word 0x02 9.--13. " PRESCALE ,Event filter prescale select" "No prescale,/2,/4,/6,/8,/10,/12,/14,/16,/18,/20,/22,/24,/26,/28,/30,/32,/34,/36,/38,/40,/42,/44,/46,/48,/50,/52,/54,/56,/58,/60,/62"
|
|
bitfld.word 0x02 8. " CAPLDEN ,Enable loading of CAP1-4 registers on a capture event" "Disabled,Enabled"
|
|
newline
|
|
bitfld.word 0x02 7. " CTRRST4 ,Counter reset on capture event 4" "No reset,Reset"
|
|
bitfld.word 0x02 6. " CAP4POL ,Capture event 4 polarity select" "Rising edge,Falling edge"
|
|
bitfld.word 0x02 5. " CTRRST3 ,Counter reset on capture event 3" "No reset,Reset"
|
|
newline
|
|
bitfld.word 0x02 4. " CAP3POL ,Capture event 3 polarity select" "Rising edge,Falling edge"
|
|
bitfld.word 0x02 3. " CTRRST2 ,Counter reset on capture event 2" "No reset,Reset"
|
|
bitfld.word 0x02 2. " CAP2POL ,Capture event 2 polarity select" "Rising edge,Falling edge"
|
|
newline
|
|
bitfld.word 0x02 1. " CTRRST1 ,Counter reset on capture event 1" "No reset,Reset"
|
|
bitfld.word 0x02 0. " CAP1POL ,Capture event 1 polarity select" "Rising edge,Falling edge"
|
|
rgroup.word 0x2C++0x01
|
|
line.word 0x00 "ECFLG,ECAP Flag Register"
|
|
bitfld.word 0x00 7. " CTR_CMP ,Counter compare equal status flag" "No event,Triggered"
|
|
bitfld.word 0x00 6. " CTR_PRD ,Counter equal period status flag" "No event,Triggered"
|
|
bitfld.word 0x00 5. " CTROVF ,Counter overflow status flag" "No event,Triggered"
|
|
newline
|
|
bitfld.word 0x00 4. " CEVT4 ,Capture event 4 status flag" "No event,Triggered"
|
|
bitfld.word 0x00 3. " CEVT3 ,Capture event 3 status flag" "No event,Triggered"
|
|
bitfld.word 0x00 2. " CEVT2 ,Capture event 2 status flag" "No event,Triggered"
|
|
newline
|
|
bitfld.word 0x00 1. " CEVT1 ,Capture event 1 status flag" "No event,Triggered"
|
|
bitfld.word 0x00 0. " INT ,Global interrupt status flag" "No event,Triggered"
|
|
group.word 0x2E++0x01
|
|
line.word 0x00 "ECEINT,ECAP Interrupt Enable Register"
|
|
bitfld.word 0x00 7. " CTR_CMP ,Counter equal compare interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 6. " CTR_PRD ,Counter equal period interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 5. " CTROVF ,Counter overflow interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.word 0x00 4. " CEVT4 ,Capture event 4 interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 3. " CEVT3 ,Capture event 3 interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.word 0x00 2. " CEVT2 ,Capture event 2 interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 1. " CEVT1 ,Capture event 1 interrupt enable" "Disabled,Enabled"
|
|
group.word 0x30++0x01
|
|
line.word 0x00 "ECFRC_SET/CLR,ECAP Force Counter Set/Clear Register"
|
|
setclrfld.word 0x00 7. 0x00 7. 0x02 7. " CTR_CMP ,Force counter equal compare interrupt" "No event,Forced"
|
|
setclrfld.word 0x00 6. 0x00 6. 0x02 6. " CTR_PRD ,Force counter equal period interrupt" "No event,Forced"
|
|
setclrfld.word 0x00 5. 0x00 5. 0x02 5. " CTROVF ,Force counter overflow interrupt" "No event,Forced"
|
|
newline
|
|
setclrfld.word 0x00 4. 0x00 4. 0x02 4. " CEVT4 ,Force capture event 4 interrupt" "No event,Forced"
|
|
setclrfld.word 0x00 3. 0x00 3. 0x02 3. " CEVT3 ,Force capture event 3 interrupt" "No event,Forced"
|
|
newline
|
|
setclrfld.word 0x00 2. 0x00 2. 0x02 2. " CEVT2 ,Force capture event 2 interrupt" "No event,Forced"
|
|
setclrfld.word 0x00 1. 0x00 1. 0x02 1. " CEVT1 ,Force capture event 1 interrupt" "No event,Forced"
|
|
endian.le
|
|
width 0x0B
|
|
tree.end
|
|
tree "ECAP3"
|
|
base ad:0xFCF79500
|
|
endian.be
|
|
width 15.
|
|
group.long 0x00++0x07
|
|
line.long 0x00 "TSCTR,Capture Time-Base Counter Register"
|
|
line.long 0x04 "CTRPHS,Counter Phase Value Register"
|
|
group.long 0x8++0x03
|
|
line.long 0x00 "CAP1,Capture register 1"
|
|
group.long 0xC++0x03
|
|
line.long 0x00 "CAP2,Capture register 2"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "CAP3,Capture register 3"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "CAP4,Capture register 4"
|
|
group.word 0x28++0x03
|
|
line.word 0x00 "ECCTL2,ECAP Control Register 2"
|
|
bitfld.word 0x00 10. " APWMPOL ,APWM output polarity select" "Active HIGH,Active LOW"
|
|
bitfld.word 0x00 9. " CAP_APWM ,CAP/APWM operating mode select" "Capture,APWM"
|
|
bitfld.word 0x00 8. " SWSYNC ,Software-focused counter synchronizing" "No effect,Forced TSCTR"
|
|
newline
|
|
bitfld.word 0x00 6.--7. " SYNCO_SEL ,Sync-out select" "Sync-in event,CTR = PRD event,Disabled,Disabled"
|
|
bitfld.word 0x00 5. " SYNCI_EN ,Counter sync-in select mode" "Disabled,Enabled"
|
|
bitfld.word 0x00 4. " TSCTRSTOP ,Time stamp counter stop control" "Stopped,Free-running"
|
|
newline
|
|
bitfld.word 0x00 3. " REARM ,One-shot re-arming control" "No effect,Enabled"
|
|
bitfld.word 0x00 1.--2. " STOP_WRAP ,Stop value for one-shot mode" "Event 1,Event 2,Event 3,Event 4"
|
|
bitfld.word 0x00 0. " CONT_ONESHT ,Continuous or one-shot mode control" "Continuous,One-shot"
|
|
line.word 0x02 "ECCTL1,ECAP Control Register 1"
|
|
bitfld.word 0x02 14.--15. " FREE_SOFT ,Emulation control effect on TSCTR counter" "Stopped,Run,Unaffected,Unaffected"
|
|
bitfld.word 0x02 9.--13. " PRESCALE ,Event filter prescale select" "No prescale,/2,/4,/6,/8,/10,/12,/14,/16,/18,/20,/22,/24,/26,/28,/30,/32,/34,/36,/38,/40,/42,/44,/46,/48,/50,/52,/54,/56,/58,/60,/62"
|
|
bitfld.word 0x02 8. " CAPLDEN ,Enable loading of CAP1-4 registers on a capture event" "Disabled,Enabled"
|
|
newline
|
|
bitfld.word 0x02 7. " CTRRST4 ,Counter reset on capture event 4" "No reset,Reset"
|
|
bitfld.word 0x02 6. " CAP4POL ,Capture event 4 polarity select" "Rising edge,Falling edge"
|
|
bitfld.word 0x02 5. " CTRRST3 ,Counter reset on capture event 3" "No reset,Reset"
|
|
newline
|
|
bitfld.word 0x02 4. " CAP3POL ,Capture event 3 polarity select" "Rising edge,Falling edge"
|
|
bitfld.word 0x02 3. " CTRRST2 ,Counter reset on capture event 2" "No reset,Reset"
|
|
bitfld.word 0x02 2. " CAP2POL ,Capture event 2 polarity select" "Rising edge,Falling edge"
|
|
newline
|
|
bitfld.word 0x02 1. " CTRRST1 ,Counter reset on capture event 1" "No reset,Reset"
|
|
bitfld.word 0x02 0. " CAP1POL ,Capture event 1 polarity select" "Rising edge,Falling edge"
|
|
rgroup.word 0x2C++0x01
|
|
line.word 0x00 "ECFLG,ECAP Flag Register"
|
|
bitfld.word 0x00 7. " CTR_CMP ,Counter compare equal status flag" "No event,Triggered"
|
|
bitfld.word 0x00 6. " CTR_PRD ,Counter equal period status flag" "No event,Triggered"
|
|
bitfld.word 0x00 5. " CTROVF ,Counter overflow status flag" "No event,Triggered"
|
|
newline
|
|
bitfld.word 0x00 4. " CEVT4 ,Capture event 4 status flag" "No event,Triggered"
|
|
bitfld.word 0x00 3. " CEVT3 ,Capture event 3 status flag" "No event,Triggered"
|
|
bitfld.word 0x00 2. " CEVT2 ,Capture event 2 status flag" "No event,Triggered"
|
|
newline
|
|
bitfld.word 0x00 1. " CEVT1 ,Capture event 1 status flag" "No event,Triggered"
|
|
bitfld.word 0x00 0. " INT ,Global interrupt status flag" "No event,Triggered"
|
|
group.word 0x2E++0x01
|
|
line.word 0x00 "ECEINT,ECAP Interrupt Enable Register"
|
|
bitfld.word 0x00 7. " CTR_CMP ,Counter equal compare interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 6. " CTR_PRD ,Counter equal period interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 5. " CTROVF ,Counter overflow interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.word 0x00 4. " CEVT4 ,Capture event 4 interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 3. " CEVT3 ,Capture event 3 interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.word 0x00 2. " CEVT2 ,Capture event 2 interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 1. " CEVT1 ,Capture event 1 interrupt enable" "Disabled,Enabled"
|
|
group.word 0x30++0x01
|
|
line.word 0x00 "ECFRC_SET/CLR,ECAP Force Counter Set/Clear Register"
|
|
setclrfld.word 0x00 7. 0x00 7. 0x02 7. " CTR_CMP ,Force counter equal compare interrupt" "No event,Forced"
|
|
setclrfld.word 0x00 6. 0x00 6. 0x02 6. " CTR_PRD ,Force counter equal period interrupt" "No event,Forced"
|
|
setclrfld.word 0x00 5. 0x00 5. 0x02 5. " CTROVF ,Force counter overflow interrupt" "No event,Forced"
|
|
newline
|
|
setclrfld.word 0x00 4. 0x00 4. 0x02 4. " CEVT4 ,Force capture event 4 interrupt" "No event,Forced"
|
|
setclrfld.word 0x00 3. 0x00 3. 0x02 3. " CEVT3 ,Force capture event 3 interrupt" "No event,Forced"
|
|
newline
|
|
setclrfld.word 0x00 2. 0x00 2. 0x02 2. " CEVT2 ,Force capture event 2 interrupt" "No event,Forced"
|
|
setclrfld.word 0x00 1. 0x00 1. 0x02 1. " CEVT1 ,Force capture event 1 interrupt" "No event,Forced"
|
|
endian.le
|
|
width 0x0B
|
|
tree.end
|
|
tree "ECAP4"
|
|
base ad:0xFCF79600
|
|
endian.be
|
|
width 15.
|
|
group.long 0x00++0x07
|
|
line.long 0x00 "TSCTR,Capture Time-Base Counter Register"
|
|
line.long 0x04 "CTRPHS,Counter Phase Value Register"
|
|
group.long 0x8++0x03
|
|
line.long 0x00 "CAP1,Capture register 1"
|
|
group.long 0xC++0x03
|
|
line.long 0x00 "CAP2,Capture register 2"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "CAP3,Capture register 3"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "CAP4,Capture register 4"
|
|
group.word 0x28++0x03
|
|
line.word 0x00 "ECCTL2,ECAP Control Register 2"
|
|
bitfld.word 0x00 10. " APWMPOL ,APWM output polarity select" "Active HIGH,Active LOW"
|
|
bitfld.word 0x00 9. " CAP_APWM ,CAP/APWM operating mode select" "Capture,APWM"
|
|
bitfld.word 0x00 8. " SWSYNC ,Software-focused counter synchronizing" "No effect,Forced TSCTR"
|
|
newline
|
|
bitfld.word 0x00 6.--7. " SYNCO_SEL ,Sync-out select" "Sync-in event,CTR = PRD event,Disabled,Disabled"
|
|
bitfld.word 0x00 5. " SYNCI_EN ,Counter sync-in select mode" "Disabled,Enabled"
|
|
bitfld.word 0x00 4. " TSCTRSTOP ,Time stamp counter stop control" "Stopped,Free-running"
|
|
newline
|
|
bitfld.word 0x00 3. " REARM ,One-shot re-arming control" "No effect,Enabled"
|
|
bitfld.word 0x00 1.--2. " STOP_WRAP ,Stop value for one-shot mode" "Event 1,Event 2,Event 3,Event 4"
|
|
bitfld.word 0x00 0. " CONT_ONESHT ,Continuous or one-shot mode control" "Continuous,One-shot"
|
|
line.word 0x02 "ECCTL1,ECAP Control Register 1"
|
|
bitfld.word 0x02 14.--15. " FREE_SOFT ,Emulation control effect on TSCTR counter" "Stopped,Run,Unaffected,Unaffected"
|
|
bitfld.word 0x02 9.--13. " PRESCALE ,Event filter prescale select" "No prescale,/2,/4,/6,/8,/10,/12,/14,/16,/18,/20,/22,/24,/26,/28,/30,/32,/34,/36,/38,/40,/42,/44,/46,/48,/50,/52,/54,/56,/58,/60,/62"
|
|
bitfld.word 0x02 8. " CAPLDEN ,Enable loading of CAP1-4 registers on a capture event" "Disabled,Enabled"
|
|
newline
|
|
bitfld.word 0x02 7. " CTRRST4 ,Counter reset on capture event 4" "No reset,Reset"
|
|
bitfld.word 0x02 6. " CAP4POL ,Capture event 4 polarity select" "Rising edge,Falling edge"
|
|
bitfld.word 0x02 5. " CTRRST3 ,Counter reset on capture event 3" "No reset,Reset"
|
|
newline
|
|
bitfld.word 0x02 4. " CAP3POL ,Capture event 3 polarity select" "Rising edge,Falling edge"
|
|
bitfld.word 0x02 3. " CTRRST2 ,Counter reset on capture event 2" "No reset,Reset"
|
|
bitfld.word 0x02 2. " CAP2POL ,Capture event 2 polarity select" "Rising edge,Falling edge"
|
|
newline
|
|
bitfld.word 0x02 1. " CTRRST1 ,Counter reset on capture event 1" "No reset,Reset"
|
|
bitfld.word 0x02 0. " CAP1POL ,Capture event 1 polarity select" "Rising edge,Falling edge"
|
|
rgroup.word 0x2C++0x01
|
|
line.word 0x00 "ECFLG,ECAP Flag Register"
|
|
bitfld.word 0x00 7. " CTR_CMP ,Counter compare equal status flag" "No event,Triggered"
|
|
bitfld.word 0x00 6. " CTR_PRD ,Counter equal period status flag" "No event,Triggered"
|
|
bitfld.word 0x00 5. " CTROVF ,Counter overflow status flag" "No event,Triggered"
|
|
newline
|
|
bitfld.word 0x00 4. " CEVT4 ,Capture event 4 status flag" "No event,Triggered"
|
|
bitfld.word 0x00 3. " CEVT3 ,Capture event 3 status flag" "No event,Triggered"
|
|
bitfld.word 0x00 2. " CEVT2 ,Capture event 2 status flag" "No event,Triggered"
|
|
newline
|
|
bitfld.word 0x00 1. " CEVT1 ,Capture event 1 status flag" "No event,Triggered"
|
|
bitfld.word 0x00 0. " INT ,Global interrupt status flag" "No event,Triggered"
|
|
group.word 0x2E++0x01
|
|
line.word 0x00 "ECEINT,ECAP Interrupt Enable Register"
|
|
bitfld.word 0x00 7. " CTR_CMP ,Counter equal compare interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 6. " CTR_PRD ,Counter equal period interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 5. " CTROVF ,Counter overflow interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.word 0x00 4. " CEVT4 ,Capture event 4 interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 3. " CEVT3 ,Capture event 3 interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.word 0x00 2. " CEVT2 ,Capture event 2 interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 1. " CEVT1 ,Capture event 1 interrupt enable" "Disabled,Enabled"
|
|
group.word 0x30++0x01
|
|
line.word 0x00 "ECFRC_SET/CLR,ECAP Force Counter Set/Clear Register"
|
|
setclrfld.word 0x00 7. 0x00 7. 0x02 7. " CTR_CMP ,Force counter equal compare interrupt" "No event,Forced"
|
|
setclrfld.word 0x00 6. 0x00 6. 0x02 6. " CTR_PRD ,Force counter equal period interrupt" "No event,Forced"
|
|
setclrfld.word 0x00 5. 0x00 5. 0x02 5. " CTROVF ,Force counter overflow interrupt" "No event,Forced"
|
|
newline
|
|
setclrfld.word 0x00 4. 0x00 4. 0x02 4. " CEVT4 ,Force capture event 4 interrupt" "No event,Forced"
|
|
setclrfld.word 0x00 3. 0x00 3. 0x02 3. " CEVT3 ,Force capture event 3 interrupt" "No event,Forced"
|
|
newline
|
|
setclrfld.word 0x00 2. 0x00 2. 0x02 2. " CEVT2 ,Force capture event 2 interrupt" "No event,Forced"
|
|
setclrfld.word 0x00 1. 0x00 1. 0x02 1. " CEVT1 ,Force capture event 1 interrupt" "No event,Forced"
|
|
endian.le
|
|
width 0x0B
|
|
tree.end
|
|
tree "ECAP5"
|
|
base ad:0xFCF79700
|
|
endian.be
|
|
width 15.
|
|
group.long 0x00++0x07
|
|
line.long 0x00 "TSCTR,Capture Time-Base Counter Register"
|
|
line.long 0x04 "CTRPHS,Counter Phase Value Register"
|
|
group.long 0x8++0x03
|
|
line.long 0x00 "CAP1,Capture register 1"
|
|
group.long 0xC++0x03
|
|
line.long 0x00 "CAP2,Capture register 2"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "CAP3,Capture register 3"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "CAP4,Capture register 4"
|
|
group.word 0x28++0x03
|
|
line.word 0x00 "ECCTL2,ECAP Control Register 2"
|
|
bitfld.word 0x00 10. " APWMPOL ,APWM output polarity select" "Active HIGH,Active LOW"
|
|
bitfld.word 0x00 9. " CAP_APWM ,CAP/APWM operating mode select" "Capture,APWM"
|
|
bitfld.word 0x00 8. " SWSYNC ,Software-focused counter synchronizing" "No effect,Forced TSCTR"
|
|
newline
|
|
bitfld.word 0x00 6.--7. " SYNCO_SEL ,Sync-out select" "Sync-in event,CTR = PRD event,Disabled,Disabled"
|
|
bitfld.word 0x00 5. " SYNCI_EN ,Counter sync-in select mode" "Disabled,Enabled"
|
|
bitfld.word 0x00 4. " TSCTRSTOP ,Time stamp counter stop control" "Stopped,Free-running"
|
|
newline
|
|
bitfld.word 0x00 3. " REARM ,One-shot re-arming control" "No effect,Enabled"
|
|
bitfld.word 0x00 1.--2. " STOP_WRAP ,Stop value for one-shot mode" "Event 1,Event 2,Event 3,Event 4"
|
|
bitfld.word 0x00 0. " CONT_ONESHT ,Continuous or one-shot mode control" "Continuous,One-shot"
|
|
line.word 0x02 "ECCTL1,ECAP Control Register 1"
|
|
bitfld.word 0x02 14.--15. " FREE_SOFT ,Emulation control effect on TSCTR counter" "Stopped,Run,Unaffected,Unaffected"
|
|
bitfld.word 0x02 9.--13. " PRESCALE ,Event filter prescale select" "No prescale,/2,/4,/6,/8,/10,/12,/14,/16,/18,/20,/22,/24,/26,/28,/30,/32,/34,/36,/38,/40,/42,/44,/46,/48,/50,/52,/54,/56,/58,/60,/62"
|
|
bitfld.word 0x02 8. " CAPLDEN ,Enable loading of CAP1-4 registers on a capture event" "Disabled,Enabled"
|
|
newline
|
|
bitfld.word 0x02 7. " CTRRST4 ,Counter reset on capture event 4" "No reset,Reset"
|
|
bitfld.word 0x02 6. " CAP4POL ,Capture event 4 polarity select" "Rising edge,Falling edge"
|
|
bitfld.word 0x02 5. " CTRRST3 ,Counter reset on capture event 3" "No reset,Reset"
|
|
newline
|
|
bitfld.word 0x02 4. " CAP3POL ,Capture event 3 polarity select" "Rising edge,Falling edge"
|
|
bitfld.word 0x02 3. " CTRRST2 ,Counter reset on capture event 2" "No reset,Reset"
|
|
bitfld.word 0x02 2. " CAP2POL ,Capture event 2 polarity select" "Rising edge,Falling edge"
|
|
newline
|
|
bitfld.word 0x02 1. " CTRRST1 ,Counter reset on capture event 1" "No reset,Reset"
|
|
bitfld.word 0x02 0. " CAP1POL ,Capture event 1 polarity select" "Rising edge,Falling edge"
|
|
rgroup.word 0x2C++0x01
|
|
line.word 0x00 "ECFLG,ECAP Flag Register"
|
|
bitfld.word 0x00 7. " CTR_CMP ,Counter compare equal status flag" "No event,Triggered"
|
|
bitfld.word 0x00 6. " CTR_PRD ,Counter equal period status flag" "No event,Triggered"
|
|
bitfld.word 0x00 5. " CTROVF ,Counter overflow status flag" "No event,Triggered"
|
|
newline
|
|
bitfld.word 0x00 4. " CEVT4 ,Capture event 4 status flag" "No event,Triggered"
|
|
bitfld.word 0x00 3. " CEVT3 ,Capture event 3 status flag" "No event,Triggered"
|
|
bitfld.word 0x00 2. " CEVT2 ,Capture event 2 status flag" "No event,Triggered"
|
|
newline
|
|
bitfld.word 0x00 1. " CEVT1 ,Capture event 1 status flag" "No event,Triggered"
|
|
bitfld.word 0x00 0. " INT ,Global interrupt status flag" "No event,Triggered"
|
|
group.word 0x2E++0x01
|
|
line.word 0x00 "ECEINT,ECAP Interrupt Enable Register"
|
|
bitfld.word 0x00 7. " CTR_CMP ,Counter equal compare interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 6. " CTR_PRD ,Counter equal period interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 5. " CTROVF ,Counter overflow interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.word 0x00 4. " CEVT4 ,Capture event 4 interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 3. " CEVT3 ,Capture event 3 interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.word 0x00 2. " CEVT2 ,Capture event 2 interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 1. " CEVT1 ,Capture event 1 interrupt enable" "Disabled,Enabled"
|
|
group.word 0x30++0x01
|
|
line.word 0x00 "ECFRC_SET/CLR,ECAP Force Counter Set/Clear Register"
|
|
setclrfld.word 0x00 7. 0x00 7. 0x02 7. " CTR_CMP ,Force counter equal compare interrupt" "No event,Forced"
|
|
setclrfld.word 0x00 6. 0x00 6. 0x02 6. " CTR_PRD ,Force counter equal period interrupt" "No event,Forced"
|
|
setclrfld.word 0x00 5. 0x00 5. 0x02 5. " CTROVF ,Force counter overflow interrupt" "No event,Forced"
|
|
newline
|
|
setclrfld.word 0x00 4. 0x00 4. 0x02 4. " CEVT4 ,Force capture event 4 interrupt" "No event,Forced"
|
|
setclrfld.word 0x00 3. 0x00 3. 0x02 3. " CEVT3 ,Force capture event 3 interrupt" "No event,Forced"
|
|
newline
|
|
setclrfld.word 0x00 2. 0x00 2. 0x02 2. " CEVT2 ,Force capture event 2 interrupt" "No event,Forced"
|
|
setclrfld.word 0x00 1. 0x00 1. 0x02 1. " CEVT1 ,Force capture event 1 interrupt" "No event,Forced"
|
|
endian.le
|
|
width 0x0B
|
|
tree.end
|
|
tree "ECAP6"
|
|
base ad:0xFCF79800
|
|
endian.be
|
|
width 15.
|
|
group.long 0x00++0x07
|
|
line.long 0x00 "TSCTR,Capture Time-Base Counter Register"
|
|
line.long 0x04 "CTRPHS,Counter Phase Value Register"
|
|
group.long 0x8++0x03
|
|
line.long 0x00 "CAP1,Capture register 1"
|
|
group.long 0xC++0x03
|
|
line.long 0x00 "CAP2,Capture register 2"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "CAP3,Capture register 3"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "CAP4,Capture register 4"
|
|
group.word 0x28++0x03
|
|
line.word 0x00 "ECCTL2,ECAP Control Register 2"
|
|
bitfld.word 0x00 10. " APWMPOL ,APWM output polarity select" "Active HIGH,Active LOW"
|
|
bitfld.word 0x00 9. " CAP_APWM ,CAP/APWM operating mode select" "Capture,APWM"
|
|
bitfld.word 0x00 8. " SWSYNC ,Software-focused counter synchronizing" "No effect,Forced TSCTR"
|
|
newline
|
|
bitfld.word 0x00 6.--7. " SYNCO_SEL ,Sync-out select" "Sync-in event,CTR = PRD event,Disabled,Disabled"
|
|
bitfld.word 0x00 5. " SYNCI_EN ,Counter sync-in select mode" "Disabled,Enabled"
|
|
bitfld.word 0x00 4. " TSCTRSTOP ,Time stamp counter stop control" "Stopped,Free-running"
|
|
newline
|
|
bitfld.word 0x00 3. " REARM ,One-shot re-arming control" "No effect,Enabled"
|
|
bitfld.word 0x00 1.--2. " STOP_WRAP ,Stop value for one-shot mode" "Event 1,Event 2,Event 3,Event 4"
|
|
bitfld.word 0x00 0. " CONT_ONESHT ,Continuous or one-shot mode control" "Continuous,One-shot"
|
|
line.word 0x02 "ECCTL1,ECAP Control Register 1"
|
|
bitfld.word 0x02 14.--15. " FREE_SOFT ,Emulation control effect on TSCTR counter" "Stopped,Run,Unaffected,Unaffected"
|
|
bitfld.word 0x02 9.--13. " PRESCALE ,Event filter prescale select" "No prescale,/2,/4,/6,/8,/10,/12,/14,/16,/18,/20,/22,/24,/26,/28,/30,/32,/34,/36,/38,/40,/42,/44,/46,/48,/50,/52,/54,/56,/58,/60,/62"
|
|
bitfld.word 0x02 8. " CAPLDEN ,Enable loading of CAP1-4 registers on a capture event" "Disabled,Enabled"
|
|
newline
|
|
bitfld.word 0x02 7. " CTRRST4 ,Counter reset on capture event 4" "No reset,Reset"
|
|
bitfld.word 0x02 6. " CAP4POL ,Capture event 4 polarity select" "Rising edge,Falling edge"
|
|
bitfld.word 0x02 5. " CTRRST3 ,Counter reset on capture event 3" "No reset,Reset"
|
|
newline
|
|
bitfld.word 0x02 4. " CAP3POL ,Capture event 3 polarity select" "Rising edge,Falling edge"
|
|
bitfld.word 0x02 3. " CTRRST2 ,Counter reset on capture event 2" "No reset,Reset"
|
|
bitfld.word 0x02 2. " CAP2POL ,Capture event 2 polarity select" "Rising edge,Falling edge"
|
|
newline
|
|
bitfld.word 0x02 1. " CTRRST1 ,Counter reset on capture event 1" "No reset,Reset"
|
|
bitfld.word 0x02 0. " CAP1POL ,Capture event 1 polarity select" "Rising edge,Falling edge"
|
|
rgroup.word 0x2C++0x01
|
|
line.word 0x00 "ECFLG,ECAP Flag Register"
|
|
bitfld.word 0x00 7. " CTR_CMP ,Counter compare equal status flag" "No event,Triggered"
|
|
bitfld.word 0x00 6. " CTR_PRD ,Counter equal period status flag" "No event,Triggered"
|
|
bitfld.word 0x00 5. " CTROVF ,Counter overflow status flag" "No event,Triggered"
|
|
newline
|
|
bitfld.word 0x00 4. " CEVT4 ,Capture event 4 status flag" "No event,Triggered"
|
|
bitfld.word 0x00 3. " CEVT3 ,Capture event 3 status flag" "No event,Triggered"
|
|
bitfld.word 0x00 2. " CEVT2 ,Capture event 2 status flag" "No event,Triggered"
|
|
newline
|
|
bitfld.word 0x00 1. " CEVT1 ,Capture event 1 status flag" "No event,Triggered"
|
|
bitfld.word 0x00 0. " INT ,Global interrupt status flag" "No event,Triggered"
|
|
group.word 0x2E++0x01
|
|
line.word 0x00 "ECEINT,ECAP Interrupt Enable Register"
|
|
bitfld.word 0x00 7. " CTR_CMP ,Counter equal compare interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 6. " CTR_PRD ,Counter equal period interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 5. " CTROVF ,Counter overflow interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.word 0x00 4. " CEVT4 ,Capture event 4 interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 3. " CEVT3 ,Capture event 3 interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.word 0x00 2. " CEVT2 ,Capture event 2 interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 1. " CEVT1 ,Capture event 1 interrupt enable" "Disabled,Enabled"
|
|
group.word 0x30++0x01
|
|
line.word 0x00 "ECFRC_SET/CLR,ECAP Force Counter Set/Clear Register"
|
|
setclrfld.word 0x00 7. 0x00 7. 0x02 7. " CTR_CMP ,Force counter equal compare interrupt" "No event,Forced"
|
|
setclrfld.word 0x00 6. 0x00 6. 0x02 6. " CTR_PRD ,Force counter equal period interrupt" "No event,Forced"
|
|
setclrfld.word 0x00 5. 0x00 5. 0x02 5. " CTROVF ,Force counter overflow interrupt" "No event,Forced"
|
|
newline
|
|
setclrfld.word 0x00 4. 0x00 4. 0x02 4. " CEVT4 ,Force capture event 4 interrupt" "No event,Forced"
|
|
setclrfld.word 0x00 3. 0x00 3. 0x02 3. " CEVT3 ,Force capture event 3 interrupt" "No event,Forced"
|
|
newline
|
|
setclrfld.word 0x00 2. 0x00 2. 0x02 2. " CEVT2 ,Force capture event 2 interrupt" "No event,Forced"
|
|
setclrfld.word 0x00 1. 0x00 1. 0x02 1. " CEVT1 ,Force capture event 1 interrupt" "No event,Forced"
|
|
endian.le
|
|
width 0x0B
|
|
tree.end
|
|
tree.end
|
|
endif
|
|
tree "eQEP (Enhanced QEP Module)"
|
|
base ad:0xFFF79900
|
|
sif cpuis("TMS570LS0232")||cpuis("TMS570LS0714*")||cpuis("TMS570LS0914*")
|
|
endian.be
|
|
endif
|
|
width 10.
|
|
group.long 0x00++0x0F
|
|
line.long 0x00 "QPOSCNT,EQEP Position Counter Register"
|
|
line.long 0x04 "QPOSINIT,EQEP Position Counter Initialization Register"
|
|
line.long 0x08 "QPOSMAX,EQEP Maximum Position Count Register"
|
|
line.long 0x0C "QPOSCMP,EQEP Position-Compare Register"
|
|
rgroup.long 0x10++0x0B
|
|
line.long 0x00 "QPOSILAT,EQEP Index Position Latch Register"
|
|
line.long 0x04 "QPOSSLAT,EQEP Strobe Position Latch Register"
|
|
line.long 0x08 "QPOSLAT,EQEP Position Counter Latch Register"
|
|
group.long 0x1C++0x07
|
|
line.long 0x00 "QUTMR,EQEP Unit Timer Register"
|
|
line.long 0x04 "QUPRD,EQEP Register Unit Period Register"
|
|
newline
|
|
group.word 0x24++0x03
|
|
line.word 0x00 "QWDPRD,EQEP Watchdog Period Register"
|
|
line.word 0x02 "QWDTMR,EQEP Watchdog Timer Register"
|
|
sif cpu()=="RM57L843-ZWT"
|
|
group.word 0x28++0x07
|
|
line.word 0x00 "QDECCTL,EQEP Decoder Control Register"
|
|
bitfld.word 0x00 14.--15. " QSRC ,Position-counter source selection" "Quadrature count,Direction-count,UP count,DOWN count"
|
|
bitfld.word 0x00 13. " SOEN ,Sync output-enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.word 0x00 12. " SPSEL ,Sync output pin selection" "Index pin,Strobe pin"
|
|
bitfld.word 0x00 11. " XCR ,External clock rate" "2x resolution,1x resolution"
|
|
newline
|
|
bitfld.word 0x00 10. " SWAP ,Swap quadrature clock inputs" "Not swapped,Swapped"
|
|
bitfld.word 0x00 9. " IGATE ,Index pulse gating option" "Disable gating of index pulse,Gate the index pin with strobe"
|
|
newline
|
|
bitfld.word 0x00 8. " QAP ,QEPA input polarity" "No effect,Negates QEPA"
|
|
bitfld.word 0x00 7. " QBP ,QEPB input polarity" "No effect,Negates QEPB"
|
|
newline
|
|
bitfld.word 0x00 6. " QIP ,QEPI input polarity" "No effect,Negates QEPI"
|
|
bitfld.word 0x00 5. " QSP ,QEPS input polarity" "No effect,Negates QEPS"
|
|
line.word 0x02 "QEPCTL,EQEP Control Register"
|
|
bitfld.word 0x02 14.--15. " FREE/SOFT ,Emulation control bits" "Stopped,Continued,Unaffected,Unaffected"
|
|
bitfld.word 0x02 12.--13. " PCRM ,Position counter reset mode" "Index event,Maximum position,First index event,Unit time event"
|
|
newline
|
|
bitfld.word 0x02 10.--11. " SEI ,Strobe event initialization of position counter" "Disabled,Disabled,Rising edge,Clockwise direction"
|
|
bitfld.word 0x02 8.--9. " IEI ,Index event initialization of position counter" "Disabled,Disabled,Rising edge,Falling edge"
|
|
newline
|
|
bitfld.word 0x02 7. " SWI ,Software initialization of position counter" "Disabled,Enabled"
|
|
bitfld.word 0x02 6. " SEL ,Strobe event latch of position counter" "Rising edge,Rising/faling edge"
|
|
newline
|
|
bitfld.word 0x02 4.--5. " IEL ,Index event latch of position counter" ",Rising edge,Faling edge,Software index marker"
|
|
bitfld.word 0x02 3. " QPEN ,Quadrature position counter enable/software reset" "Reset,Enabled"
|
|
newline
|
|
bitfld.word 0x02 2. " QCLM ,EQEP capture latch mode" "Position counter read by CPU,Unit time out"
|
|
bitfld.word 0x02 1. " UTE ,EQEP unit timer enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.word 0x02 0. " WDE ,EQEP watchdog enable" "Disabled,Enabled"
|
|
line.word 0x04 "QCAPCTL,EQEP Capture Control Register"
|
|
bitfld.word 0x04 15. " CEN ,Enable EQEP capture" "Disabled,Enabled"
|
|
bitfld.word 0x04 4.--6. " CCPS ,EQEP capture timer clock prescaler" "VCLK/1,VCLK/2,VCLK/4,VCLK/8,VCLK/16,VCLK/32,VCLK/64,VCLK/128"
|
|
newline
|
|
bitfld.word 0x04 0.--3. " UPPS ,Unit position event prescaler" "QCLK/1,QCLK/2,QCLK/4,QCLK/8,QCLK/16,QCLK/32,QCLK/64,QCLK/128,QCLK/256,QCLK/512,QCLK/1024,QCLK/2048,?..."
|
|
line.word 0x06 "QPOSCTL,EQEP Position-Compare Control Register"
|
|
bitfld.word 0x06 15. " PCSHDW ,Position-compare shadow enable" "Disabled,Enabled"
|
|
bitfld.word 0x06 14. " PCLOAD ,Position-compare shadow load mode" "QPOSCNT = 0,QPOSCNT = QPOSCMP"
|
|
newline
|
|
bitfld.word 0x06 13. " PCPOL ,Polarity of sync output" "High,Low"
|
|
bitfld.word 0x06 12. " PCE ,Position-compare enable/disable" "Disabled,Enabled"
|
|
newline
|
|
hexmask.word 0x06 0.--11. 1. " PCSPW ,Select-position-compare sync output pulse width"
|
|
else
|
|
group.word 0x28++0x07
|
|
line.word 0x00 "QEPCTL,EQEP Control Register"
|
|
bitfld.word 0x00 14.--15. " FREE/SOFT ,Emulation control bits" "Stopped,Continued,Unaffected,Unaffected"
|
|
bitfld.word 0x00 12.--13. " PCRM ,Position counter reset mode" "Index event,Maximum position,First index event,Unit time event"
|
|
newline
|
|
bitfld.word 0x00 10.--11. " SEI ,Strobe event initialization of position counter" "Disabled,Disabled,Rising edge,Clockwise direction"
|
|
bitfld.word 0x00 8.--9. " IEI ,Index event initialization of position counter" "Disabled,Disabled,Rising edge,Falling edge"
|
|
newline
|
|
bitfld.word 0x00 7. " SWI ,Software initialization of position counter" "Disabled,Enabled"
|
|
bitfld.word 0x00 6. " SEL ,Strobe event latch of position counter" "Rising edge,Falling edge"
|
|
newline
|
|
bitfld.word 0x00 4.--5. " IEL ,Index event latch of position counter" ",Rising edge,Falling edge,Software index marker"
|
|
bitfld.word 0x00 3. " QPEN ,Quadrature position counter enable/software reset" "Reset,Enabled"
|
|
newline
|
|
bitfld.word 0x00 2. " QCLM ,EQEP capture latch mode" "Read by CPU,Unit time out"
|
|
bitfld.word 0x00 1. " UTE ,EQEP unit timer enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.word 0x00 0. " WDE ,EQEP watchdog enable" "Disabled,Enabled"
|
|
line.word 0x02 "QDECCTL,EQEP Decoder Control Register"
|
|
bitfld.word 0x02 14.--15. " QSRC ,Position-counter source selection" "Quadrature,Direction,UP,DOWN"
|
|
bitfld.word 0x02 13. " SOEN ,Sync output-enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.word 0x02 12. " SPSEL ,Sync output pin selection" "Index,Strobe"
|
|
bitfld.word 0x02 11. " XCR ,External clock rate" "2x resolution,1x resolution"
|
|
newline
|
|
bitfld.word 0x02 10. " SWAP ,Swap quadrature clock inputs" "Not swapped,Swapped"
|
|
bitfld.word 0x02 9. " IGATE ,Index pulse gating option enable" "Disable,Enabled"
|
|
newline
|
|
bitfld.word 0x02 8. " QAP ,QEPA input polarity" "No effect,Negates QEPA"
|
|
bitfld.word 0x02 7. " QBP ,QEPB input polarity" "No effect,Negates QEPB"
|
|
newline
|
|
bitfld.word 0x02 6. " QIP ,QEPI input polarity" "No effect,Negates QEPI"
|
|
bitfld.word 0x02 5. " QSP ,QEPS input polarity" "No effect,Negates QEPS"
|
|
line.word 0x04 "QPOSCTL,EQEP Position-Compare Control Register"
|
|
bitfld.word 0x04 15. " PCSHDW ,Position-compare shadow enable" "Disabled,Enabled"
|
|
bitfld.word 0x04 14. " PCLOAD ,Position-compare shadow load mode" "QPOSCNT = 0,QPOSCNT = QPOSCMP"
|
|
newline
|
|
bitfld.word 0x04 13. " PCPOL ,Polarity of sync output" "High,Low"
|
|
bitfld.word 0x04 12. " PCE ,Position-compare enable/disable" "Disabled,Enabled"
|
|
newline
|
|
hexmask.word 0x04 0.--11. 1. " PCSPW ,Select-position-compare sync output pulse width"
|
|
line.word 0x06 "QCAPCTL,EQEP Capture Control Register"
|
|
bitfld.word 0x06 15. " CEN ,Enable EQEP capture" "Disabled,Enabled"
|
|
bitfld.word 0x06 4.--6. " CCPS ,EQEP capture timer clock prescaler" "VCLK/1,VCLK/2,VCLK/4,VCLK/8,VCLK/16,VCLK/32,VCLK/64,VCLK/128"
|
|
newline
|
|
bitfld.word 0x06 0.--3. " UPPS ,Unit position event prescaler" "QCLK/1,QCLK/2,QCLK/4,QCLK/8,QCLK/16,QCLK/32,QCLK/64,QCLK/128,QCLK/256,QCLK/512,QCLK/1024,QCLK/2048,?..."
|
|
endif
|
|
newline
|
|
sif cpu()=="RM57L843-ZWT"
|
|
rgroup.word 0x32++0x01
|
|
line.word 0x00 "QFLG,EQEP Interrupt Flag Register"
|
|
bitfld.word 0x00 11. " UTO ,Unit time out interrupt" "Not generated,Generated"
|
|
bitfld.word 0x00 10. " IEL ,Index event latch interrupt" "Not generated,Generated"
|
|
bitfld.word 0x00 9. " SEL ,Strobe event latch interrupt" "Not generated,Generated"
|
|
bitfld.word 0x00 8. " PCM ,Position-compare match interrupt" "Not generated,Generated"
|
|
newline
|
|
bitfld.word 0x00 7. " PCR ,Position-compare ready interrupt" "Not generated,Generated"
|
|
bitfld.word 0x00 6. " PCO ,Position counter overflow interrupt" "Not generated,Generated"
|
|
bitfld.word 0x00 5. " PCU ,Position counter underflow interrupt" "Not generated,Generated"
|
|
bitfld.word 0x00 4. " WTO ,Watchdog time out interrupt" "Not generated,Generated"
|
|
newline
|
|
bitfld.word 0x00 3. " QDC ,Quadrature direction change interrupt" "Not generated,Generated"
|
|
bitfld.word 0x00 2. " PHE ,Quadrature phase error interrupt" "Not generated,Generated"
|
|
bitfld.word 0x00 1. " PCE ,Position counter error interrupt" "Not generated,Generated"
|
|
bitfld.word 0x00 0. " INT ,Global interrupt status flag" "Not generated,Generated"
|
|
group.word 0x30++0x01
|
|
line.word 0x00 "QEINT,EQEP Interrupt Enable Register"
|
|
bitfld.word 0x00 11. " UTO ,Unit time out interrupt enable" "Disabled,Enable"
|
|
bitfld.word 0x00 10. " IEL ,Index event latch interrupt enable" "Disabled,Enable"
|
|
bitfld.word 0x00 9. " SEL ,Strobe event latch interrupt enable" "Disabled,Enable"
|
|
bitfld.word 0x00 8. " PCM ,Position-compare match interrupt enable" "Disabled,Enable"
|
|
newline
|
|
bitfld.word 0x00 7. " PCR ,Position-compare ready interrupt enable" "Disabled,Enable"
|
|
bitfld.word 0x00 6. " PCO ,Position counter overflow interrupt enable" "Disabled,Enable"
|
|
bitfld.word 0x00 5. " PCU ,Position counter underflow interrupt enable" "Disabled,Enable"
|
|
bitfld.word 0x00 4. " WTO ,Watchdog time out interrupt enable" "Disabled,Enable"
|
|
newline
|
|
bitfld.word 0x00 3. " QDC ,Quadrature direction change interrupt enable" "Disabled,Enable"
|
|
bitfld.word 0x00 2. " QPE ,Quadrature phase error interrupt enable" "Disabled,Enable"
|
|
bitfld.word 0x00 1. " PCE ,Position counter error interrupt enable" "Disabled,Enable"
|
|
group.word 0x36++0x01
|
|
line.word 0x00 "QFRC,EQEP Interrupt Force Register"
|
|
bitfld.word 0x00 11. " UTO ,Force unit time out interrupt" "No effect,Forced"
|
|
bitfld.word 0x00 10. " IEL ,Force index event latch interrupt" "No effect,Forced"
|
|
bitfld.word 0x00 9. " SEL ,Force strobe event latch interrupt" "No effect,Forced"
|
|
bitfld.word 0x00 8. " PCM ,Force position-compare match interrupt" "No effect,Forced"
|
|
newline
|
|
bitfld.word 0x00 7. " PCR ,Force position-compare ready interrupt" "No effect,Forced"
|
|
bitfld.word 0x00 6. " PCO ,Force position counter overflow interrupt" "No effect,Forced"
|
|
bitfld.word 0x00 5. " PCU ,Force position counter underflow interrupt" "No effect,Forced"
|
|
bitfld.word 0x00 4. " WTO ,Force watchdog time out interrupt" "No effect,Forced"
|
|
newline
|
|
bitfld.word 0x00 3. " QDC ,Force quadrature direction change interrupt" "No effect,Forced"
|
|
bitfld.word 0x00 2. " PHE ,Force quadrature phase error interrupt" "No effect,Forced"
|
|
bitfld.word 0x00 1. " PCE ,Force position counter error interrupt" "No effect,Forced"
|
|
group.word 0x34++0x01
|
|
line.word 0x00 "QCLR,EQEP Interrupt Clear Register"
|
|
bitfld.word 0x00 11. " UTO ,Clear unit time out interrupt flag" "No effect,Clears flag"
|
|
bitfld.word 0x00 10. " IEL ,Clear index event latch interrupt flag" "No effect,Clears flag"
|
|
bitfld.word 0x00 9. " SEL ,Clear strobe event latch interrupt flag" "No effect,Clears flag"
|
|
bitfld.word 0x00 8. " PCM ,Clear EQEP compare match event interrupt flag" "No effect,Clears flag"
|
|
newline
|
|
bitfld.word 0x00 7. " PCR ,Clear position-compare ready interrupt flag" "No effect,Clears flag"
|
|
bitfld.word 0x00 6. " PCO ,Clear position counter overflow interrupt flag" "No effect,Clears flag"
|
|
bitfld.word 0x00 5. " PCU ,Clear position counter underflow interrupt flag" "No effect,Clears flag"
|
|
bitfld.word 0x00 4. " WTO ,Clear watchdog timeout interrupt flag" "No effect,Clears flag"
|
|
newline
|
|
bitfld.word 0x00 3. " QDC ,Clear quadrature direction change interrupt flag" "No effect,Clears flag"
|
|
bitfld.word 0x00 2. " PHE ,Clear quadrature phase error interrupt flag" "No effect,Clears flag"
|
|
bitfld.word 0x00 1. " PCE ,Clear position counter error interrupt flag" "No effect,Clears flag"
|
|
bitfld.word 0x00 0. " INT ,Global interrupt clear flag" "No effect,Clears flag"
|
|
group.word 0x3A++0x01
|
|
line.word 0x00 "QCTMR,EQEP Capture Timer Register"
|
|
group.word 0x38++0x01
|
|
line.word 0x00 "QEPSTS,EQEP Status Register"
|
|
eventfld.word 0x00 7. " UPEVNT ,Unit position event flag" "Not detected,Detected"
|
|
rbitfld.word 0x00 6. " FIDF ,Direction on the first index marker" "Counter-clockwise rotation,Clockwise rotation"
|
|
newline
|
|
rbitfld.word 0x00 5. " QDF ,Quadrature direction flag" "Counter-clockwise rotation,Clockwise rotation"
|
|
rbitfld.word 0x00 4. " QDLF ,EQEP direction latch flag" "Counter-clockwise rotation,Clockwise rotation"
|
|
newline
|
|
eventfld.word 0x00 3. " COEF ,Capture overflow error flag" "Not occurred,Occurred"
|
|
eventfld.word 0x00 2. " CDEF ,Capture direction error flag" "Not occurred,Occurred"
|
|
newline
|
|
eventfld.word 0x00 1. " FIMF ,First index marker flag" "Not occurred,Occurred"
|
|
rbitfld.word 0x00 0. " PCEF ,Position counter error flag" "No error,Error"
|
|
rgroup.word 0x3E++0x01
|
|
line.word 0x00 "QCTMRLAT,EQEP Capture Timer Latch Register"
|
|
group.word 0x3C++0x03
|
|
line.word 0x00 "QCPRD,EQEP Capture Period Register"
|
|
line.word 0x02 "QCPRDLAT,EQEP Capture Period Latch Register"
|
|
else
|
|
rgroup.word 0x30++0x01
|
|
line.word 0x00 "QFLG,EQEP Interrupt Flag Register"
|
|
bitfld.word 0x00 11. " UTO ,Unit time out interrupt" "Not generated,Generated"
|
|
bitfld.word 0x00 10. " IEL ,Index event latch interrupt" "Not generated,Generated"
|
|
bitfld.word 0x00 9. " SEL ,Strobe event latch interrupt" "Not generated,Generated"
|
|
bitfld.word 0x00 8. " PCM ,Position-compare match interrupt" "Not generated,Generated"
|
|
newline
|
|
bitfld.word 0x00 7. " PCR ,Position-compare ready interrupt" "Not generated,Generated"
|
|
bitfld.word 0x00 6. " PCO ,Position counter overflow interrupt" "Not generated,Generated"
|
|
bitfld.word 0x00 5. " PCU ,Position counter underflow interrupt" "Not generated,Generated"
|
|
bitfld.word 0x00 4. " WTO ,Watchdog time out interrupt" "Not generated,Generated"
|
|
newline
|
|
bitfld.word 0x00 3. " QDC ,Quadrature direction change interrupt" "Not generated,Generated"
|
|
bitfld.word 0x00 2. " PHE ,Quadrature phase error interrupt" "Not generated,Generated"
|
|
bitfld.word 0x00 1. " PCE ,Position counter error interrupt" "Not generated,Generated"
|
|
bitfld.word 0x00 0. " INT ,Global interrupt status flag" "Not generated,Generated"
|
|
group.word 0x32++0x0D
|
|
line.word 0x00 "QEINT,EQEP Interrupt Enable Register"
|
|
bitfld.word 0x00 11. " UTO ,Unit time out interrupt enable" "Disabled,Enable"
|
|
bitfld.word 0x00 10. " IEL ,Index event latch interrupt enable" "Disabled,Enable"
|
|
bitfld.word 0x00 9. " SEL ,Strobe event latch interrupt enable" "Disabled,Enable"
|
|
bitfld.word 0x00 8. " PCM ,Position-compare match interrupt enable" "Disabled,Enable"
|
|
newline
|
|
bitfld.word 0x00 7. " PCR ,Position-compare ready interrupt enable" "Disabled,Enable"
|
|
bitfld.word 0x00 6. " PCO ,Position counter overflow interrupt enable" "Disabled,Enable"
|
|
bitfld.word 0x00 5. " PCU ,Position counter underflow interrupt enable" "Disabled,Enable"
|
|
bitfld.word 0x00 4. " WTO ,Watchdog time out interrupt enable" "Disabled,Enable"
|
|
newline
|
|
bitfld.word 0x00 3. " QDC ,Quadrature direction change interrupt enable" "Disabled,Enable"
|
|
bitfld.word 0x00 2. " QPE ,Quadrature phase error interrupt enable" "Disabled,Enable"
|
|
bitfld.word 0x00 1. " PCE ,Position counter error interrupt enable" "Disabled,Enable"
|
|
line.word 0x02 "QFRC,EQEP Interrupt Force Register"
|
|
bitfld.word 0x02 11. " UTO ,Force unit time out interrupt" "No effect,Forced"
|
|
bitfld.word 0x02 10. " IEL ,Force index event latch interrupt" "No effect,Forced"
|
|
bitfld.word 0x02 9. " SEL ,Force strobe event latch interrupt" "No effect,Forced"
|
|
bitfld.word 0x02 8. " PCM ,Force position-compare match interrupt" "No effect,Forced"
|
|
newline
|
|
bitfld.word 0x02 7. " PCR ,Force position-compare ready interrupt" "No effect,Forced"
|
|
bitfld.word 0x02 6. " PCO ,Force position counter overflow interrupt" "No effect,Forced"
|
|
bitfld.word 0x02 5. " PCU ,Force position counter underflow interrupt" "No effect,Forced"
|
|
bitfld.word 0x02 4. " WTO ,Force watchdog time out interrupt" "No effect,Forced"
|
|
newline
|
|
bitfld.word 0x02 3. " QDC ,Force quadrature direction change interrupt" "No effect,Forced"
|
|
bitfld.word 0x02 2. " PHE ,Force quadrature phase error interrupt" "No effect,Forced"
|
|
bitfld.word 0x02 1. " PCE ,Force position counter error interrupt" "No effect,Forced"
|
|
line.word 0x04 "QCLR,EQEP Interrupt Clear Register"
|
|
bitfld.word 0x04 11. " UTO ,Clear unit time out interrupt flag" "No effect,Clears flag"
|
|
bitfld.word 0x04 10. " IEL ,Clear index event latch interrupt flag" "No effect,Clears flag"
|
|
bitfld.word 0x04 9. " SEL ,Clear strobe event latch interrupt flag" "No effect,Clears flag"
|
|
bitfld.word 0x04 8. " PCM ,Clear EQEP compare match event interrupt flag" "No effect,Clears flag"
|
|
newline
|
|
bitfld.word 0x04 7. " PCR ,Clear position-compare ready interrupt flag" "No effect,Clears flag"
|
|
bitfld.word 0x04 6. " PCO ,Clear position counter overflow interrupt flag" "No effect,Clears flag"
|
|
bitfld.word 0x04 5. " PCU ,Clear position counter underflow interrupt flag" "No effect,Clears flag"
|
|
bitfld.word 0x04 4. " WTO ,Clear watchdog timeout interrupt flag" "No effect,Clears flag"
|
|
newline
|
|
bitfld.word 0x04 3. " QDC ,Clear quadrature direction change interrupt flag" "No effect,Clears flag"
|
|
bitfld.word 0x04 2. " PHE ,Clear quadrature phase error interrupt flag" "No effect,Clears flag"
|
|
bitfld.word 0x04 1. " PCE ,Clear position counter error interrupt flag" "No effect,Clears flag"
|
|
bitfld.word 0x04 0. " INT ,Global interrupt clear flag" "No effect,Clears flag"
|
|
line.word 0x06 "QCTMR,EQEP Capture Timer Register"
|
|
line.word 0x08 "QEPSTS,EQEP Status Register"
|
|
eventfld.word 0x08 7. " UPEVNT ,Unit position event flag" "Not detected,Detected"
|
|
rbitfld.word 0x08 6. " FIDF ,Direction on the first index marker" "Counter-clockwise rotation,Clockwise rotation"
|
|
newline
|
|
rbitfld.word 0x08 5. " QDF ,Quadrature direction flag" "Counter-clockwise rotation,Clockwise rotation"
|
|
rbitfld.word 0x08 4. " QDLF ,EQEP direction latch flag" "Counter-clockwise rotation,Clockwise rotation"
|
|
newline
|
|
eventfld.word 0x08 3. " COEF ,Capture overflow error flag" "Not occurred,Occurred"
|
|
eventfld.word 0x08 2. " CDEF ,Capture direction error flag" "Not occurred,Occurred"
|
|
newline
|
|
eventfld.word 0x08 1. " FIMF ,First index marker flag" "Not occurred,Occurred"
|
|
rbitfld.word 0x08 0. " PCEF ,Position counter error flag" "No error,Error"
|
|
line.word 0x0A "QCTMRLAT,EQEP Capture Timer Latch Register"
|
|
line.word 0x0C "QCPRD,EQEP Capture Period Register"
|
|
group.word 0x42++0x01
|
|
line.word 0x00 "QCPRDLAT,EQEP Capture Period Latch Register"
|
|
endif
|
|
sif cpuis("TMS570LS0232")||cpuis("TMS570LS0714*")||cpuis("TMS570LS0914*")
|
|
endian.le
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
sif cpuis("TMS570LS0232")||cpuis("TMS570LS0714*")||cpuis("TMS570LS0914*")
|
|
tree "ADC (Analog To Digital Converter Module)"
|
|
base ad:0xFFF7C000
|
|
width 10.
|
|
group.long 0x00++0x0B
|
|
line.long 0x0 "RSTCR,Reset Control Register"
|
|
bitfld.long 0x00 0. " RESET ,ADC reset" "No reset,Reset"
|
|
line.long 0x04 "OPMODECR,Operating Mode Control Register"
|
|
bitfld.long 0x04 31. " 10/12_BIT ,Resolution of the ADC core" "10-bit,12-bit"
|
|
bitfld.long 0x04 24. " COS ,Continue on suspend enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x04 17.--20. " CHN_TEST_EN ,ADC channel test enable" "Disabled,Disabled,Disabled,Disabled,Disabled,Enabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled"
|
|
bitfld.long 0x04 16. " RAM_TEST_EN ,ADC RAM test enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x04 8. " POWERDOWN ,ADC internal clocks powerdown mode" "Normal,Power-down"
|
|
bitfld.long 0x04 4. " NORMAL ,ADC power down when idle" "Normal,Power-down"
|
|
newline
|
|
bitfld.long 0x04 0. " ADC_EN ,ADC enable" "Disabled,Enabled"
|
|
line.long 0x08 "CLOCKCR,Clock Prescaler"
|
|
bitfld.long 0x08 0.--4. " PS[4:0] ,ADC Clock Prescaler" "1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles,16 cycles,17 cycles,18 cycles,19 cycles,20 cycles,21 cycles,22 cycles,23 cycles,24 cycles,25 cycles,26 cycles,27 cycles,28 cycles,29 cycles,30 cycles,31 cycles,32 cycles"
|
|
if (((per.l.be((ad:0xFFF7C000+0x0C)))&0x1000000)==0x1000000)
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "CALCR,Calibration Conversion Register"
|
|
bitfld.long 0x00 24. " SELF_TEST ,Self-test enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " CAL_ST ,Calibration conversion start" "No effect/completed,Started"
|
|
newline
|
|
bitfld.long 0x00 9. " BRIDGE_EN ,Bridge enable" "Midpoint,Full"
|
|
bitfld.long 0x00 8. " HILO ,Test and reference source selection" "AD REFLO via R1 || R2,AD REFHI via R1 || R2"
|
|
newline
|
|
rbitfld.long 0x00 0. " CAL_EN ,Calibration enable" "Disabled,Enabled"
|
|
elif (((per.l.be((ad:0xFFF7C000+0x0C)))&0x201)==0x001)
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "CALCR,Calibration Conversion Register"
|
|
rbitfld.long 0x00 24. " SELF_TEST ,Self-test enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " CAL_ST ,Calibration conversion start" "No effect/completed,Started"
|
|
newline
|
|
bitfld.long 0x00 9. " BRIDGE_EN ,Bridge enable" "Midpoint,Full"
|
|
bitfld.long 0x00 8. " HILO ,Test and reference source selection" "(AD_REFHI*R1+AD_REFLO*R2)/(R1+R2),(AD_REFLO*R1+AD_REFHI*R2)/(R1+R2)"
|
|
newline
|
|
bitfld.long 0x00 0. " CAL_EN ,Calibration enable" "Disabled,Enabled"
|
|
elif (((per.l.be((ad:0xFFF7C000+0x0C)))&0x201)==0x201)
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "CALCR,Calibration Conversion Register"
|
|
rbitfld.long 0x00 24. " SELF_TEST ,Self-test enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " CAL_ST ,Calibration conversion start" "No effect/completed,Started"
|
|
newline
|
|
bitfld.long 0x00 9. " BRIDGE_EN ,Bridge enable" "Midpoint,Full"
|
|
bitfld.long 0x00 8. " HILO ,Test and reference source selection" "AD_REFLO,AD_REFHI"
|
|
newline
|
|
bitfld.long 0x00 0. " CAL_EN ,Calibration enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "CALCR,Calibration Conversion Register"
|
|
bitfld.long 0x00 24. " SELF_TEST ,Self-test enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " CAL_ST ,Calibration conversion start" "No effect/completed,Started"
|
|
newline
|
|
bitfld.long 0x00 9. " BRIDGE_EN ,Bridge enable" "Midpoint,Full"
|
|
newline
|
|
bitfld.long 0x00 0. " CAL_EN ,Calibration enable" "Disabled,Enabled"
|
|
endif
|
|
width 18.
|
|
tree "Event Group Registers"
|
|
if (((per.l.be((ad:0xFFF7C000+0x04)))&0x80000000)==0x80000000)
|
|
group.long 0x10++0x3
|
|
line.long 0x0 "EVMODECR,Event Group MODE Control Register"
|
|
bitfld.long 0x00 16. " NO_RESET_ON_CHNSEL ,No Event Group results memory reset on new channel select" "Reset,No reset"
|
|
bitfld.long 0x00 8.--9. " EV_DATA_FMT ,Event Group (read) data format" "12 bit,10 bit,8 bit,?..."
|
|
newline
|
|
bitfld.long 0x00 5. " EV_CHID ,Channel ID mode for the Event Group" "Forced to 0,ID of A/D channel"
|
|
bitfld.long 0x00 4. " OVR_EV_RAM_IGN ,Overrun event group ram ignore" "Not ignored,Ignored"
|
|
newline
|
|
bitfld.long 0x00 1. " EV_MODE ,Event mode" "Single,Continuous"
|
|
bitfld.long 0x00 0. " FRZ_EV ,Freeze conversion Event Group" "Completed,Frozen"
|
|
else
|
|
group.long 0x10++0x3
|
|
line.long 0x00 "EVMODECR,Event Group MODE Control Register"
|
|
bitfld.long 0x00 16. " NO_RESET_ON_CHNSEL ,No Event Group results memory reset on new channel select" "Reset,No reset"
|
|
bitfld.long 0x00 5. " EV_CHID ,Channel ID mode for the Event Group" "Forced to 0,ID of A/D channel"
|
|
bitfld.long 0x00 4. " OVR_EV_RAM_IGN ,Overrun Event Group RAM Ignore" "Not ignored,Ignored"
|
|
newline
|
|
bitfld.long 0x00 2. " EV_8BIT ,Event Group 8-bit result mode" "10-bit,8-bit"
|
|
bitfld.long 0x00 1. " EV_MODE ,Event mode" "Single,Continuous"
|
|
bitfld.long 0x00 0. " FRZ_EV ,Freeze conversion Event Group" "Completed,Frozen"
|
|
endif
|
|
group.long (0x10+0x0C)++0x3
|
|
line.long 0x00 "EVSRC,Event Group Trigger Source Select"
|
|
bitfld.long 0x00 4. " EV_EDG_BOTH ,Event Group trigger edge polarity select" "Defined edge,Any edge"
|
|
bitfld.long 0x00 3. " EV_EDG_SEL ,ADC Event Group trigger edge select" "High/low,Low/high"
|
|
bitfld.long 0x00 0.--2. " EVSRC[2:0] ,Event Group trigger source select" "Internal,Internal,Internal,Internal,Internal,Internal,Internal,Internal"
|
|
group.long (0x10+0x18)++0x3
|
|
line.long 0x00 "EVINTENA,Event Group Interrupt Enable"
|
|
bitfld.long 0x00 3. " EV_END_INT_EN ,Event Group conversion end interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " EV_OVR_INT_EN ,Event Group memory overrun interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " EV_THR_INT_EN ,Event Group memory threshold interrupt enable" "Disabled,Enabled"
|
|
group.long (0x10+0x24)++0x3
|
|
line.long 0x00 "EVINTFLG,Event Group Interrupt Flag"
|
|
eventfld.long 0x00 3. " EV_END ,Event Group conversion end" "Not converted,Converted"
|
|
rbitfld.long 0x00 2. " EV_MEM_EMPTY ,Event Group FIFO empty status" "Not empty,Empty"
|
|
newline
|
|
rbitfld.long 0x00 1. " EV_MEM_OVERRUN ,Event Group memory overrun flag" "No overrun,Overrun"
|
|
eventfld.long 0x00 0. " EV_THR_INT_FLAG ,Event Group threshold interrupt flag" "No interrupt,Interrupt"
|
|
group.long (0x10+0x30)++0x3
|
|
line.long 0x00 "EVINTCR,Event Group Interrupt Threshold Counter"
|
|
hexmask.long.byte 0x00 9.--15. 1. " SIGN_EXTENSION ,Sign extension"
|
|
hexmask.long.word 0x00 0.--8. 1. " EV_THR[8:0] ,Event Group interrupt threshold counter"
|
|
sif cpuis("TMS570LS0714*")||cpuis("TMS570LS0914*")||cpuis("TMS570LS3137-EP")
|
|
group.long (0x10+0x3C)++0x3
|
|
line.long 0x00 "EVDMACR,Event Group DMA Control Register"
|
|
hexmask.long.word 0x00 16.--24. 1. " EVBLOCKS[8:0] ,Number of Event Group memory buffers to be transferred"
|
|
bitfld.long 0x00 3. " DMA_EV_END ,Event Group conversion end DMA transfer enable" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. " EV_BLK_XFER ,Event Group block DMA transfer enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " EV_DMA_EN ,Event Group DMA transfer enable" "Disabled,Enabled"
|
|
endif
|
|
group.long (0x10+0x50)++0x3
|
|
line.long 0x00 "EVSAMP,Event Group Sample Window"
|
|
hexmask.long.word 0x00 0.--11. 1. " EV_ACQ ,Event Group Acquisition Prescale Bits"
|
|
group.long (0x10+0x5C)++0x3
|
|
line.long 0x0 "EVSR,Event Group Status Register"
|
|
rbitfld.long 0x00 3. " EV_MEM_EMPTY ,Event Group memory empty" "Not empty,Empty"
|
|
rbitfld.long 0x00 2. " EV_BUSY ,Event Group conversion-busy flag" "Not active,Busy"
|
|
newline
|
|
rbitfld.long 0x00 1. " EV_STOP ,Event Group conversion stopped flag" "Not frozen,Frozen"
|
|
eventfld.long 0x00 0. " EV_END ,Event Group conversion-ended flag R/W" "Not completed,Completed"
|
|
newline
|
|
group.long (0x10+0x68)++0x3
|
|
line.long 0x0 "EVSEL,Event Group select register"
|
|
sif cpuis("TMS570LS0714*")||cpuis("TMS570LS0914*")||cpuis("TMS570LS3137-EP")
|
|
bitfld.long 0x00 23. " EVCHNSEL[23] ,A/D Event Group Channel 23 selection bit" "Not converted,Converted"
|
|
bitfld.long 0x00 22. " [22] ,A/D Event Group Channel 22 selection bit" "Not converted,Converted"
|
|
bitfld.long 0x00 21. " [21] ,A/D Event Group Channel 21 selection bit" "Not converted,Converted"
|
|
newline
|
|
bitfld.long 0x00 20. " [20] ,A/D Event Group Channel 20 selection bit" "Not converted,Converted"
|
|
bitfld.long 0x00 19. " [19] ,A/D Event Group Channel 19 selection bit" "Not converted,Converted"
|
|
bitfld.long 0x00 18. " [18] ,A/D Event Group Channel 18 selection bit" "Not converted,Converted"
|
|
newline
|
|
bitfld.long 0x00 17. " [17] ,A/D Event Group Channel 17 selection bit" "Not converted,Converted"
|
|
bitfld.long 0x00 16. " [16] ,A/D Event Group Channel 16 selection bit" "Not converted,Converted"
|
|
bitfld.long 0x00 15. " [15] ,A/D Event Group Channel 15 selection bit" "Not converted,Converted"
|
|
newline
|
|
else
|
|
bitfld.long 0x00 15. " EVCHNSEL[15] ,A/D Event Group Channel 15 selection bit" "Not converted,Converted"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 14. " [14] ,A/D Event Group Channel 14 selection bit" "Not converted,Converted"
|
|
bitfld.long 0x00 13. " [13] ,A/D Event Group Channel 13 selection bit" "Not converted,Converted"
|
|
bitfld.long 0x00 12. " [12] ,A/D Event Group Channel 12 selection bit" "Not converted,Converted"
|
|
newline
|
|
bitfld.long 0x00 11. " [11] ,A/D Event Group Channel 11 selection bit" "Not converted,Converted"
|
|
bitfld.long 0x00 10. " [10] ,A/D Event Group Channel 10 selection bit" "Not converted,Converted"
|
|
bitfld.long 0x00 9. " [9] ,A/D Event Group Channel 9 selection bit" "Not converted,Converted"
|
|
newline
|
|
bitfld.long 0x00 8. " [8] ,A/D Event Group Channel 8 selection bit" "Not converted,Converted"
|
|
bitfld.long 0x00 7. " [7] ,A/D Event Group Channel 7 selection bit" "Not converted,Converted"
|
|
bitfld.long 0x00 6. " [6] ,A/D Event Group Channel 6 selection bit" "Not converted,Converted"
|
|
newline
|
|
bitfld.long 0x00 5. " [5] ,A/D Event Group Channel 5 selection bit" "Not converted,Converted"
|
|
bitfld.long 0x00 4. " [4] ,A/D Event Group Channel 4 selection bit" "Not converted,Converted"
|
|
bitfld.long 0x00 3. " [3] ,A/D Event Group Channel 3 selection bit" "Not converted,Converted"
|
|
newline
|
|
bitfld.long 0x00 2. " [2] ,A/D Event Group Channel 2 selection bit" "Not converted,Converted"
|
|
bitfld.long 0x00 1. " [1] ,A/D Event Group Channel 1 selection bit" "Not converted,Converted"
|
|
bitfld.long 0x00 0. " [0] ,A/D Event Group Channel 0 selection bit" "Not converted,Converted"
|
|
newline
|
|
hgroup.long 0x90++0x03
|
|
hide.long 0x00 "EVBUFFER0,ADC Event Group Results Emulation FIFO Register 0"
|
|
in
|
|
hgroup.long (0x90+0x04)++0x03
|
|
hide.long 0x00 "EVBUFFER1,ADC Event Group Results Emulation FIFO Register 1"
|
|
in
|
|
hgroup.long (0x90+0x08)++0x03
|
|
hide.long 0x00 "EVBUFFER2,ADC Event Group Results Emulation FIFO Register 2"
|
|
in
|
|
hgroup.long (0x90+0x0C)++0x03
|
|
hide.long 0x00 "EVBUFFER3,ADC Event Group Results Emulation FIFO Register 3"
|
|
in
|
|
hgroup.long (0x90+0x10)++0x03
|
|
hide.long 0x00 "EVBUFFER4,ADC Event Group Results Emulation FIFO Register 4"
|
|
in
|
|
hgroup.long (0x90+0x14)++0x03
|
|
hide.long 0x00 "EVBUFFER5,ADC Event Group Results Emulation FIFO Register 5"
|
|
in
|
|
hgroup.long (0x90+0x18)++0x03
|
|
hide.long 0x00 "EVBUFFER6,ADC Event Group Results Emulation FIFO Register 6"
|
|
in
|
|
hgroup.long (0x90+0x1C)++0x03
|
|
hide.long 0x00 "EVBUFFER7,ADC Event Group Results Emulation FIFO Register 7"
|
|
in
|
|
hgroup.long (0x10+0xF0)++0x3
|
|
hide.long 0x00 "EVEMUBUFFER,Event Group Result Emulation FIFO Register"
|
|
in
|
|
newline
|
|
group.long 0xFC++0x07
|
|
line.long 0x0 "EVTDIR,Event Group Pin Direction Selection"
|
|
bitfld.long 0x00 0. " EVT_DIR ,ADEVT pin direction selection" "Input,Output"
|
|
line.long 0x04 "EVTOUT,Event Group pin data output"
|
|
bitfld.long 0x04 0. " EVT_OUT ,ADEVT pin data output" "Low,High"
|
|
rgroup.long 0x104++0x3
|
|
line.long 0x0 "EVTIN,Event Group Pin Input Value"
|
|
bitfld.long 0x00 0. " EVT_IN ,ADEVT pin input value" "Low,High"
|
|
group.long 0x108++0x3
|
|
line.long 0x0 "EVTSET_SET/CLR,Event Group Pin Set/Clear Register"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x04 0. " ADEVT ,ADEVT pin set/clear" "Low,High"
|
|
group.long 0x110++0x0B
|
|
line.long 0x0 "EVTPDR,Event Group Pin Open-Drain Enable"
|
|
bitfld.long 0x00 0. " ADEVT_PDR ,ADEVT Pin open-drain enable" "Disabled,Enabled"
|
|
line.long 0x04 "EVTPDIS,Event Group pin pull control enable"
|
|
bitfld.long 0x04 0. " ADEVT_PDIS ,ADEVT Pin pull control enable" "Enabled,Disabled"
|
|
line.long 0x08 "EVTPSEL,Event Group pull select"
|
|
bitfld.long 0x08 0. " ADEVT_PSEL ,ADEVT Pull select" "Pull-down,Pull-up"
|
|
group.long (0x10+0x11C)++0x3
|
|
line.long 0x00 "EVSAMPDISEN,Event Group Sampling Capacitor Discharge Mode"
|
|
hexmask.long.byte 0x00 8.--15. 1. " EV_SAMP_DIS_CYC[7:0] ,ADC sampling capacitor is discharged cycles"
|
|
bitfld.long 0x00 0. " EV_SAMP_DIS_EN ,Sampling capacitor discharge mode" "Disabled,Enabled"
|
|
group.long (0x10+0x168)++0x3
|
|
line.long 0x00 "EVFIFORESETCR,Event Group FIFO Reset"
|
|
bitfld.long 0x00 0. " EV_FIFO_RESET ,Reset the ADC Event Group FIFO" "No reset,Reset"
|
|
group.long (0x10+0x174)++0x3
|
|
line.long 0x00 "EVRAMADDR,Event Group ADC RAM Pointer"
|
|
hexmask.long.word 0x00 0.--8. 0x01 " EV_RAM_ADDR ,Event Group ADC RAM pointer"
|
|
group.long (0x10+0x190)++0x03
|
|
line.long 0x00 "EVCHNSELMODECTRL, ADC Event Group Channel Selection Mode Control Register"
|
|
bitfld.long 0x00 0.--3. " EV_ENH_CHNSEL_MODE_ENABLE , Enable enhanced channel selection mode" ",,,,,Disabled,,,,,Enabled,?..."
|
|
group.long 0x19C++0x07
|
|
line.long 0x00 "EVCURRCOUNT, ADC Event Group Current Count Register"
|
|
bitfld.long 0x00 0.--4. " EV_CURRENT_COUNT , Value for the Event Group conversions" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
line.long 0x04 "EVMAXCOUNT, ADC Event Group Maximum Count Register"
|
|
bitfld.long 0x04 0.--4. " EV_MAX_COUNT , Value for the Event Group conversions" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
tree.end
|
|
tree "Group 1 Registers"
|
|
if (((per.l.be((ad:0xFFF7C000+0x04)))&0x80000000)==0x80000000)
|
|
group.long 0x14++0x3
|
|
line.long 0x0 "G1MODECR,Group 1 MODE Control Register"
|
|
bitfld.long 0x00 16. " NO_RESET_ON_CHNSEL ,No Group 1 results memory reset on new channel select" "Reset,No reset"
|
|
bitfld.long 0x00 8.--9. " G1_DATA_FMT ,Group 1 (read) data format" "12 bit,10 bit,8 bit,?..."
|
|
newline
|
|
bitfld.long 0x00 5. " G1_CHID ,Channel ID mode for the Group 1" "Forced to 0,ID of A/D channel"
|
|
bitfld.long 0x00 4. " OVR_G1_RAM_IGN ,Overrun event group ram ignore" "Not ignored,Ignored"
|
|
newline
|
|
bitfld.long 0x00 3. " G1_HW_TRIG ,Group 1 hardware triggered" "Software,Event"
|
|
bitfld.long 0x00 2. " G1_8BIT ,Group 1 8-bit result mode" "10-bit,8-bit"
|
|
newline
|
|
bitfld.long 0x00 1. " G1_MODE ,Group 1 mode" "Single,Continuous"
|
|
bitfld.long 0x00 0. " FRZ_G1 ,Freeze conversion Group 1" "Completed,Frozen"
|
|
else
|
|
group.long 0x14++0x3
|
|
line.long 0x00 "G1MODECR,Group 1 MODE Control Register"
|
|
bitfld.long 0x00 16. " NO_RESET_ON_CHNSEL ,No Group 1 results memory reset on new channel select" "Reset,No reset"
|
|
bitfld.long 0x00 5. " G1_CHID ,Channel ID mode for the Group 1" "Forced to 0,ID of A/D channel"
|
|
bitfld.long 0x00 4. " OVR_G1_RAM_IGN ,Overrun Event Group RAM Ignore" "Not ignored,Ignored"
|
|
newline
|
|
bitfld.long 0x00 3. " G1_HW_TRIG ,Group 1 Hardware Triggered" "Software,Event"
|
|
bitfld.long 0x00 2. " G1_8BIT ,Group 1 8-bit result mode" "10-bit,8-bit"
|
|
newline
|
|
bitfld.long 0x00 1. " G1_MODE ,Group 1 mode" "Single,Continuous"
|
|
bitfld.long 0x00 0. " FRZ_G1 ,Freeze Conversion Group 1" "Completed,Frozen"
|
|
endif
|
|
group.long (0x14+0x0C)++0x3
|
|
line.long 0x00 "G1SRC,Group 1 Trigger Source Select"
|
|
bitfld.long 0x00 4. " G1_EDG_BOTH ,Group 1 trigger edge polarity select" "Defined edge,Any edge"
|
|
bitfld.long 0x00 3. " G1_EDG_SEL ,ADC Group 1 trigger edge select" "High/low,Low/high"
|
|
bitfld.long 0x00 0.--2. " G1SRC[2:0] ,Group 1 trigger source select" "Internal,Internal,Internal,Internal,Internal,Internal,Internal,Internal"
|
|
group.long (0x14+0x18)++0x3
|
|
line.long 0x00 "G1INTENA,Group 1 Interrupt Enable"
|
|
bitfld.long 0x00 3. " G1_END_INT_EN ,Group 1 conversion end interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " G1_OVR_INT_EN ,Group 1 memory overrun interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " G1_THR_INT_EN ,Group 1 memory threshold interrupt enable" "Disabled,Enabled"
|
|
group.long (0x14+0x24)++0x3
|
|
line.long 0x00 "G1INTFLG,Group 1 Interrupt Flag"
|
|
eventfld.long 0x00 3. " G1_END ,Group 1 conversion end" "Not converted,Converted"
|
|
rbitfld.long 0x00 2. " G1_MEM_EMPTY ,Group 1 FIFO empty status" "Not empty,Empty"
|
|
newline
|
|
rbitfld.long 0x00 1. " G1_MEM_OVERRUN ,Group 1 memory overrun flag" "No overrun,Overrun"
|
|
eventfld.long 0x00 0. " G1_THR_INT_FLAG ,Group 1 threshold interrupt flag" "No interrupt,Interrupt"
|
|
group.long (0x14+0x30)++0x3
|
|
line.long 0x00 "G1INTCR,Group 1 Interrupt Threshold Counter"
|
|
hexmask.long.byte 0x00 9.--15. 1. " SIGN_EXTENSION ,Sign extension"
|
|
hexmask.long.word 0x00 0.--8. 1. " G1_THR[8:0] ,Group 1 interrupt threshold counter"
|
|
sif cpuis("TMS570LS0714*")||cpuis("TMS570LS0914*")||cpuis("TMS570LS3137-EP")
|
|
group.long (0x14+0x3C)++0x3
|
|
line.long 0x00 "G1DMACR,Group 1 DMA Control Register"
|
|
hexmask.long.word 0x00 16.--24. 1. " G1BLOCKS[8:0] ,Number of Group 1 memory buffers to be transferred"
|
|
bitfld.long 0x00 3. " DMA_G1_END ,Group 1 conversion end DMA transfer enable" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. " G1_BLK_XFER ,Group 1 block DMA transfer enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " G1_DMA_EN ,Group 1 DMA transfer enable" "Disabled,Enabled"
|
|
endif
|
|
group.long (0x14+0x50)++0x3
|
|
line.long 0x00 "G1SAMP,Group 1 Sample Window"
|
|
hexmask.long.word 0x00 0.--11. 1. " G1_ACQ ,Group 1 Acquisition Prescale Bits"
|
|
group.long (0x14+0x5C)++0x3
|
|
line.long 0x0 "G1SR,Group 1 Status Register"
|
|
rbitfld.long 0x00 3. " G1_MEM_EMPTY ,Group 1 memory empty" "Not empty,Empty"
|
|
rbitfld.long 0x00 2. " G1_BUSY ,Group 1 conversion-busy flag" "Not active,Busy"
|
|
newline
|
|
rbitfld.long 0x00 1. " G1_STOP ,Group 1 conversion stopped flag" "Not frozen,Frozen"
|
|
eventfld.long 0x00 0. " G1_END ,Group 1 conversion-ended flag R/W" "Not completed,Completed"
|
|
newline
|
|
group.long (0x14+0x68)++0x3
|
|
line.long 0x0 "G1SEL,Group 1 select register"
|
|
sif cpuis("TMS570LS0714*")||cpuis("TMS570LS0914*")||cpuis("TMS570LS3137-EP")
|
|
bitfld.long 0x00 23. " EVCHNSEL[23] ,A/D Group 1 Channel 23 selection bit" "Not converted,Converted"
|
|
bitfld.long 0x00 22. " [22] ,A/D Group 1 Channel 22 selection bit" "Not converted,Converted"
|
|
bitfld.long 0x00 21. " [21] ,A/D Group 1 Channel 21 selection bit" "Not converted,Converted"
|
|
newline
|
|
bitfld.long 0x00 20. " [20] ,A/D Group 1 Channel 20 selection bit" "Not converted,Converted"
|
|
bitfld.long 0x00 19. " [19] ,A/D Group 1 Channel 19 selection bit" "Not converted,Converted"
|
|
bitfld.long 0x00 18. " [18] ,A/D Group 1 Channel 18 selection bit" "Not converted,Converted"
|
|
newline
|
|
bitfld.long 0x00 17. " [17] ,A/D Group 1 Channel 17 selection bit" "Not converted,Converted"
|
|
bitfld.long 0x00 16. " [16] ,A/D Group 1 Channel 16 selection bit" "Not converted,Converted"
|
|
bitfld.long 0x00 15. " [15] ,A/D Group 1 Channel 15 selection bit" "Not converted,Converted"
|
|
newline
|
|
else
|
|
bitfld.long 0x00 15. " EVCHNSEL[15] ,A/D Group 1 Channel 15 selection bit" "Not converted,Converted"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 14. " [14] ,A/D Group 1 Channel 14 selection bit" "Not converted,Converted"
|
|
bitfld.long 0x00 13. " [13] ,A/D Group 1 Channel 13 selection bit" "Not converted,Converted"
|
|
bitfld.long 0x00 12. " [12] ,A/D Group 1 Channel 12 selection bit" "Not converted,Converted"
|
|
newline
|
|
bitfld.long 0x00 11. " [11] ,A/D Group 1 Channel 11 selection bit" "Not converted,Converted"
|
|
bitfld.long 0x00 10. " [10] ,A/D Group 1 Channel 10 selection bit" "Not converted,Converted"
|
|
bitfld.long 0x00 9. " [9] ,A/D Group 1 Channel 9 selection bit" "Not converted,Converted"
|
|
newline
|
|
bitfld.long 0x00 8. " [8] ,A/D Group 1 Channel 8 selection bit" "Not converted,Converted"
|
|
bitfld.long 0x00 7. " [7] ,A/D Group 1 Channel 7 selection bit" "Not converted,Converted"
|
|
bitfld.long 0x00 6. " [6] ,A/D Group 1 Channel 6 selection bit" "Not converted,Converted"
|
|
newline
|
|
bitfld.long 0x00 5. " [5] ,A/D Group 1 Channel 5 selection bit" "Not converted,Converted"
|
|
bitfld.long 0x00 4. " [4] ,A/D Group 1 Channel 4 selection bit" "Not converted,Converted"
|
|
bitfld.long 0x00 3. " [3] ,A/D Group 1 Channel 3 selection bit" "Not converted,Converted"
|
|
newline
|
|
bitfld.long 0x00 2. " [2] ,A/D Group 1 Channel 2 selection bit" "Not converted,Converted"
|
|
bitfld.long 0x00 1. " [1] ,A/D Group 1 Channel 1 selection bit" "Not converted,Converted"
|
|
bitfld.long 0x00 0. " [0] ,A/D Group 1 Channel 0 selection bit" "Not converted,Converted"
|
|
newline
|
|
hgroup.long 0xB0++0x03
|
|
hide.long 0x00 "G1BUFFER0,ADC Group 1 Results Emulation FIFO Register 0"
|
|
in
|
|
hgroup.long (0xB0+0x04)++0x03
|
|
hide.long 0x00 "G1BUFFER1,ADC Group 1 Results Emulation FIFO Register 1"
|
|
in
|
|
hgroup.long (0xB0+0x08)++0x03
|
|
hide.long 0x00 "G1BUFFER2,ADC Group 1 Results Emulation FIFO Register 2"
|
|
in
|
|
hgroup.long (0xB0+0x0C)++0x03
|
|
hide.long 0x00 "G1BUFFER3,ADC Group 1 Results Emulation FIFO Register 3"
|
|
in
|
|
hgroup.long (0xB0+0x10)++0x03
|
|
hide.long 0x00 "G1BUFFER4,ADC Group 1 Results Emulation FIFO Register 4"
|
|
in
|
|
hgroup.long (0xB0+0x14)++0x03
|
|
hide.long 0x00 "G1BUFFER5,ADC Group 1 Results Emulation FIFO Register 5"
|
|
in
|
|
hgroup.long (0xB0+0x18)++0x03
|
|
hide.long 0x00 "G1BUFFER6,ADC Group 1 Results Emulation FIFO Register 6"
|
|
in
|
|
hgroup.long (0xB0+0x1C)++0x03
|
|
hide.long 0x00 "G1BUFFER7,ADC Group 1 Results Emulation FIFO Register 7"
|
|
in
|
|
hgroup.long (0x14+0xF0)++0x3
|
|
hide.long 0x00 "G1EMUBUFFER,Group 1 Result Emulation FIFO Register"
|
|
in
|
|
newline
|
|
group.long (0x14+0x11C)++0x3
|
|
line.long 0x00 "G1SAMPDISEN,Group 1 Sampling Capacitor Discharge Mode"
|
|
hexmask.long.byte 0x00 8.--15. 1. " G1_SAMP_DIS_CYC[7:0] ,ADC sampling capacitor is discharged cycles"
|
|
bitfld.long 0x00 0. " G1_SAMP_DIS_EN ,Sampling capacitor discharge mode" "Disabled,Enabled"
|
|
group.long (0x14+0x168)++0x3
|
|
line.long 0x00 "G1FIFORESETCR,Group 1 FIFO Reset"
|
|
bitfld.long 0x00 0. " G1_FIFO_RESET ,Reset the ADC Group 1 FIFO" "No reset,Reset"
|
|
group.long (0x14+0x174)++0x3
|
|
line.long 0x00 "G1RAMADDR,Group 1 ADC RAM Pointer"
|
|
hexmask.long.word 0x00 0.--8. 0x01 " G1_RAM_ADDR ,Group 1 ADC RAM pointer"
|
|
group.long (0x14+0x190)++0x03
|
|
line.long 0x00 "G1CHNSELMODECTRL, ADC Group 1 Channel Selection Mode Control Register"
|
|
bitfld.long 0x00 0.--3. " G1_ENH_CHNSEL_MODE_ENABLE , Enable enhanced channel selection mode" ",,,,,Disabled,,,,,Enabled,?..."
|
|
group.long 0x1A4++0x07
|
|
line.long 0x00 "G1CURRCOUNT, ADC Group 1 Current Count Register"
|
|
bitfld.long 0x00 0.--4. " G1_CURRENT_COUNT , Value for the Group 1 conversions" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
line.long 0x04 "G1MAXCOUNT, ADC Group 1 Maximum Count Register"
|
|
bitfld.long 0x04 0.--4. " G1_MAX_COUNT , Value for the Group 1 conversions" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
tree.end
|
|
tree "Group 2 Registers"
|
|
if (((per.l.be((ad:0xFFF7C000+0x04)))&0x80000000)==0x80000000)
|
|
group.long 0x18++0x3
|
|
line.long 0x0 "G2MODECR,Group 2 MODE Control Register"
|
|
bitfld.long 0x00 16. " NO_RESET_ON_CHNSEL ,No Group 2 results memory reset on new channel select" "Reset,No reset"
|
|
bitfld.long 0x00 8.--9. " G2_DATA_FMT ,Group 2 (read) data format" "12 bit,10 bit,8 bit,?..."
|
|
newline
|
|
bitfld.long 0x00 5. " G2_CHID ,Channel ID mode for the Group 2" "Forced to 0,ID of A/D channel"
|
|
bitfld.long 0x00 4. " OVR_G2_RAM_IGN ,Overrun event group ram ignore" "Not ignored,Ignored"
|
|
newline
|
|
bitfld.long 0x00 3. " G2_HW_TRIG ,Group 2 hardware triggered" "Software,Event"
|
|
bitfld.long 0x00 2. " G2_8BIT ,Group 2 8-bit result mode" "10-bit,8-bit"
|
|
newline
|
|
bitfld.long 0x00 1. " G2_MODE ,Group 2 mode" "Single,Continuous"
|
|
bitfld.long 0x00 0. " FRZ_G2 ,Freeze conversion Group 2" "Completed,Frozen"
|
|
else
|
|
group.long 0x18++0x3
|
|
line.long 0x00 "G2MODECR,Group 2 MODE Control Register"
|
|
bitfld.long 0x00 16. " NO_RESET_ON_CHNSEL ,No Group 2 results memory reset on new channel select" "Reset,No reset"
|
|
bitfld.long 0x00 5. " G2_CHID ,Channel ID mode for the Group 2" "Forced to 0,ID of A/D channel"
|
|
bitfld.long 0x00 4. " OVR_G2_RAM_IGN ,Overrun Event Group RAM Ignore" "Not ignored,Ignored"
|
|
newline
|
|
bitfld.long 0x00 3. " G2_HW_TRIG ,Group 2 Hardware Triggered" "Software,Event"
|
|
bitfld.long 0x00 2. " G2_8BIT ,Group 2 8-bit result mode" "10-bit,8-bit"
|
|
newline
|
|
bitfld.long 0x00 1. " G2_MODE ,Group 2 mode" "Single,Continuous"
|
|
bitfld.long 0x00 0. " FRZ_G2 ,Freeze Conversion Group 2" "Completed,Frozen"
|
|
endif
|
|
group.long (0x18+0x0C)++0x3
|
|
line.long 0x00 "G2SRC,Group 2 Trigger Source Select"
|
|
bitfld.long 0x00 4. " G2_EDG_BOTH ,Group 2 trigger edge polarity select" "Defined edge,Any edge"
|
|
bitfld.long 0x00 3. " G2_EDG_SEL ,ADC Group 2 trigger edge select" "High/low,Low/high"
|
|
bitfld.long 0x00 0.--2. " G2SRC[2:0] ,Group 2 trigger source select" "Internal,Internal,Internal,Internal,Internal,Internal,Internal,Internal"
|
|
group.long (0x18+0x18)++0x3
|
|
line.long 0x00 "G2INTENA,Group 2 Interrupt Enable"
|
|
bitfld.long 0x00 3. " G2_END_INT_EN ,Group 2 conversion end interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " G2_OVR_INT_EN ,Group 2 memory overrun interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " G2_THR_INT_EN ,Group 2 memory threshold interrupt enable" "Disabled,Enabled"
|
|
group.long (0x18+0x24)++0x3
|
|
line.long 0x00 "G2INTFLG,Group 2 Interrupt Flag"
|
|
eventfld.long 0x00 3. " G2_END ,Group 2 conversion end" "Not converted,Converted"
|
|
rbitfld.long 0x00 2. " G2_MEM_EMPTY ,Group 2 FIFO empty status" "Not empty,Empty"
|
|
newline
|
|
rbitfld.long 0x00 1. " G2_MEM_OVERRUN ,Group 2 memory overrun flag" "No overrun,Overrun"
|
|
eventfld.long 0x00 0. " G2_THR_INT_FLAG ,Group 2 threshold interrupt flag" "No interrupt,Interrupt"
|
|
group.long (0x18+0x30)++0x3
|
|
line.long 0x00 "G2INTCR,Group 2 Interrupt Threshold Counter"
|
|
hexmask.long.byte 0x00 9.--15. 1. " SIGN_EXTENSION ,Sign extension"
|
|
hexmask.long.word 0x00 0.--8. 1. " G2_THR[8:0] ,Group 2 interrupt threshold counter"
|
|
sif cpuis("TMS570LS0714*")||cpuis("TMS570LS0914*")||cpuis("TMS570LS3137-EP")
|
|
group.long (0x18+0x3C)++0x3
|
|
line.long 0x00 "G2DMACR,Group 2 DMA Control Register"
|
|
hexmask.long.word 0x00 16.--24. 1. " G2BLOCKS[8:0] ,Number of Group 2 memory buffers to be transferred"
|
|
bitfld.long 0x00 3. " DMA_G2_END ,Group 2 conversion end DMA transfer enable" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. " G2_BLK_XFER ,Group 2 block DMA transfer enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " G2_DMA_EN ,Group 2 DMA transfer enable" "Disabled,Enabled"
|
|
endif
|
|
group.long (0x18+0x50)++0x3
|
|
line.long 0x00 "G2SAMP,Group 2 Sample Window"
|
|
hexmask.long.word 0x00 0.--11. 1. " G2_ACQ ,Group 2 Acquisition Prescale Bits"
|
|
group.long (0x18+0x5C)++0x3
|
|
line.long 0x0 "G2SR,Group 2 Status Register"
|
|
rbitfld.long 0x00 3. " G2_MEM_EMPTY ,Group 2 memory empty" "Not empty,Empty"
|
|
rbitfld.long 0x00 2. " G2_BUSY ,Group 2 conversion-busy flag" "Not active,Busy"
|
|
newline
|
|
rbitfld.long 0x00 1. " G2_STOP ,Group 2 conversion stopped flag" "Not frozen,Frozen"
|
|
eventfld.long 0x00 0. " G2_END ,Group 2 conversion-ended flag R/W" "Not completed,Completed"
|
|
newline
|
|
group.long (0x18+0x68)++0x3
|
|
line.long 0x0 "G2SEL,Group 2 select register"
|
|
sif cpuis("TMS570LS0714*")||cpuis("TMS570LS0914*")||cpuis("TMS570LS3137-EP")
|
|
bitfld.long 0x00 23. " EVCHNSEL[23] ,A/D Group 2 Channel 23 selection bit" "Not converted,Converted"
|
|
bitfld.long 0x00 22. " [22] ,A/D Group 2 Channel 22 selection bit" "Not converted,Converted"
|
|
bitfld.long 0x00 21. " [21] ,A/D Group 2 Channel 21 selection bit" "Not converted,Converted"
|
|
newline
|
|
bitfld.long 0x00 20. " [20] ,A/D Group 2 Channel 20 selection bit" "Not converted,Converted"
|
|
bitfld.long 0x00 19. " [19] ,A/D Group 2 Channel 19 selection bit" "Not converted,Converted"
|
|
bitfld.long 0x00 18. " [18] ,A/D Group 2 Channel 18 selection bit" "Not converted,Converted"
|
|
newline
|
|
bitfld.long 0x00 17. " [17] ,A/D Group 2 Channel 17 selection bit" "Not converted,Converted"
|
|
bitfld.long 0x00 16. " [16] ,A/D Group 2 Channel 16 selection bit" "Not converted,Converted"
|
|
bitfld.long 0x00 15. " [15] ,A/D Group 2 Channel 15 selection bit" "Not converted,Converted"
|
|
newline
|
|
else
|
|
bitfld.long 0x00 15. " EVCHNSEL[15] ,A/D Group 2 Channel 15 selection bit" "Not converted,Converted"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 14. " [14] ,A/D Group 2 Channel 14 selection bit" "Not converted,Converted"
|
|
bitfld.long 0x00 13. " [13] ,A/D Group 2 Channel 13 selection bit" "Not converted,Converted"
|
|
bitfld.long 0x00 12. " [12] ,A/D Group 2 Channel 12 selection bit" "Not converted,Converted"
|
|
newline
|
|
bitfld.long 0x00 11. " [11] ,A/D Group 2 Channel 11 selection bit" "Not converted,Converted"
|
|
bitfld.long 0x00 10. " [10] ,A/D Group 2 Channel 10 selection bit" "Not converted,Converted"
|
|
bitfld.long 0x00 9. " [9] ,A/D Group 2 Channel 9 selection bit" "Not converted,Converted"
|
|
newline
|
|
bitfld.long 0x00 8. " [8] ,A/D Group 2 Channel 8 selection bit" "Not converted,Converted"
|
|
bitfld.long 0x00 7. " [7] ,A/D Group 2 Channel 7 selection bit" "Not converted,Converted"
|
|
bitfld.long 0x00 6. " [6] ,A/D Group 2 Channel 6 selection bit" "Not converted,Converted"
|
|
newline
|
|
bitfld.long 0x00 5. " [5] ,A/D Group 2 Channel 5 selection bit" "Not converted,Converted"
|
|
bitfld.long 0x00 4. " [4] ,A/D Group 2 Channel 4 selection bit" "Not converted,Converted"
|
|
bitfld.long 0x00 3. " [3] ,A/D Group 2 Channel 3 selection bit" "Not converted,Converted"
|
|
newline
|
|
bitfld.long 0x00 2. " [2] ,A/D Group 2 Channel 2 selection bit" "Not converted,Converted"
|
|
bitfld.long 0x00 1. " [1] ,A/D Group 2 Channel 1 selection bit" "Not converted,Converted"
|
|
bitfld.long 0x00 0. " [0] ,A/D Group 2 Channel 0 selection bit" "Not converted,Converted"
|
|
newline
|
|
hgroup.long 0xD0++0x03
|
|
hide.long 0x00 "G2BUFFER0,ADC Group 2 Results Emulation FIFO Register 0"
|
|
in
|
|
hgroup.long (0xD0+0x04)++0x03
|
|
hide.long 0x00 "G2BUFFER1,ADC Group 2 Results Emulation FIFO Register 1"
|
|
in
|
|
hgroup.long (0xD0+0x08)++0x03
|
|
hide.long 0x00 "G2BUFFER2,ADC Group 2 Results Emulation FIFO Register 2"
|
|
in
|
|
hgroup.long (0xD0+0x0C)++0x03
|
|
hide.long 0x00 "G2BUFFER3,ADC Group 2 Results Emulation FIFO Register 3"
|
|
in
|
|
hgroup.long (0xD0+0x10)++0x03
|
|
hide.long 0x00 "G2BUFFER4,ADC Group 2 Results Emulation FIFO Register 4"
|
|
in
|
|
hgroup.long (0xD0+0x14)++0x03
|
|
hide.long 0x00 "G2BUFFER5,ADC Group 2 Results Emulation FIFO Register 5"
|
|
in
|
|
hgroup.long (0xD0+0x18)++0x03
|
|
hide.long 0x00 "G2BUFFER6,ADC Group 2 Results Emulation FIFO Register 6"
|
|
in
|
|
hgroup.long (0xD0+0x1C)++0x03
|
|
hide.long 0x00 "G2BUFFER7,ADC Group 2 Results Emulation FIFO Register 7"
|
|
in
|
|
hgroup.long (0x18+0xF0)++0x3
|
|
hide.long 0x00 "G2EMUBUFFER,Group 2 Result Emulation FIFO Register"
|
|
in
|
|
newline
|
|
group.long (0x18+0x11C)++0x3
|
|
line.long 0x00 "G2SAMPDISEN,Group 2 Sampling Capacitor Discharge Mode"
|
|
hexmask.long.byte 0x00 8.--15. 1. " G2_SAMP_DIS_CYC[7:0] ,ADC sampling capacitor is discharged cycles"
|
|
bitfld.long 0x00 0. " G2_SAMP_DIS_EN ,Sampling capacitor discharge mode" "Disabled,Enabled"
|
|
group.long (0x18+0x168)++0x3
|
|
line.long 0x00 "G2FIFORESETCR,Group 2 FIFO Reset"
|
|
bitfld.long 0x00 0. " G2_FIFO_RESET ,Reset the ADC Group 2 FIFO" "No reset,Reset"
|
|
group.long (0x18+0x174)++0x3
|
|
line.long 0x00 "G2RAMADDR,Group 2 ADC RAM Pointer"
|
|
hexmask.long.word 0x00 0.--8. 0x01 " G2_RAM_ADDR ,Group 2 ADC RAM pointer"
|
|
group.long (0x18+0x190)++0x03
|
|
line.long 0x00 "G2CHNSELMODECTRL, ADC Group 2 Channel Selection Mode Control Register"
|
|
bitfld.long 0x00 0.--3. " G2_ENH_CHNSEL_MODE_ENABLE , Enable enhanced channel selection mode" ",,,,,Disabled,,,,,Enabled,?..."
|
|
group.long 0x1AC++0x07
|
|
line.long 0x00 "G2CURRCOUNT, ADC Group 2 Current Count Register"
|
|
bitfld.long 0x00 0.--4. " G2_CURRENT_COUNT , Value for the Group 2 conversions" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
line.long 0x04 "G2MAXCOUNT, ADC Group 2 Maximum Count Register"
|
|
bitfld.long 0x04 0.--4. " G2_MAX_COUNT , Value for the Group 2 conversions" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
tree.end
|
|
newline
|
|
width 10.
|
|
group.long 0x58++0x07
|
|
line.long 0x00 "BNDCR,Buffer Boundary Control Register"
|
|
hexmask.long.word 0x00 16.--24. 1. " BNDA[8:0] ,Buffer boundary A"
|
|
hexmask.long.word 0x00 0.--8. 1. " BNDB[8:0] ,Buffer boundary B"
|
|
line.long 0x04 "BNDEND,Buffer End Boundary"
|
|
rbitfld.long 0x04 16. " BUF_INIT_ACTIVE ,Indicates the status of the ADC RAM initialization process" "Not initialized,Initialized"
|
|
newline
|
|
bitfld.long 0x04 0.--2. " BNDEND[2:0] ,Buffer end boundary" "16 words,32 words,64 words,?..."
|
|
if ((per.l.be(ad:0xFFF7C000+0x04)&0x80000000)==0x80000000)
|
|
group.long 0x84++0x3
|
|
line.long 0x0 "CALR,Calibration Register"
|
|
hexmask.long.word 0x00 0.--11. 1. " CALR[11:0] ,Calibration bits"
|
|
else
|
|
group.long 0x84++0x3
|
|
line.long 0x0 "CALR,Calibration Register"
|
|
hexmask.long.word 0x00 0.--9. 1. " CALR[9:0] ,Calibration bits"
|
|
endif
|
|
rgroup.long 0x88++0x3
|
|
line.long 0x0 "SMSTATE,State Machine Current State"
|
|
bitfld.long 0x00 0.--3. " SMSTATE[3:0] ,ADC State Machine Current State" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
rgroup.long 0x8C++0x03
|
|
line.long 0x00 "LASTCONV,Last Conversion"
|
|
bitfld.long 0x00 23. " LAST_CONV[23] ,Digital input pin 23" "Low,High"
|
|
bitfld.long 0x00 22. " [22] ,Digital input pin 22" "Low,High"
|
|
bitfld.long 0x00 21. " [21] ,Digital input pin 21" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 20. " [20] ,Digital input pin 20" "Low,High"
|
|
bitfld.long 0x00 19. " [19] ,Digital input pin 19" "Low,High"
|
|
bitfld.long 0x00 18. " [18] ,Digital input pin 18" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 17. " [17] ,Digital input pin 17" "Low,High"
|
|
bitfld.long 0x00 16. " [16] ,Digital input pin 16" "Low,High"
|
|
bitfld.long 0x00 15. " [15] ,Digital input pin 15" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 14. " [14] ,Digital input pin 14" "Low,High"
|
|
bitfld.long 0x00 13. " [13] ,Digital input pin 13" "Low,High"
|
|
bitfld.long 0x00 12. " [12] ,Digital input pin 12" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 11. " [11] ,Digital input pin 11" "Low,High"
|
|
bitfld.long 0x00 10. " [10] ,Digital input pin 10" "Low,High"
|
|
bitfld.long 0x00 9. " [9] ,Digital input pin 9" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 8. " [8] ,Digital input pin 8" "Low,High"
|
|
bitfld.long 0x00 7. " [7] ,Digital input pin 7" "Low,High"
|
|
bitfld.long 0x00 6. " [6] ,Digital input pin 6" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 5. " [5] ,Digital input pin 5" "Low,High"
|
|
bitfld.long 0x00 4. " [4] ,Digital input pin 4" "Low,High"
|
|
bitfld.long 0x00 3. " [3] ,Digital input pin 3" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 2. " [2] ,Digital input pin 2" "Low,High"
|
|
bitfld.long 0x00 1. " [1] ,Digital input pin 1" "Low,High"
|
|
bitfld.long 0x00 0. " [0] ,Digital input pin 0" "Low,High"
|
|
width 16.
|
|
tree "ADC Interrupt Control Registers"
|
|
if ((per.l.be(ad:0xFFF7C000+0x04)&0x80000000)==0x80000000)
|
|
group.long 0x128++0x07
|
|
line.long 0x0 "MAGINT1 CR,Magnitude Interrupt 1 Control Register"
|
|
hexmask.long.word 0x00 16.--27. 1. " MAG_THR1 ,Compare Value"
|
|
bitfld.long 0x00 15. " CHN/THR_COMP1 , Channel OR Threshold Comparison" "Threshold,Channel"
|
|
bitfld.long 0x00 14. " CMP_GE/LT1 , Greater than or equal to OR Less than comparison operator" "Lower,Greater"
|
|
newline
|
|
bitfld.long 0x00 8.--12. " COMP_CHID1[4:0] ,COMP CHID1 [4:0]" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,Channel 8,Channel 9,Channel 10,Channel 11,Channel 12,Channel 13,Channel 14,Channel 15,Channel 16,Channel 17,Channel 18,Channel 19,Channel 20,Channel 21,Channel 22,Channel 23,Channel 24,Channel 25,Channel 26,Channel 27,Channel 28,Channel 29,Channel 30,Channel 31"
|
|
bitfld.long 0x00 0.--4. " MAG_CHID1 [4:0] ,MAG CHID1 [4:0]" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,Channel 8,Channel 9,Channel 10,Channel 11,Channel 12,Channel 13,Channel 14,Channel 15,Channel 16,Channel 17,Channel 18,Channel 19,Channel 20,Channel 21,Channel 22,Channel 23,Channel 24,Channel 25,Channel 26,Channel 27,Channel 28,Channel 29,Channel 30,Channel 31"
|
|
newline
|
|
line.long 0x04 "MAGINT1 MASK,Magnitude Interrupt Mask 1 "
|
|
bitfld.long 0x04 11. " MAG_INT1 _MASK[11] ,Comparison for the Magnitude Threshold Interrupt 1 Mask 11" "Not masked,Masked"
|
|
bitfld.long 0x04 10. " [10] ,Comparison for the Magnitude Threshold Interrupt 1 Mask 10" "Not masked,Masked"
|
|
bitfld.long 0x04 9. " [9] ,Comparison for the Magnitude Threshold Interrupt 1 Mask 9" "Not masked,Masked"
|
|
newline
|
|
bitfld.long 0x04 8. " [8] ,Comparison for the Magnitude Threshold Interrupt 1 Mask 8" "Not masked,Masked"
|
|
bitfld.long 0x04 7. " [7] ,Comparison for the Magnitude Threshold Interrupt 1 Mask 7" "Not masked,Masked"
|
|
bitfld.long 0x04 6. " [6] ,Comparison for the Magnitude Threshold Interrupt 1 Mask 6" "Not masked,Masked"
|
|
newline
|
|
bitfld.long 0x04 5. " [5] ,Comparison for the Magnitude Threshold Interrupt 1 Mask 5" "Not masked,Masked"
|
|
bitfld.long 0x04 4. " [4] ,Comparison for the Magnitude Threshold Interrupt 1 Mask 4" "Not masked,Masked"
|
|
bitfld.long 0x04 3. " [3] ,Comparison for the Magnitude Threshold Interrupt 1 Mask 3" "Not masked,Masked"
|
|
newline
|
|
bitfld.long 0x04 2. " [2] ,Comparison for the Magnitude Threshold Interrupt 1 Mask 2" "Not masked,Masked"
|
|
bitfld.long 0x04 1. " [1] ,Comparison for the Magnitude Threshold Interrupt 1 Mask 1" "Not masked,Masked"
|
|
bitfld.long 0x04 0. " [0] ,Comparison for the Magnitude Threshold Interrupt 1 Mask 0" "Not masked,Masked"
|
|
newline
|
|
else
|
|
group.long 0x128++0x07
|
|
line.long 0x0 "MAGINT1 CR,Magnitude Interrupt 1 Control Register"
|
|
sif cpuis("TMS570LS0714*")||cpuis("TMS570LS0914*")
|
|
hexmask.long.word 0x00 16.--25. 1. " MAG_THR1 ,Compare Value"
|
|
bitfld.long 0x00 15. " CHN/THR_COMP1 , Channel OR Threshold Comparison" "Threshold,Channel"
|
|
bitfld.long 0x00 14. " CMP_GE/LT1 , Greater than or equal to OR Less than comparison operator" "Lower,Greater"
|
|
newline
|
|
bitfld.long 0x00 8.--12. " COMP_CHID1[4:0] ,COMP CHID1 [4:0]" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,Channel 8,Channel 9,Channel 10,Channel 11,Channel 12,Channel 13,Channel 14,Channel 15,Channel 16,Channel 17,Channel 18,Channel 19,Channel 20,Channel 21,Channel 22,Channel 23,Channel 24,Channel 25,Channel 26,Channel 27,Channel 28,Channel 29,Channel 30,Channel 31"
|
|
bitfld.long 0x00 0.--4. " MAG_CHID1 [4:0] ,MAG CHID1 [4:0]" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,Channel 8,Channel 9,Channel 10,Channel 11,Channel 12,Channel 13,Channel 14,Channel 15,Channel 16,Channel 17,Channel 18,Channel 19,Channel 20,Channel 21,Channel 22,Channel 23,Channel 24,Channel 25,Channel 26,Channel 27,Channel 28,Channel 29,Channel 30,Channel 31"
|
|
else
|
|
bitfld.long 0x00 26.--30. " MAG_CHID1 [4:0] ,MAG CHID1 [4:0]" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,Channel 8,Channel 9,Channel 10,Channel 11,Channel 12,Channel 13,Channel 14,Channel 15,Channel 16,Channel 17,Channel 18,Channel 19,Channel 20,Channel 21,Channel 22,Channel 23,Channel 24,Channel 25,Channel 26,Channel 27,Channel 28,Channel 29,Channel 30,Channel 31"
|
|
hexmask.long.word 0x00 16.--25. 1. " MAG_THR1 ,Compare Value"
|
|
bitfld.long 0x00 8.--12. " COMP_CHID1 [4:0] ,COMP CHID1 [4:0]" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,Channel 8,Channel 9,Channel 10,Channel 11,Channel 12,Channel 13,Channel 14,Channel 15,Channel 16,Channel 17,Channel 18,Channel 19,Channel 20,Channel 21,Channel 22,Channel 23,Channel 24,Channel 25,Channel 26,Channel 27,Channel 28,Channel 29,Channel 30,Channel 31"
|
|
newline
|
|
bitfld.long 0x00 1. " CHN/THR_COMP1 , Channel OR Threshold Comparison" "Threshold,Channel"
|
|
bitfld.long 0x00 0. " CMP_GE/LT1 , Greater than or equal to OR Less than comparison operator" "Lower,Greater"
|
|
endif
|
|
newline
|
|
line.long 0x04 "MAGINT1 MASK,Magnitude Interrupt Mask 1 "
|
|
bitfld.long 0x04 9. " MAG_INT1 _MASK[9] ,Comparison for the magnitude threshold interrupt 1 Mask 9" "Not masked,Masked"
|
|
bitfld.long 0x04 8. " [8] ,Comparison for the magnitude threshold interrupt 1 Mask 8" "Not masked,Masked"
|
|
bitfld.long 0x04 7. " [7] ,Comparison for the magnitude threshold interrupt 1 Mask 7" "Not masked,Masked"
|
|
newline
|
|
bitfld.long 0x04 6. " [6] ,Comparison for the magnitude threshold interrupt 1 Mask 6" "Not masked,Masked"
|
|
bitfld.long 0x04 5. " [5] ,Comparison for the magnitude threshold interrupt 1 Mask 5" "Not masked,Masked"
|
|
bitfld.long 0x04 4. " [4] ,Comparison for the magnitude threshold interrupt 1 Mask 4" "Not masked,Masked"
|
|
newline
|
|
bitfld.long 0x04 3. " [3] ,Comparison for the magnitude threshold interrupt 1 Mask 3" "Not masked,Masked"
|
|
bitfld.long 0x04 2. " [2] ,Comparison for the magnitude threshold interrupt 1 Mask 2" "Not masked,Masked"
|
|
newline
|
|
bitfld.long 0x04 1. " [1] ,Comparison for the magnitude threshold interrupt 1 Mask 1" "Not masked,Masked"
|
|
bitfld.long 0x04 0. " [0] ,Comparison for the magnitude threshold interrupt 1 Mask 0" "Not masked,Masked"
|
|
newline
|
|
endif
|
|
if ((per.l.be(ad:0xFFF7C000+0x04)&0x80000000)==0x80000000)
|
|
group.long 0x128++0x07
|
|
line.long 0x0 "MAGINT2 CR,Magnitude Interrupt 2 Control Register"
|
|
hexmask.long.word 0x00 16.--27. 1. " MAG_THR2 ,Compare Value"
|
|
bitfld.long 0x00 15. " CHN/THR_COMP2 , Channel OR Threshold Comparison" "Threshold,Channel"
|
|
bitfld.long 0x00 14. " CMP_GE/LT2 , Greater than or equal to OR Less than comparison operator" "Lower,Greater"
|
|
newline
|
|
bitfld.long 0x00 8.--12. " COMP_CHID1[4:0] ,COMP CHID1 [4:0]" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,Channel 8,Channel 9,Channel 10,Channel 11,Channel 12,Channel 13,Channel 14,Channel 15,Channel 16,Channel 17,Channel 18,Channel 19,Channel 20,Channel 21,Channel 22,Channel 23,Channel 24,Channel 25,Channel 26,Channel 27,Channel 28,Channel 29,Channel 30,Channel 31"
|
|
bitfld.long 0x00 0.--4. " MAG_CHID2 [4:0] ,MAG CHID2 [4:0]" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,Channel 8,Channel 9,Channel 10,Channel 11,Channel 12,Channel 13,Channel 14,Channel 15,Channel 16,Channel 17,Channel 18,Channel 19,Channel 20,Channel 21,Channel 22,Channel 23,Channel 24,Channel 25,Channel 26,Channel 27,Channel 28,Channel 29,Channel 30,Channel 31"
|
|
newline
|
|
line.long 0x04 "MAGINT2 MASK,Magnitude Interrupt Mask 2 "
|
|
bitfld.long 0x04 11. " MAG_INT2 _MASK[11] ,Comparison for the Magnitude Threshold Interrupt 2 Mask 11" "Not masked,Masked"
|
|
bitfld.long 0x04 10. " [10] ,Comparison for the Magnitude Threshold Interrupt 2 Mask 10" "Not masked,Masked"
|
|
bitfld.long 0x04 9. " [9] ,Comparison for the Magnitude Threshold Interrupt 2 Mask 9" "Not masked,Masked"
|
|
newline
|
|
bitfld.long 0x04 8. " [8] ,Comparison for the Magnitude Threshold Interrupt 2 Mask 8" "Not masked,Masked"
|
|
bitfld.long 0x04 7. " [7] ,Comparison for the Magnitude Threshold Interrupt 2 Mask 7" "Not masked,Masked"
|
|
bitfld.long 0x04 6. " [6] ,Comparison for the Magnitude Threshold Interrupt 2 Mask 6" "Not masked,Masked"
|
|
newline
|
|
bitfld.long 0x04 5. " [5] ,Comparison for the Magnitude Threshold Interrupt 2 Mask 5" "Not masked,Masked"
|
|
bitfld.long 0x04 4. " [4] ,Comparison for the Magnitude Threshold Interrupt 1 Mask 4" "Not masked,Masked"
|
|
bitfld.long 0x04 3. " [3] ,Comparison for the Magnitude Threshold Interrupt 2 Mask 3" "Not masked,Masked"
|
|
newline
|
|
bitfld.long 0x04 2. " [2] ,Comparison for the Magnitude Threshold Interrupt 2 Mask 2" "Not masked,Masked"
|
|
bitfld.long 0x04 1. " [1] ,Comparison for the Magnitude Threshold Interrupt 2 Mask 1" "Not masked,Masked"
|
|
bitfld.long 0x04 0. " [0] ,Comparison for the Magnitude Threshold Interrupt 2 Mask 0" "Not masked,Masked"
|
|
newline
|
|
else
|
|
group.long 0x128++0x07
|
|
line.long 0x0 "MAGINT2 CR,Magnitude Interrupt 2 Control Register"
|
|
sif cpuis("TMS570LS0714*")||cpuis("TMS570LS0914*")
|
|
hexmask.long.word 0x00 16.--25. 1. " MAG_THR2 ,Compare Value"
|
|
bitfld.long 0x00 15. " CHN/THR_COMP2 , Channel OR Threshold Comparison" "Threshold,Channel"
|
|
bitfld.long 0x00 14. " CMP_GE/LT2 , Greater than or equal to OR Less than comparison operator" "Lower,Greater"
|
|
newline
|
|
bitfld.long 0x00 8.--12. " COMP_CHID1[4:0] ,COMP CHID1 [4:0]" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,Channel 8,Channel 9,Channel 10,Channel 11,Channel 12,Channel 13,Channel 14,Channel 15,Channel 16,Channel 17,Channel 18,Channel 19,Channel 20,Channel 21,Channel 22,Channel 23,Channel 24,Channel 25,Channel 26,Channel 27,Channel 28,Channel 29,Channel 30,Channel 31"
|
|
bitfld.long 0x00 0.--4. " MAG_CHID2 [4:0] ,MAG CHID2 [4:0]" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,Channel 8,Channel 9,Channel 10,Channel 11,Channel 12,Channel 13,Channel 14,Channel 15,Channel 16,Channel 17,Channel 18,Channel 19,Channel 20,Channel 21,Channel 22,Channel 23,Channel 24,Channel 25,Channel 26,Channel 27,Channel 28,Channel 29,Channel 30,Channel 31"
|
|
else
|
|
bitfld.long 0x00 26.--30. " MAG_CHID2 [4:0] ,MAG CHID2 [4:0]" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,Channel 8,Channel 9,Channel 10,Channel 11,Channel 12,Channel 13,Channel 14,Channel 15,Channel 16,Channel 17,Channel 18,Channel 19,Channel 20,Channel 21,Channel 22,Channel 23,Channel 24,Channel 25,Channel 26,Channel 27,Channel 28,Channel 29,Channel 30,Channel 31"
|
|
hexmask.long.word 0x00 16.--25. 1. " MAG_THR2 ,Compare Value"
|
|
bitfld.long 0x00 8.--12. " COMP_CHID2 [4:0] ,COMP CHID1 [4:0]" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,Channel 8,Channel 9,Channel 10,Channel 11,Channel 12,Channel 13,Channel 14,Channel 15,Channel 16,Channel 17,Channel 18,Channel 19,Channel 20,Channel 21,Channel 22,Channel 23,Channel 24,Channel 25,Channel 26,Channel 27,Channel 28,Channel 29,Channel 30,Channel 31"
|
|
newline
|
|
bitfld.long 0x00 1. " CHN/THR_COMP2 , Channel OR Threshold Comparison" "Threshold,Channel"
|
|
bitfld.long 0x00 0. " CMP_GE/LT2 , Greater than or equal to OR Less than comparison operator" "Lower,Greater"
|
|
endif
|
|
newline
|
|
line.long 0x04 "MAGINT2 MASK,Magnitude Interrupt Mask 2 "
|
|
bitfld.long 0x04 9. " MAG_INT2 _MASK[9] ,Comparison for the magnitude threshold interrupt 2 Mask 9" "Not masked,Masked"
|
|
bitfld.long 0x04 8. " [8] ,Comparison for the magnitude threshold interrupt 2 Mask 8" "Not masked,Masked"
|
|
bitfld.long 0x04 7. " [7] ,Comparison for the magnitude threshold interrupt 2 Mask 7" "Not masked,Masked"
|
|
newline
|
|
bitfld.long 0x04 6. " [6] ,Comparison for the magnitude threshold interrupt 2 Mask 6" "Not masked,Masked"
|
|
bitfld.long 0x04 5. " [5] ,Comparison for the magnitude threshold interrupt 2 Mask 5" "Not masked,Masked"
|
|
bitfld.long 0x04 4. " [4] ,Comparison for the magnitude threshold interrupt 1 Mask 4" "Not masked,Masked"
|
|
newline
|
|
bitfld.long 0x04 3. " [3] ,Comparison for the magnitude threshold interrupt 2 Mask 3" "Not masked,Masked"
|
|
bitfld.long 0x04 2. " [2] ,Comparison for the magnitude threshold interrupt 2 Mask 2" "Not masked,Masked"
|
|
newline
|
|
bitfld.long 0x04 1. " [1] ,Comparison for the magnitude threshold interrupt 2 Mask 1" "Not masked,Masked"
|
|
bitfld.long 0x04 0. " [0] ,Comparison for the magnitude threshold interrupt 2 Mask 0" "Not masked,Masked"
|
|
newline
|
|
endif
|
|
if ((per.l.be(ad:0xFFF7C000+0x04)&0x80000000)==0x80000000)
|
|
group.long 0x128++0x07
|
|
line.long 0x0 "MAGINT3 CR,Magnitude Interrupt 3 Control Register"
|
|
hexmask.long.word 0x00 16.--27. 1. " MAG_THR3 ,Compare Value"
|
|
bitfld.long 0x00 15. " CHN/THR_COMP3 , Channel OR Threshold Comparison" "Threshold,Channel"
|
|
bitfld.long 0x00 14. " CMP_GE/LT3 , Greater than or equal to OR Less than comparison operator" "Lower,Greater"
|
|
newline
|
|
bitfld.long 0x00 8.--12. " COMP_CHID1[4:0] ,COMP CHID1 [4:0]" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,Channel 8,Channel 9,Channel 10,Channel 11,Channel 12,Channel 13,Channel 14,Channel 15,Channel 16,Channel 17,Channel 18,Channel 19,Channel 20,Channel 21,Channel 22,Channel 23,Channel 24,Channel 25,Channel 26,Channel 27,Channel 28,Channel 29,Channel 30,Channel 31"
|
|
bitfld.long 0x00 0.--4. " MAG_CHID3 [4:0] ,MAG CHID3 [4:0]" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,Channel 8,Channel 9,Channel 10,Channel 11,Channel 12,Channel 13,Channel 14,Channel 15,Channel 16,Channel 17,Channel 18,Channel 19,Channel 20,Channel 21,Channel 22,Channel 23,Channel 24,Channel 25,Channel 26,Channel 27,Channel 28,Channel 29,Channel 30,Channel 31"
|
|
newline
|
|
line.long 0x04 "MAGINT3 MASK,Magnitude Interrupt Mask 3 "
|
|
bitfld.long 0x04 11. " MAG_INT3 _MASK[11] ,Comparison for the Magnitude Threshold Interrupt 3 Mask 11" "Not masked,Masked"
|
|
bitfld.long 0x04 10. " [10] ,Comparison for the Magnitude Threshold Interrupt 3 Mask 10" "Not masked,Masked"
|
|
bitfld.long 0x04 9. " [9] ,Comparison for the Magnitude Threshold Interrupt 3 Mask 9" "Not masked,Masked"
|
|
newline
|
|
bitfld.long 0x04 8. " [8] ,Comparison for the Magnitude Threshold Interrupt 3 Mask 8" "Not masked,Masked"
|
|
bitfld.long 0x04 7. " [7] ,Comparison for the Magnitude Threshold Interrupt 3 Mask 7" "Not masked,Masked"
|
|
bitfld.long 0x04 6. " [6] ,Comparison for the Magnitude Threshold Interrupt 3 Mask 6" "Not masked,Masked"
|
|
newline
|
|
bitfld.long 0x04 5. " [5] ,Comparison for the Magnitude Threshold Interrupt 3 Mask 5" "Not masked,Masked"
|
|
bitfld.long 0x04 4. " [4] ,Comparison for the Magnitude Threshold Interrupt 1 Mask 4" "Not masked,Masked"
|
|
bitfld.long 0x04 3. " [3] ,Comparison for the Magnitude Threshold Interrupt 3 Mask 3" "Not masked,Masked"
|
|
newline
|
|
bitfld.long 0x04 2. " [2] ,Comparison for the Magnitude Threshold Interrupt 3 Mask 2" "Not masked,Masked"
|
|
bitfld.long 0x04 1. " [1] ,Comparison for the Magnitude Threshold Interrupt 3 Mask 1" "Not masked,Masked"
|
|
bitfld.long 0x04 0. " [0] ,Comparison for the Magnitude Threshold Interrupt 3 Mask 0" "Not masked,Masked"
|
|
newline
|
|
else
|
|
group.long 0x128++0x07
|
|
line.long 0x0 "MAGINT3 CR,Magnitude Interrupt 3 Control Register"
|
|
sif cpuis("TMS570LS0714*")||cpuis("TMS570LS0914*")
|
|
hexmask.long.word 0x00 16.--25. 1. " MAG_THR3 ,Compare Value"
|
|
bitfld.long 0x00 15. " CHN/THR_COMP3 , Channel OR Threshold Comparison" "Threshold,Channel"
|
|
bitfld.long 0x00 14. " CMP_GE/LT3 , Greater than or equal to OR Less than comparison operator" "Lower,Greater"
|
|
newline
|
|
bitfld.long 0x00 8.--12. " COMP_CHID1[4:0] ,COMP CHID1 [4:0]" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,Channel 8,Channel 9,Channel 10,Channel 11,Channel 12,Channel 13,Channel 14,Channel 15,Channel 16,Channel 17,Channel 18,Channel 19,Channel 20,Channel 21,Channel 22,Channel 23,Channel 24,Channel 25,Channel 26,Channel 27,Channel 28,Channel 29,Channel 30,Channel 31"
|
|
bitfld.long 0x00 0.--4. " MAG_CHID3 [4:0] ,MAG CHID3 [4:0]" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,Channel 8,Channel 9,Channel 10,Channel 11,Channel 12,Channel 13,Channel 14,Channel 15,Channel 16,Channel 17,Channel 18,Channel 19,Channel 20,Channel 21,Channel 22,Channel 23,Channel 24,Channel 25,Channel 26,Channel 27,Channel 28,Channel 29,Channel 30,Channel 31"
|
|
else
|
|
bitfld.long 0x00 26.--30. " MAG_CHID3 [4:0] ,MAG CHID3 [4:0]" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,Channel 8,Channel 9,Channel 10,Channel 11,Channel 12,Channel 13,Channel 14,Channel 15,Channel 16,Channel 17,Channel 18,Channel 19,Channel 20,Channel 21,Channel 22,Channel 23,Channel 24,Channel 25,Channel 26,Channel 27,Channel 28,Channel 29,Channel 30,Channel 31"
|
|
hexmask.long.word 0x00 16.--25. 1. " MAG_THR3 ,Compare Value"
|
|
bitfld.long 0x00 8.--12. " COMP_CHID3 [4:0] ,COMP CHID1 [4:0]" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,Channel 8,Channel 9,Channel 10,Channel 11,Channel 12,Channel 13,Channel 14,Channel 15,Channel 16,Channel 17,Channel 18,Channel 19,Channel 20,Channel 21,Channel 22,Channel 23,Channel 24,Channel 25,Channel 26,Channel 27,Channel 28,Channel 29,Channel 30,Channel 31"
|
|
newline
|
|
bitfld.long 0x00 1. " CHN/THR_COMP3 , Channel OR Threshold Comparison" "Threshold,Channel"
|
|
bitfld.long 0x00 0. " CMP_GE/LT3 , Greater than or equal to OR Less than comparison operator" "Lower,Greater"
|
|
endif
|
|
newline
|
|
line.long 0x04 "MAGINT3 MASK,Magnitude Interrupt Mask 3 "
|
|
bitfld.long 0x04 9. " MAG_INT3 _MASK[9] ,Comparison for the magnitude threshold interrupt 3 Mask 9" "Not masked,Masked"
|
|
bitfld.long 0x04 8. " [8] ,Comparison for the magnitude threshold interrupt 3 Mask 8" "Not masked,Masked"
|
|
bitfld.long 0x04 7. " [7] ,Comparison for the magnitude threshold interrupt 3 Mask 7" "Not masked,Masked"
|
|
newline
|
|
bitfld.long 0x04 6. " [6] ,Comparison for the magnitude threshold interrupt 3 Mask 6" "Not masked,Masked"
|
|
bitfld.long 0x04 5. " [5] ,Comparison for the magnitude threshold interrupt 3 Mask 5" "Not masked,Masked"
|
|
bitfld.long 0x04 4. " [4] ,Comparison for the magnitude threshold interrupt 1 Mask 4" "Not masked,Masked"
|
|
newline
|
|
bitfld.long 0x04 3. " [3] ,Comparison for the magnitude threshold interrupt 3 Mask 3" "Not masked,Masked"
|
|
bitfld.long 0x04 2. " [2] ,Comparison for the magnitude threshold interrupt 3 Mask 2" "Not masked,Masked"
|
|
newline
|
|
bitfld.long 0x04 1. " [1] ,Comparison for the magnitude threshold interrupt 3 Mask 1" "Not masked,Masked"
|
|
bitfld.long 0x04 0. " [0] ,Comparison for the magnitude threshold interrupt 3 Mask 0" "Not masked,Masked"
|
|
newline
|
|
endif
|
|
width 22.
|
|
newline
|
|
group.long 0x160++0x3
|
|
line.long 0x0 "MAGTHRINTFLG_SET/CLR,Magnitude Threshold Interrupt Flag Set/Clear Register"
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " MAG_THR_INT[2] ,Magnitude threshold interrupt flag bit[2]" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " [1] ,Magnitude threshold interrupt flag bit[1]" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " [0] ,Magnitude threshold interrupt flag bit[0]" "No interrupt,Interrupt"
|
|
group.long 0x164++0x3
|
|
line.long 0x0 "MAGTHRINTOFFSET,Magnitude Threshold Interrupt Offset Register"
|
|
hexmask.long.byte 0x00 0.--3. 0x01 " INT_OFF[3:0] ,Magnitude Threshold Interrupt Offset"
|
|
tree.end
|
|
newline
|
|
group.long 0x180++0x3
|
|
line.long 0x0 "PARCR,Parity Control Register"
|
|
bitfld.long 0x00 8. " TEST ,Parity Bits Map" "Not mapped,Mapped"
|
|
bitfld.long 0x00 0.--3. " PARITY_ENA[3:0] ,Enable/Disable Parity Checking" "Enabled,Enabled,Enabled,Enabled,Enabled,Disabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled"
|
|
rgroup.long 0x184++0x3
|
|
line.long 0x0 "PARADDR,Parity Address"
|
|
hexmask.long.word 0x00 2.--11. 0x4 " ERROR_ADDRESS ,ERROR ADDRESS"
|
|
group.long 0x188++0x03
|
|
line.long 0x00 "PWRUPDLYCTRL, ADC Power-Up Delay Control Register"
|
|
hexmask.long.word 0x00 0.--9. 1. " PWRUP_DLY , Number Of VCLK Cycles"
|
|
width 0x0B
|
|
tree.end
|
|
else
|
|
tree "ADC (Analog To Digital Converter Module)"
|
|
base ad:0xFFF7C000
|
|
width 10.
|
|
group.long 0x00++0x3
|
|
line.long 0x0 "RSTCR,Reset Control Register"
|
|
bitfld.long 0x00 0. " RESET ,ADC Reset" "No reset,Reset"
|
|
group.long 0x04++0x3
|
|
line.long 0x0 "OPMODECR,Operating Mode Control Register"
|
|
bitfld.long 0x00 31. " 10/12_BIT ,Resolution of the ADC core" "10-bit,12-bit"
|
|
bitfld.long 0x00 24. " COS ,Continue on Suspend Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 17.--20. " CHN_TEST_EN ,ADC Channel Test Enable" "Disabled,Disabled,Disabled,Disabled,Disabled,Enabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled"
|
|
bitfld.long 0x00 16. " RAM_TEST_EN ,ADC RAM Test Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8. " POWERDOWN ,ADC Internal Clocks Powerdown Mode" "Normal,Power-down"
|
|
bitfld.long 0x00 4. " NORMAL ,ADC Power Down When Idle" "Normal,Power-down"
|
|
textline " "
|
|
bitfld.long 0x00 0. " ADC_EN ,ADC Enable" "Disabled,Enabled"
|
|
group.long 0x08++0x3
|
|
line.long 0x0 "CLOCKCR,Clock Prescaler"
|
|
bitfld.long 0x00 0.--4. " PS[4:0] ,ADC Clock Prescaler" "1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles,16 cycles,17 cycles,18 cycles,19 cycles,20 cycles,21 cycles,22 cycles,23 cycles,24 cycles,25 cycles,26 cycles,27 cycles,28 cycles,29 cycles,30 cycles,31 cycles,32 cycles"
|
|
if (((d.l((ad:0xFFF7C000+0x0c)))&0x01000201)==0x00000001)
|
|
group.long (0x0c)++0x03
|
|
line.long 0x00 "CALCR,Calibration Conversion Register"
|
|
bitfld.long 0x00 24. " SELF_TEST ,Self-Test Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " CAL_ST ,Calibration Conversion Start" "No effect/completed,Started"
|
|
textline " "
|
|
bitfld.long 0x00 9. " BRIDGE_EN ,Bridge Enable" "Midpoint,Full"
|
|
bitfld.long 0x00 8. " HILO ,Test and Reference Source Selection" "(AD_REFHI*R1+AD_REFLO*R2)/(R1+R2),(AD_REFLO*R1+AD_REFHI*R2)/(R1+R2)"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CAL_EN ,Calibration Enable" "Disabled,Enabled"
|
|
elif (((d.l((ad:0xFFF7C000+0x0c)))&0x01000201)==0x01000000)
|
|
group.long (0x0c)++0x03
|
|
line.long 0x00 "CALCR,Calibration Conversion Register"
|
|
bitfld.long 0x00 24. " SELF_TEST ,Self-Test Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " CAL_ST ,Calibration Conversion Start" "No effect/completed,Started"
|
|
textline " "
|
|
bitfld.long 0x00 9. " BRIDGE_EN ,Bridge Enable" "Midpoint,Full"
|
|
bitfld.long 0x00 8. " HILO ,Test and Reference Source Selection" "(AD_REFLO via R1)||(R2 to Vin),(AD_REFHI via R1)||(R2 to Vin)"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CAL_EN ,Calibration Enable" "Disabled,Enabled"
|
|
elif (((d.l((ad:0xFFF7C000+0x0c)))&0x01000201)==0x00000201)
|
|
group.long (0x0c)++0x03
|
|
line.long 0x00 "CALCR,Calibration Conversion Register"
|
|
bitfld.long 0x00 24. " SELF_TEST ,Self-Test Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " CAL_ST ,Calibration Conversion Start" "No effect/completed,Started"
|
|
textline " "
|
|
bitfld.long 0x00 9. " BRIDGE_EN ,Bridge Enable" "Midpoint,Full"
|
|
bitfld.long 0x00 8. " HILO ,Test and Reference Source Selection" "AD_REFLO,AD_REFHI"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CAL_EN ,Calibration Enable" "Disabled,Enabled"
|
|
elif (((d.l((ad:0xFFF7C000+0x0c)))&0x01000201)==0x01000200)
|
|
group.long (0x0c)++0x03
|
|
line.long 0x00 "CALCR,Calibration Conversion Register"
|
|
bitfld.long 0x00 24. " SELF_TEST ,Self-Test Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " CAL_ST ,Calibration Conversion Start" "No effect/completed,Started"
|
|
textline " "
|
|
bitfld.long 0x00 9. " BRIDGE_EN ,Bridge Enable" "Midpoint,Full"
|
|
bitfld.long 0x00 8. " HILO ,Test and Reference Source Selection" "(AD_REFLO via R1)||(R2 to Vin),(AD_REFHI via R1)||(R2 to Vin)"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CAL_EN ,Calibration Enable" "Disabled,Enabled"
|
|
else
|
|
group.long (0x0c)++0x03
|
|
line.long 0x00 "CALCR,Calibration Conversion Register"
|
|
bitfld.long 0x00 24. " SELF_TEST ,Self-Test Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " CAL_ST ,Calibration Conversion Start" "No effect/completed,Started"
|
|
textline " "
|
|
bitfld.long 0x00 9. " BRIDGE_EN ,Bridge Enable" "Midpoint,Full"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CAL_EN ,Calibration Enable" "Disabled,Enabled"
|
|
endif
|
|
width 13.
|
|
tree "Event Group Registers"
|
|
group.long (0x0+0x10)++0x3
|
|
line.long 0x0 "EVMODECR,Event Group MODE Control Register"
|
|
bitfld.long 0x00 16. " NO_RESET_ON_CHNSEL ,No Event Group Results Memory Reset on New Channel Select" "Reset,No reset"
|
|
bitfld.long 0x00 8.--9. " EV_DATA_FMT ,Event Group (Read) Data Format" "12 bit,10 bit,8 bit,?..."
|
|
textline " "
|
|
bitfld.long 0x00 5. " EV_CHID ,Channel ID Mode for the Event Group" "Forced to 0,ID of A/D channel"
|
|
bitfld.long 0x00 4. " OVR_EV_RAM_IGN ,Overrun Event Group RAM Ignore" "Not ignored,Ignored"
|
|
textline " "
|
|
bitfld.long 0x00 2. " EV_8BIT ,Event Group 8-bit result mode" "10-bit,8-bit"
|
|
bitfld.long 0x00 1. " EV_MODE ,Event mode" "Single,Continuous"
|
|
textline " "
|
|
bitfld.long 0x00 0. " FRZ_EV ,Freeze conversion Event Group" "Completed,Frozen"
|
|
group.long (0x0+0x1C)++0x3
|
|
line.long 0x0 "EVSRC,Event Group Trigger Source Select"
|
|
bitfld.long 0x00 4. " EV_EDG_BOTH ,Event Group Trigger Edge Polarity Select" "Defined edge,Any edge"
|
|
bitfld.long 0x00 3. " EV_EDG_SEL ,ADC Event Group Trigger Edge Select" "High/low,Low/high"
|
|
textline " "
|
|
bitfld.long 0x00 0.--2. " EVSRC[2:0] ,Event Group Trigger Source Select" "ADEVT,Internal,Internal,Internal,Internal,Internal,Internal,Internal"
|
|
group.long (0x0+0x28)++0x3
|
|
line.long 0x0 "EVINTENA,Event Group Interrupt Enable"
|
|
bitfld.long 0x00 3. " EV_END_INT_EN ,Event Group Conversion End Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " EV_OVR_INT_EN ,Event Group Memory Overrun Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " EV_THR_INT_EN ,Event Group Memory Threshold Interrupt Enable" "Disabled,Enabled"
|
|
group.long (0x0+0x34)++0x3
|
|
line.long 0x0 "EVINTFLG,Event Group Interrupt Flag"
|
|
eventfld.long 0x00 3. " EV_END ,Event Group Conversion End" "Not converted,Converted"
|
|
rbitfld.long 0x00 2. " EV_MEM_EMPTY ,Event Group FIFO Empty Status" "Not empty,Empty"
|
|
textline " "
|
|
rbitfld.long 0x00 1. " EV_MEM_OVERFLOW ,Event Group Memory Overrun Flag" "No overrun,Overrun"
|
|
eventfld.long 0x00 0. " EV_THR_INT_FLAG ,Event Group Threshold Interrupt Flag" "No interrupt,Interrupt"
|
|
group.long (0x0+0x40)++0x3
|
|
line.long 0x0 "EVINTCR,Event Group Interrupt Threshold Counter"
|
|
hexmask.long.byte 0x00 9.--15. 1. " SIGN_EXTENSION ,Sign Extension"
|
|
hexmask.long.word 0x00 0.--8. 1. " EV_THR[8:0] ,Event Group Interrupt Threshold Counter"
|
|
group.long (0x0+0x4C)++0x3
|
|
line.long 0x0 "EVDMACR,Event Group DMA Control Register"
|
|
hexmask.long.word 0x00 16.--24. 1. " EVBLOCKS[8:0] ,Number of Event Group Memory Buffers to be Transferred"
|
|
bitfld.long 0x00 3. " DMA_EV_END ,Event Group Conversion End DMA Transfer Enable" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 2. " EV_BLK_XFER ,Event Group Block DMA Transfer Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " EV_DMA_EN ,Event Group DMA Transfer Enable" "Disabled,Enabled"
|
|
group.long (0x0+0x60)++0x3
|
|
line.long 0x0 "EVSAMP,Event Group Sample Window"
|
|
hexmask.long.word 0x00 0.--11. 1. " EV_ACQ ,Event Group Acquisition Prescale Bits"
|
|
group.long (0x0+0x6C)++0x3
|
|
line.long 0x0 "EVSR,Event Group Status Register"
|
|
rbitfld.long 0x00 3. " EV_MEM_EMPTY ,Event Group Memory Empty" "Not empty,Empty"
|
|
rbitfld.long 0x00 2. " EV_BUSY ,Event Group Conversion-Busy Flag" "Not active,Busy"
|
|
textline " "
|
|
rbitfld.long 0x00 1. " EV_STOP ,Event Group Conversion Stopped Flag" "Not frozen,Frozen"
|
|
eventfld.long 0x00 0. " EV_END ,Event Group Conversion-Ended Flag R/W" "Not completed,Completed"
|
|
group.long (0x0+0x78)++0x3
|
|
line.long 0x0 "EVSEL,Event Group select register"
|
|
bitfld.long 0x00 23. " EVCHNSEL [23] ,A/D Event Group Channel 23 Selection Bit" "Not converted,Converted"
|
|
bitfld.long 0x00 22. " [22] ,A/D Event Group Channel 22 Selection Bit" "Not converted,Converted"
|
|
bitfld.long 0x00 21. " [21] ,A/D Event Group Channel 21 Selection Bit" "Not converted,Converted"
|
|
bitfld.long 0x00 20. " [20] ,A/D Event Group Channel 20 Selection Bit" "Not converted,Converted"
|
|
textline " "
|
|
bitfld.long 0x00 19. " [19] ,A/D Event Group Channel 19 Selection Bit" "Not converted,Converted"
|
|
bitfld.long 0x00 18. " [18] ,A/D Event Group Channel 18 Selection Bit" "Not converted,Converted"
|
|
bitfld.long 0x00 17. " [17] ,A/D Event Group Channel 17 Selection Bit" "Not converted,Converted"
|
|
bitfld.long 0x00 16. " [16] ,A/D Event Group Channel 16 Selection Bit" "Not converted,Converted"
|
|
textline " "
|
|
bitfld.long 0x00 15. " [15] ,A/D Event Group Channel 15 Selection Bit" "Not converted,Converted"
|
|
bitfld.long 0x00 14. " [14] ,A/D Event Group Channel 14 Selection Bit" "Not converted,Converted"
|
|
bitfld.long 0x00 13. " [13] ,A/D Event Group Channel 13 Selection Bit" "Not converted,Converted"
|
|
bitfld.long 0x00 12. " [12] ,A/D Event Group Channel 12 Selection Bit" "Not converted,Converted"
|
|
textline " "
|
|
bitfld.long 0x00 11. " [11] ,A/D Event Group Channel 11 Selection Bit" "Not converted,Converted"
|
|
bitfld.long 0x00 10. " [10] ,A/D Event Group Channel 10 Selection Bit" "Not converted,Converted"
|
|
bitfld.long 0x00 9. " [9] ,A/D Event Group Channel 9 Selection Bit" "Not converted,Converted"
|
|
bitfld.long 0x00 8. " [8] ,A/D Event Group Channel 8 Selection Bit" "Not converted,Converted"
|
|
textline " "
|
|
bitfld.long 0x00 7. " [7] ,A/D Event Group Channel 7 Selection Bit" "Not converted,Converted"
|
|
bitfld.long 0x00 6. " [6] ,A/D Event Group Channel 6 Selection Bit" "Not converted,Converted"
|
|
bitfld.long 0x00 5. " [5] ,A/D Event Group Channel 5 Selection Bit" "Not converted,Converted"
|
|
bitfld.long 0x00 4. " [4] ,A/D Event Group Channel 4 Selection Bit" "Not converted,Converted"
|
|
textline " "
|
|
bitfld.long 0x00 3. " [3] ,A/D Event Group Channel 3 Selection Bit" "Not converted,Converted"
|
|
bitfld.long 0x00 2. " [2] ,A/D Event Group Channel 2 Selection Bit" "Not converted,Converted"
|
|
bitfld.long 0x00 1. " [1] ,A/D Event Group Channel 1 Selection Bit" "Not converted,Converted"
|
|
bitfld.long 0x00 0. " [0] ,A/D Event Group Channel 0 Selection Bit" "Not converted,Converted"
|
|
hgroup.long (0x0+0x90)++0x3
|
|
hide.long 0x0 "EVBUFFER0,Event Group Buffer 0"
|
|
in
|
|
hgroup.long (0x0+0x94)++0x3
|
|
hide.long 0x0 "EVBUFFER1,Event Group Buffer 1"
|
|
in
|
|
hgroup.long (0x0+0x98)++0x3
|
|
hide.long 0x0 "EVBUFFER2,Event Group Buffer 2"
|
|
in
|
|
hgroup.long (0x0+0x9C)++0x3
|
|
hide.long 0x0 "EVBUFFER3,Event Group Buffer 3"
|
|
in
|
|
hgroup.long (0x0+0xA0)++0x3
|
|
hide.long 0x0 "EVBUFFER4,Event Group Buffer 4"
|
|
in
|
|
hgroup.long (0x0+0xA4)++0x3
|
|
hide.long 0x0 "EVBUFFER5,Event Group Buffer 5"
|
|
in
|
|
hgroup.long (0x0+0xA8)++0x3
|
|
hide.long 0x0 "EVBUFFER6,Event Group Buffer 6"
|
|
in
|
|
hgroup.long (0x0+0xAC)++0x3
|
|
hide.long 0x0 "EVBUFFER7,Event Group Buffer 7"
|
|
in
|
|
if ((d.l(ad:0xFFF7C000+0x04)&0x80000000)==0x80000000)
|
|
group.long (0x0+0xF0)++0x3
|
|
line.long 0x0 "EVEMUBUFFER,Event Group EMU Buffer"
|
|
bitfld.long 0x00 31. " EV_EMPTY ,Event Group FIFO Empty" "Not empty,Empty"
|
|
bitfld.long 0x00 16.--20. " EVCHID[4:0] ,Event Group Channel ID" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,Channel 8,Channel 9,Channel 10,Channel 11,Channel 12,Channel 13,Channel 14,Channel 15,Channel 16,Channel 17,Channel 18,Channel 19,Channel 20,Channel 21,Channel 22,Channel 23,Channel 24,Channel 25,Channel 26,Channel 27,Channel 28,Channel 29,Channel 30,Channel 31"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--11. 1. " EVDR[11:0] ,Event Group Digital Result"
|
|
else
|
|
group.long (0x0+0xF0)++0x3
|
|
line.long 0x0 "EVEMUBUFFER,Event Group EMU Buffer"
|
|
bitfld.long 0x00 15. " EV_EMPTY ,Event Group FIFO Empty" "Not empty,Empty"
|
|
bitfld.long 0x00 10.--14. " EVCHID[4:0] ,Event Group Channel ID" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,Channel 8,Channel 9,Channel 10,Channel 11,Channel 12,Channel 13,Channel 14,Channel 15,Channel 16,Channel 17,Channel 18,Channel 19,Channel 20,Channel 21,Channel 22,Channel 23,Channel 24,Channel 25,Channel 26,Channel 27,Channel 28,Channel 29,Channel 30,Channel 31"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--9. 1. " EVDR[9:0] ,Event Group Digital Result"
|
|
endif
|
|
width 9.
|
|
tree "ADC ADEVT Pin Control Registers"
|
|
group.long 0xFC++0x3
|
|
line.long 0x0 "EVTDIR,Event Group pin direction selection"
|
|
bitfld.long 0x00 0. " EVT_DIR ,ADEVT Pin Direction Selection" "Input,Output"
|
|
if (((d.l((ad:0xFFF7C000+0xfc)))&0x01)==0x01)
|
|
group.long 0x100++0x3
|
|
line.long 0x0 "EVTOUT,Event Group pin data output"
|
|
bitfld.long 0x00 0. " EVT_OUT ,ADEVT Pin Data Output" "Low,High"
|
|
else
|
|
hgroup.long 0x100++0x3
|
|
hide.long 0x0 "EVTOUT,Event Group pin data output"
|
|
endif
|
|
rgroup.long 0x104++0x3
|
|
line.long 0x0 "EVTIN,Event Group pin input value"
|
|
bitfld.long 0x00 0. " EVT_IN ,ADEVT Pin Input Value" "Low,High"
|
|
group.long 0x108++0x3
|
|
line.long 0x0 "EVTSET,Event Group pin set"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x04 0. " ADEVT_set/clr ,ADEVT Pin Set" "Low,High"
|
|
if ((((d.l((ad:0xFFF7C000+0xfc)))&0x01)==0x01)&&(((d.l((ad:0xFFF7C000+0x0100)))&0x01)==0x01))
|
|
group.long 0x110++0x3
|
|
line.long 0x0 "EVTPDR,Event Group pin open-drain enable"
|
|
bitfld.long 0x00 0. " ADEVT_PDR ,ADEVT Pin Open-Drain Enable" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0x110++0x3
|
|
hide.long 0x0 "EVTPDR,Event Group pin open-drain enable"
|
|
endif
|
|
if (((d.l((ad:0xFFF7C000+0xfc)))&0x01)==0x00)
|
|
group.long 0x114++0x3
|
|
line.long 0x0 "EVTPDIS,Event Group pin pull control enable"
|
|
bitfld.long 0x00 0. " ADEVT_PDIS ,ADEVT Pin Pull Control Enable" "Enabled,Disabled"
|
|
group.long 0x118++0x3
|
|
line.long 0x0 "EVTPSEL,Event Group pull select"
|
|
bitfld.long 0x00 0. " ADEVT_PSEL ,ADEVT Pull Select" "Pull-down,Pull-up"
|
|
else
|
|
hgroup.long 0x114++0x3
|
|
hide.long 0x0 "EVTPDIS,Event Group pin pull control enable"
|
|
hgroup.long 0x118++0x3
|
|
hide.long 0x0 "EVTPSEL,Event Group pull select"
|
|
endif
|
|
tree.end
|
|
width 18.
|
|
group.long (0x0+0x11C)++0x3
|
|
line.long 0x0 "EVSAMPDISEN,Event Group Sampling Capacitor Discharge Mode"
|
|
hexmask.long.byte 0x00 8.--15. 1. " EV_SAMP_DIS_CYC[7:0] ,ADC Sampling Capacitor is Dicharged Cycles"
|
|
bitfld.long 0x00 0. " EV_SAMP_DIS_EN ,Sampling Capacitor Discharge Mode" "Disabled,Enabled"
|
|
group.long (0x0+0x168)++0x3
|
|
line.long 0x0 "EVFIFORESETCR,Event Group FIFO Reset"
|
|
bitfld.long 0x00 0. " EV_FIFO_RESET ,Reset the ADC Event Group FIFO" "No reset,Reset"
|
|
group.long (0x0+0x174)++0x3
|
|
line.long 0x0 "EVRAMADDR,Event Group ADC RAM Pointer"
|
|
hexmask.long.word 0x00 0.--8. 1. " EV_RAM_ADDR ,Event Group ADC RAM Pointer"
|
|
group.long (0x0+0x190)++0x03
|
|
line.long 0x00 "EVCHNSELMODECTRL, ADC Event Group Channel Selection Mode Control Register"
|
|
bitfld.long 0x00 0.--3. " EV_ENH_CHNSEL_MODE_ENABLE , Enable Enhanced Channel Selection Mode" ",,,,,Disabled,,,,,Enabled,?..."
|
|
group.long (0x0+0x19C)++0x07
|
|
line.long 0x00 "EVCURRCOUNT, ADC Event Group Current Count Register"
|
|
bitfld.long 0x00 0.--4. " EV_CURRENT_COUNT , Value For The Event Group Conversions" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
line.long 0x04 "EVMAXCOUNT, ADC Event Group Maximum Count Register"
|
|
bitfld.long 0x04 0.--4. " EV_MAX_COUNT , Value For The Event Group Conversions" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
tree.end
|
|
width 13.
|
|
tree "Group 1 Registers"
|
|
group.long (0x4+0x10)++0x3
|
|
line.long 0x0 "G1MODECR,Group 1 MODE Control Register"
|
|
bitfld.long 0x00 16. " NO_RESET_ON_CHNSEL ,No Group 1 Results Memory Reset on New Channel Select" "Reset,No reset"
|
|
bitfld.long 0x00 8.--9. " G1_DATA_FMT ,Group 1 (Read) Data Format" "12 bit,10 bit,8 bit,?..."
|
|
textline " "
|
|
bitfld.long 0x00 5. " G1_CHID ,Channel ID Mode for the Group 1" "Forced to 0,ID of A/D channel"
|
|
bitfld.long 0x00 4. " OVR_G1_RAM_IGN ,Overrun Event Group RAM Ignore" "Not ignored,Ignored"
|
|
textline " "
|
|
bitfld.long 0x00 3. " G1_HW_TRIG ,Group 1 Hardware Triggered" "Software,Event"
|
|
bitfld.long 0x00 2. " G1_SBIT ,Group1 8-bit result mode" "10-bit,8-bit"
|
|
textline " "
|
|
bitfld.long 0x00 1. " G1_MODE ,Group 1 mode" "Single,Continuous"
|
|
bitfld.long 0x00 0. " FRZ_G1 ,Freeze Conversion Group 1" "Completed,Frozen"
|
|
group.long (0x4+0x1C)++0x3
|
|
line.long 0x0 "G1SRC,Group 1 Trigger Source Select"
|
|
bitfld.long 0x00 4. " G1_EDG_BOTH ,Group 1 Trigger Edge Polarity Select" "Defined edge,Any edge"
|
|
bitfld.long 0x00 3. " G1_EDG_SEL ,ADC Group 1 Trigger Edge Select" "High/low,Low/high"
|
|
textline " "
|
|
bitfld.long 0x00 0.--2. " G1SRC[2:0] ,Group 1 Trigger Source Select" "ADEVT,Internal,Internal,Internal,Internal,Internal,Internal,Internal"
|
|
group.long (0x4+0x28)++0x3
|
|
line.long 0x0 "G1INTENA,Group 1 Interrupt Enable"
|
|
bitfld.long 0x00 3. " G1_END_INT_EN ,Group 1 Conversion End Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " G1_OVR_INT_EN ,Group 1 Memory Overrun Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " G1_THR_INT_EN ,Group 1 Memory Threshold Interrupt Enable" "Disabled,Enabled"
|
|
group.long (0x4+0x34)++0x3
|
|
line.long 0x0 "G1INTFLG,Group 1 Interrupt Flag"
|
|
eventfld.long 0x00 3. " G1_END ,Group 1 Conversion End" "Not converted,Converted"
|
|
rbitfld.long 0x00 2. " G1_MEM_EMPTY ,Group 1 FIFO Empty Status" "Not empty,Empty"
|
|
textline " "
|
|
rbitfld.long 0x00 1. " G1_MEM_OVERFLOW ,Group 1 Memory Overrun Flag" "No overrun,Overrun"
|
|
eventfld.long 0x00 0. " G1_THR_INT_FLAG ,Group 1 Threshold Interrupt Flag" "No interrupt,Interrupt"
|
|
group.long (0x4+0x40)++0x3
|
|
line.long 0x0 "G1INTCR,Group 1 Interrupt Threshold Counter"
|
|
hexmask.long.byte 0x00 9.--15. 1. " SIGN_EXTENSION ,Sign Extension"
|
|
hexmask.long.word 0x00 0.--8. 1. " G1_THR[8:0] ,Group 1 Interrupt Threshold Counter"
|
|
group.long (0x4+0x4C)++0x3
|
|
line.long 0x0 "G1DMACR,Group 1 DMA Control Register"
|
|
hexmask.long.word 0x00 16.--24. 1. " G1BLOCKS[8:0] ,Number of Group 1 Memory Buffers to be Transferred"
|
|
bitfld.long 0x00 3. " DMA_G1_END ,Group 1 Conversion End DMA Transfer Enable" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 2. " G1_BLK_XFER ,Group 1 Block DMA Transfer Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " G1_DMA_EN ,Group 1 DMA Transfer Enable" "Disabled,Enabled"
|
|
group.long (0x4+0x60)++0x3
|
|
line.long 0x0 "G1SAMP,Group 1 Sample Window"
|
|
hexmask.long.word 0x00 0.--11. 1. " G1_ACQ ,Group 1 Acquisition Prescale Bits"
|
|
group.long (0x4+0x6C)++0x3
|
|
line.long 0x0 "G1SR,Group 1 Status Register"
|
|
rbitfld.long 0x00 3. " G1_MEM_EMPTY ,Group 1 Memory Empty" "Not empty,Empty"
|
|
rbitfld.long 0x00 2. " G1_BUSY ,Group 1 Conversion-Busy Flag" "Not active,Busy"
|
|
textline " "
|
|
rbitfld.long 0x00 1. " G1_STOP ,Group 1 Conversion Stopped Flag" "Not frozen,Frozen"
|
|
eventfld.long 0x00 0. " G1_END ,Group 1 Conversion-Ended Flag R/W" "Not completed,Completed"
|
|
group.long (0x4+0x78)++0x3
|
|
line.long 0x0 "G1SEL,Group 1 select register"
|
|
bitfld.long 0x00 23. " G1CHNSEL [23] ,A/D Group 1 Channel 23 Selection Bit" "Not converted,Converted"
|
|
bitfld.long 0x00 22. " [22] ,A/D Group 1 Channel 22 Selection Bit" "Not converted,Converted"
|
|
bitfld.long 0x00 21. " [21] ,A/D Group 1 Channel 21 Selection Bit" "Not converted,Converted"
|
|
bitfld.long 0x00 20. " [20] ,A/D Group 1 Channel 20 Selection Bit" "Not converted,Converted"
|
|
textline " "
|
|
bitfld.long 0x00 19. " [19] ,A/D Group 1 Channel 19 Selection Bit" "Not converted,Converted"
|
|
bitfld.long 0x00 18. " [18] ,A/D Group 1 Channel 18 Selection Bit" "Not converted,Converted"
|
|
bitfld.long 0x00 17. " [17] ,A/D Group 1 Channel 17 Selection Bit" "Not converted,Converted"
|
|
bitfld.long 0x00 16. " [16] ,A/D Group 1 Channel 16 Selection Bit" "Not converted,Converted"
|
|
textline " "
|
|
bitfld.long 0x00 15. " [15] ,A/D Group 1 Channel 15 Selection Bit" "Not converted,Converted"
|
|
bitfld.long 0x00 14. " [14] ,A/D Group 1 Channel 14 Selection Bit" "Not converted,Converted"
|
|
bitfld.long 0x00 13. " [13] ,A/D Group 1 Channel 13 Selection Bit" "Not converted,Converted"
|
|
bitfld.long 0x00 12. " [12] ,A/D Group 1 Channel 12 Selection Bit" "Not converted,Converted"
|
|
textline " "
|
|
bitfld.long 0x00 11. " [11] ,A/D Group 1 Channel 11 Selection Bit" "Not converted,Converted"
|
|
bitfld.long 0x00 10. " [10] ,A/D Group 1 Channel 10 Selection Bit" "Not converted,Converted"
|
|
bitfld.long 0x00 9. " [9] ,A/D Group 1 Channel 9 Selection Bit" "Not converted,Converted"
|
|
bitfld.long 0x00 8. " [8] ,A/D Group 1 Channel 8 Selection Bit" "Not converted,Converted"
|
|
textline " "
|
|
bitfld.long 0x00 7. " [7] ,A/D Group 1 Channel 7 Selection Bit" "Not converted,Converted"
|
|
bitfld.long 0x00 6. " [6] ,A/D Group 1 Channel 6 Selection Bit" "Not converted,Converted"
|
|
bitfld.long 0x00 5. " [5] ,A/D Group 1 Channel 5 Selection Bit" "Not converted,Converted"
|
|
bitfld.long 0x00 4. " [4] ,A/D Group 1 Channel 4 Selection Bit" "Not converted,Converted"
|
|
textline " "
|
|
bitfld.long 0x00 3. " [3] ,A/D Group 1 Channel 3 Selection Bit" "Not converted,Converted"
|
|
bitfld.long 0x00 2. " [2] ,A/D Group 1 Channel 2 Selection Bit" "Not converted,Converted"
|
|
bitfld.long 0x00 1. " [1] ,A/D Group 1 Channel 1 Selection Bit" "Not converted,Converted"
|
|
bitfld.long 0x00 0. " [0] ,A/D Group 1 Channel 0 Selection Bit" "Not converted,Converted"
|
|
hgroup.long (0x20+0x90)++0x3
|
|
hide.long 0x0 "G1BUFFER0,Group 1 Buffer 0"
|
|
in
|
|
hgroup.long (0x20+0x94)++0x3
|
|
hide.long 0x0 "G1BUFFER1,Group 1 Buffer 1"
|
|
in
|
|
hgroup.long (0x20+0x98)++0x3
|
|
hide.long 0x0 "G1BUFFER2,Group 1 Buffer 2"
|
|
in
|
|
hgroup.long (0x20+0x9C)++0x3
|
|
hide.long 0x0 "G1BUFFER3,Group 1 Buffer 3"
|
|
in
|
|
hgroup.long (0x20+0xA0)++0x3
|
|
hide.long 0x0 "G1BUFFER4,Group 1 Buffer 4"
|
|
in
|
|
hgroup.long (0x20+0xA4)++0x3
|
|
hide.long 0x0 "G1BUFFER5,Group 1 Buffer 5"
|
|
in
|
|
hgroup.long (0x20+0xA8)++0x3
|
|
hide.long 0x0 "G1BUFFER6,Group 1 Buffer 6"
|
|
in
|
|
hgroup.long (0x20+0xAC)++0x3
|
|
hide.long 0x0 "G1BUFFER7,Group 1 Buffer 7"
|
|
in
|
|
if ((d.l(ad:0xFFF7C000+0x04)&0x80000000)==0x80000000)
|
|
group.long (0x4+0xF0)++0x3
|
|
line.long 0x0 "G1EMUBUFFER,Group 1 EMU Buffer"
|
|
bitfld.long 0x00 31. " G1_EMPTY ,Group 1 FIFO Empty" "Not empty,Empty"
|
|
bitfld.long 0x00 16.--20. " G1CHID[4:0] ,Group 1 Channel ID" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,Channel 8,Channel 9,Channel 10,Channel 11,Channel 12,Channel 13,Channel 14,Channel 15,Channel 16,Channel 17,Channel 18,Channel 19,Channel 20,Channel 21,Channel 22,Channel 23,Channel 24,Channel 25,Channel 26,Channel 27,Channel 28,Channel 29,Channel 30,Channel 31"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--11. 1. " G1DR[11:0] ,Group 1 Digital Result"
|
|
else
|
|
group.long (0x4+0xF0)++0x3
|
|
line.long 0x0 "G1EMUBUFFER,Group 1 EMU Buffer"
|
|
bitfld.long 0x00 15. " G1_EMPTY ,Group 1 FIFO Empty" "Not empty,Empty"
|
|
bitfld.long 0x00 10.--14. " G1CHID[4:0] ,Group 1 Channel ID" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,Channel 8,Channel 9,Channel 10,Channel 11,Channel 12,Channel 13,Channel 14,Channel 15,Channel 16,Channel 17,Channel 18,Channel 19,Channel 20,Channel 21,Channel 22,Channel 23,Channel 24,Channel 25,Channel 26,Channel 27,Channel 28,Channel 29,Channel 30,Channel 31"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--9. 1. " G1DR[9:0] ,Group 1 Digital Result"
|
|
endif
|
|
width 18.
|
|
group.long (0x4+0x11C)++0x3
|
|
line.long 0x0 "G1SAMPDISEN,Group 1 Sampling Capacitor Discharge Mode"
|
|
hexmask.long.byte 0x00 8.--15. 1. " G1_SAMP_DIS_CYC[7:0] ,ADC Sampling Capacitor is Dicharged Cycles"
|
|
bitfld.long 0x00 0. " G1_SAMP_DIS_EN ,Sampling Capacitor Discharge Mode" "Disabled,Enabled"
|
|
group.long (0x4+0x168)++0x3
|
|
line.long 0x0 "G1FIFORESETCR,Group 1 FIFO Reset"
|
|
bitfld.long 0x00 0. " G1_FIFO_RESET ,Reset the ADC Group 1 FIFO" "No reset,Reset"
|
|
group.long (0x4+0x174)++0x3
|
|
line.long 0x0 "G1RAMADDR,Group 1 ADC RAM Pointer"
|
|
hexmask.long.word 0x00 0.--8. 1. " G1_RAM_ADDR ,Group 1 ADC RAM Pointer"
|
|
group.long (0x4+0x190)++0x03
|
|
line.long 0x00 "G1CHNSELMODECTRL, ADC Group 1 Channel Selection Mode Control Register"
|
|
bitfld.long 0x00 0.--3. " G1_ENH_CHNSEL_MODE_ENABLE , Enable Enhanced Channel Selection Mode" ",,,,,Disabled,,,,,Enabled,?..."
|
|
group.long (0x8+0x19C)++0x07
|
|
line.long 0x00 "G1CURRCOUNT, ADC Group 1 Current Count Register"
|
|
bitfld.long 0x00 0.--4. " G1_CURRENT_COUNT , Value For The Group 1 Conversions" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
line.long 0x04 "G1MAXCOUNT, ADC Group 1 Maximum Count Register"
|
|
bitfld.long 0x04 0.--4. " G1_MAX_COUNT , Value For The Group 1 Conversions" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
tree.end
|
|
width 13.
|
|
tree "Group 2 Registers"
|
|
group.long (0x8+0x10)++0x3
|
|
line.long 0x0 "G2MODECR,Group 2 MODE Control Register"
|
|
bitfld.long 0x00 16. " NO_RESET_ON_CHNSEL ,No Group 2 Results Memory Reset on New Channel Select" "Reset,No reset"
|
|
bitfld.long 0x00 8.--9. " G2_DATA_FMT ,Group 2 (Read) Data Format" "12 bit,10 bit,8 bit,?..."
|
|
textline " "
|
|
bitfld.long 0x00 5. " G2_CHID ,Channel ID Mode for the Group 2" "Forced to 0,ID of A/D channel"
|
|
bitfld.long 0x00 4. " OVR_G2_RAM_IGN ,Overrun Event Group RAM Ignore" "Not ignored,Ignored"
|
|
textline " "
|
|
bitfld.long 0x00 3. " G2_HW_TRIG ,Group 2 Hardware Triggered" "Software,Event"
|
|
bitfld.long 0x00 2. " G2_SBIT ,Group1 8-bit result mode" "10-bit,8-bit"
|
|
textline " "
|
|
bitfld.long 0x00 1. " G2_MODE ,Group 2 mode" "Single,Continuous"
|
|
bitfld.long 0x00 0. " FRZ_G1 ,Freeze Conversion Group 2" "Completed,Frozen"
|
|
group.long (0x8+0x1C)++0x3
|
|
line.long 0x0 "G2SRC,Group 2 Trigger Source Select"
|
|
bitfld.long 0x00 4. " G2_EDG_BOTH ,Group 2 Trigger Edge Polarity Select" "Defined edge,Any edge"
|
|
bitfld.long 0x00 3. " G2_EDG_SEL ,ADC Group 2 Trigger Edge Select" "High/low,Low/high"
|
|
textline " "
|
|
bitfld.long 0x00 0.--2. " G2SRC[2:0] ,Group 2 Trigger Source Select" "ADEVT,Internal,Internal,Internal,Internal,Internal,Internal,Internal"
|
|
group.long (0x8+0x28)++0x3
|
|
line.long 0x0 "G2INTENA,Group 2 Interrupt Enable"
|
|
bitfld.long 0x00 3. " G2_END_INT_EN ,Group 2 Conversion End Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " G2_OVR_INT_EN ,Group 2 Memory Overrun Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " G2_THR_INT_EN ,Group 2 Memory Threshold Interrupt Enable" "Disabled,Enabled"
|
|
group.long (0x8+0x34)++0x3
|
|
line.long 0x0 "G2INTFLG,Group 2 Interrupt Flag"
|
|
eventfld.long 0x00 3. " G2_END ,Group 2 Conversion End" "Not converted,Converted"
|
|
rbitfld.long 0x00 2. " G2_MEM_EMPTY ,Group 2 FIFO Empty Status" "Not empty,Empty"
|
|
textline " "
|
|
rbitfld.long 0x00 1. " G2_MEM_OVERFLOW ,Group 2 Memory Overrun Flag" "No overrun,Overrun"
|
|
eventfld.long 0x00 0. " G2_THR_INT_FLAG ,Group 2 Threshold Interrupt Flag" "No interrupt,Interrupt"
|
|
group.long (0x8+0x40)++0x3
|
|
line.long 0x0 "G2INTCR,Group 2 Interrupt Threshold Counter"
|
|
hexmask.long.byte 0x00 9.--15. 1. " SIGN_EXTENSION ,Sign Extension"
|
|
hexmask.long.word 0x00 0.--8. 1. " G2_THR[8:0] ,Group 2 Interrupt Threshold Counter"
|
|
group.long (0x8+0x4C)++0x3
|
|
line.long 0x0 "G2DMACR,Group 2 DMA Control Register"
|
|
hexmask.long.word 0x00 16.--24. 1. " G2BLOCKS[8:0] ,Number of Group 2 Memory Buffers to be Transferred"
|
|
bitfld.long 0x00 3. " DMA_G2_END ,Group 2 Conversion End DMA Transfer Enable" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 2. " G2_BLK_XFER ,Group 2 Block DMA Transfer Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " G2_DMA_EN ,Group 2 DMA Transfer Enable" "Disabled,Enabled"
|
|
group.long (0x8+0x60)++0x3
|
|
line.long 0x0 "G2SAMP,Group 2 Sample Window"
|
|
hexmask.long.word 0x00 0.--11. 1. " G2_ACQ ,Group 2 Acquisition Prescale Bits"
|
|
group.long (0x8+0x6C)++0x3
|
|
line.long 0x0 "G2SR,Group 2 Status Register"
|
|
rbitfld.long 0x00 3. " G2_MEM_EMPTY ,Group 2 Memory Empty" "Not empty,Empty"
|
|
rbitfld.long 0x00 2. " G2_BUSY ,Group 2 Conversion-Busy Flag" "Not active,Busy"
|
|
textline " "
|
|
rbitfld.long 0x00 1. " G2_STOP ,Group 2 Conversion Stopped Flag" "Not frozen,Frozen"
|
|
eventfld.long 0x00 0. " G2_END ,Group 2 Conversion-Ended Flag R/W" "Not completed,Completed"
|
|
group.long (0x8+0x78)++0x3
|
|
line.long 0x0 "G2SEL,Group 2 select register"
|
|
bitfld.long 0x00 23. " G2CHNSEL [23] ,A/D Group 2 Channel 23 Selection Bit" "Not converted,Converted"
|
|
bitfld.long 0x00 22. " [22] ,A/D Group 2 Channel 22 Selection Bit" "Not converted,Converted"
|
|
bitfld.long 0x00 21. " [21] ,A/D Group 2 Channel 21 Selection Bit" "Not converted,Converted"
|
|
bitfld.long 0x00 20. " [20] ,A/D Group 2 Channel 20 Selection Bit" "Not converted,Converted"
|
|
textline " "
|
|
bitfld.long 0x00 19. " [19] ,A/D Group 2 Channel 19 Selection Bit" "Not converted,Converted"
|
|
bitfld.long 0x00 18. " [18] ,A/D Group 2 Channel 18 Selection Bit" "Not converted,Converted"
|
|
bitfld.long 0x00 17. " [17] ,A/D Group 2 Channel 17 Selection Bit" "Not converted,Converted"
|
|
bitfld.long 0x00 16. " [16] ,A/D Group 2 Channel 16 Selection Bit" "Not converted,Converted"
|
|
textline " "
|
|
bitfld.long 0x00 15. " [15] ,A/D Group 2 Channel 15 Selection Bit" "Not converted,Converted"
|
|
bitfld.long 0x00 14. " [14] ,A/D Group 2 Channel 14 Selection Bit" "Not converted,Converted"
|
|
bitfld.long 0x00 13. " [13] ,A/D Group 2 Channel 13 Selection Bit" "Not converted,Converted"
|
|
bitfld.long 0x00 12. " [12] ,A/D Group 2 Channel 12 Selection Bit" "Not converted,Converted"
|
|
textline " "
|
|
bitfld.long 0x00 11. " [11] ,A/D Group 2 Channel 11 Selection Bit" "Not converted,Converted"
|
|
bitfld.long 0x00 10. " [10] ,A/D Group 2 Channel 10 Selection Bit" "Not converted,Converted"
|
|
bitfld.long 0x00 9. " [9] ,A/D Group 2 Channel 9 Selection Bit" "Not converted,Converted"
|
|
bitfld.long 0x00 8. " [8] ,A/D Group 2 Channel 8 Selection Bit" "Not converted,Converted"
|
|
textline " "
|
|
bitfld.long 0x00 7. " [7] ,A/D Group 2 Channel 7 Selection Bit" "Not converted,Converted"
|
|
bitfld.long 0x00 6. " [6] ,A/D Group 2 Channel 6 Selection Bit" "Not converted,Converted"
|
|
bitfld.long 0x00 5. " [5] ,A/D Group 2 Channel 5 Selection Bit" "Not converted,Converted"
|
|
bitfld.long 0x00 4. " [4] ,A/D Group 2 Channel 4 Selection Bit" "Not converted,Converted"
|
|
textline " "
|
|
bitfld.long 0x00 3. " [3] ,A/D Group 2 Channel 3 Selection Bit" "Not converted,Converted"
|
|
bitfld.long 0x00 2. " [2] ,A/D Group 2 Channel 2 Selection Bit" "Not converted,Converted"
|
|
bitfld.long 0x00 1. " [1] ,A/D Group 2 Channel 1 Selection Bit" "Not converted,Converted"
|
|
bitfld.long 0x00 0. " [0] ,A/D Group 2 Channel 0 Selection Bit" "Not converted,Converted"
|
|
hgroup.long (0x40+0x90)++0x3
|
|
hide.long 0x0 "G2BUFFER0,Group 2 Buffer 0"
|
|
in
|
|
hgroup.long (0x40+0x94)++0x3
|
|
hide.long 0x0 "G2BUFFER1,Group 2 Buffer 1"
|
|
in
|
|
hgroup.long (0x40+0x98)++0x3
|
|
hide.long 0x0 "G2BUFFER2,Group 2 Buffer 2"
|
|
in
|
|
hgroup.long (0x40+0x9C)++0x3
|
|
hide.long 0x0 "G2BUFFER3,Group 2 Buffer 3"
|
|
in
|
|
hgroup.long (0x40+0xA0)++0x3
|
|
hide.long 0x0 "G2BUFFER4,Group 2 Buffer 4"
|
|
in
|
|
hgroup.long (0x40+0xA4)++0x3
|
|
hide.long 0x0 "G2BUFFER5,Group 2 Buffer 5"
|
|
in
|
|
hgroup.long (0x40+0xA8)++0x3
|
|
hide.long 0x0 "G2BUFFER6,Group 2 Buffer 6"
|
|
in
|
|
hgroup.long (0x40+0xAC)++0x3
|
|
hide.long 0x0 "G2BUFFER7,Group 2 Buffer 7"
|
|
in
|
|
if ((d.l(ad:0xFFF7C000+0x04)&0x80000000)==0x80000000)
|
|
group.long (0x8+0xF0)++0x3
|
|
line.long 0x0 "G2EMUBUFFER,Group 2 EMU Buffer"
|
|
bitfld.long 0x00 31. " G2_EMPTY ,Group 2 FIFO Empty" "Not empty,Empty"
|
|
bitfld.long 0x00 16.--20. " G2CHID[4:0] ,Group 2 Channel ID" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,Channel 8,Channel 9,Channel 10,Channel 11,Channel 12,Channel 13,Channel 14,Channel 15,Channel 16,Channel 17,Channel 18,Channel 19,Channel 20,Channel 21,Channel 22,Channel 23,Channel 24,Channel 25,Channel 26,Channel 27,Channel 28,Channel 29,Channel 30,Channel 31"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--11. 1. " G2DR[11:0] ,Group 2 Digital Result"
|
|
else
|
|
group.long (0x8+0xF0)++0x3
|
|
line.long 0x0 "G2EMUBUFFER,Group 2 EMU Buffer"
|
|
bitfld.long 0x00 15. " G2_EMPTY ,Group 2 FIFO Empty" "Not empty,Empty"
|
|
bitfld.long 0x00 10.--14. " G2CHID[4:0] ,Group 2 Channel ID" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,Channel 8,Channel 9,Channel 10,Channel 11,Channel 12,Channel 13,Channel 14,Channel 15,Channel 16,Channel 17,Channel 18,Channel 19,Channel 20,Channel 21,Channel 22,Channel 23,Channel 24,Channel 25,Channel 26,Channel 27,Channel 28,Channel 29,Channel 30,Channel 31"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--9. 1. " G2DR[9:0] ,Group 2 Digital Result"
|
|
endif
|
|
width 18.
|
|
group.long (0x8+0x11C)++0x3
|
|
line.long 0x0 "G2SAMPDISEN,Group 2 Sampling Capacitor Discharge Mode"
|
|
hexmask.long.byte 0x00 8.--15. 1. " G2_SAMP_DIS_CYC[7:0] ,ADC Sampling Capacitor is Dicharged Cycles"
|
|
bitfld.long 0x00 0. " G2_SAMP_DIS_EN ,Sampling Capacitor Discharge Mode" "Disabled,Enabled"
|
|
group.long (0x8+0x168)++0x3
|
|
line.long 0x0 "G2FIFORESETCR,Group 2 FIFO Reset"
|
|
bitfld.long 0x00 0. " G2_FIFO_RESET ,Reset the ADC Group 2 FIFO" "No reset,Reset"
|
|
group.long (0x8+0x174)++0x3
|
|
line.long 0x0 "G2RAMADDR,Group 2 ADC RAM Pointer"
|
|
hexmask.long.word 0x00 0.--8. 1. " G2_RAM_ADDR ,Group 2 ADC RAM Pointer"
|
|
group.long (0x8+0x190)++0x03
|
|
line.long 0x00 "G2CHNSELMODECTRL, ADC Group 2 Channel Selection Mode Control Register"
|
|
bitfld.long 0x00 0.--3. " G2_ENH_CHNSEL_MODE_ENABLE , Enable Enhanced Channel Selection Mode" ",,,,,Disabled,,,,,Enabled,?..."
|
|
group.long (0x10+0x19C)++0x07
|
|
line.long 0x00 "G2CURRCOUNT, ADC Group 2 Current Count Register"
|
|
bitfld.long 0x00 0.--4. " G2_CURRENT_COUNT , Value For The Group 2 Conversions" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
line.long 0x04 "G2MAXCOUNT, ADC Group 2 Maximum Count Register"
|
|
bitfld.long 0x04 0.--4. " G2_MAX_COUNT , Value For The Group 2 Conversions" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
tree.end
|
|
width 10.
|
|
group.long 0x58++0x3
|
|
line.long 0x0 "BNDCR,Buffer Boundary Control Register"
|
|
hexmask.long.word 0x00 16.--24. 1. " BNDA[8:0] ,Buffer Boundary A"
|
|
hexmask.long.word 0x00 0.--8. 1. " BNDB[8:0] ,Buffer Boundary B"
|
|
group.long 0x5C++0x3
|
|
line.long 0x0 "BNDEND,Buffer End Boundary"
|
|
rbitfld.long 0x00 16. " BUF_INIT_ACTIVE ,Indicates the Status of the ADC RAM Intialization Process" "Not initialized,Initialized"
|
|
bitfld.long 0x00 0.--2. " BNDEND[2:0] ,Buffer End Boundary" "16 words,32 words,64 words,128 words,192 words,256 words,512 words,1024 words"
|
|
if ((d.l(ad:0xFFF7C000+0x04)&0x80000000)==0x80000000)
|
|
group.long 0x84++0x3
|
|
line.long 0x0 "CALR,Calibration Register"
|
|
hexmask.long.word 0x00 0.--11. 1. " CALR[11:0] ,Calibration Bits"
|
|
else
|
|
group.long 0x84++0x3
|
|
line.long 0x0 "CALR,Calibration Register"
|
|
hexmask.long.word 0x00 0.--9. 1. " CALR[9:0] ,Calibration Bits"
|
|
endif
|
|
rgroup.long 0x88++0x3
|
|
line.long 0x0 "SMSTATE,State Macine Current State"
|
|
bitfld.long 0x00 0.--3. " SMSTATE[3:0] ,ADC State Macine Current State" "Idle,Conv_EV,Conv_SW1,Conv_SW2,Conv_Cal,Start_EV,Start_SW1,Start_SW2,Start_Cal,Wait_EV,Wait_SW1,Wait_SW2,Wait_CAL,?..."
|
|
width 10.
|
|
rgroup.long 0x8C++0x3
|
|
line.long 0x0 "LASTCONV,Last Conversion"
|
|
bitfld.long 0x00 23. " IN [23] ,Digital input pin 23" "Low,High"
|
|
bitfld.long 0x00 22. " [22] ,Digital input pin 22" "Low,High"
|
|
bitfld.long 0x00 21. " [21] ,Digital input pin 21" "Low,High"
|
|
bitfld.long 0x00 20. " [20] ,Digital input pin 20" "Low,High"
|
|
bitfld.long 0x00 19. " [19] ,Digital input pin 19" "Low,High"
|
|
bitfld.long 0x00 18. " [18] ,Digital input pin 18" "Low,High"
|
|
bitfld.long 0x00 17. " [17] ,Digital input pin 17" "Low,High"
|
|
bitfld.long 0x00 16. " [16] ,Digital input pin 16" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 15. " [15] ,Digital input pin 15" "Low,High"
|
|
bitfld.long 0x00 14. " [14] ,Digital input pin 14" "Low,High"
|
|
bitfld.long 0x00 13. " [13] ,Digital input pin 13" "Low,High"
|
|
bitfld.long 0x00 12. " [12] ,Digital input pin 12" "Low,High"
|
|
bitfld.long 0x00 11. " [11] ,Digital input pin 11" "Low,High"
|
|
bitfld.long 0x00 10. " [10] ,Digital input pin 10" "Low,High"
|
|
bitfld.long 0x00 9. " [9] ,Digital input pin 9" "Low,High"
|
|
bitfld.long 0x00 8. " [8] ,Digital input pin 8" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 7. " [7] ,Digital input pin 7" "Low,High"
|
|
bitfld.long 0x00 6. " [6] ,Digital input pin 6" "Low,High"
|
|
bitfld.long 0x00 5. " [5] ,Digital input pin 5" "Low,High"
|
|
bitfld.long 0x00 4. " [4] ,Digital input pin 4" "Low,High"
|
|
bitfld.long 0x00 3. " [3] ,Digital input pin 3" "Low,High"
|
|
bitfld.long 0x00 2. " [2] ,Digital input pin 2" "Low,High"
|
|
bitfld.long 0x00 1. " [1] ,Digital input pin 1" "Low,High"
|
|
bitfld.long 0x00 0. " [0] ,Digital input pin 0" "Low,High"
|
|
tree "ADC Interrupt Control Registers"
|
|
width 17.
|
|
group.long 0x128++0x3
|
|
line.long 0x0 "MAGINTCR1,Magnitude Interrupt Control Register 1"
|
|
bitfld.long 0x00 26.--30. " MAG_CHID1[4:0] ,MAG CHID1 [4:0]" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,Channel 8,Channel 9,Channel 10,Channel 11,Channel 12,Channel 13,Channel 14,Channel 15,Channel 16,Channel 17,Channel 18,Channel 19,Channel 20,Channel 21,Channel 22,Channel 23,Channel 24,Channel 25,Channel 26,Channel 27,Channel 28,Channel 29,Channel 30,Channel 31"
|
|
hexmask.long.word 0x00 16.--25. 1. " MAG_THR1 ,Compare Value"
|
|
textline " "
|
|
bitfld.long 0x00 8.--12. " COMP_CHID1[4:0] ,COMP CHID1 [4:0]" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,Channel 8,Channel 9,Channel 10,Channel 11,Channel 12,Channel 13,Channel 14,Channel 15,Channel 16,Channel 17,Channel 18,Channel 19,Channel 20,Channel 21,Channel 22,Channel 23,Channel 24,Channel 25,Channel 26,Channel 27,Channel 28,Channel 29,Channel 30,Channel 31"
|
|
bitfld.long 0x00 1. " CHN/THR_COMP1 , Channel OR Threshold Comparison" "Treshold,Channel"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CMP_GE/LT1 , Greater than or equal to OR Less than comparison operator" "Lower,Greater"
|
|
width 17.
|
|
group.long 0x12C++0x3
|
|
line.long 0x0 "MAGINT1MASK,Magnitude Interrupt Mask 1"
|
|
bitfld.long 0x00 9. " MAG_INT1_MASK [9] ,Comparison for the Magnitude Threshold Interrupt 1 Mask 9" "Not masked,Masked"
|
|
bitfld.long 0x00 8. " [8] ,Comparison for the Magnitude Threshold Interrupt 1 Mask 8" "Not masked,Masked"
|
|
bitfld.long 0x00 7. " [7] ,Comparison for the Magnitude Threshold Interrupt 1 Mask 7" "Not masked,Masked"
|
|
bitfld.long 0x00 6. " [6] ,Comparison for the Magnitude Threshold Interrupt 1 Mask 6" "Not masked,Masked"
|
|
bitfld.long 0x00 5. " [5] ,Comparison for the Magnitude Threshold Interrupt 1 Mask 5" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 4. " [4] ,Comparison for the Magnitude Threshold Interrupt 1 Mask 4" "Not masked,Masked"
|
|
bitfld.long 0x00 3. " [3] ,Comparison for the Magnitude Threshold Interrupt 1 Mask 3" "Not masked,Masked"
|
|
bitfld.long 0x00 2. " [2] ,Comparison for the Magnitude Threshold Interrupt 1 Mask 2" "Not masked,Masked"
|
|
bitfld.long 0x00 1. " [1] ,Comparison for the Magnitude Threshold Interrupt 1 Mask 1" "Not masked,Masked"
|
|
bitfld.long 0x00 0. " [0] ,Comparison for the Magnitude Threshold Interrupt 1 Mask 0" "Not masked,Masked"
|
|
width 17.
|
|
group.long 0x130++0x3
|
|
line.long 0x0 "MAGINTCR2,Magnitude Interrupt Control Register 2"
|
|
bitfld.long 0x00 26.--30. " MAG_CHID2[4:0] ,MAG CHID2 [4:0]" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,Channel 8,Channel 9,Channel 10,Channel 11,Channel 12,Channel 13,Channel 14,Channel 15,Channel 16,Channel 17,Channel 18,Channel 19,Channel 20,Channel 21,Channel 22,Channel 23,Channel 24,Channel 25,Channel 26,Channel 27,Channel 28,Channel 29,Channel 30,Channel 31"
|
|
hexmask.long.word 0x00 16.--25. 1. " MAG_THR2 ,Compare Value"
|
|
textline " "
|
|
bitfld.long 0x00 8.--12. " COMP_CHID2[4:0] ,COMP CHID2 [4:0]" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,Channel 8,Channel 9,Channel 10,Channel 11,Channel 12,Channel 13,Channel 14,Channel 15,Channel 16,Channel 17,Channel 18,Channel 19,Channel 20,Channel 21,Channel 22,Channel 23,Channel 24,Channel 25,Channel 26,Channel 27,Channel 28,Channel 29,Channel 30,Channel 31"
|
|
bitfld.long 0x00 1. " CHN/THR_COMP2 , Channel OR Threshold Comparison" "Treshold,Channel"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CMP_GE/LT2 , Greater than or equal to OR Less than comparison operator" "Lower,Greater"
|
|
width 17.
|
|
group.long 0x134++0x3
|
|
line.long 0x0 "MAGINT2MASK,Magnitude Interrupt Mask 2"
|
|
bitfld.long 0x00 9. " MAG_INT2_MASK [9] ,Comparison for the Magnitude Threshold Interrupt 2 Mask 9" "Not masked,Masked"
|
|
bitfld.long 0x00 8. " [8] ,Comparison for the Magnitude Threshold Interrupt 2 Mask 8" "Not masked,Masked"
|
|
bitfld.long 0x00 7. " [7] ,Comparison for the Magnitude Threshold Interrupt 2 Mask 7" "Not masked,Masked"
|
|
bitfld.long 0x00 6. " [6] ,Comparison for the Magnitude Threshold Interrupt 2 Mask 6" "Not masked,Masked"
|
|
bitfld.long 0x00 5. " [5] ,Comparison for the Magnitude Threshold Interrupt 2 Mask 5" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 4. " [4] ,Comparison for the Magnitude Threshold Interrupt 2 Mask 4" "Not masked,Masked"
|
|
bitfld.long 0x00 3. " [3] ,Comparison for the Magnitude Threshold Interrupt 2 Mask 3" "Not masked,Masked"
|
|
bitfld.long 0x00 2. " [2] ,Comparison for the Magnitude Threshold Interrupt 2 Mask 2" "Not masked,Masked"
|
|
bitfld.long 0x00 1. " [1] ,Comparison for the Magnitude Threshold Interrupt 2 Mask 1" "Not masked,Masked"
|
|
bitfld.long 0x00 0. " [0] ,Comparison for the Magnitude Threshold Interrupt 2 Mask 0" "Not masked,Masked"
|
|
width 17.
|
|
group.long 0x138++0x3
|
|
line.long 0x0 "MAGINTCR3,Magnitude Interrupt Control Register 3"
|
|
bitfld.long 0x00 26.--30. " MAG_CHID3[4:0] ,MAG CHID3 [4:0]" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,Channel 8,Channel 9,Channel 10,Channel 11,Channel 12,Channel 13,Channel 14,Channel 15,Channel 16,Channel 17,Channel 18,Channel 19,Channel 20,Channel 21,Channel 22,Channel 23,Channel 24,Channel 25,Channel 26,Channel 27,Channel 28,Channel 29,Channel 30,Channel 31"
|
|
hexmask.long.word 0x00 16.--25. 1. " MAG_THR3 ,Compare Value"
|
|
textline " "
|
|
bitfld.long 0x00 8.--12. " COMP_CHID3[4:0] ,COMP CHID3 [4:0]" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,Channel 8,Channel 9,Channel 10,Channel 11,Channel 12,Channel 13,Channel 14,Channel 15,Channel 16,Channel 17,Channel 18,Channel 19,Channel 20,Channel 21,Channel 22,Channel 23,Channel 24,Channel 25,Channel 26,Channel 27,Channel 28,Channel 29,Channel 30,Channel 31"
|
|
bitfld.long 0x00 1. " CHN/THR_COMP3 , Channel OR Threshold Comparison" "Treshold,Channel"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CMP_GE/LT3 , Greater than or equal to OR Less than comparison operator" "Lower,Greater"
|
|
width 17.
|
|
group.long 0x13C++0x3
|
|
line.long 0x0 "MAGINT3MASK,Magnitude Interrupt Mask 3"
|
|
bitfld.long 0x00 9. " MAG_INT3_MASK [9] ,Comparison for the Magnitude Threshold Interrupt 3 Mask 9" "Not masked,Masked"
|
|
bitfld.long 0x00 8. " [8] ,Comparison for the Magnitude Threshold Interrupt 3 Mask 8" "Not masked,Masked"
|
|
bitfld.long 0x00 7. " [7] ,Comparison for the Magnitude Threshold Interrupt 3 Mask 7" "Not masked,Masked"
|
|
bitfld.long 0x00 6. " [6] ,Comparison for the Magnitude Threshold Interrupt 3 Mask 6" "Not masked,Masked"
|
|
bitfld.long 0x00 5. " [5] ,Comparison for the Magnitude Threshold Interrupt 3 Mask 5" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 4. " [4] ,Comparison for the Magnitude Threshold Interrupt 3 Mask 4" "Not masked,Masked"
|
|
bitfld.long 0x00 3. " [3] ,Comparison for the Magnitude Threshold Interrupt 3 Mask 3" "Not masked,Masked"
|
|
bitfld.long 0x00 2. " [2] ,Comparison for the Magnitude Threshold Interrupt 3 Mask 2" "Not masked,Masked"
|
|
bitfld.long 0x00 1. " [1] ,Comparison for the Magnitude Threshold Interrupt 3 Mask 1" "Not masked,Masked"
|
|
bitfld.long 0x00 0. " [0] ,Comparison for the Magnitude Threshold Interrupt 3 Mask 0" "Not masked,Masked"
|
|
width 17.
|
|
group.long 0x160++0x3
|
|
line.long 0x0 "MAGTHRINTFLG,Magnitude Threshold Interrupt Flag"
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " MAG_THR_INT2_set/clr ,Magnitude Threshold Interrupt Flag Bit[2]" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " MAG_THR_INT1_set/clr ,Magnitude Threshold Interrupt Flag Bit[1]" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " MAG_THR_INT0_set/clr ,Magnitude Threshold Interrupt Flag Bit[0]" "No interrupt,Interrupt"
|
|
group.long 0x164++0x3
|
|
line.long 0x0 "MAGTHRINTOFFSET,Magnitude Threshold Interrupt Offset Register"
|
|
bitfld.long 0x00 0.--3. " INT_OFF[3:0] ,Magnitude Threshold Interrupt Offset" "No interrupt,Interrupt 1,Interrupt 2,Interrupt 3,?..."
|
|
tree.end
|
|
width 13.
|
|
group.long 0x180++0x3
|
|
line.long 0x0 "PARCR,Parity Control Register"
|
|
bitfld.long 0x00 8. " TEST ,Parity Bits Map" "Not mapped,Mapped"
|
|
bitfld.long 0x00 0.--3. " PARITY_ENA[3:0] ,Enable/Disable Parity Checking" "Enabled,Enabled,Enabled,Enabled,Enabled,Disabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled"
|
|
rgroup.long 0x184++0x3
|
|
line.long 0x0 "PARADDR,Parity Address"
|
|
hexmask.long.word 0x00 2.--11. 0x4 " ERROR_ADDRESS ,ERROR ADDRESS"
|
|
group.long 0x188++0x03
|
|
line.long 0x00 "PWRUPDLYCTRL, ADC Power-Up Delay Control Register"
|
|
hexmask.long.word 0x00 0.--9. 1. " PWRUP_DLY , Number Of VCLK Cycles"
|
|
width 0xB
|
|
tree.end
|
|
endif
|
|
sif cpuis("TMS570LS0714*")||cpuis("TMS570LS0914*")
|
|
tree.open "N2HET (High-End Timer Module)"
|
|
tree "N2HET1"
|
|
base ad:0xFFF7B800
|
|
sif cpuis("TMS570LS0232")||cpuis("TMS570LS0714*")||cpuis("TMS570LS0914*")
|
|
endian.be
|
|
endif
|
|
width 15.
|
|
group.long 0x00++0x07
|
|
line.long 0x0 "GCR,Global Control Register"
|
|
bitfld.long 0x00 24. " HET_PIN_ENA ,NHET Pin Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 21.--22. " MP ,Master Priority" "Lower,Higher,Round robin,?..."
|
|
bitfld.long 0x00 18. " PPF ,Protect Program Fields" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 17. " IS ,Ignore Suspend" "Not ignored,Ignored"
|
|
bitfld.long 0x00 16. " CMS ,Clk_master/Slave" "Slave,Master"
|
|
bitfld.long 0x00 0. " TO ,Turn On/Off" "Off,On"
|
|
line.long 0x04 "PFR,Prescaler Factor Register"
|
|
bitfld.long 0x04 8.--10. " LRPFC ,Loop Resolution Pre-scale Factor Code" "1,2,4,8,16,32,64,128"
|
|
bitfld.long 0x04 0.--5. " HRPFC ,HR Prescale Factor Code" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64"
|
|
rgroup.long 0x08++0x0B
|
|
line.long 0x0 "ADDR,Current Address Register"
|
|
hexmask.long.word 0x00 0.--8. 1. " HETADDR ,N2HET Current Address"
|
|
line.long 0x04 "OFF1,Offset Level 1 Register"
|
|
hexmask.long.byte 0x04 0.--5. 1. " Offset1 ,Indexes the Currently Pending High-Priority Interrupt"
|
|
line.long 0x08 "OFF2,Offset Level 2 Register"
|
|
hexmask.long.byte 0x08 0.--5. 1. " Offset2 ,Indexes the Currently Pending High-Priority Interrupt"
|
|
newline
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "INTENA_SETCLR,Interrupt Enable Set/Clear Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x04 31. " HETINTENAS_setclr[31] ,Interrupt Enable Set Pin 31" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x04 30. " [30] ,Interrupt enable set/clear bit 30" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x04 29. " [29] ,Interrupt enable set/clear bit 29" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x04 28. " [28] ,Interrupt enable set/clear bit 28" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 27. 0x00 27. 0x04 27. " [27] ,Interrupt enable set/clear bit 27" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x04 26. " [26] ,Interrupt enable set/clear bit 26" "Disabled,Enabled"
|
|
setclrfld.long 0x00 25. 0x00 25. 0x04 25. " [25] ,Interrupt enable set/clear bit 25" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x04 24. " [24] ,Interrupt enable set/clear bit 24" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 23. 0x00 23. 0x04 23. " [23] ,Interrupt enable set/clear bit 23" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x04 22. " [22] ,Interrupt enable set/clear bit 22" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x04 21. " [21] ,Interrupt enable set/clear bit 21" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x04 20. " [20] ,Interrupt enable set/clear bit 20" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 19. 0x00 19. 0x04 19. " [19] ,Interrupt enable set/clear bit 19" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x04 18. " [18] ,Interrupt enable set/clear bit 18" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x04 17. " [17] ,Interrupt enable set/clear bit 17" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x04 16. " [16] ,Interrupt enable set/clear bit 16" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 15. 0x00 15. 0x04 15. " [15] ,Interrupt enable set/clear bit 15" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x04 14. " [14] ,Interrupt enable set/clear bit 14" "Disabled,Enabled"
|
|
setclrfld.long 0x00 13. 0x00 13. 0x04 13. " [13] ,Interrupt enable set/clear bit 13" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x04 12. " [12] ,Interrupt enable set/clear bit 12" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 11. 0x00 11. 0x04 11. " [11] ,Interrupt enable set/clear bit 11" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x04 10. " [10] ,Interrupt enable set/clear bit 10" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x04 9. " [9] ,Interrupt enable set/clear bit 9" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x04 8. " [8] ,Interrupt enable set/clear bit 8" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 7. 0x00 7. 0x04 7. " [7] ,Interrupt enable set/clear bit 7" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x04 6. " [6] ,Interrupt enable set/clear bit 6" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x04 5. " [5] ,Interrupt enable set/clear bit 5" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x04 4. " [4] ,Interrupt enable set/clear bit 4" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 3. 0x00 3. 0x04 3. " [3] ,Interrupt enable set/clear bit 3" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x04 2. " [2] ,Interrupt enable set/clear bit 2" "Disabled,Enabled"
|
|
setclrfld.long 0x00 1. 0x00 1. 0x04 1. " [1] ,Interrupt enable set/clear bit 1" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x04 0. " [0] ,Interrupt enable set/clear bit 0" "Disabled,Enabled"
|
|
newline
|
|
group.long 0x1C++0x0F
|
|
line.long 0x00 "EXC1,Exception Control Register 1"
|
|
bitfld.long 0x00 24. " APCNT_OVRFL_ENA ,APCNT Overflow Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " APCNT_UNDRFL_ENA ,APCNT Underflow Enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 8. " PRGM_OVRFL_ENA ,Program Overflow Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " APCNT_OVRFL_ENA_PRY ,APCNT_Ovrfl_Ena Priority" "Level 2,Level 1"
|
|
newline
|
|
bitfld.long 0x00 1. " APCNT_UNDRFL_ENA_PRY ,APCNT_Undrfl_Ena Priority" "Level 2,Level 1"
|
|
bitfld.long 0x00 0. " PRGM_OVRFL_ENA_PRY ,Prgm_Ovrfl_Ena Priority" "Level 2,Level 1"
|
|
line.long 0x04 "EXC2,Exception Control Register 2"
|
|
eventfld.long 0x04 8. " DEBUG_STATUS_FLG ,Debug_Status Flag" "No NHET,NHET"
|
|
eventfld.long 0x04 2. " APCNT_OVRFL_FLG ,APCNT Overflow Flag" "Not occurred,Occurred"
|
|
newline
|
|
eventfld.long 0x04 1. " APCNT_UNDRFL_FLG ,APCNT Underflow Flag" "Not occurred,Occurred"
|
|
eventfld.long 0x04 0. " PRGM_OVERFL_FLG ,Program Overflow Flag" "Not occurred,Occurred"
|
|
newline
|
|
line.long 0x08 "PRY,Interrupt Priority Register"
|
|
bitfld.long 0x08 31. " HETPRY[31] ,HET Priority Level Bit[31]" "Level 2,Level 1"
|
|
bitfld.long 0x08 30. " [30] ,HET Priority Level Bit[30]" "Level 2,Level 1"
|
|
bitfld.long 0x08 29. " [29] ,HET Priority Level Bit[29]" "Level 2,Level 1"
|
|
newline
|
|
bitfld.long 0x08 28. " [28] ,HET Priority Level Bit[28]" "Level 2,Level 1"
|
|
bitfld.long 0x08 27. " [27] ,HET Priority Level Bit[27]" "Level 2,Level 1"
|
|
bitfld.long 0x08 26. " [26] ,HET Priority Level Bit[26]" "Level 2,Level 1"
|
|
newline
|
|
bitfld.long 0x08 25. " [25] ,HET Priority Level Bit[25]" "Level 2,Level 1"
|
|
bitfld.long 0x08 24. " [24] ,HET Priority Level Bit[24]" "Level 2,Level 1"
|
|
bitfld.long 0x08 23. " [23] ,HET Priority Level Bit[23]" "Level 2,Level 1"
|
|
newline
|
|
bitfld.long 0x08 22. " [22] ,HET Priority Level Bit[22]" "Level 2,Level 1"
|
|
bitfld.long 0x08 21. " [21] ,HET Priority Level Bit[21]" "Level 2,Level 1"
|
|
bitfld.long 0x08 20. " [20] ,HET Priority Level Bit[20]" "Level 2,Level 1"
|
|
newline
|
|
bitfld.long 0x08 19. " [19] ,HET Priority Level Bit[19]" "Level 2,Level 1"
|
|
bitfld.long 0x08 18. " [18] ,HET Priority Level Bit[18]" "Level 2,Level 1"
|
|
bitfld.long 0x08 17. " [17] ,HET Priority Level Bit[17]" "Level 2,Level 1"
|
|
newline
|
|
bitfld.long 0x08 16. " [16] ,HET Priority Level Bit[16]" "Level 2,Level 1"
|
|
bitfld.long 0x08 15. " [15] ,HET Priority Level Bit[15]" "Level 2,Level 1"
|
|
bitfld.long 0x08 14. " [14] ,HET Priority Level Bit[14]" "Level 2,Level 1"
|
|
newline
|
|
bitfld.long 0x08 13. " [13] ,HET Priority Level Bit[13]" "Level 2,Level 1"
|
|
bitfld.long 0x08 12. " [12] ,HET Priority Level Bit[12]" "Level 2,Level 1"
|
|
bitfld.long 0x08 11. " [11] ,HET Priority Level Bit[11]" "Level 2,Level 1"
|
|
newline
|
|
bitfld.long 0x08 10. " [10] ,HET Priority Level Bit[10]" "Level 2,Level 1"
|
|
bitfld.long 0x08 9. " [9] ,HET Priority Level Bit[9]" "Level 2,Level 1"
|
|
bitfld.long 0x08 8. " [8] ,HET Priority Level Bit[8]" "Level 2,Level 1"
|
|
newline
|
|
bitfld.long 0x08 7. " [7] ,HET Priority Level Bit[7]" "Level 2,Level 1"
|
|
bitfld.long 0x08 6. " [6] ,HET Priority Level Bit[6]" "Level 2,Level 1"
|
|
bitfld.long 0x08 5. " [5] ,HET Priority Level Bit[5]" "Level 2,Level 1"
|
|
newline
|
|
bitfld.long 0x08 4. " [4] ,HET Priority Level Bit[4]" "Level 2,Level 1"
|
|
bitfld.long 0x08 3. " [3] ,HET Priority Level Bit[3]" "Level 2,Level 1"
|
|
bitfld.long 0x08 2. " [2] ,HET Priority Level Bit[2]" "Level 2,Level 1"
|
|
newline
|
|
bitfld.long 0x08 1. " [1] ,HET Priority Level Bit[1]" "Level 2,Level 1"
|
|
bitfld.long 0x08 0. " HETPRY[0] ,HET Priority Level Bit[0]" "Level 2,Level 1"
|
|
line.long 0x0C "FLG,Interrupt Flag Register"
|
|
eventfld.long 0x0C 31. " HETFLAG[31] ,Interrupt Flag Register Bit[31]" "No interrupt,Interrupt"
|
|
eventfld.long 0x0C 30. " [30] ,Interrupt Flag Register Bit[30]" "No interrupt,Interrupt"
|
|
newline
|
|
eventfld.long 0x0C 29. " [29] ,Interrupt Flag Register Bit[29]" "No interrupt,Interrupt"
|
|
eventfld.long 0x0C 28. " [28] ,Interrupt Flag Register Bit[28]" "No interrupt,Interrupt"
|
|
newline
|
|
eventfld.long 0x0C 27. " [27] ,Interrupt Flag Register Bit[27]" "No interrupt,Interrupt"
|
|
eventfld.long 0x0C 26. " [26] ,Interrupt Flag Register Bit[26]" "No interrupt,Interrupt"
|
|
newline
|
|
eventfld.long 0x0C 25. " [25] ,Interrupt Flag Register Bit[25]" "No interrupt,Interrupt"
|
|
eventfld.long 0x0C 24. " [24] ,Interrupt Flag Register Bit[24]" "No interrupt,Interrupt"
|
|
newline
|
|
eventfld.long 0x0C 23. " [23] ,Interrupt Flag Register Bit[23]" "No interrupt,Interrupt"
|
|
eventfld.long 0x0C 22. " [22] ,Interrupt Flag Register Bit[22]" "No interrupt,Interrupt"
|
|
newline
|
|
eventfld.long 0x0C 21. " [21] ,Interrupt Flag Register Bit[21]" "No interrupt,Interrupt"
|
|
eventfld.long 0x0C 20. " [20] ,Interrupt Flag Register Bit[20]" "No interrupt,Interrupt"
|
|
newline
|
|
eventfld.long 0x0C 19. " [19] ,Interrupt Flag Register Bit[19]" "No interrupt,Interrupt"
|
|
eventfld.long 0x0C 18. " [18] ,Interrupt Flag Register Bit[18]" "No interrupt,Interrupt"
|
|
newline
|
|
eventfld.long 0x0C 17. " [17] ,Interrupt Flag Register Bit[17]" "No interrupt,Interrupt"
|
|
eventfld.long 0x0C 16. " [16] ,Interrupt Flag Register Bit[16]" "No interrupt,Interrupt"
|
|
newline
|
|
eventfld.long 0x0C 15. " [15] ,Interrupt Flag Register Bit[15]" "No interrupt,Interrupt"
|
|
eventfld.long 0x0C 14. " [14] ,Interrupt Flag Register Bit[14]" "No interrupt,Interrupt"
|
|
newline
|
|
eventfld.long 0x0C 13. " [13] ,Interrupt Flag Register Bit[13]" "No interrupt,Interrupt"
|
|
eventfld.long 0x0C 12. " [12] ,Interrupt Flag Register Bit[12]" "No interrupt,Interrupt"
|
|
newline
|
|
eventfld.long 0x0C 11. " [11] ,Interrupt Flag Register Bit[11]" "No interrupt,Interrupt"
|
|
eventfld.long 0x0C 10. " [10] ,Interrupt Flag Register Bit[10]" "No interrupt,Interrupt"
|
|
newline
|
|
eventfld.long 0x0C 9. " [9] ,Interrupt Flag Register Bit[9]" "No interrupt,Interrupt"
|
|
eventfld.long 0x0C 8. " [8] ,Interrupt Flag Register Bit[8]" "No interrupt,Interrupt"
|
|
newline
|
|
eventfld.long 0x0C 7. " [7] ,Interrupt Flag Register Bit[7]" "No interrupt,Interrupt"
|
|
eventfld.long 0x0C 6. " [6] ,Interrupt Flag Register Bit[6]" "No interrupt,Interrupt"
|
|
newline
|
|
eventfld.long 0x0C 5. " [5] ,Interrupt Flag Register Bit[5]" "No interrupt,Interrupt"
|
|
eventfld.long 0x0C 4. " [4] ,Interrupt Flag Register Bit[4]" "No interrupt,Interrupt"
|
|
newline
|
|
eventfld.long 0x0C 3. " [3] ,Interrupt Flag Register Bit[3]" "No interrupt,Interrupt"
|
|
eventfld.long 0x0C 2. " [2] ,Interrupt Flag Register Bit[2]" "No interrupt,Interrupt"
|
|
newline
|
|
eventfld.long 0x0C 1. " [1] ,Interrupt Flag Register Bit[1]" "No interrupt,Interrupt"
|
|
eventfld.long 0x0C 0. " [0] ,Interrupt Flag Register Bit[0]" "No interrupt,Interrupt"
|
|
sif (CPU()==("TMS570LS2124-PGE")||CPU()==("TMS570LS2124-ZWT")||CPU()==("TMS570LS2134-PGE")||CPU()==("TMS570LS2134-ZWT")||CPU()==("TMS570LS3134-PGE")||CPU()==("TMS570LS3134-ZWT")||CPU()==("TMS570LS3135-PGE")||CPU()==("TMS570LS3135-ZWT")||CPU()==("TMS570LS3136")||CPU()==("TMS570LS3137-PGE")||CPU()==("TMS570LS3137-ZWT")||CPU()==("TMS570LS30336")||CPU()==("TMS570LS2126")||CPU()==("TMS570LS2127")||CPU()==("TMS570LS2136")||CPU()==("TMS570LS2137")||CPU()==("TMS570LS2125-PGE")||CPU()==("TMS570LS2125-ZWT")||CPU()==("TMS570LS2135-PGE")||CPU()==("TMS570LS2135-ZWT")||CPU()==("RM48L950")||cpu()=="RM48L952-PGE"||cpu()=="RM48L952-ZWT"||CPU()=="RM48L950-PGE"||CPU()=="RM48L950-ZWT"||CPU()=="RM48L940-ZWT"||CPU()=="RM48L940-PGE"||CPU()=="RM48L930-ZWT"||CPU()=="RM48L930-PGE"||CPU()=="RM48L750-ZWT"||CPU()=="RM48L750-PGE"||CPU()=="RM48L740-ZWT"||CPU()=="RM48L740-PGE"||CPU()=="RM48L730-ZWT"||CPU()=="RM48L730-PGE"||CPU()=="RM48L550-PGE"||CPU()=="RM48L540-ZWT"||CPU()=="RM48L540-PGE"||CPU()=="RM48L530-ZWT"||CPU()=="RM48L530-PGE"||CPU()=="RM46L852-PGE"||CPU()=="RM46L852-ZWT"||CPU()=="RM46L850-PGE"||CPU()=="RM46L850-ZWT"||CPU()=="RM46L840-ZWT"||CPU()=="RM46L840-PGE"||CPU()=="RM46L830-ZWT"||CPU()=="RM46L830-PGE"||CPU()=="RM46L450-ZWT"||CPU()=="RM46L450-PGE"||CPU()=="RM46L440-ZWT"||CPU()=="RM46L440-PGE"||CPU()=="RM46L430-ZWT"||CPU()=="RM46L430-PGE"||CPU()=="RM42L432"||CPU()=="TMS570LC4357"||CPU()==("TMS570LS0332")||CPU()==("TMS570LS0432")||CPUIS("TMS570LS1114*")||CPUIS("TMS570LS1115*")||CPUIS("TMS570LS1224*")||CPUIS("TMS570LS1225*")||CPUIS("TMS570LS1227*")||cpuis("TMS570LS0232")||cpuis("TMS570LS0714*")||cpuis("TMS570LS0914*"))
|
|
group.long 0x2C++0x3
|
|
line.long 0x00 "HETAND,And Share Control Register"
|
|
bitfld.long 0x00 15. " AND_SHARE[31/30] ,And share 31/30" "Not shared,Shared"
|
|
bitfld.long 0x00 14. " [29/28] ,And share 29/28" "Not shared,Shared"
|
|
newline
|
|
bitfld.long 0x00 13. " [27/26] ,And share 27/26" "Not shared,Shared"
|
|
bitfld.long 0x00 12. " [25/24] ,And share 25/24" "Not shared,Shared"
|
|
newline
|
|
bitfld.long 0x00 11. " [23/22] ,And share 23/22" "Not shared,Shared"
|
|
bitfld.long 0x00 10. " [21/20] ,And share 21/20" "Not shared,Shared"
|
|
newline
|
|
bitfld.long 0x00 9. " [19/18] ,And share 19/18" "Not shared,Shared"
|
|
bitfld.long 0x00 8. " [17/16] ,And share 17/16" "Not shared,Shared"
|
|
newline
|
|
bitfld.long 0x00 7. " [15/14] ,And share 15/14" "Not shared,Shared"
|
|
bitfld.long 0x00 6. " [13/12] ,And share 13/12" "Not shared,Shared"
|
|
newline
|
|
bitfld.long 0x00 5. " [11/10] ,And share 11/10" "Not shared,Shared"
|
|
bitfld.long 0x00 4. " [9/8] ,And share 9/8" "Not shared,Shared"
|
|
newline
|
|
bitfld.long 0x00 3. " [7/6] ,And share 7/6" "Not shared,Shared"
|
|
bitfld.long 0x00 2. " [5/4] ,And share 5/4" "Not shared,Shared"
|
|
newline
|
|
bitfld.long 0x00 1. " [3/2] ,And share 3/2" "Not shared,Shared"
|
|
bitfld.long 0x00 0. " [1/0] ,And share 1/0" "Not shared,Shared"
|
|
endif
|
|
group.long 0x34++0x07
|
|
line.long 0x0 "HRSH,HR Share Control Register"
|
|
bitfld.long 0x00 15. " HR_SHARE[31/30] ,HR Share 31/30" "Not shared,Shared"
|
|
bitfld.long 0x00 14. " [29/28] ,HR Share 29/28" "Not shared,Shared"
|
|
newline
|
|
bitfld.long 0x00 13. " [27/26] ,HR Share 27/26" "Not shared,Shared"
|
|
bitfld.long 0x00 12. " [25/24] ,HR Share 25/24" "Not shared,Shared"
|
|
newline
|
|
bitfld.long 0x00 11. " [23/22] ,HR Share 23/22" "Not shared,Shared"
|
|
bitfld.long 0x00 10. " [21/20] ,HR Share 21/20" "Not shared,Shared"
|
|
newline
|
|
bitfld.long 0x00 9. " [19/18] ,HR Share 19/18" "Not shared,Shared"
|
|
bitfld.long 0x00 8. " [17/16] ,HR Share 17/16" "Not shared,Shared"
|
|
newline
|
|
bitfld.long 0x00 7. " [15/14] ,HR Share 15/14" "Not shared,Shared"
|
|
bitfld.long 0x00 6. " [13/12] ,HR Share 13/12" "Not shared,Shared"
|
|
newline
|
|
bitfld.long 0x00 5. " [11/10] ,HR Share 11/10" "Not shared,Shared"
|
|
bitfld.long 0x00 4. " [9/8] ,HR Share 9/8" "Not shared,Shared"
|
|
newline
|
|
bitfld.long 0x00 3. " [7/6] ,HR Share 7/6" "Not shared,Shared"
|
|
bitfld.long 0x00 2. " [5/4] ,HR Share 5/4" "Not shared,Shared"
|
|
newline
|
|
bitfld.long 0x00 1. " [3/2] ,HR Share 3/2" "Not shared,Shared"
|
|
bitfld.long 0x00 0. " [1/0] ,HR Share 1/0" "Not shared,Shared"
|
|
line.long 0x04 "XOR,HR XOR Control Register"
|
|
bitfld.long 0x04 15. " HR_XOR_SHARE[31/30] ,HR XOR-Share 31/30" "Not XOR-shared,XOR-shared"
|
|
bitfld.long 0x04 14. " [29/28] ,HR XOR-Share 29/28" "Not XOR-shared,XOR-shared"
|
|
newline
|
|
bitfld.long 0x04 13. " [27/26] ,HR XOR-Share 27/26" "Not XOR-shared,XOR-shared"
|
|
bitfld.long 0x04 12. " [25/24] ,HR XOR-Share 25/24" "Not XOR-shared,XOR-shared"
|
|
newline
|
|
bitfld.long 0x04 11. " [23/22] ,HR XOR-Share 23/22" "Not XOR-shared,XOR-shared"
|
|
bitfld.long 0x04 10. " [21/20] ,HR XOR-Share 21/20" "Not XOR-shared,XOR-shared"
|
|
newline
|
|
bitfld.long 0x04 9. " [19/18] ,HR XOR-Share 19/18" "Not XOR-shared,XOR-shared"
|
|
bitfld.long 0x04 8. " [17/16] ,HR XOR-Share 17/16" "Not XOR-shared,XOR-shared"
|
|
newline
|
|
bitfld.long 0x04 7. " [15/14] ,HR XOR-Share 15/14" "Not XOR-shared,XOR-shared"
|
|
bitfld.long 0x04 6. " [13/12] ,HR XOR-Share 13/12" "Not XOR-shared,XOR-shared"
|
|
newline
|
|
bitfld.long 0x04 5. " [11/10] ,HR XOR-Share 11/10" "Not XOR-shared,XOR-shared"
|
|
bitfld.long 0x04 4. " [9/8] ,HR XOR-Share 9/8" "Not XOR-shared,XOR-shared"
|
|
newline
|
|
bitfld.long 0x04 3. " [7/6] ,HR XOR-Share 7/6" "Not XOR-shared,XOR-shared"
|
|
bitfld.long 0x04 2. " [5/4] ,HR XOR-Share 5/4" "Not XOR-shared,XOR-shared"
|
|
newline
|
|
bitfld.long 0x04 1. " [3/2] ,HR XOR-Share 3/2" "Not XOR-shared,XOR-shared"
|
|
bitfld.long 0x04 0. " [1/0] ,HR XOR-Share 1/0" "Not XOR-shared,XOR-shared"
|
|
group.long 0x3C++0x03
|
|
line.long 0x00 "REQEN_SETCLR,Request Enable Set/Clear Register"
|
|
setclrfld.long 0x00 7. 0x00 7. 0x04 7. " REQENA_SET/CLR[7] ,Request enable set/clear bit [7]" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x04 6. " [6] ,Request enable set/clear bit [6]" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x04 5. " [5] ,Request enable set/clear bit [5]" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x04 4. " [4] ,Request enable set/clear bit [4]" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 3. 0x00 3. 0x04 3. " [3] ,Request enable set/clear bit [3]" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x04 2. " [2] ,Request enable set/clear bit [2]" "Disabled,Enabled"
|
|
setclrfld.long 0x00 1. 0x00 1. 0x04 1. " [1] ,Request enable set/clear bit [1]" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x04 0. " [0] ,Request enable set/clear bit [0]" "Disabled,Enabled"
|
|
sif (cpu()!=("TMS570LS0332")&&cpu()!=("TMS570LS0432")&&!cpuis("TMS570LS0232"))
|
|
group.long 0x44++0x3
|
|
line.long 0x00 "REQDS,Request Destination Select Register"
|
|
bitfld.long 0x00 23. " TDBS[7] ,HTU/DMA or Both Select Bit[7]" "HTU,Both"
|
|
bitfld.long 0x00 22. " [6] ,HTU/DMA or Both Select Bit[6]" "HTU,Both"
|
|
bitfld.long 0x00 21. " [5] ,HTU/DMA or Both Select Bit[5]" "HTU,Both"
|
|
bitfld.long 0x00 20. " [4] ,HTU/DMA or Both Select Bit[4]" "HTU,Both"
|
|
newline
|
|
bitfld.long 0x00 19. " [3] ,HTU/DMA or Both Select Bit[3]" "HTU,Both"
|
|
bitfld.long 0x00 18. " [2] ,HTU/DMA or Both Select Bit[2]" "HTU,Both"
|
|
bitfld.long 0x00 17. " [1] ,HTU/DMA or Both Select Bit[1]" "HTU,Both"
|
|
bitfld.long 0x00 16. " [0] ,HTU/DMA or Both Select Bit[0]" "HTU,Both"
|
|
newline
|
|
bitfld.long 0x00 7. " TDS[7] ,HTU or DMA Select Bit[7]" "HTU,DMA"
|
|
bitfld.long 0x00 6. " TDS[6] ,HTU or DMA Select Bit[6]" "HTU,DMA"
|
|
bitfld.long 0x00 5. " TDS[5] ,HTU or DMA Select Bit[5]" "HTU,DMA"
|
|
bitfld.long 0x00 4. " TDS[4] ,HTU or DMA Select Bit[4]" "HTU,DMA"
|
|
newline
|
|
bitfld.long 0x00 3. " TDS[3] ,HTU or DMA Select Bit[3]" "HTU,DMA"
|
|
bitfld.long 0x00 2. " TDS[2] ,HTU or DMA Select Bit[2]" "HTU,DMA"
|
|
bitfld.long 0x00 1. " TDS[1] ,HTU or DMA Select Bit[1]" "HTU,DMA"
|
|
bitfld.long 0x00 0. " TDS[0] ,HTU or DMA Select Bit[0]" "HTU,DMA"
|
|
endif
|
|
group.long 0x4C++0x3
|
|
line.long 0x00 "DIR,Direction Register"
|
|
bitfld.long 0x00 31. " HET_DIR[31] ,Input/Output Direction Pin 31" "Input,Output"
|
|
bitfld.long 0x00 30. " [30] ,Input/Output Direction Pin 30" "Input,Output"
|
|
bitfld.long 0x00 29. " [29] ,Input/Output Direction Pin 29" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 28. " [28] ,Input/Output Direction Pin 28" "Input,Output"
|
|
bitfld.long 0x00 27. " [27] ,Input/Output Direction Pin 27" "Input,Output"
|
|
bitfld.long 0x00 26. " [26] ,Input/Output Direction Pin 26" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 25. " [25] ,Input/Output Direction Pin 25" "Input,Output"
|
|
bitfld.long 0x00 24. " [24] ,Input/Output Direction Pin 24" "Input,Output"
|
|
bitfld.long 0x00 23. " [23] ,Input/Output Direction Pin 23" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 22. " [22] ,Input/Output Direction Pin 22" "Input,Output"
|
|
bitfld.long 0x00 21. " [21] ,Input/Output Direction Pin 21" "Input,Output"
|
|
bitfld.long 0x00 20. " [20] ,Input/Output Direction Pin 20" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 19. " [19] ,Input/Output Direction Pin 19" "Input,Output"
|
|
bitfld.long 0x00 18. " [18] ,Input/Output Direction Pin 18" "Input,Output"
|
|
bitfld.long 0x00 17. " [17] ,Input/Output Direction Pin 17" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 16. " [16] ,Input/Output Direction Pin 16" "Input,Output"
|
|
bitfld.long 0x00 15. " [15] ,Input/Output Direction Pin 15" "Input,Output"
|
|
bitfld.long 0x00 14. " [14] ,Input/Output Direction Pin 14" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 13. " [13] ,Input/Output Direction Pin 13" "Input,Output"
|
|
bitfld.long 0x00 12. " [12] ,Input/Output Direction Pin 12" "Input,Output"
|
|
bitfld.long 0x00 11. " [11] ,Input/Output Direction Pin 11" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 10. " [10] ,Input/Output Direction Pin 10" "Input,Output"
|
|
bitfld.long 0x00 9. " [9] ,Input/Output Direction Pin 9" "Input,Output"
|
|
bitfld.long 0x00 8. " [8] ,Input/Output Direction Pin 8" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 7. " [7] ,Input/Output Direction Pin 7" "Input,Output"
|
|
bitfld.long 0x00 6. " [6] ,Input/Output Direction Pin 6" "Input,Output"
|
|
bitfld.long 0x00 5. " [5] ,Input/Output Direction Pin 5" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 4. " [4] ,Input/Output Direction Pin 4" "Input,Output"
|
|
bitfld.long 0x00 3. " [3] ,Input/Output Direction Pin 3" "Input,Output"
|
|
bitfld.long 0x00 2. " [2] ,Input/Output Direction Pin 2" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 1. " [1] ,Input/Output Direction Pin 1" "Input,Output"
|
|
bitfld.long 0x00 0. " [0] ,Input/Output Direction Pin 0" "Input,Output"
|
|
rgroup.long 0x50++0x3
|
|
line.long 0x00 "DIN,Input Data Register"
|
|
bitfld.long 0x00 31. " HETDIN[31] ,NHET Data Input Register Pin 31" "Low,High"
|
|
bitfld.long 0x00 30. " [30] ,NHET Data Input Register Pin 30" "Low,High"
|
|
bitfld.long 0x00 29. " [29] ,NHET Data Input Register Pin 29" "Low,High"
|
|
bitfld.long 0x00 28. " [28] ,NHET Data Input Register Pin 28" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 27. " [27] ,NHET Data Input Register Pin 27" "Low,High"
|
|
bitfld.long 0x00 26. " [26] ,NHET Data Input Register Pin 26" "Low,High"
|
|
bitfld.long 0x00 25. " [25] ,NHET Data Input Register Pin 25" "Low,High"
|
|
bitfld.long 0x00 24. " [24] ,NHET Data Input Register Pin 24" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 23. " [23] ,NHET Data Input Register Pin 23" "Low,High"
|
|
bitfld.long 0x00 22. " [22] ,NHET Data Input Register Pin 22" "Low,High"
|
|
bitfld.long 0x00 21. " [21] ,NHET Data Input Register Pin 21" "Low,High"
|
|
bitfld.long 0x00 20. " [20] ,NHET Data Input Register Pin 20" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 19. " [19] ,NHET Data Input Register Pin 19" "Low,High"
|
|
bitfld.long 0x00 18. " [18] ,NHET Data Input Register Pin 18" "Low,High"
|
|
bitfld.long 0x00 17. " [17] ,NHET Data Input Register Pin 17" "Low,High"
|
|
bitfld.long 0x00 16. " [16] ,NHET Data Input Register Pin 16" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 15. " [15] ,NHET Data Input Register Pin 15" "Low,High"
|
|
bitfld.long 0x00 14. " [14] ,NHET Data Input Register Pin 14" "Low,High"
|
|
bitfld.long 0x00 13. " [13] ,NHET Data Input Register Pin 13" "Low,High"
|
|
bitfld.long 0x00 12. " [12] ,NHET Data Input Register Pin 12" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 11. " [11] ,NHET Data Input Register Pin 11" "Low,High"
|
|
bitfld.long 0x00 10. " [10] ,NHET Data Input Register Pin 10" "Low,High"
|
|
bitfld.long 0x00 9. " [9] ,NHET Data Input Register Pin 9" "Low,High"
|
|
bitfld.long 0x00 8. " [8] ,NHET Data Input Register Pin 8" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 7. " [7] ,NHET Data Input Register Pin 7" "Low,High"
|
|
bitfld.long 0x00 6. " [6] ,NHET Data Input Register Pin 6" "Low,High"
|
|
bitfld.long 0x00 5. " [5] ,NHET Data Input Register Pin 5" "Low,High"
|
|
bitfld.long 0x00 4. " [4] ,NHET Data Input Register Pin 4" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 3. " [3] ,NHET Data Input Register Pin 3" "Low,High"
|
|
bitfld.long 0x00 2. " [2] ,NHET Data Input Register Pin 2" "Low,High"
|
|
bitfld.long 0x00 1. " [1] ,NHET Data Input Register Pin 1" "Low,High"
|
|
bitfld.long 0x00 0. " [0] ,NHET Data Input Register Pin 0" "Low,High"
|
|
group.long 0x54++0x3
|
|
line.long 0x00 "DOUT_SET/CLR,Output Data Set/Clear Register"
|
|
setclrfld.long 0x00 31. 0x04 31. 0x08 31. " HETDOUT[31] ,NHET Data Output Register Bit[31]" "Low,High"
|
|
setclrfld.long 0x00 30. 0x04 30. 0x08 30. " [30] ,NHET Data Output Register Bit[30]" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 29. 0x04 29. 0x08 29. " [29] ,NHET Data Output Register Bit[29]" "Low,High"
|
|
setclrfld.long 0x00 28. 0x04 28. 0x08 28. " [28] ,NHET Data Output Register Bit[28]" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 27. 0x04 27. 0x08 27. " [27] ,NHET Data Output Register Bit[27]" "Low,High"
|
|
setclrfld.long 0x00 26. 0x04 26. 0x08 26. " [26] ,NHET Data Output Register Bit[26]" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 25. 0x04 25. 0x08 25. " [25] ,NHET Data Output Register Bit[25]" "Low,High"
|
|
setclrfld.long 0x00 24. 0x04 24. 0x08 24. " [24] ,NHET Data Output Register Bit[24]" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 23. 0x04 23. 0x08 23. " [23] ,NHET Data Output Register Bit[23]" "Low,High"
|
|
setclrfld.long 0x00 22. 0x04 22. 0x08 22. " [22] ,NHET Data Output Register Bit[22]" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 21. 0x04 21. 0x08 21. " [21] ,NHET Data Output Register Bit[21]" "Low,High"
|
|
setclrfld.long 0x00 20. 0x04 20. 0x08 20. " [20] ,NHET Data Output Register Bit[20]" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 19. 0x04 19. 0x08 19. " [19] ,NHET Data Output Register Bit[19]" "Low,High"
|
|
setclrfld.long 0x00 18. 0x04 18. 0x08 18. " [18] ,NHET Data Output Register Bit[18]" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 17. 0x04 17. 0x08 17. " [17] ,NHET Data Output Register Bit[17]" "Low,High"
|
|
setclrfld.long 0x00 16. 0x04 16. 0x08 16. " [16] ,NHET Data Output Register Bit[16]" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 15. 0x04 15. 0x08 15. " [15] ,NHET Data Output Register Bit[15]" "Low,High"
|
|
setclrfld.long 0x00 14. 0x04 14. 0x08 14. " [14] ,NHET Data Output Register Bit[14]" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 13. 0x04 13. 0x08 13. " [13] ,NHET Data Output Register Bit[13]" "Low,High"
|
|
setclrfld.long 0x00 12. 0x04 12. 0x08 12. " [12] ,NHET Data Output Register Bit[12]" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 11. 0x04 11. 0x08 11. " [11] ,NHET Data Output Register Bit[11]" "Low,High"
|
|
setclrfld.long 0x00 10. 0x04 10. 0x08 10. " [10] ,NHET Data Output Register Bit[10]" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 9. 0x04 9. 0x08 9. " [9] ,NHET Data Output Register Bit[9]" "Low,High"
|
|
setclrfld.long 0x00 8. 0x04 8. 0x08 8. " [8] ,NHET Data Output Register Bit[8]" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 7. 0x04 7. 0x08 7. " [7] ,NHET Data Output Register Bit[7]" "Low,High"
|
|
setclrfld.long 0x00 6. 0x04 6. 0x08 6. " [6] ,NHET Data Output Register Bit[6]" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 5. 0x04 5. 0x08 5. " [5] ,NHET Data Output Register Bit[5]" "Low,High"
|
|
setclrfld.long 0x00 4. 0x04 4. 0x08 4. " [4] ,NHET Data Output Register Bit[4]" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 3. 0x04 3. 0x08 3. " [3] ,NHET Data Output Register Bit[3]" "Low,High"
|
|
setclrfld.long 0x00 2. 0x04 2. 0x08 2. " [2] ,NHET Data Output Register Bit[2]" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 1. 0x04 1. 0x08 1. " [1] ,NHET Data Output Register Bit[1]" "Low,High"
|
|
setclrfld.long 0x00 0. 0x04 0. 0x08 0. " [0] ,NHET Data Output Register Bit[0]" "Low,High"
|
|
group.long 0x60++0x0B
|
|
line.long 0x00 "PDR,Open Drain Register"
|
|
bitfld.long 0x00 31. " HETPDR[31] ,NHET Open Drain Bit[31]" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " [30] ,NHET Open Drain Bit[30]" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " [29] ,NHET Open Drain Bit[29]" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 28. " [28] ,NHET Open Drain Bit[28]" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " [27] ,NHET Open Drain Bit[27]" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " [26] ,NHET Open Drain Bit[26]" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 25. " [25] ,NHET Open Drain Bit[25]" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " [24] ,NHET Open Drain Bit[24]" "Disabled,Enabled"
|
|
bitfld.long 0x00 23. " [23] ,NHET Open Drain Bit[23]" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 22. " [22] ,NHET Open Drain Bit[22]" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " [21] ,NHET Open Drain Bit[21]" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " [20] ,NHET Open Drain Bit[20]" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 19. " [19] ,NHET Open Drain Bit[19]" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " [18] ,NHET Open Drain Bit[18]" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " [17] ,NHET Open Drain Bit[17]" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 16. " [16] ,NHET Open Drain Bit[16]" "Disabled,Enabled"
|
|
bitfld.long 0x00 15. " [15] ,NHET Open Drain Bit[15]" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " [14] ,NHET Open Drain Bit[14]" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 13. " [13] ,NHET Open Drain Bit[13]" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " [12] ,NHET Open Drain Bit[12]" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " [11] ,NHET Open Drain Bit[11]" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 10. " [10] ,NHET Open Drain Bit[10]" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " [9] ,NHET Open Drain Bit[9]" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " [8] ,NHET Open Drain Bit[8]" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 7. " [7] ,NHET Open Drain Bit[7]" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " [6] ,NHET Open Drain Bit[6]" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " [5] ,NHET Open Drain Bit[5]" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 4. " [4] ,NHET Open Drain Bit[4]" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " [3] ,NHET Open Drain Bit[3]" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " [2] ,NHET Open Drain Bit[2]" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 1. " [1] ,NHET Open Drain Bit[1]" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,NHET Open Drain Bit[0]" "Disabled,Enabled"
|
|
line.long 0x04 "PULDIS,Pull Disable Register"
|
|
bitfld.long 0x04 31. " HETPULDIS[31] ,NHET Pull Disable Bit[31]" "No,Yes"
|
|
bitfld.long 0x04 30. " [30] ,NHET Pull Disable Bit[30]" "No,Yes"
|
|
bitfld.long 0x04 29. " [29] ,NHET Pull Disable Bit[29]" "No,Yes"
|
|
newline
|
|
bitfld.long 0x04 28. " [28] ,NHET Pull Disable Bit[28]" "No,Yes"
|
|
bitfld.long 0x04 27. " [27] ,NHET Pull Disable Bit[27]" "No,Yes"
|
|
bitfld.long 0x04 26. " [26] ,NHET Pull Disable Bit[26]" "No,Yes"
|
|
newline
|
|
bitfld.long 0x04 25. " [25] ,NHET Pull Disable Bit[25]" "No,Yes"
|
|
bitfld.long 0x04 24. " [24] ,NHET Pull Disable Bit[24]" "No,Yes"
|
|
bitfld.long 0x04 23. " [23] ,NHET Pull Disable Bit[23]" "No,Yes"
|
|
newline
|
|
bitfld.long 0x04 22. " [22] ,NHET Pull Disable Bit[22]" "No,Yes"
|
|
bitfld.long 0x04 21. " [21] ,NHET Pull Disable Bit[21]" "No,Yes"
|
|
bitfld.long 0x04 20. " [20] ,NHET Pull Disable Bit[20]" "No,Yes"
|
|
newline
|
|
bitfld.long 0x04 19. " [19] ,NHET Pull Disable Bit[19]" "No,Yes"
|
|
bitfld.long 0x04 18. " [18] ,NHET Pull Disable Bit[18]" "No,Yes"
|
|
bitfld.long 0x04 17. " [17] ,NHET Pull Disable Bit[17]" "No,Yes"
|
|
newline
|
|
bitfld.long 0x04 16. " [16] ,NHET Pull Disable Bit[16]" "No,Yes"
|
|
bitfld.long 0x04 15. " [15] ,NHET Pull Disable Bit[15]" "No,Yes"
|
|
bitfld.long 0x04 14. " [14] ,NHET Pull Disable Bit[14]" "No,Yes"
|
|
newline
|
|
bitfld.long 0x04 13. " [13] ,NHET Pull Disable Bit[13]" "No,Yes"
|
|
bitfld.long 0x04 12. " [12] ,NHET Pull Disable Bit[12]" "No,Yes"
|
|
bitfld.long 0x04 11. " [11] ,NHET Pull Disable Bit[11]" "No,Yes"
|
|
newline
|
|
bitfld.long 0x04 10. " [10] ,NHET Pull Disable Bit[10]" "No,Yes"
|
|
bitfld.long 0x04 9. " [9] ,NHET Pull Disable Bit[9]" "No,Yes"
|
|
bitfld.long 0x04 8. " [8] ,NHET Pull Disable Bit[8]" "No,Yes"
|
|
newline
|
|
bitfld.long 0x04 7. " [7] ,NHET Pull Disable Bit[7]" "No,Yes"
|
|
bitfld.long 0x04 6. " [6] ,NHET Pull Disable Bit[6]" "No,Yes"
|
|
bitfld.long 0x04 5. " [5] ,NHET Pull Disable Bit[5]" "No,Yes"
|
|
newline
|
|
bitfld.long 0x04 4. " [4] ,NHET Pull Disable Bit[4]" "No,Yes"
|
|
bitfld.long 0x04 3. " [3] ,NHET Pull Disable Bit[3]" "No,Yes"
|
|
bitfld.long 0x04 2. " [2] ,NHET Pull Disable Bit[2]" "No,Yes"
|
|
newline
|
|
bitfld.long 0x04 1. " [1] ,NHET Pull Disable Bit[1]" "No,Yes"
|
|
bitfld.long 0x04 0. " [0] ,NHET Pull Disable Bit[0]" "No,Yes"
|
|
line.long 0x08 "PSL,Pull Select Register"
|
|
bitfld.long 0x08 31. " HETPSL[31] ,NHET Pull Select Bit[31]" "Pull down,Pull up"
|
|
bitfld.long 0x08 30. " [30] ,NHET Pull Select Bit[30]" "Pull down,Pull up"
|
|
bitfld.long 0x08 29. " [29] ,NHET Pull Select Bit[29]" "Pull down,Pull up"
|
|
newline
|
|
bitfld.long 0x08 28. " [28] ,NHET Pull Select Bit[28]" "Pull down,Pull up"
|
|
bitfld.long 0x08 27. " [27] ,NHET Pull Select Bit[27]" "Pull down,Pull up"
|
|
bitfld.long 0x08 26. " [26] ,NHET Pull Select Bit[26]" "Pull down,Pull up"
|
|
newline
|
|
bitfld.long 0x08 25. " [25] ,NHET Pull Select Bit[25]" "Pull down,Pull up"
|
|
bitfld.long 0x08 24. " [24] ,NHET Pull Select Bit[24]" "Pull down,Pull up"
|
|
bitfld.long 0x08 23. " [23] ,NHET Pull Select Bit[23]" "Pull down,Pull up"
|
|
newline
|
|
bitfld.long 0x08 22. " [22] ,NHET Pull Select Bit[22]" "Pull down,Pull up"
|
|
bitfld.long 0x08 21. " [21] ,NHET Pull Select Bit[21]" "Pull down,Pull up"
|
|
bitfld.long 0x08 20. " [20] ,NHET Pull Select Bit[20]" "Pull down,Pull up"
|
|
newline
|
|
bitfld.long 0x08 19. " [19] ,NHET Pull Select Bit[19]" "Pull down,Pull up"
|
|
bitfld.long 0x08 18. " [18] ,NHET Pull Select Bit[18]" "Pull down,Pull up"
|
|
bitfld.long 0x08 17. " [17] ,NHET Pull Select Bit[17]" "Pull down,Pull up"
|
|
newline
|
|
bitfld.long 0x08 16. " [16] ,NHET Pull Select Bit[16]" "Pull down,Pull up"
|
|
bitfld.long 0x08 15. " [15] ,NHET Pull Select Bit[15]" "Pull down,Pull up"
|
|
bitfld.long 0x08 14. " [14] ,NHET Pull Select Bit[14]" "Pull down,Pull up"
|
|
newline
|
|
bitfld.long 0x08 13. " [13] ,NHET Pull Select Bit[13]" "Pull down,Pull up"
|
|
bitfld.long 0x08 12. " [12] ,NHET Pull Select Bit[12]" "Pull down,Pull up"
|
|
bitfld.long 0x08 11. " [11] ,NHET Pull Select Bit[11]" "Pull down,Pull up"
|
|
newline
|
|
bitfld.long 0x08 10. " [10] ,NHET Pull Select Bit[10]" "Pull down,Pull up"
|
|
bitfld.long 0x08 9. " [9] ,NHET Pull Select Bit[9]" "Pull down,Pull up"
|
|
bitfld.long 0x08 8. " [8] ,NHET Pull Select Bit[8]" "Pull down,Pull up"
|
|
newline
|
|
bitfld.long 0x08 7. " [7] ,NHET Pull Select Bit[7]" "Pull down,Pull up"
|
|
bitfld.long 0x08 6. " [6] ,NHET Pull Select Bit[6]" "Pull down,Pull up"
|
|
bitfld.long 0x08 5. " [5] ,NHET Pull Select Bit[5]" "Pull down,Pull up"
|
|
newline
|
|
bitfld.long 0x08 4. " [4] ,NHET Pull Select Bit[4]" "Pull down,Pull up"
|
|
bitfld.long 0x08 3. " [3] ,NHET Pull Select Bit[3]" "Pull down,Pull up"
|
|
bitfld.long 0x08 2. " [2] ,NHET Pull Select Bit[2]" "Pull down,Pull up"
|
|
newline
|
|
bitfld.long 0x08 1. " [1] ,NHET Pull Select Bit[1]" "Pull down,Pull up"
|
|
bitfld.long 0x08 0. " [0] ,NHET Pull Select Bit[0]" "Pull down,Pull up"
|
|
group.long 0x74++0x3
|
|
line.long 0x0 "PCR,Parity Control Register"
|
|
bitfld.long 0x00 8. " TEST ,TEST" "Not mapped,Mapped"
|
|
bitfld.long 0x00 0.--3. " PARITY_ENA ,Enable / Disable Parity Checking" "Enabled,Enabled,Enabled,Enabled,Enabled,Disabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled"
|
|
rgroup.long 0x78++0x3
|
|
line.long 0x0 "PAR,Parity Address Register"
|
|
hexmask.long.word 0x00 2.--12. 0x4 " PAOFF ,Parity Error Address Offset"
|
|
group.long 0x7C++0x0B
|
|
line.long 0x0 "PPR,Parity Pin Register"
|
|
bitfld.long 0x00 31. " HETPPR[31] ,NHET Parity Pin Select Bit[31]" "Low,High"
|
|
bitfld.long 0x00 30. " [30] ,NHET Parity Pin Select Bit[30]" "Low,High"
|
|
bitfld.long 0x00 29. " [29] ,NHET Parity Pin Select Bit[29]" "Low,High"
|
|
bitfld.long 0x00 28. " [28] ,NHET Parity Pin Select Bit[28]" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 27. " [27] ,NHET Parity Pin Select Bit[27]" "Low,High"
|
|
bitfld.long 0x00 26. " [26] ,NHET Parity Pin Select Bit[26]" "Low,High"
|
|
bitfld.long 0x00 25. " [25] ,NHET Parity Pin Select Bit[25]" "Low,High"
|
|
bitfld.long 0x00 24. " [24] ,NHET Parity Pin Select Bit[24]" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 23. " [23] ,NHET Parity Pin Select Bit[23]" "Low,High"
|
|
bitfld.long 0x00 22. " [22] ,NHET Parity Pin Select Bit[22]" "Low,High"
|
|
bitfld.long 0x00 21. " [21] ,NHET Parity Pin Select Bit[21]" "Low,High"
|
|
bitfld.long 0x00 20. " [20] ,NHET Parity Pin Select Bit[20]" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 19. " [19] ,NHET Parity Pin Select Bit[19]" "Low,High"
|
|
bitfld.long 0x00 18. " [18] ,NHET Parity Pin Select Bit[18]" "Low,High"
|
|
bitfld.long 0x00 17. " [17] ,NHET Parity Pin Select Bit[17]" "Low,High"
|
|
bitfld.long 0x00 16. " [16] ,NHET Parity Pin Select Bit[16]" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 15. " [15] ,NHET Parity Pin Select Bit[15]" "Low,High"
|
|
bitfld.long 0x00 14. " [14] ,NHET Parity Pin Select Bit[14]" "Low,High"
|
|
bitfld.long 0x00 13. " [13] ,NHET Parity Pin Select Bit[13]" "Low,High"
|
|
bitfld.long 0x00 12. " [12] ,NHET Parity Pin Select Bit[12]" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 11. " [11] ,NHET Parity Pin Select Bit[11]" "Low,High"
|
|
bitfld.long 0x00 10. " [10] ,NHET Parity Pin Select Bit[10]" "Low,High"
|
|
bitfld.long 0x00 9. " [9] ,NHET Parity Pin Select Bit[9]" "Low,High"
|
|
bitfld.long 0x00 8. " [8] ,NHET Parity Pin Select Bit[8]" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 7. " [7] ,NHET Parity Pin Select Bit[7]" "Low,High"
|
|
bitfld.long 0x00 6. " [6] ,NHET Parity Pin Select Bit[6]" "Low,High"
|
|
bitfld.long 0x00 5. " [5] ,NHET Parity Pin Select Bit[5]" "Low,High"
|
|
bitfld.long 0x00 4. " [4] ,NHET Parity Pin Select Bit[4]" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 3. " [3] ,NHET Parity Pin Select Bit[3]" "Low,High"
|
|
bitfld.long 0x00 2. " [2] ,NHET Parity Pin Select Bit[2]" "Low,High"
|
|
bitfld.long 0x00 1. " [1] ,NHET Parity Pin Select Bit[1]" "Low,High"
|
|
bitfld.long 0x00 0. " [0] ,NHET Parity Pin Select Bit[0]" "Low,High"
|
|
line.long 0x04 "SFPRLD,Suppresion Filter Preload Register"
|
|
bitfld.long 0x04 16.--17. " CCDIV ,Counter Clock Divider" "VCLK2,VCLK2/2,VCLK2/3,VCLK2/4"
|
|
hexmask.long.word 0x04 0.--9. 1. " CPRLD ,Counter Preload Value"
|
|
line.long 0x08 "SFENA,Suppresion Filter Enable Register"
|
|
bitfld.long 0x08 31. " HETSFENA[31] ,Suppression Filter Enable Bit[31]" "Disabled,Enabled"
|
|
bitfld.long 0x08 30. " [30] ,Suppression Filter Enable Bit[30]" "Disabled,Enabled"
|
|
bitfld.long 0x08 29. " [29] ,Suppression Filter Enable Bit[29]" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x08 28. " [28] ,Suppression Filter Enable Bit[28]" "Disabled,Enabled"
|
|
bitfld.long 0x08 27. " [27] ,Suppression Filter Enable Bit[27]" "Disabled,Enabled"
|
|
bitfld.long 0x08 26. " [26] ,Suppression Filter Enable Bit[26]" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x08 25. " [25] ,Suppression Filter Enable Bit[25]" "Disabled,Enabled"
|
|
bitfld.long 0x08 24. " [24] ,Suppression Filter Enable Bit[24]" "Disabled,Enabled"
|
|
bitfld.long 0x08 23. " [23] ,Suppression Filter Enable Bit[23]" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x08 22. " [22] ,Suppression Filter Enable Bit[22]" "Disabled,Enabled"
|
|
bitfld.long 0x08 21. " [21] ,Suppression Filter Enable Bit[21]" "Disabled,Enabled"
|
|
bitfld.long 0x08 20. " [20] ,Suppression Filter Enable Bit[20]" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x08 19. " [19] ,Suppression Filter Enable Bit[19]" "Disabled,Enabled"
|
|
bitfld.long 0x08 18. " [18] ,Suppression Filter Enable Bit[18]" "Disabled,Enabled"
|
|
bitfld.long 0x08 17. " [17] ,Suppression Filter Enable Bit[17]" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x08 16. " [16] ,Suppression Filter Enable Bit[16]" "Disabled,Enabled"
|
|
bitfld.long 0x08 15. " [15] ,Suppression Filter Enable Bit[15]" "Disabled,Enabled"
|
|
bitfld.long 0x08 14. " [14] ,Suppression Filter Enable Bit[14]" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x08 13. " [13] ,Suppression Filter Enable Bit[13]" "Disabled,Enabled"
|
|
bitfld.long 0x08 12. " [12] ,Suppression Filter Enable Bit[12]" "Disabled,Enabled"
|
|
bitfld.long 0x08 11. " [11] ,Suppression Filter Enable Bit[11]" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x08 10. " [10] ,Suppression Filter Enable Bit[10]" "Disabled,Enabled"
|
|
bitfld.long 0x08 9. " [9] ,Suppression Filter Enable Bit[9]" "Disabled,Enabled"
|
|
bitfld.long 0x08 8. " [8] ,Suppression Filter Enable Bit[8]" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x08 7. " [7] ,Suppression Filter Enable Bit[7]" "Disabled,Enabled"
|
|
bitfld.long 0x08 6. " [6] ,Suppression Filter Enable Bit[6]" "Disabled,Enabled"
|
|
bitfld.long 0x08 5. " [5] ,Suppression Filter Enable Bit[5]" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x08 4. " [4] ,Suppression Filter Enable Bit[4]" "Disabled,Enabled"
|
|
bitfld.long 0x08 3. " [3] ,Suppression Filter Enable Bit[3]" "Disabled,Enabled"
|
|
bitfld.long 0x08 2. " [2] ,Suppression Filter Enable Bit[2]" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x08 1. " [1] ,Suppression Filter Enable Bit[1]" "Disabled,Enabled"
|
|
bitfld.long 0x08 0. " [0] ,Suppression Filter Enable Bit[0]" "Disabled,Enabled"
|
|
sif (cpu()!="RM48L952-PGE"&&cpu()!="RM48L952-ZWT"&&cpu()!="RM48L950-PGE"&&cpu()!="RM48L950-ZWT"&&cpu()!="RM48L940-ZWT"&&cpu()!="RM48L940-PGE"&&cpu()!="RM48L930-ZWT"&&cpu()!="RM48L930-PGE"&&cpu()!="RM48L750-ZWT"&&cpu()!="RM48L750-PGE"&&cpu()!="RM48L740-ZWT"&&cpu()!="RM48L740-PGE"&&cpu()!="RM48L730-ZWT"&&cpu()!="RM48L730-PGE"&&cpu()!="RM48L550-PGE"&&cpu()!="RM48L540-ZWT"&&cpu()!="RM48L540-PGE"&&cpu()!="RM48L530-ZWT"&&cpu()!="RM48L530-PGE"&&cpu()!="RM46L852-PGE"&&cpu()!="RM46L852-ZWT"&&cpu()!="RM46L850-PGE"&&cpu()!="RM46L850-ZWT"&&cpu()!="RM46L840-ZWT"&&cpu()!="RM46L840-PGE"&&cpu()!="RM46L830-ZWT"&&cpu()!="RM46L830-PGE"&&cpu()!="RM46L450-ZWT"&&cpu()!="RM46L450-PGE"&&cpu()!="RM46L440-ZWT"&&cpu()!="RM46L440-PGE"&&cpu()!="RM46L430-ZWT"&&cpu()!="RM46L430-PGE"&&cpu()!="TMS570LC4357"&&cpu()!="RM48L550-ZWT"&&cpu()!="RM42L432"&&!cpuis("TMS570LS0232")&&!cpuis("TMS570LS0714*")&&!cpuis("TMS570LS0914*"))
|
|
if ((per.l(ad:0xFFF7B800+0x90)&0xF00)==0xA00)
|
|
group.long 0x8C++0x3
|
|
line.long 0x0 "LBPSEL,Loop Back Pair Select Register"
|
|
bitfld.long 0x00 31. " LBPTYPE[15] ,Loop Back Pair Type Select Bit[15]" "Digital,Analog"
|
|
bitfld.long 0x00 30. " [14] ,Loop Back Pair Type Select Bit[14]" "Digital,Analog"
|
|
newline
|
|
bitfld.long 0x00 29. " [13] ,Loop Back Pair Type Select Bit[13]" "Digital,Analog"
|
|
bitfld.long 0x00 28. " [12] ,Loop Back Pair Type Select Bit[12]" "Digital,Analog"
|
|
newline
|
|
bitfld.long 0x00 27. " [11] ,Loop Back Pair Type Select Bit[11]" "Digital,Analog"
|
|
bitfld.long 0x00 26. " [10] ,Loop Back Pair Type Select Bit[10]" "Digital,Analog"
|
|
newline
|
|
bitfld.long 0x00 25. " [9] ,Loop Back Pair Type Select Bit[9]" "Digital,Analog"
|
|
bitfld.long 0x00 24. " [8] ,Loop Back Pair Type Select Bit[8]" "Digital,Analog"
|
|
newline
|
|
bitfld.long 0x00 23. " [7] ,Loop Back Pair Type Select Bit[7]" "Digital,Analog"
|
|
bitfld.long 0x00 22. " [6] ,Loop Back Pair Type Select Bit[6]" "Digital,Analog"
|
|
newline
|
|
bitfld.long 0x00 21. " [5] ,Loop Back Pair Type Select Bit[5]" "Digital,Analog"
|
|
bitfld.long 0x00 20. " [4] ,Loop Back Pair Type Select Bit[4]" "Digital,Analog"
|
|
newline
|
|
bitfld.long 0x00 19. " [3] ,Loop Back Pair Type Select Bit[3]" "Digital,Analog"
|
|
bitfld.long 0x00 18. " [2] ,Loop Back Pair Type Select Bit[2]" "Digital,Analog"
|
|
newline
|
|
bitfld.long 0x00 17. " [1] ,Loop Back Pair Type Select Bit[1]" "Digital,Analog"
|
|
bitfld.long 0x00 16. " [0] ,Loop Back Pair Type Select Bit[0]" "Digital,Analog"
|
|
newline
|
|
bitfld.long 0x00 15. " LBPSEL[15] ,Loop Back Pair Select Bit[15]" "Not selected,Selected"
|
|
bitfld.long 0x00 14. " [14] ,Loop Back Pair Select Bit[14]" "Not selected,Selected"
|
|
newline
|
|
bitfld.long 0x00 13. " [13] ,Loop Back Pair Select Bit[13]" "Not selected,Selected"
|
|
bitfld.long 0x00 12. " [12] ,Loop Back Pair Select Bit[12]" "Not selected,Selected"
|
|
newline
|
|
bitfld.long 0x00 11. " [11] ,Loop Back Pair Select Bit[11]" "Not selected,Selected"
|
|
bitfld.long 0x00 10. " [10] ,Loop Back Pair Select Bit[10]" "Not selected,Selected"
|
|
newline
|
|
bitfld.long 0x00 9. " [9] ,Loop Back Pair Select Bit[9]" "Not selected,Selected"
|
|
bitfld.long 0x00 8. " [8] ,Loop Back Pair Select Bit[8]" "Not selected,Selected"
|
|
newline
|
|
bitfld.long 0x00 7. " [7] ,Loop Back Pair Select Bit[7]" "Not selected,Selected"
|
|
bitfld.long 0x00 6. " [6] ,Loop Back Pair Select Bit[6]" "Not selected,Selected"
|
|
newline
|
|
bitfld.long 0x00 5. " [5] ,Loop Back Pair Select Bit[5]" "Not selected,Selected"
|
|
bitfld.long 0x00 4. " [4] ,Loop Back Pair Select Bit[4]" "Not selected,Selected"
|
|
newline
|
|
bitfld.long 0x00 3. " [3] ,Loop Back Pair Select Bit[3]" "Not selected,Selected"
|
|
bitfld.long 0x00 2. " [2] ,Loop Back Pair Select Bit[2]" "Not selected,Selected"
|
|
newline
|
|
bitfld.long 0x00 1. " [1] ,Loop Back Pair Select Bit[1]" "Not selected,Selected"
|
|
bitfld.long 0x00 0. " [0] ,Loop Back Pair Select Bit[0]" "Not selected,Selected"
|
|
else
|
|
hgroup.long 0x8C++0x3
|
|
hide.long 0x0 "LBPSEL,Loop Back Pair Select Register"
|
|
endif
|
|
elif cpuis("TMS570LS0232")||cpuis("TMS570LS0714*")||cpuis("TMS570LS0914*")
|
|
if ((per.l.be(ad:0xFFF7B800+0x90)&0xF0000)==0xA0000)
|
|
group.long 0x8C++0x3
|
|
line.long 0x0 "LBPSEL,Loop Back Pair Select Register"
|
|
bitfld.long 0x00 31. " LBPTYPE[31/30] ,Loop Back Pair Type Select Bits 31/30" "Digital,Analog"
|
|
bitfld.long 0x00 30. " [29/28] ,Loop Back Pair Type Select Bits 29/28" "Digital,Analog"
|
|
newline
|
|
bitfld.long 0x00 29. " [27/26] ,Loop Back Pair Type Select Bits 27/26" "Digital,Analog"
|
|
bitfld.long 0x00 28. " [25/24] ,Loop Back Pair Type Select Bits 25/24" "Digital,Analog"
|
|
newline
|
|
bitfld.long 0x00 27. " [23/22] ,Loop Back Pair Type Select Bits 23/22" "Digital,Analog"
|
|
bitfld.long 0x00 26. " [21/20] ,Loop Back Pair Type Select Bits 21/20" "Digital,Analog"
|
|
newline
|
|
bitfld.long 0x00 25. " [19/18] ,Loop Back Pair Type Select Bits 19/18" "Digital,Analog"
|
|
bitfld.long 0x00 24. " [17/16] ,Loop Back Pair Type Select Bits 17/16" "Digital,Analog"
|
|
newline
|
|
bitfld.long 0x00 23. " [15/14] ,Loop Back Pair Type Select Bits 15/14" "Digital,Analog"
|
|
bitfld.long 0x00 22. " [13/12] ,Loop Back Pair Type Select Bits 13/12" "Digital,Analog"
|
|
newline
|
|
bitfld.long 0x00 21. " [11/10] ,Loop Back Pair Type Select Bits 11/10" "Digital,Analog"
|
|
bitfld.long 0x00 20. " [9/8] ,Loop Back Pair Type Select Bits 9/8" "Digital,Analog"
|
|
newline
|
|
bitfld.long 0x00 19. " [7/6] ,Loop Back Pair Type Select Bits 7/6" "Digital,Analog"
|
|
bitfld.long 0x00 18. " [5/4] ,Loop Back Pair Type Select Bits 5/4" "Digital,Analog"
|
|
newline
|
|
bitfld.long 0x00 17. " [3/2] ,Loop Back Pair Type Select Bits 3/2" "Digital,Analog"
|
|
bitfld.long 0x00 16. " [1/0] ,Loop Back Pair Type Select Bits 1/0" "Digital,Analog"
|
|
newline
|
|
bitfld.long 0x00 15. " LBPSEL31/30] ,Loop Back Pair Select Bits 31/30" "Not selected,Selected"
|
|
bitfld.long 0x00 14. " [29/28] ,Loop Back Pair Select Bits 29/28" "Not selected,Selected"
|
|
newline
|
|
bitfld.long 0x00 13. " [27/26] ,Loop Back Pair Select Bits 27/26" "Not selected,Selected"
|
|
bitfld.long 0x00 12. " [25/24] ,Loop Back Pair Select Bits 25/24" "Not selected,Selected"
|
|
newline
|
|
bitfld.long 0x00 11. " [23/22] ,Loop Back Pair Select Bits 23/22" "Not selected,Selected"
|
|
bitfld.long 0x00 10. " [21/20] ,Loop Back Pair Select Bits 21/20" "Not selected,Selected"
|
|
newline
|
|
bitfld.long 0x00 9. " [19/18] ,Loop Back Pair Select Bits 19/18" "Not selected,Selected"
|
|
bitfld.long 0x00 8. " [17/16] ,Loop Back Pair Select Bits 17/16" "Not selected,Selected"
|
|
newline
|
|
bitfld.long 0x00 7. " [15/14] ,Loop Back Pair Select Bits 15/14" "Not selected,Selected"
|
|
bitfld.long 0x00 6. " [13/12] ,Loop Back Pair Select Bits 13/12" "Not selected,Selected"
|
|
newline
|
|
bitfld.long 0x00 5. " [11/10] ,Loop Back Pair Select Bits 11/10" "Not selected,Selected"
|
|
bitfld.long 0x00 4. " [9/8] ,Loop Back Pair Select Bits 9/8" "Not selected,Selected"
|
|
newline
|
|
bitfld.long 0x00 3. " [7/6] ,Loop Back Pair Select Bits 7/6" "Not selected,Selected"
|
|
bitfld.long 0x00 2. " [5/4] ,Loop Back Pair Select Bits 5/4" "Not selected,Selected"
|
|
newline
|
|
bitfld.long 0x00 1. " [3/2] ,Loop Back Pair Select Bits 3/2" "Not selected,Selected"
|
|
bitfld.long 0x00 0. " [1/0] ,Loop Back Pair Select Bits 1/0" "Not selected,Selected"
|
|
else
|
|
hgroup.long 0x8C++0x3
|
|
hide.long 0x0 "LBPSEL,Loop Back Pair Select Register"
|
|
endif
|
|
else
|
|
if ((per.l(ad:0xFFF7B800+0x90)&0xF0000)==0xA0000)
|
|
group.long 0x8C++0x3
|
|
line.long 0x0 "LBPSEL,Loop Back Pair Select Register"
|
|
bitfld.long 0x00 31. " LBPTYPE[15] ,Loop Back Pair Type Select Bit[15]" "Digital,Analog"
|
|
bitfld.long 0x00 30. " [14] ,Loop Back Pair Type Select Bit[14]" "Digital,Analog"
|
|
newline
|
|
bitfld.long 0x00 29. " [13] ,Loop Back Pair Type Select Bit[13]" "Digital,Analog"
|
|
bitfld.long 0x00 28. " [12] ,Loop Back Pair Type Select Bit[12]" "Digital,Analog"
|
|
newline
|
|
bitfld.long 0x00 27. " [11] ,Loop Back Pair Type Select Bit[11]" "Digital,Analog"
|
|
bitfld.long 0x00 26. " [10] ,Loop Back Pair Type Select Bit[10]" "Digital,Analog"
|
|
newline
|
|
bitfld.long 0x00 25. " [9] ,Loop Back Pair Type Select Bit[9]" "Digital,Analog"
|
|
bitfld.long 0x00 24. " [8] ,Loop Back Pair Type Select Bit[8]" "Digital,Analog"
|
|
newline
|
|
bitfld.long 0x00 23. " [7] ,Loop Back Pair Type Select Bit[7]" "Digital,Analog"
|
|
bitfld.long 0x00 22. " [6] ,Loop Back Pair Type Select Bit[6]" "Digital,Analog"
|
|
newline
|
|
bitfld.long 0x00 21. " [5] ,Loop Back Pair Type Select Bit[5]" "Digital,Analog"
|
|
bitfld.long 0x00 20. " [4] ,Loop Back Pair Type Select Bit[4]" "Digital,Analog"
|
|
newline
|
|
bitfld.long 0x00 19. " [3] ,Loop Back Pair Type Select Bit[3]" "Digital,Analog"
|
|
bitfld.long 0x00 18. " [2] ,Loop Back Pair Type Select Bit[2]" "Digital,Analog"
|
|
newline
|
|
bitfld.long 0x00 17. " [1] ,Loop Back Pair Type Select Bit[1]" "Digital,Analog"
|
|
bitfld.long 0x00 16. " [0] ,Loop Back Pair Type Select Bit[0]" "Digital,Analog"
|
|
newline
|
|
bitfld.long 0x00 15. " LBPSEL[15] ,Loop Back Pair Select Bit[15]" "Not selected,Selected"
|
|
bitfld.long 0x00 14. " [14] ,Loop Back Pair Select Bit[14]" "Not selected,Selected"
|
|
newline
|
|
bitfld.long 0x00 13. " [13] ,Loop Back Pair Select Bit[13]" "Not selected,Selected"
|
|
bitfld.long 0x00 12. " [12] ,Loop Back Pair Select Bit[12]" "Not selected,Selected"
|
|
newline
|
|
bitfld.long 0x00 11. " [11] ,Loop Back Pair Select Bit[11]" "Not selected,Selected"
|
|
bitfld.long 0x00 10. " [10] ,Loop Back Pair Select Bit[10]" "Not selected,Selected"
|
|
newline
|
|
bitfld.long 0x00 9. " [9] ,Loop Back Pair Select Bit[9]" "Not selected,Selected"
|
|
bitfld.long 0x00 8. " [8] ,Loop Back Pair Select Bit[8]" "Not selected,Selected"
|
|
newline
|
|
bitfld.long 0x00 7. " [7] ,Loop Back Pair Select Bit[7]" "Not selected,Selected"
|
|
bitfld.long 0x00 6. " [6] ,Loop Back Pair Select Bit[6]" "Not selected,Selected"
|
|
newline
|
|
bitfld.long 0x00 5. " [5] ,Loop Back Pair Select Bit[5]" "Not selected,Selected"
|
|
bitfld.long 0x00 4. " [4] ,Loop Back Pair Select Bit[4]" "Not selected,Selected"
|
|
newline
|
|
bitfld.long 0x00 3. " [3] ,Loop Back Pair Select Bit[3]" "Not selected,Selected"
|
|
bitfld.long 0x00 2. " [2] ,Loop Back Pair Select Bit[2]" "Not selected,Selected"
|
|
newline
|
|
bitfld.long 0x00 1. " [1] ,Loop Back Pair Select Bit[1]" "Not selected,Selected"
|
|
bitfld.long 0x00 0. " [0] ,Loop Back Pair Select Bit[0]" "Not selected,Selected"
|
|
else
|
|
hgroup.long 0x8C++0x3
|
|
hide.long 0x0 "LBPSEL,Loop Back Pair Select Register"
|
|
endif
|
|
endif
|
|
group.long 0x90++0x07
|
|
line.long 0x00 "LBPDIR,Loop Back Pair Direction Register"
|
|
bitfld.long 0x00 16.--19. " IODFTENA ,Module IODFT Enable Key" "Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Enabled,Disabled,Disabled,Disabled,Disabled,Disabled"
|
|
bitfld.long 0x00 15. " LBPDIR[15] ,Loop Back Pair Direction Bit[15]" "Input,Output"
|
|
bitfld.long 0x00 14. " [14] ,Loop Back Pair Direction Bit[14]" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 13. " [13] ,Loop Back Pair Direction Bit[13]" "Input,Output"
|
|
bitfld.long 0x00 12. " [12] ,Loop Back Pair Direction Bit[12]" "Input,Output"
|
|
bitfld.long 0x00 11. " [11] ,Loop Back Pair Direction Bit[11]" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 10. " [10] ,Loop Back Pair Direction Bit[10]" "Input,Output"
|
|
bitfld.long 0x00 9. " [9] ,Loop Back Pair Direction Bit[9]" "Input,Output"
|
|
bitfld.long 0x00 8. " [8] ,Loop Back Pair Direction Bit[8]" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 7. " [7] ,Loop Back Pair Direction Bit[7]" "Input,Output"
|
|
bitfld.long 0x00 6. " [6] ,Loop Back Pair Direction Bit[6]" "Input,Output"
|
|
bitfld.long 0x00 5. " [5] ,Loop Back Pair Direction Bit[5]" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 4. " [4] ,Loop Back Pair Direction Bit[4]" "Input,Output"
|
|
bitfld.long 0x00 3. " [3] ,Loop Back Pair Direction Bit[3]" "Input,Output"
|
|
bitfld.long 0x00 2. " [2] ,Loop Back Pair Direction Bit[2]" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 1. " [1] ,Loop Back Pair Direction Bit[1]" "Input,Output"
|
|
bitfld.long 0x00 0. " [0] ,Loop Back Pair Direction Bit[0]" "Input,Output"
|
|
line.long 0x04 "PINDIS,Pin Disable Register"
|
|
bitfld.long 0x04 31. " HETPINDIS[31] ,NHET Pin Disable Bit[31]" "No,Yes"
|
|
bitfld.long 0x04 30. " [30] ,NHET Pin Disable Bit[30]" "No,Yes"
|
|
bitfld.long 0x04 29. " [29] ,NHET Pin Disable Bit[29]" "No,Yes"
|
|
newline
|
|
bitfld.long 0x04 28. " [28] ,NHET Pin Disable Bit[28]" "No,Yes"
|
|
bitfld.long 0x04 27. " [27] ,NHET Pin Disable Bit[27]" "No,Yes"
|
|
bitfld.long 0x04 26. " [26] ,NHET Pin Disable Bit[26]" "No,Yes"
|
|
newline
|
|
bitfld.long 0x04 25. " [25] ,NHET Pin Disable Bit[25]" "No,Yes"
|
|
bitfld.long 0x04 24. " [24] ,NHET Pin Disable Bit[24]" "No,Yes"
|
|
bitfld.long 0x04 23. " [23] ,NHET Pin Disable Bit[23]" "No,Yes"
|
|
newline
|
|
bitfld.long 0x04 22. " [22] ,NHET Pin Disable Bit[22]" "No,Yes"
|
|
bitfld.long 0x04 21. " [21] ,NHET Pin Disable Bit[21]" "No,Yes"
|
|
bitfld.long 0x04 20. " [20] ,NHET Pin Disable Bit[20]" "No,Yes"
|
|
newline
|
|
bitfld.long 0x04 19. " [19] ,NHET Pin Disable Bit[19]" "No,Yes"
|
|
bitfld.long 0x04 18. " [18] ,NHET Pin Disable Bit[18]" "No,Yes"
|
|
bitfld.long 0x04 17. " [17] ,NHET Pin Disable Bit[17]" "No,Yes"
|
|
newline
|
|
bitfld.long 0x04 16. " [16] ,NHET Pin Disable Bit[16]" "No,Yes"
|
|
bitfld.long 0x04 15. " [15] ,NHET Pin Disable Bit[15]" "No,Yes"
|
|
bitfld.long 0x04 14. " [14] ,NHET Pin Disable Bit[14]" "No,Yes"
|
|
newline
|
|
bitfld.long 0x04 13. " [13] ,NHET Pin Disable Bit[13]" "No,Yes"
|
|
bitfld.long 0x04 12. " [12] ,NHET Pin Disable Bit[12]" "No,Yes"
|
|
bitfld.long 0x04 11. " [11] ,NHET Pin Disable Bit[11]" "No,Yes"
|
|
newline
|
|
bitfld.long 0x04 10. " [10] ,NHET Pin Disable Bit[10]" "No,Yes"
|
|
bitfld.long 0x04 9. " [9] ,NHET Pin Disable Bit[9]" "No,Yes"
|
|
bitfld.long 0x04 8. " [8] ,NHET Pin Disable Bit[8]" "No,Yes"
|
|
newline
|
|
bitfld.long 0x04 7. " [7] ,NHET Pin Disable Bit[7]" "No,Yes"
|
|
bitfld.long 0x04 6. " [6] ,NHET Pin Disable Bit[6]" "No,Yes"
|
|
bitfld.long 0x04 5. " [5] ,NHET Pin Disable Bit[5]" "No,Yes"
|
|
newline
|
|
bitfld.long 0x04 4. " [4] ,NHET Pin Disable Bit[4]" "No,Yes"
|
|
bitfld.long 0x04 3. " [3] ,NHET Pin Disable Bit[3]" "No,Yes"
|
|
bitfld.long 0x04 2. " [2] ,NHET Pin Disable Bit[2]" "No,Yes"
|
|
newline
|
|
bitfld.long 0x04 1. " [1] ,NHET Pin Disable Bit[1]" "No,Yes"
|
|
bitfld.long 0x04 0. " [0] ,NHET Pin Disable Bit[0]" "No,Yes"
|
|
sif cpuis("TMS570LS0714*")||cpuis("TMS570LS0914*")
|
|
width 16.
|
|
group.long 0x9C++0x13 "HWAG Registers"
|
|
line.long 0x00 "HWAPINSEL,HWAG Pin Select Register"
|
|
bitfld.long 0x00 0.--4. " PINSEL ,HWAG pin select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
line.long 0x04 "HWAGCR0,HWAG Control Register 0"
|
|
bitfld.long 0x04 0. " RESET ,HWAG module reset" "Reset,No reset"
|
|
line.long 0x08 "HWAGCR1,HWAG Control Register 1"
|
|
bitfld.long 0x08 0. " PPWN ,HWAG module power down" "Powered up,Powered down"
|
|
line.long 0x0C "HWAGCR2,HWAG Control Register 2"
|
|
bitfld.long 0x0C 24. " ARST ,Angle reset" "No reset,Reset"
|
|
bitfld.long 0x0C 17. " TED ,Tooth edge" "Falling,Rising"
|
|
bitfld.long 0x0C 16. " CRI ,Criteria enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x0C 8. " FIL ,Input filter enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 0. " STRT ,Put the HWAG into run time start bit" "Stopped,Started"
|
|
line.long 0x10 "HWAENA_SET/CLR,HWAG Interrupt Enable Set/Clear Register"
|
|
setclrfld.long 0x10 7. 0x10 7. 0x14 7. " INTENA[7] ,Enable interrupt [7]" "Disabled,Enabled"
|
|
setclrfld.long 0x10 6. 0x10 6. 0x14 6. " [6] ,Enable interrupt [6]" "Disabled,Enabled"
|
|
setclrfld.long 0x10 5. 0x10 5. 0x14 5. " [5] ,Enable interrupt [5]" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x10 4. 0x10 4. 0x14 4. " [4] ,Enable interrupt [4]" "Disabled,Enabled"
|
|
setclrfld.long 0x10 3. 0x10 3. 0x14 3. " [3] ,Enable interrupt [3]" "Disabled,Enabled"
|
|
setclrfld.long 0x10 2. 0x10 2. 0x14 2. " [2] ,Enable interrupt [2]" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x10 1. 0x10 1. 0x14 1. " [1] ,Enable interrupt [1]" "Disabled,Enabled"
|
|
setclrfld.long 0x10 0. 0x10 0. 0x14 0. " [0] ,Enable interrupt [0]" "Disabled,Enabled"
|
|
group.long 0xB0++0x03
|
|
line.long 0x00 "HWALVL_SET/CLR,HWAG Interrupt Priority Set Register"
|
|
setclrfld.long 0x00 7. 0x00 7. 0x04 7. " LVLSET[7] ,Set interrupt [7] priority level" "Low,High"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x04 6. " [6] ,Set interrupt [6] priority level" "Low,High"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x04 5. " [5] ,Set interrupt [5] priority level" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 4. 0x00 4. 0x04 4. " [4] ,Set interrupt [4] priority level" "Low,High"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x04 3. " [3] ,Set interrupt [3] priority level" "Low,High"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x04 2. " [2] ,Set interrupt [2] priority level" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 1. 0x00 1. 0x04 1. " [1] ,Set interrupt [1] priority level" "Low,High"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x04 0. " [0] ,Set interrupt [0] priority level" "Low,High"
|
|
group.long 0xB8++0x27
|
|
line.long 0x00 "HWAFLG,HWAG Interrupt Flags Register"
|
|
eventfld.long 0x00 7. " INTFLG[7] ,Interrupt 7 flag" "No effect,Pending"
|
|
eventfld.long 0x00 6. " [6] ,Interrupt 6 flag" "No effect,Pending"
|
|
eventfld.long 0x00 5. " [5] ,Interrupt 5 flag" "No effect,Pending"
|
|
newline
|
|
eventfld.long 0x00 4. " [4] ,Interrupt 4 flag" "No effect,Pending"
|
|
eventfld.long 0x00 3. " [3] ,Interrupt 3 flag" "No effect,Pending"
|
|
eventfld.long 0x00 2. " [2] ,Interrupt 2 flag" "No effect,Pending"
|
|
newline
|
|
eventfld.long 0x00 1. " [1] ,Interrupt 1 flag" "No effect,Pending"
|
|
eventfld.long 0x00 0. " [0] ,Interrupt 0 flag" "No effect,Pending"
|
|
line.long 0x04 "HWAOFF0,HWAG Interrupt Offset Register 0"
|
|
hexmask.long.byte 0x04 0.--7. 0x01 " OFFSET1 ,High-priority interrupt offset"
|
|
line.long 0x08 "HWAOFF1,HWAG Interrupt Offset Register 1"
|
|
hexmask.long.byte 0x08 0.--7. 0x01 " OFFSET2 ,Low-priority interrupt offset"
|
|
line.long 0x0C "HWAACNT,HWAG ACNT Register, HWAG Angle Value"
|
|
hexmask.long.tbyte 0x0C 0.--23. 1. " ACNT ,Angle value"
|
|
line.long 0x10 "HWAPCNT1,HWAG PCNT (n-1) Register, HWAG Previous Tooth Period"
|
|
hexmask.long.tbyte 0x10 0.--23. 1. " PCNT(N-1) ,Period (n-1) value"
|
|
line.long 0x14 "HWAPCNT,HWAG PCNT (n) Register, HWAG Current Tooth Period"
|
|
hexmask.long.tbyte 0x14 0.--23. 1. " PCNT(N) ,Period (n) value"
|
|
line.long 0x18 "HWASTWD,HWAG Step Register"
|
|
bitfld.long 0x18 0.--3. " STWD ,Step width (ticks per period)" "4,8,16,32,64,128,256,512,1024,2048,4096,8192,16384,32768,65536,131072"
|
|
line.long 0x1C "HWATHNB,HWAG Teeth Number Register"
|
|
hexmask.long.byte 0x1C 0.--7. 1. " THNB ,Teeth number"
|
|
line.long 0x20 "HWATHVL,HHWAG Current Teeth Number Register"
|
|
hexmask.long.byte 0x20 0.--7. 1. " THVL ,Teeth value"
|
|
line.long 0x24 "HWAFIL,HWAG Filter Register"
|
|
hexmask.long.word 0x24 0.--9. 1. " FIL1 ,Filter value 1"
|
|
group.long 0xE8++0x07
|
|
line.long 0x00 "HWAFIL2,HWAG Filter Register 2, HWAG Tick Counter Compare Value During Singularity Tooth"
|
|
hexmask.long.word 0x00 0.--11. 1. " FIL2 ,Filter value 2"
|
|
line.long 0x04 "HWAANGI,HWAG Angle Increment Register"
|
|
hexmask.long.word 0x04 0.--9. 1. " ANGI ,Angle increment value"
|
|
elif (cpu()==("TMS570LS2126")||cpu()==("TMS570LS2127")||cpu()==("TMS570LS2136")||cpu()==("TMS570LS2137")||cpu()==("TMS570LS2125-PGE")||cpu()==("TMS570LS2125-ZWT")||cpu()==("TMS570LS2135-PGE")||cpu()==("TMS570LS2135-ZWT")||cpu()==("TMS570LS2124-PGE")||cpu()==("TMS570LS2124-ZWT")||cpu()==("TMS570LS2134-PGE")||cpu()==("TMS570LS2134-ZWT")||cpu()==("TMS570LS3134-PGE")||cpu()==("TMS570LS3134-ZWT")||cpu()==("TMS570LS3135-PGE")||cpu()==("TMS570LS3135-ZWT")||cpu()==("TMS570LS3136")||cpu()==("TMS570LS3137-PGE")||cpu()==("TMS570LS3137-ZWT")||cpu()==("TMS570LS30336")||cpuis("RM48L950*"))
|
|
group.long 0xA0++0x43
|
|
line.long 0x00 "HWAGCR0,HWAG Control Register 0"
|
|
line.long 0x04 "HWAGCR1,HWAG Control Register 1"
|
|
line.long 0x08 "HWAGCR2,HWAG Control Register 2"
|
|
line.long 0x0C "HWAENASET,HWAG Interrupt Enable Set Register"
|
|
line.long 0x10 "HWAENACLR,HWAG Interrupt Enable Clear Register"
|
|
line.long 0x14 "HWALVLSET,HWAG Interrupt Priority Set Register"
|
|
line.long 0x18 "HWALVLCLR,HWAG Interrupt Priority Clear Register"
|
|
line.long 0x1C "HWAFLG,HWAG Interrupt Flags Register"
|
|
line.long 0x20 "HWAOFF0,HWAG Interrupt Offset Register 1, HWAG Low Priority Interrupt Offset"
|
|
line.long 0x24 "HWAOFF1,HWAG Interrupt Offset Register 2, HWAG High Priority Interrupt Offset"
|
|
line.long 0x28 "HWAACNT,HWAG ACNT Register, HWAG Angle Value"
|
|
line.long 0x2C "HWAPCNT1,HWAG PCNT (n-1) Register, HWAG Previous Tooth Period"
|
|
line.long 0x30 "HWAPCNT,HWAG PCNT (n) Register, HWAG Current Tooth Period"
|
|
line.long 0x34 "HWASTWD,HWAG Step Register"
|
|
line.long 0x38 "HWATHNB,HWAG Teeth Number Register"
|
|
line.long 0x3C "HWATHVL,HHWAG Current Teeth Number Register"
|
|
line.long 0x40 "HWAFIL,HWAG Filter Register, HWAG Tick Counter Compare Value"
|
|
group.long 0xE8++0x07
|
|
line.long 0x00 "HWAFIL2,HWAG Filter Register 2, HWAG Tick Counter Compare Value During Singularity Tooth"
|
|
line.long 0x04 "HWAANGI,HWAG Angle Increment Register"
|
|
endif
|
|
sif cpuis("TMS570LS0232")||cpuis("TMS570LS0714*")||cpuis("TMS570LS0914*")
|
|
endian.le
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
tree "N2HET2"
|
|
base ad:0xFFF7B900
|
|
sif cpuis("TMS570LS0232")||cpuis("TMS570LS0714*")||cpuis("TMS570LS0914*")
|
|
endian.be
|
|
endif
|
|
width 15.
|
|
group.long 0x00++0x07
|
|
line.long 0x0 "GCR,Global Control Register"
|
|
bitfld.long 0x00 24. " HET_PIN_ENA ,NHET Pin Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 21.--22. " MP ,Master Priority" "Lower,Higher,Round robin,?..."
|
|
bitfld.long 0x00 18. " PPF ,Protect Program Fields" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 17. " IS ,Ignore Suspend" "Not ignored,Ignored"
|
|
bitfld.long 0x00 16. " CMS ,Clk_master/Slave" "Slave,Master"
|
|
bitfld.long 0x00 0. " TO ,Turn On/Off" "Off,On"
|
|
line.long 0x04 "PFR,Prescaler Factor Register"
|
|
bitfld.long 0x04 8.--10. " LRPFC ,Loop Resolution Pre-scale Factor Code" "1,2,4,8,16,32,64,128"
|
|
bitfld.long 0x04 0.--5. " HRPFC ,HR Prescale Factor Code" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64"
|
|
rgroup.long 0x08++0x0B
|
|
line.long 0x0 "ADDR,Current Address Register"
|
|
hexmask.long.word 0x00 0.--8. 1. " HETADDR ,N2HET Current Address"
|
|
line.long 0x04 "OFF1,Offset Level 1 Register"
|
|
hexmask.long.byte 0x04 0.--5. 1. " Offset1 ,Indexes the Currently Pending High-Priority Interrupt"
|
|
line.long 0x08 "OFF2,Offset Level 2 Register"
|
|
hexmask.long.byte 0x08 0.--5. 1. " Offset2 ,Indexes the Currently Pending High-Priority Interrupt"
|
|
newline
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "INTENA_SETCLR,Interrupt Enable Set/Clear Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x04 31. " HETINTENAS_setclr[31] ,Interrupt Enable Set Pin 31" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x04 30. " [30] ,Interrupt enable set/clear bit 30" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x04 29. " [29] ,Interrupt enable set/clear bit 29" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x04 28. " [28] ,Interrupt enable set/clear bit 28" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 27. 0x00 27. 0x04 27. " [27] ,Interrupt enable set/clear bit 27" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x04 26. " [26] ,Interrupt enable set/clear bit 26" "Disabled,Enabled"
|
|
setclrfld.long 0x00 25. 0x00 25. 0x04 25. " [25] ,Interrupt enable set/clear bit 25" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x04 24. " [24] ,Interrupt enable set/clear bit 24" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 23. 0x00 23. 0x04 23. " [23] ,Interrupt enable set/clear bit 23" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x04 22. " [22] ,Interrupt enable set/clear bit 22" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x04 21. " [21] ,Interrupt enable set/clear bit 21" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x04 20. " [20] ,Interrupt enable set/clear bit 20" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 19. 0x00 19. 0x04 19. " [19] ,Interrupt enable set/clear bit 19" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x04 18. " [18] ,Interrupt enable set/clear bit 18" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x04 17. " [17] ,Interrupt enable set/clear bit 17" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x04 16. " [16] ,Interrupt enable set/clear bit 16" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 15. 0x00 15. 0x04 15. " [15] ,Interrupt enable set/clear bit 15" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x04 14. " [14] ,Interrupt enable set/clear bit 14" "Disabled,Enabled"
|
|
setclrfld.long 0x00 13. 0x00 13. 0x04 13. " [13] ,Interrupt enable set/clear bit 13" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x04 12. " [12] ,Interrupt enable set/clear bit 12" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 11. 0x00 11. 0x04 11. " [11] ,Interrupt enable set/clear bit 11" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x04 10. " [10] ,Interrupt enable set/clear bit 10" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x04 9. " [9] ,Interrupt enable set/clear bit 9" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x04 8. " [8] ,Interrupt enable set/clear bit 8" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 7. 0x00 7. 0x04 7. " [7] ,Interrupt enable set/clear bit 7" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x04 6. " [6] ,Interrupt enable set/clear bit 6" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x04 5. " [5] ,Interrupt enable set/clear bit 5" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x04 4. " [4] ,Interrupt enable set/clear bit 4" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 3. 0x00 3. 0x04 3. " [3] ,Interrupt enable set/clear bit 3" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x04 2. " [2] ,Interrupt enable set/clear bit 2" "Disabled,Enabled"
|
|
setclrfld.long 0x00 1. 0x00 1. 0x04 1. " [1] ,Interrupt enable set/clear bit 1" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x04 0. " [0] ,Interrupt enable set/clear bit 0" "Disabled,Enabled"
|
|
newline
|
|
group.long 0x1C++0x0F
|
|
line.long 0x00 "EXC1,Exception Control Register 1"
|
|
bitfld.long 0x00 24. " APCNT_OVRFL_ENA ,APCNT Overflow Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " APCNT_UNDRFL_ENA ,APCNT Underflow Enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 8. " PRGM_OVRFL_ENA ,Program Overflow Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " APCNT_OVRFL_ENA_PRY ,APCNT_Ovrfl_Ena Priority" "Level 2,Level 1"
|
|
newline
|
|
bitfld.long 0x00 1. " APCNT_UNDRFL_ENA_PRY ,APCNT_Undrfl_Ena Priority" "Level 2,Level 1"
|
|
bitfld.long 0x00 0. " PRGM_OVRFL_ENA_PRY ,Prgm_Ovrfl_Ena Priority" "Level 2,Level 1"
|
|
line.long 0x04 "EXC2,Exception Control Register 2"
|
|
eventfld.long 0x04 8. " DEBUG_STATUS_FLG ,Debug_Status Flag" "No NHET,NHET"
|
|
eventfld.long 0x04 2. " APCNT_OVRFL_FLG ,APCNT Overflow Flag" "Not occurred,Occurred"
|
|
newline
|
|
eventfld.long 0x04 1. " APCNT_UNDRFL_FLG ,APCNT Underflow Flag" "Not occurred,Occurred"
|
|
eventfld.long 0x04 0. " PRGM_OVERFL_FLG ,Program Overflow Flag" "Not occurred,Occurred"
|
|
newline
|
|
line.long 0x08 "PRY,Interrupt Priority Register"
|
|
bitfld.long 0x08 31. " HETPRY[31] ,HET Priority Level Bit[31]" "Level 2,Level 1"
|
|
bitfld.long 0x08 30. " [30] ,HET Priority Level Bit[30]" "Level 2,Level 1"
|
|
bitfld.long 0x08 29. " [29] ,HET Priority Level Bit[29]" "Level 2,Level 1"
|
|
newline
|
|
bitfld.long 0x08 28. " [28] ,HET Priority Level Bit[28]" "Level 2,Level 1"
|
|
bitfld.long 0x08 27. " [27] ,HET Priority Level Bit[27]" "Level 2,Level 1"
|
|
bitfld.long 0x08 26. " [26] ,HET Priority Level Bit[26]" "Level 2,Level 1"
|
|
newline
|
|
bitfld.long 0x08 25. " [25] ,HET Priority Level Bit[25]" "Level 2,Level 1"
|
|
bitfld.long 0x08 24. " [24] ,HET Priority Level Bit[24]" "Level 2,Level 1"
|
|
bitfld.long 0x08 23. " [23] ,HET Priority Level Bit[23]" "Level 2,Level 1"
|
|
newline
|
|
bitfld.long 0x08 22. " [22] ,HET Priority Level Bit[22]" "Level 2,Level 1"
|
|
bitfld.long 0x08 21. " [21] ,HET Priority Level Bit[21]" "Level 2,Level 1"
|
|
bitfld.long 0x08 20. " [20] ,HET Priority Level Bit[20]" "Level 2,Level 1"
|
|
newline
|
|
bitfld.long 0x08 19. " [19] ,HET Priority Level Bit[19]" "Level 2,Level 1"
|
|
bitfld.long 0x08 18. " [18] ,HET Priority Level Bit[18]" "Level 2,Level 1"
|
|
bitfld.long 0x08 17. " [17] ,HET Priority Level Bit[17]" "Level 2,Level 1"
|
|
newline
|
|
bitfld.long 0x08 16. " [16] ,HET Priority Level Bit[16]" "Level 2,Level 1"
|
|
bitfld.long 0x08 15. " [15] ,HET Priority Level Bit[15]" "Level 2,Level 1"
|
|
bitfld.long 0x08 14. " [14] ,HET Priority Level Bit[14]" "Level 2,Level 1"
|
|
newline
|
|
bitfld.long 0x08 13. " [13] ,HET Priority Level Bit[13]" "Level 2,Level 1"
|
|
bitfld.long 0x08 12. " [12] ,HET Priority Level Bit[12]" "Level 2,Level 1"
|
|
bitfld.long 0x08 11. " [11] ,HET Priority Level Bit[11]" "Level 2,Level 1"
|
|
newline
|
|
bitfld.long 0x08 10. " [10] ,HET Priority Level Bit[10]" "Level 2,Level 1"
|
|
bitfld.long 0x08 9. " [9] ,HET Priority Level Bit[9]" "Level 2,Level 1"
|
|
bitfld.long 0x08 8. " [8] ,HET Priority Level Bit[8]" "Level 2,Level 1"
|
|
newline
|
|
bitfld.long 0x08 7. " [7] ,HET Priority Level Bit[7]" "Level 2,Level 1"
|
|
bitfld.long 0x08 6. " [6] ,HET Priority Level Bit[6]" "Level 2,Level 1"
|
|
bitfld.long 0x08 5. " [5] ,HET Priority Level Bit[5]" "Level 2,Level 1"
|
|
newline
|
|
bitfld.long 0x08 4. " [4] ,HET Priority Level Bit[4]" "Level 2,Level 1"
|
|
bitfld.long 0x08 3. " [3] ,HET Priority Level Bit[3]" "Level 2,Level 1"
|
|
bitfld.long 0x08 2. " [2] ,HET Priority Level Bit[2]" "Level 2,Level 1"
|
|
newline
|
|
bitfld.long 0x08 1. " [1] ,HET Priority Level Bit[1]" "Level 2,Level 1"
|
|
bitfld.long 0x08 0. " HETPRY[0] ,HET Priority Level Bit[0]" "Level 2,Level 1"
|
|
line.long 0x0C "FLG,Interrupt Flag Register"
|
|
eventfld.long 0x0C 31. " HETFLAG[31] ,Interrupt Flag Register Bit[31]" "No interrupt,Interrupt"
|
|
eventfld.long 0x0C 30. " [30] ,Interrupt Flag Register Bit[30]" "No interrupt,Interrupt"
|
|
newline
|
|
eventfld.long 0x0C 29. " [29] ,Interrupt Flag Register Bit[29]" "No interrupt,Interrupt"
|
|
eventfld.long 0x0C 28. " [28] ,Interrupt Flag Register Bit[28]" "No interrupt,Interrupt"
|
|
newline
|
|
eventfld.long 0x0C 27. " [27] ,Interrupt Flag Register Bit[27]" "No interrupt,Interrupt"
|
|
eventfld.long 0x0C 26. " [26] ,Interrupt Flag Register Bit[26]" "No interrupt,Interrupt"
|
|
newline
|
|
eventfld.long 0x0C 25. " [25] ,Interrupt Flag Register Bit[25]" "No interrupt,Interrupt"
|
|
eventfld.long 0x0C 24. " [24] ,Interrupt Flag Register Bit[24]" "No interrupt,Interrupt"
|
|
newline
|
|
eventfld.long 0x0C 23. " [23] ,Interrupt Flag Register Bit[23]" "No interrupt,Interrupt"
|
|
eventfld.long 0x0C 22. " [22] ,Interrupt Flag Register Bit[22]" "No interrupt,Interrupt"
|
|
newline
|
|
eventfld.long 0x0C 21. " [21] ,Interrupt Flag Register Bit[21]" "No interrupt,Interrupt"
|
|
eventfld.long 0x0C 20. " [20] ,Interrupt Flag Register Bit[20]" "No interrupt,Interrupt"
|
|
newline
|
|
eventfld.long 0x0C 19. " [19] ,Interrupt Flag Register Bit[19]" "No interrupt,Interrupt"
|
|
eventfld.long 0x0C 18. " [18] ,Interrupt Flag Register Bit[18]" "No interrupt,Interrupt"
|
|
newline
|
|
eventfld.long 0x0C 17. " [17] ,Interrupt Flag Register Bit[17]" "No interrupt,Interrupt"
|
|
eventfld.long 0x0C 16. " [16] ,Interrupt Flag Register Bit[16]" "No interrupt,Interrupt"
|
|
newline
|
|
eventfld.long 0x0C 15. " [15] ,Interrupt Flag Register Bit[15]" "No interrupt,Interrupt"
|
|
eventfld.long 0x0C 14. " [14] ,Interrupt Flag Register Bit[14]" "No interrupt,Interrupt"
|
|
newline
|
|
eventfld.long 0x0C 13. " [13] ,Interrupt Flag Register Bit[13]" "No interrupt,Interrupt"
|
|
eventfld.long 0x0C 12. " [12] ,Interrupt Flag Register Bit[12]" "No interrupt,Interrupt"
|
|
newline
|
|
eventfld.long 0x0C 11. " [11] ,Interrupt Flag Register Bit[11]" "No interrupt,Interrupt"
|
|
eventfld.long 0x0C 10. " [10] ,Interrupt Flag Register Bit[10]" "No interrupt,Interrupt"
|
|
newline
|
|
eventfld.long 0x0C 9. " [9] ,Interrupt Flag Register Bit[9]" "No interrupt,Interrupt"
|
|
eventfld.long 0x0C 8. " [8] ,Interrupt Flag Register Bit[8]" "No interrupt,Interrupt"
|
|
newline
|
|
eventfld.long 0x0C 7. " [7] ,Interrupt Flag Register Bit[7]" "No interrupt,Interrupt"
|
|
eventfld.long 0x0C 6. " [6] ,Interrupt Flag Register Bit[6]" "No interrupt,Interrupt"
|
|
newline
|
|
eventfld.long 0x0C 5. " [5] ,Interrupt Flag Register Bit[5]" "No interrupt,Interrupt"
|
|
eventfld.long 0x0C 4. " [4] ,Interrupt Flag Register Bit[4]" "No interrupt,Interrupt"
|
|
newline
|
|
eventfld.long 0x0C 3. " [3] ,Interrupt Flag Register Bit[3]" "No interrupt,Interrupt"
|
|
eventfld.long 0x0C 2. " [2] ,Interrupt Flag Register Bit[2]" "No interrupt,Interrupt"
|
|
newline
|
|
eventfld.long 0x0C 1. " [1] ,Interrupt Flag Register Bit[1]" "No interrupt,Interrupt"
|
|
eventfld.long 0x0C 0. " [0] ,Interrupt Flag Register Bit[0]" "No interrupt,Interrupt"
|
|
sif (CPU()==("TMS570LS2124-PGE")||CPU()==("TMS570LS2124-ZWT")||CPU()==("TMS570LS2134-PGE")||CPU()==("TMS570LS2134-ZWT")||CPU()==("TMS570LS3134-PGE")||CPU()==("TMS570LS3134-ZWT")||CPU()==("TMS570LS3135-PGE")||CPU()==("TMS570LS3135-ZWT")||CPU()==("TMS570LS3136")||CPU()==("TMS570LS3137-PGE")||CPU()==("TMS570LS3137-ZWT")||CPU()==("TMS570LS30336")||CPU()==("TMS570LS2126")||CPU()==("TMS570LS2127")||CPU()==("TMS570LS2136")||CPU()==("TMS570LS2137")||CPU()==("TMS570LS2125-PGE")||CPU()==("TMS570LS2125-ZWT")||CPU()==("TMS570LS2135-PGE")||CPU()==("TMS570LS2135-ZWT")||CPU()==("RM48L950")||cpu()=="RM48L952-PGE"||cpu()=="RM48L952-ZWT"||CPU()=="RM48L950-PGE"||CPU()=="RM48L950-ZWT"||CPU()=="RM48L940-ZWT"||CPU()=="RM48L940-PGE"||CPU()=="RM48L930-ZWT"||CPU()=="RM48L930-PGE"||CPU()=="RM48L750-ZWT"||CPU()=="RM48L750-PGE"||CPU()=="RM48L740-ZWT"||CPU()=="RM48L740-PGE"||CPU()=="RM48L730-ZWT"||CPU()=="RM48L730-PGE"||CPU()=="RM48L550-PGE"||CPU()=="RM48L540-ZWT"||CPU()=="RM48L540-PGE"||CPU()=="RM48L530-ZWT"||CPU()=="RM48L530-PGE"||CPU()=="RM46L852-PGE"||CPU()=="RM46L852-ZWT"||CPU()=="RM46L850-PGE"||CPU()=="RM46L850-ZWT"||CPU()=="RM46L840-ZWT"||CPU()=="RM46L840-PGE"||CPU()=="RM46L830-ZWT"||CPU()=="RM46L830-PGE"||CPU()=="RM46L450-ZWT"||CPU()=="RM46L450-PGE"||CPU()=="RM46L440-ZWT"||CPU()=="RM46L440-PGE"||CPU()=="RM46L430-ZWT"||CPU()=="RM46L430-PGE"||CPU()=="RM42L432"||CPU()=="TMS570LC4357"||CPU()==("TMS570LS0332")||CPU()==("TMS570LS0432")||CPUIS("TMS570LS1114*")||CPUIS("TMS570LS1115*")||CPUIS("TMS570LS1224*")||CPUIS("TMS570LS1225*")||CPUIS("TMS570LS1227*")||cpuis("TMS570LS0232")||cpuis("TMS570LS0714*")||cpuis("TMS570LS0914*"))
|
|
group.long 0x2C++0x3
|
|
line.long 0x00 "HETAND,And Share Control Register"
|
|
bitfld.long 0x00 15. " AND_SHARE[31/30] ,And share 31/30" "Not shared,Shared"
|
|
bitfld.long 0x00 14. " [29/28] ,And share 29/28" "Not shared,Shared"
|
|
newline
|
|
bitfld.long 0x00 13. " [27/26] ,And share 27/26" "Not shared,Shared"
|
|
bitfld.long 0x00 12. " [25/24] ,And share 25/24" "Not shared,Shared"
|
|
newline
|
|
bitfld.long 0x00 11. " [23/22] ,And share 23/22" "Not shared,Shared"
|
|
bitfld.long 0x00 10. " [21/20] ,And share 21/20" "Not shared,Shared"
|
|
newline
|
|
bitfld.long 0x00 9. " [19/18] ,And share 19/18" "Not shared,Shared"
|
|
bitfld.long 0x00 8. " [17/16] ,And share 17/16" "Not shared,Shared"
|
|
newline
|
|
bitfld.long 0x00 7. " [15/14] ,And share 15/14" "Not shared,Shared"
|
|
bitfld.long 0x00 6. " [13/12] ,And share 13/12" "Not shared,Shared"
|
|
newline
|
|
bitfld.long 0x00 5. " [11/10] ,And share 11/10" "Not shared,Shared"
|
|
bitfld.long 0x00 4. " [9/8] ,And share 9/8" "Not shared,Shared"
|
|
newline
|
|
bitfld.long 0x00 3. " [7/6] ,And share 7/6" "Not shared,Shared"
|
|
bitfld.long 0x00 2. " [5/4] ,And share 5/4" "Not shared,Shared"
|
|
newline
|
|
bitfld.long 0x00 1. " [3/2] ,And share 3/2" "Not shared,Shared"
|
|
bitfld.long 0x00 0. " [1/0] ,And share 1/0" "Not shared,Shared"
|
|
endif
|
|
group.long 0x34++0x07
|
|
line.long 0x0 "HRSH,HR Share Control Register"
|
|
bitfld.long 0x00 15. " HR_SHARE[31/30] ,HR Share 31/30" "Not shared,Shared"
|
|
bitfld.long 0x00 14. " [29/28] ,HR Share 29/28" "Not shared,Shared"
|
|
newline
|
|
bitfld.long 0x00 13. " [27/26] ,HR Share 27/26" "Not shared,Shared"
|
|
bitfld.long 0x00 12. " [25/24] ,HR Share 25/24" "Not shared,Shared"
|
|
newline
|
|
bitfld.long 0x00 11. " [23/22] ,HR Share 23/22" "Not shared,Shared"
|
|
bitfld.long 0x00 10. " [21/20] ,HR Share 21/20" "Not shared,Shared"
|
|
newline
|
|
bitfld.long 0x00 9. " [19/18] ,HR Share 19/18" "Not shared,Shared"
|
|
bitfld.long 0x00 8. " [17/16] ,HR Share 17/16" "Not shared,Shared"
|
|
newline
|
|
bitfld.long 0x00 7. " [15/14] ,HR Share 15/14" "Not shared,Shared"
|
|
bitfld.long 0x00 6. " [13/12] ,HR Share 13/12" "Not shared,Shared"
|
|
newline
|
|
bitfld.long 0x00 5. " [11/10] ,HR Share 11/10" "Not shared,Shared"
|
|
bitfld.long 0x00 4. " [9/8] ,HR Share 9/8" "Not shared,Shared"
|
|
newline
|
|
bitfld.long 0x00 3. " [7/6] ,HR Share 7/6" "Not shared,Shared"
|
|
bitfld.long 0x00 2. " [5/4] ,HR Share 5/4" "Not shared,Shared"
|
|
newline
|
|
bitfld.long 0x00 1. " [3/2] ,HR Share 3/2" "Not shared,Shared"
|
|
bitfld.long 0x00 0. " [1/0] ,HR Share 1/0" "Not shared,Shared"
|
|
line.long 0x04 "XOR,HR XOR Control Register"
|
|
bitfld.long 0x04 15. " HR_XOR_SHARE[31/30] ,HR XOR-Share 31/30" "Not XOR-shared,XOR-shared"
|
|
bitfld.long 0x04 14. " [29/28] ,HR XOR-Share 29/28" "Not XOR-shared,XOR-shared"
|
|
newline
|
|
bitfld.long 0x04 13. " [27/26] ,HR XOR-Share 27/26" "Not XOR-shared,XOR-shared"
|
|
bitfld.long 0x04 12. " [25/24] ,HR XOR-Share 25/24" "Not XOR-shared,XOR-shared"
|
|
newline
|
|
bitfld.long 0x04 11. " [23/22] ,HR XOR-Share 23/22" "Not XOR-shared,XOR-shared"
|
|
bitfld.long 0x04 10. " [21/20] ,HR XOR-Share 21/20" "Not XOR-shared,XOR-shared"
|
|
newline
|
|
bitfld.long 0x04 9. " [19/18] ,HR XOR-Share 19/18" "Not XOR-shared,XOR-shared"
|
|
bitfld.long 0x04 8. " [17/16] ,HR XOR-Share 17/16" "Not XOR-shared,XOR-shared"
|
|
newline
|
|
bitfld.long 0x04 7. " [15/14] ,HR XOR-Share 15/14" "Not XOR-shared,XOR-shared"
|
|
bitfld.long 0x04 6. " [13/12] ,HR XOR-Share 13/12" "Not XOR-shared,XOR-shared"
|
|
newline
|
|
bitfld.long 0x04 5. " [11/10] ,HR XOR-Share 11/10" "Not XOR-shared,XOR-shared"
|
|
bitfld.long 0x04 4. " [9/8] ,HR XOR-Share 9/8" "Not XOR-shared,XOR-shared"
|
|
newline
|
|
bitfld.long 0x04 3. " [7/6] ,HR XOR-Share 7/6" "Not XOR-shared,XOR-shared"
|
|
bitfld.long 0x04 2. " [5/4] ,HR XOR-Share 5/4" "Not XOR-shared,XOR-shared"
|
|
newline
|
|
bitfld.long 0x04 1. " [3/2] ,HR XOR-Share 3/2" "Not XOR-shared,XOR-shared"
|
|
bitfld.long 0x04 0. " [1/0] ,HR XOR-Share 1/0" "Not XOR-shared,XOR-shared"
|
|
group.long 0x3C++0x03
|
|
line.long 0x00 "REQEN_SETCLR,Request Enable Set/Clear Register"
|
|
setclrfld.long 0x00 7. 0x00 7. 0x04 7. " REQENA_SET/CLR[7] ,Request enable set/clear bit [7]" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x04 6. " [6] ,Request enable set/clear bit [6]" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x04 5. " [5] ,Request enable set/clear bit [5]" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x04 4. " [4] ,Request enable set/clear bit [4]" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 3. 0x00 3. 0x04 3. " [3] ,Request enable set/clear bit [3]" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x04 2. " [2] ,Request enable set/clear bit [2]" "Disabled,Enabled"
|
|
setclrfld.long 0x00 1. 0x00 1. 0x04 1. " [1] ,Request enable set/clear bit [1]" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x04 0. " [0] ,Request enable set/clear bit [0]" "Disabled,Enabled"
|
|
sif (cpu()!=("TMS570LS0332")&&cpu()!=("TMS570LS0432")&&!cpuis("TMS570LS0232"))
|
|
group.long 0x44++0x3
|
|
line.long 0x00 "REQDS,Request Destination Select Register"
|
|
bitfld.long 0x00 23. " TDBS[7] ,HTU/DMA or Both Select Bit[7]" "HTU,Both"
|
|
bitfld.long 0x00 22. " [6] ,HTU/DMA or Both Select Bit[6]" "HTU,Both"
|
|
bitfld.long 0x00 21. " [5] ,HTU/DMA or Both Select Bit[5]" "HTU,Both"
|
|
bitfld.long 0x00 20. " [4] ,HTU/DMA or Both Select Bit[4]" "HTU,Both"
|
|
newline
|
|
bitfld.long 0x00 19. " [3] ,HTU/DMA or Both Select Bit[3]" "HTU,Both"
|
|
bitfld.long 0x00 18. " [2] ,HTU/DMA or Both Select Bit[2]" "HTU,Both"
|
|
bitfld.long 0x00 17. " [1] ,HTU/DMA or Both Select Bit[1]" "HTU,Both"
|
|
bitfld.long 0x00 16. " [0] ,HTU/DMA or Both Select Bit[0]" "HTU,Both"
|
|
newline
|
|
bitfld.long 0x00 7. " TDS[7] ,HTU or DMA Select Bit[7]" "HTU,DMA"
|
|
bitfld.long 0x00 6. " TDS[6] ,HTU or DMA Select Bit[6]" "HTU,DMA"
|
|
bitfld.long 0x00 5. " TDS[5] ,HTU or DMA Select Bit[5]" "HTU,DMA"
|
|
bitfld.long 0x00 4. " TDS[4] ,HTU or DMA Select Bit[4]" "HTU,DMA"
|
|
newline
|
|
bitfld.long 0x00 3. " TDS[3] ,HTU or DMA Select Bit[3]" "HTU,DMA"
|
|
bitfld.long 0x00 2. " TDS[2] ,HTU or DMA Select Bit[2]" "HTU,DMA"
|
|
bitfld.long 0x00 1. " TDS[1] ,HTU or DMA Select Bit[1]" "HTU,DMA"
|
|
bitfld.long 0x00 0. " TDS[0] ,HTU or DMA Select Bit[0]" "HTU,DMA"
|
|
endif
|
|
group.long 0x4C++0x3
|
|
line.long 0x00 "DIR,Direction Register"
|
|
bitfld.long 0x00 31. " HET_DIR[31] ,Input/Output Direction Pin 31" "Input,Output"
|
|
bitfld.long 0x00 30. " [30] ,Input/Output Direction Pin 30" "Input,Output"
|
|
bitfld.long 0x00 29. " [29] ,Input/Output Direction Pin 29" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 28. " [28] ,Input/Output Direction Pin 28" "Input,Output"
|
|
bitfld.long 0x00 27. " [27] ,Input/Output Direction Pin 27" "Input,Output"
|
|
bitfld.long 0x00 26. " [26] ,Input/Output Direction Pin 26" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 25. " [25] ,Input/Output Direction Pin 25" "Input,Output"
|
|
bitfld.long 0x00 24. " [24] ,Input/Output Direction Pin 24" "Input,Output"
|
|
bitfld.long 0x00 23. " [23] ,Input/Output Direction Pin 23" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 22. " [22] ,Input/Output Direction Pin 22" "Input,Output"
|
|
bitfld.long 0x00 21. " [21] ,Input/Output Direction Pin 21" "Input,Output"
|
|
bitfld.long 0x00 20. " [20] ,Input/Output Direction Pin 20" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 19. " [19] ,Input/Output Direction Pin 19" "Input,Output"
|
|
bitfld.long 0x00 18. " [18] ,Input/Output Direction Pin 18" "Input,Output"
|
|
bitfld.long 0x00 17. " [17] ,Input/Output Direction Pin 17" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 16. " [16] ,Input/Output Direction Pin 16" "Input,Output"
|
|
bitfld.long 0x00 15. " [15] ,Input/Output Direction Pin 15" "Input,Output"
|
|
bitfld.long 0x00 14. " [14] ,Input/Output Direction Pin 14" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 13. " [13] ,Input/Output Direction Pin 13" "Input,Output"
|
|
bitfld.long 0x00 12. " [12] ,Input/Output Direction Pin 12" "Input,Output"
|
|
bitfld.long 0x00 11. " [11] ,Input/Output Direction Pin 11" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 10. " [10] ,Input/Output Direction Pin 10" "Input,Output"
|
|
bitfld.long 0x00 9. " [9] ,Input/Output Direction Pin 9" "Input,Output"
|
|
bitfld.long 0x00 8. " [8] ,Input/Output Direction Pin 8" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 7. " [7] ,Input/Output Direction Pin 7" "Input,Output"
|
|
bitfld.long 0x00 6. " [6] ,Input/Output Direction Pin 6" "Input,Output"
|
|
bitfld.long 0x00 5. " [5] ,Input/Output Direction Pin 5" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 4. " [4] ,Input/Output Direction Pin 4" "Input,Output"
|
|
bitfld.long 0x00 3. " [3] ,Input/Output Direction Pin 3" "Input,Output"
|
|
bitfld.long 0x00 2. " [2] ,Input/Output Direction Pin 2" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 1. " [1] ,Input/Output Direction Pin 1" "Input,Output"
|
|
bitfld.long 0x00 0. " [0] ,Input/Output Direction Pin 0" "Input,Output"
|
|
rgroup.long 0x50++0x3
|
|
line.long 0x00 "DIN,Input Data Register"
|
|
bitfld.long 0x00 31. " HETDIN[31] ,NHET Data Input Register Pin 31" "Low,High"
|
|
bitfld.long 0x00 30. " [30] ,NHET Data Input Register Pin 30" "Low,High"
|
|
bitfld.long 0x00 29. " [29] ,NHET Data Input Register Pin 29" "Low,High"
|
|
bitfld.long 0x00 28. " [28] ,NHET Data Input Register Pin 28" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 27. " [27] ,NHET Data Input Register Pin 27" "Low,High"
|
|
bitfld.long 0x00 26. " [26] ,NHET Data Input Register Pin 26" "Low,High"
|
|
bitfld.long 0x00 25. " [25] ,NHET Data Input Register Pin 25" "Low,High"
|
|
bitfld.long 0x00 24. " [24] ,NHET Data Input Register Pin 24" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 23. " [23] ,NHET Data Input Register Pin 23" "Low,High"
|
|
bitfld.long 0x00 22. " [22] ,NHET Data Input Register Pin 22" "Low,High"
|
|
bitfld.long 0x00 21. " [21] ,NHET Data Input Register Pin 21" "Low,High"
|
|
bitfld.long 0x00 20. " [20] ,NHET Data Input Register Pin 20" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 19. " [19] ,NHET Data Input Register Pin 19" "Low,High"
|
|
bitfld.long 0x00 18. " [18] ,NHET Data Input Register Pin 18" "Low,High"
|
|
bitfld.long 0x00 17. " [17] ,NHET Data Input Register Pin 17" "Low,High"
|
|
bitfld.long 0x00 16. " [16] ,NHET Data Input Register Pin 16" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 15. " [15] ,NHET Data Input Register Pin 15" "Low,High"
|
|
bitfld.long 0x00 14. " [14] ,NHET Data Input Register Pin 14" "Low,High"
|
|
bitfld.long 0x00 13. " [13] ,NHET Data Input Register Pin 13" "Low,High"
|
|
bitfld.long 0x00 12. " [12] ,NHET Data Input Register Pin 12" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 11. " [11] ,NHET Data Input Register Pin 11" "Low,High"
|
|
bitfld.long 0x00 10. " [10] ,NHET Data Input Register Pin 10" "Low,High"
|
|
bitfld.long 0x00 9. " [9] ,NHET Data Input Register Pin 9" "Low,High"
|
|
bitfld.long 0x00 8. " [8] ,NHET Data Input Register Pin 8" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 7. " [7] ,NHET Data Input Register Pin 7" "Low,High"
|
|
bitfld.long 0x00 6. " [6] ,NHET Data Input Register Pin 6" "Low,High"
|
|
bitfld.long 0x00 5. " [5] ,NHET Data Input Register Pin 5" "Low,High"
|
|
bitfld.long 0x00 4. " [4] ,NHET Data Input Register Pin 4" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 3. " [3] ,NHET Data Input Register Pin 3" "Low,High"
|
|
bitfld.long 0x00 2. " [2] ,NHET Data Input Register Pin 2" "Low,High"
|
|
bitfld.long 0x00 1. " [1] ,NHET Data Input Register Pin 1" "Low,High"
|
|
bitfld.long 0x00 0. " [0] ,NHET Data Input Register Pin 0" "Low,High"
|
|
group.long 0x54++0x3
|
|
line.long 0x00 "DOUT_SET/CLR,Output Data Set/Clear Register"
|
|
setclrfld.long 0x00 31. 0x04 31. 0x08 31. " HETDOUT[31] ,NHET Data Output Register Bit[31]" "Low,High"
|
|
setclrfld.long 0x00 30. 0x04 30. 0x08 30. " [30] ,NHET Data Output Register Bit[30]" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 29. 0x04 29. 0x08 29. " [29] ,NHET Data Output Register Bit[29]" "Low,High"
|
|
setclrfld.long 0x00 28. 0x04 28. 0x08 28. " [28] ,NHET Data Output Register Bit[28]" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 27. 0x04 27. 0x08 27. " [27] ,NHET Data Output Register Bit[27]" "Low,High"
|
|
setclrfld.long 0x00 26. 0x04 26. 0x08 26. " [26] ,NHET Data Output Register Bit[26]" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 25. 0x04 25. 0x08 25. " [25] ,NHET Data Output Register Bit[25]" "Low,High"
|
|
setclrfld.long 0x00 24. 0x04 24. 0x08 24. " [24] ,NHET Data Output Register Bit[24]" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 23. 0x04 23. 0x08 23. " [23] ,NHET Data Output Register Bit[23]" "Low,High"
|
|
setclrfld.long 0x00 22. 0x04 22. 0x08 22. " [22] ,NHET Data Output Register Bit[22]" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 21. 0x04 21. 0x08 21. " [21] ,NHET Data Output Register Bit[21]" "Low,High"
|
|
setclrfld.long 0x00 20. 0x04 20. 0x08 20. " [20] ,NHET Data Output Register Bit[20]" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 19. 0x04 19. 0x08 19. " [19] ,NHET Data Output Register Bit[19]" "Low,High"
|
|
setclrfld.long 0x00 18. 0x04 18. 0x08 18. " [18] ,NHET Data Output Register Bit[18]" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 17. 0x04 17. 0x08 17. " [17] ,NHET Data Output Register Bit[17]" "Low,High"
|
|
setclrfld.long 0x00 16. 0x04 16. 0x08 16. " [16] ,NHET Data Output Register Bit[16]" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 15. 0x04 15. 0x08 15. " [15] ,NHET Data Output Register Bit[15]" "Low,High"
|
|
setclrfld.long 0x00 14. 0x04 14. 0x08 14. " [14] ,NHET Data Output Register Bit[14]" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 13. 0x04 13. 0x08 13. " [13] ,NHET Data Output Register Bit[13]" "Low,High"
|
|
setclrfld.long 0x00 12. 0x04 12. 0x08 12. " [12] ,NHET Data Output Register Bit[12]" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 11. 0x04 11. 0x08 11. " [11] ,NHET Data Output Register Bit[11]" "Low,High"
|
|
setclrfld.long 0x00 10. 0x04 10. 0x08 10. " [10] ,NHET Data Output Register Bit[10]" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 9. 0x04 9. 0x08 9. " [9] ,NHET Data Output Register Bit[9]" "Low,High"
|
|
setclrfld.long 0x00 8. 0x04 8. 0x08 8. " [8] ,NHET Data Output Register Bit[8]" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 7. 0x04 7. 0x08 7. " [7] ,NHET Data Output Register Bit[7]" "Low,High"
|
|
setclrfld.long 0x00 6. 0x04 6. 0x08 6. " [6] ,NHET Data Output Register Bit[6]" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 5. 0x04 5. 0x08 5. " [5] ,NHET Data Output Register Bit[5]" "Low,High"
|
|
setclrfld.long 0x00 4. 0x04 4. 0x08 4. " [4] ,NHET Data Output Register Bit[4]" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 3. 0x04 3. 0x08 3. " [3] ,NHET Data Output Register Bit[3]" "Low,High"
|
|
setclrfld.long 0x00 2. 0x04 2. 0x08 2. " [2] ,NHET Data Output Register Bit[2]" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 1. 0x04 1. 0x08 1. " [1] ,NHET Data Output Register Bit[1]" "Low,High"
|
|
setclrfld.long 0x00 0. 0x04 0. 0x08 0. " [0] ,NHET Data Output Register Bit[0]" "Low,High"
|
|
group.long 0x60++0x0B
|
|
line.long 0x00 "PDR,Open Drain Register"
|
|
bitfld.long 0x00 31. " HETPDR[31] ,NHET Open Drain Bit[31]" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " [30] ,NHET Open Drain Bit[30]" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " [29] ,NHET Open Drain Bit[29]" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 28. " [28] ,NHET Open Drain Bit[28]" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " [27] ,NHET Open Drain Bit[27]" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " [26] ,NHET Open Drain Bit[26]" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 25. " [25] ,NHET Open Drain Bit[25]" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " [24] ,NHET Open Drain Bit[24]" "Disabled,Enabled"
|
|
bitfld.long 0x00 23. " [23] ,NHET Open Drain Bit[23]" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 22. " [22] ,NHET Open Drain Bit[22]" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " [21] ,NHET Open Drain Bit[21]" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " [20] ,NHET Open Drain Bit[20]" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 19. " [19] ,NHET Open Drain Bit[19]" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " [18] ,NHET Open Drain Bit[18]" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " [17] ,NHET Open Drain Bit[17]" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 16. " [16] ,NHET Open Drain Bit[16]" "Disabled,Enabled"
|
|
bitfld.long 0x00 15. " [15] ,NHET Open Drain Bit[15]" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " [14] ,NHET Open Drain Bit[14]" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 13. " [13] ,NHET Open Drain Bit[13]" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " [12] ,NHET Open Drain Bit[12]" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " [11] ,NHET Open Drain Bit[11]" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 10. " [10] ,NHET Open Drain Bit[10]" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " [9] ,NHET Open Drain Bit[9]" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " [8] ,NHET Open Drain Bit[8]" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 7. " [7] ,NHET Open Drain Bit[7]" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " [6] ,NHET Open Drain Bit[6]" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " [5] ,NHET Open Drain Bit[5]" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 4. " [4] ,NHET Open Drain Bit[4]" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " [3] ,NHET Open Drain Bit[3]" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " [2] ,NHET Open Drain Bit[2]" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 1. " [1] ,NHET Open Drain Bit[1]" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,NHET Open Drain Bit[0]" "Disabled,Enabled"
|
|
line.long 0x04 "PULDIS,Pull Disable Register"
|
|
bitfld.long 0x04 31. " HETPULDIS[31] ,NHET Pull Disable Bit[31]" "No,Yes"
|
|
bitfld.long 0x04 30. " [30] ,NHET Pull Disable Bit[30]" "No,Yes"
|
|
bitfld.long 0x04 29. " [29] ,NHET Pull Disable Bit[29]" "No,Yes"
|
|
newline
|
|
bitfld.long 0x04 28. " [28] ,NHET Pull Disable Bit[28]" "No,Yes"
|
|
bitfld.long 0x04 27. " [27] ,NHET Pull Disable Bit[27]" "No,Yes"
|
|
bitfld.long 0x04 26. " [26] ,NHET Pull Disable Bit[26]" "No,Yes"
|
|
newline
|
|
bitfld.long 0x04 25. " [25] ,NHET Pull Disable Bit[25]" "No,Yes"
|
|
bitfld.long 0x04 24. " [24] ,NHET Pull Disable Bit[24]" "No,Yes"
|
|
bitfld.long 0x04 23. " [23] ,NHET Pull Disable Bit[23]" "No,Yes"
|
|
newline
|
|
bitfld.long 0x04 22. " [22] ,NHET Pull Disable Bit[22]" "No,Yes"
|
|
bitfld.long 0x04 21. " [21] ,NHET Pull Disable Bit[21]" "No,Yes"
|
|
bitfld.long 0x04 20. " [20] ,NHET Pull Disable Bit[20]" "No,Yes"
|
|
newline
|
|
bitfld.long 0x04 19. " [19] ,NHET Pull Disable Bit[19]" "No,Yes"
|
|
bitfld.long 0x04 18. " [18] ,NHET Pull Disable Bit[18]" "No,Yes"
|
|
bitfld.long 0x04 17. " [17] ,NHET Pull Disable Bit[17]" "No,Yes"
|
|
newline
|
|
bitfld.long 0x04 16. " [16] ,NHET Pull Disable Bit[16]" "No,Yes"
|
|
bitfld.long 0x04 15. " [15] ,NHET Pull Disable Bit[15]" "No,Yes"
|
|
bitfld.long 0x04 14. " [14] ,NHET Pull Disable Bit[14]" "No,Yes"
|
|
newline
|
|
bitfld.long 0x04 13. " [13] ,NHET Pull Disable Bit[13]" "No,Yes"
|
|
bitfld.long 0x04 12. " [12] ,NHET Pull Disable Bit[12]" "No,Yes"
|
|
bitfld.long 0x04 11. " [11] ,NHET Pull Disable Bit[11]" "No,Yes"
|
|
newline
|
|
bitfld.long 0x04 10. " [10] ,NHET Pull Disable Bit[10]" "No,Yes"
|
|
bitfld.long 0x04 9. " [9] ,NHET Pull Disable Bit[9]" "No,Yes"
|
|
bitfld.long 0x04 8. " [8] ,NHET Pull Disable Bit[8]" "No,Yes"
|
|
newline
|
|
bitfld.long 0x04 7. " [7] ,NHET Pull Disable Bit[7]" "No,Yes"
|
|
bitfld.long 0x04 6. " [6] ,NHET Pull Disable Bit[6]" "No,Yes"
|
|
bitfld.long 0x04 5. " [5] ,NHET Pull Disable Bit[5]" "No,Yes"
|
|
newline
|
|
bitfld.long 0x04 4. " [4] ,NHET Pull Disable Bit[4]" "No,Yes"
|
|
bitfld.long 0x04 3. " [3] ,NHET Pull Disable Bit[3]" "No,Yes"
|
|
bitfld.long 0x04 2. " [2] ,NHET Pull Disable Bit[2]" "No,Yes"
|
|
newline
|
|
bitfld.long 0x04 1. " [1] ,NHET Pull Disable Bit[1]" "No,Yes"
|
|
bitfld.long 0x04 0. " [0] ,NHET Pull Disable Bit[0]" "No,Yes"
|
|
line.long 0x08 "PSL,Pull Select Register"
|
|
bitfld.long 0x08 31. " HETPSL[31] ,NHET Pull Select Bit[31]" "Pull down,Pull up"
|
|
bitfld.long 0x08 30. " [30] ,NHET Pull Select Bit[30]" "Pull down,Pull up"
|
|
bitfld.long 0x08 29. " [29] ,NHET Pull Select Bit[29]" "Pull down,Pull up"
|
|
newline
|
|
bitfld.long 0x08 28. " [28] ,NHET Pull Select Bit[28]" "Pull down,Pull up"
|
|
bitfld.long 0x08 27. " [27] ,NHET Pull Select Bit[27]" "Pull down,Pull up"
|
|
bitfld.long 0x08 26. " [26] ,NHET Pull Select Bit[26]" "Pull down,Pull up"
|
|
newline
|
|
bitfld.long 0x08 25. " [25] ,NHET Pull Select Bit[25]" "Pull down,Pull up"
|
|
bitfld.long 0x08 24. " [24] ,NHET Pull Select Bit[24]" "Pull down,Pull up"
|
|
bitfld.long 0x08 23. " [23] ,NHET Pull Select Bit[23]" "Pull down,Pull up"
|
|
newline
|
|
bitfld.long 0x08 22. " [22] ,NHET Pull Select Bit[22]" "Pull down,Pull up"
|
|
bitfld.long 0x08 21. " [21] ,NHET Pull Select Bit[21]" "Pull down,Pull up"
|
|
bitfld.long 0x08 20. " [20] ,NHET Pull Select Bit[20]" "Pull down,Pull up"
|
|
newline
|
|
bitfld.long 0x08 19. " [19] ,NHET Pull Select Bit[19]" "Pull down,Pull up"
|
|
bitfld.long 0x08 18. " [18] ,NHET Pull Select Bit[18]" "Pull down,Pull up"
|
|
bitfld.long 0x08 17. " [17] ,NHET Pull Select Bit[17]" "Pull down,Pull up"
|
|
newline
|
|
bitfld.long 0x08 16. " [16] ,NHET Pull Select Bit[16]" "Pull down,Pull up"
|
|
bitfld.long 0x08 15. " [15] ,NHET Pull Select Bit[15]" "Pull down,Pull up"
|
|
bitfld.long 0x08 14. " [14] ,NHET Pull Select Bit[14]" "Pull down,Pull up"
|
|
newline
|
|
bitfld.long 0x08 13. " [13] ,NHET Pull Select Bit[13]" "Pull down,Pull up"
|
|
bitfld.long 0x08 12. " [12] ,NHET Pull Select Bit[12]" "Pull down,Pull up"
|
|
bitfld.long 0x08 11. " [11] ,NHET Pull Select Bit[11]" "Pull down,Pull up"
|
|
newline
|
|
bitfld.long 0x08 10. " [10] ,NHET Pull Select Bit[10]" "Pull down,Pull up"
|
|
bitfld.long 0x08 9. " [9] ,NHET Pull Select Bit[9]" "Pull down,Pull up"
|
|
bitfld.long 0x08 8. " [8] ,NHET Pull Select Bit[8]" "Pull down,Pull up"
|
|
newline
|
|
bitfld.long 0x08 7. " [7] ,NHET Pull Select Bit[7]" "Pull down,Pull up"
|
|
bitfld.long 0x08 6. " [6] ,NHET Pull Select Bit[6]" "Pull down,Pull up"
|
|
bitfld.long 0x08 5. " [5] ,NHET Pull Select Bit[5]" "Pull down,Pull up"
|
|
newline
|
|
bitfld.long 0x08 4. " [4] ,NHET Pull Select Bit[4]" "Pull down,Pull up"
|
|
bitfld.long 0x08 3. " [3] ,NHET Pull Select Bit[3]" "Pull down,Pull up"
|
|
bitfld.long 0x08 2. " [2] ,NHET Pull Select Bit[2]" "Pull down,Pull up"
|
|
newline
|
|
bitfld.long 0x08 1. " [1] ,NHET Pull Select Bit[1]" "Pull down,Pull up"
|
|
bitfld.long 0x08 0. " [0] ,NHET Pull Select Bit[0]" "Pull down,Pull up"
|
|
group.long 0x74++0x3
|
|
line.long 0x0 "PCR,Parity Control Register"
|
|
bitfld.long 0x00 8. " TEST ,TEST" "Not mapped,Mapped"
|
|
bitfld.long 0x00 0.--3. " PARITY_ENA ,Enable / Disable Parity Checking" "Enabled,Enabled,Enabled,Enabled,Enabled,Disabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled"
|
|
rgroup.long 0x78++0x3
|
|
line.long 0x0 "PAR,Parity Address Register"
|
|
hexmask.long.word 0x00 2.--12. 0x4 " PAOFF ,Parity Error Address Offset"
|
|
group.long 0x7C++0x0B
|
|
line.long 0x0 "PPR,Parity Pin Register"
|
|
bitfld.long 0x00 31. " HETPPR[31] ,NHET Parity Pin Select Bit[31]" "Low,High"
|
|
bitfld.long 0x00 30. " [30] ,NHET Parity Pin Select Bit[30]" "Low,High"
|
|
bitfld.long 0x00 29. " [29] ,NHET Parity Pin Select Bit[29]" "Low,High"
|
|
bitfld.long 0x00 28. " [28] ,NHET Parity Pin Select Bit[28]" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 27. " [27] ,NHET Parity Pin Select Bit[27]" "Low,High"
|
|
bitfld.long 0x00 26. " [26] ,NHET Parity Pin Select Bit[26]" "Low,High"
|
|
bitfld.long 0x00 25. " [25] ,NHET Parity Pin Select Bit[25]" "Low,High"
|
|
bitfld.long 0x00 24. " [24] ,NHET Parity Pin Select Bit[24]" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 23. " [23] ,NHET Parity Pin Select Bit[23]" "Low,High"
|
|
bitfld.long 0x00 22. " [22] ,NHET Parity Pin Select Bit[22]" "Low,High"
|
|
bitfld.long 0x00 21. " [21] ,NHET Parity Pin Select Bit[21]" "Low,High"
|
|
bitfld.long 0x00 20. " [20] ,NHET Parity Pin Select Bit[20]" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 19. " [19] ,NHET Parity Pin Select Bit[19]" "Low,High"
|
|
bitfld.long 0x00 18. " [18] ,NHET Parity Pin Select Bit[18]" "Low,High"
|
|
bitfld.long 0x00 17. " [17] ,NHET Parity Pin Select Bit[17]" "Low,High"
|
|
bitfld.long 0x00 16. " [16] ,NHET Parity Pin Select Bit[16]" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 15. " [15] ,NHET Parity Pin Select Bit[15]" "Low,High"
|
|
bitfld.long 0x00 14. " [14] ,NHET Parity Pin Select Bit[14]" "Low,High"
|
|
bitfld.long 0x00 13. " [13] ,NHET Parity Pin Select Bit[13]" "Low,High"
|
|
bitfld.long 0x00 12. " [12] ,NHET Parity Pin Select Bit[12]" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 11. " [11] ,NHET Parity Pin Select Bit[11]" "Low,High"
|
|
bitfld.long 0x00 10. " [10] ,NHET Parity Pin Select Bit[10]" "Low,High"
|
|
bitfld.long 0x00 9. " [9] ,NHET Parity Pin Select Bit[9]" "Low,High"
|
|
bitfld.long 0x00 8. " [8] ,NHET Parity Pin Select Bit[8]" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 7. " [7] ,NHET Parity Pin Select Bit[7]" "Low,High"
|
|
bitfld.long 0x00 6. " [6] ,NHET Parity Pin Select Bit[6]" "Low,High"
|
|
bitfld.long 0x00 5. " [5] ,NHET Parity Pin Select Bit[5]" "Low,High"
|
|
bitfld.long 0x00 4. " [4] ,NHET Parity Pin Select Bit[4]" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 3. " [3] ,NHET Parity Pin Select Bit[3]" "Low,High"
|
|
bitfld.long 0x00 2. " [2] ,NHET Parity Pin Select Bit[2]" "Low,High"
|
|
bitfld.long 0x00 1. " [1] ,NHET Parity Pin Select Bit[1]" "Low,High"
|
|
bitfld.long 0x00 0. " [0] ,NHET Parity Pin Select Bit[0]" "Low,High"
|
|
line.long 0x04 "SFPRLD,Suppresion Filter Preload Register"
|
|
bitfld.long 0x04 16.--17. " CCDIV ,Counter Clock Divider" "VCLK2,VCLK2/2,VCLK2/3,VCLK2/4"
|
|
hexmask.long.word 0x04 0.--9. 1. " CPRLD ,Counter Preload Value"
|
|
line.long 0x08 "SFENA,Suppresion Filter Enable Register"
|
|
bitfld.long 0x08 31. " HETSFENA[31] ,Suppression Filter Enable Bit[31]" "Disabled,Enabled"
|
|
bitfld.long 0x08 30. " [30] ,Suppression Filter Enable Bit[30]" "Disabled,Enabled"
|
|
bitfld.long 0x08 29. " [29] ,Suppression Filter Enable Bit[29]" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x08 28. " [28] ,Suppression Filter Enable Bit[28]" "Disabled,Enabled"
|
|
bitfld.long 0x08 27. " [27] ,Suppression Filter Enable Bit[27]" "Disabled,Enabled"
|
|
bitfld.long 0x08 26. " [26] ,Suppression Filter Enable Bit[26]" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x08 25. " [25] ,Suppression Filter Enable Bit[25]" "Disabled,Enabled"
|
|
bitfld.long 0x08 24. " [24] ,Suppression Filter Enable Bit[24]" "Disabled,Enabled"
|
|
bitfld.long 0x08 23. " [23] ,Suppression Filter Enable Bit[23]" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x08 22. " [22] ,Suppression Filter Enable Bit[22]" "Disabled,Enabled"
|
|
bitfld.long 0x08 21. " [21] ,Suppression Filter Enable Bit[21]" "Disabled,Enabled"
|
|
bitfld.long 0x08 20. " [20] ,Suppression Filter Enable Bit[20]" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x08 19. " [19] ,Suppression Filter Enable Bit[19]" "Disabled,Enabled"
|
|
bitfld.long 0x08 18. " [18] ,Suppression Filter Enable Bit[18]" "Disabled,Enabled"
|
|
bitfld.long 0x08 17. " [17] ,Suppression Filter Enable Bit[17]" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x08 16. " [16] ,Suppression Filter Enable Bit[16]" "Disabled,Enabled"
|
|
bitfld.long 0x08 15. " [15] ,Suppression Filter Enable Bit[15]" "Disabled,Enabled"
|
|
bitfld.long 0x08 14. " [14] ,Suppression Filter Enable Bit[14]" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x08 13. " [13] ,Suppression Filter Enable Bit[13]" "Disabled,Enabled"
|
|
bitfld.long 0x08 12. " [12] ,Suppression Filter Enable Bit[12]" "Disabled,Enabled"
|
|
bitfld.long 0x08 11. " [11] ,Suppression Filter Enable Bit[11]" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x08 10. " [10] ,Suppression Filter Enable Bit[10]" "Disabled,Enabled"
|
|
bitfld.long 0x08 9. " [9] ,Suppression Filter Enable Bit[9]" "Disabled,Enabled"
|
|
bitfld.long 0x08 8. " [8] ,Suppression Filter Enable Bit[8]" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x08 7. " [7] ,Suppression Filter Enable Bit[7]" "Disabled,Enabled"
|
|
bitfld.long 0x08 6. " [6] ,Suppression Filter Enable Bit[6]" "Disabled,Enabled"
|
|
bitfld.long 0x08 5. " [5] ,Suppression Filter Enable Bit[5]" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x08 4. " [4] ,Suppression Filter Enable Bit[4]" "Disabled,Enabled"
|
|
bitfld.long 0x08 3. " [3] ,Suppression Filter Enable Bit[3]" "Disabled,Enabled"
|
|
bitfld.long 0x08 2. " [2] ,Suppression Filter Enable Bit[2]" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x08 1. " [1] ,Suppression Filter Enable Bit[1]" "Disabled,Enabled"
|
|
bitfld.long 0x08 0. " [0] ,Suppression Filter Enable Bit[0]" "Disabled,Enabled"
|
|
sif (cpu()!="RM48L952-PGE"&&cpu()!="RM48L952-ZWT"&&cpu()!="RM48L950-PGE"&&cpu()!="RM48L950-ZWT"&&cpu()!="RM48L940-ZWT"&&cpu()!="RM48L940-PGE"&&cpu()!="RM48L930-ZWT"&&cpu()!="RM48L930-PGE"&&cpu()!="RM48L750-ZWT"&&cpu()!="RM48L750-PGE"&&cpu()!="RM48L740-ZWT"&&cpu()!="RM48L740-PGE"&&cpu()!="RM48L730-ZWT"&&cpu()!="RM48L730-PGE"&&cpu()!="RM48L550-PGE"&&cpu()!="RM48L540-ZWT"&&cpu()!="RM48L540-PGE"&&cpu()!="RM48L530-ZWT"&&cpu()!="RM48L530-PGE"&&cpu()!="RM46L852-PGE"&&cpu()!="RM46L852-ZWT"&&cpu()!="RM46L850-PGE"&&cpu()!="RM46L850-ZWT"&&cpu()!="RM46L840-ZWT"&&cpu()!="RM46L840-PGE"&&cpu()!="RM46L830-ZWT"&&cpu()!="RM46L830-PGE"&&cpu()!="RM46L450-ZWT"&&cpu()!="RM46L450-PGE"&&cpu()!="RM46L440-ZWT"&&cpu()!="RM46L440-PGE"&&cpu()!="RM46L430-ZWT"&&cpu()!="RM46L430-PGE"&&cpu()!="TMS570LC4357"&&cpu()!="RM48L550-ZWT"&&cpu()!="RM42L432"&&!cpuis("TMS570LS0232")&&!cpuis("TMS570LS0714*")&&!cpuis("TMS570LS0914*"))
|
|
if ((per.l(ad:0xFFF7B900+0x90)&0xF00)==0xA00)
|
|
group.long 0x8C++0x3
|
|
line.long 0x0 "LBPSEL,Loop Back Pair Select Register"
|
|
bitfld.long 0x00 31. " LBPTYPE[15] ,Loop Back Pair Type Select Bit[15]" "Digital,Analog"
|
|
bitfld.long 0x00 30. " [14] ,Loop Back Pair Type Select Bit[14]" "Digital,Analog"
|
|
newline
|
|
bitfld.long 0x00 29. " [13] ,Loop Back Pair Type Select Bit[13]" "Digital,Analog"
|
|
bitfld.long 0x00 28. " [12] ,Loop Back Pair Type Select Bit[12]" "Digital,Analog"
|
|
newline
|
|
bitfld.long 0x00 27. " [11] ,Loop Back Pair Type Select Bit[11]" "Digital,Analog"
|
|
bitfld.long 0x00 26. " [10] ,Loop Back Pair Type Select Bit[10]" "Digital,Analog"
|
|
newline
|
|
bitfld.long 0x00 25. " [9] ,Loop Back Pair Type Select Bit[9]" "Digital,Analog"
|
|
bitfld.long 0x00 24. " [8] ,Loop Back Pair Type Select Bit[8]" "Digital,Analog"
|
|
newline
|
|
bitfld.long 0x00 23. " [7] ,Loop Back Pair Type Select Bit[7]" "Digital,Analog"
|
|
bitfld.long 0x00 22. " [6] ,Loop Back Pair Type Select Bit[6]" "Digital,Analog"
|
|
newline
|
|
bitfld.long 0x00 21. " [5] ,Loop Back Pair Type Select Bit[5]" "Digital,Analog"
|
|
bitfld.long 0x00 20. " [4] ,Loop Back Pair Type Select Bit[4]" "Digital,Analog"
|
|
newline
|
|
bitfld.long 0x00 19. " [3] ,Loop Back Pair Type Select Bit[3]" "Digital,Analog"
|
|
bitfld.long 0x00 18. " [2] ,Loop Back Pair Type Select Bit[2]" "Digital,Analog"
|
|
newline
|
|
bitfld.long 0x00 17. " [1] ,Loop Back Pair Type Select Bit[1]" "Digital,Analog"
|
|
bitfld.long 0x00 16. " [0] ,Loop Back Pair Type Select Bit[0]" "Digital,Analog"
|
|
newline
|
|
bitfld.long 0x00 15. " LBPSEL[15] ,Loop Back Pair Select Bit[15]" "Not selected,Selected"
|
|
bitfld.long 0x00 14. " [14] ,Loop Back Pair Select Bit[14]" "Not selected,Selected"
|
|
newline
|
|
bitfld.long 0x00 13. " [13] ,Loop Back Pair Select Bit[13]" "Not selected,Selected"
|
|
bitfld.long 0x00 12. " [12] ,Loop Back Pair Select Bit[12]" "Not selected,Selected"
|
|
newline
|
|
bitfld.long 0x00 11. " [11] ,Loop Back Pair Select Bit[11]" "Not selected,Selected"
|
|
bitfld.long 0x00 10. " [10] ,Loop Back Pair Select Bit[10]" "Not selected,Selected"
|
|
newline
|
|
bitfld.long 0x00 9. " [9] ,Loop Back Pair Select Bit[9]" "Not selected,Selected"
|
|
bitfld.long 0x00 8. " [8] ,Loop Back Pair Select Bit[8]" "Not selected,Selected"
|
|
newline
|
|
bitfld.long 0x00 7. " [7] ,Loop Back Pair Select Bit[7]" "Not selected,Selected"
|
|
bitfld.long 0x00 6. " [6] ,Loop Back Pair Select Bit[6]" "Not selected,Selected"
|
|
newline
|
|
bitfld.long 0x00 5. " [5] ,Loop Back Pair Select Bit[5]" "Not selected,Selected"
|
|
bitfld.long 0x00 4. " [4] ,Loop Back Pair Select Bit[4]" "Not selected,Selected"
|
|
newline
|
|
bitfld.long 0x00 3. " [3] ,Loop Back Pair Select Bit[3]" "Not selected,Selected"
|
|
bitfld.long 0x00 2. " [2] ,Loop Back Pair Select Bit[2]" "Not selected,Selected"
|
|
newline
|
|
bitfld.long 0x00 1. " [1] ,Loop Back Pair Select Bit[1]" "Not selected,Selected"
|
|
bitfld.long 0x00 0. " [0] ,Loop Back Pair Select Bit[0]" "Not selected,Selected"
|
|
else
|
|
hgroup.long 0x8C++0x3
|
|
hide.long 0x0 "LBPSEL,Loop Back Pair Select Register"
|
|
endif
|
|
elif cpuis("TMS570LS0232")||cpuis("TMS570LS0714*")||cpuis("TMS570LS0914*")
|
|
if ((per.l.be(ad:0xFFF7B900+0x90)&0xF0000)==0xA0000)
|
|
group.long 0x8C++0x3
|
|
line.long 0x0 "LBPSEL,Loop Back Pair Select Register"
|
|
bitfld.long 0x00 31. " LBPTYPE[31/30] ,Loop Back Pair Type Select Bits 31/30" "Digital,Analog"
|
|
bitfld.long 0x00 30. " [29/28] ,Loop Back Pair Type Select Bits 29/28" "Digital,Analog"
|
|
newline
|
|
bitfld.long 0x00 29. " [27/26] ,Loop Back Pair Type Select Bits 27/26" "Digital,Analog"
|
|
bitfld.long 0x00 28. " [25/24] ,Loop Back Pair Type Select Bits 25/24" "Digital,Analog"
|
|
newline
|
|
bitfld.long 0x00 27. " [23/22] ,Loop Back Pair Type Select Bits 23/22" "Digital,Analog"
|
|
bitfld.long 0x00 26. " [21/20] ,Loop Back Pair Type Select Bits 21/20" "Digital,Analog"
|
|
newline
|
|
bitfld.long 0x00 25. " [19/18] ,Loop Back Pair Type Select Bits 19/18" "Digital,Analog"
|
|
bitfld.long 0x00 24. " [17/16] ,Loop Back Pair Type Select Bits 17/16" "Digital,Analog"
|
|
newline
|
|
bitfld.long 0x00 23. " [15/14] ,Loop Back Pair Type Select Bits 15/14" "Digital,Analog"
|
|
bitfld.long 0x00 22. " [13/12] ,Loop Back Pair Type Select Bits 13/12" "Digital,Analog"
|
|
newline
|
|
bitfld.long 0x00 21. " [11/10] ,Loop Back Pair Type Select Bits 11/10" "Digital,Analog"
|
|
bitfld.long 0x00 20. " [9/8] ,Loop Back Pair Type Select Bits 9/8" "Digital,Analog"
|
|
newline
|
|
bitfld.long 0x00 19. " [7/6] ,Loop Back Pair Type Select Bits 7/6" "Digital,Analog"
|
|
bitfld.long 0x00 18. " [5/4] ,Loop Back Pair Type Select Bits 5/4" "Digital,Analog"
|
|
newline
|
|
bitfld.long 0x00 17. " [3/2] ,Loop Back Pair Type Select Bits 3/2" "Digital,Analog"
|
|
bitfld.long 0x00 16. " [1/0] ,Loop Back Pair Type Select Bits 1/0" "Digital,Analog"
|
|
newline
|
|
bitfld.long 0x00 15. " LBPSEL31/30] ,Loop Back Pair Select Bits 31/30" "Not selected,Selected"
|
|
bitfld.long 0x00 14. " [29/28] ,Loop Back Pair Select Bits 29/28" "Not selected,Selected"
|
|
newline
|
|
bitfld.long 0x00 13. " [27/26] ,Loop Back Pair Select Bits 27/26" "Not selected,Selected"
|
|
bitfld.long 0x00 12. " [25/24] ,Loop Back Pair Select Bits 25/24" "Not selected,Selected"
|
|
newline
|
|
bitfld.long 0x00 11. " [23/22] ,Loop Back Pair Select Bits 23/22" "Not selected,Selected"
|
|
bitfld.long 0x00 10. " [21/20] ,Loop Back Pair Select Bits 21/20" "Not selected,Selected"
|
|
newline
|
|
bitfld.long 0x00 9. " [19/18] ,Loop Back Pair Select Bits 19/18" "Not selected,Selected"
|
|
bitfld.long 0x00 8. " [17/16] ,Loop Back Pair Select Bits 17/16" "Not selected,Selected"
|
|
newline
|
|
bitfld.long 0x00 7. " [15/14] ,Loop Back Pair Select Bits 15/14" "Not selected,Selected"
|
|
bitfld.long 0x00 6. " [13/12] ,Loop Back Pair Select Bits 13/12" "Not selected,Selected"
|
|
newline
|
|
bitfld.long 0x00 5. " [11/10] ,Loop Back Pair Select Bits 11/10" "Not selected,Selected"
|
|
bitfld.long 0x00 4. " [9/8] ,Loop Back Pair Select Bits 9/8" "Not selected,Selected"
|
|
newline
|
|
bitfld.long 0x00 3. " [7/6] ,Loop Back Pair Select Bits 7/6" "Not selected,Selected"
|
|
bitfld.long 0x00 2. " [5/4] ,Loop Back Pair Select Bits 5/4" "Not selected,Selected"
|
|
newline
|
|
bitfld.long 0x00 1. " [3/2] ,Loop Back Pair Select Bits 3/2" "Not selected,Selected"
|
|
bitfld.long 0x00 0. " [1/0] ,Loop Back Pair Select Bits 1/0" "Not selected,Selected"
|
|
else
|
|
hgroup.long 0x8C++0x3
|
|
hide.long 0x0 "LBPSEL,Loop Back Pair Select Register"
|
|
endif
|
|
else
|
|
if ((per.l(ad:0xFFF7B900+0x90)&0xF0000)==0xA0000)
|
|
group.long 0x8C++0x3
|
|
line.long 0x0 "LBPSEL,Loop Back Pair Select Register"
|
|
bitfld.long 0x00 31. " LBPTYPE[15] ,Loop Back Pair Type Select Bit[15]" "Digital,Analog"
|
|
bitfld.long 0x00 30. " [14] ,Loop Back Pair Type Select Bit[14]" "Digital,Analog"
|
|
newline
|
|
bitfld.long 0x00 29. " [13] ,Loop Back Pair Type Select Bit[13]" "Digital,Analog"
|
|
bitfld.long 0x00 28. " [12] ,Loop Back Pair Type Select Bit[12]" "Digital,Analog"
|
|
newline
|
|
bitfld.long 0x00 27. " [11] ,Loop Back Pair Type Select Bit[11]" "Digital,Analog"
|
|
bitfld.long 0x00 26. " [10] ,Loop Back Pair Type Select Bit[10]" "Digital,Analog"
|
|
newline
|
|
bitfld.long 0x00 25. " [9] ,Loop Back Pair Type Select Bit[9]" "Digital,Analog"
|
|
bitfld.long 0x00 24. " [8] ,Loop Back Pair Type Select Bit[8]" "Digital,Analog"
|
|
newline
|
|
bitfld.long 0x00 23. " [7] ,Loop Back Pair Type Select Bit[7]" "Digital,Analog"
|
|
bitfld.long 0x00 22. " [6] ,Loop Back Pair Type Select Bit[6]" "Digital,Analog"
|
|
newline
|
|
bitfld.long 0x00 21. " [5] ,Loop Back Pair Type Select Bit[5]" "Digital,Analog"
|
|
bitfld.long 0x00 20. " [4] ,Loop Back Pair Type Select Bit[4]" "Digital,Analog"
|
|
newline
|
|
bitfld.long 0x00 19. " [3] ,Loop Back Pair Type Select Bit[3]" "Digital,Analog"
|
|
bitfld.long 0x00 18. " [2] ,Loop Back Pair Type Select Bit[2]" "Digital,Analog"
|
|
newline
|
|
bitfld.long 0x00 17. " [1] ,Loop Back Pair Type Select Bit[1]" "Digital,Analog"
|
|
bitfld.long 0x00 16. " [0] ,Loop Back Pair Type Select Bit[0]" "Digital,Analog"
|
|
newline
|
|
bitfld.long 0x00 15. " LBPSEL[15] ,Loop Back Pair Select Bit[15]" "Not selected,Selected"
|
|
bitfld.long 0x00 14. " [14] ,Loop Back Pair Select Bit[14]" "Not selected,Selected"
|
|
newline
|
|
bitfld.long 0x00 13. " [13] ,Loop Back Pair Select Bit[13]" "Not selected,Selected"
|
|
bitfld.long 0x00 12. " [12] ,Loop Back Pair Select Bit[12]" "Not selected,Selected"
|
|
newline
|
|
bitfld.long 0x00 11. " [11] ,Loop Back Pair Select Bit[11]" "Not selected,Selected"
|
|
bitfld.long 0x00 10. " [10] ,Loop Back Pair Select Bit[10]" "Not selected,Selected"
|
|
newline
|
|
bitfld.long 0x00 9. " [9] ,Loop Back Pair Select Bit[9]" "Not selected,Selected"
|
|
bitfld.long 0x00 8. " [8] ,Loop Back Pair Select Bit[8]" "Not selected,Selected"
|
|
newline
|
|
bitfld.long 0x00 7. " [7] ,Loop Back Pair Select Bit[7]" "Not selected,Selected"
|
|
bitfld.long 0x00 6. " [6] ,Loop Back Pair Select Bit[6]" "Not selected,Selected"
|
|
newline
|
|
bitfld.long 0x00 5. " [5] ,Loop Back Pair Select Bit[5]" "Not selected,Selected"
|
|
bitfld.long 0x00 4. " [4] ,Loop Back Pair Select Bit[4]" "Not selected,Selected"
|
|
newline
|
|
bitfld.long 0x00 3. " [3] ,Loop Back Pair Select Bit[3]" "Not selected,Selected"
|
|
bitfld.long 0x00 2. " [2] ,Loop Back Pair Select Bit[2]" "Not selected,Selected"
|
|
newline
|
|
bitfld.long 0x00 1. " [1] ,Loop Back Pair Select Bit[1]" "Not selected,Selected"
|
|
bitfld.long 0x00 0. " [0] ,Loop Back Pair Select Bit[0]" "Not selected,Selected"
|
|
else
|
|
hgroup.long 0x8C++0x3
|
|
hide.long 0x0 "LBPSEL,Loop Back Pair Select Register"
|
|
endif
|
|
endif
|
|
group.long 0x90++0x07
|
|
line.long 0x00 "LBPDIR,Loop Back Pair Direction Register"
|
|
bitfld.long 0x00 16.--19. " IODFTENA ,Module IODFT Enable Key" "Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Enabled,Disabled,Disabled,Disabled,Disabled,Disabled"
|
|
bitfld.long 0x00 15. " LBPDIR[15] ,Loop Back Pair Direction Bit[15]" "Input,Output"
|
|
bitfld.long 0x00 14. " [14] ,Loop Back Pair Direction Bit[14]" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 13. " [13] ,Loop Back Pair Direction Bit[13]" "Input,Output"
|
|
bitfld.long 0x00 12. " [12] ,Loop Back Pair Direction Bit[12]" "Input,Output"
|
|
bitfld.long 0x00 11. " [11] ,Loop Back Pair Direction Bit[11]" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 10. " [10] ,Loop Back Pair Direction Bit[10]" "Input,Output"
|
|
bitfld.long 0x00 9. " [9] ,Loop Back Pair Direction Bit[9]" "Input,Output"
|
|
bitfld.long 0x00 8. " [8] ,Loop Back Pair Direction Bit[8]" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 7. " [7] ,Loop Back Pair Direction Bit[7]" "Input,Output"
|
|
bitfld.long 0x00 6. " [6] ,Loop Back Pair Direction Bit[6]" "Input,Output"
|
|
bitfld.long 0x00 5. " [5] ,Loop Back Pair Direction Bit[5]" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 4. " [4] ,Loop Back Pair Direction Bit[4]" "Input,Output"
|
|
bitfld.long 0x00 3. " [3] ,Loop Back Pair Direction Bit[3]" "Input,Output"
|
|
bitfld.long 0x00 2. " [2] ,Loop Back Pair Direction Bit[2]" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 1. " [1] ,Loop Back Pair Direction Bit[1]" "Input,Output"
|
|
bitfld.long 0x00 0. " [0] ,Loop Back Pair Direction Bit[0]" "Input,Output"
|
|
line.long 0x04 "PINDIS,Pin Disable Register"
|
|
bitfld.long 0x04 31. " HETPINDIS[31] ,NHET Pin Disable Bit[31]" "No,Yes"
|
|
bitfld.long 0x04 30. " [30] ,NHET Pin Disable Bit[30]" "No,Yes"
|
|
bitfld.long 0x04 29. " [29] ,NHET Pin Disable Bit[29]" "No,Yes"
|
|
newline
|
|
bitfld.long 0x04 28. " [28] ,NHET Pin Disable Bit[28]" "No,Yes"
|
|
bitfld.long 0x04 27. " [27] ,NHET Pin Disable Bit[27]" "No,Yes"
|
|
bitfld.long 0x04 26. " [26] ,NHET Pin Disable Bit[26]" "No,Yes"
|
|
newline
|
|
bitfld.long 0x04 25. " [25] ,NHET Pin Disable Bit[25]" "No,Yes"
|
|
bitfld.long 0x04 24. " [24] ,NHET Pin Disable Bit[24]" "No,Yes"
|
|
bitfld.long 0x04 23. " [23] ,NHET Pin Disable Bit[23]" "No,Yes"
|
|
newline
|
|
bitfld.long 0x04 22. " [22] ,NHET Pin Disable Bit[22]" "No,Yes"
|
|
bitfld.long 0x04 21. " [21] ,NHET Pin Disable Bit[21]" "No,Yes"
|
|
bitfld.long 0x04 20. " [20] ,NHET Pin Disable Bit[20]" "No,Yes"
|
|
newline
|
|
bitfld.long 0x04 19. " [19] ,NHET Pin Disable Bit[19]" "No,Yes"
|
|
bitfld.long 0x04 18. " [18] ,NHET Pin Disable Bit[18]" "No,Yes"
|
|
bitfld.long 0x04 17. " [17] ,NHET Pin Disable Bit[17]" "No,Yes"
|
|
newline
|
|
bitfld.long 0x04 16. " [16] ,NHET Pin Disable Bit[16]" "No,Yes"
|
|
bitfld.long 0x04 15. " [15] ,NHET Pin Disable Bit[15]" "No,Yes"
|
|
bitfld.long 0x04 14. " [14] ,NHET Pin Disable Bit[14]" "No,Yes"
|
|
newline
|
|
bitfld.long 0x04 13. " [13] ,NHET Pin Disable Bit[13]" "No,Yes"
|
|
bitfld.long 0x04 12. " [12] ,NHET Pin Disable Bit[12]" "No,Yes"
|
|
bitfld.long 0x04 11. " [11] ,NHET Pin Disable Bit[11]" "No,Yes"
|
|
newline
|
|
bitfld.long 0x04 10. " [10] ,NHET Pin Disable Bit[10]" "No,Yes"
|
|
bitfld.long 0x04 9. " [9] ,NHET Pin Disable Bit[9]" "No,Yes"
|
|
bitfld.long 0x04 8. " [8] ,NHET Pin Disable Bit[8]" "No,Yes"
|
|
newline
|
|
bitfld.long 0x04 7. " [7] ,NHET Pin Disable Bit[7]" "No,Yes"
|
|
bitfld.long 0x04 6. " [6] ,NHET Pin Disable Bit[6]" "No,Yes"
|
|
bitfld.long 0x04 5. " [5] ,NHET Pin Disable Bit[5]" "No,Yes"
|
|
newline
|
|
bitfld.long 0x04 4. " [4] ,NHET Pin Disable Bit[4]" "No,Yes"
|
|
bitfld.long 0x04 3. " [3] ,NHET Pin Disable Bit[3]" "No,Yes"
|
|
bitfld.long 0x04 2. " [2] ,NHET Pin Disable Bit[2]" "No,Yes"
|
|
newline
|
|
bitfld.long 0x04 1. " [1] ,NHET Pin Disable Bit[1]" "No,Yes"
|
|
bitfld.long 0x04 0. " [0] ,NHET Pin Disable Bit[0]" "No,Yes"
|
|
sif cpuis("TMS570LS0714*")||cpuis("TMS570LS0914*")
|
|
width 16.
|
|
group.long 0x9C++0x13 "HWAG Registers"
|
|
line.long 0x00 "HWAPINSEL,HWAG Pin Select Register"
|
|
bitfld.long 0x00 0.--4. " PINSEL ,HWAG pin select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
line.long 0x04 "HWAGCR0,HWAG Control Register 0"
|
|
bitfld.long 0x04 0. " RESET ,HWAG module reset" "Reset,No reset"
|
|
line.long 0x08 "HWAGCR1,HWAG Control Register 1"
|
|
bitfld.long 0x08 0. " PPWN ,HWAG module power down" "Powered up,Powered down"
|
|
line.long 0x0C "HWAGCR2,HWAG Control Register 2"
|
|
bitfld.long 0x0C 24. " ARST ,Angle reset" "No reset,Reset"
|
|
bitfld.long 0x0C 17. " TED ,Tooth edge" "Falling,Rising"
|
|
bitfld.long 0x0C 16. " CRI ,Criteria enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x0C 8. " FIL ,Input filter enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 0. " STRT ,Put the HWAG into run time start bit" "Stopped,Started"
|
|
line.long 0x10 "HWAENA_SET/CLR,HWAG Interrupt Enable Set/Clear Register"
|
|
setclrfld.long 0x10 7. 0x10 7. 0x14 7. " INTENA[7] ,Enable interrupt [7]" "Disabled,Enabled"
|
|
setclrfld.long 0x10 6. 0x10 6. 0x14 6. " [6] ,Enable interrupt [6]" "Disabled,Enabled"
|
|
setclrfld.long 0x10 5. 0x10 5. 0x14 5. " [5] ,Enable interrupt [5]" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x10 4. 0x10 4. 0x14 4. " [4] ,Enable interrupt [4]" "Disabled,Enabled"
|
|
setclrfld.long 0x10 3. 0x10 3. 0x14 3. " [3] ,Enable interrupt [3]" "Disabled,Enabled"
|
|
setclrfld.long 0x10 2. 0x10 2. 0x14 2. " [2] ,Enable interrupt [2]" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x10 1. 0x10 1. 0x14 1. " [1] ,Enable interrupt [1]" "Disabled,Enabled"
|
|
setclrfld.long 0x10 0. 0x10 0. 0x14 0. " [0] ,Enable interrupt [0]" "Disabled,Enabled"
|
|
group.long 0xB0++0x03
|
|
line.long 0x00 "HWALVL_SET/CLR,HWAG Interrupt Priority Set Register"
|
|
setclrfld.long 0x00 7. 0x00 7. 0x04 7. " LVLSET[7] ,Set interrupt [7] priority level" "Low,High"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x04 6. " [6] ,Set interrupt [6] priority level" "Low,High"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x04 5. " [5] ,Set interrupt [5] priority level" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 4. 0x00 4. 0x04 4. " [4] ,Set interrupt [4] priority level" "Low,High"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x04 3. " [3] ,Set interrupt [3] priority level" "Low,High"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x04 2. " [2] ,Set interrupt [2] priority level" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 1. 0x00 1. 0x04 1. " [1] ,Set interrupt [1] priority level" "Low,High"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x04 0. " [0] ,Set interrupt [0] priority level" "Low,High"
|
|
group.long 0xB8++0x27
|
|
line.long 0x00 "HWAFLG,HWAG Interrupt Flags Register"
|
|
eventfld.long 0x00 7. " INTFLG[7] ,Interrupt 7 flag" "No effect,Pending"
|
|
eventfld.long 0x00 6. " [6] ,Interrupt 6 flag" "No effect,Pending"
|
|
eventfld.long 0x00 5. " [5] ,Interrupt 5 flag" "No effect,Pending"
|
|
newline
|
|
eventfld.long 0x00 4. " [4] ,Interrupt 4 flag" "No effect,Pending"
|
|
eventfld.long 0x00 3. " [3] ,Interrupt 3 flag" "No effect,Pending"
|
|
eventfld.long 0x00 2. " [2] ,Interrupt 2 flag" "No effect,Pending"
|
|
newline
|
|
eventfld.long 0x00 1. " [1] ,Interrupt 1 flag" "No effect,Pending"
|
|
eventfld.long 0x00 0. " [0] ,Interrupt 0 flag" "No effect,Pending"
|
|
line.long 0x04 "HWAOFF0,HWAG Interrupt Offset Register 0"
|
|
hexmask.long.byte 0x04 0.--7. 0x01 " OFFSET1 ,High-priority interrupt offset"
|
|
line.long 0x08 "HWAOFF1,HWAG Interrupt Offset Register 1"
|
|
hexmask.long.byte 0x08 0.--7. 0x01 " OFFSET2 ,Low-priority interrupt offset"
|
|
line.long 0x0C "HWAACNT,HWAG ACNT Register, HWAG Angle Value"
|
|
hexmask.long.tbyte 0x0C 0.--23. 1. " ACNT ,Angle value"
|
|
line.long 0x10 "HWAPCNT1,HWAG PCNT (n-1) Register, HWAG Previous Tooth Period"
|
|
hexmask.long.tbyte 0x10 0.--23. 1. " PCNT(N-1) ,Period (n-1) value"
|
|
line.long 0x14 "HWAPCNT,HWAG PCNT (n) Register, HWAG Current Tooth Period"
|
|
hexmask.long.tbyte 0x14 0.--23. 1. " PCNT(N) ,Period (n) value"
|
|
line.long 0x18 "HWASTWD,HWAG Step Register"
|
|
bitfld.long 0x18 0.--3. " STWD ,Step width (ticks per period)" "4,8,16,32,64,128,256,512,1024,2048,4096,8192,16384,32768,65536,131072"
|
|
line.long 0x1C "HWATHNB,HWAG Teeth Number Register"
|
|
hexmask.long.byte 0x1C 0.--7. 1. " THNB ,Teeth number"
|
|
line.long 0x20 "HWATHVL,HHWAG Current Teeth Number Register"
|
|
hexmask.long.byte 0x20 0.--7. 1. " THVL ,Teeth value"
|
|
line.long 0x24 "HWAFIL,HWAG Filter Register"
|
|
hexmask.long.word 0x24 0.--9. 1. " FIL1 ,Filter value 1"
|
|
group.long 0xE8++0x07
|
|
line.long 0x00 "HWAFIL2,HWAG Filter Register 2, HWAG Tick Counter Compare Value During Singularity Tooth"
|
|
hexmask.long.word 0x00 0.--11. 1. " FIL2 ,Filter value 2"
|
|
line.long 0x04 "HWAANGI,HWAG Angle Increment Register"
|
|
hexmask.long.word 0x04 0.--9. 1. " ANGI ,Angle increment value"
|
|
elif (cpu()==("TMS570LS2126")||cpu()==("TMS570LS2127")||cpu()==("TMS570LS2136")||cpu()==("TMS570LS2137")||cpu()==("TMS570LS2125-PGE")||cpu()==("TMS570LS2125-ZWT")||cpu()==("TMS570LS2135-PGE")||cpu()==("TMS570LS2135-ZWT")||cpu()==("TMS570LS2124-PGE")||cpu()==("TMS570LS2124-ZWT")||cpu()==("TMS570LS2134-PGE")||cpu()==("TMS570LS2134-ZWT")||cpu()==("TMS570LS3134-PGE")||cpu()==("TMS570LS3134-ZWT")||cpu()==("TMS570LS3135-PGE")||cpu()==("TMS570LS3135-ZWT")||cpu()==("TMS570LS3136")||cpu()==("TMS570LS3137-PGE")||cpu()==("TMS570LS3137-ZWT")||cpu()==("TMS570LS30336")||cpuis("RM48L950*"))
|
|
group.long 0xA0++0x43
|
|
line.long 0x00 "HWAGCR0,HWAG Control Register 0"
|
|
line.long 0x04 "HWAGCR1,HWAG Control Register 1"
|
|
line.long 0x08 "HWAGCR2,HWAG Control Register 2"
|
|
line.long 0x0C "HWAENASET,HWAG Interrupt Enable Set Register"
|
|
line.long 0x10 "HWAENACLR,HWAG Interrupt Enable Clear Register"
|
|
line.long 0x14 "HWALVLSET,HWAG Interrupt Priority Set Register"
|
|
line.long 0x18 "HWALVLCLR,HWAG Interrupt Priority Clear Register"
|
|
line.long 0x1C "HWAFLG,HWAG Interrupt Flags Register"
|
|
line.long 0x20 "HWAOFF0,HWAG Interrupt Offset Register 1, HWAG Low Priority Interrupt Offset"
|
|
line.long 0x24 "HWAOFF1,HWAG Interrupt Offset Register 2, HWAG High Priority Interrupt Offset"
|
|
line.long 0x28 "HWAACNT,HWAG ACNT Register, HWAG Angle Value"
|
|
line.long 0x2C "HWAPCNT1,HWAG PCNT (n-1) Register, HWAG Previous Tooth Period"
|
|
line.long 0x30 "HWAPCNT,HWAG PCNT (n) Register, HWAG Current Tooth Period"
|
|
line.long 0x34 "HWASTWD,HWAG Step Register"
|
|
line.long 0x38 "HWATHNB,HWAG Teeth Number Register"
|
|
line.long 0x3C "HWATHVL,HHWAG Current Teeth Number Register"
|
|
line.long 0x40 "HWAFIL,HWAG Filter Register, HWAG Tick Counter Compare Value"
|
|
group.long 0xE8++0x07
|
|
line.long 0x00 "HWAFIL2,HWAG Filter Register 2, HWAG Tick Counter Compare Value During Singularity Tooth"
|
|
line.long 0x04 "HWAANGI,HWAG Angle Increment Register"
|
|
endif
|
|
sif cpuis("TMS570LS0232")||cpuis("TMS570LS0714*")||cpuis("TMS570LS0914*")
|
|
endian.le
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
tree.end
|
|
else
|
|
tree "N2HET (High-End Timer Module)"
|
|
base ad:0xFFF7B800
|
|
sif cpuis("TMS570LS0232")||cpuis("TMS570LS0714*")||cpuis("TMS570LS0914*")
|
|
endian.be
|
|
endif
|
|
width 15.
|
|
group.long 0x00++0x07
|
|
line.long 0x0 "GCR,Global Control Register"
|
|
bitfld.long 0x00 24. " HET_PIN_ENA ,NHET Pin Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 21.--22. " MP ,Master Priority" "Lower,Higher,Round robin,?..."
|
|
bitfld.long 0x00 18. " PPF ,Protect Program Fields" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 17. " IS ,Ignore Suspend" "Not ignored,Ignored"
|
|
bitfld.long 0x00 16. " CMS ,Clk_master/Slave" "Slave,Master"
|
|
bitfld.long 0x00 0. " TO ,Turn On/Off" "Off,On"
|
|
line.long 0x04 "PFR,Prescaler Factor Register"
|
|
bitfld.long 0x04 8.--10. " LRPFC ,Loop Resolution Pre-scale Factor Code" "1,2,4,8,16,32,64,128"
|
|
bitfld.long 0x04 0.--5. " HRPFC ,HR Prescale Factor Code" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64"
|
|
rgroup.long 0x08++0x0B
|
|
line.long 0x0 "ADDR,Current Address Register"
|
|
hexmask.long.word 0x00 0.--8. 1. " HETADDR ,N2HET Current Address"
|
|
line.long 0x04 "OFF1,Offset Level 1 Register"
|
|
hexmask.long.byte 0x04 0.--5. 1. " Offset1 ,Indexes the Currently Pending High-Priority Interrupt"
|
|
line.long 0x08 "OFF2,Offset Level 2 Register"
|
|
hexmask.long.byte 0x08 0.--5. 1. " Offset2 ,Indexes the Currently Pending High-Priority Interrupt"
|
|
newline
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "INTENA_SETCLR,Interrupt Enable Set/Clear Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x04 31. " HETINTENAS_setclr[31] ,Interrupt Enable Set Pin 31" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x04 30. " [30] ,Interrupt enable set/clear bit 30" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x04 29. " [29] ,Interrupt enable set/clear bit 29" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x04 28. " [28] ,Interrupt enable set/clear bit 28" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 27. 0x00 27. 0x04 27. " [27] ,Interrupt enable set/clear bit 27" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x04 26. " [26] ,Interrupt enable set/clear bit 26" "Disabled,Enabled"
|
|
setclrfld.long 0x00 25. 0x00 25. 0x04 25. " [25] ,Interrupt enable set/clear bit 25" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x04 24. " [24] ,Interrupt enable set/clear bit 24" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 23. 0x00 23. 0x04 23. " [23] ,Interrupt enable set/clear bit 23" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x04 22. " [22] ,Interrupt enable set/clear bit 22" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x04 21. " [21] ,Interrupt enable set/clear bit 21" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x04 20. " [20] ,Interrupt enable set/clear bit 20" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 19. 0x00 19. 0x04 19. " [19] ,Interrupt enable set/clear bit 19" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x04 18. " [18] ,Interrupt enable set/clear bit 18" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x04 17. " [17] ,Interrupt enable set/clear bit 17" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x04 16. " [16] ,Interrupt enable set/clear bit 16" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 15. 0x00 15. 0x04 15. " [15] ,Interrupt enable set/clear bit 15" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x04 14. " [14] ,Interrupt enable set/clear bit 14" "Disabled,Enabled"
|
|
setclrfld.long 0x00 13. 0x00 13. 0x04 13. " [13] ,Interrupt enable set/clear bit 13" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x04 12. " [12] ,Interrupt enable set/clear bit 12" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 11. 0x00 11. 0x04 11. " [11] ,Interrupt enable set/clear bit 11" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x04 10. " [10] ,Interrupt enable set/clear bit 10" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x04 9. " [9] ,Interrupt enable set/clear bit 9" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x04 8. " [8] ,Interrupt enable set/clear bit 8" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 7. 0x00 7. 0x04 7. " [7] ,Interrupt enable set/clear bit 7" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x04 6. " [6] ,Interrupt enable set/clear bit 6" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x04 5. " [5] ,Interrupt enable set/clear bit 5" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x04 4. " [4] ,Interrupt enable set/clear bit 4" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 3. 0x00 3. 0x04 3. " [3] ,Interrupt enable set/clear bit 3" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x04 2. " [2] ,Interrupt enable set/clear bit 2" "Disabled,Enabled"
|
|
setclrfld.long 0x00 1. 0x00 1. 0x04 1. " [1] ,Interrupt enable set/clear bit 1" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x04 0. " [0] ,Interrupt enable set/clear bit 0" "Disabled,Enabled"
|
|
newline
|
|
group.long 0x1C++0x0F
|
|
line.long 0x00 "EXC1,Exception Control Register 1"
|
|
bitfld.long 0x00 24. " APCNT_OVRFL_ENA ,APCNT Overflow Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " APCNT_UNDRFL_ENA ,APCNT Underflow Enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 8. " PRGM_OVRFL_ENA ,Program Overflow Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " APCNT_OVRFL_ENA_PRY ,APCNT_Ovrfl_Ena Priority" "Level 2,Level 1"
|
|
newline
|
|
bitfld.long 0x00 1. " APCNT_UNDRFL_ENA_PRY ,APCNT_Undrfl_Ena Priority" "Level 2,Level 1"
|
|
bitfld.long 0x00 0. " PRGM_OVRFL_ENA_PRY ,Prgm_Ovrfl_Ena Priority" "Level 2,Level 1"
|
|
line.long 0x04 "EXC2,Exception Control Register 2"
|
|
eventfld.long 0x04 8. " DEBUG_STATUS_FLG ,Debug_Status Flag" "No NHET,NHET"
|
|
eventfld.long 0x04 2. " APCNT_OVRFL_FLG ,APCNT Overflow Flag" "Not occurred,Occurred"
|
|
newline
|
|
eventfld.long 0x04 1. " APCNT_UNDRFL_FLG ,APCNT Underflow Flag" "Not occurred,Occurred"
|
|
eventfld.long 0x04 0. " PRGM_OVERFL_FLG ,Program Overflow Flag" "Not occurred,Occurred"
|
|
newline
|
|
line.long 0x08 "PRY,Interrupt Priority Register"
|
|
bitfld.long 0x08 31. " HETPRY[31] ,HET Priority Level Bit[31]" "Level 2,Level 1"
|
|
bitfld.long 0x08 30. " [30] ,HET Priority Level Bit[30]" "Level 2,Level 1"
|
|
bitfld.long 0x08 29. " [29] ,HET Priority Level Bit[29]" "Level 2,Level 1"
|
|
newline
|
|
bitfld.long 0x08 28. " [28] ,HET Priority Level Bit[28]" "Level 2,Level 1"
|
|
bitfld.long 0x08 27. " [27] ,HET Priority Level Bit[27]" "Level 2,Level 1"
|
|
bitfld.long 0x08 26. " [26] ,HET Priority Level Bit[26]" "Level 2,Level 1"
|
|
newline
|
|
bitfld.long 0x08 25. " [25] ,HET Priority Level Bit[25]" "Level 2,Level 1"
|
|
bitfld.long 0x08 24. " [24] ,HET Priority Level Bit[24]" "Level 2,Level 1"
|
|
bitfld.long 0x08 23. " [23] ,HET Priority Level Bit[23]" "Level 2,Level 1"
|
|
newline
|
|
bitfld.long 0x08 22. " [22] ,HET Priority Level Bit[22]" "Level 2,Level 1"
|
|
bitfld.long 0x08 21. " [21] ,HET Priority Level Bit[21]" "Level 2,Level 1"
|
|
bitfld.long 0x08 20. " [20] ,HET Priority Level Bit[20]" "Level 2,Level 1"
|
|
newline
|
|
bitfld.long 0x08 19. " [19] ,HET Priority Level Bit[19]" "Level 2,Level 1"
|
|
bitfld.long 0x08 18. " [18] ,HET Priority Level Bit[18]" "Level 2,Level 1"
|
|
bitfld.long 0x08 17. " [17] ,HET Priority Level Bit[17]" "Level 2,Level 1"
|
|
newline
|
|
bitfld.long 0x08 16. " [16] ,HET Priority Level Bit[16]" "Level 2,Level 1"
|
|
bitfld.long 0x08 15. " [15] ,HET Priority Level Bit[15]" "Level 2,Level 1"
|
|
bitfld.long 0x08 14. " [14] ,HET Priority Level Bit[14]" "Level 2,Level 1"
|
|
newline
|
|
bitfld.long 0x08 13. " [13] ,HET Priority Level Bit[13]" "Level 2,Level 1"
|
|
bitfld.long 0x08 12. " [12] ,HET Priority Level Bit[12]" "Level 2,Level 1"
|
|
bitfld.long 0x08 11. " [11] ,HET Priority Level Bit[11]" "Level 2,Level 1"
|
|
newline
|
|
bitfld.long 0x08 10. " [10] ,HET Priority Level Bit[10]" "Level 2,Level 1"
|
|
bitfld.long 0x08 9. " [9] ,HET Priority Level Bit[9]" "Level 2,Level 1"
|
|
bitfld.long 0x08 8. " [8] ,HET Priority Level Bit[8]" "Level 2,Level 1"
|
|
newline
|
|
bitfld.long 0x08 7. " [7] ,HET Priority Level Bit[7]" "Level 2,Level 1"
|
|
bitfld.long 0x08 6. " [6] ,HET Priority Level Bit[6]" "Level 2,Level 1"
|
|
bitfld.long 0x08 5. " [5] ,HET Priority Level Bit[5]" "Level 2,Level 1"
|
|
newline
|
|
bitfld.long 0x08 4. " [4] ,HET Priority Level Bit[4]" "Level 2,Level 1"
|
|
bitfld.long 0x08 3. " [3] ,HET Priority Level Bit[3]" "Level 2,Level 1"
|
|
bitfld.long 0x08 2. " [2] ,HET Priority Level Bit[2]" "Level 2,Level 1"
|
|
newline
|
|
bitfld.long 0x08 1. " [1] ,HET Priority Level Bit[1]" "Level 2,Level 1"
|
|
bitfld.long 0x08 0. " HETPRY[0] ,HET Priority Level Bit[0]" "Level 2,Level 1"
|
|
line.long 0x0C "FLG,Interrupt Flag Register"
|
|
eventfld.long 0x0C 31. " HETFLAG[31] ,Interrupt Flag Register Bit[31]" "No interrupt,Interrupt"
|
|
eventfld.long 0x0C 30. " [30] ,Interrupt Flag Register Bit[30]" "No interrupt,Interrupt"
|
|
newline
|
|
eventfld.long 0x0C 29. " [29] ,Interrupt Flag Register Bit[29]" "No interrupt,Interrupt"
|
|
eventfld.long 0x0C 28. " [28] ,Interrupt Flag Register Bit[28]" "No interrupt,Interrupt"
|
|
newline
|
|
eventfld.long 0x0C 27. " [27] ,Interrupt Flag Register Bit[27]" "No interrupt,Interrupt"
|
|
eventfld.long 0x0C 26. " [26] ,Interrupt Flag Register Bit[26]" "No interrupt,Interrupt"
|
|
newline
|
|
eventfld.long 0x0C 25. " [25] ,Interrupt Flag Register Bit[25]" "No interrupt,Interrupt"
|
|
eventfld.long 0x0C 24. " [24] ,Interrupt Flag Register Bit[24]" "No interrupt,Interrupt"
|
|
newline
|
|
eventfld.long 0x0C 23. " [23] ,Interrupt Flag Register Bit[23]" "No interrupt,Interrupt"
|
|
eventfld.long 0x0C 22. " [22] ,Interrupt Flag Register Bit[22]" "No interrupt,Interrupt"
|
|
newline
|
|
eventfld.long 0x0C 21. " [21] ,Interrupt Flag Register Bit[21]" "No interrupt,Interrupt"
|
|
eventfld.long 0x0C 20. " [20] ,Interrupt Flag Register Bit[20]" "No interrupt,Interrupt"
|
|
newline
|
|
eventfld.long 0x0C 19. " [19] ,Interrupt Flag Register Bit[19]" "No interrupt,Interrupt"
|
|
eventfld.long 0x0C 18. " [18] ,Interrupt Flag Register Bit[18]" "No interrupt,Interrupt"
|
|
newline
|
|
eventfld.long 0x0C 17. " [17] ,Interrupt Flag Register Bit[17]" "No interrupt,Interrupt"
|
|
eventfld.long 0x0C 16. " [16] ,Interrupt Flag Register Bit[16]" "No interrupt,Interrupt"
|
|
newline
|
|
eventfld.long 0x0C 15. " [15] ,Interrupt Flag Register Bit[15]" "No interrupt,Interrupt"
|
|
eventfld.long 0x0C 14. " [14] ,Interrupt Flag Register Bit[14]" "No interrupt,Interrupt"
|
|
newline
|
|
eventfld.long 0x0C 13. " [13] ,Interrupt Flag Register Bit[13]" "No interrupt,Interrupt"
|
|
eventfld.long 0x0C 12. " [12] ,Interrupt Flag Register Bit[12]" "No interrupt,Interrupt"
|
|
newline
|
|
eventfld.long 0x0C 11. " [11] ,Interrupt Flag Register Bit[11]" "No interrupt,Interrupt"
|
|
eventfld.long 0x0C 10. " [10] ,Interrupt Flag Register Bit[10]" "No interrupt,Interrupt"
|
|
newline
|
|
eventfld.long 0x0C 9. " [9] ,Interrupt Flag Register Bit[9]" "No interrupt,Interrupt"
|
|
eventfld.long 0x0C 8. " [8] ,Interrupt Flag Register Bit[8]" "No interrupt,Interrupt"
|
|
newline
|
|
eventfld.long 0x0C 7. " [7] ,Interrupt Flag Register Bit[7]" "No interrupt,Interrupt"
|
|
eventfld.long 0x0C 6. " [6] ,Interrupt Flag Register Bit[6]" "No interrupt,Interrupt"
|
|
newline
|
|
eventfld.long 0x0C 5. " [5] ,Interrupt Flag Register Bit[5]" "No interrupt,Interrupt"
|
|
eventfld.long 0x0C 4. " [4] ,Interrupt Flag Register Bit[4]" "No interrupt,Interrupt"
|
|
newline
|
|
eventfld.long 0x0C 3. " [3] ,Interrupt Flag Register Bit[3]" "No interrupt,Interrupt"
|
|
eventfld.long 0x0C 2. " [2] ,Interrupt Flag Register Bit[2]" "No interrupt,Interrupt"
|
|
newline
|
|
eventfld.long 0x0C 1. " [1] ,Interrupt Flag Register Bit[1]" "No interrupt,Interrupt"
|
|
eventfld.long 0x0C 0. " [0] ,Interrupt Flag Register Bit[0]" "No interrupt,Interrupt"
|
|
sif (CPU()==("TMS570LS2124-PGE")||CPU()==("TMS570LS2124-ZWT")||CPU()==("TMS570LS2134-PGE")||CPU()==("TMS570LS2134-ZWT")||CPU()==("TMS570LS3134-PGE")||CPU()==("TMS570LS3134-ZWT")||CPU()==("TMS570LS3135-PGE")||CPU()==("TMS570LS3135-ZWT")||CPU()==("TMS570LS3136")||CPU()==("TMS570LS3137-PGE")||CPU()==("TMS570LS3137-ZWT")||CPU()==("TMS570LS30336")||CPU()==("TMS570LS2126")||CPU()==("TMS570LS2127")||CPU()==("TMS570LS2136")||CPU()==("TMS570LS2137")||CPU()==("TMS570LS2125-PGE")||CPU()==("TMS570LS2125-ZWT")||CPU()==("TMS570LS2135-PGE")||CPU()==("TMS570LS2135-ZWT")||CPU()==("RM48L950")||cpu()=="RM48L952-PGE"||cpu()=="RM48L952-ZWT"||CPU()=="RM48L950-PGE"||CPU()=="RM48L950-ZWT"||CPU()=="RM48L940-ZWT"||CPU()=="RM48L940-PGE"||CPU()=="RM48L930-ZWT"||CPU()=="RM48L930-PGE"||CPU()=="RM48L750-ZWT"||CPU()=="RM48L750-PGE"||CPU()=="RM48L740-ZWT"||CPU()=="RM48L740-PGE"||CPU()=="RM48L730-ZWT"||CPU()=="RM48L730-PGE"||CPU()=="RM48L550-PGE"||CPU()=="RM48L540-ZWT"||CPU()=="RM48L540-PGE"||CPU()=="RM48L530-ZWT"||CPU()=="RM48L530-PGE"||CPU()=="RM46L852-PGE"||CPU()=="RM46L852-ZWT"||CPU()=="RM46L850-PGE"||CPU()=="RM46L850-ZWT"||CPU()=="RM46L840-ZWT"||CPU()=="RM46L840-PGE"||CPU()=="RM46L830-ZWT"||CPU()=="RM46L830-PGE"||CPU()=="RM46L450-ZWT"||CPU()=="RM46L450-PGE"||CPU()=="RM46L440-ZWT"||CPU()=="RM46L440-PGE"||CPU()=="RM46L430-ZWT"||CPU()=="RM46L430-PGE"||CPU()=="RM42L432"||CPU()=="TMS570LC4357"||CPU()==("TMS570LS0332")||CPU()==("TMS570LS0432")||CPUIS("TMS570LS1114*")||CPUIS("TMS570LS1115*")||CPUIS("TMS570LS1224*")||CPUIS("TMS570LS1225*")||CPUIS("TMS570LS1227*")||cpuis("TMS570LS0232")||cpuis("TMS570LS0714*")||cpuis("TMS570LS0914*"))
|
|
group.long 0x2C++0x3
|
|
line.long 0x00 "HETAND,And Share Control Register"
|
|
bitfld.long 0x00 15. " AND_SHARE[31/30] ,And share 31/30" "Not shared,Shared"
|
|
bitfld.long 0x00 14. " [29/28] ,And share 29/28" "Not shared,Shared"
|
|
newline
|
|
bitfld.long 0x00 13. " [27/26] ,And share 27/26" "Not shared,Shared"
|
|
bitfld.long 0x00 12. " [25/24] ,And share 25/24" "Not shared,Shared"
|
|
newline
|
|
bitfld.long 0x00 11. " [23/22] ,And share 23/22" "Not shared,Shared"
|
|
bitfld.long 0x00 10. " [21/20] ,And share 21/20" "Not shared,Shared"
|
|
newline
|
|
bitfld.long 0x00 9. " [19/18] ,And share 19/18" "Not shared,Shared"
|
|
bitfld.long 0x00 8. " [17/16] ,And share 17/16" "Not shared,Shared"
|
|
newline
|
|
bitfld.long 0x00 7. " [15/14] ,And share 15/14" "Not shared,Shared"
|
|
bitfld.long 0x00 6. " [13/12] ,And share 13/12" "Not shared,Shared"
|
|
newline
|
|
bitfld.long 0x00 5. " [11/10] ,And share 11/10" "Not shared,Shared"
|
|
bitfld.long 0x00 4. " [9/8] ,And share 9/8" "Not shared,Shared"
|
|
newline
|
|
bitfld.long 0x00 3. " [7/6] ,And share 7/6" "Not shared,Shared"
|
|
bitfld.long 0x00 2. " [5/4] ,And share 5/4" "Not shared,Shared"
|
|
newline
|
|
bitfld.long 0x00 1. " [3/2] ,And share 3/2" "Not shared,Shared"
|
|
bitfld.long 0x00 0. " [1/0] ,And share 1/0" "Not shared,Shared"
|
|
endif
|
|
group.long 0x34++0x07
|
|
line.long 0x0 "HRSH,HR Share Control Register"
|
|
bitfld.long 0x00 15. " HR_SHARE[31/30] ,HR Share 31/30" "Not shared,Shared"
|
|
bitfld.long 0x00 14. " [29/28] ,HR Share 29/28" "Not shared,Shared"
|
|
newline
|
|
bitfld.long 0x00 13. " [27/26] ,HR Share 27/26" "Not shared,Shared"
|
|
bitfld.long 0x00 12. " [25/24] ,HR Share 25/24" "Not shared,Shared"
|
|
newline
|
|
bitfld.long 0x00 11. " [23/22] ,HR Share 23/22" "Not shared,Shared"
|
|
bitfld.long 0x00 10. " [21/20] ,HR Share 21/20" "Not shared,Shared"
|
|
newline
|
|
bitfld.long 0x00 9. " [19/18] ,HR Share 19/18" "Not shared,Shared"
|
|
bitfld.long 0x00 8. " [17/16] ,HR Share 17/16" "Not shared,Shared"
|
|
newline
|
|
bitfld.long 0x00 7. " [15/14] ,HR Share 15/14" "Not shared,Shared"
|
|
bitfld.long 0x00 6. " [13/12] ,HR Share 13/12" "Not shared,Shared"
|
|
newline
|
|
bitfld.long 0x00 5. " [11/10] ,HR Share 11/10" "Not shared,Shared"
|
|
bitfld.long 0x00 4. " [9/8] ,HR Share 9/8" "Not shared,Shared"
|
|
newline
|
|
bitfld.long 0x00 3. " [7/6] ,HR Share 7/6" "Not shared,Shared"
|
|
bitfld.long 0x00 2. " [5/4] ,HR Share 5/4" "Not shared,Shared"
|
|
newline
|
|
bitfld.long 0x00 1. " [3/2] ,HR Share 3/2" "Not shared,Shared"
|
|
bitfld.long 0x00 0. " [1/0] ,HR Share 1/0" "Not shared,Shared"
|
|
line.long 0x04 "XOR,HR XOR Control Register"
|
|
bitfld.long 0x04 15. " HR_XOR_SHARE[31/30] ,HR XOR-Share 31/30" "Not XOR-shared,XOR-shared"
|
|
bitfld.long 0x04 14. " [29/28] ,HR XOR-Share 29/28" "Not XOR-shared,XOR-shared"
|
|
newline
|
|
bitfld.long 0x04 13. " [27/26] ,HR XOR-Share 27/26" "Not XOR-shared,XOR-shared"
|
|
bitfld.long 0x04 12. " [25/24] ,HR XOR-Share 25/24" "Not XOR-shared,XOR-shared"
|
|
newline
|
|
bitfld.long 0x04 11. " [23/22] ,HR XOR-Share 23/22" "Not XOR-shared,XOR-shared"
|
|
bitfld.long 0x04 10. " [21/20] ,HR XOR-Share 21/20" "Not XOR-shared,XOR-shared"
|
|
newline
|
|
bitfld.long 0x04 9. " [19/18] ,HR XOR-Share 19/18" "Not XOR-shared,XOR-shared"
|
|
bitfld.long 0x04 8. " [17/16] ,HR XOR-Share 17/16" "Not XOR-shared,XOR-shared"
|
|
newline
|
|
bitfld.long 0x04 7. " [15/14] ,HR XOR-Share 15/14" "Not XOR-shared,XOR-shared"
|
|
bitfld.long 0x04 6. " [13/12] ,HR XOR-Share 13/12" "Not XOR-shared,XOR-shared"
|
|
newline
|
|
bitfld.long 0x04 5. " [11/10] ,HR XOR-Share 11/10" "Not XOR-shared,XOR-shared"
|
|
bitfld.long 0x04 4. " [9/8] ,HR XOR-Share 9/8" "Not XOR-shared,XOR-shared"
|
|
newline
|
|
bitfld.long 0x04 3. " [7/6] ,HR XOR-Share 7/6" "Not XOR-shared,XOR-shared"
|
|
bitfld.long 0x04 2. " [5/4] ,HR XOR-Share 5/4" "Not XOR-shared,XOR-shared"
|
|
newline
|
|
bitfld.long 0x04 1. " [3/2] ,HR XOR-Share 3/2" "Not XOR-shared,XOR-shared"
|
|
bitfld.long 0x04 0. " [1/0] ,HR XOR-Share 1/0" "Not XOR-shared,XOR-shared"
|
|
group.long 0x3C++0x03
|
|
line.long 0x00 "REQEN_SETCLR,Request Enable Set/Clear Register"
|
|
setclrfld.long 0x00 7. 0x00 7. 0x04 7. " REQENA_SET/CLR[7] ,Request enable set/clear bit [7]" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x04 6. " [6] ,Request enable set/clear bit [6]" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x04 5. " [5] ,Request enable set/clear bit [5]" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x04 4. " [4] ,Request enable set/clear bit [4]" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 3. 0x00 3. 0x04 3. " [3] ,Request enable set/clear bit [3]" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x04 2. " [2] ,Request enable set/clear bit [2]" "Disabled,Enabled"
|
|
setclrfld.long 0x00 1. 0x00 1. 0x04 1. " [1] ,Request enable set/clear bit [1]" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x04 0. " [0] ,Request enable set/clear bit [0]" "Disabled,Enabled"
|
|
sif (cpu()!=("TMS570LS0332")&&cpu()!=("TMS570LS0432")&&!cpuis("TMS570LS0232"))
|
|
group.long 0x44++0x3
|
|
line.long 0x00 "REQDS,Request Destination Select Register"
|
|
bitfld.long 0x00 23. " TDBS[7] ,HTU/DMA or Both Select Bit[7]" "HTU,Both"
|
|
bitfld.long 0x00 22. " [6] ,HTU/DMA or Both Select Bit[6]" "HTU,Both"
|
|
bitfld.long 0x00 21. " [5] ,HTU/DMA or Both Select Bit[5]" "HTU,Both"
|
|
bitfld.long 0x00 20. " [4] ,HTU/DMA or Both Select Bit[4]" "HTU,Both"
|
|
newline
|
|
bitfld.long 0x00 19. " [3] ,HTU/DMA or Both Select Bit[3]" "HTU,Both"
|
|
bitfld.long 0x00 18. " [2] ,HTU/DMA or Both Select Bit[2]" "HTU,Both"
|
|
bitfld.long 0x00 17. " [1] ,HTU/DMA or Both Select Bit[1]" "HTU,Both"
|
|
bitfld.long 0x00 16. " [0] ,HTU/DMA or Both Select Bit[0]" "HTU,Both"
|
|
newline
|
|
bitfld.long 0x00 7. " TDS[7] ,HTU or DMA Select Bit[7]" "HTU,DMA"
|
|
bitfld.long 0x00 6. " TDS[6] ,HTU or DMA Select Bit[6]" "HTU,DMA"
|
|
bitfld.long 0x00 5. " TDS[5] ,HTU or DMA Select Bit[5]" "HTU,DMA"
|
|
bitfld.long 0x00 4. " TDS[4] ,HTU or DMA Select Bit[4]" "HTU,DMA"
|
|
newline
|
|
bitfld.long 0x00 3. " TDS[3] ,HTU or DMA Select Bit[3]" "HTU,DMA"
|
|
bitfld.long 0x00 2. " TDS[2] ,HTU or DMA Select Bit[2]" "HTU,DMA"
|
|
bitfld.long 0x00 1. " TDS[1] ,HTU or DMA Select Bit[1]" "HTU,DMA"
|
|
bitfld.long 0x00 0. " TDS[0] ,HTU or DMA Select Bit[0]" "HTU,DMA"
|
|
endif
|
|
group.long 0x4C++0x3
|
|
line.long 0x00 "DIR,Direction Register"
|
|
bitfld.long 0x00 31. " HET_DIR[31] ,Input/Output Direction Pin 31" "Input,Output"
|
|
bitfld.long 0x00 30. " [30] ,Input/Output Direction Pin 30" "Input,Output"
|
|
bitfld.long 0x00 29. " [29] ,Input/Output Direction Pin 29" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 28. " [28] ,Input/Output Direction Pin 28" "Input,Output"
|
|
bitfld.long 0x00 27. " [27] ,Input/Output Direction Pin 27" "Input,Output"
|
|
bitfld.long 0x00 26. " [26] ,Input/Output Direction Pin 26" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 25. " [25] ,Input/Output Direction Pin 25" "Input,Output"
|
|
bitfld.long 0x00 24. " [24] ,Input/Output Direction Pin 24" "Input,Output"
|
|
bitfld.long 0x00 23. " [23] ,Input/Output Direction Pin 23" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 22. " [22] ,Input/Output Direction Pin 22" "Input,Output"
|
|
bitfld.long 0x00 21. " [21] ,Input/Output Direction Pin 21" "Input,Output"
|
|
bitfld.long 0x00 20. " [20] ,Input/Output Direction Pin 20" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 19. " [19] ,Input/Output Direction Pin 19" "Input,Output"
|
|
bitfld.long 0x00 18. " [18] ,Input/Output Direction Pin 18" "Input,Output"
|
|
bitfld.long 0x00 17. " [17] ,Input/Output Direction Pin 17" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 16. " [16] ,Input/Output Direction Pin 16" "Input,Output"
|
|
bitfld.long 0x00 15. " [15] ,Input/Output Direction Pin 15" "Input,Output"
|
|
bitfld.long 0x00 14. " [14] ,Input/Output Direction Pin 14" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 13. " [13] ,Input/Output Direction Pin 13" "Input,Output"
|
|
bitfld.long 0x00 12. " [12] ,Input/Output Direction Pin 12" "Input,Output"
|
|
bitfld.long 0x00 11. " [11] ,Input/Output Direction Pin 11" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 10. " [10] ,Input/Output Direction Pin 10" "Input,Output"
|
|
bitfld.long 0x00 9. " [9] ,Input/Output Direction Pin 9" "Input,Output"
|
|
bitfld.long 0x00 8. " [8] ,Input/Output Direction Pin 8" "Input,Output"
|
|
newline
|
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bitfld.long 0x00 7. " [7] ,Input/Output Direction Pin 7" "Input,Output"
|
|
bitfld.long 0x00 6. " [6] ,Input/Output Direction Pin 6" "Input,Output"
|
|
bitfld.long 0x00 5. " [5] ,Input/Output Direction Pin 5" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 4. " [4] ,Input/Output Direction Pin 4" "Input,Output"
|
|
bitfld.long 0x00 3. " [3] ,Input/Output Direction Pin 3" "Input,Output"
|
|
bitfld.long 0x00 2. " [2] ,Input/Output Direction Pin 2" "Input,Output"
|
|
newline
|
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bitfld.long 0x00 1. " [1] ,Input/Output Direction Pin 1" "Input,Output"
|
|
bitfld.long 0x00 0. " [0] ,Input/Output Direction Pin 0" "Input,Output"
|
|
rgroup.long 0x50++0x3
|
|
line.long 0x00 "DIN,Input Data Register"
|
|
bitfld.long 0x00 31. " HETDIN[31] ,NHET Data Input Register Pin 31" "Low,High"
|
|
bitfld.long 0x00 30. " [30] ,NHET Data Input Register Pin 30" "Low,High"
|
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bitfld.long 0x00 29. " [29] ,NHET Data Input Register Pin 29" "Low,High"
|
|
bitfld.long 0x00 28. " [28] ,NHET Data Input Register Pin 28" "Low,High"
|
|
newline
|
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bitfld.long 0x00 27. " [27] ,NHET Data Input Register Pin 27" "Low,High"
|
|
bitfld.long 0x00 26. " [26] ,NHET Data Input Register Pin 26" "Low,High"
|
|
bitfld.long 0x00 25. " [25] ,NHET Data Input Register Pin 25" "Low,High"
|
|
bitfld.long 0x00 24. " [24] ,NHET Data Input Register Pin 24" "Low,High"
|
|
newline
|
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bitfld.long 0x00 23. " [23] ,NHET Data Input Register Pin 23" "Low,High"
|
|
bitfld.long 0x00 22. " [22] ,NHET Data Input Register Pin 22" "Low,High"
|
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bitfld.long 0x00 21. " [21] ,NHET Data Input Register Pin 21" "Low,High"
|
|
bitfld.long 0x00 20. " [20] ,NHET Data Input Register Pin 20" "Low,High"
|
|
newline
|
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bitfld.long 0x00 19. " [19] ,NHET Data Input Register Pin 19" "Low,High"
|
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bitfld.long 0x00 18. " [18] ,NHET Data Input Register Pin 18" "Low,High"
|
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bitfld.long 0x00 17. " [17] ,NHET Data Input Register Pin 17" "Low,High"
|
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bitfld.long 0x00 16. " [16] ,NHET Data Input Register Pin 16" "Low,High"
|
|
newline
|
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bitfld.long 0x00 15. " [15] ,NHET Data Input Register Pin 15" "Low,High"
|
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bitfld.long 0x00 14. " [14] ,NHET Data Input Register Pin 14" "Low,High"
|
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bitfld.long 0x00 13. " [13] ,NHET Data Input Register Pin 13" "Low,High"
|
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bitfld.long 0x00 12. " [12] ,NHET Data Input Register Pin 12" "Low,High"
|
|
newline
|
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bitfld.long 0x00 11. " [11] ,NHET Data Input Register Pin 11" "Low,High"
|
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bitfld.long 0x00 10. " [10] ,NHET Data Input Register Pin 10" "Low,High"
|
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bitfld.long 0x00 9. " [9] ,NHET Data Input Register Pin 9" "Low,High"
|
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bitfld.long 0x00 8. " [8] ,NHET Data Input Register Pin 8" "Low,High"
|
|
newline
|
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bitfld.long 0x00 7. " [7] ,NHET Data Input Register Pin 7" "Low,High"
|
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bitfld.long 0x00 6. " [6] ,NHET Data Input Register Pin 6" "Low,High"
|
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bitfld.long 0x00 5. " [5] ,NHET Data Input Register Pin 5" "Low,High"
|
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bitfld.long 0x00 4. " [4] ,NHET Data Input Register Pin 4" "Low,High"
|
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newline
|
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bitfld.long 0x00 3. " [3] ,NHET Data Input Register Pin 3" "Low,High"
|
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bitfld.long 0x00 2. " [2] ,NHET Data Input Register Pin 2" "Low,High"
|
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bitfld.long 0x00 1. " [1] ,NHET Data Input Register Pin 1" "Low,High"
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bitfld.long 0x00 0. " [0] ,NHET Data Input Register Pin 0" "Low,High"
|
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group.long 0x54++0x3
|
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line.long 0x00 "DOUT_SET/CLR,Output Data Set/Clear Register"
|
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setclrfld.long 0x00 31. 0x04 31. 0x08 31. " HETDOUT[31] ,NHET Data Output Register Bit[31]" "Low,High"
|
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setclrfld.long 0x00 30. 0x04 30. 0x08 30. " [30] ,NHET Data Output Register Bit[30]" "Low,High"
|
|
newline
|
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setclrfld.long 0x00 29. 0x04 29. 0x08 29. " [29] ,NHET Data Output Register Bit[29]" "Low,High"
|
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setclrfld.long 0x00 28. 0x04 28. 0x08 28. " [28] ,NHET Data Output Register Bit[28]" "Low,High"
|
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newline
|
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setclrfld.long 0x00 27. 0x04 27. 0x08 27. " [27] ,NHET Data Output Register Bit[27]" "Low,High"
|
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setclrfld.long 0x00 26. 0x04 26. 0x08 26. " [26] ,NHET Data Output Register Bit[26]" "Low,High"
|
|
newline
|
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setclrfld.long 0x00 25. 0x04 25. 0x08 25. " [25] ,NHET Data Output Register Bit[25]" "Low,High"
|
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setclrfld.long 0x00 24. 0x04 24. 0x08 24. " [24] ,NHET Data Output Register Bit[24]" "Low,High"
|
|
newline
|
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setclrfld.long 0x00 23. 0x04 23. 0x08 23. " [23] ,NHET Data Output Register Bit[23]" "Low,High"
|
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setclrfld.long 0x00 22. 0x04 22. 0x08 22. " [22] ,NHET Data Output Register Bit[22]" "Low,High"
|
|
newline
|
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setclrfld.long 0x00 21. 0x04 21. 0x08 21. " [21] ,NHET Data Output Register Bit[21]" "Low,High"
|
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setclrfld.long 0x00 20. 0x04 20. 0x08 20. " [20] ,NHET Data Output Register Bit[20]" "Low,High"
|
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newline
|
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setclrfld.long 0x00 19. 0x04 19. 0x08 19. " [19] ,NHET Data Output Register Bit[19]" "Low,High"
|
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setclrfld.long 0x00 18. 0x04 18. 0x08 18. " [18] ,NHET Data Output Register Bit[18]" "Low,High"
|
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newline
|
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setclrfld.long 0x00 17. 0x04 17. 0x08 17. " [17] ,NHET Data Output Register Bit[17]" "Low,High"
|
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setclrfld.long 0x00 16. 0x04 16. 0x08 16. " [16] ,NHET Data Output Register Bit[16]" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 15. 0x04 15. 0x08 15. " [15] ,NHET Data Output Register Bit[15]" "Low,High"
|
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setclrfld.long 0x00 14. 0x04 14. 0x08 14. " [14] ,NHET Data Output Register Bit[14]" "Low,High"
|
|
newline
|
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setclrfld.long 0x00 13. 0x04 13. 0x08 13. " [13] ,NHET Data Output Register Bit[13]" "Low,High"
|
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setclrfld.long 0x00 12. 0x04 12. 0x08 12. " [12] ,NHET Data Output Register Bit[12]" "Low,High"
|
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newline
|
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setclrfld.long 0x00 11. 0x04 11. 0x08 11. " [11] ,NHET Data Output Register Bit[11]" "Low,High"
|
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setclrfld.long 0x00 10. 0x04 10. 0x08 10. " [10] ,NHET Data Output Register Bit[10]" "Low,High"
|
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newline
|
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setclrfld.long 0x00 9. 0x04 9. 0x08 9. " [9] ,NHET Data Output Register Bit[9]" "Low,High"
|
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setclrfld.long 0x00 8. 0x04 8. 0x08 8. " [8] ,NHET Data Output Register Bit[8]" "Low,High"
|
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newline
|
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setclrfld.long 0x00 7. 0x04 7. 0x08 7. " [7] ,NHET Data Output Register Bit[7]" "Low,High"
|
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setclrfld.long 0x00 6. 0x04 6. 0x08 6. " [6] ,NHET Data Output Register Bit[6]" "Low,High"
|
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newline
|
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setclrfld.long 0x00 5. 0x04 5. 0x08 5. " [5] ,NHET Data Output Register Bit[5]" "Low,High"
|
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setclrfld.long 0x00 4. 0x04 4. 0x08 4. " [4] ,NHET Data Output Register Bit[4]" "Low,High"
|
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newline
|
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setclrfld.long 0x00 3. 0x04 3. 0x08 3. " [3] ,NHET Data Output Register Bit[3]" "Low,High"
|
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setclrfld.long 0x00 2. 0x04 2. 0x08 2. " [2] ,NHET Data Output Register Bit[2]" "Low,High"
|
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newline
|
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setclrfld.long 0x00 1. 0x04 1. 0x08 1. " [1] ,NHET Data Output Register Bit[1]" "Low,High"
|
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setclrfld.long 0x00 0. 0x04 0. 0x08 0. " [0] ,NHET Data Output Register Bit[0]" "Low,High"
|
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group.long 0x60++0x0B
|
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line.long 0x00 "PDR,Open Drain Register"
|
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bitfld.long 0x00 31. " HETPDR[31] ,NHET Open Drain Bit[31]" "Disabled,Enabled"
|
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bitfld.long 0x00 30. " [30] ,NHET Open Drain Bit[30]" "Disabled,Enabled"
|
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bitfld.long 0x00 29. " [29] ,NHET Open Drain Bit[29]" "Disabled,Enabled"
|
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newline
|
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bitfld.long 0x00 28. " [28] ,NHET Open Drain Bit[28]" "Disabled,Enabled"
|
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bitfld.long 0x00 27. " [27] ,NHET Open Drain Bit[27]" "Disabled,Enabled"
|
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bitfld.long 0x00 26. " [26] ,NHET Open Drain Bit[26]" "Disabled,Enabled"
|
|
newline
|
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bitfld.long 0x00 25. " [25] ,NHET Open Drain Bit[25]" "Disabled,Enabled"
|
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bitfld.long 0x00 24. " [24] ,NHET Open Drain Bit[24]" "Disabled,Enabled"
|
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bitfld.long 0x00 23. " [23] ,NHET Open Drain Bit[23]" "Disabled,Enabled"
|
|
newline
|
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bitfld.long 0x00 22. " [22] ,NHET Open Drain Bit[22]" "Disabled,Enabled"
|
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bitfld.long 0x00 21. " [21] ,NHET Open Drain Bit[21]" "Disabled,Enabled"
|
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bitfld.long 0x00 20. " [20] ,NHET Open Drain Bit[20]" "Disabled,Enabled"
|
|
newline
|
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bitfld.long 0x00 19. " [19] ,NHET Open Drain Bit[19]" "Disabled,Enabled"
|
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bitfld.long 0x00 18. " [18] ,NHET Open Drain Bit[18]" "Disabled,Enabled"
|
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bitfld.long 0x00 17. " [17] ,NHET Open Drain Bit[17]" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 16. " [16] ,NHET Open Drain Bit[16]" "Disabled,Enabled"
|
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bitfld.long 0x00 15. " [15] ,NHET Open Drain Bit[15]" "Disabled,Enabled"
|
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bitfld.long 0x00 14. " [14] ,NHET Open Drain Bit[14]" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 13. " [13] ,NHET Open Drain Bit[13]" "Disabled,Enabled"
|
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bitfld.long 0x00 12. " [12] ,NHET Open Drain Bit[12]" "Disabled,Enabled"
|
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bitfld.long 0x00 11. " [11] ,NHET Open Drain Bit[11]" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 10. " [10] ,NHET Open Drain Bit[10]" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " [9] ,NHET Open Drain Bit[9]" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " [8] ,NHET Open Drain Bit[8]" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 7. " [7] ,NHET Open Drain Bit[7]" "Disabled,Enabled"
|
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bitfld.long 0x00 6. " [6] ,NHET Open Drain Bit[6]" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " [5] ,NHET Open Drain Bit[5]" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 4. " [4] ,NHET Open Drain Bit[4]" "Disabled,Enabled"
|
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bitfld.long 0x00 3. " [3] ,NHET Open Drain Bit[3]" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " [2] ,NHET Open Drain Bit[2]" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 1. " [1] ,NHET Open Drain Bit[1]" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,NHET Open Drain Bit[0]" "Disabled,Enabled"
|
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line.long 0x04 "PULDIS,Pull Disable Register"
|
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bitfld.long 0x04 31. " HETPULDIS[31] ,NHET Pull Disable Bit[31]" "No,Yes"
|
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bitfld.long 0x04 30. " [30] ,NHET Pull Disable Bit[30]" "No,Yes"
|
|
bitfld.long 0x04 29. " [29] ,NHET Pull Disable Bit[29]" "No,Yes"
|
|
newline
|
|
bitfld.long 0x04 28. " [28] ,NHET Pull Disable Bit[28]" "No,Yes"
|
|
bitfld.long 0x04 27. " [27] ,NHET Pull Disable Bit[27]" "No,Yes"
|
|
bitfld.long 0x04 26. " [26] ,NHET Pull Disable Bit[26]" "No,Yes"
|
|
newline
|
|
bitfld.long 0x04 25. " [25] ,NHET Pull Disable Bit[25]" "No,Yes"
|
|
bitfld.long 0x04 24. " [24] ,NHET Pull Disable Bit[24]" "No,Yes"
|
|
bitfld.long 0x04 23. " [23] ,NHET Pull Disable Bit[23]" "No,Yes"
|
|
newline
|
|
bitfld.long 0x04 22. " [22] ,NHET Pull Disable Bit[22]" "No,Yes"
|
|
bitfld.long 0x04 21. " [21] ,NHET Pull Disable Bit[21]" "No,Yes"
|
|
bitfld.long 0x04 20. " [20] ,NHET Pull Disable Bit[20]" "No,Yes"
|
|
newline
|
|
bitfld.long 0x04 19. " [19] ,NHET Pull Disable Bit[19]" "No,Yes"
|
|
bitfld.long 0x04 18. " [18] ,NHET Pull Disable Bit[18]" "No,Yes"
|
|
bitfld.long 0x04 17. " [17] ,NHET Pull Disable Bit[17]" "No,Yes"
|
|
newline
|
|
bitfld.long 0x04 16. " [16] ,NHET Pull Disable Bit[16]" "No,Yes"
|
|
bitfld.long 0x04 15. " [15] ,NHET Pull Disable Bit[15]" "No,Yes"
|
|
bitfld.long 0x04 14. " [14] ,NHET Pull Disable Bit[14]" "No,Yes"
|
|
newline
|
|
bitfld.long 0x04 13. " [13] ,NHET Pull Disable Bit[13]" "No,Yes"
|
|
bitfld.long 0x04 12. " [12] ,NHET Pull Disable Bit[12]" "No,Yes"
|
|
bitfld.long 0x04 11. " [11] ,NHET Pull Disable Bit[11]" "No,Yes"
|
|
newline
|
|
bitfld.long 0x04 10. " [10] ,NHET Pull Disable Bit[10]" "No,Yes"
|
|
bitfld.long 0x04 9. " [9] ,NHET Pull Disable Bit[9]" "No,Yes"
|
|
bitfld.long 0x04 8. " [8] ,NHET Pull Disable Bit[8]" "No,Yes"
|
|
newline
|
|
bitfld.long 0x04 7. " [7] ,NHET Pull Disable Bit[7]" "No,Yes"
|
|
bitfld.long 0x04 6. " [6] ,NHET Pull Disable Bit[6]" "No,Yes"
|
|
bitfld.long 0x04 5. " [5] ,NHET Pull Disable Bit[5]" "No,Yes"
|
|
newline
|
|
bitfld.long 0x04 4. " [4] ,NHET Pull Disable Bit[4]" "No,Yes"
|
|
bitfld.long 0x04 3. " [3] ,NHET Pull Disable Bit[3]" "No,Yes"
|
|
bitfld.long 0x04 2. " [2] ,NHET Pull Disable Bit[2]" "No,Yes"
|
|
newline
|
|
bitfld.long 0x04 1. " [1] ,NHET Pull Disable Bit[1]" "No,Yes"
|
|
bitfld.long 0x04 0. " [0] ,NHET Pull Disable Bit[0]" "No,Yes"
|
|
line.long 0x08 "PSL,Pull Select Register"
|
|
bitfld.long 0x08 31. " HETPSL[31] ,NHET Pull Select Bit[31]" "Pull down,Pull up"
|
|
bitfld.long 0x08 30. " [30] ,NHET Pull Select Bit[30]" "Pull down,Pull up"
|
|
bitfld.long 0x08 29. " [29] ,NHET Pull Select Bit[29]" "Pull down,Pull up"
|
|
newline
|
|
bitfld.long 0x08 28. " [28] ,NHET Pull Select Bit[28]" "Pull down,Pull up"
|
|
bitfld.long 0x08 27. " [27] ,NHET Pull Select Bit[27]" "Pull down,Pull up"
|
|
bitfld.long 0x08 26. " [26] ,NHET Pull Select Bit[26]" "Pull down,Pull up"
|
|
newline
|
|
bitfld.long 0x08 25. " [25] ,NHET Pull Select Bit[25]" "Pull down,Pull up"
|
|
bitfld.long 0x08 24. " [24] ,NHET Pull Select Bit[24]" "Pull down,Pull up"
|
|
bitfld.long 0x08 23. " [23] ,NHET Pull Select Bit[23]" "Pull down,Pull up"
|
|
newline
|
|
bitfld.long 0x08 22. " [22] ,NHET Pull Select Bit[22]" "Pull down,Pull up"
|
|
bitfld.long 0x08 21. " [21] ,NHET Pull Select Bit[21]" "Pull down,Pull up"
|
|
bitfld.long 0x08 20. " [20] ,NHET Pull Select Bit[20]" "Pull down,Pull up"
|
|
newline
|
|
bitfld.long 0x08 19. " [19] ,NHET Pull Select Bit[19]" "Pull down,Pull up"
|
|
bitfld.long 0x08 18. " [18] ,NHET Pull Select Bit[18]" "Pull down,Pull up"
|
|
bitfld.long 0x08 17. " [17] ,NHET Pull Select Bit[17]" "Pull down,Pull up"
|
|
newline
|
|
bitfld.long 0x08 16. " [16] ,NHET Pull Select Bit[16]" "Pull down,Pull up"
|
|
bitfld.long 0x08 15. " [15] ,NHET Pull Select Bit[15]" "Pull down,Pull up"
|
|
bitfld.long 0x08 14. " [14] ,NHET Pull Select Bit[14]" "Pull down,Pull up"
|
|
newline
|
|
bitfld.long 0x08 13. " [13] ,NHET Pull Select Bit[13]" "Pull down,Pull up"
|
|
bitfld.long 0x08 12. " [12] ,NHET Pull Select Bit[12]" "Pull down,Pull up"
|
|
bitfld.long 0x08 11. " [11] ,NHET Pull Select Bit[11]" "Pull down,Pull up"
|
|
newline
|
|
bitfld.long 0x08 10. " [10] ,NHET Pull Select Bit[10]" "Pull down,Pull up"
|
|
bitfld.long 0x08 9. " [9] ,NHET Pull Select Bit[9]" "Pull down,Pull up"
|
|
bitfld.long 0x08 8. " [8] ,NHET Pull Select Bit[8]" "Pull down,Pull up"
|
|
newline
|
|
bitfld.long 0x08 7. " [7] ,NHET Pull Select Bit[7]" "Pull down,Pull up"
|
|
bitfld.long 0x08 6. " [6] ,NHET Pull Select Bit[6]" "Pull down,Pull up"
|
|
bitfld.long 0x08 5. " [5] ,NHET Pull Select Bit[5]" "Pull down,Pull up"
|
|
newline
|
|
bitfld.long 0x08 4. " [4] ,NHET Pull Select Bit[4]" "Pull down,Pull up"
|
|
bitfld.long 0x08 3. " [3] ,NHET Pull Select Bit[3]" "Pull down,Pull up"
|
|
bitfld.long 0x08 2. " [2] ,NHET Pull Select Bit[2]" "Pull down,Pull up"
|
|
newline
|
|
bitfld.long 0x08 1. " [1] ,NHET Pull Select Bit[1]" "Pull down,Pull up"
|
|
bitfld.long 0x08 0. " [0] ,NHET Pull Select Bit[0]" "Pull down,Pull up"
|
|
group.long 0x74++0x3
|
|
line.long 0x0 "PCR,Parity Control Register"
|
|
bitfld.long 0x00 8. " TEST ,TEST" "Not mapped,Mapped"
|
|
bitfld.long 0x00 0.--3. " PARITY_ENA ,Enable / Disable Parity Checking" "Enabled,Enabled,Enabled,Enabled,Enabled,Disabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled"
|
|
rgroup.long 0x78++0x3
|
|
line.long 0x0 "PAR,Parity Address Register"
|
|
hexmask.long.word 0x00 2.--12. 0x4 " PAOFF ,Parity Error Address Offset"
|
|
group.long 0x7C++0x0B
|
|
line.long 0x0 "PPR,Parity Pin Register"
|
|
bitfld.long 0x00 31. " HETPPR[31] ,NHET Parity Pin Select Bit[31]" "Low,High"
|
|
bitfld.long 0x00 30. " [30] ,NHET Parity Pin Select Bit[30]" "Low,High"
|
|
bitfld.long 0x00 29. " [29] ,NHET Parity Pin Select Bit[29]" "Low,High"
|
|
bitfld.long 0x00 28. " [28] ,NHET Parity Pin Select Bit[28]" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 27. " [27] ,NHET Parity Pin Select Bit[27]" "Low,High"
|
|
bitfld.long 0x00 26. " [26] ,NHET Parity Pin Select Bit[26]" "Low,High"
|
|
bitfld.long 0x00 25. " [25] ,NHET Parity Pin Select Bit[25]" "Low,High"
|
|
bitfld.long 0x00 24. " [24] ,NHET Parity Pin Select Bit[24]" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 23. " [23] ,NHET Parity Pin Select Bit[23]" "Low,High"
|
|
bitfld.long 0x00 22. " [22] ,NHET Parity Pin Select Bit[22]" "Low,High"
|
|
bitfld.long 0x00 21. " [21] ,NHET Parity Pin Select Bit[21]" "Low,High"
|
|
bitfld.long 0x00 20. " [20] ,NHET Parity Pin Select Bit[20]" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 19. " [19] ,NHET Parity Pin Select Bit[19]" "Low,High"
|
|
bitfld.long 0x00 18. " [18] ,NHET Parity Pin Select Bit[18]" "Low,High"
|
|
bitfld.long 0x00 17. " [17] ,NHET Parity Pin Select Bit[17]" "Low,High"
|
|
bitfld.long 0x00 16. " [16] ,NHET Parity Pin Select Bit[16]" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 15. " [15] ,NHET Parity Pin Select Bit[15]" "Low,High"
|
|
bitfld.long 0x00 14. " [14] ,NHET Parity Pin Select Bit[14]" "Low,High"
|
|
bitfld.long 0x00 13. " [13] ,NHET Parity Pin Select Bit[13]" "Low,High"
|
|
bitfld.long 0x00 12. " [12] ,NHET Parity Pin Select Bit[12]" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 11. " [11] ,NHET Parity Pin Select Bit[11]" "Low,High"
|
|
bitfld.long 0x00 10. " [10] ,NHET Parity Pin Select Bit[10]" "Low,High"
|
|
bitfld.long 0x00 9. " [9] ,NHET Parity Pin Select Bit[9]" "Low,High"
|
|
bitfld.long 0x00 8. " [8] ,NHET Parity Pin Select Bit[8]" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 7. " [7] ,NHET Parity Pin Select Bit[7]" "Low,High"
|
|
bitfld.long 0x00 6. " [6] ,NHET Parity Pin Select Bit[6]" "Low,High"
|
|
bitfld.long 0x00 5. " [5] ,NHET Parity Pin Select Bit[5]" "Low,High"
|
|
bitfld.long 0x00 4. " [4] ,NHET Parity Pin Select Bit[4]" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 3. " [3] ,NHET Parity Pin Select Bit[3]" "Low,High"
|
|
bitfld.long 0x00 2. " [2] ,NHET Parity Pin Select Bit[2]" "Low,High"
|
|
bitfld.long 0x00 1. " [1] ,NHET Parity Pin Select Bit[1]" "Low,High"
|
|
bitfld.long 0x00 0. " [0] ,NHET Parity Pin Select Bit[0]" "Low,High"
|
|
line.long 0x04 "SFPRLD,Suppresion Filter Preload Register"
|
|
bitfld.long 0x04 16.--17. " CCDIV ,Counter Clock Divider" "VCLK2,VCLK2/2,VCLK2/3,VCLK2/4"
|
|
hexmask.long.word 0x04 0.--9. 1. " CPRLD ,Counter Preload Value"
|
|
line.long 0x08 "SFENA,Suppresion Filter Enable Register"
|
|
bitfld.long 0x08 31. " HETSFENA[31] ,Suppression Filter Enable Bit[31]" "Disabled,Enabled"
|
|
bitfld.long 0x08 30. " [30] ,Suppression Filter Enable Bit[30]" "Disabled,Enabled"
|
|
bitfld.long 0x08 29. " [29] ,Suppression Filter Enable Bit[29]" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x08 28. " [28] ,Suppression Filter Enable Bit[28]" "Disabled,Enabled"
|
|
bitfld.long 0x08 27. " [27] ,Suppression Filter Enable Bit[27]" "Disabled,Enabled"
|
|
bitfld.long 0x08 26. " [26] ,Suppression Filter Enable Bit[26]" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x08 25. " [25] ,Suppression Filter Enable Bit[25]" "Disabled,Enabled"
|
|
bitfld.long 0x08 24. " [24] ,Suppression Filter Enable Bit[24]" "Disabled,Enabled"
|
|
bitfld.long 0x08 23. " [23] ,Suppression Filter Enable Bit[23]" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x08 22. " [22] ,Suppression Filter Enable Bit[22]" "Disabled,Enabled"
|
|
bitfld.long 0x08 21. " [21] ,Suppression Filter Enable Bit[21]" "Disabled,Enabled"
|
|
bitfld.long 0x08 20. " [20] ,Suppression Filter Enable Bit[20]" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x08 19. " [19] ,Suppression Filter Enable Bit[19]" "Disabled,Enabled"
|
|
bitfld.long 0x08 18. " [18] ,Suppression Filter Enable Bit[18]" "Disabled,Enabled"
|
|
bitfld.long 0x08 17. " [17] ,Suppression Filter Enable Bit[17]" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x08 16. " [16] ,Suppression Filter Enable Bit[16]" "Disabled,Enabled"
|
|
bitfld.long 0x08 15. " [15] ,Suppression Filter Enable Bit[15]" "Disabled,Enabled"
|
|
bitfld.long 0x08 14. " [14] ,Suppression Filter Enable Bit[14]" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x08 13. " [13] ,Suppression Filter Enable Bit[13]" "Disabled,Enabled"
|
|
bitfld.long 0x08 12. " [12] ,Suppression Filter Enable Bit[12]" "Disabled,Enabled"
|
|
bitfld.long 0x08 11. " [11] ,Suppression Filter Enable Bit[11]" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x08 10. " [10] ,Suppression Filter Enable Bit[10]" "Disabled,Enabled"
|
|
bitfld.long 0x08 9. " [9] ,Suppression Filter Enable Bit[9]" "Disabled,Enabled"
|
|
bitfld.long 0x08 8. " [8] ,Suppression Filter Enable Bit[8]" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x08 7. " [7] ,Suppression Filter Enable Bit[7]" "Disabled,Enabled"
|
|
bitfld.long 0x08 6. " [6] ,Suppression Filter Enable Bit[6]" "Disabled,Enabled"
|
|
bitfld.long 0x08 5. " [5] ,Suppression Filter Enable Bit[5]" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x08 4. " [4] ,Suppression Filter Enable Bit[4]" "Disabled,Enabled"
|
|
bitfld.long 0x08 3. " [3] ,Suppression Filter Enable Bit[3]" "Disabled,Enabled"
|
|
bitfld.long 0x08 2. " [2] ,Suppression Filter Enable Bit[2]" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x08 1. " [1] ,Suppression Filter Enable Bit[1]" "Disabled,Enabled"
|
|
bitfld.long 0x08 0. " [0] ,Suppression Filter Enable Bit[0]" "Disabled,Enabled"
|
|
sif (cpu()!="RM48L952-PGE"&&cpu()!="RM48L952-ZWT"&&cpu()!="RM48L950-PGE"&&cpu()!="RM48L950-ZWT"&&cpu()!="RM48L940-ZWT"&&cpu()!="RM48L940-PGE"&&cpu()!="RM48L930-ZWT"&&cpu()!="RM48L930-PGE"&&cpu()!="RM48L750-ZWT"&&cpu()!="RM48L750-PGE"&&cpu()!="RM48L740-ZWT"&&cpu()!="RM48L740-PGE"&&cpu()!="RM48L730-ZWT"&&cpu()!="RM48L730-PGE"&&cpu()!="RM48L550-PGE"&&cpu()!="RM48L540-ZWT"&&cpu()!="RM48L540-PGE"&&cpu()!="RM48L530-ZWT"&&cpu()!="RM48L530-PGE"&&cpu()!="RM46L852-PGE"&&cpu()!="RM46L852-ZWT"&&cpu()!="RM46L850-PGE"&&cpu()!="RM46L850-ZWT"&&cpu()!="RM46L840-ZWT"&&cpu()!="RM46L840-PGE"&&cpu()!="RM46L830-ZWT"&&cpu()!="RM46L830-PGE"&&cpu()!="RM46L450-ZWT"&&cpu()!="RM46L450-PGE"&&cpu()!="RM46L440-ZWT"&&cpu()!="RM46L440-PGE"&&cpu()!="RM46L430-ZWT"&&cpu()!="RM46L430-PGE"&&cpu()!="TMS570LC4357"&&cpu()!="RM48L550-ZWT"&&cpu()!="RM42L432"&&!cpuis("TMS570LS0232")&&!cpuis("TMS570LS0714*")&&!cpuis("TMS570LS0914*"))
|
|
if ((per.l(ad:0xFFF7B800+0x90)&0xF00)==0xA00)
|
|
group.long 0x8C++0x3
|
|
line.long 0x0 "LBPSEL,Loop Back Pair Select Register"
|
|
bitfld.long 0x00 31. " LBPTYPE[15] ,Loop Back Pair Type Select Bit[15]" "Digital,Analog"
|
|
bitfld.long 0x00 30. " [14] ,Loop Back Pair Type Select Bit[14]" "Digital,Analog"
|
|
newline
|
|
bitfld.long 0x00 29. " [13] ,Loop Back Pair Type Select Bit[13]" "Digital,Analog"
|
|
bitfld.long 0x00 28. " [12] ,Loop Back Pair Type Select Bit[12]" "Digital,Analog"
|
|
newline
|
|
bitfld.long 0x00 27. " [11] ,Loop Back Pair Type Select Bit[11]" "Digital,Analog"
|
|
bitfld.long 0x00 26. " [10] ,Loop Back Pair Type Select Bit[10]" "Digital,Analog"
|
|
newline
|
|
bitfld.long 0x00 25. " [9] ,Loop Back Pair Type Select Bit[9]" "Digital,Analog"
|
|
bitfld.long 0x00 24. " [8] ,Loop Back Pair Type Select Bit[8]" "Digital,Analog"
|
|
newline
|
|
bitfld.long 0x00 23. " [7] ,Loop Back Pair Type Select Bit[7]" "Digital,Analog"
|
|
bitfld.long 0x00 22. " [6] ,Loop Back Pair Type Select Bit[6]" "Digital,Analog"
|
|
newline
|
|
bitfld.long 0x00 21. " [5] ,Loop Back Pair Type Select Bit[5]" "Digital,Analog"
|
|
bitfld.long 0x00 20. " [4] ,Loop Back Pair Type Select Bit[4]" "Digital,Analog"
|
|
newline
|
|
bitfld.long 0x00 19. " [3] ,Loop Back Pair Type Select Bit[3]" "Digital,Analog"
|
|
bitfld.long 0x00 18. " [2] ,Loop Back Pair Type Select Bit[2]" "Digital,Analog"
|
|
newline
|
|
bitfld.long 0x00 17. " [1] ,Loop Back Pair Type Select Bit[1]" "Digital,Analog"
|
|
bitfld.long 0x00 16. " [0] ,Loop Back Pair Type Select Bit[0]" "Digital,Analog"
|
|
newline
|
|
bitfld.long 0x00 15. " LBPSEL[15] ,Loop Back Pair Select Bit[15]" "Not selected,Selected"
|
|
bitfld.long 0x00 14. " [14] ,Loop Back Pair Select Bit[14]" "Not selected,Selected"
|
|
newline
|
|
bitfld.long 0x00 13. " [13] ,Loop Back Pair Select Bit[13]" "Not selected,Selected"
|
|
bitfld.long 0x00 12. " [12] ,Loop Back Pair Select Bit[12]" "Not selected,Selected"
|
|
newline
|
|
bitfld.long 0x00 11. " [11] ,Loop Back Pair Select Bit[11]" "Not selected,Selected"
|
|
bitfld.long 0x00 10. " [10] ,Loop Back Pair Select Bit[10]" "Not selected,Selected"
|
|
newline
|
|
bitfld.long 0x00 9. " [9] ,Loop Back Pair Select Bit[9]" "Not selected,Selected"
|
|
bitfld.long 0x00 8. " [8] ,Loop Back Pair Select Bit[8]" "Not selected,Selected"
|
|
newline
|
|
bitfld.long 0x00 7. " [7] ,Loop Back Pair Select Bit[7]" "Not selected,Selected"
|
|
bitfld.long 0x00 6. " [6] ,Loop Back Pair Select Bit[6]" "Not selected,Selected"
|
|
newline
|
|
bitfld.long 0x00 5. " [5] ,Loop Back Pair Select Bit[5]" "Not selected,Selected"
|
|
bitfld.long 0x00 4. " [4] ,Loop Back Pair Select Bit[4]" "Not selected,Selected"
|
|
newline
|
|
bitfld.long 0x00 3. " [3] ,Loop Back Pair Select Bit[3]" "Not selected,Selected"
|
|
bitfld.long 0x00 2. " [2] ,Loop Back Pair Select Bit[2]" "Not selected,Selected"
|
|
newline
|
|
bitfld.long 0x00 1. " [1] ,Loop Back Pair Select Bit[1]" "Not selected,Selected"
|
|
bitfld.long 0x00 0. " [0] ,Loop Back Pair Select Bit[0]" "Not selected,Selected"
|
|
else
|
|
hgroup.long 0x8C++0x3
|
|
hide.long 0x0 "LBPSEL,Loop Back Pair Select Register"
|
|
endif
|
|
elif cpuis("TMS570LS0232")||cpuis("TMS570LS0714*")||cpuis("TMS570LS0914*")
|
|
if ((per.l.be(ad:0xFFF7B800+0x90)&0xF0000)==0xA0000)
|
|
group.long 0x8C++0x3
|
|
line.long 0x0 "LBPSEL,Loop Back Pair Select Register"
|
|
bitfld.long 0x00 31. " LBPTYPE[31/30] ,Loop Back Pair Type Select Bits 31/30" "Digital,Analog"
|
|
bitfld.long 0x00 30. " [29/28] ,Loop Back Pair Type Select Bits 29/28" "Digital,Analog"
|
|
newline
|
|
bitfld.long 0x00 29. " [27/26] ,Loop Back Pair Type Select Bits 27/26" "Digital,Analog"
|
|
bitfld.long 0x00 28. " [25/24] ,Loop Back Pair Type Select Bits 25/24" "Digital,Analog"
|
|
newline
|
|
bitfld.long 0x00 27. " [23/22] ,Loop Back Pair Type Select Bits 23/22" "Digital,Analog"
|
|
bitfld.long 0x00 26. " [21/20] ,Loop Back Pair Type Select Bits 21/20" "Digital,Analog"
|
|
newline
|
|
bitfld.long 0x00 25. " [19/18] ,Loop Back Pair Type Select Bits 19/18" "Digital,Analog"
|
|
bitfld.long 0x00 24. " [17/16] ,Loop Back Pair Type Select Bits 17/16" "Digital,Analog"
|
|
newline
|
|
bitfld.long 0x00 23. " [15/14] ,Loop Back Pair Type Select Bits 15/14" "Digital,Analog"
|
|
bitfld.long 0x00 22. " [13/12] ,Loop Back Pair Type Select Bits 13/12" "Digital,Analog"
|
|
newline
|
|
bitfld.long 0x00 21. " [11/10] ,Loop Back Pair Type Select Bits 11/10" "Digital,Analog"
|
|
bitfld.long 0x00 20. " [9/8] ,Loop Back Pair Type Select Bits 9/8" "Digital,Analog"
|
|
newline
|
|
bitfld.long 0x00 19. " [7/6] ,Loop Back Pair Type Select Bits 7/6" "Digital,Analog"
|
|
bitfld.long 0x00 18. " [5/4] ,Loop Back Pair Type Select Bits 5/4" "Digital,Analog"
|
|
newline
|
|
bitfld.long 0x00 17. " [3/2] ,Loop Back Pair Type Select Bits 3/2" "Digital,Analog"
|
|
bitfld.long 0x00 16. " [1/0] ,Loop Back Pair Type Select Bits 1/0" "Digital,Analog"
|
|
newline
|
|
bitfld.long 0x00 15. " LBPSEL31/30] ,Loop Back Pair Select Bits 31/30" "Not selected,Selected"
|
|
bitfld.long 0x00 14. " [29/28] ,Loop Back Pair Select Bits 29/28" "Not selected,Selected"
|
|
newline
|
|
bitfld.long 0x00 13. " [27/26] ,Loop Back Pair Select Bits 27/26" "Not selected,Selected"
|
|
bitfld.long 0x00 12. " [25/24] ,Loop Back Pair Select Bits 25/24" "Not selected,Selected"
|
|
newline
|
|
bitfld.long 0x00 11. " [23/22] ,Loop Back Pair Select Bits 23/22" "Not selected,Selected"
|
|
bitfld.long 0x00 10. " [21/20] ,Loop Back Pair Select Bits 21/20" "Not selected,Selected"
|
|
newline
|
|
bitfld.long 0x00 9. " [19/18] ,Loop Back Pair Select Bits 19/18" "Not selected,Selected"
|
|
bitfld.long 0x00 8. " [17/16] ,Loop Back Pair Select Bits 17/16" "Not selected,Selected"
|
|
newline
|
|
bitfld.long 0x00 7. " [15/14] ,Loop Back Pair Select Bits 15/14" "Not selected,Selected"
|
|
bitfld.long 0x00 6. " [13/12] ,Loop Back Pair Select Bits 13/12" "Not selected,Selected"
|
|
newline
|
|
bitfld.long 0x00 5. " [11/10] ,Loop Back Pair Select Bits 11/10" "Not selected,Selected"
|
|
bitfld.long 0x00 4. " [9/8] ,Loop Back Pair Select Bits 9/8" "Not selected,Selected"
|
|
newline
|
|
bitfld.long 0x00 3. " [7/6] ,Loop Back Pair Select Bits 7/6" "Not selected,Selected"
|
|
bitfld.long 0x00 2. " [5/4] ,Loop Back Pair Select Bits 5/4" "Not selected,Selected"
|
|
newline
|
|
bitfld.long 0x00 1. " [3/2] ,Loop Back Pair Select Bits 3/2" "Not selected,Selected"
|
|
bitfld.long 0x00 0. " [1/0] ,Loop Back Pair Select Bits 1/0" "Not selected,Selected"
|
|
else
|
|
hgroup.long 0x8C++0x3
|
|
hide.long 0x0 "LBPSEL,Loop Back Pair Select Register"
|
|
endif
|
|
else
|
|
if ((per.l(ad:0xFFF7B800+0x90)&0xF0000)==0xA0000)
|
|
group.long 0x8C++0x3
|
|
line.long 0x0 "LBPSEL,Loop Back Pair Select Register"
|
|
bitfld.long 0x00 31. " LBPTYPE[15] ,Loop Back Pair Type Select Bit[15]" "Digital,Analog"
|
|
bitfld.long 0x00 30. " [14] ,Loop Back Pair Type Select Bit[14]" "Digital,Analog"
|
|
newline
|
|
bitfld.long 0x00 29. " [13] ,Loop Back Pair Type Select Bit[13]" "Digital,Analog"
|
|
bitfld.long 0x00 28. " [12] ,Loop Back Pair Type Select Bit[12]" "Digital,Analog"
|
|
newline
|
|
bitfld.long 0x00 27. " [11] ,Loop Back Pair Type Select Bit[11]" "Digital,Analog"
|
|
bitfld.long 0x00 26. " [10] ,Loop Back Pair Type Select Bit[10]" "Digital,Analog"
|
|
newline
|
|
bitfld.long 0x00 25. " [9] ,Loop Back Pair Type Select Bit[9]" "Digital,Analog"
|
|
bitfld.long 0x00 24. " [8] ,Loop Back Pair Type Select Bit[8]" "Digital,Analog"
|
|
newline
|
|
bitfld.long 0x00 23. " [7] ,Loop Back Pair Type Select Bit[7]" "Digital,Analog"
|
|
bitfld.long 0x00 22. " [6] ,Loop Back Pair Type Select Bit[6]" "Digital,Analog"
|
|
newline
|
|
bitfld.long 0x00 21. " [5] ,Loop Back Pair Type Select Bit[5]" "Digital,Analog"
|
|
bitfld.long 0x00 20. " [4] ,Loop Back Pair Type Select Bit[4]" "Digital,Analog"
|
|
newline
|
|
bitfld.long 0x00 19. " [3] ,Loop Back Pair Type Select Bit[3]" "Digital,Analog"
|
|
bitfld.long 0x00 18. " [2] ,Loop Back Pair Type Select Bit[2]" "Digital,Analog"
|
|
newline
|
|
bitfld.long 0x00 17. " [1] ,Loop Back Pair Type Select Bit[1]" "Digital,Analog"
|
|
bitfld.long 0x00 16. " [0] ,Loop Back Pair Type Select Bit[0]" "Digital,Analog"
|
|
newline
|
|
bitfld.long 0x00 15. " LBPSEL[15] ,Loop Back Pair Select Bit[15]" "Not selected,Selected"
|
|
bitfld.long 0x00 14. " [14] ,Loop Back Pair Select Bit[14]" "Not selected,Selected"
|
|
newline
|
|
bitfld.long 0x00 13. " [13] ,Loop Back Pair Select Bit[13]" "Not selected,Selected"
|
|
bitfld.long 0x00 12. " [12] ,Loop Back Pair Select Bit[12]" "Not selected,Selected"
|
|
newline
|
|
bitfld.long 0x00 11. " [11] ,Loop Back Pair Select Bit[11]" "Not selected,Selected"
|
|
bitfld.long 0x00 10. " [10] ,Loop Back Pair Select Bit[10]" "Not selected,Selected"
|
|
newline
|
|
bitfld.long 0x00 9. " [9] ,Loop Back Pair Select Bit[9]" "Not selected,Selected"
|
|
bitfld.long 0x00 8. " [8] ,Loop Back Pair Select Bit[8]" "Not selected,Selected"
|
|
newline
|
|
bitfld.long 0x00 7. " [7] ,Loop Back Pair Select Bit[7]" "Not selected,Selected"
|
|
bitfld.long 0x00 6. " [6] ,Loop Back Pair Select Bit[6]" "Not selected,Selected"
|
|
newline
|
|
bitfld.long 0x00 5. " [5] ,Loop Back Pair Select Bit[5]" "Not selected,Selected"
|
|
bitfld.long 0x00 4. " [4] ,Loop Back Pair Select Bit[4]" "Not selected,Selected"
|
|
newline
|
|
bitfld.long 0x00 3. " [3] ,Loop Back Pair Select Bit[3]" "Not selected,Selected"
|
|
bitfld.long 0x00 2. " [2] ,Loop Back Pair Select Bit[2]" "Not selected,Selected"
|
|
newline
|
|
bitfld.long 0x00 1. " [1] ,Loop Back Pair Select Bit[1]" "Not selected,Selected"
|
|
bitfld.long 0x00 0. " [0] ,Loop Back Pair Select Bit[0]" "Not selected,Selected"
|
|
else
|
|
hgroup.long 0x8C++0x3
|
|
hide.long 0x0 "LBPSEL,Loop Back Pair Select Register"
|
|
endif
|
|
endif
|
|
group.long 0x90++0x07
|
|
line.long 0x00 "LBPDIR,Loop Back Pair Direction Register"
|
|
bitfld.long 0x00 16.--19. " IODFTENA ,Module IODFT Enable Key" "Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Enabled,Disabled,Disabled,Disabled,Disabled,Disabled"
|
|
bitfld.long 0x00 15. " LBPDIR[15] ,Loop Back Pair Direction Bit[15]" "Input,Output"
|
|
bitfld.long 0x00 14. " [14] ,Loop Back Pair Direction Bit[14]" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 13. " [13] ,Loop Back Pair Direction Bit[13]" "Input,Output"
|
|
bitfld.long 0x00 12. " [12] ,Loop Back Pair Direction Bit[12]" "Input,Output"
|
|
bitfld.long 0x00 11. " [11] ,Loop Back Pair Direction Bit[11]" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 10. " [10] ,Loop Back Pair Direction Bit[10]" "Input,Output"
|
|
bitfld.long 0x00 9. " [9] ,Loop Back Pair Direction Bit[9]" "Input,Output"
|
|
bitfld.long 0x00 8. " [8] ,Loop Back Pair Direction Bit[8]" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 7. " [7] ,Loop Back Pair Direction Bit[7]" "Input,Output"
|
|
bitfld.long 0x00 6. " [6] ,Loop Back Pair Direction Bit[6]" "Input,Output"
|
|
bitfld.long 0x00 5. " [5] ,Loop Back Pair Direction Bit[5]" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 4. " [4] ,Loop Back Pair Direction Bit[4]" "Input,Output"
|
|
bitfld.long 0x00 3. " [3] ,Loop Back Pair Direction Bit[3]" "Input,Output"
|
|
bitfld.long 0x00 2. " [2] ,Loop Back Pair Direction Bit[2]" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 1. " [1] ,Loop Back Pair Direction Bit[1]" "Input,Output"
|
|
bitfld.long 0x00 0. " [0] ,Loop Back Pair Direction Bit[0]" "Input,Output"
|
|
line.long 0x04 "PINDIS,Pin Disable Register"
|
|
bitfld.long 0x04 31. " HETPINDIS[31] ,NHET Pin Disable Bit[31]" "No,Yes"
|
|
bitfld.long 0x04 30. " [30] ,NHET Pin Disable Bit[30]" "No,Yes"
|
|
bitfld.long 0x04 29. " [29] ,NHET Pin Disable Bit[29]" "No,Yes"
|
|
newline
|
|
bitfld.long 0x04 28. " [28] ,NHET Pin Disable Bit[28]" "No,Yes"
|
|
bitfld.long 0x04 27. " [27] ,NHET Pin Disable Bit[27]" "No,Yes"
|
|
bitfld.long 0x04 26. " [26] ,NHET Pin Disable Bit[26]" "No,Yes"
|
|
newline
|
|
bitfld.long 0x04 25. " [25] ,NHET Pin Disable Bit[25]" "No,Yes"
|
|
bitfld.long 0x04 24. " [24] ,NHET Pin Disable Bit[24]" "No,Yes"
|
|
bitfld.long 0x04 23. " [23] ,NHET Pin Disable Bit[23]" "No,Yes"
|
|
newline
|
|
bitfld.long 0x04 22. " [22] ,NHET Pin Disable Bit[22]" "No,Yes"
|
|
bitfld.long 0x04 21. " [21] ,NHET Pin Disable Bit[21]" "No,Yes"
|
|
bitfld.long 0x04 20. " [20] ,NHET Pin Disable Bit[20]" "No,Yes"
|
|
newline
|
|
bitfld.long 0x04 19. " [19] ,NHET Pin Disable Bit[19]" "No,Yes"
|
|
bitfld.long 0x04 18. " [18] ,NHET Pin Disable Bit[18]" "No,Yes"
|
|
bitfld.long 0x04 17. " [17] ,NHET Pin Disable Bit[17]" "No,Yes"
|
|
newline
|
|
bitfld.long 0x04 16. " [16] ,NHET Pin Disable Bit[16]" "No,Yes"
|
|
bitfld.long 0x04 15. " [15] ,NHET Pin Disable Bit[15]" "No,Yes"
|
|
bitfld.long 0x04 14. " [14] ,NHET Pin Disable Bit[14]" "No,Yes"
|
|
newline
|
|
bitfld.long 0x04 13. " [13] ,NHET Pin Disable Bit[13]" "No,Yes"
|
|
bitfld.long 0x04 12. " [12] ,NHET Pin Disable Bit[12]" "No,Yes"
|
|
bitfld.long 0x04 11. " [11] ,NHET Pin Disable Bit[11]" "No,Yes"
|
|
newline
|
|
bitfld.long 0x04 10. " [10] ,NHET Pin Disable Bit[10]" "No,Yes"
|
|
bitfld.long 0x04 9. " [9] ,NHET Pin Disable Bit[9]" "No,Yes"
|
|
bitfld.long 0x04 8. " [8] ,NHET Pin Disable Bit[8]" "No,Yes"
|
|
newline
|
|
bitfld.long 0x04 7. " [7] ,NHET Pin Disable Bit[7]" "No,Yes"
|
|
bitfld.long 0x04 6. " [6] ,NHET Pin Disable Bit[6]" "No,Yes"
|
|
bitfld.long 0x04 5. " [5] ,NHET Pin Disable Bit[5]" "No,Yes"
|
|
newline
|
|
bitfld.long 0x04 4. " [4] ,NHET Pin Disable Bit[4]" "No,Yes"
|
|
bitfld.long 0x04 3. " [3] ,NHET Pin Disable Bit[3]" "No,Yes"
|
|
bitfld.long 0x04 2. " [2] ,NHET Pin Disable Bit[2]" "No,Yes"
|
|
newline
|
|
bitfld.long 0x04 1. " [1] ,NHET Pin Disable Bit[1]" "No,Yes"
|
|
bitfld.long 0x04 0. " [0] ,NHET Pin Disable Bit[0]" "No,Yes"
|
|
sif cpuis("TMS570LS0714*")||cpuis("TMS570LS0914*")
|
|
width 16.
|
|
group.long 0x9C++0x13 "HWAG Registers"
|
|
line.long 0x00 "HWAPINSEL,HWAG Pin Select Register"
|
|
bitfld.long 0x00 0.--4. " PINSEL ,HWAG pin select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
line.long 0x04 "HWAGCR0,HWAG Control Register 0"
|
|
bitfld.long 0x04 0. " RESET ,HWAG module reset" "Reset,No reset"
|
|
line.long 0x08 "HWAGCR1,HWAG Control Register 1"
|
|
bitfld.long 0x08 0. " PPWN ,HWAG module power down" "Powered up,Powered down"
|
|
line.long 0x0C "HWAGCR2,HWAG Control Register 2"
|
|
bitfld.long 0x0C 24. " ARST ,Angle reset" "No reset,Reset"
|
|
bitfld.long 0x0C 17. " TED ,Tooth edge" "Falling,Rising"
|
|
bitfld.long 0x0C 16. " CRI ,Criteria enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x0C 8. " FIL ,Input filter enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 0. " STRT ,Put the HWAG into run time start bit" "Stopped,Started"
|
|
line.long 0x10 "HWAENA_SET/CLR,HWAG Interrupt Enable Set/Clear Register"
|
|
setclrfld.long 0x10 7. 0x10 7. 0x14 7. " INTENA[7] ,Enable interrupt [7]" "Disabled,Enabled"
|
|
setclrfld.long 0x10 6. 0x10 6. 0x14 6. " [6] ,Enable interrupt [6]" "Disabled,Enabled"
|
|
setclrfld.long 0x10 5. 0x10 5. 0x14 5. " [5] ,Enable interrupt [5]" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x10 4. 0x10 4. 0x14 4. " [4] ,Enable interrupt [4]" "Disabled,Enabled"
|
|
setclrfld.long 0x10 3. 0x10 3. 0x14 3. " [3] ,Enable interrupt [3]" "Disabled,Enabled"
|
|
setclrfld.long 0x10 2. 0x10 2. 0x14 2. " [2] ,Enable interrupt [2]" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x10 1. 0x10 1. 0x14 1. " [1] ,Enable interrupt [1]" "Disabled,Enabled"
|
|
setclrfld.long 0x10 0. 0x10 0. 0x14 0. " [0] ,Enable interrupt [0]" "Disabled,Enabled"
|
|
group.long 0xB0++0x03
|
|
line.long 0x00 "HWALVL_SET/CLR,HWAG Interrupt Priority Set Register"
|
|
setclrfld.long 0x00 7. 0x00 7. 0x04 7. " LVLSET[7] ,Set interrupt [7] priority level" "Low,High"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x04 6. " [6] ,Set interrupt [6] priority level" "Low,High"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x04 5. " [5] ,Set interrupt [5] priority level" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 4. 0x00 4. 0x04 4. " [4] ,Set interrupt [4] priority level" "Low,High"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x04 3. " [3] ,Set interrupt [3] priority level" "Low,High"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x04 2. " [2] ,Set interrupt [2] priority level" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 1. 0x00 1. 0x04 1. " [1] ,Set interrupt [1] priority level" "Low,High"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x04 0. " [0] ,Set interrupt [0] priority level" "Low,High"
|
|
group.long 0xB8++0x27
|
|
line.long 0x00 "HWAFLG,HWAG Interrupt Flags Register"
|
|
eventfld.long 0x00 7. " INTFLG[7] ,Interrupt 7 flag" "No effect,Pending"
|
|
eventfld.long 0x00 6. " [6] ,Interrupt 6 flag" "No effect,Pending"
|
|
eventfld.long 0x00 5. " [5] ,Interrupt 5 flag" "No effect,Pending"
|
|
newline
|
|
eventfld.long 0x00 4. " [4] ,Interrupt 4 flag" "No effect,Pending"
|
|
eventfld.long 0x00 3. " [3] ,Interrupt 3 flag" "No effect,Pending"
|
|
eventfld.long 0x00 2. " [2] ,Interrupt 2 flag" "No effect,Pending"
|
|
newline
|
|
eventfld.long 0x00 1. " [1] ,Interrupt 1 flag" "No effect,Pending"
|
|
eventfld.long 0x00 0. " [0] ,Interrupt 0 flag" "No effect,Pending"
|
|
line.long 0x04 "HWAOFF0,HWAG Interrupt Offset Register 0"
|
|
hexmask.long.byte 0x04 0.--7. 0x01 " OFFSET1 ,High-priority interrupt offset"
|
|
line.long 0x08 "HWAOFF1,HWAG Interrupt Offset Register 1"
|
|
hexmask.long.byte 0x08 0.--7. 0x01 " OFFSET2 ,Low-priority interrupt offset"
|
|
line.long 0x0C "HWAACNT,HWAG ACNT Register, HWAG Angle Value"
|
|
hexmask.long.tbyte 0x0C 0.--23. 1. " ACNT ,Angle value"
|
|
line.long 0x10 "HWAPCNT1,HWAG PCNT (n-1) Register, HWAG Previous Tooth Period"
|
|
hexmask.long.tbyte 0x10 0.--23. 1. " PCNT(N-1) ,Period (n-1) value"
|
|
line.long 0x14 "HWAPCNT,HWAG PCNT (n) Register, HWAG Current Tooth Period"
|
|
hexmask.long.tbyte 0x14 0.--23. 1. " PCNT(N) ,Period (n) value"
|
|
line.long 0x18 "HWASTWD,HWAG Step Register"
|
|
bitfld.long 0x18 0.--3. " STWD ,Step width (ticks per period)" "4,8,16,32,64,128,256,512,1024,2048,4096,8192,16384,32768,65536,131072"
|
|
line.long 0x1C "HWATHNB,HWAG Teeth Number Register"
|
|
hexmask.long.byte 0x1C 0.--7. 1. " THNB ,Teeth number"
|
|
line.long 0x20 "HWATHVL,HHWAG Current Teeth Number Register"
|
|
hexmask.long.byte 0x20 0.--7. 1. " THVL ,Teeth value"
|
|
line.long 0x24 "HWAFIL,HWAG Filter Register"
|
|
hexmask.long.word 0x24 0.--9. 1. " FIL1 ,Filter value 1"
|
|
group.long 0xE8++0x07
|
|
line.long 0x00 "HWAFIL2,HWAG Filter Register 2, HWAG Tick Counter Compare Value During Singularity Tooth"
|
|
hexmask.long.word 0x00 0.--11. 1. " FIL2 ,Filter value 2"
|
|
line.long 0x04 "HWAANGI,HWAG Angle Increment Register"
|
|
hexmask.long.word 0x04 0.--9. 1. " ANGI ,Angle increment value"
|
|
elif (cpu()==("TMS570LS2126")||cpu()==("TMS570LS2127")||cpu()==("TMS570LS2136")||cpu()==("TMS570LS2137")||cpu()==("TMS570LS2125-PGE")||cpu()==("TMS570LS2125-ZWT")||cpu()==("TMS570LS2135-PGE")||cpu()==("TMS570LS2135-ZWT")||cpu()==("TMS570LS2124-PGE")||cpu()==("TMS570LS2124-ZWT")||cpu()==("TMS570LS2134-PGE")||cpu()==("TMS570LS2134-ZWT")||cpu()==("TMS570LS3134-PGE")||cpu()==("TMS570LS3134-ZWT")||cpu()==("TMS570LS3135-PGE")||cpu()==("TMS570LS3135-ZWT")||cpu()==("TMS570LS3136")||cpu()==("TMS570LS3137-PGE")||cpu()==("TMS570LS3137-ZWT")||cpu()==("TMS570LS30336")||cpuis("RM48L950*"))
|
|
group.long 0xA0++0x43
|
|
line.long 0x00 "HWAGCR0,HWAG Control Register 0"
|
|
line.long 0x04 "HWAGCR1,HWAG Control Register 1"
|
|
line.long 0x08 "HWAGCR2,HWAG Control Register 2"
|
|
line.long 0x0C "HWAENASET,HWAG Interrupt Enable Set Register"
|
|
line.long 0x10 "HWAENACLR,HWAG Interrupt Enable Clear Register"
|
|
line.long 0x14 "HWALVLSET,HWAG Interrupt Priority Set Register"
|
|
line.long 0x18 "HWALVLCLR,HWAG Interrupt Priority Clear Register"
|
|
line.long 0x1C "HWAFLG,HWAG Interrupt Flags Register"
|
|
line.long 0x20 "HWAOFF0,HWAG Interrupt Offset Register 1, HWAG Low Priority Interrupt Offset"
|
|
line.long 0x24 "HWAOFF1,HWAG Interrupt Offset Register 2, HWAG High Priority Interrupt Offset"
|
|
line.long 0x28 "HWAACNT,HWAG ACNT Register, HWAG Angle Value"
|
|
line.long 0x2C "HWAPCNT1,HWAG PCNT (n-1) Register, HWAG Previous Tooth Period"
|
|
line.long 0x30 "HWAPCNT,HWAG PCNT (n) Register, HWAG Current Tooth Period"
|
|
line.long 0x34 "HWASTWD,HWAG Step Register"
|
|
line.long 0x38 "HWATHNB,HWAG Teeth Number Register"
|
|
line.long 0x3C "HWATHVL,HHWAG Current Teeth Number Register"
|
|
line.long 0x40 "HWAFIL,HWAG Filter Register, HWAG Tick Counter Compare Value"
|
|
group.long 0xE8++0x07
|
|
line.long 0x00 "HWAFIL2,HWAG Filter Register 2, HWAG Tick Counter Compare Value During Singularity Tooth"
|
|
line.long 0x04 "HWAANGI,HWAG Angle Increment Register"
|
|
endif
|
|
sif cpuis("TMS570LS0232")||cpuis("TMS570LS0714*")||cpuis("TMS570LS0914*")
|
|
endian.le
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
endif
|
|
sif cpuis("TMS570LS0714*")||cpuis("TMS570LS0914*")
|
|
tree.open "HTU (High-End Timer Transfer Unit Module)"
|
|
tree "HTU1"
|
|
base ad:0xFFF7A400
|
|
sif cpuis("TMS570LS0232")||cpuis("TMS570LS0714*")||cpuis("TMS570LS0914*")
|
|
endian.be
|
|
endif
|
|
width 10.
|
|
group.long 0x00++0x07
|
|
line.long 0x00 "GC,Global Control Register"
|
|
bitfld.long 0x00 24. " VBUS_HOLD ,Hold the VBUS bus" "Not held,Held"
|
|
bitfld.long 0x00 16. " HTUEN ,Transfer unit enable bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " DEBM ,Debug mode" "Suspended,Continue"
|
|
newline
|
|
bitfld.long 0x00 0. " HTU_RES ,HTU software reset" "No reset,Reset"
|
|
line.long 0x04 "CPENA,Control Packet Enable Register"
|
|
bitfld.long 0x04 14.--15. " CPENA7 ,CP enable bits 7 (CP B/CP A)" "Disabled,Disabled/Enabled,Enabled/Disabled,Disabled"
|
|
bitfld.long 0x04 12.--13. " CPENA6 ,CP enable bits 6 (CP B/CP A)" "Disabled,Disabled/Enabled,Enabled/Disabled,Disabled"
|
|
newline
|
|
bitfld.long 0x04 10.--11. " CPENA5 ,CP enable bits 5 (CP B/CP A)" "Disabled,Disabled/Enabled,Enabled/Disabled,Disabled"
|
|
bitfld.long 0x04 8.--9. " CPENA4 ,CP enable bits 4 (CP B/CP A)" "Disabled,Disabled/Enabled,Enabled/Disabled,Disabled"
|
|
newline
|
|
bitfld.long 0x04 6.--7. " CPENA3 ,CP enable bits 3 (CP B/CP A)" "Disabled,Disabled/Enabled,Enabled/Disabled,Disabled"
|
|
bitfld.long 0x04 4.--5. " CPENA2 ,CP enable bits 2 (CP B/CP A)" "Disabled,Disabled/Enabled,Enabled/Disabled,Disabled"
|
|
newline
|
|
bitfld.long 0x04 2.--3. " CPENA1 ,CP enable bits 1 (CP B/CP A)" "Disabled,Disabled/Enabled,Enabled/Disabled,Disabled"
|
|
bitfld.long 0x04 0.--1. " CPENA0 ,CP enable bits 0 (CP B/CP A)" "Disabled,Disabled/Enabled,Enabled/Disabled,Disabled"
|
|
group.long 0x8++0x03
|
|
line.long 0x00 "BUSY0,Control Packet (CP) Busy Register 0"
|
|
eventfld.long 0x00 24. " BUSY0A ,Busy flag for CP A of double CP 0" "Low,High"
|
|
eventfld.long 0x00 16. " BUSY0B ,Busy flag for CP B of double CP 0" "Low,High"
|
|
eventfld.long 0x00 8. " BUSY1A ,Busy flag for CP A of double CP 1" "Low,High"
|
|
eventfld.long 0x00 0. " BUSY1B ,Busy flag for CP B of double CP 1" "Low,High"
|
|
group.long 0xC++0x03
|
|
line.long 0x00 "BUSY1,Control Packet (CP) Busy Register 1"
|
|
eventfld.long 0x00 24. " BUSY2A ,Busy flag for CP A of double CP 2" "Low,High"
|
|
eventfld.long 0x00 16. " BUSY2B ,Busy flag for CP B of double CP 2" "Low,High"
|
|
eventfld.long 0x00 8. " BUSY3A ,Busy flag for CP A of double CP 3" "Low,High"
|
|
eventfld.long 0x00 0. " BUSY3B ,Busy flag for CP B of double CP 3" "Low,High"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "BUSY2,Control Packet (CP) Busy Register 2"
|
|
eventfld.long 0x00 24. " BUSY4A ,Busy flag for CP A of double CP 4" "Low,High"
|
|
eventfld.long 0x00 16. " BUSY4B ,Busy flag for CP B of double CP 4" "Low,High"
|
|
eventfld.long 0x00 8. " BUSY5A ,Busy flag for CP A of double CP 5" "Low,High"
|
|
eventfld.long 0x00 0. " BUSY5B ,Busy flag for CP B of double CP 5" "Low,High"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "BUSY3,Control Packet (CP) Busy Register 3"
|
|
eventfld.long 0x00 24. " BUSY6A ,Busy flag for CP A of double CP 6" "Low,High"
|
|
eventfld.long 0x00 16. " BUSY6B ,Busy flag for CP B of double CP 6" "Low,High"
|
|
eventfld.long 0x00 8. " BUSY7A ,Busy flag for CP A of double CP 7" "Low,High"
|
|
eventfld.long 0x00 0. " BUSY7B ,Busy flag for CP B of double CP 7" "Low,High"
|
|
sif cpuis("TMS570LS0232")||cpuis("TMS570LS0714*")||cpuis("TMS570LS0914*")||cpuis("TMS570LS3137-EP")
|
|
group.long 0x18++0x3
|
|
line.long 0x00 "ACPE,Active Control Packet Register"
|
|
eventfld.long 0x00 31. " ERRF ,Error flag" "No error,Error"
|
|
rbitfld.long 0x00 24.--28. " ERRETC ,Error element transfer counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
rbitfld.long 0x00 16.--19. " ERRCPN ,Error control packet number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rbitfld.long 0x00 15. " TIPF ,Transfer in progress flag" "Not active,Active"
|
|
newline
|
|
rbitfld.long 0x00 14. " BUS_BUSY ,VBUSP bus is busy" "Not busy,Busy"
|
|
rbitfld.long 0x00 8.--12. " CETCOUNT ,Current element transfer counter" "No transfer,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
rbitfld.long 0x00 0.--3. " NACP ,Number of active control packet" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
else
|
|
group.long 0x18++0x3
|
|
line.long 0x00 "ACPE,Active Control Packet Register"
|
|
eventfld.long 0x00 31. " ERRF ,Error flag" "No error,Error"
|
|
bitfld.long 0x00 24.--28. " ERRETC ,Error element transfer counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
hexmask.long.byte 0x00 16.--19. 1. " ERRCPN ,Error control packet number"
|
|
bitfld.long 0x00 15. " TIPF ,Transfer in progress flag" "Not active,Active"
|
|
newline
|
|
bitfld.long 0x00 14. " BUS_BUSY ,VBUSP bus is busy" "Not busy,Busy"
|
|
bitfld.long 0x00 8.--12. " CETCOUNT ,Current element transfer counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
hexmask.long.byte 0x00 0.--3. 1. " NACP ,Number of active control packet"
|
|
endif
|
|
newline
|
|
width 16.
|
|
group.long 0x20++0x07
|
|
line.long 0x00 "RLBECTRL,Request Lost and Bus Error Control Register"
|
|
bitfld.long 0x00 16. " BERINTENA ,Bus error interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " CORL ,Continue on request lost error" "Lost,Continue"
|
|
bitfld.long 0x00 0. " RLINTENA ,Request lost interrupt enable bit" "Disabled,Enabled"
|
|
line.long 0x04 "BFINTS_SET/CLR,Buffer Full Interrupt Enable Set/Clr Register"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x08 15. " BFINTENA[15] ,CP B Buffer full interrupt enable bit 15" "Disabled,Enabled"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x08 14. " [14] ,CP A Buffer full interrupt enable Bit 14" "Disabled,Enabled"
|
|
setclrfld.long 0x04 13. 0x04 13. 0x08 13. " [13] ,CP B Bit 13" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x04 12. 0x04 12. 0x08 12. " [12] ,CP A Buffer Full Interrupt Enable Bit 12" "Disabled,Enabled"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x08 11. " [11] ,CP B buffer full interrupt enable bit 11" "Disabled,Enabled"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x08 10. " [10] ,CP A buffer full interrupt enable bit 10" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x04 9. 0x04 9. 0x08 9. " [9] ,CP B buffer full interrupt enable bit 9" "Disabled,Enabled"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x08 8. " [8] ,CP A buffer full interrupt enable bit 8" "Disabled,Enabled"
|
|
setclrfld.long 0x04 7. 0x04 7. 0x08 7. " [7] ,CP B buffer full interrupt enable bit 7" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x04 6. 0x04 6. 0x08 6. " [6] ,CP A buffer full interrupt enable bit 6" "Disabled,Enabled"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x08 5. " [5] ,CP B buffer full interrupt enable bit 5" "Disabled,Enabled"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x08 4. " [4] ,CP A buffer full interrupt enable bit 4" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x04 3. 0x04 3. 0x08 3. " [3] ,CP B buffer full interrupt enable bit 3" "Disabled,Enabled"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x08 2. " [2] ,CP A buffer full interrupt enable bit 2" "Disabled,Enabled"
|
|
setclrfld.long 0x04 1. 0x04 1. 0x08 1. " [1] ,CP B buffer full interrupt enable bit 1" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x04 0. 0x04 0. 0x08 0. " [0] ,CP A buffer full interrupt enable bit 0" "Disabled,Enabled"
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "INTMAP,Interrupt Mapping Register"
|
|
bitfld.long 0x00 16. " MAPSEL ,Interrupt mapping select bit" "Low,High"
|
|
bitfld.long 0x00 15. " CPINTMAP[15] ,CP B Interrupt mapping bit 15" "Line 0,Line 1"
|
|
bitfld.long 0x00 14. " [14] ,CP A Interrupt mapping bit 14" "Line 0,Line 1"
|
|
newline
|
|
bitfld.long 0x00 13. " [13] ,CP B Interrupt mapping bit 13" "Line 0,Line 1"
|
|
bitfld.long 0x00 12. " [12] ,CP A Interrupt mapping bit 12" "Line 0,Line 1"
|
|
bitfld.long 0x00 11. " [11] ,CP B Interrupt mapping bit 11" "Line 0,Line 1"
|
|
newline
|
|
bitfld.long 0x00 10. " [10] ,CP A Interrupt mapping bit 10" "Line 0,Line 1"
|
|
bitfld.long 0x00 9. " [9] ,CP B Interrupt mapping bit 9" "Line 0,Line 1"
|
|
bitfld.long 0x00 8. " [8] ,CP A Interrupt mapping bit 8" "Line 0,Line 1"
|
|
newline
|
|
bitfld.long 0x00 7. " [7] ,CP B Interrupt mapping bit 7" "Line 0,Line 1"
|
|
bitfld.long 0x00 6. " [6] ,CP A Interrupt mapping bit 6" "Line 0,Line 1"
|
|
bitfld.long 0x00 5. " [5] ,CP B Interrupt mapping bit 5" "Line 0,Line 1"
|
|
newline
|
|
bitfld.long 0x00 4. " [4] ,CP A Interrupt mapping bit 4" "Line 0,Line 1"
|
|
bitfld.long 0x00 3. " [3] ,CP B Interrupt mapping bit 3" "Line 0,Line 1"
|
|
bitfld.long 0x00 2. " [2] ,CP A Interrupt mapping bit 2" "Line 0,Line 1"
|
|
newline
|
|
bitfld.long 0x00 1. " [1] ,CP B Interrupt mapping bit 1" "Line 0,Line 1"
|
|
bitfld.long 0x00 0. " [0] ,CP A Interrupt mapping bit 0" "Line 0,Line 1"
|
|
newline
|
|
width 10.
|
|
hgroup.long 0x34++0x3
|
|
hide.long 0x0 "INTOFF0,Interrupt Offset Register 0"
|
|
in
|
|
hgroup.long 0x38++0x3
|
|
hide.long 0x0 "INTOFF1,Interrupt Offset Register 1"
|
|
in
|
|
newline
|
|
group.long 0x3C++0x23
|
|
line.long 0x00 "BIM,Buffer Initialization Mode Register"
|
|
bitfld.long 0x00 7. " BIM[7] ,Buffer initialization mode bit 7" "Normal,Special"
|
|
bitfld.long 0x00 6. " BIM[6] ,Buffer initialization mode bit 6" "Normal,Special"
|
|
bitfld.long 0x00 5. " BIM[5] ,Buffer initialization mode bit 5" "Normal,Special"
|
|
bitfld.long 0x00 4. " BIM[4] ,Buffer initialization mode bit 4" "Normal,Special"
|
|
newline
|
|
bitfld.long 0x00 3. " BIM[3] ,Buffer initialization mode bit 3" "Normal,Special"
|
|
bitfld.long 0x00 2. " BIM[2] ,Buffer initialization mode bit 2" "Normal,Special"
|
|
bitfld.long 0x00 1. " BIM[1] ,Buffer initialization mode bit 1" "Normal,Special"
|
|
bitfld.long 0x00 0. " BIM[0] ,Buffer initialization mode bit 0" "Normal,Special"
|
|
line.long 0x04 "RLOSTFL,Request Lost Flag Register"
|
|
eventfld.long 0x04 15. " CPRLFL[15] ,CP B request lost flag 15" "Not requested,Requested"
|
|
eventfld.long 0x04 14. " CPRLFL[14] ,CP A request lost flag 14" "Not requested,Requested"
|
|
newline
|
|
eventfld.long 0x04 13. " CPRLFL[13] ,CP B request lost flag 13" "Not requested,Requested"
|
|
eventfld.long 0x04 12. " CPRLFL[12] ,CP A request lost flag 12" "Not requested,Requested"
|
|
newline
|
|
eventfld.long 0x04 11. " CPRLFL[11] ,CP B request lost flag 11" "Not requested,Requested"
|
|
eventfld.long 0x04 10. " CPRLFL[10] ,CP A request lost flag 10" "Not requested,Requested"
|
|
newline
|
|
eventfld.long 0x04 9. " CPRLFL[9] ,CP B request lost flag 9" "Not requested,Requested"
|
|
eventfld.long 0x04 8. " CPRLFL[8] ,CP A request lost flag 8" "Not requested,Requested"
|
|
newline
|
|
eventfld.long 0x04 7. " CPRLFL[7] ,CP B request lost flag 7" "Not requested,Requested"
|
|
eventfld.long 0x04 6. " CPRLFL[6] ,CP A request lost flag 6" "Not requested,Requested"
|
|
newline
|
|
eventfld.long 0x04 5. " CPRLFL[5] ,CP B request lost flag 5" "Not requested,Requested"
|
|
eventfld.long 0x04 4. " CPRLFL[4] ,CP A request lost flag 4" "Not requested,Requested"
|
|
newline
|
|
eventfld.long 0x04 3. " CPRLFL[3] ,CP B request lost flag 3" "Not requested,Requested"
|
|
eventfld.long 0x04 2. " CPRLFL[2] ,CP A request lost flag 2" "Not requested,Requested"
|
|
newline
|
|
eventfld.long 0x04 1. " CPRLFL[1] ,CP B request lost flag 1" "Not requested,Requested"
|
|
eventfld.long 0x04 0. " CPRLFL[0] ,CP A request lost flag 0" "Not requested,Requested"
|
|
line.long 0x08 "BFINTFL,Buffer Full Interrupt Flag Register"
|
|
eventfld.long 0x08 15. " BFINTFL[15] ,CP B buffer full interrupt flag 15" "No interrupt,Interrupt"
|
|
eventfld.long 0x08 14. " BFINTFL[14] ,CP A buffer full interrupt flag 14" "No interrupt,Interrupt"
|
|
newline
|
|
eventfld.long 0x08 13. " BFINTFL[13] ,CP B buffer full interrupt flag 13" "No interrupt,Interrupt"
|
|
eventfld.long 0x08 12. " BFINTFL[12] ,CP A buffer full interrupt flag 12" "No interrupt,Interrupt"
|
|
newline
|
|
eventfld.long 0x08 11. " BFINTFL[11] ,CP B buffer full interrupt flag 11" "No interrupt,Interrupt"
|
|
eventfld.long 0x08 10. " BFINTFL[10] ,CP A buffer full interrupt flag 10" "No interrupt,Interrupt"
|
|
newline
|
|
eventfld.long 0x08 9. " BFINTFL[9] ,CP B buffer full interrupt flag 9" "No interrupt,Interrupt"
|
|
eventfld.long 0x08 8. " BFINTFL[8] ,CP A buffer full interrupt flag 8" "No interrupt,Interrupt"
|
|
newline
|
|
eventfld.long 0x08 7. " BFINTFL[7] ,CP B buffer full interrupt flag 7" "No interrupt,Interrupt"
|
|
eventfld.long 0x08 6. " BFINTFL[6] ,CP A buffer full interrupt flag 6" "No interrupt,Interrupt"
|
|
newline
|
|
eventfld.long 0x08 5. " BFINTFL[5] ,CP B buffer full interrupt flag 5" "No interrupt,Interrupt"
|
|
eventfld.long 0x08 4. " BFINTFL[4] ,CP A buffer full interrupt flag 4" "No interrupt,Interrupt"
|
|
newline
|
|
eventfld.long 0x08 3. " BFINTFL[3] ,CP B buffer full interrupt flag 3" "No interrupt,Interrupt"
|
|
eventfld.long 0x08 2. " BFINTFL[2] ,CP A buffer full interrupt flag 2" "No interrupt,Interrupt"
|
|
newline
|
|
eventfld.long 0x08 1. " BFINTFL[1] ,CP B buffer full interrupt flag 1" "No interrupt,Interrupt"
|
|
eventfld.long 0x08 0. " BFINTFL[0] ,CP A buffer full interrupt flag 0" "No interrupt,Interrupt"
|
|
line.long 0x0C "BERINTFL,BER Interrupt Flag Register"
|
|
eventfld.long 0x0C 15. " BERINTFL[15] ,CP B bus error interrupt flag 15" "No interrupt,Interrupt"
|
|
eventfld.long 0x0C 14. " BERINTFL[14] ,CP A bus error interrupt flag 14" "No interrupt,Interrupt"
|
|
newline
|
|
eventfld.long 0x0C 13. " BERINTFL[13] ,CP B bus error interrupt flag 13" "No interrupt,Interrupt"
|
|
eventfld.long 0x0C 12. " BERINTFL[12] ,CP A bus error interrupt flag 12" "No interrupt,Interrupt"
|
|
newline
|
|
eventfld.long 0x0C 11. " BERINTFL[11] ,CP B bus error interrupt flag 11" "No interrupt,Interrupt"
|
|
eventfld.long 0x0C 10. " BERINTFL[10] ,CP A bus error interrupt flag 10" "No interrupt,Interrupt"
|
|
newline
|
|
eventfld.long 0x0C 9. " BERINTFL[9] ,CP B bus error interrupt flag 9" "No interrupt,Interrupt"
|
|
eventfld.long 0x0C 8. " BERINTFL[8] ,CP A bus error interrupt flag 8" "No interrupt,Interrupt"
|
|
newline
|
|
eventfld.long 0x0C 7. " BERINTFL[7] ,CP B bus error interrupt flag 7" "No interrupt,Interrupt"
|
|
eventfld.long 0x0C 6. " BERINTFL[6] ,CP A bus error interrupt flag 6" "No interrupt,Interrupt"
|
|
newline
|
|
eventfld.long 0x0C 5. " BERINTFL[5] ,CP B bus error interrupt flag 5" "No interrupt,Interrupt"
|
|
eventfld.long 0x0C 4. " BERINTFL[4] ,CP A bus error interrupt flag 4" "No interrupt,Interrupt"
|
|
newline
|
|
eventfld.long 0x0C 3. " BERINTFL[3] ,CP B bus error interrupt flag 3" "No interrupt,Interrupt"
|
|
eventfld.long 0x0C 2. " BERINTFL[2] ,CP A bus error interrupt flag 2" "No interrupt,Interrupt"
|
|
newline
|
|
eventfld.long 0x0C 1. " BERINTFL[1] ,CP B bus error interrupt flag 1" "No interrupt,Interrupt"
|
|
eventfld.long 0x0C 0. " BERINTFL[0] ,CP A bus error interrupt flag 0" "No interrupt,Interrupt"
|
|
line.long 0x10 "MP1S,Memory Protection 1 Start Address"
|
|
line.long 0x14 "MP1E,Memory Protection 1 End Address"
|
|
line.long 0x18 "DCTRL,Debug Control Register"
|
|
sif (cpuis("TMS570LS0332")||cpuis("TMS570LS0432")||cpuis("TMS570LS1114*")||cpuis("TMS570LS1115*")||cpuis("TMS570LS1224*")||cpuis("TMS570LS1225*")||cpuis("TMS570LS1227*"))
|
|
rbitfld.long 0x18 24.--27. " CPNUM ,CP number" "CP A of DCP0,CP B of DCP0,CP A of DCP1,,,,,,,,,,,,CP A of DCP7,CP B of DCP7"
|
|
elif cpuis("TMS570LS0232")||cpuis("TMS570LS0714*")||cpuis("TMS570LS0914*")||cpuis("TMS570LS3137-EP")
|
|
bitfld.long 0x18 24.--27. " CPNUM ,CP number" "CP A of DCP 0,CP B of DCP 0,CP A of DCP 1,CP B of DCP 1,CP A of DCP 2,CP B of DCP 2,CP A of DCP 3,CP B of DCP 3,CP A of DCP 4,CP B of DCP 4,CP A of DCP 5,CP B of DCP 5,CP A of DCP 6,CP B of DCP 6,CP A of DCP 7,CP B of DCP 7"
|
|
else
|
|
bitfld.long 0x18 24.--27. " CPNUM ,CP number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
newline
|
|
eventfld.long 0x18 16. " HTUDBGS ,HTU debug status" "Not detected,Detected"
|
|
bitfld.long 0x18 0. " DBREN ,Debug request enable" "Disabled,Enabled"
|
|
line.long 0x1C "WPR,Watch Point Register"
|
|
line.long 0x20 "WMR,Watch Mask Register"
|
|
rgroup.long 0x60++0x03
|
|
line.long 0x00 "ID,Module Identification Register"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CLASS ,Module class"
|
|
hexmask.long.byte 0x00 8.--15. 1. " TYPE ,Subtype within a class"
|
|
hexmask.long.byte 0x00 0.--7. 1. " REV ,Module revision number"
|
|
group.long 0x64++0x07
|
|
line.long 0x0 "PCR,Parity Control Register"
|
|
bitfld.long 0x00 16. " COPE , Continue on parity error" "Stopped,Continued"
|
|
bitfld.long 0x00 8. " TEST ,Test" "Not mapped,Mapped"
|
|
bitfld.long 0x00 0.--3. " PARITY_ENA ,Enable/disable parity checking" "Enabled,Enabled,Enabled,Enabled,Enabled,Disabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled"
|
|
line.long 0x04 "PAR,Parity Address Register"
|
|
eventfld.long 0x04 16. " PEFT ,Parity Error fault flag" "Not detected,Detected"
|
|
hexmask.long.word 0x04 0.--8. 1. " PAOFF ,Parity error address offset"
|
|
group.long 0x70++0x0B
|
|
line.long 0x00 "MPCS,Memory Protection Control and Status Register"
|
|
sif cpuis("TMS570LS0232")||cpuis("TMS570LS0714*")||cpuis("TMS570LS0914*")||cpuis("TMS570LS3137-EP")
|
|
rbitfld.long 0x00 24.--27. " CPNUM0 ,CP number" "CP A of DCP 0,CP B of DCP 0,CP A of DCP 1,CP B of DCP 1,CP A of DCP 2,CP B of DCP 2,CP A of DCP 3,CP B of DCP 3,CP A of DCP 4,CP B of DCP 4,CP A of DCP 5,CP B of DCP 5,CP A of DCP 6,CP B of DCP 6,CP A of DCP 7,CP B of DCP 7"
|
|
else
|
|
bitfld.long 0x00 24.--27. " CPNUM0 ,CP number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
newline
|
|
eventfld.long 0x00 17. " MPEFT1 ,Memory protection error fault flag" "Not detected,Detected"
|
|
eventfld.long 0x00 16. " MPEFT0 ,Memory protection error fault flag" "Not detected,Detected"
|
|
newline
|
|
sif (cpuis("TMS570LS0332")||cpuis("TMS570LS0432")||cpuis("TMS570LS1114*")||cpuis("TMS570LS1115*")||cpuis("TMS570LS1224*")||cpuis("TMS570LS1225*")||cpuis("TMS570LS1227*"))
|
|
rbitfld.long 0x00 8.--11. " CPNUM1 ,CP number" "CP A of DCP0,CP B of DCP0,CP A of DCP1,,,,,,,,,,,,CP A of DCP7,CP B of DCP7"
|
|
elif cpuis("TMS570LS0232")||cpuis("TMS570LS0714*")||cpuis("TMS570LS0914*")||cpuis("TMS570LS3137-EP")
|
|
rbitfld.long 0x00 8.--11. " CPNUM1 ,CP number" "CP A of DCP 0,CP B of DCP 0,CP A of DCP 1,CP B of DCP 1,CP A of DCP 2,CP B of DCP 2,CP A of DCP 3,CP B of DCP 3,CP A of DCP 4,CP B of DCP 4,CP A of DCP 5,CP B of DCP 5,CP A of DCP 6,CP B of DCP 6,CP A of DCP 7,CP B of DCP 7"
|
|
else
|
|
bitfld.long 0x00 8.--11. " CPNUM1 ,CP number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
newline
|
|
bitfld.long 0x00 5. " INTENA01 ,Interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " ACCR01 ,Access rights HTU" "Allowed,Forbidden"
|
|
newline
|
|
bitfld.long 0x00 3. " REG01ENA ,Region enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " INTENA0 ,Interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " ACCR ,Access rights HTU" "Allowed,Forbidden"
|
|
newline
|
|
bitfld.long 0x00 0. " REG0ENA ,Region enable" "Disabled,Enabled"
|
|
line.long 0x04 "MP0S,Memory Protection Start Address Register"
|
|
line.long 0x08 "MP0E,Memory Protection End Address Register"
|
|
sif (cpuis("TMS570LS10106-PGE")||cpuis("TMS570LS10106-ZWT")||cpuis("TMS570LS10116-PGE")||cpuis("TMS570LS10116-ZWT")||cpuis("TMS570LS10206-PGE")||cpuis("TMS570LS10206-ZWT")||cpuis("TMS570LS10216-PGE")||cpuis("TMS570LS10216-ZWT")||cpuis("TMS570LS20206-PGE")||cpuis("TMS570LS20206-ZWT")||cpuis("TMS570LS20216-PGE")||cpuis("TMS570LS20216-ZWT")||cpuis("RM48L952-PGE")||cpuis("RM48L952-ZWT")||cpuis("RM48L950-PGE")||cpuis("RM48L950-ZWT")||cpuis("RM48L940-ZWT")||cpuis("RM48L940-PGE")||cpuis("RM48L930-ZWT")||cpuis("RM48L930-PGE")||cpuis("RM48L750-ZWT")||cpuis("RM48L750-PGE")||cpuis("RM48L740-ZWT")||cpuis("RM48L740-PGE")||cpuis("RM48L730-ZWT")||cpuis("RM48L730-PGE")||cpuis("RM48L550-PGE")||cpuis("RM48L540-ZWT")||cpuis("RM48L540-PGE")||cpuis("RM48L530-ZWT")||cpuis("RM48L530-PGE")||cpuis("RM46L852-PGE")||cpuis("RM46L852-ZWT")||cpuis("RM46L850-PGE")||cpuis("RM46L850-ZWT")||cpuis("RM46L840-ZWT")||cpuis("RM46L840-PGE")||cpuis("RM46L830-ZWT")||cpuis("RM46L830-PGE")||cpuis("RM46L450-ZWT")||cpuis("RM46L450-PGE")||cpuis("RM46L440-ZWT")||cpuis("RM46L440-PGE")||cpuis("RM46L430-ZWT")||cpuis("RM46L430-PGE")||cpuis("RM42L432")||cpuis("RM48L550-ZWT")||cpuis("TMS570LC4357")||cpuis("TMS570LS0332")||cpuis("TMS570LS0432")||cpuis("TMS570LS1114*")||cpuis("TMS570LS1115*")||cpuis("TMS570LS1224*")||cpuis("TMS570LS1225*")||cpuis("TMS570LS1227*")||cpuis("TMS570LS0232")||cpuis("TMS570LS0714*")||cpuis("TMS570LS0914*")||cpuis("TMS570LS3137-EP"))
|
|
tree "Double Control Packet Configuration Memory"
|
|
base ad:0xFF4E0000
|
|
sif !cpuis("TMS570LS0714*")&&!cpuis("TMS570LS0914*")&&!cpuis("RM46L852*")&&!cpuis("TMS570LS3137-EP")
|
|
group.long 0x00++0xF
|
|
line.long 0x00 "IFADDRA,Initial main memory address Control Packet A"
|
|
line.long 0x04 "IFADDRB,Initial main memory address Control Packet B"
|
|
line.long 0x08 "IHADDRCT,Initial NHET address and control"
|
|
bitfld.long 0x08 23. " DIR ,Direction of transfer (read->write)" "NHET->Main,Main->NHET"
|
|
bitfld.long 0x08 22. " SIZE ,Size of transferred data" "32-bit,64-bit"
|
|
newline
|
|
bitfld.long 0x08 21. " ADDMH ,Addressing mode NHET address (increment value)" "16 bytes,8 bytes"
|
|
bitfld.long 0x08 20. " ADDMF ,Addressing mode main memory address" "Post-increment,Constant"
|
|
newline
|
|
bitfld.long 0x08 18.--19. " TMBA ,Transfer mode for buffer A" "One Shot,Circular,Auto Switch,Auto Switch"
|
|
bitfld.long 0x08 16.--17. " TMBB ,Transfer mode for buffer B" "One Shot,Circular,Auto Switch,Auto Switch"
|
|
newline
|
|
hexmask.long.word 0x08 2.--12. 0x4 " IHADDR ,Initial NHET address"
|
|
line.long 0x0C "ITCOUNT,Initial transfer count"
|
|
bitfld.long 0x0C 16.--20. " IETCOUNT ,Initial element transfer count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
hexmask.long.byte 0x0C 0.--7. 1. " IFTCOUNT ,Initial frame transfer count"
|
|
group.long 0x100++0xB
|
|
line.long 0x00 "CFADDRA,Current main memory address Control Packet A"
|
|
line.long 0x04 "CFADDRB,Current main memory address Control Packet B"
|
|
line.long 0x08 "CFCOUNT,Current frame count"
|
|
hexmask.long.byte 0x08 16.--23. 1. " CFTCTA ,Current frame transfer count for CP A"
|
|
hexmask.long.byte 0x08 0.--7. 1. " CFTCTB ,Current frame transfer count for CP B"
|
|
else
|
|
width 15.
|
|
group.long 0x0++0x0F "DCP0"
|
|
line.long 0x00 "DCP0IFADDRA,DCP0 Initial main memory address Control Packet A"
|
|
line.long 0x04 "DCP0IFADDRB,DCP0 Initial main memory address Control Packet B"
|
|
line.long 0x08 "DCP0IHADDRCT,DCP0 Initial NHET address and control"
|
|
bitfld.long 0x08 23. " DIR ,Direction of transfer (read->write)" "NHET->Main,Main->NHET"
|
|
bitfld.long 0x08 22. " SIZE ,Size of transferred data" "32-bit,64-bit"
|
|
newline
|
|
bitfld.long 0x08 21. " ADDMH ,Addressing mode NHET address (Increment value)" "16 bytes,8 bytes"
|
|
bitfld.long 0x08 20. " ADDMF ,Addressing mode main memory address" "Post-increment,Constant"
|
|
newline
|
|
bitfld.long 0x08 18.--19. " TMBA ,Transfer mode for buffer A" "One Shot,Circular,Auto Switch,Auto Switch"
|
|
bitfld.long 0x08 16.--17. " TMBB ,Transfer mode for buffer B" "One Shot,Circular,Auto Switch,Auto Switch"
|
|
newline
|
|
hexmask.long.word 0x08 2.--12. 0x4 " IHADDR ,Initial NHET address"
|
|
line.long 0x0C "DCP0ITCOUNT,DCP0 Initial transfer count"
|
|
bitfld.long 0x0C 16.--20. " IETCOUNT ,Initial element transfer count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
hexmask.long.byte 0x0C 0.--7. 1. " IFTCOUNT ,Initial frame transfer count"
|
|
group.long (0x0+0x100)++0xB
|
|
line.long 0x00 "DCP0CFADDRA,DCP0 Current main memory address control packet A"
|
|
line.long 0x04 "DCP0CFADDRB,DCP0 Current main memory address control packet B"
|
|
line.long 0x08 "DCP0CFCOUNT,DCP0 Current frame count"
|
|
hexmask.long.byte 0x08 16.--23. 1. " CFTCTA ,Current frame transfer count for CP A"
|
|
hexmask.long.byte 0x08 0.--7. 1. " CFTCTB ,Current frame transfer count for CP B"
|
|
group.long 0x10++0x0F "DCP1"
|
|
line.long 0x00 "DCP1IFADDRA,DCP1 Initial main memory address Control Packet A"
|
|
line.long 0x04 "DCP1IFADDRB,DCP1 Initial main memory address Control Packet B"
|
|
line.long 0x08 "DCP1IHADDRCT,DCP1 Initial NHET address and control"
|
|
bitfld.long 0x08 23. " DIR ,Direction of transfer (read->write)" "NHET->Main,Main->NHET"
|
|
bitfld.long 0x08 22. " SIZE ,Size of transferred data" "32-bit,64-bit"
|
|
newline
|
|
bitfld.long 0x08 21. " ADDMH ,Addressing mode NHET address (Increment value)" "16 bytes,8 bytes"
|
|
bitfld.long 0x08 20. " ADDMF ,Addressing mode main memory address" "Post-increment,Constant"
|
|
newline
|
|
bitfld.long 0x08 18.--19. " TMBA ,Transfer mode for buffer A" "One Shot,Circular,Auto Switch,Auto Switch"
|
|
bitfld.long 0x08 16.--17. " TMBB ,Transfer mode for buffer B" "One Shot,Circular,Auto Switch,Auto Switch"
|
|
newline
|
|
hexmask.long.word 0x08 2.--12. 0x4 " IHADDR ,Initial NHET address"
|
|
line.long 0x0C "DCP1ITCOUNT,DCP1 Initial transfer count"
|
|
bitfld.long 0x0C 16.--20. " IETCOUNT ,Initial element transfer count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
hexmask.long.byte 0x0C 0.--7. 1. " IFTCOUNT ,Initial frame transfer count"
|
|
group.long (0x10+0x100)++0xB
|
|
line.long 0x00 "DCP1CFADDRA,DCP1 Current main memory address control packet A"
|
|
line.long 0x04 "DCP1CFADDRB,DCP1 Current main memory address control packet B"
|
|
line.long 0x08 "DCP1CFCOUNT,DCP1 Current frame count"
|
|
hexmask.long.byte 0x08 16.--23. 1. " CFTCTA ,Current frame transfer count for CP A"
|
|
hexmask.long.byte 0x08 0.--7. 1. " CFTCTB ,Current frame transfer count for CP B"
|
|
group.long 0x20++0x0F "DCP2"
|
|
line.long 0x00 "DCP2IFADDRA,DCP2 Initial main memory address Control Packet A"
|
|
line.long 0x04 "DCP2IFADDRB,DCP2 Initial main memory address Control Packet B"
|
|
line.long 0x08 "DCP2IHADDRCT,DCP2 Initial NHET address and control"
|
|
bitfld.long 0x08 23. " DIR ,Direction of transfer (read->write)" "NHET->Main,Main->NHET"
|
|
bitfld.long 0x08 22. " SIZE ,Size of transferred data" "32-bit,64-bit"
|
|
newline
|
|
bitfld.long 0x08 21. " ADDMH ,Addressing mode NHET address (Increment value)" "16 bytes,8 bytes"
|
|
bitfld.long 0x08 20. " ADDMF ,Addressing mode main memory address" "Post-increment,Constant"
|
|
newline
|
|
bitfld.long 0x08 18.--19. " TMBA ,Transfer mode for buffer A" "One Shot,Circular,Auto Switch,Auto Switch"
|
|
bitfld.long 0x08 16.--17. " TMBB ,Transfer mode for buffer B" "One Shot,Circular,Auto Switch,Auto Switch"
|
|
newline
|
|
hexmask.long.word 0x08 2.--12. 0x4 " IHADDR ,Initial NHET address"
|
|
line.long 0x0C "DCP2ITCOUNT,DCP2 Initial transfer count"
|
|
bitfld.long 0x0C 16.--20. " IETCOUNT ,Initial element transfer count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
hexmask.long.byte 0x0C 0.--7. 1. " IFTCOUNT ,Initial frame transfer count"
|
|
group.long (0x20+0x100)++0xB
|
|
line.long 0x00 "DCP2CFADDRA,DCP2 Current main memory address control packet A"
|
|
line.long 0x04 "DCP2CFADDRB,DCP2 Current main memory address control packet B"
|
|
line.long 0x08 "DCP2CFCOUNT,DCP2 Current frame count"
|
|
hexmask.long.byte 0x08 16.--23. 1. " CFTCTA ,Current frame transfer count for CP A"
|
|
hexmask.long.byte 0x08 0.--7. 1. " CFTCTB ,Current frame transfer count for CP B"
|
|
group.long 0x30++0x0F "DCP3"
|
|
line.long 0x00 "DCP3IFADDRA,DCP3 Initial main memory address Control Packet A"
|
|
line.long 0x04 "DCP3IFADDRB,DCP3 Initial main memory address Control Packet B"
|
|
line.long 0x08 "DCP3IHADDRCT,DCP3 Initial NHET address and control"
|
|
bitfld.long 0x08 23. " DIR ,Direction of transfer (read->write)" "NHET->Main,Main->NHET"
|
|
bitfld.long 0x08 22. " SIZE ,Size of transferred data" "32-bit,64-bit"
|
|
newline
|
|
bitfld.long 0x08 21. " ADDMH ,Addressing mode NHET address (Increment value)" "16 bytes,8 bytes"
|
|
bitfld.long 0x08 20. " ADDMF ,Addressing mode main memory address" "Post-increment,Constant"
|
|
newline
|
|
bitfld.long 0x08 18.--19. " TMBA ,Transfer mode for buffer A" "One Shot,Circular,Auto Switch,Auto Switch"
|
|
bitfld.long 0x08 16.--17. " TMBB ,Transfer mode for buffer B" "One Shot,Circular,Auto Switch,Auto Switch"
|
|
newline
|
|
hexmask.long.word 0x08 2.--12. 0x4 " IHADDR ,Initial NHET address"
|
|
line.long 0x0C "DCP3ITCOUNT,DCP3 Initial transfer count"
|
|
bitfld.long 0x0C 16.--20. " IETCOUNT ,Initial element transfer count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
hexmask.long.byte 0x0C 0.--7. 1. " IFTCOUNT ,Initial frame transfer count"
|
|
group.long (0x30+0x100)++0xB
|
|
line.long 0x00 "DCP3CFADDRA,DCP3 Current main memory address control packet A"
|
|
line.long 0x04 "DCP3CFADDRB,DCP3 Current main memory address control packet B"
|
|
line.long 0x08 "DCP3CFCOUNT,DCP3 Current frame count"
|
|
hexmask.long.byte 0x08 16.--23. 1. " CFTCTA ,Current frame transfer count for CP A"
|
|
hexmask.long.byte 0x08 0.--7. 1. " CFTCTB ,Current frame transfer count for CP B"
|
|
group.long 0x40++0x0F "DCP4"
|
|
line.long 0x00 "DCP4IFADDRA,DCP4 Initial main memory address Control Packet A"
|
|
line.long 0x04 "DCP4IFADDRB,DCP4 Initial main memory address Control Packet B"
|
|
line.long 0x08 "DCP4IHADDRCT,DCP4 Initial NHET address and control"
|
|
bitfld.long 0x08 23. " DIR ,Direction of transfer (read->write)" "NHET->Main,Main->NHET"
|
|
bitfld.long 0x08 22. " SIZE ,Size of transferred data" "32-bit,64-bit"
|
|
newline
|
|
bitfld.long 0x08 21. " ADDMH ,Addressing mode NHET address (Increment value)" "16 bytes,8 bytes"
|
|
bitfld.long 0x08 20. " ADDMF ,Addressing mode main memory address" "Post-increment,Constant"
|
|
newline
|
|
bitfld.long 0x08 18.--19. " TMBA ,Transfer mode for buffer A" "One Shot,Circular,Auto Switch,Auto Switch"
|
|
bitfld.long 0x08 16.--17. " TMBB ,Transfer mode for buffer B" "One Shot,Circular,Auto Switch,Auto Switch"
|
|
newline
|
|
hexmask.long.word 0x08 2.--12. 0x4 " IHADDR ,Initial NHET address"
|
|
line.long 0x0C "DCP4ITCOUNT,DCP4 Initial transfer count"
|
|
bitfld.long 0x0C 16.--20. " IETCOUNT ,Initial element transfer count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
hexmask.long.byte 0x0C 0.--7. 1. " IFTCOUNT ,Initial frame transfer count"
|
|
group.long (0x40+0x100)++0xB
|
|
line.long 0x00 "DCP4CFADDRA,DCP4 Current main memory address control packet A"
|
|
line.long 0x04 "DCP4CFADDRB,DCP4 Current main memory address control packet B"
|
|
line.long 0x08 "DCP4CFCOUNT,DCP4 Current frame count"
|
|
hexmask.long.byte 0x08 16.--23. 1. " CFTCTA ,Current frame transfer count for CP A"
|
|
hexmask.long.byte 0x08 0.--7. 1. " CFTCTB ,Current frame transfer count for CP B"
|
|
group.long 0x50++0x0F "DCP5"
|
|
line.long 0x00 "DCP5IFADDRA,DCP5 Initial main memory address Control Packet A"
|
|
line.long 0x04 "DCP5IFADDRB,DCP5 Initial main memory address Control Packet B"
|
|
line.long 0x08 "DCP5IHADDRCT,DCP5 Initial NHET address and control"
|
|
bitfld.long 0x08 23. " DIR ,Direction of transfer (read->write)" "NHET->Main,Main->NHET"
|
|
bitfld.long 0x08 22. " SIZE ,Size of transferred data" "32-bit,64-bit"
|
|
newline
|
|
bitfld.long 0x08 21. " ADDMH ,Addressing mode NHET address (Increment value)" "16 bytes,8 bytes"
|
|
bitfld.long 0x08 20. " ADDMF ,Addressing mode main memory address" "Post-increment,Constant"
|
|
newline
|
|
bitfld.long 0x08 18.--19. " TMBA ,Transfer mode for buffer A" "One Shot,Circular,Auto Switch,Auto Switch"
|
|
bitfld.long 0x08 16.--17. " TMBB ,Transfer mode for buffer B" "One Shot,Circular,Auto Switch,Auto Switch"
|
|
newline
|
|
hexmask.long.word 0x08 2.--12. 0x4 " IHADDR ,Initial NHET address"
|
|
line.long 0x0C "DCP5ITCOUNT,DCP5 Initial transfer count"
|
|
bitfld.long 0x0C 16.--20. " IETCOUNT ,Initial element transfer count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
hexmask.long.byte 0x0C 0.--7. 1. " IFTCOUNT ,Initial frame transfer count"
|
|
group.long (0x50+0x100)++0xB
|
|
line.long 0x00 "DCP5CFADDRA,DCP5 Current main memory address control packet A"
|
|
line.long 0x04 "DCP5CFADDRB,DCP5 Current main memory address control packet B"
|
|
line.long 0x08 "DCP5CFCOUNT,DCP5 Current frame count"
|
|
hexmask.long.byte 0x08 16.--23. 1. " CFTCTA ,Current frame transfer count for CP A"
|
|
hexmask.long.byte 0x08 0.--7. 1. " CFTCTB ,Current frame transfer count for CP B"
|
|
group.long 0x60++0x0F "DCP6"
|
|
line.long 0x00 "DCP6IFADDRA,DCP6 Initial main memory address Control Packet A"
|
|
line.long 0x04 "DCP6IFADDRB,DCP6 Initial main memory address Control Packet B"
|
|
line.long 0x08 "DCP6IHADDRCT,DCP6 Initial NHET address and control"
|
|
bitfld.long 0x08 23. " DIR ,Direction of transfer (read->write)" "NHET->Main,Main->NHET"
|
|
bitfld.long 0x08 22. " SIZE ,Size of transferred data" "32-bit,64-bit"
|
|
newline
|
|
bitfld.long 0x08 21. " ADDMH ,Addressing mode NHET address (Increment value)" "16 bytes,8 bytes"
|
|
bitfld.long 0x08 20. " ADDMF ,Addressing mode main memory address" "Post-increment,Constant"
|
|
newline
|
|
bitfld.long 0x08 18.--19. " TMBA ,Transfer mode for buffer A" "One Shot,Circular,Auto Switch,Auto Switch"
|
|
bitfld.long 0x08 16.--17. " TMBB ,Transfer mode for buffer B" "One Shot,Circular,Auto Switch,Auto Switch"
|
|
newline
|
|
hexmask.long.word 0x08 2.--12. 0x4 " IHADDR ,Initial NHET address"
|
|
line.long 0x0C "DCP6ITCOUNT,DCP6 Initial transfer count"
|
|
bitfld.long 0x0C 16.--20. " IETCOUNT ,Initial element transfer count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
hexmask.long.byte 0x0C 0.--7. 1. " IFTCOUNT ,Initial frame transfer count"
|
|
group.long (0x60+0x100)++0xB
|
|
line.long 0x00 "DCP6CFADDRA,DCP6 Current main memory address control packet A"
|
|
line.long 0x04 "DCP6CFADDRB,DCP6 Current main memory address control packet B"
|
|
line.long 0x08 "DCP6CFCOUNT,DCP6 Current frame count"
|
|
hexmask.long.byte 0x08 16.--23. 1. " CFTCTA ,Current frame transfer count for CP A"
|
|
hexmask.long.byte 0x08 0.--7. 1. " CFTCTB ,Current frame transfer count for CP B"
|
|
group.long 0x70++0x0F "DCP7"
|
|
line.long 0x00 "DCP7IFADDRA,DCP7 Initial main memory address Control Packet A"
|
|
line.long 0x04 "DCP7IFADDRB,DCP7 Initial main memory address Control Packet B"
|
|
line.long 0x08 "DCP7IHADDRCT,DCP7 Initial NHET address and control"
|
|
bitfld.long 0x08 23. " DIR ,Direction of transfer (read->write)" "NHET->Main,Main->NHET"
|
|
bitfld.long 0x08 22. " SIZE ,Size of transferred data" "32-bit,64-bit"
|
|
newline
|
|
bitfld.long 0x08 21. " ADDMH ,Addressing mode NHET address (Increment value)" "16 bytes,8 bytes"
|
|
bitfld.long 0x08 20. " ADDMF ,Addressing mode main memory address" "Post-increment,Constant"
|
|
newline
|
|
bitfld.long 0x08 18.--19. " TMBA ,Transfer mode for buffer A" "One Shot,Circular,Auto Switch,Auto Switch"
|
|
bitfld.long 0x08 16.--17. " TMBB ,Transfer mode for buffer B" "One Shot,Circular,Auto Switch,Auto Switch"
|
|
newline
|
|
hexmask.long.word 0x08 2.--12. 0x4 " IHADDR ,Initial NHET address"
|
|
line.long 0x0C "DCP7ITCOUNT,DCP7 Initial transfer count"
|
|
bitfld.long 0x0C 16.--20. " IETCOUNT ,Initial element transfer count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
hexmask.long.byte 0x0C 0.--7. 1. " IFTCOUNT ,Initial frame transfer count"
|
|
group.long (0x70+0x100)++0xB
|
|
line.long 0x00 "DCP7CFADDRA,DCP7 Current main memory address control packet A"
|
|
line.long 0x04 "DCP7CFADDRB,DCP7 Current main memory address control packet B"
|
|
line.long 0x08 "DCP7CFCOUNT,DCP7 Current frame count"
|
|
hexmask.long.byte 0x08 16.--23. 1. " CFTCTA ,Current frame transfer count for CP A"
|
|
hexmask.long.byte 0x08 0.--7. 1. " CFTCTB ,Current frame transfer count for CP B"
|
|
endif
|
|
tree.end
|
|
endif
|
|
sif cpuis("TMS570LS0232")||cpuis("TMS570LS0714*")||cpuis("TMS570LS0914*")
|
|
endian.le
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
tree "HTU2"
|
|
base ad:0xFFF7A500
|
|
sif cpuis("TMS570LS0232")||cpuis("TMS570LS0714*")||cpuis("TMS570LS0914*")
|
|
endian.be
|
|
endif
|
|
width 10.
|
|
group.long 0x00++0x07
|
|
line.long 0x00 "GC,Global Control Register"
|
|
bitfld.long 0x00 24. " VBUS_HOLD ,Hold the VBUS bus" "Not held,Held"
|
|
bitfld.long 0x00 16. " HTUEN ,Transfer unit enable bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " DEBM ,Debug mode" "Suspended,Continue"
|
|
newline
|
|
bitfld.long 0x00 0. " HTU_RES ,HTU software reset" "No reset,Reset"
|
|
line.long 0x04 "CPENA,Control Packet Enable Register"
|
|
bitfld.long 0x04 14.--15. " CPENA7 ,CP enable bits 7 (CP B/CP A)" "Disabled,Disabled/Enabled,Enabled/Disabled,Disabled"
|
|
bitfld.long 0x04 12.--13. " CPENA6 ,CP enable bits 6 (CP B/CP A)" "Disabled,Disabled/Enabled,Enabled/Disabled,Disabled"
|
|
newline
|
|
bitfld.long 0x04 10.--11. " CPENA5 ,CP enable bits 5 (CP B/CP A)" "Disabled,Disabled/Enabled,Enabled/Disabled,Disabled"
|
|
bitfld.long 0x04 8.--9. " CPENA4 ,CP enable bits 4 (CP B/CP A)" "Disabled,Disabled/Enabled,Enabled/Disabled,Disabled"
|
|
newline
|
|
bitfld.long 0x04 6.--7. " CPENA3 ,CP enable bits 3 (CP B/CP A)" "Disabled,Disabled/Enabled,Enabled/Disabled,Disabled"
|
|
bitfld.long 0x04 4.--5. " CPENA2 ,CP enable bits 2 (CP B/CP A)" "Disabled,Disabled/Enabled,Enabled/Disabled,Disabled"
|
|
newline
|
|
bitfld.long 0x04 2.--3. " CPENA1 ,CP enable bits 1 (CP B/CP A)" "Disabled,Disabled/Enabled,Enabled/Disabled,Disabled"
|
|
bitfld.long 0x04 0.--1. " CPENA0 ,CP enable bits 0 (CP B/CP A)" "Disabled,Disabled/Enabled,Enabled/Disabled,Disabled"
|
|
group.long 0x8++0x03
|
|
line.long 0x00 "BUSY0,Control Packet (CP) Busy Register 0"
|
|
eventfld.long 0x00 24. " BUSY0A ,Busy flag for CP A of double CP 0" "Low,High"
|
|
eventfld.long 0x00 16. " BUSY0B ,Busy flag for CP B of double CP 0" "Low,High"
|
|
eventfld.long 0x00 8. " BUSY1A ,Busy flag for CP A of double CP 1" "Low,High"
|
|
eventfld.long 0x00 0. " BUSY1B ,Busy flag for CP B of double CP 1" "Low,High"
|
|
group.long 0xC++0x03
|
|
line.long 0x00 "BUSY1,Control Packet (CP) Busy Register 1"
|
|
eventfld.long 0x00 24. " BUSY2A ,Busy flag for CP A of double CP 2" "Low,High"
|
|
eventfld.long 0x00 16. " BUSY2B ,Busy flag for CP B of double CP 2" "Low,High"
|
|
eventfld.long 0x00 8. " BUSY3A ,Busy flag for CP A of double CP 3" "Low,High"
|
|
eventfld.long 0x00 0. " BUSY3B ,Busy flag for CP B of double CP 3" "Low,High"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "BUSY2,Control Packet (CP) Busy Register 2"
|
|
eventfld.long 0x00 24. " BUSY4A ,Busy flag for CP A of double CP 4" "Low,High"
|
|
eventfld.long 0x00 16. " BUSY4B ,Busy flag for CP B of double CP 4" "Low,High"
|
|
eventfld.long 0x00 8. " BUSY5A ,Busy flag for CP A of double CP 5" "Low,High"
|
|
eventfld.long 0x00 0. " BUSY5B ,Busy flag for CP B of double CP 5" "Low,High"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "BUSY3,Control Packet (CP) Busy Register 3"
|
|
eventfld.long 0x00 24. " BUSY6A ,Busy flag for CP A of double CP 6" "Low,High"
|
|
eventfld.long 0x00 16. " BUSY6B ,Busy flag for CP B of double CP 6" "Low,High"
|
|
eventfld.long 0x00 8. " BUSY7A ,Busy flag for CP A of double CP 7" "Low,High"
|
|
eventfld.long 0x00 0. " BUSY7B ,Busy flag for CP B of double CP 7" "Low,High"
|
|
sif cpuis("TMS570LS0232")||cpuis("TMS570LS0714*")||cpuis("TMS570LS0914*")||cpuis("TMS570LS3137-EP")
|
|
group.long 0x18++0x3
|
|
line.long 0x00 "ACPE,Active Control Packet Register"
|
|
eventfld.long 0x00 31. " ERRF ,Error flag" "No error,Error"
|
|
rbitfld.long 0x00 24.--28. " ERRETC ,Error element transfer counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
rbitfld.long 0x00 16.--19. " ERRCPN ,Error control packet number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rbitfld.long 0x00 15. " TIPF ,Transfer in progress flag" "Not active,Active"
|
|
newline
|
|
rbitfld.long 0x00 14. " BUS_BUSY ,VBUSP bus is busy" "Not busy,Busy"
|
|
rbitfld.long 0x00 8.--12. " CETCOUNT ,Current element transfer counter" "No transfer,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
rbitfld.long 0x00 0.--3. " NACP ,Number of active control packet" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
else
|
|
group.long 0x18++0x3
|
|
line.long 0x00 "ACPE,Active Control Packet Register"
|
|
eventfld.long 0x00 31. " ERRF ,Error flag" "No error,Error"
|
|
bitfld.long 0x00 24.--28. " ERRETC ,Error element transfer counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
hexmask.long.byte 0x00 16.--19. 1. " ERRCPN ,Error control packet number"
|
|
bitfld.long 0x00 15. " TIPF ,Transfer in progress flag" "Not active,Active"
|
|
newline
|
|
bitfld.long 0x00 14. " BUS_BUSY ,VBUSP bus is busy" "Not busy,Busy"
|
|
bitfld.long 0x00 8.--12. " CETCOUNT ,Current element transfer counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
hexmask.long.byte 0x00 0.--3. 1. " NACP ,Number of active control packet"
|
|
endif
|
|
newline
|
|
width 16.
|
|
group.long 0x20++0x07
|
|
line.long 0x00 "RLBECTRL,Request Lost and Bus Error Control Register"
|
|
bitfld.long 0x00 16. " BERINTENA ,Bus error interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " CORL ,Continue on request lost error" "Lost,Continue"
|
|
bitfld.long 0x00 0. " RLINTENA ,Request lost interrupt enable bit" "Disabled,Enabled"
|
|
line.long 0x04 "BFINTS_SET/CLR,Buffer Full Interrupt Enable Set/Clr Register"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x08 15. " BFINTENA[15] ,CP B Buffer full interrupt enable bit 15" "Disabled,Enabled"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x08 14. " [14] ,CP A Buffer full interrupt enable Bit 14" "Disabled,Enabled"
|
|
setclrfld.long 0x04 13. 0x04 13. 0x08 13. " [13] ,CP B Bit 13" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x04 12. 0x04 12. 0x08 12. " [12] ,CP A Buffer Full Interrupt Enable Bit 12" "Disabled,Enabled"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x08 11. " [11] ,CP B buffer full interrupt enable bit 11" "Disabled,Enabled"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x08 10. " [10] ,CP A buffer full interrupt enable bit 10" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x04 9. 0x04 9. 0x08 9. " [9] ,CP B buffer full interrupt enable bit 9" "Disabled,Enabled"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x08 8. " [8] ,CP A buffer full interrupt enable bit 8" "Disabled,Enabled"
|
|
setclrfld.long 0x04 7. 0x04 7. 0x08 7. " [7] ,CP B buffer full interrupt enable bit 7" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x04 6. 0x04 6. 0x08 6. " [6] ,CP A buffer full interrupt enable bit 6" "Disabled,Enabled"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x08 5. " [5] ,CP B buffer full interrupt enable bit 5" "Disabled,Enabled"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x08 4. " [4] ,CP A buffer full interrupt enable bit 4" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x04 3. 0x04 3. 0x08 3. " [3] ,CP B buffer full interrupt enable bit 3" "Disabled,Enabled"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x08 2. " [2] ,CP A buffer full interrupt enable bit 2" "Disabled,Enabled"
|
|
setclrfld.long 0x04 1. 0x04 1. 0x08 1. " [1] ,CP B buffer full interrupt enable bit 1" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x04 0. 0x04 0. 0x08 0. " [0] ,CP A buffer full interrupt enable bit 0" "Disabled,Enabled"
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "INTMAP,Interrupt Mapping Register"
|
|
bitfld.long 0x00 16. " MAPSEL ,Interrupt mapping select bit" "Low,High"
|
|
bitfld.long 0x00 15. " CPINTMAP[15] ,CP B Interrupt mapping bit 15" "Line 0,Line 1"
|
|
bitfld.long 0x00 14. " [14] ,CP A Interrupt mapping bit 14" "Line 0,Line 1"
|
|
newline
|
|
bitfld.long 0x00 13. " [13] ,CP B Interrupt mapping bit 13" "Line 0,Line 1"
|
|
bitfld.long 0x00 12. " [12] ,CP A Interrupt mapping bit 12" "Line 0,Line 1"
|
|
bitfld.long 0x00 11. " [11] ,CP B Interrupt mapping bit 11" "Line 0,Line 1"
|
|
newline
|
|
bitfld.long 0x00 10. " [10] ,CP A Interrupt mapping bit 10" "Line 0,Line 1"
|
|
bitfld.long 0x00 9. " [9] ,CP B Interrupt mapping bit 9" "Line 0,Line 1"
|
|
bitfld.long 0x00 8. " [8] ,CP A Interrupt mapping bit 8" "Line 0,Line 1"
|
|
newline
|
|
bitfld.long 0x00 7. " [7] ,CP B Interrupt mapping bit 7" "Line 0,Line 1"
|
|
bitfld.long 0x00 6. " [6] ,CP A Interrupt mapping bit 6" "Line 0,Line 1"
|
|
bitfld.long 0x00 5. " [5] ,CP B Interrupt mapping bit 5" "Line 0,Line 1"
|
|
newline
|
|
bitfld.long 0x00 4. " [4] ,CP A Interrupt mapping bit 4" "Line 0,Line 1"
|
|
bitfld.long 0x00 3. " [3] ,CP B Interrupt mapping bit 3" "Line 0,Line 1"
|
|
bitfld.long 0x00 2. " [2] ,CP A Interrupt mapping bit 2" "Line 0,Line 1"
|
|
newline
|
|
bitfld.long 0x00 1. " [1] ,CP B Interrupt mapping bit 1" "Line 0,Line 1"
|
|
bitfld.long 0x00 0. " [0] ,CP A Interrupt mapping bit 0" "Line 0,Line 1"
|
|
newline
|
|
width 10.
|
|
hgroup.long 0x34++0x3
|
|
hide.long 0x0 "INTOFF0,Interrupt Offset Register 0"
|
|
in
|
|
hgroup.long 0x38++0x3
|
|
hide.long 0x0 "INTOFF1,Interrupt Offset Register 1"
|
|
in
|
|
newline
|
|
group.long 0x3C++0x23
|
|
line.long 0x00 "BIM,Buffer Initialization Mode Register"
|
|
bitfld.long 0x00 7. " BIM[7] ,Buffer initialization mode bit 7" "Normal,Special"
|
|
bitfld.long 0x00 6. " BIM[6] ,Buffer initialization mode bit 6" "Normal,Special"
|
|
bitfld.long 0x00 5. " BIM[5] ,Buffer initialization mode bit 5" "Normal,Special"
|
|
bitfld.long 0x00 4. " BIM[4] ,Buffer initialization mode bit 4" "Normal,Special"
|
|
newline
|
|
bitfld.long 0x00 3. " BIM[3] ,Buffer initialization mode bit 3" "Normal,Special"
|
|
bitfld.long 0x00 2. " BIM[2] ,Buffer initialization mode bit 2" "Normal,Special"
|
|
bitfld.long 0x00 1. " BIM[1] ,Buffer initialization mode bit 1" "Normal,Special"
|
|
bitfld.long 0x00 0. " BIM[0] ,Buffer initialization mode bit 0" "Normal,Special"
|
|
line.long 0x04 "RLOSTFL,Request Lost Flag Register"
|
|
eventfld.long 0x04 15. " CPRLFL[15] ,CP B request lost flag 15" "Not requested,Requested"
|
|
eventfld.long 0x04 14. " CPRLFL[14] ,CP A request lost flag 14" "Not requested,Requested"
|
|
newline
|
|
eventfld.long 0x04 13. " CPRLFL[13] ,CP B request lost flag 13" "Not requested,Requested"
|
|
eventfld.long 0x04 12. " CPRLFL[12] ,CP A request lost flag 12" "Not requested,Requested"
|
|
newline
|
|
eventfld.long 0x04 11. " CPRLFL[11] ,CP B request lost flag 11" "Not requested,Requested"
|
|
eventfld.long 0x04 10. " CPRLFL[10] ,CP A request lost flag 10" "Not requested,Requested"
|
|
newline
|
|
eventfld.long 0x04 9. " CPRLFL[9] ,CP B request lost flag 9" "Not requested,Requested"
|
|
eventfld.long 0x04 8. " CPRLFL[8] ,CP A request lost flag 8" "Not requested,Requested"
|
|
newline
|
|
eventfld.long 0x04 7. " CPRLFL[7] ,CP B request lost flag 7" "Not requested,Requested"
|
|
eventfld.long 0x04 6. " CPRLFL[6] ,CP A request lost flag 6" "Not requested,Requested"
|
|
newline
|
|
eventfld.long 0x04 5. " CPRLFL[5] ,CP B request lost flag 5" "Not requested,Requested"
|
|
eventfld.long 0x04 4. " CPRLFL[4] ,CP A request lost flag 4" "Not requested,Requested"
|
|
newline
|
|
eventfld.long 0x04 3. " CPRLFL[3] ,CP B request lost flag 3" "Not requested,Requested"
|
|
eventfld.long 0x04 2. " CPRLFL[2] ,CP A request lost flag 2" "Not requested,Requested"
|
|
newline
|
|
eventfld.long 0x04 1. " CPRLFL[1] ,CP B request lost flag 1" "Not requested,Requested"
|
|
eventfld.long 0x04 0. " CPRLFL[0] ,CP A request lost flag 0" "Not requested,Requested"
|
|
line.long 0x08 "BFINTFL,Buffer Full Interrupt Flag Register"
|
|
eventfld.long 0x08 15. " BFINTFL[15] ,CP B buffer full interrupt flag 15" "No interrupt,Interrupt"
|
|
eventfld.long 0x08 14. " BFINTFL[14] ,CP A buffer full interrupt flag 14" "No interrupt,Interrupt"
|
|
newline
|
|
eventfld.long 0x08 13. " BFINTFL[13] ,CP B buffer full interrupt flag 13" "No interrupt,Interrupt"
|
|
eventfld.long 0x08 12. " BFINTFL[12] ,CP A buffer full interrupt flag 12" "No interrupt,Interrupt"
|
|
newline
|
|
eventfld.long 0x08 11. " BFINTFL[11] ,CP B buffer full interrupt flag 11" "No interrupt,Interrupt"
|
|
eventfld.long 0x08 10. " BFINTFL[10] ,CP A buffer full interrupt flag 10" "No interrupt,Interrupt"
|
|
newline
|
|
eventfld.long 0x08 9. " BFINTFL[9] ,CP B buffer full interrupt flag 9" "No interrupt,Interrupt"
|
|
eventfld.long 0x08 8. " BFINTFL[8] ,CP A buffer full interrupt flag 8" "No interrupt,Interrupt"
|
|
newline
|
|
eventfld.long 0x08 7. " BFINTFL[7] ,CP B buffer full interrupt flag 7" "No interrupt,Interrupt"
|
|
eventfld.long 0x08 6. " BFINTFL[6] ,CP A buffer full interrupt flag 6" "No interrupt,Interrupt"
|
|
newline
|
|
eventfld.long 0x08 5. " BFINTFL[5] ,CP B buffer full interrupt flag 5" "No interrupt,Interrupt"
|
|
eventfld.long 0x08 4. " BFINTFL[4] ,CP A buffer full interrupt flag 4" "No interrupt,Interrupt"
|
|
newline
|
|
eventfld.long 0x08 3. " BFINTFL[3] ,CP B buffer full interrupt flag 3" "No interrupt,Interrupt"
|
|
eventfld.long 0x08 2. " BFINTFL[2] ,CP A buffer full interrupt flag 2" "No interrupt,Interrupt"
|
|
newline
|
|
eventfld.long 0x08 1. " BFINTFL[1] ,CP B buffer full interrupt flag 1" "No interrupt,Interrupt"
|
|
eventfld.long 0x08 0. " BFINTFL[0] ,CP A buffer full interrupt flag 0" "No interrupt,Interrupt"
|
|
line.long 0x0C "BERINTFL,BER Interrupt Flag Register"
|
|
eventfld.long 0x0C 15. " BERINTFL[15] ,CP B bus error interrupt flag 15" "No interrupt,Interrupt"
|
|
eventfld.long 0x0C 14. " BERINTFL[14] ,CP A bus error interrupt flag 14" "No interrupt,Interrupt"
|
|
newline
|
|
eventfld.long 0x0C 13. " BERINTFL[13] ,CP B bus error interrupt flag 13" "No interrupt,Interrupt"
|
|
eventfld.long 0x0C 12. " BERINTFL[12] ,CP A bus error interrupt flag 12" "No interrupt,Interrupt"
|
|
newline
|
|
eventfld.long 0x0C 11. " BERINTFL[11] ,CP B bus error interrupt flag 11" "No interrupt,Interrupt"
|
|
eventfld.long 0x0C 10. " BERINTFL[10] ,CP A bus error interrupt flag 10" "No interrupt,Interrupt"
|
|
newline
|
|
eventfld.long 0x0C 9. " BERINTFL[9] ,CP B bus error interrupt flag 9" "No interrupt,Interrupt"
|
|
eventfld.long 0x0C 8. " BERINTFL[8] ,CP A bus error interrupt flag 8" "No interrupt,Interrupt"
|
|
newline
|
|
eventfld.long 0x0C 7. " BERINTFL[7] ,CP B bus error interrupt flag 7" "No interrupt,Interrupt"
|
|
eventfld.long 0x0C 6. " BERINTFL[6] ,CP A bus error interrupt flag 6" "No interrupt,Interrupt"
|
|
newline
|
|
eventfld.long 0x0C 5. " BERINTFL[5] ,CP B bus error interrupt flag 5" "No interrupt,Interrupt"
|
|
eventfld.long 0x0C 4. " BERINTFL[4] ,CP A bus error interrupt flag 4" "No interrupt,Interrupt"
|
|
newline
|
|
eventfld.long 0x0C 3. " BERINTFL[3] ,CP B bus error interrupt flag 3" "No interrupt,Interrupt"
|
|
eventfld.long 0x0C 2. " BERINTFL[2] ,CP A bus error interrupt flag 2" "No interrupt,Interrupt"
|
|
newline
|
|
eventfld.long 0x0C 1. " BERINTFL[1] ,CP B bus error interrupt flag 1" "No interrupt,Interrupt"
|
|
eventfld.long 0x0C 0. " BERINTFL[0] ,CP A bus error interrupt flag 0" "No interrupt,Interrupt"
|
|
line.long 0x10 "MP1S,Memory Protection 1 Start Address"
|
|
line.long 0x14 "MP1E,Memory Protection 1 End Address"
|
|
line.long 0x18 "DCTRL,Debug Control Register"
|
|
sif (cpuis("TMS570LS0332")||cpuis("TMS570LS0432")||cpuis("TMS570LS1114*")||cpuis("TMS570LS1115*")||cpuis("TMS570LS1224*")||cpuis("TMS570LS1225*")||cpuis("TMS570LS1227*"))
|
|
rbitfld.long 0x18 24.--27. " CPNUM ,CP number" "CP A of DCP0,CP B of DCP0,CP A of DCP1,,,,,,,,,,,,CP A of DCP7,CP B of DCP7"
|
|
elif cpuis("TMS570LS0232")||cpuis("TMS570LS0714*")||cpuis("TMS570LS0914*")||cpuis("TMS570LS3137-EP")
|
|
bitfld.long 0x18 24.--27. " CPNUM ,CP number" "CP A of DCP 0,CP B of DCP 0,CP A of DCP 1,CP B of DCP 1,CP A of DCP 2,CP B of DCP 2,CP A of DCP 3,CP B of DCP 3,CP A of DCP 4,CP B of DCP 4,CP A of DCP 5,CP B of DCP 5,CP A of DCP 6,CP B of DCP 6,CP A of DCP 7,CP B of DCP 7"
|
|
else
|
|
bitfld.long 0x18 24.--27. " CPNUM ,CP number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
newline
|
|
eventfld.long 0x18 16. " HTUDBGS ,HTU debug status" "Not detected,Detected"
|
|
bitfld.long 0x18 0. " DBREN ,Debug request enable" "Disabled,Enabled"
|
|
line.long 0x1C "WPR,Watch Point Register"
|
|
line.long 0x20 "WMR,Watch Mask Register"
|
|
rgroup.long 0x60++0x03
|
|
line.long 0x00 "ID,Module Identification Register"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CLASS ,Module class"
|
|
hexmask.long.byte 0x00 8.--15. 1. " TYPE ,Subtype within a class"
|
|
hexmask.long.byte 0x00 0.--7. 1. " REV ,Module revision number"
|
|
group.long 0x64++0x07
|
|
line.long 0x0 "PCR,Parity Control Register"
|
|
bitfld.long 0x00 16. " COPE , Continue on parity error" "Stopped,Continued"
|
|
bitfld.long 0x00 8. " TEST ,Test" "Not mapped,Mapped"
|
|
bitfld.long 0x00 0.--3. " PARITY_ENA ,Enable/disable parity checking" "Enabled,Enabled,Enabled,Enabled,Enabled,Disabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled"
|
|
line.long 0x04 "PAR,Parity Address Register"
|
|
eventfld.long 0x04 16. " PEFT ,Parity Error fault flag" "Not detected,Detected"
|
|
hexmask.long.word 0x04 0.--8. 1. " PAOFF ,Parity error address offset"
|
|
group.long 0x70++0x0B
|
|
line.long 0x00 "MPCS,Memory Protection Control and Status Register"
|
|
sif cpuis("TMS570LS0232")||cpuis("TMS570LS0714*")||cpuis("TMS570LS0914*")||cpuis("TMS570LS3137-EP")
|
|
rbitfld.long 0x00 24.--27. " CPNUM0 ,CP number" "CP A of DCP 0,CP B of DCP 0,CP A of DCP 1,CP B of DCP 1,CP A of DCP 2,CP B of DCP 2,CP A of DCP 3,CP B of DCP 3,CP A of DCP 4,CP B of DCP 4,CP A of DCP 5,CP B of DCP 5,CP A of DCP 6,CP B of DCP 6,CP A of DCP 7,CP B of DCP 7"
|
|
else
|
|
bitfld.long 0x00 24.--27. " CPNUM0 ,CP number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
newline
|
|
eventfld.long 0x00 17. " MPEFT1 ,Memory protection error fault flag" "Not detected,Detected"
|
|
eventfld.long 0x00 16. " MPEFT0 ,Memory protection error fault flag" "Not detected,Detected"
|
|
newline
|
|
sif (cpuis("TMS570LS0332")||cpuis("TMS570LS0432")||cpuis("TMS570LS1114*")||cpuis("TMS570LS1115*")||cpuis("TMS570LS1224*")||cpuis("TMS570LS1225*")||cpuis("TMS570LS1227*"))
|
|
rbitfld.long 0x00 8.--11. " CPNUM1 ,CP number" "CP A of DCP0,CP B of DCP0,CP A of DCP1,,,,,,,,,,,,CP A of DCP7,CP B of DCP7"
|
|
elif cpuis("TMS570LS0232")||cpuis("TMS570LS0714*")||cpuis("TMS570LS0914*")||cpuis("TMS570LS3137-EP")
|
|
rbitfld.long 0x00 8.--11. " CPNUM1 ,CP number" "CP A of DCP 0,CP B of DCP 0,CP A of DCP 1,CP B of DCP 1,CP A of DCP 2,CP B of DCP 2,CP A of DCP 3,CP B of DCP 3,CP A of DCP 4,CP B of DCP 4,CP A of DCP 5,CP B of DCP 5,CP A of DCP 6,CP B of DCP 6,CP A of DCP 7,CP B of DCP 7"
|
|
else
|
|
bitfld.long 0x00 8.--11. " CPNUM1 ,CP number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
newline
|
|
bitfld.long 0x00 5. " INTENA01 ,Interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " ACCR01 ,Access rights HTU" "Allowed,Forbidden"
|
|
newline
|
|
bitfld.long 0x00 3. " REG01ENA ,Region enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " INTENA0 ,Interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " ACCR ,Access rights HTU" "Allowed,Forbidden"
|
|
newline
|
|
bitfld.long 0x00 0. " REG0ENA ,Region enable" "Disabled,Enabled"
|
|
line.long 0x04 "MP0S,Memory Protection Start Address Register"
|
|
line.long 0x08 "MP0E,Memory Protection End Address Register"
|
|
sif (cpuis("TMS570LS10106-PGE")||cpuis("TMS570LS10106-ZWT")||cpuis("TMS570LS10116-PGE")||cpuis("TMS570LS10116-ZWT")||cpuis("TMS570LS10206-PGE")||cpuis("TMS570LS10206-ZWT")||cpuis("TMS570LS10216-PGE")||cpuis("TMS570LS10216-ZWT")||cpuis("TMS570LS20206-PGE")||cpuis("TMS570LS20206-ZWT")||cpuis("TMS570LS20216-PGE")||cpuis("TMS570LS20216-ZWT")||cpuis("RM48L952-PGE")||cpuis("RM48L952-ZWT")||cpuis("RM48L950-PGE")||cpuis("RM48L950-ZWT")||cpuis("RM48L940-ZWT")||cpuis("RM48L940-PGE")||cpuis("RM48L930-ZWT")||cpuis("RM48L930-PGE")||cpuis("RM48L750-ZWT")||cpuis("RM48L750-PGE")||cpuis("RM48L740-ZWT")||cpuis("RM48L740-PGE")||cpuis("RM48L730-ZWT")||cpuis("RM48L730-PGE")||cpuis("RM48L550-PGE")||cpuis("RM48L540-ZWT")||cpuis("RM48L540-PGE")||cpuis("RM48L530-ZWT")||cpuis("RM48L530-PGE")||cpuis("RM46L852-PGE")||cpuis("RM46L852-ZWT")||cpuis("RM46L850-PGE")||cpuis("RM46L850-ZWT")||cpuis("RM46L840-ZWT")||cpuis("RM46L840-PGE")||cpuis("RM46L830-ZWT")||cpuis("RM46L830-PGE")||cpuis("RM46L450-ZWT")||cpuis("RM46L450-PGE")||cpuis("RM46L440-ZWT")||cpuis("RM46L440-PGE")||cpuis("RM46L430-ZWT")||cpuis("RM46L430-PGE")||cpuis("RM42L432")||cpuis("RM48L550-ZWT")||cpuis("TMS570LC4357")||cpuis("TMS570LS0332")||cpuis("TMS570LS0432")||cpuis("TMS570LS1114*")||cpuis("TMS570LS1115*")||cpuis("TMS570LS1224*")||cpuis("TMS570LS1225*")||cpuis("TMS570LS1227*")||cpuis("TMS570LS0232")||cpuis("TMS570LS0714*")||cpuis("TMS570LS0914*")||cpuis("TMS570LS3137-EP"))
|
|
tree "Double Control Packet Configuration Memory"
|
|
base ad:0xFF4C0000
|
|
sif !cpuis("TMS570LS0714*")&&!cpuis("TMS570LS0914*")&&!cpuis("RM46L852*")&&!cpuis("TMS570LS3137-EP")
|
|
group.long 0x00++0xF
|
|
line.long 0x00 "IFADDRA,Initial main memory address Control Packet A"
|
|
line.long 0x04 "IFADDRB,Initial main memory address Control Packet B"
|
|
line.long 0x08 "IHADDRCT,Initial NHET address and control"
|
|
bitfld.long 0x08 23. " DIR ,Direction of transfer (read->write)" "NHET->Main,Main->NHET"
|
|
bitfld.long 0x08 22. " SIZE ,Size of transferred data" "32-bit,64-bit"
|
|
newline
|
|
bitfld.long 0x08 21. " ADDMH ,Addressing mode NHET address (increment value)" "16 bytes,8 bytes"
|
|
bitfld.long 0x08 20. " ADDMF ,Addressing mode main memory address" "Post-increment,Constant"
|
|
newline
|
|
bitfld.long 0x08 18.--19. " TMBA ,Transfer mode for buffer A" "One Shot,Circular,Auto Switch,Auto Switch"
|
|
bitfld.long 0x08 16.--17. " TMBB ,Transfer mode for buffer B" "One Shot,Circular,Auto Switch,Auto Switch"
|
|
newline
|
|
hexmask.long.word 0x08 2.--12. 0x4 " IHADDR ,Initial NHET address"
|
|
line.long 0x0C "ITCOUNT,Initial transfer count"
|
|
bitfld.long 0x0C 16.--20. " IETCOUNT ,Initial element transfer count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
hexmask.long.byte 0x0C 0.--7. 1. " IFTCOUNT ,Initial frame transfer count"
|
|
group.long 0x100++0xB
|
|
line.long 0x00 "CFADDRA,Current main memory address Control Packet A"
|
|
line.long 0x04 "CFADDRB,Current main memory address Control Packet B"
|
|
line.long 0x08 "CFCOUNT,Current frame count"
|
|
hexmask.long.byte 0x08 16.--23. 1. " CFTCTA ,Current frame transfer count for CP A"
|
|
hexmask.long.byte 0x08 0.--7. 1. " CFTCTB ,Current frame transfer count for CP B"
|
|
else
|
|
width 15.
|
|
group.long 0x0++0x0F "DCP0"
|
|
line.long 0x00 "DCP0IFADDRA,DCP0 Initial main memory address Control Packet A"
|
|
line.long 0x04 "DCP0IFADDRB,DCP0 Initial main memory address Control Packet B"
|
|
line.long 0x08 "DCP0IHADDRCT,DCP0 Initial NHET address and control"
|
|
bitfld.long 0x08 23. " DIR ,Direction of transfer (read->write)" "NHET->Main,Main->NHET"
|
|
bitfld.long 0x08 22. " SIZE ,Size of transferred data" "32-bit,64-bit"
|
|
newline
|
|
bitfld.long 0x08 21. " ADDMH ,Addressing mode NHET address (Increment value)" "16 bytes,8 bytes"
|
|
bitfld.long 0x08 20. " ADDMF ,Addressing mode main memory address" "Post-increment,Constant"
|
|
newline
|
|
bitfld.long 0x08 18.--19. " TMBA ,Transfer mode for buffer A" "One Shot,Circular,Auto Switch,Auto Switch"
|
|
bitfld.long 0x08 16.--17. " TMBB ,Transfer mode for buffer B" "One Shot,Circular,Auto Switch,Auto Switch"
|
|
newline
|
|
hexmask.long.word 0x08 2.--12. 0x4 " IHADDR ,Initial NHET address"
|
|
line.long 0x0C "DCP0ITCOUNT,DCP0 Initial transfer count"
|
|
bitfld.long 0x0C 16.--20. " IETCOUNT ,Initial element transfer count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
hexmask.long.byte 0x0C 0.--7. 1. " IFTCOUNT ,Initial frame transfer count"
|
|
group.long (0x0+0x100)++0xB
|
|
line.long 0x00 "DCP0CFADDRA,DCP0 Current main memory address control packet A"
|
|
line.long 0x04 "DCP0CFADDRB,DCP0 Current main memory address control packet B"
|
|
line.long 0x08 "DCP0CFCOUNT,DCP0 Current frame count"
|
|
hexmask.long.byte 0x08 16.--23. 1. " CFTCTA ,Current frame transfer count for CP A"
|
|
hexmask.long.byte 0x08 0.--7. 1. " CFTCTB ,Current frame transfer count for CP B"
|
|
group.long 0x10++0x0F "DCP1"
|
|
line.long 0x00 "DCP1IFADDRA,DCP1 Initial main memory address Control Packet A"
|
|
line.long 0x04 "DCP1IFADDRB,DCP1 Initial main memory address Control Packet B"
|
|
line.long 0x08 "DCP1IHADDRCT,DCP1 Initial NHET address and control"
|
|
bitfld.long 0x08 23. " DIR ,Direction of transfer (read->write)" "NHET->Main,Main->NHET"
|
|
bitfld.long 0x08 22. " SIZE ,Size of transferred data" "32-bit,64-bit"
|
|
newline
|
|
bitfld.long 0x08 21. " ADDMH ,Addressing mode NHET address (Increment value)" "16 bytes,8 bytes"
|
|
bitfld.long 0x08 20. " ADDMF ,Addressing mode main memory address" "Post-increment,Constant"
|
|
newline
|
|
bitfld.long 0x08 18.--19. " TMBA ,Transfer mode for buffer A" "One Shot,Circular,Auto Switch,Auto Switch"
|
|
bitfld.long 0x08 16.--17. " TMBB ,Transfer mode for buffer B" "One Shot,Circular,Auto Switch,Auto Switch"
|
|
newline
|
|
hexmask.long.word 0x08 2.--12. 0x4 " IHADDR ,Initial NHET address"
|
|
line.long 0x0C "DCP1ITCOUNT,DCP1 Initial transfer count"
|
|
bitfld.long 0x0C 16.--20. " IETCOUNT ,Initial element transfer count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
hexmask.long.byte 0x0C 0.--7. 1. " IFTCOUNT ,Initial frame transfer count"
|
|
group.long (0x10+0x100)++0xB
|
|
line.long 0x00 "DCP1CFADDRA,DCP1 Current main memory address control packet A"
|
|
line.long 0x04 "DCP1CFADDRB,DCP1 Current main memory address control packet B"
|
|
line.long 0x08 "DCP1CFCOUNT,DCP1 Current frame count"
|
|
hexmask.long.byte 0x08 16.--23. 1. " CFTCTA ,Current frame transfer count for CP A"
|
|
hexmask.long.byte 0x08 0.--7. 1. " CFTCTB ,Current frame transfer count for CP B"
|
|
group.long 0x20++0x0F "DCP2"
|
|
line.long 0x00 "DCP2IFADDRA,DCP2 Initial main memory address Control Packet A"
|
|
line.long 0x04 "DCP2IFADDRB,DCP2 Initial main memory address Control Packet B"
|
|
line.long 0x08 "DCP2IHADDRCT,DCP2 Initial NHET address and control"
|
|
bitfld.long 0x08 23. " DIR ,Direction of transfer (read->write)" "NHET->Main,Main->NHET"
|
|
bitfld.long 0x08 22. " SIZE ,Size of transferred data" "32-bit,64-bit"
|
|
newline
|
|
bitfld.long 0x08 21. " ADDMH ,Addressing mode NHET address (Increment value)" "16 bytes,8 bytes"
|
|
bitfld.long 0x08 20. " ADDMF ,Addressing mode main memory address" "Post-increment,Constant"
|
|
newline
|
|
bitfld.long 0x08 18.--19. " TMBA ,Transfer mode for buffer A" "One Shot,Circular,Auto Switch,Auto Switch"
|
|
bitfld.long 0x08 16.--17. " TMBB ,Transfer mode for buffer B" "One Shot,Circular,Auto Switch,Auto Switch"
|
|
newline
|
|
hexmask.long.word 0x08 2.--12. 0x4 " IHADDR ,Initial NHET address"
|
|
line.long 0x0C "DCP2ITCOUNT,DCP2 Initial transfer count"
|
|
bitfld.long 0x0C 16.--20. " IETCOUNT ,Initial element transfer count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
hexmask.long.byte 0x0C 0.--7. 1. " IFTCOUNT ,Initial frame transfer count"
|
|
group.long (0x20+0x100)++0xB
|
|
line.long 0x00 "DCP2CFADDRA,DCP2 Current main memory address control packet A"
|
|
line.long 0x04 "DCP2CFADDRB,DCP2 Current main memory address control packet B"
|
|
line.long 0x08 "DCP2CFCOUNT,DCP2 Current frame count"
|
|
hexmask.long.byte 0x08 16.--23. 1. " CFTCTA ,Current frame transfer count for CP A"
|
|
hexmask.long.byte 0x08 0.--7. 1. " CFTCTB ,Current frame transfer count for CP B"
|
|
group.long 0x30++0x0F "DCP3"
|
|
line.long 0x00 "DCP3IFADDRA,DCP3 Initial main memory address Control Packet A"
|
|
line.long 0x04 "DCP3IFADDRB,DCP3 Initial main memory address Control Packet B"
|
|
line.long 0x08 "DCP3IHADDRCT,DCP3 Initial NHET address and control"
|
|
bitfld.long 0x08 23. " DIR ,Direction of transfer (read->write)" "NHET->Main,Main->NHET"
|
|
bitfld.long 0x08 22. " SIZE ,Size of transferred data" "32-bit,64-bit"
|
|
newline
|
|
bitfld.long 0x08 21. " ADDMH ,Addressing mode NHET address (Increment value)" "16 bytes,8 bytes"
|
|
bitfld.long 0x08 20. " ADDMF ,Addressing mode main memory address" "Post-increment,Constant"
|
|
newline
|
|
bitfld.long 0x08 18.--19. " TMBA ,Transfer mode for buffer A" "One Shot,Circular,Auto Switch,Auto Switch"
|
|
bitfld.long 0x08 16.--17. " TMBB ,Transfer mode for buffer B" "One Shot,Circular,Auto Switch,Auto Switch"
|
|
newline
|
|
hexmask.long.word 0x08 2.--12. 0x4 " IHADDR ,Initial NHET address"
|
|
line.long 0x0C "DCP3ITCOUNT,DCP3 Initial transfer count"
|
|
bitfld.long 0x0C 16.--20. " IETCOUNT ,Initial element transfer count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
hexmask.long.byte 0x0C 0.--7. 1. " IFTCOUNT ,Initial frame transfer count"
|
|
group.long (0x30+0x100)++0xB
|
|
line.long 0x00 "DCP3CFADDRA,DCP3 Current main memory address control packet A"
|
|
line.long 0x04 "DCP3CFADDRB,DCP3 Current main memory address control packet B"
|
|
line.long 0x08 "DCP3CFCOUNT,DCP3 Current frame count"
|
|
hexmask.long.byte 0x08 16.--23. 1. " CFTCTA ,Current frame transfer count for CP A"
|
|
hexmask.long.byte 0x08 0.--7. 1. " CFTCTB ,Current frame transfer count for CP B"
|
|
group.long 0x40++0x0F "DCP4"
|
|
line.long 0x00 "DCP4IFADDRA,DCP4 Initial main memory address Control Packet A"
|
|
line.long 0x04 "DCP4IFADDRB,DCP4 Initial main memory address Control Packet B"
|
|
line.long 0x08 "DCP4IHADDRCT,DCP4 Initial NHET address and control"
|
|
bitfld.long 0x08 23. " DIR ,Direction of transfer (read->write)" "NHET->Main,Main->NHET"
|
|
bitfld.long 0x08 22. " SIZE ,Size of transferred data" "32-bit,64-bit"
|
|
newline
|
|
bitfld.long 0x08 21. " ADDMH ,Addressing mode NHET address (Increment value)" "16 bytes,8 bytes"
|
|
bitfld.long 0x08 20. " ADDMF ,Addressing mode main memory address" "Post-increment,Constant"
|
|
newline
|
|
bitfld.long 0x08 18.--19. " TMBA ,Transfer mode for buffer A" "One Shot,Circular,Auto Switch,Auto Switch"
|
|
bitfld.long 0x08 16.--17. " TMBB ,Transfer mode for buffer B" "One Shot,Circular,Auto Switch,Auto Switch"
|
|
newline
|
|
hexmask.long.word 0x08 2.--12. 0x4 " IHADDR ,Initial NHET address"
|
|
line.long 0x0C "DCP4ITCOUNT,DCP4 Initial transfer count"
|
|
bitfld.long 0x0C 16.--20. " IETCOUNT ,Initial element transfer count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
hexmask.long.byte 0x0C 0.--7. 1. " IFTCOUNT ,Initial frame transfer count"
|
|
group.long (0x40+0x100)++0xB
|
|
line.long 0x00 "DCP4CFADDRA,DCP4 Current main memory address control packet A"
|
|
line.long 0x04 "DCP4CFADDRB,DCP4 Current main memory address control packet B"
|
|
line.long 0x08 "DCP4CFCOUNT,DCP4 Current frame count"
|
|
hexmask.long.byte 0x08 16.--23. 1. " CFTCTA ,Current frame transfer count for CP A"
|
|
hexmask.long.byte 0x08 0.--7. 1. " CFTCTB ,Current frame transfer count for CP B"
|
|
group.long 0x50++0x0F "DCP5"
|
|
line.long 0x00 "DCP5IFADDRA,DCP5 Initial main memory address Control Packet A"
|
|
line.long 0x04 "DCP5IFADDRB,DCP5 Initial main memory address Control Packet B"
|
|
line.long 0x08 "DCP5IHADDRCT,DCP5 Initial NHET address and control"
|
|
bitfld.long 0x08 23. " DIR ,Direction of transfer (read->write)" "NHET->Main,Main->NHET"
|
|
bitfld.long 0x08 22. " SIZE ,Size of transferred data" "32-bit,64-bit"
|
|
newline
|
|
bitfld.long 0x08 21. " ADDMH ,Addressing mode NHET address (Increment value)" "16 bytes,8 bytes"
|
|
bitfld.long 0x08 20. " ADDMF ,Addressing mode main memory address" "Post-increment,Constant"
|
|
newline
|
|
bitfld.long 0x08 18.--19. " TMBA ,Transfer mode for buffer A" "One Shot,Circular,Auto Switch,Auto Switch"
|
|
bitfld.long 0x08 16.--17. " TMBB ,Transfer mode for buffer B" "One Shot,Circular,Auto Switch,Auto Switch"
|
|
newline
|
|
hexmask.long.word 0x08 2.--12. 0x4 " IHADDR ,Initial NHET address"
|
|
line.long 0x0C "DCP5ITCOUNT,DCP5 Initial transfer count"
|
|
bitfld.long 0x0C 16.--20. " IETCOUNT ,Initial element transfer count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
hexmask.long.byte 0x0C 0.--7. 1. " IFTCOUNT ,Initial frame transfer count"
|
|
group.long (0x50+0x100)++0xB
|
|
line.long 0x00 "DCP5CFADDRA,DCP5 Current main memory address control packet A"
|
|
line.long 0x04 "DCP5CFADDRB,DCP5 Current main memory address control packet B"
|
|
line.long 0x08 "DCP5CFCOUNT,DCP5 Current frame count"
|
|
hexmask.long.byte 0x08 16.--23. 1. " CFTCTA ,Current frame transfer count for CP A"
|
|
hexmask.long.byte 0x08 0.--7. 1. " CFTCTB ,Current frame transfer count for CP B"
|
|
group.long 0x60++0x0F "DCP6"
|
|
line.long 0x00 "DCP6IFADDRA,DCP6 Initial main memory address Control Packet A"
|
|
line.long 0x04 "DCP6IFADDRB,DCP6 Initial main memory address Control Packet B"
|
|
line.long 0x08 "DCP6IHADDRCT,DCP6 Initial NHET address and control"
|
|
bitfld.long 0x08 23. " DIR ,Direction of transfer (read->write)" "NHET->Main,Main->NHET"
|
|
bitfld.long 0x08 22. " SIZE ,Size of transferred data" "32-bit,64-bit"
|
|
newline
|
|
bitfld.long 0x08 21. " ADDMH ,Addressing mode NHET address (Increment value)" "16 bytes,8 bytes"
|
|
bitfld.long 0x08 20. " ADDMF ,Addressing mode main memory address" "Post-increment,Constant"
|
|
newline
|
|
bitfld.long 0x08 18.--19. " TMBA ,Transfer mode for buffer A" "One Shot,Circular,Auto Switch,Auto Switch"
|
|
bitfld.long 0x08 16.--17. " TMBB ,Transfer mode for buffer B" "One Shot,Circular,Auto Switch,Auto Switch"
|
|
newline
|
|
hexmask.long.word 0x08 2.--12. 0x4 " IHADDR ,Initial NHET address"
|
|
line.long 0x0C "DCP6ITCOUNT,DCP6 Initial transfer count"
|
|
bitfld.long 0x0C 16.--20. " IETCOUNT ,Initial element transfer count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
hexmask.long.byte 0x0C 0.--7. 1. " IFTCOUNT ,Initial frame transfer count"
|
|
group.long (0x60+0x100)++0xB
|
|
line.long 0x00 "DCP6CFADDRA,DCP6 Current main memory address control packet A"
|
|
line.long 0x04 "DCP6CFADDRB,DCP6 Current main memory address control packet B"
|
|
line.long 0x08 "DCP6CFCOUNT,DCP6 Current frame count"
|
|
hexmask.long.byte 0x08 16.--23. 1. " CFTCTA ,Current frame transfer count for CP A"
|
|
hexmask.long.byte 0x08 0.--7. 1. " CFTCTB ,Current frame transfer count for CP B"
|
|
group.long 0x70++0x0F "DCP7"
|
|
line.long 0x00 "DCP7IFADDRA,DCP7 Initial main memory address Control Packet A"
|
|
line.long 0x04 "DCP7IFADDRB,DCP7 Initial main memory address Control Packet B"
|
|
line.long 0x08 "DCP7IHADDRCT,DCP7 Initial NHET address and control"
|
|
bitfld.long 0x08 23. " DIR ,Direction of transfer (read->write)" "NHET->Main,Main->NHET"
|
|
bitfld.long 0x08 22. " SIZE ,Size of transferred data" "32-bit,64-bit"
|
|
newline
|
|
bitfld.long 0x08 21. " ADDMH ,Addressing mode NHET address (Increment value)" "16 bytes,8 bytes"
|
|
bitfld.long 0x08 20. " ADDMF ,Addressing mode main memory address" "Post-increment,Constant"
|
|
newline
|
|
bitfld.long 0x08 18.--19. " TMBA ,Transfer mode for buffer A" "One Shot,Circular,Auto Switch,Auto Switch"
|
|
bitfld.long 0x08 16.--17. " TMBB ,Transfer mode for buffer B" "One Shot,Circular,Auto Switch,Auto Switch"
|
|
newline
|
|
hexmask.long.word 0x08 2.--12. 0x4 " IHADDR ,Initial NHET address"
|
|
line.long 0x0C "DCP7ITCOUNT,DCP7 Initial transfer count"
|
|
bitfld.long 0x0C 16.--20. " IETCOUNT ,Initial element transfer count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
hexmask.long.byte 0x0C 0.--7. 1. " IFTCOUNT ,Initial frame transfer count"
|
|
group.long (0x70+0x100)++0xB
|
|
line.long 0x00 "DCP7CFADDRA,DCP7 Current main memory address control packet A"
|
|
line.long 0x04 "DCP7CFADDRB,DCP7 Current main memory address control packet B"
|
|
line.long 0x08 "DCP7CFCOUNT,DCP7 Current frame count"
|
|
hexmask.long.byte 0x08 16.--23. 1. " CFTCTA ,Current frame transfer count for CP A"
|
|
hexmask.long.byte 0x08 0.--7. 1. " CFTCTB ,Current frame transfer count for CP B"
|
|
endif
|
|
tree.end
|
|
endif
|
|
sif cpuis("TMS570LS0232")||cpuis("TMS570LS0714*")||cpuis("TMS570LS0914*")
|
|
endian.le
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
tree.end
|
|
else
|
|
tree "HTU (High-End Timer Transfer Unit Module)"
|
|
base ad:0xFFF7A400
|
|
sif cpuis("TMS570LS0232")||cpuis("TMS570LS0714*")||cpuis("TMS570LS0914*")
|
|
endian.be
|
|
endif
|
|
width 10.
|
|
group.long 0x00++0x07
|
|
line.long 0x00 "GC,Global Control Register"
|
|
bitfld.long 0x00 24. " VBUS_HOLD ,Hold the VBUS bus" "Not held,Held"
|
|
bitfld.long 0x00 16. " HTUEN ,Transfer unit enable bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " DEBM ,Debug mode" "Suspended,Continue"
|
|
newline
|
|
bitfld.long 0x00 0. " HTU_RES ,HTU software reset" "No reset,Reset"
|
|
line.long 0x04 "CPENA,Control Packet Enable Register"
|
|
bitfld.long 0x04 14.--15. " CPENA7 ,CP enable bits 7 (CP B/CP A)" "Disabled,Disabled/Enabled,Enabled/Disabled,Disabled"
|
|
bitfld.long 0x04 12.--13. " CPENA6 ,CP enable bits 6 (CP B/CP A)" "Disabled,Disabled/Enabled,Enabled/Disabled,Disabled"
|
|
newline
|
|
bitfld.long 0x04 10.--11. " CPENA5 ,CP enable bits 5 (CP B/CP A)" "Disabled,Disabled/Enabled,Enabled/Disabled,Disabled"
|
|
bitfld.long 0x04 8.--9. " CPENA4 ,CP enable bits 4 (CP B/CP A)" "Disabled,Disabled/Enabled,Enabled/Disabled,Disabled"
|
|
newline
|
|
bitfld.long 0x04 6.--7. " CPENA3 ,CP enable bits 3 (CP B/CP A)" "Disabled,Disabled/Enabled,Enabled/Disabled,Disabled"
|
|
bitfld.long 0x04 4.--5. " CPENA2 ,CP enable bits 2 (CP B/CP A)" "Disabled,Disabled/Enabled,Enabled/Disabled,Disabled"
|
|
newline
|
|
bitfld.long 0x04 2.--3. " CPENA1 ,CP enable bits 1 (CP B/CP A)" "Disabled,Disabled/Enabled,Enabled/Disabled,Disabled"
|
|
bitfld.long 0x04 0.--1. " CPENA0 ,CP enable bits 0 (CP B/CP A)" "Disabled,Disabled/Enabled,Enabled/Disabled,Disabled"
|
|
group.long 0x8++0x03
|
|
line.long 0x00 "BUSY0,Control Packet (CP) Busy Register 0"
|
|
eventfld.long 0x00 24. " BUSY0A ,Busy flag for CP A of double CP 0" "Low,High"
|
|
eventfld.long 0x00 16. " BUSY0B ,Busy flag for CP B of double CP 0" "Low,High"
|
|
eventfld.long 0x00 8. " BUSY1A ,Busy flag for CP A of double CP 1" "Low,High"
|
|
eventfld.long 0x00 0. " BUSY1B ,Busy flag for CP B of double CP 1" "Low,High"
|
|
group.long 0xC++0x03
|
|
line.long 0x00 "BUSY1,Control Packet (CP) Busy Register 1"
|
|
eventfld.long 0x00 24. " BUSY2A ,Busy flag for CP A of double CP 2" "Low,High"
|
|
eventfld.long 0x00 16. " BUSY2B ,Busy flag for CP B of double CP 2" "Low,High"
|
|
eventfld.long 0x00 8. " BUSY3A ,Busy flag for CP A of double CP 3" "Low,High"
|
|
eventfld.long 0x00 0. " BUSY3B ,Busy flag for CP B of double CP 3" "Low,High"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "BUSY2,Control Packet (CP) Busy Register 2"
|
|
eventfld.long 0x00 24. " BUSY4A ,Busy flag for CP A of double CP 4" "Low,High"
|
|
eventfld.long 0x00 16. " BUSY4B ,Busy flag for CP B of double CP 4" "Low,High"
|
|
eventfld.long 0x00 8. " BUSY5A ,Busy flag for CP A of double CP 5" "Low,High"
|
|
eventfld.long 0x00 0. " BUSY5B ,Busy flag for CP B of double CP 5" "Low,High"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "BUSY3,Control Packet (CP) Busy Register 3"
|
|
eventfld.long 0x00 24. " BUSY6A ,Busy flag for CP A of double CP 6" "Low,High"
|
|
eventfld.long 0x00 16. " BUSY6B ,Busy flag for CP B of double CP 6" "Low,High"
|
|
eventfld.long 0x00 8. " BUSY7A ,Busy flag for CP A of double CP 7" "Low,High"
|
|
eventfld.long 0x00 0. " BUSY7B ,Busy flag for CP B of double CP 7" "Low,High"
|
|
sif cpuis("TMS570LS0232")||cpuis("TMS570LS0714*")||cpuis("TMS570LS0914*")||cpuis("TMS570LS3137-EP")
|
|
group.long 0x18++0x3
|
|
line.long 0x00 "ACPE,Active Control Packet Register"
|
|
eventfld.long 0x00 31. " ERRF ,Error flag" "No error,Error"
|
|
rbitfld.long 0x00 24.--28. " ERRETC ,Error element transfer counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
rbitfld.long 0x00 16.--19. " ERRCPN ,Error control packet number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rbitfld.long 0x00 15. " TIPF ,Transfer in progress flag" "Not active,Active"
|
|
newline
|
|
rbitfld.long 0x00 14. " BUS_BUSY ,VBUSP bus is busy" "Not busy,Busy"
|
|
rbitfld.long 0x00 8.--12. " CETCOUNT ,Current element transfer counter" "No transfer,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
rbitfld.long 0x00 0.--3. " NACP ,Number of active control packet" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
else
|
|
group.long 0x18++0x3
|
|
line.long 0x00 "ACPE,Active Control Packet Register"
|
|
eventfld.long 0x00 31. " ERRF ,Error flag" "No error,Error"
|
|
bitfld.long 0x00 24.--28. " ERRETC ,Error element transfer counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
hexmask.long.byte 0x00 16.--19. 1. " ERRCPN ,Error control packet number"
|
|
bitfld.long 0x00 15. " TIPF ,Transfer in progress flag" "Not active,Active"
|
|
newline
|
|
bitfld.long 0x00 14. " BUS_BUSY ,VBUSP bus is busy" "Not busy,Busy"
|
|
bitfld.long 0x00 8.--12. " CETCOUNT ,Current element transfer counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
hexmask.long.byte 0x00 0.--3. 1. " NACP ,Number of active control packet"
|
|
endif
|
|
newline
|
|
width 16.
|
|
group.long 0x20++0x07
|
|
line.long 0x00 "RLBECTRL,Request Lost and Bus Error Control Register"
|
|
bitfld.long 0x00 16. " BERINTENA ,Bus error interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " CORL ,Continue on request lost error" "Lost,Continue"
|
|
bitfld.long 0x00 0. " RLINTENA ,Request lost interrupt enable bit" "Disabled,Enabled"
|
|
line.long 0x04 "BFINTS_SET/CLR,Buffer Full Interrupt Enable Set/Clr Register"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x08 15. " BFINTENA[15] ,CP B Buffer full interrupt enable bit 15" "Disabled,Enabled"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x08 14. " [14] ,CP A Buffer full interrupt enable Bit 14" "Disabled,Enabled"
|
|
setclrfld.long 0x04 13. 0x04 13. 0x08 13. " [13] ,CP B Bit 13" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x04 12. 0x04 12. 0x08 12. " [12] ,CP A Buffer Full Interrupt Enable Bit 12" "Disabled,Enabled"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x08 11. " [11] ,CP B buffer full interrupt enable bit 11" "Disabled,Enabled"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x08 10. " [10] ,CP A buffer full interrupt enable bit 10" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x04 9. 0x04 9. 0x08 9. " [9] ,CP B buffer full interrupt enable bit 9" "Disabled,Enabled"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x08 8. " [8] ,CP A buffer full interrupt enable bit 8" "Disabled,Enabled"
|
|
setclrfld.long 0x04 7. 0x04 7. 0x08 7. " [7] ,CP B buffer full interrupt enable bit 7" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x04 6. 0x04 6. 0x08 6. " [6] ,CP A buffer full interrupt enable bit 6" "Disabled,Enabled"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x08 5. " [5] ,CP B buffer full interrupt enable bit 5" "Disabled,Enabled"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x08 4. " [4] ,CP A buffer full interrupt enable bit 4" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x04 3. 0x04 3. 0x08 3. " [3] ,CP B buffer full interrupt enable bit 3" "Disabled,Enabled"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x08 2. " [2] ,CP A buffer full interrupt enable bit 2" "Disabled,Enabled"
|
|
setclrfld.long 0x04 1. 0x04 1. 0x08 1. " [1] ,CP B buffer full interrupt enable bit 1" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x04 0. 0x04 0. 0x08 0. " [0] ,CP A buffer full interrupt enable bit 0" "Disabled,Enabled"
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "INTMAP,Interrupt Mapping Register"
|
|
bitfld.long 0x00 16. " MAPSEL ,Interrupt mapping select bit" "Low,High"
|
|
bitfld.long 0x00 15. " CPINTMAP[15] ,CP B Interrupt mapping bit 15" "Line 0,Line 1"
|
|
bitfld.long 0x00 14. " [14] ,CP A Interrupt mapping bit 14" "Line 0,Line 1"
|
|
newline
|
|
bitfld.long 0x00 13. " [13] ,CP B Interrupt mapping bit 13" "Line 0,Line 1"
|
|
bitfld.long 0x00 12. " [12] ,CP A Interrupt mapping bit 12" "Line 0,Line 1"
|
|
bitfld.long 0x00 11. " [11] ,CP B Interrupt mapping bit 11" "Line 0,Line 1"
|
|
newline
|
|
bitfld.long 0x00 10. " [10] ,CP A Interrupt mapping bit 10" "Line 0,Line 1"
|
|
bitfld.long 0x00 9. " [9] ,CP B Interrupt mapping bit 9" "Line 0,Line 1"
|
|
bitfld.long 0x00 8. " [8] ,CP A Interrupt mapping bit 8" "Line 0,Line 1"
|
|
newline
|
|
bitfld.long 0x00 7. " [7] ,CP B Interrupt mapping bit 7" "Line 0,Line 1"
|
|
bitfld.long 0x00 6. " [6] ,CP A Interrupt mapping bit 6" "Line 0,Line 1"
|
|
bitfld.long 0x00 5. " [5] ,CP B Interrupt mapping bit 5" "Line 0,Line 1"
|
|
newline
|
|
bitfld.long 0x00 4. " [4] ,CP A Interrupt mapping bit 4" "Line 0,Line 1"
|
|
bitfld.long 0x00 3. " [3] ,CP B Interrupt mapping bit 3" "Line 0,Line 1"
|
|
bitfld.long 0x00 2. " [2] ,CP A Interrupt mapping bit 2" "Line 0,Line 1"
|
|
newline
|
|
bitfld.long 0x00 1. " [1] ,CP B Interrupt mapping bit 1" "Line 0,Line 1"
|
|
bitfld.long 0x00 0. " [0] ,CP A Interrupt mapping bit 0" "Line 0,Line 1"
|
|
newline
|
|
width 10.
|
|
hgroup.long 0x34++0x3
|
|
hide.long 0x0 "INTOFF0,Interrupt Offset Register 0"
|
|
in
|
|
hgroup.long 0x38++0x3
|
|
hide.long 0x0 "INTOFF1,Interrupt Offset Register 1"
|
|
in
|
|
newline
|
|
group.long 0x3C++0x23
|
|
line.long 0x00 "BIM,Buffer Initialization Mode Register"
|
|
bitfld.long 0x00 7. " BIM[7] ,Buffer initialization mode bit 7" "Normal,Special"
|
|
bitfld.long 0x00 6. " BIM[6] ,Buffer initialization mode bit 6" "Normal,Special"
|
|
bitfld.long 0x00 5. " BIM[5] ,Buffer initialization mode bit 5" "Normal,Special"
|
|
bitfld.long 0x00 4. " BIM[4] ,Buffer initialization mode bit 4" "Normal,Special"
|
|
newline
|
|
bitfld.long 0x00 3. " BIM[3] ,Buffer initialization mode bit 3" "Normal,Special"
|
|
bitfld.long 0x00 2. " BIM[2] ,Buffer initialization mode bit 2" "Normal,Special"
|
|
bitfld.long 0x00 1. " BIM[1] ,Buffer initialization mode bit 1" "Normal,Special"
|
|
bitfld.long 0x00 0. " BIM[0] ,Buffer initialization mode bit 0" "Normal,Special"
|
|
line.long 0x04 "RLOSTFL,Request Lost Flag Register"
|
|
eventfld.long 0x04 15. " CPRLFL[15] ,CP B request lost flag 15" "Not requested,Requested"
|
|
eventfld.long 0x04 14. " CPRLFL[14] ,CP A request lost flag 14" "Not requested,Requested"
|
|
newline
|
|
eventfld.long 0x04 13. " CPRLFL[13] ,CP B request lost flag 13" "Not requested,Requested"
|
|
eventfld.long 0x04 12. " CPRLFL[12] ,CP A request lost flag 12" "Not requested,Requested"
|
|
newline
|
|
eventfld.long 0x04 11. " CPRLFL[11] ,CP B request lost flag 11" "Not requested,Requested"
|
|
eventfld.long 0x04 10. " CPRLFL[10] ,CP A request lost flag 10" "Not requested,Requested"
|
|
newline
|
|
eventfld.long 0x04 9. " CPRLFL[9] ,CP B request lost flag 9" "Not requested,Requested"
|
|
eventfld.long 0x04 8. " CPRLFL[8] ,CP A request lost flag 8" "Not requested,Requested"
|
|
newline
|
|
eventfld.long 0x04 7. " CPRLFL[7] ,CP B request lost flag 7" "Not requested,Requested"
|
|
eventfld.long 0x04 6. " CPRLFL[6] ,CP A request lost flag 6" "Not requested,Requested"
|
|
newline
|
|
eventfld.long 0x04 5. " CPRLFL[5] ,CP B request lost flag 5" "Not requested,Requested"
|
|
eventfld.long 0x04 4. " CPRLFL[4] ,CP A request lost flag 4" "Not requested,Requested"
|
|
newline
|
|
eventfld.long 0x04 3. " CPRLFL[3] ,CP B request lost flag 3" "Not requested,Requested"
|
|
eventfld.long 0x04 2. " CPRLFL[2] ,CP A request lost flag 2" "Not requested,Requested"
|
|
newline
|
|
eventfld.long 0x04 1. " CPRLFL[1] ,CP B request lost flag 1" "Not requested,Requested"
|
|
eventfld.long 0x04 0. " CPRLFL[0] ,CP A request lost flag 0" "Not requested,Requested"
|
|
line.long 0x08 "BFINTFL,Buffer Full Interrupt Flag Register"
|
|
eventfld.long 0x08 15. " BFINTFL[15] ,CP B buffer full interrupt flag 15" "No interrupt,Interrupt"
|
|
eventfld.long 0x08 14. " BFINTFL[14] ,CP A buffer full interrupt flag 14" "No interrupt,Interrupt"
|
|
newline
|
|
eventfld.long 0x08 13. " BFINTFL[13] ,CP B buffer full interrupt flag 13" "No interrupt,Interrupt"
|
|
eventfld.long 0x08 12. " BFINTFL[12] ,CP A buffer full interrupt flag 12" "No interrupt,Interrupt"
|
|
newline
|
|
eventfld.long 0x08 11. " BFINTFL[11] ,CP B buffer full interrupt flag 11" "No interrupt,Interrupt"
|
|
eventfld.long 0x08 10. " BFINTFL[10] ,CP A buffer full interrupt flag 10" "No interrupt,Interrupt"
|
|
newline
|
|
eventfld.long 0x08 9. " BFINTFL[9] ,CP B buffer full interrupt flag 9" "No interrupt,Interrupt"
|
|
eventfld.long 0x08 8. " BFINTFL[8] ,CP A buffer full interrupt flag 8" "No interrupt,Interrupt"
|
|
newline
|
|
eventfld.long 0x08 7. " BFINTFL[7] ,CP B buffer full interrupt flag 7" "No interrupt,Interrupt"
|
|
eventfld.long 0x08 6. " BFINTFL[6] ,CP A buffer full interrupt flag 6" "No interrupt,Interrupt"
|
|
newline
|
|
eventfld.long 0x08 5. " BFINTFL[5] ,CP B buffer full interrupt flag 5" "No interrupt,Interrupt"
|
|
eventfld.long 0x08 4. " BFINTFL[4] ,CP A buffer full interrupt flag 4" "No interrupt,Interrupt"
|
|
newline
|
|
eventfld.long 0x08 3. " BFINTFL[3] ,CP B buffer full interrupt flag 3" "No interrupt,Interrupt"
|
|
eventfld.long 0x08 2. " BFINTFL[2] ,CP A buffer full interrupt flag 2" "No interrupt,Interrupt"
|
|
newline
|
|
eventfld.long 0x08 1. " BFINTFL[1] ,CP B buffer full interrupt flag 1" "No interrupt,Interrupt"
|
|
eventfld.long 0x08 0. " BFINTFL[0] ,CP A buffer full interrupt flag 0" "No interrupt,Interrupt"
|
|
line.long 0x0C "BERINTFL,BER Interrupt Flag Register"
|
|
eventfld.long 0x0C 15. " BERINTFL[15] ,CP B bus error interrupt flag 15" "No interrupt,Interrupt"
|
|
eventfld.long 0x0C 14. " BERINTFL[14] ,CP A bus error interrupt flag 14" "No interrupt,Interrupt"
|
|
newline
|
|
eventfld.long 0x0C 13. " BERINTFL[13] ,CP B bus error interrupt flag 13" "No interrupt,Interrupt"
|
|
eventfld.long 0x0C 12. " BERINTFL[12] ,CP A bus error interrupt flag 12" "No interrupt,Interrupt"
|
|
newline
|
|
eventfld.long 0x0C 11. " BERINTFL[11] ,CP B bus error interrupt flag 11" "No interrupt,Interrupt"
|
|
eventfld.long 0x0C 10. " BERINTFL[10] ,CP A bus error interrupt flag 10" "No interrupt,Interrupt"
|
|
newline
|
|
eventfld.long 0x0C 9. " BERINTFL[9] ,CP B bus error interrupt flag 9" "No interrupt,Interrupt"
|
|
eventfld.long 0x0C 8. " BERINTFL[8] ,CP A bus error interrupt flag 8" "No interrupt,Interrupt"
|
|
newline
|
|
eventfld.long 0x0C 7. " BERINTFL[7] ,CP B bus error interrupt flag 7" "No interrupt,Interrupt"
|
|
eventfld.long 0x0C 6. " BERINTFL[6] ,CP A bus error interrupt flag 6" "No interrupt,Interrupt"
|
|
newline
|
|
eventfld.long 0x0C 5. " BERINTFL[5] ,CP B bus error interrupt flag 5" "No interrupt,Interrupt"
|
|
eventfld.long 0x0C 4. " BERINTFL[4] ,CP A bus error interrupt flag 4" "No interrupt,Interrupt"
|
|
newline
|
|
eventfld.long 0x0C 3. " BERINTFL[3] ,CP B bus error interrupt flag 3" "No interrupt,Interrupt"
|
|
eventfld.long 0x0C 2. " BERINTFL[2] ,CP A bus error interrupt flag 2" "No interrupt,Interrupt"
|
|
newline
|
|
eventfld.long 0x0C 1. " BERINTFL[1] ,CP B bus error interrupt flag 1" "No interrupt,Interrupt"
|
|
eventfld.long 0x0C 0. " BERINTFL[0] ,CP A bus error interrupt flag 0" "No interrupt,Interrupt"
|
|
line.long 0x10 "MP1S,Memory Protection 1 Start Address"
|
|
line.long 0x14 "MP1E,Memory Protection 1 End Address"
|
|
line.long 0x18 "DCTRL,Debug Control Register"
|
|
sif (cpuis("TMS570LS0332")||cpuis("TMS570LS0432")||cpuis("TMS570LS1114*")||cpuis("TMS570LS1115*")||cpuis("TMS570LS1224*")||cpuis("TMS570LS1225*")||cpuis("TMS570LS1227*"))
|
|
rbitfld.long 0x18 24.--27. " CPNUM ,CP number" "CP A of DCP0,CP B of DCP0,CP A of DCP1,,,,,,,,,,,,CP A of DCP7,CP B of DCP7"
|
|
elif cpuis("TMS570LS0232")||cpuis("TMS570LS0714*")||cpuis("TMS570LS0914*")||cpuis("TMS570LS3137-EP")
|
|
bitfld.long 0x18 24.--27. " CPNUM ,CP number" "CP A of DCP 0,CP B of DCP 0,CP A of DCP 1,CP B of DCP 1,CP A of DCP 2,CP B of DCP 2,CP A of DCP 3,CP B of DCP 3,CP A of DCP 4,CP B of DCP 4,CP A of DCP 5,CP B of DCP 5,CP A of DCP 6,CP B of DCP 6,CP A of DCP 7,CP B of DCP 7"
|
|
else
|
|
bitfld.long 0x18 24.--27. " CPNUM ,CP number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
newline
|
|
eventfld.long 0x18 16. " HTUDBGS ,HTU debug status" "Not detected,Detected"
|
|
bitfld.long 0x18 0. " DBREN ,Debug request enable" "Disabled,Enabled"
|
|
line.long 0x1C "WPR,Watch Point Register"
|
|
line.long 0x20 "WMR,Watch Mask Register"
|
|
rgroup.long 0x60++0x03
|
|
line.long 0x00 "ID,Module Identification Register"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CLASS ,Module class"
|
|
hexmask.long.byte 0x00 8.--15. 1. " TYPE ,Subtype within a class"
|
|
hexmask.long.byte 0x00 0.--7. 1. " REV ,Module revision number"
|
|
group.long 0x64++0x07
|
|
line.long 0x0 "PCR,Parity Control Register"
|
|
bitfld.long 0x00 16. " COPE , Continue on parity error" "Stopped,Continued"
|
|
bitfld.long 0x00 8. " TEST ,Test" "Not mapped,Mapped"
|
|
bitfld.long 0x00 0.--3. " PARITY_ENA ,Enable/disable parity checking" "Enabled,Enabled,Enabled,Enabled,Enabled,Disabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled"
|
|
line.long 0x04 "PAR,Parity Address Register"
|
|
eventfld.long 0x04 16. " PEFT ,Parity Error fault flag" "Not detected,Detected"
|
|
hexmask.long.word 0x04 0.--8. 1. " PAOFF ,Parity error address offset"
|
|
group.long 0x70++0x0B
|
|
line.long 0x00 "MPCS,Memory Protection Control and Status Register"
|
|
sif cpuis("TMS570LS0232")||cpuis("TMS570LS0714*")||cpuis("TMS570LS0914*")||cpuis("TMS570LS3137-EP")
|
|
rbitfld.long 0x00 24.--27. " CPNUM0 ,CP number" "CP A of DCP 0,CP B of DCP 0,CP A of DCP 1,CP B of DCP 1,CP A of DCP 2,CP B of DCP 2,CP A of DCP 3,CP B of DCP 3,CP A of DCP 4,CP B of DCP 4,CP A of DCP 5,CP B of DCP 5,CP A of DCP 6,CP B of DCP 6,CP A of DCP 7,CP B of DCP 7"
|
|
else
|
|
bitfld.long 0x00 24.--27. " CPNUM0 ,CP number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
newline
|
|
eventfld.long 0x00 17. " MPEFT1 ,Memory protection error fault flag" "Not detected,Detected"
|
|
eventfld.long 0x00 16. " MPEFT0 ,Memory protection error fault flag" "Not detected,Detected"
|
|
newline
|
|
sif (cpuis("TMS570LS0332")||cpuis("TMS570LS0432")||cpuis("TMS570LS1114*")||cpuis("TMS570LS1115*")||cpuis("TMS570LS1224*")||cpuis("TMS570LS1225*")||cpuis("TMS570LS1227*"))
|
|
rbitfld.long 0x00 8.--11. " CPNUM1 ,CP number" "CP A of DCP0,CP B of DCP0,CP A of DCP1,,,,,,,,,,,,CP A of DCP7,CP B of DCP7"
|
|
elif cpuis("TMS570LS0232")||cpuis("TMS570LS0714*")||cpuis("TMS570LS0914*")||cpuis("TMS570LS3137-EP")
|
|
rbitfld.long 0x00 8.--11. " CPNUM1 ,CP number" "CP A of DCP 0,CP B of DCP 0,CP A of DCP 1,CP B of DCP 1,CP A of DCP 2,CP B of DCP 2,CP A of DCP 3,CP B of DCP 3,CP A of DCP 4,CP B of DCP 4,CP A of DCP 5,CP B of DCP 5,CP A of DCP 6,CP B of DCP 6,CP A of DCP 7,CP B of DCP 7"
|
|
else
|
|
bitfld.long 0x00 8.--11. " CPNUM1 ,CP number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
newline
|
|
bitfld.long 0x00 5. " INTENA01 ,Interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " ACCR01 ,Access rights HTU" "Allowed,Forbidden"
|
|
newline
|
|
bitfld.long 0x00 3. " REG01ENA ,Region enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " INTENA0 ,Interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " ACCR ,Access rights HTU" "Allowed,Forbidden"
|
|
newline
|
|
bitfld.long 0x00 0. " REG0ENA ,Region enable" "Disabled,Enabled"
|
|
line.long 0x04 "MP0S,Memory Protection Start Address Register"
|
|
line.long 0x08 "MP0E,Memory Protection End Address Register"
|
|
sif (cpuis("TMS570LS10106-PGE")||cpuis("TMS570LS10106-ZWT")||cpuis("TMS570LS10116-PGE")||cpuis("TMS570LS10116-ZWT")||cpuis("TMS570LS10206-PGE")||cpuis("TMS570LS10206-ZWT")||cpuis("TMS570LS10216-PGE")||cpuis("TMS570LS10216-ZWT")||cpuis("TMS570LS20206-PGE")||cpuis("TMS570LS20206-ZWT")||cpuis("TMS570LS20216-PGE")||cpuis("TMS570LS20216-ZWT")||cpuis("RM48L952-PGE")||cpuis("RM48L952-ZWT")||cpuis("RM48L950-PGE")||cpuis("RM48L950-ZWT")||cpuis("RM48L940-ZWT")||cpuis("RM48L940-PGE")||cpuis("RM48L930-ZWT")||cpuis("RM48L930-PGE")||cpuis("RM48L750-ZWT")||cpuis("RM48L750-PGE")||cpuis("RM48L740-ZWT")||cpuis("RM48L740-PGE")||cpuis("RM48L730-ZWT")||cpuis("RM48L730-PGE")||cpuis("RM48L550-PGE")||cpuis("RM48L540-ZWT")||cpuis("RM48L540-PGE")||cpuis("RM48L530-ZWT")||cpuis("RM48L530-PGE")||cpuis("RM46L852-PGE")||cpuis("RM46L852-ZWT")||cpuis("RM46L850-PGE")||cpuis("RM46L850-ZWT")||cpuis("RM46L840-ZWT")||cpuis("RM46L840-PGE")||cpuis("RM46L830-ZWT")||cpuis("RM46L830-PGE")||cpuis("RM46L450-ZWT")||cpuis("RM46L450-PGE")||cpuis("RM46L440-ZWT")||cpuis("RM46L440-PGE")||cpuis("RM46L430-ZWT")||cpuis("RM46L430-PGE")||cpuis("RM42L432")||cpuis("RM48L550-ZWT")||cpuis("TMS570LC4357")||cpuis("TMS570LS0332")||cpuis("TMS570LS0432")||cpuis("TMS570LS1114*")||cpuis("TMS570LS1115*")||cpuis("TMS570LS1224*")||cpuis("TMS570LS1225*")||cpuis("TMS570LS1227*")||cpuis("TMS570LS0232")||cpuis("TMS570LS0714*")||cpuis("TMS570LS0914*")||cpuis("TMS570LS3137-EP"))
|
|
tree "Double Control Packet Configuration Memory"
|
|
base ad:0xFF4E0000
|
|
sif !cpuis("TMS570LS0714*")&&!cpuis("TMS570LS0914*")&&!cpuis("RM46L852*")&&!cpuis("TMS570LS3137-EP")
|
|
group.long 0x00++0xF
|
|
line.long 0x00 "IFADDRA,Initial main memory address Control Packet A"
|
|
line.long 0x04 "IFADDRB,Initial main memory address Control Packet B"
|
|
line.long 0x08 "IHADDRCT,Initial NHET address and control"
|
|
bitfld.long 0x08 23. " DIR ,Direction of transfer (read->write)" "NHET->Main,Main->NHET"
|
|
bitfld.long 0x08 22. " SIZE ,Size of transferred data" "32-bit,64-bit"
|
|
newline
|
|
bitfld.long 0x08 21. " ADDMH ,Addressing mode NHET address (increment value)" "16 bytes,8 bytes"
|
|
bitfld.long 0x08 20. " ADDMF ,Addressing mode main memory address" "Post-increment,Constant"
|
|
newline
|
|
bitfld.long 0x08 18.--19. " TMBA ,Transfer mode for buffer A" "One Shot,Circular,Auto Switch,Auto Switch"
|
|
bitfld.long 0x08 16.--17. " TMBB ,Transfer mode for buffer B" "One Shot,Circular,Auto Switch,Auto Switch"
|
|
newline
|
|
hexmask.long.word 0x08 2.--12. 0x4 " IHADDR ,Initial NHET address"
|
|
line.long 0x0C "ITCOUNT,Initial transfer count"
|
|
bitfld.long 0x0C 16.--20. " IETCOUNT ,Initial element transfer count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
hexmask.long.byte 0x0C 0.--7. 1. " IFTCOUNT ,Initial frame transfer count"
|
|
group.long 0x100++0xB
|
|
line.long 0x00 "CFADDRA,Current main memory address Control Packet A"
|
|
line.long 0x04 "CFADDRB,Current main memory address Control Packet B"
|
|
line.long 0x08 "CFCOUNT,Current frame count"
|
|
hexmask.long.byte 0x08 16.--23. 1. " CFTCTA ,Current frame transfer count for CP A"
|
|
hexmask.long.byte 0x08 0.--7. 1. " CFTCTB ,Current frame transfer count for CP B"
|
|
else
|
|
width 15.
|
|
group.long 0x0++0x0F "DCP0"
|
|
line.long 0x00 "DCP0IFADDRA,DCP0 Initial main memory address Control Packet A"
|
|
line.long 0x04 "DCP0IFADDRB,DCP0 Initial main memory address Control Packet B"
|
|
line.long 0x08 "DCP0IHADDRCT,DCP0 Initial NHET address and control"
|
|
bitfld.long 0x08 23. " DIR ,Direction of transfer (read->write)" "NHET->Main,Main->NHET"
|
|
bitfld.long 0x08 22. " SIZE ,Size of transferred data" "32-bit,64-bit"
|
|
newline
|
|
bitfld.long 0x08 21. " ADDMH ,Addressing mode NHET address (Increment value)" "16 bytes,8 bytes"
|
|
bitfld.long 0x08 20. " ADDMF ,Addressing mode main memory address" "Post-increment,Constant"
|
|
newline
|
|
bitfld.long 0x08 18.--19. " TMBA ,Transfer mode for buffer A" "One Shot,Circular,Auto Switch,Auto Switch"
|
|
bitfld.long 0x08 16.--17. " TMBB ,Transfer mode for buffer B" "One Shot,Circular,Auto Switch,Auto Switch"
|
|
newline
|
|
hexmask.long.word 0x08 2.--12. 0x4 " IHADDR ,Initial NHET address"
|
|
line.long 0x0C "DCP0ITCOUNT,DCP0 Initial transfer count"
|
|
bitfld.long 0x0C 16.--20. " IETCOUNT ,Initial element transfer count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
hexmask.long.byte 0x0C 0.--7. 1. " IFTCOUNT ,Initial frame transfer count"
|
|
group.long (0x0+0x100)++0xB
|
|
line.long 0x00 "DCP0CFADDRA,DCP0 Current main memory address control packet A"
|
|
line.long 0x04 "DCP0CFADDRB,DCP0 Current main memory address control packet B"
|
|
line.long 0x08 "DCP0CFCOUNT,DCP0 Current frame count"
|
|
hexmask.long.byte 0x08 16.--23. 1. " CFTCTA ,Current frame transfer count for CP A"
|
|
hexmask.long.byte 0x08 0.--7. 1. " CFTCTB ,Current frame transfer count for CP B"
|
|
group.long 0x10++0x0F "DCP1"
|
|
line.long 0x00 "DCP1IFADDRA,DCP1 Initial main memory address Control Packet A"
|
|
line.long 0x04 "DCP1IFADDRB,DCP1 Initial main memory address Control Packet B"
|
|
line.long 0x08 "DCP1IHADDRCT,DCP1 Initial NHET address and control"
|
|
bitfld.long 0x08 23. " DIR ,Direction of transfer (read->write)" "NHET->Main,Main->NHET"
|
|
bitfld.long 0x08 22. " SIZE ,Size of transferred data" "32-bit,64-bit"
|
|
newline
|
|
bitfld.long 0x08 21. " ADDMH ,Addressing mode NHET address (Increment value)" "16 bytes,8 bytes"
|
|
bitfld.long 0x08 20. " ADDMF ,Addressing mode main memory address" "Post-increment,Constant"
|
|
newline
|
|
bitfld.long 0x08 18.--19. " TMBA ,Transfer mode for buffer A" "One Shot,Circular,Auto Switch,Auto Switch"
|
|
bitfld.long 0x08 16.--17. " TMBB ,Transfer mode for buffer B" "One Shot,Circular,Auto Switch,Auto Switch"
|
|
newline
|
|
hexmask.long.word 0x08 2.--12. 0x4 " IHADDR ,Initial NHET address"
|
|
line.long 0x0C "DCP1ITCOUNT,DCP1 Initial transfer count"
|
|
bitfld.long 0x0C 16.--20. " IETCOUNT ,Initial element transfer count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
hexmask.long.byte 0x0C 0.--7. 1. " IFTCOUNT ,Initial frame transfer count"
|
|
group.long (0x10+0x100)++0xB
|
|
line.long 0x00 "DCP1CFADDRA,DCP1 Current main memory address control packet A"
|
|
line.long 0x04 "DCP1CFADDRB,DCP1 Current main memory address control packet B"
|
|
line.long 0x08 "DCP1CFCOUNT,DCP1 Current frame count"
|
|
hexmask.long.byte 0x08 16.--23. 1. " CFTCTA ,Current frame transfer count for CP A"
|
|
hexmask.long.byte 0x08 0.--7. 1. " CFTCTB ,Current frame transfer count for CP B"
|
|
group.long 0x20++0x0F "DCP2"
|
|
line.long 0x00 "DCP2IFADDRA,DCP2 Initial main memory address Control Packet A"
|
|
line.long 0x04 "DCP2IFADDRB,DCP2 Initial main memory address Control Packet B"
|
|
line.long 0x08 "DCP2IHADDRCT,DCP2 Initial NHET address and control"
|
|
bitfld.long 0x08 23. " DIR ,Direction of transfer (read->write)" "NHET->Main,Main->NHET"
|
|
bitfld.long 0x08 22. " SIZE ,Size of transferred data" "32-bit,64-bit"
|
|
newline
|
|
bitfld.long 0x08 21. " ADDMH ,Addressing mode NHET address (Increment value)" "16 bytes,8 bytes"
|
|
bitfld.long 0x08 20. " ADDMF ,Addressing mode main memory address" "Post-increment,Constant"
|
|
newline
|
|
bitfld.long 0x08 18.--19. " TMBA ,Transfer mode for buffer A" "One Shot,Circular,Auto Switch,Auto Switch"
|
|
bitfld.long 0x08 16.--17. " TMBB ,Transfer mode for buffer B" "One Shot,Circular,Auto Switch,Auto Switch"
|
|
newline
|
|
hexmask.long.word 0x08 2.--12. 0x4 " IHADDR ,Initial NHET address"
|
|
line.long 0x0C "DCP2ITCOUNT,DCP2 Initial transfer count"
|
|
bitfld.long 0x0C 16.--20. " IETCOUNT ,Initial element transfer count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
hexmask.long.byte 0x0C 0.--7. 1. " IFTCOUNT ,Initial frame transfer count"
|
|
group.long (0x20+0x100)++0xB
|
|
line.long 0x00 "DCP2CFADDRA,DCP2 Current main memory address control packet A"
|
|
line.long 0x04 "DCP2CFADDRB,DCP2 Current main memory address control packet B"
|
|
line.long 0x08 "DCP2CFCOUNT,DCP2 Current frame count"
|
|
hexmask.long.byte 0x08 16.--23. 1. " CFTCTA ,Current frame transfer count for CP A"
|
|
hexmask.long.byte 0x08 0.--7. 1. " CFTCTB ,Current frame transfer count for CP B"
|
|
group.long 0x30++0x0F "DCP3"
|
|
line.long 0x00 "DCP3IFADDRA,DCP3 Initial main memory address Control Packet A"
|
|
line.long 0x04 "DCP3IFADDRB,DCP3 Initial main memory address Control Packet B"
|
|
line.long 0x08 "DCP3IHADDRCT,DCP3 Initial NHET address and control"
|
|
bitfld.long 0x08 23. " DIR ,Direction of transfer (read->write)" "NHET->Main,Main->NHET"
|
|
bitfld.long 0x08 22. " SIZE ,Size of transferred data" "32-bit,64-bit"
|
|
newline
|
|
bitfld.long 0x08 21. " ADDMH ,Addressing mode NHET address (Increment value)" "16 bytes,8 bytes"
|
|
bitfld.long 0x08 20. " ADDMF ,Addressing mode main memory address" "Post-increment,Constant"
|
|
newline
|
|
bitfld.long 0x08 18.--19. " TMBA ,Transfer mode for buffer A" "One Shot,Circular,Auto Switch,Auto Switch"
|
|
bitfld.long 0x08 16.--17. " TMBB ,Transfer mode for buffer B" "One Shot,Circular,Auto Switch,Auto Switch"
|
|
newline
|
|
hexmask.long.word 0x08 2.--12. 0x4 " IHADDR ,Initial NHET address"
|
|
line.long 0x0C "DCP3ITCOUNT,DCP3 Initial transfer count"
|
|
bitfld.long 0x0C 16.--20. " IETCOUNT ,Initial element transfer count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
hexmask.long.byte 0x0C 0.--7. 1. " IFTCOUNT ,Initial frame transfer count"
|
|
group.long (0x30+0x100)++0xB
|
|
line.long 0x00 "DCP3CFADDRA,DCP3 Current main memory address control packet A"
|
|
line.long 0x04 "DCP3CFADDRB,DCP3 Current main memory address control packet B"
|
|
line.long 0x08 "DCP3CFCOUNT,DCP3 Current frame count"
|
|
hexmask.long.byte 0x08 16.--23. 1. " CFTCTA ,Current frame transfer count for CP A"
|
|
hexmask.long.byte 0x08 0.--7. 1. " CFTCTB ,Current frame transfer count for CP B"
|
|
group.long 0x40++0x0F "DCP4"
|
|
line.long 0x00 "DCP4IFADDRA,DCP4 Initial main memory address Control Packet A"
|
|
line.long 0x04 "DCP4IFADDRB,DCP4 Initial main memory address Control Packet B"
|
|
line.long 0x08 "DCP4IHADDRCT,DCP4 Initial NHET address and control"
|
|
bitfld.long 0x08 23. " DIR ,Direction of transfer (read->write)" "NHET->Main,Main->NHET"
|
|
bitfld.long 0x08 22. " SIZE ,Size of transferred data" "32-bit,64-bit"
|
|
newline
|
|
bitfld.long 0x08 21. " ADDMH ,Addressing mode NHET address (Increment value)" "16 bytes,8 bytes"
|
|
bitfld.long 0x08 20. " ADDMF ,Addressing mode main memory address" "Post-increment,Constant"
|
|
newline
|
|
bitfld.long 0x08 18.--19. " TMBA ,Transfer mode for buffer A" "One Shot,Circular,Auto Switch,Auto Switch"
|
|
bitfld.long 0x08 16.--17. " TMBB ,Transfer mode for buffer B" "One Shot,Circular,Auto Switch,Auto Switch"
|
|
newline
|
|
hexmask.long.word 0x08 2.--12. 0x4 " IHADDR ,Initial NHET address"
|
|
line.long 0x0C "DCP4ITCOUNT,DCP4 Initial transfer count"
|
|
bitfld.long 0x0C 16.--20. " IETCOUNT ,Initial element transfer count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
hexmask.long.byte 0x0C 0.--7. 1. " IFTCOUNT ,Initial frame transfer count"
|
|
group.long (0x40+0x100)++0xB
|
|
line.long 0x00 "DCP4CFADDRA,DCP4 Current main memory address control packet A"
|
|
line.long 0x04 "DCP4CFADDRB,DCP4 Current main memory address control packet B"
|
|
line.long 0x08 "DCP4CFCOUNT,DCP4 Current frame count"
|
|
hexmask.long.byte 0x08 16.--23. 1. " CFTCTA ,Current frame transfer count for CP A"
|
|
hexmask.long.byte 0x08 0.--7. 1. " CFTCTB ,Current frame transfer count for CP B"
|
|
group.long 0x50++0x0F "DCP5"
|
|
line.long 0x00 "DCP5IFADDRA,DCP5 Initial main memory address Control Packet A"
|
|
line.long 0x04 "DCP5IFADDRB,DCP5 Initial main memory address Control Packet B"
|
|
line.long 0x08 "DCP5IHADDRCT,DCP5 Initial NHET address and control"
|
|
bitfld.long 0x08 23. " DIR ,Direction of transfer (read->write)" "NHET->Main,Main->NHET"
|
|
bitfld.long 0x08 22. " SIZE ,Size of transferred data" "32-bit,64-bit"
|
|
newline
|
|
bitfld.long 0x08 21. " ADDMH ,Addressing mode NHET address (Increment value)" "16 bytes,8 bytes"
|
|
bitfld.long 0x08 20. " ADDMF ,Addressing mode main memory address" "Post-increment,Constant"
|
|
newline
|
|
bitfld.long 0x08 18.--19. " TMBA ,Transfer mode for buffer A" "One Shot,Circular,Auto Switch,Auto Switch"
|
|
bitfld.long 0x08 16.--17. " TMBB ,Transfer mode for buffer B" "One Shot,Circular,Auto Switch,Auto Switch"
|
|
newline
|
|
hexmask.long.word 0x08 2.--12. 0x4 " IHADDR ,Initial NHET address"
|
|
line.long 0x0C "DCP5ITCOUNT,DCP5 Initial transfer count"
|
|
bitfld.long 0x0C 16.--20. " IETCOUNT ,Initial element transfer count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
hexmask.long.byte 0x0C 0.--7. 1. " IFTCOUNT ,Initial frame transfer count"
|
|
group.long (0x50+0x100)++0xB
|
|
line.long 0x00 "DCP5CFADDRA,DCP5 Current main memory address control packet A"
|
|
line.long 0x04 "DCP5CFADDRB,DCP5 Current main memory address control packet B"
|
|
line.long 0x08 "DCP5CFCOUNT,DCP5 Current frame count"
|
|
hexmask.long.byte 0x08 16.--23. 1. " CFTCTA ,Current frame transfer count for CP A"
|
|
hexmask.long.byte 0x08 0.--7. 1. " CFTCTB ,Current frame transfer count for CP B"
|
|
group.long 0x60++0x0F "DCP6"
|
|
line.long 0x00 "DCP6IFADDRA,DCP6 Initial main memory address Control Packet A"
|
|
line.long 0x04 "DCP6IFADDRB,DCP6 Initial main memory address Control Packet B"
|
|
line.long 0x08 "DCP6IHADDRCT,DCP6 Initial NHET address and control"
|
|
bitfld.long 0x08 23. " DIR ,Direction of transfer (read->write)" "NHET->Main,Main->NHET"
|
|
bitfld.long 0x08 22. " SIZE ,Size of transferred data" "32-bit,64-bit"
|
|
newline
|
|
bitfld.long 0x08 21. " ADDMH ,Addressing mode NHET address (Increment value)" "16 bytes,8 bytes"
|
|
bitfld.long 0x08 20. " ADDMF ,Addressing mode main memory address" "Post-increment,Constant"
|
|
newline
|
|
bitfld.long 0x08 18.--19. " TMBA ,Transfer mode for buffer A" "One Shot,Circular,Auto Switch,Auto Switch"
|
|
bitfld.long 0x08 16.--17. " TMBB ,Transfer mode for buffer B" "One Shot,Circular,Auto Switch,Auto Switch"
|
|
newline
|
|
hexmask.long.word 0x08 2.--12. 0x4 " IHADDR ,Initial NHET address"
|
|
line.long 0x0C "DCP6ITCOUNT,DCP6 Initial transfer count"
|
|
bitfld.long 0x0C 16.--20. " IETCOUNT ,Initial element transfer count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
hexmask.long.byte 0x0C 0.--7. 1. " IFTCOUNT ,Initial frame transfer count"
|
|
group.long (0x60+0x100)++0xB
|
|
line.long 0x00 "DCP6CFADDRA,DCP6 Current main memory address control packet A"
|
|
line.long 0x04 "DCP6CFADDRB,DCP6 Current main memory address control packet B"
|
|
line.long 0x08 "DCP6CFCOUNT,DCP6 Current frame count"
|
|
hexmask.long.byte 0x08 16.--23. 1. " CFTCTA ,Current frame transfer count for CP A"
|
|
hexmask.long.byte 0x08 0.--7. 1. " CFTCTB ,Current frame transfer count for CP B"
|
|
group.long 0x70++0x0F "DCP7"
|
|
line.long 0x00 "DCP7IFADDRA,DCP7 Initial main memory address Control Packet A"
|
|
line.long 0x04 "DCP7IFADDRB,DCP7 Initial main memory address Control Packet B"
|
|
line.long 0x08 "DCP7IHADDRCT,DCP7 Initial NHET address and control"
|
|
bitfld.long 0x08 23. " DIR ,Direction of transfer (read->write)" "NHET->Main,Main->NHET"
|
|
bitfld.long 0x08 22. " SIZE ,Size of transferred data" "32-bit,64-bit"
|
|
newline
|
|
bitfld.long 0x08 21. " ADDMH ,Addressing mode NHET address (Increment value)" "16 bytes,8 bytes"
|
|
bitfld.long 0x08 20. " ADDMF ,Addressing mode main memory address" "Post-increment,Constant"
|
|
newline
|
|
bitfld.long 0x08 18.--19. " TMBA ,Transfer mode for buffer A" "One Shot,Circular,Auto Switch,Auto Switch"
|
|
bitfld.long 0x08 16.--17. " TMBB ,Transfer mode for buffer B" "One Shot,Circular,Auto Switch,Auto Switch"
|
|
newline
|
|
hexmask.long.word 0x08 2.--12. 0x4 " IHADDR ,Initial NHET address"
|
|
line.long 0x0C "DCP7ITCOUNT,DCP7 Initial transfer count"
|
|
bitfld.long 0x0C 16.--20. " IETCOUNT ,Initial element transfer count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
hexmask.long.byte 0x0C 0.--7. 1. " IFTCOUNT ,Initial frame transfer count"
|
|
group.long (0x70+0x100)++0xB
|
|
line.long 0x00 "DCP7CFADDRA,DCP7 Current main memory address control packet A"
|
|
line.long 0x04 "DCP7CFADDRB,DCP7 Current main memory address control packet B"
|
|
line.long 0x08 "DCP7CFCOUNT,DCP7 Current frame count"
|
|
hexmask.long.byte 0x08 16.--23. 1. " CFTCTA ,Current frame transfer count for CP A"
|
|
hexmask.long.byte 0x08 0.--7. 1. " CFTCTB ,Current frame transfer count for CP B"
|
|
endif
|
|
tree.end
|
|
endif
|
|
sif cpuis("TMS570LS0232")||cpuis("TMS570LS0714*")||cpuis("TMS570LS0914*")
|
|
endian.le
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
endif
|
|
tree.open "GIO (General Purpose Input/Output Module)"
|
|
sif cpuis("TMS570LS0232")||cpuis("TMS570LS0714*")||cpuis("TMS570LS0914*")
|
|
tree "GPIO"
|
|
base ad:0xFFF7BC00
|
|
endian.be
|
|
width 8.
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "GCR0,Global Control Register"
|
|
bitfld.long 0x00 0. " GIOGCR0 ,GIO global control" "Reset,Normal"
|
|
tree "GIO Interrupt Registers"
|
|
group.long 0x08++0x07
|
|
line.long 0x00 "INTDET,Interrupt Detect"
|
|
sif cpuis("TMS570LS0714-PGE")||cpuis("TMS570LS0914-PGE")
|
|
bitfld.long 0x00 11. " INTDET_1_3 ,GIOB3 interrupt detection select" "Falling/rising,Both"
|
|
bitfld.long 0x00 10. " INTDET_1_2 ,GIOB2 interrupt detection select" "Falling/rising,Both"
|
|
bitfld.long 0x00 9. " INTDET_1_1 ,GIOB1 interrupt detection select" "Falling/rising,Both"
|
|
bitfld.long 0x00 8. " INTDET_1_0 ,GIOB0 interrupt detection select" "Falling/rising,Both"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 7. " INTDET_0_7 ,GIOA7 interrupt detection select" "Falling/rising,Both"
|
|
bitfld.long 0x00 6. " INTDET_0_6 ,GIOA6 interrupt detection select" "Falling/rising,Both"
|
|
bitfld.long 0x00 5. " INTDET_0_5 ,GIOA5 interrupt detection select" "Falling/rising,Both"
|
|
newline
|
|
sif !cpuis("TMS570LS0714-PGE")&&!cpuis("TMS570LS0914-PGE")
|
|
bitfld.long 0x00 4. " INTDET_0_4 ,GIOA4 interrupt detection select" "Falling/rising,Both"
|
|
bitfld.long 0x00 3. " INTDET_0_3 ,GIOA3 interrupt detection select" "Falling/rising,Both"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 2. " INTDET_0_2 ,GIOA2 interrupt detection select" "Falling/rising,Both"
|
|
bitfld.long 0x00 1. " INTDET_0_1 ,GIOA1 interrupt detection select" "Falling/rising,Both"
|
|
bitfld.long 0x00 0. " INTDET_0_0 ,GIOA0 interrupt detection select" "Falling/rising,Both"
|
|
line.long 0x04 "POL,Interrupt Polarity"
|
|
sif cpuis("TMS570LS0714-PGE")||cpuis("TMS570LS0914-PGE")
|
|
bitfld.long 0x04 11. " GIOPOL_1_3 ,GIOB3 interrupt polarity select (User-priviledge/Low power mode)" "Falling/Low,Rising/High"
|
|
bitfld.long 0x04 10. " GIOPOL_1_2 ,GIOB2 interrupt polarity select (User-priviledge/Low power mode)" "Falling/Low,Rising/High"
|
|
bitfld.long 0x04 9. " GIOPOL_1_1 ,GIOB1 interrupt polarity select (User-priviledge/Low power mode)" "Falling/Low,Rising/High"
|
|
bitfld.long 0x04 8. " GIOPOL_1_0 ,GIOB0 interrupt polarity select (User-priviledge/Low power mode)" "Falling/Low,Rising/High"
|
|
newline
|
|
endif
|
|
bitfld.long 0x04 7. " GIOPOL_0_7 ,GIOA7 interrupt polarity select (User-priviledge/Low power mode)" "Falling/Low,Rising/High"
|
|
bitfld.long 0x04 6. " GIOPOL_0_6 ,GIOA6 interrupt polarity select (User-priviledge/Low power mode)" "Falling/Low,Rising/High"
|
|
bitfld.long 0x04 5. " GIOPOL_0_5 ,GIOA5 interrupt polarity select (User-priviledge/Low power mode)" "Falling/Low,Rising/High"
|
|
newline
|
|
sif !cpuis("TMS570LS0714-PGE")&&!cpuis("TMS570LS0914-PGE")
|
|
bitfld.long 0x04 4. " GIOPOL_0_4 ,GIOA4 interrupt polarity select (User-priviledge/Low power mode)" "Falling/Low,Rising/High"
|
|
bitfld.long 0x04 3. " GIOPOL_0_3 ,GIOA3 interrupt polarity select (User-priviledge/Low power mode)" "Falling/Low,Rising/High"
|
|
newline
|
|
endif
|
|
bitfld.long 0x04 2. " GIOPOL_0_2 ,GIOA2 interrupt polarity select (User-priviledge/Low power mode)" "Falling/Low,Rising/High"
|
|
bitfld.long 0x04 1. " GIOPOL_0_1 ,GIOA1 interrupt polarity select (User-priviledge/Low power mode)" "Falling/Low,Rising/High"
|
|
bitfld.long 0x04 0. " GIOPOL_0_0 ,GIOA0 interrupt polarity select (User-priviledge/Low power mode)" "Falling/Low,Rising/High"
|
|
tree.end
|
|
tree "GIO Interrupt Enable Registers"
|
|
width 13.
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "ENA_SET/CLR,Interrupt Enable Set/Clr"
|
|
sif cpuis("TMS570LS0714-PGE")||cpuis("TMS570LS0914-PGE")
|
|
setclrfld.long 0x00 11. 0x00 11. 0x04 11. " GIOENA_1_3 ,GIOB3 interrupt enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x04 10. " GIOENA_1_2 ,GIOB2 interrupt enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x04 9. " GIOENA_1_1 ,GIOB1 interrupt enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x04 8. " GIOENA_1_0 ,GIOB0 interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
endif
|
|
setclrfld.long 0x00 7. 0x00 7. 0x04 7. " GIOENA_0_7 ,GIOA7 interrupt enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x04 6. " GIOENA_0_6 ,GIOA6 interrupt enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x04 5. " GIOENA_0_5 ,GIOA5 interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
sif !cpuis("TMS570LS0714-PGE")&&!cpuis("TMS570LS0914-PGE")
|
|
setclrfld.long 0x00 4. 0x00 4. 0x04 4. " GIOENA_0_4 ,GIOA4 interrupt enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x04 3. " GIOENA_0_3 ,GIOA3 interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
endif
|
|
setclrfld.long 0x00 2. 0x00 2. 0x04 2. " GIOENA_0_2 ,GIOA2 interrupt enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 1. 0x00 1. 0x04 1. " GIOENA_0_1 ,GIOA1 interrupt enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x04 0. " GIOENA_0_0 ,GIOA0 interrupt enable" "Disabled,Enabled"
|
|
tree.end
|
|
tree "GIO Interrupt Priority Registers"
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "LVL_SET/CLR,Interrupt Priority Set/Clr"
|
|
sif cpuis("TMS570LS0714-PGE")||cpuis("TMS570LS0914-PGE")
|
|
setclrfld.long 0x00 11. 0x00 11. 0x00 11. " GIOLVL_1_3 ,GIOB3 high priority interrupt" "Low-level,High-level"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x00 10. " GIOLVL_1_2 ,GIOB2 high priority interrupt" "Low-level,High-level"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x00 9. " GIOLVL_1_1 ,GIOB1 high priority interrupt" "Low-level,High-level"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x00 8. " GIOLVL_1_0 ,GIOB0 high priority interrupt" "Low-level,High-level"
|
|
newline
|
|
endif
|
|
setclrfld.long 0x00 7. 0x00 7. 0x00 7. " GIOLVL_0_7 ,GIOA7 high priority interrupt" "Low-level,High-level"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x00 6. " GIOLVL_0_6 ,GIOA6 high priority interrupt" "Low-level,High-level"
|
|
newline
|
|
setclrfld.long 0x00 5. 0x00 5. 0x00 5. " GIOLVL_0_5 ,GIOA5 high priority interrupt" "Low-level,High-level"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x00 4. " GIOLVL_0_4 ,GIOA4 high priority interrupt" "Low-level,High-level"
|
|
newline
|
|
sif !cpuis("TMS570LS0714-PGE")&&!cpuis("TMS570LS0914-PGE")
|
|
setclrfld.long 0x00 3. 0x00 3. 0x00 3. " GIOLVL_0_3 ,GIOA3 high priority interrupt" "Low-level,High-level"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x00 2. " GIOLVL_0_2 ,GIOA2 high priority interrupt" "Low-level,High-level"
|
|
newline
|
|
endif
|
|
setclrfld.long 0x00 1. 0x00 1. 0x00 1. " GIOLVL_0_1 ,GIOA1 high priority interrupt" "Low-level,High-level"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x00 0. " GIOLVL_0_0 ,GIOA0 high priority interrupt" "Low-level,High-level"
|
|
tree.end
|
|
newline
|
|
width 8.
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "FLG,Interrupt Flag"
|
|
sif cpuis("TMS570LS0714-PGE")||cpuis("TMS570LS0914-PGE")
|
|
eventfld.long 0x00 11. " GIOFLG_1_3 ,GIOB3 flag" "Not occurred,Occurred"
|
|
eventfld.long 0x00 10. " GIOFLG_1_2 ,GIOB2 flag" "Not occurred,Occurred"
|
|
eventfld.long 0x00 9. " GIOFLG_1_1 ,GIOB1 flag" "Not occurred,Occurred"
|
|
eventfld.long 0x00 8. " GIOFLG_1_0 ,GIOB0 flag" "Not occurred,Occurred"
|
|
newline
|
|
endif
|
|
eventfld.long 0x00 7. " GIOFLG_0_7 ,GIOA7 flag" "Not occurred,Occurred"
|
|
eventfld.long 0x00 6. " GIOFLG_0_6 ,GIOA6 flag" "Not occurred,Occurred"
|
|
eventfld.long 0x00 5. " GIOFLG_0_5 ,GIOA5 flag" "Not occurred,Occurred"
|
|
newline
|
|
sif !cpuis("TMS570LS0714-PGE")&&!cpuis("TMS570LS0914-PGE")
|
|
eventfld.long 0x00 4. " GIOFLG_0_4 ,GIOA4 flag" "Not occurred,Occurred"
|
|
eventfld.long 0x00 3. " GIOFLG_0_3 ,GIOA3 flag" "Not occurred,Occurred"
|
|
newline
|
|
endif
|
|
eventfld.long 0x00 2. " GIOFLG_0_2 ,GIOA2 flag" "Not occurred,Occurred"
|
|
eventfld.long 0x00 1. " GIOFLG_0_1 ,GIOA1 flag" "Not occurred,Occurred"
|
|
eventfld.long 0x00 0. " GIOFLG_0_0 ,GIOA0 flag" "Not occurred,Occurred"
|
|
hgroup.long 0x24++0x03
|
|
hide.long 0x00 "OFF1,Offset Register 1"
|
|
in
|
|
hgroup.long 0x28++0x03
|
|
hide.long 0x00 "OFF2,Offset B register"
|
|
in
|
|
rgroup.long 0x2C++0x07
|
|
line.long 0x00 "EMU1,GIO Emulation A Register"
|
|
sif cpuis("TMS570LS0714-PGE")||cpuis("TMS570LS0914-PGE")
|
|
bitfld.long 0x00 0.--5. " GIOEMU1 ,Currently pending high-priority interrupt" "No interrupt,GIOA0 interrupt,GIOA1 interrupt,GIOA2 interrupt,,,GIOA5 interrupt,GIOA6 interrupt,GIOA7 interrupt,GIOB0 interrupt,GIOB1 interrupt,GIOB2 interrupt,GIOB3 interrupt,?..."
|
|
else
|
|
bitfld.long 0x00 0.--5. " GIOEMU1 ,Currently pending high-priority interrupt" "No interrupt,GIOA0 interrupt,GIOA1 interrupt,GIOA2 interrupt,GIOA3 interrupt,GIOA4 interrupt,GIOA5 interrupt,GIOA6 interrupt,GIOA7 interrupt,?..."
|
|
endif
|
|
line.long 0x04 "EMU2,GIO Emulation B Register"
|
|
sif cpuis("TMS570LS0714-PGE")||cpuis("TMS570LS0914-PGE")
|
|
bitfld.long 0x04 0.--5. " GIOEMU2 ,Currently pending low-priority interrupt" "No interrupt,GIOA0 interrupt,GIOA1 interrupt,GIOA2 interrupt,,,GIOA5 interrupt,GIOA6 interrupt,GIOA7 interrupt,GIOB0 interrupt,GIOB1 interrupt,GIOB2 interrupt,GIOB3 interrupt,?..."
|
|
else
|
|
bitfld.long 0x04 0.--5. " GIOEMU2 ,Currently pending low-priority interrupt" "No interrupt,GIOA0 interrupt,GIOA1 interrupt,GIOA2 interrupt,GIOA3 interrupt,GIOA4 interrupt,GIOA5 interrupt,GIOA6 interrupt,GIOA7 interrupt,?..."
|
|
endif
|
|
endian.le
|
|
width 0x0B
|
|
tree.end
|
|
tree "GPIO_A"
|
|
base ad:0xFFF7BC00
|
|
endian.be
|
|
width 14.
|
|
rgroup.long 0x34++0x07
|
|
line.long 0x0 "DIR,Data Direction Register"
|
|
bitfld.long 0x00 7. " GIODIR[7] ,GIOA data direction 7" "Input,Output"
|
|
bitfld.long 0x00 6. " [6] ,GIOA data direction 6" "Input,Output"
|
|
bitfld.long 0x00 5. " [5] ,GIOA data direction 5" "Input,Output"
|
|
newline
|
|
sif !cpuis("TMS570LS0714-PGE")&&!cpuis("TMS570LS0914-PGE")
|
|
bitfld.long 0x00 4. " [4] ,GIOA data direction 4" "Input,Output"
|
|
bitfld.long 0x00 3. " [3] ,GIOA data direction 3" "Input,Output"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 2. " [2] ,GIOA data direction 2" "Input,Output"
|
|
bitfld.long 0x00 1. " [1] ,GIOA data direction 1" "Input,Output"
|
|
bitfld.long 0x00 0. " [0] ,GIOA data direction 0" "Input,Output"
|
|
line.long 0x04 "DIN,Data Input"
|
|
bitfld.long 0x04 7. " GIODIN[7] ,GIOA data input 7" "Low,High"
|
|
bitfld.long 0x04 6. " [6] ,GIOA data input 6" "Low,High"
|
|
bitfld.long 0x04 5. " [5] ,GIOA data input 5" "Low,High"
|
|
newline
|
|
sif !cpuis("TMS570LS0714-PGE")&&!cpuis("TMS570LS0914-PGE")
|
|
bitfld.long 0x04 4. " [4] ,GIOA data input 4" "Low,High"
|
|
bitfld.long 0x04 3. " [3] ,GIOA data input 3" "Low,High"
|
|
newline
|
|
endif
|
|
bitfld.long 0x04 2. " [2] ,GIOA data input 2" "Low,High"
|
|
bitfld.long 0x04 1. " [1] ,GIOA data input 1" "Low,High"
|
|
bitfld.long 0x04 0. " [0] ,GIOA data input 0" "Low,High"
|
|
group.long 0x3C++0x03
|
|
line.long 0x00 "DOUT_SET/CLR,Data Output Set/Clear Register"
|
|
setclrfld.long 0x00 7. 0x04 7. 0x08 7. " GIODOUT[7] ,GIOA data output 7" "Low,High"
|
|
setclrfld.long 0x00 6. 0x04 6. 0x08 6. " [6] ,GIOA data output 6" "Low,High"
|
|
setclrfld.long 0x00 5. 0x04 5. 0x08 5. " [5] ,GIOA data output 5" "Low,High"
|
|
newline
|
|
sif !cpuis("TMS570LS0714-PGE")&&!cpuis("TMS570LS0914-PGE")
|
|
setclrfld.long 0x00 4. 0x04 4. 0x08 4. " [4] ,GIOA data output 4" "Low,High"
|
|
setclrfld.long 0x00 3. 0x04 3. 0x08 3. " [3] ,GIOA data output 3" "Low,High"
|
|
newline
|
|
endif
|
|
setclrfld.long 0x00 2. 0x04 2. 0x08 2. " [2] ,GIOA data output 2" "Low,High"
|
|
setclrfld.long 0x00 1. 0x04 1. 0x08 1. " [1] ,GIOA data output 1" "Low,High"
|
|
setclrfld.long 0x00 0. 0x04 0. 0x08 0. " [0] ,GIOA data output 0" "Low,High"
|
|
group.long 0x48++0x0B
|
|
line.long 0x00 "PDR,Open Drain Register"
|
|
bitfld.long 0x00 7. " GIOPDR[7] ,GIOA open drain 7" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " [6] ,GIOA open drain 6" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " [5] ,GIOA open drain 5" "Disabled,Enabled"
|
|
newline
|
|
sif !cpuis("TMS570LS0714-PGE")&&!cpuis("TMS570LS0914-PGE")
|
|
bitfld.long 0x00 4. " [4] ,GIOA open drain 4" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " [3] ,GIOA open drain 3" "Disabled,Enabled"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 2. " [2] ,GIOA open drain 2" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " [1] ,GIOA open drain 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,GIOA open drain 0" "Disabled,Enabled"
|
|
line.long 0x04 "PULLDIS,Pull Disable"
|
|
bitfld.long 0x04 7. " GIOPULDIS[7] ,GIOA pull disable 7" "No,Yes"
|
|
bitfld.long 0x04 6. " [6] ,GIOA pull disable 6" "No,Yes"
|
|
bitfld.long 0x04 5. " [5] ,GIOA pull disable 5" "No,Yes"
|
|
newline
|
|
sif !cpuis("TMS570LS0714-PGE")&&!cpuis("TMS570LS0914-PGE")
|
|
bitfld.long 0x04 4. " [4] ,GIOA pull disable 4" "No,Yes"
|
|
bitfld.long 0x04 3. " [3] ,GIOA pull disable 3" "No,Yes"
|
|
newline
|
|
endif
|
|
bitfld.long 0x04 2. " [2] ,GIOA pull disable 2" "No,Yes"
|
|
bitfld.long 0x04 1. " [1] ,GIOA pull disable 1" "No,Yes"
|
|
bitfld.long 0x04 0. " [0] ,GIOA pull disable 0" "No,Yes"
|
|
line.long 0x08 "PSL,Pull Select"
|
|
bitfld.long 0x08 7. " GIOPSL[7] ,GIOA pull select 7" "Pull down,Pull up"
|
|
bitfld.long 0x08 6. " [6] ,GIOA pull select 6" "Pull down,Pull up"
|
|
bitfld.long 0x08 5. " [5] ,GIOA pull select 5" "Pull down,Pull up"
|
|
newline
|
|
sif !cpuis("TMS570LS0714-PGE")&&!cpuis("TMS570LS0914-PGE")
|
|
bitfld.long 0x08 4. " [4] ,GIOA pull select 4" "Pull down,Pull up"
|
|
bitfld.long 0x08 3. " [3] ,GIOA pull select 3" "Pull down,Pull up"
|
|
newline
|
|
endif
|
|
bitfld.long 0x08 2. " [2] ,GIOA pull select 2" "Pull down,Pull up"
|
|
bitfld.long 0x08 1. " [1] ,GIOA pull select 1" "Pull down,Pull up"
|
|
bitfld.long 0x08 0. " [0] ,GIOA pull select 0" "Pull down,Pull up"
|
|
endian.le
|
|
width 0x0B
|
|
tree.end
|
|
sif cpuis("TMS570LS0714-PGE")||cpuis("TMS570LS0914-PGE")
|
|
tree "GPIO_B"
|
|
base ad:0xFFF7BC20
|
|
endian.be
|
|
width 14.
|
|
rgroup.long 0x34++0x07
|
|
line.long 0x0 "DIR,Data Direction Register"
|
|
bitfld.long 0x00 3. " GIODIR[3] ,GIOB data direction 3" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 2. " [2] ,GIOB data direction 2" "Input,Output"
|
|
bitfld.long 0x00 1. " [1] ,GIOB data direction 1" "Input,Output"
|
|
bitfld.long 0x00 0. " [0] ,GIOB data direction 0" "Input,Output"
|
|
line.long 0x04 "DIN,Data Input"
|
|
bitfld.long 0x04 3. " GIODIN[3] ,GIOB data input 3" "Low,High"
|
|
newline
|
|
bitfld.long 0x04 2. " [2] ,GIOB data input 2" "Low,High"
|
|
bitfld.long 0x04 1. " [1] ,GIOB data input 1" "Low,High"
|
|
bitfld.long 0x04 0. " [0] ,GIOB data input 0" "Low,High"
|
|
group.long 0x3C++0x03
|
|
line.long 0x00 "DOUT_SET/CLR,Data Output Set/Clear Register"
|
|
setclrfld.long 0x00 3. 0x04 3. 0x08 3. " GIODOUT[3] ,GIOB data output 3" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 2. 0x04 2. 0x08 2. " [2] ,GIOB data output 2" "Low,High"
|
|
setclrfld.long 0x00 1. 0x04 1. 0x08 1. " [1] ,GIOB data output 1" "Low,High"
|
|
setclrfld.long 0x00 0. 0x04 0. 0x08 0. " [0] ,GIOB data output 0" "Low,High"
|
|
group.long 0x48++0x0B
|
|
line.long 0x00 "PDR,Open Drain Register"
|
|
bitfld.long 0x00 3. " GIOPDR[3] ,GIOB open drain 3" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 2. " [2] ,GIOB open drain 2" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " [1] ,GIOB open drain 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,GIOB open drain 0" "Disabled,Enabled"
|
|
line.long 0x04 "PULLDIS,Pull Disable"
|
|
bitfld.long 0x04 3. " GIOPULDIS[3] ,GIOB pull disable 3" "No,Yes"
|
|
newline
|
|
bitfld.long 0x04 2. " [2] ,GIOB pull disable 2" "No,Yes"
|
|
bitfld.long 0x04 1. " [1] ,GIOB pull disable 1" "No,Yes"
|
|
bitfld.long 0x04 0. " [0] ,GIOB pull disable 0" "No,Yes"
|
|
line.long 0x08 "PSL,Pull Select"
|
|
bitfld.long 0x08 3. " GIOPSL[3] ,GIOB pull select 3" "Pull down,Pull up"
|
|
newline
|
|
bitfld.long 0x08 2. " [2] ,GIOB pull select 2" "Pull down,Pull up"
|
|
bitfld.long 0x08 1. " [1] ,GIOB pull select 1" "Pull down,Pull up"
|
|
bitfld.long 0x08 0. " [0] ,GIOB pull select 0" "Pull down,Pull up"
|
|
endian.le
|
|
width 0x0B
|
|
tree.end
|
|
endif
|
|
else
|
|
tree "GPIO"
|
|
base ad:0xFFF7BC00
|
|
width 8.
|
|
textline " "
|
|
sif (cpu()=="RM42L432"||cpu()=="TMS570LC4357"||cpu()==("TMS570LS0332")||cpu()==("TMS570LS0432")||cpuis("TMS570LS0232")||cpuis("TMS570LS3137-EP"))
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "GCR0,Global Control Register"
|
|
bitfld.long 0x00 0. " GIOGCR0 ,GIO Global Control" "Reset,Normal"
|
|
else
|
|
group.long 0x00++0x07
|
|
line.long 0x00 "GCR0,Global Control Register"
|
|
bitfld.long 0x00 0. " GIOGCR0 ,GIO Global Control" "Reset,Normal"
|
|
line.long 0x04 "PWDN,Power Down"
|
|
endif
|
|
tree "GIO Interrupt Registers"
|
|
group.long 0x08++0x07
|
|
line.long 0x00 "INTDET,Interrupt Detect"
|
|
sif (cpu()!="RM42L432"&&cpu()!=("TMS570LS0332")&&cpu()!=("TMS570LS0432"))
|
|
sif (cpu()!="TMS570LC4357")
|
|
bitfld.long 0x00 31. " INTDET_3_7 ,GIOD7 Interrupt Detection Select" "Falling/rising,Both"
|
|
bitfld.long 0x00 30. " INTDET_3_6 ,GIOD6 Interrupt Detection Select" "Falling/rising,Both"
|
|
textline " "
|
|
bitfld.long 0x00 29. " INTDET_3_5 ,GIOD5 Interrupt Detection Select" "Falling/rising,Both"
|
|
bitfld.long 0x00 28. " INTDET_3_4 ,GIOD4 Interrupt Detection Select" "Falling/rising,Both"
|
|
textline " "
|
|
bitfld.long 0x00 27. " INTDET_3_3 ,GIOD3 Interrupt Detection Select" "Falling/rising,Both"
|
|
bitfld.long 0x00 26. " INTDET_3_2 ,GIOC2 Interrupt Detection Select" "Falling/rising,Both"
|
|
textline " "
|
|
bitfld.long 0x00 25. " INTDET_3_1 ,GIOC1 Interrupt Detection Select" "Falling/rising,Both"
|
|
bitfld.long 0x00 24. " INTDET_3_0 ,GIOC0 Interrupt Detection Select" "Falling/rising,Both"
|
|
textline " "
|
|
bitfld.long 0x00 23. " INTDET_2_7 ,GIOC7 Interrupt Detection Select" "Falling/rising,Both"
|
|
bitfld.long 0x00 22. " INTDET_2_6 ,GIOC6 Interrupt Detection Select" "Falling/rising,Both"
|
|
textline " "
|
|
bitfld.long 0x00 21. " INTDET_2_5 ,GIOC5 Interrupt Detection Select" "Falling/rising,Both"
|
|
bitfld.long 0x00 20. " INTDET_2_4 ,GIOC4 Interrupt Detection Select" "Falling/rising,Both"
|
|
textline " "
|
|
bitfld.long 0x00 19. " INTDET_2_3 ,GIOC3 Interrupt Detection Select" "Falling/rising,Both"
|
|
bitfld.long 0x00 18. " INTDET_2_2 ,GIOC2 Interrupt Detection Select" "Falling/rising,Both"
|
|
textline " "
|
|
bitfld.long 0x00 17. " INTDET_2_1 ,GIOC1 Interrupt Detection Select" "Falling/rising,Both"
|
|
bitfld.long 0x00 16. " INTDET_2_0 ,GIOC0 Interrupt Detection Select" "Falling/rising,Both"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 15. " INTDET_1_7 ,GIOB7 Interrupt Detection Select" "Falling/rising,Both"
|
|
bitfld.long 0x00 14. " INTDET_1_6 ,GIOB6 Interrupt Detection Select" "Falling/rising,Both"
|
|
textline " "
|
|
bitfld.long 0x00 13. " INTDET_1_5 ,GIOB5 Interrupt Detection Select" "Falling/rising,Both"
|
|
bitfld.long 0x00 12. " INTDET_1_4 ,GIOB4 Interrupt Detection Select" "Falling/rising,Both"
|
|
textline " "
|
|
bitfld.long 0x00 11. " INTDET_1_3 ,GIOB3 Interrupt Detection Select" "Falling/rising,Both"
|
|
bitfld.long 0x00 10. " INTDET_1_2 ,GIOB2 Interrupt Detection Select" "Falling/rising,Both"
|
|
textline " "
|
|
bitfld.long 0x00 9. " INTDET_1_1 ,GIOB1 Interrupt Detection Select" "Falling/rising,Both"
|
|
bitfld.long 0x00 8. " INTDET_1_0 ,GIOB0 Interrupt Detection Select" "Falling/rising,Both"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 7. " INTDET_0_7 ,GIOA7 Interrupt Detection Select" "Falling/rising,Both"
|
|
bitfld.long 0x00 6. " INTDET_0_6 ,GIOA6 Interrupt Detection Select" "Falling/rising,Both"
|
|
textline " "
|
|
bitfld.long 0x00 5. " INTDET_0_5 ,GIOA5 Interrupt Detection Select" "Falling/rising,Both"
|
|
bitfld.long 0x00 4. " INTDET_0_4 ,GIOA4 Interrupt Detection Select" "Falling/rising,Both"
|
|
textline " "
|
|
bitfld.long 0x00 3. " INTDET_0_3 ,GIOA3 Interrupt Detection Select" "Falling/rising,Both"
|
|
bitfld.long 0x00 2. " INTDET_0_2 ,GIOA2 Interrupt Detection Select" "Falling/rising,Both"
|
|
textline " "
|
|
bitfld.long 0x00 1. " INTDET_0_1 ,GIOA1 Interrupt Detection Select" "Falling/rising,Both"
|
|
bitfld.long 0x00 0. " INTDET_0_0 ,GIOA0 Interrupt Detection Select" "Falling/rising,Both"
|
|
line.long 0x04 "POL,Interrupt Polarity"
|
|
sif (cpu()!="RM42L432"&&cpu()!=("TMS570LS0332")&&cpu()!=("TMS570LS0432"))
|
|
sif (cpu()!="TMS570LC4357")
|
|
bitfld.long 0x04 31. " GIOPOL_3_7 ,GIOD7 Interrupt Polarity Select (User-priviledge/Low power mode)" "Falling/Low,Rising/High"
|
|
bitfld.long 0x04 30. " GIOPOL_3_6 ,GIOD6 Interrupt Polarity Select (User-priviledge/Low power mode)" "Falling/Low,Rising/High"
|
|
textline " "
|
|
bitfld.long 0x04 29. " GIOPOL_3_5 ,GIOD5 Interrupt Polarity Select (User-priviledge/Low power mode)" "Falling/Low,Rising/High"
|
|
bitfld.long 0x04 28. " GIOPOL_3_4 ,GIOD4 Interrupt Polarity Select (User-priviledge/Low power mode)" "Falling/Low,Rising/High"
|
|
textline " "
|
|
bitfld.long 0x04 27. " GIOPOL_3_3 ,GIOD3 Interrupt Polarity Select (User-priviledge/Low power mode)" "Falling/Low,Rising/High"
|
|
bitfld.long 0x04 26. " GIOPOL_3_2 ,GIOD2 Interrupt Polarity Select (User-priviledge/Low power mode)" "Falling/Low,Rising/High"
|
|
textline " "
|
|
bitfld.long 0x04 25. " GIOPOL_3_1 ,GIOD1 Interrupt Polarity Select (User-priviledge/Low power mode)" "Falling/Low,Rising/High"
|
|
bitfld.long 0x04 24. " GIOPOL_3_0 ,GIOD0 Interrupt Polarity Select (User-priviledge/Low power mode)" "Falling/Low,Rising/High"
|
|
textline " "
|
|
bitfld.long 0x04 23. " GIOPOL_2_7 ,GIOC7 Interrupt Polarity Select (User-priviledge/Low power mode)" "Falling/Low,Rising/High"
|
|
bitfld.long 0x04 22. " GIOPOL_2_6 ,GIOC6 Interrupt Polarity Select (User-priviledge/Low power mode)" "Falling/Low,Rising/High"
|
|
textline " "
|
|
bitfld.long 0x04 21. " GIOPOL_2_5 ,GIOC5 Interrupt Polarity Select (User-priviledge/Low power mode)" "Falling/Low,Rising/High"
|
|
bitfld.long 0x04 20. " GIOPOL_2_4 ,GIOC4 Interrupt Polarity Select (User-priviledge/Low power mode)" "Falling/Low,Rising/High"
|
|
textline " "
|
|
bitfld.long 0x04 19. " GIOPOL_2_3 ,GIOC3 Interrupt Polarity Select (User-priviledge/Low power mode)" "Falling/Low,Rising/High"
|
|
bitfld.long 0x04 18. " GIOPOL_2_2 ,GIOC2 Interrupt Polarity Select (User-priviledge/Low power mode)" "Falling/Low,Rising/High"
|
|
textline " "
|
|
bitfld.long 0x04 17. " GIOPOL_2_1 ,GIOC1 Interrupt Polarity Select (User-priviledge/Low power mode)" "Falling/Low,Rising/High"
|
|
bitfld.long 0x04 16. " GIOPOL_2_0 ,GIOC0 Interrupt Polarity Select (User-priviledge/Low power mode)" "Falling/Low,Rising/High"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x04 15. " GIOPOL_1_7 ,GIOB7 Interrupt Polarity Select (User-priviledge/Low power mode)" "Falling/Low,Rising/High"
|
|
bitfld.long 0x04 14. " GIOPOL_1_6 ,GIOB6 Interrupt Polarity Select (User-priviledge/Low power mode)" "Falling/Low,Rising/High"
|
|
textline " "
|
|
bitfld.long 0x04 13. " GIOPOL_1_5 ,GIOB5 Interrupt Polarity Select (User-priviledge/Low power mode)" "Falling/Low,Rising/High"
|
|
bitfld.long 0x04 12. " GIOPOL_1_4 ,GIOB4 Interrupt Polarity Select (User-priviledge/Low power mode)" "Falling/Low,Rising/High"
|
|
textline " "
|
|
bitfld.long 0x04 11. " GIOPOL_1_3 ,GIOB3 Interrupt Polarity Select (User-priviledge/Low power mode)" "Falling/Low,Rising/High"
|
|
bitfld.long 0x04 10. " GIOPOL_1_2 ,GIOB2 Interrupt Polarity Select (User-priviledge/Low power mode)" "Falling/Low,Rising/High"
|
|
textline " "
|
|
bitfld.long 0x04 9. " GIOPOL_1_1 ,GIOB1 Interrupt Polarity Select (User-priviledge/Low power mode)" "Falling/Low,Rising/High"
|
|
bitfld.long 0x04 8. " GIOPOL_1_0 ,GIOB0 Interrupt Polarity Select (User-priviledge/Low power mode)" "Falling/Low,Rising/High"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x04 7. " GIOPOL_0_7 ,GIOA7 Interrupt Polarity Select (User-priviledge/Low power mode)" "Falling/Low,Rising/High"
|
|
bitfld.long 0x04 6. " GIOPOL_0_6 ,GIOA6 Interrupt Polarity Select (User-priviledge/Low power mode)" "Falling/Low,Rising/High"
|
|
textline " "
|
|
bitfld.long 0x04 5. " GIOPOL_0_5 ,GIOA5 Interrupt Polarity Select (User-priviledge/Low power mode)" "Falling/Low,Rising/High"
|
|
bitfld.long 0x04 4. " GIOPOL_0_4 ,GIOA4 Interrupt Polarity Select (User-priviledge/Low power mode)" "Falling/Low,Rising/High"
|
|
textline " "
|
|
bitfld.long 0x04 3. " GIOPOL_0_3 ,GIOA3 Interrupt Polarity Select (User-priviledge/Low power mode)" "Falling/Low,Rising/High"
|
|
bitfld.long 0x04 2. " GIOPOL_0_2 ,GIOA2 Interrupt Polarity Select (User-priviledge/Low power mode)" "Falling/Low,Rising/High"
|
|
textline " "
|
|
bitfld.long 0x04 1. " GIOPOL_0_1 ,GIOA1 Interrupt Polarity Select (User-priviledge/Low power mode)" "Falling/Low,Rising/High"
|
|
bitfld.long 0x04 0. " GIOPOL_0_0 ,GIOA0 Interrupt Polarity Select (User-priviledge/Low power mode)" "Falling/Low,Rising/High"
|
|
tree.end
|
|
tree "GIO Interrupt Enable Registers"
|
|
width 13.
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "ENA_set/clr,Interrupt Enable Set/Clr"
|
|
sif (cpu()!="RM42L432"&&cpu()!=("TMS570LS0332")&&cpu()!=("TMS570LS0432"))
|
|
sif (cpu()!="TMS570LC4357")
|
|
setclrfld.long 0x00 31. 0x00 31. 0x04 31. " GIOENA_3_7 ,GIOD7 Interrupt Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x04 30. " GIOENA_3_6 ,GIOD6 Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 29. 0x00 29. 0x04 29. " GIOENA_3_5 ,GIOD5 Interrupt Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x04 28. " GIOENA_3_4 ,GIOD4 Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 27. 0x00 27. 0x04 27. " GIOENA_3_3 ,GIOD3 Interrupt Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x04 26. " GIOENA_3_2 ,GIOD2 Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x04 25. " GIOENA_3_1 ,GIOD1 Interrupt Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x04 24. " GIOENA_3_0 ,GIOD0 Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 23. 0x00 23. 0x04 23. " GIOENA_2_7 ,GIOC7 Interrupt Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x04 22. " GIOENA_2_6 ,GIOC6 Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 21. 0x00 21. 0x04 21. " GIOENA_2_5 ,GIOC5 Interrupt Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x04 20. " GIOENA_2_4 ,GIOC4 Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x04 19. " GIOENA_2_3 ,GIOC3 Interrupt Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x04 18. " GIOENA_2_2 ,GIOC2 Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 17. 0x00 17. 0x04 17. " GIOENA_2_1 ,GIOC1 Interrupt Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x04 16. " GIOENA_2_0 ,GIOC0 Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
setclrfld.long 0x00 15. 0x00 15. 0x04 15. " GIOENA_1_7 ,GIOB7 Interrupt Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x04 14. " GIOENA_1_6 ,GIOB6 Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x04 13. " GIOENA_1_5 ,GIOB5 Interrupt Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x04 12. " GIOENA_1_4 ,GIOB4 Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 11. 0x00 11. 0x04 11. " GIOENA_1_3 ,GIOB3 Interrupt Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x04 10. " GIOENA_1_2 ,GIOB2 Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 9. 0x00 9. 0x04 9. " GIOENA_1_1 ,GIOB1 Interrupt Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x04 8. " GIOENA_1_0 ,GIOB0 Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
setclrfld.long 0x00 7. 0x00 7. 0x04 7. " GIOENA_0_7 ,GIOA7 Interrupt Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x04 6. " GIOENA_0_6 ,GIOA6 Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 5. 0x00 5. 0x04 5. " GIOENA_0_5 ,GIOA5 Interrupt Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x04 4. " GIOENA_0_4 ,GIOA4 Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 3. 0x00 3. 0x04 3. " GIOENA_0_3 ,GIOA3 Interrupt Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x04 2. " GIOENA_0_2 ,GIOA2 Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x04 1. " GIOENA_0_1 ,GIOA1 Interrupt Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x04 0. " GIOENA_0_0 ,GIOA0 Interrupt Enable" "Disabled,Enabled"
|
|
tree.end
|
|
tree "GIO Interrupt Priority Registers"
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "LVL_set/clr,Interrupt Priority Set/Clr"
|
|
sif (cpu()!="RM42L432"&&cpu()!=("TMS570LS0332")&&cpu()!=("TMS570LS0432"))
|
|
sif (cpu()!="TMS570LC4357")
|
|
setclrfld.long 0x00 31. 0x00 31. 0x00 31. " GIOLVL_3_7 ,GIOD7 High Priority Interrupt" "Low-level,High-level"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x00 30. " GIOLVL_3_6 ,GIOD6 High Priority Interrupt" "Low-level,High-level"
|
|
textline " "
|
|
setclrfld.long 0x00 29. 0x00 29. 0x00 29. " GIOLVL_3_5 ,GIOD5 High Priority Interrupt" "Low-level,High-level"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x00 28. " GIOLVL_3_4 ,GIOD4 High Priority Interrupt" "Low-level,High-level"
|
|
textline " "
|
|
setclrfld.long 0x00 27. 0x00 27. 0x00 27. " GIOLVL_3_3 ,GIOD3 High Priority Interrupt" "Low-level,High-level"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x00 26. " GIOLVL_3_2 ,GIOD2 High Priority Interrupt" "Low-level,High-level"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x00 25. " GIOLVL_3_1 ,GIOD1 High Priority Interrupt" "Low-level,High-level"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x00 24. " GIOLVL_3_0 ,GIOD0 High Priority Interrupt" "Low-level,High-level"
|
|
textline " "
|
|
setclrfld.long 0x00 23. 0x00 23. 0x00 23. " GIOLVL_2_7 ,GIOC7 High Priority Interrupt" "Low-level,High-level"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x00 22. " GIOLVL_2_6 ,GIOC6 High Priority Interrupt" "Low-level,High-level"
|
|
textline " "
|
|
setclrfld.long 0x00 21. 0x00 21. 0x00 21. " GIOLVL_2_5 ,GIOC5 High Priority Interrupt" "Low-level,High-level"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x00 20. " GIOLVL_2_4 ,GIOC4 High Priority Interrupt" "Low-level,High-level"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x00 19. " GIOLVL_2_3 ,GIOC3 High Priority Interrupt" "Low-level,High-level"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x00 18. " GIOLVL_2_2 ,GIOC2 High Priority Interrupt" "Low-level,High-level"
|
|
textline " "
|
|
setclrfld.long 0x00 17. 0x00 17. 0x00 17. " GIOLVL_2_1 ,GIOC1 High Priority Interrupt" "Low-level,High-level"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x00 16. " GIOLVL_2_0 ,GIOC0 High Priority Interrupt" "Low-level,High-level"
|
|
textline " "
|
|
endif
|
|
setclrfld.long 0x00 15. 0x00 15. 0x00 15. " GIOLVL_1_7 ,GIOB7 High Priority Interrupt" "Low-level,High-level"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x00 14. " GIOLVL_1_6 ,GIOB6 High Priority Interrupt" "Low-level,High-level"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x00 13. " GIOLVL_1_5 ,GIOB5 High Priority Interrupt" "Low-level,High-level"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x00 12. " GIOLVL_1_4 ,GIOB4 High Priority Interrupt" "Low-level,High-level"
|
|
textline " "
|
|
setclrfld.long 0x00 11. 0x00 11. 0x00 11. " GIOLVL_1_3 ,GIOB3 High Priority Interrupt" "Low-level,High-level"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x00 10. " GIOLVL_1_2 ,GIOB2 High Priority Interrupt" "Low-level,High-level"
|
|
textline " "
|
|
setclrfld.long 0x00 9. 0x00 9. 0x00 9. " GIOLVL_1_1 ,GIOB1 High Priority Interrupt" "Low-level,High-level"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x00 8. " GIOLVL_1_0 ,GIOB0 High Priority Interrupt" "Low-level,High-level"
|
|
textline " "
|
|
endif
|
|
setclrfld.long 0x00 7. 0x00 7. 0x00 7. " GIOLVL_0_7 ,GIOA7 High Priority Interrupt" "Low-level,High-level"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x00 6. " GIOLVL_0_6 ,GIOA6 High Priority Interrupt" "Low-level,High-level"
|
|
textline " "
|
|
setclrfld.long 0x00 5. 0x00 5. 0x00 5. " GIOLVL_0_5 ,GIOA5 High Priority Interrupt" "Low-level,High-level"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x00 4. " GIOLVL_0_4 ,GIOA4 High Priority Interrupt" "Low-level,High-level"
|
|
textline " "
|
|
setclrfld.long 0x00 3. 0x00 3. 0x00 3. " GIOLVL_0_3 ,GIOA3 High Priority Interrupt" "Low-level,High-level"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x00 2. " GIOLVL_0_2 ,GIOA2 High Priority Interrupt" "Low-level,High-level"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x00 1. " GIOLVL_0_1 ,GIOA1 High Priority Interrupt" "Low-level,High-level"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x00 0. " GIOLVL_0_0 ,GIOA0 High Priority Interrupt" "Low-level,High-level"
|
|
tree.end
|
|
textline " "
|
|
width 8.
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "FLG,Interrupt Flag"
|
|
sif (cpu()!="RM42L432"&&cpu()!=("TMS570LS0332")&&cpu()!=("TMS570LS0432"))
|
|
sif (cpu()!="TMS570LC4357")
|
|
eventfld.long 0x00 31. " GIOFLG_3_7 ,GIOD7 Flag" "Not occurred,Occurred"
|
|
eventfld.long 0x00 30. " GIOFLG_3_6 ,GIOD6 Flag" "Not occurred,Occurred"
|
|
textline " "
|
|
eventfld.long 0x00 29. " GIOFLG_3_5 ,GIOD5 Flag" "Not occurred,Occurred"
|
|
eventfld.long 0x00 28. " GIOFLG_3_4 ,GIOD4 Flag" "Not occurred,Occurred"
|
|
textline " "
|
|
eventfld.long 0x00 27. " GIOFLG_3_3 ,GIOD3 Flag" "Not occurred,Occurred"
|
|
eventfld.long 0x00 26. " GIOFLG_3_2 ,GIOD2 Flag" "Not occurred,Occurred"
|
|
textline " "
|
|
eventfld.long 0x00 25. " GIOFLG_3_1 ,GIOD1 Flag" "Not occurred,Occurred"
|
|
eventfld.long 0x00 24. " GIOFLG_3_0 ,GIOD0 Flag" "Not occurred,Occurred"
|
|
textline " "
|
|
eventfld.long 0x00 23. " GIOFLG_2_7 ,GIOC7 Flag" "Not occurred,Occurred"
|
|
eventfld.long 0x00 22. " GIOFLG_2_6 ,GIOC6 Flag" "Not occurred,Occurred"
|
|
textline " "
|
|
eventfld.long 0x00 21. " GIOFLG_2_5 ,GIOC5 Flag" "Not occurred,Occurred"
|
|
eventfld.long 0x00 20. " GIOFLG_2_4 ,GIOC4 Flag" "Not occurred,Occurred"
|
|
textline " "
|
|
eventfld.long 0x00 19. " GIOFLG_2_3 ,GIOC3 Flag" "Not occurred,Occurred"
|
|
eventfld.long 0x00 18. " GIOFLG_2_2 ,GIOC2 Flag" "Not occurred,Occurred"
|
|
textline " "
|
|
eventfld.long 0x00 17. " GIOFLG_2_1 ,GIOC1 Flag" "Not occurred,Occurred"
|
|
eventfld.long 0x00 16. " GIOFLG_2_0 ,GIOC0 Flag" "Not occurred,Occurred"
|
|
textline " "
|
|
endif
|
|
eventfld.long 0x00 15. " GIOFLG_1_7 ,GIOB7 Flag" "Not occurred,Occurred"
|
|
eventfld.long 0x00 14. " GIOFLG_1_6 ,GIOB6 Flag" "Not occurred,Occurred"
|
|
textline " "
|
|
eventfld.long 0x00 13. " GIOFLG_1_5 ,GIOB5 Flag" "Not occurred,Occurred"
|
|
eventfld.long 0x00 12. " GIOFLG_1_4 ,GIOB4 Flag" "Not occurred,Occurred"
|
|
textline " "
|
|
eventfld.long 0x00 11. " GIOFLG_1_3 ,GIOB3 Flag" "Not occurred,Occurred"
|
|
eventfld.long 0x00 10. " GIOFLG_1_2 ,GIOB2 Flag" "Not occurred,Occurred"
|
|
textline " "
|
|
eventfld.long 0x00 9. " GIOFLG_1_1 ,GIOB1 Flag" "Not occurred,Occurred"
|
|
eventfld.long 0x00 8. " GIOFLG_1_0 ,GIOB0 Flag" "Not occurred,Occurred"
|
|
textline " "
|
|
endif
|
|
eventfld.long 0x00 7. " GIOFLG_0_7 ,GIOA7 Flag" "Not occurred,Occurred"
|
|
eventfld.long 0x00 6. " GIOFLG_0_6 ,GIOA6 Flag" "Not occurred,Occurred"
|
|
textline " "
|
|
eventfld.long 0x00 5. " GIOFLG_0_5 ,GIOA5 Flag" "Not occurred,Occurred"
|
|
eventfld.long 0x00 4. " GIOFLG_0_4 ,GIOA4 Flag" "Not occurred,Occurred"
|
|
textline " "
|
|
eventfld.long 0x00 3. " GIOFLG_0_3 ,GIOA3 Flag" "Not occurred,Occurred"
|
|
eventfld.long 0x00 2. " GIOFLG_0_2 ,GIOA2 Flag" "Not occurred,Occurred"
|
|
textline " "
|
|
eventfld.long 0x00 1. " GIOFLG_0_1 ,GIOA1 Flag" "Not occurred,Occurred"
|
|
eventfld.long 0x00 0. " GIOFLG_0_0 ,GIOA0 Flag" "Not occurred,Occurred"
|
|
sif !cpuis("TMS570LS3137-EP")
|
|
hgroup.long 0x24++0x03
|
|
hide.long 0x00 "OFFA,Offset A"
|
|
in
|
|
else
|
|
hgroup.long 0x24++0x07
|
|
hide.long 0x00 "OFF1,Offset Register 1"
|
|
in
|
|
hide.long 0x04 "OFF2,Offset B register"
|
|
in
|
|
endif
|
|
sif !cpuis("TMS570LS3137-EP")
|
|
sif (cpu()!="TMS570LC4357"&&cpu()!=("TMS570LS0332")&&cpu()!=("TMS570LS0432"))
|
|
rgroup.long 0x2C++0x03
|
|
line.long 0x00 "EMUA,Emulation A"
|
|
bitfld.long 0x00 0.--5. " GIOEMUA ,GIO Offset A" "No interrupt,Interrupt 0,Interrupt 1,Interrupt 2,Interrupt 3,Interrupt 4,Interrupt 5,Interrupt 6,Interrupt 7,Interrupt 8,Interrupt 9,Interrupt 10,Interrupt 11,Interrupt 12,Interrupt 13,Interrupt 14,Interrupt 15,Interrupt 16,Interrupt 17,Interrupt 18,Interrupt 19,Interrupt 20,Interrupt 21,Interrupt 22,Interrupt 23,Interrupt 24,Interrupt 25,Interrupt 26,Interrupt 27,Interrupt 28,Interrupt 29,Interrupt 30,Interrupt 31,?..."
|
|
elif (cpu()==("TMS570LS0332")||cpu()==("TMS570LS0432"))
|
|
rgroup.long 0x2C++0x03
|
|
line.long 0x00 "EMUA,Emulation A"
|
|
bitfld.long 0x00 0.--5. " GIOEMUA ,GIO Offset A" "No interrupt,Interrupt 0,Interrupt 1,Interrupt 2,Interrupt 3,Interrupt 4,Interrupt 5,Interrupt 6,Interrupt 7,?..."
|
|
else
|
|
rgroup.long 0x2C++0x03
|
|
line.long 0x00 "EMUA,Emulation A"
|
|
bitfld.long 0x00 0.--5. " GIOEMUA ,GIO Offset A" "No interrupt,Interrupt 0,Interrupt 1,Interrupt 2,Interrupt 3,Interrupt 4,Interrupt 5,Interrupt 6,Interrupt 7,Interrupt 8,Interrupt 9,Interrupt 10,Interrupt 11,Interrupt 12,Interrupt 13,Interrupt 14,Interrupt 15,Interrupt 16,?..."
|
|
endif
|
|
sif (cpu()!="RM42L432"&&cpu()!=("TMS570LS0332")&&cpu()!=("TMS570LS0432"))
|
|
hgroup.long 0x28++0x03
|
|
hide.long 0x00 "OFFB,Offset B"
|
|
in
|
|
sif (cpu()!="TMS570LC4357")
|
|
rgroup.long 0x30++0x03
|
|
line.long 0x00 "EMUB,Emulation B"
|
|
bitfld.long 0x00 0.--5. " GIOEMUB ,GIO Offset B" "No interrupt,Interrupt 0,Interrupt 1,Interrupt 2,Interrupt 3,Interrupt 4,Interrupt 5,Interrupt 6,Interrupt 7,Interrupt 8,Interrupt 9,Interrupt 10,Interrupt 11,Interrupt 12,Interrupt 13,Interrupt 14,Interrupt 15,Interrupt 16,Interrupt 17,Interrupt 18,Interrupt 19,Interrupt 20,Interrupt 21,Interrupt 22,Interrupt 23,Interrupt 24,Interrupt 25,Interrupt 26,Interrupt 27,Interrupt 28,Interrupt 29,Interrupt 30,Interrupt 31,?..."
|
|
else
|
|
rgroup.long 0x30++0x03
|
|
line.long 0x00 "EMUB,Emulation B"
|
|
bitfld.long 0x00 0.--5. " GIOEMUB ,GIO Offset B" "No interrupt,Interrupt 0,Interrupt 1,Interrupt 2,Interrupt 3,Interrupt 4,Interrupt 5,Interrupt 6,Interrupt 7,Interrupt 8,Interrupt 9,Interrupt 10,Interrupt 11,Interrupt 12,Interrupt 13,Interrupt 14,Interrupt 15,Interrupt 16,?..."
|
|
endif
|
|
endif
|
|
else
|
|
rgroup.long 0x2C++0x07
|
|
line.long 0x00 "EMU1,Emulation A Register"
|
|
bitfld.long 0x00 0.--5. " GIOEMUA ,GIO Offset A" "No interrupt,Interrupt 0,Interrupt 1,Interrupt 2,Interrupt 3,Interrupt 4,Interrupt 5,Interrupt 6,Interrupt 7,Interrupt 8,Interrupt 9,Interrupt 10,Interrupt 11,Interrupt 12,Interrupt 13,Interrupt 14,Interrupt 15,Interrupt 16,Interrupt 17,Interrupt 18,Interrupt 19,Interrupt 20,Interrupt 21,Interrupt 22,Interrupt 23,Interrupt 24,Interrupt 25,Interrupt 26,Interrupt 27,Interrupt 28,Interrupt 29,Interrupt 30,Interrupt 31,?..."
|
|
line.long 0x04 "EMU2,Emulation B Register"
|
|
bitfld.long 0x04 0.--5. " GIOEMUA ,GIO Offset A" "No interrupt,Interrupt 0,Interrupt 1,Interrupt 2,Interrupt 3,Interrupt 4,Interrupt 5,Interrupt 6,Interrupt 7,Interrupt 8,Interrupt 9,Interrupt 10,Interrupt 11,Interrupt 12,Interrupt 13,Interrupt 14,Interrupt 15,Interrupt 16,Interrupt 17,Interrupt 18,Interrupt 19,Interrupt 20,Interrupt 21,Interrupt 22,Interrupt 23,Interrupt 24,Interrupt 25,Interrupt 26,Interrupt 27,Interrupt 28,Interrupt 29,Interrupt 30,Interrupt 31,?..."
|
|
endif
|
|
width 0xB
|
|
tree.end
|
|
tree "GPIO_A"
|
|
base ad:0xFFF7BC00
|
|
width 9.
|
|
rgroup.long 0x34++0x07
|
|
line.long 0x0 "DIR,Data Direction GIOA"
|
|
bitfld.long 0x00 7. " GIODIR7 ,GIO Data Direction 7" "Input,Output"
|
|
bitfld.long 0x00 6. " GIODIR6 ,GIO Data Direction 6" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x00 5. " GIODIR5 ,GIO Data Direction 5" "Input,Output"
|
|
bitfld.long 0x00 4. " GIODIR4 ,GIO Data Direction 4" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x00 3. " GIODIR3 ,GIO Data Direction 3" "Input,Output"
|
|
bitfld.long 0x00 2. " GIODIR2 ,GIO Data Direction 2" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x00 1. " GIODIR1 ,GIO Data Direction 1" "Input,Output"
|
|
bitfld.long 0x00 0. " GIODIR0 ,GIO Data Direction 0" "Input,Output"
|
|
line.long 0x04 "DIN,Data Input GIOA"
|
|
bitfld.long 0x04 7. " GIODIN7 ,GIO Data Input 7" "Low,High"
|
|
bitfld.long 0x04 6. " GIODIN6 ,GIO Data Input 6" "Low,High"
|
|
bitfld.long 0x04 5. " GIODIN5 ,GIO Data Input 5" "Low,High"
|
|
bitfld.long 0x04 4. " GIODIN4 ,GIO Data Input 4" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x04 3. " GIODIN3 ,GIO Data Input 3" "Low,High"
|
|
bitfld.long 0x04 2. " GIODIN2 ,GIO Data Input 2" "Low,High"
|
|
bitfld.long 0x04 1. " GIODIN1 ,GIO Data Input 1" "Low,High"
|
|
bitfld.long 0x04 0. " GIODIN0 ,GIO Data Input 0" "Low,High"
|
|
group.long 0x3C++0x03
|
|
line.long 0x00 "DOUT,Data Output GIOA"
|
|
setclrfld.long 0x00 7. 0x04 7. 0x08 7. " GIODOUT7_set/clr ,GIO Data Output 7" "Low,High"
|
|
setclrfld.long 0x00 6. 0x04 6. 0x08 6. " GIODOUT6_set/clr ,GIO Data Output 6" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 5. 0x04 5. 0x08 5. " GIODOUT5_set/clr ,GIO Data Output 5" "Low,High"
|
|
setclrfld.long 0x00 4. 0x04 4. 0x08 4. " GIODOUT4_set/clr ,GIO Data Output 4" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 3. 0x04 3. 0x08 3. " GIODOUT3_set/clr ,GIO Data Output 3" "Low,High"
|
|
setclrfld.long 0x00 2. 0x04 2. 0x08 2. " GIODOUT2_set/clr ,GIO Data Output 2" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x04 1. 0x08 1. " GIODOUT1_set/clr ,GIO Data Output 1" "Low,High"
|
|
setclrfld.long 0x00 0. 0x04 0. 0x08 0. " GIODOUT0_set/clr ,GIO Data Output 0" "Low,High"
|
|
group.long 0x48++0x0B
|
|
line.long 0x00 "PDR,Open Drain GIOA"
|
|
bitfld.long 0x00 7. " GIOPDR7 ,GIO Open Drain 7" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " GIOPDR6 ,GIO Open Drain 6" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " GIOPDR5 ,GIO Open Drain 5" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " GIOPDR4 ,GIO Open Drain 4" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " GIOPDR3 ,GIO Open Drain 3" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " GIOPDR2 ,GIO Open Drain 2" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " GIOPDR1 ,GIO Open Drain 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " GIOPDR0 ,GIO Open Drain 0" "Disabled,Enabled"
|
|
line.long 0x04 "PULLDIS,Pull Disable GIOA"
|
|
bitfld.long 0x04 7. " GIOPULDIS7 ,GIO Pull Disable 7" "No,Yes"
|
|
bitfld.long 0x04 6. " GIOPULDIS6 ,GIO Pull Disable 6" "No,Yes"
|
|
bitfld.long 0x04 5. " GIOPULDIS5 ,GIO Pull Disable 5" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x04 4. " GIOPULDIS4 ,GIO Pull Disable 4" "No,Yes"
|
|
bitfld.long 0x04 3. " GIOPULDIS3 ,GIO Pull Disable 3" "No,Yes"
|
|
bitfld.long 0x04 2. " GIOPULDIS2 ,GIO Pull Disable 2" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x04 1. " GIOPULDIS1 ,GIO Pull Disable 1" "No,Yes"
|
|
bitfld.long 0x04 0. " GIOPULDIS0 ,GIO Pull Disable 0" "No,Yes"
|
|
line.long 0x08 "PSL,Pull Select GIOA"
|
|
bitfld.long 0x08 7. " GIOPSL7 ,GIO Pull Select 7" "Pull down,Pull up"
|
|
bitfld.long 0x08 6. " GIOPSL6 ,GIO Pull Select 6" "Pull down,Pull up"
|
|
bitfld.long 0x08 5. " GIOPSL5 ,GIO Pull Select 5" "Pull down,Pull up"
|
|
textline " "
|
|
bitfld.long 0x08 4. " GIOPSL4 ,GIO Pull Select 4" "Pull down,Pull up"
|
|
bitfld.long 0x08 3. " GIOPSL3 ,GIO Pull Select 3" "Pull down,Pull up"
|
|
bitfld.long 0x08 2. " GIOPSL2 ,GIO Pull Select 2" "Pull down,Pull up"
|
|
textline " "
|
|
bitfld.long 0x08 1. " GIOPSL1 ,GIO Pull Select 1" "Pull down,Pull up"
|
|
bitfld.long 0x08 0. " GIOPSL0 ,GIO Pull Select 0" "Pull down,Pull up"
|
|
width 0xB
|
|
tree.end
|
|
tree "GPIO_B"
|
|
base ad:0xFFF7BC20
|
|
width 9.
|
|
rgroup.long 0x34++0x07
|
|
line.long 0x0 "DIR,Data Direction GIOB"
|
|
bitfld.long 0x00 7. " GIODIR7 ,GIO Data Direction 7" "Input,Output"
|
|
bitfld.long 0x00 6. " GIODIR6 ,GIO Data Direction 6" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x00 5. " GIODIR5 ,GIO Data Direction 5" "Input,Output"
|
|
bitfld.long 0x00 4. " GIODIR4 ,GIO Data Direction 4" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x00 3. " GIODIR3 ,GIO Data Direction 3" "Input,Output"
|
|
bitfld.long 0x00 2. " GIODIR2 ,GIO Data Direction 2" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x00 1. " GIODIR1 ,GIO Data Direction 1" "Input,Output"
|
|
bitfld.long 0x00 0. " GIODIR0 ,GIO Data Direction 0" "Input,Output"
|
|
line.long 0x04 "DIN,Data Input GIOB"
|
|
bitfld.long 0x04 7. " GIODIN7 ,GIO Data Input 7" "Low,High"
|
|
bitfld.long 0x04 6. " GIODIN6 ,GIO Data Input 6" "Low,High"
|
|
bitfld.long 0x04 5. " GIODIN5 ,GIO Data Input 5" "Low,High"
|
|
bitfld.long 0x04 4. " GIODIN4 ,GIO Data Input 4" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x04 3. " GIODIN3 ,GIO Data Input 3" "Low,High"
|
|
bitfld.long 0x04 2. " GIODIN2 ,GIO Data Input 2" "Low,High"
|
|
bitfld.long 0x04 1. " GIODIN1 ,GIO Data Input 1" "Low,High"
|
|
bitfld.long 0x04 0. " GIODIN0 ,GIO Data Input 0" "Low,High"
|
|
group.long 0x3C++0x03
|
|
line.long 0x00 "DOUT,Data Output GIOB"
|
|
setclrfld.long 0x00 7. 0x04 7. 0x08 7. " GIODOUT7_set/clr ,GIO Data Output 7" "Low,High"
|
|
setclrfld.long 0x00 6. 0x04 6. 0x08 6. " GIODOUT6_set/clr ,GIO Data Output 6" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 5. 0x04 5. 0x08 5. " GIODOUT5_set/clr ,GIO Data Output 5" "Low,High"
|
|
setclrfld.long 0x00 4. 0x04 4. 0x08 4. " GIODOUT4_set/clr ,GIO Data Output 4" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 3. 0x04 3. 0x08 3. " GIODOUT3_set/clr ,GIO Data Output 3" "Low,High"
|
|
setclrfld.long 0x00 2. 0x04 2. 0x08 2. " GIODOUT2_set/clr ,GIO Data Output 2" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x04 1. 0x08 1. " GIODOUT1_set/clr ,GIO Data Output 1" "Low,High"
|
|
setclrfld.long 0x00 0. 0x04 0. 0x08 0. " GIODOUT0_set/clr ,GIO Data Output 0" "Low,High"
|
|
group.long 0x48++0x0B
|
|
line.long 0x00 "PDR,Open Drain GIOB"
|
|
bitfld.long 0x00 7. " GIOPDR7 ,GIO Open Drain 7" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " GIOPDR6 ,GIO Open Drain 6" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " GIOPDR5 ,GIO Open Drain 5" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " GIOPDR4 ,GIO Open Drain 4" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " GIOPDR3 ,GIO Open Drain 3" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " GIOPDR2 ,GIO Open Drain 2" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " GIOPDR1 ,GIO Open Drain 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " GIOPDR0 ,GIO Open Drain 0" "Disabled,Enabled"
|
|
line.long 0x04 "PULLDIS,Pull Disable GIOB"
|
|
bitfld.long 0x04 7. " GIOPULDIS7 ,GIO Pull Disable 7" "No,Yes"
|
|
bitfld.long 0x04 6. " GIOPULDIS6 ,GIO Pull Disable 6" "No,Yes"
|
|
bitfld.long 0x04 5. " GIOPULDIS5 ,GIO Pull Disable 5" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x04 4. " GIOPULDIS4 ,GIO Pull Disable 4" "No,Yes"
|
|
bitfld.long 0x04 3. " GIOPULDIS3 ,GIO Pull Disable 3" "No,Yes"
|
|
bitfld.long 0x04 2. " GIOPULDIS2 ,GIO Pull Disable 2" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x04 1. " GIOPULDIS1 ,GIO Pull Disable 1" "No,Yes"
|
|
bitfld.long 0x04 0. " GIOPULDIS0 ,GIO Pull Disable 0" "No,Yes"
|
|
line.long 0x08 "PSL,Pull Select GIOB"
|
|
bitfld.long 0x08 7. " GIOPSL7 ,GIO Pull Select 7" "Pull down,Pull up"
|
|
bitfld.long 0x08 6. " GIOPSL6 ,GIO Pull Select 6" "Pull down,Pull up"
|
|
bitfld.long 0x08 5. " GIOPSL5 ,GIO Pull Select 5" "Pull down,Pull up"
|
|
textline " "
|
|
bitfld.long 0x08 4. " GIOPSL4 ,GIO Pull Select 4" "Pull down,Pull up"
|
|
bitfld.long 0x08 3. " GIOPSL3 ,GIO Pull Select 3" "Pull down,Pull up"
|
|
bitfld.long 0x08 2. " GIOPSL2 ,GIO Pull Select 2" "Pull down,Pull up"
|
|
textline " "
|
|
bitfld.long 0x08 1. " GIOPSL1 ,GIO Pull Select 1" "Pull down,Pull up"
|
|
bitfld.long 0x08 0. " GIOPSL0 ,GIO Pull Select 0" "Pull down,Pull up"
|
|
width 0xB
|
|
tree.end
|
|
endif
|
|
tree.end
|
|
tree.open "DCAN (Controller Area Network Module)"
|
|
tree "DCAN1"
|
|
base ad:0xFFF7DC00
|
|
sif cpuis("TMS570LS0232")||cpuis("TMS570LS0714*")||cpuis("TMS570LS0914*")
|
|
endian.be
|
|
endif
|
|
width 12.
|
|
group.long 0x00++0x3
|
|
line.long 0x0 "CTRL,Config Register"
|
|
bitfld.long 0x00 25. " WUBA ,Automatic Wake Up on Bus Activity When in Local Power Down Mode" "Not detected,Detected"
|
|
bitfld.long 0x00 24. " PDR ,Request for Local Low Power Down Mode" "Not requested,Power down"
|
|
sif (cpu()!=("TMS570LS0332")&&cpu()!=("TMS570LS0432")&&!cpuis("TMS570LS0232"))
|
|
newline
|
|
bitfld.long 0x00 20. " DE3 ,DMA Enable for IF3" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 19. " DE2 ,DMA Enable for IF2" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " DE1 ,DMA Enable for IF1" "Disabled,Enabled"
|
|
endif
|
|
newline
|
|
bitfld.long 0x00 17. " IE1 ,DCAN1INT Interrupt Enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 16. " INITDBG ,Internal Init State While Debug Access Mode" "No debug,Debug"
|
|
bitfld.long 0x00 15. " SWR ,SW Reset Enable" "No reset,Reset"
|
|
bitfld.long 0x00 10.--13. " PMD ,Parity on/off" "Enabled,Enabled,Enabled,Enabled,Enabled,Disabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 9. " ABO ,Auto Bus On Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " IDS ,Interruption Debug Support Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " TEST ,Test Mode Enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 6. " CCE ,Configuration Change Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " DAR ,Disable Automatic Retransmission" "No,Yes"
|
|
bitfld.long 0x00 3. " EIE ,Error Interrupt Enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 2. " SIE ,Status Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " IE ,DCAN0INT Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " INIT ,Initialization" "Disabled,Enabled"
|
|
sif (cpu()=="TMS470MF031"||cpu()=="TMS470MF042"||cpu()=="TMS470MF066"||cpu()==("TMS570LS10116-ZWT")||cpu()==("TMS570LS10216-ZWT")||cpu()==("TMS570LS10106-ZWT")||cpu()==("TMS570LS10206-ZWT")||cpu()==("TMS570LS10116-PGE")||cpu()==("TMS570LS10216-PGE")||cpu()==("TMS570LS10106-PGE")||cpu()==("TMS570LS10206-PGE")||cpu()==("TMS570LC4357")||cpuis("TMS570LS1114*")||cpuis("TMS570LS1115*")||cpuis("TMS570LS1224*")||cpuis("TMS570LS1225*")||cpuis("TMS570LS1227*"))
|
|
group.long 0x04++0x3
|
|
line.long 0x0 "ES,Error and Status Register"
|
|
rbitfld.long 0x00 10. " PDA ,Local Power Down Mode Acknowledge" "Not in,Is in"
|
|
rbitfld.long 0x00 9. " WAKEUPPND ,Wake Up Pending" "No requested,Requested"
|
|
rbitfld.long 0x00 8. " PER ,Parity Error Detected" "No error,Error"
|
|
newline
|
|
rbitfld.long 0x00 7. " BOFF ,Bus-Off State" "Not in,In"
|
|
rbitfld.long 0x00 6. " EWARN ,Warning state" "<96,>96"
|
|
rbitfld.long 0x00 5. " EPASS ,Error Passive State" "CAN Bus,Passive"
|
|
newline
|
|
bitfld.long 0x00 4. " RXOK ,Received a Message successfully" "No,Yes"
|
|
bitfld.long 0x00 3. " TXOK ,Transmitted a Message successfully" "No,Yes"
|
|
bitfld.long 0x00 0.--2. " LEC ,Last Error Code" "No error,Stuff,Form,Ack,Bit1,Bit0,CRC,No CAN"
|
|
elif !cpuis("TMS570LS3137-EP")
|
|
hgroup.long 0x04++0x3
|
|
hide.long 0x0 "STAT,Status Register"
|
|
in
|
|
else
|
|
if (((per.l.be(ad:0xFFF7DC00))&0x100)==0x100)
|
|
group.long 0x04++0x3
|
|
line.long 0x0 "ES,Error and Status Register"
|
|
rbitfld.long 0x00 10. " PDA ,Local Power Down Mode Acknowledge" "Not in,Is in"
|
|
rbitfld.long 0x00 9. " WAKEUPPND ,Wake Up Pending" "No requested,Requested"
|
|
rbitfld.long 0x00 8. " PER ,Parity Error Detected" "No error,Error"
|
|
newline
|
|
rbitfld.long 0x00 7. " BOFF ,Bus-Off State" "Not in,In"
|
|
rbitfld.long 0x00 6. " EWARN ,Warning state" "<96,>96"
|
|
rbitfld.long 0x00 5. " EPASS ,Error Passive State" "CAN Bus,Passive"
|
|
newline
|
|
bitfld.long 0x00 4. " RXOK ,Received a Message successfully" "No,Yes"
|
|
bitfld.long 0x00 3. " TXOK ,Transmitted a Message successfully" "No,Yes"
|
|
bitfld.long 0x00 0.--2. " LEC ,Last Error Code" "No error,Stuff,Form,Ack,Bit1,Bit0,CRC,No CAN"
|
|
else
|
|
hgroup.long 0x04++0x3
|
|
hide.long 0x0 "ES,Error and Status Register"
|
|
in
|
|
endif
|
|
endif
|
|
rgroup.long 0x08++0x3
|
|
line.long 0x0 "ERRC,Error Counter Register"
|
|
bitfld.long 0x00 15. " RP ,Receive Error Passive" "Below,Reached"
|
|
hexmask.long.byte 0x00 8.--14. 1. " REC ,Receive Error Counter"
|
|
hexmask.long.byte 0x00 0.--7. 1. " TEC ,Transmit Error Counter"
|
|
sif cpuis("TMS570LS0232")||cpuis("TMS570LS0714*")||cpuis("TMS570LS0914*")
|
|
if (((per.l.be(ad:0xFFF7DC00))&0x41)==0x41)
|
|
group.long 0x0C++0x3
|
|
line.long 0x0 "BTBRP,Bit Timing_BRP Extension Register"
|
|
bitfld.long 0x00 16.--19. " BRPE ,Baud Rate Prescaler Extension" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--14. " TSEG2 ,The Time Segment After the Sample Point" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 8.--11. " TSEG1 ,The Time Segment Before the Sample Point" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 6.--7. " SJW ,Synchronization Jump Width" "0,1,2,3"
|
|
bitfld.long 0x00 0.--5. " BRP ,Baud Rate Prescaler" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
else
|
|
rgroup.long 0x0C++0x3
|
|
line.long 0x0 "BTBRP,Bit Timing_BRP Extension Register"
|
|
bitfld.long 0x00 16.--19. " BRPE ,Baud Rate Prescaler Extension" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--14. " TSEG2 ,The Time Segment After the Sample Point" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 8.--11. " TSEG1 ,The Time Segment Before the Sample Point" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 6.--7. " SJW ,Synchronization Jump Width" "0,1,2,3"
|
|
bitfld.long 0x00 0.--5. " BRP ,Baud Rate Prescaler" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
endif
|
|
else
|
|
group.long 0x0C++0x3
|
|
line.long 0x0 "BTBRP,Bit Timing_BRP Extension Register"
|
|
bitfld.long 0x00 16.--19. " BRPE ,Baud Rate Prescaler Extension" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--14. " TSEG2 ,The Time Segment After the Sample Point" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 8.--11. " TSEG1 ,The Time Segment Before the Sample Point" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 6.--7. " SJW ,Synchronization Jump Width" "0,1,2,3"
|
|
bitfld.long 0x00 0.--5. " BRP ,Baud Rate Prescaler" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
endif
|
|
rgroup.long 0x10++0x3
|
|
line.long 0x0 "INTR,Interrupt Register"
|
|
hexmask.long.byte 0x00 16.--23. 1. " INT1ID[7-0] ,Interrupt 1 Identifier"
|
|
hexmask.long.word 0x00 0.--15. 1. " INTID[15-0] ,Interrupt Identifier"
|
|
sif cpuis("TMS570LS0232")||cpuis("TMS570LS0714*")||cpuis("TMS570LS0914*")
|
|
if (((per.l.be(ad:0xFFF7DC00))&0x41)==0x41)
|
|
group.long 0x14++0x3
|
|
line.long 0x0 "TEST,Test Register"
|
|
bitfld.long 0x00 9. " RDA ,RAM Direct Access Enable" "Normal,Enabled"
|
|
bitfld.long 0x00 8. " EXL ,External Loop Back Mode" "Normal,Enabled"
|
|
bitfld.long 0x00 7. " RX ,Receive Pin" "Dominant,Recessive"
|
|
newline
|
|
bitfld.long 0x00 5.--6. " TX1-0 ,Control of CAN_TX pin" "Normal,Sample point,Dominant,Recessive"
|
|
bitfld.long 0x00 4. " LBACK ,Loop Back Mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " SILENT ,Silent Mode" "Normal,Enabled"
|
|
else
|
|
rgroup.long 0x14++0x3
|
|
line.long 0x0 "TEST,Test Register"
|
|
bitfld.long 0x00 9. " RDA ,RAM Direct Access Enable" "Normal,Enabled"
|
|
bitfld.long 0x00 8. " EXL ,External Loop Back Mode" "Normal,Enabled"
|
|
bitfld.long 0x00 7. " RX ,Receive Pin" "Dominant,Recessive"
|
|
newline
|
|
bitfld.long 0x00 5.--6. " TX1-0 ,Control of CAN_TX pin" "Normal,Sample point,Dominant,Recessive"
|
|
bitfld.long 0x00 4. " LBACK ,Loop Back Mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " SILENT ,Silent Mode" "Normal,Enabled"
|
|
endif
|
|
elif !cpuis("TMS570LS3137-EP")
|
|
group.long 0x14++0x3
|
|
line.long 0x0 "TEST,Test Register"
|
|
bitfld.long 0x00 9. " RDA ,RAM Direct Access Enable" "Normal,Enabled"
|
|
bitfld.long 0x00 8. " EXL ,External Loop Back Mode" "Normal,Enabled"
|
|
bitfld.long 0x00 7. " RX ,Receive Pin" "Dominant,Recessive"
|
|
newline
|
|
sif (cpu()=="TMS470MF031"||cpu()=="TMS470MF042"||cpu()=="TMS470MF066"||cpu()==("TMS570LS10116-ZWT")||cpu()==("TMS570LS10216-ZWT")||cpu()==("TMS570LS10106-ZWT")||cpu()==("TMS570LS10206-ZWT")||cpu()==("TMS570LS10116-PGE")||cpu()==("TMS570LS10216-PGE")||cpu()==("TMS570LS10106-PGE")||cpu()==("TMS570LS10206-PGE")||cpu()==("TMS570LC4357")||cpu()==("TMS570LS0332")||cpu()==("TMS570LS0432")||cpuis("TMS570LS1114*")||cpuis("TMS570LS1115*")||cpuis("TMS570LS1224*")||cpuis("TMS570LS1225*")||cpuis("TMS570LS1227*")||cpuis("TMS570LS21*")||cpuis("TMS570LS31*")||cpuis("TMS570LS0232")||cpuis("TMS570LS0714*")||cpuis("TMS570LS0914*"))
|
|
bitfld.long 0x00 5.--6. " TX1-0 ,Control of CAN_TX pin" "Normal,Sample point,Dominant,Recessive"
|
|
else
|
|
bitfld.long 0x00 5.--6. " TX1-0 ,Control of CAN_TX pin" "Reset,Sample point,Dominant,Recessive"
|
|
endif
|
|
bitfld.long 0x00 4. " LBACK ,Loop Back Mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " SILENT ,Silent Mode" "Normal,Enabled"
|
|
else
|
|
if (((per.l.be(ad:0xFFF7DC00))&0x80)==0x80)
|
|
group.long 0x14++0x3
|
|
line.long 0x0 "TEST,Test Register"
|
|
bitfld.long 0x00 9. " RDA ,RAM Direct Access Enable" "Normal,Enabled"
|
|
bitfld.long 0x00 8. " EXL ,External Loop Back Mode" "Normal,Enabled"
|
|
bitfld.long 0x00 7. " RX ,Receive Pin" "Dominant,Recessive"
|
|
newline
|
|
bitfld.long 0x00 5.--6. " TX1-0 ,Control of CAN_TX pin" "Normal,Sample point,Dominant,Recessive"
|
|
bitfld.long 0x00 4. " LBACK ,Loop Back Mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " SILENT ,Silent Mode" "Normal,Enabled"
|
|
else
|
|
rgroup.long 0x14++0x3
|
|
line.long 0x0 "TEST,Test Register"
|
|
bitfld.long 0x00 9. " RDA ,RAM Direct Access Enable" "Normal,Enabled"
|
|
bitfld.long 0x00 8. " EXL ,External Loop Back Mode" "Normal,Enabled"
|
|
bitfld.long 0x00 7. " RX ,Receive Pin" "Dominant,Recessive"
|
|
newline
|
|
bitfld.long 0x00 5.--6. " TX1-0 ,Control of CAN_TX pin" "Normal,Sample point,Dominant,Recessive"
|
|
bitfld.long 0x00 4. " LBACK ,Loop Back Mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " SILENT ,Silent Mode" "Normal,Enabled"
|
|
endif
|
|
endif
|
|
rgroup.long 0x1C++0x3
|
|
line.long 0x0 "PERR,Parity Error Code Register"
|
|
bitfld.long 0x00 8.--10. " WORD_NUMBER ,Word Number" ",1,2,3,4,5,?..."
|
|
hexmask.long.byte 0x00 0.--7. 1. " MESSAGE_NUMBER ,Message Number"
|
|
sif (cpu()=="TMS470MF031"||cpu()=="TMS470MF042"||cpu()=="TMS470MF066"||cpuis("TMS570LS0232")||cpuis("TMS570LS0714*")||cpuis("TMS570LS0914*"))
|
|
rgroup.long 0x20++0x3
|
|
line.long 0x00 "REL,DCAN Core Release Register"
|
|
bitfld.long 0x00 28.--31. " REL ,Core Release" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 24.--27. " STEP ,Step of Core Release" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 20.--23. " SUBSTEP ,Substep of Core Release" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " YEAR ,Design Time Stamp - Year" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. " MON ,Design Time Stamp - Month"
|
|
hexmask.long.byte 0x00 0.--7. 1. " DAY ,Design Time Stamp - Day"
|
|
endif
|
|
width 19.
|
|
sif (cpu()=="TMS570LC4357")
|
|
group.long 0x24++0x0B
|
|
line.long 0x00 "DCAN_ECCDIAG,ECC Diagnostic Register"
|
|
bitfld.long 0x00 0.--3. " ECCDIAG , SECDED diagnostic mode enable/disable" ",,,,,Enabled,,,,,Disabled,?..."
|
|
line.long 0x04 "DCAN_ECCDIAG_STAT, ECC Diagnostic Status Register"
|
|
eventfld.long 0x04 8. " DEFLG_DIAG , Double bit error diagnostic" "No error,Error"
|
|
eventfld.long 0x04 0. " SEFLG_DIAG , Single bit error diagnostic" "No error,Error"
|
|
line.long 0x08 "DCAN_ECC_CS, ECC Control and Status Register"
|
|
bitfld.long 0x08 24.--27. " SBE_EVT_EN , Single bit error event" "Enabled,Enabled,Enabled,Enabled,Enabled,Disabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled"
|
|
bitfld.long 0x08 16.--19. " ECCMODE , Single bit error correction" "Enabled,Enabled,Enabled,Enabled,Enabled,Disabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled"
|
|
eventfld.long 0x08 8. " DEFLG , Double bit error flag" "No error,Error"
|
|
eventfld.long 0x08 0. " SEFLG , Single bit error flag" "No error,Error"
|
|
rgroup.long 0x30++0x03
|
|
line.long 0x00 "DCAN_ECC_SERR, ECC Single Bit Error Code Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " Message_Number , Message object number where ECC single bit error has been detected"
|
|
endif
|
|
width 12.
|
|
group.long 0x80++0x03
|
|
line.long 0x00 "ABOT,Auto Bus On Time"
|
|
rgroup.long 0x84++0x4F
|
|
line.long 0x00 "TRREQ,Transmission Request X"
|
|
bitfld.long 0x00 14.--15. " TXRQSTREG8 ,Transmission Request 8" "0,1,2,3"
|
|
bitfld.long 0x00 12.--13. " TXRQSTREG7 ,Transmission Request 7" "0,1,2,3"
|
|
bitfld.long 0x00 10.--11. " TXRQSTREG6 ,Transmission Request 6" "0,1,2,3"
|
|
bitfld.long 0x00 8.--9. " TXRQSTREG5 ,Transmission Request 5" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 6.--7. " TXRQSTREG4 ,Transmission Request 4" "0,1,2,3"
|
|
bitfld.long 0x00 4.--5. " TXRQSTREG3 ,Transmission Request 3" "0,1,2,3"
|
|
bitfld.long 0x00 2.--3. " TXRQSTREG2 ,Transmission Request 2" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. " TXRQSTREG1 ,Transmission Request 1" "0,1,2,3"
|
|
line.long 0x04 "TRREQ12,Transmission Request 1-2"
|
|
bitfld.long 0x04 31. " TXRQST[32] ,Transmission Request Bits[32]" "Not requested,Requested"
|
|
bitfld.long 0x04 30. " [31] ,Transmission Request Bits[31]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x04 29. " [30] ,Transmission Request Bits[30]" "Not requested,Requested"
|
|
bitfld.long 0x04 28. " [29] ,Transmission Request Bits[29]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x04 27. " [28] ,Transmission Request Bits[28]" "Not requested,Requested"
|
|
bitfld.long 0x04 26. " [27] ,Transmission Request Bits[27]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x04 25. " [26] ,Transmission Request Bits[26]" "Not requested,Requested"
|
|
bitfld.long 0x04 24. " [25] ,Transmission Request Bits[25]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x04 23. " [24] ,Transmission Request Bits[24]" "Not requested,Requested"
|
|
bitfld.long 0x04 22. " [23] ,Transmission Request Bits[23]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x04 21. " [22] ,Transmission Request Bits[22]" "Not requested,Requested"
|
|
bitfld.long 0x04 20. " [21] ,Transmission Request Bits[21]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x04 19. " [20] ,Transmission Request Bits[20]" "Not requested,Requested"
|
|
bitfld.long 0x04 18. " [19] ,Transmission Request Bits[19]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x04 17. " [18] ,Transmission Request Bits[18]" "Not requested,Requested"
|
|
bitfld.long 0x04 16. " [17] ,Transmission Request Bits[17]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x04 15. " [16] ,Transmission Request Bits[16]" "Not requested,Requested"
|
|
bitfld.long 0x04 14. " [15] ,Transmission Request Bits[15]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x04 13. " [14] ,Transmission Request Bits[14]" "Not requested,Requested"
|
|
bitfld.long 0x04 12. " [13] ,Transmission Request Bits[13]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x04 11. " [12] ,Transmission Request Bits[12]" "Not requested,Requested"
|
|
bitfld.long 0x04 10. " [11] ,Transmission Request Bits[11]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x04 9. " [10] ,Transmission Request Bits[10]" "Not requested,Requested"
|
|
bitfld.long 0x04 8. " [9] ,Transmission Request Bits[9]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x04 7. " [8] ,Transmission Request Bits[8]" "Not requested,Requested"
|
|
bitfld.long 0x04 6. " [7] ,Transmission Request Bits[7]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x04 5. " [6] ,Transmission Request Bits[6]" "Not requested,Requested"
|
|
bitfld.long 0x04 4. " [5] ,Transmission Request Bits[5]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x04 3. " [4] ,Transmission Request Bits[4]" "Not requested,Requested"
|
|
bitfld.long 0x04 2. " [3] ,Transmission Request Bits[3]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x04 1. " [2] ,Transmission Request Bits[2]" "Not requested,Requested"
|
|
bitfld.long 0x04 0. " [1] ,Transmission Request Bits[1]" "Not requested,Requested"
|
|
line.long 0x08 "TRREQ34,Transmission Request 3-4"
|
|
bitfld.long 0x08 31. " TXRQST[64] ,Transmission Request Bits[64]" "Not requested,Requested"
|
|
bitfld.long 0x08 30. " [63] ,Transmission Request Bits[63]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x08 29. " [62] ,Transmission Request Bits[62]" "Not requested,Requested"
|
|
bitfld.long 0x08 28. " [61] ,Transmission Request Bits[61]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x08 27. " [60] ,Transmission Request Bits[60]" "Not requested,Requested"
|
|
bitfld.long 0x08 26. " [59] ,Transmission Request Bits[59]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x08 25. " [58] ,Transmission Request Bits[58]" "Not requested,Requested"
|
|
bitfld.long 0x08 24. " [57] ,Transmission Request Bits[57]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x08 23. " [56] ,Transmission Request Bits[56]" "Not requested,Requested"
|
|
bitfld.long 0x08 22. " [55] ,Transmission Request Bits[55]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x08 21. " [54] ,Transmission Request Bits[54]" "Not requested,Requested"
|
|
bitfld.long 0x08 20. " [53] ,Transmission Request Bits[53]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x08 19. " [52] ,Transmission Request Bits[52]" "Not requested,Requested"
|
|
bitfld.long 0x08 18. " [51] ,Transmission Request Bits[51]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x08 17. " [50] ,Transmission Request Bits[50]" "Not requested,Requested"
|
|
bitfld.long 0x08 16. " [49] ,Transmission Request Bits[49]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x08 15. " [48] ,Transmission Request Bits[48]" "Not requested,Requested"
|
|
bitfld.long 0x08 14. " [47] ,Transmission Request Bits[47]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x08 13. " [46] ,Transmission Request Bits[46]" "Not requested,Requested"
|
|
bitfld.long 0x08 12. " [45] ,Transmission Request Bits[45]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x08 11. " [44] ,Transmission Request Bits[44]" "Not requested,Requested"
|
|
bitfld.long 0x08 10. " [43] ,Transmission Request Bits[43]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x08 9. " [42] ,Transmission Request Bits[42]" "Not requested,Requested"
|
|
bitfld.long 0x08 8. " [41] ,Transmission Request Bits[41]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x08 7. " [40] ,Transmission Request Bits[40]" "Not requested,Requested"
|
|
bitfld.long 0x08 6. " [39] ,Transmission Request Bits[39]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x08 5. " [38] ,Transmission Request Bits[38]" "Not requested,Requested"
|
|
bitfld.long 0x08 4. " [37] ,Transmission Request Bits[37]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x08 3. " [36] ,Transmission Request Bits[36]" "Not requested,Requested"
|
|
bitfld.long 0x08 2. " [35] ,Transmission Request Bits[35]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x08 1. " [34] ,Transmission Request Bits[34]" "Not requested,Requested"
|
|
bitfld.long 0x08 0. " [33] ,Transmission Request Bits[33]" "Not requested,Requested"
|
|
line.long 0x0C "TRREQ56,Transmission Request 5-6"
|
|
bitfld.long 0x0C 31. " TXRQST[96] ,Transmission Request Bits[96]" "Not requested,Requested"
|
|
bitfld.long 0x0C 30. " [95] ,Transmission Request Bits[95]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x0C 29. " [94] ,Transmission Request Bits[94]" "Not requested,Requested"
|
|
bitfld.long 0x0C 28. " [93] ,Transmission Request Bits[93]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x0C 27. " [92] ,Transmission Request Bits[92]" "Not requested,Requested"
|
|
bitfld.long 0x0C 26. " [91] ,Transmission Request Bits[91]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x0C 25. " [90] ,Transmission Request Bits[90]" "Not requested,Requested"
|
|
bitfld.long 0x0C 24. " [89] ,Transmission Request Bits[89]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x0C 23. " [88] ,Transmission Request Bits[88]" "Not requested,Requested"
|
|
bitfld.long 0x0C 22. " [87] ,Transmission Request Bits[87]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x0C 21. " [86] ,Transmission Request Bits[86]" "Not requested,Requested"
|
|
bitfld.long 0x0C 20. " [85] ,Transmission Request Bits[85]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x0C 19. " [84] ,Transmission Request Bits[84]" "Not requested,Requested"
|
|
bitfld.long 0x0C 18. " [83] ,Transmission Request Bits[83]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x0C 17. " [82] ,Transmission Request Bits[82]" "Not requested,Requested"
|
|
bitfld.long 0x0C 16. " [81] ,Transmission Request Bits[81]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x0C 15. " [80] ,Transmission Request Bits[80]" "Not requested,Requested"
|
|
bitfld.long 0x0C 14. " [79] ,Transmission Request Bits[79]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x0C 13. " [78] ,Transmission Request Bits[78]" "Not requested,Requested"
|
|
bitfld.long 0x0C 12. " [77] ,Transmission Request Bits[77]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x0C 11. " [76] ,Transmission Request Bits[76]" "Not requested,Requested"
|
|
bitfld.long 0x0C 10. " [75] ,Transmission Request Bits[75]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x0C 9. " [74] ,Transmission Request Bits[74]" "Not requested,Requested"
|
|
bitfld.long 0x0C 8. " [73] ,Transmission Request Bits[73]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x0C 7. " [72] ,Transmission Request Bits[72]" "Not requested,Requested"
|
|
bitfld.long 0x0C 6. " [71] ,Transmission Request Bits[71]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x0C 5. " [70] ,Transmission Request Bits[70]" "Not requested,Requested"
|
|
bitfld.long 0x0C 4. " [69] ,Transmission Request Bits[69]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x0C 3. " [68] ,Transmission Request Bits[68]" "Not requested,Requested"
|
|
bitfld.long 0x0C 2. " [67] ,Transmission Request Bits[67]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x0C 1. " [66] ,Transmission Request Bits[66]" "Not requested,Requested"
|
|
bitfld.long 0x0C 0. " [65] ,Transmission Request Bits[65]" "Not requested,Requested"
|
|
line.long 0x10 "TRREQ78,Transmission Request 7-8"
|
|
bitfld.long 0x10 31. " TXRQST[128] ,Transmission Request Bits[128]" "Not requested,Requested"
|
|
bitfld.long 0x10 30. " [127] ,Transmission Request Bits[127]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x10 29. " [126] ,Transmission Request Bits[126]" "Not requested,Requested"
|
|
bitfld.long 0x10 28. " [125] ,Transmission Request Bits[125]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x10 27. " [124] ,Transmission Request Bits[124]" "Not requested,Requested"
|
|
bitfld.long 0x10 26. " [123] ,Transmission Request Bits[123]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x10 25. " [122] ,Transmission Request Bits[122]" "Not requested,Requested"
|
|
bitfld.long 0x10 24. " [121] ,Transmission Request Bits[121]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x10 23. " [120] ,Transmission Request Bits[120]" "Not requested,Requested"
|
|
bitfld.long 0x10 22. " [119] ,Transmission Request Bits[119]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x10 21. " [118] ,Transmission Request Bits[118]" "Not requested,Requested"
|
|
bitfld.long 0x10 20. " [117] ,Transmission Request Bits[117]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x10 19. " [116] ,Transmission Request Bits[116]" "Not requested,Requested"
|
|
bitfld.long 0x10 18. " [115] ,Transmission Request Bits[115]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x10 17. " [114] ,Transmission Request Bits[114]" "Not requested,Requested"
|
|
bitfld.long 0x10 16. " [113] ,Transmission Request Bits[113]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x10 15. " [112] ,Transmission Request Bits[112]" "Not requested,Requested"
|
|
bitfld.long 0x10 14. " [111] ,Transmission Request Bits[111]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x10 13. " [110] ,Transmission Request Bits[110]" "Not requested,Requested"
|
|
bitfld.long 0x10 12. " [109] ,Transmission Request Bits[109]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x10 11. " [108] ,Transmission Request Bits[108]" "Not requested,Requested"
|
|
bitfld.long 0x10 10. " [107] ,Transmission Request Bits[107]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x10 9. " [106] ,Transmission Request Bits[106]" "Not requested,Requested"
|
|
bitfld.long 0x10 8. " [105] ,Transmission Request Bits[105]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x10 7. " [104] ,Transmission Request Bits[104]" "Not requested,Requested"
|
|
bitfld.long 0x10 6. " [103] ,Transmission Request Bits[103]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x10 5. " [102] ,Transmission Request Bits[102]" "Not requested,Requested"
|
|
bitfld.long 0x10 4. " [101] ,Transmission Request Bits[101]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x10 3. " [100] ,Transmission Request Bits[100]" "Not requested,Requested"
|
|
bitfld.long 0x10 2. " [99] ,Transmission Request Bits[99]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x10 1. " [98] ,Transmission Request Bits[98]" "Not requested,Requested"
|
|
bitfld.long 0x10 0. " [97] ,Transmission Request Bits[97]" "Not requested,Requested"
|
|
line.long 0x14 "NEWDAT,New Data X"
|
|
bitfld.long 0x14 14.--15. " NEWDATREG8 ,New Data 8" "0,1,2,3"
|
|
bitfld.long 0x14 12.--13. " NEWDATREG7 ,New Data 7" "0,1,2,3"
|
|
bitfld.long 0x14 10.--11. " NEWDATREG6 ,New Data 6" "0,1,2,3"
|
|
bitfld.long 0x14 8.--9. " NEWDATREG5 ,New Data 5" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x14 6.--7. " NEWDATREG4 ,NEW DATA 4" "0,1,2,3"
|
|
bitfld.long 0x14 4.--5. " NEWDATREG3 ,New Data 3" "0,1,2,3"
|
|
bitfld.long 0x14 2.--3. " NEWDATREG2 ,New Data 2" "0,1,2,3"
|
|
bitfld.long 0x14 0.--1. " NEWDATREG1 ,New Data 1" "0,1,2,3"
|
|
line.long 0x18 "NEWDAT12,New Data 1-2"
|
|
bitfld.long 0x18 31. " NEWDAT[32] ,New Data Bit[32]" "Not requested,Requested"
|
|
bitfld.long 0x18 30. " [31] ,New Data Bit[31]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x18 29. " [30] ,New Data Bit[30]" "Not requested,Requested"
|
|
bitfld.long 0x18 28. " [29] ,New Data Bit[29]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x18 27. " [28] ,New Data Bit[28]" "Not requested,Requested"
|
|
bitfld.long 0x18 26. " [27] ,New Data Bit[27]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x18 25. " [26] ,New Data Bit[26]" "Not requested,Requested"
|
|
bitfld.long 0x18 24. " [25] ,New Data Bit[25]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x18 23. " [24] ,New Data Bit[24]" "Not requested,Requested"
|
|
bitfld.long 0x18 22. " [23] ,New Data Bit[23]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x18 21. " [22] ,New Data Bit[22]" "Not requested,Requested"
|
|
bitfld.long 0x18 20. " [21] ,New Data Bit[21]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x18 19. " [20] ,New Data Bit[20]" "Not requested,Requested"
|
|
bitfld.long 0x18 18. " [19] ,New Data Bit[19]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x18 17. " [18] ,New Data Bit[18]" "Not requested,Requested"
|
|
bitfld.long 0x18 16. " [17] ,New Data Bit[17]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x18 15. " [16] ,New Data Bit[16]" "Not requested,Requested"
|
|
bitfld.long 0x18 14. " [15] ,New Data Bit[15]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x18 13. " [14] ,New Data Bit[14]" "Not requested,Requested"
|
|
bitfld.long 0x18 12. " [13] ,New Data Bit[13]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x18 11. " [12] ,New Data Bit[12]" "Not requested,Requested"
|
|
bitfld.long 0x18 10. " [11] ,New Data Bit[11]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x18 9. " [10] ,New Data Bit[10]" "Not requested,Requested"
|
|
bitfld.long 0x18 8. " [9] ,New Data Bit[9]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x18 7. " [8] ,New Data Bit[8]" "Not requested,Requested"
|
|
bitfld.long 0x18 6. " [7] ,New Data Bit[7]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x18 5. " [6] ,New Data Bit[6]" "Not requested,Requested"
|
|
bitfld.long 0x18 4. " [5] ,New Data Bit[5]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x18 3. " [4] ,New Data Bit[4]" "Not requested,Requested"
|
|
bitfld.long 0x18 2. " [3] ,New Data Bit[3]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x18 1. " [2] ,New Data Bit[2]" "Not requested,Requested"
|
|
bitfld.long 0x18 0. " [1] ,New Data Bit[1]" "Not requested,Requested"
|
|
line.long 0x1C "NEWDAT34,New Data 3-4"
|
|
bitfld.long 0x1C 31. " NEWDAT[64] ,New Data Bit[64]" "Not requested,Requested"
|
|
bitfld.long 0x1C 30. " [63] ,New Data Bit[63]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x1C 29. " [62] ,New Data Bit[62]" "Not requested,Requested"
|
|
bitfld.long 0x1C 28. " [61] ,New Data Bit[61]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x1C 27. " [60] ,New Data Bit[60]" "Not requested,Requested"
|
|
bitfld.long 0x1C 26. " [59] ,New Data Bit[59]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x1C 25. " [58] ,New Data Bit[58]" "Not requested,Requested"
|
|
bitfld.long 0x1C 24. " [57] ,New Data Bit[57]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x1C 23. " [56] ,New Data Bit[56]" "Not requested,Requested"
|
|
bitfld.long 0x1C 22. " [55] ,New Data Bit[55]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x1C 21. " [54] ,New Data Bit[54]" "Not requested,Requested"
|
|
bitfld.long 0x1C 20. " [53] ,New Data Bit[53]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x1C 19. " [52] ,New Data Bit[52]" "Not requested,Requested"
|
|
bitfld.long 0x1C 18. " [51] ,New Data Bit[51]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x1C 17. " [50] ,New Data Bit[50]" "Not requested,Requested"
|
|
bitfld.long 0x1C 16. " [49] ,New Data Bit[49]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x1C 15. " [48] ,New Data Bit[48]" "Not requested,Requested"
|
|
bitfld.long 0x1C 14. " [47] ,New Data Bit[47]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x1C 13. " [46] ,New Data Bit[46]" "Not requested,Requested"
|
|
bitfld.long 0x1C 12. " [45] ,New Data Bit[45]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x1C 11. " [44] ,New Data Bit[44]" "Not requested,Requested"
|
|
bitfld.long 0x1C 10. " [43] ,New Data Bit[43]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x1C 9. " [42] ,New Data Bit[42]" "Not requested,Requested"
|
|
bitfld.long 0x1C 8. " [41] ,New Data Bit[41]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x1C 7. " [40] ,New Data Bit[40]" "Not requested,Requested"
|
|
bitfld.long 0x1C 6. " [39] ,New Data Bit[39]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x1C 5. " [38] ,New Data Bit[38]" "Not requested,Requested"
|
|
bitfld.long 0x1C 4. " [37] ,New Data Bit[37]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x1C 3. " [36] ,New Data Bit[36]" "Not requested,Requested"
|
|
bitfld.long 0x1C 2. " [35] ,New Data Bit[35]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x1C 1. " [34] ,New Data Bit[34]" "Not requested,Requested"
|
|
bitfld.long 0x1C 0. " [33] ,New Data Bit[33]" "Not requested,Requested"
|
|
line.long 0x20 "NEWDAT56,New Data 5-6"
|
|
bitfld.long 0x20 31. " NEWDAT[96] ,New Data Bit[96]" "Not requested,Requested"
|
|
bitfld.long 0x20 30. " [95] ,New Data Bit[95]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x20 29. " [94] ,New Data Bit[94]" "Not requested,Requested"
|
|
bitfld.long 0x20 28. " [93] ,New Data Bit[93]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x20 27. " [92] ,New Data Bit[92]" "Not requested,Requested"
|
|
bitfld.long 0x20 26. " [91] ,New Data Bit[91]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x20 25. " [90] ,New Data Bit[90]" "Not requested,Requested"
|
|
bitfld.long 0x20 24. " [89] ,New Data Bit[89]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x20 23. " [88] ,New Data Bit[88]" "Not requested,Requested"
|
|
bitfld.long 0x20 22. " [87] ,New Data Bit[87]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x20 21. " [86] ,New Data Bit[86]" "Not requested,Requested"
|
|
bitfld.long 0x20 20. " [85] ,New Data Bit[85]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x20 19. " [84] ,New Data Bit[84]" "Not requested,Requested"
|
|
bitfld.long 0x20 18. " [83] ,New Data Bit[83]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x20 17. " [82] ,New Data Bit[82]" "Not requested,Requested"
|
|
bitfld.long 0x20 16. " [81] ,New Data Bit[81]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x20 15. " [80] ,New Data Bit[80]" "Not requested,Requested"
|
|
bitfld.long 0x20 14. " [79] ,New Data Bit[79]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x20 13. " [78] ,New Data Bit[78]" "Not requested,Requested"
|
|
bitfld.long 0x20 12. " [77] ,New Data Bit[77]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x20 11. " [76] ,New Data Bit[76]" "Not requested,Requested"
|
|
bitfld.long 0x20 10. " [75] ,New Data Bit[75]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x20 9. " [74] ,New Data Bit[74]" "Not requested,Requested"
|
|
bitfld.long 0x20 8. " [73] ,New Data Bit[73]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x20 7. " [72] ,New Data Bit[72]" "Not requested,Requested"
|
|
bitfld.long 0x20 6. " [71] ,New Data Bit[71]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x20 5. " [70] ,New Data Bit[70]" "Not requested,Requested"
|
|
bitfld.long 0x20 4. " [69] ,New Data Bit[69]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x20 3. " [68] ,New Data Bit[68]" "Not requested,Requested"
|
|
bitfld.long 0x20 2. " [67] ,New Data Bit[67]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x20 1. " [66] ,New Data Bit[66]" "Not requested,Requested"
|
|
bitfld.long 0x20 0. " [65] ,New Data Bit[65]" "Not requested,Requested"
|
|
line.long 0x24 "NEWDAT78,New Data 7-8"
|
|
bitfld.long 0x24 31. " NEWDAT[128] ,New Data Bit[128]" "Not requested,Requested"
|
|
bitfld.long 0x24 30. " [127] ,New Data Bit[127]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x24 29. " [126] ,New Data Bit[126]" "Not requested,Requested"
|
|
bitfld.long 0x24 28. " [125] ,New Data Bit[125]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x24 27. " [124] ,New Data Bit[124]" "Not requested,Requested"
|
|
bitfld.long 0x24 26. " [123] ,New Data Bit[123]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x24 25. " [122] ,New Data Bit[122]" "Not requested,Requested"
|
|
bitfld.long 0x24 24. " [121] ,New Data Bit[121]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x24 23. " [120] ,New Data Bit[120]" "Not requested,Requested"
|
|
bitfld.long 0x24 22. " [119] ,New Data Bit[119]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x24 21. " [118] ,New Data Bit[118]" "Not requested,Requested"
|
|
bitfld.long 0x24 20. " [117] ,New Data Bit[117]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x24 19. " [116] ,New Data Bit[116]" "Not requested,Requested"
|
|
bitfld.long 0x24 18. " [115] ,New Data Bit[115]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x24 17. " [114] ,New Data Bit[114]" "Not requested,Requested"
|
|
bitfld.long 0x24 16. " [113] ,New Data Bit[113]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x24 15. " [112] ,New Data Bit[112]" "Not requested,Requested"
|
|
bitfld.long 0x24 14. " [111] ,New Data Bit[111]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x24 13. " [110] ,New Data Bit[110]" "Not requested,Requested"
|
|
bitfld.long 0x24 12. " [109] ,New Data Bit[109]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x24 11. " [108] ,New Data Bit[108]" "Not requested,Requested"
|
|
bitfld.long 0x24 10. " [107] ,New Data Bit[107]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x24 9. " [106] ,New Data Bit[106]" "Not requested,Requested"
|
|
bitfld.long 0x24 8. " [105] ,New Data Bit[105]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x24 7. " [104] ,New Data Bit[104]" "Not requested,Requested"
|
|
bitfld.long 0x24 6. " [103] ,New Data Bit[103]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x24 5. " [102] ,New Data Bit[102]" "Not requested,Requested"
|
|
bitfld.long 0x24 4. " [101] ,New Data Bit[101]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x24 3. " [100] ,New Data Bit[100]" "Not requested,Requested"
|
|
bitfld.long 0x24 2. " [99] ,New Data Bit[99]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x24 1. " [98] ,New Data Bit[98]" "Not requested,Requested"
|
|
bitfld.long 0x24 0. " [97] ,New Data Bit[97]" "Not requested,Requested"
|
|
line.long 0x28 "INTPEN,Interrupt Pending X"
|
|
bitfld.long 0x28 14.--15. " INTPENDREG[8] ,Interrupt Pending 8" "0,1,2,3"
|
|
bitfld.long 0x28 12.--13. " [7] ,Interrupt Pending 7" "0,1,2,3"
|
|
bitfld.long 0x28 10.--11. " [6] ,Interrupt Pending 6" "0,1,2,3"
|
|
bitfld.long 0x28 8.--9. " [5] ,Interrupt Pending 5" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x28 6.--7. " [4] ,Interrupt Pending 4" "0,1,2,3"
|
|
bitfld.long 0x28 4.--5. " [3] ,Interrupt Pending 3" "0,1,2,3"
|
|
bitfld.long 0x28 2.--3. " [2] ,Interrupt Pending 2" "0,1,2,3"
|
|
bitfld.long 0x28 0.--1. " [1] ,Interrupt Pending 1" "0,1,2,3"
|
|
line.long 0x2C "INTPEN12,Interrupt Pending 1-2"
|
|
bitfld.long 0x2C 31. " IntPnd[32] ,Interrupt Pending Bit[32]" "No interrupt,Interrupt"
|
|
bitfld.long 0x2C 30. " [31] ,Interrupt Pending Bit[31]" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x2C 29. " [30] ,Interrupt Pending Bit[30]" "No interrupt,Interrupt"
|
|
bitfld.long 0x2C 28. " [29] ,Interrupt Pending Bit[29]" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x2C 27. " [28] ,Interrupt Pending Bit[28]" "No interrupt,Interrupt"
|
|
bitfld.long 0x2C 26. " [27] ,Interrupt Pending Bit[27]" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x2C 25. " [26] ,Interrupt Pending Bit[26]" "No interrupt,Interrupt"
|
|
bitfld.long 0x2C 24. " [25] ,Interrupt Pending Bit[25]" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x2C 23. " [24] ,Interrupt Pending Bit[24]" "No interrupt,Interrupt"
|
|
bitfld.long 0x2C 22. " [23] ,Interrupt Pending Bit[23]" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x2C 21. " [22] ,Interrupt Pending Bit[22]" "No interrupt,Interrupt"
|
|
bitfld.long 0x2C 20. " [21] ,Interrupt Pending Bit[21]" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x2C 19. " [20] ,Interrupt Pending Bit[20]" "No interrupt,Interrupt"
|
|
bitfld.long 0x2C 18. " [19] ,Interrupt Pending Bit[19]" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x2C 17. " [18] ,Interrupt Pending Bit[18]" "No interrupt,Interrupt"
|
|
bitfld.long 0x2C 16. " [17] ,Interrupt Pending Bit[17]" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x2C 15. " [16] ,Interrupt Pending Bit[16]" "No interrupt,Interrupt"
|
|
bitfld.long 0x2C 14. " [15] ,Interrupt Pending Bit[15]" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x2C 13. " [14] ,Interrupt Pending Bit[14]" "No interrupt,Interrupt"
|
|
bitfld.long 0x2C 12. " [13] ,Interrupt Pending Bit[13]" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x2C 11. " [12] ,Interrupt Pending Bit[12]" "No interrupt,Interrupt"
|
|
bitfld.long 0x2C 10. " [11] ,Interrupt Pending Bit[11]" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x2C 9. " [10] ,Interrupt Pending Bit[10]" "No interrupt,Interrupt"
|
|
bitfld.long 0x2C 8. " [9] ,Interrupt Pending Bit[9]" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x2C 7. " [8] ,Interrupt Pending Bit[8]" "No interrupt,Interrupt"
|
|
bitfld.long 0x2C 6. " [7] ,Interrupt Pending Bit[7]" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x2C 5. " [6] ,Interrupt Pending Bit[6]" "No interrupt,Interrupt"
|
|
bitfld.long 0x2C 4. " [5] ,Interrupt Pending Bit[5]" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x2C 3. " [4] ,Interrupt Pending Bit[4]" "No interrupt,Interrupt"
|
|
bitfld.long 0x2C 2. " [3] ,Interrupt Pending Bit[3]" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x2C 1. " [2] ,Interrupt Pending Bit[2]" "No interrupt,Interrupt"
|
|
bitfld.long 0x2C 0. " [1] ,Interrupt Pending Bit[1]" "No interrupt,Interrupt"
|
|
line.long 0x30 "INTPEN34,Interrupt Pending 3-4"
|
|
bitfld.long 0x30 31. " INTPND[64] ,Interrupt Pending Bit[64]" "No interrupt,Interrupt"
|
|
bitfld.long 0x30 30. " [63] ,Interrupt Pending Bit[63]" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x30 29. " [62] ,Interrupt Pending Bit[62]" "No interrupt,Interrupt"
|
|
bitfld.long 0x30 28. " [61] ,Interrupt Pending Bit[61]" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x30 27. " [60] ,Interrupt Pending Bit[60]" "No interrupt,Interrupt"
|
|
bitfld.long 0x30 26. " [59] ,Interrupt Pending Bit[59]" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x30 25. " [58] ,Interrupt Pending Bit[58]" "No interrupt,Interrupt"
|
|
bitfld.long 0x30 24. " [57] ,Interrupt Pending Bit[57]" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x30 23. " [56] ,Interrupt Pending Bit[56]" "No interrupt,Interrupt"
|
|
bitfld.long 0x30 22. " [55] ,Interrupt Pending Bit[55]" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x30 21. " [54] ,Interrupt Pending Bit[54]" "No interrupt,Interrupt"
|
|
bitfld.long 0x30 20. " [53] ,Interrupt Pending Bit[53]" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x30 19. " [52] ,Interrupt Pending Bit[52]" "No interrupt,Interrupt"
|
|
bitfld.long 0x30 18. " [51] ,Interrupt Pending Bit[51]" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x30 17. " [50] ,Interrupt Pending Bit[50]" "No interrupt,Interrupt"
|
|
bitfld.long 0x30 16. " [49] ,Interrupt Pending Bit[49]" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x30 15. " [48] ,Interrupt Pending Bit[48]" "No interrupt,Interrupt"
|
|
bitfld.long 0x30 14. " [47] ,Interrupt Pending Bit[47]" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x30 13. " [46] ,Interrupt Pending Bit[46]" "No interrupt,Interrupt"
|
|
bitfld.long 0x30 12. " [45] ,Interrupt Pending Bit[45]" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x30 11. " [44] ,Interrupt Pending Bit[44]" "No interrupt,Interrupt"
|
|
bitfld.long 0x30 10. " [43] ,Interrupt Pending Bit[43]" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x30 9. " [42] ,Interrupt Pending Bit[42]" "No interrupt,Interrupt"
|
|
bitfld.long 0x30 8. " [41] ,Interrupt Pending Bit[41]" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x30 7. " [40] ,Interrupt Pending Bit[40]" "No interrupt,Interrupt"
|
|
bitfld.long 0x30 6. " [39] ,Interrupt Pending Bit[39]" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x30 5. " [38] ,Interrupt Pending Bit[38]" "No interrupt,Interrupt"
|
|
bitfld.long 0x30 4. " [37] ,Interrupt Pending Bit[37]" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x30 3. " [36] ,Interrupt Pending Bit[36]" "No interrupt,Interrupt"
|
|
bitfld.long 0x30 2. " [35] ,Interrupt Pending Bit[35]" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x30 1. " [34] ,Interrupt Pending Bit[34]" "No interrupt,Interrupt"
|
|
bitfld.long 0x30 0. " [33] ,Interrupt Pending Bit[33]" "No interrupt,Interrupt"
|
|
line.long 0x34 "INTPEN56,Interrupt Pending 5-6"
|
|
bitfld.long 0x34 31. " INTPND[96] ,Interrupt Pending Bit[96]" "No interrupt,Interrupt"
|
|
bitfld.long 0x34 30. " [95] ,Interrupt Pending Bit[95]" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x34 29. " [94] ,Interrupt Pending Bit[94]" "No interrupt,Interrupt"
|
|
bitfld.long 0x34 28. " [93] ,Interrupt Pending Bit[93]" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x34 27. " [92] ,Interrupt Pending Bit[92]" "No interrupt,Interrupt"
|
|
bitfld.long 0x34 26. " [91] ,Interrupt Pending Bit[91]" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x34 25. " [90] ,Interrupt Pending Bit[90]" "No interrupt,Interrupt"
|
|
bitfld.long 0x34 24. " [89] ,Interrupt Pending Bit[89]" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x34 23. " [88] ,Interrupt Pending Bit[88]" "No interrupt,Interrupt"
|
|
bitfld.long 0x34 22. " [87] ,Interrupt Pending Bit[87]" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x34 21. " [86] ,Interrupt Pending Bit[86]" "No interrupt,Interrupt"
|
|
bitfld.long 0x34 20. " [85] ,Interrupt Pending Bit[85]" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x34 19. " [84] ,Interrupt Pending Bit[84]" "No interrupt,Interrupt"
|
|
bitfld.long 0x34 18. " [83] ,Interrupt Pending Bit[83]" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x34 17. " [82] ,Interrupt Pending Bit[82]" "No interrupt,Interrupt"
|
|
bitfld.long 0x34 16. " [81] ,Interrupt Pending Bit[81]" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x34 15. " [80] ,Interrupt Pending Bit[80]" "No interrupt,Interrupt"
|
|
bitfld.long 0x34 14. " [79] ,Interrupt Pending Bit[79]" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x34 13. " [78] ,Interrupt Pending Bit[78]" "No interrupt,Interrupt"
|
|
bitfld.long 0x34 12. " [77] ,Interrupt Pending Bit[77]" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x34 11. " [76] ,Interrupt Pending Bit[76]" "No interrupt,Interrupt"
|
|
bitfld.long 0x34 10. " [75] ,Interrupt Pending Bit[75]" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x34 9. " [74] ,Interrupt Pending Bit[74]" "No interrupt,Interrupt"
|
|
bitfld.long 0x34 8. " [73] ,Interrupt Pending Bit[73]" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x34 7. " [72] ,Interrupt Pending Bit[72]" "No interrupt,Interrupt"
|
|
bitfld.long 0x34 6. " [71] ,Interrupt Pending Bit[71]" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x34 5. " [70] ,Interrupt Pending Bit[70]" "No interrupt,Interrupt"
|
|
bitfld.long 0x34 4. " [69] ,Interrupt Pending Bit[69]" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x34 3. " [68] ,Interrupt Pending Bit[68]" "No interrupt,Interrupt"
|
|
bitfld.long 0x34 2. " [67] ,Interrupt Pending Bit[67]" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x34 1. " [66] ,Interrupt Pending Bit[66]" "No interrupt,Interrupt"
|
|
bitfld.long 0x34 0. " [65] ,Interrupt Pending Bit[65]" "No interrupt,Interrupt"
|
|
line.long 0x38 "INTPEN78,Interrupt Pending 7-8"
|
|
bitfld.long 0x38 31. " INTPND[128] ,Interrupt Pending Bit[128]" "No interrupt,Interrupt"
|
|
bitfld.long 0x38 30. " [127] ,Interrupt Pending Bit[127]" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x38 29. " [126] ,Interrupt Pending Bit[126]" "No interrupt,Interrupt"
|
|
bitfld.long 0x38 28. " [125] ,Interrupt Pending Bit[125]" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x38 27. " [124] ,Interrupt Pending Bit[124]" "No interrupt,Interrupt"
|
|
bitfld.long 0x38 26. " [123] ,Interrupt Pending Bit[123]" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x38 25. " [122] ,Interrupt Pending Bit[122]" "No interrupt,Interrupt"
|
|
bitfld.long 0x38 24. " [121] ,Interrupt Pending Bit[121]" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x38 23. " [120] ,Interrupt Pending Bit[120]" "No interrupt,Interrupt"
|
|
bitfld.long 0x38 22. " [119] ,Interrupt Pending Bit[119]" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x38 21. " [118] ,Interrupt Pending Bit[118]" "No interrupt,Interrupt"
|
|
bitfld.long 0x38 20. " [117] ,Interrupt Pending Bit[117]" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x38 19. " [116] ,Interrupt Pending Bit[116]" "No interrupt,Interrupt"
|
|
bitfld.long 0x38 18. " [115] ,Interrupt Pending Bit[115]" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x38 17. " [114] ,Interrupt Pending Bit[114]" "No interrupt,Interrupt"
|
|
bitfld.long 0x38 16. " [113] ,Interrupt Pending Bit[113]" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x38 15. " [112] ,Interrupt Pending Bit[112]" "No interrupt,Interrupt"
|
|
bitfld.long 0x38 14. " [111] ,Interrupt Pending Bit[111]" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x38 13. " [110] ,Interrupt Pending Bit[110]" "No interrupt,Interrupt"
|
|
bitfld.long 0x38 12. " [109] ,Interrupt Pending Bit[109]" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x38 11. " [108] ,Interrupt Pending Bit[108]" "No interrupt,Interrupt"
|
|
bitfld.long 0x38 10. " [107] ,Interrupt Pending Bit[107]" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x38 9. " [106] ,Interrupt Pending Bit[106]" "No interrupt,Interrupt"
|
|
bitfld.long 0x38 8. " [105] ,Interrupt Pending Bit[105]" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x38 7. " [104] ,Interrupt Pending Bit[104]" "No interrupt,Interrupt"
|
|
bitfld.long 0x38 6. " [103] ,Interrupt Pending Bit[103]" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x38 5. " [102] ,Interrupt Pending Bit[102]" "No interrupt,Interrupt"
|
|
bitfld.long 0x38 4. " [101] ,Interrupt Pending Bit[101]" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x38 3. " [100] ,Interrupt Pending Bit[100]" "No interrupt,Interrupt"
|
|
bitfld.long 0x38 2. " [99] ,Interrupt Pending Bit[99]" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x38 1. " [98] ,Interrupt Pending Bit[98]" "No interrupt,Interrupt"
|
|
bitfld.long 0x38 0. " [97] ,Interrupt Pending Bit[97]" "No interrupt,Interrupt"
|
|
line.long 0x3C "MVAL,Message Valid X"
|
|
bitfld.long 0x3C 14.--15. " MSGVALREG8 ,Message Valid Register 8" "0,1,2,3"
|
|
bitfld.long 0x3C 12.--13. " [7] ,Message Valid Register 7" "0,1,2,3"
|
|
bitfld.long 0x3C 10.--11. " [6] ,Message Valid Register 6" "0,1,2,3"
|
|
bitfld.long 0x3C 8.--9. " [5] ,Message Valid Register 5" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x3C 6.--7. " [4] ,Message Valid Register 4" "0,1,2,3"
|
|
bitfld.long 0x3C 4.--5. " [3] ,Message Valid Register 3" "0,1,2,3"
|
|
bitfld.long 0x3C 2.--3. " [2] ,Message Valid Register 2" "0,1,2,3"
|
|
bitfld.long 0x3C 0.--1. " [1] ,Message Valid Register 1" "0,1,2,3"
|
|
line.long 0x40 "MVAL12,Message Valid 1-2"
|
|
bitfld.long 0x40 31. " MSGVAL[32] ,Message Valid Bit[32]" "Ignored,Configured"
|
|
bitfld.long 0x40 30. " [31] ,Message Valid Bit[31]" "Ignored,Configured"
|
|
newline
|
|
bitfld.long 0x40 29. " [30] ,Message Valid Bit[30]" "Ignored,Configured"
|
|
bitfld.long 0x40 28. " [29] ,Message Valid Bit[29]" "Ignored,Configured"
|
|
newline
|
|
bitfld.long 0x40 27. " [28] ,Message Valid Bit[28]" "Ignored,Configured"
|
|
bitfld.long 0x40 26. " [27] ,Message Valid Bit[27]" "Ignored,Configured"
|
|
newline
|
|
bitfld.long 0x40 25. " [26] ,Message Valid Bit[26]" "Ignored,Configured"
|
|
bitfld.long 0x40 24. " [25] ,Message Valid Bit[25]" "Ignored,Configured"
|
|
newline
|
|
bitfld.long 0x40 23. " [24] ,Message Valid Bit[24]" "Ignored,Configured"
|
|
bitfld.long 0x40 22. " [23] ,Message Valid Bit[23]" "Ignored,Configured"
|
|
newline
|
|
bitfld.long 0x40 21. " [22] ,Message Valid Bit[22]" "Ignored,Configured"
|
|
bitfld.long 0x40 20. " [21] ,Message Valid Bit[21]" "Ignored,Configured"
|
|
newline
|
|
bitfld.long 0x40 19. " [20] ,Message Valid Bit[20]" "Ignored,Configured"
|
|
bitfld.long 0x40 18. " [19] ,Message Valid Bit[19]" "Ignored,Configured"
|
|
newline
|
|
bitfld.long 0x40 17. " [18] ,Message Valid Bit[18]" "Ignored,Configured"
|
|
bitfld.long 0x40 16. " [17] ,Message Valid Bit[17]" "Ignored,Configured"
|
|
newline
|
|
bitfld.long 0x40 15. " [16] ,Message Valid Bit[16]" "Ignored,Configured"
|
|
bitfld.long 0x40 14. " [15] ,Message Valid Bit[15]" "Ignored,Configured"
|
|
newline
|
|
bitfld.long 0x40 13. " [14] ,Message Valid Bit[14]" "Ignored,Configured"
|
|
bitfld.long 0x40 12. " [13] ,Message Valid Bit[13]" "Ignored,Configured"
|
|
newline
|
|
bitfld.long 0x40 11. " [12] ,Message Valid Bit[12]" "Ignored,Configured"
|
|
bitfld.long 0x40 10. " [11] ,Message Valid Bit[11]" "Ignored,Configured"
|
|
newline
|
|
bitfld.long 0x40 9. " [10] ,Message Valid Bit[10]" "Ignored,Configured"
|
|
bitfld.long 0x40 8. " [9] ,Message Valid Bit[9]" "Ignored,Configured"
|
|
newline
|
|
bitfld.long 0x40 7. " [8] ,Message Valid Bit[8]" "Ignored,Configured"
|
|
bitfld.long 0x40 6. " [7] ,Message Valid Bit[7]" "Ignored,Configured"
|
|
newline
|
|
bitfld.long 0x40 5. " [6] ,Message Valid Bit[6]" "Ignored,Configured"
|
|
bitfld.long 0x40 4. " [5] ,Message Valid Bit[5]" "Ignored,Configured"
|
|
newline
|
|
bitfld.long 0x40 3. " [4] ,Message Valid Bit[4]" "Ignored,Configured"
|
|
bitfld.long 0x40 2. " [3] ,Message Valid Bit[3]" "Ignored,Configured"
|
|
newline
|
|
bitfld.long 0x40 1. " [2] ,Message Valid Bit[2]" "Ignored,Configured"
|
|
bitfld.long 0x40 0. " [1] ,Message Valid Bit[1]" "Ignored,Configured"
|
|
line.long 0x44 "MVAL34,Message Valid 3-4"
|
|
bitfld.long 0x44 31. " MSGVAl[64] ,Message Valid Bit[64]" "Ignored,Configured"
|
|
bitfld.long 0x44 30. " [63] ,Message Valid Bit[63]" "Ignored,Configured"
|
|
newline
|
|
bitfld.long 0x44 29. " [62] ,Message Valid Bit[62]" "Ignored,Configured"
|
|
bitfld.long 0x44 28. " [61] ,Message Valid Bit[61]" "Ignored,Configured"
|
|
newline
|
|
bitfld.long 0x44 27. " [60] ,Message Valid Bit[60]" "Ignored,Configured"
|
|
bitfld.long 0x44 26. " [59] ,Message Valid Bit[59]" "Ignored,Configured"
|
|
newline
|
|
bitfld.long 0x44 25. " [58] ,Message Valid Bit[58]" "Ignored,Configured"
|
|
bitfld.long 0x44 24. " [57] ,Message Valid Bit[57]" "Ignored,Configured"
|
|
newline
|
|
bitfld.long 0x44 23. " [56] ,Message Valid Bit[56]" "Ignored,Configured"
|
|
bitfld.long 0x44 22. " [55] ,Message Valid Bit[55]" "Ignored,Configured"
|
|
newline
|
|
bitfld.long 0x44 21. " [54] ,Message Valid Bit[54]" "Ignored,Configured"
|
|
bitfld.long 0x44 20. " [53] ,Message Valid Bit[53]" "Ignored,Configured"
|
|
newline
|
|
bitfld.long 0x44 19. " [52] ,Message Valid Bit[52]" "Ignored,Configured"
|
|
bitfld.long 0x44 18. " [51] ,Message Valid Bit[51]" "Ignored,Configured"
|
|
newline
|
|
bitfld.long 0x44 17. " [50] ,Message Valid Bit[50]" "Ignored,Configured"
|
|
bitfld.long 0x44 16. " [49] ,Message Valid Bit[49]" "Ignored,Configured"
|
|
newline
|
|
bitfld.long 0x44 15. " [48] ,Message Valid Bit[48]" "Ignored,Configured"
|
|
bitfld.long 0x44 14. " [47] ,Message Valid Bit[47]" "Ignored,Configured"
|
|
newline
|
|
bitfld.long 0x44 13. " [46] ,Message Valid Bit[46]" "Ignored,Configured"
|
|
bitfld.long 0x44 12. " [45] ,Message Valid Bit[45]" "Ignored,Configured"
|
|
newline
|
|
bitfld.long 0x44 11. " [44] ,Message Valid Bit[44]" "Ignored,Configured"
|
|
bitfld.long 0x44 10. " [43] ,Message Valid Bit[43]" "Ignored,Configured"
|
|
newline
|
|
bitfld.long 0x44 9. " [42] ,Message Valid Bit[42]" "Ignored,Configured"
|
|
bitfld.long 0x44 8. " [41] ,Message Valid Bit[41]" "Ignored,Configured"
|
|
newline
|
|
bitfld.long 0x44 7. " [40] ,Message Valid Bit[40]" "Ignored,Configured"
|
|
bitfld.long 0x44 6. " [39] ,Message Valid Bit[39]" "Ignored,Configured"
|
|
newline
|
|
bitfld.long 0x44 5. " [38] ,Message Valid Bit[38]" "Ignored,Configured"
|
|
bitfld.long 0x44 4. " [37] ,Message Valid Bit[37]" "Ignored,Configured"
|
|
newline
|
|
bitfld.long 0x44 3. " [36] ,Message Valid Bit[36]" "Ignored,Configured"
|
|
bitfld.long 0x44 2. " [35] ,Message Valid Bit[35]" "Ignored,Configured"
|
|
newline
|
|
bitfld.long 0x44 1. " [34] ,Message Valid Bit[34]" "Ignored,Configured"
|
|
bitfld.long 0x44 0. " [33] ,Message Valid Bit[33]" "Ignored,Configured"
|
|
line.long 0x48 "MVAL56,Message Valid 5-6"
|
|
bitfld.long 0x48 31. " MSGVAl[96] ,Message Valid Bit[96]" "Ignored,Configured"
|
|
bitfld.long 0x48 30. " [95] ,Message Valid Bit[95]" "Ignored,Configured"
|
|
newline
|
|
bitfld.long 0x48 29. " [94] ,Message Valid Bit[94]" "Ignored,Configured"
|
|
bitfld.long 0x48 28. " [93] ,Message Valid Bit[93]" "Ignored,Configured"
|
|
newline
|
|
bitfld.long 0x48 27. " [92] ,Message Valid Bit[92]" "Ignored,Configured"
|
|
bitfld.long 0x48 26. " [91] ,Message Valid Bit[91]" "Ignored,Configured"
|
|
newline
|
|
bitfld.long 0x48 25. " [90] ,Message Valid Bit[90]" "Ignored,Configured"
|
|
bitfld.long 0x48 24. " [89] ,Message Valid Bit[89]" "Ignored,Configured"
|
|
newline
|
|
bitfld.long 0x48 23. " [88] ,Message Valid Bit[88]" "Ignored,Configured"
|
|
bitfld.long 0x48 22. " [87] ,Message Valid Bit[87]" "Ignored,Configured"
|
|
newline
|
|
bitfld.long 0x48 21. " [86] ,Message Valid Bit[86]" "Ignored,Configured"
|
|
bitfld.long 0x48 20. " [85] ,Message Valid Bit[85]" "Ignored,Configured"
|
|
newline
|
|
bitfld.long 0x48 19. " [84] ,Message Valid Bit[84]" "Ignored,Configured"
|
|
bitfld.long 0x48 18. " [83] ,Message Valid Bit[83]" "Ignored,Configured"
|
|
newline
|
|
bitfld.long 0x48 17. " [82] ,Message Valid Bit[82]" "Ignored,Configured"
|
|
bitfld.long 0x48 16. " [81] ,Message Valid Bit[81]" "Ignored,Configured"
|
|
newline
|
|
bitfld.long 0x48 15. " [80] ,Message Valid Bit[80]" "Ignored,Configured"
|
|
bitfld.long 0x48 14. " [79] ,Message Valid Bit[79]" "Ignored,Configured"
|
|
newline
|
|
bitfld.long 0x48 13. " [78] ,Message Valid Bit[78]" "Ignored,Configured"
|
|
bitfld.long 0x48 12. " [77] ,Message Valid Bit[77]" "Ignored,Configured"
|
|
newline
|
|
bitfld.long 0x48 11. " [76] ,Message Valid Bit[76]" "Ignored,Configured"
|
|
bitfld.long 0x48 10. " [75] ,Message Valid Bit[75]" "Ignored,Configured"
|
|
newline
|
|
bitfld.long 0x48 9. " [74] ,Message Valid Bit[74]" "Ignored,Configured"
|
|
bitfld.long 0x48 8. " [73] ,Message Valid Bit[73]" "Ignored,Configured"
|
|
newline
|
|
bitfld.long 0x48 7. " [72] ,Message Valid Bit[72]" "Ignored,Configured"
|
|
bitfld.long 0x48 6. " [71] ,Message Valid Bit[71]" "Ignored,Configured"
|
|
newline
|
|
bitfld.long 0x48 5. " [70] ,Message Valid Bit[70]" "Ignored,Configured"
|
|
bitfld.long 0x48 4. " [69] ,Message Valid Bit[69]" "Ignored,Configured"
|
|
newline
|
|
bitfld.long 0x48 3. " [68] ,Message Valid Bit[68]" "Ignored,Configured"
|
|
bitfld.long 0x48 2. " [67] ,Message Valid Bit[67]" "Ignored,Configured"
|
|
newline
|
|
bitfld.long 0x48 1. " [66] ,Message Valid Bit[66]" "Ignored,Configured"
|
|
bitfld.long 0x48 0. " [65] ,Message Valid Bit[65]" "Ignored,Configured"
|
|
line.long 0x4C "MVAL78,Message Valid 7-8"
|
|
bitfld.long 0x4C 31. " MSGVAl[128] ,Message Valid Bit[128]" "Ignored,Configured"
|
|
bitfld.long 0x4C 30. " [127] ,Message Valid Bit[127]" "Ignored,Configured"
|
|
newline
|
|
bitfld.long 0x4C 29. " [126] ,Message Valid Bit[126]" "Ignored,Configured"
|
|
bitfld.long 0x4C 28. " [125] ,Message Valid Bit[125]" "Ignored,Configured"
|
|
newline
|
|
bitfld.long 0x4C 27. " [124] ,Message Valid Bit[124]" "Ignored,Configured"
|
|
bitfld.long 0x4C 26. " [123] ,Message Valid Bit[123]" "Ignored,Configured"
|
|
newline
|
|
bitfld.long 0x4C 25. " [122] ,Message Valid Bit[122]" "Ignored,Configured"
|
|
bitfld.long 0x4C 24. " [121] ,Message Valid Bit[121]" "Ignored,Configured"
|
|
newline
|
|
bitfld.long 0x4C 23. " [120] ,Message Valid Bit[120]" "Ignored,Configured"
|
|
bitfld.long 0x4C 22. " [119] ,Message Valid Bit[119]" "Ignored,Configured"
|
|
newline
|
|
bitfld.long 0x4C 21. " [118] ,Message Valid Bit[118]" "Ignored,Configured"
|
|
bitfld.long 0x4C 20. " [117] ,Message Valid Bit[117]" "Ignored,Configured"
|
|
newline
|
|
bitfld.long 0x4C 19. " [116] ,Message Valid Bit[116]" "Ignored,Configured"
|
|
bitfld.long 0x4C 18. " [115] ,Message Valid Bit[115]" "Ignored,Configured"
|
|
newline
|
|
bitfld.long 0x4C 17. " [114] ,Message Valid Bit[114]" "Ignored,Configured"
|
|
bitfld.long 0x4C 16. " [113] ,Message Valid Bit[113]" "Ignored,Configured"
|
|
newline
|
|
bitfld.long 0x4C 15. " [112] ,Message Valid Bit[112]" "Ignored,Configured"
|
|
bitfld.long 0x4C 14. " [111] ,Message Valid Bit[111]" "Ignored,Configured"
|
|
newline
|
|
bitfld.long 0x4C 13. " [110] ,Message Valid Bit[110]" "Ignored,Configured"
|
|
bitfld.long 0x4C 12. " [109] ,Message Valid Bit[109]" "Ignored,Configured"
|
|
newline
|
|
bitfld.long 0x4C 11. " [108] ,Message Valid Bit[108]" "Ignored,Configured"
|
|
bitfld.long 0x4C 10. " [107] ,Message Valid Bit[107]" "Ignored,Configured"
|
|
newline
|
|
bitfld.long 0x4C 9. " [106] ,Message Valid Bit[106]" "Ignored,Configured"
|
|
bitfld.long 0x4C 8. " [105] ,Message Valid Bit[105]" "Ignored,Configured"
|
|
newline
|
|
bitfld.long 0x4C 7. " [104] ,Message Valid Bit[104]" "Ignored,Configured"
|
|
bitfld.long 0x4C 6. " [103] ,Message Valid Bit[103]" "Ignored,Configured"
|
|
newline
|
|
bitfld.long 0x4C 5. " [102] ,Message Valid Bit[102]" "Ignored,Configured"
|
|
bitfld.long 0x4C 4. " [101] ,Message Valid Bit[101]" "Ignored,Configured"
|
|
newline
|
|
bitfld.long 0x4C 3. " [100] ,Message Valid Bit[100]" "Ignored,Configured"
|
|
bitfld.long 0x4C 2. " [99] ,Message Valid Bit[99]" "Ignored,Configured"
|
|
newline
|
|
bitfld.long 0x4C 1. " [98] ,Message Valid Bit[98]" "Ignored,Configured"
|
|
bitfld.long 0x4C 0. " [97] ,Message Valid Bit[97]" "Ignored,Configured"
|
|
group.long 0xD8++0x0F
|
|
line.long 0x00 "INTPMX12,Interrupt Multiplexer 1-2"
|
|
bitfld.long 0x00 31. " INTPNDMUX[32] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[32]" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x00 30. " [31] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[31]" "DCAN0INT,DCAN1INT"
|
|
newline
|
|
bitfld.long 0x00 29. " [30] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[30]" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x00 28. " [29] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[29]" "DCAN0INT,DCAN1INT"
|
|
newline
|
|
bitfld.long 0x00 27. " [28] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[28]" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x00 26. " [27] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[27]" "DCAN0INT,DCAN1INT"
|
|
newline
|
|
bitfld.long 0x00 25. " [26] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[26]" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x00 24. " [25] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[25]" "DCAN0INT,DCAN1INT"
|
|
newline
|
|
bitfld.long 0x00 23. " [24] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[24]" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x00 22. " [23] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[23]" "DCAN0INT,DCAN1INT"
|
|
newline
|
|
bitfld.long 0x00 21. " [22] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[22]" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x00 20. " [21] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[21]" "DCAN0INT,DCAN1INT"
|
|
newline
|
|
bitfld.long 0x00 19. " [20] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[20]" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x00 18. " [19] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[19]" "DCAN0INT,DCAN1INT"
|
|
newline
|
|
bitfld.long 0x00 17. " [18] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[18]" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x00 16. " [17] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[17]" "DCAN0INT,DCAN1INT"
|
|
newline
|
|
bitfld.long 0x00 15. " [16] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[16]" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x00 14. " [15] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[15]" "DCAN0INT,DCAN1INT"
|
|
newline
|
|
bitfld.long 0x00 13. " [14] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[14]" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x00 12. " [13] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[13]" "DCAN0INT,DCAN1INT"
|
|
newline
|
|
bitfld.long 0x00 11. " [12] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[12]" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x00 10. " [11] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[11]" "DCAN0INT,DCAN1INT"
|
|
newline
|
|
bitfld.long 0x00 9. " [10] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[10]" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x00 8. " [9] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[9]" "DCAN0INT,DCAN1INT"
|
|
newline
|
|
bitfld.long 0x00 7. " [8] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[8]" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x00 6. " [7] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[7]" "DCAN0INT,DCAN1INT"
|
|
newline
|
|
bitfld.long 0x00 5. " [6] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[6]" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x00 4. " [5] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[5]" "DCAN0INT,DCAN1INT"
|
|
newline
|
|
bitfld.long 0x00 3. " [4] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[4]" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x00 2. " [3] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[3]" "DCAN0INT,DCAN1INT"
|
|
newline
|
|
bitfld.long 0x00 1. " [2] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[2]" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x00 0. " [1] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[1]" "DCAN0INT,DCAN1INT"
|
|
line.long 0x04 "INTPMX34,Interrupt Multiplexer 3-4"
|
|
bitfld.long 0x04 31. " INTPNDMUX[64] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[64]" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x04 30. " [63] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[63]" "DCAN0INT,DCAN1INT"
|
|
newline
|
|
bitfld.long 0x04 29. " [62] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[62]" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x04 28. " [61] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[61]" "DCAN0INT,DCAN1INT"
|
|
newline
|
|
bitfld.long 0x04 27. " [60] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[60]" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x04 26. " [59] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[59]" "DCAN0INT,DCAN1INT"
|
|
newline
|
|
bitfld.long 0x04 25. " [58] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[58]" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x04 24. " [57] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[57]" "DCAN0INT,DCAN1INT"
|
|
newline
|
|
bitfld.long 0x04 23. " [56] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[56]" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x04 22. " [55] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[55]" "DCAN0INT,DCAN1INT"
|
|
newline
|
|
bitfld.long 0x04 21. " [54] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[54]" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x04 20. " [53] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[53]" "DCAN0INT,DCAN1INT"
|
|
newline
|
|
bitfld.long 0x04 19. " [52] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[52]" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x04 18. " [51] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[51]" "DCAN0INT,DCAN1INT"
|
|
newline
|
|
bitfld.long 0x04 17. " [50] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[50]" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x04 16. " [49] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[49]" "DCAN0INT,DCAN1INT"
|
|
newline
|
|
bitfld.long 0x04 15. " [48] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[48]" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x04 14. " [47] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[47]" "DCAN0INT,DCAN1INT"
|
|
newline
|
|
bitfld.long 0x04 13. " [46] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[46]" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x04 12. " [45] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[45]" "DCAN0INT,DCAN1INT"
|
|
newline
|
|
bitfld.long 0x04 11. " [44] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[44]" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x04 10. " [43] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[43]" "DCAN0INT,DCAN1INT"
|
|
newline
|
|
bitfld.long 0x04 9. " [42] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[42]" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x04 8. " [41] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[41]" "DCAN0INT,DCAN1INT"
|
|
newline
|
|
bitfld.long 0x04 7. " [40] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[40]" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x04 6. " [39] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[39]" "DCAN0INT,DCAN1INT"
|
|
newline
|
|
bitfld.long 0x04 5. " [38] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[38]" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x04 4. " [37] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[37]" "DCAN0INT,DCAN1INT"
|
|
newline
|
|
bitfld.long 0x04 3. " [36] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[36]" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x04 2. " [35] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[35]" "DCAN0INT,DCAN1INT"
|
|
newline
|
|
bitfld.long 0x04 1. " [34] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[34]" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x04 0. " [33] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[33]" "DCAN0INT,DCAN1INT"
|
|
line.long 0x08 "INTPMX56,Interrupt Multiplexer 5-6"
|
|
bitfld.long 0x08 31. " INTPNDMUX[96] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[96]" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x08 30. " [95] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[95]" "DCAN0INT,DCAN1INT"
|
|
newline
|
|
bitfld.long 0x08 29. " [94] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[94]" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x08 28. " [93] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[93]" "DCAN0INT,DCAN1INT"
|
|
newline
|
|
bitfld.long 0x08 27. " [92] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[92]" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x08 26. " [91] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[91]" "DCAN0INT,DCAN1INT"
|
|
newline
|
|
bitfld.long 0x08 25. " [90] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[90]" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x08 24. " [89] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[89]" "DCAN0INT,DCAN1INT"
|
|
newline
|
|
bitfld.long 0x08 23. " [88] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[88]" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x08 22. " [87] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[87]" "DCAN0INT,DCAN1INT"
|
|
newline
|
|
bitfld.long 0x08 21. " [86] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[86]" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x08 20. " [85] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[85]" "DCAN0INT,DCAN1INT"
|
|
newline
|
|
bitfld.long 0x08 19. " [84] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[84]" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x08 18. " [83] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[83]" "DCAN0INT,DCAN1INT"
|
|
newline
|
|
bitfld.long 0x08 17. " [82] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[82]" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x08 16. " [81] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[81]" "DCAN0INT,DCAN1INT"
|
|
newline
|
|
bitfld.long 0x08 15. " [80] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[80]" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x08 14. " [79] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[79]" "DCAN0INT,DCAN1INT"
|
|
newline
|
|
bitfld.long 0x08 13. " [78] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[78]" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x08 12. " [77] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[77]" "DCAN0INT,DCAN1INT"
|
|
newline
|
|
bitfld.long 0x08 11. " [76] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[76]" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x08 10. " [75] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[75]" "DCAN0INT,DCAN1INT"
|
|
newline
|
|
bitfld.long 0x08 9. " [74] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[74]" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x08 8. " [73] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[73]" "DCAN0INT,DCAN1INT"
|
|
newline
|
|
bitfld.long 0x08 7. " [72] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[72]" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x08 6. " [71] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[71]" "DCAN0INT,DCAN1INT"
|
|
newline
|
|
bitfld.long 0x08 5. " [70] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[70]" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x08 4. " [69] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[69]" "DCAN0INT,DCAN1INT"
|
|
newline
|
|
bitfld.long 0x08 3. " [68] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[68]" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x08 2. " [67] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[67]" "DCAN0INT,DCAN1INT"
|
|
newline
|
|
bitfld.long 0x08 1. " [66] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[66]" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x08 0. " [65] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[65]" "DCAN0INT,DCAN1INT"
|
|
line.long 0x0C "INTPMX78,Interrupt Multiplexer 7-8"
|
|
bitfld.long 0x0C 31. " INTPNDMUX[128] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[128]" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x0C 30. " [127] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[127]" "DCAN0INT,DCAN1INT"
|
|
newline
|
|
bitfld.long 0x0C 29. " [126] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[126]" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x0C 28. " [125] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[125]" "DCAN0INT,DCAN1INT"
|
|
newline
|
|
bitfld.long 0x0C 27. " [124] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[124]" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x0C 26. " [123] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[123]" "DCAN0INT,DCAN1INT"
|
|
newline
|
|
bitfld.long 0x0C 25. " [122] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[122]" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x0C 24. " [121] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[121]" "DCAN0INT,DCAN1INT"
|
|
newline
|
|
bitfld.long 0x0C 23. " [120] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[120]" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x0C 22. " [119] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[119]" "DCAN0INT,DCAN1INT"
|
|
newline
|
|
bitfld.long 0x0C 21. " [118] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[118]" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x0C 20. " [117] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[117]" "DCAN0INT,DCAN1INT"
|
|
newline
|
|
bitfld.long 0x0C 19. " [116] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[116]" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x0C 18. " [115] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[115]" "DCAN0INT,DCAN1INT"
|
|
newline
|
|
bitfld.long 0x0C 17. " [114] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[114]" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x0C 16. " [113] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[113]" "DCAN0INT,DCAN1INT"
|
|
newline
|
|
bitfld.long 0x0C 15. " [112] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[112]" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x0C 14. " [111] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[111]" "DCAN0INT,DCAN1INT"
|
|
newline
|
|
bitfld.long 0x0C 13. " [110] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[110]" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x0C 12. " [109] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[109]" "DCAN0INT,DCAN1INT"
|
|
newline
|
|
bitfld.long 0x0C 11. " [108] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[108]" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x0C 10. " [107] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[107]" "DCAN0INT,DCAN1INT"
|
|
newline
|
|
bitfld.long 0x0C 9. " [106] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[106]" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x0C 8. " [105] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[105]" "DCAN0INT,DCAN1INT"
|
|
newline
|
|
bitfld.long 0x0C 7. " [104] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[104]" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x0C 6. " [103] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[103]" "DCAN0INT,DCAN1INT"
|
|
newline
|
|
bitfld.long 0x0C 5. " [102] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[102]" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x0C 4. " [101] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[101]" "DCAN0INT,DCAN1INT"
|
|
newline
|
|
bitfld.long 0x0C 3. " [100] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[100]" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x0C 2. " [99] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[99]" "DCAN0INT,DCAN1INT"
|
|
newline
|
|
bitfld.long 0x0C 1. " [98] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[98]" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x0C 0. " [97] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[97]" "DCAN0INT,DCAN1INT"
|
|
group.long 0x100++0x3 "IF1"
|
|
line.long 0x00 "IF1COM,IF1 Command Mask / Command Request Register"
|
|
bitfld.long 0x00 23. " WR/RD ,Write / Read direction" "Read,Write"
|
|
newline
|
|
bitfld.long 0x00 22. " MASK ,Access Mask Bits" "Unchanged,Identifier Mask+MDir+MXtd"
|
|
newline
|
|
bitfld.long 0x00 21. " ARB ,Access Arbitration Bits" "Unchanged,Identifier+Dir+Xtd+MSGVAl"
|
|
newline
|
|
bitfld.long 0x00 20. " CONTROL ,Access Control Bits" "Unchanged,Control bits"
|
|
bitfld.long 0x00 19. " CLRINTPND ,Clear Interrupt Pending Bit" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 18. " TXRQST/NEWDAT ,Access Transmission Request Bit" "Not requested,Requested"
|
|
bitfld.long 0x00 17. " DATA_A ,Access Data Bytes 0-3" "Unchanged,Data bytes 0-3"
|
|
newline
|
|
bitfld.long 0x00 16. " DATA_B ,Access Data Bytes 4-7" "Unchanged,Data bytes 4-7"
|
|
bitfld.long 0x00 15. " BUSY ,Busy Flag" "Not busy,Busy"
|
|
newline
|
|
sif (!cpuis("TMS570LS0332")&&!cpuis("TMS570LS0432"))
|
|
bitfld.long 0x00 14. " DMAACTIVE ,Activation of DMA Feature for Subsequent Internal IF1 Update" "No active,Active"
|
|
newline
|
|
endif
|
|
hexmask.long.byte 0x00 0.--7. 1. " MESSAGE_NUMBER ,Message Number"
|
|
sif cpuis("TMS570LS0232")||cpuis("TMS570LS0714*")||cpuis("TMS570LS0914*")||cpuis("TMS570LS3137-EP")
|
|
if (((per.l.be(((ad:0xFFF7DC00+0x100+0x08))))&0x40000000)==0x0)
|
|
group.long (0x100+0x04)++0x07
|
|
line.long 0x0 "IF1MASK,IF1 Mask Register"
|
|
bitfld.long 0x00 31. " MXTD ,Mask Extended Identifier" "No effect,Filtering"
|
|
bitfld.long 0x00 30. " MDIR ,Mask Message Direction" "No effect,Filtering"
|
|
newline
|
|
bitfld.long 0x00 28. " ID ,Message Identifier bit[10]" "0,1"
|
|
bitfld.long 0x00 27. ",Message Identifier bit[9]" "0,1"
|
|
bitfld.long 0x00 26. ",Message Identifier bit[8]" "0,1"
|
|
bitfld.long 0x00 25. ",Message Identifier bit[7]" "0,1"
|
|
bitfld.long 0x00 24. ",Message Identifier bit[6]" "0,1"
|
|
bitfld.long 0x00 23. ",Message Identifier bit[5]" "0,1"
|
|
bitfld.long 0x00 22. ",Message Identifier bit[4]" "0,1"
|
|
bitfld.long 0x00 21. ",Message Identifier bit[3]" "0,1"
|
|
bitfld.long 0x00 20. ",Message Identifier bit[2]" "0,1"
|
|
bitfld.long 0x00 19. ",Message Identifier bit[1]" "0,1"
|
|
bitfld.long 0x00 18. ",Message Identifier bit[0]" "0,1"
|
|
line.long 0x04 "IF1ARB,IF1 Arbitration Register"
|
|
bitfld.long 0x04 31. " MSGVAL ,Message Valid" "Ignore,Configure"
|
|
bitfld.long 0x04 30. " XTD ,Extended Identifier" "11-bit,29-bit"
|
|
bitfld.long 0x04 29. " DIR ,Message Direction" "Receive,Transmit"
|
|
hexmask.long.word 0x04 18.--28. 1. " ID ,Message Identifier"
|
|
else
|
|
group.long (0x100+0x04)++0x07
|
|
line.long 0x00 "IF1MASK,IF1 Mask Register"
|
|
bitfld.long 0x00 31. " MXTD ,Mask Extended Identifier" "No effect,Filtering"
|
|
bitfld.long 0x00 30. " MDIR ,Mask Message Direction" "No effect,Filtering"
|
|
newline
|
|
bitfld.long 0x00 28. " ID ,Message Identifier bit[28]" "0,1"
|
|
bitfld.long 0x00 27. ",Message Identifier bit[27]" "0,1"
|
|
bitfld.long 0x00 26. ",Message Identifier bit[26]" "0,1"
|
|
bitfld.long 0x00 25. ",Message Identifier bit[25]" "0,1"
|
|
bitfld.long 0x00 24. ",Message Identifier bit[24]" "0,1"
|
|
bitfld.long 0x00 23. ",Message Identifier bit[23]" "0,1"
|
|
bitfld.long 0x00 22. ",Message Identifier bit[22]" "0,1"
|
|
bitfld.long 0x00 21. ",Message Identifier bit[21]" "0,1"
|
|
bitfld.long 0x00 20. ",Message Identifier bit[20]" "0,1"
|
|
bitfld.long 0x00 19. ",Message Identifier bit[19]" "0,1"
|
|
bitfld.long 0x00 18. ",Message Identifier bit[18]" "0,1"
|
|
bitfld.long 0x00 17. ",Message Identifier bit[17]" "0,1"
|
|
bitfld.long 0x00 16. ",Message Identifier bit[16]" "0,1"
|
|
bitfld.long 0x00 15. ",Message Identifier bit[15]" "0,1"
|
|
bitfld.long 0x00 14. ",Message Identifier bit[14]" "0,1"
|
|
bitfld.long 0x00 13. ",Message Identifier bit[13]" "0,1"
|
|
bitfld.long 0x00 12. ",Message Identifier bit[12]" "0,1"
|
|
bitfld.long 0x00 11. ",Message Identifier bit[11]" "0,1"
|
|
bitfld.long 0x00 10. ",Message Identifier bit[10]" "0,1"
|
|
bitfld.long 0x00 9. ",Message Identifier bit[9]" "0,1"
|
|
bitfld.long 0x00 8. ",Message Identifier bit[8]" "0,1"
|
|
bitfld.long 0x00 7. ",Message Identifier bit[7]" "0,1"
|
|
bitfld.long 0x00 6. ",Message Identifier bit[6]" "0,1"
|
|
bitfld.long 0x00 5. ",Message Identifier bit[5]" "0,1"
|
|
bitfld.long 0x00 4. ",Message Identifier bit[4]" "0,1"
|
|
bitfld.long 0x00 3. ",Message Identifier bit[3]" "0,1"
|
|
bitfld.long 0x00 2. ",Message Identifier bit[2]" "0,1"
|
|
bitfld.long 0x00 1. ",Message Identifier bit[1]" "0,1"
|
|
bitfld.long 0x00 0. ",Message Identifier bit[0]" "0,1"
|
|
line.long 0x04 "IF1ARB,IF1 Arbitation Register"
|
|
bitfld.long 0x04 31. " MSGVAL ,Message Valid" "Ignore,Configure"
|
|
bitfld.long 0x04 30. " XTD ,Extended Identifier" "11-bit,29-bit"
|
|
bitfld.long 0x04 29. " DIR ,Message Direction" "Receive,Transmit"
|
|
hexmask.long 0x04 0.--28. 1. " ID ,Message Identifier"
|
|
endif
|
|
else
|
|
if (((per.l(((ad:0xFFF7DC00+0x100+0x08))))&0x40000000)==0x0)
|
|
group.long (0x100+0x04)++0x07
|
|
line.long 0x0 "IF1MASK,IF1 Mask Register"
|
|
bitfld.long 0x00 31. " MXTD ,Mask Extended Identifier" "No effect,Filtering"
|
|
bitfld.long 0x00 30. " MDIR ,Mask Message Direction" "No effect,Filtering"
|
|
newline
|
|
bitfld.long 0x00 28. " ID ,Message Identifier bit[28]" "0,1"
|
|
bitfld.long 0x00 27. ",Message Identifier bit[27]" "0,1"
|
|
bitfld.long 0x00 26. ",Message Identifier bit[26]" "0,1"
|
|
bitfld.long 0x00 25. ",Message Identifier bit[25]" "0,1"
|
|
bitfld.long 0x00 24. ",Message Identifier bit[24]" "0,1"
|
|
bitfld.long 0x00 23. ",Message Identifier bit[23]" "0,1"
|
|
bitfld.long 0x00 22. ",Message Identifier bit[22]" "0,1"
|
|
bitfld.long 0x00 21. ",Message Identifier bit[21]" "0,1"
|
|
bitfld.long 0x00 20. ",Message Identifier bit[20]" "0,1"
|
|
bitfld.long 0x00 19. ",Message Identifier bit[19]" "0,1"
|
|
bitfld.long 0x00 18. ",Message Identifier bit[18]" "0,1"
|
|
line.long 0x04 "IF1ARB,IF1 Arbitation Register"
|
|
bitfld.long 0x04 31. " MSGVAL ,Message Valid" "Ignore,Configure"
|
|
bitfld.long 0x04 30. " XTD ,Extended Identifier" "11-bit,29-bit"
|
|
bitfld.long 0x04 29. " DIR ,Message Direction" "Receive,Transmit"
|
|
hexmask.long.word 0x04 18.--28. 1. " ID ,Message Identifier"
|
|
else
|
|
group.long (0x100+0x04)++0x07
|
|
line.long 0x0 "IF1MASK,IF1 Mask Register"
|
|
bitfld.long 0x00 31. " MXTD ,Mask Extended Identifier" "No effect,Filtering"
|
|
bitfld.long 0x00 30. " MDIR ,Mask Message Direction" "No effect,Filtering"
|
|
newline
|
|
bitfld.long 0x00 28. " ID ,Message Identifier bit[28]" "0,1"
|
|
bitfld.long 0x00 27. ",Message Identifier bit[27]" "0,1"
|
|
bitfld.long 0x00 26. ",Message Identifier bit[26]" "0,1"
|
|
bitfld.long 0x00 25. ",Message Identifier bit[25]" "0,1"
|
|
bitfld.long 0x00 24. ",Message Identifier bit[24]" "0,1"
|
|
bitfld.long 0x00 23. ",Message Identifier bit[23]" "0,1"
|
|
bitfld.long 0x00 22. ",Message Identifier bit[22]" "0,1"
|
|
bitfld.long 0x00 21. ",Message Identifier bit[21]" "0,1"
|
|
bitfld.long 0x00 20. ",Message Identifier bit[20]" "0,1"
|
|
bitfld.long 0x00 19. ",Message Identifier bit[19]" "0,1"
|
|
bitfld.long 0x00 18. ",Message Identifier bit[18]" "0,1"
|
|
bitfld.long 0x00 17. ",Message Identifier bit[17]" "0,1"
|
|
bitfld.long 0x00 16. ",Message Identifier bit[16]" "0,1"
|
|
bitfld.long 0x00 15. ",Message Identifier bit[15]" "0,1"
|
|
bitfld.long 0x00 14. ",Message Identifier bit[14]" "0,1"
|
|
bitfld.long 0x00 13. ",Message Identifier bit[13]" "0,1"
|
|
bitfld.long 0x00 12. ",Message Identifier bit[12]" "0,1"
|
|
bitfld.long 0x00 11. ",Message Identifier bit[11]" "0,1"
|
|
bitfld.long 0x00 10. ",Message Identifier bit[10]" "0,1"
|
|
bitfld.long 0x00 9. ",Message Identifier bit[9]" "0,1"
|
|
bitfld.long 0x00 8. ",Message Identifier bit[8]" "0,1"
|
|
bitfld.long 0x00 7. ",Message Identifier bit[7]" "0,1"
|
|
bitfld.long 0x00 6. ",Message Identifier bit[6]" "0,1"
|
|
bitfld.long 0x00 5. ",Message Identifier bit[5]" "0,1"
|
|
bitfld.long 0x00 4. ",Message Identifier bit[4]" "0,1"
|
|
bitfld.long 0x00 3. ",Message Identifier bit[3]" "0,1"
|
|
bitfld.long 0x00 2. ",Message Identifier bit[2]" "0,1"
|
|
bitfld.long 0x00 1. ",Message Identifier bit[1]" "0,1"
|
|
bitfld.long 0x00 0. ",Message Identifier bit[0]" "0,1"
|
|
line.long 0x04 "IF1ARB,IF1 Arbitation Register"
|
|
bitfld.long 0x04 31. " MSGVAL ,Message Valid" "Ignore,Configure"
|
|
bitfld.long 0x04 30. " XTD ,Extended Identifier" "11-bit,29-bit"
|
|
bitfld.long 0x04 29. " DIR ,Message Direction" "Receive,Transmit"
|
|
hexmask.long 0x04 0.--28. 1. " ID ,Message Identifier"
|
|
endif
|
|
endif
|
|
group.long (0x100+0x0C)++0x0B
|
|
line.long 0x00 "IF1MCTRL,IF1 Message Control Register"
|
|
bitfld.long 0x00 15. " NEWDAT ,New Data" "No new data,New data"
|
|
bitfld.long 0x00 14. " MSGLST ,Message Lost" "Not lost,Lost"
|
|
bitfld.long 0x00 13. " INTPND ,Interrupt Pending" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x00 12. " UMASK ,Use Acceptance Mask" "Ignored,Masked"
|
|
bitfld.long 0x00 11. " TXIE ,Transmit Interrupt Enable" "Unchanged,Set"
|
|
bitfld.long 0x00 10. " RXIE ,Receive Interrupt Enable" "Unchanged,Set"
|
|
newline
|
|
bitfld.long 0x00 9. " RMTEN ,Remote Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " TXRQST ,Transmit Request" "Not requested,Requested"
|
|
bitfld.long 0x00 7. " EOB ,End of Block" "Single/Last,Not last"
|
|
newline
|
|
bitfld.long 0x00 0.--3. " DLC[3-0] ,Data Length Code" "0 byte,1 bytes,2 bytes,3 bytes,4 bytes,5 bytes,6 bytes,7 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes"
|
|
line.long 0x04 "IF1DATA,IF1 Data A Register"
|
|
hexmask.long.byte 0x04 24.--31. 1. " DATA[3] ,4th data byte of a CAN Data Frame"
|
|
hexmask.long.byte 0x04 16.--23. 1. " [2] ,3rd data byte of a CAN Data Frame"
|
|
hexmask.long.byte 0x04 8.--15. 1. " [1] ,2nd data byte of a CAN Data Frame"
|
|
hexmask.long.byte 0x04 0.--7. 1. " [0] ,1st data byte of a CAN Data Frame"
|
|
line.long 0x08 "IF1DATB,IF1 Data B Register"
|
|
hexmask.long.byte 0x08 24.--31. 1. " DATA[7] ,8th data byte of a CAN Data Frame"
|
|
hexmask.long.byte 0x08 16.--23. 1. " [6] ,7th data byte of a CAN Data Frame"
|
|
hexmask.long.byte 0x08 8.--15. 1. " [5] ,6th data byte of a CAN Data Frame"
|
|
hexmask.long.byte 0x08 0.--7. 1. " [4] ,5th data byte of a CAN Data Frame"
|
|
group.long 0x120++0x3 "IF2"
|
|
line.long 0x00 "IF2COM,IF2 Command Mask / Command Request Register"
|
|
bitfld.long 0x00 23. " WR/RD ,Write / Read direction" "Read,Write"
|
|
newline
|
|
bitfld.long 0x00 22. " MASK ,Access Mask Bits" "Unchanged,Identifier Mask+MDir+MXtd"
|
|
newline
|
|
bitfld.long 0x00 21. " ARB ,Access Arbitration Bits" "Unchanged,Identifier+Dir+Xtd+MSGVAl"
|
|
newline
|
|
bitfld.long 0x00 20. " CONTROL ,Access Control Bits" "Unchanged,Control bits"
|
|
bitfld.long 0x00 19. " CLRINTPND ,Clear Interrupt Pending Bit" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 18. " TXRQST/NEWDAT ,Access Transmission Request Bit" "Not requested,Requested"
|
|
bitfld.long 0x00 17. " DATA_A ,Access Data Bytes 0-3" "Unchanged,Data bytes 0-3"
|
|
newline
|
|
bitfld.long 0x00 16. " DATA_B ,Access Data Bytes 4-7" "Unchanged,Data bytes 4-7"
|
|
bitfld.long 0x00 15. " BUSY ,Busy Flag" "Not busy,Busy"
|
|
newline
|
|
sif (!cpuis("TMS570LS0332")&&!cpuis("TMS570LS0432"))
|
|
bitfld.long 0x00 14. " DMAACTIVE ,Activation of DMA Feature for Subsequent Internal IF1 Update" "No active,Active"
|
|
newline
|
|
endif
|
|
hexmask.long.byte 0x00 0.--7. 1. " MESSAGE_NUMBER ,Message Number"
|
|
sif cpuis("TMS570LS0232")||cpuis("TMS570LS0714*")||cpuis("TMS570LS0914*")||cpuis("TMS570LS3137-EP")
|
|
if (((per.l.be(((ad:0xFFF7DC00+0x120+0x08))))&0x40000000)==0x0)
|
|
group.long (0x120+0x04)++0x07
|
|
line.long 0x0 "IF2MASK,IF2 Mask Register"
|
|
bitfld.long 0x00 31. " MXTD ,Mask Extended Identifier" "No effect,Filtering"
|
|
bitfld.long 0x00 30. " MDIR ,Mask Message Direction" "No effect,Filtering"
|
|
newline
|
|
bitfld.long 0x00 28. " ID ,Message Identifier bit[10]" "0,1"
|
|
bitfld.long 0x00 27. ",Message Identifier bit[9]" "0,1"
|
|
bitfld.long 0x00 26. ",Message Identifier bit[8]" "0,1"
|
|
bitfld.long 0x00 25. ",Message Identifier bit[7]" "0,1"
|
|
bitfld.long 0x00 24. ",Message Identifier bit[6]" "0,1"
|
|
bitfld.long 0x00 23. ",Message Identifier bit[5]" "0,1"
|
|
bitfld.long 0x00 22. ",Message Identifier bit[4]" "0,1"
|
|
bitfld.long 0x00 21. ",Message Identifier bit[3]" "0,1"
|
|
bitfld.long 0x00 20. ",Message Identifier bit[2]" "0,1"
|
|
bitfld.long 0x00 19. ",Message Identifier bit[1]" "0,1"
|
|
bitfld.long 0x00 18. ",Message Identifier bit[0]" "0,1"
|
|
line.long 0x04 "IF2ARB,IF2 Arbitration Register"
|
|
bitfld.long 0x04 31. " MSGVAL ,Message Valid" "Ignore,Configure"
|
|
bitfld.long 0x04 30. " XTD ,Extended Identifier" "11-bit,29-bit"
|
|
bitfld.long 0x04 29. " DIR ,Message Direction" "Receive,Transmit"
|
|
hexmask.long.word 0x04 18.--28. 1. " ID ,Message Identifier"
|
|
else
|
|
group.long (0x120+0x04)++0x07
|
|
line.long 0x00 "IF2MASK,IF2 Mask Register"
|
|
bitfld.long 0x00 31. " MXTD ,Mask Extended Identifier" "No effect,Filtering"
|
|
bitfld.long 0x00 30. " MDIR ,Mask Message Direction" "No effect,Filtering"
|
|
newline
|
|
bitfld.long 0x00 28. " ID ,Message Identifier bit[28]" "0,1"
|
|
bitfld.long 0x00 27. ",Message Identifier bit[27]" "0,1"
|
|
bitfld.long 0x00 26. ",Message Identifier bit[26]" "0,1"
|
|
bitfld.long 0x00 25. ",Message Identifier bit[25]" "0,1"
|
|
bitfld.long 0x00 24. ",Message Identifier bit[24]" "0,1"
|
|
bitfld.long 0x00 23. ",Message Identifier bit[23]" "0,1"
|
|
bitfld.long 0x00 22. ",Message Identifier bit[22]" "0,1"
|
|
bitfld.long 0x00 21. ",Message Identifier bit[21]" "0,1"
|
|
bitfld.long 0x00 20. ",Message Identifier bit[20]" "0,1"
|
|
bitfld.long 0x00 19. ",Message Identifier bit[19]" "0,1"
|
|
bitfld.long 0x00 18. ",Message Identifier bit[18]" "0,1"
|
|
bitfld.long 0x00 17. ",Message Identifier bit[17]" "0,1"
|
|
bitfld.long 0x00 16. ",Message Identifier bit[16]" "0,1"
|
|
bitfld.long 0x00 15. ",Message Identifier bit[15]" "0,1"
|
|
bitfld.long 0x00 14. ",Message Identifier bit[14]" "0,1"
|
|
bitfld.long 0x00 13. ",Message Identifier bit[13]" "0,1"
|
|
bitfld.long 0x00 12. ",Message Identifier bit[12]" "0,1"
|
|
bitfld.long 0x00 11. ",Message Identifier bit[11]" "0,1"
|
|
bitfld.long 0x00 10. ",Message Identifier bit[10]" "0,1"
|
|
bitfld.long 0x00 9. ",Message Identifier bit[9]" "0,1"
|
|
bitfld.long 0x00 8. ",Message Identifier bit[8]" "0,1"
|
|
bitfld.long 0x00 7. ",Message Identifier bit[7]" "0,1"
|
|
bitfld.long 0x00 6. ",Message Identifier bit[6]" "0,1"
|
|
bitfld.long 0x00 5. ",Message Identifier bit[5]" "0,1"
|
|
bitfld.long 0x00 4. ",Message Identifier bit[4]" "0,1"
|
|
bitfld.long 0x00 3. ",Message Identifier bit[3]" "0,1"
|
|
bitfld.long 0x00 2. ",Message Identifier bit[2]" "0,1"
|
|
bitfld.long 0x00 1. ",Message Identifier bit[1]" "0,1"
|
|
bitfld.long 0x00 0. ",Message Identifier bit[0]" "0,1"
|
|
line.long 0x04 "IF2ARB,IF2 Arbitation Register"
|
|
bitfld.long 0x04 31. " MSGVAL ,Message Valid" "Ignore,Configure"
|
|
bitfld.long 0x04 30. " XTD ,Extended Identifier" "11-bit,29-bit"
|
|
bitfld.long 0x04 29. " DIR ,Message Direction" "Receive,Transmit"
|
|
hexmask.long 0x04 0.--28. 1. " ID ,Message Identifier"
|
|
endif
|
|
else
|
|
if (((per.l(((ad:0xFFF7DC00+0x120+0x08))))&0x40000000)==0x0)
|
|
group.long (0x120+0x04)++0x07
|
|
line.long 0x0 "IF2MASK,IF2 Mask Register"
|
|
bitfld.long 0x00 31. " MXTD ,Mask Extended Identifier" "No effect,Filtering"
|
|
bitfld.long 0x00 30. " MDIR ,Mask Message Direction" "No effect,Filtering"
|
|
newline
|
|
bitfld.long 0x00 28. " ID ,Message Identifier bit[28]" "0,1"
|
|
bitfld.long 0x00 27. ",Message Identifier bit[27]" "0,1"
|
|
bitfld.long 0x00 26. ",Message Identifier bit[26]" "0,1"
|
|
bitfld.long 0x00 25. ",Message Identifier bit[25]" "0,1"
|
|
bitfld.long 0x00 24. ",Message Identifier bit[24]" "0,1"
|
|
bitfld.long 0x00 23. ",Message Identifier bit[23]" "0,1"
|
|
bitfld.long 0x00 22. ",Message Identifier bit[22]" "0,1"
|
|
bitfld.long 0x00 21. ",Message Identifier bit[21]" "0,1"
|
|
bitfld.long 0x00 20. ",Message Identifier bit[20]" "0,1"
|
|
bitfld.long 0x00 19. ",Message Identifier bit[19]" "0,1"
|
|
bitfld.long 0x00 18. ",Message Identifier bit[18]" "0,1"
|
|
line.long 0x04 "IF2ARB,IF2 Arbitation Register"
|
|
bitfld.long 0x04 31. " MSGVAL ,Message Valid" "Ignore,Configure"
|
|
bitfld.long 0x04 30. " XTD ,Extended Identifier" "11-bit,29-bit"
|
|
bitfld.long 0x04 29. " DIR ,Message Direction" "Receive,Transmit"
|
|
hexmask.long.word 0x04 18.--28. 1. " ID ,Message Identifier"
|
|
else
|
|
group.long (0x120+0x04)++0x07
|
|
line.long 0x0 "IF2MASK,IF2 Mask Register"
|
|
bitfld.long 0x00 31. " MXTD ,Mask Extended Identifier" "No effect,Filtering"
|
|
bitfld.long 0x00 30. " MDIR ,Mask Message Direction" "No effect,Filtering"
|
|
newline
|
|
bitfld.long 0x00 28. " ID ,Message Identifier bit[28]" "0,1"
|
|
bitfld.long 0x00 27. ",Message Identifier bit[27]" "0,1"
|
|
bitfld.long 0x00 26. ",Message Identifier bit[26]" "0,1"
|
|
bitfld.long 0x00 25. ",Message Identifier bit[25]" "0,1"
|
|
bitfld.long 0x00 24. ",Message Identifier bit[24]" "0,1"
|
|
bitfld.long 0x00 23. ",Message Identifier bit[23]" "0,1"
|
|
bitfld.long 0x00 22. ",Message Identifier bit[22]" "0,1"
|
|
bitfld.long 0x00 21. ",Message Identifier bit[21]" "0,1"
|
|
bitfld.long 0x00 20. ",Message Identifier bit[20]" "0,1"
|
|
bitfld.long 0x00 19. ",Message Identifier bit[19]" "0,1"
|
|
bitfld.long 0x00 18. ",Message Identifier bit[18]" "0,1"
|
|
bitfld.long 0x00 17. ",Message Identifier bit[17]" "0,1"
|
|
bitfld.long 0x00 16. ",Message Identifier bit[16]" "0,1"
|
|
bitfld.long 0x00 15. ",Message Identifier bit[15]" "0,1"
|
|
bitfld.long 0x00 14. ",Message Identifier bit[14]" "0,1"
|
|
bitfld.long 0x00 13. ",Message Identifier bit[13]" "0,1"
|
|
bitfld.long 0x00 12. ",Message Identifier bit[12]" "0,1"
|
|
bitfld.long 0x00 11. ",Message Identifier bit[11]" "0,1"
|
|
bitfld.long 0x00 10. ",Message Identifier bit[10]" "0,1"
|
|
bitfld.long 0x00 9. ",Message Identifier bit[9]" "0,1"
|
|
bitfld.long 0x00 8. ",Message Identifier bit[8]" "0,1"
|
|
bitfld.long 0x00 7. ",Message Identifier bit[7]" "0,1"
|
|
bitfld.long 0x00 6. ",Message Identifier bit[6]" "0,1"
|
|
bitfld.long 0x00 5. ",Message Identifier bit[5]" "0,1"
|
|
bitfld.long 0x00 4. ",Message Identifier bit[4]" "0,1"
|
|
bitfld.long 0x00 3. ",Message Identifier bit[3]" "0,1"
|
|
bitfld.long 0x00 2. ",Message Identifier bit[2]" "0,1"
|
|
bitfld.long 0x00 1. ",Message Identifier bit[1]" "0,1"
|
|
bitfld.long 0x00 0. ",Message Identifier bit[0]" "0,1"
|
|
line.long 0x04 "IF2ARB,IF2 Arbitation Register"
|
|
bitfld.long 0x04 31. " MSGVAL ,Message Valid" "Ignore,Configure"
|
|
bitfld.long 0x04 30. " XTD ,Extended Identifier" "11-bit,29-bit"
|
|
bitfld.long 0x04 29. " DIR ,Message Direction" "Receive,Transmit"
|
|
hexmask.long 0x04 0.--28. 1. " ID ,Message Identifier"
|
|
endif
|
|
endif
|
|
group.long (0x120+0x0C)++0x0B
|
|
line.long 0x00 "IF2MCTRL,IF2 Message Control Register"
|
|
bitfld.long 0x00 15. " NEWDAT ,New Data" "No new data,New data"
|
|
bitfld.long 0x00 14. " MSGLST ,Message Lost" "Not lost,Lost"
|
|
bitfld.long 0x00 13. " INTPND ,Interrupt Pending" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x00 12. " UMASK ,Use Acceptance Mask" "Ignored,Masked"
|
|
bitfld.long 0x00 11. " TXIE ,Transmit Interrupt Enable" "Unchanged,Set"
|
|
bitfld.long 0x00 10. " RXIE ,Receive Interrupt Enable" "Unchanged,Set"
|
|
newline
|
|
bitfld.long 0x00 9. " RMTEN ,Remote Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " TXRQST ,Transmit Request" "Not requested,Requested"
|
|
bitfld.long 0x00 7. " EOB ,End of Block" "Single/Last,Not last"
|
|
newline
|
|
bitfld.long 0x00 0.--3. " DLC[3-0] ,Data Length Code" "0 byte,1 bytes,2 bytes,3 bytes,4 bytes,5 bytes,6 bytes,7 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes"
|
|
line.long 0x04 "IF2DATA,IF2 Data A Register"
|
|
hexmask.long.byte 0x04 24.--31. 1. " DATA[3] ,4th data byte of a CAN Data Frame"
|
|
hexmask.long.byte 0x04 16.--23. 1. " [2] ,3rd data byte of a CAN Data Frame"
|
|
hexmask.long.byte 0x04 8.--15. 1. " [1] ,2nd data byte of a CAN Data Frame"
|
|
hexmask.long.byte 0x04 0.--7. 1. " [0] ,1st data byte of a CAN Data Frame"
|
|
line.long 0x08 "IF2DATB,IF2 Data B Register"
|
|
hexmask.long.byte 0x08 24.--31. 1. " DATA[7] ,8th data byte of a CAN Data Frame"
|
|
hexmask.long.byte 0x08 16.--23. 1. " [6] ,7th data byte of a CAN Data Frame"
|
|
hexmask.long.byte 0x08 8.--15. 1. " [5] ,6th data byte of a CAN Data Frame"
|
|
hexmask.long.byte 0x08 0.--7. 1. " [4] ,5th data byte of a CAN Data Frame"
|
|
group.long 0x140++0x3 "IF3"
|
|
line.long 0x00 "IF3OB,IF3 Observation Register"
|
|
sif (cpu()==("TMS570LS0332")||cpu()==("TMS570LS0432")||cpuis("TMS570LS1114*")||cpuis("TMS570LS1115*")||cpuis("TMS570LS1224*")||cpuis("TMS570LS1225*")||cpuis("TMS570LS1227*")||cpuis("TMS570LS21*")||cpuis("TMS570LS31*")||cpuis("TMS570LS0232")||cpuis("TMS570LS0714*")||cpuis("TMS570LS0914*"))
|
|
rbitfld.long 0x00 15. " IF3UPD ,IF3 Updata Data" "Not loaded,Loaded"
|
|
rbitfld.long 0x00 12. " IF3SDB ,IF3 Status of Data B Read Access" "Low,High"
|
|
rbitfld.long 0x00 11. " IF3SDA ,IF3 Status of Data A Read Access" "Low,High"
|
|
newline
|
|
rbitfld.long 0x00 10. " IF3SC ,IF3 Status of Control Bits Read Access" "Low,High"
|
|
rbitfld.long 0x00 9. " IF3SA ,IF3 Status of Arbitration Data Read Access" "Low,High"
|
|
rbitfld.long 0x00 8. " IF3SM ,IF3 Status of Mask Data Read Access" "Low,High"
|
|
else
|
|
bitfld.long 0x00 15. " IF3UPD ,IF3 Updata Data" "Not loaded,Loaded"
|
|
bitfld.long 0x00 12. " IF3SDB ,IF3 Status of Data B Read Access" "Low,High"
|
|
bitfld.long 0x00 11. " IF3SDA ,IF3 Status of Data A Read Access" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 10. " IF3SC ,IF3 Status of Control Bits Read Access" "Low,High"
|
|
bitfld.long 0x00 9. " IF3SA ,IF3 Status of Arbitration Data Read Access" "Low,High"
|
|
bitfld.long 0x00 8. " IF3SM ,IF3 Status of Mask Data Read Access" "Low,High"
|
|
endif
|
|
newline
|
|
bitfld.long 0x00 4. " DATA_B ,Data B Read Observation" "Not read,Read"
|
|
bitfld.long 0x00 3. " DATA_A ,Data A Read Observation" "Not read,Read"
|
|
bitfld.long 0x00 2. " CTRL ,Ctrl Read Observation" "Not read,Read"
|
|
newline
|
|
bitfld.long 0x00 1. " ARB ,Arbitration Data Read Observation" "Not read,Read"
|
|
bitfld.long 0x00 0. " MASK ,Mask Data Read Observation" "Not read,Read"
|
|
sif cpuis("TMS570LS0232")||cpuis("TMS570LS0714*")||cpuis("TMS570LS0914*")
|
|
if (((per.l.be((ad:0xFFF7DC00+0x148)))&0x40000000)==0x0)
|
|
rgroup.long 0x144++0x07
|
|
line.long 0x00 "IF3MASK,IF3 Mask Register"
|
|
bitfld.long 0x00 31. " MXtd ,Mask Extended Identifier" "No effect,Filtering"
|
|
bitfld.long 0x00 30. " MDir ,Mask Message Direction" "No effect,Filtering"
|
|
newline
|
|
bitfld.long 0x00 28. " ID ,Message Identifier bit[28]" "0,1"
|
|
bitfld.long 0x00 27. ",Message Identifier bit[27]" "0,1"
|
|
bitfld.long 0x00 26. ",Message Identifier bit[26]" "0,1"
|
|
bitfld.long 0x00 25. ",Message Identifier bit[25]" "0,1"
|
|
bitfld.long 0x00 24. ",Message Identifier bit[24]" "0,1"
|
|
bitfld.long 0x00 23. ",Message Identifier bit[23]" "0,1"
|
|
bitfld.long 0x00 22. ",Message Identifier bit[22]" "0,1"
|
|
bitfld.long 0x00 21. ",Message Identifier bit[21]" "0,1"
|
|
bitfld.long 0x00 20. ",Message Identifier bit[20]" "0,1"
|
|
bitfld.long 0x00 19. ",Message Identifier bit[19]" "0,1"
|
|
bitfld.long 0x00 18. ",Message Identifier bit[18]" "0,1"
|
|
line.long 0x04 "IF3ARB,IF3 Arbitation Register"
|
|
bitfld.long 0x04 31. " MSGVAl ,Message Valid" "Ignored,Configured"
|
|
bitfld.long 0x04 30. " XTD ,Extended Identifier" "11-bit,29-bit"
|
|
bitfld.long 0x04 29. " DIR ,Message Direction" "Receive,Transmit"
|
|
newline
|
|
hexmask.long.word 0x04 18.--28. 1. " ID ,Message Identifier"
|
|
else
|
|
rgroup.long 0x144++0x07
|
|
line.long 0x0 "IF3MASK,IF3 Mask Register"
|
|
bitfld.long 0x00 31. " MXTD ,Mask Extended Identifier" "No effect,Filtering"
|
|
bitfld.long 0x00 30. " MDIR ,Mask Message Direction" "No effect,Filtering"
|
|
newline
|
|
bitfld.long 0x00 28. " ID ,Message Identifier bit[28]" "0,1"
|
|
bitfld.long 0x00 27. ",Message Identifier bit[27]" "0,1"
|
|
bitfld.long 0x00 26. ",Message Identifier bit[26]" "0,1"
|
|
bitfld.long 0x00 25. ",Message Identifier bit[25]" "0,1"
|
|
bitfld.long 0x00 24. ",Message Identifier bit[24]" "0,1"
|
|
bitfld.long 0x00 23. ",Message Identifier bit[23]" "0,1"
|
|
bitfld.long 0x00 22. ",Message Identifier bit[22]" "0,1"
|
|
bitfld.long 0x00 21. ",Message Identifier bit[21]" "0,1"
|
|
bitfld.long 0x00 20. ",Message Identifier bit[20]" "0,1"
|
|
bitfld.long 0x00 19. ",Message Identifier bit[19]" "0,1"
|
|
bitfld.long 0x00 18. ",Message Identifier bit[18]" "0,1"
|
|
bitfld.long 0x00 17. ",Message Identifier bit[17]" "0,1"
|
|
bitfld.long 0x00 16. ",Message Identifier bit[16]" "0,1"
|
|
bitfld.long 0x00 15. ",Message Identifier bit[15]" "0,1"
|
|
bitfld.long 0x00 14. ",Message Identifier bit[14]" "0,1"
|
|
bitfld.long 0x00 13. ",Message Identifier bit[13]" "0,1"
|
|
bitfld.long 0x00 12. ",Message Identifier bit[12]" "0,1"
|
|
bitfld.long 0x00 11. ",Message Identifier bit[11]" "0,1"
|
|
bitfld.long 0x00 10. ",Message Identifier bit[10]" "0,1"
|
|
bitfld.long 0x00 9. ",Message Identifier bit[9]" "0,1"
|
|
bitfld.long 0x00 8. ",Message Identifier bit[8]" "0,1"
|
|
bitfld.long 0x00 7. ",Message Identifier bit[7]" "0,1"
|
|
bitfld.long 0x00 6. ",Message Identifier bit[6]" "0,1"
|
|
bitfld.long 0x00 5. ",Message Identifier bit[5]" "0,1"
|
|
bitfld.long 0x00 4. ",Message Identifier bit[4]" "0,1"
|
|
bitfld.long 0x00 3. ",Message Identifier bit[3]" "0,1"
|
|
bitfld.long 0x00 2. ",Message Identifier bit[2]" "0,1"
|
|
bitfld.long 0x00 1. ",Message Identifier bit[1]" "0,1"
|
|
bitfld.long 0x00 0. ",Message Identifier bit[0]" "0,1"
|
|
line.long 0x04 "IF3ARB,IF3 Arbitation Register"
|
|
bitfld.long 0x04 31. " MSGVAl ,Message Valid" "Ignored,Configured"
|
|
bitfld.long 0x04 30. " XTD ,Extended Identifier" "11-bit,29-bit"
|
|
bitfld.long 0x04 29. " DIR ,Message Direction" "Receive,Transmit"
|
|
newline
|
|
hexmask.long 0x04 0.--28. 1. " ID ,Message Identifier"
|
|
endif
|
|
else
|
|
if (((per.l((ad:0xFFF7DC00+0x148)))&0x40000000)==0x0)
|
|
rgroup.long 0x144++0x07
|
|
line.long 0x0 "IF3MASK,IF3 Mask Register"
|
|
bitfld.long 0x00 31. " MXtd ,Mask Extended Identifier" "No effect,Filtering"
|
|
bitfld.long 0x00 30. " MDir ,Mask Message Direction" "No effect,Filtering"
|
|
newline
|
|
bitfld.long 0x00 28. " ID ,Message Identifier bit[28]" "0,1"
|
|
bitfld.long 0x00 27. ",Message Identifier bit[27]" "0,1"
|
|
bitfld.long 0x00 26. ",Message Identifier bit[26]" "0,1"
|
|
bitfld.long 0x00 25. ",Message Identifier bit[25]" "0,1"
|
|
bitfld.long 0x00 24. ",Message Identifier bit[24]" "0,1"
|
|
bitfld.long 0x00 23. ",Message Identifier bit[23]" "0,1"
|
|
bitfld.long 0x00 22. ",Message Identifier bit[22]" "0,1"
|
|
bitfld.long 0x00 21. ",Message Identifier bit[21]" "0,1"
|
|
bitfld.long 0x00 20. ",Message Identifier bit[20]" "0,1"
|
|
bitfld.long 0x00 19. ",Message Identifier bit[19]" "0,1"
|
|
bitfld.long 0x00 18. ",Message Identifier bit[18]" "0,1"
|
|
line.long 0x04 "IF3ARB,IF3 Arbitation Register"
|
|
bitfld.long 0x04 31. " MSGVAl ,Message Valid" "Ignored,Configured"
|
|
bitfld.long 0x04 30. " XTD ,Extended Identifier" "11-bit,29-bit"
|
|
bitfld.long 0x04 29. " DIR ,Message Direction" "Receive,Transmit"
|
|
newline
|
|
hexmask.long.word 0x04 18.--28. 1. " ID ,Message Identifier"
|
|
else
|
|
rgroup.long 0x144++0x07
|
|
line.long 0x0 "IF3MASK,IF3 Mask Register"
|
|
bitfld.long 0x00 31. " MXTD ,Mask Extended Identifier" "No effect,Filtering"
|
|
bitfld.long 0x00 30. " MDIR ,Mask Message Direction" "No effect,Filtering"
|
|
newline
|
|
bitfld.long 0x00 28. " ID ,Message Identifier bit[28]" "0,1"
|
|
bitfld.long 0x00 27. ",Message Identifier bit[27]" "0,1"
|
|
bitfld.long 0x00 26. ",Message Identifier bit[26]" "0,1"
|
|
bitfld.long 0x00 25. ",Message Identifier bit[25]" "0,1"
|
|
bitfld.long 0x00 24. ",Message Identifier bit[24]" "0,1"
|
|
bitfld.long 0x00 23. ",Message Identifier bit[23]" "0,1"
|
|
bitfld.long 0x00 22. ",Message Identifier bit[22]" "0,1"
|
|
bitfld.long 0x00 21. ",Message Identifier bit[21]" "0,1"
|
|
bitfld.long 0x00 20. ",Message Identifier bit[20]" "0,1"
|
|
bitfld.long 0x00 19. ",Message Identifier bit[19]" "0,1"
|
|
bitfld.long 0x00 18. ",Message Identifier bit[18]" "0,1"
|
|
bitfld.long 0x00 17. ",Message Identifier bit[17]" "0,1"
|
|
bitfld.long 0x00 16. ",Message Identifier bit[16]" "0,1"
|
|
bitfld.long 0x00 15. ",Message Identifier bit[15]" "0,1"
|
|
bitfld.long 0x00 14. ",Message Identifier bit[14]" "0,1"
|
|
bitfld.long 0x00 13. ",Message Identifier bit[13]" "0,1"
|
|
bitfld.long 0x00 12. ",Message Identifier bit[12]" "0,1"
|
|
bitfld.long 0x00 11. ",Message Identifier bit[11]" "0,1"
|
|
bitfld.long 0x00 10. ",Message Identifier bit[10]" "0,1"
|
|
bitfld.long 0x00 9. ",Message Identifier bit[9]" "0,1"
|
|
bitfld.long 0x00 8. ",Message Identifier bit[8]" "0,1"
|
|
bitfld.long 0x00 7. ",Message Identifier bit[7]" "0,1"
|
|
bitfld.long 0x00 6. ",Message Identifier bit[6]" "0,1"
|
|
bitfld.long 0x00 5. ",Message Identifier bit[5]" "0,1"
|
|
bitfld.long 0x00 4. ",Message Identifier bit[4]" "0,1"
|
|
bitfld.long 0x00 3. ",Message Identifier bit[3]" "0,1"
|
|
bitfld.long 0x00 2. ",Message Identifier bit[2]" "0,1"
|
|
bitfld.long 0x00 1. ",Message Identifier bit[1]" "0,1"
|
|
bitfld.long 0x00 0. ",Message Identifier bit[0]" "0,1"
|
|
line.long 0x04 "IF3ARB,IF3 Arbitation Register"
|
|
bitfld.long 0x04 31. " MSGVAl ,Message Valid" "Ignored,Configured"
|
|
bitfld.long 0x04 30. " XTD ,Extended Identifier" "11-bit,29-bit"
|
|
bitfld.long 0x04 29. " DIR ,Message Direction" "Receive,Transmit"
|
|
newline
|
|
hexmask.long 0x04 0.--28. 1. " ID ,Message Identifier"
|
|
endif
|
|
endif
|
|
group.long 0x14C++0x0B
|
|
line.long 0x00 "IF3MCTRL,IF3 Message Control Register"
|
|
bitfld.long 0x00 15. " NEWDAT ,New Data" "No new data,New data"
|
|
bitfld.long 0x00 14. " MSGLST ,Message Lost" "Not lost,Lost"
|
|
bitfld.long 0x00 13. " INTPND ,Interrupt Pending" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x00 12. " UMASK ,Use Acceptance Mask" "Ignored,Masked"
|
|
bitfld.long 0x00 11. " TXIE ,Transmit Interrupt Enable" "Unchanged,Enabled"
|
|
bitfld.long 0x00 10. " RXIE ,Receive Interrupt Enable" "Unchanged,Enabled"
|
|
newline
|
|
bitfld.long 0x00 9. " RMTEN ,Remote Enable" "Unchanged,Enabled"
|
|
bitfld.long 0x00 8. " TXRQST ,Transmit Request" "Not requested,Requested"
|
|
bitfld.long 0x00 7. " EOB ,End of Block" "Not last,Single/Last"
|
|
newline
|
|
bitfld.long 0x00 0.--3. " DLC[3-0] ,Data Length Code" "0 byte,1 byte,2 bytes,3 bytes,4 bytes,5 bytes,6 bytes,7 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes"
|
|
line.long 0x04 "IF3DATA,IF3 Data A Register"
|
|
hexmask.long.byte 0x04 24.--31. 1. " DATA[3] ,4th data byte of a CAN Data Frame"
|
|
hexmask.long.byte 0x04 16.--23. 1. " [2] ,3rd data byte of a CAN Data Frame"
|
|
hexmask.long.byte 0x04 8.--15. 1. " [1] ,2nd data byte of a CAN Data Frame"
|
|
hexmask.long.byte 0x04 0.--7. 1. " [0] ,1st data byte of a CAN Data Frame"
|
|
line.long 0x08 "IF3DATB,IF3 Data B Register"
|
|
hexmask.long.byte 0x08 24.--31. 1. " DATA[7] ,8th data byte of a CAN Data Frame"
|
|
hexmask.long.byte 0x08 16.--23. 1. " [6] ,7th data byte of a CAN Data Frame"
|
|
hexmask.long.byte 0x08 8.--15. 1. " [5] ,6th data byte of a CAN Data Frame"
|
|
hexmask.long.byte 0x08 0.--7. 1. " [4] ,5th data byte of a CAN Data Frame"
|
|
group.long 0x160++0x0F
|
|
line.long 0x0 "IF3UENA2_1,Update Enable 2_1 Register"
|
|
bitfld.long 0x00 31. " IF3UPDATEEN[32] ,IF3 Update Enabled Bit[32]" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " [31] ,IF3 Update Enabled Bit[31]" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 29. " [30] ,IF3 Update Enabled Bit[30]" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " [29] ,IF3 Update Enabled Bit[29]" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 27. " [28] ,IF3 Update Enabled Bit[28]" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " [27] ,IF3 Update Enabled Bit[27]" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 25. " [26] ,IF3 Update Enabled Bit[26]" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " [25] ,IF3 Update Enabled Bit[25]" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 23. " [24] ,IF3 Update Enabled Bit[24]" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " [23] ,IF3 Update Enabled Bit[23]" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 21. " [22] ,IF3 Update Enabled Bit[22]" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " [21] ,IF3 Update Enabled Bit[21]" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 19. " [20] ,IF3 Update Enabled Bit[20]" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " [19] ,IF3 Update Enabled Bit[19]" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 17. " [18] ,IF3 Update Enabled Bit[18]" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " [17] ,IF3 Update Enabled Bit[17]" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 15. " [16] ,IF3 Update Enabled Bit[16]" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " [15] ,IF3 Update Enabled Bit[15]" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 13. " [14] ,IF3 Update Enabled Bit[14]" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " [13] ,IF3 Update Enabled Bit[13]" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 11. " [12] ,IF3 Update Enabled Bit[12]" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " [11] ,IF3 Update Enabled Bit[11]" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 9. " [10] ,IF3 Update Enabled Bit[10]" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " [9] ,IF3 Update Enabled Bit[9]" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 7. " [8] ,IF3 Update Enabled Bit[8]" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " [7] ,IF3 Update Enabled Bit[7]" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 5. " [6] ,IF3 Update Enabled Bit[6]" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " [5] ,IF3 Update Enabled Bit[5]" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 3. " [4] ,IF3 Update Enabled Bit[4]" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " [3] ,IF3 Update Enabled Bit[3]" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 1. " [2] ,IF3 Update Enabled Bit[2]" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [1] ,IF3 Update Enabled Bit[1]" "Disabled,Enabled"
|
|
line.long 0x04 "IF3UENA4_3,Update Enable 4_3 Register"
|
|
bitfld.long 0x04 31. " IF3UPDATEEN[64] ,IF3 Update Enabled Bit[64]" "Disabled,Enabled"
|
|
bitfld.long 0x04 30. " [63] ,IF3 Update Enabled Bit[63]" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x04 29. " [62] ,IF3 Update Enabled Bit[62]" "Disabled,Enabled"
|
|
bitfld.long 0x04 28. " [61] ,IF3 Update Enabled Bit[61]" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x04 27. " [60] ,IF3 Update Enabled Bit[60]" "Disabled,Enabled"
|
|
bitfld.long 0x04 26. " [59] ,IF3 Update Enabled Bit[59]" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x04 25. " [58] ,IF3 Update Enabled Bit[58]" "Disabled,Enabled"
|
|
bitfld.long 0x04 24. " [57] ,IF3 Update Enabled Bit[57]" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x04 23. " [56] ,IF3 Update Enabled Bit[56]" "Disabled,Enabled"
|
|
bitfld.long 0x04 22. " [55] ,IF3 Update Enabled Bit[55]" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x04 21. " [54] ,IF3 Update Enabled Bit[54]" "Disabled,Enabled"
|
|
bitfld.long 0x04 20. " [53] ,IF3 Update Enabled Bit[53]" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x04 19. " [52] ,IF3 Update Enabled Bit[52]" "Disabled,Enabled"
|
|
bitfld.long 0x04 18. " [51] ,IF3 Update Enabled Bit[51]" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x04 17. " [50] ,IF3 Update Enabled Bit[50]" "Disabled,Enabled"
|
|
bitfld.long 0x04 16. " [49] ,IF3 Update Enabled Bit[49]" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x04 15. " [48] ,IF3 Update Enabled Bit[48]" "Disabled,Enabled"
|
|
bitfld.long 0x04 14. " [47] ,IF3 Update Enabled Bit[47]" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x04 13. " [46] ,IF3 Update Enabled Bit[46]" "Disabled,Enabled"
|
|
bitfld.long 0x04 12. " [45] ,IF3 Update Enabled Bit[45]" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x04 11. " [44] ,IF3 Update Enabled Bit[44]" "Disabled,Enabled"
|
|
bitfld.long 0x04 10. " [43] ,IF3 Update Enabled Bit[43]" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x04 9. " [42] ,IF3 Update Enabled Bit[42]" "Disabled,Enabled"
|
|
bitfld.long 0x04 8. " [41] ,IF3 Update Enabled Bit[41]" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x04 7. " [40] ,IF3 Update Enabled Bit[40]" "Disabled,Enabled"
|
|
bitfld.long 0x04 6. " [39] ,IF3 Update Enabled Bit[39]" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x04 5. " [38] ,IF3 Update Enabled Bit[38]" "Disabled,Enabled"
|
|
bitfld.long 0x04 4. " [37] ,IF3 Update Enabled Bit[37]" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x04 3. " [36] ,IF3 Update Enabled Bit[36]" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " [35] ,IF3 Update Enabled Bit[35]" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x04 1. " [34] ,IF3 Update Enabled Bit[34]" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " [33] ,IF3 Update Enabled Bit[33]" "Disabled,Enabled"
|
|
line.long 0x08 "IF3UENA6_5,Update Enable 6_5 Register"
|
|
bitfld.long 0x08 31. " IF3UPDATEEN[96] ,IF3 Update Enabled Bit[96]" "Disabled,Enabled"
|
|
bitfld.long 0x08 30. " [95] ,IF3 Update Enabled Bit[95]" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x08 29. " [94] ,IF3 Update Enabled Bit[94]" "Disabled,Enabled"
|
|
bitfld.long 0x08 28. " [93] ,IF3 Update Enabled Bit[93]" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x08 27. " [92] ,IF3 Update Enabled Bit[92]" "Disabled,Enabled"
|
|
bitfld.long 0x08 26. " [91] ,IF3 Update Enabled Bit[91]" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x08 25. " [90] ,IF3 Update Enabled Bit[90]" "Disabled,Enabled"
|
|
bitfld.long 0x08 24. " [89] ,IF3 Update Enabled Bit[89]" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x08 23. " [88] ,IF3 Update Enabled Bit[88]" "Disabled,Enabled"
|
|
bitfld.long 0x08 22. " [87] ,IF3 Update Enabled Bit[87]" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x08 21. " [86] ,IF3 Update Enabled Bit[86]" "Disabled,Enabled"
|
|
bitfld.long 0x08 20. " [85] ,IF3 Update Enabled Bit[85]" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x08 19. " [84] ,IF3 Update Enabled Bit[84]" "Disabled,Enabled"
|
|
bitfld.long 0x08 18. " [83] ,IF3 Update Enabled Bit[83]" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x08 17. " [82] ,IF3 Update Enabled Bit[82]" "Disabled,Enabled"
|
|
bitfld.long 0x08 16. " [81] ,IF3 Update Enabled Bit[81]" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x08 15. " [80] ,IF3 Update Enabled Bit[80]" "Disabled,Enabled"
|
|
bitfld.long 0x08 14. " [79] ,IF3 Update Enabled Bit[79]" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x08 13. " [78] ,IF3 Update Enabled Bit[78]" "Disabled,Enabled"
|
|
bitfld.long 0x08 12. " [77] ,IF3 Update Enabled Bit[77]" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x08 11. " [76] ,IF3 Update Enabled Bit[76]" "Disabled,Enabled"
|
|
bitfld.long 0x08 10. " [75] ,IF3 Update Enabled Bit[75]" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x08 9. " [74] ,IF3 Update Enabled Bit[74]" "Disabled,Enabled"
|
|
bitfld.long 0x08 8. " [73] ,IF3 Update Enabled Bit[73]" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x08 7. " [72] ,IF3 Update Enabled Bit[72]" "Disabled,Enabled"
|
|
bitfld.long 0x08 6. " [71] ,IF3 Update Enabled Bit[71]" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x08 5. " [70] ,IF3 Update Enabled Bit[70]" "Disabled,Enabled"
|
|
bitfld.long 0x08 4. " [69] ,IF3 Update Enabled Bit[69]" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x08 3. " [68] ,IF3 Update Enabled Bit[68]" "Disabled,Enabled"
|
|
bitfld.long 0x08 2. " [67] ,IF3 Update Enabled Bit[67]" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x08 1. " [66] ,IF3 Update Enabled Bit[66]" "Disabled,Enabled"
|
|
bitfld.long 0x08 0. " [65] ,IF3 Update Enabled Bit[65]" "Disabled,Enabled"
|
|
line.long 0x0C "IF3UENA8_7,Update Enable 8_7 Register"
|
|
bitfld.long 0x0C 31. " IF3UPDATEEN[128] ,IF3 Update Enabled Bit[128]" "Disabled,Enabled"
|
|
bitfld.long 0x0C 30. " [127] ,IF3 Update Enabled Bit[127]" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x0C 29. " [126] ,IF3 Update Enabled Bit[126]" "Disabled,Enabled"
|
|
bitfld.long 0x0C 28. " [125] ,IF3 Update Enabled Bit[125]" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x0C 27. " [124] ,IF3 Update Enabled Bit[124]" "Disabled,Enabled"
|
|
bitfld.long 0x0C 26. " [123] ,IF3 Update Enabled Bit[123]" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x0C 25. " [122] ,IF3 Update Enabled Bit[122]" "Disabled,Enabled"
|
|
bitfld.long 0x0C 24. " [121] ,IF3 Update Enabled Bit[121]" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x0C 23. " [120] ,IF3 Update Enabled Bit[120]" "Disabled,Enabled"
|
|
bitfld.long 0x0C 22. " [119] ,IF3 Update Enabled Bit[119]" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x0C 21. " [118] ,IF3 Update Enabled Bit[118]" "Disabled,Enabled"
|
|
bitfld.long 0x0C 20. " [117] ,IF3 Update Enabled Bit[117]" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x0C 19. " [116] ,IF3 Update Enabled Bit[116]" "Disabled,Enabled"
|
|
bitfld.long 0x0C 18. " [115] ,IF3 Update Enabled Bit[115]" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x0C 17. " [114] ,IF3 Update Enabled Bit[114]" "Disabled,Enabled"
|
|
bitfld.long 0x0C 16. " [113] ,IF3 Update Enabled Bit[113]" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x0C 15. " [112] ,IF3 Update Enabled Bit[112]" "Disabled,Enabled"
|
|
bitfld.long 0x0C 14. " [111] ,IF3 Update Enabled Bit[111]" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x0C 13. " [110] ,IF3 Update Enabled Bit[110]" "Disabled,Enabled"
|
|
bitfld.long 0x0C 12. " [109] ,IF3 Update Enabled Bit[109]" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x0C 11. " [108] ,IF3 Update Enabled Bit[108]" "Disabled,Enabled"
|
|
bitfld.long 0x0C 10. " [107] ,IF3 Update Enabled Bit[107]" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x0C 9. " [106] ,IF3 Update Enabled Bit[106]" "Disabled,Enabled"
|
|
bitfld.long 0x0C 8. " [105] ,IF3 Update Enabled Bit[105]" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x0C 7. " [104] ,IF3 Update Enabled Bit[104]" "Disabled,Enabled"
|
|
bitfld.long 0x0C 6. " [103] ,IF3 Update Enabled Bit[103]" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x0C 5. " [102] ,IF3 Update Enabled Bit[102]" "Disabled,Enabled"
|
|
bitfld.long 0x0C 4. " [101] ,IF3 Update Enabled Bit[101]" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x0C 3. " [100] ,IF3 Update Enabled Bit[100]" "Disabled,Enabled"
|
|
bitfld.long 0x0C 2. " [99] ,IF3 Update Enabled Bit[99]" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x0C 1. " [98] ,IF3 Update Enabled Bit[98]" "Disabled,Enabled"
|
|
bitfld.long 0x0C 0. " [97] ,IF3 Update Enabled Bit[97]" "Disabled,Enabled"
|
|
newline
|
|
group.long 0x1E0++0x03
|
|
line.long 0x0 "IOCTRLTX,TX IO Control Register"
|
|
sif (cpu()!="TMS470MF031"&&cpu()!="TMS470MF042"&&cpu()!="TMS470MF066"&&cpu()!=("TMS570LS10116-ZWT")&&cpu()!=("TMS570LS10216-ZWT")&&cpu()!=("TMS570LS10106-ZWT")&&cpu()!=("TMS570LS10206-ZWT")&&cpu()!=("TMS570LS10116-PGE")&&cpu()!=("TMS570LS10216-PGE")&&cpu()!=("TMS570LS10106-PGE")&&cpu()!=("TMS570LS10206-PGE")&&cpu()!=("TMS570LC4357")&&cpu()!=("TMS570LS0332")&&cpu()!=("TMS570LS0432")&&!cpuis("TMS570LS1114*")&&!cpuis("TMS570LS1115*")&&!cpuis("TMS570LS1224*")&&!cpuis("TMS570LS1225*")&&!cpuis("TMS570LS1227*")&&!cpuis("TMS570LS21*")&&!cpuis("TMS570LS31*")&&!cpuis("TMS570LS0232")&&!cpuis("TMS570LS0714*")&&!cpuis("TMS570LS0914*"))
|
|
bitfld.long 0x00 19. " SR ,Slew Rate Selection of Output Driver" "Normal,Slow"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 18. " PU ,Selection of Pull Direction" "Pull down,Pull up"
|
|
bitfld.long 0x00 17. " PD ,Pull Functionality Disable" "No,Yes"
|
|
bitfld.long 0x00 16. " OD ,Open Drain Mode" "Push pull,Open Drain"
|
|
bitfld.long 0x00 3. " FUNC ,Functionality of Pin" "General,CAN"
|
|
newline
|
|
bitfld.long 0x00 2. " DIR ,Direction of Pin" "Input,Output"
|
|
bitfld.long 0x00 1. " OUT ,Value to Drive to Pin if Configured for I/O" "Low,High"
|
|
bitfld.long 0x00 0. " IN ,Value of Pin" "Low,High"
|
|
group.long 0x1E4++0x03
|
|
line.long 0x0 "IOCTRLRX,RX IO Control Register"
|
|
sif (cpu()!="TMS470MF031"&&cpu()!="TMS470MF042"&&cpu()!="TMS470MF066"&&cpu()!=("TMS570LS10116-ZWT")&&cpu()!=("TMS570LS10216-ZWT")&&cpu()!=("TMS570LS10106-ZWT")&&cpu()!=("TMS570LS10206-ZWT")&&cpu()!=("TMS570LS10116-PGE")&&cpu()!=("TMS570LS10216-PGE")&&cpu()!=("TMS570LS10106-PGE")&&cpu()!=("TMS570LS10206-PGE")&&cpu()!=("TMS570LC4357")&&cpu()!=("TMS570LS0332")&&cpu()!=("TMS570LS0432")&&!cpuis("TMS570LS1114*")&&!cpuis("TMS570LS1115*")&&!cpuis("TMS570LS1224*")&&!cpuis("TMS570LS1225*")&&!cpuis("TMS570LS1227*")&&!cpuis("TMS570LS21*")&&!cpuis("TMS570LS31*")&&!cpuis("TMS570LS0232")&&!cpuis("TMS570LS0714*")&&!cpuis("TMS570LS0914*"))
|
|
bitfld.long 0x00 19. " SR ,Slew Rate Selection of Output Driver" "Normal,Slow"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 18. " PU ,Selection of Pull Direction" "Pull down,Pull up"
|
|
bitfld.long 0x00 17. " PD ,Pull Functionality Disable" "No,Yes"
|
|
bitfld.long 0x00 16. " OD ,Open Drain Mode" "Push pull,Open Drain"
|
|
bitfld.long 0x00 3. " FUNC ,Functionality of Pin" "General,CAN"
|
|
newline
|
|
bitfld.long 0x00 2. " DIR ,Direction of Pin" "Input,Output"
|
|
bitfld.long 0x00 1. " OUT ,Value to Drive to Pin if Configured for I/O" "Low,High"
|
|
bitfld.long 0x00 0. " IN ,Value of Pin" "Low,High"
|
|
sif cpuis("TMS570LS0232")||cpuis("TMS570LS0714*")||cpuis("TMS570LS0914*")
|
|
endian.le
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
tree "DCAN2"
|
|
base ad:0xFFF7DE00
|
|
sif cpuis("TMS570LS0232")||cpuis("TMS570LS0714*")||cpuis("TMS570LS0914*")
|
|
endian.be
|
|
endif
|
|
width 12.
|
|
group.long 0x00++0x3
|
|
line.long 0x0 "CTRL,Config Register"
|
|
bitfld.long 0x00 25. " WUBA ,Automatic Wake Up on Bus Activity When in Local Power Down Mode" "Not detected,Detected"
|
|
bitfld.long 0x00 24. " PDR ,Request for Local Low Power Down Mode" "Not requested,Power down"
|
|
sif (cpu()!=("TMS570LS0332")&&cpu()!=("TMS570LS0432")&&!cpuis("TMS570LS0232"))
|
|
newline
|
|
bitfld.long 0x00 20. " DE3 ,DMA Enable for IF3" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 19. " DE2 ,DMA Enable for IF2" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " DE1 ,DMA Enable for IF1" "Disabled,Enabled"
|
|
endif
|
|
newline
|
|
bitfld.long 0x00 17. " IE1 ,DCAN1INT Interrupt Enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 16. " INITDBG ,Internal Init State While Debug Access Mode" "No debug,Debug"
|
|
bitfld.long 0x00 15. " SWR ,SW Reset Enable" "No reset,Reset"
|
|
bitfld.long 0x00 10.--13. " PMD ,Parity on/off" "Enabled,Enabled,Enabled,Enabled,Enabled,Disabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 9. " ABO ,Auto Bus On Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " IDS ,Interruption Debug Support Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " TEST ,Test Mode Enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 6. " CCE ,Configuration Change Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " DAR ,Disable Automatic Retransmission" "No,Yes"
|
|
bitfld.long 0x00 3. " EIE ,Error Interrupt Enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 2. " SIE ,Status Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " IE ,DCAN0INT Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " INIT ,Initialization" "Disabled,Enabled"
|
|
sif (cpu()=="TMS470MF031"||cpu()=="TMS470MF042"||cpu()=="TMS470MF066"||cpu()==("TMS570LS10116-ZWT")||cpu()==("TMS570LS10216-ZWT")||cpu()==("TMS570LS10106-ZWT")||cpu()==("TMS570LS10206-ZWT")||cpu()==("TMS570LS10116-PGE")||cpu()==("TMS570LS10216-PGE")||cpu()==("TMS570LS10106-PGE")||cpu()==("TMS570LS10206-PGE")||cpu()==("TMS570LC4357")||cpuis("TMS570LS1114*")||cpuis("TMS570LS1115*")||cpuis("TMS570LS1224*")||cpuis("TMS570LS1225*")||cpuis("TMS570LS1227*"))
|
|
group.long 0x04++0x3
|
|
line.long 0x0 "ES,Error and Status Register"
|
|
rbitfld.long 0x00 10. " PDA ,Local Power Down Mode Acknowledge" "Not in,Is in"
|
|
rbitfld.long 0x00 9. " WAKEUPPND ,Wake Up Pending" "No requested,Requested"
|
|
rbitfld.long 0x00 8. " PER ,Parity Error Detected" "No error,Error"
|
|
newline
|
|
rbitfld.long 0x00 7. " BOFF ,Bus-Off State" "Not in,In"
|
|
rbitfld.long 0x00 6. " EWARN ,Warning state" "<96,>96"
|
|
rbitfld.long 0x00 5. " EPASS ,Error Passive State" "CAN Bus,Passive"
|
|
newline
|
|
bitfld.long 0x00 4. " RXOK ,Received a Message successfully" "No,Yes"
|
|
bitfld.long 0x00 3. " TXOK ,Transmitted a Message successfully" "No,Yes"
|
|
bitfld.long 0x00 0.--2. " LEC ,Last Error Code" "No error,Stuff,Form,Ack,Bit1,Bit0,CRC,No CAN"
|
|
elif !cpuis("TMS570LS3137-EP")
|
|
hgroup.long 0x04++0x3
|
|
hide.long 0x0 "STAT,Status Register"
|
|
in
|
|
else
|
|
if (((per.l.be(ad:0xFFF7DE00))&0x100)==0x100)
|
|
group.long 0x04++0x3
|
|
line.long 0x0 "ES,Error and Status Register"
|
|
rbitfld.long 0x00 10. " PDA ,Local Power Down Mode Acknowledge" "Not in,Is in"
|
|
rbitfld.long 0x00 9. " WAKEUPPND ,Wake Up Pending" "No requested,Requested"
|
|
rbitfld.long 0x00 8. " PER ,Parity Error Detected" "No error,Error"
|
|
newline
|
|
rbitfld.long 0x00 7. " BOFF ,Bus-Off State" "Not in,In"
|
|
rbitfld.long 0x00 6. " EWARN ,Warning state" "<96,>96"
|
|
rbitfld.long 0x00 5. " EPASS ,Error Passive State" "CAN Bus,Passive"
|
|
newline
|
|
bitfld.long 0x00 4. " RXOK ,Received a Message successfully" "No,Yes"
|
|
bitfld.long 0x00 3. " TXOK ,Transmitted a Message successfully" "No,Yes"
|
|
bitfld.long 0x00 0.--2. " LEC ,Last Error Code" "No error,Stuff,Form,Ack,Bit1,Bit0,CRC,No CAN"
|
|
else
|
|
hgroup.long 0x04++0x3
|
|
hide.long 0x0 "ES,Error and Status Register"
|
|
in
|
|
endif
|
|
endif
|
|
rgroup.long 0x08++0x3
|
|
line.long 0x0 "ERRC,Error Counter Register"
|
|
bitfld.long 0x00 15. " RP ,Receive Error Passive" "Below,Reached"
|
|
hexmask.long.byte 0x00 8.--14. 1. " REC ,Receive Error Counter"
|
|
hexmask.long.byte 0x00 0.--7. 1. " TEC ,Transmit Error Counter"
|
|
sif cpuis("TMS570LS0232")||cpuis("TMS570LS0714*")||cpuis("TMS570LS0914*")
|
|
if (((per.l.be(ad:0xFFF7DE00))&0x41)==0x41)
|
|
group.long 0x0C++0x3
|
|
line.long 0x0 "BTBRP,Bit Timing_BRP Extension Register"
|
|
bitfld.long 0x00 16.--19. " BRPE ,Baud Rate Prescaler Extension" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--14. " TSEG2 ,The Time Segment After the Sample Point" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 8.--11. " TSEG1 ,The Time Segment Before the Sample Point" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 6.--7. " SJW ,Synchronization Jump Width" "0,1,2,3"
|
|
bitfld.long 0x00 0.--5. " BRP ,Baud Rate Prescaler" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
else
|
|
rgroup.long 0x0C++0x3
|
|
line.long 0x0 "BTBRP,Bit Timing_BRP Extension Register"
|
|
bitfld.long 0x00 16.--19. " BRPE ,Baud Rate Prescaler Extension" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--14. " TSEG2 ,The Time Segment After the Sample Point" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 8.--11. " TSEG1 ,The Time Segment Before the Sample Point" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 6.--7. " SJW ,Synchronization Jump Width" "0,1,2,3"
|
|
bitfld.long 0x00 0.--5. " BRP ,Baud Rate Prescaler" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
endif
|
|
else
|
|
group.long 0x0C++0x3
|
|
line.long 0x0 "BTBRP,Bit Timing_BRP Extension Register"
|
|
bitfld.long 0x00 16.--19. " BRPE ,Baud Rate Prescaler Extension" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--14. " TSEG2 ,The Time Segment After the Sample Point" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 8.--11. " TSEG1 ,The Time Segment Before the Sample Point" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 6.--7. " SJW ,Synchronization Jump Width" "0,1,2,3"
|
|
bitfld.long 0x00 0.--5. " BRP ,Baud Rate Prescaler" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
endif
|
|
rgroup.long 0x10++0x3
|
|
line.long 0x0 "INTR,Interrupt Register"
|
|
hexmask.long.byte 0x00 16.--23. 1. " INT1ID[7-0] ,Interrupt 1 Identifier"
|
|
hexmask.long.word 0x00 0.--15. 1. " INTID[15-0] ,Interrupt Identifier"
|
|
sif cpuis("TMS570LS0232")||cpuis("TMS570LS0714*")||cpuis("TMS570LS0914*")
|
|
if (((per.l.be(ad:0xFFF7DE00))&0x41)==0x41)
|
|
group.long 0x14++0x3
|
|
line.long 0x0 "TEST,Test Register"
|
|
bitfld.long 0x00 9. " RDA ,RAM Direct Access Enable" "Normal,Enabled"
|
|
bitfld.long 0x00 8. " EXL ,External Loop Back Mode" "Normal,Enabled"
|
|
bitfld.long 0x00 7. " RX ,Receive Pin" "Dominant,Recessive"
|
|
newline
|
|
bitfld.long 0x00 5.--6. " TX1-0 ,Control of CAN_TX pin" "Normal,Sample point,Dominant,Recessive"
|
|
bitfld.long 0x00 4. " LBACK ,Loop Back Mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " SILENT ,Silent Mode" "Normal,Enabled"
|
|
else
|
|
rgroup.long 0x14++0x3
|
|
line.long 0x0 "TEST,Test Register"
|
|
bitfld.long 0x00 9. " RDA ,RAM Direct Access Enable" "Normal,Enabled"
|
|
bitfld.long 0x00 8. " EXL ,External Loop Back Mode" "Normal,Enabled"
|
|
bitfld.long 0x00 7. " RX ,Receive Pin" "Dominant,Recessive"
|
|
newline
|
|
bitfld.long 0x00 5.--6. " TX1-0 ,Control of CAN_TX pin" "Normal,Sample point,Dominant,Recessive"
|
|
bitfld.long 0x00 4. " LBACK ,Loop Back Mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " SILENT ,Silent Mode" "Normal,Enabled"
|
|
endif
|
|
elif !cpuis("TMS570LS3137-EP")
|
|
group.long 0x14++0x3
|
|
line.long 0x0 "TEST,Test Register"
|
|
bitfld.long 0x00 9. " RDA ,RAM Direct Access Enable" "Normal,Enabled"
|
|
bitfld.long 0x00 8. " EXL ,External Loop Back Mode" "Normal,Enabled"
|
|
bitfld.long 0x00 7. " RX ,Receive Pin" "Dominant,Recessive"
|
|
newline
|
|
sif (cpu()=="TMS470MF031"||cpu()=="TMS470MF042"||cpu()=="TMS470MF066"||cpu()==("TMS570LS10116-ZWT")||cpu()==("TMS570LS10216-ZWT")||cpu()==("TMS570LS10106-ZWT")||cpu()==("TMS570LS10206-ZWT")||cpu()==("TMS570LS10116-PGE")||cpu()==("TMS570LS10216-PGE")||cpu()==("TMS570LS10106-PGE")||cpu()==("TMS570LS10206-PGE")||cpu()==("TMS570LC4357")||cpu()==("TMS570LS0332")||cpu()==("TMS570LS0432")||cpuis("TMS570LS1114*")||cpuis("TMS570LS1115*")||cpuis("TMS570LS1224*")||cpuis("TMS570LS1225*")||cpuis("TMS570LS1227*")||cpuis("TMS570LS21*")||cpuis("TMS570LS31*")||cpuis("TMS570LS0232")||cpuis("TMS570LS0714*")||cpuis("TMS570LS0914*"))
|
|
bitfld.long 0x00 5.--6. " TX1-0 ,Control of CAN_TX pin" "Normal,Sample point,Dominant,Recessive"
|
|
else
|
|
bitfld.long 0x00 5.--6. " TX1-0 ,Control of CAN_TX pin" "Reset,Sample point,Dominant,Recessive"
|
|
endif
|
|
bitfld.long 0x00 4. " LBACK ,Loop Back Mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " SILENT ,Silent Mode" "Normal,Enabled"
|
|
else
|
|
if (((per.l.be(ad:0xFFF7DE00))&0x80)==0x80)
|
|
group.long 0x14++0x3
|
|
line.long 0x0 "TEST,Test Register"
|
|
bitfld.long 0x00 9. " RDA ,RAM Direct Access Enable" "Normal,Enabled"
|
|
bitfld.long 0x00 8. " EXL ,External Loop Back Mode" "Normal,Enabled"
|
|
bitfld.long 0x00 7. " RX ,Receive Pin" "Dominant,Recessive"
|
|
newline
|
|
bitfld.long 0x00 5.--6. " TX1-0 ,Control of CAN_TX pin" "Normal,Sample point,Dominant,Recessive"
|
|
bitfld.long 0x00 4. " LBACK ,Loop Back Mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " SILENT ,Silent Mode" "Normal,Enabled"
|
|
else
|
|
rgroup.long 0x14++0x3
|
|
line.long 0x0 "TEST,Test Register"
|
|
bitfld.long 0x00 9. " RDA ,RAM Direct Access Enable" "Normal,Enabled"
|
|
bitfld.long 0x00 8. " EXL ,External Loop Back Mode" "Normal,Enabled"
|
|
bitfld.long 0x00 7. " RX ,Receive Pin" "Dominant,Recessive"
|
|
newline
|
|
bitfld.long 0x00 5.--6. " TX1-0 ,Control of CAN_TX pin" "Normal,Sample point,Dominant,Recessive"
|
|
bitfld.long 0x00 4. " LBACK ,Loop Back Mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " SILENT ,Silent Mode" "Normal,Enabled"
|
|
endif
|
|
endif
|
|
rgroup.long 0x1C++0x3
|
|
line.long 0x0 "PERR,Parity Error Code Register"
|
|
bitfld.long 0x00 8.--10. " WORD_NUMBER ,Word Number" ",1,2,3,4,5,?..."
|
|
hexmask.long.byte 0x00 0.--7. 1. " MESSAGE_NUMBER ,Message Number"
|
|
sif (cpu()=="TMS470MF031"||cpu()=="TMS470MF042"||cpu()=="TMS470MF066"||cpuis("TMS570LS0232")||cpuis("TMS570LS0714*")||cpuis("TMS570LS0914*"))
|
|
rgroup.long 0x20++0x3
|
|
line.long 0x00 "REL,DCAN Core Release Register"
|
|
bitfld.long 0x00 28.--31. " REL ,Core Release" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 24.--27. " STEP ,Step of Core Release" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 20.--23. " SUBSTEP ,Substep of Core Release" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " YEAR ,Design Time Stamp - Year" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. " MON ,Design Time Stamp - Month"
|
|
hexmask.long.byte 0x00 0.--7. 1. " DAY ,Design Time Stamp - Day"
|
|
endif
|
|
width 19.
|
|
sif (cpu()=="TMS570LC4357")
|
|
group.long 0x24++0x0B
|
|
line.long 0x00 "DCAN_ECCDIAG,ECC Diagnostic Register"
|
|
bitfld.long 0x00 0.--3. " ECCDIAG , SECDED diagnostic mode enable/disable" ",,,,,Enabled,,,,,Disabled,?..."
|
|
line.long 0x04 "DCAN_ECCDIAG_STAT, ECC Diagnostic Status Register"
|
|
eventfld.long 0x04 8. " DEFLG_DIAG , Double bit error diagnostic" "No error,Error"
|
|
eventfld.long 0x04 0. " SEFLG_DIAG , Single bit error diagnostic" "No error,Error"
|
|
line.long 0x08 "DCAN_ECC_CS, ECC Control and Status Register"
|
|
bitfld.long 0x08 24.--27. " SBE_EVT_EN , Single bit error event" "Enabled,Enabled,Enabled,Enabled,Enabled,Disabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled"
|
|
bitfld.long 0x08 16.--19. " ECCMODE , Single bit error correction" "Enabled,Enabled,Enabled,Enabled,Enabled,Disabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled"
|
|
eventfld.long 0x08 8. " DEFLG , Double bit error flag" "No error,Error"
|
|
eventfld.long 0x08 0. " SEFLG , Single bit error flag" "No error,Error"
|
|
rgroup.long 0x30++0x03
|
|
line.long 0x00 "DCAN_ECC_SERR, ECC Single Bit Error Code Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " Message_Number , Message object number where ECC single bit error has been detected"
|
|
endif
|
|
width 12.
|
|
group.long 0x80++0x03
|
|
line.long 0x00 "ABOT,Auto Bus On Time"
|
|
rgroup.long 0x84++0x4F
|
|
line.long 0x00 "TRREQ,Transmission Request X"
|
|
bitfld.long 0x00 14.--15. " TXRQSTREG8 ,Transmission Request 8" "0,1,2,3"
|
|
bitfld.long 0x00 12.--13. " TXRQSTREG7 ,Transmission Request 7" "0,1,2,3"
|
|
bitfld.long 0x00 10.--11. " TXRQSTREG6 ,Transmission Request 6" "0,1,2,3"
|
|
bitfld.long 0x00 8.--9. " TXRQSTREG5 ,Transmission Request 5" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 6.--7. " TXRQSTREG4 ,Transmission Request 4" "0,1,2,3"
|
|
bitfld.long 0x00 4.--5. " TXRQSTREG3 ,Transmission Request 3" "0,1,2,3"
|
|
bitfld.long 0x00 2.--3. " TXRQSTREG2 ,Transmission Request 2" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. " TXRQSTREG1 ,Transmission Request 1" "0,1,2,3"
|
|
line.long 0x04 "TRREQ12,Transmission Request 1-2"
|
|
bitfld.long 0x04 31. " TXRQST[32] ,Transmission Request Bits[32]" "Not requested,Requested"
|
|
bitfld.long 0x04 30. " [31] ,Transmission Request Bits[31]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x04 29. " [30] ,Transmission Request Bits[30]" "Not requested,Requested"
|
|
bitfld.long 0x04 28. " [29] ,Transmission Request Bits[29]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x04 27. " [28] ,Transmission Request Bits[28]" "Not requested,Requested"
|
|
bitfld.long 0x04 26. " [27] ,Transmission Request Bits[27]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x04 25. " [26] ,Transmission Request Bits[26]" "Not requested,Requested"
|
|
bitfld.long 0x04 24. " [25] ,Transmission Request Bits[25]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x04 23. " [24] ,Transmission Request Bits[24]" "Not requested,Requested"
|
|
bitfld.long 0x04 22. " [23] ,Transmission Request Bits[23]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x04 21. " [22] ,Transmission Request Bits[22]" "Not requested,Requested"
|
|
bitfld.long 0x04 20. " [21] ,Transmission Request Bits[21]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x04 19. " [20] ,Transmission Request Bits[20]" "Not requested,Requested"
|
|
bitfld.long 0x04 18. " [19] ,Transmission Request Bits[19]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x04 17. " [18] ,Transmission Request Bits[18]" "Not requested,Requested"
|
|
bitfld.long 0x04 16. " [17] ,Transmission Request Bits[17]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x04 15. " [16] ,Transmission Request Bits[16]" "Not requested,Requested"
|
|
bitfld.long 0x04 14. " [15] ,Transmission Request Bits[15]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x04 13. " [14] ,Transmission Request Bits[14]" "Not requested,Requested"
|
|
bitfld.long 0x04 12. " [13] ,Transmission Request Bits[13]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x04 11. " [12] ,Transmission Request Bits[12]" "Not requested,Requested"
|
|
bitfld.long 0x04 10. " [11] ,Transmission Request Bits[11]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x04 9. " [10] ,Transmission Request Bits[10]" "Not requested,Requested"
|
|
bitfld.long 0x04 8. " [9] ,Transmission Request Bits[9]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x04 7. " [8] ,Transmission Request Bits[8]" "Not requested,Requested"
|
|
bitfld.long 0x04 6. " [7] ,Transmission Request Bits[7]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x04 5. " [6] ,Transmission Request Bits[6]" "Not requested,Requested"
|
|
bitfld.long 0x04 4. " [5] ,Transmission Request Bits[5]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x04 3. " [4] ,Transmission Request Bits[4]" "Not requested,Requested"
|
|
bitfld.long 0x04 2. " [3] ,Transmission Request Bits[3]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x04 1. " [2] ,Transmission Request Bits[2]" "Not requested,Requested"
|
|
bitfld.long 0x04 0. " [1] ,Transmission Request Bits[1]" "Not requested,Requested"
|
|
line.long 0x08 "TRREQ34,Transmission Request 3-4"
|
|
bitfld.long 0x08 31. " TXRQST[64] ,Transmission Request Bits[64]" "Not requested,Requested"
|
|
bitfld.long 0x08 30. " [63] ,Transmission Request Bits[63]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x08 29. " [62] ,Transmission Request Bits[62]" "Not requested,Requested"
|
|
bitfld.long 0x08 28. " [61] ,Transmission Request Bits[61]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x08 27. " [60] ,Transmission Request Bits[60]" "Not requested,Requested"
|
|
bitfld.long 0x08 26. " [59] ,Transmission Request Bits[59]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x08 25. " [58] ,Transmission Request Bits[58]" "Not requested,Requested"
|
|
bitfld.long 0x08 24. " [57] ,Transmission Request Bits[57]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x08 23. " [56] ,Transmission Request Bits[56]" "Not requested,Requested"
|
|
bitfld.long 0x08 22. " [55] ,Transmission Request Bits[55]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x08 21. " [54] ,Transmission Request Bits[54]" "Not requested,Requested"
|
|
bitfld.long 0x08 20. " [53] ,Transmission Request Bits[53]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x08 19. " [52] ,Transmission Request Bits[52]" "Not requested,Requested"
|
|
bitfld.long 0x08 18. " [51] ,Transmission Request Bits[51]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x08 17. " [50] ,Transmission Request Bits[50]" "Not requested,Requested"
|
|
bitfld.long 0x08 16. " [49] ,Transmission Request Bits[49]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x08 15. " [48] ,Transmission Request Bits[48]" "Not requested,Requested"
|
|
bitfld.long 0x08 14. " [47] ,Transmission Request Bits[47]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x08 13. " [46] ,Transmission Request Bits[46]" "Not requested,Requested"
|
|
bitfld.long 0x08 12. " [45] ,Transmission Request Bits[45]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x08 11. " [44] ,Transmission Request Bits[44]" "Not requested,Requested"
|
|
bitfld.long 0x08 10. " [43] ,Transmission Request Bits[43]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x08 9. " [42] ,Transmission Request Bits[42]" "Not requested,Requested"
|
|
bitfld.long 0x08 8. " [41] ,Transmission Request Bits[41]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x08 7. " [40] ,Transmission Request Bits[40]" "Not requested,Requested"
|
|
bitfld.long 0x08 6. " [39] ,Transmission Request Bits[39]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x08 5. " [38] ,Transmission Request Bits[38]" "Not requested,Requested"
|
|
bitfld.long 0x08 4. " [37] ,Transmission Request Bits[37]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x08 3. " [36] ,Transmission Request Bits[36]" "Not requested,Requested"
|
|
bitfld.long 0x08 2. " [35] ,Transmission Request Bits[35]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x08 1. " [34] ,Transmission Request Bits[34]" "Not requested,Requested"
|
|
bitfld.long 0x08 0. " [33] ,Transmission Request Bits[33]" "Not requested,Requested"
|
|
line.long 0x0C "TRREQ56,Transmission Request 5-6"
|
|
bitfld.long 0x0C 31. " TXRQST[96] ,Transmission Request Bits[96]" "Not requested,Requested"
|
|
bitfld.long 0x0C 30. " [95] ,Transmission Request Bits[95]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x0C 29. " [94] ,Transmission Request Bits[94]" "Not requested,Requested"
|
|
bitfld.long 0x0C 28. " [93] ,Transmission Request Bits[93]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x0C 27. " [92] ,Transmission Request Bits[92]" "Not requested,Requested"
|
|
bitfld.long 0x0C 26. " [91] ,Transmission Request Bits[91]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x0C 25. " [90] ,Transmission Request Bits[90]" "Not requested,Requested"
|
|
bitfld.long 0x0C 24. " [89] ,Transmission Request Bits[89]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x0C 23. " [88] ,Transmission Request Bits[88]" "Not requested,Requested"
|
|
bitfld.long 0x0C 22. " [87] ,Transmission Request Bits[87]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x0C 21. " [86] ,Transmission Request Bits[86]" "Not requested,Requested"
|
|
bitfld.long 0x0C 20. " [85] ,Transmission Request Bits[85]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x0C 19. " [84] ,Transmission Request Bits[84]" "Not requested,Requested"
|
|
bitfld.long 0x0C 18. " [83] ,Transmission Request Bits[83]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x0C 17. " [82] ,Transmission Request Bits[82]" "Not requested,Requested"
|
|
bitfld.long 0x0C 16. " [81] ,Transmission Request Bits[81]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x0C 15. " [80] ,Transmission Request Bits[80]" "Not requested,Requested"
|
|
bitfld.long 0x0C 14. " [79] ,Transmission Request Bits[79]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x0C 13. " [78] ,Transmission Request Bits[78]" "Not requested,Requested"
|
|
bitfld.long 0x0C 12. " [77] ,Transmission Request Bits[77]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x0C 11. " [76] ,Transmission Request Bits[76]" "Not requested,Requested"
|
|
bitfld.long 0x0C 10. " [75] ,Transmission Request Bits[75]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x0C 9. " [74] ,Transmission Request Bits[74]" "Not requested,Requested"
|
|
bitfld.long 0x0C 8. " [73] ,Transmission Request Bits[73]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x0C 7. " [72] ,Transmission Request Bits[72]" "Not requested,Requested"
|
|
bitfld.long 0x0C 6. " [71] ,Transmission Request Bits[71]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x0C 5. " [70] ,Transmission Request Bits[70]" "Not requested,Requested"
|
|
bitfld.long 0x0C 4. " [69] ,Transmission Request Bits[69]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x0C 3. " [68] ,Transmission Request Bits[68]" "Not requested,Requested"
|
|
bitfld.long 0x0C 2. " [67] ,Transmission Request Bits[67]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x0C 1. " [66] ,Transmission Request Bits[66]" "Not requested,Requested"
|
|
bitfld.long 0x0C 0. " [65] ,Transmission Request Bits[65]" "Not requested,Requested"
|
|
line.long 0x10 "TRREQ78,Transmission Request 7-8"
|
|
bitfld.long 0x10 31. " TXRQST[128] ,Transmission Request Bits[128]" "Not requested,Requested"
|
|
bitfld.long 0x10 30. " [127] ,Transmission Request Bits[127]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x10 29. " [126] ,Transmission Request Bits[126]" "Not requested,Requested"
|
|
bitfld.long 0x10 28. " [125] ,Transmission Request Bits[125]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x10 27. " [124] ,Transmission Request Bits[124]" "Not requested,Requested"
|
|
bitfld.long 0x10 26. " [123] ,Transmission Request Bits[123]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x10 25. " [122] ,Transmission Request Bits[122]" "Not requested,Requested"
|
|
bitfld.long 0x10 24. " [121] ,Transmission Request Bits[121]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x10 23. " [120] ,Transmission Request Bits[120]" "Not requested,Requested"
|
|
bitfld.long 0x10 22. " [119] ,Transmission Request Bits[119]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x10 21. " [118] ,Transmission Request Bits[118]" "Not requested,Requested"
|
|
bitfld.long 0x10 20. " [117] ,Transmission Request Bits[117]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x10 19. " [116] ,Transmission Request Bits[116]" "Not requested,Requested"
|
|
bitfld.long 0x10 18. " [115] ,Transmission Request Bits[115]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x10 17. " [114] ,Transmission Request Bits[114]" "Not requested,Requested"
|
|
bitfld.long 0x10 16. " [113] ,Transmission Request Bits[113]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x10 15. " [112] ,Transmission Request Bits[112]" "Not requested,Requested"
|
|
bitfld.long 0x10 14. " [111] ,Transmission Request Bits[111]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x10 13. " [110] ,Transmission Request Bits[110]" "Not requested,Requested"
|
|
bitfld.long 0x10 12. " [109] ,Transmission Request Bits[109]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x10 11. " [108] ,Transmission Request Bits[108]" "Not requested,Requested"
|
|
bitfld.long 0x10 10. " [107] ,Transmission Request Bits[107]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x10 9. " [106] ,Transmission Request Bits[106]" "Not requested,Requested"
|
|
bitfld.long 0x10 8. " [105] ,Transmission Request Bits[105]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x10 7. " [104] ,Transmission Request Bits[104]" "Not requested,Requested"
|
|
bitfld.long 0x10 6. " [103] ,Transmission Request Bits[103]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x10 5. " [102] ,Transmission Request Bits[102]" "Not requested,Requested"
|
|
bitfld.long 0x10 4. " [101] ,Transmission Request Bits[101]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x10 3. " [100] ,Transmission Request Bits[100]" "Not requested,Requested"
|
|
bitfld.long 0x10 2. " [99] ,Transmission Request Bits[99]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x10 1. " [98] ,Transmission Request Bits[98]" "Not requested,Requested"
|
|
bitfld.long 0x10 0. " [97] ,Transmission Request Bits[97]" "Not requested,Requested"
|
|
line.long 0x14 "NEWDAT,New Data X"
|
|
bitfld.long 0x14 14.--15. " NEWDATREG8 ,New Data 8" "0,1,2,3"
|
|
bitfld.long 0x14 12.--13. " NEWDATREG7 ,New Data 7" "0,1,2,3"
|
|
bitfld.long 0x14 10.--11. " NEWDATREG6 ,New Data 6" "0,1,2,3"
|
|
bitfld.long 0x14 8.--9. " NEWDATREG5 ,New Data 5" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x14 6.--7. " NEWDATREG4 ,NEW DATA 4" "0,1,2,3"
|
|
bitfld.long 0x14 4.--5. " NEWDATREG3 ,New Data 3" "0,1,2,3"
|
|
bitfld.long 0x14 2.--3. " NEWDATREG2 ,New Data 2" "0,1,2,3"
|
|
bitfld.long 0x14 0.--1. " NEWDATREG1 ,New Data 1" "0,1,2,3"
|
|
line.long 0x18 "NEWDAT12,New Data 1-2"
|
|
bitfld.long 0x18 31. " NEWDAT[32] ,New Data Bit[32]" "Not requested,Requested"
|
|
bitfld.long 0x18 30. " [31] ,New Data Bit[31]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x18 29. " [30] ,New Data Bit[30]" "Not requested,Requested"
|
|
bitfld.long 0x18 28. " [29] ,New Data Bit[29]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x18 27. " [28] ,New Data Bit[28]" "Not requested,Requested"
|
|
bitfld.long 0x18 26. " [27] ,New Data Bit[27]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x18 25. " [26] ,New Data Bit[26]" "Not requested,Requested"
|
|
bitfld.long 0x18 24. " [25] ,New Data Bit[25]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x18 23. " [24] ,New Data Bit[24]" "Not requested,Requested"
|
|
bitfld.long 0x18 22. " [23] ,New Data Bit[23]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x18 21. " [22] ,New Data Bit[22]" "Not requested,Requested"
|
|
bitfld.long 0x18 20. " [21] ,New Data Bit[21]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x18 19. " [20] ,New Data Bit[20]" "Not requested,Requested"
|
|
bitfld.long 0x18 18. " [19] ,New Data Bit[19]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x18 17. " [18] ,New Data Bit[18]" "Not requested,Requested"
|
|
bitfld.long 0x18 16. " [17] ,New Data Bit[17]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x18 15. " [16] ,New Data Bit[16]" "Not requested,Requested"
|
|
bitfld.long 0x18 14. " [15] ,New Data Bit[15]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x18 13. " [14] ,New Data Bit[14]" "Not requested,Requested"
|
|
bitfld.long 0x18 12. " [13] ,New Data Bit[13]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x18 11. " [12] ,New Data Bit[12]" "Not requested,Requested"
|
|
bitfld.long 0x18 10. " [11] ,New Data Bit[11]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x18 9. " [10] ,New Data Bit[10]" "Not requested,Requested"
|
|
bitfld.long 0x18 8. " [9] ,New Data Bit[9]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x18 7. " [8] ,New Data Bit[8]" "Not requested,Requested"
|
|
bitfld.long 0x18 6. " [7] ,New Data Bit[7]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x18 5. " [6] ,New Data Bit[6]" "Not requested,Requested"
|
|
bitfld.long 0x18 4. " [5] ,New Data Bit[5]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x18 3. " [4] ,New Data Bit[4]" "Not requested,Requested"
|
|
bitfld.long 0x18 2. " [3] ,New Data Bit[3]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x18 1. " [2] ,New Data Bit[2]" "Not requested,Requested"
|
|
bitfld.long 0x18 0. " [1] ,New Data Bit[1]" "Not requested,Requested"
|
|
line.long 0x1C "NEWDAT34,New Data 3-4"
|
|
bitfld.long 0x1C 31. " NEWDAT[64] ,New Data Bit[64]" "Not requested,Requested"
|
|
bitfld.long 0x1C 30. " [63] ,New Data Bit[63]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x1C 29. " [62] ,New Data Bit[62]" "Not requested,Requested"
|
|
bitfld.long 0x1C 28. " [61] ,New Data Bit[61]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x1C 27. " [60] ,New Data Bit[60]" "Not requested,Requested"
|
|
bitfld.long 0x1C 26. " [59] ,New Data Bit[59]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x1C 25. " [58] ,New Data Bit[58]" "Not requested,Requested"
|
|
bitfld.long 0x1C 24. " [57] ,New Data Bit[57]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x1C 23. " [56] ,New Data Bit[56]" "Not requested,Requested"
|
|
bitfld.long 0x1C 22. " [55] ,New Data Bit[55]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x1C 21. " [54] ,New Data Bit[54]" "Not requested,Requested"
|
|
bitfld.long 0x1C 20. " [53] ,New Data Bit[53]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x1C 19. " [52] ,New Data Bit[52]" "Not requested,Requested"
|
|
bitfld.long 0x1C 18. " [51] ,New Data Bit[51]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x1C 17. " [50] ,New Data Bit[50]" "Not requested,Requested"
|
|
bitfld.long 0x1C 16. " [49] ,New Data Bit[49]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x1C 15. " [48] ,New Data Bit[48]" "Not requested,Requested"
|
|
bitfld.long 0x1C 14. " [47] ,New Data Bit[47]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x1C 13. " [46] ,New Data Bit[46]" "Not requested,Requested"
|
|
bitfld.long 0x1C 12. " [45] ,New Data Bit[45]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x1C 11. " [44] ,New Data Bit[44]" "Not requested,Requested"
|
|
bitfld.long 0x1C 10. " [43] ,New Data Bit[43]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x1C 9. " [42] ,New Data Bit[42]" "Not requested,Requested"
|
|
bitfld.long 0x1C 8. " [41] ,New Data Bit[41]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x1C 7. " [40] ,New Data Bit[40]" "Not requested,Requested"
|
|
bitfld.long 0x1C 6. " [39] ,New Data Bit[39]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x1C 5. " [38] ,New Data Bit[38]" "Not requested,Requested"
|
|
bitfld.long 0x1C 4. " [37] ,New Data Bit[37]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x1C 3. " [36] ,New Data Bit[36]" "Not requested,Requested"
|
|
bitfld.long 0x1C 2. " [35] ,New Data Bit[35]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x1C 1. " [34] ,New Data Bit[34]" "Not requested,Requested"
|
|
bitfld.long 0x1C 0. " [33] ,New Data Bit[33]" "Not requested,Requested"
|
|
line.long 0x20 "NEWDAT56,New Data 5-6"
|
|
bitfld.long 0x20 31. " NEWDAT[96] ,New Data Bit[96]" "Not requested,Requested"
|
|
bitfld.long 0x20 30. " [95] ,New Data Bit[95]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x20 29. " [94] ,New Data Bit[94]" "Not requested,Requested"
|
|
bitfld.long 0x20 28. " [93] ,New Data Bit[93]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x20 27. " [92] ,New Data Bit[92]" "Not requested,Requested"
|
|
bitfld.long 0x20 26. " [91] ,New Data Bit[91]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x20 25. " [90] ,New Data Bit[90]" "Not requested,Requested"
|
|
bitfld.long 0x20 24. " [89] ,New Data Bit[89]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x20 23. " [88] ,New Data Bit[88]" "Not requested,Requested"
|
|
bitfld.long 0x20 22. " [87] ,New Data Bit[87]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x20 21. " [86] ,New Data Bit[86]" "Not requested,Requested"
|
|
bitfld.long 0x20 20. " [85] ,New Data Bit[85]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x20 19. " [84] ,New Data Bit[84]" "Not requested,Requested"
|
|
bitfld.long 0x20 18. " [83] ,New Data Bit[83]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x20 17. " [82] ,New Data Bit[82]" "Not requested,Requested"
|
|
bitfld.long 0x20 16. " [81] ,New Data Bit[81]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x20 15. " [80] ,New Data Bit[80]" "Not requested,Requested"
|
|
bitfld.long 0x20 14. " [79] ,New Data Bit[79]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x20 13. " [78] ,New Data Bit[78]" "Not requested,Requested"
|
|
bitfld.long 0x20 12. " [77] ,New Data Bit[77]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x20 11. " [76] ,New Data Bit[76]" "Not requested,Requested"
|
|
bitfld.long 0x20 10. " [75] ,New Data Bit[75]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x20 9. " [74] ,New Data Bit[74]" "Not requested,Requested"
|
|
bitfld.long 0x20 8. " [73] ,New Data Bit[73]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x20 7. " [72] ,New Data Bit[72]" "Not requested,Requested"
|
|
bitfld.long 0x20 6. " [71] ,New Data Bit[71]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x20 5. " [70] ,New Data Bit[70]" "Not requested,Requested"
|
|
bitfld.long 0x20 4. " [69] ,New Data Bit[69]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x20 3. " [68] ,New Data Bit[68]" "Not requested,Requested"
|
|
bitfld.long 0x20 2. " [67] ,New Data Bit[67]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x20 1. " [66] ,New Data Bit[66]" "Not requested,Requested"
|
|
bitfld.long 0x20 0. " [65] ,New Data Bit[65]" "Not requested,Requested"
|
|
line.long 0x24 "NEWDAT78,New Data 7-8"
|
|
bitfld.long 0x24 31. " NEWDAT[128] ,New Data Bit[128]" "Not requested,Requested"
|
|
bitfld.long 0x24 30. " [127] ,New Data Bit[127]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x24 29. " [126] ,New Data Bit[126]" "Not requested,Requested"
|
|
bitfld.long 0x24 28. " [125] ,New Data Bit[125]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x24 27. " [124] ,New Data Bit[124]" "Not requested,Requested"
|
|
bitfld.long 0x24 26. " [123] ,New Data Bit[123]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x24 25. " [122] ,New Data Bit[122]" "Not requested,Requested"
|
|
bitfld.long 0x24 24. " [121] ,New Data Bit[121]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x24 23. " [120] ,New Data Bit[120]" "Not requested,Requested"
|
|
bitfld.long 0x24 22. " [119] ,New Data Bit[119]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x24 21. " [118] ,New Data Bit[118]" "Not requested,Requested"
|
|
bitfld.long 0x24 20. " [117] ,New Data Bit[117]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x24 19. " [116] ,New Data Bit[116]" "Not requested,Requested"
|
|
bitfld.long 0x24 18. " [115] ,New Data Bit[115]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x24 17. " [114] ,New Data Bit[114]" "Not requested,Requested"
|
|
bitfld.long 0x24 16. " [113] ,New Data Bit[113]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x24 15. " [112] ,New Data Bit[112]" "Not requested,Requested"
|
|
bitfld.long 0x24 14. " [111] ,New Data Bit[111]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x24 13. " [110] ,New Data Bit[110]" "Not requested,Requested"
|
|
bitfld.long 0x24 12. " [109] ,New Data Bit[109]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x24 11. " [108] ,New Data Bit[108]" "Not requested,Requested"
|
|
bitfld.long 0x24 10. " [107] ,New Data Bit[107]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x24 9. " [106] ,New Data Bit[106]" "Not requested,Requested"
|
|
bitfld.long 0x24 8. " [105] ,New Data Bit[105]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x24 7. " [104] ,New Data Bit[104]" "Not requested,Requested"
|
|
bitfld.long 0x24 6. " [103] ,New Data Bit[103]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x24 5. " [102] ,New Data Bit[102]" "Not requested,Requested"
|
|
bitfld.long 0x24 4. " [101] ,New Data Bit[101]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x24 3. " [100] ,New Data Bit[100]" "Not requested,Requested"
|
|
bitfld.long 0x24 2. " [99] ,New Data Bit[99]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x24 1. " [98] ,New Data Bit[98]" "Not requested,Requested"
|
|
bitfld.long 0x24 0. " [97] ,New Data Bit[97]" "Not requested,Requested"
|
|
line.long 0x28 "INTPEN,Interrupt Pending X"
|
|
bitfld.long 0x28 14.--15. " INTPENDREG[8] ,Interrupt Pending 8" "0,1,2,3"
|
|
bitfld.long 0x28 12.--13. " [7] ,Interrupt Pending 7" "0,1,2,3"
|
|
bitfld.long 0x28 10.--11. " [6] ,Interrupt Pending 6" "0,1,2,3"
|
|
bitfld.long 0x28 8.--9. " [5] ,Interrupt Pending 5" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x28 6.--7. " [4] ,Interrupt Pending 4" "0,1,2,3"
|
|
bitfld.long 0x28 4.--5. " [3] ,Interrupt Pending 3" "0,1,2,3"
|
|
bitfld.long 0x28 2.--3. " [2] ,Interrupt Pending 2" "0,1,2,3"
|
|
bitfld.long 0x28 0.--1. " [1] ,Interrupt Pending 1" "0,1,2,3"
|
|
line.long 0x2C "INTPEN12,Interrupt Pending 1-2"
|
|
bitfld.long 0x2C 31. " IntPnd[32] ,Interrupt Pending Bit[32]" "No interrupt,Interrupt"
|
|
bitfld.long 0x2C 30. " [31] ,Interrupt Pending Bit[31]" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x2C 29. " [30] ,Interrupt Pending Bit[30]" "No interrupt,Interrupt"
|
|
bitfld.long 0x2C 28. " [29] ,Interrupt Pending Bit[29]" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x2C 27. " [28] ,Interrupt Pending Bit[28]" "No interrupt,Interrupt"
|
|
bitfld.long 0x2C 26. " [27] ,Interrupt Pending Bit[27]" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x2C 25. " [26] ,Interrupt Pending Bit[26]" "No interrupt,Interrupt"
|
|
bitfld.long 0x2C 24. " [25] ,Interrupt Pending Bit[25]" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x2C 23. " [24] ,Interrupt Pending Bit[24]" "No interrupt,Interrupt"
|
|
bitfld.long 0x2C 22. " [23] ,Interrupt Pending Bit[23]" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x2C 21. " [22] ,Interrupt Pending Bit[22]" "No interrupt,Interrupt"
|
|
bitfld.long 0x2C 20. " [21] ,Interrupt Pending Bit[21]" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x2C 19. " [20] ,Interrupt Pending Bit[20]" "No interrupt,Interrupt"
|
|
bitfld.long 0x2C 18. " [19] ,Interrupt Pending Bit[19]" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x2C 17. " [18] ,Interrupt Pending Bit[18]" "No interrupt,Interrupt"
|
|
bitfld.long 0x2C 16. " [17] ,Interrupt Pending Bit[17]" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x2C 15. " [16] ,Interrupt Pending Bit[16]" "No interrupt,Interrupt"
|
|
bitfld.long 0x2C 14. " [15] ,Interrupt Pending Bit[15]" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x2C 13. " [14] ,Interrupt Pending Bit[14]" "No interrupt,Interrupt"
|
|
bitfld.long 0x2C 12. " [13] ,Interrupt Pending Bit[13]" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x2C 11. " [12] ,Interrupt Pending Bit[12]" "No interrupt,Interrupt"
|
|
bitfld.long 0x2C 10. " [11] ,Interrupt Pending Bit[11]" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x2C 9. " [10] ,Interrupt Pending Bit[10]" "No interrupt,Interrupt"
|
|
bitfld.long 0x2C 8. " [9] ,Interrupt Pending Bit[9]" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x2C 7. " [8] ,Interrupt Pending Bit[8]" "No interrupt,Interrupt"
|
|
bitfld.long 0x2C 6. " [7] ,Interrupt Pending Bit[7]" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x2C 5. " [6] ,Interrupt Pending Bit[6]" "No interrupt,Interrupt"
|
|
bitfld.long 0x2C 4. " [5] ,Interrupt Pending Bit[5]" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x2C 3. " [4] ,Interrupt Pending Bit[4]" "No interrupt,Interrupt"
|
|
bitfld.long 0x2C 2. " [3] ,Interrupt Pending Bit[3]" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x2C 1. " [2] ,Interrupt Pending Bit[2]" "No interrupt,Interrupt"
|
|
bitfld.long 0x2C 0. " [1] ,Interrupt Pending Bit[1]" "No interrupt,Interrupt"
|
|
line.long 0x30 "INTPEN34,Interrupt Pending 3-4"
|
|
bitfld.long 0x30 31. " INTPND[64] ,Interrupt Pending Bit[64]" "No interrupt,Interrupt"
|
|
bitfld.long 0x30 30. " [63] ,Interrupt Pending Bit[63]" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x30 29. " [62] ,Interrupt Pending Bit[62]" "No interrupt,Interrupt"
|
|
bitfld.long 0x30 28. " [61] ,Interrupt Pending Bit[61]" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x30 27. " [60] ,Interrupt Pending Bit[60]" "No interrupt,Interrupt"
|
|
bitfld.long 0x30 26. " [59] ,Interrupt Pending Bit[59]" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x30 25. " [58] ,Interrupt Pending Bit[58]" "No interrupt,Interrupt"
|
|
bitfld.long 0x30 24. " [57] ,Interrupt Pending Bit[57]" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x30 23. " [56] ,Interrupt Pending Bit[56]" "No interrupt,Interrupt"
|
|
bitfld.long 0x30 22. " [55] ,Interrupt Pending Bit[55]" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x30 21. " [54] ,Interrupt Pending Bit[54]" "No interrupt,Interrupt"
|
|
bitfld.long 0x30 20. " [53] ,Interrupt Pending Bit[53]" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x30 19. " [52] ,Interrupt Pending Bit[52]" "No interrupt,Interrupt"
|
|
bitfld.long 0x30 18. " [51] ,Interrupt Pending Bit[51]" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x30 17. " [50] ,Interrupt Pending Bit[50]" "No interrupt,Interrupt"
|
|
bitfld.long 0x30 16. " [49] ,Interrupt Pending Bit[49]" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x30 15. " [48] ,Interrupt Pending Bit[48]" "No interrupt,Interrupt"
|
|
bitfld.long 0x30 14. " [47] ,Interrupt Pending Bit[47]" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x30 13. " [46] ,Interrupt Pending Bit[46]" "No interrupt,Interrupt"
|
|
bitfld.long 0x30 12. " [45] ,Interrupt Pending Bit[45]" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x30 11. " [44] ,Interrupt Pending Bit[44]" "No interrupt,Interrupt"
|
|
bitfld.long 0x30 10. " [43] ,Interrupt Pending Bit[43]" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x30 9. " [42] ,Interrupt Pending Bit[42]" "No interrupt,Interrupt"
|
|
bitfld.long 0x30 8. " [41] ,Interrupt Pending Bit[41]" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x30 7. " [40] ,Interrupt Pending Bit[40]" "No interrupt,Interrupt"
|
|
bitfld.long 0x30 6. " [39] ,Interrupt Pending Bit[39]" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x30 5. " [38] ,Interrupt Pending Bit[38]" "No interrupt,Interrupt"
|
|
bitfld.long 0x30 4. " [37] ,Interrupt Pending Bit[37]" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x30 3. " [36] ,Interrupt Pending Bit[36]" "No interrupt,Interrupt"
|
|
bitfld.long 0x30 2. " [35] ,Interrupt Pending Bit[35]" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x30 1. " [34] ,Interrupt Pending Bit[34]" "No interrupt,Interrupt"
|
|
bitfld.long 0x30 0. " [33] ,Interrupt Pending Bit[33]" "No interrupt,Interrupt"
|
|
line.long 0x34 "INTPEN56,Interrupt Pending 5-6"
|
|
bitfld.long 0x34 31. " INTPND[96] ,Interrupt Pending Bit[96]" "No interrupt,Interrupt"
|
|
bitfld.long 0x34 30. " [95] ,Interrupt Pending Bit[95]" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x34 29. " [94] ,Interrupt Pending Bit[94]" "No interrupt,Interrupt"
|
|
bitfld.long 0x34 28. " [93] ,Interrupt Pending Bit[93]" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x34 27. " [92] ,Interrupt Pending Bit[92]" "No interrupt,Interrupt"
|
|
bitfld.long 0x34 26. " [91] ,Interrupt Pending Bit[91]" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x34 25. " [90] ,Interrupt Pending Bit[90]" "No interrupt,Interrupt"
|
|
bitfld.long 0x34 24. " [89] ,Interrupt Pending Bit[89]" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x34 23. " [88] ,Interrupt Pending Bit[88]" "No interrupt,Interrupt"
|
|
bitfld.long 0x34 22. " [87] ,Interrupt Pending Bit[87]" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x34 21. " [86] ,Interrupt Pending Bit[86]" "No interrupt,Interrupt"
|
|
bitfld.long 0x34 20. " [85] ,Interrupt Pending Bit[85]" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x34 19. " [84] ,Interrupt Pending Bit[84]" "No interrupt,Interrupt"
|
|
bitfld.long 0x34 18. " [83] ,Interrupt Pending Bit[83]" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x34 17. " [82] ,Interrupt Pending Bit[82]" "No interrupt,Interrupt"
|
|
bitfld.long 0x34 16. " [81] ,Interrupt Pending Bit[81]" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x34 15. " [80] ,Interrupt Pending Bit[80]" "No interrupt,Interrupt"
|
|
bitfld.long 0x34 14. " [79] ,Interrupt Pending Bit[79]" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x34 13. " [78] ,Interrupt Pending Bit[78]" "No interrupt,Interrupt"
|
|
bitfld.long 0x34 12. " [77] ,Interrupt Pending Bit[77]" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x34 11. " [76] ,Interrupt Pending Bit[76]" "No interrupt,Interrupt"
|
|
bitfld.long 0x34 10. " [75] ,Interrupt Pending Bit[75]" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x34 9. " [74] ,Interrupt Pending Bit[74]" "No interrupt,Interrupt"
|
|
bitfld.long 0x34 8. " [73] ,Interrupt Pending Bit[73]" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x34 7. " [72] ,Interrupt Pending Bit[72]" "No interrupt,Interrupt"
|
|
bitfld.long 0x34 6. " [71] ,Interrupt Pending Bit[71]" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x34 5. " [70] ,Interrupt Pending Bit[70]" "No interrupt,Interrupt"
|
|
bitfld.long 0x34 4. " [69] ,Interrupt Pending Bit[69]" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x34 3. " [68] ,Interrupt Pending Bit[68]" "No interrupt,Interrupt"
|
|
bitfld.long 0x34 2. " [67] ,Interrupt Pending Bit[67]" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x34 1. " [66] ,Interrupt Pending Bit[66]" "No interrupt,Interrupt"
|
|
bitfld.long 0x34 0. " [65] ,Interrupt Pending Bit[65]" "No interrupt,Interrupt"
|
|
line.long 0x38 "INTPEN78,Interrupt Pending 7-8"
|
|
bitfld.long 0x38 31. " INTPND[128] ,Interrupt Pending Bit[128]" "No interrupt,Interrupt"
|
|
bitfld.long 0x38 30. " [127] ,Interrupt Pending Bit[127]" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x38 29. " [126] ,Interrupt Pending Bit[126]" "No interrupt,Interrupt"
|
|
bitfld.long 0x38 28. " [125] ,Interrupt Pending Bit[125]" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x38 27. " [124] ,Interrupt Pending Bit[124]" "No interrupt,Interrupt"
|
|
bitfld.long 0x38 26. " [123] ,Interrupt Pending Bit[123]" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x38 25. " [122] ,Interrupt Pending Bit[122]" "No interrupt,Interrupt"
|
|
bitfld.long 0x38 24. " [121] ,Interrupt Pending Bit[121]" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x38 23. " [120] ,Interrupt Pending Bit[120]" "No interrupt,Interrupt"
|
|
bitfld.long 0x38 22. " [119] ,Interrupt Pending Bit[119]" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x38 21. " [118] ,Interrupt Pending Bit[118]" "No interrupt,Interrupt"
|
|
bitfld.long 0x38 20. " [117] ,Interrupt Pending Bit[117]" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x38 19. " [116] ,Interrupt Pending Bit[116]" "No interrupt,Interrupt"
|
|
bitfld.long 0x38 18. " [115] ,Interrupt Pending Bit[115]" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x38 17. " [114] ,Interrupt Pending Bit[114]" "No interrupt,Interrupt"
|
|
bitfld.long 0x38 16. " [113] ,Interrupt Pending Bit[113]" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x38 15. " [112] ,Interrupt Pending Bit[112]" "No interrupt,Interrupt"
|
|
bitfld.long 0x38 14. " [111] ,Interrupt Pending Bit[111]" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x38 13. " [110] ,Interrupt Pending Bit[110]" "No interrupt,Interrupt"
|
|
bitfld.long 0x38 12. " [109] ,Interrupt Pending Bit[109]" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x38 11. " [108] ,Interrupt Pending Bit[108]" "No interrupt,Interrupt"
|
|
bitfld.long 0x38 10. " [107] ,Interrupt Pending Bit[107]" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x38 9. " [106] ,Interrupt Pending Bit[106]" "No interrupt,Interrupt"
|
|
bitfld.long 0x38 8. " [105] ,Interrupt Pending Bit[105]" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x38 7. " [104] ,Interrupt Pending Bit[104]" "No interrupt,Interrupt"
|
|
bitfld.long 0x38 6. " [103] ,Interrupt Pending Bit[103]" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x38 5. " [102] ,Interrupt Pending Bit[102]" "No interrupt,Interrupt"
|
|
bitfld.long 0x38 4. " [101] ,Interrupt Pending Bit[101]" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x38 3. " [100] ,Interrupt Pending Bit[100]" "No interrupt,Interrupt"
|
|
bitfld.long 0x38 2. " [99] ,Interrupt Pending Bit[99]" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x38 1. " [98] ,Interrupt Pending Bit[98]" "No interrupt,Interrupt"
|
|
bitfld.long 0x38 0. " [97] ,Interrupt Pending Bit[97]" "No interrupt,Interrupt"
|
|
line.long 0x3C "MVAL,Message Valid X"
|
|
bitfld.long 0x3C 14.--15. " MSGVALREG8 ,Message Valid Register 8" "0,1,2,3"
|
|
bitfld.long 0x3C 12.--13. " [7] ,Message Valid Register 7" "0,1,2,3"
|
|
bitfld.long 0x3C 10.--11. " [6] ,Message Valid Register 6" "0,1,2,3"
|
|
bitfld.long 0x3C 8.--9. " [5] ,Message Valid Register 5" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x3C 6.--7. " [4] ,Message Valid Register 4" "0,1,2,3"
|
|
bitfld.long 0x3C 4.--5. " [3] ,Message Valid Register 3" "0,1,2,3"
|
|
bitfld.long 0x3C 2.--3. " [2] ,Message Valid Register 2" "0,1,2,3"
|
|
bitfld.long 0x3C 0.--1. " [1] ,Message Valid Register 1" "0,1,2,3"
|
|
line.long 0x40 "MVAL12,Message Valid 1-2"
|
|
bitfld.long 0x40 31. " MSGVAL[32] ,Message Valid Bit[32]" "Ignored,Configured"
|
|
bitfld.long 0x40 30. " [31] ,Message Valid Bit[31]" "Ignored,Configured"
|
|
newline
|
|
bitfld.long 0x40 29. " [30] ,Message Valid Bit[30]" "Ignored,Configured"
|
|
bitfld.long 0x40 28. " [29] ,Message Valid Bit[29]" "Ignored,Configured"
|
|
newline
|
|
bitfld.long 0x40 27. " [28] ,Message Valid Bit[28]" "Ignored,Configured"
|
|
bitfld.long 0x40 26. " [27] ,Message Valid Bit[27]" "Ignored,Configured"
|
|
newline
|
|
bitfld.long 0x40 25. " [26] ,Message Valid Bit[26]" "Ignored,Configured"
|
|
bitfld.long 0x40 24. " [25] ,Message Valid Bit[25]" "Ignored,Configured"
|
|
newline
|
|
bitfld.long 0x40 23. " [24] ,Message Valid Bit[24]" "Ignored,Configured"
|
|
bitfld.long 0x40 22. " [23] ,Message Valid Bit[23]" "Ignored,Configured"
|
|
newline
|
|
bitfld.long 0x40 21. " [22] ,Message Valid Bit[22]" "Ignored,Configured"
|
|
bitfld.long 0x40 20. " [21] ,Message Valid Bit[21]" "Ignored,Configured"
|
|
newline
|
|
bitfld.long 0x40 19. " [20] ,Message Valid Bit[20]" "Ignored,Configured"
|
|
bitfld.long 0x40 18. " [19] ,Message Valid Bit[19]" "Ignored,Configured"
|
|
newline
|
|
bitfld.long 0x40 17. " [18] ,Message Valid Bit[18]" "Ignored,Configured"
|
|
bitfld.long 0x40 16. " [17] ,Message Valid Bit[17]" "Ignored,Configured"
|
|
newline
|
|
bitfld.long 0x40 15. " [16] ,Message Valid Bit[16]" "Ignored,Configured"
|
|
bitfld.long 0x40 14. " [15] ,Message Valid Bit[15]" "Ignored,Configured"
|
|
newline
|
|
bitfld.long 0x40 13. " [14] ,Message Valid Bit[14]" "Ignored,Configured"
|
|
bitfld.long 0x40 12. " [13] ,Message Valid Bit[13]" "Ignored,Configured"
|
|
newline
|
|
bitfld.long 0x40 11. " [12] ,Message Valid Bit[12]" "Ignored,Configured"
|
|
bitfld.long 0x40 10. " [11] ,Message Valid Bit[11]" "Ignored,Configured"
|
|
newline
|
|
bitfld.long 0x40 9. " [10] ,Message Valid Bit[10]" "Ignored,Configured"
|
|
bitfld.long 0x40 8. " [9] ,Message Valid Bit[9]" "Ignored,Configured"
|
|
newline
|
|
bitfld.long 0x40 7. " [8] ,Message Valid Bit[8]" "Ignored,Configured"
|
|
bitfld.long 0x40 6. " [7] ,Message Valid Bit[7]" "Ignored,Configured"
|
|
newline
|
|
bitfld.long 0x40 5. " [6] ,Message Valid Bit[6]" "Ignored,Configured"
|
|
bitfld.long 0x40 4. " [5] ,Message Valid Bit[5]" "Ignored,Configured"
|
|
newline
|
|
bitfld.long 0x40 3. " [4] ,Message Valid Bit[4]" "Ignored,Configured"
|
|
bitfld.long 0x40 2. " [3] ,Message Valid Bit[3]" "Ignored,Configured"
|
|
newline
|
|
bitfld.long 0x40 1. " [2] ,Message Valid Bit[2]" "Ignored,Configured"
|
|
bitfld.long 0x40 0. " [1] ,Message Valid Bit[1]" "Ignored,Configured"
|
|
line.long 0x44 "MVAL34,Message Valid 3-4"
|
|
bitfld.long 0x44 31. " MSGVAl[64] ,Message Valid Bit[64]" "Ignored,Configured"
|
|
bitfld.long 0x44 30. " [63] ,Message Valid Bit[63]" "Ignored,Configured"
|
|
newline
|
|
bitfld.long 0x44 29. " [62] ,Message Valid Bit[62]" "Ignored,Configured"
|
|
bitfld.long 0x44 28. " [61] ,Message Valid Bit[61]" "Ignored,Configured"
|
|
newline
|
|
bitfld.long 0x44 27. " [60] ,Message Valid Bit[60]" "Ignored,Configured"
|
|
bitfld.long 0x44 26. " [59] ,Message Valid Bit[59]" "Ignored,Configured"
|
|
newline
|
|
bitfld.long 0x44 25. " [58] ,Message Valid Bit[58]" "Ignored,Configured"
|
|
bitfld.long 0x44 24. " [57] ,Message Valid Bit[57]" "Ignored,Configured"
|
|
newline
|
|
bitfld.long 0x44 23. " [56] ,Message Valid Bit[56]" "Ignored,Configured"
|
|
bitfld.long 0x44 22. " [55] ,Message Valid Bit[55]" "Ignored,Configured"
|
|
newline
|
|
bitfld.long 0x44 21. " [54] ,Message Valid Bit[54]" "Ignored,Configured"
|
|
bitfld.long 0x44 20. " [53] ,Message Valid Bit[53]" "Ignored,Configured"
|
|
newline
|
|
bitfld.long 0x44 19. " [52] ,Message Valid Bit[52]" "Ignored,Configured"
|
|
bitfld.long 0x44 18. " [51] ,Message Valid Bit[51]" "Ignored,Configured"
|
|
newline
|
|
bitfld.long 0x44 17. " [50] ,Message Valid Bit[50]" "Ignored,Configured"
|
|
bitfld.long 0x44 16. " [49] ,Message Valid Bit[49]" "Ignored,Configured"
|
|
newline
|
|
bitfld.long 0x44 15. " [48] ,Message Valid Bit[48]" "Ignored,Configured"
|
|
bitfld.long 0x44 14. " [47] ,Message Valid Bit[47]" "Ignored,Configured"
|
|
newline
|
|
bitfld.long 0x44 13. " [46] ,Message Valid Bit[46]" "Ignored,Configured"
|
|
bitfld.long 0x44 12. " [45] ,Message Valid Bit[45]" "Ignored,Configured"
|
|
newline
|
|
bitfld.long 0x44 11. " [44] ,Message Valid Bit[44]" "Ignored,Configured"
|
|
bitfld.long 0x44 10. " [43] ,Message Valid Bit[43]" "Ignored,Configured"
|
|
newline
|
|
bitfld.long 0x44 9. " [42] ,Message Valid Bit[42]" "Ignored,Configured"
|
|
bitfld.long 0x44 8. " [41] ,Message Valid Bit[41]" "Ignored,Configured"
|
|
newline
|
|
bitfld.long 0x44 7. " [40] ,Message Valid Bit[40]" "Ignored,Configured"
|
|
bitfld.long 0x44 6. " [39] ,Message Valid Bit[39]" "Ignored,Configured"
|
|
newline
|
|
bitfld.long 0x44 5. " [38] ,Message Valid Bit[38]" "Ignored,Configured"
|
|
bitfld.long 0x44 4. " [37] ,Message Valid Bit[37]" "Ignored,Configured"
|
|
newline
|
|
bitfld.long 0x44 3. " [36] ,Message Valid Bit[36]" "Ignored,Configured"
|
|
bitfld.long 0x44 2. " [35] ,Message Valid Bit[35]" "Ignored,Configured"
|
|
newline
|
|
bitfld.long 0x44 1. " [34] ,Message Valid Bit[34]" "Ignored,Configured"
|
|
bitfld.long 0x44 0. " [33] ,Message Valid Bit[33]" "Ignored,Configured"
|
|
line.long 0x48 "MVAL56,Message Valid 5-6"
|
|
bitfld.long 0x48 31. " MSGVAl[96] ,Message Valid Bit[96]" "Ignored,Configured"
|
|
bitfld.long 0x48 30. " [95] ,Message Valid Bit[95]" "Ignored,Configured"
|
|
newline
|
|
bitfld.long 0x48 29. " [94] ,Message Valid Bit[94]" "Ignored,Configured"
|
|
bitfld.long 0x48 28. " [93] ,Message Valid Bit[93]" "Ignored,Configured"
|
|
newline
|
|
bitfld.long 0x48 27. " [92] ,Message Valid Bit[92]" "Ignored,Configured"
|
|
bitfld.long 0x48 26. " [91] ,Message Valid Bit[91]" "Ignored,Configured"
|
|
newline
|
|
bitfld.long 0x48 25. " [90] ,Message Valid Bit[90]" "Ignored,Configured"
|
|
bitfld.long 0x48 24. " [89] ,Message Valid Bit[89]" "Ignored,Configured"
|
|
newline
|
|
bitfld.long 0x48 23. " [88] ,Message Valid Bit[88]" "Ignored,Configured"
|
|
bitfld.long 0x48 22. " [87] ,Message Valid Bit[87]" "Ignored,Configured"
|
|
newline
|
|
bitfld.long 0x48 21. " [86] ,Message Valid Bit[86]" "Ignored,Configured"
|
|
bitfld.long 0x48 20. " [85] ,Message Valid Bit[85]" "Ignored,Configured"
|
|
newline
|
|
bitfld.long 0x48 19. " [84] ,Message Valid Bit[84]" "Ignored,Configured"
|
|
bitfld.long 0x48 18. " [83] ,Message Valid Bit[83]" "Ignored,Configured"
|
|
newline
|
|
bitfld.long 0x48 17. " [82] ,Message Valid Bit[82]" "Ignored,Configured"
|
|
bitfld.long 0x48 16. " [81] ,Message Valid Bit[81]" "Ignored,Configured"
|
|
newline
|
|
bitfld.long 0x48 15. " [80] ,Message Valid Bit[80]" "Ignored,Configured"
|
|
bitfld.long 0x48 14. " [79] ,Message Valid Bit[79]" "Ignored,Configured"
|
|
newline
|
|
bitfld.long 0x48 13. " [78] ,Message Valid Bit[78]" "Ignored,Configured"
|
|
bitfld.long 0x48 12. " [77] ,Message Valid Bit[77]" "Ignored,Configured"
|
|
newline
|
|
bitfld.long 0x48 11. " [76] ,Message Valid Bit[76]" "Ignored,Configured"
|
|
bitfld.long 0x48 10. " [75] ,Message Valid Bit[75]" "Ignored,Configured"
|
|
newline
|
|
bitfld.long 0x48 9. " [74] ,Message Valid Bit[74]" "Ignored,Configured"
|
|
bitfld.long 0x48 8. " [73] ,Message Valid Bit[73]" "Ignored,Configured"
|
|
newline
|
|
bitfld.long 0x48 7. " [72] ,Message Valid Bit[72]" "Ignored,Configured"
|
|
bitfld.long 0x48 6. " [71] ,Message Valid Bit[71]" "Ignored,Configured"
|
|
newline
|
|
bitfld.long 0x48 5. " [70] ,Message Valid Bit[70]" "Ignored,Configured"
|
|
bitfld.long 0x48 4. " [69] ,Message Valid Bit[69]" "Ignored,Configured"
|
|
newline
|
|
bitfld.long 0x48 3. " [68] ,Message Valid Bit[68]" "Ignored,Configured"
|
|
bitfld.long 0x48 2. " [67] ,Message Valid Bit[67]" "Ignored,Configured"
|
|
newline
|
|
bitfld.long 0x48 1. " [66] ,Message Valid Bit[66]" "Ignored,Configured"
|
|
bitfld.long 0x48 0. " [65] ,Message Valid Bit[65]" "Ignored,Configured"
|
|
line.long 0x4C "MVAL78,Message Valid 7-8"
|
|
bitfld.long 0x4C 31. " MSGVAl[128] ,Message Valid Bit[128]" "Ignored,Configured"
|
|
bitfld.long 0x4C 30. " [127] ,Message Valid Bit[127]" "Ignored,Configured"
|
|
newline
|
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bitfld.long 0x4C 29. " [126] ,Message Valid Bit[126]" "Ignored,Configured"
|
|
bitfld.long 0x4C 28. " [125] ,Message Valid Bit[125]" "Ignored,Configured"
|
|
newline
|
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bitfld.long 0x4C 27. " [124] ,Message Valid Bit[124]" "Ignored,Configured"
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bitfld.long 0x4C 26. " [123] ,Message Valid Bit[123]" "Ignored,Configured"
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newline
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bitfld.long 0x4C 25. " [122] ,Message Valid Bit[122]" "Ignored,Configured"
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bitfld.long 0x4C 24. " [121] ,Message Valid Bit[121]" "Ignored,Configured"
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newline
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bitfld.long 0x4C 23. " [120] ,Message Valid Bit[120]" "Ignored,Configured"
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bitfld.long 0x4C 22. " [119] ,Message Valid Bit[119]" "Ignored,Configured"
|
|
newline
|
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bitfld.long 0x4C 21. " [118] ,Message Valid Bit[118]" "Ignored,Configured"
|
|
bitfld.long 0x4C 20. " [117] ,Message Valid Bit[117]" "Ignored,Configured"
|
|
newline
|
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bitfld.long 0x4C 19. " [116] ,Message Valid Bit[116]" "Ignored,Configured"
|
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bitfld.long 0x4C 18. " [115] ,Message Valid Bit[115]" "Ignored,Configured"
|
|
newline
|
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bitfld.long 0x4C 17. " [114] ,Message Valid Bit[114]" "Ignored,Configured"
|
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bitfld.long 0x4C 16. " [113] ,Message Valid Bit[113]" "Ignored,Configured"
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newline
|
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bitfld.long 0x4C 15. " [112] ,Message Valid Bit[112]" "Ignored,Configured"
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bitfld.long 0x4C 14. " [111] ,Message Valid Bit[111]" "Ignored,Configured"
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newline
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bitfld.long 0x4C 13. " [110] ,Message Valid Bit[110]" "Ignored,Configured"
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bitfld.long 0x4C 12. " [109] ,Message Valid Bit[109]" "Ignored,Configured"
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newline
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bitfld.long 0x4C 11. " [108] ,Message Valid Bit[108]" "Ignored,Configured"
|
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bitfld.long 0x4C 10. " [107] ,Message Valid Bit[107]" "Ignored,Configured"
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newline
|
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bitfld.long 0x4C 9. " [106] ,Message Valid Bit[106]" "Ignored,Configured"
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bitfld.long 0x4C 8. " [105] ,Message Valid Bit[105]" "Ignored,Configured"
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newline
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bitfld.long 0x4C 7. " [104] ,Message Valid Bit[104]" "Ignored,Configured"
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bitfld.long 0x4C 6. " [103] ,Message Valid Bit[103]" "Ignored,Configured"
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newline
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bitfld.long 0x4C 5. " [102] ,Message Valid Bit[102]" "Ignored,Configured"
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bitfld.long 0x4C 4. " [101] ,Message Valid Bit[101]" "Ignored,Configured"
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newline
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bitfld.long 0x4C 3. " [100] ,Message Valid Bit[100]" "Ignored,Configured"
|
|
bitfld.long 0x4C 2. " [99] ,Message Valid Bit[99]" "Ignored,Configured"
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newline
|
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bitfld.long 0x4C 1. " [98] ,Message Valid Bit[98]" "Ignored,Configured"
|
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bitfld.long 0x4C 0. " [97] ,Message Valid Bit[97]" "Ignored,Configured"
|
|
group.long 0xD8++0x0F
|
|
line.long 0x00 "INTPMX12,Interrupt Multiplexer 1-2"
|
|
bitfld.long 0x00 31. " INTPNDMUX[32] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[32]" "DCAN0INT,DCAN1INT"
|
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bitfld.long 0x00 30. " [31] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[31]" "DCAN0INT,DCAN1INT"
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newline
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bitfld.long 0x00 29. " [30] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[30]" "DCAN0INT,DCAN1INT"
|
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bitfld.long 0x00 28. " [29] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[29]" "DCAN0INT,DCAN1INT"
|
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newline
|
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bitfld.long 0x00 27. " [28] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[28]" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x00 26. " [27] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[27]" "DCAN0INT,DCAN1INT"
|
|
newline
|
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bitfld.long 0x00 25. " [26] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[26]" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x00 24. " [25] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[25]" "DCAN0INT,DCAN1INT"
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newline
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bitfld.long 0x00 23. " [24] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[24]" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x00 22. " [23] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[23]" "DCAN0INT,DCAN1INT"
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newline
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bitfld.long 0x00 21. " [22] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[22]" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x00 20. " [21] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[21]" "DCAN0INT,DCAN1INT"
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|
newline
|
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bitfld.long 0x00 19. " [20] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[20]" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x00 18. " [19] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[19]" "DCAN0INT,DCAN1INT"
|
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newline
|
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bitfld.long 0x00 17. " [18] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[18]" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x00 16. " [17] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[17]" "DCAN0INT,DCAN1INT"
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newline
|
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bitfld.long 0x00 15. " [16] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[16]" "DCAN0INT,DCAN1INT"
|
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bitfld.long 0x00 14. " [15] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[15]" "DCAN0INT,DCAN1INT"
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newline
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bitfld.long 0x00 13. " [14] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[14]" "DCAN0INT,DCAN1INT"
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|
bitfld.long 0x00 12. " [13] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[13]" "DCAN0INT,DCAN1INT"
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newline
|
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bitfld.long 0x00 11. " [12] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[12]" "DCAN0INT,DCAN1INT"
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|
bitfld.long 0x00 10. " [11] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[11]" "DCAN0INT,DCAN1INT"
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newline
|
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bitfld.long 0x00 9. " [10] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[10]" "DCAN0INT,DCAN1INT"
|
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bitfld.long 0x00 8. " [9] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[9]" "DCAN0INT,DCAN1INT"
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newline
|
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bitfld.long 0x00 7. " [8] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[8]" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x00 6. " [7] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[7]" "DCAN0INT,DCAN1INT"
|
|
newline
|
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bitfld.long 0x00 5. " [6] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[6]" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x00 4. " [5] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[5]" "DCAN0INT,DCAN1INT"
|
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newline
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bitfld.long 0x00 3. " [4] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[4]" "DCAN0INT,DCAN1INT"
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bitfld.long 0x00 2. " [3] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[3]" "DCAN0INT,DCAN1INT"
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newline
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bitfld.long 0x00 1. " [2] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[2]" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x00 0. " [1] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[1]" "DCAN0INT,DCAN1INT"
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line.long 0x04 "INTPMX34,Interrupt Multiplexer 3-4"
|
|
bitfld.long 0x04 31. " INTPNDMUX[64] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[64]" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x04 30. " [63] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[63]" "DCAN0INT,DCAN1INT"
|
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newline
|
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bitfld.long 0x04 29. " [62] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[62]" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x04 28. " [61] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[61]" "DCAN0INT,DCAN1INT"
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newline
|
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bitfld.long 0x04 27. " [60] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[60]" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x04 26. " [59] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[59]" "DCAN0INT,DCAN1INT"
|
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newline
|
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bitfld.long 0x04 25. " [58] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[58]" "DCAN0INT,DCAN1INT"
|
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bitfld.long 0x04 24. " [57] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[57]" "DCAN0INT,DCAN1INT"
|
|
newline
|
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bitfld.long 0x04 23. " [56] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[56]" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x04 22. " [55] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[55]" "DCAN0INT,DCAN1INT"
|
|
newline
|
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bitfld.long 0x04 21. " [54] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[54]" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x04 20. " [53] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[53]" "DCAN0INT,DCAN1INT"
|
|
newline
|
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bitfld.long 0x04 19. " [52] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[52]" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x04 18. " [51] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[51]" "DCAN0INT,DCAN1INT"
|
|
newline
|
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bitfld.long 0x04 17. " [50] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[50]" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x04 16. " [49] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[49]" "DCAN0INT,DCAN1INT"
|
|
newline
|
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bitfld.long 0x04 15. " [48] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[48]" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x04 14. " [47] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[47]" "DCAN0INT,DCAN1INT"
|
|
newline
|
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bitfld.long 0x04 13. " [46] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[46]" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x04 12. " [45] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[45]" "DCAN0INT,DCAN1INT"
|
|
newline
|
|
bitfld.long 0x04 11. " [44] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[44]" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x04 10. " [43] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[43]" "DCAN0INT,DCAN1INT"
|
|
newline
|
|
bitfld.long 0x04 9. " [42] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[42]" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x04 8. " [41] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[41]" "DCAN0INT,DCAN1INT"
|
|
newline
|
|
bitfld.long 0x04 7. " [40] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[40]" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x04 6. " [39] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[39]" "DCAN0INT,DCAN1INT"
|
|
newline
|
|
bitfld.long 0x04 5. " [38] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[38]" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x04 4. " [37] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[37]" "DCAN0INT,DCAN1INT"
|
|
newline
|
|
bitfld.long 0x04 3. " [36] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[36]" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x04 2. " [35] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[35]" "DCAN0INT,DCAN1INT"
|
|
newline
|
|
bitfld.long 0x04 1. " [34] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[34]" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x04 0. " [33] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[33]" "DCAN0INT,DCAN1INT"
|
|
line.long 0x08 "INTPMX56,Interrupt Multiplexer 5-6"
|
|
bitfld.long 0x08 31. " INTPNDMUX[96] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[96]" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x08 30. " [95] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[95]" "DCAN0INT,DCAN1INT"
|
|
newline
|
|
bitfld.long 0x08 29. " [94] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[94]" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x08 28. " [93] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[93]" "DCAN0INT,DCAN1INT"
|
|
newline
|
|
bitfld.long 0x08 27. " [92] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[92]" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x08 26. " [91] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[91]" "DCAN0INT,DCAN1INT"
|
|
newline
|
|
bitfld.long 0x08 25. " [90] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[90]" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x08 24. " [89] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[89]" "DCAN0INT,DCAN1INT"
|
|
newline
|
|
bitfld.long 0x08 23. " [88] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[88]" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x08 22. " [87] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[87]" "DCAN0INT,DCAN1INT"
|
|
newline
|
|
bitfld.long 0x08 21. " [86] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[86]" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x08 20. " [85] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[85]" "DCAN0INT,DCAN1INT"
|
|
newline
|
|
bitfld.long 0x08 19. " [84] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[84]" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x08 18. " [83] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[83]" "DCAN0INT,DCAN1INT"
|
|
newline
|
|
bitfld.long 0x08 17. " [82] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[82]" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x08 16. " [81] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[81]" "DCAN0INT,DCAN1INT"
|
|
newline
|
|
bitfld.long 0x08 15. " [80] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[80]" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x08 14. " [79] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[79]" "DCAN0INT,DCAN1INT"
|
|
newline
|
|
bitfld.long 0x08 13. " [78] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[78]" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x08 12. " [77] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[77]" "DCAN0INT,DCAN1INT"
|
|
newline
|
|
bitfld.long 0x08 11. " [76] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[76]" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x08 10. " [75] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[75]" "DCAN0INT,DCAN1INT"
|
|
newline
|
|
bitfld.long 0x08 9. " [74] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[74]" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x08 8. " [73] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[73]" "DCAN0INT,DCAN1INT"
|
|
newline
|
|
bitfld.long 0x08 7. " [72] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[72]" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x08 6. " [71] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[71]" "DCAN0INT,DCAN1INT"
|
|
newline
|
|
bitfld.long 0x08 5. " [70] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[70]" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x08 4. " [69] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[69]" "DCAN0INT,DCAN1INT"
|
|
newline
|
|
bitfld.long 0x08 3. " [68] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[68]" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x08 2. " [67] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[67]" "DCAN0INT,DCAN1INT"
|
|
newline
|
|
bitfld.long 0x08 1. " [66] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[66]" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x08 0. " [65] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[65]" "DCAN0INT,DCAN1INT"
|
|
line.long 0x0C "INTPMX78,Interrupt Multiplexer 7-8"
|
|
bitfld.long 0x0C 31. " INTPNDMUX[128] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[128]" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x0C 30. " [127] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[127]" "DCAN0INT,DCAN1INT"
|
|
newline
|
|
bitfld.long 0x0C 29. " [126] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[126]" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x0C 28. " [125] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[125]" "DCAN0INT,DCAN1INT"
|
|
newline
|
|
bitfld.long 0x0C 27. " [124] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[124]" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x0C 26. " [123] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[123]" "DCAN0INT,DCAN1INT"
|
|
newline
|
|
bitfld.long 0x0C 25. " [122] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[122]" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x0C 24. " [121] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[121]" "DCAN0INT,DCAN1INT"
|
|
newline
|
|
bitfld.long 0x0C 23. " [120] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[120]" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x0C 22. " [119] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[119]" "DCAN0INT,DCAN1INT"
|
|
newline
|
|
bitfld.long 0x0C 21. " [118] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[118]" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x0C 20. " [117] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[117]" "DCAN0INT,DCAN1INT"
|
|
newline
|
|
bitfld.long 0x0C 19. " [116] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[116]" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x0C 18. " [115] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[115]" "DCAN0INT,DCAN1INT"
|
|
newline
|
|
bitfld.long 0x0C 17. " [114] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[114]" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x0C 16. " [113] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[113]" "DCAN0INT,DCAN1INT"
|
|
newline
|
|
bitfld.long 0x0C 15. " [112] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[112]" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x0C 14. " [111] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[111]" "DCAN0INT,DCAN1INT"
|
|
newline
|
|
bitfld.long 0x0C 13. " [110] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[110]" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x0C 12. " [109] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[109]" "DCAN0INT,DCAN1INT"
|
|
newline
|
|
bitfld.long 0x0C 11. " [108] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[108]" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x0C 10. " [107] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[107]" "DCAN0INT,DCAN1INT"
|
|
newline
|
|
bitfld.long 0x0C 9. " [106] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[106]" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x0C 8. " [105] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[105]" "DCAN0INT,DCAN1INT"
|
|
newline
|
|
bitfld.long 0x0C 7. " [104] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[104]" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x0C 6. " [103] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[103]" "DCAN0INT,DCAN1INT"
|
|
newline
|
|
bitfld.long 0x0C 5. " [102] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[102]" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x0C 4. " [101] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[101]" "DCAN0INT,DCAN1INT"
|
|
newline
|
|
bitfld.long 0x0C 3. " [100] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[100]" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x0C 2. " [99] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[99]" "DCAN0INT,DCAN1INT"
|
|
newline
|
|
bitfld.long 0x0C 1. " [98] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[98]" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x0C 0. " [97] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[97]" "DCAN0INT,DCAN1INT"
|
|
group.long 0x100++0x3 "IF1"
|
|
line.long 0x00 "IF1COM,IF1 Command Mask / Command Request Register"
|
|
bitfld.long 0x00 23. " WR/RD ,Write / Read direction" "Read,Write"
|
|
newline
|
|
bitfld.long 0x00 22. " MASK ,Access Mask Bits" "Unchanged,Identifier Mask+MDir+MXtd"
|
|
newline
|
|
bitfld.long 0x00 21. " ARB ,Access Arbitration Bits" "Unchanged,Identifier+Dir+Xtd+MSGVAl"
|
|
newline
|
|
bitfld.long 0x00 20. " CONTROL ,Access Control Bits" "Unchanged,Control bits"
|
|
bitfld.long 0x00 19. " CLRINTPND ,Clear Interrupt Pending Bit" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 18. " TXRQST/NEWDAT ,Access Transmission Request Bit" "Not requested,Requested"
|
|
bitfld.long 0x00 17. " DATA_A ,Access Data Bytes 0-3" "Unchanged,Data bytes 0-3"
|
|
newline
|
|
bitfld.long 0x00 16. " DATA_B ,Access Data Bytes 4-7" "Unchanged,Data bytes 4-7"
|
|
bitfld.long 0x00 15. " BUSY ,Busy Flag" "Not busy,Busy"
|
|
newline
|
|
sif (!cpuis("TMS570LS0332")&&!cpuis("TMS570LS0432"))
|
|
bitfld.long 0x00 14. " DMAACTIVE ,Activation of DMA Feature for Subsequent Internal IF1 Update" "No active,Active"
|
|
newline
|
|
endif
|
|
hexmask.long.byte 0x00 0.--7. 1. " MESSAGE_NUMBER ,Message Number"
|
|
sif cpuis("TMS570LS0232")||cpuis("TMS570LS0714*")||cpuis("TMS570LS0914*")||cpuis("TMS570LS3137-EP")
|
|
if (((per.l.be(((ad:0xFFF7DE00+0x100+0x08))))&0x40000000)==0x0)
|
|
group.long (0x100+0x04)++0x07
|
|
line.long 0x0 "IF1MASK,IF1 Mask Register"
|
|
bitfld.long 0x00 31. " MXTD ,Mask Extended Identifier" "No effect,Filtering"
|
|
bitfld.long 0x00 30. " MDIR ,Mask Message Direction" "No effect,Filtering"
|
|
newline
|
|
bitfld.long 0x00 28. " ID ,Message Identifier bit[10]" "0,1"
|
|
bitfld.long 0x00 27. ",Message Identifier bit[9]" "0,1"
|
|
bitfld.long 0x00 26. ",Message Identifier bit[8]" "0,1"
|
|
bitfld.long 0x00 25. ",Message Identifier bit[7]" "0,1"
|
|
bitfld.long 0x00 24. ",Message Identifier bit[6]" "0,1"
|
|
bitfld.long 0x00 23. ",Message Identifier bit[5]" "0,1"
|
|
bitfld.long 0x00 22. ",Message Identifier bit[4]" "0,1"
|
|
bitfld.long 0x00 21. ",Message Identifier bit[3]" "0,1"
|
|
bitfld.long 0x00 20. ",Message Identifier bit[2]" "0,1"
|
|
bitfld.long 0x00 19. ",Message Identifier bit[1]" "0,1"
|
|
bitfld.long 0x00 18. ",Message Identifier bit[0]" "0,1"
|
|
line.long 0x04 "IF1ARB,IF1 Arbitration Register"
|
|
bitfld.long 0x04 31. " MSGVAL ,Message Valid" "Ignore,Configure"
|
|
bitfld.long 0x04 30. " XTD ,Extended Identifier" "11-bit,29-bit"
|
|
bitfld.long 0x04 29. " DIR ,Message Direction" "Receive,Transmit"
|
|
hexmask.long.word 0x04 18.--28. 1. " ID ,Message Identifier"
|
|
else
|
|
group.long (0x100+0x04)++0x07
|
|
line.long 0x00 "IF1MASK,IF1 Mask Register"
|
|
bitfld.long 0x00 31. " MXTD ,Mask Extended Identifier" "No effect,Filtering"
|
|
bitfld.long 0x00 30. " MDIR ,Mask Message Direction" "No effect,Filtering"
|
|
newline
|
|
bitfld.long 0x00 28. " ID ,Message Identifier bit[28]" "0,1"
|
|
bitfld.long 0x00 27. ",Message Identifier bit[27]" "0,1"
|
|
bitfld.long 0x00 26. ",Message Identifier bit[26]" "0,1"
|
|
bitfld.long 0x00 25. ",Message Identifier bit[25]" "0,1"
|
|
bitfld.long 0x00 24. ",Message Identifier bit[24]" "0,1"
|
|
bitfld.long 0x00 23. ",Message Identifier bit[23]" "0,1"
|
|
bitfld.long 0x00 22. ",Message Identifier bit[22]" "0,1"
|
|
bitfld.long 0x00 21. ",Message Identifier bit[21]" "0,1"
|
|
bitfld.long 0x00 20. ",Message Identifier bit[20]" "0,1"
|
|
bitfld.long 0x00 19. ",Message Identifier bit[19]" "0,1"
|
|
bitfld.long 0x00 18. ",Message Identifier bit[18]" "0,1"
|
|
bitfld.long 0x00 17. ",Message Identifier bit[17]" "0,1"
|
|
bitfld.long 0x00 16. ",Message Identifier bit[16]" "0,1"
|
|
bitfld.long 0x00 15. ",Message Identifier bit[15]" "0,1"
|
|
bitfld.long 0x00 14. ",Message Identifier bit[14]" "0,1"
|
|
bitfld.long 0x00 13. ",Message Identifier bit[13]" "0,1"
|
|
bitfld.long 0x00 12. ",Message Identifier bit[12]" "0,1"
|
|
bitfld.long 0x00 11. ",Message Identifier bit[11]" "0,1"
|
|
bitfld.long 0x00 10. ",Message Identifier bit[10]" "0,1"
|
|
bitfld.long 0x00 9. ",Message Identifier bit[9]" "0,1"
|
|
bitfld.long 0x00 8. ",Message Identifier bit[8]" "0,1"
|
|
bitfld.long 0x00 7. ",Message Identifier bit[7]" "0,1"
|
|
bitfld.long 0x00 6. ",Message Identifier bit[6]" "0,1"
|
|
bitfld.long 0x00 5. ",Message Identifier bit[5]" "0,1"
|
|
bitfld.long 0x00 4. ",Message Identifier bit[4]" "0,1"
|
|
bitfld.long 0x00 3. ",Message Identifier bit[3]" "0,1"
|
|
bitfld.long 0x00 2. ",Message Identifier bit[2]" "0,1"
|
|
bitfld.long 0x00 1. ",Message Identifier bit[1]" "0,1"
|
|
bitfld.long 0x00 0. ",Message Identifier bit[0]" "0,1"
|
|
line.long 0x04 "IF1ARB,IF1 Arbitation Register"
|
|
bitfld.long 0x04 31. " MSGVAL ,Message Valid" "Ignore,Configure"
|
|
bitfld.long 0x04 30. " XTD ,Extended Identifier" "11-bit,29-bit"
|
|
bitfld.long 0x04 29. " DIR ,Message Direction" "Receive,Transmit"
|
|
hexmask.long 0x04 0.--28. 1. " ID ,Message Identifier"
|
|
endif
|
|
else
|
|
if (((per.l(((ad:0xFFF7DE00+0x100+0x08))))&0x40000000)==0x0)
|
|
group.long (0x100+0x04)++0x07
|
|
line.long 0x0 "IF1MASK,IF1 Mask Register"
|
|
bitfld.long 0x00 31. " MXTD ,Mask Extended Identifier" "No effect,Filtering"
|
|
bitfld.long 0x00 30. " MDIR ,Mask Message Direction" "No effect,Filtering"
|
|
newline
|
|
bitfld.long 0x00 28. " ID ,Message Identifier bit[28]" "0,1"
|
|
bitfld.long 0x00 27. ",Message Identifier bit[27]" "0,1"
|
|
bitfld.long 0x00 26. ",Message Identifier bit[26]" "0,1"
|
|
bitfld.long 0x00 25. ",Message Identifier bit[25]" "0,1"
|
|
bitfld.long 0x00 24. ",Message Identifier bit[24]" "0,1"
|
|
bitfld.long 0x00 23. ",Message Identifier bit[23]" "0,1"
|
|
bitfld.long 0x00 22. ",Message Identifier bit[22]" "0,1"
|
|
bitfld.long 0x00 21. ",Message Identifier bit[21]" "0,1"
|
|
bitfld.long 0x00 20. ",Message Identifier bit[20]" "0,1"
|
|
bitfld.long 0x00 19. ",Message Identifier bit[19]" "0,1"
|
|
bitfld.long 0x00 18. ",Message Identifier bit[18]" "0,1"
|
|
line.long 0x04 "IF1ARB,IF1 Arbitation Register"
|
|
bitfld.long 0x04 31. " MSGVAL ,Message Valid" "Ignore,Configure"
|
|
bitfld.long 0x04 30. " XTD ,Extended Identifier" "11-bit,29-bit"
|
|
bitfld.long 0x04 29. " DIR ,Message Direction" "Receive,Transmit"
|
|
hexmask.long.word 0x04 18.--28. 1. " ID ,Message Identifier"
|
|
else
|
|
group.long (0x100+0x04)++0x07
|
|
line.long 0x0 "IF1MASK,IF1 Mask Register"
|
|
bitfld.long 0x00 31. " MXTD ,Mask Extended Identifier" "No effect,Filtering"
|
|
bitfld.long 0x00 30. " MDIR ,Mask Message Direction" "No effect,Filtering"
|
|
newline
|
|
bitfld.long 0x00 28. " ID ,Message Identifier bit[28]" "0,1"
|
|
bitfld.long 0x00 27. ",Message Identifier bit[27]" "0,1"
|
|
bitfld.long 0x00 26. ",Message Identifier bit[26]" "0,1"
|
|
bitfld.long 0x00 25. ",Message Identifier bit[25]" "0,1"
|
|
bitfld.long 0x00 24. ",Message Identifier bit[24]" "0,1"
|
|
bitfld.long 0x00 23. ",Message Identifier bit[23]" "0,1"
|
|
bitfld.long 0x00 22. ",Message Identifier bit[22]" "0,1"
|
|
bitfld.long 0x00 21. ",Message Identifier bit[21]" "0,1"
|
|
bitfld.long 0x00 20. ",Message Identifier bit[20]" "0,1"
|
|
bitfld.long 0x00 19. ",Message Identifier bit[19]" "0,1"
|
|
bitfld.long 0x00 18. ",Message Identifier bit[18]" "0,1"
|
|
bitfld.long 0x00 17. ",Message Identifier bit[17]" "0,1"
|
|
bitfld.long 0x00 16. ",Message Identifier bit[16]" "0,1"
|
|
bitfld.long 0x00 15. ",Message Identifier bit[15]" "0,1"
|
|
bitfld.long 0x00 14. ",Message Identifier bit[14]" "0,1"
|
|
bitfld.long 0x00 13. ",Message Identifier bit[13]" "0,1"
|
|
bitfld.long 0x00 12. ",Message Identifier bit[12]" "0,1"
|
|
bitfld.long 0x00 11. ",Message Identifier bit[11]" "0,1"
|
|
bitfld.long 0x00 10. ",Message Identifier bit[10]" "0,1"
|
|
bitfld.long 0x00 9. ",Message Identifier bit[9]" "0,1"
|
|
bitfld.long 0x00 8. ",Message Identifier bit[8]" "0,1"
|
|
bitfld.long 0x00 7. ",Message Identifier bit[7]" "0,1"
|
|
bitfld.long 0x00 6. ",Message Identifier bit[6]" "0,1"
|
|
bitfld.long 0x00 5. ",Message Identifier bit[5]" "0,1"
|
|
bitfld.long 0x00 4. ",Message Identifier bit[4]" "0,1"
|
|
bitfld.long 0x00 3. ",Message Identifier bit[3]" "0,1"
|
|
bitfld.long 0x00 2. ",Message Identifier bit[2]" "0,1"
|
|
bitfld.long 0x00 1. ",Message Identifier bit[1]" "0,1"
|
|
bitfld.long 0x00 0. ",Message Identifier bit[0]" "0,1"
|
|
line.long 0x04 "IF1ARB,IF1 Arbitation Register"
|
|
bitfld.long 0x04 31. " MSGVAL ,Message Valid" "Ignore,Configure"
|
|
bitfld.long 0x04 30. " XTD ,Extended Identifier" "11-bit,29-bit"
|
|
bitfld.long 0x04 29. " DIR ,Message Direction" "Receive,Transmit"
|
|
hexmask.long 0x04 0.--28. 1. " ID ,Message Identifier"
|
|
endif
|
|
endif
|
|
group.long (0x100+0x0C)++0x0B
|
|
line.long 0x00 "IF1MCTRL,IF1 Message Control Register"
|
|
bitfld.long 0x00 15. " NEWDAT ,New Data" "No new data,New data"
|
|
bitfld.long 0x00 14. " MSGLST ,Message Lost" "Not lost,Lost"
|
|
bitfld.long 0x00 13. " INTPND ,Interrupt Pending" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x00 12. " UMASK ,Use Acceptance Mask" "Ignored,Masked"
|
|
bitfld.long 0x00 11. " TXIE ,Transmit Interrupt Enable" "Unchanged,Set"
|
|
bitfld.long 0x00 10. " RXIE ,Receive Interrupt Enable" "Unchanged,Set"
|
|
newline
|
|
bitfld.long 0x00 9. " RMTEN ,Remote Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " TXRQST ,Transmit Request" "Not requested,Requested"
|
|
bitfld.long 0x00 7. " EOB ,End of Block" "Single/Last,Not last"
|
|
newline
|
|
bitfld.long 0x00 0.--3. " DLC[3-0] ,Data Length Code" "0 byte,1 bytes,2 bytes,3 bytes,4 bytes,5 bytes,6 bytes,7 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes"
|
|
line.long 0x04 "IF1DATA,IF1 Data A Register"
|
|
hexmask.long.byte 0x04 24.--31. 1. " DATA[3] ,4th data byte of a CAN Data Frame"
|
|
hexmask.long.byte 0x04 16.--23. 1. " [2] ,3rd data byte of a CAN Data Frame"
|
|
hexmask.long.byte 0x04 8.--15. 1. " [1] ,2nd data byte of a CAN Data Frame"
|
|
hexmask.long.byte 0x04 0.--7. 1. " [0] ,1st data byte of a CAN Data Frame"
|
|
line.long 0x08 "IF1DATB,IF1 Data B Register"
|
|
hexmask.long.byte 0x08 24.--31. 1. " DATA[7] ,8th data byte of a CAN Data Frame"
|
|
hexmask.long.byte 0x08 16.--23. 1. " [6] ,7th data byte of a CAN Data Frame"
|
|
hexmask.long.byte 0x08 8.--15. 1. " [5] ,6th data byte of a CAN Data Frame"
|
|
hexmask.long.byte 0x08 0.--7. 1. " [4] ,5th data byte of a CAN Data Frame"
|
|
group.long 0x120++0x3 "IF2"
|
|
line.long 0x00 "IF2COM,IF2 Command Mask / Command Request Register"
|
|
bitfld.long 0x00 23. " WR/RD ,Write / Read direction" "Read,Write"
|
|
newline
|
|
bitfld.long 0x00 22. " MASK ,Access Mask Bits" "Unchanged,Identifier Mask+MDir+MXtd"
|
|
newline
|
|
bitfld.long 0x00 21. " ARB ,Access Arbitration Bits" "Unchanged,Identifier+Dir+Xtd+MSGVAl"
|
|
newline
|
|
bitfld.long 0x00 20. " CONTROL ,Access Control Bits" "Unchanged,Control bits"
|
|
bitfld.long 0x00 19. " CLRINTPND ,Clear Interrupt Pending Bit" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 18. " TXRQST/NEWDAT ,Access Transmission Request Bit" "Not requested,Requested"
|
|
bitfld.long 0x00 17. " DATA_A ,Access Data Bytes 0-3" "Unchanged,Data bytes 0-3"
|
|
newline
|
|
bitfld.long 0x00 16. " DATA_B ,Access Data Bytes 4-7" "Unchanged,Data bytes 4-7"
|
|
bitfld.long 0x00 15. " BUSY ,Busy Flag" "Not busy,Busy"
|
|
newline
|
|
sif (!cpuis("TMS570LS0332")&&!cpuis("TMS570LS0432"))
|
|
bitfld.long 0x00 14. " DMAACTIVE ,Activation of DMA Feature for Subsequent Internal IF1 Update" "No active,Active"
|
|
newline
|
|
endif
|
|
hexmask.long.byte 0x00 0.--7. 1. " MESSAGE_NUMBER ,Message Number"
|
|
sif cpuis("TMS570LS0232")||cpuis("TMS570LS0714*")||cpuis("TMS570LS0914*")||cpuis("TMS570LS3137-EP")
|
|
if (((per.l.be(((ad:0xFFF7DE00+0x120+0x08))))&0x40000000)==0x0)
|
|
group.long (0x120+0x04)++0x07
|
|
line.long 0x0 "IF2MASK,IF2 Mask Register"
|
|
bitfld.long 0x00 31. " MXTD ,Mask Extended Identifier" "No effect,Filtering"
|
|
bitfld.long 0x00 30. " MDIR ,Mask Message Direction" "No effect,Filtering"
|
|
newline
|
|
bitfld.long 0x00 28. " ID ,Message Identifier bit[10]" "0,1"
|
|
bitfld.long 0x00 27. ",Message Identifier bit[9]" "0,1"
|
|
bitfld.long 0x00 26. ",Message Identifier bit[8]" "0,1"
|
|
bitfld.long 0x00 25. ",Message Identifier bit[7]" "0,1"
|
|
bitfld.long 0x00 24. ",Message Identifier bit[6]" "0,1"
|
|
bitfld.long 0x00 23. ",Message Identifier bit[5]" "0,1"
|
|
bitfld.long 0x00 22. ",Message Identifier bit[4]" "0,1"
|
|
bitfld.long 0x00 21. ",Message Identifier bit[3]" "0,1"
|
|
bitfld.long 0x00 20. ",Message Identifier bit[2]" "0,1"
|
|
bitfld.long 0x00 19. ",Message Identifier bit[1]" "0,1"
|
|
bitfld.long 0x00 18. ",Message Identifier bit[0]" "0,1"
|
|
line.long 0x04 "IF2ARB,IF2 Arbitration Register"
|
|
bitfld.long 0x04 31. " MSGVAL ,Message Valid" "Ignore,Configure"
|
|
bitfld.long 0x04 30. " XTD ,Extended Identifier" "11-bit,29-bit"
|
|
bitfld.long 0x04 29. " DIR ,Message Direction" "Receive,Transmit"
|
|
hexmask.long.word 0x04 18.--28. 1. " ID ,Message Identifier"
|
|
else
|
|
group.long (0x120+0x04)++0x07
|
|
line.long 0x00 "IF2MASK,IF2 Mask Register"
|
|
bitfld.long 0x00 31. " MXTD ,Mask Extended Identifier" "No effect,Filtering"
|
|
bitfld.long 0x00 30. " MDIR ,Mask Message Direction" "No effect,Filtering"
|
|
newline
|
|
bitfld.long 0x00 28. " ID ,Message Identifier bit[28]" "0,1"
|
|
bitfld.long 0x00 27. ",Message Identifier bit[27]" "0,1"
|
|
bitfld.long 0x00 26. ",Message Identifier bit[26]" "0,1"
|
|
bitfld.long 0x00 25. ",Message Identifier bit[25]" "0,1"
|
|
bitfld.long 0x00 24. ",Message Identifier bit[24]" "0,1"
|
|
bitfld.long 0x00 23. ",Message Identifier bit[23]" "0,1"
|
|
bitfld.long 0x00 22. ",Message Identifier bit[22]" "0,1"
|
|
bitfld.long 0x00 21. ",Message Identifier bit[21]" "0,1"
|
|
bitfld.long 0x00 20. ",Message Identifier bit[20]" "0,1"
|
|
bitfld.long 0x00 19. ",Message Identifier bit[19]" "0,1"
|
|
bitfld.long 0x00 18. ",Message Identifier bit[18]" "0,1"
|
|
bitfld.long 0x00 17. ",Message Identifier bit[17]" "0,1"
|
|
bitfld.long 0x00 16. ",Message Identifier bit[16]" "0,1"
|
|
bitfld.long 0x00 15. ",Message Identifier bit[15]" "0,1"
|
|
bitfld.long 0x00 14. ",Message Identifier bit[14]" "0,1"
|
|
bitfld.long 0x00 13. ",Message Identifier bit[13]" "0,1"
|
|
bitfld.long 0x00 12. ",Message Identifier bit[12]" "0,1"
|
|
bitfld.long 0x00 11. ",Message Identifier bit[11]" "0,1"
|
|
bitfld.long 0x00 10. ",Message Identifier bit[10]" "0,1"
|
|
bitfld.long 0x00 9. ",Message Identifier bit[9]" "0,1"
|
|
bitfld.long 0x00 8. ",Message Identifier bit[8]" "0,1"
|
|
bitfld.long 0x00 7. ",Message Identifier bit[7]" "0,1"
|
|
bitfld.long 0x00 6. ",Message Identifier bit[6]" "0,1"
|
|
bitfld.long 0x00 5. ",Message Identifier bit[5]" "0,1"
|
|
bitfld.long 0x00 4. ",Message Identifier bit[4]" "0,1"
|
|
bitfld.long 0x00 3. ",Message Identifier bit[3]" "0,1"
|
|
bitfld.long 0x00 2. ",Message Identifier bit[2]" "0,1"
|
|
bitfld.long 0x00 1. ",Message Identifier bit[1]" "0,1"
|
|
bitfld.long 0x00 0. ",Message Identifier bit[0]" "0,1"
|
|
line.long 0x04 "IF2ARB,IF2 Arbitation Register"
|
|
bitfld.long 0x04 31. " MSGVAL ,Message Valid" "Ignore,Configure"
|
|
bitfld.long 0x04 30. " XTD ,Extended Identifier" "11-bit,29-bit"
|
|
bitfld.long 0x04 29. " DIR ,Message Direction" "Receive,Transmit"
|
|
hexmask.long 0x04 0.--28. 1. " ID ,Message Identifier"
|
|
endif
|
|
else
|
|
if (((per.l(((ad:0xFFF7DE00+0x120+0x08))))&0x40000000)==0x0)
|
|
group.long (0x120+0x04)++0x07
|
|
line.long 0x0 "IF2MASK,IF2 Mask Register"
|
|
bitfld.long 0x00 31. " MXTD ,Mask Extended Identifier" "No effect,Filtering"
|
|
bitfld.long 0x00 30. " MDIR ,Mask Message Direction" "No effect,Filtering"
|
|
newline
|
|
bitfld.long 0x00 28. " ID ,Message Identifier bit[28]" "0,1"
|
|
bitfld.long 0x00 27. ",Message Identifier bit[27]" "0,1"
|
|
bitfld.long 0x00 26. ",Message Identifier bit[26]" "0,1"
|
|
bitfld.long 0x00 25. ",Message Identifier bit[25]" "0,1"
|
|
bitfld.long 0x00 24. ",Message Identifier bit[24]" "0,1"
|
|
bitfld.long 0x00 23. ",Message Identifier bit[23]" "0,1"
|
|
bitfld.long 0x00 22. ",Message Identifier bit[22]" "0,1"
|
|
bitfld.long 0x00 21. ",Message Identifier bit[21]" "0,1"
|
|
bitfld.long 0x00 20. ",Message Identifier bit[20]" "0,1"
|
|
bitfld.long 0x00 19. ",Message Identifier bit[19]" "0,1"
|
|
bitfld.long 0x00 18. ",Message Identifier bit[18]" "0,1"
|
|
line.long 0x04 "IF2ARB,IF2 Arbitation Register"
|
|
bitfld.long 0x04 31. " MSGVAL ,Message Valid" "Ignore,Configure"
|
|
bitfld.long 0x04 30. " XTD ,Extended Identifier" "11-bit,29-bit"
|
|
bitfld.long 0x04 29. " DIR ,Message Direction" "Receive,Transmit"
|
|
hexmask.long.word 0x04 18.--28. 1. " ID ,Message Identifier"
|
|
else
|
|
group.long (0x120+0x04)++0x07
|
|
line.long 0x0 "IF2MASK,IF2 Mask Register"
|
|
bitfld.long 0x00 31. " MXTD ,Mask Extended Identifier" "No effect,Filtering"
|
|
bitfld.long 0x00 30. " MDIR ,Mask Message Direction" "No effect,Filtering"
|
|
newline
|
|
bitfld.long 0x00 28. " ID ,Message Identifier bit[28]" "0,1"
|
|
bitfld.long 0x00 27. ",Message Identifier bit[27]" "0,1"
|
|
bitfld.long 0x00 26. ",Message Identifier bit[26]" "0,1"
|
|
bitfld.long 0x00 25. ",Message Identifier bit[25]" "0,1"
|
|
bitfld.long 0x00 24. ",Message Identifier bit[24]" "0,1"
|
|
bitfld.long 0x00 23. ",Message Identifier bit[23]" "0,1"
|
|
bitfld.long 0x00 22. ",Message Identifier bit[22]" "0,1"
|
|
bitfld.long 0x00 21. ",Message Identifier bit[21]" "0,1"
|
|
bitfld.long 0x00 20. ",Message Identifier bit[20]" "0,1"
|
|
bitfld.long 0x00 19. ",Message Identifier bit[19]" "0,1"
|
|
bitfld.long 0x00 18. ",Message Identifier bit[18]" "0,1"
|
|
bitfld.long 0x00 17. ",Message Identifier bit[17]" "0,1"
|
|
bitfld.long 0x00 16. ",Message Identifier bit[16]" "0,1"
|
|
bitfld.long 0x00 15. ",Message Identifier bit[15]" "0,1"
|
|
bitfld.long 0x00 14. ",Message Identifier bit[14]" "0,1"
|
|
bitfld.long 0x00 13. ",Message Identifier bit[13]" "0,1"
|
|
bitfld.long 0x00 12. ",Message Identifier bit[12]" "0,1"
|
|
bitfld.long 0x00 11. ",Message Identifier bit[11]" "0,1"
|
|
bitfld.long 0x00 10. ",Message Identifier bit[10]" "0,1"
|
|
bitfld.long 0x00 9. ",Message Identifier bit[9]" "0,1"
|
|
bitfld.long 0x00 8. ",Message Identifier bit[8]" "0,1"
|
|
bitfld.long 0x00 7. ",Message Identifier bit[7]" "0,1"
|
|
bitfld.long 0x00 6. ",Message Identifier bit[6]" "0,1"
|
|
bitfld.long 0x00 5. ",Message Identifier bit[5]" "0,1"
|
|
bitfld.long 0x00 4. ",Message Identifier bit[4]" "0,1"
|
|
bitfld.long 0x00 3. ",Message Identifier bit[3]" "0,1"
|
|
bitfld.long 0x00 2. ",Message Identifier bit[2]" "0,1"
|
|
bitfld.long 0x00 1. ",Message Identifier bit[1]" "0,1"
|
|
bitfld.long 0x00 0. ",Message Identifier bit[0]" "0,1"
|
|
line.long 0x04 "IF2ARB,IF2 Arbitation Register"
|
|
bitfld.long 0x04 31. " MSGVAL ,Message Valid" "Ignore,Configure"
|
|
bitfld.long 0x04 30. " XTD ,Extended Identifier" "11-bit,29-bit"
|
|
bitfld.long 0x04 29. " DIR ,Message Direction" "Receive,Transmit"
|
|
hexmask.long 0x04 0.--28. 1. " ID ,Message Identifier"
|
|
endif
|
|
endif
|
|
group.long (0x120+0x0C)++0x0B
|
|
line.long 0x00 "IF2MCTRL,IF2 Message Control Register"
|
|
bitfld.long 0x00 15. " NEWDAT ,New Data" "No new data,New data"
|
|
bitfld.long 0x00 14. " MSGLST ,Message Lost" "Not lost,Lost"
|
|
bitfld.long 0x00 13. " INTPND ,Interrupt Pending" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x00 12. " UMASK ,Use Acceptance Mask" "Ignored,Masked"
|
|
bitfld.long 0x00 11. " TXIE ,Transmit Interrupt Enable" "Unchanged,Set"
|
|
bitfld.long 0x00 10. " RXIE ,Receive Interrupt Enable" "Unchanged,Set"
|
|
newline
|
|
bitfld.long 0x00 9. " RMTEN ,Remote Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " TXRQST ,Transmit Request" "Not requested,Requested"
|
|
bitfld.long 0x00 7. " EOB ,End of Block" "Single/Last,Not last"
|
|
newline
|
|
bitfld.long 0x00 0.--3. " DLC[3-0] ,Data Length Code" "0 byte,1 bytes,2 bytes,3 bytes,4 bytes,5 bytes,6 bytes,7 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes"
|
|
line.long 0x04 "IF2DATA,IF2 Data A Register"
|
|
hexmask.long.byte 0x04 24.--31. 1. " DATA[3] ,4th data byte of a CAN Data Frame"
|
|
hexmask.long.byte 0x04 16.--23. 1. " [2] ,3rd data byte of a CAN Data Frame"
|
|
hexmask.long.byte 0x04 8.--15. 1. " [1] ,2nd data byte of a CAN Data Frame"
|
|
hexmask.long.byte 0x04 0.--7. 1. " [0] ,1st data byte of a CAN Data Frame"
|
|
line.long 0x08 "IF2DATB,IF2 Data B Register"
|
|
hexmask.long.byte 0x08 24.--31. 1. " DATA[7] ,8th data byte of a CAN Data Frame"
|
|
hexmask.long.byte 0x08 16.--23. 1. " [6] ,7th data byte of a CAN Data Frame"
|
|
hexmask.long.byte 0x08 8.--15. 1. " [5] ,6th data byte of a CAN Data Frame"
|
|
hexmask.long.byte 0x08 0.--7. 1. " [4] ,5th data byte of a CAN Data Frame"
|
|
group.long 0x140++0x3 "IF3"
|
|
line.long 0x00 "IF3OB,IF3 Observation Register"
|
|
sif (cpu()==("TMS570LS0332")||cpu()==("TMS570LS0432")||cpuis("TMS570LS1114*")||cpuis("TMS570LS1115*")||cpuis("TMS570LS1224*")||cpuis("TMS570LS1225*")||cpuis("TMS570LS1227*")||cpuis("TMS570LS21*")||cpuis("TMS570LS31*")||cpuis("TMS570LS0232")||cpuis("TMS570LS0714*")||cpuis("TMS570LS0914*"))
|
|
rbitfld.long 0x00 15. " IF3UPD ,IF3 Updata Data" "Not loaded,Loaded"
|
|
rbitfld.long 0x00 12. " IF3SDB ,IF3 Status of Data B Read Access" "Low,High"
|
|
rbitfld.long 0x00 11. " IF3SDA ,IF3 Status of Data A Read Access" "Low,High"
|
|
newline
|
|
rbitfld.long 0x00 10. " IF3SC ,IF3 Status of Control Bits Read Access" "Low,High"
|
|
rbitfld.long 0x00 9. " IF3SA ,IF3 Status of Arbitration Data Read Access" "Low,High"
|
|
rbitfld.long 0x00 8. " IF3SM ,IF3 Status of Mask Data Read Access" "Low,High"
|
|
else
|
|
bitfld.long 0x00 15. " IF3UPD ,IF3 Updata Data" "Not loaded,Loaded"
|
|
bitfld.long 0x00 12. " IF3SDB ,IF3 Status of Data B Read Access" "Low,High"
|
|
bitfld.long 0x00 11. " IF3SDA ,IF3 Status of Data A Read Access" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 10. " IF3SC ,IF3 Status of Control Bits Read Access" "Low,High"
|
|
bitfld.long 0x00 9. " IF3SA ,IF3 Status of Arbitration Data Read Access" "Low,High"
|
|
bitfld.long 0x00 8. " IF3SM ,IF3 Status of Mask Data Read Access" "Low,High"
|
|
endif
|
|
newline
|
|
bitfld.long 0x00 4. " DATA_B ,Data B Read Observation" "Not read,Read"
|
|
bitfld.long 0x00 3. " DATA_A ,Data A Read Observation" "Not read,Read"
|
|
bitfld.long 0x00 2. " CTRL ,Ctrl Read Observation" "Not read,Read"
|
|
newline
|
|
bitfld.long 0x00 1. " ARB ,Arbitration Data Read Observation" "Not read,Read"
|
|
bitfld.long 0x00 0. " MASK ,Mask Data Read Observation" "Not read,Read"
|
|
sif cpuis("TMS570LS0232")||cpuis("TMS570LS0714*")||cpuis("TMS570LS0914*")
|
|
if (((per.l.be((ad:0xFFF7DE00+0x148)))&0x40000000)==0x0)
|
|
rgroup.long 0x144++0x07
|
|
line.long 0x00 "IF3MASK,IF3 Mask Register"
|
|
bitfld.long 0x00 31. " MXtd ,Mask Extended Identifier" "No effect,Filtering"
|
|
bitfld.long 0x00 30. " MDir ,Mask Message Direction" "No effect,Filtering"
|
|
newline
|
|
bitfld.long 0x00 28. " ID ,Message Identifier bit[28]" "0,1"
|
|
bitfld.long 0x00 27. ",Message Identifier bit[27]" "0,1"
|
|
bitfld.long 0x00 26. ",Message Identifier bit[26]" "0,1"
|
|
bitfld.long 0x00 25. ",Message Identifier bit[25]" "0,1"
|
|
bitfld.long 0x00 24. ",Message Identifier bit[24]" "0,1"
|
|
bitfld.long 0x00 23. ",Message Identifier bit[23]" "0,1"
|
|
bitfld.long 0x00 22. ",Message Identifier bit[22]" "0,1"
|
|
bitfld.long 0x00 21. ",Message Identifier bit[21]" "0,1"
|
|
bitfld.long 0x00 20. ",Message Identifier bit[20]" "0,1"
|
|
bitfld.long 0x00 19. ",Message Identifier bit[19]" "0,1"
|
|
bitfld.long 0x00 18. ",Message Identifier bit[18]" "0,1"
|
|
line.long 0x04 "IF3ARB,IF3 Arbitation Register"
|
|
bitfld.long 0x04 31. " MSGVAl ,Message Valid" "Ignored,Configured"
|
|
bitfld.long 0x04 30. " XTD ,Extended Identifier" "11-bit,29-bit"
|
|
bitfld.long 0x04 29. " DIR ,Message Direction" "Receive,Transmit"
|
|
newline
|
|
hexmask.long.word 0x04 18.--28. 1. " ID ,Message Identifier"
|
|
else
|
|
rgroup.long 0x144++0x07
|
|
line.long 0x0 "IF3MASK,IF3 Mask Register"
|
|
bitfld.long 0x00 31. " MXTD ,Mask Extended Identifier" "No effect,Filtering"
|
|
bitfld.long 0x00 30. " MDIR ,Mask Message Direction" "No effect,Filtering"
|
|
newline
|
|
bitfld.long 0x00 28. " ID ,Message Identifier bit[28]" "0,1"
|
|
bitfld.long 0x00 27. ",Message Identifier bit[27]" "0,1"
|
|
bitfld.long 0x00 26. ",Message Identifier bit[26]" "0,1"
|
|
bitfld.long 0x00 25. ",Message Identifier bit[25]" "0,1"
|
|
bitfld.long 0x00 24. ",Message Identifier bit[24]" "0,1"
|
|
bitfld.long 0x00 23. ",Message Identifier bit[23]" "0,1"
|
|
bitfld.long 0x00 22. ",Message Identifier bit[22]" "0,1"
|
|
bitfld.long 0x00 21. ",Message Identifier bit[21]" "0,1"
|
|
bitfld.long 0x00 20. ",Message Identifier bit[20]" "0,1"
|
|
bitfld.long 0x00 19. ",Message Identifier bit[19]" "0,1"
|
|
bitfld.long 0x00 18. ",Message Identifier bit[18]" "0,1"
|
|
bitfld.long 0x00 17. ",Message Identifier bit[17]" "0,1"
|
|
bitfld.long 0x00 16. ",Message Identifier bit[16]" "0,1"
|
|
bitfld.long 0x00 15. ",Message Identifier bit[15]" "0,1"
|
|
bitfld.long 0x00 14. ",Message Identifier bit[14]" "0,1"
|
|
bitfld.long 0x00 13. ",Message Identifier bit[13]" "0,1"
|
|
bitfld.long 0x00 12. ",Message Identifier bit[12]" "0,1"
|
|
bitfld.long 0x00 11. ",Message Identifier bit[11]" "0,1"
|
|
bitfld.long 0x00 10. ",Message Identifier bit[10]" "0,1"
|
|
bitfld.long 0x00 9. ",Message Identifier bit[9]" "0,1"
|
|
bitfld.long 0x00 8. ",Message Identifier bit[8]" "0,1"
|
|
bitfld.long 0x00 7. ",Message Identifier bit[7]" "0,1"
|
|
bitfld.long 0x00 6. ",Message Identifier bit[6]" "0,1"
|
|
bitfld.long 0x00 5. ",Message Identifier bit[5]" "0,1"
|
|
bitfld.long 0x00 4. ",Message Identifier bit[4]" "0,1"
|
|
bitfld.long 0x00 3. ",Message Identifier bit[3]" "0,1"
|
|
bitfld.long 0x00 2. ",Message Identifier bit[2]" "0,1"
|
|
bitfld.long 0x00 1. ",Message Identifier bit[1]" "0,1"
|
|
bitfld.long 0x00 0. ",Message Identifier bit[0]" "0,1"
|
|
line.long 0x04 "IF3ARB,IF3 Arbitation Register"
|
|
bitfld.long 0x04 31. " MSGVAl ,Message Valid" "Ignored,Configured"
|
|
bitfld.long 0x04 30. " XTD ,Extended Identifier" "11-bit,29-bit"
|
|
bitfld.long 0x04 29. " DIR ,Message Direction" "Receive,Transmit"
|
|
newline
|
|
hexmask.long 0x04 0.--28. 1. " ID ,Message Identifier"
|
|
endif
|
|
else
|
|
if (((per.l((ad:0xFFF7DE00+0x148)))&0x40000000)==0x0)
|
|
rgroup.long 0x144++0x07
|
|
line.long 0x0 "IF3MASK,IF3 Mask Register"
|
|
bitfld.long 0x00 31. " MXtd ,Mask Extended Identifier" "No effect,Filtering"
|
|
bitfld.long 0x00 30. " MDir ,Mask Message Direction" "No effect,Filtering"
|
|
newline
|
|
bitfld.long 0x00 28. " ID ,Message Identifier bit[28]" "0,1"
|
|
bitfld.long 0x00 27. ",Message Identifier bit[27]" "0,1"
|
|
bitfld.long 0x00 26. ",Message Identifier bit[26]" "0,1"
|
|
bitfld.long 0x00 25. ",Message Identifier bit[25]" "0,1"
|
|
bitfld.long 0x00 24. ",Message Identifier bit[24]" "0,1"
|
|
bitfld.long 0x00 23. ",Message Identifier bit[23]" "0,1"
|
|
bitfld.long 0x00 22. ",Message Identifier bit[22]" "0,1"
|
|
bitfld.long 0x00 21. ",Message Identifier bit[21]" "0,1"
|
|
bitfld.long 0x00 20. ",Message Identifier bit[20]" "0,1"
|
|
bitfld.long 0x00 19. ",Message Identifier bit[19]" "0,1"
|
|
bitfld.long 0x00 18. ",Message Identifier bit[18]" "0,1"
|
|
line.long 0x04 "IF3ARB,IF3 Arbitation Register"
|
|
bitfld.long 0x04 31. " MSGVAl ,Message Valid" "Ignored,Configured"
|
|
bitfld.long 0x04 30. " XTD ,Extended Identifier" "11-bit,29-bit"
|
|
bitfld.long 0x04 29. " DIR ,Message Direction" "Receive,Transmit"
|
|
newline
|
|
hexmask.long.word 0x04 18.--28. 1. " ID ,Message Identifier"
|
|
else
|
|
rgroup.long 0x144++0x07
|
|
line.long 0x0 "IF3MASK,IF3 Mask Register"
|
|
bitfld.long 0x00 31. " MXTD ,Mask Extended Identifier" "No effect,Filtering"
|
|
bitfld.long 0x00 30. " MDIR ,Mask Message Direction" "No effect,Filtering"
|
|
newline
|
|
bitfld.long 0x00 28. " ID ,Message Identifier bit[28]" "0,1"
|
|
bitfld.long 0x00 27. ",Message Identifier bit[27]" "0,1"
|
|
bitfld.long 0x00 26. ",Message Identifier bit[26]" "0,1"
|
|
bitfld.long 0x00 25. ",Message Identifier bit[25]" "0,1"
|
|
bitfld.long 0x00 24. ",Message Identifier bit[24]" "0,1"
|
|
bitfld.long 0x00 23. ",Message Identifier bit[23]" "0,1"
|
|
bitfld.long 0x00 22. ",Message Identifier bit[22]" "0,1"
|
|
bitfld.long 0x00 21. ",Message Identifier bit[21]" "0,1"
|
|
bitfld.long 0x00 20. ",Message Identifier bit[20]" "0,1"
|
|
bitfld.long 0x00 19. ",Message Identifier bit[19]" "0,1"
|
|
bitfld.long 0x00 18. ",Message Identifier bit[18]" "0,1"
|
|
bitfld.long 0x00 17. ",Message Identifier bit[17]" "0,1"
|
|
bitfld.long 0x00 16. ",Message Identifier bit[16]" "0,1"
|
|
bitfld.long 0x00 15. ",Message Identifier bit[15]" "0,1"
|
|
bitfld.long 0x00 14. ",Message Identifier bit[14]" "0,1"
|
|
bitfld.long 0x00 13. ",Message Identifier bit[13]" "0,1"
|
|
bitfld.long 0x00 12. ",Message Identifier bit[12]" "0,1"
|
|
bitfld.long 0x00 11. ",Message Identifier bit[11]" "0,1"
|
|
bitfld.long 0x00 10. ",Message Identifier bit[10]" "0,1"
|
|
bitfld.long 0x00 9. ",Message Identifier bit[9]" "0,1"
|
|
bitfld.long 0x00 8. ",Message Identifier bit[8]" "0,1"
|
|
bitfld.long 0x00 7. ",Message Identifier bit[7]" "0,1"
|
|
bitfld.long 0x00 6. ",Message Identifier bit[6]" "0,1"
|
|
bitfld.long 0x00 5. ",Message Identifier bit[5]" "0,1"
|
|
bitfld.long 0x00 4. ",Message Identifier bit[4]" "0,1"
|
|
bitfld.long 0x00 3. ",Message Identifier bit[3]" "0,1"
|
|
bitfld.long 0x00 2. ",Message Identifier bit[2]" "0,1"
|
|
bitfld.long 0x00 1. ",Message Identifier bit[1]" "0,1"
|
|
bitfld.long 0x00 0. ",Message Identifier bit[0]" "0,1"
|
|
line.long 0x04 "IF3ARB,IF3 Arbitation Register"
|
|
bitfld.long 0x04 31. " MSGVAl ,Message Valid" "Ignored,Configured"
|
|
bitfld.long 0x04 30. " XTD ,Extended Identifier" "11-bit,29-bit"
|
|
bitfld.long 0x04 29. " DIR ,Message Direction" "Receive,Transmit"
|
|
newline
|
|
hexmask.long 0x04 0.--28. 1. " ID ,Message Identifier"
|
|
endif
|
|
endif
|
|
group.long 0x14C++0x0B
|
|
line.long 0x00 "IF3MCTRL,IF3 Message Control Register"
|
|
bitfld.long 0x00 15. " NEWDAT ,New Data" "No new data,New data"
|
|
bitfld.long 0x00 14. " MSGLST ,Message Lost" "Not lost,Lost"
|
|
bitfld.long 0x00 13. " INTPND ,Interrupt Pending" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x00 12. " UMASK ,Use Acceptance Mask" "Ignored,Masked"
|
|
bitfld.long 0x00 11. " TXIE ,Transmit Interrupt Enable" "Unchanged,Enabled"
|
|
bitfld.long 0x00 10. " RXIE ,Receive Interrupt Enable" "Unchanged,Enabled"
|
|
newline
|
|
bitfld.long 0x00 9. " RMTEN ,Remote Enable" "Unchanged,Enabled"
|
|
bitfld.long 0x00 8. " TXRQST ,Transmit Request" "Not requested,Requested"
|
|
bitfld.long 0x00 7. " EOB ,End of Block" "Not last,Single/Last"
|
|
newline
|
|
bitfld.long 0x00 0.--3. " DLC[3-0] ,Data Length Code" "0 byte,1 byte,2 bytes,3 bytes,4 bytes,5 bytes,6 bytes,7 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes"
|
|
line.long 0x04 "IF3DATA,IF3 Data A Register"
|
|
hexmask.long.byte 0x04 24.--31. 1. " DATA[3] ,4th data byte of a CAN Data Frame"
|
|
hexmask.long.byte 0x04 16.--23. 1. " [2] ,3rd data byte of a CAN Data Frame"
|
|
hexmask.long.byte 0x04 8.--15. 1. " [1] ,2nd data byte of a CAN Data Frame"
|
|
hexmask.long.byte 0x04 0.--7. 1. " [0] ,1st data byte of a CAN Data Frame"
|
|
line.long 0x08 "IF3DATB,IF3 Data B Register"
|
|
hexmask.long.byte 0x08 24.--31. 1. " DATA[7] ,8th data byte of a CAN Data Frame"
|
|
hexmask.long.byte 0x08 16.--23. 1. " [6] ,7th data byte of a CAN Data Frame"
|
|
hexmask.long.byte 0x08 8.--15. 1. " [5] ,6th data byte of a CAN Data Frame"
|
|
hexmask.long.byte 0x08 0.--7. 1. " [4] ,5th data byte of a CAN Data Frame"
|
|
group.long 0x160++0x0F
|
|
line.long 0x0 "IF3UENA2_1,Update Enable 2_1 Register"
|
|
bitfld.long 0x00 31. " IF3UPDATEEN[32] ,IF3 Update Enabled Bit[32]" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " [31] ,IF3 Update Enabled Bit[31]" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 29. " [30] ,IF3 Update Enabled Bit[30]" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " [29] ,IF3 Update Enabled Bit[29]" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 27. " [28] ,IF3 Update Enabled Bit[28]" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " [27] ,IF3 Update Enabled Bit[27]" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 25. " [26] ,IF3 Update Enabled Bit[26]" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " [25] ,IF3 Update Enabled Bit[25]" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 23. " [24] ,IF3 Update Enabled Bit[24]" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " [23] ,IF3 Update Enabled Bit[23]" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 21. " [22] ,IF3 Update Enabled Bit[22]" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " [21] ,IF3 Update Enabled Bit[21]" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 19. " [20] ,IF3 Update Enabled Bit[20]" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " [19] ,IF3 Update Enabled Bit[19]" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 17. " [18] ,IF3 Update Enabled Bit[18]" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " [17] ,IF3 Update Enabled Bit[17]" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 15. " [16] ,IF3 Update Enabled Bit[16]" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " [15] ,IF3 Update Enabled Bit[15]" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 13. " [14] ,IF3 Update Enabled Bit[14]" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " [13] ,IF3 Update Enabled Bit[13]" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 11. " [12] ,IF3 Update Enabled Bit[12]" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " [11] ,IF3 Update Enabled Bit[11]" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 9. " [10] ,IF3 Update Enabled Bit[10]" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " [9] ,IF3 Update Enabled Bit[9]" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 7. " [8] ,IF3 Update Enabled Bit[8]" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " [7] ,IF3 Update Enabled Bit[7]" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 5. " [6] ,IF3 Update Enabled Bit[6]" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " [5] ,IF3 Update Enabled Bit[5]" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 3. " [4] ,IF3 Update Enabled Bit[4]" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " [3] ,IF3 Update Enabled Bit[3]" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 1. " [2] ,IF3 Update Enabled Bit[2]" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [1] ,IF3 Update Enabled Bit[1]" "Disabled,Enabled"
|
|
line.long 0x04 "IF3UENA4_3,Update Enable 4_3 Register"
|
|
bitfld.long 0x04 31. " IF3UPDATEEN[64] ,IF3 Update Enabled Bit[64]" "Disabled,Enabled"
|
|
bitfld.long 0x04 30. " [63] ,IF3 Update Enabled Bit[63]" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x04 29. " [62] ,IF3 Update Enabled Bit[62]" "Disabled,Enabled"
|
|
bitfld.long 0x04 28. " [61] ,IF3 Update Enabled Bit[61]" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x04 27. " [60] ,IF3 Update Enabled Bit[60]" "Disabled,Enabled"
|
|
bitfld.long 0x04 26. " [59] ,IF3 Update Enabled Bit[59]" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x04 25. " [58] ,IF3 Update Enabled Bit[58]" "Disabled,Enabled"
|
|
bitfld.long 0x04 24. " [57] ,IF3 Update Enabled Bit[57]" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x04 23. " [56] ,IF3 Update Enabled Bit[56]" "Disabled,Enabled"
|
|
bitfld.long 0x04 22. " [55] ,IF3 Update Enabled Bit[55]" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x04 21. " [54] ,IF3 Update Enabled Bit[54]" "Disabled,Enabled"
|
|
bitfld.long 0x04 20. " [53] ,IF3 Update Enabled Bit[53]" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x04 19. " [52] ,IF3 Update Enabled Bit[52]" "Disabled,Enabled"
|
|
bitfld.long 0x04 18. " [51] ,IF3 Update Enabled Bit[51]" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x04 17. " [50] ,IF3 Update Enabled Bit[50]" "Disabled,Enabled"
|
|
bitfld.long 0x04 16. " [49] ,IF3 Update Enabled Bit[49]" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x04 15. " [48] ,IF3 Update Enabled Bit[48]" "Disabled,Enabled"
|
|
bitfld.long 0x04 14. " [47] ,IF3 Update Enabled Bit[47]" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x04 13. " [46] ,IF3 Update Enabled Bit[46]" "Disabled,Enabled"
|
|
bitfld.long 0x04 12. " [45] ,IF3 Update Enabled Bit[45]" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x04 11. " [44] ,IF3 Update Enabled Bit[44]" "Disabled,Enabled"
|
|
bitfld.long 0x04 10. " [43] ,IF3 Update Enabled Bit[43]" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x04 9. " [42] ,IF3 Update Enabled Bit[42]" "Disabled,Enabled"
|
|
bitfld.long 0x04 8. " [41] ,IF3 Update Enabled Bit[41]" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x04 7. " [40] ,IF3 Update Enabled Bit[40]" "Disabled,Enabled"
|
|
bitfld.long 0x04 6. " [39] ,IF3 Update Enabled Bit[39]" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x04 5. " [38] ,IF3 Update Enabled Bit[38]" "Disabled,Enabled"
|
|
bitfld.long 0x04 4. " [37] ,IF3 Update Enabled Bit[37]" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x04 3. " [36] ,IF3 Update Enabled Bit[36]" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " [35] ,IF3 Update Enabled Bit[35]" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x04 1. " [34] ,IF3 Update Enabled Bit[34]" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " [33] ,IF3 Update Enabled Bit[33]" "Disabled,Enabled"
|
|
line.long 0x08 "IF3UENA6_5,Update Enable 6_5 Register"
|
|
bitfld.long 0x08 31. " IF3UPDATEEN[96] ,IF3 Update Enabled Bit[96]" "Disabled,Enabled"
|
|
bitfld.long 0x08 30. " [95] ,IF3 Update Enabled Bit[95]" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x08 29. " [94] ,IF3 Update Enabled Bit[94]" "Disabled,Enabled"
|
|
bitfld.long 0x08 28. " [93] ,IF3 Update Enabled Bit[93]" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x08 27. " [92] ,IF3 Update Enabled Bit[92]" "Disabled,Enabled"
|
|
bitfld.long 0x08 26. " [91] ,IF3 Update Enabled Bit[91]" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x08 25. " [90] ,IF3 Update Enabled Bit[90]" "Disabled,Enabled"
|
|
bitfld.long 0x08 24. " [89] ,IF3 Update Enabled Bit[89]" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x08 23. " [88] ,IF3 Update Enabled Bit[88]" "Disabled,Enabled"
|
|
bitfld.long 0x08 22. " [87] ,IF3 Update Enabled Bit[87]" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x08 21. " [86] ,IF3 Update Enabled Bit[86]" "Disabled,Enabled"
|
|
bitfld.long 0x08 20. " [85] ,IF3 Update Enabled Bit[85]" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x08 19. " [84] ,IF3 Update Enabled Bit[84]" "Disabled,Enabled"
|
|
bitfld.long 0x08 18. " [83] ,IF3 Update Enabled Bit[83]" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x08 17. " [82] ,IF3 Update Enabled Bit[82]" "Disabled,Enabled"
|
|
bitfld.long 0x08 16. " [81] ,IF3 Update Enabled Bit[81]" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x08 15. " [80] ,IF3 Update Enabled Bit[80]" "Disabled,Enabled"
|
|
bitfld.long 0x08 14. " [79] ,IF3 Update Enabled Bit[79]" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x08 13. " [78] ,IF3 Update Enabled Bit[78]" "Disabled,Enabled"
|
|
bitfld.long 0x08 12. " [77] ,IF3 Update Enabled Bit[77]" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x08 11. " [76] ,IF3 Update Enabled Bit[76]" "Disabled,Enabled"
|
|
bitfld.long 0x08 10. " [75] ,IF3 Update Enabled Bit[75]" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x08 9. " [74] ,IF3 Update Enabled Bit[74]" "Disabled,Enabled"
|
|
bitfld.long 0x08 8. " [73] ,IF3 Update Enabled Bit[73]" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x08 7. " [72] ,IF3 Update Enabled Bit[72]" "Disabled,Enabled"
|
|
bitfld.long 0x08 6. " [71] ,IF3 Update Enabled Bit[71]" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x08 5. " [70] ,IF3 Update Enabled Bit[70]" "Disabled,Enabled"
|
|
bitfld.long 0x08 4. " [69] ,IF3 Update Enabled Bit[69]" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x08 3. " [68] ,IF3 Update Enabled Bit[68]" "Disabled,Enabled"
|
|
bitfld.long 0x08 2. " [67] ,IF3 Update Enabled Bit[67]" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x08 1. " [66] ,IF3 Update Enabled Bit[66]" "Disabled,Enabled"
|
|
bitfld.long 0x08 0. " [65] ,IF3 Update Enabled Bit[65]" "Disabled,Enabled"
|
|
line.long 0x0C "IF3UENA8_7,Update Enable 8_7 Register"
|
|
bitfld.long 0x0C 31. " IF3UPDATEEN[128] ,IF3 Update Enabled Bit[128]" "Disabled,Enabled"
|
|
bitfld.long 0x0C 30. " [127] ,IF3 Update Enabled Bit[127]" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x0C 29. " [126] ,IF3 Update Enabled Bit[126]" "Disabled,Enabled"
|
|
bitfld.long 0x0C 28. " [125] ,IF3 Update Enabled Bit[125]" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x0C 27. " [124] ,IF3 Update Enabled Bit[124]" "Disabled,Enabled"
|
|
bitfld.long 0x0C 26. " [123] ,IF3 Update Enabled Bit[123]" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x0C 25. " [122] ,IF3 Update Enabled Bit[122]" "Disabled,Enabled"
|
|
bitfld.long 0x0C 24. " [121] ,IF3 Update Enabled Bit[121]" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x0C 23. " [120] ,IF3 Update Enabled Bit[120]" "Disabled,Enabled"
|
|
bitfld.long 0x0C 22. " [119] ,IF3 Update Enabled Bit[119]" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x0C 21. " [118] ,IF3 Update Enabled Bit[118]" "Disabled,Enabled"
|
|
bitfld.long 0x0C 20. " [117] ,IF3 Update Enabled Bit[117]" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x0C 19. " [116] ,IF3 Update Enabled Bit[116]" "Disabled,Enabled"
|
|
bitfld.long 0x0C 18. " [115] ,IF3 Update Enabled Bit[115]" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x0C 17. " [114] ,IF3 Update Enabled Bit[114]" "Disabled,Enabled"
|
|
bitfld.long 0x0C 16. " [113] ,IF3 Update Enabled Bit[113]" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x0C 15. " [112] ,IF3 Update Enabled Bit[112]" "Disabled,Enabled"
|
|
bitfld.long 0x0C 14. " [111] ,IF3 Update Enabled Bit[111]" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x0C 13. " [110] ,IF3 Update Enabled Bit[110]" "Disabled,Enabled"
|
|
bitfld.long 0x0C 12. " [109] ,IF3 Update Enabled Bit[109]" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x0C 11. " [108] ,IF3 Update Enabled Bit[108]" "Disabled,Enabled"
|
|
bitfld.long 0x0C 10. " [107] ,IF3 Update Enabled Bit[107]" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x0C 9. " [106] ,IF3 Update Enabled Bit[106]" "Disabled,Enabled"
|
|
bitfld.long 0x0C 8. " [105] ,IF3 Update Enabled Bit[105]" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x0C 7. " [104] ,IF3 Update Enabled Bit[104]" "Disabled,Enabled"
|
|
bitfld.long 0x0C 6. " [103] ,IF3 Update Enabled Bit[103]" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x0C 5. " [102] ,IF3 Update Enabled Bit[102]" "Disabled,Enabled"
|
|
bitfld.long 0x0C 4. " [101] ,IF3 Update Enabled Bit[101]" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x0C 3. " [100] ,IF3 Update Enabled Bit[100]" "Disabled,Enabled"
|
|
bitfld.long 0x0C 2. " [99] ,IF3 Update Enabled Bit[99]" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x0C 1. " [98] ,IF3 Update Enabled Bit[98]" "Disabled,Enabled"
|
|
bitfld.long 0x0C 0. " [97] ,IF3 Update Enabled Bit[97]" "Disabled,Enabled"
|
|
newline
|
|
group.long 0x1E0++0x03
|
|
line.long 0x0 "IOCTRLTX,TX IO Control Register"
|
|
sif (cpu()!="TMS470MF031"&&cpu()!="TMS470MF042"&&cpu()!="TMS470MF066"&&cpu()!=("TMS570LS10116-ZWT")&&cpu()!=("TMS570LS10216-ZWT")&&cpu()!=("TMS570LS10106-ZWT")&&cpu()!=("TMS570LS10206-ZWT")&&cpu()!=("TMS570LS10116-PGE")&&cpu()!=("TMS570LS10216-PGE")&&cpu()!=("TMS570LS10106-PGE")&&cpu()!=("TMS570LS10206-PGE")&&cpu()!=("TMS570LC4357")&&cpu()!=("TMS570LS0332")&&cpu()!=("TMS570LS0432")&&!cpuis("TMS570LS1114*")&&!cpuis("TMS570LS1115*")&&!cpuis("TMS570LS1224*")&&!cpuis("TMS570LS1225*")&&!cpuis("TMS570LS1227*")&&!cpuis("TMS570LS21*")&&!cpuis("TMS570LS31*")&&!cpuis("TMS570LS0232")&&!cpuis("TMS570LS0714*")&&!cpuis("TMS570LS0914*"))
|
|
bitfld.long 0x00 19. " SR ,Slew Rate Selection of Output Driver" "Normal,Slow"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 18. " PU ,Selection of Pull Direction" "Pull down,Pull up"
|
|
bitfld.long 0x00 17. " PD ,Pull Functionality Disable" "No,Yes"
|
|
bitfld.long 0x00 16. " OD ,Open Drain Mode" "Push pull,Open Drain"
|
|
bitfld.long 0x00 3. " FUNC ,Functionality of Pin" "General,CAN"
|
|
newline
|
|
bitfld.long 0x00 2. " DIR ,Direction of Pin" "Input,Output"
|
|
bitfld.long 0x00 1. " OUT ,Value to Drive to Pin if Configured for I/O" "Low,High"
|
|
bitfld.long 0x00 0. " IN ,Value of Pin" "Low,High"
|
|
group.long 0x1E4++0x03
|
|
line.long 0x0 "IOCTRLRX,RX IO Control Register"
|
|
sif (cpu()!="TMS470MF031"&&cpu()!="TMS470MF042"&&cpu()!="TMS470MF066"&&cpu()!=("TMS570LS10116-ZWT")&&cpu()!=("TMS570LS10216-ZWT")&&cpu()!=("TMS570LS10106-ZWT")&&cpu()!=("TMS570LS10206-ZWT")&&cpu()!=("TMS570LS10116-PGE")&&cpu()!=("TMS570LS10216-PGE")&&cpu()!=("TMS570LS10106-PGE")&&cpu()!=("TMS570LS10206-PGE")&&cpu()!=("TMS570LC4357")&&cpu()!=("TMS570LS0332")&&cpu()!=("TMS570LS0432")&&!cpuis("TMS570LS1114*")&&!cpuis("TMS570LS1115*")&&!cpuis("TMS570LS1224*")&&!cpuis("TMS570LS1225*")&&!cpuis("TMS570LS1227*")&&!cpuis("TMS570LS21*")&&!cpuis("TMS570LS31*")&&!cpuis("TMS570LS0232")&&!cpuis("TMS570LS0714*")&&!cpuis("TMS570LS0914*"))
|
|
bitfld.long 0x00 19. " SR ,Slew Rate Selection of Output Driver" "Normal,Slow"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 18. " PU ,Selection of Pull Direction" "Pull down,Pull up"
|
|
bitfld.long 0x00 17. " PD ,Pull Functionality Disable" "No,Yes"
|
|
bitfld.long 0x00 16. " OD ,Open Drain Mode" "Push pull,Open Drain"
|
|
bitfld.long 0x00 3. " FUNC ,Functionality of Pin" "General,CAN"
|
|
newline
|
|
bitfld.long 0x00 2. " DIR ,Direction of Pin" "Input,Output"
|
|
bitfld.long 0x00 1. " OUT ,Value to Drive to Pin if Configured for I/O" "Low,High"
|
|
bitfld.long 0x00 0. " IN ,Value of Pin" "Low,High"
|
|
sif cpuis("TMS570LS0232")||cpuis("TMS570LS0714*")||cpuis("TMS570LS0914*")
|
|
endian.le
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
sif cpuis("TMS570LS0714*")||cpuis("TMS570LS0914*")
|
|
tree "DCAN3"
|
|
base ad:0xFFF7E000
|
|
sif cpuis("TMS570LS0232")||cpuis("TMS570LS0714*")||cpuis("TMS570LS0914*")
|
|
endian.be
|
|
endif
|
|
width 12.
|
|
group.long 0x00++0x3
|
|
line.long 0x0 "CTRL,Config Register"
|
|
bitfld.long 0x00 25. " WUBA ,Automatic Wake Up on Bus Activity When in Local Power Down Mode" "Not detected,Detected"
|
|
bitfld.long 0x00 24. " PDR ,Request for Local Low Power Down Mode" "Not requested,Power down"
|
|
sif (cpu()!=("TMS570LS0332")&&cpu()!=("TMS570LS0432")&&!cpuis("TMS570LS0232"))
|
|
newline
|
|
bitfld.long 0x00 20. " DE3 ,DMA Enable for IF3" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 19. " DE2 ,DMA Enable for IF2" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " DE1 ,DMA Enable for IF1" "Disabled,Enabled"
|
|
endif
|
|
newline
|
|
bitfld.long 0x00 17. " IE1 ,DCAN1INT Interrupt Enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 16. " INITDBG ,Internal Init State While Debug Access Mode" "No debug,Debug"
|
|
bitfld.long 0x00 15. " SWR ,SW Reset Enable" "No reset,Reset"
|
|
bitfld.long 0x00 10.--13. " PMD ,Parity on/off" "Enabled,Enabled,Enabled,Enabled,Enabled,Disabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 9. " ABO ,Auto Bus On Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " IDS ,Interruption Debug Support Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " TEST ,Test Mode Enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 6. " CCE ,Configuration Change Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " DAR ,Disable Automatic Retransmission" "No,Yes"
|
|
bitfld.long 0x00 3. " EIE ,Error Interrupt Enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 2. " SIE ,Status Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " IE ,DCAN0INT Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " INIT ,Initialization" "Disabled,Enabled"
|
|
sif (cpu()=="TMS470MF031"||cpu()=="TMS470MF042"||cpu()=="TMS470MF066"||cpu()==("TMS570LS10116-ZWT")||cpu()==("TMS570LS10216-ZWT")||cpu()==("TMS570LS10106-ZWT")||cpu()==("TMS570LS10206-ZWT")||cpu()==("TMS570LS10116-PGE")||cpu()==("TMS570LS10216-PGE")||cpu()==("TMS570LS10106-PGE")||cpu()==("TMS570LS10206-PGE")||cpu()==("TMS570LC4357")||cpuis("TMS570LS1114*")||cpuis("TMS570LS1115*")||cpuis("TMS570LS1224*")||cpuis("TMS570LS1225*")||cpuis("TMS570LS1227*"))
|
|
group.long 0x04++0x3
|
|
line.long 0x0 "ES,Error and Status Register"
|
|
rbitfld.long 0x00 10. " PDA ,Local Power Down Mode Acknowledge" "Not in,Is in"
|
|
rbitfld.long 0x00 9. " WAKEUPPND ,Wake Up Pending" "No requested,Requested"
|
|
rbitfld.long 0x00 8. " PER ,Parity Error Detected" "No error,Error"
|
|
newline
|
|
rbitfld.long 0x00 7. " BOFF ,Bus-Off State" "Not in,In"
|
|
rbitfld.long 0x00 6. " EWARN ,Warning state" "<96,>96"
|
|
rbitfld.long 0x00 5. " EPASS ,Error Passive State" "CAN Bus,Passive"
|
|
newline
|
|
bitfld.long 0x00 4. " RXOK ,Received a Message successfully" "No,Yes"
|
|
bitfld.long 0x00 3. " TXOK ,Transmitted a Message successfully" "No,Yes"
|
|
bitfld.long 0x00 0.--2. " LEC ,Last Error Code" "No error,Stuff,Form,Ack,Bit1,Bit0,CRC,No CAN"
|
|
elif !cpuis("TMS570LS3137-EP")
|
|
hgroup.long 0x04++0x3
|
|
hide.long 0x0 "STAT,Status Register"
|
|
in
|
|
else
|
|
if (((per.l.be(ad:0xFFF7E000))&0x100)==0x100)
|
|
group.long 0x04++0x3
|
|
line.long 0x0 "ES,Error and Status Register"
|
|
rbitfld.long 0x00 10. " PDA ,Local Power Down Mode Acknowledge" "Not in,Is in"
|
|
rbitfld.long 0x00 9. " WAKEUPPND ,Wake Up Pending" "No requested,Requested"
|
|
rbitfld.long 0x00 8. " PER ,Parity Error Detected" "No error,Error"
|
|
newline
|
|
rbitfld.long 0x00 7. " BOFF ,Bus-Off State" "Not in,In"
|
|
rbitfld.long 0x00 6. " EWARN ,Warning state" "<96,>96"
|
|
rbitfld.long 0x00 5. " EPASS ,Error Passive State" "CAN Bus,Passive"
|
|
newline
|
|
bitfld.long 0x00 4. " RXOK ,Received a Message successfully" "No,Yes"
|
|
bitfld.long 0x00 3. " TXOK ,Transmitted a Message successfully" "No,Yes"
|
|
bitfld.long 0x00 0.--2. " LEC ,Last Error Code" "No error,Stuff,Form,Ack,Bit1,Bit0,CRC,No CAN"
|
|
else
|
|
hgroup.long 0x04++0x3
|
|
hide.long 0x0 "ES,Error and Status Register"
|
|
in
|
|
endif
|
|
endif
|
|
rgroup.long 0x08++0x3
|
|
line.long 0x0 "ERRC,Error Counter Register"
|
|
bitfld.long 0x00 15. " RP ,Receive Error Passive" "Below,Reached"
|
|
hexmask.long.byte 0x00 8.--14. 1. " REC ,Receive Error Counter"
|
|
hexmask.long.byte 0x00 0.--7. 1. " TEC ,Transmit Error Counter"
|
|
sif cpuis("TMS570LS0232")||cpuis("TMS570LS0714*")||cpuis("TMS570LS0914*")
|
|
if (((per.l.be(ad:0xFFF7E000))&0x41)==0x41)
|
|
group.long 0x0C++0x3
|
|
line.long 0x0 "BTBRP,Bit Timing_BRP Extension Register"
|
|
bitfld.long 0x00 16.--19. " BRPE ,Baud Rate Prescaler Extension" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--14. " TSEG2 ,The Time Segment After the Sample Point" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 8.--11. " TSEG1 ,The Time Segment Before the Sample Point" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 6.--7. " SJW ,Synchronization Jump Width" "0,1,2,3"
|
|
bitfld.long 0x00 0.--5. " BRP ,Baud Rate Prescaler" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
else
|
|
rgroup.long 0x0C++0x3
|
|
line.long 0x0 "BTBRP,Bit Timing_BRP Extension Register"
|
|
bitfld.long 0x00 16.--19. " BRPE ,Baud Rate Prescaler Extension" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--14. " TSEG2 ,The Time Segment After the Sample Point" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 8.--11. " TSEG1 ,The Time Segment Before the Sample Point" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 6.--7. " SJW ,Synchronization Jump Width" "0,1,2,3"
|
|
bitfld.long 0x00 0.--5. " BRP ,Baud Rate Prescaler" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
endif
|
|
else
|
|
group.long 0x0C++0x3
|
|
line.long 0x0 "BTBRP,Bit Timing_BRP Extension Register"
|
|
bitfld.long 0x00 16.--19. " BRPE ,Baud Rate Prescaler Extension" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--14. " TSEG2 ,The Time Segment After the Sample Point" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 8.--11. " TSEG1 ,The Time Segment Before the Sample Point" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 6.--7. " SJW ,Synchronization Jump Width" "0,1,2,3"
|
|
bitfld.long 0x00 0.--5. " BRP ,Baud Rate Prescaler" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
endif
|
|
rgroup.long 0x10++0x3
|
|
line.long 0x0 "INTR,Interrupt Register"
|
|
hexmask.long.byte 0x00 16.--23. 1. " INT1ID[7-0] ,Interrupt 1 Identifier"
|
|
hexmask.long.word 0x00 0.--15. 1. " INTID[15-0] ,Interrupt Identifier"
|
|
sif cpuis("TMS570LS0232")||cpuis("TMS570LS0714*")||cpuis("TMS570LS0914*")
|
|
if (((per.l.be(ad:0xFFF7E000))&0x41)==0x41)
|
|
group.long 0x14++0x3
|
|
line.long 0x0 "TEST,Test Register"
|
|
bitfld.long 0x00 9. " RDA ,RAM Direct Access Enable" "Normal,Enabled"
|
|
bitfld.long 0x00 8. " EXL ,External Loop Back Mode" "Normal,Enabled"
|
|
bitfld.long 0x00 7. " RX ,Receive Pin" "Dominant,Recessive"
|
|
newline
|
|
bitfld.long 0x00 5.--6. " TX1-0 ,Control of CAN_TX pin" "Normal,Sample point,Dominant,Recessive"
|
|
bitfld.long 0x00 4. " LBACK ,Loop Back Mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " SILENT ,Silent Mode" "Normal,Enabled"
|
|
else
|
|
rgroup.long 0x14++0x3
|
|
line.long 0x0 "TEST,Test Register"
|
|
bitfld.long 0x00 9. " RDA ,RAM Direct Access Enable" "Normal,Enabled"
|
|
bitfld.long 0x00 8. " EXL ,External Loop Back Mode" "Normal,Enabled"
|
|
bitfld.long 0x00 7. " RX ,Receive Pin" "Dominant,Recessive"
|
|
newline
|
|
bitfld.long 0x00 5.--6. " TX1-0 ,Control of CAN_TX pin" "Normal,Sample point,Dominant,Recessive"
|
|
bitfld.long 0x00 4. " LBACK ,Loop Back Mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " SILENT ,Silent Mode" "Normal,Enabled"
|
|
endif
|
|
elif !cpuis("TMS570LS3137-EP")
|
|
group.long 0x14++0x3
|
|
line.long 0x0 "TEST,Test Register"
|
|
bitfld.long 0x00 9. " RDA ,RAM Direct Access Enable" "Normal,Enabled"
|
|
bitfld.long 0x00 8. " EXL ,External Loop Back Mode" "Normal,Enabled"
|
|
bitfld.long 0x00 7. " RX ,Receive Pin" "Dominant,Recessive"
|
|
newline
|
|
sif (cpu()=="TMS470MF031"||cpu()=="TMS470MF042"||cpu()=="TMS470MF066"||cpu()==("TMS570LS10116-ZWT")||cpu()==("TMS570LS10216-ZWT")||cpu()==("TMS570LS10106-ZWT")||cpu()==("TMS570LS10206-ZWT")||cpu()==("TMS570LS10116-PGE")||cpu()==("TMS570LS10216-PGE")||cpu()==("TMS570LS10106-PGE")||cpu()==("TMS570LS10206-PGE")||cpu()==("TMS570LC4357")||cpu()==("TMS570LS0332")||cpu()==("TMS570LS0432")||cpuis("TMS570LS1114*")||cpuis("TMS570LS1115*")||cpuis("TMS570LS1224*")||cpuis("TMS570LS1225*")||cpuis("TMS570LS1227*")||cpuis("TMS570LS21*")||cpuis("TMS570LS31*")||cpuis("TMS570LS0232")||cpuis("TMS570LS0714*")||cpuis("TMS570LS0914*"))
|
|
bitfld.long 0x00 5.--6. " TX1-0 ,Control of CAN_TX pin" "Normal,Sample point,Dominant,Recessive"
|
|
else
|
|
bitfld.long 0x00 5.--6. " TX1-0 ,Control of CAN_TX pin" "Reset,Sample point,Dominant,Recessive"
|
|
endif
|
|
bitfld.long 0x00 4. " LBACK ,Loop Back Mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " SILENT ,Silent Mode" "Normal,Enabled"
|
|
else
|
|
if (((per.l.be(ad:0xFFF7E000))&0x80)==0x80)
|
|
group.long 0x14++0x3
|
|
line.long 0x0 "TEST,Test Register"
|
|
bitfld.long 0x00 9. " RDA ,RAM Direct Access Enable" "Normal,Enabled"
|
|
bitfld.long 0x00 8. " EXL ,External Loop Back Mode" "Normal,Enabled"
|
|
bitfld.long 0x00 7. " RX ,Receive Pin" "Dominant,Recessive"
|
|
newline
|
|
bitfld.long 0x00 5.--6. " TX1-0 ,Control of CAN_TX pin" "Normal,Sample point,Dominant,Recessive"
|
|
bitfld.long 0x00 4. " LBACK ,Loop Back Mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " SILENT ,Silent Mode" "Normal,Enabled"
|
|
else
|
|
rgroup.long 0x14++0x3
|
|
line.long 0x0 "TEST,Test Register"
|
|
bitfld.long 0x00 9. " RDA ,RAM Direct Access Enable" "Normal,Enabled"
|
|
bitfld.long 0x00 8. " EXL ,External Loop Back Mode" "Normal,Enabled"
|
|
bitfld.long 0x00 7. " RX ,Receive Pin" "Dominant,Recessive"
|
|
newline
|
|
bitfld.long 0x00 5.--6. " TX1-0 ,Control of CAN_TX pin" "Normal,Sample point,Dominant,Recessive"
|
|
bitfld.long 0x00 4. " LBACK ,Loop Back Mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " SILENT ,Silent Mode" "Normal,Enabled"
|
|
endif
|
|
endif
|
|
rgroup.long 0x1C++0x3
|
|
line.long 0x0 "PERR,Parity Error Code Register"
|
|
bitfld.long 0x00 8.--10. " WORD_NUMBER ,Word Number" ",1,2,3,4,5,?..."
|
|
hexmask.long.byte 0x00 0.--7. 1. " MESSAGE_NUMBER ,Message Number"
|
|
sif (cpu()=="TMS470MF031"||cpu()=="TMS470MF042"||cpu()=="TMS470MF066"||cpuis("TMS570LS0232")||cpuis("TMS570LS0714*")||cpuis("TMS570LS0914*"))
|
|
rgroup.long 0x20++0x3
|
|
line.long 0x00 "REL,DCAN Core Release Register"
|
|
bitfld.long 0x00 28.--31. " REL ,Core Release" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 24.--27. " STEP ,Step of Core Release" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 20.--23. " SUBSTEP ,Substep of Core Release" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " YEAR ,Design Time Stamp - Year" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. " MON ,Design Time Stamp - Month"
|
|
hexmask.long.byte 0x00 0.--7. 1. " DAY ,Design Time Stamp - Day"
|
|
endif
|
|
width 19.
|
|
sif (cpu()=="TMS570LC4357")
|
|
group.long 0x24++0x0B
|
|
line.long 0x00 "DCAN_ECCDIAG,ECC Diagnostic Register"
|
|
bitfld.long 0x00 0.--3. " ECCDIAG , SECDED diagnostic mode enable/disable" ",,,,,Enabled,,,,,Disabled,?..."
|
|
line.long 0x04 "DCAN_ECCDIAG_STAT, ECC Diagnostic Status Register"
|
|
eventfld.long 0x04 8. " DEFLG_DIAG , Double bit error diagnostic" "No error,Error"
|
|
eventfld.long 0x04 0. " SEFLG_DIAG , Single bit error diagnostic" "No error,Error"
|
|
line.long 0x08 "DCAN_ECC_CS, ECC Control and Status Register"
|
|
bitfld.long 0x08 24.--27. " SBE_EVT_EN , Single bit error event" "Enabled,Enabled,Enabled,Enabled,Enabled,Disabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled"
|
|
bitfld.long 0x08 16.--19. " ECCMODE , Single bit error correction" "Enabled,Enabled,Enabled,Enabled,Enabled,Disabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled"
|
|
eventfld.long 0x08 8. " DEFLG , Double bit error flag" "No error,Error"
|
|
eventfld.long 0x08 0. " SEFLG , Single bit error flag" "No error,Error"
|
|
rgroup.long 0x30++0x03
|
|
line.long 0x00 "DCAN_ECC_SERR, ECC Single Bit Error Code Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " Message_Number , Message object number where ECC single bit error has been detected"
|
|
endif
|
|
width 12.
|
|
group.long 0x80++0x03
|
|
line.long 0x00 "ABOT,Auto Bus On Time"
|
|
rgroup.long 0x84++0x4F
|
|
line.long 0x00 "TRREQ,Transmission Request X"
|
|
bitfld.long 0x00 14.--15. " TXRQSTREG8 ,Transmission Request 8" "0,1,2,3"
|
|
bitfld.long 0x00 12.--13. " TXRQSTREG7 ,Transmission Request 7" "0,1,2,3"
|
|
bitfld.long 0x00 10.--11. " TXRQSTREG6 ,Transmission Request 6" "0,1,2,3"
|
|
bitfld.long 0x00 8.--9. " TXRQSTREG5 ,Transmission Request 5" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 6.--7. " TXRQSTREG4 ,Transmission Request 4" "0,1,2,3"
|
|
bitfld.long 0x00 4.--5. " TXRQSTREG3 ,Transmission Request 3" "0,1,2,3"
|
|
bitfld.long 0x00 2.--3. " TXRQSTREG2 ,Transmission Request 2" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. " TXRQSTREG1 ,Transmission Request 1" "0,1,2,3"
|
|
line.long 0x04 "TRREQ12,Transmission Request 1-2"
|
|
bitfld.long 0x04 31. " TXRQST[32] ,Transmission Request Bits[32]" "Not requested,Requested"
|
|
bitfld.long 0x04 30. " [31] ,Transmission Request Bits[31]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x04 29. " [30] ,Transmission Request Bits[30]" "Not requested,Requested"
|
|
bitfld.long 0x04 28. " [29] ,Transmission Request Bits[29]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x04 27. " [28] ,Transmission Request Bits[28]" "Not requested,Requested"
|
|
bitfld.long 0x04 26. " [27] ,Transmission Request Bits[27]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x04 25. " [26] ,Transmission Request Bits[26]" "Not requested,Requested"
|
|
bitfld.long 0x04 24. " [25] ,Transmission Request Bits[25]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x04 23. " [24] ,Transmission Request Bits[24]" "Not requested,Requested"
|
|
bitfld.long 0x04 22. " [23] ,Transmission Request Bits[23]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x04 21. " [22] ,Transmission Request Bits[22]" "Not requested,Requested"
|
|
bitfld.long 0x04 20. " [21] ,Transmission Request Bits[21]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x04 19. " [20] ,Transmission Request Bits[20]" "Not requested,Requested"
|
|
bitfld.long 0x04 18. " [19] ,Transmission Request Bits[19]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x04 17. " [18] ,Transmission Request Bits[18]" "Not requested,Requested"
|
|
bitfld.long 0x04 16. " [17] ,Transmission Request Bits[17]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x04 15. " [16] ,Transmission Request Bits[16]" "Not requested,Requested"
|
|
bitfld.long 0x04 14. " [15] ,Transmission Request Bits[15]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x04 13. " [14] ,Transmission Request Bits[14]" "Not requested,Requested"
|
|
bitfld.long 0x04 12. " [13] ,Transmission Request Bits[13]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x04 11. " [12] ,Transmission Request Bits[12]" "Not requested,Requested"
|
|
bitfld.long 0x04 10. " [11] ,Transmission Request Bits[11]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x04 9. " [10] ,Transmission Request Bits[10]" "Not requested,Requested"
|
|
bitfld.long 0x04 8. " [9] ,Transmission Request Bits[9]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x04 7. " [8] ,Transmission Request Bits[8]" "Not requested,Requested"
|
|
bitfld.long 0x04 6. " [7] ,Transmission Request Bits[7]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x04 5. " [6] ,Transmission Request Bits[6]" "Not requested,Requested"
|
|
bitfld.long 0x04 4. " [5] ,Transmission Request Bits[5]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x04 3. " [4] ,Transmission Request Bits[4]" "Not requested,Requested"
|
|
bitfld.long 0x04 2. " [3] ,Transmission Request Bits[3]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x04 1. " [2] ,Transmission Request Bits[2]" "Not requested,Requested"
|
|
bitfld.long 0x04 0. " [1] ,Transmission Request Bits[1]" "Not requested,Requested"
|
|
line.long 0x08 "TRREQ34,Transmission Request 3-4"
|
|
bitfld.long 0x08 31. " TXRQST[64] ,Transmission Request Bits[64]" "Not requested,Requested"
|
|
bitfld.long 0x08 30. " [63] ,Transmission Request Bits[63]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x08 29. " [62] ,Transmission Request Bits[62]" "Not requested,Requested"
|
|
bitfld.long 0x08 28. " [61] ,Transmission Request Bits[61]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x08 27. " [60] ,Transmission Request Bits[60]" "Not requested,Requested"
|
|
bitfld.long 0x08 26. " [59] ,Transmission Request Bits[59]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x08 25. " [58] ,Transmission Request Bits[58]" "Not requested,Requested"
|
|
bitfld.long 0x08 24. " [57] ,Transmission Request Bits[57]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x08 23. " [56] ,Transmission Request Bits[56]" "Not requested,Requested"
|
|
bitfld.long 0x08 22. " [55] ,Transmission Request Bits[55]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x08 21. " [54] ,Transmission Request Bits[54]" "Not requested,Requested"
|
|
bitfld.long 0x08 20. " [53] ,Transmission Request Bits[53]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x08 19. " [52] ,Transmission Request Bits[52]" "Not requested,Requested"
|
|
bitfld.long 0x08 18. " [51] ,Transmission Request Bits[51]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x08 17. " [50] ,Transmission Request Bits[50]" "Not requested,Requested"
|
|
bitfld.long 0x08 16. " [49] ,Transmission Request Bits[49]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x08 15. " [48] ,Transmission Request Bits[48]" "Not requested,Requested"
|
|
bitfld.long 0x08 14. " [47] ,Transmission Request Bits[47]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x08 13. " [46] ,Transmission Request Bits[46]" "Not requested,Requested"
|
|
bitfld.long 0x08 12. " [45] ,Transmission Request Bits[45]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x08 11. " [44] ,Transmission Request Bits[44]" "Not requested,Requested"
|
|
bitfld.long 0x08 10. " [43] ,Transmission Request Bits[43]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x08 9. " [42] ,Transmission Request Bits[42]" "Not requested,Requested"
|
|
bitfld.long 0x08 8. " [41] ,Transmission Request Bits[41]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x08 7. " [40] ,Transmission Request Bits[40]" "Not requested,Requested"
|
|
bitfld.long 0x08 6. " [39] ,Transmission Request Bits[39]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x08 5. " [38] ,Transmission Request Bits[38]" "Not requested,Requested"
|
|
bitfld.long 0x08 4. " [37] ,Transmission Request Bits[37]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x08 3. " [36] ,Transmission Request Bits[36]" "Not requested,Requested"
|
|
bitfld.long 0x08 2. " [35] ,Transmission Request Bits[35]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x08 1. " [34] ,Transmission Request Bits[34]" "Not requested,Requested"
|
|
bitfld.long 0x08 0. " [33] ,Transmission Request Bits[33]" "Not requested,Requested"
|
|
line.long 0x0C "TRREQ56,Transmission Request 5-6"
|
|
bitfld.long 0x0C 31. " TXRQST[96] ,Transmission Request Bits[96]" "Not requested,Requested"
|
|
bitfld.long 0x0C 30. " [95] ,Transmission Request Bits[95]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x0C 29. " [94] ,Transmission Request Bits[94]" "Not requested,Requested"
|
|
bitfld.long 0x0C 28. " [93] ,Transmission Request Bits[93]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x0C 27. " [92] ,Transmission Request Bits[92]" "Not requested,Requested"
|
|
bitfld.long 0x0C 26. " [91] ,Transmission Request Bits[91]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x0C 25. " [90] ,Transmission Request Bits[90]" "Not requested,Requested"
|
|
bitfld.long 0x0C 24. " [89] ,Transmission Request Bits[89]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x0C 23. " [88] ,Transmission Request Bits[88]" "Not requested,Requested"
|
|
bitfld.long 0x0C 22. " [87] ,Transmission Request Bits[87]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x0C 21. " [86] ,Transmission Request Bits[86]" "Not requested,Requested"
|
|
bitfld.long 0x0C 20. " [85] ,Transmission Request Bits[85]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x0C 19. " [84] ,Transmission Request Bits[84]" "Not requested,Requested"
|
|
bitfld.long 0x0C 18. " [83] ,Transmission Request Bits[83]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x0C 17. " [82] ,Transmission Request Bits[82]" "Not requested,Requested"
|
|
bitfld.long 0x0C 16. " [81] ,Transmission Request Bits[81]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x0C 15. " [80] ,Transmission Request Bits[80]" "Not requested,Requested"
|
|
bitfld.long 0x0C 14. " [79] ,Transmission Request Bits[79]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x0C 13. " [78] ,Transmission Request Bits[78]" "Not requested,Requested"
|
|
bitfld.long 0x0C 12. " [77] ,Transmission Request Bits[77]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x0C 11. " [76] ,Transmission Request Bits[76]" "Not requested,Requested"
|
|
bitfld.long 0x0C 10. " [75] ,Transmission Request Bits[75]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x0C 9. " [74] ,Transmission Request Bits[74]" "Not requested,Requested"
|
|
bitfld.long 0x0C 8. " [73] ,Transmission Request Bits[73]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x0C 7. " [72] ,Transmission Request Bits[72]" "Not requested,Requested"
|
|
bitfld.long 0x0C 6. " [71] ,Transmission Request Bits[71]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x0C 5. " [70] ,Transmission Request Bits[70]" "Not requested,Requested"
|
|
bitfld.long 0x0C 4. " [69] ,Transmission Request Bits[69]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x0C 3. " [68] ,Transmission Request Bits[68]" "Not requested,Requested"
|
|
bitfld.long 0x0C 2. " [67] ,Transmission Request Bits[67]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x0C 1. " [66] ,Transmission Request Bits[66]" "Not requested,Requested"
|
|
bitfld.long 0x0C 0. " [65] ,Transmission Request Bits[65]" "Not requested,Requested"
|
|
line.long 0x10 "TRREQ78,Transmission Request 7-8"
|
|
bitfld.long 0x10 31. " TXRQST[128] ,Transmission Request Bits[128]" "Not requested,Requested"
|
|
bitfld.long 0x10 30. " [127] ,Transmission Request Bits[127]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x10 29. " [126] ,Transmission Request Bits[126]" "Not requested,Requested"
|
|
bitfld.long 0x10 28. " [125] ,Transmission Request Bits[125]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x10 27. " [124] ,Transmission Request Bits[124]" "Not requested,Requested"
|
|
bitfld.long 0x10 26. " [123] ,Transmission Request Bits[123]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x10 25. " [122] ,Transmission Request Bits[122]" "Not requested,Requested"
|
|
bitfld.long 0x10 24. " [121] ,Transmission Request Bits[121]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x10 23. " [120] ,Transmission Request Bits[120]" "Not requested,Requested"
|
|
bitfld.long 0x10 22. " [119] ,Transmission Request Bits[119]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x10 21. " [118] ,Transmission Request Bits[118]" "Not requested,Requested"
|
|
bitfld.long 0x10 20. " [117] ,Transmission Request Bits[117]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x10 19. " [116] ,Transmission Request Bits[116]" "Not requested,Requested"
|
|
bitfld.long 0x10 18. " [115] ,Transmission Request Bits[115]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x10 17. " [114] ,Transmission Request Bits[114]" "Not requested,Requested"
|
|
bitfld.long 0x10 16. " [113] ,Transmission Request Bits[113]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x10 15. " [112] ,Transmission Request Bits[112]" "Not requested,Requested"
|
|
bitfld.long 0x10 14. " [111] ,Transmission Request Bits[111]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x10 13. " [110] ,Transmission Request Bits[110]" "Not requested,Requested"
|
|
bitfld.long 0x10 12. " [109] ,Transmission Request Bits[109]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x10 11. " [108] ,Transmission Request Bits[108]" "Not requested,Requested"
|
|
bitfld.long 0x10 10. " [107] ,Transmission Request Bits[107]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x10 9. " [106] ,Transmission Request Bits[106]" "Not requested,Requested"
|
|
bitfld.long 0x10 8. " [105] ,Transmission Request Bits[105]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x10 7. " [104] ,Transmission Request Bits[104]" "Not requested,Requested"
|
|
bitfld.long 0x10 6. " [103] ,Transmission Request Bits[103]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x10 5. " [102] ,Transmission Request Bits[102]" "Not requested,Requested"
|
|
bitfld.long 0x10 4. " [101] ,Transmission Request Bits[101]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x10 3. " [100] ,Transmission Request Bits[100]" "Not requested,Requested"
|
|
bitfld.long 0x10 2. " [99] ,Transmission Request Bits[99]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x10 1. " [98] ,Transmission Request Bits[98]" "Not requested,Requested"
|
|
bitfld.long 0x10 0. " [97] ,Transmission Request Bits[97]" "Not requested,Requested"
|
|
line.long 0x14 "NEWDAT,New Data X"
|
|
bitfld.long 0x14 14.--15. " NEWDATREG8 ,New Data 8" "0,1,2,3"
|
|
bitfld.long 0x14 12.--13. " NEWDATREG7 ,New Data 7" "0,1,2,3"
|
|
bitfld.long 0x14 10.--11. " NEWDATREG6 ,New Data 6" "0,1,2,3"
|
|
bitfld.long 0x14 8.--9. " NEWDATREG5 ,New Data 5" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x14 6.--7. " NEWDATREG4 ,NEW DATA 4" "0,1,2,3"
|
|
bitfld.long 0x14 4.--5. " NEWDATREG3 ,New Data 3" "0,1,2,3"
|
|
bitfld.long 0x14 2.--3. " NEWDATREG2 ,New Data 2" "0,1,2,3"
|
|
bitfld.long 0x14 0.--1. " NEWDATREG1 ,New Data 1" "0,1,2,3"
|
|
line.long 0x18 "NEWDAT12,New Data 1-2"
|
|
bitfld.long 0x18 31. " NEWDAT[32] ,New Data Bit[32]" "Not requested,Requested"
|
|
bitfld.long 0x18 30. " [31] ,New Data Bit[31]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x18 29. " [30] ,New Data Bit[30]" "Not requested,Requested"
|
|
bitfld.long 0x18 28. " [29] ,New Data Bit[29]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x18 27. " [28] ,New Data Bit[28]" "Not requested,Requested"
|
|
bitfld.long 0x18 26. " [27] ,New Data Bit[27]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x18 25. " [26] ,New Data Bit[26]" "Not requested,Requested"
|
|
bitfld.long 0x18 24. " [25] ,New Data Bit[25]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x18 23. " [24] ,New Data Bit[24]" "Not requested,Requested"
|
|
bitfld.long 0x18 22. " [23] ,New Data Bit[23]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x18 21. " [22] ,New Data Bit[22]" "Not requested,Requested"
|
|
bitfld.long 0x18 20. " [21] ,New Data Bit[21]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x18 19. " [20] ,New Data Bit[20]" "Not requested,Requested"
|
|
bitfld.long 0x18 18. " [19] ,New Data Bit[19]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x18 17. " [18] ,New Data Bit[18]" "Not requested,Requested"
|
|
bitfld.long 0x18 16. " [17] ,New Data Bit[17]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x18 15. " [16] ,New Data Bit[16]" "Not requested,Requested"
|
|
bitfld.long 0x18 14. " [15] ,New Data Bit[15]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x18 13. " [14] ,New Data Bit[14]" "Not requested,Requested"
|
|
bitfld.long 0x18 12. " [13] ,New Data Bit[13]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x18 11. " [12] ,New Data Bit[12]" "Not requested,Requested"
|
|
bitfld.long 0x18 10. " [11] ,New Data Bit[11]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x18 9. " [10] ,New Data Bit[10]" "Not requested,Requested"
|
|
bitfld.long 0x18 8. " [9] ,New Data Bit[9]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x18 7. " [8] ,New Data Bit[8]" "Not requested,Requested"
|
|
bitfld.long 0x18 6. " [7] ,New Data Bit[7]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x18 5. " [6] ,New Data Bit[6]" "Not requested,Requested"
|
|
bitfld.long 0x18 4. " [5] ,New Data Bit[5]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x18 3. " [4] ,New Data Bit[4]" "Not requested,Requested"
|
|
bitfld.long 0x18 2. " [3] ,New Data Bit[3]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x18 1. " [2] ,New Data Bit[2]" "Not requested,Requested"
|
|
bitfld.long 0x18 0. " [1] ,New Data Bit[1]" "Not requested,Requested"
|
|
line.long 0x1C "NEWDAT34,New Data 3-4"
|
|
bitfld.long 0x1C 31. " NEWDAT[64] ,New Data Bit[64]" "Not requested,Requested"
|
|
bitfld.long 0x1C 30. " [63] ,New Data Bit[63]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x1C 29. " [62] ,New Data Bit[62]" "Not requested,Requested"
|
|
bitfld.long 0x1C 28. " [61] ,New Data Bit[61]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x1C 27. " [60] ,New Data Bit[60]" "Not requested,Requested"
|
|
bitfld.long 0x1C 26. " [59] ,New Data Bit[59]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x1C 25. " [58] ,New Data Bit[58]" "Not requested,Requested"
|
|
bitfld.long 0x1C 24. " [57] ,New Data Bit[57]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x1C 23. " [56] ,New Data Bit[56]" "Not requested,Requested"
|
|
bitfld.long 0x1C 22. " [55] ,New Data Bit[55]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x1C 21. " [54] ,New Data Bit[54]" "Not requested,Requested"
|
|
bitfld.long 0x1C 20. " [53] ,New Data Bit[53]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x1C 19. " [52] ,New Data Bit[52]" "Not requested,Requested"
|
|
bitfld.long 0x1C 18. " [51] ,New Data Bit[51]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x1C 17. " [50] ,New Data Bit[50]" "Not requested,Requested"
|
|
bitfld.long 0x1C 16. " [49] ,New Data Bit[49]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x1C 15. " [48] ,New Data Bit[48]" "Not requested,Requested"
|
|
bitfld.long 0x1C 14. " [47] ,New Data Bit[47]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x1C 13. " [46] ,New Data Bit[46]" "Not requested,Requested"
|
|
bitfld.long 0x1C 12. " [45] ,New Data Bit[45]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x1C 11. " [44] ,New Data Bit[44]" "Not requested,Requested"
|
|
bitfld.long 0x1C 10. " [43] ,New Data Bit[43]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x1C 9. " [42] ,New Data Bit[42]" "Not requested,Requested"
|
|
bitfld.long 0x1C 8. " [41] ,New Data Bit[41]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x1C 7. " [40] ,New Data Bit[40]" "Not requested,Requested"
|
|
bitfld.long 0x1C 6. " [39] ,New Data Bit[39]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x1C 5. " [38] ,New Data Bit[38]" "Not requested,Requested"
|
|
bitfld.long 0x1C 4. " [37] ,New Data Bit[37]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x1C 3. " [36] ,New Data Bit[36]" "Not requested,Requested"
|
|
bitfld.long 0x1C 2. " [35] ,New Data Bit[35]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x1C 1. " [34] ,New Data Bit[34]" "Not requested,Requested"
|
|
bitfld.long 0x1C 0. " [33] ,New Data Bit[33]" "Not requested,Requested"
|
|
line.long 0x20 "NEWDAT56,New Data 5-6"
|
|
bitfld.long 0x20 31. " NEWDAT[96] ,New Data Bit[96]" "Not requested,Requested"
|
|
bitfld.long 0x20 30. " [95] ,New Data Bit[95]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x20 29. " [94] ,New Data Bit[94]" "Not requested,Requested"
|
|
bitfld.long 0x20 28. " [93] ,New Data Bit[93]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x20 27. " [92] ,New Data Bit[92]" "Not requested,Requested"
|
|
bitfld.long 0x20 26. " [91] ,New Data Bit[91]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x20 25. " [90] ,New Data Bit[90]" "Not requested,Requested"
|
|
bitfld.long 0x20 24. " [89] ,New Data Bit[89]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x20 23. " [88] ,New Data Bit[88]" "Not requested,Requested"
|
|
bitfld.long 0x20 22. " [87] ,New Data Bit[87]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x20 21. " [86] ,New Data Bit[86]" "Not requested,Requested"
|
|
bitfld.long 0x20 20. " [85] ,New Data Bit[85]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x20 19. " [84] ,New Data Bit[84]" "Not requested,Requested"
|
|
bitfld.long 0x20 18. " [83] ,New Data Bit[83]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x20 17. " [82] ,New Data Bit[82]" "Not requested,Requested"
|
|
bitfld.long 0x20 16. " [81] ,New Data Bit[81]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x20 15. " [80] ,New Data Bit[80]" "Not requested,Requested"
|
|
bitfld.long 0x20 14. " [79] ,New Data Bit[79]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x20 13. " [78] ,New Data Bit[78]" "Not requested,Requested"
|
|
bitfld.long 0x20 12. " [77] ,New Data Bit[77]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x20 11. " [76] ,New Data Bit[76]" "Not requested,Requested"
|
|
bitfld.long 0x20 10. " [75] ,New Data Bit[75]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x20 9. " [74] ,New Data Bit[74]" "Not requested,Requested"
|
|
bitfld.long 0x20 8. " [73] ,New Data Bit[73]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x20 7. " [72] ,New Data Bit[72]" "Not requested,Requested"
|
|
bitfld.long 0x20 6. " [71] ,New Data Bit[71]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x20 5. " [70] ,New Data Bit[70]" "Not requested,Requested"
|
|
bitfld.long 0x20 4. " [69] ,New Data Bit[69]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x20 3. " [68] ,New Data Bit[68]" "Not requested,Requested"
|
|
bitfld.long 0x20 2. " [67] ,New Data Bit[67]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x20 1. " [66] ,New Data Bit[66]" "Not requested,Requested"
|
|
bitfld.long 0x20 0. " [65] ,New Data Bit[65]" "Not requested,Requested"
|
|
line.long 0x24 "NEWDAT78,New Data 7-8"
|
|
bitfld.long 0x24 31. " NEWDAT[128] ,New Data Bit[128]" "Not requested,Requested"
|
|
bitfld.long 0x24 30. " [127] ,New Data Bit[127]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x24 29. " [126] ,New Data Bit[126]" "Not requested,Requested"
|
|
bitfld.long 0x24 28. " [125] ,New Data Bit[125]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x24 27. " [124] ,New Data Bit[124]" "Not requested,Requested"
|
|
bitfld.long 0x24 26. " [123] ,New Data Bit[123]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x24 25. " [122] ,New Data Bit[122]" "Not requested,Requested"
|
|
bitfld.long 0x24 24. " [121] ,New Data Bit[121]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x24 23. " [120] ,New Data Bit[120]" "Not requested,Requested"
|
|
bitfld.long 0x24 22. " [119] ,New Data Bit[119]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x24 21. " [118] ,New Data Bit[118]" "Not requested,Requested"
|
|
bitfld.long 0x24 20. " [117] ,New Data Bit[117]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x24 19. " [116] ,New Data Bit[116]" "Not requested,Requested"
|
|
bitfld.long 0x24 18. " [115] ,New Data Bit[115]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x24 17. " [114] ,New Data Bit[114]" "Not requested,Requested"
|
|
bitfld.long 0x24 16. " [113] ,New Data Bit[113]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x24 15. " [112] ,New Data Bit[112]" "Not requested,Requested"
|
|
bitfld.long 0x24 14. " [111] ,New Data Bit[111]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x24 13. " [110] ,New Data Bit[110]" "Not requested,Requested"
|
|
bitfld.long 0x24 12. " [109] ,New Data Bit[109]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x24 11. " [108] ,New Data Bit[108]" "Not requested,Requested"
|
|
bitfld.long 0x24 10. " [107] ,New Data Bit[107]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x24 9. " [106] ,New Data Bit[106]" "Not requested,Requested"
|
|
bitfld.long 0x24 8. " [105] ,New Data Bit[105]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x24 7. " [104] ,New Data Bit[104]" "Not requested,Requested"
|
|
bitfld.long 0x24 6. " [103] ,New Data Bit[103]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x24 5. " [102] ,New Data Bit[102]" "Not requested,Requested"
|
|
bitfld.long 0x24 4. " [101] ,New Data Bit[101]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x24 3. " [100] ,New Data Bit[100]" "Not requested,Requested"
|
|
bitfld.long 0x24 2. " [99] ,New Data Bit[99]" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x24 1. " [98] ,New Data Bit[98]" "Not requested,Requested"
|
|
bitfld.long 0x24 0. " [97] ,New Data Bit[97]" "Not requested,Requested"
|
|
line.long 0x28 "INTPEN,Interrupt Pending X"
|
|
bitfld.long 0x28 14.--15. " INTPENDREG[8] ,Interrupt Pending 8" "0,1,2,3"
|
|
bitfld.long 0x28 12.--13. " [7] ,Interrupt Pending 7" "0,1,2,3"
|
|
bitfld.long 0x28 10.--11. " [6] ,Interrupt Pending 6" "0,1,2,3"
|
|
bitfld.long 0x28 8.--9. " [5] ,Interrupt Pending 5" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x28 6.--7. " [4] ,Interrupt Pending 4" "0,1,2,3"
|
|
bitfld.long 0x28 4.--5. " [3] ,Interrupt Pending 3" "0,1,2,3"
|
|
bitfld.long 0x28 2.--3. " [2] ,Interrupt Pending 2" "0,1,2,3"
|
|
bitfld.long 0x28 0.--1. " [1] ,Interrupt Pending 1" "0,1,2,3"
|
|
line.long 0x2C "INTPEN12,Interrupt Pending 1-2"
|
|
bitfld.long 0x2C 31. " IntPnd[32] ,Interrupt Pending Bit[32]" "No interrupt,Interrupt"
|
|
bitfld.long 0x2C 30. " [31] ,Interrupt Pending Bit[31]" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x2C 29. " [30] ,Interrupt Pending Bit[30]" "No interrupt,Interrupt"
|
|
bitfld.long 0x2C 28. " [29] ,Interrupt Pending Bit[29]" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x2C 27. " [28] ,Interrupt Pending Bit[28]" "No interrupt,Interrupt"
|
|
bitfld.long 0x2C 26. " [27] ,Interrupt Pending Bit[27]" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x2C 25. " [26] ,Interrupt Pending Bit[26]" "No interrupt,Interrupt"
|
|
bitfld.long 0x2C 24. " [25] ,Interrupt Pending Bit[25]" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x2C 23. " [24] ,Interrupt Pending Bit[24]" "No interrupt,Interrupt"
|
|
bitfld.long 0x2C 22. " [23] ,Interrupt Pending Bit[23]" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x2C 21. " [22] ,Interrupt Pending Bit[22]" "No interrupt,Interrupt"
|
|
bitfld.long 0x2C 20. " [21] ,Interrupt Pending Bit[21]" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x2C 19. " [20] ,Interrupt Pending Bit[20]" "No interrupt,Interrupt"
|
|
bitfld.long 0x2C 18. " [19] ,Interrupt Pending Bit[19]" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x2C 17. " [18] ,Interrupt Pending Bit[18]" "No interrupt,Interrupt"
|
|
bitfld.long 0x2C 16. " [17] ,Interrupt Pending Bit[17]" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x2C 15. " [16] ,Interrupt Pending Bit[16]" "No interrupt,Interrupt"
|
|
bitfld.long 0x2C 14. " [15] ,Interrupt Pending Bit[15]" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x2C 13. " [14] ,Interrupt Pending Bit[14]" "No interrupt,Interrupt"
|
|
bitfld.long 0x2C 12. " [13] ,Interrupt Pending Bit[13]" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x2C 11. " [12] ,Interrupt Pending Bit[12]" "No interrupt,Interrupt"
|
|
bitfld.long 0x2C 10. " [11] ,Interrupt Pending Bit[11]" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x2C 9. " [10] ,Interrupt Pending Bit[10]" "No interrupt,Interrupt"
|
|
bitfld.long 0x2C 8. " [9] ,Interrupt Pending Bit[9]" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x2C 7. " [8] ,Interrupt Pending Bit[8]" "No interrupt,Interrupt"
|
|
bitfld.long 0x2C 6. " [7] ,Interrupt Pending Bit[7]" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x2C 5. " [6] ,Interrupt Pending Bit[6]" "No interrupt,Interrupt"
|
|
bitfld.long 0x2C 4. " [5] ,Interrupt Pending Bit[5]" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x2C 3. " [4] ,Interrupt Pending Bit[4]" "No interrupt,Interrupt"
|
|
bitfld.long 0x2C 2. " [3] ,Interrupt Pending Bit[3]" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x2C 1. " [2] ,Interrupt Pending Bit[2]" "No interrupt,Interrupt"
|
|
bitfld.long 0x2C 0. " [1] ,Interrupt Pending Bit[1]" "No interrupt,Interrupt"
|
|
line.long 0x30 "INTPEN34,Interrupt Pending 3-4"
|
|
bitfld.long 0x30 31. " INTPND[64] ,Interrupt Pending Bit[64]" "No interrupt,Interrupt"
|
|
bitfld.long 0x30 30. " [63] ,Interrupt Pending Bit[63]" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x30 29. " [62] ,Interrupt Pending Bit[62]" "No interrupt,Interrupt"
|
|
bitfld.long 0x30 28. " [61] ,Interrupt Pending Bit[61]" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x30 27. " [60] ,Interrupt Pending Bit[60]" "No interrupt,Interrupt"
|
|
bitfld.long 0x30 26. " [59] ,Interrupt Pending Bit[59]" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x30 25. " [58] ,Interrupt Pending Bit[58]" "No interrupt,Interrupt"
|
|
bitfld.long 0x30 24. " [57] ,Interrupt Pending Bit[57]" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x30 23. " [56] ,Interrupt Pending Bit[56]" "No interrupt,Interrupt"
|
|
bitfld.long 0x30 22. " [55] ,Interrupt Pending Bit[55]" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x30 21. " [54] ,Interrupt Pending Bit[54]" "No interrupt,Interrupt"
|
|
bitfld.long 0x30 20. " [53] ,Interrupt Pending Bit[53]" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x30 19. " [52] ,Interrupt Pending Bit[52]" "No interrupt,Interrupt"
|
|
bitfld.long 0x30 18. " [51] ,Interrupt Pending Bit[51]" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x30 17. " [50] ,Interrupt Pending Bit[50]" "No interrupt,Interrupt"
|
|
bitfld.long 0x30 16. " [49] ,Interrupt Pending Bit[49]" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x30 15. " [48] ,Interrupt Pending Bit[48]" "No interrupt,Interrupt"
|
|
bitfld.long 0x30 14. " [47] ,Interrupt Pending Bit[47]" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x30 13. " [46] ,Interrupt Pending Bit[46]" "No interrupt,Interrupt"
|
|
bitfld.long 0x30 12. " [45] ,Interrupt Pending Bit[45]" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x30 11. " [44] ,Interrupt Pending Bit[44]" "No interrupt,Interrupt"
|
|
bitfld.long 0x30 10. " [43] ,Interrupt Pending Bit[43]" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x30 9. " [42] ,Interrupt Pending Bit[42]" "No interrupt,Interrupt"
|
|
bitfld.long 0x30 8. " [41] ,Interrupt Pending Bit[41]" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x30 7. " [40] ,Interrupt Pending Bit[40]" "No interrupt,Interrupt"
|
|
bitfld.long 0x30 6. " [39] ,Interrupt Pending Bit[39]" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x30 5. " [38] ,Interrupt Pending Bit[38]" "No interrupt,Interrupt"
|
|
bitfld.long 0x30 4. " [37] ,Interrupt Pending Bit[37]" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x30 3. " [36] ,Interrupt Pending Bit[36]" "No interrupt,Interrupt"
|
|
bitfld.long 0x30 2. " [35] ,Interrupt Pending Bit[35]" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x30 1. " [34] ,Interrupt Pending Bit[34]" "No interrupt,Interrupt"
|
|
bitfld.long 0x30 0. " [33] ,Interrupt Pending Bit[33]" "No interrupt,Interrupt"
|
|
line.long 0x34 "INTPEN56,Interrupt Pending 5-6"
|
|
bitfld.long 0x34 31. " INTPND[96] ,Interrupt Pending Bit[96]" "No interrupt,Interrupt"
|
|
bitfld.long 0x34 30. " [95] ,Interrupt Pending Bit[95]" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x34 29. " [94] ,Interrupt Pending Bit[94]" "No interrupt,Interrupt"
|
|
bitfld.long 0x34 28. " [93] ,Interrupt Pending Bit[93]" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x34 27. " [92] ,Interrupt Pending Bit[92]" "No interrupt,Interrupt"
|
|
bitfld.long 0x34 26. " [91] ,Interrupt Pending Bit[91]" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x34 25. " [90] ,Interrupt Pending Bit[90]" "No interrupt,Interrupt"
|
|
bitfld.long 0x34 24. " [89] ,Interrupt Pending Bit[89]" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x34 23. " [88] ,Interrupt Pending Bit[88]" "No interrupt,Interrupt"
|
|
bitfld.long 0x34 22. " [87] ,Interrupt Pending Bit[87]" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x34 21. " [86] ,Interrupt Pending Bit[86]" "No interrupt,Interrupt"
|
|
bitfld.long 0x34 20. " [85] ,Interrupt Pending Bit[85]" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x34 19. " [84] ,Interrupt Pending Bit[84]" "No interrupt,Interrupt"
|
|
bitfld.long 0x34 18. " [83] ,Interrupt Pending Bit[83]" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x34 17. " [82] ,Interrupt Pending Bit[82]" "No interrupt,Interrupt"
|
|
bitfld.long 0x34 16. " [81] ,Interrupt Pending Bit[81]" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x34 15. " [80] ,Interrupt Pending Bit[80]" "No interrupt,Interrupt"
|
|
bitfld.long 0x34 14. " [79] ,Interrupt Pending Bit[79]" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x34 13. " [78] ,Interrupt Pending Bit[78]" "No interrupt,Interrupt"
|
|
bitfld.long 0x34 12. " [77] ,Interrupt Pending Bit[77]" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x34 11. " [76] ,Interrupt Pending Bit[76]" "No interrupt,Interrupt"
|
|
bitfld.long 0x34 10. " [75] ,Interrupt Pending Bit[75]" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x34 9. " [74] ,Interrupt Pending Bit[74]" "No interrupt,Interrupt"
|
|
bitfld.long 0x34 8. " [73] ,Interrupt Pending Bit[73]" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x34 7. " [72] ,Interrupt Pending Bit[72]" "No interrupt,Interrupt"
|
|
bitfld.long 0x34 6. " [71] ,Interrupt Pending Bit[71]" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x34 5. " [70] ,Interrupt Pending Bit[70]" "No interrupt,Interrupt"
|
|
bitfld.long 0x34 4. " [69] ,Interrupt Pending Bit[69]" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x34 3. " [68] ,Interrupt Pending Bit[68]" "No interrupt,Interrupt"
|
|
bitfld.long 0x34 2. " [67] ,Interrupt Pending Bit[67]" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x34 1. " [66] ,Interrupt Pending Bit[66]" "No interrupt,Interrupt"
|
|
bitfld.long 0x34 0. " [65] ,Interrupt Pending Bit[65]" "No interrupt,Interrupt"
|
|
line.long 0x38 "INTPEN78,Interrupt Pending 7-8"
|
|
bitfld.long 0x38 31. " INTPND[128] ,Interrupt Pending Bit[128]" "No interrupt,Interrupt"
|
|
bitfld.long 0x38 30. " [127] ,Interrupt Pending Bit[127]" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x38 29. " [126] ,Interrupt Pending Bit[126]" "No interrupt,Interrupt"
|
|
bitfld.long 0x38 28. " [125] ,Interrupt Pending Bit[125]" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x38 27. " [124] ,Interrupt Pending Bit[124]" "No interrupt,Interrupt"
|
|
bitfld.long 0x38 26. " [123] ,Interrupt Pending Bit[123]" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x38 25. " [122] ,Interrupt Pending Bit[122]" "No interrupt,Interrupt"
|
|
bitfld.long 0x38 24. " [121] ,Interrupt Pending Bit[121]" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x38 23. " [120] ,Interrupt Pending Bit[120]" "No interrupt,Interrupt"
|
|
bitfld.long 0x38 22. " [119] ,Interrupt Pending Bit[119]" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x38 21. " [118] ,Interrupt Pending Bit[118]" "No interrupt,Interrupt"
|
|
bitfld.long 0x38 20. " [117] ,Interrupt Pending Bit[117]" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x38 19. " [116] ,Interrupt Pending Bit[116]" "No interrupt,Interrupt"
|
|
bitfld.long 0x38 18. " [115] ,Interrupt Pending Bit[115]" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x38 17. " [114] ,Interrupt Pending Bit[114]" "No interrupt,Interrupt"
|
|
bitfld.long 0x38 16. " [113] ,Interrupt Pending Bit[113]" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x38 15. " [112] ,Interrupt Pending Bit[112]" "No interrupt,Interrupt"
|
|
bitfld.long 0x38 14. " [111] ,Interrupt Pending Bit[111]" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x38 13. " [110] ,Interrupt Pending Bit[110]" "No interrupt,Interrupt"
|
|
bitfld.long 0x38 12. " [109] ,Interrupt Pending Bit[109]" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x38 11. " [108] ,Interrupt Pending Bit[108]" "No interrupt,Interrupt"
|
|
bitfld.long 0x38 10. " [107] ,Interrupt Pending Bit[107]" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x38 9. " [106] ,Interrupt Pending Bit[106]" "No interrupt,Interrupt"
|
|
bitfld.long 0x38 8. " [105] ,Interrupt Pending Bit[105]" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x38 7. " [104] ,Interrupt Pending Bit[104]" "No interrupt,Interrupt"
|
|
bitfld.long 0x38 6. " [103] ,Interrupt Pending Bit[103]" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x38 5. " [102] ,Interrupt Pending Bit[102]" "No interrupt,Interrupt"
|
|
bitfld.long 0x38 4. " [101] ,Interrupt Pending Bit[101]" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x38 3. " [100] ,Interrupt Pending Bit[100]" "No interrupt,Interrupt"
|
|
bitfld.long 0x38 2. " [99] ,Interrupt Pending Bit[99]" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x38 1. " [98] ,Interrupt Pending Bit[98]" "No interrupt,Interrupt"
|
|
bitfld.long 0x38 0. " [97] ,Interrupt Pending Bit[97]" "No interrupt,Interrupt"
|
|
line.long 0x3C "MVAL,Message Valid X"
|
|
bitfld.long 0x3C 14.--15. " MSGVALREG8 ,Message Valid Register 8" "0,1,2,3"
|
|
bitfld.long 0x3C 12.--13. " [7] ,Message Valid Register 7" "0,1,2,3"
|
|
bitfld.long 0x3C 10.--11. " [6] ,Message Valid Register 6" "0,1,2,3"
|
|
bitfld.long 0x3C 8.--9. " [5] ,Message Valid Register 5" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x3C 6.--7. " [4] ,Message Valid Register 4" "0,1,2,3"
|
|
bitfld.long 0x3C 4.--5. " [3] ,Message Valid Register 3" "0,1,2,3"
|
|
bitfld.long 0x3C 2.--3. " [2] ,Message Valid Register 2" "0,1,2,3"
|
|
bitfld.long 0x3C 0.--1. " [1] ,Message Valid Register 1" "0,1,2,3"
|
|
line.long 0x40 "MVAL12,Message Valid 1-2"
|
|
bitfld.long 0x40 31. " MSGVAL[32] ,Message Valid Bit[32]" "Ignored,Configured"
|
|
bitfld.long 0x40 30. " [31] ,Message Valid Bit[31]" "Ignored,Configured"
|
|
newline
|
|
bitfld.long 0x40 29. " [30] ,Message Valid Bit[30]" "Ignored,Configured"
|
|
bitfld.long 0x40 28. " [29] ,Message Valid Bit[29]" "Ignored,Configured"
|
|
newline
|
|
bitfld.long 0x40 27. " [28] ,Message Valid Bit[28]" "Ignored,Configured"
|
|
bitfld.long 0x40 26. " [27] ,Message Valid Bit[27]" "Ignored,Configured"
|
|
newline
|
|
bitfld.long 0x40 25. " [26] ,Message Valid Bit[26]" "Ignored,Configured"
|
|
bitfld.long 0x40 24. " [25] ,Message Valid Bit[25]" "Ignored,Configured"
|
|
newline
|
|
bitfld.long 0x40 23. " [24] ,Message Valid Bit[24]" "Ignored,Configured"
|
|
bitfld.long 0x40 22. " [23] ,Message Valid Bit[23]" "Ignored,Configured"
|
|
newline
|
|
bitfld.long 0x40 21. " [22] ,Message Valid Bit[22]" "Ignored,Configured"
|
|
bitfld.long 0x40 20. " [21] ,Message Valid Bit[21]" "Ignored,Configured"
|
|
newline
|
|
bitfld.long 0x40 19. " [20] ,Message Valid Bit[20]" "Ignored,Configured"
|
|
bitfld.long 0x40 18. " [19] ,Message Valid Bit[19]" "Ignored,Configured"
|
|
newline
|
|
bitfld.long 0x40 17. " [18] ,Message Valid Bit[18]" "Ignored,Configured"
|
|
bitfld.long 0x40 16. " [17] ,Message Valid Bit[17]" "Ignored,Configured"
|
|
newline
|
|
bitfld.long 0x40 15. " [16] ,Message Valid Bit[16]" "Ignored,Configured"
|
|
bitfld.long 0x40 14. " [15] ,Message Valid Bit[15]" "Ignored,Configured"
|
|
newline
|
|
bitfld.long 0x40 13. " [14] ,Message Valid Bit[14]" "Ignored,Configured"
|
|
bitfld.long 0x40 12. " [13] ,Message Valid Bit[13]" "Ignored,Configured"
|
|
newline
|
|
bitfld.long 0x40 11. " [12] ,Message Valid Bit[12]" "Ignored,Configured"
|
|
bitfld.long 0x40 10. " [11] ,Message Valid Bit[11]" "Ignored,Configured"
|
|
newline
|
|
bitfld.long 0x40 9. " [10] ,Message Valid Bit[10]" "Ignored,Configured"
|
|
bitfld.long 0x40 8. " [9] ,Message Valid Bit[9]" "Ignored,Configured"
|
|
newline
|
|
bitfld.long 0x40 7. " [8] ,Message Valid Bit[8]" "Ignored,Configured"
|
|
bitfld.long 0x40 6. " [7] ,Message Valid Bit[7]" "Ignored,Configured"
|
|
newline
|
|
bitfld.long 0x40 5. " [6] ,Message Valid Bit[6]" "Ignored,Configured"
|
|
bitfld.long 0x40 4. " [5] ,Message Valid Bit[5]" "Ignored,Configured"
|
|
newline
|
|
bitfld.long 0x40 3. " [4] ,Message Valid Bit[4]" "Ignored,Configured"
|
|
bitfld.long 0x40 2. " [3] ,Message Valid Bit[3]" "Ignored,Configured"
|
|
newline
|
|
bitfld.long 0x40 1. " [2] ,Message Valid Bit[2]" "Ignored,Configured"
|
|
bitfld.long 0x40 0. " [1] ,Message Valid Bit[1]" "Ignored,Configured"
|
|
line.long 0x44 "MVAL34,Message Valid 3-4"
|
|
bitfld.long 0x44 31. " MSGVAl[64] ,Message Valid Bit[64]" "Ignored,Configured"
|
|
bitfld.long 0x44 30. " [63] ,Message Valid Bit[63]" "Ignored,Configured"
|
|
newline
|
|
bitfld.long 0x44 29. " [62] ,Message Valid Bit[62]" "Ignored,Configured"
|
|
bitfld.long 0x44 28. " [61] ,Message Valid Bit[61]" "Ignored,Configured"
|
|
newline
|
|
bitfld.long 0x44 27. " [60] ,Message Valid Bit[60]" "Ignored,Configured"
|
|
bitfld.long 0x44 26. " [59] ,Message Valid Bit[59]" "Ignored,Configured"
|
|
newline
|
|
bitfld.long 0x44 25. " [58] ,Message Valid Bit[58]" "Ignored,Configured"
|
|
bitfld.long 0x44 24. " [57] ,Message Valid Bit[57]" "Ignored,Configured"
|
|
newline
|
|
bitfld.long 0x44 23. " [56] ,Message Valid Bit[56]" "Ignored,Configured"
|
|
bitfld.long 0x44 22. " [55] ,Message Valid Bit[55]" "Ignored,Configured"
|
|
newline
|
|
bitfld.long 0x44 21. " [54] ,Message Valid Bit[54]" "Ignored,Configured"
|
|
bitfld.long 0x44 20. " [53] ,Message Valid Bit[53]" "Ignored,Configured"
|
|
newline
|
|
bitfld.long 0x44 19. " [52] ,Message Valid Bit[52]" "Ignored,Configured"
|
|
bitfld.long 0x44 18. " [51] ,Message Valid Bit[51]" "Ignored,Configured"
|
|
newline
|
|
bitfld.long 0x44 17. " [50] ,Message Valid Bit[50]" "Ignored,Configured"
|
|
bitfld.long 0x44 16. " [49] ,Message Valid Bit[49]" "Ignored,Configured"
|
|
newline
|
|
bitfld.long 0x44 15. " [48] ,Message Valid Bit[48]" "Ignored,Configured"
|
|
bitfld.long 0x44 14. " [47] ,Message Valid Bit[47]" "Ignored,Configured"
|
|
newline
|
|
bitfld.long 0x44 13. " [46] ,Message Valid Bit[46]" "Ignored,Configured"
|
|
bitfld.long 0x44 12. " [45] ,Message Valid Bit[45]" "Ignored,Configured"
|
|
newline
|
|
bitfld.long 0x44 11. " [44] ,Message Valid Bit[44]" "Ignored,Configured"
|
|
bitfld.long 0x44 10. " [43] ,Message Valid Bit[43]" "Ignored,Configured"
|
|
newline
|
|
bitfld.long 0x44 9. " [42] ,Message Valid Bit[42]" "Ignored,Configured"
|
|
bitfld.long 0x44 8. " [41] ,Message Valid Bit[41]" "Ignored,Configured"
|
|
newline
|
|
bitfld.long 0x44 7. " [40] ,Message Valid Bit[40]" "Ignored,Configured"
|
|
bitfld.long 0x44 6. " [39] ,Message Valid Bit[39]" "Ignored,Configured"
|
|
newline
|
|
bitfld.long 0x44 5. " [38] ,Message Valid Bit[38]" "Ignored,Configured"
|
|
bitfld.long 0x44 4. " [37] ,Message Valid Bit[37]" "Ignored,Configured"
|
|
newline
|
|
bitfld.long 0x44 3. " [36] ,Message Valid Bit[36]" "Ignored,Configured"
|
|
bitfld.long 0x44 2. " [35] ,Message Valid Bit[35]" "Ignored,Configured"
|
|
newline
|
|
bitfld.long 0x44 1. " [34] ,Message Valid Bit[34]" "Ignored,Configured"
|
|
bitfld.long 0x44 0. " [33] ,Message Valid Bit[33]" "Ignored,Configured"
|
|
line.long 0x48 "MVAL56,Message Valid 5-6"
|
|
bitfld.long 0x48 31. " MSGVAl[96] ,Message Valid Bit[96]" "Ignored,Configured"
|
|
bitfld.long 0x48 30. " [95] ,Message Valid Bit[95]" "Ignored,Configured"
|
|
newline
|
|
bitfld.long 0x48 29. " [94] ,Message Valid Bit[94]" "Ignored,Configured"
|
|
bitfld.long 0x48 28. " [93] ,Message Valid Bit[93]" "Ignored,Configured"
|
|
newline
|
|
bitfld.long 0x48 27. " [92] ,Message Valid Bit[92]" "Ignored,Configured"
|
|
bitfld.long 0x48 26. " [91] ,Message Valid Bit[91]" "Ignored,Configured"
|
|
newline
|
|
bitfld.long 0x48 25. " [90] ,Message Valid Bit[90]" "Ignored,Configured"
|
|
bitfld.long 0x48 24. " [89] ,Message Valid Bit[89]" "Ignored,Configured"
|
|
newline
|
|
bitfld.long 0x48 23. " [88] ,Message Valid Bit[88]" "Ignored,Configured"
|
|
bitfld.long 0x48 22. " [87] ,Message Valid Bit[87]" "Ignored,Configured"
|
|
newline
|
|
bitfld.long 0x48 21. " [86] ,Message Valid Bit[86]" "Ignored,Configured"
|
|
bitfld.long 0x48 20. " [85] ,Message Valid Bit[85]" "Ignored,Configured"
|
|
newline
|
|
bitfld.long 0x48 19. " [84] ,Message Valid Bit[84]" "Ignored,Configured"
|
|
bitfld.long 0x48 18. " [83] ,Message Valid Bit[83]" "Ignored,Configured"
|
|
newline
|
|
bitfld.long 0x48 17. " [82] ,Message Valid Bit[82]" "Ignored,Configured"
|
|
bitfld.long 0x48 16. " [81] ,Message Valid Bit[81]" "Ignored,Configured"
|
|
newline
|
|
bitfld.long 0x48 15. " [80] ,Message Valid Bit[80]" "Ignored,Configured"
|
|
bitfld.long 0x48 14. " [79] ,Message Valid Bit[79]" "Ignored,Configured"
|
|
newline
|
|
bitfld.long 0x48 13. " [78] ,Message Valid Bit[78]" "Ignored,Configured"
|
|
bitfld.long 0x48 12. " [77] ,Message Valid Bit[77]" "Ignored,Configured"
|
|
newline
|
|
bitfld.long 0x48 11. " [76] ,Message Valid Bit[76]" "Ignored,Configured"
|
|
bitfld.long 0x48 10. " [75] ,Message Valid Bit[75]" "Ignored,Configured"
|
|
newline
|
|
bitfld.long 0x48 9. " [74] ,Message Valid Bit[74]" "Ignored,Configured"
|
|
bitfld.long 0x48 8. " [73] ,Message Valid Bit[73]" "Ignored,Configured"
|
|
newline
|
|
bitfld.long 0x48 7. " [72] ,Message Valid Bit[72]" "Ignored,Configured"
|
|
bitfld.long 0x48 6. " [71] ,Message Valid Bit[71]" "Ignored,Configured"
|
|
newline
|
|
bitfld.long 0x48 5. " [70] ,Message Valid Bit[70]" "Ignored,Configured"
|
|
bitfld.long 0x48 4. " [69] ,Message Valid Bit[69]" "Ignored,Configured"
|
|
newline
|
|
bitfld.long 0x48 3. " [68] ,Message Valid Bit[68]" "Ignored,Configured"
|
|
bitfld.long 0x48 2. " [67] ,Message Valid Bit[67]" "Ignored,Configured"
|
|
newline
|
|
bitfld.long 0x48 1. " [66] ,Message Valid Bit[66]" "Ignored,Configured"
|
|
bitfld.long 0x48 0. " [65] ,Message Valid Bit[65]" "Ignored,Configured"
|
|
line.long 0x4C "MVAL78,Message Valid 7-8"
|
|
bitfld.long 0x4C 31. " MSGVAl[128] ,Message Valid Bit[128]" "Ignored,Configured"
|
|
bitfld.long 0x4C 30. " [127] ,Message Valid Bit[127]" "Ignored,Configured"
|
|
newline
|
|
bitfld.long 0x4C 29. " [126] ,Message Valid Bit[126]" "Ignored,Configured"
|
|
bitfld.long 0x4C 28. " [125] ,Message Valid Bit[125]" "Ignored,Configured"
|
|
newline
|
|
bitfld.long 0x4C 27. " [124] ,Message Valid Bit[124]" "Ignored,Configured"
|
|
bitfld.long 0x4C 26. " [123] ,Message Valid Bit[123]" "Ignored,Configured"
|
|
newline
|
|
bitfld.long 0x4C 25. " [122] ,Message Valid Bit[122]" "Ignored,Configured"
|
|
bitfld.long 0x4C 24. " [121] ,Message Valid Bit[121]" "Ignored,Configured"
|
|
newline
|
|
bitfld.long 0x4C 23. " [120] ,Message Valid Bit[120]" "Ignored,Configured"
|
|
bitfld.long 0x4C 22. " [119] ,Message Valid Bit[119]" "Ignored,Configured"
|
|
newline
|
|
bitfld.long 0x4C 21. " [118] ,Message Valid Bit[118]" "Ignored,Configured"
|
|
bitfld.long 0x4C 20. " [117] ,Message Valid Bit[117]" "Ignored,Configured"
|
|
newline
|
|
bitfld.long 0x4C 19. " [116] ,Message Valid Bit[116]" "Ignored,Configured"
|
|
bitfld.long 0x4C 18. " [115] ,Message Valid Bit[115]" "Ignored,Configured"
|
|
newline
|
|
bitfld.long 0x4C 17. " [114] ,Message Valid Bit[114]" "Ignored,Configured"
|
|
bitfld.long 0x4C 16. " [113] ,Message Valid Bit[113]" "Ignored,Configured"
|
|
newline
|
|
bitfld.long 0x4C 15. " [112] ,Message Valid Bit[112]" "Ignored,Configured"
|
|
bitfld.long 0x4C 14. " [111] ,Message Valid Bit[111]" "Ignored,Configured"
|
|
newline
|
|
bitfld.long 0x4C 13. " [110] ,Message Valid Bit[110]" "Ignored,Configured"
|
|
bitfld.long 0x4C 12. " [109] ,Message Valid Bit[109]" "Ignored,Configured"
|
|
newline
|
|
bitfld.long 0x4C 11. " [108] ,Message Valid Bit[108]" "Ignored,Configured"
|
|
bitfld.long 0x4C 10. " [107] ,Message Valid Bit[107]" "Ignored,Configured"
|
|
newline
|
|
bitfld.long 0x4C 9. " [106] ,Message Valid Bit[106]" "Ignored,Configured"
|
|
bitfld.long 0x4C 8. " [105] ,Message Valid Bit[105]" "Ignored,Configured"
|
|
newline
|
|
bitfld.long 0x4C 7. " [104] ,Message Valid Bit[104]" "Ignored,Configured"
|
|
bitfld.long 0x4C 6. " [103] ,Message Valid Bit[103]" "Ignored,Configured"
|
|
newline
|
|
bitfld.long 0x4C 5. " [102] ,Message Valid Bit[102]" "Ignored,Configured"
|
|
bitfld.long 0x4C 4. " [101] ,Message Valid Bit[101]" "Ignored,Configured"
|
|
newline
|
|
bitfld.long 0x4C 3. " [100] ,Message Valid Bit[100]" "Ignored,Configured"
|
|
bitfld.long 0x4C 2. " [99] ,Message Valid Bit[99]" "Ignored,Configured"
|
|
newline
|
|
bitfld.long 0x4C 1. " [98] ,Message Valid Bit[98]" "Ignored,Configured"
|
|
bitfld.long 0x4C 0. " [97] ,Message Valid Bit[97]" "Ignored,Configured"
|
|
group.long 0xD8++0x0F
|
|
line.long 0x00 "INTPMX12,Interrupt Multiplexer 1-2"
|
|
bitfld.long 0x00 31. " INTPNDMUX[32] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[32]" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x00 30. " [31] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[31]" "DCAN0INT,DCAN1INT"
|
|
newline
|
|
bitfld.long 0x00 29. " [30] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[30]" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x00 28. " [29] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[29]" "DCAN0INT,DCAN1INT"
|
|
newline
|
|
bitfld.long 0x00 27. " [28] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[28]" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x00 26. " [27] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[27]" "DCAN0INT,DCAN1INT"
|
|
newline
|
|
bitfld.long 0x00 25. " [26] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[26]" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x00 24. " [25] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[25]" "DCAN0INT,DCAN1INT"
|
|
newline
|
|
bitfld.long 0x00 23. " [24] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[24]" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x00 22. " [23] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[23]" "DCAN0INT,DCAN1INT"
|
|
newline
|
|
bitfld.long 0x00 21. " [22] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[22]" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x00 20. " [21] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[21]" "DCAN0INT,DCAN1INT"
|
|
newline
|
|
bitfld.long 0x00 19. " [20] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[20]" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x00 18. " [19] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[19]" "DCAN0INT,DCAN1INT"
|
|
newline
|
|
bitfld.long 0x00 17. " [18] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[18]" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x00 16. " [17] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[17]" "DCAN0INT,DCAN1INT"
|
|
newline
|
|
bitfld.long 0x00 15. " [16] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[16]" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x00 14. " [15] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[15]" "DCAN0INT,DCAN1INT"
|
|
newline
|
|
bitfld.long 0x00 13. " [14] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[14]" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x00 12. " [13] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[13]" "DCAN0INT,DCAN1INT"
|
|
newline
|
|
bitfld.long 0x00 11. " [12] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[12]" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x00 10. " [11] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[11]" "DCAN0INT,DCAN1INT"
|
|
newline
|
|
bitfld.long 0x00 9. " [10] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[10]" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x00 8. " [9] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[9]" "DCAN0INT,DCAN1INT"
|
|
newline
|
|
bitfld.long 0x00 7. " [8] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[8]" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x00 6. " [7] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[7]" "DCAN0INT,DCAN1INT"
|
|
newline
|
|
bitfld.long 0x00 5. " [6] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[6]" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x00 4. " [5] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[5]" "DCAN0INT,DCAN1INT"
|
|
newline
|
|
bitfld.long 0x00 3. " [4] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[4]" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x00 2. " [3] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[3]" "DCAN0INT,DCAN1INT"
|
|
newline
|
|
bitfld.long 0x00 1. " [2] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[2]" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x00 0. " [1] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[1]" "DCAN0INT,DCAN1INT"
|
|
line.long 0x04 "INTPMX34,Interrupt Multiplexer 3-4"
|
|
bitfld.long 0x04 31. " INTPNDMUX[64] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[64]" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x04 30. " [63] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[63]" "DCAN0INT,DCAN1INT"
|
|
newline
|
|
bitfld.long 0x04 29. " [62] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[62]" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x04 28. " [61] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[61]" "DCAN0INT,DCAN1INT"
|
|
newline
|
|
bitfld.long 0x04 27. " [60] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[60]" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x04 26. " [59] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[59]" "DCAN0INT,DCAN1INT"
|
|
newline
|
|
bitfld.long 0x04 25. " [58] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[58]" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x04 24. " [57] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[57]" "DCAN0INT,DCAN1INT"
|
|
newline
|
|
bitfld.long 0x04 23. " [56] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[56]" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x04 22. " [55] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[55]" "DCAN0INT,DCAN1INT"
|
|
newline
|
|
bitfld.long 0x04 21. " [54] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[54]" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x04 20. " [53] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[53]" "DCAN0INT,DCAN1INT"
|
|
newline
|
|
bitfld.long 0x04 19. " [52] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[52]" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x04 18. " [51] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[51]" "DCAN0INT,DCAN1INT"
|
|
newline
|
|
bitfld.long 0x04 17. " [50] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[50]" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x04 16. " [49] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[49]" "DCAN0INT,DCAN1INT"
|
|
newline
|
|
bitfld.long 0x04 15. " [48] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[48]" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x04 14. " [47] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[47]" "DCAN0INT,DCAN1INT"
|
|
newline
|
|
bitfld.long 0x04 13. " [46] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[46]" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x04 12. " [45] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[45]" "DCAN0INT,DCAN1INT"
|
|
newline
|
|
bitfld.long 0x04 11. " [44] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[44]" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x04 10. " [43] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[43]" "DCAN0INT,DCAN1INT"
|
|
newline
|
|
bitfld.long 0x04 9. " [42] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[42]" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x04 8. " [41] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[41]" "DCAN0INT,DCAN1INT"
|
|
newline
|
|
bitfld.long 0x04 7. " [40] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[40]" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x04 6. " [39] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[39]" "DCAN0INT,DCAN1INT"
|
|
newline
|
|
bitfld.long 0x04 5. " [38] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[38]" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x04 4. " [37] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[37]" "DCAN0INT,DCAN1INT"
|
|
newline
|
|
bitfld.long 0x04 3. " [36] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[36]" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x04 2. " [35] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[35]" "DCAN0INT,DCAN1INT"
|
|
newline
|
|
bitfld.long 0x04 1. " [34] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[34]" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x04 0. " [33] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[33]" "DCAN0INT,DCAN1INT"
|
|
line.long 0x08 "INTPMX56,Interrupt Multiplexer 5-6"
|
|
bitfld.long 0x08 31. " INTPNDMUX[96] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[96]" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x08 30. " [95] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[95]" "DCAN0INT,DCAN1INT"
|
|
newline
|
|
bitfld.long 0x08 29. " [94] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[94]" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x08 28. " [93] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[93]" "DCAN0INT,DCAN1INT"
|
|
newline
|
|
bitfld.long 0x08 27. " [92] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[92]" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x08 26. " [91] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[91]" "DCAN0INT,DCAN1INT"
|
|
newline
|
|
bitfld.long 0x08 25. " [90] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[90]" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x08 24. " [89] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[89]" "DCAN0INT,DCAN1INT"
|
|
newline
|
|
bitfld.long 0x08 23. " [88] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[88]" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x08 22. " [87] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[87]" "DCAN0INT,DCAN1INT"
|
|
newline
|
|
bitfld.long 0x08 21. " [86] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[86]" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x08 20. " [85] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[85]" "DCAN0INT,DCAN1INT"
|
|
newline
|
|
bitfld.long 0x08 19. " [84] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[84]" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x08 18. " [83] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[83]" "DCAN0INT,DCAN1INT"
|
|
newline
|
|
bitfld.long 0x08 17. " [82] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[82]" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x08 16. " [81] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[81]" "DCAN0INT,DCAN1INT"
|
|
newline
|
|
bitfld.long 0x08 15. " [80] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[80]" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x08 14. " [79] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[79]" "DCAN0INT,DCAN1INT"
|
|
newline
|
|
bitfld.long 0x08 13. " [78] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[78]" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x08 12. " [77] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[77]" "DCAN0INT,DCAN1INT"
|
|
newline
|
|
bitfld.long 0x08 11. " [76] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[76]" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x08 10. " [75] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[75]" "DCAN0INT,DCAN1INT"
|
|
newline
|
|
bitfld.long 0x08 9. " [74] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[74]" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x08 8. " [73] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[73]" "DCAN0INT,DCAN1INT"
|
|
newline
|
|
bitfld.long 0x08 7. " [72] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[72]" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x08 6. " [71] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[71]" "DCAN0INT,DCAN1INT"
|
|
newline
|
|
bitfld.long 0x08 5. " [70] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[70]" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x08 4. " [69] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[69]" "DCAN0INT,DCAN1INT"
|
|
newline
|
|
bitfld.long 0x08 3. " [68] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[68]" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x08 2. " [67] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[67]" "DCAN0INT,DCAN1INT"
|
|
newline
|
|
bitfld.long 0x08 1. " [66] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[66]" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x08 0. " [65] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[65]" "DCAN0INT,DCAN1INT"
|
|
line.long 0x0C "INTPMX78,Interrupt Multiplexer 7-8"
|
|
bitfld.long 0x0C 31. " INTPNDMUX[128] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[128]" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x0C 30. " [127] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[127]" "DCAN0INT,DCAN1INT"
|
|
newline
|
|
bitfld.long 0x0C 29. " [126] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[126]" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x0C 28. " [125] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[125]" "DCAN0INT,DCAN1INT"
|
|
newline
|
|
bitfld.long 0x0C 27. " [124] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[124]" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x0C 26. " [123] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[123]" "DCAN0INT,DCAN1INT"
|
|
newline
|
|
bitfld.long 0x0C 25. " [122] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[122]" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x0C 24. " [121] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[121]" "DCAN0INT,DCAN1INT"
|
|
newline
|
|
bitfld.long 0x0C 23. " [120] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[120]" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x0C 22. " [119] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[119]" "DCAN0INT,DCAN1INT"
|
|
newline
|
|
bitfld.long 0x0C 21. " [118] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[118]" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x0C 20. " [117] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[117]" "DCAN0INT,DCAN1INT"
|
|
newline
|
|
bitfld.long 0x0C 19. " [116] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[116]" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x0C 18. " [115] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[115]" "DCAN0INT,DCAN1INT"
|
|
newline
|
|
bitfld.long 0x0C 17. " [114] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[114]" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x0C 16. " [113] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[113]" "DCAN0INT,DCAN1INT"
|
|
newline
|
|
bitfld.long 0x0C 15. " [112] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[112]" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x0C 14. " [111] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[111]" "DCAN0INT,DCAN1INT"
|
|
newline
|
|
bitfld.long 0x0C 13. " [110] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[110]" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x0C 12. " [109] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[109]" "DCAN0INT,DCAN1INT"
|
|
newline
|
|
bitfld.long 0x0C 11. " [108] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[108]" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x0C 10. " [107] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[107]" "DCAN0INT,DCAN1INT"
|
|
newline
|
|
bitfld.long 0x0C 9. " [106] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[106]" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x0C 8. " [105] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[105]" "DCAN0INT,DCAN1INT"
|
|
newline
|
|
bitfld.long 0x0C 7. " [104] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[104]" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x0C 6. " [103] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[103]" "DCAN0INT,DCAN1INT"
|
|
newline
|
|
bitfld.long 0x0C 5. " [102] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[102]" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x0C 4. " [101] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[101]" "DCAN0INT,DCAN1INT"
|
|
newline
|
|
bitfld.long 0x0C 3. " [100] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[100]" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x0C 2. " [99] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[99]" "DCAN0INT,DCAN1INT"
|
|
newline
|
|
bitfld.long 0x0C 1. " [98] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[98]" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x0C 0. " [97] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[97]" "DCAN0INT,DCAN1INT"
|
|
group.long 0x100++0x3 "IF1"
|
|
line.long 0x00 "IF1COM,IF1 Command Mask / Command Request Register"
|
|
bitfld.long 0x00 23. " WR/RD ,Write / Read direction" "Read,Write"
|
|
newline
|
|
bitfld.long 0x00 22. " MASK ,Access Mask Bits" "Unchanged,Identifier Mask+MDir+MXtd"
|
|
newline
|
|
bitfld.long 0x00 21. " ARB ,Access Arbitration Bits" "Unchanged,Identifier+Dir+Xtd+MSGVAl"
|
|
newline
|
|
bitfld.long 0x00 20. " CONTROL ,Access Control Bits" "Unchanged,Control bits"
|
|
bitfld.long 0x00 19. " CLRINTPND ,Clear Interrupt Pending Bit" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 18. " TXRQST/NEWDAT ,Access Transmission Request Bit" "Not requested,Requested"
|
|
bitfld.long 0x00 17. " DATA_A ,Access Data Bytes 0-3" "Unchanged,Data bytes 0-3"
|
|
newline
|
|
bitfld.long 0x00 16. " DATA_B ,Access Data Bytes 4-7" "Unchanged,Data bytes 4-7"
|
|
bitfld.long 0x00 15. " BUSY ,Busy Flag" "Not busy,Busy"
|
|
newline
|
|
sif (!cpuis("TMS570LS0332")&&!cpuis("TMS570LS0432"))
|
|
bitfld.long 0x00 14. " DMAACTIVE ,Activation of DMA Feature for Subsequent Internal IF1 Update" "No active,Active"
|
|
newline
|
|
endif
|
|
hexmask.long.byte 0x00 0.--7. 1. " MESSAGE_NUMBER ,Message Number"
|
|
sif cpuis("TMS570LS0232")||cpuis("TMS570LS0714*")||cpuis("TMS570LS0914*")||cpuis("TMS570LS3137-EP")
|
|
if (((per.l.be(((ad:0xFFF7E000+0x100+0x08))))&0x40000000)==0x0)
|
|
group.long (0x100+0x04)++0x07
|
|
line.long 0x0 "IF1MASK,IF1 Mask Register"
|
|
bitfld.long 0x00 31. " MXTD ,Mask Extended Identifier" "No effect,Filtering"
|
|
bitfld.long 0x00 30. " MDIR ,Mask Message Direction" "No effect,Filtering"
|
|
newline
|
|
bitfld.long 0x00 28. " ID ,Message Identifier bit[10]" "0,1"
|
|
bitfld.long 0x00 27. ",Message Identifier bit[9]" "0,1"
|
|
bitfld.long 0x00 26. ",Message Identifier bit[8]" "0,1"
|
|
bitfld.long 0x00 25. ",Message Identifier bit[7]" "0,1"
|
|
bitfld.long 0x00 24. ",Message Identifier bit[6]" "0,1"
|
|
bitfld.long 0x00 23. ",Message Identifier bit[5]" "0,1"
|
|
bitfld.long 0x00 22. ",Message Identifier bit[4]" "0,1"
|
|
bitfld.long 0x00 21. ",Message Identifier bit[3]" "0,1"
|
|
bitfld.long 0x00 20. ",Message Identifier bit[2]" "0,1"
|
|
bitfld.long 0x00 19. ",Message Identifier bit[1]" "0,1"
|
|
bitfld.long 0x00 18. ",Message Identifier bit[0]" "0,1"
|
|
line.long 0x04 "IF1ARB,IF1 Arbitration Register"
|
|
bitfld.long 0x04 31. " MSGVAL ,Message Valid" "Ignore,Configure"
|
|
bitfld.long 0x04 30. " XTD ,Extended Identifier" "11-bit,29-bit"
|
|
bitfld.long 0x04 29. " DIR ,Message Direction" "Receive,Transmit"
|
|
hexmask.long.word 0x04 18.--28. 1. " ID ,Message Identifier"
|
|
else
|
|
group.long (0x100+0x04)++0x07
|
|
line.long 0x00 "IF1MASK,IF1 Mask Register"
|
|
bitfld.long 0x00 31. " MXTD ,Mask Extended Identifier" "No effect,Filtering"
|
|
bitfld.long 0x00 30. " MDIR ,Mask Message Direction" "No effect,Filtering"
|
|
newline
|
|
bitfld.long 0x00 28. " ID ,Message Identifier bit[28]" "0,1"
|
|
bitfld.long 0x00 27. ",Message Identifier bit[27]" "0,1"
|
|
bitfld.long 0x00 26. ",Message Identifier bit[26]" "0,1"
|
|
bitfld.long 0x00 25. ",Message Identifier bit[25]" "0,1"
|
|
bitfld.long 0x00 24. ",Message Identifier bit[24]" "0,1"
|
|
bitfld.long 0x00 23. ",Message Identifier bit[23]" "0,1"
|
|
bitfld.long 0x00 22. ",Message Identifier bit[22]" "0,1"
|
|
bitfld.long 0x00 21. ",Message Identifier bit[21]" "0,1"
|
|
bitfld.long 0x00 20. ",Message Identifier bit[20]" "0,1"
|
|
bitfld.long 0x00 19. ",Message Identifier bit[19]" "0,1"
|
|
bitfld.long 0x00 18. ",Message Identifier bit[18]" "0,1"
|
|
bitfld.long 0x00 17. ",Message Identifier bit[17]" "0,1"
|
|
bitfld.long 0x00 16. ",Message Identifier bit[16]" "0,1"
|
|
bitfld.long 0x00 15. ",Message Identifier bit[15]" "0,1"
|
|
bitfld.long 0x00 14. ",Message Identifier bit[14]" "0,1"
|
|
bitfld.long 0x00 13. ",Message Identifier bit[13]" "0,1"
|
|
bitfld.long 0x00 12. ",Message Identifier bit[12]" "0,1"
|
|
bitfld.long 0x00 11. ",Message Identifier bit[11]" "0,1"
|
|
bitfld.long 0x00 10. ",Message Identifier bit[10]" "0,1"
|
|
bitfld.long 0x00 9. ",Message Identifier bit[9]" "0,1"
|
|
bitfld.long 0x00 8. ",Message Identifier bit[8]" "0,1"
|
|
bitfld.long 0x00 7. ",Message Identifier bit[7]" "0,1"
|
|
bitfld.long 0x00 6. ",Message Identifier bit[6]" "0,1"
|
|
bitfld.long 0x00 5. ",Message Identifier bit[5]" "0,1"
|
|
bitfld.long 0x00 4. ",Message Identifier bit[4]" "0,1"
|
|
bitfld.long 0x00 3. ",Message Identifier bit[3]" "0,1"
|
|
bitfld.long 0x00 2. ",Message Identifier bit[2]" "0,1"
|
|
bitfld.long 0x00 1. ",Message Identifier bit[1]" "0,1"
|
|
bitfld.long 0x00 0. ",Message Identifier bit[0]" "0,1"
|
|
line.long 0x04 "IF1ARB,IF1 Arbitation Register"
|
|
bitfld.long 0x04 31. " MSGVAL ,Message Valid" "Ignore,Configure"
|
|
bitfld.long 0x04 30. " XTD ,Extended Identifier" "11-bit,29-bit"
|
|
bitfld.long 0x04 29. " DIR ,Message Direction" "Receive,Transmit"
|
|
hexmask.long 0x04 0.--28. 1. " ID ,Message Identifier"
|
|
endif
|
|
else
|
|
if (((per.l(((ad:0xFFF7E000+0x100+0x08))))&0x40000000)==0x0)
|
|
group.long (0x100+0x04)++0x07
|
|
line.long 0x0 "IF1MASK,IF1 Mask Register"
|
|
bitfld.long 0x00 31. " MXTD ,Mask Extended Identifier" "No effect,Filtering"
|
|
bitfld.long 0x00 30. " MDIR ,Mask Message Direction" "No effect,Filtering"
|
|
newline
|
|
bitfld.long 0x00 28. " ID ,Message Identifier bit[28]" "0,1"
|
|
bitfld.long 0x00 27. ",Message Identifier bit[27]" "0,1"
|
|
bitfld.long 0x00 26. ",Message Identifier bit[26]" "0,1"
|
|
bitfld.long 0x00 25. ",Message Identifier bit[25]" "0,1"
|
|
bitfld.long 0x00 24. ",Message Identifier bit[24]" "0,1"
|
|
bitfld.long 0x00 23. ",Message Identifier bit[23]" "0,1"
|
|
bitfld.long 0x00 22. ",Message Identifier bit[22]" "0,1"
|
|
bitfld.long 0x00 21. ",Message Identifier bit[21]" "0,1"
|
|
bitfld.long 0x00 20. ",Message Identifier bit[20]" "0,1"
|
|
bitfld.long 0x00 19. ",Message Identifier bit[19]" "0,1"
|
|
bitfld.long 0x00 18. ",Message Identifier bit[18]" "0,1"
|
|
line.long 0x04 "IF1ARB,IF1 Arbitation Register"
|
|
bitfld.long 0x04 31. " MSGVAL ,Message Valid" "Ignore,Configure"
|
|
bitfld.long 0x04 30. " XTD ,Extended Identifier" "11-bit,29-bit"
|
|
bitfld.long 0x04 29. " DIR ,Message Direction" "Receive,Transmit"
|
|
hexmask.long.word 0x04 18.--28. 1. " ID ,Message Identifier"
|
|
else
|
|
group.long (0x100+0x04)++0x07
|
|
line.long 0x0 "IF1MASK,IF1 Mask Register"
|
|
bitfld.long 0x00 31. " MXTD ,Mask Extended Identifier" "No effect,Filtering"
|
|
bitfld.long 0x00 30. " MDIR ,Mask Message Direction" "No effect,Filtering"
|
|
newline
|
|
bitfld.long 0x00 28. " ID ,Message Identifier bit[28]" "0,1"
|
|
bitfld.long 0x00 27. ",Message Identifier bit[27]" "0,1"
|
|
bitfld.long 0x00 26. ",Message Identifier bit[26]" "0,1"
|
|
bitfld.long 0x00 25. ",Message Identifier bit[25]" "0,1"
|
|
bitfld.long 0x00 24. ",Message Identifier bit[24]" "0,1"
|
|
bitfld.long 0x00 23. ",Message Identifier bit[23]" "0,1"
|
|
bitfld.long 0x00 22. ",Message Identifier bit[22]" "0,1"
|
|
bitfld.long 0x00 21. ",Message Identifier bit[21]" "0,1"
|
|
bitfld.long 0x00 20. ",Message Identifier bit[20]" "0,1"
|
|
bitfld.long 0x00 19. ",Message Identifier bit[19]" "0,1"
|
|
bitfld.long 0x00 18. ",Message Identifier bit[18]" "0,1"
|
|
bitfld.long 0x00 17. ",Message Identifier bit[17]" "0,1"
|
|
bitfld.long 0x00 16. ",Message Identifier bit[16]" "0,1"
|
|
bitfld.long 0x00 15. ",Message Identifier bit[15]" "0,1"
|
|
bitfld.long 0x00 14. ",Message Identifier bit[14]" "0,1"
|
|
bitfld.long 0x00 13. ",Message Identifier bit[13]" "0,1"
|
|
bitfld.long 0x00 12. ",Message Identifier bit[12]" "0,1"
|
|
bitfld.long 0x00 11. ",Message Identifier bit[11]" "0,1"
|
|
bitfld.long 0x00 10. ",Message Identifier bit[10]" "0,1"
|
|
bitfld.long 0x00 9. ",Message Identifier bit[9]" "0,1"
|
|
bitfld.long 0x00 8. ",Message Identifier bit[8]" "0,1"
|
|
bitfld.long 0x00 7. ",Message Identifier bit[7]" "0,1"
|
|
bitfld.long 0x00 6. ",Message Identifier bit[6]" "0,1"
|
|
bitfld.long 0x00 5. ",Message Identifier bit[5]" "0,1"
|
|
bitfld.long 0x00 4. ",Message Identifier bit[4]" "0,1"
|
|
bitfld.long 0x00 3. ",Message Identifier bit[3]" "0,1"
|
|
bitfld.long 0x00 2. ",Message Identifier bit[2]" "0,1"
|
|
bitfld.long 0x00 1. ",Message Identifier bit[1]" "0,1"
|
|
bitfld.long 0x00 0. ",Message Identifier bit[0]" "0,1"
|
|
line.long 0x04 "IF1ARB,IF1 Arbitation Register"
|
|
bitfld.long 0x04 31. " MSGVAL ,Message Valid" "Ignore,Configure"
|
|
bitfld.long 0x04 30. " XTD ,Extended Identifier" "11-bit,29-bit"
|
|
bitfld.long 0x04 29. " DIR ,Message Direction" "Receive,Transmit"
|
|
hexmask.long 0x04 0.--28. 1. " ID ,Message Identifier"
|
|
endif
|
|
endif
|
|
group.long (0x100+0x0C)++0x0B
|
|
line.long 0x00 "IF1MCTRL,IF1 Message Control Register"
|
|
bitfld.long 0x00 15. " NEWDAT ,New Data" "No new data,New data"
|
|
bitfld.long 0x00 14. " MSGLST ,Message Lost" "Not lost,Lost"
|
|
bitfld.long 0x00 13. " INTPND ,Interrupt Pending" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x00 12. " UMASK ,Use Acceptance Mask" "Ignored,Masked"
|
|
bitfld.long 0x00 11. " TXIE ,Transmit Interrupt Enable" "Unchanged,Set"
|
|
bitfld.long 0x00 10. " RXIE ,Receive Interrupt Enable" "Unchanged,Set"
|
|
newline
|
|
bitfld.long 0x00 9. " RMTEN ,Remote Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " TXRQST ,Transmit Request" "Not requested,Requested"
|
|
bitfld.long 0x00 7. " EOB ,End of Block" "Single/Last,Not last"
|
|
newline
|
|
bitfld.long 0x00 0.--3. " DLC[3-0] ,Data Length Code" "0 byte,1 bytes,2 bytes,3 bytes,4 bytes,5 bytes,6 bytes,7 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes"
|
|
line.long 0x04 "IF1DATA,IF1 Data A Register"
|
|
hexmask.long.byte 0x04 24.--31. 1. " DATA[3] ,4th data byte of a CAN Data Frame"
|
|
hexmask.long.byte 0x04 16.--23. 1. " [2] ,3rd data byte of a CAN Data Frame"
|
|
hexmask.long.byte 0x04 8.--15. 1. " [1] ,2nd data byte of a CAN Data Frame"
|
|
hexmask.long.byte 0x04 0.--7. 1. " [0] ,1st data byte of a CAN Data Frame"
|
|
line.long 0x08 "IF1DATB,IF1 Data B Register"
|
|
hexmask.long.byte 0x08 24.--31. 1. " DATA[7] ,8th data byte of a CAN Data Frame"
|
|
hexmask.long.byte 0x08 16.--23. 1. " [6] ,7th data byte of a CAN Data Frame"
|
|
hexmask.long.byte 0x08 8.--15. 1. " [5] ,6th data byte of a CAN Data Frame"
|
|
hexmask.long.byte 0x08 0.--7. 1. " [4] ,5th data byte of a CAN Data Frame"
|
|
group.long 0x120++0x3 "IF2"
|
|
line.long 0x00 "IF2COM,IF2 Command Mask / Command Request Register"
|
|
bitfld.long 0x00 23. " WR/RD ,Write / Read direction" "Read,Write"
|
|
newline
|
|
bitfld.long 0x00 22. " MASK ,Access Mask Bits" "Unchanged,Identifier Mask+MDir+MXtd"
|
|
newline
|
|
bitfld.long 0x00 21. " ARB ,Access Arbitration Bits" "Unchanged,Identifier+Dir+Xtd+MSGVAl"
|
|
newline
|
|
bitfld.long 0x00 20. " CONTROL ,Access Control Bits" "Unchanged,Control bits"
|
|
bitfld.long 0x00 19. " CLRINTPND ,Clear Interrupt Pending Bit" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 18. " TXRQST/NEWDAT ,Access Transmission Request Bit" "Not requested,Requested"
|
|
bitfld.long 0x00 17. " DATA_A ,Access Data Bytes 0-3" "Unchanged,Data bytes 0-3"
|
|
newline
|
|
bitfld.long 0x00 16. " DATA_B ,Access Data Bytes 4-7" "Unchanged,Data bytes 4-7"
|
|
bitfld.long 0x00 15. " BUSY ,Busy Flag" "Not busy,Busy"
|
|
newline
|
|
sif (!cpuis("TMS570LS0332")&&!cpuis("TMS570LS0432"))
|
|
bitfld.long 0x00 14. " DMAACTIVE ,Activation of DMA Feature for Subsequent Internal IF1 Update" "No active,Active"
|
|
newline
|
|
endif
|
|
hexmask.long.byte 0x00 0.--7. 1. " MESSAGE_NUMBER ,Message Number"
|
|
sif cpuis("TMS570LS0232")||cpuis("TMS570LS0714*")||cpuis("TMS570LS0914*")||cpuis("TMS570LS3137-EP")
|
|
if (((per.l.be(((ad:0xFFF7E000+0x120+0x08))))&0x40000000)==0x0)
|
|
group.long (0x120+0x04)++0x07
|
|
line.long 0x0 "IF2MASK,IF2 Mask Register"
|
|
bitfld.long 0x00 31. " MXTD ,Mask Extended Identifier" "No effect,Filtering"
|
|
bitfld.long 0x00 30. " MDIR ,Mask Message Direction" "No effect,Filtering"
|
|
newline
|
|
bitfld.long 0x00 28. " ID ,Message Identifier bit[10]" "0,1"
|
|
bitfld.long 0x00 27. ",Message Identifier bit[9]" "0,1"
|
|
bitfld.long 0x00 26. ",Message Identifier bit[8]" "0,1"
|
|
bitfld.long 0x00 25. ",Message Identifier bit[7]" "0,1"
|
|
bitfld.long 0x00 24. ",Message Identifier bit[6]" "0,1"
|
|
bitfld.long 0x00 23. ",Message Identifier bit[5]" "0,1"
|
|
bitfld.long 0x00 22. ",Message Identifier bit[4]" "0,1"
|
|
bitfld.long 0x00 21. ",Message Identifier bit[3]" "0,1"
|
|
bitfld.long 0x00 20. ",Message Identifier bit[2]" "0,1"
|
|
bitfld.long 0x00 19. ",Message Identifier bit[1]" "0,1"
|
|
bitfld.long 0x00 18. ",Message Identifier bit[0]" "0,1"
|
|
line.long 0x04 "IF2ARB,IF2 Arbitration Register"
|
|
bitfld.long 0x04 31. " MSGVAL ,Message Valid" "Ignore,Configure"
|
|
bitfld.long 0x04 30. " XTD ,Extended Identifier" "11-bit,29-bit"
|
|
bitfld.long 0x04 29. " DIR ,Message Direction" "Receive,Transmit"
|
|
hexmask.long.word 0x04 18.--28. 1. " ID ,Message Identifier"
|
|
else
|
|
group.long (0x120+0x04)++0x07
|
|
line.long 0x00 "IF2MASK,IF2 Mask Register"
|
|
bitfld.long 0x00 31. " MXTD ,Mask Extended Identifier" "No effect,Filtering"
|
|
bitfld.long 0x00 30. " MDIR ,Mask Message Direction" "No effect,Filtering"
|
|
newline
|
|
bitfld.long 0x00 28. " ID ,Message Identifier bit[28]" "0,1"
|
|
bitfld.long 0x00 27. ",Message Identifier bit[27]" "0,1"
|
|
bitfld.long 0x00 26. ",Message Identifier bit[26]" "0,1"
|
|
bitfld.long 0x00 25. ",Message Identifier bit[25]" "0,1"
|
|
bitfld.long 0x00 24. ",Message Identifier bit[24]" "0,1"
|
|
bitfld.long 0x00 23. ",Message Identifier bit[23]" "0,1"
|
|
bitfld.long 0x00 22. ",Message Identifier bit[22]" "0,1"
|
|
bitfld.long 0x00 21. ",Message Identifier bit[21]" "0,1"
|
|
bitfld.long 0x00 20. ",Message Identifier bit[20]" "0,1"
|
|
bitfld.long 0x00 19. ",Message Identifier bit[19]" "0,1"
|
|
bitfld.long 0x00 18. ",Message Identifier bit[18]" "0,1"
|
|
bitfld.long 0x00 17. ",Message Identifier bit[17]" "0,1"
|
|
bitfld.long 0x00 16. ",Message Identifier bit[16]" "0,1"
|
|
bitfld.long 0x00 15. ",Message Identifier bit[15]" "0,1"
|
|
bitfld.long 0x00 14. ",Message Identifier bit[14]" "0,1"
|
|
bitfld.long 0x00 13. ",Message Identifier bit[13]" "0,1"
|
|
bitfld.long 0x00 12. ",Message Identifier bit[12]" "0,1"
|
|
bitfld.long 0x00 11. ",Message Identifier bit[11]" "0,1"
|
|
bitfld.long 0x00 10. ",Message Identifier bit[10]" "0,1"
|
|
bitfld.long 0x00 9. ",Message Identifier bit[9]" "0,1"
|
|
bitfld.long 0x00 8. ",Message Identifier bit[8]" "0,1"
|
|
bitfld.long 0x00 7. ",Message Identifier bit[7]" "0,1"
|
|
bitfld.long 0x00 6. ",Message Identifier bit[6]" "0,1"
|
|
bitfld.long 0x00 5. ",Message Identifier bit[5]" "0,1"
|
|
bitfld.long 0x00 4. ",Message Identifier bit[4]" "0,1"
|
|
bitfld.long 0x00 3. ",Message Identifier bit[3]" "0,1"
|
|
bitfld.long 0x00 2. ",Message Identifier bit[2]" "0,1"
|
|
bitfld.long 0x00 1. ",Message Identifier bit[1]" "0,1"
|
|
bitfld.long 0x00 0. ",Message Identifier bit[0]" "0,1"
|
|
line.long 0x04 "IF2ARB,IF2 Arbitation Register"
|
|
bitfld.long 0x04 31. " MSGVAL ,Message Valid" "Ignore,Configure"
|
|
bitfld.long 0x04 30. " XTD ,Extended Identifier" "11-bit,29-bit"
|
|
bitfld.long 0x04 29. " DIR ,Message Direction" "Receive,Transmit"
|
|
hexmask.long 0x04 0.--28. 1. " ID ,Message Identifier"
|
|
endif
|
|
else
|
|
if (((per.l(((ad:0xFFF7E000+0x120+0x08))))&0x40000000)==0x0)
|
|
group.long (0x120+0x04)++0x07
|
|
line.long 0x0 "IF2MASK,IF2 Mask Register"
|
|
bitfld.long 0x00 31. " MXTD ,Mask Extended Identifier" "No effect,Filtering"
|
|
bitfld.long 0x00 30. " MDIR ,Mask Message Direction" "No effect,Filtering"
|
|
newline
|
|
bitfld.long 0x00 28. " ID ,Message Identifier bit[28]" "0,1"
|
|
bitfld.long 0x00 27. ",Message Identifier bit[27]" "0,1"
|
|
bitfld.long 0x00 26. ",Message Identifier bit[26]" "0,1"
|
|
bitfld.long 0x00 25. ",Message Identifier bit[25]" "0,1"
|
|
bitfld.long 0x00 24. ",Message Identifier bit[24]" "0,1"
|
|
bitfld.long 0x00 23. ",Message Identifier bit[23]" "0,1"
|
|
bitfld.long 0x00 22. ",Message Identifier bit[22]" "0,1"
|
|
bitfld.long 0x00 21. ",Message Identifier bit[21]" "0,1"
|
|
bitfld.long 0x00 20. ",Message Identifier bit[20]" "0,1"
|
|
bitfld.long 0x00 19. ",Message Identifier bit[19]" "0,1"
|
|
bitfld.long 0x00 18. ",Message Identifier bit[18]" "0,1"
|
|
line.long 0x04 "IF2ARB,IF2 Arbitation Register"
|
|
bitfld.long 0x04 31. " MSGVAL ,Message Valid" "Ignore,Configure"
|
|
bitfld.long 0x04 30. " XTD ,Extended Identifier" "11-bit,29-bit"
|
|
bitfld.long 0x04 29. " DIR ,Message Direction" "Receive,Transmit"
|
|
hexmask.long.word 0x04 18.--28. 1. " ID ,Message Identifier"
|
|
else
|
|
group.long (0x120+0x04)++0x07
|
|
line.long 0x0 "IF2MASK,IF2 Mask Register"
|
|
bitfld.long 0x00 31. " MXTD ,Mask Extended Identifier" "No effect,Filtering"
|
|
bitfld.long 0x00 30. " MDIR ,Mask Message Direction" "No effect,Filtering"
|
|
newline
|
|
bitfld.long 0x00 28. " ID ,Message Identifier bit[28]" "0,1"
|
|
bitfld.long 0x00 27. ",Message Identifier bit[27]" "0,1"
|
|
bitfld.long 0x00 26. ",Message Identifier bit[26]" "0,1"
|
|
bitfld.long 0x00 25. ",Message Identifier bit[25]" "0,1"
|
|
bitfld.long 0x00 24. ",Message Identifier bit[24]" "0,1"
|
|
bitfld.long 0x00 23. ",Message Identifier bit[23]" "0,1"
|
|
bitfld.long 0x00 22. ",Message Identifier bit[22]" "0,1"
|
|
bitfld.long 0x00 21. ",Message Identifier bit[21]" "0,1"
|
|
bitfld.long 0x00 20. ",Message Identifier bit[20]" "0,1"
|
|
bitfld.long 0x00 19. ",Message Identifier bit[19]" "0,1"
|
|
bitfld.long 0x00 18. ",Message Identifier bit[18]" "0,1"
|
|
bitfld.long 0x00 17. ",Message Identifier bit[17]" "0,1"
|
|
bitfld.long 0x00 16. ",Message Identifier bit[16]" "0,1"
|
|
bitfld.long 0x00 15. ",Message Identifier bit[15]" "0,1"
|
|
bitfld.long 0x00 14. ",Message Identifier bit[14]" "0,1"
|
|
bitfld.long 0x00 13. ",Message Identifier bit[13]" "0,1"
|
|
bitfld.long 0x00 12. ",Message Identifier bit[12]" "0,1"
|
|
bitfld.long 0x00 11. ",Message Identifier bit[11]" "0,1"
|
|
bitfld.long 0x00 10. ",Message Identifier bit[10]" "0,1"
|
|
bitfld.long 0x00 9. ",Message Identifier bit[9]" "0,1"
|
|
bitfld.long 0x00 8. ",Message Identifier bit[8]" "0,1"
|
|
bitfld.long 0x00 7. ",Message Identifier bit[7]" "0,1"
|
|
bitfld.long 0x00 6. ",Message Identifier bit[6]" "0,1"
|
|
bitfld.long 0x00 5. ",Message Identifier bit[5]" "0,1"
|
|
bitfld.long 0x00 4. ",Message Identifier bit[4]" "0,1"
|
|
bitfld.long 0x00 3. ",Message Identifier bit[3]" "0,1"
|
|
bitfld.long 0x00 2. ",Message Identifier bit[2]" "0,1"
|
|
bitfld.long 0x00 1. ",Message Identifier bit[1]" "0,1"
|
|
bitfld.long 0x00 0. ",Message Identifier bit[0]" "0,1"
|
|
line.long 0x04 "IF2ARB,IF2 Arbitation Register"
|
|
bitfld.long 0x04 31. " MSGVAL ,Message Valid" "Ignore,Configure"
|
|
bitfld.long 0x04 30. " XTD ,Extended Identifier" "11-bit,29-bit"
|
|
bitfld.long 0x04 29. " DIR ,Message Direction" "Receive,Transmit"
|
|
hexmask.long 0x04 0.--28. 1. " ID ,Message Identifier"
|
|
endif
|
|
endif
|
|
group.long (0x120+0x0C)++0x0B
|
|
line.long 0x00 "IF2MCTRL,IF2 Message Control Register"
|
|
bitfld.long 0x00 15. " NEWDAT ,New Data" "No new data,New data"
|
|
bitfld.long 0x00 14. " MSGLST ,Message Lost" "Not lost,Lost"
|
|
bitfld.long 0x00 13. " INTPND ,Interrupt Pending" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x00 12. " UMASK ,Use Acceptance Mask" "Ignored,Masked"
|
|
bitfld.long 0x00 11. " TXIE ,Transmit Interrupt Enable" "Unchanged,Set"
|
|
bitfld.long 0x00 10. " RXIE ,Receive Interrupt Enable" "Unchanged,Set"
|
|
newline
|
|
bitfld.long 0x00 9. " RMTEN ,Remote Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " TXRQST ,Transmit Request" "Not requested,Requested"
|
|
bitfld.long 0x00 7. " EOB ,End of Block" "Single/Last,Not last"
|
|
newline
|
|
bitfld.long 0x00 0.--3. " DLC[3-0] ,Data Length Code" "0 byte,1 bytes,2 bytes,3 bytes,4 bytes,5 bytes,6 bytes,7 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes"
|
|
line.long 0x04 "IF2DATA,IF2 Data A Register"
|
|
hexmask.long.byte 0x04 24.--31. 1. " DATA[3] ,4th data byte of a CAN Data Frame"
|
|
hexmask.long.byte 0x04 16.--23. 1. " [2] ,3rd data byte of a CAN Data Frame"
|
|
hexmask.long.byte 0x04 8.--15. 1. " [1] ,2nd data byte of a CAN Data Frame"
|
|
hexmask.long.byte 0x04 0.--7. 1. " [0] ,1st data byte of a CAN Data Frame"
|
|
line.long 0x08 "IF2DATB,IF2 Data B Register"
|
|
hexmask.long.byte 0x08 24.--31. 1. " DATA[7] ,8th data byte of a CAN Data Frame"
|
|
hexmask.long.byte 0x08 16.--23. 1. " [6] ,7th data byte of a CAN Data Frame"
|
|
hexmask.long.byte 0x08 8.--15. 1. " [5] ,6th data byte of a CAN Data Frame"
|
|
hexmask.long.byte 0x08 0.--7. 1. " [4] ,5th data byte of a CAN Data Frame"
|
|
group.long 0x140++0x3 "IF3"
|
|
line.long 0x00 "IF3OB,IF3 Observation Register"
|
|
sif (cpu()==("TMS570LS0332")||cpu()==("TMS570LS0432")||cpuis("TMS570LS1114*")||cpuis("TMS570LS1115*")||cpuis("TMS570LS1224*")||cpuis("TMS570LS1225*")||cpuis("TMS570LS1227*")||cpuis("TMS570LS21*")||cpuis("TMS570LS31*")||cpuis("TMS570LS0232")||cpuis("TMS570LS0714*")||cpuis("TMS570LS0914*"))
|
|
rbitfld.long 0x00 15. " IF3UPD ,IF3 Updata Data" "Not loaded,Loaded"
|
|
rbitfld.long 0x00 12. " IF3SDB ,IF3 Status of Data B Read Access" "Low,High"
|
|
rbitfld.long 0x00 11. " IF3SDA ,IF3 Status of Data A Read Access" "Low,High"
|
|
newline
|
|
rbitfld.long 0x00 10. " IF3SC ,IF3 Status of Control Bits Read Access" "Low,High"
|
|
rbitfld.long 0x00 9. " IF3SA ,IF3 Status of Arbitration Data Read Access" "Low,High"
|
|
rbitfld.long 0x00 8. " IF3SM ,IF3 Status of Mask Data Read Access" "Low,High"
|
|
else
|
|
bitfld.long 0x00 15. " IF3UPD ,IF3 Updata Data" "Not loaded,Loaded"
|
|
bitfld.long 0x00 12. " IF3SDB ,IF3 Status of Data B Read Access" "Low,High"
|
|
bitfld.long 0x00 11. " IF3SDA ,IF3 Status of Data A Read Access" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 10. " IF3SC ,IF3 Status of Control Bits Read Access" "Low,High"
|
|
bitfld.long 0x00 9. " IF3SA ,IF3 Status of Arbitration Data Read Access" "Low,High"
|
|
bitfld.long 0x00 8. " IF3SM ,IF3 Status of Mask Data Read Access" "Low,High"
|
|
endif
|
|
newline
|
|
bitfld.long 0x00 4. " DATA_B ,Data B Read Observation" "Not read,Read"
|
|
bitfld.long 0x00 3. " DATA_A ,Data A Read Observation" "Not read,Read"
|
|
bitfld.long 0x00 2. " CTRL ,Ctrl Read Observation" "Not read,Read"
|
|
newline
|
|
bitfld.long 0x00 1. " ARB ,Arbitration Data Read Observation" "Not read,Read"
|
|
bitfld.long 0x00 0. " MASK ,Mask Data Read Observation" "Not read,Read"
|
|
sif cpuis("TMS570LS0232")||cpuis("TMS570LS0714*")||cpuis("TMS570LS0914*")
|
|
if (((per.l.be((ad:0xFFF7E000+0x148)))&0x40000000)==0x0)
|
|
rgroup.long 0x144++0x07
|
|
line.long 0x00 "IF3MASK,IF3 Mask Register"
|
|
bitfld.long 0x00 31. " MXtd ,Mask Extended Identifier" "No effect,Filtering"
|
|
bitfld.long 0x00 30. " MDir ,Mask Message Direction" "No effect,Filtering"
|
|
newline
|
|
bitfld.long 0x00 28. " ID ,Message Identifier bit[28]" "0,1"
|
|
bitfld.long 0x00 27. ",Message Identifier bit[27]" "0,1"
|
|
bitfld.long 0x00 26. ",Message Identifier bit[26]" "0,1"
|
|
bitfld.long 0x00 25. ",Message Identifier bit[25]" "0,1"
|
|
bitfld.long 0x00 24. ",Message Identifier bit[24]" "0,1"
|
|
bitfld.long 0x00 23. ",Message Identifier bit[23]" "0,1"
|
|
bitfld.long 0x00 22. ",Message Identifier bit[22]" "0,1"
|
|
bitfld.long 0x00 21. ",Message Identifier bit[21]" "0,1"
|
|
bitfld.long 0x00 20. ",Message Identifier bit[20]" "0,1"
|
|
bitfld.long 0x00 19. ",Message Identifier bit[19]" "0,1"
|
|
bitfld.long 0x00 18. ",Message Identifier bit[18]" "0,1"
|
|
line.long 0x04 "IF3ARB,IF3 Arbitation Register"
|
|
bitfld.long 0x04 31. " MSGVAl ,Message Valid" "Ignored,Configured"
|
|
bitfld.long 0x04 30. " XTD ,Extended Identifier" "11-bit,29-bit"
|
|
bitfld.long 0x04 29. " DIR ,Message Direction" "Receive,Transmit"
|
|
newline
|
|
hexmask.long.word 0x04 18.--28. 1. " ID ,Message Identifier"
|
|
else
|
|
rgroup.long 0x144++0x07
|
|
line.long 0x0 "IF3MASK,IF3 Mask Register"
|
|
bitfld.long 0x00 31. " MXTD ,Mask Extended Identifier" "No effect,Filtering"
|
|
bitfld.long 0x00 30. " MDIR ,Mask Message Direction" "No effect,Filtering"
|
|
newline
|
|
bitfld.long 0x00 28. " ID ,Message Identifier bit[28]" "0,1"
|
|
bitfld.long 0x00 27. ",Message Identifier bit[27]" "0,1"
|
|
bitfld.long 0x00 26. ",Message Identifier bit[26]" "0,1"
|
|
bitfld.long 0x00 25. ",Message Identifier bit[25]" "0,1"
|
|
bitfld.long 0x00 24. ",Message Identifier bit[24]" "0,1"
|
|
bitfld.long 0x00 23. ",Message Identifier bit[23]" "0,1"
|
|
bitfld.long 0x00 22. ",Message Identifier bit[22]" "0,1"
|
|
bitfld.long 0x00 21. ",Message Identifier bit[21]" "0,1"
|
|
bitfld.long 0x00 20. ",Message Identifier bit[20]" "0,1"
|
|
bitfld.long 0x00 19. ",Message Identifier bit[19]" "0,1"
|
|
bitfld.long 0x00 18. ",Message Identifier bit[18]" "0,1"
|
|
bitfld.long 0x00 17. ",Message Identifier bit[17]" "0,1"
|
|
bitfld.long 0x00 16. ",Message Identifier bit[16]" "0,1"
|
|
bitfld.long 0x00 15. ",Message Identifier bit[15]" "0,1"
|
|
bitfld.long 0x00 14. ",Message Identifier bit[14]" "0,1"
|
|
bitfld.long 0x00 13. ",Message Identifier bit[13]" "0,1"
|
|
bitfld.long 0x00 12. ",Message Identifier bit[12]" "0,1"
|
|
bitfld.long 0x00 11. ",Message Identifier bit[11]" "0,1"
|
|
bitfld.long 0x00 10. ",Message Identifier bit[10]" "0,1"
|
|
bitfld.long 0x00 9. ",Message Identifier bit[9]" "0,1"
|
|
bitfld.long 0x00 8. ",Message Identifier bit[8]" "0,1"
|
|
bitfld.long 0x00 7. ",Message Identifier bit[7]" "0,1"
|
|
bitfld.long 0x00 6. ",Message Identifier bit[6]" "0,1"
|
|
bitfld.long 0x00 5. ",Message Identifier bit[5]" "0,1"
|
|
bitfld.long 0x00 4. ",Message Identifier bit[4]" "0,1"
|
|
bitfld.long 0x00 3. ",Message Identifier bit[3]" "0,1"
|
|
bitfld.long 0x00 2. ",Message Identifier bit[2]" "0,1"
|
|
bitfld.long 0x00 1. ",Message Identifier bit[1]" "0,1"
|
|
bitfld.long 0x00 0. ",Message Identifier bit[0]" "0,1"
|
|
line.long 0x04 "IF3ARB,IF3 Arbitation Register"
|
|
bitfld.long 0x04 31. " MSGVAl ,Message Valid" "Ignored,Configured"
|
|
bitfld.long 0x04 30. " XTD ,Extended Identifier" "11-bit,29-bit"
|
|
bitfld.long 0x04 29. " DIR ,Message Direction" "Receive,Transmit"
|
|
newline
|
|
hexmask.long 0x04 0.--28. 1. " ID ,Message Identifier"
|
|
endif
|
|
else
|
|
if (((per.l((ad:0xFFF7E000+0x148)))&0x40000000)==0x0)
|
|
rgroup.long 0x144++0x07
|
|
line.long 0x0 "IF3MASK,IF3 Mask Register"
|
|
bitfld.long 0x00 31. " MXtd ,Mask Extended Identifier" "No effect,Filtering"
|
|
bitfld.long 0x00 30. " MDir ,Mask Message Direction" "No effect,Filtering"
|
|
newline
|
|
bitfld.long 0x00 28. " ID ,Message Identifier bit[28]" "0,1"
|
|
bitfld.long 0x00 27. ",Message Identifier bit[27]" "0,1"
|
|
bitfld.long 0x00 26. ",Message Identifier bit[26]" "0,1"
|
|
bitfld.long 0x00 25. ",Message Identifier bit[25]" "0,1"
|
|
bitfld.long 0x00 24. ",Message Identifier bit[24]" "0,1"
|
|
bitfld.long 0x00 23. ",Message Identifier bit[23]" "0,1"
|
|
bitfld.long 0x00 22. ",Message Identifier bit[22]" "0,1"
|
|
bitfld.long 0x00 21. ",Message Identifier bit[21]" "0,1"
|
|
bitfld.long 0x00 20. ",Message Identifier bit[20]" "0,1"
|
|
bitfld.long 0x00 19. ",Message Identifier bit[19]" "0,1"
|
|
bitfld.long 0x00 18. ",Message Identifier bit[18]" "0,1"
|
|
line.long 0x04 "IF3ARB,IF3 Arbitation Register"
|
|
bitfld.long 0x04 31. " MSGVAl ,Message Valid" "Ignored,Configured"
|
|
bitfld.long 0x04 30. " XTD ,Extended Identifier" "11-bit,29-bit"
|
|
bitfld.long 0x04 29. " DIR ,Message Direction" "Receive,Transmit"
|
|
newline
|
|
hexmask.long.word 0x04 18.--28. 1. " ID ,Message Identifier"
|
|
else
|
|
rgroup.long 0x144++0x07
|
|
line.long 0x0 "IF3MASK,IF3 Mask Register"
|
|
bitfld.long 0x00 31. " MXTD ,Mask Extended Identifier" "No effect,Filtering"
|
|
bitfld.long 0x00 30. " MDIR ,Mask Message Direction" "No effect,Filtering"
|
|
newline
|
|
bitfld.long 0x00 28. " ID ,Message Identifier bit[28]" "0,1"
|
|
bitfld.long 0x00 27. ",Message Identifier bit[27]" "0,1"
|
|
bitfld.long 0x00 26. ",Message Identifier bit[26]" "0,1"
|
|
bitfld.long 0x00 25. ",Message Identifier bit[25]" "0,1"
|
|
bitfld.long 0x00 24. ",Message Identifier bit[24]" "0,1"
|
|
bitfld.long 0x00 23. ",Message Identifier bit[23]" "0,1"
|
|
bitfld.long 0x00 22. ",Message Identifier bit[22]" "0,1"
|
|
bitfld.long 0x00 21. ",Message Identifier bit[21]" "0,1"
|
|
bitfld.long 0x00 20. ",Message Identifier bit[20]" "0,1"
|
|
bitfld.long 0x00 19. ",Message Identifier bit[19]" "0,1"
|
|
bitfld.long 0x00 18. ",Message Identifier bit[18]" "0,1"
|
|
bitfld.long 0x00 17. ",Message Identifier bit[17]" "0,1"
|
|
bitfld.long 0x00 16. ",Message Identifier bit[16]" "0,1"
|
|
bitfld.long 0x00 15. ",Message Identifier bit[15]" "0,1"
|
|
bitfld.long 0x00 14. ",Message Identifier bit[14]" "0,1"
|
|
bitfld.long 0x00 13. ",Message Identifier bit[13]" "0,1"
|
|
bitfld.long 0x00 12. ",Message Identifier bit[12]" "0,1"
|
|
bitfld.long 0x00 11. ",Message Identifier bit[11]" "0,1"
|
|
bitfld.long 0x00 10. ",Message Identifier bit[10]" "0,1"
|
|
bitfld.long 0x00 9. ",Message Identifier bit[9]" "0,1"
|
|
bitfld.long 0x00 8. ",Message Identifier bit[8]" "0,1"
|
|
bitfld.long 0x00 7. ",Message Identifier bit[7]" "0,1"
|
|
bitfld.long 0x00 6. ",Message Identifier bit[6]" "0,1"
|
|
bitfld.long 0x00 5. ",Message Identifier bit[5]" "0,1"
|
|
bitfld.long 0x00 4. ",Message Identifier bit[4]" "0,1"
|
|
bitfld.long 0x00 3. ",Message Identifier bit[3]" "0,1"
|
|
bitfld.long 0x00 2. ",Message Identifier bit[2]" "0,1"
|
|
bitfld.long 0x00 1. ",Message Identifier bit[1]" "0,1"
|
|
bitfld.long 0x00 0. ",Message Identifier bit[0]" "0,1"
|
|
line.long 0x04 "IF3ARB,IF3 Arbitation Register"
|
|
bitfld.long 0x04 31. " MSGVAl ,Message Valid" "Ignored,Configured"
|
|
bitfld.long 0x04 30. " XTD ,Extended Identifier" "11-bit,29-bit"
|
|
bitfld.long 0x04 29. " DIR ,Message Direction" "Receive,Transmit"
|
|
newline
|
|
hexmask.long 0x04 0.--28. 1. " ID ,Message Identifier"
|
|
endif
|
|
endif
|
|
group.long 0x14C++0x0B
|
|
line.long 0x00 "IF3MCTRL,IF3 Message Control Register"
|
|
bitfld.long 0x00 15. " NEWDAT ,New Data" "No new data,New data"
|
|
bitfld.long 0x00 14. " MSGLST ,Message Lost" "Not lost,Lost"
|
|
bitfld.long 0x00 13. " INTPND ,Interrupt Pending" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x00 12. " UMASK ,Use Acceptance Mask" "Ignored,Masked"
|
|
bitfld.long 0x00 11. " TXIE ,Transmit Interrupt Enable" "Unchanged,Enabled"
|
|
bitfld.long 0x00 10. " RXIE ,Receive Interrupt Enable" "Unchanged,Enabled"
|
|
newline
|
|
bitfld.long 0x00 9. " RMTEN ,Remote Enable" "Unchanged,Enabled"
|
|
bitfld.long 0x00 8. " TXRQST ,Transmit Request" "Not requested,Requested"
|
|
bitfld.long 0x00 7. " EOB ,End of Block" "Not last,Single/Last"
|
|
newline
|
|
bitfld.long 0x00 0.--3. " DLC[3-0] ,Data Length Code" "0 byte,1 byte,2 bytes,3 bytes,4 bytes,5 bytes,6 bytes,7 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes"
|
|
line.long 0x04 "IF3DATA,IF3 Data A Register"
|
|
hexmask.long.byte 0x04 24.--31. 1. " DATA[3] ,4th data byte of a CAN Data Frame"
|
|
hexmask.long.byte 0x04 16.--23. 1. " [2] ,3rd data byte of a CAN Data Frame"
|
|
hexmask.long.byte 0x04 8.--15. 1. " [1] ,2nd data byte of a CAN Data Frame"
|
|
hexmask.long.byte 0x04 0.--7. 1. " [0] ,1st data byte of a CAN Data Frame"
|
|
line.long 0x08 "IF3DATB,IF3 Data B Register"
|
|
hexmask.long.byte 0x08 24.--31. 1. " DATA[7] ,8th data byte of a CAN Data Frame"
|
|
hexmask.long.byte 0x08 16.--23. 1. " [6] ,7th data byte of a CAN Data Frame"
|
|
hexmask.long.byte 0x08 8.--15. 1. " [5] ,6th data byte of a CAN Data Frame"
|
|
hexmask.long.byte 0x08 0.--7. 1. " [4] ,5th data byte of a CAN Data Frame"
|
|
group.long 0x160++0x0F
|
|
line.long 0x0 "IF3UENA2_1,Update Enable 2_1 Register"
|
|
bitfld.long 0x00 31. " IF3UPDATEEN[32] ,IF3 Update Enabled Bit[32]" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " [31] ,IF3 Update Enabled Bit[31]" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 29. " [30] ,IF3 Update Enabled Bit[30]" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " [29] ,IF3 Update Enabled Bit[29]" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 27. " [28] ,IF3 Update Enabled Bit[28]" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " [27] ,IF3 Update Enabled Bit[27]" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 25. " [26] ,IF3 Update Enabled Bit[26]" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " [25] ,IF3 Update Enabled Bit[25]" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 23. " [24] ,IF3 Update Enabled Bit[24]" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " [23] ,IF3 Update Enabled Bit[23]" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 21. " [22] ,IF3 Update Enabled Bit[22]" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " [21] ,IF3 Update Enabled Bit[21]" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 19. " [20] ,IF3 Update Enabled Bit[20]" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " [19] ,IF3 Update Enabled Bit[19]" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 17. " [18] ,IF3 Update Enabled Bit[18]" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " [17] ,IF3 Update Enabled Bit[17]" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 15. " [16] ,IF3 Update Enabled Bit[16]" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " [15] ,IF3 Update Enabled Bit[15]" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 13. " [14] ,IF3 Update Enabled Bit[14]" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " [13] ,IF3 Update Enabled Bit[13]" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 11. " [12] ,IF3 Update Enabled Bit[12]" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " [11] ,IF3 Update Enabled Bit[11]" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 9. " [10] ,IF3 Update Enabled Bit[10]" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " [9] ,IF3 Update Enabled Bit[9]" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 7. " [8] ,IF3 Update Enabled Bit[8]" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " [7] ,IF3 Update Enabled Bit[7]" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 5. " [6] ,IF3 Update Enabled Bit[6]" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " [5] ,IF3 Update Enabled Bit[5]" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 3. " [4] ,IF3 Update Enabled Bit[4]" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " [3] ,IF3 Update Enabled Bit[3]" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 1. " [2] ,IF3 Update Enabled Bit[2]" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [1] ,IF3 Update Enabled Bit[1]" "Disabled,Enabled"
|
|
line.long 0x04 "IF3UENA4_3,Update Enable 4_3 Register"
|
|
bitfld.long 0x04 31. " IF3UPDATEEN[64] ,IF3 Update Enabled Bit[64]" "Disabled,Enabled"
|
|
bitfld.long 0x04 30. " [63] ,IF3 Update Enabled Bit[63]" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x04 29. " [62] ,IF3 Update Enabled Bit[62]" "Disabled,Enabled"
|
|
bitfld.long 0x04 28. " [61] ,IF3 Update Enabled Bit[61]" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x04 27. " [60] ,IF3 Update Enabled Bit[60]" "Disabled,Enabled"
|
|
bitfld.long 0x04 26. " [59] ,IF3 Update Enabled Bit[59]" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x04 25. " [58] ,IF3 Update Enabled Bit[58]" "Disabled,Enabled"
|
|
bitfld.long 0x04 24. " [57] ,IF3 Update Enabled Bit[57]" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x04 23. " [56] ,IF3 Update Enabled Bit[56]" "Disabled,Enabled"
|
|
bitfld.long 0x04 22. " [55] ,IF3 Update Enabled Bit[55]" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x04 21. " [54] ,IF3 Update Enabled Bit[54]" "Disabled,Enabled"
|
|
bitfld.long 0x04 20. " [53] ,IF3 Update Enabled Bit[53]" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x04 19. " [52] ,IF3 Update Enabled Bit[52]" "Disabled,Enabled"
|
|
bitfld.long 0x04 18. " [51] ,IF3 Update Enabled Bit[51]" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x04 17. " [50] ,IF3 Update Enabled Bit[50]" "Disabled,Enabled"
|
|
bitfld.long 0x04 16. " [49] ,IF3 Update Enabled Bit[49]" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x04 15. " [48] ,IF3 Update Enabled Bit[48]" "Disabled,Enabled"
|
|
bitfld.long 0x04 14. " [47] ,IF3 Update Enabled Bit[47]" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x04 13. " [46] ,IF3 Update Enabled Bit[46]" "Disabled,Enabled"
|
|
bitfld.long 0x04 12. " [45] ,IF3 Update Enabled Bit[45]" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x04 11. " [44] ,IF3 Update Enabled Bit[44]" "Disabled,Enabled"
|
|
bitfld.long 0x04 10. " [43] ,IF3 Update Enabled Bit[43]" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x04 9. " [42] ,IF3 Update Enabled Bit[42]" "Disabled,Enabled"
|
|
bitfld.long 0x04 8. " [41] ,IF3 Update Enabled Bit[41]" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x04 7. " [40] ,IF3 Update Enabled Bit[40]" "Disabled,Enabled"
|
|
bitfld.long 0x04 6. " [39] ,IF3 Update Enabled Bit[39]" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x04 5. " [38] ,IF3 Update Enabled Bit[38]" "Disabled,Enabled"
|
|
bitfld.long 0x04 4. " [37] ,IF3 Update Enabled Bit[37]" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x04 3. " [36] ,IF3 Update Enabled Bit[36]" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " [35] ,IF3 Update Enabled Bit[35]" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x04 1. " [34] ,IF3 Update Enabled Bit[34]" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " [33] ,IF3 Update Enabled Bit[33]" "Disabled,Enabled"
|
|
line.long 0x08 "IF3UENA6_5,Update Enable 6_5 Register"
|
|
bitfld.long 0x08 31. " IF3UPDATEEN[96] ,IF3 Update Enabled Bit[96]" "Disabled,Enabled"
|
|
bitfld.long 0x08 30. " [95] ,IF3 Update Enabled Bit[95]" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x08 29. " [94] ,IF3 Update Enabled Bit[94]" "Disabled,Enabled"
|
|
bitfld.long 0x08 28. " [93] ,IF3 Update Enabled Bit[93]" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x08 27. " [92] ,IF3 Update Enabled Bit[92]" "Disabled,Enabled"
|
|
bitfld.long 0x08 26. " [91] ,IF3 Update Enabled Bit[91]" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x08 25. " [90] ,IF3 Update Enabled Bit[90]" "Disabled,Enabled"
|
|
bitfld.long 0x08 24. " [89] ,IF3 Update Enabled Bit[89]" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x08 23. " [88] ,IF3 Update Enabled Bit[88]" "Disabled,Enabled"
|
|
bitfld.long 0x08 22. " [87] ,IF3 Update Enabled Bit[87]" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x08 21. " [86] ,IF3 Update Enabled Bit[86]" "Disabled,Enabled"
|
|
bitfld.long 0x08 20. " [85] ,IF3 Update Enabled Bit[85]" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x08 19. " [84] ,IF3 Update Enabled Bit[84]" "Disabled,Enabled"
|
|
bitfld.long 0x08 18. " [83] ,IF3 Update Enabled Bit[83]" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x08 17. " [82] ,IF3 Update Enabled Bit[82]" "Disabled,Enabled"
|
|
bitfld.long 0x08 16. " [81] ,IF3 Update Enabled Bit[81]" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x08 15. " [80] ,IF3 Update Enabled Bit[80]" "Disabled,Enabled"
|
|
bitfld.long 0x08 14. " [79] ,IF3 Update Enabled Bit[79]" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x08 13. " [78] ,IF3 Update Enabled Bit[78]" "Disabled,Enabled"
|
|
bitfld.long 0x08 12. " [77] ,IF3 Update Enabled Bit[77]" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x08 11. " [76] ,IF3 Update Enabled Bit[76]" "Disabled,Enabled"
|
|
bitfld.long 0x08 10. " [75] ,IF3 Update Enabled Bit[75]" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x08 9. " [74] ,IF3 Update Enabled Bit[74]" "Disabled,Enabled"
|
|
bitfld.long 0x08 8. " [73] ,IF3 Update Enabled Bit[73]" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x08 7. " [72] ,IF3 Update Enabled Bit[72]" "Disabled,Enabled"
|
|
bitfld.long 0x08 6. " [71] ,IF3 Update Enabled Bit[71]" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x08 5. " [70] ,IF3 Update Enabled Bit[70]" "Disabled,Enabled"
|
|
bitfld.long 0x08 4. " [69] ,IF3 Update Enabled Bit[69]" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x08 3. " [68] ,IF3 Update Enabled Bit[68]" "Disabled,Enabled"
|
|
bitfld.long 0x08 2. " [67] ,IF3 Update Enabled Bit[67]" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x08 1. " [66] ,IF3 Update Enabled Bit[66]" "Disabled,Enabled"
|
|
bitfld.long 0x08 0. " [65] ,IF3 Update Enabled Bit[65]" "Disabled,Enabled"
|
|
line.long 0x0C "IF3UENA8_7,Update Enable 8_7 Register"
|
|
bitfld.long 0x0C 31. " IF3UPDATEEN[128] ,IF3 Update Enabled Bit[128]" "Disabled,Enabled"
|
|
bitfld.long 0x0C 30. " [127] ,IF3 Update Enabled Bit[127]" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x0C 29. " [126] ,IF3 Update Enabled Bit[126]" "Disabled,Enabled"
|
|
bitfld.long 0x0C 28. " [125] ,IF3 Update Enabled Bit[125]" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x0C 27. " [124] ,IF3 Update Enabled Bit[124]" "Disabled,Enabled"
|
|
bitfld.long 0x0C 26. " [123] ,IF3 Update Enabled Bit[123]" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x0C 25. " [122] ,IF3 Update Enabled Bit[122]" "Disabled,Enabled"
|
|
bitfld.long 0x0C 24. " [121] ,IF3 Update Enabled Bit[121]" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x0C 23. " [120] ,IF3 Update Enabled Bit[120]" "Disabled,Enabled"
|
|
bitfld.long 0x0C 22. " [119] ,IF3 Update Enabled Bit[119]" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x0C 21. " [118] ,IF3 Update Enabled Bit[118]" "Disabled,Enabled"
|
|
bitfld.long 0x0C 20. " [117] ,IF3 Update Enabled Bit[117]" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x0C 19. " [116] ,IF3 Update Enabled Bit[116]" "Disabled,Enabled"
|
|
bitfld.long 0x0C 18. " [115] ,IF3 Update Enabled Bit[115]" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x0C 17. " [114] ,IF3 Update Enabled Bit[114]" "Disabled,Enabled"
|
|
bitfld.long 0x0C 16. " [113] ,IF3 Update Enabled Bit[113]" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x0C 15. " [112] ,IF3 Update Enabled Bit[112]" "Disabled,Enabled"
|
|
bitfld.long 0x0C 14. " [111] ,IF3 Update Enabled Bit[111]" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x0C 13. " [110] ,IF3 Update Enabled Bit[110]" "Disabled,Enabled"
|
|
bitfld.long 0x0C 12. " [109] ,IF3 Update Enabled Bit[109]" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x0C 11. " [108] ,IF3 Update Enabled Bit[108]" "Disabled,Enabled"
|
|
bitfld.long 0x0C 10. " [107] ,IF3 Update Enabled Bit[107]" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x0C 9. " [106] ,IF3 Update Enabled Bit[106]" "Disabled,Enabled"
|
|
bitfld.long 0x0C 8. " [105] ,IF3 Update Enabled Bit[105]" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x0C 7. " [104] ,IF3 Update Enabled Bit[104]" "Disabled,Enabled"
|
|
bitfld.long 0x0C 6. " [103] ,IF3 Update Enabled Bit[103]" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x0C 5. " [102] ,IF3 Update Enabled Bit[102]" "Disabled,Enabled"
|
|
bitfld.long 0x0C 4. " [101] ,IF3 Update Enabled Bit[101]" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x0C 3. " [100] ,IF3 Update Enabled Bit[100]" "Disabled,Enabled"
|
|
bitfld.long 0x0C 2. " [99] ,IF3 Update Enabled Bit[99]" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x0C 1. " [98] ,IF3 Update Enabled Bit[98]" "Disabled,Enabled"
|
|
bitfld.long 0x0C 0. " [97] ,IF3 Update Enabled Bit[97]" "Disabled,Enabled"
|
|
newline
|
|
group.long 0x1E0++0x03
|
|
line.long 0x0 "IOCTRLTX,TX IO Control Register"
|
|
sif (cpu()!="TMS470MF031"&&cpu()!="TMS470MF042"&&cpu()!="TMS470MF066"&&cpu()!=("TMS570LS10116-ZWT")&&cpu()!=("TMS570LS10216-ZWT")&&cpu()!=("TMS570LS10106-ZWT")&&cpu()!=("TMS570LS10206-ZWT")&&cpu()!=("TMS570LS10116-PGE")&&cpu()!=("TMS570LS10216-PGE")&&cpu()!=("TMS570LS10106-PGE")&&cpu()!=("TMS570LS10206-PGE")&&cpu()!=("TMS570LC4357")&&cpu()!=("TMS570LS0332")&&cpu()!=("TMS570LS0432")&&!cpuis("TMS570LS1114*")&&!cpuis("TMS570LS1115*")&&!cpuis("TMS570LS1224*")&&!cpuis("TMS570LS1225*")&&!cpuis("TMS570LS1227*")&&!cpuis("TMS570LS21*")&&!cpuis("TMS570LS31*")&&!cpuis("TMS570LS0232")&&!cpuis("TMS570LS0714*")&&!cpuis("TMS570LS0914*"))
|
|
bitfld.long 0x00 19. " SR ,Slew Rate Selection of Output Driver" "Normal,Slow"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 18. " PU ,Selection of Pull Direction" "Pull down,Pull up"
|
|
bitfld.long 0x00 17. " PD ,Pull Functionality Disable" "No,Yes"
|
|
bitfld.long 0x00 16. " OD ,Open Drain Mode" "Push pull,Open Drain"
|
|
bitfld.long 0x00 3. " FUNC ,Functionality of Pin" "General,CAN"
|
|
newline
|
|
bitfld.long 0x00 2. " DIR ,Direction of Pin" "Input,Output"
|
|
bitfld.long 0x00 1. " OUT ,Value to Drive to Pin if Configured for I/O" "Low,High"
|
|
bitfld.long 0x00 0. " IN ,Value of Pin" "Low,High"
|
|
group.long 0x1E4++0x03
|
|
line.long 0x0 "IOCTRLRX,RX IO Control Register"
|
|
sif (cpu()!="TMS470MF031"&&cpu()!="TMS470MF042"&&cpu()!="TMS470MF066"&&cpu()!=("TMS570LS10116-ZWT")&&cpu()!=("TMS570LS10216-ZWT")&&cpu()!=("TMS570LS10106-ZWT")&&cpu()!=("TMS570LS10206-ZWT")&&cpu()!=("TMS570LS10116-PGE")&&cpu()!=("TMS570LS10216-PGE")&&cpu()!=("TMS570LS10106-PGE")&&cpu()!=("TMS570LS10206-PGE")&&cpu()!=("TMS570LC4357")&&cpu()!=("TMS570LS0332")&&cpu()!=("TMS570LS0432")&&!cpuis("TMS570LS1114*")&&!cpuis("TMS570LS1115*")&&!cpuis("TMS570LS1224*")&&!cpuis("TMS570LS1225*")&&!cpuis("TMS570LS1227*")&&!cpuis("TMS570LS21*")&&!cpuis("TMS570LS31*")&&!cpuis("TMS570LS0232")&&!cpuis("TMS570LS0714*")&&!cpuis("TMS570LS0914*"))
|
|
bitfld.long 0x00 19. " SR ,Slew Rate Selection of Output Driver" "Normal,Slow"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 18. " PU ,Selection of Pull Direction" "Pull down,Pull up"
|
|
bitfld.long 0x00 17. " PD ,Pull Functionality Disable" "No,Yes"
|
|
bitfld.long 0x00 16. " OD ,Open Drain Mode" "Push pull,Open Drain"
|
|
bitfld.long 0x00 3. " FUNC ,Functionality of Pin" "General,CAN"
|
|
newline
|
|
bitfld.long 0x00 2. " DIR ,Direction of Pin" "Input,Output"
|
|
bitfld.long 0x00 1. " OUT ,Value to Drive to Pin if Configured for I/O" "Low,High"
|
|
bitfld.long 0x00 0. " IN ,Value of Pin" "Low,High"
|
|
sif cpuis("TMS570LS0232")||cpuis("TMS570LS0714*")||cpuis("TMS570LS0914*")
|
|
endian.le
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
endif
|
|
tree.end
|
|
sif cpuis("TMS570LS0714*")||cpuis("TMS570LS0914*")
|
|
tree.open "MibSPI (Multi-Buffered Serial Peripheral Interface Module)"
|
|
tree "MibSPI1"
|
|
base ad:0xFFF7F400
|
|
width 17.
|
|
sif cpuis("TMS570LS0232")||cpuis("TMS570LS0714*")||cpuis("TMS570LS0914*")
|
|
endian.be
|
|
endif
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "SPIGCR0,SPI Global Control Register 0"
|
|
bitfld.long 0x00 0. " NRESET ,Reset bit for the module" "No reset,Reset"
|
|
group.long 0x04++0x0F
|
|
line.long 0x00 "SPIGCR1,SPI Global Control Register 1"
|
|
bitfld.long 0x00 24. " SPIEN ,SPI enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " LOOPBACK ,Internal loop-back test mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " POWERDOWN ,SPI state machine enters a power-down state" "No power-down,Power-down"
|
|
newline
|
|
bitfld.long 0x00 1. " CLKMOD ,Clock mode" "External,Internally"
|
|
bitfld.long 0x00 0. " MASTER ,SPISIMO/SPISOMI pin direction determination" "Input/output,Output/input"
|
|
line.long 0x04 "SPIINT0,SPI Interrupt Register"
|
|
bitfld.long 0x04 24. " ENABLEHIGHZ ,SPIENA pin high-impedance enable" "Inactive,Active"
|
|
bitfld.long 0x04 16. " DMAREQEN ,DMA request enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 9. " TXINTENA ,TX interrupt flag enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x04 8. " RXINTENA ,RX interrupt flag enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 6. " RXOVRNINTENA ,Overrun interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 4. " BITERRENA ,Enables interrupt on bit error" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x04 3. " DESYNCENA ,Enables interrupt on desynchronized slave" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " PARERRENA ,Enables interrupt-on-parity-error" "Disabled,Enabled"
|
|
bitfld.long 0x04 1. " TIMEOUTENA ,Enables interrupt on ENA signal time-out" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x04 0. " DLENERRENA ,Data length error interrupt enable" "Disabled,Enabled"
|
|
line.long 0x08 "SPILVL,SPI Interrupt Level Register"
|
|
bitfld.long 0x08 9. " TXINTLVL ,Transmit interrupt level" "INT0,INT1"
|
|
bitfld.long 0x08 8. " RXINTLVL ,Receive interrupt level" "INT0,INT1"
|
|
sif !cpuis("TMS570LS0232")
|
|
bitfld.long 0x08 6. " RXOVRNINTLVL ,Receive overrun interrupt level" "INT0,INT1"
|
|
endif
|
|
newline
|
|
bitfld.long 0x08 4. " BITERRLVL ,Bit error interrupt level" "INT0,INT1"
|
|
bitfld.long 0x08 3. " DESYNCLVL ,Desynchronized slave interrupt level (master mode only)" "INT0,INT1"
|
|
bitfld.long 0x08 2. " PARERRLVL ,Parity error interrupt level" "INT0,INT1"
|
|
newline
|
|
bitfld.long 0x08 1. " TIMEOUTLVL ,SPIENA pin time-out interrupt level" "INT0,INT1"
|
|
bitfld.long 0x08 0. " DLENERRLVL ,Data length error interrupt level (line) select" "INT0,INT1"
|
|
line.long 0x0C "SPIFLG,SPI Flag Register"
|
|
bitfld.long 0x0C 24. " BUFINITACTIVE ,Indicates the status of multi-buffer initialization process" "Completed,Not completed"
|
|
bitfld.long 0x0C 9. " TXINTFLG ,Transmitter-empty interrupt flag" "No interrupt,Interrupt"
|
|
eventfld.long 0x0C 8. " RXINTFLG ,Receiver-full interrupt flag" "No interrupt,Interrupt"
|
|
newline
|
|
eventfld.long 0x0C 6. " RXOVRNINTFLG ,Overrun interrupt enable" "Disabled,Enabled"
|
|
eventfld.long 0x0C 4. " BITERRFLG ,Enables interrupt on bit error" "Disabled,Enabled"
|
|
eventfld.long 0x0C 3. " DESYNCFLG ,Enables interrupt on desynchronized slave" "No interrupt,Interrupt"
|
|
newline
|
|
eventfld.long 0x0C 2. " PARITYERRFLG ,Enables interrupt-on-parity-error" "No error,Error"
|
|
eventfld.long 0x0C 1. " TIMEOUTFLG ,Enables interrupt on ENA signal time-out" "No interrupt,Interrupt"
|
|
eventfld.long 0x0C 0. " DLENERRFLG ,Data length error interrupt enable" "No interrupt,Interrupt"
|
|
group.long 0x14++0x23
|
|
line.long 0x00 "SPIPC0,SPI Pin Control Register 0"
|
|
sif !cpuis("TMS570LS0232")&&!cpuis("TMS570LS0332")&&!cpuis("TMS570LS0432")
|
|
bitfld.long 0x00 31. " SOMIFUN7 ,SPISOMI[7] pin function" "GIO,SPI"
|
|
bitfld.long 0x00 30. " SOMIFUN6 ,SPISOMI[6] pin function" "GIO,SPI"
|
|
bitfld.long 0x00 29. " SOMIFUN5 ,SPISOMI[5] pin function" "GIO,SPI"
|
|
newline
|
|
bitfld.long 0x00 28. " SOMIFUN4 ,SPISOMI[4] pin function" "GIO,SPI"
|
|
bitfld.long 0x00 27. " SOMIFUN3 ,SPISOMI[3] pin function" "GIO,SPI"
|
|
bitfld.long 0x00 26. " SOMIFUN2 ,SPISOMI[2] pin function" "GIO,SPI"
|
|
newline
|
|
bitfld.long 0x00 25. " SOMIFUN1 ,SPISOMI[1] pin function" "GIO,SPI"
|
|
bitfld.long 0x00 24. " SOMIFUN0 ,SPISOMI[0] pin function (mirror of bit 11)" "GIO,SPI"
|
|
bitfld.long 0x00 23. " SIMOFUN7 ,SPISIMO[7] pin function" "GIO,SPI"
|
|
newline
|
|
bitfld.long 0x00 22. " SIMOFUN6 ,SPISIMO[6] pin function" "GIO,SPI"
|
|
bitfld.long 0x00 21. " SIMOFUN5 ,SPISIMO[5] pin function" "GIO,SPI"
|
|
bitfld.long 0x00 20. " SIMOFUN4 ,SPISIMO[4] pin function" "GIO,SPI"
|
|
newline
|
|
bitfld.long 0x00 19. " SIMOFUN3 ,SPISIMO[3] pin function" "GIO,SPI"
|
|
bitfld.long 0x00 18. " SIMOFUN2 ,SPISIMO[2] pin function" "GIO,SPI"
|
|
bitfld.long 0x00 17. " SIMOFUN1 ,SPISIMO[1] pin function" "GIO,SPI"
|
|
newline
|
|
bitfld.long 0x00 16. " SIMOFUN0 ,SPISIMO[0] pin function (mirror of bit 10)" "GIO,SPI"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 11. " SOMIFUN0 ,SPISOMI[0] pin function" "GIO,SPI"
|
|
bitfld.long 0x00 10. " SIMOFUN0 ,SPISIMO[0] pin function" "GIO,SPI"
|
|
newline
|
|
bitfld.long 0x00 9. " CLKFUN ,SPI clock function" "GIO,SPI"
|
|
bitfld.long 0x00 8. " ENAFUN ,SPIENA function" "GIO,SPI"
|
|
bitfld.long 0x00 7. " SCSFUN7 ,SPISCS7 function 7" "GIO,SPI"
|
|
newline
|
|
bitfld.long 0x00 6. " SCSFUN6 ,SPISCS6 function 6" "GIO,SPI"
|
|
bitfld.long 0x00 5. " SCSFUN5 ,SPISCS5 function 5" "GIO,SPI"
|
|
bitfld.long 0x00 4. " SCSFUN4 ,SPISCS4 function 4" "GIO,SPI"
|
|
newline
|
|
bitfld.long 0x00 3. " SCSFUN3 ,SPISCS3 function 3" "GIO,SPI"
|
|
bitfld.long 0x00 2. " SCSFUN2 ,SPISCS2 function 2" "GIO,SPI"
|
|
bitfld.long 0x00 1. " SCSFUN1 ,SPISCS1 function 1" "GIO,SPI"
|
|
newline
|
|
bitfld.long 0x00 0. " SCSFUN0 ,SPISCS0 function 0" "GIO,SPI"
|
|
line.long 0x04 "SPIPC1,SPI Pin Control Register 1"
|
|
bitfld.long 0x04 31. " SOMIDIR7 ,SPISOMI[7] pin direction" "GIO,SPI"
|
|
bitfld.long 0x04 30. " SOMIDIR6 ,SPISOMI[6] pin direction" "GIO,SPI"
|
|
bitfld.long 0x04 29. " SOMIDIR5 ,SPISOMI[5] pin direction" "GIO,SPI"
|
|
newline
|
|
bitfld.long 0x04 28. " SOMIDIR4 ,SPISOMI[4] pin direction" "GIO,SPI"
|
|
bitfld.long 0x04 27. " SOMIDIR3 ,SPISOMI[3] pin direction" "GIO,SPI"
|
|
bitfld.long 0x04 26. " SOMIDIR2 ,SPISOMI[2] pin direction" "GIO,SPI"
|
|
newline
|
|
bitfld.long 0x04 25. " SOMIDIR1 ,SPISOMI[1] pin direction" "GIO,SPI"
|
|
bitfld.long 0x04 24. " SOMIDIR0 ,SPISOMI[0] pin direction (mirror of bit 11)" "GIO,SPI"
|
|
bitfld.long 0x04 23. " SIMODIR7 ,SPISIMO[7] pin direction" "GIO,SPI"
|
|
newline
|
|
bitfld.long 0x04 22. " SIMODIR6 ,SPISIMO[6] pin direction" "GIO,SPI"
|
|
bitfld.long 0x04 21. " SIMODIR5 ,SPISIMO[5] pin direction" "GIO,SPI"
|
|
bitfld.long 0x04 20. " SIMODIR4 ,SPISIMO[4] pin direction" "GIO,SPI"
|
|
newline
|
|
bitfld.long 0x04 19. " SIMODIR3 ,SPISIMO[3] pin direction" "GIO,SPI"
|
|
bitfld.long 0x04 18. " SIMODIR2 ,SPISIMO[2] pin direction" "GIO,SPI"
|
|
bitfld.long 0x04 17. " SIMODIR1 ,SPISIMO[1] pin direction" "GIO,SPI"
|
|
newline
|
|
bitfld.long 0x04 16. " SIMODIR0 ,SPISIMO[0] pin direction (mirror of bit 10)" "GIO,SPI"
|
|
bitfld.long 0x04 11. " SOMIDIR0 ,SPISOMI[0] pin direction" "GIO,SPI"
|
|
bitfld.long 0x04 10. " SIMODIR0 ,SPISIMO[0] pin direction" "GIO,SPI"
|
|
newline
|
|
bitfld.long 0x04 9. " CLKDIR ,SPI clock direction" "GIO,SPI"
|
|
bitfld.long 0x04 8. " ENADIR ,SPIENA direction" "GIO,SPI"
|
|
bitfld.long 0x04 7. " SCSDIR7 ,SPISCS7 direction 7" "GIO,SPI"
|
|
newline
|
|
bitfld.long 0x04 6. " SCSDIR6 ,SPISCS6 direction 6" "GIO,SPI"
|
|
bitfld.long 0x04 5. " SCSDIR5 ,SPISCS5 direction 5" "GIO,SPI"
|
|
bitfld.long 0x04 4. " SCSDIR4 ,SPISCS4 direction 4" "GIO,SPI"
|
|
newline
|
|
bitfld.long 0x04 3. " SCSDIR3 ,SPISCS3 direction 3" "GIO,SPI"
|
|
bitfld.long 0x04 2. " SCSDIR2 ,SPISCS2 direction 2" "GIO,SPI"
|
|
bitfld.long 0x04 1. " SCSDIR1 ,SPISCS1 direction 1" "GIO,SPI"
|
|
newline
|
|
bitfld.long 0x04 0. " SCSDIR0 ,SPISCS0 direction 0" "GIO,SPI"
|
|
line.long 0x08 "SPIPC2,SPI Pin Control Register 2"
|
|
bitfld.long 0x08 31. " SOMIDIN7 ,SPISOMI[7] data in" "0,1"
|
|
bitfld.long 0x08 30. " SOMIDIN6 ,SPISOMI[6] data in" "0,1"
|
|
bitfld.long 0x08 29. " SOMIDIN5 ,SPISOMI[5] data in" "0,1"
|
|
newline
|
|
bitfld.long 0x08 28. " SOMIDIN4 ,SPISOMI[4] data in" "0,1"
|
|
bitfld.long 0x08 27. " SOMIDIN3 ,SPISOMI[3] data in" "0,1"
|
|
bitfld.long 0x08 26. " SOMIDIN2 ,SPISOMI[2] data in" "0,1"
|
|
newline
|
|
bitfld.long 0x08 25. " SOMIDIN1 ,SPISOMI[1] data in" "0,1"
|
|
bitfld.long 0x08 24. " SOMIDIN0 ,SPISOMI[0] data in (mirror of bit 11)" "0,1"
|
|
bitfld.long 0x08 23. " SIMODIN7 ,SPISIMO[7] data in" "0,1"
|
|
newline
|
|
bitfld.long 0x08 22. " SIMODIN6 ,SPISIMO[6] data in" "0,1"
|
|
bitfld.long 0x08 21. " SIMODIN5 ,SPISIMO[5] data in" "0,1"
|
|
bitfld.long 0x08 20. " SIMODIN4 ,SPISIMO[4] data in" "0,1"
|
|
newline
|
|
bitfld.long 0x08 19. " SIMODIN3 ,SPISIMO[3] data in" "0,1"
|
|
bitfld.long 0x08 18. " SIMODIN2 ,SPISIMO[2] data in" "0,1"
|
|
bitfld.long 0x08 17. " SIMODIN1 ,SPISIMO[1] data in" "0,1"
|
|
newline
|
|
bitfld.long 0x08 16. " SIMODIN0 ,SPISIMO[0] data in (mirror of bit 10)" "0,1"
|
|
bitfld.long 0x08 11. " SOMIDIN0 ,SPISOMI[0] data in" "0,1"
|
|
bitfld.long 0x08 10. " SIMODIN0 ,SPISIMO[0] data in" "0,1"
|
|
newline
|
|
bitfld.long 0x08 9. " CLKDIN ,SPI clock data in" "0,1"
|
|
bitfld.long 0x08 8. " ENADIN ,SPIENA data in" "0,1"
|
|
bitfld.long 0x08 7. " SCSDIN7 ,SPISCS7 data in" "0,1"
|
|
newline
|
|
bitfld.long 0x08 6. " SCSDIN6 ,SPISCS6 data in" "0,1"
|
|
bitfld.long 0x08 5. " SCSDIN5 ,SPISCS5 data in" "0,1"
|
|
bitfld.long 0x08 4. " SCSDIN4 ,SPISCS4 data in" "0,1"
|
|
newline
|
|
bitfld.long 0x08 3. " SCSDIN3 ,SPISCS3 data in" "0,1"
|
|
bitfld.long 0x08 2. " SCSDIN2 ,SPISCS2 data in" "0,1"
|
|
bitfld.long 0x08 1. " SCSDIN1 ,SPISCS1 data in" "0,1"
|
|
newline
|
|
bitfld.long 0x08 0. " SCSDIN0 ,SPISCS0 direction 0" "0,1"
|
|
line.long 0x0C "SPIPC3,SPI Pin Control Register 3"
|
|
bitfld.long 0x0C 31. " SOMIDOUT7 ,SPISOMI[7] data out write" "0,1"
|
|
bitfld.long 0x0C 30. " SOMIDOUT6 ,SPISOMI[6] data out write" "0,1"
|
|
bitfld.long 0x0C 29. " SOMIDOUT5 ,SPISOMI[5] data out write" "0,1"
|
|
newline
|
|
bitfld.long 0x0C 28. " SOMIDOUT4 ,SPISOMI[4] data out write" "0,1"
|
|
bitfld.long 0x0C 27. " SOMIDOUT3 ,SPISOMI[3] data out write" "0,1"
|
|
bitfld.long 0x0C 26. " SOMIDOUT2 ,SPISOMI[2] data out write" "0,1"
|
|
newline
|
|
bitfld.long 0x0C 25. " SOMIDOUT1 ,SPISOMI[1] data out write" "0,1"
|
|
bitfld.long 0x0C 24. " SOMIDOUT0 ,SPISOMI[0] data out write (mirror of bit 11)" "0,1"
|
|
bitfld.long 0x0C 23. " SIMODOUT7 ,SPISIMO[7] data out write" "0,1"
|
|
newline
|
|
bitfld.long 0x0C 22. " SIMODOUT6 ,SPISIMO[6] data out write" "0,1"
|
|
bitfld.long 0x0C 21. " SIMODOUT5 ,SPISIMO[5] data out write" "0,1"
|
|
bitfld.long 0x0C 20. " SIMODOUT4 ,SPISIMO[4] data out write" "0,1"
|
|
newline
|
|
bitfld.long 0x0C 19. " SIMODOUT3 ,SPISIMO[3] data out write" "0,1"
|
|
bitfld.long 0x0C 18. " SIMODOUT2 ,SPISIMO[2] data out write" "0,1"
|
|
bitfld.long 0x0C 17. " SIMODOUT1 ,SPISIMO[1] data out write" "0,1"
|
|
newline
|
|
bitfld.long 0x0C 16. " SIMODOUT0 ,SPISIMO[0] data out write (mirror of bit 10)" "0,1"
|
|
bitfld.long 0x0C 11. " SOMIDOUT0 ,SPISOMI[0] data out write" "0,1"
|
|
bitfld.long 0x0C 10. " SIMODOUT0 ,SPISIMO[0] data out write" "0,1"
|
|
newline
|
|
bitfld.long 0x0C 9. " CLKDOUT ,SPI clock data out write" "0,1"
|
|
bitfld.long 0x0C 8. " ENADOUT ,SPIENA data out write" "0,1"
|
|
bitfld.long 0x0C 7. " SCSDOUT7 ,SPISCS7 data out write" "0,1"
|
|
newline
|
|
bitfld.long 0x0C 6. " SCSDOUT6 ,SPISCS6 data out write" "0,1"
|
|
bitfld.long 0x0C 5. " SCSDOUT5 ,SPISCS5 data out write" "0,1"
|
|
bitfld.long 0x0C 4. " SCSDOUT4 ,SPISCS4 data out write" "0,1"
|
|
newline
|
|
bitfld.long 0x0C 3. " SCSDOUT3 ,SPISCS3 data out write" "0,1"
|
|
bitfld.long 0x0C 2. " SCSDOUT2 ,SPISCS2 data out write" "0,1"
|
|
bitfld.long 0x0C 1. " SCSDOUT1 ,SPISCS1 data out write" "0,1"
|
|
newline
|
|
bitfld.long 0x0C 0. " SCSDOUT0 ,SPISCS0 data out write" "0,1"
|
|
line.long 0x10 "SPIPC4,SPI Pin Control Register 4"
|
|
bitfld.long 0x10 31. " SOMISET7 ,SPISOMI[7] data out set" "0,1"
|
|
bitfld.long 0x10 30. " SOMISET6 ,SPISOMI[6] data out set" "0,1"
|
|
bitfld.long 0x10 29. " SOMISET5 ,SPISOMI[5] data out set" "0,1"
|
|
newline
|
|
bitfld.long 0x10 28. " SOMISET4 ,SPISOMI[4] data out set" "0,1"
|
|
bitfld.long 0x10 27. " SOMISET3 ,SPISOMI[3] data out set" "0,1"
|
|
bitfld.long 0x10 26. " SOMISET2 ,SPISOMI[2] data out set" "0,1"
|
|
newline
|
|
bitfld.long 0x10 25. " SOMISET1 ,SPISOMI[1] data out set" "0,1"
|
|
bitfld.long 0x10 24. " SOMISET0 ,SPISOMI[0] data out set (mirror of bit 11)" "0,1"
|
|
bitfld.long 0x10 23. " SIMOSET7 ,SPISIMO[7] data out set" "0,1"
|
|
newline
|
|
bitfld.long 0x10 22. " SIMOSET6 ,SPISIMO[6] data out set" "0,1"
|
|
bitfld.long 0x10 21. " SIMOSET5 ,SPISIMO[5] data out set" "0,1"
|
|
bitfld.long 0x10 20. " SIMOSET4 ,SPISIMO[4] data out set" "0,1"
|
|
newline
|
|
bitfld.long 0x10 19. " SIMOSET3 ,SPISIMO[3] data out set" "0,1"
|
|
bitfld.long 0x10 18. " SIMOSET2 ,SPISIMO[2] data out set" "0,1"
|
|
bitfld.long 0x10 17. " SIMOSET1 ,SPISIMO[1] data out set" "0,1"
|
|
newline
|
|
bitfld.long 0x10 16. " SIMOSET0 ,SPISIMO[0] data out set (mirror of bit 10)" "0,1"
|
|
bitfld.long 0x10 11. " SOMISET0 ,SPISOMI[0] data out set" "0,1"
|
|
bitfld.long 0x10 10. " SIMOSET0 ,SPISIMO[0] data out set" "0,1"
|
|
newline
|
|
bitfld.long 0x10 9. " CLKSET ,SPI clock data out set" "0,1"
|
|
bitfld.long 0x10 8. " ENASET ,SPIENA data out set" "0,1"
|
|
bitfld.long 0x10 7. " SCSSET7 ,SPISCS7 data out set" "0,1"
|
|
newline
|
|
bitfld.long 0x10 6. " SCSSET6 ,SPISCS6 data out set" "0,1"
|
|
bitfld.long 0x10 5. " SCSSET5 ,SPISCS5 data out set" "0,1"
|
|
bitfld.long 0x10 4. " SCSSET4 ,SPISCS4 data out set" "0,1"
|
|
newline
|
|
bitfld.long 0x10 3. " SCSSET3 ,SPISCS3 data out set" "0,1"
|
|
bitfld.long 0x10 2. " SCSSET2 ,SPISCS2 data out set" "0,1"
|
|
bitfld.long 0x10 1. " SCSSET1 ,SPISCS1 data out set" "0,1"
|
|
newline
|
|
bitfld.long 0x10 0. " SCSSET0 ,SPISCS0 data out set" "0,1"
|
|
line.long 0x14 "SPIPC5,SPI Pin Control Register 5"
|
|
bitfld.long 0x14 31. " SOMICLR7 ,SPISOMI[7] data out clear" "0,1"
|
|
bitfld.long 0x14 30. " SOMICLR6 ,SPISOMI[6] data out clear" "0,1"
|
|
bitfld.long 0x14 29. " SOMICLR5 ,SPISOMI[5] data out clear" "0,1"
|
|
newline
|
|
bitfld.long 0x14 28. " SOMICLR4 ,SPISOMI[4] data out clear" "0,1"
|
|
bitfld.long 0x14 27. " SOMICLR3 ,SPISOMI[3] data out clear" "0,1"
|
|
bitfld.long 0x14 26. " SOMICLR2 ,SPISOMI[2] data out clear" "0,1"
|
|
newline
|
|
bitfld.long 0x14 25. " SOMICLR1 ,SPISOMI[1] data out clear" "0,1"
|
|
bitfld.long 0x14 24. " SOMICLR0 ,SPISOMI[0] data out clear (mirror of bit 11)" "0,1"
|
|
bitfld.long 0x14 23. " SIMOCLR7 ,SPISIMO[7] data out clear" "0,1"
|
|
newline
|
|
bitfld.long 0x14 22. " SIMOCLR6 ,SPISIMO[6] data out clear" "0,1"
|
|
bitfld.long 0x14 21. " SIMOCLR5 ,SPISIMO[5] data out clear" "0,1"
|
|
bitfld.long 0x14 20. " SIMOCLR4 ,SPISIMO[4] data out clear" "0,1"
|
|
newline
|
|
bitfld.long 0x14 19. " SIMOCLR3 ,SPISIMO[3] data out clear" "0,1"
|
|
bitfld.long 0x14 18. " SIMOCLR2 ,SPISIMO[2] data out clear" "0,1"
|
|
bitfld.long 0x14 17. " SIMOCLR1 ,SPISIMO[1] data out clear" "0,1"
|
|
newline
|
|
bitfld.long 0x14 16. " SIMOCLR0 ,SPISIMO[0] data out clear (mirror of bit 10)" "0,1"
|
|
bitfld.long 0x14 11. " SOMICLR0 ,SPISOMI[0] data out clear" "0,1"
|
|
bitfld.long 0x14 10. " SIMOCLR0 ,SPISIMO[0] data out clear" "0,1"
|
|
newline
|
|
bitfld.long 0x14 9. " CLKCLR ,SPI clock data out clear" "0,1"
|
|
bitfld.long 0x14 8. " ENACLR ,SPIENA data out clear" "0,1"
|
|
bitfld.long 0x14 7. " SCSCLR7 ,SPISCS7 data out clear" "0,1"
|
|
newline
|
|
bitfld.long 0x14 6. " SCSCLR6 ,SPISCS6 data out clear" "0,1"
|
|
bitfld.long 0x14 5. " SCSCLR5 ,SPISCS5 data out clear" "0,1"
|
|
bitfld.long 0x14 4. " SCSCLR4 ,SPISCS4 data out clear" "0,1"
|
|
newline
|
|
bitfld.long 0x14 3. " SCSCLR3 ,SPISCS3 data out clear" "0,1"
|
|
bitfld.long 0x14 2. " SCSCLR2 ,SPISCS2 data out clear" "0,1"
|
|
bitfld.long 0x14 1. " SCSCLR1 ,SPISCS1 data out clear" "0,1"
|
|
newline
|
|
bitfld.long 0x14 0. " SCSCLR0 ,SPISCS0 data out clear" "0,1"
|
|
line.long 0x18 "SPIPC6,SPI Pin Control Register 6"
|
|
bitfld.long 0x18 31. " SOMIPDR7 ,SPISOMI[7] open drain enable" "Disabled,Enabled"
|
|
bitfld.long 0x18 30. " SOMIPDR6 ,SPISOMI[6] open drain enable" "Disabled,Enabled"
|
|
bitfld.long 0x18 29. " SOMIPDR5 ,SPISOMI[5] open drain enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x18 28. " SOMIPDR4 ,SPISOMI[4] open drain enable" "Disabled,Enabled"
|
|
bitfld.long 0x18 27. " SOMIPDR3 ,SPISOMI[3] open drain enable" "Disabled,Enabled"
|
|
bitfld.long 0x18 26. " SOMIPDR2 ,SPISOMI[2] open drain enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x18 25. " SOMIPDR1 ,SPISOMI[1] open drain enable" "Disabled,Enabled"
|
|
bitfld.long 0x18 24. " SOMIPDR0 ,SPISOMI[0] open drain enable (mirror of bit 11)" "Disabled,Enabled"
|
|
bitfld.long 0x18 23. " SIMOPDR7 ,SPISIMO[7] open drain enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x18 22. " SIMOPDR6 ,SPISIMO[6] open drain enable" "Disabled,Enabled"
|
|
bitfld.long 0x18 21. " SIMOPDR5 ,SPISIMO[5] open drain enable" "Disabled,Enabled"
|
|
bitfld.long 0x18 20. " SIMOPDR4 ,SPISIMO[4] open drain enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x18 19. " SIMOPDR3 ,SPISIMO[3] open drain enable" "Disabled,Enabled"
|
|
bitfld.long 0x18 18. " SIMOPDR2 ,SPISIMO[2] open drain enable" "Disabled,Enabled"
|
|
bitfld.long 0x18 17. " SIMOPDR1 ,SPISIMO[1] open drain enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x18 16. " SIMOPDR0 ,SPISIMO[0] open drain enable (mirror of bit 10)" "Disabled,Enabled"
|
|
bitfld.long 0x18 11. " SOMIPDR0 ,SPISOMI[0] open drain enable" "Disabled,Enabled"
|
|
bitfld.long 0x18 10. " SIMOPDR0 ,SPISIMO[0] open drain enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x18 9. " CLKPDR ,SPI clock open drain enable" "Disabled,Enabled"
|
|
bitfld.long 0x18 8. " ENAPDR ,SPIENA open drain enable" "Disabled,Enabled"
|
|
bitfld.long 0x18 7. " SCSPDR7 ,SPISCS7 open drain enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x18 6. " SCSPDR6 ,SPISCS6 open drain enable" "Disabled,Enabled"
|
|
bitfld.long 0x18 5. " SCSPDR5 ,SPISCS5 open drain enable" "Disabled,Enabled"
|
|
bitfld.long 0x18 4. " SCSPDR4 ,SPISCS4 open drain enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x18 3. " SCSPDR3 ,SPISCS3 open drain enable" "Disabled,Enabled"
|
|
bitfld.long 0x18 2. " SCSPDR2 ,SPISCS2 open drain enable" "Disabled,Enabled"
|
|
bitfld.long 0x18 1. " SCSPDR1 ,SPISCS1 open drain enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x18 0. " SCSPDR0 ,SPISCS0 open drain enable" "Disabled,Enabled"
|
|
line.long 0x1C "SPIPC7,SPI Pin Control Register 7"
|
|
bitfld.long 0x1C 31. " SOMIPDIS7 ,SPISOMI[7] pull control enable/disable" "No,Yes"
|
|
bitfld.long 0x1C 30. " SOMIPDIS6 ,SPISOMI[6] pull control enable/disable" "No,Yes"
|
|
bitfld.long 0x1C 29. " SOMIPDIS5 ,SPISOMI[5] pull control enable/disable" "No,Yes"
|
|
newline
|
|
bitfld.long 0x1C 28. " SOMIPDIS4 ,SPISOMI[4] pull control enable/disable" "No,Yes"
|
|
bitfld.long 0x1C 27. " SOMIPDIS3 ,SPISOMI[3] pull control enable/disable" "No,Yes"
|
|
bitfld.long 0x1C 26. " SOMIPDIS2 ,SPISOMI[2] pull control enable/disable" "No,Yes"
|
|
newline
|
|
bitfld.long 0x1C 25. " SOMIPDIS1 ,SPISOMI[1] pull control enable/disable" "No,Yes"
|
|
bitfld.long 0x1C 24. " SOMIPDIS0 ,SPISOMI[0] pull control enable/disable (mirror of bit 11)" "No,Yes"
|
|
bitfld.long 0x1C 23. " SIMOPDIS7 ,SPISIMO[7] pull control enable/disable" "No,Yes"
|
|
newline
|
|
bitfld.long 0x1C 22. " SIMOPDIS6 ,SPISIMO[6] pull control enable/disable" "No,Yes"
|
|
bitfld.long 0x1C 21. " SIMOPDIS5 ,SPISIMO[5] pull control enable/disable" "No,Yes"
|
|
bitfld.long 0x1C 20. " SIMOPDIS4 ,SPISIMO[4] pull control enable/disable" "No,Yes"
|
|
newline
|
|
bitfld.long 0x1C 19. " SIMOPDIS3 ,SPISIMO[3] pull control enable/disable" "No,Yes"
|
|
bitfld.long 0x1C 18. " SIMOPDIS2 ,SPISIMO[2] pull control enable/disable" "No,Yes"
|
|
bitfld.long 0x1C 17. " SIMOPDIS1 ,SPISIMO[1] pull control enable/disable" "No,Yes"
|
|
newline
|
|
bitfld.long 0x1C 16. " SIMOPDIS0 ,SPISIMO[0] pull control enable/disable (mirror of bit 10)" "No,Yes"
|
|
bitfld.long 0x1C 11. " SOMIPDIS0 ,SPISOMI[0] pull control enable/disable" "No,Yes"
|
|
bitfld.long 0x1C 10. " SIMOPDIS0 ,SPISIMO[0] pull control enable/disable" "No,Yes"
|
|
newline
|
|
bitfld.long 0x1C 9. " CLKPDIS ,SPI clock pull control enable/disable" "No,Yes"
|
|
bitfld.long 0x1C 8. " ENAPDIS ,SPIENA pull control enable/disable" "No,Yes"
|
|
bitfld.long 0x1C 7. " SCSPDIS7 ,SPISCS7 pull control enable/disable" "No,Yes"
|
|
newline
|
|
bitfld.long 0x1C 6. " SCSPDIS6 ,SPISCS6 pull control enable/disable" "No,Yes"
|
|
bitfld.long 0x1C 5. " SCSPDIS5 ,SPISCS5 pull control enable/disable" "No,Yes"
|
|
bitfld.long 0x1C 4. " SCSPDIS4 ,SPISCS4 pull control enable/disable" "No,Yes"
|
|
newline
|
|
bitfld.long 0x1C 3. " SCSPDIS3 ,SPISCS3 pull control enable/disable" "No,Yes"
|
|
bitfld.long 0x1C 2. " SCSPDIS2 ,SPISCS2 pull control enable/disable" "No,Yes"
|
|
bitfld.long 0x1C 1. " SCSPDIS1 ,SPISCS1 pull control enable/disable" "No,Yes"
|
|
newline
|
|
bitfld.long 0x1C 0. " SCSPDIS0 ,SPISCS0 pull control enable/disable" "No,Yes"
|
|
line.long 0x20 "SPIPC8,SPI Pin Control Register 8"
|
|
bitfld.long 0x20 31. " SOMIPSEL7 ,SPISOMI[7] pull select" "Pull down,Pull up"
|
|
bitfld.long 0x20 30. " SOMIPSEL6 ,SPISOMI[6] pull select" "Pull down,Pull up"
|
|
bitfld.long 0x20 29. " SOMIPSEL5 ,SPISOMI[5] pull select" "Pull down,Pull up"
|
|
newline
|
|
bitfld.long 0x20 28. " SOMIPSEL4 ,SPISOMI[4] pull select" "Pull down,Pull up"
|
|
bitfld.long 0x20 27. " SOMIPSEL3 ,SPISOMI[3] pull select" "Pull down,Pull up"
|
|
bitfld.long 0x20 26. " SOMIPSEL2 ,SPISOMI[2] pull select" "Pull down,Pull up"
|
|
newline
|
|
bitfld.long 0x20 25. " SOMIPSEL1 ,SPISOMI[1] pull select" "Pull down,Pull up"
|
|
bitfld.long 0x20 24. " SOMIPSEL0 ,SPISOMI[0] pull select (mirror of bit 11)" "Pull down,Pull up"
|
|
bitfld.long 0x20 23. " SIMOPSEL7 ,SPISIMO[7] pull select" "Pull down,Pull up"
|
|
newline
|
|
bitfld.long 0x20 22. " SIMOPSEL6 ,SPISIMO[6] pull select" "Pull down,Pull up"
|
|
bitfld.long 0x20 21. " SIMOPSEL5 ,SPISIMO[5] pull select" "Pull down,Pull up"
|
|
bitfld.long 0x20 20. " SIMOPSEL4 ,SPISIMO[4] pull select" "Pull down,Pull up"
|
|
newline
|
|
bitfld.long 0x20 19. " SIMOPSEL3 ,SPISIMO[3] pull select" "Pull down,Pull up"
|
|
bitfld.long 0x20 18. " SIMOPSEL2 ,SPISIMO[2] pull select" "Pull down,Pull up"
|
|
bitfld.long 0x20 17. " SIMOPSEL1 ,SPISIMO[1] pull select" "Pull down,Pull up"
|
|
newline
|
|
bitfld.long 0x20 16. " SIMOPSEL0 ,SPISIMO[0] pull select (mirror of bit 10)" "Pull down,Pull up"
|
|
bitfld.long 0x20 11. " SOMIPSEL0 ,SPISOMI[0] pull select" "Pull down,Pull up"
|
|
bitfld.long 0x20 10. " SIMOPSEL0 ,SPISIMO[0] pull select" "Pull down,Pull up"
|
|
newline
|
|
bitfld.long 0x20 9. " CLKPSEL ,SPI clock pull select" "Pull down,Pull up"
|
|
bitfld.long 0x20 8. " ENAPSEL ,SPIENA pull select" "Pull down,Pull up"
|
|
bitfld.long 0x20 7. " SCSPSEL7 ,SPISCS7 pull select" "Pull down,Pull up"
|
|
newline
|
|
bitfld.long 0x20 6. " SCSPSEL6 ,SPISCS6 pull select" "Pull down,Pull up"
|
|
bitfld.long 0x20 5. " SCSPSEL5 ,SPISCS5 pull select" "Pull down,Pull up"
|
|
bitfld.long 0x20 4. " SCSPSEL4 ,SPISCS4 pull select" "Pull down,Pull up"
|
|
newline
|
|
bitfld.long 0x20 3. " SCSPSEL3 ,SPISCS3 pull select" "Pull down,Pull up"
|
|
bitfld.long 0x20 2. " SCSPSEL2 ,SPISCS2 pull select" "Pull down,Pull up"
|
|
bitfld.long 0x20 1. " SCSPSEL1 ,SPISCS1 pull select" "Pull down,Pull up"
|
|
newline
|
|
bitfld.long 0x20 0. " SCSPSEL0 ,SPISCS0 pull select" "Pull down,Pull up"
|
|
group.long 0x38++0x07
|
|
line.long 0x00 "SPIDAT0,SPI Transmit Data Register 0"
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,SPI transmit data"
|
|
line.long 0x04 "SPIDAT1,Transmit Data Register 1"
|
|
bitfld.long 0x04 28. " CSHOLD ,Chip select hold mode" "Inactive,Active"
|
|
bitfld.long 0x04 26. " WDEL ,Enable the delay counter at the end of the current transaction" "No delay,After transaction"
|
|
bitfld.long 0x04 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
newline
|
|
hexmask.long.byte 0x04 16.--23. 1. " CSNR ,Chip select number"
|
|
hexmask.long.word 0x04 0.--15. 1. " TXDATA ,Transfer data"
|
|
hgroup.long 0x40++0x03
|
|
hide.long 0x00 "SPIBUF,SPI Receive Buffer Register"
|
|
in
|
|
rgroup.long 0x44++0x03
|
|
line.long 0x00 "SPIEMU,SPI Emulation Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " EMU_RXDATA ,SPI receive data"
|
|
sif cpuis("TMS570LS0232")||cpuis("TMS570LS0714*")||cpuis("TMS570LS0914*")
|
|
group.long 0x48++0x03
|
|
line.long 0x00 "SPIDELAY,SPI Delay Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " C2TDELAY ,Chip-select-active to transmit-start delay"
|
|
hexmask.long.byte 0x00 16.--23. 1. " T2CDELAY ,Transmit-end-to-chip-select-inactive-delay"
|
|
hexmask.long.byte 0x00 8.--15. 1. " T2EDELAY ,Transmit-data-finished to ENA-pin-inactive time-out"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--7. 1. " C2EDELAY ,Chip-select-active to ENA-signal-active time-out"
|
|
else
|
|
rgroup.long 0x48++0x03
|
|
line.long 0x00 "SPIDELAY,SPI Delay Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " C2TDELAY ,Chip-select-active to transmit-start delay"
|
|
hexmask.long.byte 0x00 16.--23. 1. " T2CDELAY ,Transmit-end-to-chip-select-inactive-delay"
|
|
hexmask.long.byte 0x00 8.--15. 1. " T2EDELAY ,Transmit-data-finished to ENA-pin-inactive time-out"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--7. 1. " C2EDELAY ,Chip-select-active to ENA-signal-active time-out"
|
|
endif
|
|
group.long 0x4C++0x13
|
|
line.long 0x00 "SPIDEF,SPI Default Chip Select Register"
|
|
bitfld.long 0x00 7. " CSDEF7 ,Chip select default pattern 7" "0,1"
|
|
bitfld.long 0x00 6. " CSDEF6 ,Chip select default pattern 6" "0,1"
|
|
bitfld.long 0x00 5. " CSDEF5 ,Chip select default pattern 5" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. " CSDEF4 ,Chip select default pattern 4" "0,1"
|
|
bitfld.long 0x00 3. " CSDEF3 ,Chip select default pattern 3" "0,1"
|
|
bitfld.long 0x00 2. " CSDEF2 ,Chip select default pattern 2" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. " CSDEF1 ,Chip select default pattern 1" "0,1"
|
|
bitfld.long 0x00 0. " CSDEF0 ,Chip select default pattern 0" "0,1"
|
|
line.long 0x4 "SPIFMT0,SPI Data Format Register 0"
|
|
sif (cpuis("TMS570LS0332")||cpuis("TMS570LS0432")||cpuis("TMS570LS1114*")||cpuis("TMS570LS1115*")||cpuis("TMS570LS1224*")||cpuis("TMS570LS1225*")||cpuis("TMS570LS1227*")||cpuis("TMS570LS0232")||cpuis("TMS570LS0714*")||cpuis("TMS570LS0914*"))
|
|
hexmask.long.byte 0x4 24.--31. 1. " WDELAY ,Delay in between transmissions for data format 0"
|
|
else
|
|
bitfld.long 0x4 24.--29. " WDELAY ,Delay in between transmissions for data format 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
endif
|
|
bitfld.long 0x4 23. " PARPOL ,Parity polarity: even or odd" "Even,Odd"
|
|
newline
|
|
bitfld.long 0x4 22. " PARITYENA ,Parity enable for data format 0" "Disabled,Enabled"
|
|
bitfld.long 0x4 21. " WAITENA ,The master waits for the ENA signal from slave for data format 0" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x4 20. " SHIFTDIR ,Shift direction for data format $" "MSB,LSB"
|
|
sif (cpu()==("TMS570LS0332")||cpu()==("TMS570LS0432")||cpuis("TMS570LS1114*")||cpuis("TMS570LS1115*")||cpuis("TMS570LS1224*")||cpuis("TMS570LS1225*")||cpuis("TMS570LS1227*")||cpuis("TMS570LS0232")||cpuis("TMS570LS0714*")||cpuis("TMS570LS0914*"))
|
|
bitfld.long 0x4 19. " HDUPLEX_ENA0 ,Half Duplex transfer mode enable for Data Format 0" "Normal,RX/TX"
|
|
endif
|
|
newline
|
|
bitfld.long 0x4 18. " DISCSTIMERS ,Disable chip-select timers for this format" "No,Yes"
|
|
newline
|
|
bitfld.long 0x4 17. " POLARITY ,SPI data format 0 clock polarity" "Low,High"
|
|
bitfld.long 0x4 16. " PHASE ,SPI data format 0 clock delay" "Disabled,Enabled"
|
|
newline
|
|
hexmask.long.byte 0x4 8.--15. 1. " PRESCALE ,SPI data format 0 prescaler"
|
|
bitfld.long 0x4 0.--4. " CHARLEN ,SPI data format 0 data-word length" ",,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,?..."
|
|
line.long 0x8 "SPIFMT1,SPI Data Format Register 1"
|
|
sif (cpuis("TMS570LS0332")||cpuis("TMS570LS0432")||cpuis("TMS570LS1114*")||cpuis("TMS570LS1115*")||cpuis("TMS570LS1224*")||cpuis("TMS570LS1225*")||cpuis("TMS570LS1227*")||cpuis("TMS570LS0232")||cpuis("TMS570LS0714*")||cpuis("TMS570LS0914*"))
|
|
hexmask.long.byte 0x8 24.--31. 1. " WDELAY ,Delay in between transmissions for data format 1"
|
|
else
|
|
bitfld.long 0x8 24.--29. " WDELAY ,Delay in between transmissions for data format 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
endif
|
|
bitfld.long 0x8 23. " PARPOL ,Parity polarity: even or odd" "Even,Odd"
|
|
newline
|
|
bitfld.long 0x8 22. " PARITYENA ,Parity enable for data format 1" "Disabled,Enabled"
|
|
bitfld.long 0x8 21. " WAITENA ,The master waits for the ENA signal from slave for data format 1" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x8 20. " SHIFTDIR ,Shift direction for data format $" "MSB,LSB"
|
|
sif (cpu()==("TMS570LS0332")||cpu()==("TMS570LS0432")||cpuis("TMS570LS1114*")||cpuis("TMS570LS1115*")||cpuis("TMS570LS1224*")||cpuis("TMS570LS1225*")||cpuis("TMS570LS1227*")||cpuis("TMS570LS0232")||cpuis("TMS570LS0714*")||cpuis("TMS570LS0914*"))
|
|
bitfld.long 0x8 19. " HDUPLEX_ENA1 ,Half Duplex transfer mode enable for Data Format 1" "Normal,RX/TX"
|
|
endif
|
|
newline
|
|
bitfld.long 0x8 18. " DISCSTIMERS ,Disable chip-select timers for this format" "No,Yes"
|
|
newline
|
|
bitfld.long 0x8 17. " POLARITY ,SPI data format 1 clock polarity" "Low,High"
|
|
bitfld.long 0x8 16. " PHASE ,SPI data format 1 clock delay" "Disabled,Enabled"
|
|
newline
|
|
hexmask.long.byte 0x8 8.--15. 1. " PRESCALE ,SPI data format 1 prescaler"
|
|
bitfld.long 0x8 0.--4. " CHARLEN ,SPI data format 1 data-word length" ",,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,?..."
|
|
line.long 0xC "SPIFMT2,SPI Data Format Register 2"
|
|
sif (cpuis("TMS570LS0332")||cpuis("TMS570LS0432")||cpuis("TMS570LS1114*")||cpuis("TMS570LS1115*")||cpuis("TMS570LS1224*")||cpuis("TMS570LS1225*")||cpuis("TMS570LS1227*")||cpuis("TMS570LS0232")||cpuis("TMS570LS0714*")||cpuis("TMS570LS0914*"))
|
|
hexmask.long.byte 0xC 24.--31. 1. " WDELAY ,Delay in between transmissions for data format 2"
|
|
else
|
|
bitfld.long 0xC 24.--29. " WDELAY ,Delay in between transmissions for data format 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
endif
|
|
bitfld.long 0xC 23. " PARPOL ,Parity polarity: even or odd" "Even,Odd"
|
|
newline
|
|
bitfld.long 0xC 22. " PARITYENA ,Parity enable for data format 2" "Disabled,Enabled"
|
|
bitfld.long 0xC 21. " WAITENA ,The master waits for the ENA signal from slave for data format 2" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0xC 20. " SHIFTDIR ,Shift direction for data format $" "MSB,LSB"
|
|
sif (cpu()==("TMS570LS0332")||cpu()==("TMS570LS0432")||cpuis("TMS570LS1114*")||cpuis("TMS570LS1115*")||cpuis("TMS570LS1224*")||cpuis("TMS570LS1225*")||cpuis("TMS570LS1227*")||cpuis("TMS570LS0232")||cpuis("TMS570LS0714*")||cpuis("TMS570LS0914*"))
|
|
bitfld.long 0xC 19. " HDUPLEX_ENA2 ,Half Duplex transfer mode enable for Data Format 2" "Normal,RX/TX"
|
|
endif
|
|
newline
|
|
bitfld.long 0xC 18. " DISCSTIMERS ,Disable chip-select timers for this format" "No,Yes"
|
|
newline
|
|
bitfld.long 0xC 17. " POLARITY ,SPI data format 2 clock polarity" "Low,High"
|
|
bitfld.long 0xC 16. " PHASE ,SPI data format 2 clock delay" "Disabled,Enabled"
|
|
newline
|
|
hexmask.long.byte 0xC 8.--15. 1. " PRESCALE ,SPI data format 2 prescaler"
|
|
bitfld.long 0xC 0.--4. " CHARLEN ,SPI data format 2 data-word length" ",,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,?..."
|
|
line.long 0x10 "SPIFMT3,SPI Data Format Register 3"
|
|
sif (cpuis("TMS570LS0332")||cpuis("TMS570LS0432")||cpuis("TMS570LS1114*")||cpuis("TMS570LS1115*")||cpuis("TMS570LS1224*")||cpuis("TMS570LS1225*")||cpuis("TMS570LS1227*")||cpuis("TMS570LS0232")||cpuis("TMS570LS0714*")||cpuis("TMS570LS0914*"))
|
|
hexmask.long.byte 0x10 24.--31. 1. " WDELAY ,Delay in between transmissions for data format 3"
|
|
else
|
|
bitfld.long 0x10 24.--29. " WDELAY ,Delay in between transmissions for data format 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
endif
|
|
bitfld.long 0x10 23. " PARPOL ,Parity polarity: even or odd" "Even,Odd"
|
|
newline
|
|
bitfld.long 0x10 22. " PARITYENA ,Parity enable for data format 3" "Disabled,Enabled"
|
|
bitfld.long 0x10 21. " WAITENA ,The master waits for the ENA signal from slave for data format 3" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x10 20. " SHIFTDIR ,Shift direction for data format $" "MSB,LSB"
|
|
sif (cpu()==("TMS570LS0332")||cpu()==("TMS570LS0432")||cpuis("TMS570LS1114*")||cpuis("TMS570LS1115*")||cpuis("TMS570LS1224*")||cpuis("TMS570LS1225*")||cpuis("TMS570LS1227*")||cpuis("TMS570LS0232")||cpuis("TMS570LS0714*")||cpuis("TMS570LS0914*"))
|
|
bitfld.long 0x10 19. " HDUPLEX_ENA3 ,Half Duplex transfer mode enable for Data Format 3" "Normal,RX/TX"
|
|
endif
|
|
newline
|
|
bitfld.long 0x10 18. " DISCSTIMERS ,Disable chip-select timers for this format" "No,Yes"
|
|
newline
|
|
bitfld.long 0x10 17. " POLARITY ,SPI data format 3 clock polarity" "Low,High"
|
|
bitfld.long 0x10 16. " PHASE ,SPI data format 3 clock delay" "Disabled,Enabled"
|
|
newline
|
|
hexmask.long.byte 0x10 8.--15. 1. " PRESCALE ,SPI data format 3 prescaler"
|
|
bitfld.long 0x10 0.--4. " CHARLEN ,SPI data format 3 data-word length" ",,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,?..."
|
|
hgroup.long 0x60++0x03
|
|
hide.long 0x00 "TGINTVECT0,SPI Interrupt Vector Register 0 / MibSPI Transfer Group Interrupt Vector Register 0"
|
|
in
|
|
hgroup.long 0x64++0x03
|
|
hide.long 0x00 "TGINTVECT1,SPI Interrupt Vector Register 1 / MibSPI Transfer Group Interrupt Vector Register 1"
|
|
in
|
|
sif (cpu()!=("TMS570LS0332")&&cpu()!=("TMS570LS0432")&&!cpuis("TMS570LS0232"))
|
|
group.long 0x6C++0x07
|
|
line.long 0x00 "SPIPMCTRL,SPI Parallel/Modulo Mode Control Register"
|
|
bitfld.long 0x00 29. " MODCLKPOL3 ,Modulo mode SPICLK polarity" "Normal,Inverted"
|
|
bitfld.long 0x00 26.--28. " MMODE3 ,SPI/MibSPI data lines " "1,2,3,4,5,6,?..."
|
|
bitfld.long 0x00 24.--25. " PMODE3 ,Parallel mode data lines" "1,2,4,8"
|
|
newline
|
|
bitfld.long 0x00 21. " MODCLKPOL2 ,Modulo mode SPICLK polarity" "Normal,Inverted"
|
|
bitfld.long 0x00 18.--20. " MMODE2 ,SPI/MibSPI data lines " "1,2,3,4,5,6,?..."
|
|
bitfld.long 0x00 16.--17. " PMODE2 ,Parallel mode data lines" "1,2,4,8"
|
|
newline
|
|
bitfld.long 0x00 13. " MODCLKPOL1 ,Modulo mode SPICLK polarity" "Normal,Inverted"
|
|
bitfld.long 0x00 10.--12. " MMODE1 ,SPI/MibSPI data lines " "1,2,3,4,5,6,?..."
|
|
bitfld.long 0x00 8.--9. " PMODE1 ,Parallel mode data lines" "1,2,4,8"
|
|
newline
|
|
bitfld.long 0x00 5. " MODCLKPOL0 ,Modulo mode SPICLK polarity" "Normal,Inverted"
|
|
bitfld.long 0x00 2.--4. " MMODE0 ,SPI/MibSPI data lines " "1,2,3,4,5,6,?..."
|
|
bitfld.long 0x00 0.--1. " PMODE0 ,Parallel mode data lines" "1,2,4,8"
|
|
line.long 0x04 "MIBSPIE,MibSPI Enable Register"
|
|
bitfld.long 0x04 16. " RXRAMACCESS ,Receive-RAM access control" "Not writable,Accessible"
|
|
bitfld.long 0x04 0. " MIBSPIENA ,Multi-buffer mode enable" "Disabled,Enabled"
|
|
elif cpuis("TMS570LS0332")||cpuis("TMS570LS0432")||cpuis("TMS570LS0714*")||cpuis("TMS570LS0914*")||cpuis("TMS570LS0232")
|
|
group.long 0x70++0x03
|
|
line.long 0x00 "MIBSPIE,MibSPI Enable Register"
|
|
bitfld.long 0x00 16. " RXRAMACCESS ,Receive-RAM access control" "Not writable,Accessible"
|
|
bitfld.long 0x00 0. " MIBSPIENA ,Multi-buffer mode enable" "Disabled,Enabled"
|
|
endif
|
|
group.long 0x74++0x0F
|
|
line.long 0x00 "TGITENST,MibSPI Transfer Group Interrupt Enable Set Register"
|
|
bitfld.long 0x00 31. " SETINTENRDY15 ,TG interrupt set (enable) when transfer finished" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " SETINTENRDY14 ,TG interrupt set (enable) when transfer finished" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " SETINTENRDY13 ,TG interrupt set (enable) when transfer finished" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 28. " SETINTENRDY12 ,TG interrupt set (enable) when transfer finished" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " SETINTENRDY11 ,TG interrupt set (enable) when transfer finished" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " SETINTENRDY10 ,TG interrupt set (enable) when transfer finished" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 25. " SETINTENRDY9 ,TG interrupt set (enable) when transfer finished" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " SETINTENRDY8 ,TG interrupt set (enable) when transfer finished" "Disabled,Enabled"
|
|
bitfld.long 0x00 23. " SETINTENRDY7 ,TG interrupt set (enable) when transfer finished" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 22. " SETINTENRDY6 ,TG interrupt set (enable) when transfer finished" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " SETINTENRDY5 ,TG interrupt set (enable) when transfer finished" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " SETINTENRDY4 ,SETTG interrupt set (enable) when transfer finished" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 19. " SETINTENRDY3 ,TG interrupt set (enable) when transfer finished" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SETINTENRDY2 ,TG interrupt set (enable) when transfer finished" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SETINTENRDY1 ,TG interrupt set (enable) when transfer finished" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 16. " SETINTENRDY0 ,TG interrupt set (enable) when transfer finished" "Disabled,Enabled"
|
|
bitfld.long 0x00 15. " SETINTENSUS15 ,TG interrupt set (enabled) when transfer suspended" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " SETINTENSUS14 ,TG interrupt set (enabled) when transfer suspended" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 13. " SETINTENSUS13 ,TG interrupt set (enabled) when transfer suspended" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " SETINTENSUS12 ,TG interrupt set (enabled) when transfer suspended" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " SETINTENSUS11 ,TG interrupt set (enabled) when transfer suspended" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 10. " SETINTENSUS10 ,TG interrupt set (enabled) when transfer suspended" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " SETINTENSUS9 ,TG interrupt set (enabled) when transfer suspended" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " SETINTENSUS8 ,TG interrupt set (enabled) when transfer suspended" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 7. " SETINTENSUS7 ,TG interrupt set (enabled) when transfer suspended" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " SETINTENSUS6 ,TG interrupt set (enabled) when transfer suspended" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " SETINTENSUS5 ,TG interrupt set (enabled) when transfer suspended" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 4. " SETINTENSUS4 ,TG interrupt set (enabled) when transfer suspended" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " SETINTENSUS3 ,TG interrupt set (enabled) when transfer suspended" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " SETINTENSUS2 ,TG interrupt set (enabled) when transfer suspended" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 1. " SETINTENSUS1 ,TG interrupt set (enabled) when transfer suspended" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SETINTENSUS0 ,TG interrupt set (enabled) when transfer suspended" "Disabled,Enabled"
|
|
line.long 0x04 "TGITENCR,MibSPI Transfer Group Interrupt Enable Clear Register"
|
|
bitfld.long 0x04 31. " CLRINTENRDY15 ,TG interrupt clear (disabled) when transfer finished" "Disabled,Enabled"
|
|
bitfld.long 0x04 30. " CLRINTENRDY14 ,TG interrupt clear (disabled) when transfer finished" "Disabled,Enabled"
|
|
bitfld.long 0x04 29. " CLRINTENRDY13 ,TG interrupt clear (disabled) when transfer finished" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x04 28. " CLRINTENRDY12 ,TG interrupt clear (disabled) when transfer finished" "Disabled,Enabled"
|
|
bitfld.long 0x04 27. " CLRINTENRDY11 ,TG interrupt clear (disabled) when transfer finished" "Disabled,Enabled"
|
|
bitfld.long 0x04 26. " CLRINTENRDY10 ,TG interrupt clear (disabled) when transfer finished" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x04 25. " CLRINTENRDY9 ,TG interrupt clear (disabled) when transfer finished" "Disabled,Enabled"
|
|
bitfld.long 0x04 24. " CLRINTENRDY8 ,TG interrupt clear (disabled) when transfer finished" "Disabled,Enabled"
|
|
bitfld.long 0x04 23. " CLRINTENRDY7 ,TG interrupt clear (disabled) when transfer finished" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x04 22. " CLRINTENRDY6 ,TG interrupt clear (disabled) when transfer finished" "Disabled,Enabled"
|
|
bitfld.long 0x04 21. " CLRINTENRDY5 ,TG interrupt clear (disabled) when transfer finished" "Disabled,Enabled"
|
|
bitfld.long 0x04 20. " CLRINTENRDY4 ,TG interrupt clear (disabled) when transfer finished" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x04 19. " CLRINTENRDY3 ,TG interrupt clear (disabled) when transfer finished" "Disabled,Enabled"
|
|
bitfld.long 0x04 18. " CLRINTENRDY2 ,TG interrupt clear (disabled) when transfer finished" "Disabled,Enabled"
|
|
bitfld.long 0x04 17. " CLRINTENRDY1 ,TG interrupt clear (disabled) when transfer finished" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x04 16. " CLRINTENRDY0 ,TG interrupt clear (disabled) when transfer finished" "Disabled,Enabled"
|
|
bitfld.long 0x04 15. " CLRINTENSUS15 ,TG interrupt clear (disabled) when transfer suspended" "Disabled,Enabled"
|
|
bitfld.long 0x04 14. " CLRINTENSUS14 ,TG interrupt clear (disabled) when transfer suspended" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x04 13. " CLRINTENSUS13 ,TG interrupt clear (disabled) when transfer suspended" "Disabled,Enabled"
|
|
bitfld.long 0x04 12. " CLRINTENSUS12 ,TG interrupt clear (disabled) when transfer suspended" "Disabled,Enabled"
|
|
bitfld.long 0x04 11. " CLRINTENSUS11 ,TG interrupt clear (disabled) when transfer suspended" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x04 10. " CLRINTENSUS10 ,TG interrupt clear (disabled) when transfer suspended" "Disabled,Enabled"
|
|
bitfld.long 0x04 9. " CLRINTENSUS9 ,TG interrupt clear (disabled) when transfer suspended" "Disabled,Enabled"
|
|
bitfld.long 0x04 8. " CLRINTENSUS8 ,TG interrupt clear (disabled) when transfer suspended" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x04 7. " CLRINTENSUS7 ,TG interrupt clear (disabled) when transfer suspended" "Disabled,Enabled"
|
|
bitfld.long 0x04 6. " CLRINTENSUS6 ,TG interrupt clear (disabled) when transfer suspended" "Disabled,Enabled"
|
|
bitfld.long 0x04 5. " CLRINTENSUS5 ,TG interrupt clear (disabled) when transfer suspended" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x04 4. " CLRINTENSUS4 ,TG interrupt clear (disabled) when transfer suspended" "Disabled,Enabled"
|
|
bitfld.long 0x04 3. " CLRINTENSUS3 ,TG interrupt clear (disabled) when transfer suspended" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " CLRINTENSUS2 ,TG interrupt clear (disabled) when transfer suspended" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x04 1. " CLRINTENSUS1 ,TG interrupt clear (disabled) when transfer suspended" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " CLRINTENSUS0 ,TG interrupt clear (disabled) when transfer suspended" "Disabled,Enabled"
|
|
line.long 0x08 "TGITLVST,MibSPI Transfer Group Interrupt Level Set Register"
|
|
bitfld.long 0x08 31. " SETINTLVLRDY15 ,Transfer-group completed interrupt level set" "INT0,INT1"
|
|
bitfld.long 0x08 30. " SETINTLVLRDY14 ,Transfer-group completed interrupt level set" "INT0,INT1"
|
|
bitfld.long 0x08 29. " SETINTLVLRDY13 ,Transfer-group completed interrupt level set" "INT0,INT1"
|
|
newline
|
|
bitfld.long 0x08 28. " SETINTLVLRDY12 ,Transfer-group completed interrupt level set" "INT0,INT1"
|
|
bitfld.long 0x08 27. " SETINTLVLRDY11 ,Transfer-group completed interrupt level set" "INT0,INT1"
|
|
bitfld.long 0x08 26. " SETINTLVLRDY10 ,Transfer-group completed interrupt level set" "INT0,INT1"
|
|
newline
|
|
bitfld.long 0x08 25. " SETINTLVLRDY9 ,Transfer-group completed interrupt level set" "INT0,INT1"
|
|
bitfld.long 0x08 24. " SETINTLVLRDY8 ,Transfer-group completed interrupt level set" "INT0,INT1"
|
|
bitfld.long 0x08 23. " SETINTLVLRDY7 ,Transfer-group completed interrupt level set" "INT0,INT1"
|
|
newline
|
|
bitfld.long 0x08 22. " SETINTLVLRDY6 ,Transfer-group completed interrupt level set" "INT0,INT1"
|
|
bitfld.long 0x08 21. " SETINTLVLRDY5 ,Transfer-group completed interrupt level set" "INT0,INT1"
|
|
bitfld.long 0x08 20. " SETINTLVLRDY4 ,Transfer-group completed interrupt level set" "INT0,INT1"
|
|
newline
|
|
bitfld.long 0x08 19. " SETINTLVLRDY3 ,Transfer-group completed interrupt level set" "INT0,INT1"
|
|
bitfld.long 0x08 18. " SETINTLVLRDY2 ,Transfer-group completed interrupt level set" "INT0,INT1"
|
|
bitfld.long 0x08 17. " SETINTLVLRDY1 ,Transfer-group completed interrupt level set" "INT0,INT1"
|
|
newline
|
|
bitfld.long 0x08 16. " SETINTLVLRDY0 ,Transfer-group completed interrupt level set" "INT0,INT1"
|
|
bitfld.long 0x08 15. " SETINTLVLSUS15 ,Transfer-group suspended interrupt level set" "INT0,INT1"
|
|
bitfld.long 0x08 14. " SETINTLVLSUS14 ,Transfer-group suspended interrupt level set" "INT0,INT1"
|
|
newline
|
|
bitfld.long 0x08 13. " SETINTLVLSUS13 ,Transfer-group suspended interrupt level set" "INT0,INT1"
|
|
bitfld.long 0x08 12. " SETINTLVLSUS12 ,Transfer-group suspended interrupt level set" "INT0,INT1"
|
|
bitfld.long 0x08 11. " SETINTLVLSUS11 ,Transfer-group suspended interrupt level set" "INT0,INT1"
|
|
newline
|
|
bitfld.long 0x08 10. " SETINTLVLSUS10 ,Transfer-group suspended interrupt level set" "INT0,INT1"
|
|
bitfld.long 0x08 9. " SETINTLVLSUS9 ,Transfer-group suspended interrupt level set" "INT0,INT1"
|
|
bitfld.long 0x08 8. " SETINTLVLSUS8 ,Transfer-group suspended interrupt level set" "INT0,INT1"
|
|
newline
|
|
bitfld.long 0x08 7. " SETINTLVLSUS7 ,Transfer-group suspended interrupt level set" "INT0,INT1"
|
|
bitfld.long 0x08 6. " SETINTLVLSUS6 ,Transfer-group suspended interrupt level set" "INT0,INT1"
|
|
bitfld.long 0x08 5. " SETINTLVLSUS5 ,Transfer-group suspended interrupt level set" "INT0,INT1"
|
|
newline
|
|
bitfld.long 0x08 4. " SETINTLVLSUS4 ,Transfer-group suspended interrupt level set" "INT0,INT1"
|
|
bitfld.long 0x08 3. " SETINTLVLSUS3 ,Transfer-group suspended interrupt level set" "INT0,INT1"
|
|
bitfld.long 0x08 2. " SETINTLVLSUS2 ,Transfer-group suspended interrupt level set" "INT0,INT1"
|
|
newline
|
|
bitfld.long 0x08 1. " SETINTLVLSUS1 ,Transfer-group suspended interrupt level set" "INT0,INT1"
|
|
bitfld.long 0x08 0. " SETINTLVLSUS0 ,Transfer-group suspended interrupt level set" "INT0,INT1"
|
|
line.long 0x0C "TGITLVCR,MibSPI Transfer Group Interrupt Level Clear Register"
|
|
bitfld.long 0x0C 31. " CLRINTLVLRDY15 ,Transfer-group completed interrupt level clear" "INT0,INT1"
|
|
bitfld.long 0x0C 30. " CLRINTLVLRDY14 ,Transfer-group completed interrupt level clear" "INT0,INT1"
|
|
bitfld.long 0x0C 29. " CLRINTLVLRDY13 ,Transfer-group completed interrupt level clear" "INT0,INT1"
|
|
newline
|
|
bitfld.long 0x0C 28. " CLRINTLVLRDY12 ,Transfer-group completed interrupt level clear" "INT0,INT1"
|
|
bitfld.long 0x0C 27. " CLRINTLVLRDY11 ,Transfer-group completed interrupt level clear" "INT0,INT1"
|
|
bitfld.long 0x0C 26. " CLRINTLVLRDY10 ,Transfer-group completed interrupt level clear" "INT0,INT1"
|
|
newline
|
|
bitfld.long 0x0C 25. " CLRINTLVLRDY9 ,Transfer-group completed interrupt level clear" "INT0,INT1"
|
|
bitfld.long 0x0C 24. " CLRINTLVLRDY8 ,Transfer-group completed interrupt level clear" "INT0,INT1"
|
|
bitfld.long 0x0C 23. " CLRINTLVLRDY7 ,Transfer-group completed interrupt level clear" "INT0,INT1"
|
|
newline
|
|
bitfld.long 0x0C 22. " CLRINTLVLRDY6 ,Transfer-group completed interrupt level clear" "INT0,INT1"
|
|
bitfld.long 0x0C 21. " CLRINTLVLRDY5 ,Transfer-group completed interrupt level clear" "INT0,INT1"
|
|
bitfld.long 0x0C 20. " CLRINTLVLRDY4 ,Transfer-group completed interrupt level clear" "INT0,INT1"
|
|
newline
|
|
bitfld.long 0x0C 19. " CLRINTLVLRDY3 ,Transfer-group completed interrupt level clear" "INT0,INT1"
|
|
bitfld.long 0x0C 18. " CLRINTLVLRDY2 ,Transfer-group completed interrupt level clear" "INT0,INT1"
|
|
bitfld.long 0x0C 17. " CLRINTLVLRDY1 ,Transfer-group completed interrupt level clear" "INT0,INT1"
|
|
newline
|
|
bitfld.long 0x0C 16. " CLRINTLVLRDY0 ,Transfer-group completed interrupt level clear" "INT0,INT1"
|
|
bitfld.long 0x0C 15. " CLRINTLVLSUS15 ,Transfer group suspended interrupt level clear" "INT0,INT1"
|
|
bitfld.long 0x0C 14. " CLRINTLVLSUS14 ,Transfer group suspended interrupt level clear" "INT0,INT1"
|
|
newline
|
|
bitfld.long 0x0C 13. " CLRINTLVLSUS13 ,Transfer group suspended interrupt level clear" "INT0,INT1"
|
|
bitfld.long 0x0C 12. " CLRINTLVLSUS12 ,Transfer group suspended interrupt level clear" "INT0,INT1"
|
|
bitfld.long 0x0C 11. " CLRINTLVLSUS11 ,Transfer group suspended interrupt level clear" "INT0,INT1"
|
|
newline
|
|
bitfld.long 0x0C 10. " CLRINTLVLSUS10 ,Transfer group suspended interrupt level clear" "INT0,INT1"
|
|
bitfld.long 0x0C 9. " CLRINTLVLSUS9 ,Transfer group suspended interrupt level clear" "INT0,INT1"
|
|
bitfld.long 0x0C 8. " CLRINTLVLSUS8 ,Transfer group suspended interrupt level clear" "INT0,INT1"
|
|
newline
|
|
bitfld.long 0x0C 7. " CLRINTLVLSUS7 ,Transfer group suspended interrupt level clear" "INT0,INT1"
|
|
bitfld.long 0x0C 6. " CLRINTLVLSUS6 ,Transfer group suspended interrupt level clear" "INT0,INT1"
|
|
bitfld.long 0x0C 5. " CLRINTLVLSUS5 ,Transfer group suspended interrupt level clear" "INT0,INT1"
|
|
newline
|
|
bitfld.long 0x0C 4. " CLRINTLVLSUS4 ,Transfer group suspended interrupt level clear" "INT0,INT1"
|
|
bitfld.long 0x0C 3. " CLRINTLVLSUS3 ,Transfer group suspended interrupt level clear" "INT0,INT1"
|
|
bitfld.long 0x0C 2. " CLRINTLVLSUS2 ,Transfer group suspended interrupt level clear" "INT0,INT1"
|
|
newline
|
|
bitfld.long 0x0C 1. " CLRINTLVLSUS1 ,Transfer group suspended interrupt level clear" "INT0,INT1"
|
|
bitfld.long 0x0C 0. " CLRINTLVLSUS0 ,Transfer group suspended interrupt level clear" "INT0,INT1"
|
|
group.long 0x84++0x03
|
|
line.long 0x00 "TGITFLG,Transfer Group Interrupt Flag Register"
|
|
sif (cpu()==("TMS570LS0332")||cpu()==("TMS570LS0432")||cpuis("TMS570LS1114*")||cpuis("TMS570LS1115*")||cpuis("TMS570LS1224*")||cpuis("TMS570LS1225*")||cpuis("TMS570LS1227*")||cpuis("TMS570LS0232")||cpuis("TMS570LS0714*")||cpuis("TMS570LS0914*"))
|
|
bitfld.long 0x00 31. " INTFLGRDY[15] ,Transfer-group interrupt flag for a transfer-completed interrupt 15" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " INTFLGRDY[14] ,Transfer-group interrupt flag for a transfer-completed interrupt 14" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 29. " INTFLGRDY[13] ,Transfer-group interrupt flag for a transfer-completed interrupt 13" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " INTFLGRDY[12] ,Transfer-group interrupt flag for a transfer-completed interrupt 12" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 27. " INTFLGRDY[11] ,Transfer-group interrupt flag for a transfer-completed interrupt 11" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " INTFLGRDY[10] ,Transfer-group interrupt flag for a transfer-completed interrupt 10" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 25. " INTFLGRDY[9] ,Transfer-group interrupt flag for a transfer-completed interrupt 9" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " INTFLGRDY[8] ,Transfer-group interrupt flag for a transfer-completed interrupt 8" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 23. " INTFLGRDY[7] ,Transfer-group interrupt flag for a transfer-completed interrupt 7" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " INTFLGRDY[6] ,Transfer-group interrupt flag for a transfer-completed interrupt 6" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 21. " INTFLGRDY[5] ,Transfer-group interrupt flag for a transfer-completed interrupt 5" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " INTFLGRDY[4] ,Transfer-group interrupt flag for a transfer-completed interrupt 4" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 19. " INTFLGRDY[3] ,Transfer-group interrupt flag for a transfer-completed interrupt 3" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " INTFLGRDY[2] ,Transfer-group interrupt flag for a transfer-completed interrupt 2" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 17. " INTFLGRDY[1] ,Transfer-group interrupt flag for a transfer-completed interrupt 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " INTFLGRDY[0] ,Transfer-group interrupt flag for a transfer-completed interrupt 0" "Disabled,Enabled"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 15. " INTFLGSUS[15] ,Transfer-group interrupt flag for a transfer-suspend interrupt 15" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " INTFLGSUS[14] ,Transfer-group interrupt flag for a transfer-suspend interrupt 14" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 13. " INTFLGSUS[13] ,Transfer-group interrupt flag for a transfer-suspend interrupt 13" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " INTFLGSUS[12] ,Transfer-group interrupt flag for a transfer-suspend interrupt 12" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 11. " INTFLGSUS[11] ,Transfer-group interrupt flag for a transfer-suspend interrupt 11" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " INTFLGSUS[10] ,Transfer-group interrupt flag for a transfer-suspend interrupt 10" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 9. " INTFLGSUS[9] ,Transfer-group interrupt flag for a transfer-suspend interrupt 9" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " INTFLGSUS[8] ,Transfer-group interrupt flag for a transfer-suspend interrupt 8" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 7. " INTFLGSUS[7] ,Transfer-group interrupt flag for a transfer-suspend interrupt 7" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " INTFLGSUS[6] ,Transfer-group interrupt flag for a transfer-suspend interrupt 6" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 5. " INTFLGSUS[5] ,Transfer-group interrupt flag for a transfer-suspend interrupt 5" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " INTFLGSUS[4] ,Transfer-group interrupt flag for a transfer-suspend interrupt 4" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 3. " INTFLGSUS[3] ,Transfer-group interrupt flag for a transfer-suspend interrupt 3" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " INTFLGSUS[2] ,Transfer-group interrupt flag for a transfer-suspend interrupt 2" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 1. " INTFLGSUS[1] ,Transfer-group interrupt flag for a transfer-suspend interrupt 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " INTFLGSUS[0] ,Transfer-group interrupt flag for a transfer-suspend interrupt 0" "Disabled,Enabled"
|
|
group.long 0x90++0x47
|
|
line.long 0x00 "TICKCNT,Tick Count Register"
|
|
bitfld.long 0x00 31. " TICKENA ,Tick counter enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " RELOAD ,Pre-load the tick counter" "No effect,Reload"
|
|
bitfld.long 0x00 28.--29. " CLKCTRL ,Tick counter clock source control" "0,1,2,3"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TICKVALUE ,Initial value for the tick counter"
|
|
line.long 0x04 "LTGPEND,Last Transfer Group End Pointer Register"
|
|
bitfld.long 0x04 24.--28. " TGINSERVICE ,The TG number currently being serviced by the sequencer" "No TG,TG0,TG1,TG2,TG3,TG4,TG5,TG6,TG7,TG8,TG9,TG10,TG11,TG12,TG13,TG14,TG15,?..."
|
|
hexmask.long.byte 0x04 8.--14. 1. " LPEND ,Last TG end pointer"
|
|
line.long 0x8 "TG0CTRL,MibSPI Transfer Group Control Register 0"
|
|
bitfld.long 0x8 31. " TGENA ,TG enable" "Disabled,Enabled"
|
|
bitfld.long 0x8 30. " ONESHOT ,Single transfer for TG" "Disabled,Enabled"
|
|
bitfld.long 0x8 29. " PRST ,TG pointer reset mode" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x8 28. " TGTD ,TG triggered" "Not triggered,Triggered"
|
|
bitfld.long 0x8 20.--23. " TRGEVT ,Type of trigger event" "Never,Rising edge,Falling edge,Both edges,,High active,Low-active,Always,?..."
|
|
sif cpuis("TMS570LS0232")||cpuis("TMS570LS0714*")||cpuis("TMS570LS0914*")
|
|
bitfld.long 0x8 16.--19. " TRIGSRC ,Trigger source" "Disabled,EXT0,EXT1,EXT2,EXT3,EXT4,EXT5,EXT6,EXT7,EXT8,EXT9,EXT10,EXT11,EXT12,EXT13,TICK"
|
|
else
|
|
bitfld.long 0x8 16.--19. " TRIGSRC ,Trigger source" "Disabled,GIOA[0],GIOA[1],GIOA[2],GIOA[3],GIOA[4],GIOA[5],GIOA[6],GIOA[7],N2HET1[8],N2HET1[10],N2HET1[12],N2HET1[14],N2HET1[16],N2HET1[18],TICK"
|
|
endif
|
|
newline
|
|
hexmask.long.byte 0x8 8.--14. 0x01 " PSTART ,TG start address"
|
|
hexmask.long.byte 0x8 0.--6. 0x01 " PCURRENT ,Pointer to current buffer"
|
|
line.long 0xC "TG1CTRL,MibSPI Transfer Group Control Register 1"
|
|
bitfld.long 0xC 31. " TGENA ,TG enable" "Disabled,Enabled"
|
|
bitfld.long 0xC 30. " ONESHOT ,Single transfer for TG" "Disabled,Enabled"
|
|
bitfld.long 0xC 29. " PRST ,TG pointer reset mode" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0xC 28. " TGTD ,TG triggered" "Not triggered,Triggered"
|
|
bitfld.long 0xC 20.--23. " TRGEVT ,Type of trigger event" "Never,Rising edge,Falling edge,Both edges,,High active,Low-active,Always,?..."
|
|
sif cpuis("TMS570LS0232")||cpuis("TMS570LS0714*")||cpuis("TMS570LS0914*")
|
|
bitfld.long 0xC 16.--19. " TRIGSRC ,Trigger source" "Disabled,EXT0,EXT1,EXT2,EXT3,EXT4,EXT5,EXT6,EXT7,EXT8,EXT9,EXT10,EXT11,EXT12,EXT13,TICK"
|
|
else
|
|
bitfld.long 0xC 16.--19. " TRIGSRC ,Trigger source" "Disabled,GIOA[0],GIOA[1],GIOA[2],GIOA[3],GIOA[4],GIOA[5],GIOA[6],GIOA[7],N2HET1[8],N2HET1[10],N2HET1[12],N2HET1[14],N2HET1[16],N2HET1[18],TICK"
|
|
endif
|
|
newline
|
|
hexmask.long.byte 0xC 8.--14. 0x01 " PSTART ,TG start address"
|
|
hexmask.long.byte 0xC 0.--6. 0x01 " PCURRENT ,Pointer to current buffer"
|
|
line.long 0x10 "TG2CTRL,MibSPI Transfer Group Control Register 2"
|
|
bitfld.long 0x10 31. " TGENA ,TG enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 30. " ONESHOT ,Single transfer for TG" "Disabled,Enabled"
|
|
bitfld.long 0x10 29. " PRST ,TG pointer reset mode" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x10 28. " TGTD ,TG triggered" "Not triggered,Triggered"
|
|
bitfld.long 0x10 20.--23. " TRGEVT ,Type of trigger event" "Never,Rising edge,Falling edge,Both edges,,High active,Low-active,Always,?..."
|
|
sif cpuis("TMS570LS0232")||cpuis("TMS570LS0714*")||cpuis("TMS570LS0914*")
|
|
bitfld.long 0x10 16.--19. " TRIGSRC ,Trigger source" "Disabled,EXT0,EXT1,EXT2,EXT3,EXT4,EXT5,EXT6,EXT7,EXT8,EXT9,EXT10,EXT11,EXT12,EXT13,TICK"
|
|
else
|
|
bitfld.long 0x10 16.--19. " TRIGSRC ,Trigger source" "Disabled,GIOA[0],GIOA[1],GIOA[2],GIOA[3],GIOA[4],GIOA[5],GIOA[6],GIOA[7],N2HET1[8],N2HET1[10],N2HET1[12],N2HET1[14],N2HET1[16],N2HET1[18],TICK"
|
|
endif
|
|
newline
|
|
hexmask.long.byte 0x10 8.--14. 0x01 " PSTART ,TG start address"
|
|
hexmask.long.byte 0x10 0.--6. 0x01 " PCURRENT ,Pointer to current buffer"
|
|
line.long 0x14 "TG3CTRL,MibSPI Transfer Group Control Register 3"
|
|
bitfld.long 0x14 31. " TGENA ,TG enable" "Disabled,Enabled"
|
|
bitfld.long 0x14 30. " ONESHOT ,Single transfer for TG" "Disabled,Enabled"
|
|
bitfld.long 0x14 29. " PRST ,TG pointer reset mode" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x14 28. " TGTD ,TG triggered" "Not triggered,Triggered"
|
|
bitfld.long 0x14 20.--23. " TRGEVT ,Type of trigger event" "Never,Rising edge,Falling edge,Both edges,,High active,Low-active,Always,?..."
|
|
sif cpuis("TMS570LS0232")||cpuis("TMS570LS0714*")||cpuis("TMS570LS0914*")
|
|
bitfld.long 0x14 16.--19. " TRIGSRC ,Trigger source" "Disabled,EXT0,EXT1,EXT2,EXT3,EXT4,EXT5,EXT6,EXT7,EXT8,EXT9,EXT10,EXT11,EXT12,EXT13,TICK"
|
|
else
|
|
bitfld.long 0x14 16.--19. " TRIGSRC ,Trigger source" "Disabled,GIOA[0],GIOA[1],GIOA[2],GIOA[3],GIOA[4],GIOA[5],GIOA[6],GIOA[7],N2HET1[8],N2HET1[10],N2HET1[12],N2HET1[14],N2HET1[16],N2HET1[18],TICK"
|
|
endif
|
|
newline
|
|
hexmask.long.byte 0x14 8.--14. 0x01 " PSTART ,TG start address"
|
|
hexmask.long.byte 0x14 0.--6. 0x01 " PCURRENT ,Pointer to current buffer"
|
|
line.long 0x18 "TG4CTRL,MibSPI Transfer Group Control Register 4"
|
|
bitfld.long 0x18 31. " TGENA ,TG enable" "Disabled,Enabled"
|
|
bitfld.long 0x18 30. " ONESHOT ,Single transfer for TG" "Disabled,Enabled"
|
|
bitfld.long 0x18 29. " PRST ,TG pointer reset mode" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x18 28. " TGTD ,TG triggered" "Not triggered,Triggered"
|
|
bitfld.long 0x18 20.--23. " TRGEVT ,Type of trigger event" "Never,Rising edge,Falling edge,Both edges,,High active,Low-active,Always,?..."
|
|
sif cpuis("TMS570LS0232")||cpuis("TMS570LS0714*")||cpuis("TMS570LS0914*")
|
|
bitfld.long 0x18 16.--19. " TRIGSRC ,Trigger source" "Disabled,EXT0,EXT1,EXT2,EXT3,EXT4,EXT5,EXT6,EXT7,EXT8,EXT9,EXT10,EXT11,EXT12,EXT13,TICK"
|
|
else
|
|
bitfld.long 0x18 16.--19. " TRIGSRC ,Trigger source" "Disabled,GIOA[0],GIOA[1],GIOA[2],GIOA[3],GIOA[4],GIOA[5],GIOA[6],GIOA[7],N2HET1[8],N2HET1[10],N2HET1[12],N2HET1[14],N2HET1[16],N2HET1[18],TICK"
|
|
endif
|
|
newline
|
|
hexmask.long.byte 0x18 8.--14. 0x01 " PSTART ,TG start address"
|
|
hexmask.long.byte 0x18 0.--6. 0x01 " PCURRENT ,Pointer to current buffer"
|
|
line.long 0x1C "TG5CTRL,MibSPI Transfer Group Control Register 5"
|
|
bitfld.long 0x1C 31. " TGENA ,TG enable" "Disabled,Enabled"
|
|
bitfld.long 0x1C 30. " ONESHOT ,Single transfer for TG" "Disabled,Enabled"
|
|
bitfld.long 0x1C 29. " PRST ,TG pointer reset mode" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x1C 28. " TGTD ,TG triggered" "Not triggered,Triggered"
|
|
bitfld.long 0x1C 20.--23. " TRGEVT ,Type of trigger event" "Never,Rising edge,Falling edge,Both edges,,High active,Low-active,Always,?..."
|
|
sif cpuis("TMS570LS0232")||cpuis("TMS570LS0714*")||cpuis("TMS570LS0914*")
|
|
bitfld.long 0x1C 16.--19. " TRIGSRC ,Trigger source" "Disabled,EXT0,EXT1,EXT2,EXT3,EXT4,EXT5,EXT6,EXT7,EXT8,EXT9,EXT10,EXT11,EXT12,EXT13,TICK"
|
|
else
|
|
bitfld.long 0x1C 16.--19. " TRIGSRC ,Trigger source" "Disabled,GIOA[0],GIOA[1],GIOA[2],GIOA[3],GIOA[4],GIOA[5],GIOA[6],GIOA[7],N2HET1[8],N2HET1[10],N2HET1[12],N2HET1[14],N2HET1[16],N2HET1[18],TICK"
|
|
endif
|
|
newline
|
|
hexmask.long.byte 0x1C 8.--14. 0x01 " PSTART ,TG start address"
|
|
hexmask.long.byte 0x1C 0.--6. 0x01 " PCURRENT ,Pointer to current buffer"
|
|
line.long 0x20 "TG6CTRL,MibSPI Transfer Group Control Register 6"
|
|
bitfld.long 0x20 31. " TGENA ,TG enable" "Disabled,Enabled"
|
|
bitfld.long 0x20 30. " ONESHOT ,Single transfer for TG" "Disabled,Enabled"
|
|
bitfld.long 0x20 29. " PRST ,TG pointer reset mode" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x20 28. " TGTD ,TG triggered" "Not triggered,Triggered"
|
|
bitfld.long 0x20 20.--23. " TRGEVT ,Type of trigger event" "Never,Rising edge,Falling edge,Both edges,,High active,Low-active,Always,?..."
|
|
sif cpuis("TMS570LS0232")||cpuis("TMS570LS0714*")||cpuis("TMS570LS0914*")
|
|
bitfld.long 0x20 16.--19. " TRIGSRC ,Trigger source" "Disabled,EXT0,EXT1,EXT2,EXT3,EXT4,EXT5,EXT6,EXT7,EXT8,EXT9,EXT10,EXT11,EXT12,EXT13,TICK"
|
|
else
|
|
bitfld.long 0x20 16.--19. " TRIGSRC ,Trigger source" "Disabled,GIOA[0],GIOA[1],GIOA[2],GIOA[3],GIOA[4],GIOA[5],GIOA[6],GIOA[7],N2HET1[8],N2HET1[10],N2HET1[12],N2HET1[14],N2HET1[16],N2HET1[18],TICK"
|
|
endif
|
|
newline
|
|
hexmask.long.byte 0x20 8.--14. 0x01 " PSTART ,TG start address"
|
|
hexmask.long.byte 0x20 0.--6. 0x01 " PCURRENT ,Pointer to current buffer"
|
|
line.long 0x24 "TG7CTRL,MibSPI Transfer Group Control Register 7"
|
|
bitfld.long 0x24 31. " TGENA ,TG enable" "Disabled,Enabled"
|
|
bitfld.long 0x24 30. " ONESHOT ,Single transfer for TG" "Disabled,Enabled"
|
|
bitfld.long 0x24 29. " PRST ,TG pointer reset mode" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x24 28. " TGTD ,TG triggered" "Not triggered,Triggered"
|
|
bitfld.long 0x24 20.--23. " TRGEVT ,Type of trigger event" "Never,Rising edge,Falling edge,Both edges,,High active,Low-active,Always,?..."
|
|
sif cpuis("TMS570LS0232")||cpuis("TMS570LS0714*")||cpuis("TMS570LS0914*")
|
|
bitfld.long 0x24 16.--19. " TRIGSRC ,Trigger source" "Disabled,EXT0,EXT1,EXT2,EXT3,EXT4,EXT5,EXT6,EXT7,EXT8,EXT9,EXT10,EXT11,EXT12,EXT13,TICK"
|
|
else
|
|
bitfld.long 0x24 16.--19. " TRIGSRC ,Trigger source" "Disabled,GIOA[0],GIOA[1],GIOA[2],GIOA[3],GIOA[4],GIOA[5],GIOA[6],GIOA[7],N2HET1[8],N2HET1[10],N2HET1[12],N2HET1[14],N2HET1[16],N2HET1[18],TICK"
|
|
endif
|
|
newline
|
|
hexmask.long.byte 0x24 8.--14. 0x01 " PSTART ,TG start address"
|
|
hexmask.long.byte 0x24 0.--6. 0x01 " PCURRENT ,Pointer to current buffer"
|
|
line.long 0x28 "TG8CTRL,MibSPI Transfer Group Control Register 8"
|
|
bitfld.long 0x28 31. " TGENA ,TG enable" "Disabled,Enabled"
|
|
bitfld.long 0x28 30. " ONESHOT ,Single transfer for TG" "Disabled,Enabled"
|
|
bitfld.long 0x28 29. " PRST ,TG pointer reset mode" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x28 28. " TGTD ,TG triggered" "Not triggered,Triggered"
|
|
bitfld.long 0x28 20.--23. " TRGEVT ,Type of trigger event" "Never,Rising edge,Falling edge,Both edges,,High active,Low-active,Always,?..."
|
|
sif cpuis("TMS570LS0232")||cpuis("TMS570LS0714*")||cpuis("TMS570LS0914*")
|
|
bitfld.long 0x28 16.--19. " TRIGSRC ,Trigger source" "Disabled,EXT0,EXT1,EXT2,EXT3,EXT4,EXT5,EXT6,EXT7,EXT8,EXT9,EXT10,EXT11,EXT12,EXT13,TICK"
|
|
else
|
|
bitfld.long 0x28 16.--19. " TRIGSRC ,Trigger source" "Disabled,GIOA[0],GIOA[1],GIOA[2],GIOA[3],GIOA[4],GIOA[5],GIOA[6],GIOA[7],N2HET1[8],N2HET1[10],N2HET1[12],N2HET1[14],N2HET1[16],N2HET1[18],TICK"
|
|
endif
|
|
newline
|
|
hexmask.long.byte 0x28 8.--14. 0x01 " PSTART ,TG start address"
|
|
hexmask.long.byte 0x28 0.--6. 0x01 " PCURRENT ,Pointer to current buffer"
|
|
line.long 0x2C "TG9CTRL,MibSPI Transfer Group Control Register 9"
|
|
bitfld.long 0x2C 31. " TGENA ,TG enable" "Disabled,Enabled"
|
|
bitfld.long 0x2C 30. " ONESHOT ,Single transfer for TG" "Disabled,Enabled"
|
|
bitfld.long 0x2C 29. " PRST ,TG pointer reset mode" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x2C 28. " TGTD ,TG triggered" "Not triggered,Triggered"
|
|
bitfld.long 0x2C 20.--23. " TRGEVT ,Type of trigger event" "Never,Rising edge,Falling edge,Both edges,,High active,Low-active,Always,?..."
|
|
sif cpuis("TMS570LS0232")||cpuis("TMS570LS0714*")||cpuis("TMS570LS0914*")
|
|
bitfld.long 0x2C 16.--19. " TRIGSRC ,Trigger source" "Disabled,EXT0,EXT1,EXT2,EXT3,EXT4,EXT5,EXT6,EXT7,EXT8,EXT9,EXT10,EXT11,EXT12,EXT13,TICK"
|
|
else
|
|
bitfld.long 0x2C 16.--19. " TRIGSRC ,Trigger source" "Disabled,GIOA[0],GIOA[1],GIOA[2],GIOA[3],GIOA[4],GIOA[5],GIOA[6],GIOA[7],N2HET1[8],N2HET1[10],N2HET1[12],N2HET1[14],N2HET1[16],N2HET1[18],TICK"
|
|
endif
|
|
newline
|
|
hexmask.long.byte 0x2C 8.--14. 0x01 " PSTART ,TG start address"
|
|
hexmask.long.byte 0x2C 0.--6. 0x01 " PCURRENT ,Pointer to current buffer"
|
|
line.long 0x30 "TG10CTRL,MibSPI Transfer Group Control Register 10"
|
|
bitfld.long 0x30 31. " TGENA ,TG enable" "Disabled,Enabled"
|
|
bitfld.long 0x30 30. " ONESHOT ,Single transfer for TG" "Disabled,Enabled"
|
|
bitfld.long 0x30 29. " PRST ,TG pointer reset mode" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x30 28. " TGTD ,TG triggered" "Not triggered,Triggered"
|
|
bitfld.long 0x30 20.--23. " TRGEVT ,Type of trigger event" "Never,Rising edge,Falling edge,Both edges,,High active,Low-active,Always,?..."
|
|
sif cpuis("TMS570LS0232")||cpuis("TMS570LS0714*")||cpuis("TMS570LS0914*")
|
|
bitfld.long 0x30 16.--19. " TRIGSRC ,Trigger source" "Disabled,EXT0,EXT1,EXT2,EXT3,EXT4,EXT5,EXT6,EXT7,EXT8,EXT9,EXT10,EXT11,EXT12,EXT13,TICK"
|
|
else
|
|
bitfld.long 0x30 16.--19. " TRIGSRC ,Trigger source" "Disabled,GIOA[0],GIOA[1],GIOA[2],GIOA[3],GIOA[4],GIOA[5],GIOA[6],GIOA[7],N2HET1[8],N2HET1[10],N2HET1[12],N2HET1[14],N2HET1[16],N2HET1[18],TICK"
|
|
endif
|
|
newline
|
|
hexmask.long.byte 0x30 8.--14. 0x01 " PSTART ,TG start address"
|
|
hexmask.long.byte 0x30 0.--6. 0x01 " PCURRENT ,Pointer to current buffer"
|
|
line.long 0x34 "TG11CTRL,MibSPI Transfer Group Control Register 11"
|
|
bitfld.long 0x34 31. " TGENA ,TG enable" "Disabled,Enabled"
|
|
bitfld.long 0x34 30. " ONESHOT ,Single transfer for TG" "Disabled,Enabled"
|
|
bitfld.long 0x34 29. " PRST ,TG pointer reset mode" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x34 28. " TGTD ,TG triggered" "Not triggered,Triggered"
|
|
bitfld.long 0x34 20.--23. " TRGEVT ,Type of trigger event" "Never,Rising edge,Falling edge,Both edges,,High active,Low-active,Always,?..."
|
|
sif cpuis("TMS570LS0232")||cpuis("TMS570LS0714*")||cpuis("TMS570LS0914*")
|
|
bitfld.long 0x34 16.--19. " TRIGSRC ,Trigger source" "Disabled,EXT0,EXT1,EXT2,EXT3,EXT4,EXT5,EXT6,EXT7,EXT8,EXT9,EXT10,EXT11,EXT12,EXT13,TICK"
|
|
else
|
|
bitfld.long 0x34 16.--19. " TRIGSRC ,Trigger source" "Disabled,GIOA[0],GIOA[1],GIOA[2],GIOA[3],GIOA[4],GIOA[5],GIOA[6],GIOA[7],N2HET1[8],N2HET1[10],N2HET1[12],N2HET1[14],N2HET1[16],N2HET1[18],TICK"
|
|
endif
|
|
newline
|
|
hexmask.long.byte 0x34 8.--14. 0x01 " PSTART ,TG start address"
|
|
hexmask.long.byte 0x34 0.--6. 0x01 " PCURRENT ,Pointer to current buffer"
|
|
line.long 0x38 "TG12CTRL,MibSPI Transfer Group Control Register 12"
|
|
bitfld.long 0x38 31. " TGENA ,TG enable" "Disabled,Enabled"
|
|
bitfld.long 0x38 30. " ONESHOT ,Single transfer for TG" "Disabled,Enabled"
|
|
bitfld.long 0x38 29. " PRST ,TG pointer reset mode" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x38 28. " TGTD ,TG triggered" "Not triggered,Triggered"
|
|
bitfld.long 0x38 20.--23. " TRGEVT ,Type of trigger event" "Never,Rising edge,Falling edge,Both edges,,High active,Low-active,Always,?..."
|
|
sif cpuis("TMS570LS0232")||cpuis("TMS570LS0714*")||cpuis("TMS570LS0914*")
|
|
bitfld.long 0x38 16.--19. " TRIGSRC ,Trigger source" "Disabled,EXT0,EXT1,EXT2,EXT3,EXT4,EXT5,EXT6,EXT7,EXT8,EXT9,EXT10,EXT11,EXT12,EXT13,TICK"
|
|
else
|
|
bitfld.long 0x38 16.--19. " TRIGSRC ,Trigger source" "Disabled,GIOA[0],GIOA[1],GIOA[2],GIOA[3],GIOA[4],GIOA[5],GIOA[6],GIOA[7],N2HET1[8],N2HET1[10],N2HET1[12],N2HET1[14],N2HET1[16],N2HET1[18],TICK"
|
|
endif
|
|
newline
|
|
hexmask.long.byte 0x38 8.--14. 0x01 " PSTART ,TG start address"
|
|
hexmask.long.byte 0x38 0.--6. 0x01 " PCURRENT ,Pointer to current buffer"
|
|
line.long 0x3C "TG13CTRL,MibSPI Transfer Group Control Register 13"
|
|
bitfld.long 0x3C 31. " TGENA ,TG enable" "Disabled,Enabled"
|
|
bitfld.long 0x3C 30. " ONESHOT ,Single transfer for TG" "Disabled,Enabled"
|
|
bitfld.long 0x3C 29. " PRST ,TG pointer reset mode" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x3C 28. " TGTD ,TG triggered" "Not triggered,Triggered"
|
|
bitfld.long 0x3C 20.--23. " TRGEVT ,Type of trigger event" "Never,Rising edge,Falling edge,Both edges,,High active,Low-active,Always,?..."
|
|
sif cpuis("TMS570LS0232")||cpuis("TMS570LS0714*")||cpuis("TMS570LS0914*")
|
|
bitfld.long 0x3C 16.--19. " TRIGSRC ,Trigger source" "Disabled,EXT0,EXT1,EXT2,EXT3,EXT4,EXT5,EXT6,EXT7,EXT8,EXT9,EXT10,EXT11,EXT12,EXT13,TICK"
|
|
else
|
|
bitfld.long 0x3C 16.--19. " TRIGSRC ,Trigger source" "Disabled,GIOA[0],GIOA[1],GIOA[2],GIOA[3],GIOA[4],GIOA[5],GIOA[6],GIOA[7],N2HET1[8],N2HET1[10],N2HET1[12],N2HET1[14],N2HET1[16],N2HET1[18],TICK"
|
|
endif
|
|
newline
|
|
hexmask.long.byte 0x3C 8.--14. 0x01 " PSTART ,TG start address"
|
|
hexmask.long.byte 0x3C 0.--6. 0x01 " PCURRENT ,Pointer to current buffer"
|
|
line.long 0x40 "TG14CTRL,MibSPI Transfer Group Control Register 14"
|
|
bitfld.long 0x40 31. " TGENA ,TG enable" "Disabled,Enabled"
|
|
bitfld.long 0x40 30. " ONESHOT ,Single transfer for TG" "Disabled,Enabled"
|
|
bitfld.long 0x40 29. " PRST ,TG pointer reset mode" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x40 28. " TGTD ,TG triggered" "Not triggered,Triggered"
|
|
bitfld.long 0x40 20.--23. " TRGEVT ,Type of trigger event" "Never,Rising edge,Falling edge,Both edges,,High active,Low-active,Always,?..."
|
|
sif cpuis("TMS570LS0232")||cpuis("TMS570LS0714*")||cpuis("TMS570LS0914*")
|
|
bitfld.long 0x40 16.--19. " TRIGSRC ,Trigger source" "Disabled,EXT0,EXT1,EXT2,EXT3,EXT4,EXT5,EXT6,EXT7,EXT8,EXT9,EXT10,EXT11,EXT12,EXT13,TICK"
|
|
else
|
|
bitfld.long 0x40 16.--19. " TRIGSRC ,Trigger source" "Disabled,GIOA[0],GIOA[1],GIOA[2],GIOA[3],GIOA[4],GIOA[5],GIOA[6],GIOA[7],N2HET1[8],N2HET1[10],N2HET1[12],N2HET1[14],N2HET1[16],N2HET1[18],TICK"
|
|
endif
|
|
newline
|
|
hexmask.long.byte 0x40 8.--14. 0x01 " PSTART ,TG start address"
|
|
hexmask.long.byte 0x40 0.--6. 0x01 " PCURRENT ,Pointer to current buffer"
|
|
line.long 0x44 "TG15CTRL,MibSPI Transfer Group Control Register 15"
|
|
bitfld.long 0x44 31. " TGENA ,TG enable" "Disabled,Enabled"
|
|
bitfld.long 0x44 30. " ONESHOT ,Single transfer for TG" "Disabled,Enabled"
|
|
bitfld.long 0x44 29. " PRST ,TG pointer reset mode" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x44 28. " TGTD ,TG triggered" "Not triggered,Triggered"
|
|
bitfld.long 0x44 20.--23. " TRGEVT ,Type of trigger event" "Never,Rising edge,Falling edge,Both edges,,High active,Low-active,Always,?..."
|
|
sif cpuis("TMS570LS0232")||cpuis("TMS570LS0714*")||cpuis("TMS570LS0914*")
|
|
bitfld.long 0x44 16.--19. " TRIGSRC ,Trigger source" "Disabled,EXT0,EXT1,EXT2,EXT3,EXT4,EXT5,EXT6,EXT7,EXT8,EXT9,EXT10,EXT11,EXT12,EXT13,TICK"
|
|
else
|
|
bitfld.long 0x44 16.--19. " TRIGSRC ,Trigger source" "Disabled,GIOA[0],GIOA[1],GIOA[2],GIOA[3],GIOA[4],GIOA[5],GIOA[6],GIOA[7],N2HET1[8],N2HET1[10],N2HET1[12],N2HET1[14],N2HET1[16],N2HET1[18],TICK"
|
|
endif
|
|
newline
|
|
hexmask.long.byte 0x44 8.--14. 0x01 " PSTART ,TG start address"
|
|
hexmask.long.byte 0x44 0.--6. 0x01 " PCURRENT ,Pointer to current buffer"
|
|
sif (cpu()!=("TMS570LS0332")&&cpu()!=("TMS570LS0432")&&!cpuis("TMS570LS0232"))
|
|
group.long 0xD8++0x1F
|
|
line.long 0x0 "DMA0CTRL,MibSPI DMA Channel Control Register 1"
|
|
bitfld.long 0x0 31. " ONESHOT ,Auto-disable of DMA channel after ICOUNT+1 transfers" "0,1"
|
|
hexmask.long.byte 0x0 24.--30. 1. " BUFID ,Buffer utilized for DMA transfer"
|
|
bitfld.long 0x0 20.--23. " RXDMA_MAP ,Each MibSPI DMA channel can be linked to two physical DMA" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x0 16.--19. " TXDMA_MAP ,Each MibSPI DMA channel can be linked to two physical DMA" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x0 15. " RXDMAENA ,Receive data DMA channel enable" "Disabled,Enabled"
|
|
bitfld.long 0x0 14. " TXDMAENA ,Transmit data DMA channel enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x0 13. " NOBRK ,Non-interleaved DMA block transfer" "Not performed,Performed"
|
|
bitfld.long 0x0 8.--12. " ICOUNT ,Initial count of DMA transfers" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32"
|
|
bitfld.long 0x0 6. " COUNTBIT17 ,17th bit of the COUNT field of DMAxCOUNT register" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0.--5. " COUNT ,Actual number of remaining DMA transfers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
line.long 0x4 "DMA1CTRL,MibSPI DMA Channel Control Register 1"
|
|
bitfld.long 0x4 31. " ONESHOT ,Auto-disable of DMA channel after ICOUNT+1 transfers" "0,1"
|
|
hexmask.long.byte 0x4 24.--30. 1. " BUFID ,Buffer utilized for DMA transfer"
|
|
bitfld.long 0x4 20.--23. " RXDMA_MAP ,Each MibSPI DMA channel can be linked to two physical DMA" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x4 16.--19. " TXDMA_MAP ,Each MibSPI DMA channel can be linked to two physical DMA" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x4 15. " RXDMAENA ,Receive data DMA channel enable" "Disabled,Enabled"
|
|
bitfld.long 0x4 14. " TXDMAENA ,Transmit data DMA channel enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x4 13. " NOBRK ,Non-interleaved DMA block transfer" "Not performed,Performed"
|
|
bitfld.long 0x4 8.--12. " ICOUNT ,Initial count of DMA transfers" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32"
|
|
bitfld.long 0x4 6. " COUNTBIT17 ,17th bit of the COUNT field of DMAxCOUNT register" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0.--5. " COUNT ,Actual number of remaining DMA transfers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
line.long 0x8 "DMA2CTRL,MibSPI DMA Channel Control Register 1"
|
|
bitfld.long 0x8 31. " ONESHOT ,Auto-disable of DMA channel after ICOUNT+1 transfers" "0,1"
|
|
hexmask.long.byte 0x8 24.--30. 1. " BUFID ,Buffer utilized for DMA transfer"
|
|
bitfld.long 0x8 20.--23. " RXDMA_MAP ,Each MibSPI DMA channel can be linked to two physical DMA" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x8 16.--19. " TXDMA_MAP ,Each MibSPI DMA channel can be linked to two physical DMA" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x8 15. " RXDMAENA ,Receive data DMA channel enable" "Disabled,Enabled"
|
|
bitfld.long 0x8 14. " TXDMAENA ,Transmit data DMA channel enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x8 13. " NOBRK ,Non-interleaved DMA block transfer" "Not performed,Performed"
|
|
bitfld.long 0x8 8.--12. " ICOUNT ,Initial count of DMA transfers" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32"
|
|
bitfld.long 0x8 6. " COUNTBIT17 ,17th bit of the COUNT field of DMAxCOUNT register" "0,1"
|
|
newline
|
|
bitfld.long 0x8 0.--5. " COUNT ,Actual number of remaining DMA transfers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
line.long 0xC "DMA3CTRL,MibSPI DMA Channel Control Register 1"
|
|
bitfld.long 0xC 31. " ONESHOT ,Auto-disable of DMA channel after ICOUNT+1 transfers" "0,1"
|
|
hexmask.long.byte 0xC 24.--30. 1. " BUFID ,Buffer utilized for DMA transfer"
|
|
bitfld.long 0xC 20.--23. " RXDMA_MAP ,Each MibSPI DMA channel can be linked to two physical DMA" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0xC 16.--19. " TXDMA_MAP ,Each MibSPI DMA channel can be linked to two physical DMA" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0xC 15. " RXDMAENA ,Receive data DMA channel enable" "Disabled,Enabled"
|
|
bitfld.long 0xC 14. " TXDMAENA ,Transmit data DMA channel enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0xC 13. " NOBRK ,Non-interleaved DMA block transfer" "Not performed,Performed"
|
|
bitfld.long 0xC 8.--12. " ICOUNT ,Initial count of DMA transfers" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32"
|
|
bitfld.long 0xC 6. " COUNTBIT17 ,17th bit of the COUNT field of DMAxCOUNT register" "0,1"
|
|
newline
|
|
bitfld.long 0xC 0.--5. " COUNT ,Actual number of remaining DMA transfers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
line.long 0x10 "DMA4CTRL,MibSPI DMA Channel Control Register 1"
|
|
bitfld.long 0x10 31. " ONESHOT ,Auto-disable of DMA channel after ICOUNT+1 transfers" "0,1"
|
|
hexmask.long.byte 0x10 24.--30. 1. " BUFID ,Buffer utilized for DMA transfer"
|
|
bitfld.long 0x10 20.--23. " RXDMA_MAP ,Each MibSPI DMA channel can be linked to two physical DMA" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x10 16.--19. " TXDMA_MAP ,Each MibSPI DMA channel can be linked to two physical DMA" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x10 15. " RXDMAENA ,Receive data DMA channel enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 14. " TXDMAENA ,Transmit data DMA channel enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x10 13. " NOBRK ,Non-interleaved DMA block transfer" "Not performed,Performed"
|
|
bitfld.long 0x10 8.--12. " ICOUNT ,Initial count of DMA transfers" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32"
|
|
bitfld.long 0x10 6. " COUNTBIT17 ,17th bit of the COUNT field of DMAxCOUNT register" "0,1"
|
|
newline
|
|
bitfld.long 0x10 0.--5. " COUNT ,Actual number of remaining DMA transfers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
line.long 0x14 "DMA5CTRL,MibSPI DMA Channel Control Register 1"
|
|
bitfld.long 0x14 31. " ONESHOT ,Auto-disable of DMA channel after ICOUNT+1 transfers" "0,1"
|
|
hexmask.long.byte 0x14 24.--30. 1. " BUFID ,Buffer utilized for DMA transfer"
|
|
bitfld.long 0x14 20.--23. " RXDMA_MAP ,Each MibSPI DMA channel can be linked to two physical DMA" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x14 16.--19. " TXDMA_MAP ,Each MibSPI DMA channel can be linked to two physical DMA" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x14 15. " RXDMAENA ,Receive data DMA channel enable" "Disabled,Enabled"
|
|
bitfld.long 0x14 14. " TXDMAENA ,Transmit data DMA channel enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x14 13. " NOBRK ,Non-interleaved DMA block transfer" "Not performed,Performed"
|
|
bitfld.long 0x14 8.--12. " ICOUNT ,Initial count of DMA transfers" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32"
|
|
bitfld.long 0x14 6. " COUNTBIT17 ,17th bit of the COUNT field of DMAxCOUNT register" "0,1"
|
|
newline
|
|
bitfld.long 0x14 0.--5. " COUNT ,Actual number of remaining DMA transfers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
line.long 0x18 "DMA6CTRL,MibSPI DMA Channel Control Register 1"
|
|
bitfld.long 0x18 31. " ONESHOT ,Auto-disable of DMA channel after ICOUNT+1 transfers" "0,1"
|
|
hexmask.long.byte 0x18 24.--30. 1. " BUFID ,Buffer utilized for DMA transfer"
|
|
bitfld.long 0x18 20.--23. " RXDMA_MAP ,Each MibSPI DMA channel can be linked to two physical DMA" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x18 16.--19. " TXDMA_MAP ,Each MibSPI DMA channel can be linked to two physical DMA" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x18 15. " RXDMAENA ,Receive data DMA channel enable" "Disabled,Enabled"
|
|
bitfld.long 0x18 14. " TXDMAENA ,Transmit data DMA channel enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x18 13. " NOBRK ,Non-interleaved DMA block transfer" "Not performed,Performed"
|
|
bitfld.long 0x18 8.--12. " ICOUNT ,Initial count of DMA transfers" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32"
|
|
bitfld.long 0x18 6. " COUNTBIT17 ,17th bit of the COUNT field of DMAxCOUNT register" "0,1"
|
|
newline
|
|
bitfld.long 0x18 0.--5. " COUNT ,Actual number of remaining DMA transfers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
line.long 0x1C "DMA7CTRL,MibSPI DMA Channel Control Register 1"
|
|
bitfld.long 0x1C 31. " ONESHOT ,Auto-disable of DMA channel after ICOUNT+1 transfers" "0,1"
|
|
hexmask.long.byte 0x1C 24.--30. 1. " BUFID ,Buffer utilized for DMA transfer"
|
|
bitfld.long 0x1C 20.--23. " RXDMA_MAP ,Each MibSPI DMA channel can be linked to two physical DMA" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x1C 16.--19. " TXDMA_MAP ,Each MibSPI DMA channel can be linked to two physical DMA" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x1C 15. " RXDMAENA ,Receive data DMA channel enable" "Disabled,Enabled"
|
|
bitfld.long 0x1C 14. " TXDMAENA ,Transmit data DMA channel enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x1C 13. " NOBRK ,Non-interleaved DMA block transfer" "Not performed,Performed"
|
|
bitfld.long 0x1C 8.--12. " ICOUNT ,Initial count of DMA transfers" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32"
|
|
bitfld.long 0x1C 6. " COUNTBIT17 ,17th bit of the COUNT field of DMAxCOUNT register" "0,1"
|
|
newline
|
|
bitfld.long 0x1C 0.--5. " COUNT ,Actual number of remaining DMA transfers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
group.long 0xF8++0x1F
|
|
line.long 0x0 "DMA0 COUNT,MibSPI DMA0 COUNT Register"
|
|
hexmask.long.word 0x0 16.--31. 1. " ICOUNT0 ,Initial number of DMA transfers"
|
|
hexmask.long.word 0x0 0.--15. 1. " COUNT0 ,The actual number of remaining DMA transfers"
|
|
line.long 0x4 "DMA1 COUNT,MibSPI DMA1 COUNT Register"
|
|
hexmask.long.word 0x4 16.--31. 1. " ICOUNT1 ,Initial number of DMA transfers"
|
|
hexmask.long.word 0x4 0.--15. 1. " COUNT1 ,The actual number of remaining DMA transfers"
|
|
line.long 0x8 "DMA2 COUNT,MibSPI DMA2 COUNT Register"
|
|
hexmask.long.word 0x8 16.--31. 1. " ICOUNT2 ,Initial number of DMA transfers"
|
|
hexmask.long.word 0x8 0.--15. 1. " COUNT2 ,The actual number of remaining DMA transfers"
|
|
line.long 0xC "DMA3 COUNT,MibSPI DMA3 COUNT Register"
|
|
hexmask.long.word 0xC 16.--31. 1. " ICOUNT3 ,Initial number of DMA transfers"
|
|
hexmask.long.word 0xC 0.--15. 1. " COUNT3 ,The actual number of remaining DMA transfers"
|
|
line.long 0x10 "DMA4 COUNT,MibSPI DMA4 COUNT Register"
|
|
hexmask.long.word 0x10 16.--31. 1. " ICOUNT4 ,Initial number of DMA transfers"
|
|
hexmask.long.word 0x10 0.--15. 1. " COUNT4 ,The actual number of remaining DMA transfers"
|
|
line.long 0x14 "DMA5 COUNT,MibSPI DMA5 COUNT Register"
|
|
hexmask.long.word 0x14 16.--31. 1. " ICOUNT5 ,Initial number of DMA transfers"
|
|
hexmask.long.word 0x14 0.--15. 1. " COUNT5 ,The actual number of remaining DMA transfers"
|
|
line.long 0x18 "DMA6 COUNT,MibSPI DMA6 COUNT Register"
|
|
hexmask.long.word 0x18 16.--31. 1. " ICOUNT6 ,Initial number of DMA transfers"
|
|
hexmask.long.word 0x18 0.--15. 1. " COUNT6 ,The actual number of remaining DMA transfers"
|
|
line.long 0x1C "DMA7 COUNT,MibSPI DMA7 COUNT Register"
|
|
hexmask.long.word 0x1C 16.--31. 1. " ICOUNT7 ,Initial number of DMA transfers"
|
|
hexmask.long.word 0x1C 0.--15. 1. " COUNT7 ,The actual number of remaining DMA transfers"
|
|
group.long 0x118++0x03
|
|
line.long 0x00 "DMACNTLEN,MibSPI DMACNTLEN Register"
|
|
bitfld.long 0x00 0. " LARGECOUNT ,Counters select" "DMAxCTRL,DMAxCOUNT"
|
|
endif
|
|
group.long 0x120++0x03
|
|
line.long 0x00 "UERRCTRL,Uncorrectable Parity Error Control Register"
|
|
bitfld.long 0x00 8. " PTESTEN ,Parity memory test enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--3. " EDEN ,Error detection enable" "Enabled,Enabled,Enabled,Enabled,Enabled,Disabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled"
|
|
group.long 0x124++0x03
|
|
line.long 0x00 "UERRSTAT,Uncorrectable Parity Error Status Register"
|
|
eventfld.long 0x00 1. " EDFLG1 ,Uncorrectable parity error detection flag" "Not occurred,Occurred"
|
|
eventfld.long 0x00 0. " EDFLG0 ,Uncorrectable parity error detection flag" "Not occurred,Occurred"
|
|
hgroup.long 0x128++0x03
|
|
hide.long 0x00 "UERRADDR1,Uncorrectable Parity Error Address Register"
|
|
in
|
|
hgroup.long 0x12C++0x03
|
|
hide.long 0x00 "UERRADDR0,Uncorrectable Parity Error Address Register"
|
|
in
|
|
hgroup.long 0x130++0x03
|
|
hide.long 0x00 "RXOVRN_BUF_ADDR,Receive RAM Overrun Buffer Address Register"
|
|
in
|
|
sif cpuis("TMS570LS0714*")||cpuis("TMS570LS0914*")||cpuis("TMS570LS0232")
|
|
if (((per.l.be(ad:0xFFF7F400+0x134))&0x2)==0x2)
|
|
group.long 0x134++0x03
|
|
line.long 0x00 "IOLPBKTSTCR,SPI IO Loopback Test Control Register"
|
|
bitfld.long 0x00 24. " SCSFAILFLG ,Failure on SPISCS pin compare during analog loopback" "Not occurred,Occurred"
|
|
bitfld.long 0x00 20. " CTRL_BITERR ,Controls inducing of BITERR during I/O loopback test mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " CTRL_DESYNC ,Controls inducing of the desync error during I/O loopback test mode" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 18. " CTRL_PARERR ,Controls inducing of parity errors during I/O loopback test mode" "No error,Error"
|
|
bitfld.long 0x00 17. " CTRL_TIMEOUT ,Controls inducing of the timeout error during I/O loopbacK test mode" "No error,Error"
|
|
bitfld.long 0x00 16. " CTRL_DLENERR ,Controls inducing of the data length error during I/O loopback test mode" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 8.--11. " IOLPBKTSTENA ,Module I/O loopback test enable key" "Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Enabled,Disabled,Disabled,Disabled,Disabled,Disabled"
|
|
sif cpuis("TMS570LS0232")
|
|
bitfld.long 0x00 3.--5. " ERRSCSPIN ,Inject error on chip-select pin number" "/SPISCS[0],/SPISCS[1],/SPISCS[2],/SPISCS[3],?..."
|
|
else
|
|
bitfld.long 0x00 3.--5. " ERRSCSPIN ,Inject error on chip-select pin number" "/SPISCS[0],/SPISCS[1],/SPISCS[2],/SPISCS[3],/SPISCS[4],/SPISCS[5],/SPISCS[6],/SPISCS[7]"
|
|
endif
|
|
bitfld.long 0x00 2. " CTRLSCSPINERR ,Enable/disable the injection of an error on the SPISCS[3:0] pins" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 1. " LPBK_TYPE ,Module I/O loopback type (analog/digital)" "Digital,Analog"
|
|
bitfld.long 0x00 0. " RXP_ENA ,Enable analog loopback through the receive pin" "Transmit,Receive"
|
|
else
|
|
group.long 0x134++0x03
|
|
line.long 0x00 "IOLPBKTSTCR,SPI IO Loopback Test Control Register"
|
|
bitfld.long 0x00 24. " SCSFAILFLG ,Failure on SPISCS pin compare during analog loopback" "Not occurred,Occurred"
|
|
bitfld.long 0x00 20. " CTRL_BITERR ,Controls inducing of BITERR during I/O loopback test mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " CTRL_DESYNC ,Controls inducing of the desync error during I/O loopback test mode" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 18. " CTRL_PARERR ,Controls inducing of parity errors during I/O loopback test mode" "No error,Error"
|
|
bitfld.long 0x00 17. " CTRL_TIMEOUT ,Controls inducing of the timeout error during I/O loopbacK test mode" "No error,Error"
|
|
bitfld.long 0x00 16. " CTRL_DLENERR ,Controls inducing of the data length error during I/O loopback test mode" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 8.--11. " IOLPBKTSTENA ,Module I/O loopback test enable key" "Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Enabled,Disabled,Disabled,Disabled,Disabled,Disabled"
|
|
sif cpuis("TMS570LS0232")
|
|
bitfld.long 0x00 3.--5. " ERRSCSPIN ,Inject error on chip-select pin number" "/SPISCS[0],/SPISCS[1],/SPISCS[2],/SPISCS[3],?..."
|
|
else
|
|
bitfld.long 0x00 3.--5. " ERRSCSPIN ,Inject error on chip-select pin number" "/SPISCS[0],/SPISCS[1],/SPISCS[2],/SPISCS[3],/SPISCS[4],/SPISCS[5],/SPISCS[6],/SPISCS[7]"
|
|
endif
|
|
bitfld.long 0x00 2. " CTRLSCSPINERR ,Enable/disable the injection of an error on the SPISCS[3:0] pins" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 1. " LPBK_TYPE ,Module I/O loopback type (analog/digital)" "Digital,Analog"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0xFFF7F400+0x134))&0x2)==0x2)
|
|
group.long 0x134++0x03
|
|
line.long 0x00 "IOLPBKTSTCR,SPI IO Loopback Test Control Register"
|
|
bitfld.long 0x00 24. " SCSFAILFLG ,Failure on SPISCS pin compare during analog loopback" "Not occurred,Occurred"
|
|
bitfld.long 0x00 20. " CTRL_BITERR ,Controls inducing of BITERR during I/O loopback test mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " CTRL_DESYNC ,Controls inducing of the desync error during I/O loopback test mode" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 18. " CTRL_PARERR ,Controls inducing of parity errors during I/O loopback test mode" "No error,Error"
|
|
bitfld.long 0x00 17. " CTRL_TIMEOUT ,Controls inducing of the timeout error during I/O loopbacK test mode" "No error,Error"
|
|
bitfld.long 0x00 16. " CTRL_DLENERR ,Controls inducing of the data length error during I/O loopback test mode" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 8.--11. " IOLPBKTSTENA ,Module I/O loopback test enable key" "Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Enabled,Disabled,Disabled,Disabled,Disabled,Disabled"
|
|
bitfld.long 0x00 3.--5. " ERRSCSPIN ,Inject error on chip-select pin number" "/SPISCS[0],/SPISCS[1],/SPISCS[2],/SPISCS[3],/SPISCS[4],/SPISCS[5],/SPISCS[6],/SPISCS[7]"
|
|
bitfld.long 0x00 2. " CTRLSCSPINERR ,Enable/disable the injection of an error on the SPISCS[3:0] pins" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 1. " LPBK_TYPE ,Module I/O loopback type (analog/digital)" "Digital,Analog"
|
|
bitfld.long 0x00 0. " RXP_ENA ,Enable analog loopback through the receive pin" "Transmit,Receive"
|
|
else
|
|
group.long 0x134++0x03
|
|
line.long 0x00 "IOLPBKTSTCR,SPI IO Loopback Test Control Register"
|
|
bitfld.long 0x00 24. " SCSFAILFLG ,Failure on SPISCS pin compare during analog loopback" "Not occurred,Occurred"
|
|
bitfld.long 0x00 20. " CTRL_BITERR ,Controls inducing of BITERR during I/O loopback test mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " CTRL_DESYNC ,Controls inducing of the desync error during I/O loopback test mode" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 18. " CTRL_PARERR ,Controls inducing of parity errors during I/O loopback test mode" "No error,Error"
|
|
bitfld.long 0x00 17. " CTRL_TIMEOUT ,Controls inducing of the timeout error during I/O loopbacK test mode" "No error,Error"
|
|
bitfld.long 0x00 16. " CTRL_DLENERR ,Controls inducing of the data length error during I/O loopback test mode" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 8.--11. " IOLPBKTSTENA ,Module I/O loopback test enable key" "Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Enabled,Disabled,Disabled,Disabled,Disabled,Disabled"
|
|
bitfld.long 0x00 3.--5. " ERRSCSPIN ,Inject error on chip-select pin number" "/SPISCS[0],/SPISCS[1],/SPISCS[2],/SPISCS[3],/SPISCS[4],/SPISCS[5],/SPISCS[6],/SPISCS[7]"
|
|
bitfld.long 0x00 2. " CTRLSCSPINERR ,Enable/disable the injection of an error on the SPISCS[3:0] pins" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 1. " LPBK_TYPE ,Module I/O loopback type (analog/digital)" "Digital,Analog"
|
|
endif
|
|
endif
|
|
sif (cpu()=="TMS570LC4357"||cpu()==("TMS570LS0332")||cpu()==("TMS570LS0432")||cpuis("TMS570LS1114*")||cpuis("TMS570LS1115*")||cpuis("TMS570LS1224*")||cpuis("TMS570LS1225*")||cpuis("TMS570LS1227*")||cpuis("TMS570LS0232")||cpuis("TMS570LS0714*")||cpuis("TMS570LS0914*"))
|
|
width 21.
|
|
newline
|
|
group.long 0x138++0x07
|
|
line.long 0x00 "EXTENDED_PRESCALE_1, SPI Extended Prescale Register 1"
|
|
hexmask.long.word 0x00 16.--26. 1. " EPRESCALE_FMT1 , Extended Prescale value for SPIFMT1"
|
|
hexmask.long.word 0x00 0.--10. 1. " EPRESCALE_FMT0 , Extended Prescale value for SPIFMT0"
|
|
line.long 0x04 "EXTENDED_PRESCALE_2, SPI Extended Prescale Register 2"
|
|
hexmask.long.word 0x04 16.--26. 1. " EPRESCALE_FMT3 , Extended Prescale value for SPIFMT3"
|
|
hexmask.long.word 0x04 0.--10. 1. " EPRESCALE_FMT2 , Extended Prescale value for SPIFMT2"
|
|
endif
|
|
sif !cpuis("TMS570LS0232")&&!cpuis("TMS570LS0714*")&&!cpuis("TMS570LS0914*")
|
|
sif (cpu()=="TMS570LC4357"||cpu()==("TMS570LS0332")||cpu()==("TMS570LS0432")||cpuis("TMS570LS1114*")||cpuis("TMS570LS1115*")||cpuis("TMS570LS1224*")||cpuis("TMS570LS1225*")||cpuis("TMS570LS1227*"))
|
|
sif cpuis("TMS570LC4357")
|
|
group.long 0x140++0x03
|
|
line.long 0x00 "ECCDIAG_CTRL, ECC Diagnostic Control register"
|
|
bitfld.long 0x00 0.--3. " ECCDIAG_EN , ECC Diagnostic mode Enable Key bits" "Disabled,Disabled,Disabled,Disabled,Disabled,Enabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled"
|
|
endif
|
|
if ((per.l(ad:0xFFF7F400+0x140)&0x5)==0x5)
|
|
group.long 0x144++0x03
|
|
line.long 0x00 "ECCDIAG_STAT, ECC Diagnostic Status register"
|
|
eventfld.long 0x00 17. " DEFLG[1] , Double bit Error is detected for RXRAM" "No error,Error"
|
|
eventfld.long 0x00 16. " DEFLG[0] , Double bit Error is detected for TXRAM" "No error,Error"
|
|
eventfld.long 0x00 1. " SEFLG[1] , Single bit Error is detected for RXRAM" "No error,Error"
|
|
eventfld.long 0x00 0. " SEFLG[0] , Single bit Error is detected for TXRAM" "No error,Error"
|
|
else
|
|
hgroup.long 0x144++0x03
|
|
hide.long 0x00 "ECCDIAG_STAT, ECC Diagnostic Status register"
|
|
in
|
|
endif
|
|
hgroup.long 0x148++0x03
|
|
hide.long 0x00 "SBERRADDR1, Single Bit Error Address Register - RXRAM"
|
|
in
|
|
hgroup.long 0x14C++0x03
|
|
hide.long 0x00 "SBERRADDR0, Single Bit Error Address Register - TXRAM"
|
|
in
|
|
endif
|
|
endif
|
|
sif cpuis("TMS570LS0232")||cpuis("TMS570LS0714*")||cpuis("TMS570LS0914*")
|
|
endian.be
|
|
endif
|
|
width 0xB
|
|
tree.end
|
|
tree "MibSPI1 RAM"
|
|
base ad:0xFF0E0000
|
|
sif cpuis("TMS570LS0232")||cpuis("TMS570LS0714*")||cpuis("TMS570LS0914*")
|
|
endian.be
|
|
endif
|
|
width 11.
|
|
sif (cpu()==("TMS570LS0332")||cpu()==("TMS570LS0432")||cpuis("TMS570LS1114*")||cpuis("TMS570LS1115*")||cpuis("TMS570LS1224*")||cpuis("TMS570LS1225*")||cpuis("TMS570LS1227*"))
|
|
group.long 0x0++0x03
|
|
line.long 0x00 "TXRAM, Multi-buffer RAM Transmit Data Register 0"
|
|
bitfld.long 0x00 29.--31. " BUFMODE , Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip Single Transfer,Skip Overwrite,Skip ST-Overwrite,Continuous,Suspend Single Transfer,Suspend Overwrite,Suspend ST-Overwrite"
|
|
bitfld.long 0x00 28. " CSHOLD , Chip select hold mode" "Deactivated,Activated"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK , Lock two consecutive buffer words" "0,1"
|
|
bitfld.long 0x00 26. " WDEL , Enable the delay counter at the end of the current transaction" "Disable,Enable"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL , Data word format select" "Format 0,Format 1,Format 2,Format 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR , Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA , Transfer data"
|
|
group.long 0x4++0x03
|
|
line.long 0x00 "TXRAM, Multi-buffer RAM Transmit Data Register 1"
|
|
bitfld.long 0x00 29.--31. " BUFMODE , Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip Single Transfer,Skip Overwrite,Skip ST-Overwrite,Continuous,Suspend Single Transfer,Suspend Overwrite,Suspend ST-Overwrite"
|
|
bitfld.long 0x00 28. " CSHOLD , Chip select hold mode" "Deactivated,Activated"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK , Lock two consecutive buffer words" "0,1"
|
|
bitfld.long 0x00 26. " WDEL , Enable the delay counter at the end of the current transaction" "Disable,Enable"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL , Data word format select" "Format 0,Format 1,Format 2,Format 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR , Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA , Transfer data"
|
|
group.long 0x8++0x03
|
|
line.long 0x00 "TXRAM, Multi-buffer RAM Transmit Data Register 2"
|
|
bitfld.long 0x00 29.--31. " BUFMODE , Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip Single Transfer,Skip Overwrite,Skip ST-Overwrite,Continuous,Suspend Single Transfer,Suspend Overwrite,Suspend ST-Overwrite"
|
|
bitfld.long 0x00 28. " CSHOLD , Chip select hold mode" "Deactivated,Activated"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK , Lock two consecutive buffer words" "0,1"
|
|
bitfld.long 0x00 26. " WDEL , Enable the delay counter at the end of the current transaction" "Disable,Enable"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL , Data word format select" "Format 0,Format 1,Format 2,Format 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR , Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA , Transfer data"
|
|
group.long 0xC++0x03
|
|
line.long 0x00 "TXRAM, Multi-buffer RAM Transmit Data Register 3"
|
|
bitfld.long 0x00 29.--31. " BUFMODE , Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip Single Transfer,Skip Overwrite,Skip ST-Overwrite,Continuous,Suspend Single Transfer,Suspend Overwrite,Suspend ST-Overwrite"
|
|
bitfld.long 0x00 28. " CSHOLD , Chip select hold mode" "Deactivated,Activated"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK , Lock two consecutive buffer words" "0,1"
|
|
bitfld.long 0x00 26. " WDEL , Enable the delay counter at the end of the current transaction" "Disable,Enable"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL , Data word format select" "Format 0,Format 1,Format 2,Format 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR , Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA , Transfer data"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "TXRAM, Multi-buffer RAM Transmit Data Register 4"
|
|
bitfld.long 0x00 29.--31. " BUFMODE , Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip Single Transfer,Skip Overwrite,Skip ST-Overwrite,Continuous,Suspend Single Transfer,Suspend Overwrite,Suspend ST-Overwrite"
|
|
bitfld.long 0x00 28. " CSHOLD , Chip select hold mode" "Deactivated,Activated"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK , Lock two consecutive buffer words" "0,1"
|
|
bitfld.long 0x00 26. " WDEL , Enable the delay counter at the end of the current transaction" "Disable,Enable"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL , Data word format select" "Format 0,Format 1,Format 2,Format 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR , Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA , Transfer data"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "TXRAM, Multi-buffer RAM Transmit Data Register 5"
|
|
bitfld.long 0x00 29.--31. " BUFMODE , Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip Single Transfer,Skip Overwrite,Skip ST-Overwrite,Continuous,Suspend Single Transfer,Suspend Overwrite,Suspend ST-Overwrite"
|
|
bitfld.long 0x00 28. " CSHOLD , Chip select hold mode" "Deactivated,Activated"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK , Lock two consecutive buffer words" "0,1"
|
|
bitfld.long 0x00 26. " WDEL , Enable the delay counter at the end of the current transaction" "Disable,Enable"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL , Data word format select" "Format 0,Format 1,Format 2,Format 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR , Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA , Transfer data"
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "TXRAM, Multi-buffer RAM Transmit Data Register 6"
|
|
bitfld.long 0x00 29.--31. " BUFMODE , Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip Single Transfer,Skip Overwrite,Skip ST-Overwrite,Continuous,Suspend Single Transfer,Suspend Overwrite,Suspend ST-Overwrite"
|
|
bitfld.long 0x00 28. " CSHOLD , Chip select hold mode" "Deactivated,Activated"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK , Lock two consecutive buffer words" "0,1"
|
|
bitfld.long 0x00 26. " WDEL , Enable the delay counter at the end of the current transaction" "Disable,Enable"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL , Data word format select" "Format 0,Format 1,Format 2,Format 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR , Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA , Transfer data"
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "TXRAM, Multi-buffer RAM Transmit Data Register 7"
|
|
bitfld.long 0x00 29.--31. " BUFMODE , Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip Single Transfer,Skip Overwrite,Skip ST-Overwrite,Continuous,Suspend Single Transfer,Suspend Overwrite,Suspend ST-Overwrite"
|
|
bitfld.long 0x00 28. " CSHOLD , Chip select hold mode" "Deactivated,Activated"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK , Lock two consecutive buffer words" "0,1"
|
|
bitfld.long 0x00 26. " WDEL , Enable the delay counter at the end of the current transaction" "Disable,Enable"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL , Data word format select" "Format 0,Format 1,Format 2,Format 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR , Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA , Transfer data"
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "TXRAM, Multi-buffer RAM Transmit Data Register 8"
|
|
bitfld.long 0x00 29.--31. " BUFMODE , Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip Single Transfer,Skip Overwrite,Skip ST-Overwrite,Continuous,Suspend Single Transfer,Suspend Overwrite,Suspend ST-Overwrite"
|
|
bitfld.long 0x00 28. " CSHOLD , Chip select hold mode" "Deactivated,Activated"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK , Lock two consecutive buffer words" "0,1"
|
|
bitfld.long 0x00 26. " WDEL , Enable the delay counter at the end of the current transaction" "Disable,Enable"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL , Data word format select" "Format 0,Format 1,Format 2,Format 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR , Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA , Transfer data"
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "TXRAM, Multi-buffer RAM Transmit Data Register 9"
|
|
bitfld.long 0x00 29.--31. " BUFMODE , Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip Single Transfer,Skip Overwrite,Skip ST-Overwrite,Continuous,Suspend Single Transfer,Suspend Overwrite,Suspend ST-Overwrite"
|
|
bitfld.long 0x00 28. " CSHOLD , Chip select hold mode" "Deactivated,Activated"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK , Lock two consecutive buffer words" "0,1"
|
|
bitfld.long 0x00 26. " WDEL , Enable the delay counter at the end of the current transaction" "Disable,Enable"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL , Data word format select" "Format 0,Format 1,Format 2,Format 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR , Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA , Transfer data"
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "TXRAM, Multi-buffer RAM Transmit Data Register 10"
|
|
bitfld.long 0x00 29.--31. " BUFMODE , Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip Single Transfer,Skip Overwrite,Skip ST-Overwrite,Continuous,Suspend Single Transfer,Suspend Overwrite,Suspend ST-Overwrite"
|
|
bitfld.long 0x00 28. " CSHOLD , Chip select hold mode" "Deactivated,Activated"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK , Lock two consecutive buffer words" "0,1"
|
|
bitfld.long 0x00 26. " WDEL , Enable the delay counter at the end of the current transaction" "Disable,Enable"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL , Data word format select" "Format 0,Format 1,Format 2,Format 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR , Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA , Transfer data"
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "TXRAM, Multi-buffer RAM Transmit Data Register 11"
|
|
bitfld.long 0x00 29.--31. " BUFMODE , Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip Single Transfer,Skip Overwrite,Skip ST-Overwrite,Continuous,Suspend Single Transfer,Suspend Overwrite,Suspend ST-Overwrite"
|
|
bitfld.long 0x00 28. " CSHOLD , Chip select hold mode" "Deactivated,Activated"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK , Lock two consecutive buffer words" "0,1"
|
|
bitfld.long 0x00 26. " WDEL , Enable the delay counter at the end of the current transaction" "Disable,Enable"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL , Data word format select" "Format 0,Format 1,Format 2,Format 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR , Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA , Transfer data"
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "TXRAM, Multi-buffer RAM Transmit Data Register 12"
|
|
bitfld.long 0x00 29.--31. " BUFMODE , Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip Single Transfer,Skip Overwrite,Skip ST-Overwrite,Continuous,Suspend Single Transfer,Suspend Overwrite,Suspend ST-Overwrite"
|
|
bitfld.long 0x00 28. " CSHOLD , Chip select hold mode" "Deactivated,Activated"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK , Lock two consecutive buffer words" "0,1"
|
|
bitfld.long 0x00 26. " WDEL , Enable the delay counter at the end of the current transaction" "Disable,Enable"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL , Data word format select" "Format 0,Format 1,Format 2,Format 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR , Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA , Transfer data"
|
|
group.long 0x34++0x03
|
|
line.long 0x00 "TXRAM, Multi-buffer RAM Transmit Data Register 13"
|
|
bitfld.long 0x00 29.--31. " BUFMODE , Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip Single Transfer,Skip Overwrite,Skip ST-Overwrite,Continuous,Suspend Single Transfer,Suspend Overwrite,Suspend ST-Overwrite"
|
|
bitfld.long 0x00 28. " CSHOLD , Chip select hold mode" "Deactivated,Activated"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK , Lock two consecutive buffer words" "0,1"
|
|
bitfld.long 0x00 26. " WDEL , Enable the delay counter at the end of the current transaction" "Disable,Enable"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL , Data word format select" "Format 0,Format 1,Format 2,Format 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR , Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA , Transfer data"
|
|
group.long 0x38++0x03
|
|
line.long 0x00 "TXRAM, Multi-buffer RAM Transmit Data Register 14"
|
|
bitfld.long 0x00 29.--31. " BUFMODE , Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip Single Transfer,Skip Overwrite,Skip ST-Overwrite,Continuous,Suspend Single Transfer,Suspend Overwrite,Suspend ST-Overwrite"
|
|
bitfld.long 0x00 28. " CSHOLD , Chip select hold mode" "Deactivated,Activated"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK , Lock two consecutive buffer words" "0,1"
|
|
bitfld.long 0x00 26. " WDEL , Enable the delay counter at the end of the current transaction" "Disable,Enable"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL , Data word format select" "Format 0,Format 1,Format 2,Format 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR , Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA , Transfer data"
|
|
group.long 0x3C++0x03
|
|
line.long 0x00 "TXRAM, Multi-buffer RAM Transmit Data Register 15"
|
|
bitfld.long 0x00 29.--31. " BUFMODE , Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip Single Transfer,Skip Overwrite,Skip ST-Overwrite,Continuous,Suspend Single Transfer,Suspend Overwrite,Suspend ST-Overwrite"
|
|
bitfld.long 0x00 28. " CSHOLD , Chip select hold mode" "Deactivated,Activated"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK , Lock two consecutive buffer words" "0,1"
|
|
bitfld.long 0x00 26. " WDEL , Enable the delay counter at the end of the current transaction" "Disable,Enable"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL , Data word format select" "Format 0,Format 1,Format 2,Format 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR , Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA , Transfer data"
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "TXRAM, Multi-buffer RAM Transmit Data Register 16"
|
|
bitfld.long 0x00 29.--31. " BUFMODE , Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip Single Transfer,Skip Overwrite,Skip ST-Overwrite,Continuous,Suspend Single Transfer,Suspend Overwrite,Suspend ST-Overwrite"
|
|
bitfld.long 0x00 28. " CSHOLD , Chip select hold mode" "Deactivated,Activated"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK , Lock two consecutive buffer words" "0,1"
|
|
bitfld.long 0x00 26. " WDEL , Enable the delay counter at the end of the current transaction" "Disable,Enable"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL , Data word format select" "Format 0,Format 1,Format 2,Format 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR , Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA , Transfer data"
|
|
group.long 0x44++0x03
|
|
line.long 0x00 "TXRAM, Multi-buffer RAM Transmit Data Register 17"
|
|
bitfld.long 0x00 29.--31. " BUFMODE , Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip Single Transfer,Skip Overwrite,Skip ST-Overwrite,Continuous,Suspend Single Transfer,Suspend Overwrite,Suspend ST-Overwrite"
|
|
bitfld.long 0x00 28. " CSHOLD , Chip select hold mode" "Deactivated,Activated"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK , Lock two consecutive buffer words" "0,1"
|
|
bitfld.long 0x00 26. " WDEL , Enable the delay counter at the end of the current transaction" "Disable,Enable"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL , Data word format select" "Format 0,Format 1,Format 2,Format 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR , Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA , Transfer data"
|
|
group.long 0x48++0x03
|
|
line.long 0x00 "TXRAM, Multi-buffer RAM Transmit Data Register 18"
|
|
bitfld.long 0x00 29.--31. " BUFMODE , Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip Single Transfer,Skip Overwrite,Skip ST-Overwrite,Continuous,Suspend Single Transfer,Suspend Overwrite,Suspend ST-Overwrite"
|
|
bitfld.long 0x00 28. " CSHOLD , Chip select hold mode" "Deactivated,Activated"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK , Lock two consecutive buffer words" "0,1"
|
|
bitfld.long 0x00 26. " WDEL , Enable the delay counter at the end of the current transaction" "Disable,Enable"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL , Data word format select" "Format 0,Format 1,Format 2,Format 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR , Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA , Transfer data"
|
|
group.long 0x4C++0x03
|
|
line.long 0x00 "TXRAM, Multi-buffer RAM Transmit Data Register 19"
|
|
bitfld.long 0x00 29.--31. " BUFMODE , Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip Single Transfer,Skip Overwrite,Skip ST-Overwrite,Continuous,Suspend Single Transfer,Suspend Overwrite,Suspend ST-Overwrite"
|
|
bitfld.long 0x00 28. " CSHOLD , Chip select hold mode" "Deactivated,Activated"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK , Lock two consecutive buffer words" "0,1"
|
|
bitfld.long 0x00 26. " WDEL , Enable the delay counter at the end of the current transaction" "Disable,Enable"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL , Data word format select" "Format 0,Format 1,Format 2,Format 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR , Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA , Transfer data"
|
|
group.long 0x50++0x03
|
|
line.long 0x00 "TXRAM, Multi-buffer RAM Transmit Data Register 20"
|
|
bitfld.long 0x00 29.--31. " BUFMODE , Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip Single Transfer,Skip Overwrite,Skip ST-Overwrite,Continuous,Suspend Single Transfer,Suspend Overwrite,Suspend ST-Overwrite"
|
|
bitfld.long 0x00 28. " CSHOLD , Chip select hold mode" "Deactivated,Activated"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK , Lock two consecutive buffer words" "0,1"
|
|
bitfld.long 0x00 26. " WDEL , Enable the delay counter at the end of the current transaction" "Disable,Enable"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL , Data word format select" "Format 0,Format 1,Format 2,Format 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR , Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA , Transfer data"
|
|
group.long 0x54++0x03
|
|
line.long 0x00 "TXRAM, Multi-buffer RAM Transmit Data Register 21"
|
|
bitfld.long 0x00 29.--31. " BUFMODE , Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip Single Transfer,Skip Overwrite,Skip ST-Overwrite,Continuous,Suspend Single Transfer,Suspend Overwrite,Suspend ST-Overwrite"
|
|
bitfld.long 0x00 28. " CSHOLD , Chip select hold mode" "Deactivated,Activated"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK , Lock two consecutive buffer words" "0,1"
|
|
bitfld.long 0x00 26. " WDEL , Enable the delay counter at the end of the current transaction" "Disable,Enable"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL , Data word format select" "Format 0,Format 1,Format 2,Format 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR , Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA , Transfer data"
|
|
group.long 0x58++0x03
|
|
line.long 0x00 "TXRAM, Multi-buffer RAM Transmit Data Register 22"
|
|
bitfld.long 0x00 29.--31. " BUFMODE , Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip Single Transfer,Skip Overwrite,Skip ST-Overwrite,Continuous,Suspend Single Transfer,Suspend Overwrite,Suspend ST-Overwrite"
|
|
bitfld.long 0x00 28. " CSHOLD , Chip select hold mode" "Deactivated,Activated"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK , Lock two consecutive buffer words" "0,1"
|
|
bitfld.long 0x00 26. " WDEL , Enable the delay counter at the end of the current transaction" "Disable,Enable"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL , Data word format select" "Format 0,Format 1,Format 2,Format 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR , Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA , Transfer data"
|
|
group.long 0x5C++0x03
|
|
line.long 0x00 "TXRAM, Multi-buffer RAM Transmit Data Register 23"
|
|
bitfld.long 0x00 29.--31. " BUFMODE , Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip Single Transfer,Skip Overwrite,Skip ST-Overwrite,Continuous,Suspend Single Transfer,Suspend Overwrite,Suspend ST-Overwrite"
|
|
bitfld.long 0x00 28. " CSHOLD , Chip select hold mode" "Deactivated,Activated"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK , Lock two consecutive buffer words" "0,1"
|
|
bitfld.long 0x00 26. " WDEL , Enable the delay counter at the end of the current transaction" "Disable,Enable"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL , Data word format select" "Format 0,Format 1,Format 2,Format 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR , Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA , Transfer data"
|
|
group.long 0x60++0x03
|
|
line.long 0x00 "TXRAM, Multi-buffer RAM Transmit Data Register 24"
|
|
bitfld.long 0x00 29.--31. " BUFMODE , Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip Single Transfer,Skip Overwrite,Skip ST-Overwrite,Continuous,Suspend Single Transfer,Suspend Overwrite,Suspend ST-Overwrite"
|
|
bitfld.long 0x00 28. " CSHOLD , Chip select hold mode" "Deactivated,Activated"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK , Lock two consecutive buffer words" "0,1"
|
|
bitfld.long 0x00 26. " WDEL , Enable the delay counter at the end of the current transaction" "Disable,Enable"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL , Data word format select" "Format 0,Format 1,Format 2,Format 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR , Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA , Transfer data"
|
|
group.long 0x64++0x03
|
|
line.long 0x00 "TXRAM, Multi-buffer RAM Transmit Data Register 25"
|
|
bitfld.long 0x00 29.--31. " BUFMODE , Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip Single Transfer,Skip Overwrite,Skip ST-Overwrite,Continuous,Suspend Single Transfer,Suspend Overwrite,Suspend ST-Overwrite"
|
|
bitfld.long 0x00 28. " CSHOLD , Chip select hold mode" "Deactivated,Activated"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK , Lock two consecutive buffer words" "0,1"
|
|
bitfld.long 0x00 26. " WDEL , Enable the delay counter at the end of the current transaction" "Disable,Enable"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL , Data word format select" "Format 0,Format 1,Format 2,Format 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR , Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA , Transfer data"
|
|
group.long 0x68++0x03
|
|
line.long 0x00 "TXRAM, Multi-buffer RAM Transmit Data Register 26"
|
|
bitfld.long 0x00 29.--31. " BUFMODE , Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip Single Transfer,Skip Overwrite,Skip ST-Overwrite,Continuous,Suspend Single Transfer,Suspend Overwrite,Suspend ST-Overwrite"
|
|
bitfld.long 0x00 28. " CSHOLD , Chip select hold mode" "Deactivated,Activated"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK , Lock two consecutive buffer words" "0,1"
|
|
bitfld.long 0x00 26. " WDEL , Enable the delay counter at the end of the current transaction" "Disable,Enable"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL , Data word format select" "Format 0,Format 1,Format 2,Format 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR , Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA , Transfer data"
|
|
group.long 0x6C++0x03
|
|
line.long 0x00 "TXRAM, Multi-buffer RAM Transmit Data Register 27"
|
|
bitfld.long 0x00 29.--31. " BUFMODE , Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip Single Transfer,Skip Overwrite,Skip ST-Overwrite,Continuous,Suspend Single Transfer,Suspend Overwrite,Suspend ST-Overwrite"
|
|
bitfld.long 0x00 28. " CSHOLD , Chip select hold mode" "Deactivated,Activated"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK , Lock two consecutive buffer words" "0,1"
|
|
bitfld.long 0x00 26. " WDEL , Enable the delay counter at the end of the current transaction" "Disable,Enable"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL , Data word format select" "Format 0,Format 1,Format 2,Format 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR , Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA , Transfer data"
|
|
group.long 0x70++0x03
|
|
line.long 0x00 "TXRAM, Multi-buffer RAM Transmit Data Register 28"
|
|
bitfld.long 0x00 29.--31. " BUFMODE , Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip Single Transfer,Skip Overwrite,Skip ST-Overwrite,Continuous,Suspend Single Transfer,Suspend Overwrite,Suspend ST-Overwrite"
|
|
bitfld.long 0x00 28. " CSHOLD , Chip select hold mode" "Deactivated,Activated"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK , Lock two consecutive buffer words" "0,1"
|
|
bitfld.long 0x00 26. " WDEL , Enable the delay counter at the end of the current transaction" "Disable,Enable"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL , Data word format select" "Format 0,Format 1,Format 2,Format 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR , Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA , Transfer data"
|
|
group.long 0x74++0x03
|
|
line.long 0x00 "TXRAM, Multi-buffer RAM Transmit Data Register 29"
|
|
bitfld.long 0x00 29.--31. " BUFMODE , Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip Single Transfer,Skip Overwrite,Skip ST-Overwrite,Continuous,Suspend Single Transfer,Suspend Overwrite,Suspend ST-Overwrite"
|
|
bitfld.long 0x00 28. " CSHOLD , Chip select hold mode" "Deactivated,Activated"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK , Lock two consecutive buffer words" "0,1"
|
|
bitfld.long 0x00 26. " WDEL , Enable the delay counter at the end of the current transaction" "Disable,Enable"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL , Data word format select" "Format 0,Format 1,Format 2,Format 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR , Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA , Transfer data"
|
|
group.long 0x78++0x03
|
|
line.long 0x00 "TXRAM, Multi-buffer RAM Transmit Data Register 30"
|
|
bitfld.long 0x00 29.--31. " BUFMODE , Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip Single Transfer,Skip Overwrite,Skip ST-Overwrite,Continuous,Suspend Single Transfer,Suspend Overwrite,Suspend ST-Overwrite"
|
|
bitfld.long 0x00 28. " CSHOLD , Chip select hold mode" "Deactivated,Activated"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK , Lock two consecutive buffer words" "0,1"
|
|
bitfld.long 0x00 26. " WDEL , Enable the delay counter at the end of the current transaction" "Disable,Enable"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL , Data word format select" "Format 0,Format 1,Format 2,Format 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR , Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA , Transfer data"
|
|
group.long 0x7C++0x03
|
|
line.long 0x00 "TXRAM, Multi-buffer RAM Transmit Data Register 31"
|
|
bitfld.long 0x00 29.--31. " BUFMODE , Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip Single Transfer,Skip Overwrite,Skip ST-Overwrite,Continuous,Suspend Single Transfer,Suspend Overwrite,Suspend ST-Overwrite"
|
|
bitfld.long 0x00 28. " CSHOLD , Chip select hold mode" "Deactivated,Activated"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK , Lock two consecutive buffer words" "0,1"
|
|
bitfld.long 0x00 26. " WDEL , Enable the delay counter at the end of the current transaction" "Disable,Enable"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL , Data word format select" "Format 0,Format 1,Format 2,Format 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR , Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA , Transfer data"
|
|
group.long 0x80++0x03
|
|
line.long 0x00 "TXRAM, Multi-buffer RAM Transmit Data Register 32"
|
|
bitfld.long 0x00 29.--31. " BUFMODE , Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip Single Transfer,Skip Overwrite,Skip ST-Overwrite,Continuous,Suspend Single Transfer,Suspend Overwrite,Suspend ST-Overwrite"
|
|
bitfld.long 0x00 28. " CSHOLD , Chip select hold mode" "Deactivated,Activated"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK , Lock two consecutive buffer words" "0,1"
|
|
bitfld.long 0x00 26. " WDEL , Enable the delay counter at the end of the current transaction" "Disable,Enable"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL , Data word format select" "Format 0,Format 1,Format 2,Format 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR , Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA , Transfer data"
|
|
group.long 0x84++0x03
|
|
line.long 0x00 "TXRAM, Multi-buffer RAM Transmit Data Register 33"
|
|
bitfld.long 0x00 29.--31. " BUFMODE , Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip Single Transfer,Skip Overwrite,Skip ST-Overwrite,Continuous,Suspend Single Transfer,Suspend Overwrite,Suspend ST-Overwrite"
|
|
bitfld.long 0x00 28. " CSHOLD , Chip select hold mode" "Deactivated,Activated"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK , Lock two consecutive buffer words" "0,1"
|
|
bitfld.long 0x00 26. " WDEL , Enable the delay counter at the end of the current transaction" "Disable,Enable"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL , Data word format select" "Format 0,Format 1,Format 2,Format 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR , Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA , Transfer data"
|
|
group.long 0x88++0x03
|
|
line.long 0x00 "TXRAM, Multi-buffer RAM Transmit Data Register 34"
|
|
bitfld.long 0x00 29.--31. " BUFMODE , Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip Single Transfer,Skip Overwrite,Skip ST-Overwrite,Continuous,Suspend Single Transfer,Suspend Overwrite,Suspend ST-Overwrite"
|
|
bitfld.long 0x00 28. " CSHOLD , Chip select hold mode" "Deactivated,Activated"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK , Lock two consecutive buffer words" "0,1"
|
|
bitfld.long 0x00 26. " WDEL , Enable the delay counter at the end of the current transaction" "Disable,Enable"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL , Data word format select" "Format 0,Format 1,Format 2,Format 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR , Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA , Transfer data"
|
|
group.long 0x8C++0x03
|
|
line.long 0x00 "TXRAM, Multi-buffer RAM Transmit Data Register 35"
|
|
bitfld.long 0x00 29.--31. " BUFMODE , Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip Single Transfer,Skip Overwrite,Skip ST-Overwrite,Continuous,Suspend Single Transfer,Suspend Overwrite,Suspend ST-Overwrite"
|
|
bitfld.long 0x00 28. " CSHOLD , Chip select hold mode" "Deactivated,Activated"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK , Lock two consecutive buffer words" "0,1"
|
|
bitfld.long 0x00 26. " WDEL , Enable the delay counter at the end of the current transaction" "Disable,Enable"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL , Data word format select" "Format 0,Format 1,Format 2,Format 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR , Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA , Transfer data"
|
|
group.long 0x90++0x03
|
|
line.long 0x00 "TXRAM, Multi-buffer RAM Transmit Data Register 36"
|
|
bitfld.long 0x00 29.--31. " BUFMODE , Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip Single Transfer,Skip Overwrite,Skip ST-Overwrite,Continuous,Suspend Single Transfer,Suspend Overwrite,Suspend ST-Overwrite"
|
|
bitfld.long 0x00 28. " CSHOLD , Chip select hold mode" "Deactivated,Activated"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK , Lock two consecutive buffer words" "0,1"
|
|
bitfld.long 0x00 26. " WDEL , Enable the delay counter at the end of the current transaction" "Disable,Enable"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL , Data word format select" "Format 0,Format 1,Format 2,Format 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR , Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA , Transfer data"
|
|
group.long 0x94++0x03
|
|
line.long 0x00 "TXRAM, Multi-buffer RAM Transmit Data Register 37"
|
|
bitfld.long 0x00 29.--31. " BUFMODE , Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip Single Transfer,Skip Overwrite,Skip ST-Overwrite,Continuous,Suspend Single Transfer,Suspend Overwrite,Suspend ST-Overwrite"
|
|
bitfld.long 0x00 28. " CSHOLD , Chip select hold mode" "Deactivated,Activated"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK , Lock two consecutive buffer words" "0,1"
|
|
bitfld.long 0x00 26. " WDEL , Enable the delay counter at the end of the current transaction" "Disable,Enable"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL , Data word format select" "Format 0,Format 1,Format 2,Format 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR , Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA , Transfer data"
|
|
group.long 0x98++0x03
|
|
line.long 0x00 "TXRAM, Multi-buffer RAM Transmit Data Register 38"
|
|
bitfld.long 0x00 29.--31. " BUFMODE , Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip Single Transfer,Skip Overwrite,Skip ST-Overwrite,Continuous,Suspend Single Transfer,Suspend Overwrite,Suspend ST-Overwrite"
|
|
bitfld.long 0x00 28. " CSHOLD , Chip select hold mode" "Deactivated,Activated"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK , Lock two consecutive buffer words" "0,1"
|
|
bitfld.long 0x00 26. " WDEL , Enable the delay counter at the end of the current transaction" "Disable,Enable"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL , Data word format select" "Format 0,Format 1,Format 2,Format 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR , Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA , Transfer data"
|
|
group.long 0x9C++0x03
|
|
line.long 0x00 "TXRAM, Multi-buffer RAM Transmit Data Register 39"
|
|
bitfld.long 0x00 29.--31. " BUFMODE , Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip Single Transfer,Skip Overwrite,Skip ST-Overwrite,Continuous,Suspend Single Transfer,Suspend Overwrite,Suspend ST-Overwrite"
|
|
bitfld.long 0x00 28. " CSHOLD , Chip select hold mode" "Deactivated,Activated"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK , Lock two consecutive buffer words" "0,1"
|
|
bitfld.long 0x00 26. " WDEL , Enable the delay counter at the end of the current transaction" "Disable,Enable"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL , Data word format select" "Format 0,Format 1,Format 2,Format 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR , Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA , Transfer data"
|
|
group.long 0xA0++0x03
|
|
line.long 0x00 "TXRAM, Multi-buffer RAM Transmit Data Register 40"
|
|
bitfld.long 0x00 29.--31. " BUFMODE , Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip Single Transfer,Skip Overwrite,Skip ST-Overwrite,Continuous,Suspend Single Transfer,Suspend Overwrite,Suspend ST-Overwrite"
|
|
bitfld.long 0x00 28. " CSHOLD , Chip select hold mode" "Deactivated,Activated"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK , Lock two consecutive buffer words" "0,1"
|
|
bitfld.long 0x00 26. " WDEL , Enable the delay counter at the end of the current transaction" "Disable,Enable"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL , Data word format select" "Format 0,Format 1,Format 2,Format 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR , Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA , Transfer data"
|
|
group.long 0xA4++0x03
|
|
line.long 0x00 "TXRAM, Multi-buffer RAM Transmit Data Register 41"
|
|
bitfld.long 0x00 29.--31. " BUFMODE , Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip Single Transfer,Skip Overwrite,Skip ST-Overwrite,Continuous,Suspend Single Transfer,Suspend Overwrite,Suspend ST-Overwrite"
|
|
bitfld.long 0x00 28. " CSHOLD , Chip select hold mode" "Deactivated,Activated"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK , Lock two consecutive buffer words" "0,1"
|
|
bitfld.long 0x00 26. " WDEL , Enable the delay counter at the end of the current transaction" "Disable,Enable"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL , Data word format select" "Format 0,Format 1,Format 2,Format 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR , Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA , Transfer data"
|
|
group.long 0xA8++0x03
|
|
line.long 0x00 "TXRAM, Multi-buffer RAM Transmit Data Register 42"
|
|
bitfld.long 0x00 29.--31. " BUFMODE , Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip Single Transfer,Skip Overwrite,Skip ST-Overwrite,Continuous,Suspend Single Transfer,Suspend Overwrite,Suspend ST-Overwrite"
|
|
bitfld.long 0x00 28. " CSHOLD , Chip select hold mode" "Deactivated,Activated"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK , Lock two consecutive buffer words" "0,1"
|
|
bitfld.long 0x00 26. " WDEL , Enable the delay counter at the end of the current transaction" "Disable,Enable"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL , Data word format select" "Format 0,Format 1,Format 2,Format 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR , Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA , Transfer data"
|
|
group.long 0xAC++0x03
|
|
line.long 0x00 "TXRAM, Multi-buffer RAM Transmit Data Register 43"
|
|
bitfld.long 0x00 29.--31. " BUFMODE , Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip Single Transfer,Skip Overwrite,Skip ST-Overwrite,Continuous,Suspend Single Transfer,Suspend Overwrite,Suspend ST-Overwrite"
|
|
bitfld.long 0x00 28. " CSHOLD , Chip select hold mode" "Deactivated,Activated"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK , Lock two consecutive buffer words" "0,1"
|
|
bitfld.long 0x00 26. " WDEL , Enable the delay counter at the end of the current transaction" "Disable,Enable"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL , Data word format select" "Format 0,Format 1,Format 2,Format 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR , Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA , Transfer data"
|
|
group.long 0xB0++0x03
|
|
line.long 0x00 "TXRAM, Multi-buffer RAM Transmit Data Register 44"
|
|
bitfld.long 0x00 29.--31. " BUFMODE , Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip Single Transfer,Skip Overwrite,Skip ST-Overwrite,Continuous,Suspend Single Transfer,Suspend Overwrite,Suspend ST-Overwrite"
|
|
bitfld.long 0x00 28. " CSHOLD , Chip select hold mode" "Deactivated,Activated"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK , Lock two consecutive buffer words" "0,1"
|
|
bitfld.long 0x00 26. " WDEL , Enable the delay counter at the end of the current transaction" "Disable,Enable"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL , Data word format select" "Format 0,Format 1,Format 2,Format 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR , Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA , Transfer data"
|
|
group.long 0xB4++0x03
|
|
line.long 0x00 "TXRAM, Multi-buffer RAM Transmit Data Register 45"
|
|
bitfld.long 0x00 29.--31. " BUFMODE , Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip Single Transfer,Skip Overwrite,Skip ST-Overwrite,Continuous,Suspend Single Transfer,Suspend Overwrite,Suspend ST-Overwrite"
|
|
bitfld.long 0x00 28. " CSHOLD , Chip select hold mode" "Deactivated,Activated"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK , Lock two consecutive buffer words" "0,1"
|
|
bitfld.long 0x00 26. " WDEL , Enable the delay counter at the end of the current transaction" "Disable,Enable"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL , Data word format select" "Format 0,Format 1,Format 2,Format 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR , Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA , Transfer data"
|
|
group.long 0xB8++0x03
|
|
line.long 0x00 "TXRAM, Multi-buffer RAM Transmit Data Register 46"
|
|
bitfld.long 0x00 29.--31. " BUFMODE , Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip Single Transfer,Skip Overwrite,Skip ST-Overwrite,Continuous,Suspend Single Transfer,Suspend Overwrite,Suspend ST-Overwrite"
|
|
bitfld.long 0x00 28. " CSHOLD , Chip select hold mode" "Deactivated,Activated"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK , Lock two consecutive buffer words" "0,1"
|
|
bitfld.long 0x00 26. " WDEL , Enable the delay counter at the end of the current transaction" "Disable,Enable"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL , Data word format select" "Format 0,Format 1,Format 2,Format 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR , Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA , Transfer data"
|
|
group.long 0xBC++0x03
|
|
line.long 0x00 "TXRAM, Multi-buffer RAM Transmit Data Register 47"
|
|
bitfld.long 0x00 29.--31. " BUFMODE , Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip Single Transfer,Skip Overwrite,Skip ST-Overwrite,Continuous,Suspend Single Transfer,Suspend Overwrite,Suspend ST-Overwrite"
|
|
bitfld.long 0x00 28. " CSHOLD , Chip select hold mode" "Deactivated,Activated"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK , Lock two consecutive buffer words" "0,1"
|
|
bitfld.long 0x00 26. " WDEL , Enable the delay counter at the end of the current transaction" "Disable,Enable"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL , Data word format select" "Format 0,Format 1,Format 2,Format 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR , Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA , Transfer data"
|
|
group.long 0xC0++0x03
|
|
line.long 0x00 "TXRAM, Multi-buffer RAM Transmit Data Register 48"
|
|
bitfld.long 0x00 29.--31. " BUFMODE , Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip Single Transfer,Skip Overwrite,Skip ST-Overwrite,Continuous,Suspend Single Transfer,Suspend Overwrite,Suspend ST-Overwrite"
|
|
bitfld.long 0x00 28. " CSHOLD , Chip select hold mode" "Deactivated,Activated"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK , Lock two consecutive buffer words" "0,1"
|
|
bitfld.long 0x00 26. " WDEL , Enable the delay counter at the end of the current transaction" "Disable,Enable"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL , Data word format select" "Format 0,Format 1,Format 2,Format 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR , Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA , Transfer data"
|
|
group.long 0xC4++0x03
|
|
line.long 0x00 "TXRAM, Multi-buffer RAM Transmit Data Register 49"
|
|
bitfld.long 0x00 29.--31. " BUFMODE , Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip Single Transfer,Skip Overwrite,Skip ST-Overwrite,Continuous,Suspend Single Transfer,Suspend Overwrite,Suspend ST-Overwrite"
|
|
bitfld.long 0x00 28. " CSHOLD , Chip select hold mode" "Deactivated,Activated"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK , Lock two consecutive buffer words" "0,1"
|
|
bitfld.long 0x00 26. " WDEL , Enable the delay counter at the end of the current transaction" "Disable,Enable"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL , Data word format select" "Format 0,Format 1,Format 2,Format 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR , Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA , Transfer data"
|
|
group.long 0xC8++0x03
|
|
line.long 0x00 "TXRAM, Multi-buffer RAM Transmit Data Register 50"
|
|
bitfld.long 0x00 29.--31. " BUFMODE , Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip Single Transfer,Skip Overwrite,Skip ST-Overwrite,Continuous,Suspend Single Transfer,Suspend Overwrite,Suspend ST-Overwrite"
|
|
bitfld.long 0x00 28. " CSHOLD , Chip select hold mode" "Deactivated,Activated"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK , Lock two consecutive buffer words" "0,1"
|
|
bitfld.long 0x00 26. " WDEL , Enable the delay counter at the end of the current transaction" "Disable,Enable"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL , Data word format select" "Format 0,Format 1,Format 2,Format 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR , Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA , Transfer data"
|
|
group.long 0xCC++0x03
|
|
line.long 0x00 "TXRAM, Multi-buffer RAM Transmit Data Register 51"
|
|
bitfld.long 0x00 29.--31. " BUFMODE , Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip Single Transfer,Skip Overwrite,Skip ST-Overwrite,Continuous,Suspend Single Transfer,Suspend Overwrite,Suspend ST-Overwrite"
|
|
bitfld.long 0x00 28. " CSHOLD , Chip select hold mode" "Deactivated,Activated"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK , Lock two consecutive buffer words" "0,1"
|
|
bitfld.long 0x00 26. " WDEL , Enable the delay counter at the end of the current transaction" "Disable,Enable"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL , Data word format select" "Format 0,Format 1,Format 2,Format 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR , Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA , Transfer data"
|
|
group.long 0xD0++0x03
|
|
line.long 0x00 "TXRAM, Multi-buffer RAM Transmit Data Register 52"
|
|
bitfld.long 0x00 29.--31. " BUFMODE , Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip Single Transfer,Skip Overwrite,Skip ST-Overwrite,Continuous,Suspend Single Transfer,Suspend Overwrite,Suspend ST-Overwrite"
|
|
bitfld.long 0x00 28. " CSHOLD , Chip select hold mode" "Deactivated,Activated"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK , Lock two consecutive buffer words" "0,1"
|
|
bitfld.long 0x00 26. " WDEL , Enable the delay counter at the end of the current transaction" "Disable,Enable"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL , Data word format select" "Format 0,Format 1,Format 2,Format 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR , Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA , Transfer data"
|
|
group.long 0xD4++0x03
|
|
line.long 0x00 "TXRAM, Multi-buffer RAM Transmit Data Register 53"
|
|
bitfld.long 0x00 29.--31. " BUFMODE , Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip Single Transfer,Skip Overwrite,Skip ST-Overwrite,Continuous,Suspend Single Transfer,Suspend Overwrite,Suspend ST-Overwrite"
|
|
bitfld.long 0x00 28. " CSHOLD , Chip select hold mode" "Deactivated,Activated"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK , Lock two consecutive buffer words" "0,1"
|
|
bitfld.long 0x00 26. " WDEL , Enable the delay counter at the end of the current transaction" "Disable,Enable"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL , Data word format select" "Format 0,Format 1,Format 2,Format 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR , Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA , Transfer data"
|
|
group.long 0xD8++0x03
|
|
line.long 0x00 "TXRAM, Multi-buffer RAM Transmit Data Register 54"
|
|
bitfld.long 0x00 29.--31. " BUFMODE , Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip Single Transfer,Skip Overwrite,Skip ST-Overwrite,Continuous,Suspend Single Transfer,Suspend Overwrite,Suspend ST-Overwrite"
|
|
bitfld.long 0x00 28. " CSHOLD , Chip select hold mode" "Deactivated,Activated"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK , Lock two consecutive buffer words" "0,1"
|
|
bitfld.long 0x00 26. " WDEL , Enable the delay counter at the end of the current transaction" "Disable,Enable"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL , Data word format select" "Format 0,Format 1,Format 2,Format 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR , Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA , Transfer data"
|
|
group.long 0xDC++0x03
|
|
line.long 0x00 "TXRAM, Multi-buffer RAM Transmit Data Register 55"
|
|
bitfld.long 0x00 29.--31. " BUFMODE , Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip Single Transfer,Skip Overwrite,Skip ST-Overwrite,Continuous,Suspend Single Transfer,Suspend Overwrite,Suspend ST-Overwrite"
|
|
bitfld.long 0x00 28. " CSHOLD , Chip select hold mode" "Deactivated,Activated"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK , Lock two consecutive buffer words" "0,1"
|
|
bitfld.long 0x00 26. " WDEL , Enable the delay counter at the end of the current transaction" "Disable,Enable"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL , Data word format select" "Format 0,Format 1,Format 2,Format 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR , Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA , Transfer data"
|
|
group.long 0xE0++0x03
|
|
line.long 0x00 "TXRAM, Multi-buffer RAM Transmit Data Register 56"
|
|
bitfld.long 0x00 29.--31. " BUFMODE , Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip Single Transfer,Skip Overwrite,Skip ST-Overwrite,Continuous,Suspend Single Transfer,Suspend Overwrite,Suspend ST-Overwrite"
|
|
bitfld.long 0x00 28. " CSHOLD , Chip select hold mode" "Deactivated,Activated"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK , Lock two consecutive buffer words" "0,1"
|
|
bitfld.long 0x00 26. " WDEL , Enable the delay counter at the end of the current transaction" "Disable,Enable"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL , Data word format select" "Format 0,Format 1,Format 2,Format 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR , Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA , Transfer data"
|
|
group.long 0xE4++0x03
|
|
line.long 0x00 "TXRAM, Multi-buffer RAM Transmit Data Register 57"
|
|
bitfld.long 0x00 29.--31. " BUFMODE , Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip Single Transfer,Skip Overwrite,Skip ST-Overwrite,Continuous,Suspend Single Transfer,Suspend Overwrite,Suspend ST-Overwrite"
|
|
bitfld.long 0x00 28. " CSHOLD , Chip select hold mode" "Deactivated,Activated"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK , Lock two consecutive buffer words" "0,1"
|
|
bitfld.long 0x00 26. " WDEL , Enable the delay counter at the end of the current transaction" "Disable,Enable"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL , Data word format select" "Format 0,Format 1,Format 2,Format 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR , Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA , Transfer data"
|
|
group.long 0xE8++0x03
|
|
line.long 0x00 "TXRAM, Multi-buffer RAM Transmit Data Register 58"
|
|
bitfld.long 0x00 29.--31. " BUFMODE , Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip Single Transfer,Skip Overwrite,Skip ST-Overwrite,Continuous,Suspend Single Transfer,Suspend Overwrite,Suspend ST-Overwrite"
|
|
bitfld.long 0x00 28. " CSHOLD , Chip select hold mode" "Deactivated,Activated"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK , Lock two consecutive buffer words" "0,1"
|
|
bitfld.long 0x00 26. " WDEL , Enable the delay counter at the end of the current transaction" "Disable,Enable"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL , Data word format select" "Format 0,Format 1,Format 2,Format 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR , Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA , Transfer data"
|
|
group.long 0xEC++0x03
|
|
line.long 0x00 "TXRAM, Multi-buffer RAM Transmit Data Register 59"
|
|
bitfld.long 0x00 29.--31. " BUFMODE , Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip Single Transfer,Skip Overwrite,Skip ST-Overwrite,Continuous,Suspend Single Transfer,Suspend Overwrite,Suspend ST-Overwrite"
|
|
bitfld.long 0x00 28. " CSHOLD , Chip select hold mode" "Deactivated,Activated"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK , Lock two consecutive buffer words" "0,1"
|
|
bitfld.long 0x00 26. " WDEL , Enable the delay counter at the end of the current transaction" "Disable,Enable"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL , Data word format select" "Format 0,Format 1,Format 2,Format 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR , Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA , Transfer data"
|
|
group.long 0xF0++0x03
|
|
line.long 0x00 "TXRAM, Multi-buffer RAM Transmit Data Register 60"
|
|
bitfld.long 0x00 29.--31. " BUFMODE , Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip Single Transfer,Skip Overwrite,Skip ST-Overwrite,Continuous,Suspend Single Transfer,Suspend Overwrite,Suspend ST-Overwrite"
|
|
bitfld.long 0x00 28. " CSHOLD , Chip select hold mode" "Deactivated,Activated"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK , Lock two consecutive buffer words" "0,1"
|
|
bitfld.long 0x00 26. " WDEL , Enable the delay counter at the end of the current transaction" "Disable,Enable"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL , Data word format select" "Format 0,Format 1,Format 2,Format 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR , Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA , Transfer data"
|
|
group.long 0xF4++0x03
|
|
line.long 0x00 "TXRAM, Multi-buffer RAM Transmit Data Register 61"
|
|
bitfld.long 0x00 29.--31. " BUFMODE , Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip Single Transfer,Skip Overwrite,Skip ST-Overwrite,Continuous,Suspend Single Transfer,Suspend Overwrite,Suspend ST-Overwrite"
|
|
bitfld.long 0x00 28. " CSHOLD , Chip select hold mode" "Deactivated,Activated"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK , Lock two consecutive buffer words" "0,1"
|
|
bitfld.long 0x00 26. " WDEL , Enable the delay counter at the end of the current transaction" "Disable,Enable"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL , Data word format select" "Format 0,Format 1,Format 2,Format 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR , Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA , Transfer data"
|
|
group.long 0xF8++0x03
|
|
line.long 0x00 "TXRAM, Multi-buffer RAM Transmit Data Register 62"
|
|
bitfld.long 0x00 29.--31. " BUFMODE , Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip Single Transfer,Skip Overwrite,Skip ST-Overwrite,Continuous,Suspend Single Transfer,Suspend Overwrite,Suspend ST-Overwrite"
|
|
bitfld.long 0x00 28. " CSHOLD , Chip select hold mode" "Deactivated,Activated"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK , Lock two consecutive buffer words" "0,1"
|
|
bitfld.long 0x00 26. " WDEL , Enable the delay counter at the end of the current transaction" "Disable,Enable"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL , Data word format select" "Format 0,Format 1,Format 2,Format 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR , Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA , Transfer data"
|
|
group.long 0xFC++0x03
|
|
line.long 0x00 "TXRAM, Multi-buffer RAM Transmit Data Register 63"
|
|
bitfld.long 0x00 29.--31. " BUFMODE , Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip Single Transfer,Skip Overwrite,Skip ST-Overwrite,Continuous,Suspend Single Transfer,Suspend Overwrite,Suspend ST-Overwrite"
|
|
bitfld.long 0x00 28. " CSHOLD , Chip select hold mode" "Deactivated,Activated"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK , Lock two consecutive buffer words" "0,1"
|
|
bitfld.long 0x00 26. " WDEL , Enable the delay counter at the end of the current transaction" "Disable,Enable"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL , Data word format select" "Format 0,Format 1,Format 2,Format 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR , Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA , Transfer data"
|
|
group.long 0x100++0x03
|
|
line.long 0x00 "TXRAM, Multi-buffer RAM Transmit Data Register 64"
|
|
bitfld.long 0x00 29.--31. " BUFMODE , Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip Single Transfer,Skip Overwrite,Skip ST-Overwrite,Continuous,Suspend Single Transfer,Suspend Overwrite,Suspend ST-Overwrite"
|
|
bitfld.long 0x00 28. " CSHOLD , Chip select hold mode" "Deactivated,Activated"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK , Lock two consecutive buffer words" "0,1"
|
|
bitfld.long 0x00 26. " WDEL , Enable the delay counter at the end of the current transaction" "Disable,Enable"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL , Data word format select" "Format 0,Format 1,Format 2,Format 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR , Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA , Transfer data"
|
|
group.long 0x104++0x03
|
|
line.long 0x00 "TXRAM, Multi-buffer RAM Transmit Data Register 65"
|
|
bitfld.long 0x00 29.--31. " BUFMODE , Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip Single Transfer,Skip Overwrite,Skip ST-Overwrite,Continuous,Suspend Single Transfer,Suspend Overwrite,Suspend ST-Overwrite"
|
|
bitfld.long 0x00 28. " CSHOLD , Chip select hold mode" "Deactivated,Activated"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK , Lock two consecutive buffer words" "0,1"
|
|
bitfld.long 0x00 26. " WDEL , Enable the delay counter at the end of the current transaction" "Disable,Enable"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL , Data word format select" "Format 0,Format 1,Format 2,Format 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR , Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA , Transfer data"
|
|
group.long 0x108++0x03
|
|
line.long 0x00 "TXRAM, Multi-buffer RAM Transmit Data Register 66"
|
|
bitfld.long 0x00 29.--31. " BUFMODE , Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip Single Transfer,Skip Overwrite,Skip ST-Overwrite,Continuous,Suspend Single Transfer,Suspend Overwrite,Suspend ST-Overwrite"
|
|
bitfld.long 0x00 28. " CSHOLD , Chip select hold mode" "Deactivated,Activated"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK , Lock two consecutive buffer words" "0,1"
|
|
bitfld.long 0x00 26. " WDEL , Enable the delay counter at the end of the current transaction" "Disable,Enable"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL , Data word format select" "Format 0,Format 1,Format 2,Format 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR , Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA , Transfer data"
|
|
group.long 0x10C++0x03
|
|
line.long 0x00 "TXRAM, Multi-buffer RAM Transmit Data Register 67"
|
|
bitfld.long 0x00 29.--31. " BUFMODE , Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip Single Transfer,Skip Overwrite,Skip ST-Overwrite,Continuous,Suspend Single Transfer,Suspend Overwrite,Suspend ST-Overwrite"
|
|
bitfld.long 0x00 28. " CSHOLD , Chip select hold mode" "Deactivated,Activated"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK , Lock two consecutive buffer words" "0,1"
|
|
bitfld.long 0x00 26. " WDEL , Enable the delay counter at the end of the current transaction" "Disable,Enable"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL , Data word format select" "Format 0,Format 1,Format 2,Format 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR , Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA , Transfer data"
|
|
group.long 0x110++0x03
|
|
line.long 0x00 "TXRAM, Multi-buffer RAM Transmit Data Register 68"
|
|
bitfld.long 0x00 29.--31. " BUFMODE , Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip Single Transfer,Skip Overwrite,Skip ST-Overwrite,Continuous,Suspend Single Transfer,Suspend Overwrite,Suspend ST-Overwrite"
|
|
bitfld.long 0x00 28. " CSHOLD , Chip select hold mode" "Deactivated,Activated"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK , Lock two consecutive buffer words" "0,1"
|
|
bitfld.long 0x00 26. " WDEL , Enable the delay counter at the end of the current transaction" "Disable,Enable"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL , Data word format select" "Format 0,Format 1,Format 2,Format 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR , Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA , Transfer data"
|
|
group.long 0x114++0x03
|
|
line.long 0x00 "TXRAM, Multi-buffer RAM Transmit Data Register 69"
|
|
bitfld.long 0x00 29.--31. " BUFMODE , Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip Single Transfer,Skip Overwrite,Skip ST-Overwrite,Continuous,Suspend Single Transfer,Suspend Overwrite,Suspend ST-Overwrite"
|
|
bitfld.long 0x00 28. " CSHOLD , Chip select hold mode" "Deactivated,Activated"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK , Lock two consecutive buffer words" "0,1"
|
|
bitfld.long 0x00 26. " WDEL , Enable the delay counter at the end of the current transaction" "Disable,Enable"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL , Data word format select" "Format 0,Format 1,Format 2,Format 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR , Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA , Transfer data"
|
|
group.long 0x118++0x03
|
|
line.long 0x00 "TXRAM, Multi-buffer RAM Transmit Data Register 70"
|
|
bitfld.long 0x00 29.--31. " BUFMODE , Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip Single Transfer,Skip Overwrite,Skip ST-Overwrite,Continuous,Suspend Single Transfer,Suspend Overwrite,Suspend ST-Overwrite"
|
|
bitfld.long 0x00 28. " CSHOLD , Chip select hold mode" "Deactivated,Activated"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK , Lock two consecutive buffer words" "0,1"
|
|
bitfld.long 0x00 26. " WDEL , Enable the delay counter at the end of the current transaction" "Disable,Enable"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL , Data word format select" "Format 0,Format 1,Format 2,Format 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR , Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA , Transfer data"
|
|
group.long 0x11C++0x03
|
|
line.long 0x00 "TXRAM, Multi-buffer RAM Transmit Data Register 71"
|
|
bitfld.long 0x00 29.--31. " BUFMODE , Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip Single Transfer,Skip Overwrite,Skip ST-Overwrite,Continuous,Suspend Single Transfer,Suspend Overwrite,Suspend ST-Overwrite"
|
|
bitfld.long 0x00 28. " CSHOLD , Chip select hold mode" "Deactivated,Activated"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK , Lock two consecutive buffer words" "0,1"
|
|
bitfld.long 0x00 26. " WDEL , Enable the delay counter at the end of the current transaction" "Disable,Enable"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL , Data word format select" "Format 0,Format 1,Format 2,Format 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR , Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA , Transfer data"
|
|
group.long 0x120++0x03
|
|
line.long 0x00 "TXRAM, Multi-buffer RAM Transmit Data Register 72"
|
|
bitfld.long 0x00 29.--31. " BUFMODE , Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip Single Transfer,Skip Overwrite,Skip ST-Overwrite,Continuous,Suspend Single Transfer,Suspend Overwrite,Suspend ST-Overwrite"
|
|
bitfld.long 0x00 28. " CSHOLD , Chip select hold mode" "Deactivated,Activated"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK , Lock two consecutive buffer words" "0,1"
|
|
bitfld.long 0x00 26. " WDEL , Enable the delay counter at the end of the current transaction" "Disable,Enable"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL , Data word format select" "Format 0,Format 1,Format 2,Format 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR , Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA , Transfer data"
|
|
group.long 0x124++0x03
|
|
line.long 0x00 "TXRAM, Multi-buffer RAM Transmit Data Register 73"
|
|
bitfld.long 0x00 29.--31. " BUFMODE , Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip Single Transfer,Skip Overwrite,Skip ST-Overwrite,Continuous,Suspend Single Transfer,Suspend Overwrite,Suspend ST-Overwrite"
|
|
bitfld.long 0x00 28. " CSHOLD , Chip select hold mode" "Deactivated,Activated"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK , Lock two consecutive buffer words" "0,1"
|
|
bitfld.long 0x00 26. " WDEL , Enable the delay counter at the end of the current transaction" "Disable,Enable"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL , Data word format select" "Format 0,Format 1,Format 2,Format 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR , Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA , Transfer data"
|
|
group.long 0x128++0x03
|
|
line.long 0x00 "TXRAM, Multi-buffer RAM Transmit Data Register 74"
|
|
bitfld.long 0x00 29.--31. " BUFMODE , Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip Single Transfer,Skip Overwrite,Skip ST-Overwrite,Continuous,Suspend Single Transfer,Suspend Overwrite,Suspend ST-Overwrite"
|
|
bitfld.long 0x00 28. " CSHOLD , Chip select hold mode" "Deactivated,Activated"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK , Lock two consecutive buffer words" "0,1"
|
|
bitfld.long 0x00 26. " WDEL , Enable the delay counter at the end of the current transaction" "Disable,Enable"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL , Data word format select" "Format 0,Format 1,Format 2,Format 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR , Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA , Transfer data"
|
|
group.long 0x12C++0x03
|
|
line.long 0x00 "TXRAM, Multi-buffer RAM Transmit Data Register 75"
|
|
bitfld.long 0x00 29.--31. " BUFMODE , Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip Single Transfer,Skip Overwrite,Skip ST-Overwrite,Continuous,Suspend Single Transfer,Suspend Overwrite,Suspend ST-Overwrite"
|
|
bitfld.long 0x00 28. " CSHOLD , Chip select hold mode" "Deactivated,Activated"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK , Lock two consecutive buffer words" "0,1"
|
|
bitfld.long 0x00 26. " WDEL , Enable the delay counter at the end of the current transaction" "Disable,Enable"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL , Data word format select" "Format 0,Format 1,Format 2,Format 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR , Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA , Transfer data"
|
|
group.long 0x130++0x03
|
|
line.long 0x00 "TXRAM, Multi-buffer RAM Transmit Data Register 76"
|
|
bitfld.long 0x00 29.--31. " BUFMODE , Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip Single Transfer,Skip Overwrite,Skip ST-Overwrite,Continuous,Suspend Single Transfer,Suspend Overwrite,Suspend ST-Overwrite"
|
|
bitfld.long 0x00 28. " CSHOLD , Chip select hold mode" "Deactivated,Activated"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK , Lock two consecutive buffer words" "0,1"
|
|
bitfld.long 0x00 26. " WDEL , Enable the delay counter at the end of the current transaction" "Disable,Enable"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL , Data word format select" "Format 0,Format 1,Format 2,Format 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR , Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA , Transfer data"
|
|
group.long 0x134++0x03
|
|
line.long 0x00 "TXRAM, Multi-buffer RAM Transmit Data Register 77"
|
|
bitfld.long 0x00 29.--31. " BUFMODE , Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip Single Transfer,Skip Overwrite,Skip ST-Overwrite,Continuous,Suspend Single Transfer,Suspend Overwrite,Suspend ST-Overwrite"
|
|
bitfld.long 0x00 28. " CSHOLD , Chip select hold mode" "Deactivated,Activated"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK , Lock two consecutive buffer words" "0,1"
|
|
bitfld.long 0x00 26. " WDEL , Enable the delay counter at the end of the current transaction" "Disable,Enable"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL , Data word format select" "Format 0,Format 1,Format 2,Format 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR , Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA , Transfer data"
|
|
group.long 0x138++0x03
|
|
line.long 0x00 "TXRAM, Multi-buffer RAM Transmit Data Register 78"
|
|
bitfld.long 0x00 29.--31. " BUFMODE , Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip Single Transfer,Skip Overwrite,Skip ST-Overwrite,Continuous,Suspend Single Transfer,Suspend Overwrite,Suspend ST-Overwrite"
|
|
bitfld.long 0x00 28. " CSHOLD , Chip select hold mode" "Deactivated,Activated"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK , Lock two consecutive buffer words" "0,1"
|
|
bitfld.long 0x00 26. " WDEL , Enable the delay counter at the end of the current transaction" "Disable,Enable"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL , Data word format select" "Format 0,Format 1,Format 2,Format 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR , Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA , Transfer data"
|
|
group.long 0x13C++0x03
|
|
line.long 0x00 "TXRAM, Multi-buffer RAM Transmit Data Register 79"
|
|
bitfld.long 0x00 29.--31. " BUFMODE , Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip Single Transfer,Skip Overwrite,Skip ST-Overwrite,Continuous,Suspend Single Transfer,Suspend Overwrite,Suspend ST-Overwrite"
|
|
bitfld.long 0x00 28. " CSHOLD , Chip select hold mode" "Deactivated,Activated"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK , Lock two consecutive buffer words" "0,1"
|
|
bitfld.long 0x00 26. " WDEL , Enable the delay counter at the end of the current transaction" "Disable,Enable"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL , Data word format select" "Format 0,Format 1,Format 2,Format 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR , Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA , Transfer data"
|
|
rgroup.long (0x0+0x200)++0x03
|
|
line.long 0x00 "RXRAM, Multi-buffer RAM Receive Buffer Register 0"
|
|
bitfld.long 0x00 31. " RXEMPTY , Receive data buffer empty" "Not empty,Empty"
|
|
bitfld.long 0x00 30. " RXOVR , Receive data buffer overrun" "No overrun,Overrun"
|
|
newline
|
|
bitfld.long 0x00 29. " TXFULL , Transmit data buffer full" "Not full,Full"
|
|
bitfld.long 0x00 28. " BITERR , Bit error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 27. " DESYNC , Desynchronization of slave device" "No,Yes"
|
|
bitfld.long 0x00 26. " PARITYERR , Parity error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 25. " TIMEOUT , Time-out because of non-activation of ENA pin" "No timeout,Timeout"
|
|
bitfld.long 0x00 24. " DLENERR , Data length error flag" "No,Yes"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " LCSNR , Last chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " RXDATA , SPI receive data"
|
|
rgroup.long (0x4+0x200)++0x03
|
|
line.long 0x00 "RXRAM, Multi-buffer RAM Receive Buffer Register 1"
|
|
bitfld.long 0x00 31. " RXEMPTY , Receive data buffer empty" "Not empty,Empty"
|
|
bitfld.long 0x00 30. " RXOVR , Receive data buffer overrun" "No overrun,Overrun"
|
|
newline
|
|
bitfld.long 0x00 29. " TXFULL , Transmit data buffer full" "Not full,Full"
|
|
bitfld.long 0x00 28. " BITERR , Bit error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 27. " DESYNC , Desynchronization of slave device" "No,Yes"
|
|
bitfld.long 0x00 26. " PARITYERR , Parity error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 25. " TIMEOUT , Time-out because of non-activation of ENA pin" "No timeout,Timeout"
|
|
bitfld.long 0x00 24. " DLENERR , Data length error flag" "No,Yes"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " LCSNR , Last chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " RXDATA , SPI receive data"
|
|
rgroup.long (0x8+0x200)++0x03
|
|
line.long 0x00 "RXRAM, Multi-buffer RAM Receive Buffer Register 2"
|
|
bitfld.long 0x00 31. " RXEMPTY , Receive data buffer empty" "Not empty,Empty"
|
|
bitfld.long 0x00 30. " RXOVR , Receive data buffer overrun" "No overrun,Overrun"
|
|
newline
|
|
bitfld.long 0x00 29. " TXFULL , Transmit data buffer full" "Not full,Full"
|
|
bitfld.long 0x00 28. " BITERR , Bit error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 27. " DESYNC , Desynchronization of slave device" "No,Yes"
|
|
bitfld.long 0x00 26. " PARITYERR , Parity error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 25. " TIMEOUT , Time-out because of non-activation of ENA pin" "No timeout,Timeout"
|
|
bitfld.long 0x00 24. " DLENERR , Data length error flag" "No,Yes"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " LCSNR , Last chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " RXDATA , SPI receive data"
|
|
rgroup.long (0xC+0x200)++0x03
|
|
line.long 0x00 "RXRAM, Multi-buffer RAM Receive Buffer Register 3"
|
|
bitfld.long 0x00 31. " RXEMPTY , Receive data buffer empty" "Not empty,Empty"
|
|
bitfld.long 0x00 30. " RXOVR , Receive data buffer overrun" "No overrun,Overrun"
|
|
newline
|
|
bitfld.long 0x00 29. " TXFULL , Transmit data buffer full" "Not full,Full"
|
|
bitfld.long 0x00 28. " BITERR , Bit error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 27. " DESYNC , Desynchronization of slave device" "No,Yes"
|
|
bitfld.long 0x00 26. " PARITYERR , Parity error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 25. " TIMEOUT , Time-out because of non-activation of ENA pin" "No timeout,Timeout"
|
|
bitfld.long 0x00 24. " DLENERR , Data length error flag" "No,Yes"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " LCSNR , Last chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " RXDATA , SPI receive data"
|
|
rgroup.long (0x10+0x200)++0x03
|
|
line.long 0x00 "RXRAM, Multi-buffer RAM Receive Buffer Register 4"
|
|
bitfld.long 0x00 31. " RXEMPTY , Receive data buffer empty" "Not empty,Empty"
|
|
bitfld.long 0x00 30. " RXOVR , Receive data buffer overrun" "No overrun,Overrun"
|
|
newline
|
|
bitfld.long 0x00 29. " TXFULL , Transmit data buffer full" "Not full,Full"
|
|
bitfld.long 0x00 28. " BITERR , Bit error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 27. " DESYNC , Desynchronization of slave device" "No,Yes"
|
|
bitfld.long 0x00 26. " PARITYERR , Parity error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 25. " TIMEOUT , Time-out because of non-activation of ENA pin" "No timeout,Timeout"
|
|
bitfld.long 0x00 24. " DLENERR , Data length error flag" "No,Yes"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " LCSNR , Last chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " RXDATA , SPI receive data"
|
|
rgroup.long (0x14+0x200)++0x03
|
|
line.long 0x00 "RXRAM, Multi-buffer RAM Receive Buffer Register 5"
|
|
bitfld.long 0x00 31. " RXEMPTY , Receive data buffer empty" "Not empty,Empty"
|
|
bitfld.long 0x00 30. " RXOVR , Receive data buffer overrun" "No overrun,Overrun"
|
|
newline
|
|
bitfld.long 0x00 29. " TXFULL , Transmit data buffer full" "Not full,Full"
|
|
bitfld.long 0x00 28. " BITERR , Bit error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 27. " DESYNC , Desynchronization of slave device" "No,Yes"
|
|
bitfld.long 0x00 26. " PARITYERR , Parity error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 25. " TIMEOUT , Time-out because of non-activation of ENA pin" "No timeout,Timeout"
|
|
bitfld.long 0x00 24. " DLENERR , Data length error flag" "No,Yes"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " LCSNR , Last chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " RXDATA , SPI receive data"
|
|
rgroup.long (0x18+0x200)++0x03
|
|
line.long 0x00 "RXRAM, Multi-buffer RAM Receive Buffer Register 6"
|
|
bitfld.long 0x00 31. " RXEMPTY , Receive data buffer empty" "Not empty,Empty"
|
|
bitfld.long 0x00 30. " RXOVR , Receive data buffer overrun" "No overrun,Overrun"
|
|
newline
|
|
bitfld.long 0x00 29. " TXFULL , Transmit data buffer full" "Not full,Full"
|
|
bitfld.long 0x00 28. " BITERR , Bit error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 27. " DESYNC , Desynchronization of slave device" "No,Yes"
|
|
bitfld.long 0x00 26. " PARITYERR , Parity error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 25. " TIMEOUT , Time-out because of non-activation of ENA pin" "No timeout,Timeout"
|
|
bitfld.long 0x00 24. " DLENERR , Data length error flag" "No,Yes"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " LCSNR , Last chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " RXDATA , SPI receive data"
|
|
rgroup.long (0x1C+0x200)++0x03
|
|
line.long 0x00 "RXRAM, Multi-buffer RAM Receive Buffer Register 7"
|
|
bitfld.long 0x00 31. " RXEMPTY , Receive data buffer empty" "Not empty,Empty"
|
|
bitfld.long 0x00 30. " RXOVR , Receive data buffer overrun" "No overrun,Overrun"
|
|
newline
|
|
bitfld.long 0x00 29. " TXFULL , Transmit data buffer full" "Not full,Full"
|
|
bitfld.long 0x00 28. " BITERR , Bit error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 27. " DESYNC , Desynchronization of slave device" "No,Yes"
|
|
bitfld.long 0x00 26. " PARITYERR , Parity error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 25. " TIMEOUT , Time-out because of non-activation of ENA pin" "No timeout,Timeout"
|
|
bitfld.long 0x00 24. " DLENERR , Data length error flag" "No,Yes"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " LCSNR , Last chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " RXDATA , SPI receive data"
|
|
rgroup.long (0x20+0x200)++0x03
|
|
line.long 0x00 "RXRAM, Multi-buffer RAM Receive Buffer Register 8"
|
|
bitfld.long 0x00 31. " RXEMPTY , Receive data buffer empty" "Not empty,Empty"
|
|
bitfld.long 0x00 30. " RXOVR , Receive data buffer overrun" "No overrun,Overrun"
|
|
newline
|
|
bitfld.long 0x00 29. " TXFULL , Transmit data buffer full" "Not full,Full"
|
|
bitfld.long 0x00 28. " BITERR , Bit error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 27. " DESYNC , Desynchronization of slave device" "No,Yes"
|
|
bitfld.long 0x00 26. " PARITYERR , Parity error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 25. " TIMEOUT , Time-out because of non-activation of ENA pin" "No timeout,Timeout"
|
|
bitfld.long 0x00 24. " DLENERR , Data length error flag" "No,Yes"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " LCSNR , Last chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " RXDATA , SPI receive data"
|
|
rgroup.long (0x24+0x200)++0x03
|
|
line.long 0x00 "RXRAM, Multi-buffer RAM Receive Buffer Register 9"
|
|
bitfld.long 0x00 31. " RXEMPTY , Receive data buffer empty" "Not empty,Empty"
|
|
bitfld.long 0x00 30. " RXOVR , Receive data buffer overrun" "No overrun,Overrun"
|
|
newline
|
|
bitfld.long 0x00 29. " TXFULL , Transmit data buffer full" "Not full,Full"
|
|
bitfld.long 0x00 28. " BITERR , Bit error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 27. " DESYNC , Desynchronization of slave device" "No,Yes"
|
|
bitfld.long 0x00 26. " PARITYERR , Parity error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 25. " TIMEOUT , Time-out because of non-activation of ENA pin" "No timeout,Timeout"
|
|
bitfld.long 0x00 24. " DLENERR , Data length error flag" "No,Yes"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " LCSNR , Last chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " RXDATA , SPI receive data"
|
|
rgroup.long (0x28+0x200)++0x03
|
|
line.long 0x00 "RXRAM, Multi-buffer RAM Receive Buffer Register 10"
|
|
bitfld.long 0x00 31. " RXEMPTY , Receive data buffer empty" "Not empty,Empty"
|
|
bitfld.long 0x00 30. " RXOVR , Receive data buffer overrun" "No overrun,Overrun"
|
|
newline
|
|
bitfld.long 0x00 29. " TXFULL , Transmit data buffer full" "Not full,Full"
|
|
bitfld.long 0x00 28. " BITERR , Bit error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 27. " DESYNC , Desynchronization of slave device" "No,Yes"
|
|
bitfld.long 0x00 26. " PARITYERR , Parity error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 25. " TIMEOUT , Time-out because of non-activation of ENA pin" "No timeout,Timeout"
|
|
bitfld.long 0x00 24. " DLENERR , Data length error flag" "No,Yes"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " LCSNR , Last chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " RXDATA , SPI receive data"
|
|
rgroup.long (0x2C+0x200)++0x03
|
|
line.long 0x00 "RXRAM, Multi-buffer RAM Receive Buffer Register 11"
|
|
bitfld.long 0x00 31. " RXEMPTY , Receive data buffer empty" "Not empty,Empty"
|
|
bitfld.long 0x00 30. " RXOVR , Receive data buffer overrun" "No overrun,Overrun"
|
|
newline
|
|
bitfld.long 0x00 29. " TXFULL , Transmit data buffer full" "Not full,Full"
|
|
bitfld.long 0x00 28. " BITERR , Bit error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 27. " DESYNC , Desynchronization of slave device" "No,Yes"
|
|
bitfld.long 0x00 26. " PARITYERR , Parity error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 25. " TIMEOUT , Time-out because of non-activation of ENA pin" "No timeout,Timeout"
|
|
bitfld.long 0x00 24. " DLENERR , Data length error flag" "No,Yes"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " LCSNR , Last chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " RXDATA , SPI receive data"
|
|
rgroup.long (0x30+0x200)++0x03
|
|
line.long 0x00 "RXRAM, Multi-buffer RAM Receive Buffer Register 12"
|
|
bitfld.long 0x00 31. " RXEMPTY , Receive data buffer empty" "Not empty,Empty"
|
|
bitfld.long 0x00 30. " RXOVR , Receive data buffer overrun" "No overrun,Overrun"
|
|
newline
|
|
bitfld.long 0x00 29. " TXFULL , Transmit data buffer full" "Not full,Full"
|
|
bitfld.long 0x00 28. " BITERR , Bit error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 27. " DESYNC , Desynchronization of slave device" "No,Yes"
|
|
bitfld.long 0x00 26. " PARITYERR , Parity error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 25. " TIMEOUT , Time-out because of non-activation of ENA pin" "No timeout,Timeout"
|
|
bitfld.long 0x00 24. " DLENERR , Data length error flag" "No,Yes"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " LCSNR , Last chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " RXDATA , SPI receive data"
|
|
rgroup.long (0x34+0x200)++0x03
|
|
line.long 0x00 "RXRAM, Multi-buffer RAM Receive Buffer Register 13"
|
|
bitfld.long 0x00 31. " RXEMPTY , Receive data buffer empty" "Not empty,Empty"
|
|
bitfld.long 0x00 30. " RXOVR , Receive data buffer overrun" "No overrun,Overrun"
|
|
newline
|
|
bitfld.long 0x00 29. " TXFULL , Transmit data buffer full" "Not full,Full"
|
|
bitfld.long 0x00 28. " BITERR , Bit error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 27. " DESYNC , Desynchronization of slave device" "No,Yes"
|
|
bitfld.long 0x00 26. " PARITYERR , Parity error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 25. " TIMEOUT , Time-out because of non-activation of ENA pin" "No timeout,Timeout"
|
|
bitfld.long 0x00 24. " DLENERR , Data length error flag" "No,Yes"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " LCSNR , Last chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " RXDATA , SPI receive data"
|
|
rgroup.long (0x38+0x200)++0x03
|
|
line.long 0x00 "RXRAM, Multi-buffer RAM Receive Buffer Register 14"
|
|
bitfld.long 0x00 31. " RXEMPTY , Receive data buffer empty" "Not empty,Empty"
|
|
bitfld.long 0x00 30. " RXOVR , Receive data buffer overrun" "No overrun,Overrun"
|
|
newline
|
|
bitfld.long 0x00 29. " TXFULL , Transmit data buffer full" "Not full,Full"
|
|
bitfld.long 0x00 28. " BITERR , Bit error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 27. " DESYNC , Desynchronization of slave device" "No,Yes"
|
|
bitfld.long 0x00 26. " PARITYERR , Parity error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 25. " TIMEOUT , Time-out because of non-activation of ENA pin" "No timeout,Timeout"
|
|
bitfld.long 0x00 24. " DLENERR , Data length error flag" "No,Yes"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " LCSNR , Last chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " RXDATA , SPI receive data"
|
|
rgroup.long (0x3C+0x200)++0x03
|
|
line.long 0x00 "RXRAM, Multi-buffer RAM Receive Buffer Register 15"
|
|
bitfld.long 0x00 31. " RXEMPTY , Receive data buffer empty" "Not empty,Empty"
|
|
bitfld.long 0x00 30. " RXOVR , Receive data buffer overrun" "No overrun,Overrun"
|
|
newline
|
|
bitfld.long 0x00 29. " TXFULL , Transmit data buffer full" "Not full,Full"
|
|
bitfld.long 0x00 28. " BITERR , Bit error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 27. " DESYNC , Desynchronization of slave device" "No,Yes"
|
|
bitfld.long 0x00 26. " PARITYERR , Parity error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 25. " TIMEOUT , Time-out because of non-activation of ENA pin" "No timeout,Timeout"
|
|
bitfld.long 0x00 24. " DLENERR , Data length error flag" "No,Yes"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " LCSNR , Last chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " RXDATA , SPI receive data"
|
|
rgroup.long (0x40+0x200)++0x03
|
|
line.long 0x00 "RXRAM, Multi-buffer RAM Receive Buffer Register 16"
|
|
bitfld.long 0x00 31. " RXEMPTY , Receive data buffer empty" "Not empty,Empty"
|
|
bitfld.long 0x00 30. " RXOVR , Receive data buffer overrun" "No overrun,Overrun"
|
|
newline
|
|
bitfld.long 0x00 29. " TXFULL , Transmit data buffer full" "Not full,Full"
|
|
bitfld.long 0x00 28. " BITERR , Bit error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 27. " DESYNC , Desynchronization of slave device" "No,Yes"
|
|
bitfld.long 0x00 26. " PARITYERR , Parity error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 25. " TIMEOUT , Time-out because of non-activation of ENA pin" "No timeout,Timeout"
|
|
bitfld.long 0x00 24. " DLENERR , Data length error flag" "No,Yes"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " LCSNR , Last chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " RXDATA , SPI receive data"
|
|
rgroup.long (0x44+0x200)++0x03
|
|
line.long 0x00 "RXRAM, Multi-buffer RAM Receive Buffer Register 17"
|
|
bitfld.long 0x00 31. " RXEMPTY , Receive data buffer empty" "Not empty,Empty"
|
|
bitfld.long 0x00 30. " RXOVR , Receive data buffer overrun" "No overrun,Overrun"
|
|
newline
|
|
bitfld.long 0x00 29. " TXFULL , Transmit data buffer full" "Not full,Full"
|
|
bitfld.long 0x00 28. " BITERR , Bit error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 27. " DESYNC , Desynchronization of slave device" "No,Yes"
|
|
bitfld.long 0x00 26. " PARITYERR , Parity error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 25. " TIMEOUT , Time-out because of non-activation of ENA pin" "No timeout,Timeout"
|
|
bitfld.long 0x00 24. " DLENERR , Data length error flag" "No,Yes"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " LCSNR , Last chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " RXDATA , SPI receive data"
|
|
rgroup.long (0x48+0x200)++0x03
|
|
line.long 0x00 "RXRAM, Multi-buffer RAM Receive Buffer Register 18"
|
|
bitfld.long 0x00 31. " RXEMPTY , Receive data buffer empty" "Not empty,Empty"
|
|
bitfld.long 0x00 30. " RXOVR , Receive data buffer overrun" "No overrun,Overrun"
|
|
newline
|
|
bitfld.long 0x00 29. " TXFULL , Transmit data buffer full" "Not full,Full"
|
|
bitfld.long 0x00 28. " BITERR , Bit error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 27. " DESYNC , Desynchronization of slave device" "No,Yes"
|
|
bitfld.long 0x00 26. " PARITYERR , Parity error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 25. " TIMEOUT , Time-out because of non-activation of ENA pin" "No timeout,Timeout"
|
|
bitfld.long 0x00 24. " DLENERR , Data length error flag" "No,Yes"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " LCSNR , Last chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " RXDATA , SPI receive data"
|
|
rgroup.long (0x4C+0x200)++0x03
|
|
line.long 0x00 "RXRAM, Multi-buffer RAM Receive Buffer Register 19"
|
|
bitfld.long 0x00 31. " RXEMPTY , Receive data buffer empty" "Not empty,Empty"
|
|
bitfld.long 0x00 30. " RXOVR , Receive data buffer overrun" "No overrun,Overrun"
|
|
newline
|
|
bitfld.long 0x00 29. " TXFULL , Transmit data buffer full" "Not full,Full"
|
|
bitfld.long 0x00 28. " BITERR , Bit error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 27. " DESYNC , Desynchronization of slave device" "No,Yes"
|
|
bitfld.long 0x00 26. " PARITYERR , Parity error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 25. " TIMEOUT , Time-out because of non-activation of ENA pin" "No timeout,Timeout"
|
|
bitfld.long 0x00 24. " DLENERR , Data length error flag" "No,Yes"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " LCSNR , Last chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " RXDATA , SPI receive data"
|
|
rgroup.long (0x50+0x200)++0x03
|
|
line.long 0x00 "RXRAM, Multi-buffer RAM Receive Buffer Register 20"
|
|
bitfld.long 0x00 31. " RXEMPTY , Receive data buffer empty" "Not empty,Empty"
|
|
bitfld.long 0x00 30. " RXOVR , Receive data buffer overrun" "No overrun,Overrun"
|
|
newline
|
|
bitfld.long 0x00 29. " TXFULL , Transmit data buffer full" "Not full,Full"
|
|
bitfld.long 0x00 28. " BITERR , Bit error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 27. " DESYNC , Desynchronization of slave device" "No,Yes"
|
|
bitfld.long 0x00 26. " PARITYERR , Parity error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 25. " TIMEOUT , Time-out because of non-activation of ENA pin" "No timeout,Timeout"
|
|
bitfld.long 0x00 24. " DLENERR , Data length error flag" "No,Yes"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " LCSNR , Last chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " RXDATA , SPI receive data"
|
|
rgroup.long (0x54+0x200)++0x03
|
|
line.long 0x00 "RXRAM, Multi-buffer RAM Receive Buffer Register 21"
|
|
bitfld.long 0x00 31. " RXEMPTY , Receive data buffer empty" "Not empty,Empty"
|
|
bitfld.long 0x00 30. " RXOVR , Receive data buffer overrun" "No overrun,Overrun"
|
|
newline
|
|
bitfld.long 0x00 29. " TXFULL , Transmit data buffer full" "Not full,Full"
|
|
bitfld.long 0x00 28. " BITERR , Bit error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 27. " DESYNC , Desynchronization of slave device" "No,Yes"
|
|
bitfld.long 0x00 26. " PARITYERR , Parity error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 25. " TIMEOUT , Time-out because of non-activation of ENA pin" "No timeout,Timeout"
|
|
bitfld.long 0x00 24. " DLENERR , Data length error flag" "No,Yes"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " LCSNR , Last chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " RXDATA , SPI receive data"
|
|
rgroup.long (0x58+0x200)++0x03
|
|
line.long 0x00 "RXRAM, Multi-buffer RAM Receive Buffer Register 22"
|
|
bitfld.long 0x00 31. " RXEMPTY , Receive data buffer empty" "Not empty,Empty"
|
|
bitfld.long 0x00 30. " RXOVR , Receive data buffer overrun" "No overrun,Overrun"
|
|
newline
|
|
bitfld.long 0x00 29. " TXFULL , Transmit data buffer full" "Not full,Full"
|
|
bitfld.long 0x00 28. " BITERR , Bit error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 27. " DESYNC , Desynchronization of slave device" "No,Yes"
|
|
bitfld.long 0x00 26. " PARITYERR , Parity error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 25. " TIMEOUT , Time-out because of non-activation of ENA pin" "No timeout,Timeout"
|
|
bitfld.long 0x00 24. " DLENERR , Data length error flag" "No,Yes"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " LCSNR , Last chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " RXDATA , SPI receive data"
|
|
rgroup.long (0x5C+0x200)++0x03
|
|
line.long 0x00 "RXRAM, Multi-buffer RAM Receive Buffer Register 23"
|
|
bitfld.long 0x00 31. " RXEMPTY , Receive data buffer empty" "Not empty,Empty"
|
|
bitfld.long 0x00 30. " RXOVR , Receive data buffer overrun" "No overrun,Overrun"
|
|
newline
|
|
bitfld.long 0x00 29. " TXFULL , Transmit data buffer full" "Not full,Full"
|
|
bitfld.long 0x00 28. " BITERR , Bit error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 27. " DESYNC , Desynchronization of slave device" "No,Yes"
|
|
bitfld.long 0x00 26. " PARITYERR , Parity error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 25. " TIMEOUT , Time-out because of non-activation of ENA pin" "No timeout,Timeout"
|
|
bitfld.long 0x00 24. " DLENERR , Data length error flag" "No,Yes"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " LCSNR , Last chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " RXDATA , SPI receive data"
|
|
rgroup.long (0x60+0x200)++0x03
|
|
line.long 0x00 "RXRAM, Multi-buffer RAM Receive Buffer Register 24"
|
|
bitfld.long 0x00 31. " RXEMPTY , Receive data buffer empty" "Not empty,Empty"
|
|
bitfld.long 0x00 30. " RXOVR , Receive data buffer overrun" "No overrun,Overrun"
|
|
newline
|
|
bitfld.long 0x00 29. " TXFULL , Transmit data buffer full" "Not full,Full"
|
|
bitfld.long 0x00 28. " BITERR , Bit error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 27. " DESYNC , Desynchronization of slave device" "No,Yes"
|
|
bitfld.long 0x00 26. " PARITYERR , Parity error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 25. " TIMEOUT , Time-out because of non-activation of ENA pin" "No timeout,Timeout"
|
|
bitfld.long 0x00 24. " DLENERR , Data length error flag" "No,Yes"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " LCSNR , Last chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " RXDATA , SPI receive data"
|
|
rgroup.long (0x64+0x200)++0x03
|
|
line.long 0x00 "RXRAM, Multi-buffer RAM Receive Buffer Register 25"
|
|
bitfld.long 0x00 31. " RXEMPTY , Receive data buffer empty" "Not empty,Empty"
|
|
bitfld.long 0x00 30. " RXOVR , Receive data buffer overrun" "No overrun,Overrun"
|
|
newline
|
|
bitfld.long 0x00 29. " TXFULL , Transmit data buffer full" "Not full,Full"
|
|
bitfld.long 0x00 28. " BITERR , Bit error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 27. " DESYNC , Desynchronization of slave device" "No,Yes"
|
|
bitfld.long 0x00 26. " PARITYERR , Parity error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 25. " TIMEOUT , Time-out because of non-activation of ENA pin" "No timeout,Timeout"
|
|
bitfld.long 0x00 24. " DLENERR , Data length error flag" "No,Yes"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " LCSNR , Last chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " RXDATA , SPI receive data"
|
|
rgroup.long (0x68+0x200)++0x03
|
|
line.long 0x00 "RXRAM, Multi-buffer RAM Receive Buffer Register 26"
|
|
bitfld.long 0x00 31. " RXEMPTY , Receive data buffer empty" "Not empty,Empty"
|
|
bitfld.long 0x00 30. " RXOVR , Receive data buffer overrun" "No overrun,Overrun"
|
|
newline
|
|
bitfld.long 0x00 29. " TXFULL , Transmit data buffer full" "Not full,Full"
|
|
bitfld.long 0x00 28. " BITERR , Bit error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 27. " DESYNC , Desynchronization of slave device" "No,Yes"
|
|
bitfld.long 0x00 26. " PARITYERR , Parity error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 25. " TIMEOUT , Time-out because of non-activation of ENA pin" "No timeout,Timeout"
|
|
bitfld.long 0x00 24. " DLENERR , Data length error flag" "No,Yes"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " LCSNR , Last chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " RXDATA , SPI receive data"
|
|
rgroup.long (0x6C+0x200)++0x03
|
|
line.long 0x00 "RXRAM, Multi-buffer RAM Receive Buffer Register 27"
|
|
bitfld.long 0x00 31. " RXEMPTY , Receive data buffer empty" "Not empty,Empty"
|
|
bitfld.long 0x00 30. " RXOVR , Receive data buffer overrun" "No overrun,Overrun"
|
|
newline
|
|
bitfld.long 0x00 29. " TXFULL , Transmit data buffer full" "Not full,Full"
|
|
bitfld.long 0x00 28. " BITERR , Bit error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 27. " DESYNC , Desynchronization of slave device" "No,Yes"
|
|
bitfld.long 0x00 26. " PARITYERR , Parity error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 25. " TIMEOUT , Time-out because of non-activation of ENA pin" "No timeout,Timeout"
|
|
bitfld.long 0x00 24. " DLENERR , Data length error flag" "No,Yes"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " LCSNR , Last chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " RXDATA , SPI receive data"
|
|
rgroup.long (0x70+0x200)++0x03
|
|
line.long 0x00 "RXRAM, Multi-buffer RAM Receive Buffer Register 28"
|
|
bitfld.long 0x00 31. " RXEMPTY , Receive data buffer empty" "Not empty,Empty"
|
|
bitfld.long 0x00 30. " RXOVR , Receive data buffer overrun" "No overrun,Overrun"
|
|
newline
|
|
bitfld.long 0x00 29. " TXFULL , Transmit data buffer full" "Not full,Full"
|
|
bitfld.long 0x00 28. " BITERR , Bit error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 27. " DESYNC , Desynchronization of slave device" "No,Yes"
|
|
bitfld.long 0x00 26. " PARITYERR , Parity error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 25. " TIMEOUT , Time-out because of non-activation of ENA pin" "No timeout,Timeout"
|
|
bitfld.long 0x00 24. " DLENERR , Data length error flag" "No,Yes"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " LCSNR , Last chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " RXDATA , SPI receive data"
|
|
rgroup.long (0x74+0x200)++0x03
|
|
line.long 0x00 "RXRAM, Multi-buffer RAM Receive Buffer Register 29"
|
|
bitfld.long 0x00 31. " RXEMPTY , Receive data buffer empty" "Not empty,Empty"
|
|
bitfld.long 0x00 30. " RXOVR , Receive data buffer overrun" "No overrun,Overrun"
|
|
newline
|
|
bitfld.long 0x00 29. " TXFULL , Transmit data buffer full" "Not full,Full"
|
|
bitfld.long 0x00 28. " BITERR , Bit error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 27. " DESYNC , Desynchronization of slave device" "No,Yes"
|
|
bitfld.long 0x00 26. " PARITYERR , Parity error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 25. " TIMEOUT , Time-out because of non-activation of ENA pin" "No timeout,Timeout"
|
|
bitfld.long 0x00 24. " DLENERR , Data length error flag" "No,Yes"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " LCSNR , Last chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " RXDATA , SPI receive data"
|
|
rgroup.long (0x78+0x200)++0x03
|
|
line.long 0x00 "RXRAM, Multi-buffer RAM Receive Buffer Register 30"
|
|
bitfld.long 0x00 31. " RXEMPTY , Receive data buffer empty" "Not empty,Empty"
|
|
bitfld.long 0x00 30. " RXOVR , Receive data buffer overrun" "No overrun,Overrun"
|
|
newline
|
|
bitfld.long 0x00 29. " TXFULL , Transmit data buffer full" "Not full,Full"
|
|
bitfld.long 0x00 28. " BITERR , Bit error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 27. " DESYNC , Desynchronization of slave device" "No,Yes"
|
|
bitfld.long 0x00 26. " PARITYERR , Parity error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 25. " TIMEOUT , Time-out because of non-activation of ENA pin" "No timeout,Timeout"
|
|
bitfld.long 0x00 24. " DLENERR , Data length error flag" "No,Yes"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " LCSNR , Last chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " RXDATA , SPI receive data"
|
|
rgroup.long (0x7C+0x200)++0x03
|
|
line.long 0x00 "RXRAM, Multi-buffer RAM Receive Buffer Register 31"
|
|
bitfld.long 0x00 31. " RXEMPTY , Receive data buffer empty" "Not empty,Empty"
|
|
bitfld.long 0x00 30. " RXOVR , Receive data buffer overrun" "No overrun,Overrun"
|
|
newline
|
|
bitfld.long 0x00 29. " TXFULL , Transmit data buffer full" "Not full,Full"
|
|
bitfld.long 0x00 28. " BITERR , Bit error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 27. " DESYNC , Desynchronization of slave device" "No,Yes"
|
|
bitfld.long 0x00 26. " PARITYERR , Parity error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 25. " TIMEOUT , Time-out because of non-activation of ENA pin" "No timeout,Timeout"
|
|
bitfld.long 0x00 24. " DLENERR , Data length error flag" "No,Yes"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " LCSNR , Last chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " RXDATA , SPI receive data"
|
|
rgroup.long (0x80+0x200)++0x03
|
|
line.long 0x00 "RXRAM, Multi-buffer RAM Receive Buffer Register 32"
|
|
bitfld.long 0x00 31. " RXEMPTY , Receive data buffer empty" "Not empty,Empty"
|
|
bitfld.long 0x00 30. " RXOVR , Receive data buffer overrun" "No overrun,Overrun"
|
|
newline
|
|
bitfld.long 0x00 29. " TXFULL , Transmit data buffer full" "Not full,Full"
|
|
bitfld.long 0x00 28. " BITERR , Bit error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 27. " DESYNC , Desynchronization of slave device" "No,Yes"
|
|
bitfld.long 0x00 26. " PARITYERR , Parity error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 25. " TIMEOUT , Time-out because of non-activation of ENA pin" "No timeout,Timeout"
|
|
bitfld.long 0x00 24. " DLENERR , Data length error flag" "No,Yes"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " LCSNR , Last chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " RXDATA , SPI receive data"
|
|
rgroup.long (0x84+0x200)++0x03
|
|
line.long 0x00 "RXRAM, Multi-buffer RAM Receive Buffer Register 33"
|
|
bitfld.long 0x00 31. " RXEMPTY , Receive data buffer empty" "Not empty,Empty"
|
|
bitfld.long 0x00 30. " RXOVR , Receive data buffer overrun" "No overrun,Overrun"
|
|
newline
|
|
bitfld.long 0x00 29. " TXFULL , Transmit data buffer full" "Not full,Full"
|
|
bitfld.long 0x00 28. " BITERR , Bit error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 27. " DESYNC , Desynchronization of slave device" "No,Yes"
|
|
bitfld.long 0x00 26. " PARITYERR , Parity error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 25. " TIMEOUT , Time-out because of non-activation of ENA pin" "No timeout,Timeout"
|
|
bitfld.long 0x00 24. " DLENERR , Data length error flag" "No,Yes"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " LCSNR , Last chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " RXDATA , SPI receive data"
|
|
rgroup.long (0x88+0x200)++0x03
|
|
line.long 0x00 "RXRAM, Multi-buffer RAM Receive Buffer Register 34"
|
|
bitfld.long 0x00 31. " RXEMPTY , Receive data buffer empty" "Not empty,Empty"
|
|
bitfld.long 0x00 30. " RXOVR , Receive data buffer overrun" "No overrun,Overrun"
|
|
newline
|
|
bitfld.long 0x00 29. " TXFULL , Transmit data buffer full" "Not full,Full"
|
|
bitfld.long 0x00 28. " BITERR , Bit error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 27. " DESYNC , Desynchronization of slave device" "No,Yes"
|
|
bitfld.long 0x00 26. " PARITYERR , Parity error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 25. " TIMEOUT , Time-out because of non-activation of ENA pin" "No timeout,Timeout"
|
|
bitfld.long 0x00 24. " DLENERR , Data length error flag" "No,Yes"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " LCSNR , Last chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " RXDATA , SPI receive data"
|
|
rgroup.long (0x8C+0x200)++0x03
|
|
line.long 0x00 "RXRAM, Multi-buffer RAM Receive Buffer Register 35"
|
|
bitfld.long 0x00 31. " RXEMPTY , Receive data buffer empty" "Not empty,Empty"
|
|
bitfld.long 0x00 30. " RXOVR , Receive data buffer overrun" "No overrun,Overrun"
|
|
newline
|
|
bitfld.long 0x00 29. " TXFULL , Transmit data buffer full" "Not full,Full"
|
|
bitfld.long 0x00 28. " BITERR , Bit error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 27. " DESYNC , Desynchronization of slave device" "No,Yes"
|
|
bitfld.long 0x00 26. " PARITYERR , Parity error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 25. " TIMEOUT , Time-out because of non-activation of ENA pin" "No timeout,Timeout"
|
|
bitfld.long 0x00 24. " DLENERR , Data length error flag" "No,Yes"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " LCSNR , Last chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " RXDATA , SPI receive data"
|
|
rgroup.long (0x90+0x200)++0x03
|
|
line.long 0x00 "RXRAM, Multi-buffer RAM Receive Buffer Register 36"
|
|
bitfld.long 0x00 31. " RXEMPTY , Receive data buffer empty" "Not empty,Empty"
|
|
bitfld.long 0x00 30. " RXOVR , Receive data buffer overrun" "No overrun,Overrun"
|
|
newline
|
|
bitfld.long 0x00 29. " TXFULL , Transmit data buffer full" "Not full,Full"
|
|
bitfld.long 0x00 28. " BITERR , Bit error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 27. " DESYNC , Desynchronization of slave device" "No,Yes"
|
|
bitfld.long 0x00 26. " PARITYERR , Parity error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 25. " TIMEOUT , Time-out because of non-activation of ENA pin" "No timeout,Timeout"
|
|
bitfld.long 0x00 24. " DLENERR , Data length error flag" "No,Yes"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " LCSNR , Last chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " RXDATA , SPI receive data"
|
|
rgroup.long (0x94+0x200)++0x03
|
|
line.long 0x00 "RXRAM, Multi-buffer RAM Receive Buffer Register 37"
|
|
bitfld.long 0x00 31. " RXEMPTY , Receive data buffer empty" "Not empty,Empty"
|
|
bitfld.long 0x00 30. " RXOVR , Receive data buffer overrun" "No overrun,Overrun"
|
|
newline
|
|
bitfld.long 0x00 29. " TXFULL , Transmit data buffer full" "Not full,Full"
|
|
bitfld.long 0x00 28. " BITERR , Bit error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 27. " DESYNC , Desynchronization of slave device" "No,Yes"
|
|
bitfld.long 0x00 26. " PARITYERR , Parity error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 25. " TIMEOUT , Time-out because of non-activation of ENA pin" "No timeout,Timeout"
|
|
bitfld.long 0x00 24. " DLENERR , Data length error flag" "No,Yes"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " LCSNR , Last chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " RXDATA , SPI receive data"
|
|
rgroup.long (0x98+0x200)++0x03
|
|
line.long 0x00 "RXRAM, Multi-buffer RAM Receive Buffer Register 38"
|
|
bitfld.long 0x00 31. " RXEMPTY , Receive data buffer empty" "Not empty,Empty"
|
|
bitfld.long 0x00 30. " RXOVR , Receive data buffer overrun" "No overrun,Overrun"
|
|
newline
|
|
bitfld.long 0x00 29. " TXFULL , Transmit data buffer full" "Not full,Full"
|
|
bitfld.long 0x00 28. " BITERR , Bit error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 27. " DESYNC , Desynchronization of slave device" "No,Yes"
|
|
bitfld.long 0x00 26. " PARITYERR , Parity error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 25. " TIMEOUT , Time-out because of non-activation of ENA pin" "No timeout,Timeout"
|
|
bitfld.long 0x00 24. " DLENERR , Data length error flag" "No,Yes"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " LCSNR , Last chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " RXDATA , SPI receive data"
|
|
rgroup.long (0x9C+0x200)++0x03
|
|
line.long 0x00 "RXRAM, Multi-buffer RAM Receive Buffer Register 39"
|
|
bitfld.long 0x00 31. " RXEMPTY , Receive data buffer empty" "Not empty,Empty"
|
|
bitfld.long 0x00 30. " RXOVR , Receive data buffer overrun" "No overrun,Overrun"
|
|
newline
|
|
bitfld.long 0x00 29. " TXFULL , Transmit data buffer full" "Not full,Full"
|
|
bitfld.long 0x00 28. " BITERR , Bit error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 27. " DESYNC , Desynchronization of slave device" "No,Yes"
|
|
bitfld.long 0x00 26. " PARITYERR , Parity error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 25. " TIMEOUT , Time-out because of non-activation of ENA pin" "No timeout,Timeout"
|
|
bitfld.long 0x00 24. " DLENERR , Data length error flag" "No,Yes"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " LCSNR , Last chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " RXDATA , SPI receive data"
|
|
rgroup.long (0xA0+0x200)++0x03
|
|
line.long 0x00 "RXRAM, Multi-buffer RAM Receive Buffer Register 40"
|
|
bitfld.long 0x00 31. " RXEMPTY , Receive data buffer empty" "Not empty,Empty"
|
|
bitfld.long 0x00 30. " RXOVR , Receive data buffer overrun" "No overrun,Overrun"
|
|
newline
|
|
bitfld.long 0x00 29. " TXFULL , Transmit data buffer full" "Not full,Full"
|
|
bitfld.long 0x00 28. " BITERR , Bit error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 27. " DESYNC , Desynchronization of slave device" "No,Yes"
|
|
bitfld.long 0x00 26. " PARITYERR , Parity error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 25. " TIMEOUT , Time-out because of non-activation of ENA pin" "No timeout,Timeout"
|
|
bitfld.long 0x00 24. " DLENERR , Data length error flag" "No,Yes"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " LCSNR , Last chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " RXDATA , SPI receive data"
|
|
rgroup.long (0xA4+0x200)++0x03
|
|
line.long 0x00 "RXRAM, Multi-buffer RAM Receive Buffer Register 41"
|
|
bitfld.long 0x00 31. " RXEMPTY , Receive data buffer empty" "Not empty,Empty"
|
|
bitfld.long 0x00 30. " RXOVR , Receive data buffer overrun" "No overrun,Overrun"
|
|
newline
|
|
bitfld.long 0x00 29. " TXFULL , Transmit data buffer full" "Not full,Full"
|
|
bitfld.long 0x00 28. " BITERR , Bit error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 27. " DESYNC , Desynchronization of slave device" "No,Yes"
|
|
bitfld.long 0x00 26. " PARITYERR , Parity error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 25. " TIMEOUT , Time-out because of non-activation of ENA pin" "No timeout,Timeout"
|
|
bitfld.long 0x00 24. " DLENERR , Data length error flag" "No,Yes"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " LCSNR , Last chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " RXDATA , SPI receive data"
|
|
rgroup.long (0xA8+0x200)++0x03
|
|
line.long 0x00 "RXRAM, Multi-buffer RAM Receive Buffer Register 42"
|
|
bitfld.long 0x00 31. " RXEMPTY , Receive data buffer empty" "Not empty,Empty"
|
|
bitfld.long 0x00 30. " RXOVR , Receive data buffer overrun" "No overrun,Overrun"
|
|
newline
|
|
bitfld.long 0x00 29. " TXFULL , Transmit data buffer full" "Not full,Full"
|
|
bitfld.long 0x00 28. " BITERR , Bit error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 27. " DESYNC , Desynchronization of slave device" "No,Yes"
|
|
bitfld.long 0x00 26. " PARITYERR , Parity error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 25. " TIMEOUT , Time-out because of non-activation of ENA pin" "No timeout,Timeout"
|
|
bitfld.long 0x00 24. " DLENERR , Data length error flag" "No,Yes"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " LCSNR , Last chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " RXDATA , SPI receive data"
|
|
rgroup.long (0xAC+0x200)++0x03
|
|
line.long 0x00 "RXRAM, Multi-buffer RAM Receive Buffer Register 43"
|
|
bitfld.long 0x00 31. " RXEMPTY , Receive data buffer empty" "Not empty,Empty"
|
|
bitfld.long 0x00 30. " RXOVR , Receive data buffer overrun" "No overrun,Overrun"
|
|
newline
|
|
bitfld.long 0x00 29. " TXFULL , Transmit data buffer full" "Not full,Full"
|
|
bitfld.long 0x00 28. " BITERR , Bit error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 27. " DESYNC , Desynchronization of slave device" "No,Yes"
|
|
bitfld.long 0x00 26. " PARITYERR , Parity error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 25. " TIMEOUT , Time-out because of non-activation of ENA pin" "No timeout,Timeout"
|
|
bitfld.long 0x00 24. " DLENERR , Data length error flag" "No,Yes"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " LCSNR , Last chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " RXDATA , SPI receive data"
|
|
rgroup.long (0xB0+0x200)++0x03
|
|
line.long 0x00 "RXRAM, Multi-buffer RAM Receive Buffer Register 44"
|
|
bitfld.long 0x00 31. " RXEMPTY , Receive data buffer empty" "Not empty,Empty"
|
|
bitfld.long 0x00 30. " RXOVR , Receive data buffer overrun" "No overrun,Overrun"
|
|
newline
|
|
bitfld.long 0x00 29. " TXFULL , Transmit data buffer full" "Not full,Full"
|
|
bitfld.long 0x00 28. " BITERR , Bit error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 27. " DESYNC , Desynchronization of slave device" "No,Yes"
|
|
bitfld.long 0x00 26. " PARITYERR , Parity error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 25. " TIMEOUT , Time-out because of non-activation of ENA pin" "No timeout,Timeout"
|
|
bitfld.long 0x00 24. " DLENERR , Data length error flag" "No,Yes"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " LCSNR , Last chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " RXDATA , SPI receive data"
|
|
rgroup.long (0xB4+0x200)++0x03
|
|
line.long 0x00 "RXRAM, Multi-buffer RAM Receive Buffer Register 45"
|
|
bitfld.long 0x00 31. " RXEMPTY , Receive data buffer empty" "Not empty,Empty"
|
|
bitfld.long 0x00 30. " RXOVR , Receive data buffer overrun" "No overrun,Overrun"
|
|
newline
|
|
bitfld.long 0x00 29. " TXFULL , Transmit data buffer full" "Not full,Full"
|
|
bitfld.long 0x00 28. " BITERR , Bit error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 27. " DESYNC , Desynchronization of slave device" "No,Yes"
|
|
bitfld.long 0x00 26. " PARITYERR , Parity error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 25. " TIMEOUT , Time-out because of non-activation of ENA pin" "No timeout,Timeout"
|
|
bitfld.long 0x00 24. " DLENERR , Data length error flag" "No,Yes"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " LCSNR , Last chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " RXDATA , SPI receive data"
|
|
rgroup.long (0xB8+0x200)++0x03
|
|
line.long 0x00 "RXRAM, Multi-buffer RAM Receive Buffer Register 46"
|
|
bitfld.long 0x00 31. " RXEMPTY , Receive data buffer empty" "Not empty,Empty"
|
|
bitfld.long 0x00 30. " RXOVR , Receive data buffer overrun" "No overrun,Overrun"
|
|
newline
|
|
bitfld.long 0x00 29. " TXFULL , Transmit data buffer full" "Not full,Full"
|
|
bitfld.long 0x00 28. " BITERR , Bit error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 27. " DESYNC , Desynchronization of slave device" "No,Yes"
|
|
bitfld.long 0x00 26. " PARITYERR , Parity error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 25. " TIMEOUT , Time-out because of non-activation of ENA pin" "No timeout,Timeout"
|
|
bitfld.long 0x00 24. " DLENERR , Data length error flag" "No,Yes"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " LCSNR , Last chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " RXDATA , SPI receive data"
|
|
rgroup.long (0xBC+0x200)++0x03
|
|
line.long 0x00 "RXRAM, Multi-buffer RAM Receive Buffer Register 47"
|
|
bitfld.long 0x00 31. " RXEMPTY , Receive data buffer empty" "Not empty,Empty"
|
|
bitfld.long 0x00 30. " RXOVR , Receive data buffer overrun" "No overrun,Overrun"
|
|
newline
|
|
bitfld.long 0x00 29. " TXFULL , Transmit data buffer full" "Not full,Full"
|
|
bitfld.long 0x00 28. " BITERR , Bit error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 27. " DESYNC , Desynchronization of slave device" "No,Yes"
|
|
bitfld.long 0x00 26. " PARITYERR , Parity error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 25. " TIMEOUT , Time-out because of non-activation of ENA pin" "No timeout,Timeout"
|
|
bitfld.long 0x00 24. " DLENERR , Data length error flag" "No,Yes"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " LCSNR , Last chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " RXDATA , SPI receive data"
|
|
rgroup.long (0xC0+0x200)++0x03
|
|
line.long 0x00 "RXRAM, Multi-buffer RAM Receive Buffer Register 48"
|
|
bitfld.long 0x00 31. " RXEMPTY , Receive data buffer empty" "Not empty,Empty"
|
|
bitfld.long 0x00 30. " RXOVR , Receive data buffer overrun" "No overrun,Overrun"
|
|
newline
|
|
bitfld.long 0x00 29. " TXFULL , Transmit data buffer full" "Not full,Full"
|
|
bitfld.long 0x00 28. " BITERR , Bit error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 27. " DESYNC , Desynchronization of slave device" "No,Yes"
|
|
bitfld.long 0x00 26. " PARITYERR , Parity error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 25. " TIMEOUT , Time-out because of non-activation of ENA pin" "No timeout,Timeout"
|
|
bitfld.long 0x00 24. " DLENERR , Data length error flag" "No,Yes"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " LCSNR , Last chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " RXDATA , SPI receive data"
|
|
rgroup.long (0xC4+0x200)++0x03
|
|
line.long 0x00 "RXRAM, Multi-buffer RAM Receive Buffer Register 49"
|
|
bitfld.long 0x00 31. " RXEMPTY , Receive data buffer empty" "Not empty,Empty"
|
|
bitfld.long 0x00 30. " RXOVR , Receive data buffer overrun" "No overrun,Overrun"
|
|
newline
|
|
bitfld.long 0x00 29. " TXFULL , Transmit data buffer full" "Not full,Full"
|
|
bitfld.long 0x00 28. " BITERR , Bit error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 27. " DESYNC , Desynchronization of slave device" "No,Yes"
|
|
bitfld.long 0x00 26. " PARITYERR , Parity error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 25. " TIMEOUT , Time-out because of non-activation of ENA pin" "No timeout,Timeout"
|
|
bitfld.long 0x00 24. " DLENERR , Data length error flag" "No,Yes"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " LCSNR , Last chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " RXDATA , SPI receive data"
|
|
rgroup.long (0xC8+0x200)++0x03
|
|
line.long 0x00 "RXRAM, Multi-buffer RAM Receive Buffer Register 50"
|
|
bitfld.long 0x00 31. " RXEMPTY , Receive data buffer empty" "Not empty,Empty"
|
|
bitfld.long 0x00 30. " RXOVR , Receive data buffer overrun" "No overrun,Overrun"
|
|
newline
|
|
bitfld.long 0x00 29. " TXFULL , Transmit data buffer full" "Not full,Full"
|
|
bitfld.long 0x00 28. " BITERR , Bit error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 27. " DESYNC , Desynchronization of slave device" "No,Yes"
|
|
bitfld.long 0x00 26. " PARITYERR , Parity error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 25. " TIMEOUT , Time-out because of non-activation of ENA pin" "No timeout,Timeout"
|
|
bitfld.long 0x00 24. " DLENERR , Data length error flag" "No,Yes"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " LCSNR , Last chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " RXDATA , SPI receive data"
|
|
rgroup.long (0xCC+0x200)++0x03
|
|
line.long 0x00 "RXRAM, Multi-buffer RAM Receive Buffer Register 51"
|
|
bitfld.long 0x00 31. " RXEMPTY , Receive data buffer empty" "Not empty,Empty"
|
|
bitfld.long 0x00 30. " RXOVR , Receive data buffer overrun" "No overrun,Overrun"
|
|
newline
|
|
bitfld.long 0x00 29. " TXFULL , Transmit data buffer full" "Not full,Full"
|
|
bitfld.long 0x00 28. " BITERR , Bit error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 27. " DESYNC , Desynchronization of slave device" "No,Yes"
|
|
bitfld.long 0x00 26. " PARITYERR , Parity error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 25. " TIMEOUT , Time-out because of non-activation of ENA pin" "No timeout,Timeout"
|
|
bitfld.long 0x00 24. " DLENERR , Data length error flag" "No,Yes"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " LCSNR , Last chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " RXDATA , SPI receive data"
|
|
rgroup.long (0xD0+0x200)++0x03
|
|
line.long 0x00 "RXRAM, Multi-buffer RAM Receive Buffer Register 52"
|
|
bitfld.long 0x00 31. " RXEMPTY , Receive data buffer empty" "Not empty,Empty"
|
|
bitfld.long 0x00 30. " RXOVR , Receive data buffer overrun" "No overrun,Overrun"
|
|
newline
|
|
bitfld.long 0x00 29. " TXFULL , Transmit data buffer full" "Not full,Full"
|
|
bitfld.long 0x00 28. " BITERR , Bit error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 27. " DESYNC , Desynchronization of slave device" "No,Yes"
|
|
bitfld.long 0x00 26. " PARITYERR , Parity error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 25. " TIMEOUT , Time-out because of non-activation of ENA pin" "No timeout,Timeout"
|
|
bitfld.long 0x00 24. " DLENERR , Data length error flag" "No,Yes"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " LCSNR , Last chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " RXDATA , SPI receive data"
|
|
rgroup.long (0xD4+0x200)++0x03
|
|
line.long 0x00 "RXRAM, Multi-buffer RAM Receive Buffer Register 53"
|
|
bitfld.long 0x00 31. " RXEMPTY , Receive data buffer empty" "Not empty,Empty"
|
|
bitfld.long 0x00 30. " RXOVR , Receive data buffer overrun" "No overrun,Overrun"
|
|
newline
|
|
bitfld.long 0x00 29. " TXFULL , Transmit data buffer full" "Not full,Full"
|
|
bitfld.long 0x00 28. " BITERR , Bit error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 27. " DESYNC , Desynchronization of slave device" "No,Yes"
|
|
bitfld.long 0x00 26. " PARITYERR , Parity error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 25. " TIMEOUT , Time-out because of non-activation of ENA pin" "No timeout,Timeout"
|
|
bitfld.long 0x00 24. " DLENERR , Data length error flag" "No,Yes"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " LCSNR , Last chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " RXDATA , SPI receive data"
|
|
rgroup.long (0xD8+0x200)++0x03
|
|
line.long 0x00 "RXRAM, Multi-buffer RAM Receive Buffer Register 54"
|
|
bitfld.long 0x00 31. " RXEMPTY , Receive data buffer empty" "Not empty,Empty"
|
|
bitfld.long 0x00 30. " RXOVR , Receive data buffer overrun" "No overrun,Overrun"
|
|
newline
|
|
bitfld.long 0x00 29. " TXFULL , Transmit data buffer full" "Not full,Full"
|
|
bitfld.long 0x00 28. " BITERR , Bit error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 27. " DESYNC , Desynchronization of slave device" "No,Yes"
|
|
bitfld.long 0x00 26. " PARITYERR , Parity error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 25. " TIMEOUT , Time-out because of non-activation of ENA pin" "No timeout,Timeout"
|
|
bitfld.long 0x00 24. " DLENERR , Data length error flag" "No,Yes"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " LCSNR , Last chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " RXDATA , SPI receive data"
|
|
rgroup.long (0xDC+0x200)++0x03
|
|
line.long 0x00 "RXRAM, Multi-buffer RAM Receive Buffer Register 55"
|
|
bitfld.long 0x00 31. " RXEMPTY , Receive data buffer empty" "Not empty,Empty"
|
|
bitfld.long 0x00 30. " RXOVR , Receive data buffer overrun" "No overrun,Overrun"
|
|
newline
|
|
bitfld.long 0x00 29. " TXFULL , Transmit data buffer full" "Not full,Full"
|
|
bitfld.long 0x00 28. " BITERR , Bit error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 27. " DESYNC , Desynchronization of slave device" "No,Yes"
|
|
bitfld.long 0x00 26. " PARITYERR , Parity error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 25. " TIMEOUT , Time-out because of non-activation of ENA pin" "No timeout,Timeout"
|
|
bitfld.long 0x00 24. " DLENERR , Data length error flag" "No,Yes"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " LCSNR , Last chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " RXDATA , SPI receive data"
|
|
rgroup.long (0xE0+0x200)++0x03
|
|
line.long 0x00 "RXRAM, Multi-buffer RAM Receive Buffer Register 56"
|
|
bitfld.long 0x00 31. " RXEMPTY , Receive data buffer empty" "Not empty,Empty"
|
|
bitfld.long 0x00 30. " RXOVR , Receive data buffer overrun" "No overrun,Overrun"
|
|
newline
|
|
bitfld.long 0x00 29. " TXFULL , Transmit data buffer full" "Not full,Full"
|
|
bitfld.long 0x00 28. " BITERR , Bit error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 27. " DESYNC , Desynchronization of slave device" "No,Yes"
|
|
bitfld.long 0x00 26. " PARITYERR , Parity error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 25. " TIMEOUT , Time-out because of non-activation of ENA pin" "No timeout,Timeout"
|
|
bitfld.long 0x00 24. " DLENERR , Data length error flag" "No,Yes"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " LCSNR , Last chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " RXDATA , SPI receive data"
|
|
rgroup.long (0xE4+0x200)++0x03
|
|
line.long 0x00 "RXRAM, Multi-buffer RAM Receive Buffer Register 57"
|
|
bitfld.long 0x00 31. " RXEMPTY , Receive data buffer empty" "Not empty,Empty"
|
|
bitfld.long 0x00 30. " RXOVR , Receive data buffer overrun" "No overrun,Overrun"
|
|
newline
|
|
bitfld.long 0x00 29. " TXFULL , Transmit data buffer full" "Not full,Full"
|
|
bitfld.long 0x00 28. " BITERR , Bit error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 27. " DESYNC , Desynchronization of slave device" "No,Yes"
|
|
bitfld.long 0x00 26. " PARITYERR , Parity error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 25. " TIMEOUT , Time-out because of non-activation of ENA pin" "No timeout,Timeout"
|
|
bitfld.long 0x00 24. " DLENERR , Data length error flag" "No,Yes"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " LCSNR , Last chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " RXDATA , SPI receive data"
|
|
rgroup.long (0xE8+0x200)++0x03
|
|
line.long 0x00 "RXRAM, Multi-buffer RAM Receive Buffer Register 58"
|
|
bitfld.long 0x00 31. " RXEMPTY , Receive data buffer empty" "Not empty,Empty"
|
|
bitfld.long 0x00 30. " RXOVR , Receive data buffer overrun" "No overrun,Overrun"
|
|
newline
|
|
bitfld.long 0x00 29. " TXFULL , Transmit data buffer full" "Not full,Full"
|
|
bitfld.long 0x00 28. " BITERR , Bit error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 27. " DESYNC , Desynchronization of slave device" "No,Yes"
|
|
bitfld.long 0x00 26. " PARITYERR , Parity error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 25. " TIMEOUT , Time-out because of non-activation of ENA pin" "No timeout,Timeout"
|
|
bitfld.long 0x00 24. " DLENERR , Data length error flag" "No,Yes"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " LCSNR , Last chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " RXDATA , SPI receive data"
|
|
rgroup.long (0xEC+0x200)++0x03
|
|
line.long 0x00 "RXRAM, Multi-buffer RAM Receive Buffer Register 59"
|
|
bitfld.long 0x00 31. " RXEMPTY , Receive data buffer empty" "Not empty,Empty"
|
|
bitfld.long 0x00 30. " RXOVR , Receive data buffer overrun" "No overrun,Overrun"
|
|
newline
|
|
bitfld.long 0x00 29. " TXFULL , Transmit data buffer full" "Not full,Full"
|
|
bitfld.long 0x00 28. " BITERR , Bit error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 27. " DESYNC , Desynchronization of slave device" "No,Yes"
|
|
bitfld.long 0x00 26. " PARITYERR , Parity error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 25. " TIMEOUT , Time-out because of non-activation of ENA pin" "No timeout,Timeout"
|
|
bitfld.long 0x00 24. " DLENERR , Data length error flag" "No,Yes"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " LCSNR , Last chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " RXDATA , SPI receive data"
|
|
rgroup.long (0xF0+0x200)++0x03
|
|
line.long 0x00 "RXRAM, Multi-buffer RAM Receive Buffer Register 60"
|
|
bitfld.long 0x00 31. " RXEMPTY , Receive data buffer empty" "Not empty,Empty"
|
|
bitfld.long 0x00 30. " RXOVR , Receive data buffer overrun" "No overrun,Overrun"
|
|
newline
|
|
bitfld.long 0x00 29. " TXFULL , Transmit data buffer full" "Not full,Full"
|
|
bitfld.long 0x00 28. " BITERR , Bit error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 27. " DESYNC , Desynchronization of slave device" "No,Yes"
|
|
bitfld.long 0x00 26. " PARITYERR , Parity error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 25. " TIMEOUT , Time-out because of non-activation of ENA pin" "No timeout,Timeout"
|
|
bitfld.long 0x00 24. " DLENERR , Data length error flag" "No,Yes"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " LCSNR , Last chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " RXDATA , SPI receive data"
|
|
rgroup.long (0xF4+0x200)++0x03
|
|
line.long 0x00 "RXRAM, Multi-buffer RAM Receive Buffer Register 61"
|
|
bitfld.long 0x00 31. " RXEMPTY , Receive data buffer empty" "Not empty,Empty"
|
|
bitfld.long 0x00 30. " RXOVR , Receive data buffer overrun" "No overrun,Overrun"
|
|
newline
|
|
bitfld.long 0x00 29. " TXFULL , Transmit data buffer full" "Not full,Full"
|
|
bitfld.long 0x00 28. " BITERR , Bit error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 27. " DESYNC , Desynchronization of slave device" "No,Yes"
|
|
bitfld.long 0x00 26. " PARITYERR , Parity error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 25. " TIMEOUT , Time-out because of non-activation of ENA pin" "No timeout,Timeout"
|
|
bitfld.long 0x00 24. " DLENERR , Data length error flag" "No,Yes"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " LCSNR , Last chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " RXDATA , SPI receive data"
|
|
rgroup.long (0xF8+0x200)++0x03
|
|
line.long 0x00 "RXRAM, Multi-buffer RAM Receive Buffer Register 62"
|
|
bitfld.long 0x00 31. " RXEMPTY , Receive data buffer empty" "Not empty,Empty"
|
|
bitfld.long 0x00 30. " RXOVR , Receive data buffer overrun" "No overrun,Overrun"
|
|
newline
|
|
bitfld.long 0x00 29. " TXFULL , Transmit data buffer full" "Not full,Full"
|
|
bitfld.long 0x00 28. " BITERR , Bit error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 27. " DESYNC , Desynchronization of slave device" "No,Yes"
|
|
bitfld.long 0x00 26. " PARITYERR , Parity error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 25. " TIMEOUT , Time-out because of non-activation of ENA pin" "No timeout,Timeout"
|
|
bitfld.long 0x00 24. " DLENERR , Data length error flag" "No,Yes"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " LCSNR , Last chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " RXDATA , SPI receive data"
|
|
rgroup.long (0xFC+0x200)++0x03
|
|
line.long 0x00 "RXRAM, Multi-buffer RAM Receive Buffer Register 63"
|
|
bitfld.long 0x00 31. " RXEMPTY , Receive data buffer empty" "Not empty,Empty"
|
|
bitfld.long 0x00 30. " RXOVR , Receive data buffer overrun" "No overrun,Overrun"
|
|
newline
|
|
bitfld.long 0x00 29. " TXFULL , Transmit data buffer full" "Not full,Full"
|
|
bitfld.long 0x00 28. " BITERR , Bit error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 27. " DESYNC , Desynchronization of slave device" "No,Yes"
|
|
bitfld.long 0x00 26. " PARITYERR , Parity error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 25. " TIMEOUT , Time-out because of non-activation of ENA pin" "No timeout,Timeout"
|
|
bitfld.long 0x00 24. " DLENERR , Data length error flag" "No,Yes"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " LCSNR , Last chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " RXDATA , SPI receive data"
|
|
rgroup.long (0x100+0x200)++0x03
|
|
line.long 0x00 "RXRAM, Multi-buffer RAM Receive Buffer Register 64"
|
|
bitfld.long 0x00 31. " RXEMPTY , Receive data buffer empty" "Not empty,Empty"
|
|
bitfld.long 0x00 30. " RXOVR , Receive data buffer overrun" "No overrun,Overrun"
|
|
newline
|
|
bitfld.long 0x00 29. " TXFULL , Transmit data buffer full" "Not full,Full"
|
|
bitfld.long 0x00 28. " BITERR , Bit error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 27. " DESYNC , Desynchronization of slave device" "No,Yes"
|
|
bitfld.long 0x00 26. " PARITYERR , Parity error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 25. " TIMEOUT , Time-out because of non-activation of ENA pin" "No timeout,Timeout"
|
|
bitfld.long 0x00 24. " DLENERR , Data length error flag" "No,Yes"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " LCSNR , Last chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " RXDATA , SPI receive data"
|
|
rgroup.long (0x104+0x200)++0x03
|
|
line.long 0x00 "RXRAM, Multi-buffer RAM Receive Buffer Register 65"
|
|
bitfld.long 0x00 31. " RXEMPTY , Receive data buffer empty" "Not empty,Empty"
|
|
bitfld.long 0x00 30. " RXOVR , Receive data buffer overrun" "No overrun,Overrun"
|
|
newline
|
|
bitfld.long 0x00 29. " TXFULL , Transmit data buffer full" "Not full,Full"
|
|
bitfld.long 0x00 28. " BITERR , Bit error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 27. " DESYNC , Desynchronization of slave device" "No,Yes"
|
|
bitfld.long 0x00 26. " PARITYERR , Parity error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 25. " TIMEOUT , Time-out because of non-activation of ENA pin" "No timeout,Timeout"
|
|
bitfld.long 0x00 24. " DLENERR , Data length error flag" "No,Yes"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " LCSNR , Last chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " RXDATA , SPI receive data"
|
|
rgroup.long (0x108+0x200)++0x03
|
|
line.long 0x00 "RXRAM, Multi-buffer RAM Receive Buffer Register 66"
|
|
bitfld.long 0x00 31. " RXEMPTY , Receive data buffer empty" "Not empty,Empty"
|
|
bitfld.long 0x00 30. " RXOVR , Receive data buffer overrun" "No overrun,Overrun"
|
|
newline
|
|
bitfld.long 0x00 29. " TXFULL , Transmit data buffer full" "Not full,Full"
|
|
bitfld.long 0x00 28. " BITERR , Bit error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 27. " DESYNC , Desynchronization of slave device" "No,Yes"
|
|
bitfld.long 0x00 26. " PARITYERR , Parity error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 25. " TIMEOUT , Time-out because of non-activation of ENA pin" "No timeout,Timeout"
|
|
bitfld.long 0x00 24. " DLENERR , Data length error flag" "No,Yes"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " LCSNR , Last chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " RXDATA , SPI receive data"
|
|
rgroup.long (0x10C+0x200)++0x03
|
|
line.long 0x00 "RXRAM, Multi-buffer RAM Receive Buffer Register 67"
|
|
bitfld.long 0x00 31. " RXEMPTY , Receive data buffer empty" "Not empty,Empty"
|
|
bitfld.long 0x00 30. " RXOVR , Receive data buffer overrun" "No overrun,Overrun"
|
|
newline
|
|
bitfld.long 0x00 29. " TXFULL , Transmit data buffer full" "Not full,Full"
|
|
bitfld.long 0x00 28. " BITERR , Bit error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 27. " DESYNC , Desynchronization of slave device" "No,Yes"
|
|
bitfld.long 0x00 26. " PARITYERR , Parity error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 25. " TIMEOUT , Time-out because of non-activation of ENA pin" "No timeout,Timeout"
|
|
bitfld.long 0x00 24. " DLENERR , Data length error flag" "No,Yes"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " LCSNR , Last chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " RXDATA , SPI receive data"
|
|
rgroup.long (0x110+0x200)++0x03
|
|
line.long 0x00 "RXRAM, Multi-buffer RAM Receive Buffer Register 68"
|
|
bitfld.long 0x00 31. " RXEMPTY , Receive data buffer empty" "Not empty,Empty"
|
|
bitfld.long 0x00 30. " RXOVR , Receive data buffer overrun" "No overrun,Overrun"
|
|
newline
|
|
bitfld.long 0x00 29. " TXFULL , Transmit data buffer full" "Not full,Full"
|
|
bitfld.long 0x00 28. " BITERR , Bit error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 27. " DESYNC , Desynchronization of slave device" "No,Yes"
|
|
bitfld.long 0x00 26. " PARITYERR , Parity error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 25. " TIMEOUT , Time-out because of non-activation of ENA pin" "No timeout,Timeout"
|
|
bitfld.long 0x00 24. " DLENERR , Data length error flag" "No,Yes"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " LCSNR , Last chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " RXDATA , SPI receive data"
|
|
rgroup.long (0x114+0x200)++0x03
|
|
line.long 0x00 "RXRAM, Multi-buffer RAM Receive Buffer Register 69"
|
|
bitfld.long 0x00 31. " RXEMPTY , Receive data buffer empty" "Not empty,Empty"
|
|
bitfld.long 0x00 30. " RXOVR , Receive data buffer overrun" "No overrun,Overrun"
|
|
newline
|
|
bitfld.long 0x00 29. " TXFULL , Transmit data buffer full" "Not full,Full"
|
|
bitfld.long 0x00 28. " BITERR , Bit error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 27. " DESYNC , Desynchronization of slave device" "No,Yes"
|
|
bitfld.long 0x00 26. " PARITYERR , Parity error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 25. " TIMEOUT , Time-out because of non-activation of ENA pin" "No timeout,Timeout"
|
|
bitfld.long 0x00 24. " DLENERR , Data length error flag" "No,Yes"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " LCSNR , Last chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " RXDATA , SPI receive data"
|
|
rgroup.long (0x118+0x200)++0x03
|
|
line.long 0x00 "RXRAM, Multi-buffer RAM Receive Buffer Register 70"
|
|
bitfld.long 0x00 31. " RXEMPTY , Receive data buffer empty" "Not empty,Empty"
|
|
bitfld.long 0x00 30. " RXOVR , Receive data buffer overrun" "No overrun,Overrun"
|
|
newline
|
|
bitfld.long 0x00 29. " TXFULL , Transmit data buffer full" "Not full,Full"
|
|
bitfld.long 0x00 28. " BITERR , Bit error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 27. " DESYNC , Desynchronization of slave device" "No,Yes"
|
|
bitfld.long 0x00 26. " PARITYERR , Parity error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 25. " TIMEOUT , Time-out because of non-activation of ENA pin" "No timeout,Timeout"
|
|
bitfld.long 0x00 24. " DLENERR , Data length error flag" "No,Yes"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " LCSNR , Last chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " RXDATA , SPI receive data"
|
|
rgroup.long (0x11C+0x200)++0x03
|
|
line.long 0x00 "RXRAM, Multi-buffer RAM Receive Buffer Register 71"
|
|
bitfld.long 0x00 31. " RXEMPTY , Receive data buffer empty" "Not empty,Empty"
|
|
bitfld.long 0x00 30. " RXOVR , Receive data buffer overrun" "No overrun,Overrun"
|
|
newline
|
|
bitfld.long 0x00 29. " TXFULL , Transmit data buffer full" "Not full,Full"
|
|
bitfld.long 0x00 28. " BITERR , Bit error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 27. " DESYNC , Desynchronization of slave device" "No,Yes"
|
|
bitfld.long 0x00 26. " PARITYERR , Parity error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 25. " TIMEOUT , Time-out because of non-activation of ENA pin" "No timeout,Timeout"
|
|
bitfld.long 0x00 24. " DLENERR , Data length error flag" "No,Yes"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " LCSNR , Last chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " RXDATA , SPI receive data"
|
|
rgroup.long (0x120+0x200)++0x03
|
|
line.long 0x00 "RXRAM, Multi-buffer RAM Receive Buffer Register 72"
|
|
bitfld.long 0x00 31. " RXEMPTY , Receive data buffer empty" "Not empty,Empty"
|
|
bitfld.long 0x00 30. " RXOVR , Receive data buffer overrun" "No overrun,Overrun"
|
|
newline
|
|
bitfld.long 0x00 29. " TXFULL , Transmit data buffer full" "Not full,Full"
|
|
bitfld.long 0x00 28. " BITERR , Bit error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 27. " DESYNC , Desynchronization of slave device" "No,Yes"
|
|
bitfld.long 0x00 26. " PARITYERR , Parity error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 25. " TIMEOUT , Time-out because of non-activation of ENA pin" "No timeout,Timeout"
|
|
bitfld.long 0x00 24. " DLENERR , Data length error flag" "No,Yes"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " LCSNR , Last chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " RXDATA , SPI receive data"
|
|
rgroup.long (0x124+0x200)++0x03
|
|
line.long 0x00 "RXRAM, Multi-buffer RAM Receive Buffer Register 73"
|
|
bitfld.long 0x00 31. " RXEMPTY , Receive data buffer empty" "Not empty,Empty"
|
|
bitfld.long 0x00 30. " RXOVR , Receive data buffer overrun" "No overrun,Overrun"
|
|
newline
|
|
bitfld.long 0x00 29. " TXFULL , Transmit data buffer full" "Not full,Full"
|
|
bitfld.long 0x00 28. " BITERR , Bit error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 27. " DESYNC , Desynchronization of slave device" "No,Yes"
|
|
bitfld.long 0x00 26. " PARITYERR , Parity error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 25. " TIMEOUT , Time-out because of non-activation of ENA pin" "No timeout,Timeout"
|
|
bitfld.long 0x00 24. " DLENERR , Data length error flag" "No,Yes"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " LCSNR , Last chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " RXDATA , SPI receive data"
|
|
rgroup.long (0x128+0x200)++0x03
|
|
line.long 0x00 "RXRAM, Multi-buffer RAM Receive Buffer Register 74"
|
|
bitfld.long 0x00 31. " RXEMPTY , Receive data buffer empty" "Not empty,Empty"
|
|
bitfld.long 0x00 30. " RXOVR , Receive data buffer overrun" "No overrun,Overrun"
|
|
newline
|
|
bitfld.long 0x00 29. " TXFULL , Transmit data buffer full" "Not full,Full"
|
|
bitfld.long 0x00 28. " BITERR , Bit error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 27. " DESYNC , Desynchronization of slave device" "No,Yes"
|
|
bitfld.long 0x00 26. " PARITYERR , Parity error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 25. " TIMEOUT , Time-out because of non-activation of ENA pin" "No timeout,Timeout"
|
|
bitfld.long 0x00 24. " DLENERR , Data length error flag" "No,Yes"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " LCSNR , Last chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " RXDATA , SPI receive data"
|
|
rgroup.long (0x12C+0x200)++0x03
|
|
line.long 0x00 "RXRAM, Multi-buffer RAM Receive Buffer Register 75"
|
|
bitfld.long 0x00 31. " RXEMPTY , Receive data buffer empty" "Not empty,Empty"
|
|
bitfld.long 0x00 30. " RXOVR , Receive data buffer overrun" "No overrun,Overrun"
|
|
newline
|
|
bitfld.long 0x00 29. " TXFULL , Transmit data buffer full" "Not full,Full"
|
|
bitfld.long 0x00 28. " BITERR , Bit error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 27. " DESYNC , Desynchronization of slave device" "No,Yes"
|
|
bitfld.long 0x00 26. " PARITYERR , Parity error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 25. " TIMEOUT , Time-out because of non-activation of ENA pin" "No timeout,Timeout"
|
|
bitfld.long 0x00 24. " DLENERR , Data length error flag" "No,Yes"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " LCSNR , Last chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " RXDATA , SPI receive data"
|
|
rgroup.long (0x130+0x200)++0x03
|
|
line.long 0x00 "RXRAM, Multi-buffer RAM Receive Buffer Register 76"
|
|
bitfld.long 0x00 31. " RXEMPTY , Receive data buffer empty" "Not empty,Empty"
|
|
bitfld.long 0x00 30. " RXOVR , Receive data buffer overrun" "No overrun,Overrun"
|
|
newline
|
|
bitfld.long 0x00 29. " TXFULL , Transmit data buffer full" "Not full,Full"
|
|
bitfld.long 0x00 28. " BITERR , Bit error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 27. " DESYNC , Desynchronization of slave device" "No,Yes"
|
|
bitfld.long 0x00 26. " PARITYERR , Parity error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 25. " TIMEOUT , Time-out because of non-activation of ENA pin" "No timeout,Timeout"
|
|
bitfld.long 0x00 24. " DLENERR , Data length error flag" "No,Yes"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " LCSNR , Last chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " RXDATA , SPI receive data"
|
|
rgroup.long (0x134+0x200)++0x03
|
|
line.long 0x00 "RXRAM, Multi-buffer RAM Receive Buffer Register 77"
|
|
bitfld.long 0x00 31. " RXEMPTY , Receive data buffer empty" "Not empty,Empty"
|
|
bitfld.long 0x00 30. " RXOVR , Receive data buffer overrun" "No overrun,Overrun"
|
|
newline
|
|
bitfld.long 0x00 29. " TXFULL , Transmit data buffer full" "Not full,Full"
|
|
bitfld.long 0x00 28. " BITERR , Bit error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 27. " DESYNC , Desynchronization of slave device" "No,Yes"
|
|
bitfld.long 0x00 26. " PARITYERR , Parity error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 25. " TIMEOUT , Time-out because of non-activation of ENA pin" "No timeout,Timeout"
|
|
bitfld.long 0x00 24. " DLENERR , Data length error flag" "No,Yes"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " LCSNR , Last chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " RXDATA , SPI receive data"
|
|
rgroup.long (0x138+0x200)++0x03
|
|
line.long 0x00 "RXRAM, Multi-buffer RAM Receive Buffer Register 78"
|
|
bitfld.long 0x00 31. " RXEMPTY , Receive data buffer empty" "Not empty,Empty"
|
|
bitfld.long 0x00 30. " RXOVR , Receive data buffer overrun" "No overrun,Overrun"
|
|
newline
|
|
bitfld.long 0x00 29. " TXFULL , Transmit data buffer full" "Not full,Full"
|
|
bitfld.long 0x00 28. " BITERR , Bit error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 27. " DESYNC , Desynchronization of slave device" "No,Yes"
|
|
bitfld.long 0x00 26. " PARITYERR , Parity error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 25. " TIMEOUT , Time-out because of non-activation of ENA pin" "No timeout,Timeout"
|
|
bitfld.long 0x00 24. " DLENERR , Data length error flag" "No,Yes"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " LCSNR , Last chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " RXDATA , SPI receive data"
|
|
rgroup.long (0x13C+0x200)++0x03
|
|
line.long 0x00 "RXRAM, Multi-buffer RAM Receive Buffer Register 79"
|
|
bitfld.long 0x00 31. " RXEMPTY , Receive data buffer empty" "Not empty,Empty"
|
|
bitfld.long 0x00 30. " RXOVR , Receive data buffer overrun" "No overrun,Overrun"
|
|
newline
|
|
bitfld.long 0x00 29. " TXFULL , Transmit data buffer full" "Not full,Full"
|
|
bitfld.long 0x00 28. " BITERR , Bit error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 27. " DESYNC , Desynchronization of slave device" "No,Yes"
|
|
bitfld.long 0x00 26. " PARITYERR , Parity error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 25. " TIMEOUT , Time-out because of non-activation of ENA pin" "No timeout,Timeout"
|
|
bitfld.long 0x00 24. " DLENERR , Data length error flag" "No,Yes"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " LCSNR , Last chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " RXDATA , SPI receive data"
|
|
else
|
|
tree "Transmit Buffers"
|
|
group.long 0x0++0x03
|
|
line.long 0x00 "BUFFER0,Buffer 0 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x4++0x03
|
|
line.long 0x00 "BUFFER1,Buffer 1 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x8++0x03
|
|
line.long 0x00 "BUFFER2,Buffer 2 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0xC++0x03
|
|
line.long 0x00 "BUFFER3,Buffer 3 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "BUFFER4,Buffer 4 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "BUFFER5,Buffer 5 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "BUFFER6,Buffer 6 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "BUFFER7,Buffer 7 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "BUFFER8,Buffer 8 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "BUFFER9,Buffer 9 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "BUFFER10,Buffer 10 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "BUFFER11,Buffer 11 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "BUFFER12,Buffer 12 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x34++0x03
|
|
line.long 0x00 "BUFFER13,Buffer 13 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x38++0x03
|
|
line.long 0x00 "BUFFER14,Buffer 14 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x3C++0x03
|
|
line.long 0x00 "BUFFER15,Buffer 15 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "BUFFER16,Buffer 16 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x44++0x03
|
|
line.long 0x00 "BUFFER17,Buffer 17 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x48++0x03
|
|
line.long 0x00 "BUFFER18,Buffer 18 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x4C++0x03
|
|
line.long 0x00 "BUFFER19,Buffer 19 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x50++0x03
|
|
line.long 0x00 "BUFFER20,Buffer 20 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x54++0x03
|
|
line.long 0x00 "BUFFER21,Buffer 21 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x58++0x03
|
|
line.long 0x00 "BUFFER22,Buffer 22 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x5C++0x03
|
|
line.long 0x00 "BUFFER23,Buffer 23 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x60++0x03
|
|
line.long 0x00 "BUFFER24,Buffer 24 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x64++0x03
|
|
line.long 0x00 "BUFFER25,Buffer 25 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x68++0x03
|
|
line.long 0x00 "BUFFER26,Buffer 26 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x6C++0x03
|
|
line.long 0x00 "BUFFER27,Buffer 27 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x70++0x03
|
|
line.long 0x00 "BUFFER28,Buffer 28 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x74++0x03
|
|
line.long 0x00 "BUFFER29,Buffer 29 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x78++0x03
|
|
line.long 0x00 "BUFFER30,Buffer 30 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x7C++0x03
|
|
line.long 0x00 "BUFFER31,Buffer 31 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x80++0x03
|
|
line.long 0x00 "BUFFER32,Buffer 32 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x84++0x03
|
|
line.long 0x00 "BUFFER33,Buffer 33 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x88++0x03
|
|
line.long 0x00 "BUFFER34,Buffer 34 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x8C++0x03
|
|
line.long 0x00 "BUFFER35,Buffer 35 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x90++0x03
|
|
line.long 0x00 "BUFFER36,Buffer 36 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x94++0x03
|
|
line.long 0x00 "BUFFER37,Buffer 37 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x98++0x03
|
|
line.long 0x00 "BUFFER38,Buffer 38 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x9C++0x03
|
|
line.long 0x00 "BUFFER39,Buffer 39 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0xA0++0x03
|
|
line.long 0x00 "BUFFER40,Buffer 40 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0xA4++0x03
|
|
line.long 0x00 "BUFFER41,Buffer 41 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0xA8++0x03
|
|
line.long 0x00 "BUFFER42,Buffer 42 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0xAC++0x03
|
|
line.long 0x00 "BUFFER43,Buffer 43 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0xB0++0x03
|
|
line.long 0x00 "BUFFER44,Buffer 44 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0xB4++0x03
|
|
line.long 0x00 "BUFFER45,Buffer 45 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0xB8++0x03
|
|
line.long 0x00 "BUFFER46,Buffer 46 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0xBC++0x03
|
|
line.long 0x00 "BUFFER47,Buffer 47 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0xC0++0x03
|
|
line.long 0x00 "BUFFER48,Buffer 48 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0xC4++0x03
|
|
line.long 0x00 "BUFFER49,Buffer 49 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0xC8++0x03
|
|
line.long 0x00 "BUFFER50,Buffer 50 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0xCC++0x03
|
|
line.long 0x00 "BUFFER51,Buffer 51 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0xD0++0x03
|
|
line.long 0x00 "BUFFER52,Buffer 52 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0xD4++0x03
|
|
line.long 0x00 "BUFFER53,Buffer 53 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0xD8++0x03
|
|
line.long 0x00 "BUFFER54,Buffer 54 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0xDC++0x03
|
|
line.long 0x00 "BUFFER55,Buffer 55 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0xE0++0x03
|
|
line.long 0x00 "BUFFER56,Buffer 56 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0xE4++0x03
|
|
line.long 0x00 "BUFFER57,Buffer 57 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0xE8++0x03
|
|
line.long 0x00 "BUFFER58,Buffer 58 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0xEC++0x03
|
|
line.long 0x00 "BUFFER59,Buffer 59 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0xF0++0x03
|
|
line.long 0x00 "BUFFER60,Buffer 60 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0xF4++0x03
|
|
line.long 0x00 "BUFFER61,Buffer 61 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0xF8++0x03
|
|
line.long 0x00 "BUFFER62,Buffer 62 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0xFC++0x03
|
|
line.long 0x00 "BUFFER63,Buffer 63 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x100++0x03
|
|
line.long 0x00 "BUFFER64,Buffer 64 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x104++0x03
|
|
line.long 0x00 "BUFFER65,Buffer 65 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x108++0x03
|
|
line.long 0x00 "BUFFER66,Buffer 66 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x10C++0x03
|
|
line.long 0x00 "BUFFER67,Buffer 67 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x110++0x03
|
|
line.long 0x00 "BUFFER68,Buffer 68 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x114++0x03
|
|
line.long 0x00 "BUFFER69,Buffer 69 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x118++0x03
|
|
line.long 0x00 "BUFFER70,Buffer 70 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x11C++0x03
|
|
line.long 0x00 "BUFFER71,Buffer 71 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x120++0x03
|
|
line.long 0x00 "BUFFER72,Buffer 72 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x124++0x03
|
|
line.long 0x00 "BUFFER73,Buffer 73 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x128++0x03
|
|
line.long 0x00 "BUFFER74,Buffer 74 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x12C++0x03
|
|
line.long 0x00 "BUFFER75,Buffer 75 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x130++0x03
|
|
line.long 0x00 "BUFFER76,Buffer 76 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x134++0x03
|
|
line.long 0x00 "BUFFER77,Buffer 77 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x138++0x03
|
|
line.long 0x00 "BUFFER78,Buffer 78 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x13C++0x03
|
|
line.long 0x00 "BUFFER79,Buffer 79 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x140++0x03
|
|
line.long 0x00 "BUFFER80,Buffer 80 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x144++0x03
|
|
line.long 0x00 "BUFFER81,Buffer 81 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x148++0x03
|
|
line.long 0x00 "BUFFER82,Buffer 82 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x14C++0x03
|
|
line.long 0x00 "BUFFER83,Buffer 83 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x150++0x03
|
|
line.long 0x00 "BUFFER84,Buffer 84 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x154++0x03
|
|
line.long 0x00 "BUFFER85,Buffer 85 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x158++0x03
|
|
line.long 0x00 "BUFFER86,Buffer 86 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x15C++0x03
|
|
line.long 0x00 "BUFFER87,Buffer 87 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x160++0x03
|
|
line.long 0x00 "BUFFER88,Buffer 88 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x164++0x03
|
|
line.long 0x00 "BUFFER89,Buffer 89 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x168++0x03
|
|
line.long 0x00 "BUFFER90,Buffer 90 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x16C++0x03
|
|
line.long 0x00 "BUFFER91,Buffer 91 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x170++0x03
|
|
line.long 0x00 "BUFFER92,Buffer 92 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x174++0x03
|
|
line.long 0x00 "BUFFER93,Buffer 93 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x178++0x03
|
|
line.long 0x00 "BUFFER94,Buffer 94 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x17C++0x03
|
|
line.long 0x00 "BUFFER95,Buffer 95 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x180++0x03
|
|
line.long 0x00 "BUFFER96,Buffer 96 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x184++0x03
|
|
line.long 0x00 "BUFFER97,Buffer 97 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x188++0x03
|
|
line.long 0x00 "BUFFER98,Buffer 98 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x18C++0x03
|
|
line.long 0x00 "BUFFER99,Buffer 99 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x190++0x03
|
|
line.long 0x00 "BUFFER100,Buffer 100 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x194++0x03
|
|
line.long 0x00 "BUFFER101,Buffer 101 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x198++0x03
|
|
line.long 0x00 "BUFFER102,Buffer 102 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x19C++0x03
|
|
line.long 0x00 "BUFFER103,Buffer 103 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x1A0++0x03
|
|
line.long 0x00 "BUFFER104,Buffer 104 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x1A4++0x03
|
|
line.long 0x00 "BUFFER105,Buffer 105 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x1A8++0x03
|
|
line.long 0x00 "BUFFER106,Buffer 106 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x1AC++0x03
|
|
line.long 0x00 "BUFFER107,Buffer 107 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x1B0++0x03
|
|
line.long 0x00 "BUFFER108,Buffer 108 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x1B4++0x03
|
|
line.long 0x00 "BUFFER109,Buffer 109 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x1B8++0x03
|
|
line.long 0x00 "BUFFER110,Buffer 110 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x1BC++0x03
|
|
line.long 0x00 "BUFFER111,Buffer 111 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x1C0++0x03
|
|
line.long 0x00 "BUFFER112,Buffer 112 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x1C4++0x03
|
|
line.long 0x00 "BUFFER113,Buffer 113 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x1C8++0x03
|
|
line.long 0x00 "BUFFER114,Buffer 114 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x1CC++0x03
|
|
line.long 0x00 "BUFFER115,Buffer 115 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x1D0++0x03
|
|
line.long 0x00 "BUFFER116,Buffer 116 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x1D4++0x03
|
|
line.long 0x00 "BUFFER117,Buffer 117 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x1D8++0x03
|
|
line.long 0x00 "BUFFER118,Buffer 118 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x1DC++0x03
|
|
line.long 0x00 "BUFFER119,Buffer 119 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x1E0++0x03
|
|
line.long 0x00 "BUFFER120,Buffer 120 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x1E4++0x03
|
|
line.long 0x00 "BUFFER121,Buffer 121 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x1E8++0x03
|
|
line.long 0x00 "BUFFER122,Buffer 122 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x1EC++0x03
|
|
line.long 0x00 "BUFFER123,Buffer 123 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x1F0++0x03
|
|
line.long 0x00 "BUFFER124,Buffer 124 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x1F4++0x03
|
|
line.long 0x00 "BUFFER125,Buffer 125 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x1F8++0x03
|
|
line.long 0x00 "BUFFER126,Buffer 126 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x1FC++0x03
|
|
line.long 0x00 "BUFFER127,Buffer 127 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
tree.end
|
|
tree "Receive Buffers"
|
|
hgroup.long (0x0+0x200)++0x03
|
|
hide.long 0x00 "BUFFER0,Buffer 0 Register"
|
|
in
|
|
hgroup.long (0x4+0x200)++0x03
|
|
hide.long 0x00 "BUFFER1,Buffer 1 Register"
|
|
in
|
|
hgroup.long (0x8+0x200)++0x03
|
|
hide.long 0x00 "BUFFER2,Buffer 2 Register"
|
|
in
|
|
hgroup.long (0xC+0x200)++0x03
|
|
hide.long 0x00 "BUFFER3,Buffer 3 Register"
|
|
in
|
|
hgroup.long (0x10+0x200)++0x03
|
|
hide.long 0x00 "BUFFER4,Buffer 4 Register"
|
|
in
|
|
hgroup.long (0x14+0x200)++0x03
|
|
hide.long 0x00 "BUFFER5,Buffer 5 Register"
|
|
in
|
|
hgroup.long (0x18+0x200)++0x03
|
|
hide.long 0x00 "BUFFER6,Buffer 6 Register"
|
|
in
|
|
hgroup.long (0x1C+0x200)++0x03
|
|
hide.long 0x00 "BUFFER7,Buffer 7 Register"
|
|
in
|
|
hgroup.long (0x20+0x200)++0x03
|
|
hide.long 0x00 "BUFFER8,Buffer 8 Register"
|
|
in
|
|
hgroup.long (0x24+0x200)++0x03
|
|
hide.long 0x00 "BUFFER9,Buffer 9 Register"
|
|
in
|
|
hgroup.long (0x28+0x200)++0x03
|
|
hide.long 0x00 "BUFFER10,Buffer 10 Register"
|
|
in
|
|
hgroup.long (0x2C+0x200)++0x03
|
|
hide.long 0x00 "BUFFER11,Buffer 11 Register"
|
|
in
|
|
hgroup.long (0x30+0x200)++0x03
|
|
hide.long 0x00 "BUFFER12,Buffer 12 Register"
|
|
in
|
|
hgroup.long (0x34+0x200)++0x03
|
|
hide.long 0x00 "BUFFER13,Buffer 13 Register"
|
|
in
|
|
hgroup.long (0x38+0x200)++0x03
|
|
hide.long 0x00 "BUFFER14,Buffer 14 Register"
|
|
in
|
|
hgroup.long (0x3C+0x200)++0x03
|
|
hide.long 0x00 "BUFFER15,Buffer 15 Register"
|
|
in
|
|
hgroup.long (0x40+0x200)++0x03
|
|
hide.long 0x00 "BUFFER16,Buffer 16 Register"
|
|
in
|
|
hgroup.long (0x44+0x200)++0x03
|
|
hide.long 0x00 "BUFFER17,Buffer 17 Register"
|
|
in
|
|
hgroup.long (0x48+0x200)++0x03
|
|
hide.long 0x00 "BUFFER18,Buffer 18 Register"
|
|
in
|
|
hgroup.long (0x4C+0x200)++0x03
|
|
hide.long 0x00 "BUFFER19,Buffer 19 Register"
|
|
in
|
|
hgroup.long (0x50+0x200)++0x03
|
|
hide.long 0x00 "BUFFER20,Buffer 20 Register"
|
|
in
|
|
hgroup.long (0x54+0x200)++0x03
|
|
hide.long 0x00 "BUFFER21,Buffer 21 Register"
|
|
in
|
|
hgroup.long (0x58+0x200)++0x03
|
|
hide.long 0x00 "BUFFER22,Buffer 22 Register"
|
|
in
|
|
hgroup.long (0x5C+0x200)++0x03
|
|
hide.long 0x00 "BUFFER23,Buffer 23 Register"
|
|
in
|
|
hgroup.long (0x60+0x200)++0x03
|
|
hide.long 0x00 "BUFFER24,Buffer 24 Register"
|
|
in
|
|
hgroup.long (0x64+0x200)++0x03
|
|
hide.long 0x00 "BUFFER25,Buffer 25 Register"
|
|
in
|
|
hgroup.long (0x68+0x200)++0x03
|
|
hide.long 0x00 "BUFFER26,Buffer 26 Register"
|
|
in
|
|
hgroup.long (0x6C+0x200)++0x03
|
|
hide.long 0x00 "BUFFER27,Buffer 27 Register"
|
|
in
|
|
hgroup.long (0x70+0x200)++0x03
|
|
hide.long 0x00 "BUFFER28,Buffer 28 Register"
|
|
in
|
|
hgroup.long (0x74+0x200)++0x03
|
|
hide.long 0x00 "BUFFER29,Buffer 29 Register"
|
|
in
|
|
hgroup.long (0x78+0x200)++0x03
|
|
hide.long 0x00 "BUFFER30,Buffer 30 Register"
|
|
in
|
|
hgroup.long (0x7C+0x200)++0x03
|
|
hide.long 0x00 "BUFFER31,Buffer 31 Register"
|
|
in
|
|
hgroup.long (0x80+0x200)++0x03
|
|
hide.long 0x00 "BUFFER32,Buffer 32 Register"
|
|
in
|
|
hgroup.long (0x84+0x200)++0x03
|
|
hide.long 0x00 "BUFFER33,Buffer 33 Register"
|
|
in
|
|
hgroup.long (0x88+0x200)++0x03
|
|
hide.long 0x00 "BUFFER34,Buffer 34 Register"
|
|
in
|
|
hgroup.long (0x8C+0x200)++0x03
|
|
hide.long 0x00 "BUFFER35,Buffer 35 Register"
|
|
in
|
|
hgroup.long (0x90+0x200)++0x03
|
|
hide.long 0x00 "BUFFER36,Buffer 36 Register"
|
|
in
|
|
hgroup.long (0x94+0x200)++0x03
|
|
hide.long 0x00 "BUFFER37,Buffer 37 Register"
|
|
in
|
|
hgroup.long (0x98+0x200)++0x03
|
|
hide.long 0x00 "BUFFER38,Buffer 38 Register"
|
|
in
|
|
hgroup.long (0x9C+0x200)++0x03
|
|
hide.long 0x00 "BUFFER39,Buffer 39 Register"
|
|
in
|
|
hgroup.long (0xA0+0x200)++0x03
|
|
hide.long 0x00 "BUFFER40,Buffer 40 Register"
|
|
in
|
|
hgroup.long (0xA4+0x200)++0x03
|
|
hide.long 0x00 "BUFFER41,Buffer 41 Register"
|
|
in
|
|
hgroup.long (0xA8+0x200)++0x03
|
|
hide.long 0x00 "BUFFER42,Buffer 42 Register"
|
|
in
|
|
hgroup.long (0xAC+0x200)++0x03
|
|
hide.long 0x00 "BUFFER43,Buffer 43 Register"
|
|
in
|
|
hgroup.long (0xB0+0x200)++0x03
|
|
hide.long 0x00 "BUFFER44,Buffer 44 Register"
|
|
in
|
|
hgroup.long (0xB4+0x200)++0x03
|
|
hide.long 0x00 "BUFFER45,Buffer 45 Register"
|
|
in
|
|
hgroup.long (0xB8+0x200)++0x03
|
|
hide.long 0x00 "BUFFER46,Buffer 46 Register"
|
|
in
|
|
hgroup.long (0xBC+0x200)++0x03
|
|
hide.long 0x00 "BUFFER47,Buffer 47 Register"
|
|
in
|
|
hgroup.long (0xC0+0x200)++0x03
|
|
hide.long 0x00 "BUFFER48,Buffer 48 Register"
|
|
in
|
|
hgroup.long (0xC4+0x200)++0x03
|
|
hide.long 0x00 "BUFFER49,Buffer 49 Register"
|
|
in
|
|
hgroup.long (0xC8+0x200)++0x03
|
|
hide.long 0x00 "BUFFER50,Buffer 50 Register"
|
|
in
|
|
hgroup.long (0xCC+0x200)++0x03
|
|
hide.long 0x00 "BUFFER51,Buffer 51 Register"
|
|
in
|
|
hgroup.long (0xD0+0x200)++0x03
|
|
hide.long 0x00 "BUFFER52,Buffer 52 Register"
|
|
in
|
|
hgroup.long (0xD4+0x200)++0x03
|
|
hide.long 0x00 "BUFFER53,Buffer 53 Register"
|
|
in
|
|
hgroup.long (0xD8+0x200)++0x03
|
|
hide.long 0x00 "BUFFER54,Buffer 54 Register"
|
|
in
|
|
hgroup.long (0xDC+0x200)++0x03
|
|
hide.long 0x00 "BUFFER55,Buffer 55 Register"
|
|
in
|
|
hgroup.long (0xE0+0x200)++0x03
|
|
hide.long 0x00 "BUFFER56,Buffer 56 Register"
|
|
in
|
|
hgroup.long (0xE4+0x200)++0x03
|
|
hide.long 0x00 "BUFFER57,Buffer 57 Register"
|
|
in
|
|
hgroup.long (0xE8+0x200)++0x03
|
|
hide.long 0x00 "BUFFER58,Buffer 58 Register"
|
|
in
|
|
hgroup.long (0xEC+0x200)++0x03
|
|
hide.long 0x00 "BUFFER59,Buffer 59 Register"
|
|
in
|
|
hgroup.long (0xF0+0x200)++0x03
|
|
hide.long 0x00 "BUFFER60,Buffer 60 Register"
|
|
in
|
|
hgroup.long (0xF4+0x200)++0x03
|
|
hide.long 0x00 "BUFFER61,Buffer 61 Register"
|
|
in
|
|
hgroup.long (0xF8+0x200)++0x03
|
|
hide.long 0x00 "BUFFER62,Buffer 62 Register"
|
|
in
|
|
hgroup.long (0xFC+0x200)++0x03
|
|
hide.long 0x00 "BUFFER63,Buffer 63 Register"
|
|
in
|
|
hgroup.long (0x100+0x200)++0x03
|
|
hide.long 0x00 "BUFFER64,Buffer 64 Register"
|
|
in
|
|
hgroup.long (0x104+0x200)++0x03
|
|
hide.long 0x00 "BUFFER65,Buffer 65 Register"
|
|
in
|
|
hgroup.long (0x108+0x200)++0x03
|
|
hide.long 0x00 "BUFFER66,Buffer 66 Register"
|
|
in
|
|
hgroup.long (0x10C+0x200)++0x03
|
|
hide.long 0x00 "BUFFER67,Buffer 67 Register"
|
|
in
|
|
hgroup.long (0x110+0x200)++0x03
|
|
hide.long 0x00 "BUFFER68,Buffer 68 Register"
|
|
in
|
|
hgroup.long (0x114+0x200)++0x03
|
|
hide.long 0x00 "BUFFER69,Buffer 69 Register"
|
|
in
|
|
hgroup.long (0x118+0x200)++0x03
|
|
hide.long 0x00 "BUFFER70,Buffer 70 Register"
|
|
in
|
|
hgroup.long (0x11C+0x200)++0x03
|
|
hide.long 0x00 "BUFFER71,Buffer 71 Register"
|
|
in
|
|
hgroup.long (0x120+0x200)++0x03
|
|
hide.long 0x00 "BUFFER72,Buffer 72 Register"
|
|
in
|
|
hgroup.long (0x124+0x200)++0x03
|
|
hide.long 0x00 "BUFFER73,Buffer 73 Register"
|
|
in
|
|
hgroup.long (0x128+0x200)++0x03
|
|
hide.long 0x00 "BUFFER74,Buffer 74 Register"
|
|
in
|
|
hgroup.long (0x12C+0x200)++0x03
|
|
hide.long 0x00 "BUFFER75,Buffer 75 Register"
|
|
in
|
|
hgroup.long (0x130+0x200)++0x03
|
|
hide.long 0x00 "BUFFER76,Buffer 76 Register"
|
|
in
|
|
hgroup.long (0x134+0x200)++0x03
|
|
hide.long 0x00 "BUFFER77,Buffer 77 Register"
|
|
in
|
|
hgroup.long (0x138+0x200)++0x03
|
|
hide.long 0x00 "BUFFER78,Buffer 78 Register"
|
|
in
|
|
hgroup.long (0x13C+0x200)++0x03
|
|
hide.long 0x00 "BUFFER79,Buffer 79 Register"
|
|
in
|
|
hgroup.long (0x140+0x200)++0x03
|
|
hide.long 0x00 "BUFFER80,Buffer 80 Register"
|
|
in
|
|
hgroup.long (0x144+0x200)++0x03
|
|
hide.long 0x00 "BUFFER81,Buffer 81 Register"
|
|
in
|
|
hgroup.long (0x148+0x200)++0x03
|
|
hide.long 0x00 "BUFFER82,Buffer 82 Register"
|
|
in
|
|
hgroup.long (0x14C+0x200)++0x03
|
|
hide.long 0x00 "BUFFER83,Buffer 83 Register"
|
|
in
|
|
hgroup.long (0x150+0x200)++0x03
|
|
hide.long 0x00 "BUFFER84,Buffer 84 Register"
|
|
in
|
|
hgroup.long (0x154+0x200)++0x03
|
|
hide.long 0x00 "BUFFER85,Buffer 85 Register"
|
|
in
|
|
hgroup.long (0x158+0x200)++0x03
|
|
hide.long 0x00 "BUFFER86,Buffer 86 Register"
|
|
in
|
|
hgroup.long (0x15C+0x200)++0x03
|
|
hide.long 0x00 "BUFFER87,Buffer 87 Register"
|
|
in
|
|
hgroup.long (0x160+0x200)++0x03
|
|
hide.long 0x00 "BUFFER88,Buffer 88 Register"
|
|
in
|
|
hgroup.long (0x164+0x200)++0x03
|
|
hide.long 0x00 "BUFFER89,Buffer 89 Register"
|
|
in
|
|
hgroup.long (0x168+0x200)++0x03
|
|
hide.long 0x00 "BUFFER90,Buffer 90 Register"
|
|
in
|
|
hgroup.long (0x16C+0x200)++0x03
|
|
hide.long 0x00 "BUFFER91,Buffer 91 Register"
|
|
in
|
|
hgroup.long (0x170+0x200)++0x03
|
|
hide.long 0x00 "BUFFER92,Buffer 92 Register"
|
|
in
|
|
hgroup.long (0x174+0x200)++0x03
|
|
hide.long 0x00 "BUFFER93,Buffer 93 Register"
|
|
in
|
|
hgroup.long (0x178+0x200)++0x03
|
|
hide.long 0x00 "BUFFER94,Buffer 94 Register"
|
|
in
|
|
hgroup.long (0x17C+0x200)++0x03
|
|
hide.long 0x00 "BUFFER95,Buffer 95 Register"
|
|
in
|
|
hgroup.long (0x180+0x200)++0x03
|
|
hide.long 0x00 "BUFFER96,Buffer 96 Register"
|
|
in
|
|
hgroup.long (0x184+0x200)++0x03
|
|
hide.long 0x00 "BUFFER97,Buffer 97 Register"
|
|
in
|
|
hgroup.long (0x188+0x200)++0x03
|
|
hide.long 0x00 "BUFFER98,Buffer 98 Register"
|
|
in
|
|
hgroup.long (0x18C+0x200)++0x03
|
|
hide.long 0x00 "BUFFER99,Buffer 99 Register"
|
|
in
|
|
hgroup.long (0x190+0x200)++0x03
|
|
hide.long 0x00 "BUFFER100,Buffer 100 Register"
|
|
in
|
|
hgroup.long (0x194+0x200)++0x03
|
|
hide.long 0x00 "BUFFER101,Buffer 101 Register"
|
|
in
|
|
hgroup.long (0x198+0x200)++0x03
|
|
hide.long 0x00 "BUFFER102,Buffer 102 Register"
|
|
in
|
|
hgroup.long (0x19C+0x200)++0x03
|
|
hide.long 0x00 "BUFFER103,Buffer 103 Register"
|
|
in
|
|
hgroup.long (0x1A0+0x200)++0x03
|
|
hide.long 0x00 "BUFFER104,Buffer 104 Register"
|
|
in
|
|
hgroup.long (0x1A4+0x200)++0x03
|
|
hide.long 0x00 "BUFFER105,Buffer 105 Register"
|
|
in
|
|
hgroup.long (0x1A8+0x200)++0x03
|
|
hide.long 0x00 "BUFFER106,Buffer 106 Register"
|
|
in
|
|
hgroup.long (0x1AC+0x200)++0x03
|
|
hide.long 0x00 "BUFFER107,Buffer 107 Register"
|
|
in
|
|
hgroup.long (0x1B0+0x200)++0x03
|
|
hide.long 0x00 "BUFFER108,Buffer 108 Register"
|
|
in
|
|
hgroup.long (0x1B4+0x200)++0x03
|
|
hide.long 0x00 "BUFFER109,Buffer 109 Register"
|
|
in
|
|
hgroup.long (0x1B8+0x200)++0x03
|
|
hide.long 0x00 "BUFFER110,Buffer 110 Register"
|
|
in
|
|
hgroup.long (0x1BC+0x200)++0x03
|
|
hide.long 0x00 "BUFFER111,Buffer 111 Register"
|
|
in
|
|
hgroup.long (0x1C0+0x200)++0x03
|
|
hide.long 0x00 "BUFFER112,Buffer 112 Register"
|
|
in
|
|
hgroup.long (0x1C4+0x200)++0x03
|
|
hide.long 0x00 "BUFFER113,Buffer 113 Register"
|
|
in
|
|
hgroup.long (0x1C8+0x200)++0x03
|
|
hide.long 0x00 "BUFFER114,Buffer 114 Register"
|
|
in
|
|
hgroup.long (0x1CC+0x200)++0x03
|
|
hide.long 0x00 "BUFFER115,Buffer 115 Register"
|
|
in
|
|
hgroup.long (0x1D0+0x200)++0x03
|
|
hide.long 0x00 "BUFFER116,Buffer 116 Register"
|
|
in
|
|
hgroup.long (0x1D4+0x200)++0x03
|
|
hide.long 0x00 "BUFFER117,Buffer 117 Register"
|
|
in
|
|
hgroup.long (0x1D8+0x200)++0x03
|
|
hide.long 0x00 "BUFFER118,Buffer 118 Register"
|
|
in
|
|
hgroup.long (0x1DC+0x200)++0x03
|
|
hide.long 0x00 "BUFFER119,Buffer 119 Register"
|
|
in
|
|
hgroup.long (0x1E0+0x200)++0x03
|
|
hide.long 0x00 "BUFFER120,Buffer 120 Register"
|
|
in
|
|
hgroup.long (0x1E4+0x200)++0x03
|
|
hide.long 0x00 "BUFFER121,Buffer 121 Register"
|
|
in
|
|
hgroup.long (0x1E8+0x200)++0x03
|
|
hide.long 0x00 "BUFFER122,Buffer 122 Register"
|
|
in
|
|
hgroup.long (0x1EC+0x200)++0x03
|
|
hide.long 0x00 "BUFFER123,Buffer 123 Register"
|
|
in
|
|
hgroup.long (0x1F0+0x200)++0x03
|
|
hide.long 0x00 "BUFFER124,Buffer 124 Register"
|
|
in
|
|
hgroup.long (0x1F4+0x200)++0x03
|
|
hide.long 0x00 "BUFFER125,Buffer 125 Register"
|
|
in
|
|
hgroup.long (0x1F8+0x200)++0x03
|
|
hide.long 0x00 "BUFFER126,Buffer 126 Register"
|
|
in
|
|
hgroup.long (0x1FC+0x200)++0x03
|
|
hide.long 0x00 "BUFFER127,Buffer 127 Register"
|
|
in
|
|
tree.end
|
|
endif
|
|
sif cpuis("TMS570LS0232")||cpuis("TMS570LS0714*")||cpuis("TMS570LS0914*")
|
|
endian.le
|
|
endif
|
|
width 0xB
|
|
tree.end
|
|
tree "SPI2"
|
|
base ad:0xFFF7F600
|
|
width 17.
|
|
sif cpuis("TMS570LS0232")||cpuis("TMS570LS0714*")||cpuis("TMS570LS0914*")
|
|
endian.be
|
|
endif
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "SPIGCR0,SPI Global Control Register 0"
|
|
bitfld.long 0x00 0. " NRESET ,Reset bit for the module" "No reset,Reset"
|
|
group.long 0x04++0x0F
|
|
line.long 0x00 "SPIGCR1,SPI Global Control Register 1"
|
|
bitfld.long 0x00 24. " SPIEN ,SPI enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " LOOPBACK ,Internal loop-back test mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " POWERDOWN ,SPI state machine enters a power-down state" "No power-down,Power-down"
|
|
newline
|
|
bitfld.long 0x00 1. " CLKMOD ,Clock mode" "External,Internally"
|
|
bitfld.long 0x00 0. " MASTER ,SPISIMO/SPISOMI pin direction determination" "Input/output,Output/input"
|
|
line.long 0x04 "SPIINT0,SPI Interrupt Register"
|
|
bitfld.long 0x04 24. " ENABLEHIGHZ ,SPIENA pin high-impedance enable" "Inactive,Active"
|
|
bitfld.long 0x04 16. " DMAREQEN ,DMA request enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 9. " TXINTENA ,TX interrupt flag enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x04 8. " RXINTENA ,RX interrupt flag enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 6. " RXOVRNINTENA ,Overrun interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 4. " BITERRENA ,Enables interrupt on bit error" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x04 3. " DESYNCENA ,Enables interrupt on desynchronized slave" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " PARERRENA ,Enables interrupt-on-parity-error" "Disabled,Enabled"
|
|
bitfld.long 0x04 1. " TIMEOUTENA ,Enables interrupt on ENA signal time-out" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x04 0. " DLENERRENA ,Data length error interrupt enable" "Disabled,Enabled"
|
|
line.long 0x08 "SPILVL,SPI Interrupt Level Register"
|
|
bitfld.long 0x08 9. " TXINTLVL ,Transmit interrupt level" "INT0,INT1"
|
|
bitfld.long 0x08 8. " RXINTLVL ,Receive interrupt level" "INT0,INT1"
|
|
sif !cpuis("TMS570LS0232")
|
|
bitfld.long 0x08 6. " RXOVRNINTLVL ,Receive overrun interrupt level" "INT0,INT1"
|
|
endif
|
|
newline
|
|
bitfld.long 0x08 4. " BITERRLVL ,Bit error interrupt level" "INT0,INT1"
|
|
bitfld.long 0x08 3. " DESYNCLVL ,Desynchronized slave interrupt level (master mode only)" "INT0,INT1"
|
|
bitfld.long 0x08 2. " PARERRLVL ,Parity error interrupt level" "INT0,INT1"
|
|
newline
|
|
bitfld.long 0x08 1. " TIMEOUTLVL ,SPIENA pin time-out interrupt level" "INT0,INT1"
|
|
bitfld.long 0x08 0. " DLENERRLVL ,Data length error interrupt level (line) select" "INT0,INT1"
|
|
line.long 0x0C "SPIFLG,SPI Flag Register"
|
|
bitfld.long 0x0C 24. " BUFINITACTIVE ,Indicates the status of multi-buffer initialization process" "Completed,Not completed"
|
|
bitfld.long 0x0C 9. " TXINTFLG ,Transmitter-empty interrupt flag" "No interrupt,Interrupt"
|
|
eventfld.long 0x0C 8. " RXINTFLG ,Receiver-full interrupt flag" "No interrupt,Interrupt"
|
|
newline
|
|
eventfld.long 0x0C 6. " RXOVRNINTFLG ,Overrun interrupt enable" "Disabled,Enabled"
|
|
eventfld.long 0x0C 4. " BITERRFLG ,Enables interrupt on bit error" "Disabled,Enabled"
|
|
eventfld.long 0x0C 3. " DESYNCFLG ,Enables interrupt on desynchronized slave" "No interrupt,Interrupt"
|
|
newline
|
|
eventfld.long 0x0C 2. " PARITYERRFLG ,Enables interrupt-on-parity-error" "No error,Error"
|
|
eventfld.long 0x0C 1. " TIMEOUTFLG ,Enables interrupt on ENA signal time-out" "No interrupt,Interrupt"
|
|
eventfld.long 0x0C 0. " DLENERRFLG ,Data length error interrupt enable" "No interrupt,Interrupt"
|
|
group.long 0x14++0x23
|
|
line.long 0x00 "SPIPC0,SPI Pin Control Register 0"
|
|
sif !cpuis("TMS570LS0232")&&!cpuis("TMS570LS0332")&&!cpuis("TMS570LS0432")
|
|
bitfld.long 0x00 31. " SOMIFUN7 ,SPISOMI[7] pin function" "GIO,SPI"
|
|
bitfld.long 0x00 30. " SOMIFUN6 ,SPISOMI[6] pin function" "GIO,SPI"
|
|
bitfld.long 0x00 29. " SOMIFUN5 ,SPISOMI[5] pin function" "GIO,SPI"
|
|
newline
|
|
bitfld.long 0x00 28. " SOMIFUN4 ,SPISOMI[4] pin function" "GIO,SPI"
|
|
bitfld.long 0x00 27. " SOMIFUN3 ,SPISOMI[3] pin function" "GIO,SPI"
|
|
bitfld.long 0x00 26. " SOMIFUN2 ,SPISOMI[2] pin function" "GIO,SPI"
|
|
newline
|
|
bitfld.long 0x00 25. " SOMIFUN1 ,SPISOMI[1] pin function" "GIO,SPI"
|
|
bitfld.long 0x00 24. " SOMIFUN0 ,SPISOMI[0] pin function (mirror of bit 11)" "GIO,SPI"
|
|
bitfld.long 0x00 23. " SIMOFUN7 ,SPISIMO[7] pin function" "GIO,SPI"
|
|
newline
|
|
bitfld.long 0x00 22. " SIMOFUN6 ,SPISIMO[6] pin function" "GIO,SPI"
|
|
bitfld.long 0x00 21. " SIMOFUN5 ,SPISIMO[5] pin function" "GIO,SPI"
|
|
bitfld.long 0x00 20. " SIMOFUN4 ,SPISIMO[4] pin function" "GIO,SPI"
|
|
newline
|
|
bitfld.long 0x00 19. " SIMOFUN3 ,SPISIMO[3] pin function" "GIO,SPI"
|
|
bitfld.long 0x00 18. " SIMOFUN2 ,SPISIMO[2] pin function" "GIO,SPI"
|
|
bitfld.long 0x00 17. " SIMOFUN1 ,SPISIMO[1] pin function" "GIO,SPI"
|
|
newline
|
|
bitfld.long 0x00 16. " SIMOFUN0 ,SPISIMO[0] pin function (mirror of bit 10)" "GIO,SPI"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 11. " SOMIFUN0 ,SPISOMI[0] pin function" "GIO,SPI"
|
|
bitfld.long 0x00 10. " SIMOFUN0 ,SPISIMO[0] pin function" "GIO,SPI"
|
|
newline
|
|
bitfld.long 0x00 9. " CLKFUN ,SPI clock function" "GIO,SPI"
|
|
bitfld.long 0x00 8. " ENAFUN ,SPIENA function" "GIO,SPI"
|
|
bitfld.long 0x00 7. " SCSFUN7 ,SPISCS7 function 7" "GIO,SPI"
|
|
newline
|
|
bitfld.long 0x00 6. " SCSFUN6 ,SPISCS6 function 6" "GIO,SPI"
|
|
bitfld.long 0x00 5. " SCSFUN5 ,SPISCS5 function 5" "GIO,SPI"
|
|
bitfld.long 0x00 4. " SCSFUN4 ,SPISCS4 function 4" "GIO,SPI"
|
|
newline
|
|
bitfld.long 0x00 3. " SCSFUN3 ,SPISCS3 function 3" "GIO,SPI"
|
|
bitfld.long 0x00 2. " SCSFUN2 ,SPISCS2 function 2" "GIO,SPI"
|
|
bitfld.long 0x00 1. " SCSFUN1 ,SPISCS1 function 1" "GIO,SPI"
|
|
newline
|
|
bitfld.long 0x00 0. " SCSFUN0 ,SPISCS0 function 0" "GIO,SPI"
|
|
line.long 0x04 "SPIPC1,SPI Pin Control Register 1"
|
|
bitfld.long 0x04 31. " SOMIDIR7 ,SPISOMI[7] pin direction" "GIO,SPI"
|
|
bitfld.long 0x04 30. " SOMIDIR6 ,SPISOMI[6] pin direction" "GIO,SPI"
|
|
bitfld.long 0x04 29. " SOMIDIR5 ,SPISOMI[5] pin direction" "GIO,SPI"
|
|
newline
|
|
bitfld.long 0x04 28. " SOMIDIR4 ,SPISOMI[4] pin direction" "GIO,SPI"
|
|
bitfld.long 0x04 27. " SOMIDIR3 ,SPISOMI[3] pin direction" "GIO,SPI"
|
|
bitfld.long 0x04 26. " SOMIDIR2 ,SPISOMI[2] pin direction" "GIO,SPI"
|
|
newline
|
|
bitfld.long 0x04 25. " SOMIDIR1 ,SPISOMI[1] pin direction" "GIO,SPI"
|
|
bitfld.long 0x04 24. " SOMIDIR0 ,SPISOMI[0] pin direction (mirror of bit 11)" "GIO,SPI"
|
|
bitfld.long 0x04 23. " SIMODIR7 ,SPISIMO[7] pin direction" "GIO,SPI"
|
|
newline
|
|
bitfld.long 0x04 22. " SIMODIR6 ,SPISIMO[6] pin direction" "GIO,SPI"
|
|
bitfld.long 0x04 21. " SIMODIR5 ,SPISIMO[5] pin direction" "GIO,SPI"
|
|
bitfld.long 0x04 20. " SIMODIR4 ,SPISIMO[4] pin direction" "GIO,SPI"
|
|
newline
|
|
bitfld.long 0x04 19. " SIMODIR3 ,SPISIMO[3] pin direction" "GIO,SPI"
|
|
bitfld.long 0x04 18. " SIMODIR2 ,SPISIMO[2] pin direction" "GIO,SPI"
|
|
bitfld.long 0x04 17. " SIMODIR1 ,SPISIMO[1] pin direction" "GIO,SPI"
|
|
newline
|
|
bitfld.long 0x04 16. " SIMODIR0 ,SPISIMO[0] pin direction (mirror of bit 10)" "GIO,SPI"
|
|
bitfld.long 0x04 11. " SOMIDIR0 ,SPISOMI[0] pin direction" "GIO,SPI"
|
|
bitfld.long 0x04 10. " SIMODIR0 ,SPISIMO[0] pin direction" "GIO,SPI"
|
|
newline
|
|
bitfld.long 0x04 9. " CLKDIR ,SPI clock direction" "GIO,SPI"
|
|
bitfld.long 0x04 8. " ENADIR ,SPIENA direction" "GIO,SPI"
|
|
bitfld.long 0x04 7. " SCSDIR7 ,SPISCS7 direction 7" "GIO,SPI"
|
|
newline
|
|
bitfld.long 0x04 6. " SCSDIR6 ,SPISCS6 direction 6" "GIO,SPI"
|
|
bitfld.long 0x04 5. " SCSDIR5 ,SPISCS5 direction 5" "GIO,SPI"
|
|
bitfld.long 0x04 4. " SCSDIR4 ,SPISCS4 direction 4" "GIO,SPI"
|
|
newline
|
|
bitfld.long 0x04 3. " SCSDIR3 ,SPISCS3 direction 3" "GIO,SPI"
|
|
bitfld.long 0x04 2. " SCSDIR2 ,SPISCS2 direction 2" "GIO,SPI"
|
|
bitfld.long 0x04 1. " SCSDIR1 ,SPISCS1 direction 1" "GIO,SPI"
|
|
newline
|
|
bitfld.long 0x04 0. " SCSDIR0 ,SPISCS0 direction 0" "GIO,SPI"
|
|
line.long 0x08 "SPIPC2,SPI Pin Control Register 2"
|
|
bitfld.long 0x08 31. " SOMIDIN7 ,SPISOMI[7] data in" "0,1"
|
|
bitfld.long 0x08 30. " SOMIDIN6 ,SPISOMI[6] data in" "0,1"
|
|
bitfld.long 0x08 29. " SOMIDIN5 ,SPISOMI[5] data in" "0,1"
|
|
newline
|
|
bitfld.long 0x08 28. " SOMIDIN4 ,SPISOMI[4] data in" "0,1"
|
|
bitfld.long 0x08 27. " SOMIDIN3 ,SPISOMI[3] data in" "0,1"
|
|
bitfld.long 0x08 26. " SOMIDIN2 ,SPISOMI[2] data in" "0,1"
|
|
newline
|
|
bitfld.long 0x08 25. " SOMIDIN1 ,SPISOMI[1] data in" "0,1"
|
|
bitfld.long 0x08 24. " SOMIDIN0 ,SPISOMI[0] data in (mirror of bit 11)" "0,1"
|
|
bitfld.long 0x08 23. " SIMODIN7 ,SPISIMO[7] data in" "0,1"
|
|
newline
|
|
bitfld.long 0x08 22. " SIMODIN6 ,SPISIMO[6] data in" "0,1"
|
|
bitfld.long 0x08 21. " SIMODIN5 ,SPISIMO[5] data in" "0,1"
|
|
bitfld.long 0x08 20. " SIMODIN4 ,SPISIMO[4] data in" "0,1"
|
|
newline
|
|
bitfld.long 0x08 19. " SIMODIN3 ,SPISIMO[3] data in" "0,1"
|
|
bitfld.long 0x08 18. " SIMODIN2 ,SPISIMO[2] data in" "0,1"
|
|
bitfld.long 0x08 17. " SIMODIN1 ,SPISIMO[1] data in" "0,1"
|
|
newline
|
|
bitfld.long 0x08 16. " SIMODIN0 ,SPISIMO[0] data in (mirror of bit 10)" "0,1"
|
|
bitfld.long 0x08 11. " SOMIDIN0 ,SPISOMI[0] data in" "0,1"
|
|
bitfld.long 0x08 10. " SIMODIN0 ,SPISIMO[0] data in" "0,1"
|
|
newline
|
|
bitfld.long 0x08 9. " CLKDIN ,SPI clock data in" "0,1"
|
|
bitfld.long 0x08 8. " ENADIN ,SPIENA data in" "0,1"
|
|
bitfld.long 0x08 7. " SCSDIN7 ,SPISCS7 data in" "0,1"
|
|
newline
|
|
bitfld.long 0x08 6. " SCSDIN6 ,SPISCS6 data in" "0,1"
|
|
bitfld.long 0x08 5. " SCSDIN5 ,SPISCS5 data in" "0,1"
|
|
bitfld.long 0x08 4. " SCSDIN4 ,SPISCS4 data in" "0,1"
|
|
newline
|
|
bitfld.long 0x08 3. " SCSDIN3 ,SPISCS3 data in" "0,1"
|
|
bitfld.long 0x08 2. " SCSDIN2 ,SPISCS2 data in" "0,1"
|
|
bitfld.long 0x08 1. " SCSDIN1 ,SPISCS1 data in" "0,1"
|
|
newline
|
|
bitfld.long 0x08 0. " SCSDIN0 ,SPISCS0 direction 0" "0,1"
|
|
line.long 0x0C "SPIPC3,SPI Pin Control Register 3"
|
|
bitfld.long 0x0C 31. " SOMIDOUT7 ,SPISOMI[7] data out write" "0,1"
|
|
bitfld.long 0x0C 30. " SOMIDOUT6 ,SPISOMI[6] data out write" "0,1"
|
|
bitfld.long 0x0C 29. " SOMIDOUT5 ,SPISOMI[5] data out write" "0,1"
|
|
newline
|
|
bitfld.long 0x0C 28. " SOMIDOUT4 ,SPISOMI[4] data out write" "0,1"
|
|
bitfld.long 0x0C 27. " SOMIDOUT3 ,SPISOMI[3] data out write" "0,1"
|
|
bitfld.long 0x0C 26. " SOMIDOUT2 ,SPISOMI[2] data out write" "0,1"
|
|
newline
|
|
bitfld.long 0x0C 25. " SOMIDOUT1 ,SPISOMI[1] data out write" "0,1"
|
|
bitfld.long 0x0C 24. " SOMIDOUT0 ,SPISOMI[0] data out write (mirror of bit 11)" "0,1"
|
|
bitfld.long 0x0C 23. " SIMODOUT7 ,SPISIMO[7] data out write" "0,1"
|
|
newline
|
|
bitfld.long 0x0C 22. " SIMODOUT6 ,SPISIMO[6] data out write" "0,1"
|
|
bitfld.long 0x0C 21. " SIMODOUT5 ,SPISIMO[5] data out write" "0,1"
|
|
bitfld.long 0x0C 20. " SIMODOUT4 ,SPISIMO[4] data out write" "0,1"
|
|
newline
|
|
bitfld.long 0x0C 19. " SIMODOUT3 ,SPISIMO[3] data out write" "0,1"
|
|
bitfld.long 0x0C 18. " SIMODOUT2 ,SPISIMO[2] data out write" "0,1"
|
|
bitfld.long 0x0C 17. " SIMODOUT1 ,SPISIMO[1] data out write" "0,1"
|
|
newline
|
|
bitfld.long 0x0C 16. " SIMODOUT0 ,SPISIMO[0] data out write (mirror of bit 10)" "0,1"
|
|
bitfld.long 0x0C 11. " SOMIDOUT0 ,SPISOMI[0] data out write" "0,1"
|
|
bitfld.long 0x0C 10. " SIMODOUT0 ,SPISIMO[0] data out write" "0,1"
|
|
newline
|
|
bitfld.long 0x0C 9. " CLKDOUT ,SPI clock data out write" "0,1"
|
|
bitfld.long 0x0C 8. " ENADOUT ,SPIENA data out write" "0,1"
|
|
bitfld.long 0x0C 7. " SCSDOUT7 ,SPISCS7 data out write" "0,1"
|
|
newline
|
|
bitfld.long 0x0C 6. " SCSDOUT6 ,SPISCS6 data out write" "0,1"
|
|
bitfld.long 0x0C 5. " SCSDOUT5 ,SPISCS5 data out write" "0,1"
|
|
bitfld.long 0x0C 4. " SCSDOUT4 ,SPISCS4 data out write" "0,1"
|
|
newline
|
|
bitfld.long 0x0C 3. " SCSDOUT3 ,SPISCS3 data out write" "0,1"
|
|
bitfld.long 0x0C 2. " SCSDOUT2 ,SPISCS2 data out write" "0,1"
|
|
bitfld.long 0x0C 1. " SCSDOUT1 ,SPISCS1 data out write" "0,1"
|
|
newline
|
|
bitfld.long 0x0C 0. " SCSDOUT0 ,SPISCS0 data out write" "0,1"
|
|
line.long 0x10 "SPIPC4,SPI Pin Control Register 4"
|
|
bitfld.long 0x10 31. " SOMISET7 ,SPISOMI[7] data out set" "0,1"
|
|
bitfld.long 0x10 30. " SOMISET6 ,SPISOMI[6] data out set" "0,1"
|
|
bitfld.long 0x10 29. " SOMISET5 ,SPISOMI[5] data out set" "0,1"
|
|
newline
|
|
bitfld.long 0x10 28. " SOMISET4 ,SPISOMI[4] data out set" "0,1"
|
|
bitfld.long 0x10 27. " SOMISET3 ,SPISOMI[3] data out set" "0,1"
|
|
bitfld.long 0x10 26. " SOMISET2 ,SPISOMI[2] data out set" "0,1"
|
|
newline
|
|
bitfld.long 0x10 25. " SOMISET1 ,SPISOMI[1] data out set" "0,1"
|
|
bitfld.long 0x10 24. " SOMISET0 ,SPISOMI[0] data out set (mirror of bit 11)" "0,1"
|
|
bitfld.long 0x10 23. " SIMOSET7 ,SPISIMO[7] data out set" "0,1"
|
|
newline
|
|
bitfld.long 0x10 22. " SIMOSET6 ,SPISIMO[6] data out set" "0,1"
|
|
bitfld.long 0x10 21. " SIMOSET5 ,SPISIMO[5] data out set" "0,1"
|
|
bitfld.long 0x10 20. " SIMOSET4 ,SPISIMO[4] data out set" "0,1"
|
|
newline
|
|
bitfld.long 0x10 19. " SIMOSET3 ,SPISIMO[3] data out set" "0,1"
|
|
bitfld.long 0x10 18. " SIMOSET2 ,SPISIMO[2] data out set" "0,1"
|
|
bitfld.long 0x10 17. " SIMOSET1 ,SPISIMO[1] data out set" "0,1"
|
|
newline
|
|
bitfld.long 0x10 16. " SIMOSET0 ,SPISIMO[0] data out set (mirror of bit 10)" "0,1"
|
|
bitfld.long 0x10 11. " SOMISET0 ,SPISOMI[0] data out set" "0,1"
|
|
bitfld.long 0x10 10. " SIMOSET0 ,SPISIMO[0] data out set" "0,1"
|
|
newline
|
|
bitfld.long 0x10 9. " CLKSET ,SPI clock data out set" "0,1"
|
|
bitfld.long 0x10 8. " ENASET ,SPIENA data out set" "0,1"
|
|
bitfld.long 0x10 7. " SCSSET7 ,SPISCS7 data out set" "0,1"
|
|
newline
|
|
bitfld.long 0x10 6. " SCSSET6 ,SPISCS6 data out set" "0,1"
|
|
bitfld.long 0x10 5. " SCSSET5 ,SPISCS5 data out set" "0,1"
|
|
bitfld.long 0x10 4. " SCSSET4 ,SPISCS4 data out set" "0,1"
|
|
newline
|
|
bitfld.long 0x10 3. " SCSSET3 ,SPISCS3 data out set" "0,1"
|
|
bitfld.long 0x10 2. " SCSSET2 ,SPISCS2 data out set" "0,1"
|
|
bitfld.long 0x10 1. " SCSSET1 ,SPISCS1 data out set" "0,1"
|
|
newline
|
|
bitfld.long 0x10 0. " SCSSET0 ,SPISCS0 data out set" "0,1"
|
|
line.long 0x14 "SPIPC5,SPI Pin Control Register 5"
|
|
bitfld.long 0x14 31. " SOMICLR7 ,SPISOMI[7] data out clear" "0,1"
|
|
bitfld.long 0x14 30. " SOMICLR6 ,SPISOMI[6] data out clear" "0,1"
|
|
bitfld.long 0x14 29. " SOMICLR5 ,SPISOMI[5] data out clear" "0,1"
|
|
newline
|
|
bitfld.long 0x14 28. " SOMICLR4 ,SPISOMI[4] data out clear" "0,1"
|
|
bitfld.long 0x14 27. " SOMICLR3 ,SPISOMI[3] data out clear" "0,1"
|
|
bitfld.long 0x14 26. " SOMICLR2 ,SPISOMI[2] data out clear" "0,1"
|
|
newline
|
|
bitfld.long 0x14 25. " SOMICLR1 ,SPISOMI[1] data out clear" "0,1"
|
|
bitfld.long 0x14 24. " SOMICLR0 ,SPISOMI[0] data out clear (mirror of bit 11)" "0,1"
|
|
bitfld.long 0x14 23. " SIMOCLR7 ,SPISIMO[7] data out clear" "0,1"
|
|
newline
|
|
bitfld.long 0x14 22. " SIMOCLR6 ,SPISIMO[6] data out clear" "0,1"
|
|
bitfld.long 0x14 21. " SIMOCLR5 ,SPISIMO[5] data out clear" "0,1"
|
|
bitfld.long 0x14 20. " SIMOCLR4 ,SPISIMO[4] data out clear" "0,1"
|
|
newline
|
|
bitfld.long 0x14 19. " SIMOCLR3 ,SPISIMO[3] data out clear" "0,1"
|
|
bitfld.long 0x14 18. " SIMOCLR2 ,SPISIMO[2] data out clear" "0,1"
|
|
bitfld.long 0x14 17. " SIMOCLR1 ,SPISIMO[1] data out clear" "0,1"
|
|
newline
|
|
bitfld.long 0x14 16. " SIMOCLR0 ,SPISIMO[0] data out clear (mirror of bit 10)" "0,1"
|
|
bitfld.long 0x14 11. " SOMICLR0 ,SPISOMI[0] data out clear" "0,1"
|
|
bitfld.long 0x14 10. " SIMOCLR0 ,SPISIMO[0] data out clear" "0,1"
|
|
newline
|
|
bitfld.long 0x14 9. " CLKCLR ,SPI clock data out clear" "0,1"
|
|
bitfld.long 0x14 8. " ENACLR ,SPIENA data out clear" "0,1"
|
|
bitfld.long 0x14 7. " SCSCLR7 ,SPISCS7 data out clear" "0,1"
|
|
newline
|
|
bitfld.long 0x14 6. " SCSCLR6 ,SPISCS6 data out clear" "0,1"
|
|
bitfld.long 0x14 5. " SCSCLR5 ,SPISCS5 data out clear" "0,1"
|
|
bitfld.long 0x14 4. " SCSCLR4 ,SPISCS4 data out clear" "0,1"
|
|
newline
|
|
bitfld.long 0x14 3. " SCSCLR3 ,SPISCS3 data out clear" "0,1"
|
|
bitfld.long 0x14 2. " SCSCLR2 ,SPISCS2 data out clear" "0,1"
|
|
bitfld.long 0x14 1. " SCSCLR1 ,SPISCS1 data out clear" "0,1"
|
|
newline
|
|
bitfld.long 0x14 0. " SCSCLR0 ,SPISCS0 data out clear" "0,1"
|
|
line.long 0x18 "SPIPC6,SPI Pin Control Register 6"
|
|
bitfld.long 0x18 31. " SOMIPDR7 ,SPISOMI[7] open drain enable" "Disabled,Enabled"
|
|
bitfld.long 0x18 30. " SOMIPDR6 ,SPISOMI[6] open drain enable" "Disabled,Enabled"
|
|
bitfld.long 0x18 29. " SOMIPDR5 ,SPISOMI[5] open drain enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x18 28. " SOMIPDR4 ,SPISOMI[4] open drain enable" "Disabled,Enabled"
|
|
bitfld.long 0x18 27. " SOMIPDR3 ,SPISOMI[3] open drain enable" "Disabled,Enabled"
|
|
bitfld.long 0x18 26. " SOMIPDR2 ,SPISOMI[2] open drain enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x18 25. " SOMIPDR1 ,SPISOMI[1] open drain enable" "Disabled,Enabled"
|
|
bitfld.long 0x18 24. " SOMIPDR0 ,SPISOMI[0] open drain enable (mirror of bit 11)" "Disabled,Enabled"
|
|
bitfld.long 0x18 23. " SIMOPDR7 ,SPISIMO[7] open drain enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x18 22. " SIMOPDR6 ,SPISIMO[6] open drain enable" "Disabled,Enabled"
|
|
bitfld.long 0x18 21. " SIMOPDR5 ,SPISIMO[5] open drain enable" "Disabled,Enabled"
|
|
bitfld.long 0x18 20. " SIMOPDR4 ,SPISIMO[4] open drain enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x18 19. " SIMOPDR3 ,SPISIMO[3] open drain enable" "Disabled,Enabled"
|
|
bitfld.long 0x18 18. " SIMOPDR2 ,SPISIMO[2] open drain enable" "Disabled,Enabled"
|
|
bitfld.long 0x18 17. " SIMOPDR1 ,SPISIMO[1] open drain enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x18 16. " SIMOPDR0 ,SPISIMO[0] open drain enable (mirror of bit 10)" "Disabled,Enabled"
|
|
bitfld.long 0x18 11. " SOMIPDR0 ,SPISOMI[0] open drain enable" "Disabled,Enabled"
|
|
bitfld.long 0x18 10. " SIMOPDR0 ,SPISIMO[0] open drain enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x18 9. " CLKPDR ,SPI clock open drain enable" "Disabled,Enabled"
|
|
bitfld.long 0x18 8. " ENAPDR ,SPIENA open drain enable" "Disabled,Enabled"
|
|
bitfld.long 0x18 7. " SCSPDR7 ,SPISCS7 open drain enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x18 6. " SCSPDR6 ,SPISCS6 open drain enable" "Disabled,Enabled"
|
|
bitfld.long 0x18 5. " SCSPDR5 ,SPISCS5 open drain enable" "Disabled,Enabled"
|
|
bitfld.long 0x18 4. " SCSPDR4 ,SPISCS4 open drain enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x18 3. " SCSPDR3 ,SPISCS3 open drain enable" "Disabled,Enabled"
|
|
bitfld.long 0x18 2. " SCSPDR2 ,SPISCS2 open drain enable" "Disabled,Enabled"
|
|
bitfld.long 0x18 1. " SCSPDR1 ,SPISCS1 open drain enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x18 0. " SCSPDR0 ,SPISCS0 open drain enable" "Disabled,Enabled"
|
|
line.long 0x1C "SPIPC7,SPI Pin Control Register 7"
|
|
bitfld.long 0x1C 31. " SOMIPDIS7 ,SPISOMI[7] pull control enable/disable" "No,Yes"
|
|
bitfld.long 0x1C 30. " SOMIPDIS6 ,SPISOMI[6] pull control enable/disable" "No,Yes"
|
|
bitfld.long 0x1C 29. " SOMIPDIS5 ,SPISOMI[5] pull control enable/disable" "No,Yes"
|
|
newline
|
|
bitfld.long 0x1C 28. " SOMIPDIS4 ,SPISOMI[4] pull control enable/disable" "No,Yes"
|
|
bitfld.long 0x1C 27. " SOMIPDIS3 ,SPISOMI[3] pull control enable/disable" "No,Yes"
|
|
bitfld.long 0x1C 26. " SOMIPDIS2 ,SPISOMI[2] pull control enable/disable" "No,Yes"
|
|
newline
|
|
bitfld.long 0x1C 25. " SOMIPDIS1 ,SPISOMI[1] pull control enable/disable" "No,Yes"
|
|
bitfld.long 0x1C 24. " SOMIPDIS0 ,SPISOMI[0] pull control enable/disable (mirror of bit 11)" "No,Yes"
|
|
bitfld.long 0x1C 23. " SIMOPDIS7 ,SPISIMO[7] pull control enable/disable" "No,Yes"
|
|
newline
|
|
bitfld.long 0x1C 22. " SIMOPDIS6 ,SPISIMO[6] pull control enable/disable" "No,Yes"
|
|
bitfld.long 0x1C 21. " SIMOPDIS5 ,SPISIMO[5] pull control enable/disable" "No,Yes"
|
|
bitfld.long 0x1C 20. " SIMOPDIS4 ,SPISIMO[4] pull control enable/disable" "No,Yes"
|
|
newline
|
|
bitfld.long 0x1C 19. " SIMOPDIS3 ,SPISIMO[3] pull control enable/disable" "No,Yes"
|
|
bitfld.long 0x1C 18. " SIMOPDIS2 ,SPISIMO[2] pull control enable/disable" "No,Yes"
|
|
bitfld.long 0x1C 17. " SIMOPDIS1 ,SPISIMO[1] pull control enable/disable" "No,Yes"
|
|
newline
|
|
bitfld.long 0x1C 16. " SIMOPDIS0 ,SPISIMO[0] pull control enable/disable (mirror of bit 10)" "No,Yes"
|
|
bitfld.long 0x1C 11. " SOMIPDIS0 ,SPISOMI[0] pull control enable/disable" "No,Yes"
|
|
bitfld.long 0x1C 10. " SIMOPDIS0 ,SPISIMO[0] pull control enable/disable" "No,Yes"
|
|
newline
|
|
bitfld.long 0x1C 9. " CLKPDIS ,SPI clock pull control enable/disable" "No,Yes"
|
|
bitfld.long 0x1C 8. " ENAPDIS ,SPIENA pull control enable/disable" "No,Yes"
|
|
bitfld.long 0x1C 7. " SCSPDIS7 ,SPISCS7 pull control enable/disable" "No,Yes"
|
|
newline
|
|
bitfld.long 0x1C 6. " SCSPDIS6 ,SPISCS6 pull control enable/disable" "No,Yes"
|
|
bitfld.long 0x1C 5. " SCSPDIS5 ,SPISCS5 pull control enable/disable" "No,Yes"
|
|
bitfld.long 0x1C 4. " SCSPDIS4 ,SPISCS4 pull control enable/disable" "No,Yes"
|
|
newline
|
|
bitfld.long 0x1C 3. " SCSPDIS3 ,SPISCS3 pull control enable/disable" "No,Yes"
|
|
bitfld.long 0x1C 2. " SCSPDIS2 ,SPISCS2 pull control enable/disable" "No,Yes"
|
|
bitfld.long 0x1C 1. " SCSPDIS1 ,SPISCS1 pull control enable/disable" "No,Yes"
|
|
newline
|
|
bitfld.long 0x1C 0. " SCSPDIS0 ,SPISCS0 pull control enable/disable" "No,Yes"
|
|
line.long 0x20 "SPIPC8,SPI Pin Control Register 8"
|
|
bitfld.long 0x20 31. " SOMIPSEL7 ,SPISOMI[7] pull select" "Pull down,Pull up"
|
|
bitfld.long 0x20 30. " SOMIPSEL6 ,SPISOMI[6] pull select" "Pull down,Pull up"
|
|
bitfld.long 0x20 29. " SOMIPSEL5 ,SPISOMI[5] pull select" "Pull down,Pull up"
|
|
newline
|
|
bitfld.long 0x20 28. " SOMIPSEL4 ,SPISOMI[4] pull select" "Pull down,Pull up"
|
|
bitfld.long 0x20 27. " SOMIPSEL3 ,SPISOMI[3] pull select" "Pull down,Pull up"
|
|
bitfld.long 0x20 26. " SOMIPSEL2 ,SPISOMI[2] pull select" "Pull down,Pull up"
|
|
newline
|
|
bitfld.long 0x20 25. " SOMIPSEL1 ,SPISOMI[1] pull select" "Pull down,Pull up"
|
|
bitfld.long 0x20 24. " SOMIPSEL0 ,SPISOMI[0] pull select (mirror of bit 11)" "Pull down,Pull up"
|
|
bitfld.long 0x20 23. " SIMOPSEL7 ,SPISIMO[7] pull select" "Pull down,Pull up"
|
|
newline
|
|
bitfld.long 0x20 22. " SIMOPSEL6 ,SPISIMO[6] pull select" "Pull down,Pull up"
|
|
bitfld.long 0x20 21. " SIMOPSEL5 ,SPISIMO[5] pull select" "Pull down,Pull up"
|
|
bitfld.long 0x20 20. " SIMOPSEL4 ,SPISIMO[4] pull select" "Pull down,Pull up"
|
|
newline
|
|
bitfld.long 0x20 19. " SIMOPSEL3 ,SPISIMO[3] pull select" "Pull down,Pull up"
|
|
bitfld.long 0x20 18. " SIMOPSEL2 ,SPISIMO[2] pull select" "Pull down,Pull up"
|
|
bitfld.long 0x20 17. " SIMOPSEL1 ,SPISIMO[1] pull select" "Pull down,Pull up"
|
|
newline
|
|
bitfld.long 0x20 16. " SIMOPSEL0 ,SPISIMO[0] pull select (mirror of bit 10)" "Pull down,Pull up"
|
|
bitfld.long 0x20 11. " SOMIPSEL0 ,SPISOMI[0] pull select" "Pull down,Pull up"
|
|
bitfld.long 0x20 10. " SIMOPSEL0 ,SPISIMO[0] pull select" "Pull down,Pull up"
|
|
newline
|
|
bitfld.long 0x20 9. " CLKPSEL ,SPI clock pull select" "Pull down,Pull up"
|
|
bitfld.long 0x20 8. " ENAPSEL ,SPIENA pull select" "Pull down,Pull up"
|
|
bitfld.long 0x20 7. " SCSPSEL7 ,SPISCS7 pull select" "Pull down,Pull up"
|
|
newline
|
|
bitfld.long 0x20 6. " SCSPSEL6 ,SPISCS6 pull select" "Pull down,Pull up"
|
|
bitfld.long 0x20 5. " SCSPSEL5 ,SPISCS5 pull select" "Pull down,Pull up"
|
|
bitfld.long 0x20 4. " SCSPSEL4 ,SPISCS4 pull select" "Pull down,Pull up"
|
|
newline
|
|
bitfld.long 0x20 3. " SCSPSEL3 ,SPISCS3 pull select" "Pull down,Pull up"
|
|
bitfld.long 0x20 2. " SCSPSEL2 ,SPISCS2 pull select" "Pull down,Pull up"
|
|
bitfld.long 0x20 1. " SCSPSEL1 ,SPISCS1 pull select" "Pull down,Pull up"
|
|
newline
|
|
bitfld.long 0x20 0. " SCSPSEL0 ,SPISCS0 pull select" "Pull down,Pull up"
|
|
group.long 0x38++0x07
|
|
line.long 0x00 "SPIDAT0,SPI Transmit Data Register 0"
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,SPI transmit data"
|
|
line.long 0x04 "SPIDAT1,Transmit Data Register 1"
|
|
bitfld.long 0x04 28. " CSHOLD ,Chip select hold mode" "Inactive,Active"
|
|
bitfld.long 0x04 26. " WDEL ,Enable the delay counter at the end of the current transaction" "No delay,After transaction"
|
|
bitfld.long 0x04 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
newline
|
|
hexmask.long.byte 0x04 16.--23. 1. " CSNR ,Chip select number"
|
|
hexmask.long.word 0x04 0.--15. 1. " TXDATA ,Transfer data"
|
|
hgroup.long 0x40++0x03
|
|
hide.long 0x00 "SPIBUF,SPI Receive Buffer Register"
|
|
in
|
|
rgroup.long 0x44++0x03
|
|
line.long 0x00 "SPIEMU,SPI Emulation Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " EMU_RXDATA ,SPI receive data"
|
|
sif cpuis("TMS570LS0232")||cpuis("TMS570LS0714*")||cpuis("TMS570LS0914*")
|
|
group.long 0x48++0x03
|
|
line.long 0x00 "SPIDELAY,SPI Delay Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " C2TDELAY ,Chip-select-active to transmit-start delay"
|
|
hexmask.long.byte 0x00 16.--23. 1. " T2CDELAY ,Transmit-end-to-chip-select-inactive-delay"
|
|
hexmask.long.byte 0x00 8.--15. 1. " T2EDELAY ,Transmit-data-finished to ENA-pin-inactive time-out"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--7. 1. " C2EDELAY ,Chip-select-active to ENA-signal-active time-out"
|
|
else
|
|
rgroup.long 0x48++0x03
|
|
line.long 0x00 "SPIDELAY,SPI Delay Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " C2TDELAY ,Chip-select-active to transmit-start delay"
|
|
hexmask.long.byte 0x00 16.--23. 1. " T2CDELAY ,Transmit-end-to-chip-select-inactive-delay"
|
|
hexmask.long.byte 0x00 8.--15. 1. " T2EDELAY ,Transmit-data-finished to ENA-pin-inactive time-out"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--7. 1. " C2EDELAY ,Chip-select-active to ENA-signal-active time-out"
|
|
endif
|
|
group.long 0x4C++0x13
|
|
line.long 0x00 "SPIDEF,SPI Default Chip Select Register"
|
|
bitfld.long 0x00 7. " CSDEF7 ,Chip select default pattern 7" "0,1"
|
|
bitfld.long 0x00 6. " CSDEF6 ,Chip select default pattern 6" "0,1"
|
|
bitfld.long 0x00 5. " CSDEF5 ,Chip select default pattern 5" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. " CSDEF4 ,Chip select default pattern 4" "0,1"
|
|
bitfld.long 0x00 3. " CSDEF3 ,Chip select default pattern 3" "0,1"
|
|
bitfld.long 0x00 2. " CSDEF2 ,Chip select default pattern 2" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. " CSDEF1 ,Chip select default pattern 1" "0,1"
|
|
bitfld.long 0x00 0. " CSDEF0 ,Chip select default pattern 0" "0,1"
|
|
line.long 0x4 "SPIFMT0,SPI Data Format Register 0"
|
|
sif (cpuis("TMS570LS0332")||cpuis("TMS570LS0432")||cpuis("TMS570LS1114*")||cpuis("TMS570LS1115*")||cpuis("TMS570LS1224*")||cpuis("TMS570LS1225*")||cpuis("TMS570LS1227*")||cpuis("TMS570LS0232")||cpuis("TMS570LS0714*")||cpuis("TMS570LS0914*"))
|
|
hexmask.long.byte 0x4 24.--31. 1. " WDELAY ,Delay in between transmissions for data format 0"
|
|
else
|
|
bitfld.long 0x4 24.--29. " WDELAY ,Delay in between transmissions for data format 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
endif
|
|
bitfld.long 0x4 23. " PARPOL ,Parity polarity: even or odd" "Even,Odd"
|
|
newline
|
|
bitfld.long 0x4 22. " PARITYENA ,Parity enable for data format 0" "Disabled,Enabled"
|
|
bitfld.long 0x4 21. " WAITENA ,The master waits for the ENA signal from slave for data format 0" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x4 20. " SHIFTDIR ,Shift direction for data format $" "MSB,LSB"
|
|
sif (cpu()==("TMS570LS0332")||cpu()==("TMS570LS0432")||cpuis("TMS570LS1114*")||cpuis("TMS570LS1115*")||cpuis("TMS570LS1224*")||cpuis("TMS570LS1225*")||cpuis("TMS570LS1227*")||cpuis("TMS570LS0232")||cpuis("TMS570LS0714*")||cpuis("TMS570LS0914*"))
|
|
bitfld.long 0x4 19. " HDUPLEX_ENA0 ,Half Duplex transfer mode enable for Data Format 0" "Normal,RX/TX"
|
|
endif
|
|
newline
|
|
bitfld.long 0x4 18. " DISCSTIMERS ,Disable chip-select timers for this format" "No,Yes"
|
|
newline
|
|
bitfld.long 0x4 17. " POLARITY ,SPI data format 0 clock polarity" "Low,High"
|
|
bitfld.long 0x4 16. " PHASE ,SPI data format 0 clock delay" "Disabled,Enabled"
|
|
newline
|
|
hexmask.long.byte 0x4 8.--15. 1. " PRESCALE ,SPI data format 0 prescaler"
|
|
bitfld.long 0x4 0.--4. " CHARLEN ,SPI data format 0 data-word length" ",,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,?..."
|
|
line.long 0x8 "SPIFMT1,SPI Data Format Register 1"
|
|
sif (cpuis("TMS570LS0332")||cpuis("TMS570LS0432")||cpuis("TMS570LS1114*")||cpuis("TMS570LS1115*")||cpuis("TMS570LS1224*")||cpuis("TMS570LS1225*")||cpuis("TMS570LS1227*")||cpuis("TMS570LS0232")||cpuis("TMS570LS0714*")||cpuis("TMS570LS0914*"))
|
|
hexmask.long.byte 0x8 24.--31. 1. " WDELAY ,Delay in between transmissions for data format 1"
|
|
else
|
|
bitfld.long 0x8 24.--29. " WDELAY ,Delay in between transmissions for data format 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
endif
|
|
bitfld.long 0x8 23. " PARPOL ,Parity polarity: even or odd" "Even,Odd"
|
|
newline
|
|
bitfld.long 0x8 22. " PARITYENA ,Parity enable for data format 1" "Disabled,Enabled"
|
|
bitfld.long 0x8 21. " WAITENA ,The master waits for the ENA signal from slave for data format 1" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x8 20. " SHIFTDIR ,Shift direction for data format $" "MSB,LSB"
|
|
sif (cpu()==("TMS570LS0332")||cpu()==("TMS570LS0432")||cpuis("TMS570LS1114*")||cpuis("TMS570LS1115*")||cpuis("TMS570LS1224*")||cpuis("TMS570LS1225*")||cpuis("TMS570LS1227*")||cpuis("TMS570LS0232")||cpuis("TMS570LS0714*")||cpuis("TMS570LS0914*"))
|
|
bitfld.long 0x8 19. " HDUPLEX_ENA1 ,Half Duplex transfer mode enable for Data Format 1" "Normal,RX/TX"
|
|
endif
|
|
newline
|
|
bitfld.long 0x8 18. " DISCSTIMERS ,Disable chip-select timers for this format" "No,Yes"
|
|
newline
|
|
bitfld.long 0x8 17. " POLARITY ,SPI data format 1 clock polarity" "Low,High"
|
|
bitfld.long 0x8 16. " PHASE ,SPI data format 1 clock delay" "Disabled,Enabled"
|
|
newline
|
|
hexmask.long.byte 0x8 8.--15. 1. " PRESCALE ,SPI data format 1 prescaler"
|
|
bitfld.long 0x8 0.--4. " CHARLEN ,SPI data format 1 data-word length" ",,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,?..."
|
|
line.long 0xC "SPIFMT2,SPI Data Format Register 2"
|
|
sif (cpuis("TMS570LS0332")||cpuis("TMS570LS0432")||cpuis("TMS570LS1114*")||cpuis("TMS570LS1115*")||cpuis("TMS570LS1224*")||cpuis("TMS570LS1225*")||cpuis("TMS570LS1227*")||cpuis("TMS570LS0232")||cpuis("TMS570LS0714*")||cpuis("TMS570LS0914*"))
|
|
hexmask.long.byte 0xC 24.--31. 1. " WDELAY ,Delay in between transmissions for data format 2"
|
|
else
|
|
bitfld.long 0xC 24.--29. " WDELAY ,Delay in between transmissions for data format 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
endif
|
|
bitfld.long 0xC 23. " PARPOL ,Parity polarity: even or odd" "Even,Odd"
|
|
newline
|
|
bitfld.long 0xC 22. " PARITYENA ,Parity enable for data format 2" "Disabled,Enabled"
|
|
bitfld.long 0xC 21. " WAITENA ,The master waits for the ENA signal from slave for data format 2" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0xC 20. " SHIFTDIR ,Shift direction for data format $" "MSB,LSB"
|
|
sif (cpu()==("TMS570LS0332")||cpu()==("TMS570LS0432")||cpuis("TMS570LS1114*")||cpuis("TMS570LS1115*")||cpuis("TMS570LS1224*")||cpuis("TMS570LS1225*")||cpuis("TMS570LS1227*")||cpuis("TMS570LS0232")||cpuis("TMS570LS0714*")||cpuis("TMS570LS0914*"))
|
|
bitfld.long 0xC 19. " HDUPLEX_ENA2 ,Half Duplex transfer mode enable for Data Format 2" "Normal,RX/TX"
|
|
endif
|
|
newline
|
|
bitfld.long 0xC 18. " DISCSTIMERS ,Disable chip-select timers for this format" "No,Yes"
|
|
newline
|
|
bitfld.long 0xC 17. " POLARITY ,SPI data format 2 clock polarity" "Low,High"
|
|
bitfld.long 0xC 16. " PHASE ,SPI data format 2 clock delay" "Disabled,Enabled"
|
|
newline
|
|
hexmask.long.byte 0xC 8.--15. 1. " PRESCALE ,SPI data format 2 prescaler"
|
|
bitfld.long 0xC 0.--4. " CHARLEN ,SPI data format 2 data-word length" ",,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,?..."
|
|
line.long 0x10 "SPIFMT3,SPI Data Format Register 3"
|
|
sif (cpuis("TMS570LS0332")||cpuis("TMS570LS0432")||cpuis("TMS570LS1114*")||cpuis("TMS570LS1115*")||cpuis("TMS570LS1224*")||cpuis("TMS570LS1225*")||cpuis("TMS570LS1227*")||cpuis("TMS570LS0232")||cpuis("TMS570LS0714*")||cpuis("TMS570LS0914*"))
|
|
hexmask.long.byte 0x10 24.--31. 1. " WDELAY ,Delay in between transmissions for data format 3"
|
|
else
|
|
bitfld.long 0x10 24.--29. " WDELAY ,Delay in between transmissions for data format 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
endif
|
|
bitfld.long 0x10 23. " PARPOL ,Parity polarity: even or odd" "Even,Odd"
|
|
newline
|
|
bitfld.long 0x10 22. " PARITYENA ,Parity enable for data format 3" "Disabled,Enabled"
|
|
bitfld.long 0x10 21. " WAITENA ,The master waits for the ENA signal from slave for data format 3" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x10 20. " SHIFTDIR ,Shift direction for data format $" "MSB,LSB"
|
|
sif (cpu()==("TMS570LS0332")||cpu()==("TMS570LS0432")||cpuis("TMS570LS1114*")||cpuis("TMS570LS1115*")||cpuis("TMS570LS1224*")||cpuis("TMS570LS1225*")||cpuis("TMS570LS1227*")||cpuis("TMS570LS0232")||cpuis("TMS570LS0714*")||cpuis("TMS570LS0914*"))
|
|
bitfld.long 0x10 19. " HDUPLEX_ENA3 ,Half Duplex transfer mode enable for Data Format 3" "Normal,RX/TX"
|
|
endif
|
|
newline
|
|
bitfld.long 0x10 18. " DISCSTIMERS ,Disable chip-select timers for this format" "No,Yes"
|
|
newline
|
|
bitfld.long 0x10 17. " POLARITY ,SPI data format 3 clock polarity" "Low,High"
|
|
bitfld.long 0x10 16. " PHASE ,SPI data format 3 clock delay" "Disabled,Enabled"
|
|
newline
|
|
hexmask.long.byte 0x10 8.--15. 1. " PRESCALE ,SPI data format 3 prescaler"
|
|
bitfld.long 0x10 0.--4. " CHARLEN ,SPI data format 3 data-word length" ",,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,?..."
|
|
hgroup.long 0x60++0x03
|
|
hide.long 0x00 "TGINTVECT0,SPI Interrupt Vector Register 0 / MibSPI Transfer Group Interrupt Vector Register 0"
|
|
in
|
|
hgroup.long 0x64++0x03
|
|
hide.long 0x00 "TGINTVECT1,SPI Interrupt Vector Register 1 / MibSPI Transfer Group Interrupt Vector Register 1"
|
|
in
|
|
group.long 0x68++0x03
|
|
line.long 0x00 "SPIPC9,SPI Pin Control Register 9"
|
|
bitfld.long 0x00 24. " SOMISRS0 ,SPI2 SOMI[0] slew control" "Fast mode,Slow mode"
|
|
bitfld.long 0x00 16. " SIMOSRS0 ,SPI2 SIMO[0] slew control" "Fast mode,Slow mode"
|
|
bitfld.long 0x00 11. " SOMISRS0 ,SPI2 SOMI[0] slew control" "Fast mode,Slow mode"
|
|
newline
|
|
bitfld.long 0x00 10. " SIMOSRS0 ,SPI2 SIMO[0] slew control" "Fast mode,Slow mode"
|
|
bitfld.long 0x00 9. " CLKSRS ,SPI2 Clock slew control" "Fast mode,Slow mode"
|
|
sif (cpu()!=("TMS570LS0332")&&cpu()!=("TMS570LS0432")&&!cpuis("TMS570LS0232"))
|
|
group.long 0x6C++0x07
|
|
line.long 0x00 "SPIPMCTRL,SPI Parallel/Modulo Mode Control Register"
|
|
bitfld.long 0x00 29. " MODCLKPOL3 ,Modulo mode SPICLK polarity" "Normal,Inverted"
|
|
bitfld.long 0x00 26.--28. " MMODE3 ,SPI/MibSPI data lines " "1,2,3,4,5,6,?..."
|
|
bitfld.long 0x00 24.--25. " PMODE3 ,Parallel mode data lines" "1,2,4,8"
|
|
newline
|
|
bitfld.long 0x00 21. " MODCLKPOL2 ,Modulo mode SPICLK polarity" "Normal,Inverted"
|
|
bitfld.long 0x00 18.--20. " MMODE2 ,SPI/MibSPI data lines " "1,2,3,4,5,6,?..."
|
|
bitfld.long 0x00 16.--17. " PMODE2 ,Parallel mode data lines" "1,2,4,8"
|
|
newline
|
|
bitfld.long 0x00 13. " MODCLKPOL1 ,Modulo mode SPICLK polarity" "Normal,Inverted"
|
|
bitfld.long 0x00 10.--12. " MMODE1 ,SPI/MibSPI data lines " "1,2,3,4,5,6,?..."
|
|
bitfld.long 0x00 8.--9. " PMODE1 ,Parallel mode data lines" "1,2,4,8"
|
|
newline
|
|
bitfld.long 0x00 5. " MODCLKPOL0 ,Modulo mode SPICLK polarity" "Normal,Inverted"
|
|
bitfld.long 0x00 2.--4. " MMODE0 ,SPI/MibSPI data lines " "1,2,3,4,5,6,?..."
|
|
bitfld.long 0x00 0.--1. " PMODE0 ,Parallel mode data lines" "1,2,4,8"
|
|
line.long 0x04 "MIBSPIE,MibSPI Enable Register"
|
|
bitfld.long 0x04 16. " RXRAMACCESS ,Receive-RAM access control" "Not writable,Accessible"
|
|
bitfld.long 0x04 0. " MIBSPIENA ,Multi-buffer mode enable" "Disabled,Enabled"
|
|
elif cpuis("TMS570LS0332")||cpuis("TMS570LS0432")||cpuis("TMS570LS0714*")||cpuis("TMS570LS0914*")||cpuis("TMS570LS0232")
|
|
group.long 0x70++0x03
|
|
line.long 0x00 "MIBSPIE,MibSPI Enable Register"
|
|
bitfld.long 0x00 16. " RXRAMACCESS ,Receive-RAM access control" "Not writable,Accessible"
|
|
bitfld.long 0x00 0. " MIBSPIENA ,Multi-buffer mode enable" "Disabled,Enabled"
|
|
endif
|
|
group.long 0x74++0x0F
|
|
line.long 0x00 "TGITENST,MibSPI Transfer Group Interrupt Enable Set Register"
|
|
bitfld.long 0x00 31. " SETINTENRDY15 ,TG interrupt set (enable) when transfer finished" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " SETINTENRDY14 ,TG interrupt set (enable) when transfer finished" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " SETINTENRDY13 ,TG interrupt set (enable) when transfer finished" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 28. " SETINTENRDY12 ,TG interrupt set (enable) when transfer finished" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " SETINTENRDY11 ,TG interrupt set (enable) when transfer finished" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " SETINTENRDY10 ,TG interrupt set (enable) when transfer finished" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 25. " SETINTENRDY9 ,TG interrupt set (enable) when transfer finished" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " SETINTENRDY8 ,TG interrupt set (enable) when transfer finished" "Disabled,Enabled"
|
|
bitfld.long 0x00 23. " SETINTENRDY7 ,TG interrupt set (enable) when transfer finished" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 22. " SETINTENRDY6 ,TG interrupt set (enable) when transfer finished" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " SETINTENRDY5 ,TG interrupt set (enable) when transfer finished" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " SETINTENRDY4 ,SETTG interrupt set (enable) when transfer finished" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 19. " SETINTENRDY3 ,TG interrupt set (enable) when transfer finished" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SETINTENRDY2 ,TG interrupt set (enable) when transfer finished" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SETINTENRDY1 ,TG interrupt set (enable) when transfer finished" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 16. " SETINTENRDY0 ,TG interrupt set (enable) when transfer finished" "Disabled,Enabled"
|
|
bitfld.long 0x00 15. " SETINTENSUS15 ,TG interrupt set (enabled) when transfer suspended" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " SETINTENSUS14 ,TG interrupt set (enabled) when transfer suspended" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 13. " SETINTENSUS13 ,TG interrupt set (enabled) when transfer suspended" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " SETINTENSUS12 ,TG interrupt set (enabled) when transfer suspended" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " SETINTENSUS11 ,TG interrupt set (enabled) when transfer suspended" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 10. " SETINTENSUS10 ,TG interrupt set (enabled) when transfer suspended" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " SETINTENSUS9 ,TG interrupt set (enabled) when transfer suspended" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " SETINTENSUS8 ,TG interrupt set (enabled) when transfer suspended" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 7. " SETINTENSUS7 ,TG interrupt set (enabled) when transfer suspended" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " SETINTENSUS6 ,TG interrupt set (enabled) when transfer suspended" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " SETINTENSUS5 ,TG interrupt set (enabled) when transfer suspended" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 4. " SETINTENSUS4 ,TG interrupt set (enabled) when transfer suspended" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " SETINTENSUS3 ,TG interrupt set (enabled) when transfer suspended" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " SETINTENSUS2 ,TG interrupt set (enabled) when transfer suspended" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 1. " SETINTENSUS1 ,TG interrupt set (enabled) when transfer suspended" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SETINTENSUS0 ,TG interrupt set (enabled) when transfer suspended" "Disabled,Enabled"
|
|
line.long 0x04 "TGITENCR,MibSPI Transfer Group Interrupt Enable Clear Register"
|
|
bitfld.long 0x04 31. " CLRINTENRDY15 ,TG interrupt clear (disabled) when transfer finished" "Disabled,Enabled"
|
|
bitfld.long 0x04 30. " CLRINTENRDY14 ,TG interrupt clear (disabled) when transfer finished" "Disabled,Enabled"
|
|
bitfld.long 0x04 29. " CLRINTENRDY13 ,TG interrupt clear (disabled) when transfer finished" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x04 28. " CLRINTENRDY12 ,TG interrupt clear (disabled) when transfer finished" "Disabled,Enabled"
|
|
bitfld.long 0x04 27. " CLRINTENRDY11 ,TG interrupt clear (disabled) when transfer finished" "Disabled,Enabled"
|
|
bitfld.long 0x04 26. " CLRINTENRDY10 ,TG interrupt clear (disabled) when transfer finished" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x04 25. " CLRINTENRDY9 ,TG interrupt clear (disabled) when transfer finished" "Disabled,Enabled"
|
|
bitfld.long 0x04 24. " CLRINTENRDY8 ,TG interrupt clear (disabled) when transfer finished" "Disabled,Enabled"
|
|
bitfld.long 0x04 23. " CLRINTENRDY7 ,TG interrupt clear (disabled) when transfer finished" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x04 22. " CLRINTENRDY6 ,TG interrupt clear (disabled) when transfer finished" "Disabled,Enabled"
|
|
bitfld.long 0x04 21. " CLRINTENRDY5 ,TG interrupt clear (disabled) when transfer finished" "Disabled,Enabled"
|
|
bitfld.long 0x04 20. " CLRINTENRDY4 ,TG interrupt clear (disabled) when transfer finished" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x04 19. " CLRINTENRDY3 ,TG interrupt clear (disabled) when transfer finished" "Disabled,Enabled"
|
|
bitfld.long 0x04 18. " CLRINTENRDY2 ,TG interrupt clear (disabled) when transfer finished" "Disabled,Enabled"
|
|
bitfld.long 0x04 17. " CLRINTENRDY1 ,TG interrupt clear (disabled) when transfer finished" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x04 16. " CLRINTENRDY0 ,TG interrupt clear (disabled) when transfer finished" "Disabled,Enabled"
|
|
bitfld.long 0x04 15. " CLRINTENSUS15 ,TG interrupt clear (disabled) when transfer suspended" "Disabled,Enabled"
|
|
bitfld.long 0x04 14. " CLRINTENSUS14 ,TG interrupt clear (disabled) when transfer suspended" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x04 13. " CLRINTENSUS13 ,TG interrupt clear (disabled) when transfer suspended" "Disabled,Enabled"
|
|
bitfld.long 0x04 12. " CLRINTENSUS12 ,TG interrupt clear (disabled) when transfer suspended" "Disabled,Enabled"
|
|
bitfld.long 0x04 11. " CLRINTENSUS11 ,TG interrupt clear (disabled) when transfer suspended" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x04 10. " CLRINTENSUS10 ,TG interrupt clear (disabled) when transfer suspended" "Disabled,Enabled"
|
|
bitfld.long 0x04 9. " CLRINTENSUS9 ,TG interrupt clear (disabled) when transfer suspended" "Disabled,Enabled"
|
|
bitfld.long 0x04 8. " CLRINTENSUS8 ,TG interrupt clear (disabled) when transfer suspended" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x04 7. " CLRINTENSUS7 ,TG interrupt clear (disabled) when transfer suspended" "Disabled,Enabled"
|
|
bitfld.long 0x04 6. " CLRINTENSUS6 ,TG interrupt clear (disabled) when transfer suspended" "Disabled,Enabled"
|
|
bitfld.long 0x04 5. " CLRINTENSUS5 ,TG interrupt clear (disabled) when transfer suspended" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x04 4. " CLRINTENSUS4 ,TG interrupt clear (disabled) when transfer suspended" "Disabled,Enabled"
|
|
bitfld.long 0x04 3. " CLRINTENSUS3 ,TG interrupt clear (disabled) when transfer suspended" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " CLRINTENSUS2 ,TG interrupt clear (disabled) when transfer suspended" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x04 1. " CLRINTENSUS1 ,TG interrupt clear (disabled) when transfer suspended" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " CLRINTENSUS0 ,TG interrupt clear (disabled) when transfer suspended" "Disabled,Enabled"
|
|
line.long 0x08 "TGITLVST,MibSPI Transfer Group Interrupt Level Set Register"
|
|
bitfld.long 0x08 31. " SETINTLVLRDY15 ,Transfer-group completed interrupt level set" "INT0,INT1"
|
|
bitfld.long 0x08 30. " SETINTLVLRDY14 ,Transfer-group completed interrupt level set" "INT0,INT1"
|
|
bitfld.long 0x08 29. " SETINTLVLRDY13 ,Transfer-group completed interrupt level set" "INT0,INT1"
|
|
newline
|
|
bitfld.long 0x08 28. " SETINTLVLRDY12 ,Transfer-group completed interrupt level set" "INT0,INT1"
|
|
bitfld.long 0x08 27. " SETINTLVLRDY11 ,Transfer-group completed interrupt level set" "INT0,INT1"
|
|
bitfld.long 0x08 26. " SETINTLVLRDY10 ,Transfer-group completed interrupt level set" "INT0,INT1"
|
|
newline
|
|
bitfld.long 0x08 25. " SETINTLVLRDY9 ,Transfer-group completed interrupt level set" "INT0,INT1"
|
|
bitfld.long 0x08 24. " SETINTLVLRDY8 ,Transfer-group completed interrupt level set" "INT0,INT1"
|
|
bitfld.long 0x08 23. " SETINTLVLRDY7 ,Transfer-group completed interrupt level set" "INT0,INT1"
|
|
newline
|
|
bitfld.long 0x08 22. " SETINTLVLRDY6 ,Transfer-group completed interrupt level set" "INT0,INT1"
|
|
bitfld.long 0x08 21. " SETINTLVLRDY5 ,Transfer-group completed interrupt level set" "INT0,INT1"
|
|
bitfld.long 0x08 20. " SETINTLVLRDY4 ,Transfer-group completed interrupt level set" "INT0,INT1"
|
|
newline
|
|
bitfld.long 0x08 19. " SETINTLVLRDY3 ,Transfer-group completed interrupt level set" "INT0,INT1"
|
|
bitfld.long 0x08 18. " SETINTLVLRDY2 ,Transfer-group completed interrupt level set" "INT0,INT1"
|
|
bitfld.long 0x08 17. " SETINTLVLRDY1 ,Transfer-group completed interrupt level set" "INT0,INT1"
|
|
newline
|
|
bitfld.long 0x08 16. " SETINTLVLRDY0 ,Transfer-group completed interrupt level set" "INT0,INT1"
|
|
bitfld.long 0x08 15. " SETINTLVLSUS15 ,Transfer-group suspended interrupt level set" "INT0,INT1"
|
|
bitfld.long 0x08 14. " SETINTLVLSUS14 ,Transfer-group suspended interrupt level set" "INT0,INT1"
|
|
newline
|
|
bitfld.long 0x08 13. " SETINTLVLSUS13 ,Transfer-group suspended interrupt level set" "INT0,INT1"
|
|
bitfld.long 0x08 12. " SETINTLVLSUS12 ,Transfer-group suspended interrupt level set" "INT0,INT1"
|
|
bitfld.long 0x08 11. " SETINTLVLSUS11 ,Transfer-group suspended interrupt level set" "INT0,INT1"
|
|
newline
|
|
bitfld.long 0x08 10. " SETINTLVLSUS10 ,Transfer-group suspended interrupt level set" "INT0,INT1"
|
|
bitfld.long 0x08 9. " SETINTLVLSUS9 ,Transfer-group suspended interrupt level set" "INT0,INT1"
|
|
bitfld.long 0x08 8. " SETINTLVLSUS8 ,Transfer-group suspended interrupt level set" "INT0,INT1"
|
|
newline
|
|
bitfld.long 0x08 7. " SETINTLVLSUS7 ,Transfer-group suspended interrupt level set" "INT0,INT1"
|
|
bitfld.long 0x08 6. " SETINTLVLSUS6 ,Transfer-group suspended interrupt level set" "INT0,INT1"
|
|
bitfld.long 0x08 5. " SETINTLVLSUS5 ,Transfer-group suspended interrupt level set" "INT0,INT1"
|
|
newline
|
|
bitfld.long 0x08 4. " SETINTLVLSUS4 ,Transfer-group suspended interrupt level set" "INT0,INT1"
|
|
bitfld.long 0x08 3. " SETINTLVLSUS3 ,Transfer-group suspended interrupt level set" "INT0,INT1"
|
|
bitfld.long 0x08 2. " SETINTLVLSUS2 ,Transfer-group suspended interrupt level set" "INT0,INT1"
|
|
newline
|
|
bitfld.long 0x08 1. " SETINTLVLSUS1 ,Transfer-group suspended interrupt level set" "INT0,INT1"
|
|
bitfld.long 0x08 0. " SETINTLVLSUS0 ,Transfer-group suspended interrupt level set" "INT0,INT1"
|
|
line.long 0x0C "TGITLVCR,MibSPI Transfer Group Interrupt Level Clear Register"
|
|
bitfld.long 0x0C 31. " CLRINTLVLRDY15 ,Transfer-group completed interrupt level clear" "INT0,INT1"
|
|
bitfld.long 0x0C 30. " CLRINTLVLRDY14 ,Transfer-group completed interrupt level clear" "INT0,INT1"
|
|
bitfld.long 0x0C 29. " CLRINTLVLRDY13 ,Transfer-group completed interrupt level clear" "INT0,INT1"
|
|
newline
|
|
bitfld.long 0x0C 28. " CLRINTLVLRDY12 ,Transfer-group completed interrupt level clear" "INT0,INT1"
|
|
bitfld.long 0x0C 27. " CLRINTLVLRDY11 ,Transfer-group completed interrupt level clear" "INT0,INT1"
|
|
bitfld.long 0x0C 26. " CLRINTLVLRDY10 ,Transfer-group completed interrupt level clear" "INT0,INT1"
|
|
newline
|
|
bitfld.long 0x0C 25. " CLRINTLVLRDY9 ,Transfer-group completed interrupt level clear" "INT0,INT1"
|
|
bitfld.long 0x0C 24. " CLRINTLVLRDY8 ,Transfer-group completed interrupt level clear" "INT0,INT1"
|
|
bitfld.long 0x0C 23. " CLRINTLVLRDY7 ,Transfer-group completed interrupt level clear" "INT0,INT1"
|
|
newline
|
|
bitfld.long 0x0C 22. " CLRINTLVLRDY6 ,Transfer-group completed interrupt level clear" "INT0,INT1"
|
|
bitfld.long 0x0C 21. " CLRINTLVLRDY5 ,Transfer-group completed interrupt level clear" "INT0,INT1"
|
|
bitfld.long 0x0C 20. " CLRINTLVLRDY4 ,Transfer-group completed interrupt level clear" "INT0,INT1"
|
|
newline
|
|
bitfld.long 0x0C 19. " CLRINTLVLRDY3 ,Transfer-group completed interrupt level clear" "INT0,INT1"
|
|
bitfld.long 0x0C 18. " CLRINTLVLRDY2 ,Transfer-group completed interrupt level clear" "INT0,INT1"
|
|
bitfld.long 0x0C 17. " CLRINTLVLRDY1 ,Transfer-group completed interrupt level clear" "INT0,INT1"
|
|
newline
|
|
bitfld.long 0x0C 16. " CLRINTLVLRDY0 ,Transfer-group completed interrupt level clear" "INT0,INT1"
|
|
bitfld.long 0x0C 15. " CLRINTLVLSUS15 ,Transfer group suspended interrupt level clear" "INT0,INT1"
|
|
bitfld.long 0x0C 14. " CLRINTLVLSUS14 ,Transfer group suspended interrupt level clear" "INT0,INT1"
|
|
newline
|
|
bitfld.long 0x0C 13. " CLRINTLVLSUS13 ,Transfer group suspended interrupt level clear" "INT0,INT1"
|
|
bitfld.long 0x0C 12. " CLRINTLVLSUS12 ,Transfer group suspended interrupt level clear" "INT0,INT1"
|
|
bitfld.long 0x0C 11. " CLRINTLVLSUS11 ,Transfer group suspended interrupt level clear" "INT0,INT1"
|
|
newline
|
|
bitfld.long 0x0C 10. " CLRINTLVLSUS10 ,Transfer group suspended interrupt level clear" "INT0,INT1"
|
|
bitfld.long 0x0C 9. " CLRINTLVLSUS9 ,Transfer group suspended interrupt level clear" "INT0,INT1"
|
|
bitfld.long 0x0C 8. " CLRINTLVLSUS8 ,Transfer group suspended interrupt level clear" "INT0,INT1"
|
|
newline
|
|
bitfld.long 0x0C 7. " CLRINTLVLSUS7 ,Transfer group suspended interrupt level clear" "INT0,INT1"
|
|
bitfld.long 0x0C 6. " CLRINTLVLSUS6 ,Transfer group suspended interrupt level clear" "INT0,INT1"
|
|
bitfld.long 0x0C 5. " CLRINTLVLSUS5 ,Transfer group suspended interrupt level clear" "INT0,INT1"
|
|
newline
|
|
bitfld.long 0x0C 4. " CLRINTLVLSUS4 ,Transfer group suspended interrupt level clear" "INT0,INT1"
|
|
bitfld.long 0x0C 3. " CLRINTLVLSUS3 ,Transfer group suspended interrupt level clear" "INT0,INT1"
|
|
bitfld.long 0x0C 2. " CLRINTLVLSUS2 ,Transfer group suspended interrupt level clear" "INT0,INT1"
|
|
newline
|
|
bitfld.long 0x0C 1. " CLRINTLVLSUS1 ,Transfer group suspended interrupt level clear" "INT0,INT1"
|
|
bitfld.long 0x0C 0. " CLRINTLVLSUS0 ,Transfer group suspended interrupt level clear" "INT0,INT1"
|
|
group.long 0x84++0x03
|
|
line.long 0x00 "TGITFLG,Transfer Group Interrupt Flag Register"
|
|
sif (cpu()==("TMS570LS0332")||cpu()==("TMS570LS0432")||cpuis("TMS570LS1114*")||cpuis("TMS570LS1115*")||cpuis("TMS570LS1224*")||cpuis("TMS570LS1225*")||cpuis("TMS570LS1227*")||cpuis("TMS570LS0232")||cpuis("TMS570LS0714*")||cpuis("TMS570LS0914*"))
|
|
bitfld.long 0x00 31. " INTFLGRDY[15] ,Transfer-group interrupt flag for a transfer-completed interrupt 15" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " INTFLGRDY[14] ,Transfer-group interrupt flag for a transfer-completed interrupt 14" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 29. " INTFLGRDY[13] ,Transfer-group interrupt flag for a transfer-completed interrupt 13" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " INTFLGRDY[12] ,Transfer-group interrupt flag for a transfer-completed interrupt 12" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 27. " INTFLGRDY[11] ,Transfer-group interrupt flag for a transfer-completed interrupt 11" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " INTFLGRDY[10] ,Transfer-group interrupt flag for a transfer-completed interrupt 10" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 25. " INTFLGRDY[9] ,Transfer-group interrupt flag for a transfer-completed interrupt 9" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " INTFLGRDY[8] ,Transfer-group interrupt flag for a transfer-completed interrupt 8" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 23. " INTFLGRDY[7] ,Transfer-group interrupt flag for a transfer-completed interrupt 7" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " INTFLGRDY[6] ,Transfer-group interrupt flag for a transfer-completed interrupt 6" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 21. " INTFLGRDY[5] ,Transfer-group interrupt flag for a transfer-completed interrupt 5" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " INTFLGRDY[4] ,Transfer-group interrupt flag for a transfer-completed interrupt 4" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 19. " INTFLGRDY[3] ,Transfer-group interrupt flag for a transfer-completed interrupt 3" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " INTFLGRDY[2] ,Transfer-group interrupt flag for a transfer-completed interrupt 2" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 17. " INTFLGRDY[1] ,Transfer-group interrupt flag for a transfer-completed interrupt 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " INTFLGRDY[0] ,Transfer-group interrupt flag for a transfer-completed interrupt 0" "Disabled,Enabled"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 15. " INTFLGSUS[15] ,Transfer-group interrupt flag for a transfer-suspend interrupt 15" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " INTFLGSUS[14] ,Transfer-group interrupt flag for a transfer-suspend interrupt 14" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 13. " INTFLGSUS[13] ,Transfer-group interrupt flag for a transfer-suspend interrupt 13" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " INTFLGSUS[12] ,Transfer-group interrupt flag for a transfer-suspend interrupt 12" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 11. " INTFLGSUS[11] ,Transfer-group interrupt flag for a transfer-suspend interrupt 11" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " INTFLGSUS[10] ,Transfer-group interrupt flag for a transfer-suspend interrupt 10" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 9. " INTFLGSUS[9] ,Transfer-group interrupt flag for a transfer-suspend interrupt 9" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " INTFLGSUS[8] ,Transfer-group interrupt flag for a transfer-suspend interrupt 8" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 7. " INTFLGSUS[7] ,Transfer-group interrupt flag for a transfer-suspend interrupt 7" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " INTFLGSUS[6] ,Transfer-group interrupt flag for a transfer-suspend interrupt 6" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 5. " INTFLGSUS[5] ,Transfer-group interrupt flag for a transfer-suspend interrupt 5" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " INTFLGSUS[4] ,Transfer-group interrupt flag for a transfer-suspend interrupt 4" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 3. " INTFLGSUS[3] ,Transfer-group interrupt flag for a transfer-suspend interrupt 3" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " INTFLGSUS[2] ,Transfer-group interrupt flag for a transfer-suspend interrupt 2" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 1. " INTFLGSUS[1] ,Transfer-group interrupt flag for a transfer-suspend interrupt 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " INTFLGSUS[0] ,Transfer-group interrupt flag for a transfer-suspend interrupt 0" "Disabled,Enabled"
|
|
group.long 0x90++0x47
|
|
line.long 0x00 "TICKCNT,Tick Count Register"
|
|
bitfld.long 0x00 31. " TICKENA ,Tick counter enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " RELOAD ,Pre-load the tick counter" "No effect,Reload"
|
|
bitfld.long 0x00 28.--29. " CLKCTRL ,Tick counter clock source control" "0,1,2,3"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TICKVALUE ,Initial value for the tick counter"
|
|
line.long 0x04 "LTGPEND,Last Transfer Group End Pointer Register"
|
|
bitfld.long 0x04 24.--28. " TGINSERVICE ,The TG number currently being serviced by the sequencer" "No TG,TG0,TG1,TG2,TG3,TG4,TG5,TG6,TG7,TG8,TG9,TG10,TG11,TG12,TG13,TG14,TG15,?..."
|
|
hexmask.long.byte 0x04 8.--14. 1. " LPEND ,Last TG end pointer"
|
|
line.long 0x8 "TG0CTRL,MibSPI Transfer Group Control Register 0"
|
|
bitfld.long 0x8 31. " TGENA ,TG enable" "Disabled,Enabled"
|
|
bitfld.long 0x8 30. " ONESHOT ,Single transfer for TG" "Disabled,Enabled"
|
|
bitfld.long 0x8 29. " PRST ,TG pointer reset mode" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x8 28. " TGTD ,TG triggered" "Not triggered,Triggered"
|
|
bitfld.long 0x8 20.--23. " TRGEVT ,Type of trigger event" "Never,Rising edge,Falling edge,Both edges,,High active,Low-active,Always,?..."
|
|
sif cpuis("TMS570LS0232")||cpuis("TMS570LS0714*")||cpuis("TMS570LS0914*")
|
|
bitfld.long 0x8 16.--19. " TRIGSRC ,Trigger source" "Disabled,EXT0,EXT1,EXT2,EXT3,EXT4,EXT5,EXT6,EXT7,EXT8,EXT9,EXT10,EXT11,EXT12,EXT13,TICK"
|
|
else
|
|
bitfld.long 0x8 16.--19. " TRIGSRC ,Trigger source" "Disabled,GIOA[0],GIOA[1],GIOA[2],GIOA[3],GIOA[4],GIOA[5],GIOA[6],GIOA[7],N2HET1[8],N2HET1[10],N2HET1[12],N2HET1[14],N2HET1[16],N2HET1[18],TICK"
|
|
endif
|
|
newline
|
|
hexmask.long.byte 0x8 8.--14. 0x01 " PSTART ,TG start address"
|
|
hexmask.long.byte 0x8 0.--6. 0x01 " PCURRENT ,Pointer to current buffer"
|
|
line.long 0xC "TG1CTRL,MibSPI Transfer Group Control Register 1"
|
|
bitfld.long 0xC 31. " TGENA ,TG enable" "Disabled,Enabled"
|
|
bitfld.long 0xC 30. " ONESHOT ,Single transfer for TG" "Disabled,Enabled"
|
|
bitfld.long 0xC 29. " PRST ,TG pointer reset mode" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0xC 28. " TGTD ,TG triggered" "Not triggered,Triggered"
|
|
bitfld.long 0xC 20.--23. " TRGEVT ,Type of trigger event" "Never,Rising edge,Falling edge,Both edges,,High active,Low-active,Always,?..."
|
|
sif cpuis("TMS570LS0232")||cpuis("TMS570LS0714*")||cpuis("TMS570LS0914*")
|
|
bitfld.long 0xC 16.--19. " TRIGSRC ,Trigger source" "Disabled,EXT0,EXT1,EXT2,EXT3,EXT4,EXT5,EXT6,EXT7,EXT8,EXT9,EXT10,EXT11,EXT12,EXT13,TICK"
|
|
else
|
|
bitfld.long 0xC 16.--19. " TRIGSRC ,Trigger source" "Disabled,GIOA[0],GIOA[1],GIOA[2],GIOA[3],GIOA[4],GIOA[5],GIOA[6],GIOA[7],N2HET1[8],N2HET1[10],N2HET1[12],N2HET1[14],N2HET1[16],N2HET1[18],TICK"
|
|
endif
|
|
newline
|
|
hexmask.long.byte 0xC 8.--14. 0x01 " PSTART ,TG start address"
|
|
hexmask.long.byte 0xC 0.--6. 0x01 " PCURRENT ,Pointer to current buffer"
|
|
line.long 0x10 "TG2CTRL,MibSPI Transfer Group Control Register 2"
|
|
bitfld.long 0x10 31. " TGENA ,TG enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 30. " ONESHOT ,Single transfer for TG" "Disabled,Enabled"
|
|
bitfld.long 0x10 29. " PRST ,TG pointer reset mode" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x10 28. " TGTD ,TG triggered" "Not triggered,Triggered"
|
|
bitfld.long 0x10 20.--23. " TRGEVT ,Type of trigger event" "Never,Rising edge,Falling edge,Both edges,,High active,Low-active,Always,?..."
|
|
sif cpuis("TMS570LS0232")||cpuis("TMS570LS0714*")||cpuis("TMS570LS0914*")
|
|
bitfld.long 0x10 16.--19. " TRIGSRC ,Trigger source" "Disabled,EXT0,EXT1,EXT2,EXT3,EXT4,EXT5,EXT6,EXT7,EXT8,EXT9,EXT10,EXT11,EXT12,EXT13,TICK"
|
|
else
|
|
bitfld.long 0x10 16.--19. " TRIGSRC ,Trigger source" "Disabled,GIOA[0],GIOA[1],GIOA[2],GIOA[3],GIOA[4],GIOA[5],GIOA[6],GIOA[7],N2HET1[8],N2HET1[10],N2HET1[12],N2HET1[14],N2HET1[16],N2HET1[18],TICK"
|
|
endif
|
|
newline
|
|
hexmask.long.byte 0x10 8.--14. 0x01 " PSTART ,TG start address"
|
|
hexmask.long.byte 0x10 0.--6. 0x01 " PCURRENT ,Pointer to current buffer"
|
|
line.long 0x14 "TG3CTRL,MibSPI Transfer Group Control Register 3"
|
|
bitfld.long 0x14 31. " TGENA ,TG enable" "Disabled,Enabled"
|
|
bitfld.long 0x14 30. " ONESHOT ,Single transfer for TG" "Disabled,Enabled"
|
|
bitfld.long 0x14 29. " PRST ,TG pointer reset mode" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x14 28. " TGTD ,TG triggered" "Not triggered,Triggered"
|
|
bitfld.long 0x14 20.--23. " TRGEVT ,Type of trigger event" "Never,Rising edge,Falling edge,Both edges,,High active,Low-active,Always,?..."
|
|
sif cpuis("TMS570LS0232")||cpuis("TMS570LS0714*")||cpuis("TMS570LS0914*")
|
|
bitfld.long 0x14 16.--19. " TRIGSRC ,Trigger source" "Disabled,EXT0,EXT1,EXT2,EXT3,EXT4,EXT5,EXT6,EXT7,EXT8,EXT9,EXT10,EXT11,EXT12,EXT13,TICK"
|
|
else
|
|
bitfld.long 0x14 16.--19. " TRIGSRC ,Trigger source" "Disabled,GIOA[0],GIOA[1],GIOA[2],GIOA[3],GIOA[4],GIOA[5],GIOA[6],GIOA[7],N2HET1[8],N2HET1[10],N2HET1[12],N2HET1[14],N2HET1[16],N2HET1[18],TICK"
|
|
endif
|
|
newline
|
|
hexmask.long.byte 0x14 8.--14. 0x01 " PSTART ,TG start address"
|
|
hexmask.long.byte 0x14 0.--6. 0x01 " PCURRENT ,Pointer to current buffer"
|
|
line.long 0x18 "TG4CTRL,MibSPI Transfer Group Control Register 4"
|
|
bitfld.long 0x18 31. " TGENA ,TG enable" "Disabled,Enabled"
|
|
bitfld.long 0x18 30. " ONESHOT ,Single transfer for TG" "Disabled,Enabled"
|
|
bitfld.long 0x18 29. " PRST ,TG pointer reset mode" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x18 28. " TGTD ,TG triggered" "Not triggered,Triggered"
|
|
bitfld.long 0x18 20.--23. " TRGEVT ,Type of trigger event" "Never,Rising edge,Falling edge,Both edges,,High active,Low-active,Always,?..."
|
|
sif cpuis("TMS570LS0232")||cpuis("TMS570LS0714*")||cpuis("TMS570LS0914*")
|
|
bitfld.long 0x18 16.--19. " TRIGSRC ,Trigger source" "Disabled,EXT0,EXT1,EXT2,EXT3,EXT4,EXT5,EXT6,EXT7,EXT8,EXT9,EXT10,EXT11,EXT12,EXT13,TICK"
|
|
else
|
|
bitfld.long 0x18 16.--19. " TRIGSRC ,Trigger source" "Disabled,GIOA[0],GIOA[1],GIOA[2],GIOA[3],GIOA[4],GIOA[5],GIOA[6],GIOA[7],N2HET1[8],N2HET1[10],N2HET1[12],N2HET1[14],N2HET1[16],N2HET1[18],TICK"
|
|
endif
|
|
newline
|
|
hexmask.long.byte 0x18 8.--14. 0x01 " PSTART ,TG start address"
|
|
hexmask.long.byte 0x18 0.--6. 0x01 " PCURRENT ,Pointer to current buffer"
|
|
line.long 0x1C "TG5CTRL,MibSPI Transfer Group Control Register 5"
|
|
bitfld.long 0x1C 31. " TGENA ,TG enable" "Disabled,Enabled"
|
|
bitfld.long 0x1C 30. " ONESHOT ,Single transfer for TG" "Disabled,Enabled"
|
|
bitfld.long 0x1C 29. " PRST ,TG pointer reset mode" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x1C 28. " TGTD ,TG triggered" "Not triggered,Triggered"
|
|
bitfld.long 0x1C 20.--23. " TRGEVT ,Type of trigger event" "Never,Rising edge,Falling edge,Both edges,,High active,Low-active,Always,?..."
|
|
sif cpuis("TMS570LS0232")||cpuis("TMS570LS0714*")||cpuis("TMS570LS0914*")
|
|
bitfld.long 0x1C 16.--19. " TRIGSRC ,Trigger source" "Disabled,EXT0,EXT1,EXT2,EXT3,EXT4,EXT5,EXT6,EXT7,EXT8,EXT9,EXT10,EXT11,EXT12,EXT13,TICK"
|
|
else
|
|
bitfld.long 0x1C 16.--19. " TRIGSRC ,Trigger source" "Disabled,GIOA[0],GIOA[1],GIOA[2],GIOA[3],GIOA[4],GIOA[5],GIOA[6],GIOA[7],N2HET1[8],N2HET1[10],N2HET1[12],N2HET1[14],N2HET1[16],N2HET1[18],TICK"
|
|
endif
|
|
newline
|
|
hexmask.long.byte 0x1C 8.--14. 0x01 " PSTART ,TG start address"
|
|
hexmask.long.byte 0x1C 0.--6. 0x01 " PCURRENT ,Pointer to current buffer"
|
|
line.long 0x20 "TG6CTRL,MibSPI Transfer Group Control Register 6"
|
|
bitfld.long 0x20 31. " TGENA ,TG enable" "Disabled,Enabled"
|
|
bitfld.long 0x20 30. " ONESHOT ,Single transfer for TG" "Disabled,Enabled"
|
|
bitfld.long 0x20 29. " PRST ,TG pointer reset mode" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x20 28. " TGTD ,TG triggered" "Not triggered,Triggered"
|
|
bitfld.long 0x20 20.--23. " TRGEVT ,Type of trigger event" "Never,Rising edge,Falling edge,Both edges,,High active,Low-active,Always,?..."
|
|
sif cpuis("TMS570LS0232")||cpuis("TMS570LS0714*")||cpuis("TMS570LS0914*")
|
|
bitfld.long 0x20 16.--19. " TRIGSRC ,Trigger source" "Disabled,EXT0,EXT1,EXT2,EXT3,EXT4,EXT5,EXT6,EXT7,EXT8,EXT9,EXT10,EXT11,EXT12,EXT13,TICK"
|
|
else
|
|
bitfld.long 0x20 16.--19. " TRIGSRC ,Trigger source" "Disabled,GIOA[0],GIOA[1],GIOA[2],GIOA[3],GIOA[4],GIOA[5],GIOA[6],GIOA[7],N2HET1[8],N2HET1[10],N2HET1[12],N2HET1[14],N2HET1[16],N2HET1[18],TICK"
|
|
endif
|
|
newline
|
|
hexmask.long.byte 0x20 8.--14. 0x01 " PSTART ,TG start address"
|
|
hexmask.long.byte 0x20 0.--6. 0x01 " PCURRENT ,Pointer to current buffer"
|
|
line.long 0x24 "TG7CTRL,MibSPI Transfer Group Control Register 7"
|
|
bitfld.long 0x24 31. " TGENA ,TG enable" "Disabled,Enabled"
|
|
bitfld.long 0x24 30. " ONESHOT ,Single transfer for TG" "Disabled,Enabled"
|
|
bitfld.long 0x24 29. " PRST ,TG pointer reset mode" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x24 28. " TGTD ,TG triggered" "Not triggered,Triggered"
|
|
bitfld.long 0x24 20.--23. " TRGEVT ,Type of trigger event" "Never,Rising edge,Falling edge,Both edges,,High active,Low-active,Always,?..."
|
|
sif cpuis("TMS570LS0232")||cpuis("TMS570LS0714*")||cpuis("TMS570LS0914*")
|
|
bitfld.long 0x24 16.--19. " TRIGSRC ,Trigger source" "Disabled,EXT0,EXT1,EXT2,EXT3,EXT4,EXT5,EXT6,EXT7,EXT8,EXT9,EXT10,EXT11,EXT12,EXT13,TICK"
|
|
else
|
|
bitfld.long 0x24 16.--19. " TRIGSRC ,Trigger source" "Disabled,GIOA[0],GIOA[1],GIOA[2],GIOA[3],GIOA[4],GIOA[5],GIOA[6],GIOA[7],N2HET1[8],N2HET1[10],N2HET1[12],N2HET1[14],N2HET1[16],N2HET1[18],TICK"
|
|
endif
|
|
newline
|
|
hexmask.long.byte 0x24 8.--14. 0x01 " PSTART ,TG start address"
|
|
hexmask.long.byte 0x24 0.--6. 0x01 " PCURRENT ,Pointer to current buffer"
|
|
line.long 0x28 "TG8CTRL,MibSPI Transfer Group Control Register 8"
|
|
bitfld.long 0x28 31. " TGENA ,TG enable" "Disabled,Enabled"
|
|
bitfld.long 0x28 30. " ONESHOT ,Single transfer for TG" "Disabled,Enabled"
|
|
bitfld.long 0x28 29. " PRST ,TG pointer reset mode" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x28 28. " TGTD ,TG triggered" "Not triggered,Triggered"
|
|
bitfld.long 0x28 20.--23. " TRGEVT ,Type of trigger event" "Never,Rising edge,Falling edge,Both edges,,High active,Low-active,Always,?..."
|
|
sif cpuis("TMS570LS0232")||cpuis("TMS570LS0714*")||cpuis("TMS570LS0914*")
|
|
bitfld.long 0x28 16.--19. " TRIGSRC ,Trigger source" "Disabled,EXT0,EXT1,EXT2,EXT3,EXT4,EXT5,EXT6,EXT7,EXT8,EXT9,EXT10,EXT11,EXT12,EXT13,TICK"
|
|
else
|
|
bitfld.long 0x28 16.--19. " TRIGSRC ,Trigger source" "Disabled,GIOA[0],GIOA[1],GIOA[2],GIOA[3],GIOA[4],GIOA[5],GIOA[6],GIOA[7],N2HET1[8],N2HET1[10],N2HET1[12],N2HET1[14],N2HET1[16],N2HET1[18],TICK"
|
|
endif
|
|
newline
|
|
hexmask.long.byte 0x28 8.--14. 0x01 " PSTART ,TG start address"
|
|
hexmask.long.byte 0x28 0.--6. 0x01 " PCURRENT ,Pointer to current buffer"
|
|
line.long 0x2C "TG9CTRL,MibSPI Transfer Group Control Register 9"
|
|
bitfld.long 0x2C 31. " TGENA ,TG enable" "Disabled,Enabled"
|
|
bitfld.long 0x2C 30. " ONESHOT ,Single transfer for TG" "Disabled,Enabled"
|
|
bitfld.long 0x2C 29. " PRST ,TG pointer reset mode" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x2C 28. " TGTD ,TG triggered" "Not triggered,Triggered"
|
|
bitfld.long 0x2C 20.--23. " TRGEVT ,Type of trigger event" "Never,Rising edge,Falling edge,Both edges,,High active,Low-active,Always,?..."
|
|
sif cpuis("TMS570LS0232")||cpuis("TMS570LS0714*")||cpuis("TMS570LS0914*")
|
|
bitfld.long 0x2C 16.--19. " TRIGSRC ,Trigger source" "Disabled,EXT0,EXT1,EXT2,EXT3,EXT4,EXT5,EXT6,EXT7,EXT8,EXT9,EXT10,EXT11,EXT12,EXT13,TICK"
|
|
else
|
|
bitfld.long 0x2C 16.--19. " TRIGSRC ,Trigger source" "Disabled,GIOA[0],GIOA[1],GIOA[2],GIOA[3],GIOA[4],GIOA[5],GIOA[6],GIOA[7],N2HET1[8],N2HET1[10],N2HET1[12],N2HET1[14],N2HET1[16],N2HET1[18],TICK"
|
|
endif
|
|
newline
|
|
hexmask.long.byte 0x2C 8.--14. 0x01 " PSTART ,TG start address"
|
|
hexmask.long.byte 0x2C 0.--6. 0x01 " PCURRENT ,Pointer to current buffer"
|
|
line.long 0x30 "TG10CTRL,MibSPI Transfer Group Control Register 10"
|
|
bitfld.long 0x30 31. " TGENA ,TG enable" "Disabled,Enabled"
|
|
bitfld.long 0x30 30. " ONESHOT ,Single transfer for TG" "Disabled,Enabled"
|
|
bitfld.long 0x30 29. " PRST ,TG pointer reset mode" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x30 28. " TGTD ,TG triggered" "Not triggered,Triggered"
|
|
bitfld.long 0x30 20.--23. " TRGEVT ,Type of trigger event" "Never,Rising edge,Falling edge,Both edges,,High active,Low-active,Always,?..."
|
|
sif cpuis("TMS570LS0232")||cpuis("TMS570LS0714*")||cpuis("TMS570LS0914*")
|
|
bitfld.long 0x30 16.--19. " TRIGSRC ,Trigger source" "Disabled,EXT0,EXT1,EXT2,EXT3,EXT4,EXT5,EXT6,EXT7,EXT8,EXT9,EXT10,EXT11,EXT12,EXT13,TICK"
|
|
else
|
|
bitfld.long 0x30 16.--19. " TRIGSRC ,Trigger source" "Disabled,GIOA[0],GIOA[1],GIOA[2],GIOA[3],GIOA[4],GIOA[5],GIOA[6],GIOA[7],N2HET1[8],N2HET1[10],N2HET1[12],N2HET1[14],N2HET1[16],N2HET1[18],TICK"
|
|
endif
|
|
newline
|
|
hexmask.long.byte 0x30 8.--14. 0x01 " PSTART ,TG start address"
|
|
hexmask.long.byte 0x30 0.--6. 0x01 " PCURRENT ,Pointer to current buffer"
|
|
line.long 0x34 "TG11CTRL,MibSPI Transfer Group Control Register 11"
|
|
bitfld.long 0x34 31. " TGENA ,TG enable" "Disabled,Enabled"
|
|
bitfld.long 0x34 30. " ONESHOT ,Single transfer for TG" "Disabled,Enabled"
|
|
bitfld.long 0x34 29. " PRST ,TG pointer reset mode" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x34 28. " TGTD ,TG triggered" "Not triggered,Triggered"
|
|
bitfld.long 0x34 20.--23. " TRGEVT ,Type of trigger event" "Never,Rising edge,Falling edge,Both edges,,High active,Low-active,Always,?..."
|
|
sif cpuis("TMS570LS0232")||cpuis("TMS570LS0714*")||cpuis("TMS570LS0914*")
|
|
bitfld.long 0x34 16.--19. " TRIGSRC ,Trigger source" "Disabled,EXT0,EXT1,EXT2,EXT3,EXT4,EXT5,EXT6,EXT7,EXT8,EXT9,EXT10,EXT11,EXT12,EXT13,TICK"
|
|
else
|
|
bitfld.long 0x34 16.--19. " TRIGSRC ,Trigger source" "Disabled,GIOA[0],GIOA[1],GIOA[2],GIOA[3],GIOA[4],GIOA[5],GIOA[6],GIOA[7],N2HET1[8],N2HET1[10],N2HET1[12],N2HET1[14],N2HET1[16],N2HET1[18],TICK"
|
|
endif
|
|
newline
|
|
hexmask.long.byte 0x34 8.--14. 0x01 " PSTART ,TG start address"
|
|
hexmask.long.byte 0x34 0.--6. 0x01 " PCURRENT ,Pointer to current buffer"
|
|
line.long 0x38 "TG12CTRL,MibSPI Transfer Group Control Register 12"
|
|
bitfld.long 0x38 31. " TGENA ,TG enable" "Disabled,Enabled"
|
|
bitfld.long 0x38 30. " ONESHOT ,Single transfer for TG" "Disabled,Enabled"
|
|
bitfld.long 0x38 29. " PRST ,TG pointer reset mode" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x38 28. " TGTD ,TG triggered" "Not triggered,Triggered"
|
|
bitfld.long 0x38 20.--23. " TRGEVT ,Type of trigger event" "Never,Rising edge,Falling edge,Both edges,,High active,Low-active,Always,?..."
|
|
sif cpuis("TMS570LS0232")||cpuis("TMS570LS0714*")||cpuis("TMS570LS0914*")
|
|
bitfld.long 0x38 16.--19. " TRIGSRC ,Trigger source" "Disabled,EXT0,EXT1,EXT2,EXT3,EXT4,EXT5,EXT6,EXT7,EXT8,EXT9,EXT10,EXT11,EXT12,EXT13,TICK"
|
|
else
|
|
bitfld.long 0x38 16.--19. " TRIGSRC ,Trigger source" "Disabled,GIOA[0],GIOA[1],GIOA[2],GIOA[3],GIOA[4],GIOA[5],GIOA[6],GIOA[7],N2HET1[8],N2HET1[10],N2HET1[12],N2HET1[14],N2HET1[16],N2HET1[18],TICK"
|
|
endif
|
|
newline
|
|
hexmask.long.byte 0x38 8.--14. 0x01 " PSTART ,TG start address"
|
|
hexmask.long.byte 0x38 0.--6. 0x01 " PCURRENT ,Pointer to current buffer"
|
|
line.long 0x3C "TG13CTRL,MibSPI Transfer Group Control Register 13"
|
|
bitfld.long 0x3C 31. " TGENA ,TG enable" "Disabled,Enabled"
|
|
bitfld.long 0x3C 30. " ONESHOT ,Single transfer for TG" "Disabled,Enabled"
|
|
bitfld.long 0x3C 29. " PRST ,TG pointer reset mode" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x3C 28. " TGTD ,TG triggered" "Not triggered,Triggered"
|
|
bitfld.long 0x3C 20.--23. " TRGEVT ,Type of trigger event" "Never,Rising edge,Falling edge,Both edges,,High active,Low-active,Always,?..."
|
|
sif cpuis("TMS570LS0232")||cpuis("TMS570LS0714*")||cpuis("TMS570LS0914*")
|
|
bitfld.long 0x3C 16.--19. " TRIGSRC ,Trigger source" "Disabled,EXT0,EXT1,EXT2,EXT3,EXT4,EXT5,EXT6,EXT7,EXT8,EXT9,EXT10,EXT11,EXT12,EXT13,TICK"
|
|
else
|
|
bitfld.long 0x3C 16.--19. " TRIGSRC ,Trigger source" "Disabled,GIOA[0],GIOA[1],GIOA[2],GIOA[3],GIOA[4],GIOA[5],GIOA[6],GIOA[7],N2HET1[8],N2HET1[10],N2HET1[12],N2HET1[14],N2HET1[16],N2HET1[18],TICK"
|
|
endif
|
|
newline
|
|
hexmask.long.byte 0x3C 8.--14. 0x01 " PSTART ,TG start address"
|
|
hexmask.long.byte 0x3C 0.--6. 0x01 " PCURRENT ,Pointer to current buffer"
|
|
line.long 0x40 "TG14CTRL,MibSPI Transfer Group Control Register 14"
|
|
bitfld.long 0x40 31. " TGENA ,TG enable" "Disabled,Enabled"
|
|
bitfld.long 0x40 30. " ONESHOT ,Single transfer for TG" "Disabled,Enabled"
|
|
bitfld.long 0x40 29. " PRST ,TG pointer reset mode" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x40 28. " TGTD ,TG triggered" "Not triggered,Triggered"
|
|
bitfld.long 0x40 20.--23. " TRGEVT ,Type of trigger event" "Never,Rising edge,Falling edge,Both edges,,High active,Low-active,Always,?..."
|
|
sif cpuis("TMS570LS0232")||cpuis("TMS570LS0714*")||cpuis("TMS570LS0914*")
|
|
bitfld.long 0x40 16.--19. " TRIGSRC ,Trigger source" "Disabled,EXT0,EXT1,EXT2,EXT3,EXT4,EXT5,EXT6,EXT7,EXT8,EXT9,EXT10,EXT11,EXT12,EXT13,TICK"
|
|
else
|
|
bitfld.long 0x40 16.--19. " TRIGSRC ,Trigger source" "Disabled,GIOA[0],GIOA[1],GIOA[2],GIOA[3],GIOA[4],GIOA[5],GIOA[6],GIOA[7],N2HET1[8],N2HET1[10],N2HET1[12],N2HET1[14],N2HET1[16],N2HET1[18],TICK"
|
|
endif
|
|
newline
|
|
hexmask.long.byte 0x40 8.--14. 0x01 " PSTART ,TG start address"
|
|
hexmask.long.byte 0x40 0.--6. 0x01 " PCURRENT ,Pointer to current buffer"
|
|
line.long 0x44 "TG15CTRL,MibSPI Transfer Group Control Register 15"
|
|
bitfld.long 0x44 31. " TGENA ,TG enable" "Disabled,Enabled"
|
|
bitfld.long 0x44 30. " ONESHOT ,Single transfer for TG" "Disabled,Enabled"
|
|
bitfld.long 0x44 29. " PRST ,TG pointer reset mode" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x44 28. " TGTD ,TG triggered" "Not triggered,Triggered"
|
|
bitfld.long 0x44 20.--23. " TRGEVT ,Type of trigger event" "Never,Rising edge,Falling edge,Both edges,,High active,Low-active,Always,?..."
|
|
sif cpuis("TMS570LS0232")||cpuis("TMS570LS0714*")||cpuis("TMS570LS0914*")
|
|
bitfld.long 0x44 16.--19. " TRIGSRC ,Trigger source" "Disabled,EXT0,EXT1,EXT2,EXT3,EXT4,EXT5,EXT6,EXT7,EXT8,EXT9,EXT10,EXT11,EXT12,EXT13,TICK"
|
|
else
|
|
bitfld.long 0x44 16.--19. " TRIGSRC ,Trigger source" "Disabled,GIOA[0],GIOA[1],GIOA[2],GIOA[3],GIOA[4],GIOA[5],GIOA[6],GIOA[7],N2HET1[8],N2HET1[10],N2HET1[12],N2HET1[14],N2HET1[16],N2HET1[18],TICK"
|
|
endif
|
|
newline
|
|
hexmask.long.byte 0x44 8.--14. 0x01 " PSTART ,TG start address"
|
|
hexmask.long.byte 0x44 0.--6. 0x01 " PCURRENT ,Pointer to current buffer"
|
|
sif (cpu()!=("TMS570LS0332")&&cpu()!=("TMS570LS0432")&&!cpuis("TMS570LS0232"))
|
|
group.long 0xD8++0x1F
|
|
line.long 0x0 "DMA0CTRL,MibSPI DMA Channel Control Register 1"
|
|
bitfld.long 0x0 31. " ONESHOT ,Auto-disable of DMA channel after ICOUNT+1 transfers" "0,1"
|
|
hexmask.long.byte 0x0 24.--30. 1. " BUFID ,Buffer utilized for DMA transfer"
|
|
bitfld.long 0x0 20.--23. " RXDMA_MAP ,Each MibSPI DMA channel can be linked to two physical DMA" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x0 16.--19. " TXDMA_MAP ,Each MibSPI DMA channel can be linked to two physical DMA" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x0 15. " RXDMAENA ,Receive data DMA channel enable" "Disabled,Enabled"
|
|
bitfld.long 0x0 14. " TXDMAENA ,Transmit data DMA channel enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x0 13. " NOBRK ,Non-interleaved DMA block transfer" "Not performed,Performed"
|
|
bitfld.long 0x0 8.--12. " ICOUNT ,Initial count of DMA transfers" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32"
|
|
bitfld.long 0x0 6. " COUNTBIT17 ,17th bit of the COUNT field of DMAxCOUNT register" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0.--5. " COUNT ,Actual number of remaining DMA transfers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
line.long 0x4 "DMA1CTRL,MibSPI DMA Channel Control Register 1"
|
|
bitfld.long 0x4 31. " ONESHOT ,Auto-disable of DMA channel after ICOUNT+1 transfers" "0,1"
|
|
hexmask.long.byte 0x4 24.--30. 1. " BUFID ,Buffer utilized for DMA transfer"
|
|
bitfld.long 0x4 20.--23. " RXDMA_MAP ,Each MibSPI DMA channel can be linked to two physical DMA" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x4 16.--19. " TXDMA_MAP ,Each MibSPI DMA channel can be linked to two physical DMA" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x4 15. " RXDMAENA ,Receive data DMA channel enable" "Disabled,Enabled"
|
|
bitfld.long 0x4 14. " TXDMAENA ,Transmit data DMA channel enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x4 13. " NOBRK ,Non-interleaved DMA block transfer" "Not performed,Performed"
|
|
bitfld.long 0x4 8.--12. " ICOUNT ,Initial count of DMA transfers" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32"
|
|
bitfld.long 0x4 6. " COUNTBIT17 ,17th bit of the COUNT field of DMAxCOUNT register" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0.--5. " COUNT ,Actual number of remaining DMA transfers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
line.long 0x8 "DMA2CTRL,MibSPI DMA Channel Control Register 1"
|
|
bitfld.long 0x8 31. " ONESHOT ,Auto-disable of DMA channel after ICOUNT+1 transfers" "0,1"
|
|
hexmask.long.byte 0x8 24.--30. 1. " BUFID ,Buffer utilized for DMA transfer"
|
|
bitfld.long 0x8 20.--23. " RXDMA_MAP ,Each MibSPI DMA channel can be linked to two physical DMA" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x8 16.--19. " TXDMA_MAP ,Each MibSPI DMA channel can be linked to two physical DMA" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x8 15. " RXDMAENA ,Receive data DMA channel enable" "Disabled,Enabled"
|
|
bitfld.long 0x8 14. " TXDMAENA ,Transmit data DMA channel enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x8 13. " NOBRK ,Non-interleaved DMA block transfer" "Not performed,Performed"
|
|
bitfld.long 0x8 8.--12. " ICOUNT ,Initial count of DMA transfers" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32"
|
|
bitfld.long 0x8 6. " COUNTBIT17 ,17th bit of the COUNT field of DMAxCOUNT register" "0,1"
|
|
newline
|
|
bitfld.long 0x8 0.--5. " COUNT ,Actual number of remaining DMA transfers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
line.long 0xC "DMA3CTRL,MibSPI DMA Channel Control Register 1"
|
|
bitfld.long 0xC 31. " ONESHOT ,Auto-disable of DMA channel after ICOUNT+1 transfers" "0,1"
|
|
hexmask.long.byte 0xC 24.--30. 1. " BUFID ,Buffer utilized for DMA transfer"
|
|
bitfld.long 0xC 20.--23. " RXDMA_MAP ,Each MibSPI DMA channel can be linked to two physical DMA" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0xC 16.--19. " TXDMA_MAP ,Each MibSPI DMA channel can be linked to two physical DMA" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0xC 15. " RXDMAENA ,Receive data DMA channel enable" "Disabled,Enabled"
|
|
bitfld.long 0xC 14. " TXDMAENA ,Transmit data DMA channel enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0xC 13. " NOBRK ,Non-interleaved DMA block transfer" "Not performed,Performed"
|
|
bitfld.long 0xC 8.--12. " ICOUNT ,Initial count of DMA transfers" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32"
|
|
bitfld.long 0xC 6. " COUNTBIT17 ,17th bit of the COUNT field of DMAxCOUNT register" "0,1"
|
|
newline
|
|
bitfld.long 0xC 0.--5. " COUNT ,Actual number of remaining DMA transfers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
line.long 0x10 "DMA4CTRL,MibSPI DMA Channel Control Register 1"
|
|
bitfld.long 0x10 31. " ONESHOT ,Auto-disable of DMA channel after ICOUNT+1 transfers" "0,1"
|
|
hexmask.long.byte 0x10 24.--30. 1. " BUFID ,Buffer utilized for DMA transfer"
|
|
bitfld.long 0x10 20.--23. " RXDMA_MAP ,Each MibSPI DMA channel can be linked to two physical DMA" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x10 16.--19. " TXDMA_MAP ,Each MibSPI DMA channel can be linked to two physical DMA" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x10 15. " RXDMAENA ,Receive data DMA channel enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 14. " TXDMAENA ,Transmit data DMA channel enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x10 13. " NOBRK ,Non-interleaved DMA block transfer" "Not performed,Performed"
|
|
bitfld.long 0x10 8.--12. " ICOUNT ,Initial count of DMA transfers" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32"
|
|
bitfld.long 0x10 6. " COUNTBIT17 ,17th bit of the COUNT field of DMAxCOUNT register" "0,1"
|
|
newline
|
|
bitfld.long 0x10 0.--5. " COUNT ,Actual number of remaining DMA transfers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
line.long 0x14 "DMA5CTRL,MibSPI DMA Channel Control Register 1"
|
|
bitfld.long 0x14 31. " ONESHOT ,Auto-disable of DMA channel after ICOUNT+1 transfers" "0,1"
|
|
hexmask.long.byte 0x14 24.--30. 1. " BUFID ,Buffer utilized for DMA transfer"
|
|
bitfld.long 0x14 20.--23. " RXDMA_MAP ,Each MibSPI DMA channel can be linked to two physical DMA" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x14 16.--19. " TXDMA_MAP ,Each MibSPI DMA channel can be linked to two physical DMA" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x14 15. " RXDMAENA ,Receive data DMA channel enable" "Disabled,Enabled"
|
|
bitfld.long 0x14 14. " TXDMAENA ,Transmit data DMA channel enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x14 13. " NOBRK ,Non-interleaved DMA block transfer" "Not performed,Performed"
|
|
bitfld.long 0x14 8.--12. " ICOUNT ,Initial count of DMA transfers" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32"
|
|
bitfld.long 0x14 6. " COUNTBIT17 ,17th bit of the COUNT field of DMAxCOUNT register" "0,1"
|
|
newline
|
|
bitfld.long 0x14 0.--5. " COUNT ,Actual number of remaining DMA transfers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
line.long 0x18 "DMA6CTRL,MibSPI DMA Channel Control Register 1"
|
|
bitfld.long 0x18 31. " ONESHOT ,Auto-disable of DMA channel after ICOUNT+1 transfers" "0,1"
|
|
hexmask.long.byte 0x18 24.--30. 1. " BUFID ,Buffer utilized for DMA transfer"
|
|
bitfld.long 0x18 20.--23. " RXDMA_MAP ,Each MibSPI DMA channel can be linked to two physical DMA" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x18 16.--19. " TXDMA_MAP ,Each MibSPI DMA channel can be linked to two physical DMA" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x18 15. " RXDMAENA ,Receive data DMA channel enable" "Disabled,Enabled"
|
|
bitfld.long 0x18 14. " TXDMAENA ,Transmit data DMA channel enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x18 13. " NOBRK ,Non-interleaved DMA block transfer" "Not performed,Performed"
|
|
bitfld.long 0x18 8.--12. " ICOUNT ,Initial count of DMA transfers" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32"
|
|
bitfld.long 0x18 6. " COUNTBIT17 ,17th bit of the COUNT field of DMAxCOUNT register" "0,1"
|
|
newline
|
|
bitfld.long 0x18 0.--5. " COUNT ,Actual number of remaining DMA transfers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
line.long 0x1C "DMA7CTRL,MibSPI DMA Channel Control Register 1"
|
|
bitfld.long 0x1C 31. " ONESHOT ,Auto-disable of DMA channel after ICOUNT+1 transfers" "0,1"
|
|
hexmask.long.byte 0x1C 24.--30. 1. " BUFID ,Buffer utilized for DMA transfer"
|
|
bitfld.long 0x1C 20.--23. " RXDMA_MAP ,Each MibSPI DMA channel can be linked to two physical DMA" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x1C 16.--19. " TXDMA_MAP ,Each MibSPI DMA channel can be linked to two physical DMA" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x1C 15. " RXDMAENA ,Receive data DMA channel enable" "Disabled,Enabled"
|
|
bitfld.long 0x1C 14. " TXDMAENA ,Transmit data DMA channel enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x1C 13. " NOBRK ,Non-interleaved DMA block transfer" "Not performed,Performed"
|
|
bitfld.long 0x1C 8.--12. " ICOUNT ,Initial count of DMA transfers" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32"
|
|
bitfld.long 0x1C 6. " COUNTBIT17 ,17th bit of the COUNT field of DMAxCOUNT register" "0,1"
|
|
newline
|
|
bitfld.long 0x1C 0.--5. " COUNT ,Actual number of remaining DMA transfers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
group.long 0xF8++0x1F
|
|
line.long 0x0 "DMA0 COUNT,MibSPI DMA0 COUNT Register"
|
|
hexmask.long.word 0x0 16.--31. 1. " ICOUNT0 ,Initial number of DMA transfers"
|
|
hexmask.long.word 0x0 0.--15. 1. " COUNT0 ,The actual number of remaining DMA transfers"
|
|
line.long 0x4 "DMA1 COUNT,MibSPI DMA1 COUNT Register"
|
|
hexmask.long.word 0x4 16.--31. 1. " ICOUNT1 ,Initial number of DMA transfers"
|
|
hexmask.long.word 0x4 0.--15. 1. " COUNT1 ,The actual number of remaining DMA transfers"
|
|
line.long 0x8 "DMA2 COUNT,MibSPI DMA2 COUNT Register"
|
|
hexmask.long.word 0x8 16.--31. 1. " ICOUNT2 ,Initial number of DMA transfers"
|
|
hexmask.long.word 0x8 0.--15. 1. " COUNT2 ,The actual number of remaining DMA transfers"
|
|
line.long 0xC "DMA3 COUNT,MibSPI DMA3 COUNT Register"
|
|
hexmask.long.word 0xC 16.--31. 1. " ICOUNT3 ,Initial number of DMA transfers"
|
|
hexmask.long.word 0xC 0.--15. 1. " COUNT3 ,The actual number of remaining DMA transfers"
|
|
line.long 0x10 "DMA4 COUNT,MibSPI DMA4 COUNT Register"
|
|
hexmask.long.word 0x10 16.--31. 1. " ICOUNT4 ,Initial number of DMA transfers"
|
|
hexmask.long.word 0x10 0.--15. 1. " COUNT4 ,The actual number of remaining DMA transfers"
|
|
line.long 0x14 "DMA5 COUNT,MibSPI DMA5 COUNT Register"
|
|
hexmask.long.word 0x14 16.--31. 1. " ICOUNT5 ,Initial number of DMA transfers"
|
|
hexmask.long.word 0x14 0.--15. 1. " COUNT5 ,The actual number of remaining DMA transfers"
|
|
line.long 0x18 "DMA6 COUNT,MibSPI DMA6 COUNT Register"
|
|
hexmask.long.word 0x18 16.--31. 1. " ICOUNT6 ,Initial number of DMA transfers"
|
|
hexmask.long.word 0x18 0.--15. 1. " COUNT6 ,The actual number of remaining DMA transfers"
|
|
line.long 0x1C "DMA7 COUNT,MibSPI DMA7 COUNT Register"
|
|
hexmask.long.word 0x1C 16.--31. 1. " ICOUNT7 ,Initial number of DMA transfers"
|
|
hexmask.long.word 0x1C 0.--15. 1. " COUNT7 ,The actual number of remaining DMA transfers"
|
|
group.long 0x118++0x03
|
|
line.long 0x00 "DMACNTLEN,MibSPI DMACNTLEN Register"
|
|
bitfld.long 0x00 0. " LARGECOUNT ,Counters select" "DMAxCTRL,DMAxCOUNT"
|
|
endif
|
|
group.long 0x120++0x03
|
|
line.long 0x00 "UERRCTRL,Uncorrectable Parity Error Control Register"
|
|
bitfld.long 0x00 8. " PTESTEN ,Parity memory test enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--3. " EDEN ,Error detection enable" "Enabled,Enabled,Enabled,Enabled,Enabled,Disabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled"
|
|
group.long 0x124++0x03
|
|
line.long 0x00 "UERRSTAT,Uncorrectable Parity Error Status Register"
|
|
eventfld.long 0x00 1. " EDFLG1 ,Uncorrectable parity error detection flag" "Not occurred,Occurred"
|
|
eventfld.long 0x00 0. " EDFLG0 ,Uncorrectable parity error detection flag" "Not occurred,Occurred"
|
|
hgroup.long 0x128++0x03
|
|
hide.long 0x00 "UERRADDR1,Uncorrectable Parity Error Address Register"
|
|
in
|
|
hgroup.long 0x12C++0x03
|
|
hide.long 0x00 "UERRADDR0,Uncorrectable Parity Error Address Register"
|
|
in
|
|
hgroup.long 0x130++0x03
|
|
hide.long 0x00 "RXOVRN_BUF_ADDR,Receive RAM Overrun Buffer Address Register"
|
|
in
|
|
sif cpuis("TMS570LS0714*")||cpuis("TMS570LS0914*")||cpuis("TMS570LS0232")
|
|
if (((per.l.be(ad:0xFFF7F600+0x134))&0x2)==0x2)
|
|
group.long 0x134++0x03
|
|
line.long 0x00 "IOLPBKTSTCR,SPI IO Loopback Test Control Register"
|
|
bitfld.long 0x00 24. " SCSFAILFLG ,Failure on SPISCS pin compare during analog loopback" "Not occurred,Occurred"
|
|
bitfld.long 0x00 20. " CTRL_BITERR ,Controls inducing of BITERR during I/O loopback test mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " CTRL_DESYNC ,Controls inducing of the desync error during I/O loopback test mode" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 18. " CTRL_PARERR ,Controls inducing of parity errors during I/O loopback test mode" "No error,Error"
|
|
bitfld.long 0x00 17. " CTRL_TIMEOUT ,Controls inducing of the timeout error during I/O loopbacK test mode" "No error,Error"
|
|
bitfld.long 0x00 16. " CTRL_DLENERR ,Controls inducing of the data length error during I/O loopback test mode" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 8.--11. " IOLPBKTSTENA ,Module I/O loopback test enable key" "Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Enabled,Disabled,Disabled,Disabled,Disabled,Disabled"
|
|
sif cpuis("TMS570LS0232")
|
|
bitfld.long 0x00 3.--5. " ERRSCSPIN ,Inject error on chip-select pin number" "/SPISCS[0],/SPISCS[1],/SPISCS[2],/SPISCS[3],?..."
|
|
else
|
|
bitfld.long 0x00 3.--5. " ERRSCSPIN ,Inject error on chip-select pin number" "/SPISCS[0],/SPISCS[1],/SPISCS[2],/SPISCS[3],/SPISCS[4],/SPISCS[5],/SPISCS[6],/SPISCS[7]"
|
|
endif
|
|
bitfld.long 0x00 2. " CTRLSCSPINERR ,Enable/disable the injection of an error on the SPISCS[3:0] pins" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 1. " LPBK_TYPE ,Module I/O loopback type (analog/digital)" "Digital,Analog"
|
|
bitfld.long 0x00 0. " RXP_ENA ,Enable analog loopback through the receive pin" "Transmit,Receive"
|
|
else
|
|
group.long 0x134++0x03
|
|
line.long 0x00 "IOLPBKTSTCR,SPI IO Loopback Test Control Register"
|
|
bitfld.long 0x00 24. " SCSFAILFLG ,Failure on SPISCS pin compare during analog loopback" "Not occurred,Occurred"
|
|
bitfld.long 0x00 20. " CTRL_BITERR ,Controls inducing of BITERR during I/O loopback test mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " CTRL_DESYNC ,Controls inducing of the desync error during I/O loopback test mode" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 18. " CTRL_PARERR ,Controls inducing of parity errors during I/O loopback test mode" "No error,Error"
|
|
bitfld.long 0x00 17. " CTRL_TIMEOUT ,Controls inducing of the timeout error during I/O loopbacK test mode" "No error,Error"
|
|
bitfld.long 0x00 16. " CTRL_DLENERR ,Controls inducing of the data length error during I/O loopback test mode" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 8.--11. " IOLPBKTSTENA ,Module I/O loopback test enable key" "Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Enabled,Disabled,Disabled,Disabled,Disabled,Disabled"
|
|
sif cpuis("TMS570LS0232")
|
|
bitfld.long 0x00 3.--5. " ERRSCSPIN ,Inject error on chip-select pin number" "/SPISCS[0],/SPISCS[1],/SPISCS[2],/SPISCS[3],?..."
|
|
else
|
|
bitfld.long 0x00 3.--5. " ERRSCSPIN ,Inject error on chip-select pin number" "/SPISCS[0],/SPISCS[1],/SPISCS[2],/SPISCS[3],/SPISCS[4],/SPISCS[5],/SPISCS[6],/SPISCS[7]"
|
|
endif
|
|
bitfld.long 0x00 2. " CTRLSCSPINERR ,Enable/disable the injection of an error on the SPISCS[3:0] pins" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 1. " LPBK_TYPE ,Module I/O loopback type (analog/digital)" "Digital,Analog"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0xFFF7F600+0x134))&0x2)==0x2)
|
|
group.long 0x134++0x03
|
|
line.long 0x00 "IOLPBKTSTCR,SPI IO Loopback Test Control Register"
|
|
bitfld.long 0x00 24. " SCSFAILFLG ,Failure on SPISCS pin compare during analog loopback" "Not occurred,Occurred"
|
|
bitfld.long 0x00 20. " CTRL_BITERR ,Controls inducing of BITERR during I/O loopback test mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " CTRL_DESYNC ,Controls inducing of the desync error during I/O loopback test mode" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 18. " CTRL_PARERR ,Controls inducing of parity errors during I/O loopback test mode" "No error,Error"
|
|
bitfld.long 0x00 17. " CTRL_TIMEOUT ,Controls inducing of the timeout error during I/O loopbacK test mode" "No error,Error"
|
|
bitfld.long 0x00 16. " CTRL_DLENERR ,Controls inducing of the data length error during I/O loopback test mode" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 8.--11. " IOLPBKTSTENA ,Module I/O loopback test enable key" "Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Enabled,Disabled,Disabled,Disabled,Disabled,Disabled"
|
|
bitfld.long 0x00 3.--5. " ERRSCSPIN ,Inject error on chip-select pin number" "/SPISCS[0],/SPISCS[1],/SPISCS[2],/SPISCS[3],/SPISCS[4],/SPISCS[5],/SPISCS[6],/SPISCS[7]"
|
|
bitfld.long 0x00 2. " CTRLSCSPINERR ,Enable/disable the injection of an error on the SPISCS[3:0] pins" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 1. " LPBK_TYPE ,Module I/O loopback type (analog/digital)" "Digital,Analog"
|
|
bitfld.long 0x00 0. " RXP_ENA ,Enable analog loopback through the receive pin" "Transmit,Receive"
|
|
else
|
|
group.long 0x134++0x03
|
|
line.long 0x00 "IOLPBKTSTCR,SPI IO Loopback Test Control Register"
|
|
bitfld.long 0x00 24. " SCSFAILFLG ,Failure on SPISCS pin compare during analog loopback" "Not occurred,Occurred"
|
|
bitfld.long 0x00 20. " CTRL_BITERR ,Controls inducing of BITERR during I/O loopback test mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " CTRL_DESYNC ,Controls inducing of the desync error during I/O loopback test mode" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 18. " CTRL_PARERR ,Controls inducing of parity errors during I/O loopback test mode" "No error,Error"
|
|
bitfld.long 0x00 17. " CTRL_TIMEOUT ,Controls inducing of the timeout error during I/O loopbacK test mode" "No error,Error"
|
|
bitfld.long 0x00 16. " CTRL_DLENERR ,Controls inducing of the data length error during I/O loopback test mode" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 8.--11. " IOLPBKTSTENA ,Module I/O loopback test enable key" "Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Enabled,Disabled,Disabled,Disabled,Disabled,Disabled"
|
|
bitfld.long 0x00 3.--5. " ERRSCSPIN ,Inject error on chip-select pin number" "/SPISCS[0],/SPISCS[1],/SPISCS[2],/SPISCS[3],/SPISCS[4],/SPISCS[5],/SPISCS[6],/SPISCS[7]"
|
|
bitfld.long 0x00 2. " CTRLSCSPINERR ,Enable/disable the injection of an error on the SPISCS[3:0] pins" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 1. " LPBK_TYPE ,Module I/O loopback type (analog/digital)" "Digital,Analog"
|
|
endif
|
|
endif
|
|
sif (cpu()=="TMS570LC4357"||cpu()==("TMS570LS0332")||cpu()==("TMS570LS0432")||cpuis("TMS570LS1114*")||cpuis("TMS570LS1115*")||cpuis("TMS570LS1224*")||cpuis("TMS570LS1225*")||cpuis("TMS570LS1227*")||cpuis("TMS570LS0232")||cpuis("TMS570LS0714*")||cpuis("TMS570LS0914*"))
|
|
width 21.
|
|
newline
|
|
group.long 0x138++0x07
|
|
line.long 0x00 "EXTENDED_PRESCALE_1, SPI Extended Prescale Register 1"
|
|
hexmask.long.word 0x00 16.--26. 1. " EPRESCALE_FMT1 , Extended Prescale value for SPIFMT1"
|
|
hexmask.long.word 0x00 0.--10. 1. " EPRESCALE_FMT0 , Extended Prescale value for SPIFMT0"
|
|
line.long 0x04 "EXTENDED_PRESCALE_2, SPI Extended Prescale Register 2"
|
|
hexmask.long.word 0x04 16.--26. 1. " EPRESCALE_FMT3 , Extended Prescale value for SPIFMT3"
|
|
hexmask.long.word 0x04 0.--10. 1. " EPRESCALE_FMT2 , Extended Prescale value for SPIFMT2"
|
|
endif
|
|
sif !cpuis("TMS570LS0232")&&!cpuis("TMS570LS0714*")&&!cpuis("TMS570LS0914*")
|
|
sif (cpu()=="TMS570LC4357"||cpu()==("TMS570LS0332")||cpu()==("TMS570LS0432")||cpuis("TMS570LS1114*")||cpuis("TMS570LS1115*")||cpuis("TMS570LS1224*")||cpuis("TMS570LS1225*")||cpuis("TMS570LS1227*"))
|
|
sif cpuis("TMS570LC4357")
|
|
group.long 0x140++0x03
|
|
line.long 0x00 "ECCDIAG_CTRL, ECC Diagnostic Control register"
|
|
bitfld.long 0x00 0.--3. " ECCDIAG_EN , ECC Diagnostic mode Enable Key bits" "Disabled,Disabled,Disabled,Disabled,Disabled,Enabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled"
|
|
endif
|
|
if ((per.l(ad:0xFFF7F600+0x140)&0x5)==0x5)
|
|
group.long 0x144++0x03
|
|
line.long 0x00 "ECCDIAG_STAT, ECC Diagnostic Status register"
|
|
eventfld.long 0x00 17. " DEFLG[1] , Double bit Error is detected for RXRAM" "No error,Error"
|
|
eventfld.long 0x00 16. " DEFLG[0] , Double bit Error is detected for TXRAM" "No error,Error"
|
|
eventfld.long 0x00 1. " SEFLG[1] , Single bit Error is detected for RXRAM" "No error,Error"
|
|
eventfld.long 0x00 0. " SEFLG[0] , Single bit Error is detected for TXRAM" "No error,Error"
|
|
else
|
|
hgroup.long 0x144++0x03
|
|
hide.long 0x00 "ECCDIAG_STAT, ECC Diagnostic Status register"
|
|
in
|
|
endif
|
|
hgroup.long 0x148++0x03
|
|
hide.long 0x00 "SBERRADDR1, Single Bit Error Address Register - RXRAM"
|
|
in
|
|
hgroup.long 0x14C++0x03
|
|
hide.long 0x00 "SBERRADDR0, Single Bit Error Address Register - TXRAM"
|
|
in
|
|
endif
|
|
endif
|
|
sif cpuis("TMS570LS0232")||cpuis("TMS570LS0714*")||cpuis("TMS570LS0914*")
|
|
endian.be
|
|
endif
|
|
width 0xB
|
|
tree.end
|
|
tree "MibSPI3"
|
|
base ad:0xFFF7F800
|
|
width 17.
|
|
sif cpuis("TMS570LS0232")||cpuis("TMS570LS0714*")||cpuis("TMS570LS0914*")
|
|
endian.be
|
|
endif
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "SPIGCR0,SPI Global Control Register 0"
|
|
bitfld.long 0x00 0. " NRESET ,Reset bit for the module" "No reset,Reset"
|
|
group.long 0x04++0x0F
|
|
line.long 0x00 "SPIGCR1,SPI Global Control Register 1"
|
|
bitfld.long 0x00 24. " SPIEN ,SPI enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " LOOPBACK ,Internal loop-back test mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " POWERDOWN ,SPI state machine enters a power-down state" "No power-down,Power-down"
|
|
newline
|
|
bitfld.long 0x00 1. " CLKMOD ,Clock mode" "External,Internally"
|
|
bitfld.long 0x00 0. " MASTER ,SPISIMO/SPISOMI pin direction determination" "Input/output,Output/input"
|
|
line.long 0x04 "SPIINT0,SPI Interrupt Register"
|
|
bitfld.long 0x04 24. " ENABLEHIGHZ ,SPIENA pin high-impedance enable" "Inactive,Active"
|
|
bitfld.long 0x04 16. " DMAREQEN ,DMA request enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 9. " TXINTENA ,TX interrupt flag enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x04 8. " RXINTENA ,RX interrupt flag enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 6. " RXOVRNINTENA ,Overrun interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 4. " BITERRENA ,Enables interrupt on bit error" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x04 3. " DESYNCENA ,Enables interrupt on desynchronized slave" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " PARERRENA ,Enables interrupt-on-parity-error" "Disabled,Enabled"
|
|
bitfld.long 0x04 1. " TIMEOUTENA ,Enables interrupt on ENA signal time-out" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x04 0. " DLENERRENA ,Data length error interrupt enable" "Disabled,Enabled"
|
|
line.long 0x08 "SPILVL,SPI Interrupt Level Register"
|
|
bitfld.long 0x08 9. " TXINTLVL ,Transmit interrupt level" "INT0,INT1"
|
|
bitfld.long 0x08 8. " RXINTLVL ,Receive interrupt level" "INT0,INT1"
|
|
sif !cpuis("TMS570LS0232")
|
|
bitfld.long 0x08 6. " RXOVRNINTLVL ,Receive overrun interrupt level" "INT0,INT1"
|
|
endif
|
|
newline
|
|
bitfld.long 0x08 4. " BITERRLVL ,Bit error interrupt level" "INT0,INT1"
|
|
bitfld.long 0x08 3. " DESYNCLVL ,Desynchronized slave interrupt level (master mode only)" "INT0,INT1"
|
|
bitfld.long 0x08 2. " PARERRLVL ,Parity error interrupt level" "INT0,INT1"
|
|
newline
|
|
bitfld.long 0x08 1. " TIMEOUTLVL ,SPIENA pin time-out interrupt level" "INT0,INT1"
|
|
bitfld.long 0x08 0. " DLENERRLVL ,Data length error interrupt level (line) select" "INT0,INT1"
|
|
line.long 0x0C "SPIFLG,SPI Flag Register"
|
|
bitfld.long 0x0C 24. " BUFINITACTIVE ,Indicates the status of multi-buffer initialization process" "Completed,Not completed"
|
|
bitfld.long 0x0C 9. " TXINTFLG ,Transmitter-empty interrupt flag" "No interrupt,Interrupt"
|
|
eventfld.long 0x0C 8. " RXINTFLG ,Receiver-full interrupt flag" "No interrupt,Interrupt"
|
|
newline
|
|
eventfld.long 0x0C 6. " RXOVRNINTFLG ,Overrun interrupt enable" "Disabled,Enabled"
|
|
eventfld.long 0x0C 4. " BITERRFLG ,Enables interrupt on bit error" "Disabled,Enabled"
|
|
eventfld.long 0x0C 3. " DESYNCFLG ,Enables interrupt on desynchronized slave" "No interrupt,Interrupt"
|
|
newline
|
|
eventfld.long 0x0C 2. " PARITYERRFLG ,Enables interrupt-on-parity-error" "No error,Error"
|
|
eventfld.long 0x0C 1. " TIMEOUTFLG ,Enables interrupt on ENA signal time-out" "No interrupt,Interrupt"
|
|
eventfld.long 0x0C 0. " DLENERRFLG ,Data length error interrupt enable" "No interrupt,Interrupt"
|
|
group.long 0x14++0x23
|
|
line.long 0x00 "SPIPC0,SPI Pin Control Register 0"
|
|
sif !cpuis("TMS570LS0232")&&!cpuis("TMS570LS0332")&&!cpuis("TMS570LS0432")
|
|
bitfld.long 0x00 31. " SOMIFUN7 ,SPISOMI[7] pin function" "GIO,SPI"
|
|
bitfld.long 0x00 30. " SOMIFUN6 ,SPISOMI[6] pin function" "GIO,SPI"
|
|
bitfld.long 0x00 29. " SOMIFUN5 ,SPISOMI[5] pin function" "GIO,SPI"
|
|
newline
|
|
bitfld.long 0x00 28. " SOMIFUN4 ,SPISOMI[4] pin function" "GIO,SPI"
|
|
bitfld.long 0x00 27. " SOMIFUN3 ,SPISOMI[3] pin function" "GIO,SPI"
|
|
bitfld.long 0x00 26. " SOMIFUN2 ,SPISOMI[2] pin function" "GIO,SPI"
|
|
newline
|
|
bitfld.long 0x00 25. " SOMIFUN1 ,SPISOMI[1] pin function" "GIO,SPI"
|
|
bitfld.long 0x00 24. " SOMIFUN0 ,SPISOMI[0] pin function (mirror of bit 11)" "GIO,SPI"
|
|
bitfld.long 0x00 23. " SIMOFUN7 ,SPISIMO[7] pin function" "GIO,SPI"
|
|
newline
|
|
bitfld.long 0x00 22. " SIMOFUN6 ,SPISIMO[6] pin function" "GIO,SPI"
|
|
bitfld.long 0x00 21. " SIMOFUN5 ,SPISIMO[5] pin function" "GIO,SPI"
|
|
bitfld.long 0x00 20. " SIMOFUN4 ,SPISIMO[4] pin function" "GIO,SPI"
|
|
newline
|
|
bitfld.long 0x00 19. " SIMOFUN3 ,SPISIMO[3] pin function" "GIO,SPI"
|
|
bitfld.long 0x00 18. " SIMOFUN2 ,SPISIMO[2] pin function" "GIO,SPI"
|
|
bitfld.long 0x00 17. " SIMOFUN1 ,SPISIMO[1] pin function" "GIO,SPI"
|
|
newline
|
|
bitfld.long 0x00 16. " SIMOFUN0 ,SPISIMO[0] pin function (mirror of bit 10)" "GIO,SPI"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 11. " SOMIFUN0 ,SPISOMI[0] pin function" "GIO,SPI"
|
|
bitfld.long 0x00 10. " SIMOFUN0 ,SPISIMO[0] pin function" "GIO,SPI"
|
|
newline
|
|
bitfld.long 0x00 9. " CLKFUN ,SPI clock function" "GIO,SPI"
|
|
bitfld.long 0x00 8. " ENAFUN ,SPIENA function" "GIO,SPI"
|
|
bitfld.long 0x00 7. " SCSFUN7 ,SPISCS7 function 7" "GIO,SPI"
|
|
newline
|
|
bitfld.long 0x00 6. " SCSFUN6 ,SPISCS6 function 6" "GIO,SPI"
|
|
bitfld.long 0x00 5. " SCSFUN5 ,SPISCS5 function 5" "GIO,SPI"
|
|
bitfld.long 0x00 4. " SCSFUN4 ,SPISCS4 function 4" "GIO,SPI"
|
|
newline
|
|
bitfld.long 0x00 3. " SCSFUN3 ,SPISCS3 function 3" "GIO,SPI"
|
|
bitfld.long 0x00 2. " SCSFUN2 ,SPISCS2 function 2" "GIO,SPI"
|
|
bitfld.long 0x00 1. " SCSFUN1 ,SPISCS1 function 1" "GIO,SPI"
|
|
newline
|
|
bitfld.long 0x00 0. " SCSFUN0 ,SPISCS0 function 0" "GIO,SPI"
|
|
line.long 0x04 "SPIPC1,SPI Pin Control Register 1"
|
|
bitfld.long 0x04 31. " SOMIDIR7 ,SPISOMI[7] pin direction" "GIO,SPI"
|
|
bitfld.long 0x04 30. " SOMIDIR6 ,SPISOMI[6] pin direction" "GIO,SPI"
|
|
bitfld.long 0x04 29. " SOMIDIR5 ,SPISOMI[5] pin direction" "GIO,SPI"
|
|
newline
|
|
bitfld.long 0x04 28. " SOMIDIR4 ,SPISOMI[4] pin direction" "GIO,SPI"
|
|
bitfld.long 0x04 27. " SOMIDIR3 ,SPISOMI[3] pin direction" "GIO,SPI"
|
|
bitfld.long 0x04 26. " SOMIDIR2 ,SPISOMI[2] pin direction" "GIO,SPI"
|
|
newline
|
|
bitfld.long 0x04 25. " SOMIDIR1 ,SPISOMI[1] pin direction" "GIO,SPI"
|
|
bitfld.long 0x04 24. " SOMIDIR0 ,SPISOMI[0] pin direction (mirror of bit 11)" "GIO,SPI"
|
|
bitfld.long 0x04 23. " SIMODIR7 ,SPISIMO[7] pin direction" "GIO,SPI"
|
|
newline
|
|
bitfld.long 0x04 22. " SIMODIR6 ,SPISIMO[6] pin direction" "GIO,SPI"
|
|
bitfld.long 0x04 21. " SIMODIR5 ,SPISIMO[5] pin direction" "GIO,SPI"
|
|
bitfld.long 0x04 20. " SIMODIR4 ,SPISIMO[4] pin direction" "GIO,SPI"
|
|
newline
|
|
bitfld.long 0x04 19. " SIMODIR3 ,SPISIMO[3] pin direction" "GIO,SPI"
|
|
bitfld.long 0x04 18. " SIMODIR2 ,SPISIMO[2] pin direction" "GIO,SPI"
|
|
bitfld.long 0x04 17. " SIMODIR1 ,SPISIMO[1] pin direction" "GIO,SPI"
|
|
newline
|
|
bitfld.long 0x04 16. " SIMODIR0 ,SPISIMO[0] pin direction (mirror of bit 10)" "GIO,SPI"
|
|
bitfld.long 0x04 11. " SOMIDIR0 ,SPISOMI[0] pin direction" "GIO,SPI"
|
|
bitfld.long 0x04 10. " SIMODIR0 ,SPISIMO[0] pin direction" "GIO,SPI"
|
|
newline
|
|
bitfld.long 0x04 9. " CLKDIR ,SPI clock direction" "GIO,SPI"
|
|
bitfld.long 0x04 8. " ENADIR ,SPIENA direction" "GIO,SPI"
|
|
bitfld.long 0x04 7. " SCSDIR7 ,SPISCS7 direction 7" "GIO,SPI"
|
|
newline
|
|
bitfld.long 0x04 6. " SCSDIR6 ,SPISCS6 direction 6" "GIO,SPI"
|
|
bitfld.long 0x04 5. " SCSDIR5 ,SPISCS5 direction 5" "GIO,SPI"
|
|
bitfld.long 0x04 4. " SCSDIR4 ,SPISCS4 direction 4" "GIO,SPI"
|
|
newline
|
|
bitfld.long 0x04 3. " SCSDIR3 ,SPISCS3 direction 3" "GIO,SPI"
|
|
bitfld.long 0x04 2. " SCSDIR2 ,SPISCS2 direction 2" "GIO,SPI"
|
|
bitfld.long 0x04 1. " SCSDIR1 ,SPISCS1 direction 1" "GIO,SPI"
|
|
newline
|
|
bitfld.long 0x04 0. " SCSDIR0 ,SPISCS0 direction 0" "GIO,SPI"
|
|
line.long 0x08 "SPIPC2,SPI Pin Control Register 2"
|
|
bitfld.long 0x08 31. " SOMIDIN7 ,SPISOMI[7] data in" "0,1"
|
|
bitfld.long 0x08 30. " SOMIDIN6 ,SPISOMI[6] data in" "0,1"
|
|
bitfld.long 0x08 29. " SOMIDIN5 ,SPISOMI[5] data in" "0,1"
|
|
newline
|
|
bitfld.long 0x08 28. " SOMIDIN4 ,SPISOMI[4] data in" "0,1"
|
|
bitfld.long 0x08 27. " SOMIDIN3 ,SPISOMI[3] data in" "0,1"
|
|
bitfld.long 0x08 26. " SOMIDIN2 ,SPISOMI[2] data in" "0,1"
|
|
newline
|
|
bitfld.long 0x08 25. " SOMIDIN1 ,SPISOMI[1] data in" "0,1"
|
|
bitfld.long 0x08 24. " SOMIDIN0 ,SPISOMI[0] data in (mirror of bit 11)" "0,1"
|
|
bitfld.long 0x08 23. " SIMODIN7 ,SPISIMO[7] data in" "0,1"
|
|
newline
|
|
bitfld.long 0x08 22. " SIMODIN6 ,SPISIMO[6] data in" "0,1"
|
|
bitfld.long 0x08 21. " SIMODIN5 ,SPISIMO[5] data in" "0,1"
|
|
bitfld.long 0x08 20. " SIMODIN4 ,SPISIMO[4] data in" "0,1"
|
|
newline
|
|
bitfld.long 0x08 19. " SIMODIN3 ,SPISIMO[3] data in" "0,1"
|
|
bitfld.long 0x08 18. " SIMODIN2 ,SPISIMO[2] data in" "0,1"
|
|
bitfld.long 0x08 17. " SIMODIN1 ,SPISIMO[1] data in" "0,1"
|
|
newline
|
|
bitfld.long 0x08 16. " SIMODIN0 ,SPISIMO[0] data in (mirror of bit 10)" "0,1"
|
|
bitfld.long 0x08 11. " SOMIDIN0 ,SPISOMI[0] data in" "0,1"
|
|
bitfld.long 0x08 10. " SIMODIN0 ,SPISIMO[0] data in" "0,1"
|
|
newline
|
|
bitfld.long 0x08 9. " CLKDIN ,SPI clock data in" "0,1"
|
|
bitfld.long 0x08 8. " ENADIN ,SPIENA data in" "0,1"
|
|
bitfld.long 0x08 7. " SCSDIN7 ,SPISCS7 data in" "0,1"
|
|
newline
|
|
bitfld.long 0x08 6. " SCSDIN6 ,SPISCS6 data in" "0,1"
|
|
bitfld.long 0x08 5. " SCSDIN5 ,SPISCS5 data in" "0,1"
|
|
bitfld.long 0x08 4. " SCSDIN4 ,SPISCS4 data in" "0,1"
|
|
newline
|
|
bitfld.long 0x08 3. " SCSDIN3 ,SPISCS3 data in" "0,1"
|
|
bitfld.long 0x08 2. " SCSDIN2 ,SPISCS2 data in" "0,1"
|
|
bitfld.long 0x08 1. " SCSDIN1 ,SPISCS1 data in" "0,1"
|
|
newline
|
|
bitfld.long 0x08 0. " SCSDIN0 ,SPISCS0 direction 0" "0,1"
|
|
line.long 0x0C "SPIPC3,SPI Pin Control Register 3"
|
|
bitfld.long 0x0C 31. " SOMIDOUT7 ,SPISOMI[7] data out write" "0,1"
|
|
bitfld.long 0x0C 30. " SOMIDOUT6 ,SPISOMI[6] data out write" "0,1"
|
|
bitfld.long 0x0C 29. " SOMIDOUT5 ,SPISOMI[5] data out write" "0,1"
|
|
newline
|
|
bitfld.long 0x0C 28. " SOMIDOUT4 ,SPISOMI[4] data out write" "0,1"
|
|
bitfld.long 0x0C 27. " SOMIDOUT3 ,SPISOMI[3] data out write" "0,1"
|
|
bitfld.long 0x0C 26. " SOMIDOUT2 ,SPISOMI[2] data out write" "0,1"
|
|
newline
|
|
bitfld.long 0x0C 25. " SOMIDOUT1 ,SPISOMI[1] data out write" "0,1"
|
|
bitfld.long 0x0C 24. " SOMIDOUT0 ,SPISOMI[0] data out write (mirror of bit 11)" "0,1"
|
|
bitfld.long 0x0C 23. " SIMODOUT7 ,SPISIMO[7] data out write" "0,1"
|
|
newline
|
|
bitfld.long 0x0C 22. " SIMODOUT6 ,SPISIMO[6] data out write" "0,1"
|
|
bitfld.long 0x0C 21. " SIMODOUT5 ,SPISIMO[5] data out write" "0,1"
|
|
bitfld.long 0x0C 20. " SIMODOUT4 ,SPISIMO[4] data out write" "0,1"
|
|
newline
|
|
bitfld.long 0x0C 19. " SIMODOUT3 ,SPISIMO[3] data out write" "0,1"
|
|
bitfld.long 0x0C 18. " SIMODOUT2 ,SPISIMO[2] data out write" "0,1"
|
|
bitfld.long 0x0C 17. " SIMODOUT1 ,SPISIMO[1] data out write" "0,1"
|
|
newline
|
|
bitfld.long 0x0C 16. " SIMODOUT0 ,SPISIMO[0] data out write (mirror of bit 10)" "0,1"
|
|
bitfld.long 0x0C 11. " SOMIDOUT0 ,SPISOMI[0] data out write" "0,1"
|
|
bitfld.long 0x0C 10. " SIMODOUT0 ,SPISIMO[0] data out write" "0,1"
|
|
newline
|
|
bitfld.long 0x0C 9. " CLKDOUT ,SPI clock data out write" "0,1"
|
|
bitfld.long 0x0C 8. " ENADOUT ,SPIENA data out write" "0,1"
|
|
bitfld.long 0x0C 7. " SCSDOUT7 ,SPISCS7 data out write" "0,1"
|
|
newline
|
|
bitfld.long 0x0C 6. " SCSDOUT6 ,SPISCS6 data out write" "0,1"
|
|
bitfld.long 0x0C 5. " SCSDOUT5 ,SPISCS5 data out write" "0,1"
|
|
bitfld.long 0x0C 4. " SCSDOUT4 ,SPISCS4 data out write" "0,1"
|
|
newline
|
|
bitfld.long 0x0C 3. " SCSDOUT3 ,SPISCS3 data out write" "0,1"
|
|
bitfld.long 0x0C 2. " SCSDOUT2 ,SPISCS2 data out write" "0,1"
|
|
bitfld.long 0x0C 1. " SCSDOUT1 ,SPISCS1 data out write" "0,1"
|
|
newline
|
|
bitfld.long 0x0C 0. " SCSDOUT0 ,SPISCS0 data out write" "0,1"
|
|
line.long 0x10 "SPIPC4,SPI Pin Control Register 4"
|
|
bitfld.long 0x10 31. " SOMISET7 ,SPISOMI[7] data out set" "0,1"
|
|
bitfld.long 0x10 30. " SOMISET6 ,SPISOMI[6] data out set" "0,1"
|
|
bitfld.long 0x10 29. " SOMISET5 ,SPISOMI[5] data out set" "0,1"
|
|
newline
|
|
bitfld.long 0x10 28. " SOMISET4 ,SPISOMI[4] data out set" "0,1"
|
|
bitfld.long 0x10 27. " SOMISET3 ,SPISOMI[3] data out set" "0,1"
|
|
bitfld.long 0x10 26. " SOMISET2 ,SPISOMI[2] data out set" "0,1"
|
|
newline
|
|
bitfld.long 0x10 25. " SOMISET1 ,SPISOMI[1] data out set" "0,1"
|
|
bitfld.long 0x10 24. " SOMISET0 ,SPISOMI[0] data out set (mirror of bit 11)" "0,1"
|
|
bitfld.long 0x10 23. " SIMOSET7 ,SPISIMO[7] data out set" "0,1"
|
|
newline
|
|
bitfld.long 0x10 22. " SIMOSET6 ,SPISIMO[6] data out set" "0,1"
|
|
bitfld.long 0x10 21. " SIMOSET5 ,SPISIMO[5] data out set" "0,1"
|
|
bitfld.long 0x10 20. " SIMOSET4 ,SPISIMO[4] data out set" "0,1"
|
|
newline
|
|
bitfld.long 0x10 19. " SIMOSET3 ,SPISIMO[3] data out set" "0,1"
|
|
bitfld.long 0x10 18. " SIMOSET2 ,SPISIMO[2] data out set" "0,1"
|
|
bitfld.long 0x10 17. " SIMOSET1 ,SPISIMO[1] data out set" "0,1"
|
|
newline
|
|
bitfld.long 0x10 16. " SIMOSET0 ,SPISIMO[0] data out set (mirror of bit 10)" "0,1"
|
|
bitfld.long 0x10 11. " SOMISET0 ,SPISOMI[0] data out set" "0,1"
|
|
bitfld.long 0x10 10. " SIMOSET0 ,SPISIMO[0] data out set" "0,1"
|
|
newline
|
|
bitfld.long 0x10 9. " CLKSET ,SPI clock data out set" "0,1"
|
|
bitfld.long 0x10 8. " ENASET ,SPIENA data out set" "0,1"
|
|
bitfld.long 0x10 7. " SCSSET7 ,SPISCS7 data out set" "0,1"
|
|
newline
|
|
bitfld.long 0x10 6. " SCSSET6 ,SPISCS6 data out set" "0,1"
|
|
bitfld.long 0x10 5. " SCSSET5 ,SPISCS5 data out set" "0,1"
|
|
bitfld.long 0x10 4. " SCSSET4 ,SPISCS4 data out set" "0,1"
|
|
newline
|
|
bitfld.long 0x10 3. " SCSSET3 ,SPISCS3 data out set" "0,1"
|
|
bitfld.long 0x10 2. " SCSSET2 ,SPISCS2 data out set" "0,1"
|
|
bitfld.long 0x10 1. " SCSSET1 ,SPISCS1 data out set" "0,1"
|
|
newline
|
|
bitfld.long 0x10 0. " SCSSET0 ,SPISCS0 data out set" "0,1"
|
|
line.long 0x14 "SPIPC5,SPI Pin Control Register 5"
|
|
bitfld.long 0x14 31. " SOMICLR7 ,SPISOMI[7] data out clear" "0,1"
|
|
bitfld.long 0x14 30. " SOMICLR6 ,SPISOMI[6] data out clear" "0,1"
|
|
bitfld.long 0x14 29. " SOMICLR5 ,SPISOMI[5] data out clear" "0,1"
|
|
newline
|
|
bitfld.long 0x14 28. " SOMICLR4 ,SPISOMI[4] data out clear" "0,1"
|
|
bitfld.long 0x14 27. " SOMICLR3 ,SPISOMI[3] data out clear" "0,1"
|
|
bitfld.long 0x14 26. " SOMICLR2 ,SPISOMI[2] data out clear" "0,1"
|
|
newline
|
|
bitfld.long 0x14 25. " SOMICLR1 ,SPISOMI[1] data out clear" "0,1"
|
|
bitfld.long 0x14 24. " SOMICLR0 ,SPISOMI[0] data out clear (mirror of bit 11)" "0,1"
|
|
bitfld.long 0x14 23. " SIMOCLR7 ,SPISIMO[7] data out clear" "0,1"
|
|
newline
|
|
bitfld.long 0x14 22. " SIMOCLR6 ,SPISIMO[6] data out clear" "0,1"
|
|
bitfld.long 0x14 21. " SIMOCLR5 ,SPISIMO[5] data out clear" "0,1"
|
|
bitfld.long 0x14 20. " SIMOCLR4 ,SPISIMO[4] data out clear" "0,1"
|
|
newline
|
|
bitfld.long 0x14 19. " SIMOCLR3 ,SPISIMO[3] data out clear" "0,1"
|
|
bitfld.long 0x14 18. " SIMOCLR2 ,SPISIMO[2] data out clear" "0,1"
|
|
bitfld.long 0x14 17. " SIMOCLR1 ,SPISIMO[1] data out clear" "0,1"
|
|
newline
|
|
bitfld.long 0x14 16. " SIMOCLR0 ,SPISIMO[0] data out clear (mirror of bit 10)" "0,1"
|
|
bitfld.long 0x14 11. " SOMICLR0 ,SPISOMI[0] data out clear" "0,1"
|
|
bitfld.long 0x14 10. " SIMOCLR0 ,SPISIMO[0] data out clear" "0,1"
|
|
newline
|
|
bitfld.long 0x14 9. " CLKCLR ,SPI clock data out clear" "0,1"
|
|
bitfld.long 0x14 8. " ENACLR ,SPIENA data out clear" "0,1"
|
|
bitfld.long 0x14 7. " SCSCLR7 ,SPISCS7 data out clear" "0,1"
|
|
newline
|
|
bitfld.long 0x14 6. " SCSCLR6 ,SPISCS6 data out clear" "0,1"
|
|
bitfld.long 0x14 5. " SCSCLR5 ,SPISCS5 data out clear" "0,1"
|
|
bitfld.long 0x14 4. " SCSCLR4 ,SPISCS4 data out clear" "0,1"
|
|
newline
|
|
bitfld.long 0x14 3. " SCSCLR3 ,SPISCS3 data out clear" "0,1"
|
|
bitfld.long 0x14 2. " SCSCLR2 ,SPISCS2 data out clear" "0,1"
|
|
bitfld.long 0x14 1. " SCSCLR1 ,SPISCS1 data out clear" "0,1"
|
|
newline
|
|
bitfld.long 0x14 0. " SCSCLR0 ,SPISCS0 data out clear" "0,1"
|
|
line.long 0x18 "SPIPC6,SPI Pin Control Register 6"
|
|
bitfld.long 0x18 31. " SOMIPDR7 ,SPISOMI[7] open drain enable" "Disabled,Enabled"
|
|
bitfld.long 0x18 30. " SOMIPDR6 ,SPISOMI[6] open drain enable" "Disabled,Enabled"
|
|
bitfld.long 0x18 29. " SOMIPDR5 ,SPISOMI[5] open drain enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x18 28. " SOMIPDR4 ,SPISOMI[4] open drain enable" "Disabled,Enabled"
|
|
bitfld.long 0x18 27. " SOMIPDR3 ,SPISOMI[3] open drain enable" "Disabled,Enabled"
|
|
bitfld.long 0x18 26. " SOMIPDR2 ,SPISOMI[2] open drain enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x18 25. " SOMIPDR1 ,SPISOMI[1] open drain enable" "Disabled,Enabled"
|
|
bitfld.long 0x18 24. " SOMIPDR0 ,SPISOMI[0] open drain enable (mirror of bit 11)" "Disabled,Enabled"
|
|
bitfld.long 0x18 23. " SIMOPDR7 ,SPISIMO[7] open drain enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x18 22. " SIMOPDR6 ,SPISIMO[6] open drain enable" "Disabled,Enabled"
|
|
bitfld.long 0x18 21. " SIMOPDR5 ,SPISIMO[5] open drain enable" "Disabled,Enabled"
|
|
bitfld.long 0x18 20. " SIMOPDR4 ,SPISIMO[4] open drain enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x18 19. " SIMOPDR3 ,SPISIMO[3] open drain enable" "Disabled,Enabled"
|
|
bitfld.long 0x18 18. " SIMOPDR2 ,SPISIMO[2] open drain enable" "Disabled,Enabled"
|
|
bitfld.long 0x18 17. " SIMOPDR1 ,SPISIMO[1] open drain enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x18 16. " SIMOPDR0 ,SPISIMO[0] open drain enable (mirror of bit 10)" "Disabled,Enabled"
|
|
bitfld.long 0x18 11. " SOMIPDR0 ,SPISOMI[0] open drain enable" "Disabled,Enabled"
|
|
bitfld.long 0x18 10. " SIMOPDR0 ,SPISIMO[0] open drain enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x18 9. " CLKPDR ,SPI clock open drain enable" "Disabled,Enabled"
|
|
bitfld.long 0x18 8. " ENAPDR ,SPIENA open drain enable" "Disabled,Enabled"
|
|
bitfld.long 0x18 7. " SCSPDR7 ,SPISCS7 open drain enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x18 6. " SCSPDR6 ,SPISCS6 open drain enable" "Disabled,Enabled"
|
|
bitfld.long 0x18 5. " SCSPDR5 ,SPISCS5 open drain enable" "Disabled,Enabled"
|
|
bitfld.long 0x18 4. " SCSPDR4 ,SPISCS4 open drain enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x18 3. " SCSPDR3 ,SPISCS3 open drain enable" "Disabled,Enabled"
|
|
bitfld.long 0x18 2. " SCSPDR2 ,SPISCS2 open drain enable" "Disabled,Enabled"
|
|
bitfld.long 0x18 1. " SCSPDR1 ,SPISCS1 open drain enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x18 0. " SCSPDR0 ,SPISCS0 open drain enable" "Disabled,Enabled"
|
|
line.long 0x1C "SPIPC7,SPI Pin Control Register 7"
|
|
bitfld.long 0x1C 31. " SOMIPDIS7 ,SPISOMI[7] pull control enable/disable" "No,Yes"
|
|
bitfld.long 0x1C 30. " SOMIPDIS6 ,SPISOMI[6] pull control enable/disable" "No,Yes"
|
|
bitfld.long 0x1C 29. " SOMIPDIS5 ,SPISOMI[5] pull control enable/disable" "No,Yes"
|
|
newline
|
|
bitfld.long 0x1C 28. " SOMIPDIS4 ,SPISOMI[4] pull control enable/disable" "No,Yes"
|
|
bitfld.long 0x1C 27. " SOMIPDIS3 ,SPISOMI[3] pull control enable/disable" "No,Yes"
|
|
bitfld.long 0x1C 26. " SOMIPDIS2 ,SPISOMI[2] pull control enable/disable" "No,Yes"
|
|
newline
|
|
bitfld.long 0x1C 25. " SOMIPDIS1 ,SPISOMI[1] pull control enable/disable" "No,Yes"
|
|
bitfld.long 0x1C 24. " SOMIPDIS0 ,SPISOMI[0] pull control enable/disable (mirror of bit 11)" "No,Yes"
|
|
bitfld.long 0x1C 23. " SIMOPDIS7 ,SPISIMO[7] pull control enable/disable" "No,Yes"
|
|
newline
|
|
bitfld.long 0x1C 22. " SIMOPDIS6 ,SPISIMO[6] pull control enable/disable" "No,Yes"
|
|
bitfld.long 0x1C 21. " SIMOPDIS5 ,SPISIMO[5] pull control enable/disable" "No,Yes"
|
|
bitfld.long 0x1C 20. " SIMOPDIS4 ,SPISIMO[4] pull control enable/disable" "No,Yes"
|
|
newline
|
|
bitfld.long 0x1C 19. " SIMOPDIS3 ,SPISIMO[3] pull control enable/disable" "No,Yes"
|
|
bitfld.long 0x1C 18. " SIMOPDIS2 ,SPISIMO[2] pull control enable/disable" "No,Yes"
|
|
bitfld.long 0x1C 17. " SIMOPDIS1 ,SPISIMO[1] pull control enable/disable" "No,Yes"
|
|
newline
|
|
bitfld.long 0x1C 16. " SIMOPDIS0 ,SPISIMO[0] pull control enable/disable (mirror of bit 10)" "No,Yes"
|
|
bitfld.long 0x1C 11. " SOMIPDIS0 ,SPISOMI[0] pull control enable/disable" "No,Yes"
|
|
bitfld.long 0x1C 10. " SIMOPDIS0 ,SPISIMO[0] pull control enable/disable" "No,Yes"
|
|
newline
|
|
bitfld.long 0x1C 9. " CLKPDIS ,SPI clock pull control enable/disable" "No,Yes"
|
|
bitfld.long 0x1C 8. " ENAPDIS ,SPIENA pull control enable/disable" "No,Yes"
|
|
bitfld.long 0x1C 7. " SCSPDIS7 ,SPISCS7 pull control enable/disable" "No,Yes"
|
|
newline
|
|
bitfld.long 0x1C 6. " SCSPDIS6 ,SPISCS6 pull control enable/disable" "No,Yes"
|
|
bitfld.long 0x1C 5. " SCSPDIS5 ,SPISCS5 pull control enable/disable" "No,Yes"
|
|
bitfld.long 0x1C 4. " SCSPDIS4 ,SPISCS4 pull control enable/disable" "No,Yes"
|
|
newline
|
|
bitfld.long 0x1C 3. " SCSPDIS3 ,SPISCS3 pull control enable/disable" "No,Yes"
|
|
bitfld.long 0x1C 2. " SCSPDIS2 ,SPISCS2 pull control enable/disable" "No,Yes"
|
|
bitfld.long 0x1C 1. " SCSPDIS1 ,SPISCS1 pull control enable/disable" "No,Yes"
|
|
newline
|
|
bitfld.long 0x1C 0. " SCSPDIS0 ,SPISCS0 pull control enable/disable" "No,Yes"
|
|
line.long 0x20 "SPIPC8,SPI Pin Control Register 8"
|
|
bitfld.long 0x20 31. " SOMIPSEL7 ,SPISOMI[7] pull select" "Pull down,Pull up"
|
|
bitfld.long 0x20 30. " SOMIPSEL6 ,SPISOMI[6] pull select" "Pull down,Pull up"
|
|
bitfld.long 0x20 29. " SOMIPSEL5 ,SPISOMI[5] pull select" "Pull down,Pull up"
|
|
newline
|
|
bitfld.long 0x20 28. " SOMIPSEL4 ,SPISOMI[4] pull select" "Pull down,Pull up"
|
|
bitfld.long 0x20 27. " SOMIPSEL3 ,SPISOMI[3] pull select" "Pull down,Pull up"
|
|
bitfld.long 0x20 26. " SOMIPSEL2 ,SPISOMI[2] pull select" "Pull down,Pull up"
|
|
newline
|
|
bitfld.long 0x20 25. " SOMIPSEL1 ,SPISOMI[1] pull select" "Pull down,Pull up"
|
|
bitfld.long 0x20 24. " SOMIPSEL0 ,SPISOMI[0] pull select (mirror of bit 11)" "Pull down,Pull up"
|
|
bitfld.long 0x20 23. " SIMOPSEL7 ,SPISIMO[7] pull select" "Pull down,Pull up"
|
|
newline
|
|
bitfld.long 0x20 22. " SIMOPSEL6 ,SPISIMO[6] pull select" "Pull down,Pull up"
|
|
bitfld.long 0x20 21. " SIMOPSEL5 ,SPISIMO[5] pull select" "Pull down,Pull up"
|
|
bitfld.long 0x20 20. " SIMOPSEL4 ,SPISIMO[4] pull select" "Pull down,Pull up"
|
|
newline
|
|
bitfld.long 0x20 19. " SIMOPSEL3 ,SPISIMO[3] pull select" "Pull down,Pull up"
|
|
bitfld.long 0x20 18. " SIMOPSEL2 ,SPISIMO[2] pull select" "Pull down,Pull up"
|
|
bitfld.long 0x20 17. " SIMOPSEL1 ,SPISIMO[1] pull select" "Pull down,Pull up"
|
|
newline
|
|
bitfld.long 0x20 16. " SIMOPSEL0 ,SPISIMO[0] pull select (mirror of bit 10)" "Pull down,Pull up"
|
|
bitfld.long 0x20 11. " SOMIPSEL0 ,SPISOMI[0] pull select" "Pull down,Pull up"
|
|
bitfld.long 0x20 10. " SIMOPSEL0 ,SPISIMO[0] pull select" "Pull down,Pull up"
|
|
newline
|
|
bitfld.long 0x20 9. " CLKPSEL ,SPI clock pull select" "Pull down,Pull up"
|
|
bitfld.long 0x20 8. " ENAPSEL ,SPIENA pull select" "Pull down,Pull up"
|
|
bitfld.long 0x20 7. " SCSPSEL7 ,SPISCS7 pull select" "Pull down,Pull up"
|
|
newline
|
|
bitfld.long 0x20 6. " SCSPSEL6 ,SPISCS6 pull select" "Pull down,Pull up"
|
|
bitfld.long 0x20 5. " SCSPSEL5 ,SPISCS5 pull select" "Pull down,Pull up"
|
|
bitfld.long 0x20 4. " SCSPSEL4 ,SPISCS4 pull select" "Pull down,Pull up"
|
|
newline
|
|
bitfld.long 0x20 3. " SCSPSEL3 ,SPISCS3 pull select" "Pull down,Pull up"
|
|
bitfld.long 0x20 2. " SCSPSEL2 ,SPISCS2 pull select" "Pull down,Pull up"
|
|
bitfld.long 0x20 1. " SCSPSEL1 ,SPISCS1 pull select" "Pull down,Pull up"
|
|
newline
|
|
bitfld.long 0x20 0. " SCSPSEL0 ,SPISCS0 pull select" "Pull down,Pull up"
|
|
group.long 0x38++0x07
|
|
line.long 0x00 "SPIDAT0,SPI Transmit Data Register 0"
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,SPI transmit data"
|
|
line.long 0x04 "SPIDAT1,Transmit Data Register 1"
|
|
bitfld.long 0x04 28. " CSHOLD ,Chip select hold mode" "Inactive,Active"
|
|
bitfld.long 0x04 26. " WDEL ,Enable the delay counter at the end of the current transaction" "No delay,After transaction"
|
|
bitfld.long 0x04 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
newline
|
|
hexmask.long.byte 0x04 16.--23. 1. " CSNR ,Chip select number"
|
|
hexmask.long.word 0x04 0.--15. 1. " TXDATA ,Transfer data"
|
|
hgroup.long 0x40++0x03
|
|
hide.long 0x00 "SPIBUF,SPI Receive Buffer Register"
|
|
in
|
|
rgroup.long 0x44++0x03
|
|
line.long 0x00 "SPIEMU,SPI Emulation Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " EMU_RXDATA ,SPI receive data"
|
|
sif cpuis("TMS570LS0232")||cpuis("TMS570LS0714*")||cpuis("TMS570LS0914*")
|
|
group.long 0x48++0x03
|
|
line.long 0x00 "SPIDELAY,SPI Delay Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " C2TDELAY ,Chip-select-active to transmit-start delay"
|
|
hexmask.long.byte 0x00 16.--23. 1. " T2CDELAY ,Transmit-end-to-chip-select-inactive-delay"
|
|
hexmask.long.byte 0x00 8.--15. 1. " T2EDELAY ,Transmit-data-finished to ENA-pin-inactive time-out"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--7. 1. " C2EDELAY ,Chip-select-active to ENA-signal-active time-out"
|
|
else
|
|
rgroup.long 0x48++0x03
|
|
line.long 0x00 "SPIDELAY,SPI Delay Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " C2TDELAY ,Chip-select-active to transmit-start delay"
|
|
hexmask.long.byte 0x00 16.--23. 1. " T2CDELAY ,Transmit-end-to-chip-select-inactive-delay"
|
|
hexmask.long.byte 0x00 8.--15. 1. " T2EDELAY ,Transmit-data-finished to ENA-pin-inactive time-out"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--7. 1. " C2EDELAY ,Chip-select-active to ENA-signal-active time-out"
|
|
endif
|
|
group.long 0x4C++0x13
|
|
line.long 0x00 "SPIDEF,SPI Default Chip Select Register"
|
|
bitfld.long 0x00 7. " CSDEF7 ,Chip select default pattern 7" "0,1"
|
|
bitfld.long 0x00 6. " CSDEF6 ,Chip select default pattern 6" "0,1"
|
|
bitfld.long 0x00 5. " CSDEF5 ,Chip select default pattern 5" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. " CSDEF4 ,Chip select default pattern 4" "0,1"
|
|
bitfld.long 0x00 3. " CSDEF3 ,Chip select default pattern 3" "0,1"
|
|
bitfld.long 0x00 2. " CSDEF2 ,Chip select default pattern 2" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. " CSDEF1 ,Chip select default pattern 1" "0,1"
|
|
bitfld.long 0x00 0. " CSDEF0 ,Chip select default pattern 0" "0,1"
|
|
line.long 0x4 "SPIFMT0,SPI Data Format Register 0"
|
|
sif (cpuis("TMS570LS0332")||cpuis("TMS570LS0432")||cpuis("TMS570LS1114*")||cpuis("TMS570LS1115*")||cpuis("TMS570LS1224*")||cpuis("TMS570LS1225*")||cpuis("TMS570LS1227*")||cpuis("TMS570LS0232")||cpuis("TMS570LS0714*")||cpuis("TMS570LS0914*"))
|
|
hexmask.long.byte 0x4 24.--31. 1. " WDELAY ,Delay in between transmissions for data format 0"
|
|
else
|
|
bitfld.long 0x4 24.--29. " WDELAY ,Delay in between transmissions for data format 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
endif
|
|
bitfld.long 0x4 23. " PARPOL ,Parity polarity: even or odd" "Even,Odd"
|
|
newline
|
|
bitfld.long 0x4 22. " PARITYENA ,Parity enable for data format 0" "Disabled,Enabled"
|
|
bitfld.long 0x4 21. " WAITENA ,The master waits for the ENA signal from slave for data format 0" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x4 20. " SHIFTDIR ,Shift direction for data format $" "MSB,LSB"
|
|
sif (cpu()==("TMS570LS0332")||cpu()==("TMS570LS0432")||cpuis("TMS570LS1114*")||cpuis("TMS570LS1115*")||cpuis("TMS570LS1224*")||cpuis("TMS570LS1225*")||cpuis("TMS570LS1227*")||cpuis("TMS570LS0232")||cpuis("TMS570LS0714*")||cpuis("TMS570LS0914*"))
|
|
bitfld.long 0x4 19. " HDUPLEX_ENA0 ,Half Duplex transfer mode enable for Data Format 0" "Normal,RX/TX"
|
|
endif
|
|
newline
|
|
bitfld.long 0x4 18. " DISCSTIMERS ,Disable chip-select timers for this format" "No,Yes"
|
|
newline
|
|
bitfld.long 0x4 17. " POLARITY ,SPI data format 0 clock polarity" "Low,High"
|
|
bitfld.long 0x4 16. " PHASE ,SPI data format 0 clock delay" "Disabled,Enabled"
|
|
newline
|
|
hexmask.long.byte 0x4 8.--15. 1. " PRESCALE ,SPI data format 0 prescaler"
|
|
bitfld.long 0x4 0.--4. " CHARLEN ,SPI data format 0 data-word length" ",,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,?..."
|
|
line.long 0x8 "SPIFMT1,SPI Data Format Register 1"
|
|
sif (cpuis("TMS570LS0332")||cpuis("TMS570LS0432")||cpuis("TMS570LS1114*")||cpuis("TMS570LS1115*")||cpuis("TMS570LS1224*")||cpuis("TMS570LS1225*")||cpuis("TMS570LS1227*")||cpuis("TMS570LS0232")||cpuis("TMS570LS0714*")||cpuis("TMS570LS0914*"))
|
|
hexmask.long.byte 0x8 24.--31. 1. " WDELAY ,Delay in between transmissions for data format 1"
|
|
else
|
|
bitfld.long 0x8 24.--29. " WDELAY ,Delay in between transmissions for data format 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
endif
|
|
bitfld.long 0x8 23. " PARPOL ,Parity polarity: even or odd" "Even,Odd"
|
|
newline
|
|
bitfld.long 0x8 22. " PARITYENA ,Parity enable for data format 1" "Disabled,Enabled"
|
|
bitfld.long 0x8 21. " WAITENA ,The master waits for the ENA signal from slave for data format 1" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x8 20. " SHIFTDIR ,Shift direction for data format $" "MSB,LSB"
|
|
sif (cpu()==("TMS570LS0332")||cpu()==("TMS570LS0432")||cpuis("TMS570LS1114*")||cpuis("TMS570LS1115*")||cpuis("TMS570LS1224*")||cpuis("TMS570LS1225*")||cpuis("TMS570LS1227*")||cpuis("TMS570LS0232")||cpuis("TMS570LS0714*")||cpuis("TMS570LS0914*"))
|
|
bitfld.long 0x8 19. " HDUPLEX_ENA1 ,Half Duplex transfer mode enable for Data Format 1" "Normal,RX/TX"
|
|
endif
|
|
newline
|
|
bitfld.long 0x8 18. " DISCSTIMERS ,Disable chip-select timers for this format" "No,Yes"
|
|
newline
|
|
bitfld.long 0x8 17. " POLARITY ,SPI data format 1 clock polarity" "Low,High"
|
|
bitfld.long 0x8 16. " PHASE ,SPI data format 1 clock delay" "Disabled,Enabled"
|
|
newline
|
|
hexmask.long.byte 0x8 8.--15. 1. " PRESCALE ,SPI data format 1 prescaler"
|
|
bitfld.long 0x8 0.--4. " CHARLEN ,SPI data format 1 data-word length" ",,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,?..."
|
|
line.long 0xC "SPIFMT2,SPI Data Format Register 2"
|
|
sif (cpuis("TMS570LS0332")||cpuis("TMS570LS0432")||cpuis("TMS570LS1114*")||cpuis("TMS570LS1115*")||cpuis("TMS570LS1224*")||cpuis("TMS570LS1225*")||cpuis("TMS570LS1227*")||cpuis("TMS570LS0232")||cpuis("TMS570LS0714*")||cpuis("TMS570LS0914*"))
|
|
hexmask.long.byte 0xC 24.--31. 1. " WDELAY ,Delay in between transmissions for data format 2"
|
|
else
|
|
bitfld.long 0xC 24.--29. " WDELAY ,Delay in between transmissions for data format 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
endif
|
|
bitfld.long 0xC 23. " PARPOL ,Parity polarity: even or odd" "Even,Odd"
|
|
newline
|
|
bitfld.long 0xC 22. " PARITYENA ,Parity enable for data format 2" "Disabled,Enabled"
|
|
bitfld.long 0xC 21. " WAITENA ,The master waits for the ENA signal from slave for data format 2" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0xC 20. " SHIFTDIR ,Shift direction for data format $" "MSB,LSB"
|
|
sif (cpu()==("TMS570LS0332")||cpu()==("TMS570LS0432")||cpuis("TMS570LS1114*")||cpuis("TMS570LS1115*")||cpuis("TMS570LS1224*")||cpuis("TMS570LS1225*")||cpuis("TMS570LS1227*")||cpuis("TMS570LS0232")||cpuis("TMS570LS0714*")||cpuis("TMS570LS0914*"))
|
|
bitfld.long 0xC 19. " HDUPLEX_ENA2 ,Half Duplex transfer mode enable for Data Format 2" "Normal,RX/TX"
|
|
endif
|
|
newline
|
|
bitfld.long 0xC 18. " DISCSTIMERS ,Disable chip-select timers for this format" "No,Yes"
|
|
newline
|
|
bitfld.long 0xC 17. " POLARITY ,SPI data format 2 clock polarity" "Low,High"
|
|
bitfld.long 0xC 16. " PHASE ,SPI data format 2 clock delay" "Disabled,Enabled"
|
|
newline
|
|
hexmask.long.byte 0xC 8.--15. 1. " PRESCALE ,SPI data format 2 prescaler"
|
|
bitfld.long 0xC 0.--4. " CHARLEN ,SPI data format 2 data-word length" ",,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,?..."
|
|
line.long 0x10 "SPIFMT3,SPI Data Format Register 3"
|
|
sif (cpuis("TMS570LS0332")||cpuis("TMS570LS0432")||cpuis("TMS570LS1114*")||cpuis("TMS570LS1115*")||cpuis("TMS570LS1224*")||cpuis("TMS570LS1225*")||cpuis("TMS570LS1227*")||cpuis("TMS570LS0232")||cpuis("TMS570LS0714*")||cpuis("TMS570LS0914*"))
|
|
hexmask.long.byte 0x10 24.--31. 1. " WDELAY ,Delay in between transmissions for data format 3"
|
|
else
|
|
bitfld.long 0x10 24.--29. " WDELAY ,Delay in between transmissions for data format 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
endif
|
|
bitfld.long 0x10 23. " PARPOL ,Parity polarity: even or odd" "Even,Odd"
|
|
newline
|
|
bitfld.long 0x10 22. " PARITYENA ,Parity enable for data format 3" "Disabled,Enabled"
|
|
bitfld.long 0x10 21. " WAITENA ,The master waits for the ENA signal from slave for data format 3" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x10 20. " SHIFTDIR ,Shift direction for data format $" "MSB,LSB"
|
|
sif (cpu()==("TMS570LS0332")||cpu()==("TMS570LS0432")||cpuis("TMS570LS1114*")||cpuis("TMS570LS1115*")||cpuis("TMS570LS1224*")||cpuis("TMS570LS1225*")||cpuis("TMS570LS1227*")||cpuis("TMS570LS0232")||cpuis("TMS570LS0714*")||cpuis("TMS570LS0914*"))
|
|
bitfld.long 0x10 19. " HDUPLEX_ENA3 ,Half Duplex transfer mode enable for Data Format 3" "Normal,RX/TX"
|
|
endif
|
|
newline
|
|
bitfld.long 0x10 18. " DISCSTIMERS ,Disable chip-select timers for this format" "No,Yes"
|
|
newline
|
|
bitfld.long 0x10 17. " POLARITY ,SPI data format 3 clock polarity" "Low,High"
|
|
bitfld.long 0x10 16. " PHASE ,SPI data format 3 clock delay" "Disabled,Enabled"
|
|
newline
|
|
hexmask.long.byte 0x10 8.--15. 1. " PRESCALE ,SPI data format 3 prescaler"
|
|
bitfld.long 0x10 0.--4. " CHARLEN ,SPI data format 3 data-word length" ",,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,?..."
|
|
hgroup.long 0x60++0x03
|
|
hide.long 0x00 "TGINTVECT0,SPI Interrupt Vector Register 0 / MibSPI Transfer Group Interrupt Vector Register 0"
|
|
in
|
|
hgroup.long 0x64++0x03
|
|
hide.long 0x00 "TGINTVECT1,SPI Interrupt Vector Register 1 / MibSPI Transfer Group Interrupt Vector Register 1"
|
|
in
|
|
sif (cpu()!=("TMS570LS0332")&&cpu()!=("TMS570LS0432")&&!cpuis("TMS570LS0232"))
|
|
group.long 0x6C++0x07
|
|
line.long 0x00 "SPIPMCTRL,SPI Parallel/Modulo Mode Control Register"
|
|
bitfld.long 0x00 29. " MODCLKPOL3 ,Modulo mode SPICLK polarity" "Normal,Inverted"
|
|
bitfld.long 0x00 26.--28. " MMODE3 ,SPI/MibSPI data lines " "1,2,3,4,5,6,?..."
|
|
bitfld.long 0x00 24.--25. " PMODE3 ,Parallel mode data lines" "1,2,4,8"
|
|
newline
|
|
bitfld.long 0x00 21. " MODCLKPOL2 ,Modulo mode SPICLK polarity" "Normal,Inverted"
|
|
bitfld.long 0x00 18.--20. " MMODE2 ,SPI/MibSPI data lines " "1,2,3,4,5,6,?..."
|
|
bitfld.long 0x00 16.--17. " PMODE2 ,Parallel mode data lines" "1,2,4,8"
|
|
newline
|
|
bitfld.long 0x00 13. " MODCLKPOL1 ,Modulo mode SPICLK polarity" "Normal,Inverted"
|
|
bitfld.long 0x00 10.--12. " MMODE1 ,SPI/MibSPI data lines " "1,2,3,4,5,6,?..."
|
|
bitfld.long 0x00 8.--9. " PMODE1 ,Parallel mode data lines" "1,2,4,8"
|
|
newline
|
|
bitfld.long 0x00 5. " MODCLKPOL0 ,Modulo mode SPICLK polarity" "Normal,Inverted"
|
|
bitfld.long 0x00 2.--4. " MMODE0 ,SPI/MibSPI data lines " "1,2,3,4,5,6,?..."
|
|
bitfld.long 0x00 0.--1. " PMODE0 ,Parallel mode data lines" "1,2,4,8"
|
|
line.long 0x04 "MIBSPIE,MibSPI Enable Register"
|
|
bitfld.long 0x04 16. " RXRAMACCESS ,Receive-RAM access control" "Not writable,Accessible"
|
|
bitfld.long 0x04 0. " MIBSPIENA ,Multi-buffer mode enable" "Disabled,Enabled"
|
|
elif cpuis("TMS570LS0332")||cpuis("TMS570LS0432")||cpuis("TMS570LS0714*")||cpuis("TMS570LS0914*")||cpuis("TMS570LS0232")
|
|
group.long 0x70++0x03
|
|
line.long 0x00 "MIBSPIE,MibSPI Enable Register"
|
|
bitfld.long 0x00 16. " RXRAMACCESS ,Receive-RAM access control" "Not writable,Accessible"
|
|
bitfld.long 0x00 0. " MIBSPIENA ,Multi-buffer mode enable" "Disabled,Enabled"
|
|
endif
|
|
group.long 0x74++0x0F
|
|
line.long 0x00 "TGITENST,MibSPI Transfer Group Interrupt Enable Set Register"
|
|
bitfld.long 0x00 31. " SETINTENRDY15 ,TG interrupt set (enable) when transfer finished" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " SETINTENRDY14 ,TG interrupt set (enable) when transfer finished" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " SETINTENRDY13 ,TG interrupt set (enable) when transfer finished" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 28. " SETINTENRDY12 ,TG interrupt set (enable) when transfer finished" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " SETINTENRDY11 ,TG interrupt set (enable) when transfer finished" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " SETINTENRDY10 ,TG interrupt set (enable) when transfer finished" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 25. " SETINTENRDY9 ,TG interrupt set (enable) when transfer finished" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " SETINTENRDY8 ,TG interrupt set (enable) when transfer finished" "Disabled,Enabled"
|
|
bitfld.long 0x00 23. " SETINTENRDY7 ,TG interrupt set (enable) when transfer finished" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 22. " SETINTENRDY6 ,TG interrupt set (enable) when transfer finished" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " SETINTENRDY5 ,TG interrupt set (enable) when transfer finished" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " SETINTENRDY4 ,SETTG interrupt set (enable) when transfer finished" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 19. " SETINTENRDY3 ,TG interrupt set (enable) when transfer finished" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SETINTENRDY2 ,TG interrupt set (enable) when transfer finished" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SETINTENRDY1 ,TG interrupt set (enable) when transfer finished" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 16. " SETINTENRDY0 ,TG interrupt set (enable) when transfer finished" "Disabled,Enabled"
|
|
bitfld.long 0x00 15. " SETINTENSUS15 ,TG interrupt set (enabled) when transfer suspended" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " SETINTENSUS14 ,TG interrupt set (enabled) when transfer suspended" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 13. " SETINTENSUS13 ,TG interrupt set (enabled) when transfer suspended" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " SETINTENSUS12 ,TG interrupt set (enabled) when transfer suspended" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " SETINTENSUS11 ,TG interrupt set (enabled) when transfer suspended" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 10. " SETINTENSUS10 ,TG interrupt set (enabled) when transfer suspended" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " SETINTENSUS9 ,TG interrupt set (enabled) when transfer suspended" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " SETINTENSUS8 ,TG interrupt set (enabled) when transfer suspended" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 7. " SETINTENSUS7 ,TG interrupt set (enabled) when transfer suspended" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " SETINTENSUS6 ,TG interrupt set (enabled) when transfer suspended" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " SETINTENSUS5 ,TG interrupt set (enabled) when transfer suspended" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 4. " SETINTENSUS4 ,TG interrupt set (enabled) when transfer suspended" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " SETINTENSUS3 ,TG interrupt set (enabled) when transfer suspended" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " SETINTENSUS2 ,TG interrupt set (enabled) when transfer suspended" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 1. " SETINTENSUS1 ,TG interrupt set (enabled) when transfer suspended" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SETINTENSUS0 ,TG interrupt set (enabled) when transfer suspended" "Disabled,Enabled"
|
|
line.long 0x04 "TGITENCR,MibSPI Transfer Group Interrupt Enable Clear Register"
|
|
bitfld.long 0x04 31. " CLRINTENRDY15 ,TG interrupt clear (disabled) when transfer finished" "Disabled,Enabled"
|
|
bitfld.long 0x04 30. " CLRINTENRDY14 ,TG interrupt clear (disabled) when transfer finished" "Disabled,Enabled"
|
|
bitfld.long 0x04 29. " CLRINTENRDY13 ,TG interrupt clear (disabled) when transfer finished" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x04 28. " CLRINTENRDY12 ,TG interrupt clear (disabled) when transfer finished" "Disabled,Enabled"
|
|
bitfld.long 0x04 27. " CLRINTENRDY11 ,TG interrupt clear (disabled) when transfer finished" "Disabled,Enabled"
|
|
bitfld.long 0x04 26. " CLRINTENRDY10 ,TG interrupt clear (disabled) when transfer finished" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x04 25. " CLRINTENRDY9 ,TG interrupt clear (disabled) when transfer finished" "Disabled,Enabled"
|
|
bitfld.long 0x04 24. " CLRINTENRDY8 ,TG interrupt clear (disabled) when transfer finished" "Disabled,Enabled"
|
|
bitfld.long 0x04 23. " CLRINTENRDY7 ,TG interrupt clear (disabled) when transfer finished" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x04 22. " CLRINTENRDY6 ,TG interrupt clear (disabled) when transfer finished" "Disabled,Enabled"
|
|
bitfld.long 0x04 21. " CLRINTENRDY5 ,TG interrupt clear (disabled) when transfer finished" "Disabled,Enabled"
|
|
bitfld.long 0x04 20. " CLRINTENRDY4 ,TG interrupt clear (disabled) when transfer finished" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x04 19. " CLRINTENRDY3 ,TG interrupt clear (disabled) when transfer finished" "Disabled,Enabled"
|
|
bitfld.long 0x04 18. " CLRINTENRDY2 ,TG interrupt clear (disabled) when transfer finished" "Disabled,Enabled"
|
|
bitfld.long 0x04 17. " CLRINTENRDY1 ,TG interrupt clear (disabled) when transfer finished" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x04 16. " CLRINTENRDY0 ,TG interrupt clear (disabled) when transfer finished" "Disabled,Enabled"
|
|
bitfld.long 0x04 15. " CLRINTENSUS15 ,TG interrupt clear (disabled) when transfer suspended" "Disabled,Enabled"
|
|
bitfld.long 0x04 14. " CLRINTENSUS14 ,TG interrupt clear (disabled) when transfer suspended" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x04 13. " CLRINTENSUS13 ,TG interrupt clear (disabled) when transfer suspended" "Disabled,Enabled"
|
|
bitfld.long 0x04 12. " CLRINTENSUS12 ,TG interrupt clear (disabled) when transfer suspended" "Disabled,Enabled"
|
|
bitfld.long 0x04 11. " CLRINTENSUS11 ,TG interrupt clear (disabled) when transfer suspended" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x04 10. " CLRINTENSUS10 ,TG interrupt clear (disabled) when transfer suspended" "Disabled,Enabled"
|
|
bitfld.long 0x04 9. " CLRINTENSUS9 ,TG interrupt clear (disabled) when transfer suspended" "Disabled,Enabled"
|
|
bitfld.long 0x04 8. " CLRINTENSUS8 ,TG interrupt clear (disabled) when transfer suspended" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x04 7. " CLRINTENSUS7 ,TG interrupt clear (disabled) when transfer suspended" "Disabled,Enabled"
|
|
bitfld.long 0x04 6. " CLRINTENSUS6 ,TG interrupt clear (disabled) when transfer suspended" "Disabled,Enabled"
|
|
bitfld.long 0x04 5. " CLRINTENSUS5 ,TG interrupt clear (disabled) when transfer suspended" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x04 4. " CLRINTENSUS4 ,TG interrupt clear (disabled) when transfer suspended" "Disabled,Enabled"
|
|
bitfld.long 0x04 3. " CLRINTENSUS3 ,TG interrupt clear (disabled) when transfer suspended" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " CLRINTENSUS2 ,TG interrupt clear (disabled) when transfer suspended" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x04 1. " CLRINTENSUS1 ,TG interrupt clear (disabled) when transfer suspended" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " CLRINTENSUS0 ,TG interrupt clear (disabled) when transfer suspended" "Disabled,Enabled"
|
|
line.long 0x08 "TGITLVST,MibSPI Transfer Group Interrupt Level Set Register"
|
|
bitfld.long 0x08 31. " SETINTLVLRDY15 ,Transfer-group completed interrupt level set" "INT0,INT1"
|
|
bitfld.long 0x08 30. " SETINTLVLRDY14 ,Transfer-group completed interrupt level set" "INT0,INT1"
|
|
bitfld.long 0x08 29. " SETINTLVLRDY13 ,Transfer-group completed interrupt level set" "INT0,INT1"
|
|
newline
|
|
bitfld.long 0x08 28. " SETINTLVLRDY12 ,Transfer-group completed interrupt level set" "INT0,INT1"
|
|
bitfld.long 0x08 27. " SETINTLVLRDY11 ,Transfer-group completed interrupt level set" "INT0,INT1"
|
|
bitfld.long 0x08 26. " SETINTLVLRDY10 ,Transfer-group completed interrupt level set" "INT0,INT1"
|
|
newline
|
|
bitfld.long 0x08 25. " SETINTLVLRDY9 ,Transfer-group completed interrupt level set" "INT0,INT1"
|
|
bitfld.long 0x08 24. " SETINTLVLRDY8 ,Transfer-group completed interrupt level set" "INT0,INT1"
|
|
bitfld.long 0x08 23. " SETINTLVLRDY7 ,Transfer-group completed interrupt level set" "INT0,INT1"
|
|
newline
|
|
bitfld.long 0x08 22. " SETINTLVLRDY6 ,Transfer-group completed interrupt level set" "INT0,INT1"
|
|
bitfld.long 0x08 21. " SETINTLVLRDY5 ,Transfer-group completed interrupt level set" "INT0,INT1"
|
|
bitfld.long 0x08 20. " SETINTLVLRDY4 ,Transfer-group completed interrupt level set" "INT0,INT1"
|
|
newline
|
|
bitfld.long 0x08 19. " SETINTLVLRDY3 ,Transfer-group completed interrupt level set" "INT0,INT1"
|
|
bitfld.long 0x08 18. " SETINTLVLRDY2 ,Transfer-group completed interrupt level set" "INT0,INT1"
|
|
bitfld.long 0x08 17. " SETINTLVLRDY1 ,Transfer-group completed interrupt level set" "INT0,INT1"
|
|
newline
|
|
bitfld.long 0x08 16. " SETINTLVLRDY0 ,Transfer-group completed interrupt level set" "INT0,INT1"
|
|
bitfld.long 0x08 15. " SETINTLVLSUS15 ,Transfer-group suspended interrupt level set" "INT0,INT1"
|
|
bitfld.long 0x08 14. " SETINTLVLSUS14 ,Transfer-group suspended interrupt level set" "INT0,INT1"
|
|
newline
|
|
bitfld.long 0x08 13. " SETINTLVLSUS13 ,Transfer-group suspended interrupt level set" "INT0,INT1"
|
|
bitfld.long 0x08 12. " SETINTLVLSUS12 ,Transfer-group suspended interrupt level set" "INT0,INT1"
|
|
bitfld.long 0x08 11. " SETINTLVLSUS11 ,Transfer-group suspended interrupt level set" "INT0,INT1"
|
|
newline
|
|
bitfld.long 0x08 10. " SETINTLVLSUS10 ,Transfer-group suspended interrupt level set" "INT0,INT1"
|
|
bitfld.long 0x08 9. " SETINTLVLSUS9 ,Transfer-group suspended interrupt level set" "INT0,INT1"
|
|
bitfld.long 0x08 8. " SETINTLVLSUS8 ,Transfer-group suspended interrupt level set" "INT0,INT1"
|
|
newline
|
|
bitfld.long 0x08 7. " SETINTLVLSUS7 ,Transfer-group suspended interrupt level set" "INT0,INT1"
|
|
bitfld.long 0x08 6. " SETINTLVLSUS6 ,Transfer-group suspended interrupt level set" "INT0,INT1"
|
|
bitfld.long 0x08 5. " SETINTLVLSUS5 ,Transfer-group suspended interrupt level set" "INT0,INT1"
|
|
newline
|
|
bitfld.long 0x08 4. " SETINTLVLSUS4 ,Transfer-group suspended interrupt level set" "INT0,INT1"
|
|
bitfld.long 0x08 3. " SETINTLVLSUS3 ,Transfer-group suspended interrupt level set" "INT0,INT1"
|
|
bitfld.long 0x08 2. " SETINTLVLSUS2 ,Transfer-group suspended interrupt level set" "INT0,INT1"
|
|
newline
|
|
bitfld.long 0x08 1. " SETINTLVLSUS1 ,Transfer-group suspended interrupt level set" "INT0,INT1"
|
|
bitfld.long 0x08 0. " SETINTLVLSUS0 ,Transfer-group suspended interrupt level set" "INT0,INT1"
|
|
line.long 0x0C "TGITLVCR,MibSPI Transfer Group Interrupt Level Clear Register"
|
|
bitfld.long 0x0C 31. " CLRINTLVLRDY15 ,Transfer-group completed interrupt level clear" "INT0,INT1"
|
|
bitfld.long 0x0C 30. " CLRINTLVLRDY14 ,Transfer-group completed interrupt level clear" "INT0,INT1"
|
|
bitfld.long 0x0C 29. " CLRINTLVLRDY13 ,Transfer-group completed interrupt level clear" "INT0,INT1"
|
|
newline
|
|
bitfld.long 0x0C 28. " CLRINTLVLRDY12 ,Transfer-group completed interrupt level clear" "INT0,INT1"
|
|
bitfld.long 0x0C 27. " CLRINTLVLRDY11 ,Transfer-group completed interrupt level clear" "INT0,INT1"
|
|
bitfld.long 0x0C 26. " CLRINTLVLRDY10 ,Transfer-group completed interrupt level clear" "INT0,INT1"
|
|
newline
|
|
bitfld.long 0x0C 25. " CLRINTLVLRDY9 ,Transfer-group completed interrupt level clear" "INT0,INT1"
|
|
bitfld.long 0x0C 24. " CLRINTLVLRDY8 ,Transfer-group completed interrupt level clear" "INT0,INT1"
|
|
bitfld.long 0x0C 23. " CLRINTLVLRDY7 ,Transfer-group completed interrupt level clear" "INT0,INT1"
|
|
newline
|
|
bitfld.long 0x0C 22. " CLRINTLVLRDY6 ,Transfer-group completed interrupt level clear" "INT0,INT1"
|
|
bitfld.long 0x0C 21. " CLRINTLVLRDY5 ,Transfer-group completed interrupt level clear" "INT0,INT1"
|
|
bitfld.long 0x0C 20. " CLRINTLVLRDY4 ,Transfer-group completed interrupt level clear" "INT0,INT1"
|
|
newline
|
|
bitfld.long 0x0C 19. " CLRINTLVLRDY3 ,Transfer-group completed interrupt level clear" "INT0,INT1"
|
|
bitfld.long 0x0C 18. " CLRINTLVLRDY2 ,Transfer-group completed interrupt level clear" "INT0,INT1"
|
|
bitfld.long 0x0C 17. " CLRINTLVLRDY1 ,Transfer-group completed interrupt level clear" "INT0,INT1"
|
|
newline
|
|
bitfld.long 0x0C 16. " CLRINTLVLRDY0 ,Transfer-group completed interrupt level clear" "INT0,INT1"
|
|
bitfld.long 0x0C 15. " CLRINTLVLSUS15 ,Transfer group suspended interrupt level clear" "INT0,INT1"
|
|
bitfld.long 0x0C 14. " CLRINTLVLSUS14 ,Transfer group suspended interrupt level clear" "INT0,INT1"
|
|
newline
|
|
bitfld.long 0x0C 13. " CLRINTLVLSUS13 ,Transfer group suspended interrupt level clear" "INT0,INT1"
|
|
bitfld.long 0x0C 12. " CLRINTLVLSUS12 ,Transfer group suspended interrupt level clear" "INT0,INT1"
|
|
bitfld.long 0x0C 11. " CLRINTLVLSUS11 ,Transfer group suspended interrupt level clear" "INT0,INT1"
|
|
newline
|
|
bitfld.long 0x0C 10. " CLRINTLVLSUS10 ,Transfer group suspended interrupt level clear" "INT0,INT1"
|
|
bitfld.long 0x0C 9. " CLRINTLVLSUS9 ,Transfer group suspended interrupt level clear" "INT0,INT1"
|
|
bitfld.long 0x0C 8. " CLRINTLVLSUS8 ,Transfer group suspended interrupt level clear" "INT0,INT1"
|
|
newline
|
|
bitfld.long 0x0C 7. " CLRINTLVLSUS7 ,Transfer group suspended interrupt level clear" "INT0,INT1"
|
|
bitfld.long 0x0C 6. " CLRINTLVLSUS6 ,Transfer group suspended interrupt level clear" "INT0,INT1"
|
|
bitfld.long 0x0C 5. " CLRINTLVLSUS5 ,Transfer group suspended interrupt level clear" "INT0,INT1"
|
|
newline
|
|
bitfld.long 0x0C 4. " CLRINTLVLSUS4 ,Transfer group suspended interrupt level clear" "INT0,INT1"
|
|
bitfld.long 0x0C 3. " CLRINTLVLSUS3 ,Transfer group suspended interrupt level clear" "INT0,INT1"
|
|
bitfld.long 0x0C 2. " CLRINTLVLSUS2 ,Transfer group suspended interrupt level clear" "INT0,INT1"
|
|
newline
|
|
bitfld.long 0x0C 1. " CLRINTLVLSUS1 ,Transfer group suspended interrupt level clear" "INT0,INT1"
|
|
bitfld.long 0x0C 0. " CLRINTLVLSUS0 ,Transfer group suspended interrupt level clear" "INT0,INT1"
|
|
group.long 0x84++0x03
|
|
line.long 0x00 "TGITFLG,Transfer Group Interrupt Flag Register"
|
|
sif (cpu()==("TMS570LS0332")||cpu()==("TMS570LS0432")||cpuis("TMS570LS1114*")||cpuis("TMS570LS1115*")||cpuis("TMS570LS1224*")||cpuis("TMS570LS1225*")||cpuis("TMS570LS1227*")||cpuis("TMS570LS0232")||cpuis("TMS570LS0714*")||cpuis("TMS570LS0914*"))
|
|
bitfld.long 0x00 31. " INTFLGRDY[15] ,Transfer-group interrupt flag for a transfer-completed interrupt 15" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " INTFLGRDY[14] ,Transfer-group interrupt flag for a transfer-completed interrupt 14" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 29. " INTFLGRDY[13] ,Transfer-group interrupt flag for a transfer-completed interrupt 13" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " INTFLGRDY[12] ,Transfer-group interrupt flag for a transfer-completed interrupt 12" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 27. " INTFLGRDY[11] ,Transfer-group interrupt flag for a transfer-completed interrupt 11" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " INTFLGRDY[10] ,Transfer-group interrupt flag for a transfer-completed interrupt 10" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 25. " INTFLGRDY[9] ,Transfer-group interrupt flag for a transfer-completed interrupt 9" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " INTFLGRDY[8] ,Transfer-group interrupt flag for a transfer-completed interrupt 8" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 23. " INTFLGRDY[7] ,Transfer-group interrupt flag for a transfer-completed interrupt 7" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " INTFLGRDY[6] ,Transfer-group interrupt flag for a transfer-completed interrupt 6" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 21. " INTFLGRDY[5] ,Transfer-group interrupt flag for a transfer-completed interrupt 5" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " INTFLGRDY[4] ,Transfer-group interrupt flag for a transfer-completed interrupt 4" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 19. " INTFLGRDY[3] ,Transfer-group interrupt flag for a transfer-completed interrupt 3" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " INTFLGRDY[2] ,Transfer-group interrupt flag for a transfer-completed interrupt 2" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 17. " INTFLGRDY[1] ,Transfer-group interrupt flag for a transfer-completed interrupt 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " INTFLGRDY[0] ,Transfer-group interrupt flag for a transfer-completed interrupt 0" "Disabled,Enabled"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 15. " INTFLGSUS[15] ,Transfer-group interrupt flag for a transfer-suspend interrupt 15" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " INTFLGSUS[14] ,Transfer-group interrupt flag for a transfer-suspend interrupt 14" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 13. " INTFLGSUS[13] ,Transfer-group interrupt flag for a transfer-suspend interrupt 13" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " INTFLGSUS[12] ,Transfer-group interrupt flag for a transfer-suspend interrupt 12" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 11. " INTFLGSUS[11] ,Transfer-group interrupt flag for a transfer-suspend interrupt 11" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " INTFLGSUS[10] ,Transfer-group interrupt flag for a transfer-suspend interrupt 10" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 9. " INTFLGSUS[9] ,Transfer-group interrupt flag for a transfer-suspend interrupt 9" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " INTFLGSUS[8] ,Transfer-group interrupt flag for a transfer-suspend interrupt 8" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 7. " INTFLGSUS[7] ,Transfer-group interrupt flag for a transfer-suspend interrupt 7" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " INTFLGSUS[6] ,Transfer-group interrupt flag for a transfer-suspend interrupt 6" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 5. " INTFLGSUS[5] ,Transfer-group interrupt flag for a transfer-suspend interrupt 5" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " INTFLGSUS[4] ,Transfer-group interrupt flag for a transfer-suspend interrupt 4" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 3. " INTFLGSUS[3] ,Transfer-group interrupt flag for a transfer-suspend interrupt 3" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " INTFLGSUS[2] ,Transfer-group interrupt flag for a transfer-suspend interrupt 2" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 1. " INTFLGSUS[1] ,Transfer-group interrupt flag for a transfer-suspend interrupt 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " INTFLGSUS[0] ,Transfer-group interrupt flag for a transfer-suspend interrupt 0" "Disabled,Enabled"
|
|
group.long 0x90++0x47
|
|
line.long 0x00 "TICKCNT,Tick Count Register"
|
|
bitfld.long 0x00 31. " TICKENA ,Tick counter enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " RELOAD ,Pre-load the tick counter" "No effect,Reload"
|
|
bitfld.long 0x00 28.--29. " CLKCTRL ,Tick counter clock source control" "0,1,2,3"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TICKVALUE ,Initial value for the tick counter"
|
|
line.long 0x04 "LTGPEND,Last Transfer Group End Pointer Register"
|
|
bitfld.long 0x04 24.--28. " TGINSERVICE ,The TG number currently being serviced by the sequencer" "No TG,TG0,TG1,TG2,TG3,TG4,TG5,TG6,TG7,TG8,TG9,TG10,TG11,TG12,TG13,TG14,TG15,?..."
|
|
hexmask.long.byte 0x04 8.--14. 1. " LPEND ,Last TG end pointer"
|
|
line.long 0x8 "TG0CTRL,MibSPI Transfer Group Control Register 0"
|
|
bitfld.long 0x8 31. " TGENA ,TG enable" "Disabled,Enabled"
|
|
bitfld.long 0x8 30. " ONESHOT ,Single transfer for TG" "Disabled,Enabled"
|
|
bitfld.long 0x8 29. " PRST ,TG pointer reset mode" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x8 28. " TGTD ,TG triggered" "Not triggered,Triggered"
|
|
bitfld.long 0x8 20.--23. " TRGEVT ,Type of trigger event" "Never,Rising edge,Falling edge,Both edges,,High active,Low-active,Always,?..."
|
|
sif cpuis("TMS570LS0232")||cpuis("TMS570LS0714*")||cpuis("TMS570LS0914*")
|
|
bitfld.long 0x8 16.--19. " TRIGSRC ,Trigger source" "Disabled,EXT0,EXT1,EXT2,EXT3,EXT4,EXT5,EXT6,EXT7,EXT8,EXT9,EXT10,EXT11,EXT12,EXT13,TICK"
|
|
else
|
|
bitfld.long 0x8 16.--19. " TRIGSRC ,Trigger source" "Disabled,GIOA[0],GIOA[1],GIOA[2],GIOA[3],GIOA[4],GIOA[5],GIOA[6],GIOA[7],N2HET1[8],N2HET1[10],N2HET1[12],N2HET1[14],N2HET1[16],N2HET1[18],TICK"
|
|
endif
|
|
newline
|
|
hexmask.long.byte 0x8 8.--14. 0x01 " PSTART ,TG start address"
|
|
hexmask.long.byte 0x8 0.--6. 0x01 " PCURRENT ,Pointer to current buffer"
|
|
line.long 0xC "TG1CTRL,MibSPI Transfer Group Control Register 1"
|
|
bitfld.long 0xC 31. " TGENA ,TG enable" "Disabled,Enabled"
|
|
bitfld.long 0xC 30. " ONESHOT ,Single transfer for TG" "Disabled,Enabled"
|
|
bitfld.long 0xC 29. " PRST ,TG pointer reset mode" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0xC 28. " TGTD ,TG triggered" "Not triggered,Triggered"
|
|
bitfld.long 0xC 20.--23. " TRGEVT ,Type of trigger event" "Never,Rising edge,Falling edge,Both edges,,High active,Low-active,Always,?..."
|
|
sif cpuis("TMS570LS0232")||cpuis("TMS570LS0714*")||cpuis("TMS570LS0914*")
|
|
bitfld.long 0xC 16.--19. " TRIGSRC ,Trigger source" "Disabled,EXT0,EXT1,EXT2,EXT3,EXT4,EXT5,EXT6,EXT7,EXT8,EXT9,EXT10,EXT11,EXT12,EXT13,TICK"
|
|
else
|
|
bitfld.long 0xC 16.--19. " TRIGSRC ,Trigger source" "Disabled,GIOA[0],GIOA[1],GIOA[2],GIOA[3],GIOA[4],GIOA[5],GIOA[6],GIOA[7],N2HET1[8],N2HET1[10],N2HET1[12],N2HET1[14],N2HET1[16],N2HET1[18],TICK"
|
|
endif
|
|
newline
|
|
hexmask.long.byte 0xC 8.--14. 0x01 " PSTART ,TG start address"
|
|
hexmask.long.byte 0xC 0.--6. 0x01 " PCURRENT ,Pointer to current buffer"
|
|
line.long 0x10 "TG2CTRL,MibSPI Transfer Group Control Register 2"
|
|
bitfld.long 0x10 31. " TGENA ,TG enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 30. " ONESHOT ,Single transfer for TG" "Disabled,Enabled"
|
|
bitfld.long 0x10 29. " PRST ,TG pointer reset mode" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x10 28. " TGTD ,TG triggered" "Not triggered,Triggered"
|
|
bitfld.long 0x10 20.--23. " TRGEVT ,Type of trigger event" "Never,Rising edge,Falling edge,Both edges,,High active,Low-active,Always,?..."
|
|
sif cpuis("TMS570LS0232")||cpuis("TMS570LS0714*")||cpuis("TMS570LS0914*")
|
|
bitfld.long 0x10 16.--19. " TRIGSRC ,Trigger source" "Disabled,EXT0,EXT1,EXT2,EXT3,EXT4,EXT5,EXT6,EXT7,EXT8,EXT9,EXT10,EXT11,EXT12,EXT13,TICK"
|
|
else
|
|
bitfld.long 0x10 16.--19. " TRIGSRC ,Trigger source" "Disabled,GIOA[0],GIOA[1],GIOA[2],GIOA[3],GIOA[4],GIOA[5],GIOA[6],GIOA[7],N2HET1[8],N2HET1[10],N2HET1[12],N2HET1[14],N2HET1[16],N2HET1[18],TICK"
|
|
endif
|
|
newline
|
|
hexmask.long.byte 0x10 8.--14. 0x01 " PSTART ,TG start address"
|
|
hexmask.long.byte 0x10 0.--6. 0x01 " PCURRENT ,Pointer to current buffer"
|
|
line.long 0x14 "TG3CTRL,MibSPI Transfer Group Control Register 3"
|
|
bitfld.long 0x14 31. " TGENA ,TG enable" "Disabled,Enabled"
|
|
bitfld.long 0x14 30. " ONESHOT ,Single transfer for TG" "Disabled,Enabled"
|
|
bitfld.long 0x14 29. " PRST ,TG pointer reset mode" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x14 28. " TGTD ,TG triggered" "Not triggered,Triggered"
|
|
bitfld.long 0x14 20.--23. " TRGEVT ,Type of trigger event" "Never,Rising edge,Falling edge,Both edges,,High active,Low-active,Always,?..."
|
|
sif cpuis("TMS570LS0232")||cpuis("TMS570LS0714*")||cpuis("TMS570LS0914*")
|
|
bitfld.long 0x14 16.--19. " TRIGSRC ,Trigger source" "Disabled,EXT0,EXT1,EXT2,EXT3,EXT4,EXT5,EXT6,EXT7,EXT8,EXT9,EXT10,EXT11,EXT12,EXT13,TICK"
|
|
else
|
|
bitfld.long 0x14 16.--19. " TRIGSRC ,Trigger source" "Disabled,GIOA[0],GIOA[1],GIOA[2],GIOA[3],GIOA[4],GIOA[5],GIOA[6],GIOA[7],N2HET1[8],N2HET1[10],N2HET1[12],N2HET1[14],N2HET1[16],N2HET1[18],TICK"
|
|
endif
|
|
newline
|
|
hexmask.long.byte 0x14 8.--14. 0x01 " PSTART ,TG start address"
|
|
hexmask.long.byte 0x14 0.--6. 0x01 " PCURRENT ,Pointer to current buffer"
|
|
line.long 0x18 "TG4CTRL,MibSPI Transfer Group Control Register 4"
|
|
bitfld.long 0x18 31. " TGENA ,TG enable" "Disabled,Enabled"
|
|
bitfld.long 0x18 30. " ONESHOT ,Single transfer for TG" "Disabled,Enabled"
|
|
bitfld.long 0x18 29. " PRST ,TG pointer reset mode" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x18 28. " TGTD ,TG triggered" "Not triggered,Triggered"
|
|
bitfld.long 0x18 20.--23. " TRGEVT ,Type of trigger event" "Never,Rising edge,Falling edge,Both edges,,High active,Low-active,Always,?..."
|
|
sif cpuis("TMS570LS0232")||cpuis("TMS570LS0714*")||cpuis("TMS570LS0914*")
|
|
bitfld.long 0x18 16.--19. " TRIGSRC ,Trigger source" "Disabled,EXT0,EXT1,EXT2,EXT3,EXT4,EXT5,EXT6,EXT7,EXT8,EXT9,EXT10,EXT11,EXT12,EXT13,TICK"
|
|
else
|
|
bitfld.long 0x18 16.--19. " TRIGSRC ,Trigger source" "Disabled,GIOA[0],GIOA[1],GIOA[2],GIOA[3],GIOA[4],GIOA[5],GIOA[6],GIOA[7],N2HET1[8],N2HET1[10],N2HET1[12],N2HET1[14],N2HET1[16],N2HET1[18],TICK"
|
|
endif
|
|
newline
|
|
hexmask.long.byte 0x18 8.--14. 0x01 " PSTART ,TG start address"
|
|
hexmask.long.byte 0x18 0.--6. 0x01 " PCURRENT ,Pointer to current buffer"
|
|
line.long 0x1C "TG5CTRL,MibSPI Transfer Group Control Register 5"
|
|
bitfld.long 0x1C 31. " TGENA ,TG enable" "Disabled,Enabled"
|
|
bitfld.long 0x1C 30. " ONESHOT ,Single transfer for TG" "Disabled,Enabled"
|
|
bitfld.long 0x1C 29. " PRST ,TG pointer reset mode" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x1C 28. " TGTD ,TG triggered" "Not triggered,Triggered"
|
|
bitfld.long 0x1C 20.--23. " TRGEVT ,Type of trigger event" "Never,Rising edge,Falling edge,Both edges,,High active,Low-active,Always,?..."
|
|
sif cpuis("TMS570LS0232")||cpuis("TMS570LS0714*")||cpuis("TMS570LS0914*")
|
|
bitfld.long 0x1C 16.--19. " TRIGSRC ,Trigger source" "Disabled,EXT0,EXT1,EXT2,EXT3,EXT4,EXT5,EXT6,EXT7,EXT8,EXT9,EXT10,EXT11,EXT12,EXT13,TICK"
|
|
else
|
|
bitfld.long 0x1C 16.--19. " TRIGSRC ,Trigger source" "Disabled,GIOA[0],GIOA[1],GIOA[2],GIOA[3],GIOA[4],GIOA[5],GIOA[6],GIOA[7],N2HET1[8],N2HET1[10],N2HET1[12],N2HET1[14],N2HET1[16],N2HET1[18],TICK"
|
|
endif
|
|
newline
|
|
hexmask.long.byte 0x1C 8.--14. 0x01 " PSTART ,TG start address"
|
|
hexmask.long.byte 0x1C 0.--6. 0x01 " PCURRENT ,Pointer to current buffer"
|
|
line.long 0x20 "TG6CTRL,MibSPI Transfer Group Control Register 6"
|
|
bitfld.long 0x20 31. " TGENA ,TG enable" "Disabled,Enabled"
|
|
bitfld.long 0x20 30. " ONESHOT ,Single transfer for TG" "Disabled,Enabled"
|
|
bitfld.long 0x20 29. " PRST ,TG pointer reset mode" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x20 28. " TGTD ,TG triggered" "Not triggered,Triggered"
|
|
bitfld.long 0x20 20.--23. " TRGEVT ,Type of trigger event" "Never,Rising edge,Falling edge,Both edges,,High active,Low-active,Always,?..."
|
|
sif cpuis("TMS570LS0232")||cpuis("TMS570LS0714*")||cpuis("TMS570LS0914*")
|
|
bitfld.long 0x20 16.--19. " TRIGSRC ,Trigger source" "Disabled,EXT0,EXT1,EXT2,EXT3,EXT4,EXT5,EXT6,EXT7,EXT8,EXT9,EXT10,EXT11,EXT12,EXT13,TICK"
|
|
else
|
|
bitfld.long 0x20 16.--19. " TRIGSRC ,Trigger source" "Disabled,GIOA[0],GIOA[1],GIOA[2],GIOA[3],GIOA[4],GIOA[5],GIOA[6],GIOA[7],N2HET1[8],N2HET1[10],N2HET1[12],N2HET1[14],N2HET1[16],N2HET1[18],TICK"
|
|
endif
|
|
newline
|
|
hexmask.long.byte 0x20 8.--14. 0x01 " PSTART ,TG start address"
|
|
hexmask.long.byte 0x20 0.--6. 0x01 " PCURRENT ,Pointer to current buffer"
|
|
line.long 0x24 "TG7CTRL,MibSPI Transfer Group Control Register 7"
|
|
bitfld.long 0x24 31. " TGENA ,TG enable" "Disabled,Enabled"
|
|
bitfld.long 0x24 30. " ONESHOT ,Single transfer for TG" "Disabled,Enabled"
|
|
bitfld.long 0x24 29. " PRST ,TG pointer reset mode" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x24 28. " TGTD ,TG triggered" "Not triggered,Triggered"
|
|
bitfld.long 0x24 20.--23. " TRGEVT ,Type of trigger event" "Never,Rising edge,Falling edge,Both edges,,High active,Low-active,Always,?..."
|
|
sif cpuis("TMS570LS0232")||cpuis("TMS570LS0714*")||cpuis("TMS570LS0914*")
|
|
bitfld.long 0x24 16.--19. " TRIGSRC ,Trigger source" "Disabled,EXT0,EXT1,EXT2,EXT3,EXT4,EXT5,EXT6,EXT7,EXT8,EXT9,EXT10,EXT11,EXT12,EXT13,TICK"
|
|
else
|
|
bitfld.long 0x24 16.--19. " TRIGSRC ,Trigger source" "Disabled,GIOA[0],GIOA[1],GIOA[2],GIOA[3],GIOA[4],GIOA[5],GIOA[6],GIOA[7],N2HET1[8],N2HET1[10],N2HET1[12],N2HET1[14],N2HET1[16],N2HET1[18],TICK"
|
|
endif
|
|
newline
|
|
hexmask.long.byte 0x24 8.--14. 0x01 " PSTART ,TG start address"
|
|
hexmask.long.byte 0x24 0.--6. 0x01 " PCURRENT ,Pointer to current buffer"
|
|
line.long 0x28 "TG8CTRL,MibSPI Transfer Group Control Register 8"
|
|
bitfld.long 0x28 31. " TGENA ,TG enable" "Disabled,Enabled"
|
|
bitfld.long 0x28 30. " ONESHOT ,Single transfer for TG" "Disabled,Enabled"
|
|
bitfld.long 0x28 29. " PRST ,TG pointer reset mode" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x28 28. " TGTD ,TG triggered" "Not triggered,Triggered"
|
|
bitfld.long 0x28 20.--23. " TRGEVT ,Type of trigger event" "Never,Rising edge,Falling edge,Both edges,,High active,Low-active,Always,?..."
|
|
sif cpuis("TMS570LS0232")||cpuis("TMS570LS0714*")||cpuis("TMS570LS0914*")
|
|
bitfld.long 0x28 16.--19. " TRIGSRC ,Trigger source" "Disabled,EXT0,EXT1,EXT2,EXT3,EXT4,EXT5,EXT6,EXT7,EXT8,EXT9,EXT10,EXT11,EXT12,EXT13,TICK"
|
|
else
|
|
bitfld.long 0x28 16.--19. " TRIGSRC ,Trigger source" "Disabled,GIOA[0],GIOA[1],GIOA[2],GIOA[3],GIOA[4],GIOA[5],GIOA[6],GIOA[7],N2HET1[8],N2HET1[10],N2HET1[12],N2HET1[14],N2HET1[16],N2HET1[18],TICK"
|
|
endif
|
|
newline
|
|
hexmask.long.byte 0x28 8.--14. 0x01 " PSTART ,TG start address"
|
|
hexmask.long.byte 0x28 0.--6. 0x01 " PCURRENT ,Pointer to current buffer"
|
|
line.long 0x2C "TG9CTRL,MibSPI Transfer Group Control Register 9"
|
|
bitfld.long 0x2C 31. " TGENA ,TG enable" "Disabled,Enabled"
|
|
bitfld.long 0x2C 30. " ONESHOT ,Single transfer for TG" "Disabled,Enabled"
|
|
bitfld.long 0x2C 29. " PRST ,TG pointer reset mode" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x2C 28. " TGTD ,TG triggered" "Not triggered,Triggered"
|
|
bitfld.long 0x2C 20.--23. " TRGEVT ,Type of trigger event" "Never,Rising edge,Falling edge,Both edges,,High active,Low-active,Always,?..."
|
|
sif cpuis("TMS570LS0232")||cpuis("TMS570LS0714*")||cpuis("TMS570LS0914*")
|
|
bitfld.long 0x2C 16.--19. " TRIGSRC ,Trigger source" "Disabled,EXT0,EXT1,EXT2,EXT3,EXT4,EXT5,EXT6,EXT7,EXT8,EXT9,EXT10,EXT11,EXT12,EXT13,TICK"
|
|
else
|
|
bitfld.long 0x2C 16.--19. " TRIGSRC ,Trigger source" "Disabled,GIOA[0],GIOA[1],GIOA[2],GIOA[3],GIOA[4],GIOA[5],GIOA[6],GIOA[7],N2HET1[8],N2HET1[10],N2HET1[12],N2HET1[14],N2HET1[16],N2HET1[18],TICK"
|
|
endif
|
|
newline
|
|
hexmask.long.byte 0x2C 8.--14. 0x01 " PSTART ,TG start address"
|
|
hexmask.long.byte 0x2C 0.--6. 0x01 " PCURRENT ,Pointer to current buffer"
|
|
line.long 0x30 "TG10CTRL,MibSPI Transfer Group Control Register 10"
|
|
bitfld.long 0x30 31. " TGENA ,TG enable" "Disabled,Enabled"
|
|
bitfld.long 0x30 30. " ONESHOT ,Single transfer for TG" "Disabled,Enabled"
|
|
bitfld.long 0x30 29. " PRST ,TG pointer reset mode" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x30 28. " TGTD ,TG triggered" "Not triggered,Triggered"
|
|
bitfld.long 0x30 20.--23. " TRGEVT ,Type of trigger event" "Never,Rising edge,Falling edge,Both edges,,High active,Low-active,Always,?..."
|
|
sif cpuis("TMS570LS0232")||cpuis("TMS570LS0714*")||cpuis("TMS570LS0914*")
|
|
bitfld.long 0x30 16.--19. " TRIGSRC ,Trigger source" "Disabled,EXT0,EXT1,EXT2,EXT3,EXT4,EXT5,EXT6,EXT7,EXT8,EXT9,EXT10,EXT11,EXT12,EXT13,TICK"
|
|
else
|
|
bitfld.long 0x30 16.--19. " TRIGSRC ,Trigger source" "Disabled,GIOA[0],GIOA[1],GIOA[2],GIOA[3],GIOA[4],GIOA[5],GIOA[6],GIOA[7],N2HET1[8],N2HET1[10],N2HET1[12],N2HET1[14],N2HET1[16],N2HET1[18],TICK"
|
|
endif
|
|
newline
|
|
hexmask.long.byte 0x30 8.--14. 0x01 " PSTART ,TG start address"
|
|
hexmask.long.byte 0x30 0.--6. 0x01 " PCURRENT ,Pointer to current buffer"
|
|
line.long 0x34 "TG11CTRL,MibSPI Transfer Group Control Register 11"
|
|
bitfld.long 0x34 31. " TGENA ,TG enable" "Disabled,Enabled"
|
|
bitfld.long 0x34 30. " ONESHOT ,Single transfer for TG" "Disabled,Enabled"
|
|
bitfld.long 0x34 29. " PRST ,TG pointer reset mode" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x34 28. " TGTD ,TG triggered" "Not triggered,Triggered"
|
|
bitfld.long 0x34 20.--23. " TRGEVT ,Type of trigger event" "Never,Rising edge,Falling edge,Both edges,,High active,Low-active,Always,?..."
|
|
sif cpuis("TMS570LS0232")||cpuis("TMS570LS0714*")||cpuis("TMS570LS0914*")
|
|
bitfld.long 0x34 16.--19. " TRIGSRC ,Trigger source" "Disabled,EXT0,EXT1,EXT2,EXT3,EXT4,EXT5,EXT6,EXT7,EXT8,EXT9,EXT10,EXT11,EXT12,EXT13,TICK"
|
|
else
|
|
bitfld.long 0x34 16.--19. " TRIGSRC ,Trigger source" "Disabled,GIOA[0],GIOA[1],GIOA[2],GIOA[3],GIOA[4],GIOA[5],GIOA[6],GIOA[7],N2HET1[8],N2HET1[10],N2HET1[12],N2HET1[14],N2HET1[16],N2HET1[18],TICK"
|
|
endif
|
|
newline
|
|
hexmask.long.byte 0x34 8.--14. 0x01 " PSTART ,TG start address"
|
|
hexmask.long.byte 0x34 0.--6. 0x01 " PCURRENT ,Pointer to current buffer"
|
|
line.long 0x38 "TG12CTRL,MibSPI Transfer Group Control Register 12"
|
|
bitfld.long 0x38 31. " TGENA ,TG enable" "Disabled,Enabled"
|
|
bitfld.long 0x38 30. " ONESHOT ,Single transfer for TG" "Disabled,Enabled"
|
|
bitfld.long 0x38 29. " PRST ,TG pointer reset mode" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x38 28. " TGTD ,TG triggered" "Not triggered,Triggered"
|
|
bitfld.long 0x38 20.--23. " TRGEVT ,Type of trigger event" "Never,Rising edge,Falling edge,Both edges,,High active,Low-active,Always,?..."
|
|
sif cpuis("TMS570LS0232")||cpuis("TMS570LS0714*")||cpuis("TMS570LS0914*")
|
|
bitfld.long 0x38 16.--19. " TRIGSRC ,Trigger source" "Disabled,EXT0,EXT1,EXT2,EXT3,EXT4,EXT5,EXT6,EXT7,EXT8,EXT9,EXT10,EXT11,EXT12,EXT13,TICK"
|
|
else
|
|
bitfld.long 0x38 16.--19. " TRIGSRC ,Trigger source" "Disabled,GIOA[0],GIOA[1],GIOA[2],GIOA[3],GIOA[4],GIOA[5],GIOA[6],GIOA[7],N2HET1[8],N2HET1[10],N2HET1[12],N2HET1[14],N2HET1[16],N2HET1[18],TICK"
|
|
endif
|
|
newline
|
|
hexmask.long.byte 0x38 8.--14. 0x01 " PSTART ,TG start address"
|
|
hexmask.long.byte 0x38 0.--6. 0x01 " PCURRENT ,Pointer to current buffer"
|
|
line.long 0x3C "TG13CTRL,MibSPI Transfer Group Control Register 13"
|
|
bitfld.long 0x3C 31. " TGENA ,TG enable" "Disabled,Enabled"
|
|
bitfld.long 0x3C 30. " ONESHOT ,Single transfer for TG" "Disabled,Enabled"
|
|
bitfld.long 0x3C 29. " PRST ,TG pointer reset mode" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x3C 28. " TGTD ,TG triggered" "Not triggered,Triggered"
|
|
bitfld.long 0x3C 20.--23. " TRGEVT ,Type of trigger event" "Never,Rising edge,Falling edge,Both edges,,High active,Low-active,Always,?..."
|
|
sif cpuis("TMS570LS0232")||cpuis("TMS570LS0714*")||cpuis("TMS570LS0914*")
|
|
bitfld.long 0x3C 16.--19. " TRIGSRC ,Trigger source" "Disabled,EXT0,EXT1,EXT2,EXT3,EXT4,EXT5,EXT6,EXT7,EXT8,EXT9,EXT10,EXT11,EXT12,EXT13,TICK"
|
|
else
|
|
bitfld.long 0x3C 16.--19. " TRIGSRC ,Trigger source" "Disabled,GIOA[0],GIOA[1],GIOA[2],GIOA[3],GIOA[4],GIOA[5],GIOA[6],GIOA[7],N2HET1[8],N2HET1[10],N2HET1[12],N2HET1[14],N2HET1[16],N2HET1[18],TICK"
|
|
endif
|
|
newline
|
|
hexmask.long.byte 0x3C 8.--14. 0x01 " PSTART ,TG start address"
|
|
hexmask.long.byte 0x3C 0.--6. 0x01 " PCURRENT ,Pointer to current buffer"
|
|
line.long 0x40 "TG14CTRL,MibSPI Transfer Group Control Register 14"
|
|
bitfld.long 0x40 31. " TGENA ,TG enable" "Disabled,Enabled"
|
|
bitfld.long 0x40 30. " ONESHOT ,Single transfer for TG" "Disabled,Enabled"
|
|
bitfld.long 0x40 29. " PRST ,TG pointer reset mode" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x40 28. " TGTD ,TG triggered" "Not triggered,Triggered"
|
|
bitfld.long 0x40 20.--23. " TRGEVT ,Type of trigger event" "Never,Rising edge,Falling edge,Both edges,,High active,Low-active,Always,?..."
|
|
sif cpuis("TMS570LS0232")||cpuis("TMS570LS0714*")||cpuis("TMS570LS0914*")
|
|
bitfld.long 0x40 16.--19. " TRIGSRC ,Trigger source" "Disabled,EXT0,EXT1,EXT2,EXT3,EXT4,EXT5,EXT6,EXT7,EXT8,EXT9,EXT10,EXT11,EXT12,EXT13,TICK"
|
|
else
|
|
bitfld.long 0x40 16.--19. " TRIGSRC ,Trigger source" "Disabled,GIOA[0],GIOA[1],GIOA[2],GIOA[3],GIOA[4],GIOA[5],GIOA[6],GIOA[7],N2HET1[8],N2HET1[10],N2HET1[12],N2HET1[14],N2HET1[16],N2HET1[18],TICK"
|
|
endif
|
|
newline
|
|
hexmask.long.byte 0x40 8.--14. 0x01 " PSTART ,TG start address"
|
|
hexmask.long.byte 0x40 0.--6. 0x01 " PCURRENT ,Pointer to current buffer"
|
|
line.long 0x44 "TG15CTRL,MibSPI Transfer Group Control Register 15"
|
|
bitfld.long 0x44 31. " TGENA ,TG enable" "Disabled,Enabled"
|
|
bitfld.long 0x44 30. " ONESHOT ,Single transfer for TG" "Disabled,Enabled"
|
|
bitfld.long 0x44 29. " PRST ,TG pointer reset mode" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x44 28. " TGTD ,TG triggered" "Not triggered,Triggered"
|
|
bitfld.long 0x44 20.--23. " TRGEVT ,Type of trigger event" "Never,Rising edge,Falling edge,Both edges,,High active,Low-active,Always,?..."
|
|
sif cpuis("TMS570LS0232")||cpuis("TMS570LS0714*")||cpuis("TMS570LS0914*")
|
|
bitfld.long 0x44 16.--19. " TRIGSRC ,Trigger source" "Disabled,EXT0,EXT1,EXT2,EXT3,EXT4,EXT5,EXT6,EXT7,EXT8,EXT9,EXT10,EXT11,EXT12,EXT13,TICK"
|
|
else
|
|
bitfld.long 0x44 16.--19. " TRIGSRC ,Trigger source" "Disabled,GIOA[0],GIOA[1],GIOA[2],GIOA[3],GIOA[4],GIOA[5],GIOA[6],GIOA[7],N2HET1[8],N2HET1[10],N2HET1[12],N2HET1[14],N2HET1[16],N2HET1[18],TICK"
|
|
endif
|
|
newline
|
|
hexmask.long.byte 0x44 8.--14. 0x01 " PSTART ,TG start address"
|
|
hexmask.long.byte 0x44 0.--6. 0x01 " PCURRENT ,Pointer to current buffer"
|
|
sif (cpu()!=("TMS570LS0332")&&cpu()!=("TMS570LS0432")&&!cpuis("TMS570LS0232"))
|
|
group.long 0xD8++0x1F
|
|
line.long 0x0 "DMA0CTRL,MibSPI DMA Channel Control Register 1"
|
|
bitfld.long 0x0 31. " ONESHOT ,Auto-disable of DMA channel after ICOUNT+1 transfers" "0,1"
|
|
hexmask.long.byte 0x0 24.--30. 1. " BUFID ,Buffer utilized for DMA transfer"
|
|
bitfld.long 0x0 20.--23. " RXDMA_MAP ,Each MibSPI DMA channel can be linked to two physical DMA" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x0 16.--19. " TXDMA_MAP ,Each MibSPI DMA channel can be linked to two physical DMA" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x0 15. " RXDMAENA ,Receive data DMA channel enable" "Disabled,Enabled"
|
|
bitfld.long 0x0 14. " TXDMAENA ,Transmit data DMA channel enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x0 13. " NOBRK ,Non-interleaved DMA block transfer" "Not performed,Performed"
|
|
bitfld.long 0x0 8.--12. " ICOUNT ,Initial count of DMA transfers" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32"
|
|
bitfld.long 0x0 6. " COUNTBIT17 ,17th bit of the COUNT field of DMAxCOUNT register" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0.--5. " COUNT ,Actual number of remaining DMA transfers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
line.long 0x4 "DMA1CTRL,MibSPI DMA Channel Control Register 1"
|
|
bitfld.long 0x4 31. " ONESHOT ,Auto-disable of DMA channel after ICOUNT+1 transfers" "0,1"
|
|
hexmask.long.byte 0x4 24.--30. 1. " BUFID ,Buffer utilized for DMA transfer"
|
|
bitfld.long 0x4 20.--23. " RXDMA_MAP ,Each MibSPI DMA channel can be linked to two physical DMA" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x4 16.--19. " TXDMA_MAP ,Each MibSPI DMA channel can be linked to two physical DMA" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x4 15. " RXDMAENA ,Receive data DMA channel enable" "Disabled,Enabled"
|
|
bitfld.long 0x4 14. " TXDMAENA ,Transmit data DMA channel enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x4 13. " NOBRK ,Non-interleaved DMA block transfer" "Not performed,Performed"
|
|
bitfld.long 0x4 8.--12. " ICOUNT ,Initial count of DMA transfers" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32"
|
|
bitfld.long 0x4 6. " COUNTBIT17 ,17th bit of the COUNT field of DMAxCOUNT register" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0.--5. " COUNT ,Actual number of remaining DMA transfers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
line.long 0x8 "DMA2CTRL,MibSPI DMA Channel Control Register 1"
|
|
bitfld.long 0x8 31. " ONESHOT ,Auto-disable of DMA channel after ICOUNT+1 transfers" "0,1"
|
|
hexmask.long.byte 0x8 24.--30. 1. " BUFID ,Buffer utilized for DMA transfer"
|
|
bitfld.long 0x8 20.--23. " RXDMA_MAP ,Each MibSPI DMA channel can be linked to two physical DMA" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x8 16.--19. " TXDMA_MAP ,Each MibSPI DMA channel can be linked to two physical DMA" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x8 15. " RXDMAENA ,Receive data DMA channel enable" "Disabled,Enabled"
|
|
bitfld.long 0x8 14. " TXDMAENA ,Transmit data DMA channel enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x8 13. " NOBRK ,Non-interleaved DMA block transfer" "Not performed,Performed"
|
|
bitfld.long 0x8 8.--12. " ICOUNT ,Initial count of DMA transfers" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32"
|
|
bitfld.long 0x8 6. " COUNTBIT17 ,17th bit of the COUNT field of DMAxCOUNT register" "0,1"
|
|
newline
|
|
bitfld.long 0x8 0.--5. " COUNT ,Actual number of remaining DMA transfers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
line.long 0xC "DMA3CTRL,MibSPI DMA Channel Control Register 1"
|
|
bitfld.long 0xC 31. " ONESHOT ,Auto-disable of DMA channel after ICOUNT+1 transfers" "0,1"
|
|
hexmask.long.byte 0xC 24.--30. 1. " BUFID ,Buffer utilized for DMA transfer"
|
|
bitfld.long 0xC 20.--23. " RXDMA_MAP ,Each MibSPI DMA channel can be linked to two physical DMA" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0xC 16.--19. " TXDMA_MAP ,Each MibSPI DMA channel can be linked to two physical DMA" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0xC 15. " RXDMAENA ,Receive data DMA channel enable" "Disabled,Enabled"
|
|
bitfld.long 0xC 14. " TXDMAENA ,Transmit data DMA channel enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0xC 13. " NOBRK ,Non-interleaved DMA block transfer" "Not performed,Performed"
|
|
bitfld.long 0xC 8.--12. " ICOUNT ,Initial count of DMA transfers" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32"
|
|
bitfld.long 0xC 6. " COUNTBIT17 ,17th bit of the COUNT field of DMAxCOUNT register" "0,1"
|
|
newline
|
|
bitfld.long 0xC 0.--5. " COUNT ,Actual number of remaining DMA transfers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
line.long 0x10 "DMA4CTRL,MibSPI DMA Channel Control Register 1"
|
|
bitfld.long 0x10 31. " ONESHOT ,Auto-disable of DMA channel after ICOUNT+1 transfers" "0,1"
|
|
hexmask.long.byte 0x10 24.--30. 1. " BUFID ,Buffer utilized for DMA transfer"
|
|
bitfld.long 0x10 20.--23. " RXDMA_MAP ,Each MibSPI DMA channel can be linked to two physical DMA" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x10 16.--19. " TXDMA_MAP ,Each MibSPI DMA channel can be linked to two physical DMA" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x10 15. " RXDMAENA ,Receive data DMA channel enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 14. " TXDMAENA ,Transmit data DMA channel enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x10 13. " NOBRK ,Non-interleaved DMA block transfer" "Not performed,Performed"
|
|
bitfld.long 0x10 8.--12. " ICOUNT ,Initial count of DMA transfers" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32"
|
|
bitfld.long 0x10 6. " COUNTBIT17 ,17th bit of the COUNT field of DMAxCOUNT register" "0,1"
|
|
newline
|
|
bitfld.long 0x10 0.--5. " COUNT ,Actual number of remaining DMA transfers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
line.long 0x14 "DMA5CTRL,MibSPI DMA Channel Control Register 1"
|
|
bitfld.long 0x14 31. " ONESHOT ,Auto-disable of DMA channel after ICOUNT+1 transfers" "0,1"
|
|
hexmask.long.byte 0x14 24.--30. 1. " BUFID ,Buffer utilized for DMA transfer"
|
|
bitfld.long 0x14 20.--23. " RXDMA_MAP ,Each MibSPI DMA channel can be linked to two physical DMA" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x14 16.--19. " TXDMA_MAP ,Each MibSPI DMA channel can be linked to two physical DMA" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x14 15. " RXDMAENA ,Receive data DMA channel enable" "Disabled,Enabled"
|
|
bitfld.long 0x14 14. " TXDMAENA ,Transmit data DMA channel enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x14 13. " NOBRK ,Non-interleaved DMA block transfer" "Not performed,Performed"
|
|
bitfld.long 0x14 8.--12. " ICOUNT ,Initial count of DMA transfers" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32"
|
|
bitfld.long 0x14 6. " COUNTBIT17 ,17th bit of the COUNT field of DMAxCOUNT register" "0,1"
|
|
newline
|
|
bitfld.long 0x14 0.--5. " COUNT ,Actual number of remaining DMA transfers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
line.long 0x18 "DMA6CTRL,MibSPI DMA Channel Control Register 1"
|
|
bitfld.long 0x18 31. " ONESHOT ,Auto-disable of DMA channel after ICOUNT+1 transfers" "0,1"
|
|
hexmask.long.byte 0x18 24.--30. 1. " BUFID ,Buffer utilized for DMA transfer"
|
|
bitfld.long 0x18 20.--23. " RXDMA_MAP ,Each MibSPI DMA channel can be linked to two physical DMA" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x18 16.--19. " TXDMA_MAP ,Each MibSPI DMA channel can be linked to two physical DMA" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x18 15. " RXDMAENA ,Receive data DMA channel enable" "Disabled,Enabled"
|
|
bitfld.long 0x18 14. " TXDMAENA ,Transmit data DMA channel enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x18 13. " NOBRK ,Non-interleaved DMA block transfer" "Not performed,Performed"
|
|
bitfld.long 0x18 8.--12. " ICOUNT ,Initial count of DMA transfers" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32"
|
|
bitfld.long 0x18 6. " COUNTBIT17 ,17th bit of the COUNT field of DMAxCOUNT register" "0,1"
|
|
newline
|
|
bitfld.long 0x18 0.--5. " COUNT ,Actual number of remaining DMA transfers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
line.long 0x1C "DMA7CTRL,MibSPI DMA Channel Control Register 1"
|
|
bitfld.long 0x1C 31. " ONESHOT ,Auto-disable of DMA channel after ICOUNT+1 transfers" "0,1"
|
|
hexmask.long.byte 0x1C 24.--30. 1. " BUFID ,Buffer utilized for DMA transfer"
|
|
bitfld.long 0x1C 20.--23. " RXDMA_MAP ,Each MibSPI DMA channel can be linked to two physical DMA" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x1C 16.--19. " TXDMA_MAP ,Each MibSPI DMA channel can be linked to two physical DMA" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x1C 15. " RXDMAENA ,Receive data DMA channel enable" "Disabled,Enabled"
|
|
bitfld.long 0x1C 14. " TXDMAENA ,Transmit data DMA channel enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x1C 13. " NOBRK ,Non-interleaved DMA block transfer" "Not performed,Performed"
|
|
bitfld.long 0x1C 8.--12. " ICOUNT ,Initial count of DMA transfers" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32"
|
|
bitfld.long 0x1C 6. " COUNTBIT17 ,17th bit of the COUNT field of DMAxCOUNT register" "0,1"
|
|
newline
|
|
bitfld.long 0x1C 0.--5. " COUNT ,Actual number of remaining DMA transfers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
group.long 0xF8++0x1F
|
|
line.long 0x0 "DMA0 COUNT,MibSPI DMA0 COUNT Register"
|
|
hexmask.long.word 0x0 16.--31. 1. " ICOUNT0 ,Initial number of DMA transfers"
|
|
hexmask.long.word 0x0 0.--15. 1. " COUNT0 ,The actual number of remaining DMA transfers"
|
|
line.long 0x4 "DMA1 COUNT,MibSPI DMA1 COUNT Register"
|
|
hexmask.long.word 0x4 16.--31. 1. " ICOUNT1 ,Initial number of DMA transfers"
|
|
hexmask.long.word 0x4 0.--15. 1. " COUNT1 ,The actual number of remaining DMA transfers"
|
|
line.long 0x8 "DMA2 COUNT,MibSPI DMA2 COUNT Register"
|
|
hexmask.long.word 0x8 16.--31. 1. " ICOUNT2 ,Initial number of DMA transfers"
|
|
hexmask.long.word 0x8 0.--15. 1. " COUNT2 ,The actual number of remaining DMA transfers"
|
|
line.long 0xC "DMA3 COUNT,MibSPI DMA3 COUNT Register"
|
|
hexmask.long.word 0xC 16.--31. 1. " ICOUNT3 ,Initial number of DMA transfers"
|
|
hexmask.long.word 0xC 0.--15. 1. " COUNT3 ,The actual number of remaining DMA transfers"
|
|
line.long 0x10 "DMA4 COUNT,MibSPI DMA4 COUNT Register"
|
|
hexmask.long.word 0x10 16.--31. 1. " ICOUNT4 ,Initial number of DMA transfers"
|
|
hexmask.long.word 0x10 0.--15. 1. " COUNT4 ,The actual number of remaining DMA transfers"
|
|
line.long 0x14 "DMA5 COUNT,MibSPI DMA5 COUNT Register"
|
|
hexmask.long.word 0x14 16.--31. 1. " ICOUNT5 ,Initial number of DMA transfers"
|
|
hexmask.long.word 0x14 0.--15. 1. " COUNT5 ,The actual number of remaining DMA transfers"
|
|
line.long 0x18 "DMA6 COUNT,MibSPI DMA6 COUNT Register"
|
|
hexmask.long.word 0x18 16.--31. 1. " ICOUNT6 ,Initial number of DMA transfers"
|
|
hexmask.long.word 0x18 0.--15. 1. " COUNT6 ,The actual number of remaining DMA transfers"
|
|
line.long 0x1C "DMA7 COUNT,MibSPI DMA7 COUNT Register"
|
|
hexmask.long.word 0x1C 16.--31. 1. " ICOUNT7 ,Initial number of DMA transfers"
|
|
hexmask.long.word 0x1C 0.--15. 1. " COUNT7 ,The actual number of remaining DMA transfers"
|
|
group.long 0x118++0x03
|
|
line.long 0x00 "DMACNTLEN,MibSPI DMACNTLEN Register"
|
|
bitfld.long 0x00 0. " LARGECOUNT ,Counters select" "DMAxCTRL,DMAxCOUNT"
|
|
endif
|
|
group.long 0x120++0x03
|
|
line.long 0x00 "UERRCTRL,Uncorrectable Parity Error Control Register"
|
|
bitfld.long 0x00 8. " PTESTEN ,Parity memory test enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--3. " EDEN ,Error detection enable" "Enabled,Enabled,Enabled,Enabled,Enabled,Disabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled"
|
|
group.long 0x124++0x03
|
|
line.long 0x00 "UERRSTAT,Uncorrectable Parity Error Status Register"
|
|
eventfld.long 0x00 1. " EDFLG1 ,Uncorrectable parity error detection flag" "Not occurred,Occurred"
|
|
eventfld.long 0x00 0. " EDFLG0 ,Uncorrectable parity error detection flag" "Not occurred,Occurred"
|
|
hgroup.long 0x128++0x03
|
|
hide.long 0x00 "UERRADDR1,Uncorrectable Parity Error Address Register"
|
|
in
|
|
hgroup.long 0x12C++0x03
|
|
hide.long 0x00 "UERRADDR0,Uncorrectable Parity Error Address Register"
|
|
in
|
|
hgroup.long 0x130++0x03
|
|
hide.long 0x00 "RXOVRN_BUF_ADDR,Receive RAM Overrun Buffer Address Register"
|
|
in
|
|
sif cpuis("TMS570LS0714*")||cpuis("TMS570LS0914*")||cpuis("TMS570LS0232")
|
|
if (((per.l.be(ad:0xFFF7F800+0x134))&0x2)==0x2)
|
|
group.long 0x134++0x03
|
|
line.long 0x00 "IOLPBKTSTCR,SPI IO Loopback Test Control Register"
|
|
bitfld.long 0x00 24. " SCSFAILFLG ,Failure on SPISCS pin compare during analog loopback" "Not occurred,Occurred"
|
|
bitfld.long 0x00 20. " CTRL_BITERR ,Controls inducing of BITERR during I/O loopback test mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " CTRL_DESYNC ,Controls inducing of the desync error during I/O loopback test mode" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 18. " CTRL_PARERR ,Controls inducing of parity errors during I/O loopback test mode" "No error,Error"
|
|
bitfld.long 0x00 17. " CTRL_TIMEOUT ,Controls inducing of the timeout error during I/O loopbacK test mode" "No error,Error"
|
|
bitfld.long 0x00 16. " CTRL_DLENERR ,Controls inducing of the data length error during I/O loopback test mode" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 8.--11. " IOLPBKTSTENA ,Module I/O loopback test enable key" "Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Enabled,Disabled,Disabled,Disabled,Disabled,Disabled"
|
|
sif cpuis("TMS570LS0232")
|
|
bitfld.long 0x00 3.--5. " ERRSCSPIN ,Inject error on chip-select pin number" "/SPISCS[0],/SPISCS[1],/SPISCS[2],/SPISCS[3],?..."
|
|
else
|
|
bitfld.long 0x00 3.--5. " ERRSCSPIN ,Inject error on chip-select pin number" "/SPISCS[0],/SPISCS[1],/SPISCS[2],/SPISCS[3],/SPISCS[4],/SPISCS[5],/SPISCS[6],/SPISCS[7]"
|
|
endif
|
|
bitfld.long 0x00 2. " CTRLSCSPINERR ,Enable/disable the injection of an error on the SPISCS[3:0] pins" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 1. " LPBK_TYPE ,Module I/O loopback type (analog/digital)" "Digital,Analog"
|
|
bitfld.long 0x00 0. " RXP_ENA ,Enable analog loopback through the receive pin" "Transmit,Receive"
|
|
else
|
|
group.long 0x134++0x03
|
|
line.long 0x00 "IOLPBKTSTCR,SPI IO Loopback Test Control Register"
|
|
bitfld.long 0x00 24. " SCSFAILFLG ,Failure on SPISCS pin compare during analog loopback" "Not occurred,Occurred"
|
|
bitfld.long 0x00 20. " CTRL_BITERR ,Controls inducing of BITERR during I/O loopback test mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " CTRL_DESYNC ,Controls inducing of the desync error during I/O loopback test mode" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 18. " CTRL_PARERR ,Controls inducing of parity errors during I/O loopback test mode" "No error,Error"
|
|
bitfld.long 0x00 17. " CTRL_TIMEOUT ,Controls inducing of the timeout error during I/O loopbacK test mode" "No error,Error"
|
|
bitfld.long 0x00 16. " CTRL_DLENERR ,Controls inducing of the data length error during I/O loopback test mode" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 8.--11. " IOLPBKTSTENA ,Module I/O loopback test enable key" "Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Enabled,Disabled,Disabled,Disabled,Disabled,Disabled"
|
|
sif cpuis("TMS570LS0232")
|
|
bitfld.long 0x00 3.--5. " ERRSCSPIN ,Inject error on chip-select pin number" "/SPISCS[0],/SPISCS[1],/SPISCS[2],/SPISCS[3],?..."
|
|
else
|
|
bitfld.long 0x00 3.--5. " ERRSCSPIN ,Inject error on chip-select pin number" "/SPISCS[0],/SPISCS[1],/SPISCS[2],/SPISCS[3],/SPISCS[4],/SPISCS[5],/SPISCS[6],/SPISCS[7]"
|
|
endif
|
|
bitfld.long 0x00 2. " CTRLSCSPINERR ,Enable/disable the injection of an error on the SPISCS[3:0] pins" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 1. " LPBK_TYPE ,Module I/O loopback type (analog/digital)" "Digital,Analog"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0xFFF7F800+0x134))&0x2)==0x2)
|
|
group.long 0x134++0x03
|
|
line.long 0x00 "IOLPBKTSTCR,SPI IO Loopback Test Control Register"
|
|
bitfld.long 0x00 24. " SCSFAILFLG ,Failure on SPISCS pin compare during analog loopback" "Not occurred,Occurred"
|
|
bitfld.long 0x00 20. " CTRL_BITERR ,Controls inducing of BITERR during I/O loopback test mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " CTRL_DESYNC ,Controls inducing of the desync error during I/O loopback test mode" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 18. " CTRL_PARERR ,Controls inducing of parity errors during I/O loopback test mode" "No error,Error"
|
|
bitfld.long 0x00 17. " CTRL_TIMEOUT ,Controls inducing of the timeout error during I/O loopbacK test mode" "No error,Error"
|
|
bitfld.long 0x00 16. " CTRL_DLENERR ,Controls inducing of the data length error during I/O loopback test mode" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 8.--11. " IOLPBKTSTENA ,Module I/O loopback test enable key" "Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Enabled,Disabled,Disabled,Disabled,Disabled,Disabled"
|
|
bitfld.long 0x00 3.--5. " ERRSCSPIN ,Inject error on chip-select pin number" "/SPISCS[0],/SPISCS[1],/SPISCS[2],/SPISCS[3],/SPISCS[4],/SPISCS[5],/SPISCS[6],/SPISCS[7]"
|
|
bitfld.long 0x00 2. " CTRLSCSPINERR ,Enable/disable the injection of an error on the SPISCS[3:0] pins" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 1. " LPBK_TYPE ,Module I/O loopback type (analog/digital)" "Digital,Analog"
|
|
bitfld.long 0x00 0. " RXP_ENA ,Enable analog loopback through the receive pin" "Transmit,Receive"
|
|
else
|
|
group.long 0x134++0x03
|
|
line.long 0x00 "IOLPBKTSTCR,SPI IO Loopback Test Control Register"
|
|
bitfld.long 0x00 24. " SCSFAILFLG ,Failure on SPISCS pin compare during analog loopback" "Not occurred,Occurred"
|
|
bitfld.long 0x00 20. " CTRL_BITERR ,Controls inducing of BITERR during I/O loopback test mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " CTRL_DESYNC ,Controls inducing of the desync error during I/O loopback test mode" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 18. " CTRL_PARERR ,Controls inducing of parity errors during I/O loopback test mode" "No error,Error"
|
|
bitfld.long 0x00 17. " CTRL_TIMEOUT ,Controls inducing of the timeout error during I/O loopbacK test mode" "No error,Error"
|
|
bitfld.long 0x00 16. " CTRL_DLENERR ,Controls inducing of the data length error during I/O loopback test mode" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 8.--11. " IOLPBKTSTENA ,Module I/O loopback test enable key" "Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Enabled,Disabled,Disabled,Disabled,Disabled,Disabled"
|
|
bitfld.long 0x00 3.--5. " ERRSCSPIN ,Inject error on chip-select pin number" "/SPISCS[0],/SPISCS[1],/SPISCS[2],/SPISCS[3],/SPISCS[4],/SPISCS[5],/SPISCS[6],/SPISCS[7]"
|
|
bitfld.long 0x00 2. " CTRLSCSPINERR ,Enable/disable the injection of an error on the SPISCS[3:0] pins" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 1. " LPBK_TYPE ,Module I/O loopback type (analog/digital)" "Digital,Analog"
|
|
endif
|
|
endif
|
|
sif (cpu()=="TMS570LC4357"||cpu()==("TMS570LS0332")||cpu()==("TMS570LS0432")||cpuis("TMS570LS1114*")||cpuis("TMS570LS1115*")||cpuis("TMS570LS1224*")||cpuis("TMS570LS1225*")||cpuis("TMS570LS1227*")||cpuis("TMS570LS0232")||cpuis("TMS570LS0714*")||cpuis("TMS570LS0914*"))
|
|
width 21.
|
|
newline
|
|
group.long 0x138++0x07
|
|
line.long 0x00 "EXTENDED_PRESCALE_1, SPI Extended Prescale Register 1"
|
|
hexmask.long.word 0x00 16.--26. 1. " EPRESCALE_FMT1 , Extended Prescale value for SPIFMT1"
|
|
hexmask.long.word 0x00 0.--10. 1. " EPRESCALE_FMT0 , Extended Prescale value for SPIFMT0"
|
|
line.long 0x04 "EXTENDED_PRESCALE_2, SPI Extended Prescale Register 2"
|
|
hexmask.long.word 0x04 16.--26. 1. " EPRESCALE_FMT3 , Extended Prescale value for SPIFMT3"
|
|
hexmask.long.word 0x04 0.--10. 1. " EPRESCALE_FMT2 , Extended Prescale value for SPIFMT2"
|
|
endif
|
|
sif !cpuis("TMS570LS0232")&&!cpuis("TMS570LS0714*")&&!cpuis("TMS570LS0914*")
|
|
sif (cpu()=="TMS570LC4357"||cpu()==("TMS570LS0332")||cpu()==("TMS570LS0432")||cpuis("TMS570LS1114*")||cpuis("TMS570LS1115*")||cpuis("TMS570LS1224*")||cpuis("TMS570LS1225*")||cpuis("TMS570LS1227*"))
|
|
sif cpuis("TMS570LC4357")
|
|
group.long 0x140++0x03
|
|
line.long 0x00 "ECCDIAG_CTRL, ECC Diagnostic Control register"
|
|
bitfld.long 0x00 0.--3. " ECCDIAG_EN , ECC Diagnostic mode Enable Key bits" "Disabled,Disabled,Disabled,Disabled,Disabled,Enabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled"
|
|
endif
|
|
if ((per.l(ad:0xFFF7F800+0x140)&0x5)==0x5)
|
|
group.long 0x144++0x03
|
|
line.long 0x00 "ECCDIAG_STAT, ECC Diagnostic Status register"
|
|
eventfld.long 0x00 17. " DEFLG[1] , Double bit Error is detected for RXRAM" "No error,Error"
|
|
eventfld.long 0x00 16. " DEFLG[0] , Double bit Error is detected for TXRAM" "No error,Error"
|
|
eventfld.long 0x00 1. " SEFLG[1] , Single bit Error is detected for RXRAM" "No error,Error"
|
|
eventfld.long 0x00 0. " SEFLG[0] , Single bit Error is detected for TXRAM" "No error,Error"
|
|
else
|
|
hgroup.long 0x144++0x03
|
|
hide.long 0x00 "ECCDIAG_STAT, ECC Diagnostic Status register"
|
|
in
|
|
endif
|
|
hgroup.long 0x148++0x03
|
|
hide.long 0x00 "SBERRADDR1, Single Bit Error Address Register - RXRAM"
|
|
in
|
|
hgroup.long 0x14C++0x03
|
|
hide.long 0x00 "SBERRADDR0, Single Bit Error Address Register - TXRAM"
|
|
in
|
|
endif
|
|
endif
|
|
sif cpuis("TMS570LS0232")||cpuis("TMS570LS0714*")||cpuis("TMS570LS0914*")
|
|
endian.be
|
|
endif
|
|
width 0xB
|
|
tree.end
|
|
tree "MibSPI3 RAM"
|
|
base ad:0xFF0C0000
|
|
sif cpuis("TMS570LS0232")||cpuis("TMS570LS0714*")||cpuis("TMS570LS0914*")
|
|
endian.be
|
|
endif
|
|
width 11.
|
|
sif (cpu()==("TMS570LS0332")||cpu()==("TMS570LS0432")||cpuis("TMS570LS1114*")||cpuis("TMS570LS1115*")||cpuis("TMS570LS1224*")||cpuis("TMS570LS1225*")||cpuis("TMS570LS1227*"))
|
|
group.long 0x0++0x03
|
|
line.long 0x00 "TXRAM, Multi-buffer RAM Transmit Data Register 0"
|
|
bitfld.long 0x00 29.--31. " BUFMODE , Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip Single Transfer,Skip Overwrite,Skip ST-Overwrite,Continuous,Suspend Single Transfer,Suspend Overwrite,Suspend ST-Overwrite"
|
|
bitfld.long 0x00 28. " CSHOLD , Chip select hold mode" "Deactivated,Activated"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK , Lock two consecutive buffer words" "0,1"
|
|
bitfld.long 0x00 26. " WDEL , Enable the delay counter at the end of the current transaction" "Disable,Enable"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL , Data word format select" "Format 0,Format 1,Format 2,Format 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR , Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA , Transfer data"
|
|
group.long 0x4++0x03
|
|
line.long 0x00 "TXRAM, Multi-buffer RAM Transmit Data Register 1"
|
|
bitfld.long 0x00 29.--31. " BUFMODE , Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip Single Transfer,Skip Overwrite,Skip ST-Overwrite,Continuous,Suspend Single Transfer,Suspend Overwrite,Suspend ST-Overwrite"
|
|
bitfld.long 0x00 28. " CSHOLD , Chip select hold mode" "Deactivated,Activated"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK , Lock two consecutive buffer words" "0,1"
|
|
bitfld.long 0x00 26. " WDEL , Enable the delay counter at the end of the current transaction" "Disable,Enable"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL , Data word format select" "Format 0,Format 1,Format 2,Format 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR , Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA , Transfer data"
|
|
group.long 0x8++0x03
|
|
line.long 0x00 "TXRAM, Multi-buffer RAM Transmit Data Register 2"
|
|
bitfld.long 0x00 29.--31. " BUFMODE , Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip Single Transfer,Skip Overwrite,Skip ST-Overwrite,Continuous,Suspend Single Transfer,Suspend Overwrite,Suspend ST-Overwrite"
|
|
bitfld.long 0x00 28. " CSHOLD , Chip select hold mode" "Deactivated,Activated"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK , Lock two consecutive buffer words" "0,1"
|
|
bitfld.long 0x00 26. " WDEL , Enable the delay counter at the end of the current transaction" "Disable,Enable"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL , Data word format select" "Format 0,Format 1,Format 2,Format 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR , Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA , Transfer data"
|
|
group.long 0xC++0x03
|
|
line.long 0x00 "TXRAM, Multi-buffer RAM Transmit Data Register 3"
|
|
bitfld.long 0x00 29.--31. " BUFMODE , Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip Single Transfer,Skip Overwrite,Skip ST-Overwrite,Continuous,Suspend Single Transfer,Suspend Overwrite,Suspend ST-Overwrite"
|
|
bitfld.long 0x00 28. " CSHOLD , Chip select hold mode" "Deactivated,Activated"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK , Lock two consecutive buffer words" "0,1"
|
|
bitfld.long 0x00 26. " WDEL , Enable the delay counter at the end of the current transaction" "Disable,Enable"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL , Data word format select" "Format 0,Format 1,Format 2,Format 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR , Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA , Transfer data"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "TXRAM, Multi-buffer RAM Transmit Data Register 4"
|
|
bitfld.long 0x00 29.--31. " BUFMODE , Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip Single Transfer,Skip Overwrite,Skip ST-Overwrite,Continuous,Suspend Single Transfer,Suspend Overwrite,Suspend ST-Overwrite"
|
|
bitfld.long 0x00 28. " CSHOLD , Chip select hold mode" "Deactivated,Activated"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK , Lock two consecutive buffer words" "0,1"
|
|
bitfld.long 0x00 26. " WDEL , Enable the delay counter at the end of the current transaction" "Disable,Enable"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL , Data word format select" "Format 0,Format 1,Format 2,Format 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR , Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA , Transfer data"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "TXRAM, Multi-buffer RAM Transmit Data Register 5"
|
|
bitfld.long 0x00 29.--31. " BUFMODE , Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip Single Transfer,Skip Overwrite,Skip ST-Overwrite,Continuous,Suspend Single Transfer,Suspend Overwrite,Suspend ST-Overwrite"
|
|
bitfld.long 0x00 28. " CSHOLD , Chip select hold mode" "Deactivated,Activated"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK , Lock two consecutive buffer words" "0,1"
|
|
bitfld.long 0x00 26. " WDEL , Enable the delay counter at the end of the current transaction" "Disable,Enable"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL , Data word format select" "Format 0,Format 1,Format 2,Format 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR , Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA , Transfer data"
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "TXRAM, Multi-buffer RAM Transmit Data Register 6"
|
|
bitfld.long 0x00 29.--31. " BUFMODE , Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip Single Transfer,Skip Overwrite,Skip ST-Overwrite,Continuous,Suspend Single Transfer,Suspend Overwrite,Suspend ST-Overwrite"
|
|
bitfld.long 0x00 28. " CSHOLD , Chip select hold mode" "Deactivated,Activated"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK , Lock two consecutive buffer words" "0,1"
|
|
bitfld.long 0x00 26. " WDEL , Enable the delay counter at the end of the current transaction" "Disable,Enable"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL , Data word format select" "Format 0,Format 1,Format 2,Format 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR , Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA , Transfer data"
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "TXRAM, Multi-buffer RAM Transmit Data Register 7"
|
|
bitfld.long 0x00 29.--31. " BUFMODE , Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip Single Transfer,Skip Overwrite,Skip ST-Overwrite,Continuous,Suspend Single Transfer,Suspend Overwrite,Suspend ST-Overwrite"
|
|
bitfld.long 0x00 28. " CSHOLD , Chip select hold mode" "Deactivated,Activated"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK , Lock two consecutive buffer words" "0,1"
|
|
bitfld.long 0x00 26. " WDEL , Enable the delay counter at the end of the current transaction" "Disable,Enable"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL , Data word format select" "Format 0,Format 1,Format 2,Format 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR , Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA , Transfer data"
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "TXRAM, Multi-buffer RAM Transmit Data Register 8"
|
|
bitfld.long 0x00 29.--31. " BUFMODE , Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip Single Transfer,Skip Overwrite,Skip ST-Overwrite,Continuous,Suspend Single Transfer,Suspend Overwrite,Suspend ST-Overwrite"
|
|
bitfld.long 0x00 28. " CSHOLD , Chip select hold mode" "Deactivated,Activated"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK , Lock two consecutive buffer words" "0,1"
|
|
bitfld.long 0x00 26. " WDEL , Enable the delay counter at the end of the current transaction" "Disable,Enable"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL , Data word format select" "Format 0,Format 1,Format 2,Format 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR , Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA , Transfer data"
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "TXRAM, Multi-buffer RAM Transmit Data Register 9"
|
|
bitfld.long 0x00 29.--31. " BUFMODE , Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip Single Transfer,Skip Overwrite,Skip ST-Overwrite,Continuous,Suspend Single Transfer,Suspend Overwrite,Suspend ST-Overwrite"
|
|
bitfld.long 0x00 28. " CSHOLD , Chip select hold mode" "Deactivated,Activated"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK , Lock two consecutive buffer words" "0,1"
|
|
bitfld.long 0x00 26. " WDEL , Enable the delay counter at the end of the current transaction" "Disable,Enable"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL , Data word format select" "Format 0,Format 1,Format 2,Format 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR , Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA , Transfer data"
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "TXRAM, Multi-buffer RAM Transmit Data Register 10"
|
|
bitfld.long 0x00 29.--31. " BUFMODE , Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip Single Transfer,Skip Overwrite,Skip ST-Overwrite,Continuous,Suspend Single Transfer,Suspend Overwrite,Suspend ST-Overwrite"
|
|
bitfld.long 0x00 28. " CSHOLD , Chip select hold mode" "Deactivated,Activated"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK , Lock two consecutive buffer words" "0,1"
|
|
bitfld.long 0x00 26. " WDEL , Enable the delay counter at the end of the current transaction" "Disable,Enable"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL , Data word format select" "Format 0,Format 1,Format 2,Format 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR , Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA , Transfer data"
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "TXRAM, Multi-buffer RAM Transmit Data Register 11"
|
|
bitfld.long 0x00 29.--31. " BUFMODE , Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip Single Transfer,Skip Overwrite,Skip ST-Overwrite,Continuous,Suspend Single Transfer,Suspend Overwrite,Suspend ST-Overwrite"
|
|
bitfld.long 0x00 28. " CSHOLD , Chip select hold mode" "Deactivated,Activated"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK , Lock two consecutive buffer words" "0,1"
|
|
bitfld.long 0x00 26. " WDEL , Enable the delay counter at the end of the current transaction" "Disable,Enable"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL , Data word format select" "Format 0,Format 1,Format 2,Format 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR , Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA , Transfer data"
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "TXRAM, Multi-buffer RAM Transmit Data Register 12"
|
|
bitfld.long 0x00 29.--31. " BUFMODE , Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip Single Transfer,Skip Overwrite,Skip ST-Overwrite,Continuous,Suspend Single Transfer,Suspend Overwrite,Suspend ST-Overwrite"
|
|
bitfld.long 0x00 28. " CSHOLD , Chip select hold mode" "Deactivated,Activated"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK , Lock two consecutive buffer words" "0,1"
|
|
bitfld.long 0x00 26. " WDEL , Enable the delay counter at the end of the current transaction" "Disable,Enable"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL , Data word format select" "Format 0,Format 1,Format 2,Format 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR , Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA , Transfer data"
|
|
group.long 0x34++0x03
|
|
line.long 0x00 "TXRAM, Multi-buffer RAM Transmit Data Register 13"
|
|
bitfld.long 0x00 29.--31. " BUFMODE , Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip Single Transfer,Skip Overwrite,Skip ST-Overwrite,Continuous,Suspend Single Transfer,Suspend Overwrite,Suspend ST-Overwrite"
|
|
bitfld.long 0x00 28. " CSHOLD , Chip select hold mode" "Deactivated,Activated"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK , Lock two consecutive buffer words" "0,1"
|
|
bitfld.long 0x00 26. " WDEL , Enable the delay counter at the end of the current transaction" "Disable,Enable"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL , Data word format select" "Format 0,Format 1,Format 2,Format 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR , Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA , Transfer data"
|
|
group.long 0x38++0x03
|
|
line.long 0x00 "TXRAM, Multi-buffer RAM Transmit Data Register 14"
|
|
bitfld.long 0x00 29.--31. " BUFMODE , Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip Single Transfer,Skip Overwrite,Skip ST-Overwrite,Continuous,Suspend Single Transfer,Suspend Overwrite,Suspend ST-Overwrite"
|
|
bitfld.long 0x00 28. " CSHOLD , Chip select hold mode" "Deactivated,Activated"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK , Lock two consecutive buffer words" "0,1"
|
|
bitfld.long 0x00 26. " WDEL , Enable the delay counter at the end of the current transaction" "Disable,Enable"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL , Data word format select" "Format 0,Format 1,Format 2,Format 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR , Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA , Transfer data"
|
|
group.long 0x3C++0x03
|
|
line.long 0x00 "TXRAM, Multi-buffer RAM Transmit Data Register 15"
|
|
bitfld.long 0x00 29.--31. " BUFMODE , Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip Single Transfer,Skip Overwrite,Skip ST-Overwrite,Continuous,Suspend Single Transfer,Suspend Overwrite,Suspend ST-Overwrite"
|
|
bitfld.long 0x00 28. " CSHOLD , Chip select hold mode" "Deactivated,Activated"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK , Lock two consecutive buffer words" "0,1"
|
|
bitfld.long 0x00 26. " WDEL , Enable the delay counter at the end of the current transaction" "Disable,Enable"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL , Data word format select" "Format 0,Format 1,Format 2,Format 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR , Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA , Transfer data"
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "TXRAM, Multi-buffer RAM Transmit Data Register 16"
|
|
bitfld.long 0x00 29.--31. " BUFMODE , Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip Single Transfer,Skip Overwrite,Skip ST-Overwrite,Continuous,Suspend Single Transfer,Suspend Overwrite,Suspend ST-Overwrite"
|
|
bitfld.long 0x00 28. " CSHOLD , Chip select hold mode" "Deactivated,Activated"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK , Lock two consecutive buffer words" "0,1"
|
|
bitfld.long 0x00 26. " WDEL , Enable the delay counter at the end of the current transaction" "Disable,Enable"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL , Data word format select" "Format 0,Format 1,Format 2,Format 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR , Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA , Transfer data"
|
|
group.long 0x44++0x03
|
|
line.long 0x00 "TXRAM, Multi-buffer RAM Transmit Data Register 17"
|
|
bitfld.long 0x00 29.--31. " BUFMODE , Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip Single Transfer,Skip Overwrite,Skip ST-Overwrite,Continuous,Suspend Single Transfer,Suspend Overwrite,Suspend ST-Overwrite"
|
|
bitfld.long 0x00 28. " CSHOLD , Chip select hold mode" "Deactivated,Activated"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK , Lock two consecutive buffer words" "0,1"
|
|
bitfld.long 0x00 26. " WDEL , Enable the delay counter at the end of the current transaction" "Disable,Enable"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL , Data word format select" "Format 0,Format 1,Format 2,Format 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR , Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA , Transfer data"
|
|
group.long 0x48++0x03
|
|
line.long 0x00 "TXRAM, Multi-buffer RAM Transmit Data Register 18"
|
|
bitfld.long 0x00 29.--31. " BUFMODE , Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip Single Transfer,Skip Overwrite,Skip ST-Overwrite,Continuous,Suspend Single Transfer,Suspend Overwrite,Suspend ST-Overwrite"
|
|
bitfld.long 0x00 28. " CSHOLD , Chip select hold mode" "Deactivated,Activated"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK , Lock two consecutive buffer words" "0,1"
|
|
bitfld.long 0x00 26. " WDEL , Enable the delay counter at the end of the current transaction" "Disable,Enable"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL , Data word format select" "Format 0,Format 1,Format 2,Format 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR , Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA , Transfer data"
|
|
group.long 0x4C++0x03
|
|
line.long 0x00 "TXRAM, Multi-buffer RAM Transmit Data Register 19"
|
|
bitfld.long 0x00 29.--31. " BUFMODE , Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip Single Transfer,Skip Overwrite,Skip ST-Overwrite,Continuous,Suspend Single Transfer,Suspend Overwrite,Suspend ST-Overwrite"
|
|
bitfld.long 0x00 28. " CSHOLD , Chip select hold mode" "Deactivated,Activated"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK , Lock two consecutive buffer words" "0,1"
|
|
bitfld.long 0x00 26. " WDEL , Enable the delay counter at the end of the current transaction" "Disable,Enable"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL , Data word format select" "Format 0,Format 1,Format 2,Format 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR , Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA , Transfer data"
|
|
group.long 0x50++0x03
|
|
line.long 0x00 "TXRAM, Multi-buffer RAM Transmit Data Register 20"
|
|
bitfld.long 0x00 29.--31. " BUFMODE , Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip Single Transfer,Skip Overwrite,Skip ST-Overwrite,Continuous,Suspend Single Transfer,Suspend Overwrite,Suspend ST-Overwrite"
|
|
bitfld.long 0x00 28. " CSHOLD , Chip select hold mode" "Deactivated,Activated"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK , Lock two consecutive buffer words" "0,1"
|
|
bitfld.long 0x00 26. " WDEL , Enable the delay counter at the end of the current transaction" "Disable,Enable"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL , Data word format select" "Format 0,Format 1,Format 2,Format 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR , Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA , Transfer data"
|
|
group.long 0x54++0x03
|
|
line.long 0x00 "TXRAM, Multi-buffer RAM Transmit Data Register 21"
|
|
bitfld.long 0x00 29.--31. " BUFMODE , Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip Single Transfer,Skip Overwrite,Skip ST-Overwrite,Continuous,Suspend Single Transfer,Suspend Overwrite,Suspend ST-Overwrite"
|
|
bitfld.long 0x00 28. " CSHOLD , Chip select hold mode" "Deactivated,Activated"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK , Lock two consecutive buffer words" "0,1"
|
|
bitfld.long 0x00 26. " WDEL , Enable the delay counter at the end of the current transaction" "Disable,Enable"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL , Data word format select" "Format 0,Format 1,Format 2,Format 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR , Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA , Transfer data"
|
|
group.long 0x58++0x03
|
|
line.long 0x00 "TXRAM, Multi-buffer RAM Transmit Data Register 22"
|
|
bitfld.long 0x00 29.--31. " BUFMODE , Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip Single Transfer,Skip Overwrite,Skip ST-Overwrite,Continuous,Suspend Single Transfer,Suspend Overwrite,Suspend ST-Overwrite"
|
|
bitfld.long 0x00 28. " CSHOLD , Chip select hold mode" "Deactivated,Activated"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK , Lock two consecutive buffer words" "0,1"
|
|
bitfld.long 0x00 26. " WDEL , Enable the delay counter at the end of the current transaction" "Disable,Enable"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL , Data word format select" "Format 0,Format 1,Format 2,Format 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR , Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA , Transfer data"
|
|
group.long 0x5C++0x03
|
|
line.long 0x00 "TXRAM, Multi-buffer RAM Transmit Data Register 23"
|
|
bitfld.long 0x00 29.--31. " BUFMODE , Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip Single Transfer,Skip Overwrite,Skip ST-Overwrite,Continuous,Suspend Single Transfer,Suspend Overwrite,Suspend ST-Overwrite"
|
|
bitfld.long 0x00 28. " CSHOLD , Chip select hold mode" "Deactivated,Activated"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK , Lock two consecutive buffer words" "0,1"
|
|
bitfld.long 0x00 26. " WDEL , Enable the delay counter at the end of the current transaction" "Disable,Enable"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL , Data word format select" "Format 0,Format 1,Format 2,Format 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR , Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA , Transfer data"
|
|
group.long 0x60++0x03
|
|
line.long 0x00 "TXRAM, Multi-buffer RAM Transmit Data Register 24"
|
|
bitfld.long 0x00 29.--31. " BUFMODE , Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip Single Transfer,Skip Overwrite,Skip ST-Overwrite,Continuous,Suspend Single Transfer,Suspend Overwrite,Suspend ST-Overwrite"
|
|
bitfld.long 0x00 28. " CSHOLD , Chip select hold mode" "Deactivated,Activated"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK , Lock two consecutive buffer words" "0,1"
|
|
bitfld.long 0x00 26. " WDEL , Enable the delay counter at the end of the current transaction" "Disable,Enable"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL , Data word format select" "Format 0,Format 1,Format 2,Format 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR , Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA , Transfer data"
|
|
group.long 0x64++0x03
|
|
line.long 0x00 "TXRAM, Multi-buffer RAM Transmit Data Register 25"
|
|
bitfld.long 0x00 29.--31. " BUFMODE , Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip Single Transfer,Skip Overwrite,Skip ST-Overwrite,Continuous,Suspend Single Transfer,Suspend Overwrite,Suspend ST-Overwrite"
|
|
bitfld.long 0x00 28. " CSHOLD , Chip select hold mode" "Deactivated,Activated"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK , Lock two consecutive buffer words" "0,1"
|
|
bitfld.long 0x00 26. " WDEL , Enable the delay counter at the end of the current transaction" "Disable,Enable"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL , Data word format select" "Format 0,Format 1,Format 2,Format 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR , Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA , Transfer data"
|
|
group.long 0x68++0x03
|
|
line.long 0x00 "TXRAM, Multi-buffer RAM Transmit Data Register 26"
|
|
bitfld.long 0x00 29.--31. " BUFMODE , Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip Single Transfer,Skip Overwrite,Skip ST-Overwrite,Continuous,Suspend Single Transfer,Suspend Overwrite,Suspend ST-Overwrite"
|
|
bitfld.long 0x00 28. " CSHOLD , Chip select hold mode" "Deactivated,Activated"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK , Lock two consecutive buffer words" "0,1"
|
|
bitfld.long 0x00 26. " WDEL , Enable the delay counter at the end of the current transaction" "Disable,Enable"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL , Data word format select" "Format 0,Format 1,Format 2,Format 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR , Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA , Transfer data"
|
|
group.long 0x6C++0x03
|
|
line.long 0x00 "TXRAM, Multi-buffer RAM Transmit Data Register 27"
|
|
bitfld.long 0x00 29.--31. " BUFMODE , Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip Single Transfer,Skip Overwrite,Skip ST-Overwrite,Continuous,Suspend Single Transfer,Suspend Overwrite,Suspend ST-Overwrite"
|
|
bitfld.long 0x00 28. " CSHOLD , Chip select hold mode" "Deactivated,Activated"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK , Lock two consecutive buffer words" "0,1"
|
|
bitfld.long 0x00 26. " WDEL , Enable the delay counter at the end of the current transaction" "Disable,Enable"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL , Data word format select" "Format 0,Format 1,Format 2,Format 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR , Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA , Transfer data"
|
|
group.long 0x70++0x03
|
|
line.long 0x00 "TXRAM, Multi-buffer RAM Transmit Data Register 28"
|
|
bitfld.long 0x00 29.--31. " BUFMODE , Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip Single Transfer,Skip Overwrite,Skip ST-Overwrite,Continuous,Suspend Single Transfer,Suspend Overwrite,Suspend ST-Overwrite"
|
|
bitfld.long 0x00 28. " CSHOLD , Chip select hold mode" "Deactivated,Activated"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK , Lock two consecutive buffer words" "0,1"
|
|
bitfld.long 0x00 26. " WDEL , Enable the delay counter at the end of the current transaction" "Disable,Enable"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL , Data word format select" "Format 0,Format 1,Format 2,Format 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR , Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA , Transfer data"
|
|
group.long 0x74++0x03
|
|
line.long 0x00 "TXRAM, Multi-buffer RAM Transmit Data Register 29"
|
|
bitfld.long 0x00 29.--31. " BUFMODE , Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip Single Transfer,Skip Overwrite,Skip ST-Overwrite,Continuous,Suspend Single Transfer,Suspend Overwrite,Suspend ST-Overwrite"
|
|
bitfld.long 0x00 28. " CSHOLD , Chip select hold mode" "Deactivated,Activated"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK , Lock two consecutive buffer words" "0,1"
|
|
bitfld.long 0x00 26. " WDEL , Enable the delay counter at the end of the current transaction" "Disable,Enable"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL , Data word format select" "Format 0,Format 1,Format 2,Format 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR , Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA , Transfer data"
|
|
group.long 0x78++0x03
|
|
line.long 0x00 "TXRAM, Multi-buffer RAM Transmit Data Register 30"
|
|
bitfld.long 0x00 29.--31. " BUFMODE , Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip Single Transfer,Skip Overwrite,Skip ST-Overwrite,Continuous,Suspend Single Transfer,Suspend Overwrite,Suspend ST-Overwrite"
|
|
bitfld.long 0x00 28. " CSHOLD , Chip select hold mode" "Deactivated,Activated"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK , Lock two consecutive buffer words" "0,1"
|
|
bitfld.long 0x00 26. " WDEL , Enable the delay counter at the end of the current transaction" "Disable,Enable"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL , Data word format select" "Format 0,Format 1,Format 2,Format 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR , Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA , Transfer data"
|
|
group.long 0x7C++0x03
|
|
line.long 0x00 "TXRAM, Multi-buffer RAM Transmit Data Register 31"
|
|
bitfld.long 0x00 29.--31. " BUFMODE , Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip Single Transfer,Skip Overwrite,Skip ST-Overwrite,Continuous,Suspend Single Transfer,Suspend Overwrite,Suspend ST-Overwrite"
|
|
bitfld.long 0x00 28. " CSHOLD , Chip select hold mode" "Deactivated,Activated"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK , Lock two consecutive buffer words" "0,1"
|
|
bitfld.long 0x00 26. " WDEL , Enable the delay counter at the end of the current transaction" "Disable,Enable"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL , Data word format select" "Format 0,Format 1,Format 2,Format 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR , Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA , Transfer data"
|
|
group.long 0x80++0x03
|
|
line.long 0x00 "TXRAM, Multi-buffer RAM Transmit Data Register 32"
|
|
bitfld.long 0x00 29.--31. " BUFMODE , Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip Single Transfer,Skip Overwrite,Skip ST-Overwrite,Continuous,Suspend Single Transfer,Suspend Overwrite,Suspend ST-Overwrite"
|
|
bitfld.long 0x00 28. " CSHOLD , Chip select hold mode" "Deactivated,Activated"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK , Lock two consecutive buffer words" "0,1"
|
|
bitfld.long 0x00 26. " WDEL , Enable the delay counter at the end of the current transaction" "Disable,Enable"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL , Data word format select" "Format 0,Format 1,Format 2,Format 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR , Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA , Transfer data"
|
|
group.long 0x84++0x03
|
|
line.long 0x00 "TXRAM, Multi-buffer RAM Transmit Data Register 33"
|
|
bitfld.long 0x00 29.--31. " BUFMODE , Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip Single Transfer,Skip Overwrite,Skip ST-Overwrite,Continuous,Suspend Single Transfer,Suspend Overwrite,Suspend ST-Overwrite"
|
|
bitfld.long 0x00 28. " CSHOLD , Chip select hold mode" "Deactivated,Activated"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK , Lock two consecutive buffer words" "0,1"
|
|
bitfld.long 0x00 26. " WDEL , Enable the delay counter at the end of the current transaction" "Disable,Enable"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL , Data word format select" "Format 0,Format 1,Format 2,Format 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR , Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA , Transfer data"
|
|
group.long 0x88++0x03
|
|
line.long 0x00 "TXRAM, Multi-buffer RAM Transmit Data Register 34"
|
|
bitfld.long 0x00 29.--31. " BUFMODE , Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip Single Transfer,Skip Overwrite,Skip ST-Overwrite,Continuous,Suspend Single Transfer,Suspend Overwrite,Suspend ST-Overwrite"
|
|
bitfld.long 0x00 28. " CSHOLD , Chip select hold mode" "Deactivated,Activated"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK , Lock two consecutive buffer words" "0,1"
|
|
bitfld.long 0x00 26. " WDEL , Enable the delay counter at the end of the current transaction" "Disable,Enable"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL , Data word format select" "Format 0,Format 1,Format 2,Format 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR , Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA , Transfer data"
|
|
group.long 0x8C++0x03
|
|
line.long 0x00 "TXRAM, Multi-buffer RAM Transmit Data Register 35"
|
|
bitfld.long 0x00 29.--31. " BUFMODE , Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip Single Transfer,Skip Overwrite,Skip ST-Overwrite,Continuous,Suspend Single Transfer,Suspend Overwrite,Suspend ST-Overwrite"
|
|
bitfld.long 0x00 28. " CSHOLD , Chip select hold mode" "Deactivated,Activated"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK , Lock two consecutive buffer words" "0,1"
|
|
bitfld.long 0x00 26. " WDEL , Enable the delay counter at the end of the current transaction" "Disable,Enable"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL , Data word format select" "Format 0,Format 1,Format 2,Format 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR , Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA , Transfer data"
|
|
group.long 0x90++0x03
|
|
line.long 0x00 "TXRAM, Multi-buffer RAM Transmit Data Register 36"
|
|
bitfld.long 0x00 29.--31. " BUFMODE , Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip Single Transfer,Skip Overwrite,Skip ST-Overwrite,Continuous,Suspend Single Transfer,Suspend Overwrite,Suspend ST-Overwrite"
|
|
bitfld.long 0x00 28. " CSHOLD , Chip select hold mode" "Deactivated,Activated"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK , Lock two consecutive buffer words" "0,1"
|
|
bitfld.long 0x00 26. " WDEL , Enable the delay counter at the end of the current transaction" "Disable,Enable"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL , Data word format select" "Format 0,Format 1,Format 2,Format 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR , Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA , Transfer data"
|
|
group.long 0x94++0x03
|
|
line.long 0x00 "TXRAM, Multi-buffer RAM Transmit Data Register 37"
|
|
bitfld.long 0x00 29.--31. " BUFMODE , Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip Single Transfer,Skip Overwrite,Skip ST-Overwrite,Continuous,Suspend Single Transfer,Suspend Overwrite,Suspend ST-Overwrite"
|
|
bitfld.long 0x00 28. " CSHOLD , Chip select hold mode" "Deactivated,Activated"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK , Lock two consecutive buffer words" "0,1"
|
|
bitfld.long 0x00 26. " WDEL , Enable the delay counter at the end of the current transaction" "Disable,Enable"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL , Data word format select" "Format 0,Format 1,Format 2,Format 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR , Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA , Transfer data"
|
|
group.long 0x98++0x03
|
|
line.long 0x00 "TXRAM, Multi-buffer RAM Transmit Data Register 38"
|
|
bitfld.long 0x00 29.--31. " BUFMODE , Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip Single Transfer,Skip Overwrite,Skip ST-Overwrite,Continuous,Suspend Single Transfer,Suspend Overwrite,Suspend ST-Overwrite"
|
|
bitfld.long 0x00 28. " CSHOLD , Chip select hold mode" "Deactivated,Activated"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK , Lock two consecutive buffer words" "0,1"
|
|
bitfld.long 0x00 26. " WDEL , Enable the delay counter at the end of the current transaction" "Disable,Enable"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL , Data word format select" "Format 0,Format 1,Format 2,Format 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR , Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA , Transfer data"
|
|
group.long 0x9C++0x03
|
|
line.long 0x00 "TXRAM, Multi-buffer RAM Transmit Data Register 39"
|
|
bitfld.long 0x00 29.--31. " BUFMODE , Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip Single Transfer,Skip Overwrite,Skip ST-Overwrite,Continuous,Suspend Single Transfer,Suspend Overwrite,Suspend ST-Overwrite"
|
|
bitfld.long 0x00 28. " CSHOLD , Chip select hold mode" "Deactivated,Activated"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK , Lock two consecutive buffer words" "0,1"
|
|
bitfld.long 0x00 26. " WDEL , Enable the delay counter at the end of the current transaction" "Disable,Enable"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL , Data word format select" "Format 0,Format 1,Format 2,Format 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR , Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA , Transfer data"
|
|
group.long 0xA0++0x03
|
|
line.long 0x00 "TXRAM, Multi-buffer RAM Transmit Data Register 40"
|
|
bitfld.long 0x00 29.--31. " BUFMODE , Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip Single Transfer,Skip Overwrite,Skip ST-Overwrite,Continuous,Suspend Single Transfer,Suspend Overwrite,Suspend ST-Overwrite"
|
|
bitfld.long 0x00 28. " CSHOLD , Chip select hold mode" "Deactivated,Activated"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK , Lock two consecutive buffer words" "0,1"
|
|
bitfld.long 0x00 26. " WDEL , Enable the delay counter at the end of the current transaction" "Disable,Enable"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL , Data word format select" "Format 0,Format 1,Format 2,Format 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR , Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA , Transfer data"
|
|
group.long 0xA4++0x03
|
|
line.long 0x00 "TXRAM, Multi-buffer RAM Transmit Data Register 41"
|
|
bitfld.long 0x00 29.--31. " BUFMODE , Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip Single Transfer,Skip Overwrite,Skip ST-Overwrite,Continuous,Suspend Single Transfer,Suspend Overwrite,Suspend ST-Overwrite"
|
|
bitfld.long 0x00 28. " CSHOLD , Chip select hold mode" "Deactivated,Activated"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK , Lock two consecutive buffer words" "0,1"
|
|
bitfld.long 0x00 26. " WDEL , Enable the delay counter at the end of the current transaction" "Disable,Enable"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL , Data word format select" "Format 0,Format 1,Format 2,Format 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR , Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA , Transfer data"
|
|
group.long 0xA8++0x03
|
|
line.long 0x00 "TXRAM, Multi-buffer RAM Transmit Data Register 42"
|
|
bitfld.long 0x00 29.--31. " BUFMODE , Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip Single Transfer,Skip Overwrite,Skip ST-Overwrite,Continuous,Suspend Single Transfer,Suspend Overwrite,Suspend ST-Overwrite"
|
|
bitfld.long 0x00 28. " CSHOLD , Chip select hold mode" "Deactivated,Activated"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK , Lock two consecutive buffer words" "0,1"
|
|
bitfld.long 0x00 26. " WDEL , Enable the delay counter at the end of the current transaction" "Disable,Enable"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL , Data word format select" "Format 0,Format 1,Format 2,Format 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR , Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA , Transfer data"
|
|
group.long 0xAC++0x03
|
|
line.long 0x00 "TXRAM, Multi-buffer RAM Transmit Data Register 43"
|
|
bitfld.long 0x00 29.--31. " BUFMODE , Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip Single Transfer,Skip Overwrite,Skip ST-Overwrite,Continuous,Suspend Single Transfer,Suspend Overwrite,Suspend ST-Overwrite"
|
|
bitfld.long 0x00 28. " CSHOLD , Chip select hold mode" "Deactivated,Activated"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK , Lock two consecutive buffer words" "0,1"
|
|
bitfld.long 0x00 26. " WDEL , Enable the delay counter at the end of the current transaction" "Disable,Enable"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL , Data word format select" "Format 0,Format 1,Format 2,Format 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR , Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA , Transfer data"
|
|
group.long 0xB0++0x03
|
|
line.long 0x00 "TXRAM, Multi-buffer RAM Transmit Data Register 44"
|
|
bitfld.long 0x00 29.--31. " BUFMODE , Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip Single Transfer,Skip Overwrite,Skip ST-Overwrite,Continuous,Suspend Single Transfer,Suspend Overwrite,Suspend ST-Overwrite"
|
|
bitfld.long 0x00 28. " CSHOLD , Chip select hold mode" "Deactivated,Activated"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK , Lock two consecutive buffer words" "0,1"
|
|
bitfld.long 0x00 26. " WDEL , Enable the delay counter at the end of the current transaction" "Disable,Enable"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL , Data word format select" "Format 0,Format 1,Format 2,Format 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR , Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA , Transfer data"
|
|
group.long 0xB4++0x03
|
|
line.long 0x00 "TXRAM, Multi-buffer RAM Transmit Data Register 45"
|
|
bitfld.long 0x00 29.--31. " BUFMODE , Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip Single Transfer,Skip Overwrite,Skip ST-Overwrite,Continuous,Suspend Single Transfer,Suspend Overwrite,Suspend ST-Overwrite"
|
|
bitfld.long 0x00 28. " CSHOLD , Chip select hold mode" "Deactivated,Activated"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK , Lock two consecutive buffer words" "0,1"
|
|
bitfld.long 0x00 26. " WDEL , Enable the delay counter at the end of the current transaction" "Disable,Enable"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL , Data word format select" "Format 0,Format 1,Format 2,Format 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR , Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA , Transfer data"
|
|
group.long 0xB8++0x03
|
|
line.long 0x00 "TXRAM, Multi-buffer RAM Transmit Data Register 46"
|
|
bitfld.long 0x00 29.--31. " BUFMODE , Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip Single Transfer,Skip Overwrite,Skip ST-Overwrite,Continuous,Suspend Single Transfer,Suspend Overwrite,Suspend ST-Overwrite"
|
|
bitfld.long 0x00 28. " CSHOLD , Chip select hold mode" "Deactivated,Activated"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK , Lock two consecutive buffer words" "0,1"
|
|
bitfld.long 0x00 26. " WDEL , Enable the delay counter at the end of the current transaction" "Disable,Enable"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL , Data word format select" "Format 0,Format 1,Format 2,Format 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR , Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA , Transfer data"
|
|
group.long 0xBC++0x03
|
|
line.long 0x00 "TXRAM, Multi-buffer RAM Transmit Data Register 47"
|
|
bitfld.long 0x00 29.--31. " BUFMODE , Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip Single Transfer,Skip Overwrite,Skip ST-Overwrite,Continuous,Suspend Single Transfer,Suspend Overwrite,Suspend ST-Overwrite"
|
|
bitfld.long 0x00 28. " CSHOLD , Chip select hold mode" "Deactivated,Activated"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK , Lock two consecutive buffer words" "0,1"
|
|
bitfld.long 0x00 26. " WDEL , Enable the delay counter at the end of the current transaction" "Disable,Enable"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL , Data word format select" "Format 0,Format 1,Format 2,Format 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR , Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA , Transfer data"
|
|
group.long 0xC0++0x03
|
|
line.long 0x00 "TXRAM, Multi-buffer RAM Transmit Data Register 48"
|
|
bitfld.long 0x00 29.--31. " BUFMODE , Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip Single Transfer,Skip Overwrite,Skip ST-Overwrite,Continuous,Suspend Single Transfer,Suspend Overwrite,Suspend ST-Overwrite"
|
|
bitfld.long 0x00 28. " CSHOLD , Chip select hold mode" "Deactivated,Activated"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK , Lock two consecutive buffer words" "0,1"
|
|
bitfld.long 0x00 26. " WDEL , Enable the delay counter at the end of the current transaction" "Disable,Enable"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL , Data word format select" "Format 0,Format 1,Format 2,Format 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR , Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA , Transfer data"
|
|
group.long 0xC4++0x03
|
|
line.long 0x00 "TXRAM, Multi-buffer RAM Transmit Data Register 49"
|
|
bitfld.long 0x00 29.--31. " BUFMODE , Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip Single Transfer,Skip Overwrite,Skip ST-Overwrite,Continuous,Suspend Single Transfer,Suspend Overwrite,Suspend ST-Overwrite"
|
|
bitfld.long 0x00 28. " CSHOLD , Chip select hold mode" "Deactivated,Activated"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK , Lock two consecutive buffer words" "0,1"
|
|
bitfld.long 0x00 26. " WDEL , Enable the delay counter at the end of the current transaction" "Disable,Enable"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL , Data word format select" "Format 0,Format 1,Format 2,Format 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR , Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA , Transfer data"
|
|
group.long 0xC8++0x03
|
|
line.long 0x00 "TXRAM, Multi-buffer RAM Transmit Data Register 50"
|
|
bitfld.long 0x00 29.--31. " BUFMODE , Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip Single Transfer,Skip Overwrite,Skip ST-Overwrite,Continuous,Suspend Single Transfer,Suspend Overwrite,Suspend ST-Overwrite"
|
|
bitfld.long 0x00 28. " CSHOLD , Chip select hold mode" "Deactivated,Activated"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK , Lock two consecutive buffer words" "0,1"
|
|
bitfld.long 0x00 26. " WDEL , Enable the delay counter at the end of the current transaction" "Disable,Enable"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL , Data word format select" "Format 0,Format 1,Format 2,Format 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR , Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA , Transfer data"
|
|
group.long 0xCC++0x03
|
|
line.long 0x00 "TXRAM, Multi-buffer RAM Transmit Data Register 51"
|
|
bitfld.long 0x00 29.--31. " BUFMODE , Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip Single Transfer,Skip Overwrite,Skip ST-Overwrite,Continuous,Suspend Single Transfer,Suspend Overwrite,Suspend ST-Overwrite"
|
|
bitfld.long 0x00 28. " CSHOLD , Chip select hold mode" "Deactivated,Activated"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK , Lock two consecutive buffer words" "0,1"
|
|
bitfld.long 0x00 26. " WDEL , Enable the delay counter at the end of the current transaction" "Disable,Enable"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL , Data word format select" "Format 0,Format 1,Format 2,Format 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR , Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA , Transfer data"
|
|
group.long 0xD0++0x03
|
|
line.long 0x00 "TXRAM, Multi-buffer RAM Transmit Data Register 52"
|
|
bitfld.long 0x00 29.--31. " BUFMODE , Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip Single Transfer,Skip Overwrite,Skip ST-Overwrite,Continuous,Suspend Single Transfer,Suspend Overwrite,Suspend ST-Overwrite"
|
|
bitfld.long 0x00 28. " CSHOLD , Chip select hold mode" "Deactivated,Activated"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK , Lock two consecutive buffer words" "0,1"
|
|
bitfld.long 0x00 26. " WDEL , Enable the delay counter at the end of the current transaction" "Disable,Enable"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL , Data word format select" "Format 0,Format 1,Format 2,Format 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR , Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA , Transfer data"
|
|
group.long 0xD4++0x03
|
|
line.long 0x00 "TXRAM, Multi-buffer RAM Transmit Data Register 53"
|
|
bitfld.long 0x00 29.--31. " BUFMODE , Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip Single Transfer,Skip Overwrite,Skip ST-Overwrite,Continuous,Suspend Single Transfer,Suspend Overwrite,Suspend ST-Overwrite"
|
|
bitfld.long 0x00 28. " CSHOLD , Chip select hold mode" "Deactivated,Activated"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK , Lock two consecutive buffer words" "0,1"
|
|
bitfld.long 0x00 26. " WDEL , Enable the delay counter at the end of the current transaction" "Disable,Enable"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL , Data word format select" "Format 0,Format 1,Format 2,Format 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR , Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA , Transfer data"
|
|
group.long 0xD8++0x03
|
|
line.long 0x00 "TXRAM, Multi-buffer RAM Transmit Data Register 54"
|
|
bitfld.long 0x00 29.--31. " BUFMODE , Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip Single Transfer,Skip Overwrite,Skip ST-Overwrite,Continuous,Suspend Single Transfer,Suspend Overwrite,Suspend ST-Overwrite"
|
|
bitfld.long 0x00 28. " CSHOLD , Chip select hold mode" "Deactivated,Activated"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK , Lock two consecutive buffer words" "0,1"
|
|
bitfld.long 0x00 26. " WDEL , Enable the delay counter at the end of the current transaction" "Disable,Enable"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL , Data word format select" "Format 0,Format 1,Format 2,Format 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR , Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA , Transfer data"
|
|
group.long 0xDC++0x03
|
|
line.long 0x00 "TXRAM, Multi-buffer RAM Transmit Data Register 55"
|
|
bitfld.long 0x00 29.--31. " BUFMODE , Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip Single Transfer,Skip Overwrite,Skip ST-Overwrite,Continuous,Suspend Single Transfer,Suspend Overwrite,Suspend ST-Overwrite"
|
|
bitfld.long 0x00 28. " CSHOLD , Chip select hold mode" "Deactivated,Activated"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK , Lock two consecutive buffer words" "0,1"
|
|
bitfld.long 0x00 26. " WDEL , Enable the delay counter at the end of the current transaction" "Disable,Enable"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL , Data word format select" "Format 0,Format 1,Format 2,Format 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR , Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA , Transfer data"
|
|
group.long 0xE0++0x03
|
|
line.long 0x00 "TXRAM, Multi-buffer RAM Transmit Data Register 56"
|
|
bitfld.long 0x00 29.--31. " BUFMODE , Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip Single Transfer,Skip Overwrite,Skip ST-Overwrite,Continuous,Suspend Single Transfer,Suspend Overwrite,Suspend ST-Overwrite"
|
|
bitfld.long 0x00 28. " CSHOLD , Chip select hold mode" "Deactivated,Activated"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK , Lock two consecutive buffer words" "0,1"
|
|
bitfld.long 0x00 26. " WDEL , Enable the delay counter at the end of the current transaction" "Disable,Enable"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL , Data word format select" "Format 0,Format 1,Format 2,Format 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR , Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA , Transfer data"
|
|
group.long 0xE4++0x03
|
|
line.long 0x00 "TXRAM, Multi-buffer RAM Transmit Data Register 57"
|
|
bitfld.long 0x00 29.--31. " BUFMODE , Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip Single Transfer,Skip Overwrite,Skip ST-Overwrite,Continuous,Suspend Single Transfer,Suspend Overwrite,Suspend ST-Overwrite"
|
|
bitfld.long 0x00 28. " CSHOLD , Chip select hold mode" "Deactivated,Activated"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK , Lock two consecutive buffer words" "0,1"
|
|
bitfld.long 0x00 26. " WDEL , Enable the delay counter at the end of the current transaction" "Disable,Enable"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL , Data word format select" "Format 0,Format 1,Format 2,Format 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR , Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA , Transfer data"
|
|
group.long 0xE8++0x03
|
|
line.long 0x00 "TXRAM, Multi-buffer RAM Transmit Data Register 58"
|
|
bitfld.long 0x00 29.--31. " BUFMODE , Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip Single Transfer,Skip Overwrite,Skip ST-Overwrite,Continuous,Suspend Single Transfer,Suspend Overwrite,Suspend ST-Overwrite"
|
|
bitfld.long 0x00 28. " CSHOLD , Chip select hold mode" "Deactivated,Activated"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK , Lock two consecutive buffer words" "0,1"
|
|
bitfld.long 0x00 26. " WDEL , Enable the delay counter at the end of the current transaction" "Disable,Enable"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL , Data word format select" "Format 0,Format 1,Format 2,Format 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR , Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA , Transfer data"
|
|
group.long 0xEC++0x03
|
|
line.long 0x00 "TXRAM, Multi-buffer RAM Transmit Data Register 59"
|
|
bitfld.long 0x00 29.--31. " BUFMODE , Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip Single Transfer,Skip Overwrite,Skip ST-Overwrite,Continuous,Suspend Single Transfer,Suspend Overwrite,Suspend ST-Overwrite"
|
|
bitfld.long 0x00 28. " CSHOLD , Chip select hold mode" "Deactivated,Activated"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK , Lock two consecutive buffer words" "0,1"
|
|
bitfld.long 0x00 26. " WDEL , Enable the delay counter at the end of the current transaction" "Disable,Enable"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL , Data word format select" "Format 0,Format 1,Format 2,Format 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR , Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA , Transfer data"
|
|
group.long 0xF0++0x03
|
|
line.long 0x00 "TXRAM, Multi-buffer RAM Transmit Data Register 60"
|
|
bitfld.long 0x00 29.--31. " BUFMODE , Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip Single Transfer,Skip Overwrite,Skip ST-Overwrite,Continuous,Suspend Single Transfer,Suspend Overwrite,Suspend ST-Overwrite"
|
|
bitfld.long 0x00 28. " CSHOLD , Chip select hold mode" "Deactivated,Activated"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK , Lock two consecutive buffer words" "0,1"
|
|
bitfld.long 0x00 26. " WDEL , Enable the delay counter at the end of the current transaction" "Disable,Enable"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL , Data word format select" "Format 0,Format 1,Format 2,Format 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR , Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA , Transfer data"
|
|
group.long 0xF4++0x03
|
|
line.long 0x00 "TXRAM, Multi-buffer RAM Transmit Data Register 61"
|
|
bitfld.long 0x00 29.--31. " BUFMODE , Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip Single Transfer,Skip Overwrite,Skip ST-Overwrite,Continuous,Suspend Single Transfer,Suspend Overwrite,Suspend ST-Overwrite"
|
|
bitfld.long 0x00 28. " CSHOLD , Chip select hold mode" "Deactivated,Activated"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK , Lock two consecutive buffer words" "0,1"
|
|
bitfld.long 0x00 26. " WDEL , Enable the delay counter at the end of the current transaction" "Disable,Enable"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL , Data word format select" "Format 0,Format 1,Format 2,Format 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR , Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA , Transfer data"
|
|
group.long 0xF8++0x03
|
|
line.long 0x00 "TXRAM, Multi-buffer RAM Transmit Data Register 62"
|
|
bitfld.long 0x00 29.--31. " BUFMODE , Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip Single Transfer,Skip Overwrite,Skip ST-Overwrite,Continuous,Suspend Single Transfer,Suspend Overwrite,Suspend ST-Overwrite"
|
|
bitfld.long 0x00 28. " CSHOLD , Chip select hold mode" "Deactivated,Activated"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK , Lock two consecutive buffer words" "0,1"
|
|
bitfld.long 0x00 26. " WDEL , Enable the delay counter at the end of the current transaction" "Disable,Enable"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL , Data word format select" "Format 0,Format 1,Format 2,Format 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR , Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA , Transfer data"
|
|
group.long 0xFC++0x03
|
|
line.long 0x00 "TXRAM, Multi-buffer RAM Transmit Data Register 63"
|
|
bitfld.long 0x00 29.--31. " BUFMODE , Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip Single Transfer,Skip Overwrite,Skip ST-Overwrite,Continuous,Suspend Single Transfer,Suspend Overwrite,Suspend ST-Overwrite"
|
|
bitfld.long 0x00 28. " CSHOLD , Chip select hold mode" "Deactivated,Activated"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK , Lock two consecutive buffer words" "0,1"
|
|
bitfld.long 0x00 26. " WDEL , Enable the delay counter at the end of the current transaction" "Disable,Enable"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL , Data word format select" "Format 0,Format 1,Format 2,Format 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR , Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA , Transfer data"
|
|
group.long 0x100++0x03
|
|
line.long 0x00 "TXRAM, Multi-buffer RAM Transmit Data Register 64"
|
|
bitfld.long 0x00 29.--31. " BUFMODE , Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip Single Transfer,Skip Overwrite,Skip ST-Overwrite,Continuous,Suspend Single Transfer,Suspend Overwrite,Suspend ST-Overwrite"
|
|
bitfld.long 0x00 28. " CSHOLD , Chip select hold mode" "Deactivated,Activated"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK , Lock two consecutive buffer words" "0,1"
|
|
bitfld.long 0x00 26. " WDEL , Enable the delay counter at the end of the current transaction" "Disable,Enable"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL , Data word format select" "Format 0,Format 1,Format 2,Format 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR , Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA , Transfer data"
|
|
group.long 0x104++0x03
|
|
line.long 0x00 "TXRAM, Multi-buffer RAM Transmit Data Register 65"
|
|
bitfld.long 0x00 29.--31. " BUFMODE , Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip Single Transfer,Skip Overwrite,Skip ST-Overwrite,Continuous,Suspend Single Transfer,Suspend Overwrite,Suspend ST-Overwrite"
|
|
bitfld.long 0x00 28. " CSHOLD , Chip select hold mode" "Deactivated,Activated"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK , Lock two consecutive buffer words" "0,1"
|
|
bitfld.long 0x00 26. " WDEL , Enable the delay counter at the end of the current transaction" "Disable,Enable"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL , Data word format select" "Format 0,Format 1,Format 2,Format 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR , Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA , Transfer data"
|
|
group.long 0x108++0x03
|
|
line.long 0x00 "TXRAM, Multi-buffer RAM Transmit Data Register 66"
|
|
bitfld.long 0x00 29.--31. " BUFMODE , Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip Single Transfer,Skip Overwrite,Skip ST-Overwrite,Continuous,Suspend Single Transfer,Suspend Overwrite,Suspend ST-Overwrite"
|
|
bitfld.long 0x00 28. " CSHOLD , Chip select hold mode" "Deactivated,Activated"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK , Lock two consecutive buffer words" "0,1"
|
|
bitfld.long 0x00 26. " WDEL , Enable the delay counter at the end of the current transaction" "Disable,Enable"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL , Data word format select" "Format 0,Format 1,Format 2,Format 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR , Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA , Transfer data"
|
|
group.long 0x10C++0x03
|
|
line.long 0x00 "TXRAM, Multi-buffer RAM Transmit Data Register 67"
|
|
bitfld.long 0x00 29.--31. " BUFMODE , Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip Single Transfer,Skip Overwrite,Skip ST-Overwrite,Continuous,Suspend Single Transfer,Suspend Overwrite,Suspend ST-Overwrite"
|
|
bitfld.long 0x00 28. " CSHOLD , Chip select hold mode" "Deactivated,Activated"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK , Lock two consecutive buffer words" "0,1"
|
|
bitfld.long 0x00 26. " WDEL , Enable the delay counter at the end of the current transaction" "Disable,Enable"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL , Data word format select" "Format 0,Format 1,Format 2,Format 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR , Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA , Transfer data"
|
|
group.long 0x110++0x03
|
|
line.long 0x00 "TXRAM, Multi-buffer RAM Transmit Data Register 68"
|
|
bitfld.long 0x00 29.--31. " BUFMODE , Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip Single Transfer,Skip Overwrite,Skip ST-Overwrite,Continuous,Suspend Single Transfer,Suspend Overwrite,Suspend ST-Overwrite"
|
|
bitfld.long 0x00 28. " CSHOLD , Chip select hold mode" "Deactivated,Activated"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK , Lock two consecutive buffer words" "0,1"
|
|
bitfld.long 0x00 26. " WDEL , Enable the delay counter at the end of the current transaction" "Disable,Enable"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL , Data word format select" "Format 0,Format 1,Format 2,Format 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR , Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA , Transfer data"
|
|
group.long 0x114++0x03
|
|
line.long 0x00 "TXRAM, Multi-buffer RAM Transmit Data Register 69"
|
|
bitfld.long 0x00 29.--31. " BUFMODE , Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip Single Transfer,Skip Overwrite,Skip ST-Overwrite,Continuous,Suspend Single Transfer,Suspend Overwrite,Suspend ST-Overwrite"
|
|
bitfld.long 0x00 28. " CSHOLD , Chip select hold mode" "Deactivated,Activated"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK , Lock two consecutive buffer words" "0,1"
|
|
bitfld.long 0x00 26. " WDEL , Enable the delay counter at the end of the current transaction" "Disable,Enable"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL , Data word format select" "Format 0,Format 1,Format 2,Format 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR , Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA , Transfer data"
|
|
group.long 0x118++0x03
|
|
line.long 0x00 "TXRAM, Multi-buffer RAM Transmit Data Register 70"
|
|
bitfld.long 0x00 29.--31. " BUFMODE , Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip Single Transfer,Skip Overwrite,Skip ST-Overwrite,Continuous,Suspend Single Transfer,Suspend Overwrite,Suspend ST-Overwrite"
|
|
bitfld.long 0x00 28. " CSHOLD , Chip select hold mode" "Deactivated,Activated"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK , Lock two consecutive buffer words" "0,1"
|
|
bitfld.long 0x00 26. " WDEL , Enable the delay counter at the end of the current transaction" "Disable,Enable"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL , Data word format select" "Format 0,Format 1,Format 2,Format 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR , Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA , Transfer data"
|
|
group.long 0x11C++0x03
|
|
line.long 0x00 "TXRAM, Multi-buffer RAM Transmit Data Register 71"
|
|
bitfld.long 0x00 29.--31. " BUFMODE , Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip Single Transfer,Skip Overwrite,Skip ST-Overwrite,Continuous,Suspend Single Transfer,Suspend Overwrite,Suspend ST-Overwrite"
|
|
bitfld.long 0x00 28. " CSHOLD , Chip select hold mode" "Deactivated,Activated"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK , Lock two consecutive buffer words" "0,1"
|
|
bitfld.long 0x00 26. " WDEL , Enable the delay counter at the end of the current transaction" "Disable,Enable"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL , Data word format select" "Format 0,Format 1,Format 2,Format 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR , Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA , Transfer data"
|
|
group.long 0x120++0x03
|
|
line.long 0x00 "TXRAM, Multi-buffer RAM Transmit Data Register 72"
|
|
bitfld.long 0x00 29.--31. " BUFMODE , Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip Single Transfer,Skip Overwrite,Skip ST-Overwrite,Continuous,Suspend Single Transfer,Suspend Overwrite,Suspend ST-Overwrite"
|
|
bitfld.long 0x00 28. " CSHOLD , Chip select hold mode" "Deactivated,Activated"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK , Lock two consecutive buffer words" "0,1"
|
|
bitfld.long 0x00 26. " WDEL , Enable the delay counter at the end of the current transaction" "Disable,Enable"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL , Data word format select" "Format 0,Format 1,Format 2,Format 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR , Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA , Transfer data"
|
|
group.long 0x124++0x03
|
|
line.long 0x00 "TXRAM, Multi-buffer RAM Transmit Data Register 73"
|
|
bitfld.long 0x00 29.--31. " BUFMODE , Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip Single Transfer,Skip Overwrite,Skip ST-Overwrite,Continuous,Suspend Single Transfer,Suspend Overwrite,Suspend ST-Overwrite"
|
|
bitfld.long 0x00 28. " CSHOLD , Chip select hold mode" "Deactivated,Activated"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK , Lock two consecutive buffer words" "0,1"
|
|
bitfld.long 0x00 26. " WDEL , Enable the delay counter at the end of the current transaction" "Disable,Enable"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL , Data word format select" "Format 0,Format 1,Format 2,Format 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR , Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA , Transfer data"
|
|
group.long 0x128++0x03
|
|
line.long 0x00 "TXRAM, Multi-buffer RAM Transmit Data Register 74"
|
|
bitfld.long 0x00 29.--31. " BUFMODE , Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip Single Transfer,Skip Overwrite,Skip ST-Overwrite,Continuous,Suspend Single Transfer,Suspend Overwrite,Suspend ST-Overwrite"
|
|
bitfld.long 0x00 28. " CSHOLD , Chip select hold mode" "Deactivated,Activated"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK , Lock two consecutive buffer words" "0,1"
|
|
bitfld.long 0x00 26. " WDEL , Enable the delay counter at the end of the current transaction" "Disable,Enable"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL , Data word format select" "Format 0,Format 1,Format 2,Format 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR , Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA , Transfer data"
|
|
group.long 0x12C++0x03
|
|
line.long 0x00 "TXRAM, Multi-buffer RAM Transmit Data Register 75"
|
|
bitfld.long 0x00 29.--31. " BUFMODE , Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip Single Transfer,Skip Overwrite,Skip ST-Overwrite,Continuous,Suspend Single Transfer,Suspend Overwrite,Suspend ST-Overwrite"
|
|
bitfld.long 0x00 28. " CSHOLD , Chip select hold mode" "Deactivated,Activated"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK , Lock two consecutive buffer words" "0,1"
|
|
bitfld.long 0x00 26. " WDEL , Enable the delay counter at the end of the current transaction" "Disable,Enable"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL , Data word format select" "Format 0,Format 1,Format 2,Format 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR , Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA , Transfer data"
|
|
group.long 0x130++0x03
|
|
line.long 0x00 "TXRAM, Multi-buffer RAM Transmit Data Register 76"
|
|
bitfld.long 0x00 29.--31. " BUFMODE , Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip Single Transfer,Skip Overwrite,Skip ST-Overwrite,Continuous,Suspend Single Transfer,Suspend Overwrite,Suspend ST-Overwrite"
|
|
bitfld.long 0x00 28. " CSHOLD , Chip select hold mode" "Deactivated,Activated"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK , Lock two consecutive buffer words" "0,1"
|
|
bitfld.long 0x00 26. " WDEL , Enable the delay counter at the end of the current transaction" "Disable,Enable"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL , Data word format select" "Format 0,Format 1,Format 2,Format 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR , Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA , Transfer data"
|
|
group.long 0x134++0x03
|
|
line.long 0x00 "TXRAM, Multi-buffer RAM Transmit Data Register 77"
|
|
bitfld.long 0x00 29.--31. " BUFMODE , Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip Single Transfer,Skip Overwrite,Skip ST-Overwrite,Continuous,Suspend Single Transfer,Suspend Overwrite,Suspend ST-Overwrite"
|
|
bitfld.long 0x00 28. " CSHOLD , Chip select hold mode" "Deactivated,Activated"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK , Lock two consecutive buffer words" "0,1"
|
|
bitfld.long 0x00 26. " WDEL , Enable the delay counter at the end of the current transaction" "Disable,Enable"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL , Data word format select" "Format 0,Format 1,Format 2,Format 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR , Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA , Transfer data"
|
|
group.long 0x138++0x03
|
|
line.long 0x00 "TXRAM, Multi-buffer RAM Transmit Data Register 78"
|
|
bitfld.long 0x00 29.--31. " BUFMODE , Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip Single Transfer,Skip Overwrite,Skip ST-Overwrite,Continuous,Suspend Single Transfer,Suspend Overwrite,Suspend ST-Overwrite"
|
|
bitfld.long 0x00 28. " CSHOLD , Chip select hold mode" "Deactivated,Activated"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK , Lock two consecutive buffer words" "0,1"
|
|
bitfld.long 0x00 26. " WDEL , Enable the delay counter at the end of the current transaction" "Disable,Enable"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL , Data word format select" "Format 0,Format 1,Format 2,Format 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR , Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA , Transfer data"
|
|
group.long 0x13C++0x03
|
|
line.long 0x00 "TXRAM, Multi-buffer RAM Transmit Data Register 79"
|
|
bitfld.long 0x00 29.--31. " BUFMODE , Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip Single Transfer,Skip Overwrite,Skip ST-Overwrite,Continuous,Suspend Single Transfer,Suspend Overwrite,Suspend ST-Overwrite"
|
|
bitfld.long 0x00 28. " CSHOLD , Chip select hold mode" "Deactivated,Activated"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK , Lock two consecutive buffer words" "0,1"
|
|
bitfld.long 0x00 26. " WDEL , Enable the delay counter at the end of the current transaction" "Disable,Enable"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL , Data word format select" "Format 0,Format 1,Format 2,Format 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR , Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA , Transfer data"
|
|
rgroup.long (0x0+0x200)++0x03
|
|
line.long 0x00 "RXRAM, Multi-buffer RAM Receive Buffer Register 0"
|
|
bitfld.long 0x00 31. " RXEMPTY , Receive data buffer empty" "Not empty,Empty"
|
|
bitfld.long 0x00 30. " RXOVR , Receive data buffer overrun" "No overrun,Overrun"
|
|
newline
|
|
bitfld.long 0x00 29. " TXFULL , Transmit data buffer full" "Not full,Full"
|
|
bitfld.long 0x00 28. " BITERR , Bit error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 27. " DESYNC , Desynchronization of slave device" "No,Yes"
|
|
bitfld.long 0x00 26. " PARITYERR , Parity error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 25. " TIMEOUT , Time-out because of non-activation of ENA pin" "No timeout,Timeout"
|
|
bitfld.long 0x00 24. " DLENERR , Data length error flag" "No,Yes"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " LCSNR , Last chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " RXDATA , SPI receive data"
|
|
rgroup.long (0x4+0x200)++0x03
|
|
line.long 0x00 "RXRAM, Multi-buffer RAM Receive Buffer Register 1"
|
|
bitfld.long 0x00 31. " RXEMPTY , Receive data buffer empty" "Not empty,Empty"
|
|
bitfld.long 0x00 30. " RXOVR , Receive data buffer overrun" "No overrun,Overrun"
|
|
newline
|
|
bitfld.long 0x00 29. " TXFULL , Transmit data buffer full" "Not full,Full"
|
|
bitfld.long 0x00 28. " BITERR , Bit error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 27. " DESYNC , Desynchronization of slave device" "No,Yes"
|
|
bitfld.long 0x00 26. " PARITYERR , Parity error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 25. " TIMEOUT , Time-out because of non-activation of ENA pin" "No timeout,Timeout"
|
|
bitfld.long 0x00 24. " DLENERR , Data length error flag" "No,Yes"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " LCSNR , Last chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " RXDATA , SPI receive data"
|
|
rgroup.long (0x8+0x200)++0x03
|
|
line.long 0x00 "RXRAM, Multi-buffer RAM Receive Buffer Register 2"
|
|
bitfld.long 0x00 31. " RXEMPTY , Receive data buffer empty" "Not empty,Empty"
|
|
bitfld.long 0x00 30. " RXOVR , Receive data buffer overrun" "No overrun,Overrun"
|
|
newline
|
|
bitfld.long 0x00 29. " TXFULL , Transmit data buffer full" "Not full,Full"
|
|
bitfld.long 0x00 28. " BITERR , Bit error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 27. " DESYNC , Desynchronization of slave device" "No,Yes"
|
|
bitfld.long 0x00 26. " PARITYERR , Parity error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 25. " TIMEOUT , Time-out because of non-activation of ENA pin" "No timeout,Timeout"
|
|
bitfld.long 0x00 24. " DLENERR , Data length error flag" "No,Yes"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " LCSNR , Last chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " RXDATA , SPI receive data"
|
|
rgroup.long (0xC+0x200)++0x03
|
|
line.long 0x00 "RXRAM, Multi-buffer RAM Receive Buffer Register 3"
|
|
bitfld.long 0x00 31. " RXEMPTY , Receive data buffer empty" "Not empty,Empty"
|
|
bitfld.long 0x00 30. " RXOVR , Receive data buffer overrun" "No overrun,Overrun"
|
|
newline
|
|
bitfld.long 0x00 29. " TXFULL , Transmit data buffer full" "Not full,Full"
|
|
bitfld.long 0x00 28. " BITERR , Bit error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 27. " DESYNC , Desynchronization of slave device" "No,Yes"
|
|
bitfld.long 0x00 26. " PARITYERR , Parity error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 25. " TIMEOUT , Time-out because of non-activation of ENA pin" "No timeout,Timeout"
|
|
bitfld.long 0x00 24. " DLENERR , Data length error flag" "No,Yes"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " LCSNR , Last chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " RXDATA , SPI receive data"
|
|
rgroup.long (0x10+0x200)++0x03
|
|
line.long 0x00 "RXRAM, Multi-buffer RAM Receive Buffer Register 4"
|
|
bitfld.long 0x00 31. " RXEMPTY , Receive data buffer empty" "Not empty,Empty"
|
|
bitfld.long 0x00 30. " RXOVR , Receive data buffer overrun" "No overrun,Overrun"
|
|
newline
|
|
bitfld.long 0x00 29. " TXFULL , Transmit data buffer full" "Not full,Full"
|
|
bitfld.long 0x00 28. " BITERR , Bit error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 27. " DESYNC , Desynchronization of slave device" "No,Yes"
|
|
bitfld.long 0x00 26. " PARITYERR , Parity error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 25. " TIMEOUT , Time-out because of non-activation of ENA pin" "No timeout,Timeout"
|
|
bitfld.long 0x00 24. " DLENERR , Data length error flag" "No,Yes"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " LCSNR , Last chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " RXDATA , SPI receive data"
|
|
rgroup.long (0x14+0x200)++0x03
|
|
line.long 0x00 "RXRAM, Multi-buffer RAM Receive Buffer Register 5"
|
|
bitfld.long 0x00 31. " RXEMPTY , Receive data buffer empty" "Not empty,Empty"
|
|
bitfld.long 0x00 30. " RXOVR , Receive data buffer overrun" "No overrun,Overrun"
|
|
newline
|
|
bitfld.long 0x00 29. " TXFULL , Transmit data buffer full" "Not full,Full"
|
|
bitfld.long 0x00 28. " BITERR , Bit error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 27. " DESYNC , Desynchronization of slave device" "No,Yes"
|
|
bitfld.long 0x00 26. " PARITYERR , Parity error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 25. " TIMEOUT , Time-out because of non-activation of ENA pin" "No timeout,Timeout"
|
|
bitfld.long 0x00 24. " DLENERR , Data length error flag" "No,Yes"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " LCSNR , Last chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " RXDATA , SPI receive data"
|
|
rgroup.long (0x18+0x200)++0x03
|
|
line.long 0x00 "RXRAM, Multi-buffer RAM Receive Buffer Register 6"
|
|
bitfld.long 0x00 31. " RXEMPTY , Receive data buffer empty" "Not empty,Empty"
|
|
bitfld.long 0x00 30. " RXOVR , Receive data buffer overrun" "No overrun,Overrun"
|
|
newline
|
|
bitfld.long 0x00 29. " TXFULL , Transmit data buffer full" "Not full,Full"
|
|
bitfld.long 0x00 28. " BITERR , Bit error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 27. " DESYNC , Desynchronization of slave device" "No,Yes"
|
|
bitfld.long 0x00 26. " PARITYERR , Parity error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 25. " TIMEOUT , Time-out because of non-activation of ENA pin" "No timeout,Timeout"
|
|
bitfld.long 0x00 24. " DLENERR , Data length error flag" "No,Yes"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " LCSNR , Last chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " RXDATA , SPI receive data"
|
|
rgroup.long (0x1C+0x200)++0x03
|
|
line.long 0x00 "RXRAM, Multi-buffer RAM Receive Buffer Register 7"
|
|
bitfld.long 0x00 31. " RXEMPTY , Receive data buffer empty" "Not empty,Empty"
|
|
bitfld.long 0x00 30. " RXOVR , Receive data buffer overrun" "No overrun,Overrun"
|
|
newline
|
|
bitfld.long 0x00 29. " TXFULL , Transmit data buffer full" "Not full,Full"
|
|
bitfld.long 0x00 28. " BITERR , Bit error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 27. " DESYNC , Desynchronization of slave device" "No,Yes"
|
|
bitfld.long 0x00 26. " PARITYERR , Parity error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 25. " TIMEOUT , Time-out because of non-activation of ENA pin" "No timeout,Timeout"
|
|
bitfld.long 0x00 24. " DLENERR , Data length error flag" "No,Yes"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " LCSNR , Last chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " RXDATA , SPI receive data"
|
|
rgroup.long (0x20+0x200)++0x03
|
|
line.long 0x00 "RXRAM, Multi-buffer RAM Receive Buffer Register 8"
|
|
bitfld.long 0x00 31. " RXEMPTY , Receive data buffer empty" "Not empty,Empty"
|
|
bitfld.long 0x00 30. " RXOVR , Receive data buffer overrun" "No overrun,Overrun"
|
|
newline
|
|
bitfld.long 0x00 29. " TXFULL , Transmit data buffer full" "Not full,Full"
|
|
bitfld.long 0x00 28. " BITERR , Bit error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 27. " DESYNC , Desynchronization of slave device" "No,Yes"
|
|
bitfld.long 0x00 26. " PARITYERR , Parity error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 25. " TIMEOUT , Time-out because of non-activation of ENA pin" "No timeout,Timeout"
|
|
bitfld.long 0x00 24. " DLENERR , Data length error flag" "No,Yes"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " LCSNR , Last chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " RXDATA , SPI receive data"
|
|
rgroup.long (0x24+0x200)++0x03
|
|
line.long 0x00 "RXRAM, Multi-buffer RAM Receive Buffer Register 9"
|
|
bitfld.long 0x00 31. " RXEMPTY , Receive data buffer empty" "Not empty,Empty"
|
|
bitfld.long 0x00 30. " RXOVR , Receive data buffer overrun" "No overrun,Overrun"
|
|
newline
|
|
bitfld.long 0x00 29. " TXFULL , Transmit data buffer full" "Not full,Full"
|
|
bitfld.long 0x00 28. " BITERR , Bit error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 27. " DESYNC , Desynchronization of slave device" "No,Yes"
|
|
bitfld.long 0x00 26. " PARITYERR , Parity error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 25. " TIMEOUT , Time-out because of non-activation of ENA pin" "No timeout,Timeout"
|
|
bitfld.long 0x00 24. " DLENERR , Data length error flag" "No,Yes"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " LCSNR , Last chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " RXDATA , SPI receive data"
|
|
rgroup.long (0x28+0x200)++0x03
|
|
line.long 0x00 "RXRAM, Multi-buffer RAM Receive Buffer Register 10"
|
|
bitfld.long 0x00 31. " RXEMPTY , Receive data buffer empty" "Not empty,Empty"
|
|
bitfld.long 0x00 30. " RXOVR , Receive data buffer overrun" "No overrun,Overrun"
|
|
newline
|
|
bitfld.long 0x00 29. " TXFULL , Transmit data buffer full" "Not full,Full"
|
|
bitfld.long 0x00 28. " BITERR , Bit error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 27. " DESYNC , Desynchronization of slave device" "No,Yes"
|
|
bitfld.long 0x00 26. " PARITYERR , Parity error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 25. " TIMEOUT , Time-out because of non-activation of ENA pin" "No timeout,Timeout"
|
|
bitfld.long 0x00 24. " DLENERR , Data length error flag" "No,Yes"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " LCSNR , Last chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " RXDATA , SPI receive data"
|
|
rgroup.long (0x2C+0x200)++0x03
|
|
line.long 0x00 "RXRAM, Multi-buffer RAM Receive Buffer Register 11"
|
|
bitfld.long 0x00 31. " RXEMPTY , Receive data buffer empty" "Not empty,Empty"
|
|
bitfld.long 0x00 30. " RXOVR , Receive data buffer overrun" "No overrun,Overrun"
|
|
newline
|
|
bitfld.long 0x00 29. " TXFULL , Transmit data buffer full" "Not full,Full"
|
|
bitfld.long 0x00 28. " BITERR , Bit error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 27. " DESYNC , Desynchronization of slave device" "No,Yes"
|
|
bitfld.long 0x00 26. " PARITYERR , Parity error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 25. " TIMEOUT , Time-out because of non-activation of ENA pin" "No timeout,Timeout"
|
|
bitfld.long 0x00 24. " DLENERR , Data length error flag" "No,Yes"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " LCSNR , Last chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " RXDATA , SPI receive data"
|
|
rgroup.long (0x30+0x200)++0x03
|
|
line.long 0x00 "RXRAM, Multi-buffer RAM Receive Buffer Register 12"
|
|
bitfld.long 0x00 31. " RXEMPTY , Receive data buffer empty" "Not empty,Empty"
|
|
bitfld.long 0x00 30. " RXOVR , Receive data buffer overrun" "No overrun,Overrun"
|
|
newline
|
|
bitfld.long 0x00 29. " TXFULL , Transmit data buffer full" "Not full,Full"
|
|
bitfld.long 0x00 28. " BITERR , Bit error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 27. " DESYNC , Desynchronization of slave device" "No,Yes"
|
|
bitfld.long 0x00 26. " PARITYERR , Parity error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 25. " TIMEOUT , Time-out because of non-activation of ENA pin" "No timeout,Timeout"
|
|
bitfld.long 0x00 24. " DLENERR , Data length error flag" "No,Yes"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " LCSNR , Last chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " RXDATA , SPI receive data"
|
|
rgroup.long (0x34+0x200)++0x03
|
|
line.long 0x00 "RXRAM, Multi-buffer RAM Receive Buffer Register 13"
|
|
bitfld.long 0x00 31. " RXEMPTY , Receive data buffer empty" "Not empty,Empty"
|
|
bitfld.long 0x00 30. " RXOVR , Receive data buffer overrun" "No overrun,Overrun"
|
|
newline
|
|
bitfld.long 0x00 29. " TXFULL , Transmit data buffer full" "Not full,Full"
|
|
bitfld.long 0x00 28. " BITERR , Bit error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 27. " DESYNC , Desynchronization of slave device" "No,Yes"
|
|
bitfld.long 0x00 26. " PARITYERR , Parity error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 25. " TIMEOUT , Time-out because of non-activation of ENA pin" "No timeout,Timeout"
|
|
bitfld.long 0x00 24. " DLENERR , Data length error flag" "No,Yes"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " LCSNR , Last chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " RXDATA , SPI receive data"
|
|
rgroup.long (0x38+0x200)++0x03
|
|
line.long 0x00 "RXRAM, Multi-buffer RAM Receive Buffer Register 14"
|
|
bitfld.long 0x00 31. " RXEMPTY , Receive data buffer empty" "Not empty,Empty"
|
|
bitfld.long 0x00 30. " RXOVR , Receive data buffer overrun" "No overrun,Overrun"
|
|
newline
|
|
bitfld.long 0x00 29. " TXFULL , Transmit data buffer full" "Not full,Full"
|
|
bitfld.long 0x00 28. " BITERR , Bit error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 27. " DESYNC , Desynchronization of slave device" "No,Yes"
|
|
bitfld.long 0x00 26. " PARITYERR , Parity error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 25. " TIMEOUT , Time-out because of non-activation of ENA pin" "No timeout,Timeout"
|
|
bitfld.long 0x00 24. " DLENERR , Data length error flag" "No,Yes"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " LCSNR , Last chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " RXDATA , SPI receive data"
|
|
rgroup.long (0x3C+0x200)++0x03
|
|
line.long 0x00 "RXRAM, Multi-buffer RAM Receive Buffer Register 15"
|
|
bitfld.long 0x00 31. " RXEMPTY , Receive data buffer empty" "Not empty,Empty"
|
|
bitfld.long 0x00 30. " RXOVR , Receive data buffer overrun" "No overrun,Overrun"
|
|
newline
|
|
bitfld.long 0x00 29. " TXFULL , Transmit data buffer full" "Not full,Full"
|
|
bitfld.long 0x00 28. " BITERR , Bit error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 27. " DESYNC , Desynchronization of slave device" "No,Yes"
|
|
bitfld.long 0x00 26. " PARITYERR , Parity error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 25. " TIMEOUT , Time-out because of non-activation of ENA pin" "No timeout,Timeout"
|
|
bitfld.long 0x00 24. " DLENERR , Data length error flag" "No,Yes"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " LCSNR , Last chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " RXDATA , SPI receive data"
|
|
rgroup.long (0x40+0x200)++0x03
|
|
line.long 0x00 "RXRAM, Multi-buffer RAM Receive Buffer Register 16"
|
|
bitfld.long 0x00 31. " RXEMPTY , Receive data buffer empty" "Not empty,Empty"
|
|
bitfld.long 0x00 30. " RXOVR , Receive data buffer overrun" "No overrun,Overrun"
|
|
newline
|
|
bitfld.long 0x00 29. " TXFULL , Transmit data buffer full" "Not full,Full"
|
|
bitfld.long 0x00 28. " BITERR , Bit error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 27. " DESYNC , Desynchronization of slave device" "No,Yes"
|
|
bitfld.long 0x00 26. " PARITYERR , Parity error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 25. " TIMEOUT , Time-out because of non-activation of ENA pin" "No timeout,Timeout"
|
|
bitfld.long 0x00 24. " DLENERR , Data length error flag" "No,Yes"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " LCSNR , Last chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " RXDATA , SPI receive data"
|
|
rgroup.long (0x44+0x200)++0x03
|
|
line.long 0x00 "RXRAM, Multi-buffer RAM Receive Buffer Register 17"
|
|
bitfld.long 0x00 31. " RXEMPTY , Receive data buffer empty" "Not empty,Empty"
|
|
bitfld.long 0x00 30. " RXOVR , Receive data buffer overrun" "No overrun,Overrun"
|
|
newline
|
|
bitfld.long 0x00 29. " TXFULL , Transmit data buffer full" "Not full,Full"
|
|
bitfld.long 0x00 28. " BITERR , Bit error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 27. " DESYNC , Desynchronization of slave device" "No,Yes"
|
|
bitfld.long 0x00 26. " PARITYERR , Parity error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 25. " TIMEOUT , Time-out because of non-activation of ENA pin" "No timeout,Timeout"
|
|
bitfld.long 0x00 24. " DLENERR , Data length error flag" "No,Yes"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " LCSNR , Last chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " RXDATA , SPI receive data"
|
|
rgroup.long (0x48+0x200)++0x03
|
|
line.long 0x00 "RXRAM, Multi-buffer RAM Receive Buffer Register 18"
|
|
bitfld.long 0x00 31. " RXEMPTY , Receive data buffer empty" "Not empty,Empty"
|
|
bitfld.long 0x00 30. " RXOVR , Receive data buffer overrun" "No overrun,Overrun"
|
|
newline
|
|
bitfld.long 0x00 29. " TXFULL , Transmit data buffer full" "Not full,Full"
|
|
bitfld.long 0x00 28. " BITERR , Bit error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 27. " DESYNC , Desynchronization of slave device" "No,Yes"
|
|
bitfld.long 0x00 26. " PARITYERR , Parity error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 25. " TIMEOUT , Time-out because of non-activation of ENA pin" "No timeout,Timeout"
|
|
bitfld.long 0x00 24. " DLENERR , Data length error flag" "No,Yes"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " LCSNR , Last chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " RXDATA , SPI receive data"
|
|
rgroup.long (0x4C+0x200)++0x03
|
|
line.long 0x00 "RXRAM, Multi-buffer RAM Receive Buffer Register 19"
|
|
bitfld.long 0x00 31. " RXEMPTY , Receive data buffer empty" "Not empty,Empty"
|
|
bitfld.long 0x00 30. " RXOVR , Receive data buffer overrun" "No overrun,Overrun"
|
|
newline
|
|
bitfld.long 0x00 29. " TXFULL , Transmit data buffer full" "Not full,Full"
|
|
bitfld.long 0x00 28. " BITERR , Bit error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 27. " DESYNC , Desynchronization of slave device" "No,Yes"
|
|
bitfld.long 0x00 26. " PARITYERR , Parity error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 25. " TIMEOUT , Time-out because of non-activation of ENA pin" "No timeout,Timeout"
|
|
bitfld.long 0x00 24. " DLENERR , Data length error flag" "No,Yes"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " LCSNR , Last chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " RXDATA , SPI receive data"
|
|
rgroup.long (0x50+0x200)++0x03
|
|
line.long 0x00 "RXRAM, Multi-buffer RAM Receive Buffer Register 20"
|
|
bitfld.long 0x00 31. " RXEMPTY , Receive data buffer empty" "Not empty,Empty"
|
|
bitfld.long 0x00 30. " RXOVR , Receive data buffer overrun" "No overrun,Overrun"
|
|
newline
|
|
bitfld.long 0x00 29. " TXFULL , Transmit data buffer full" "Not full,Full"
|
|
bitfld.long 0x00 28. " BITERR , Bit error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 27. " DESYNC , Desynchronization of slave device" "No,Yes"
|
|
bitfld.long 0x00 26. " PARITYERR , Parity error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 25. " TIMEOUT , Time-out because of non-activation of ENA pin" "No timeout,Timeout"
|
|
bitfld.long 0x00 24. " DLENERR , Data length error flag" "No,Yes"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " LCSNR , Last chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " RXDATA , SPI receive data"
|
|
rgroup.long (0x54+0x200)++0x03
|
|
line.long 0x00 "RXRAM, Multi-buffer RAM Receive Buffer Register 21"
|
|
bitfld.long 0x00 31. " RXEMPTY , Receive data buffer empty" "Not empty,Empty"
|
|
bitfld.long 0x00 30. " RXOVR , Receive data buffer overrun" "No overrun,Overrun"
|
|
newline
|
|
bitfld.long 0x00 29. " TXFULL , Transmit data buffer full" "Not full,Full"
|
|
bitfld.long 0x00 28. " BITERR , Bit error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 27. " DESYNC , Desynchronization of slave device" "No,Yes"
|
|
bitfld.long 0x00 26. " PARITYERR , Parity error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 25. " TIMEOUT , Time-out because of non-activation of ENA pin" "No timeout,Timeout"
|
|
bitfld.long 0x00 24. " DLENERR , Data length error flag" "No,Yes"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " LCSNR , Last chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " RXDATA , SPI receive data"
|
|
rgroup.long (0x58+0x200)++0x03
|
|
line.long 0x00 "RXRAM, Multi-buffer RAM Receive Buffer Register 22"
|
|
bitfld.long 0x00 31. " RXEMPTY , Receive data buffer empty" "Not empty,Empty"
|
|
bitfld.long 0x00 30. " RXOVR , Receive data buffer overrun" "No overrun,Overrun"
|
|
newline
|
|
bitfld.long 0x00 29. " TXFULL , Transmit data buffer full" "Not full,Full"
|
|
bitfld.long 0x00 28. " BITERR , Bit error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 27. " DESYNC , Desynchronization of slave device" "No,Yes"
|
|
bitfld.long 0x00 26. " PARITYERR , Parity error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 25. " TIMEOUT , Time-out because of non-activation of ENA pin" "No timeout,Timeout"
|
|
bitfld.long 0x00 24. " DLENERR , Data length error flag" "No,Yes"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " LCSNR , Last chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " RXDATA , SPI receive data"
|
|
rgroup.long (0x5C+0x200)++0x03
|
|
line.long 0x00 "RXRAM, Multi-buffer RAM Receive Buffer Register 23"
|
|
bitfld.long 0x00 31. " RXEMPTY , Receive data buffer empty" "Not empty,Empty"
|
|
bitfld.long 0x00 30. " RXOVR , Receive data buffer overrun" "No overrun,Overrun"
|
|
newline
|
|
bitfld.long 0x00 29. " TXFULL , Transmit data buffer full" "Not full,Full"
|
|
bitfld.long 0x00 28. " BITERR , Bit error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 27. " DESYNC , Desynchronization of slave device" "No,Yes"
|
|
bitfld.long 0x00 26. " PARITYERR , Parity error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 25. " TIMEOUT , Time-out because of non-activation of ENA pin" "No timeout,Timeout"
|
|
bitfld.long 0x00 24. " DLENERR , Data length error flag" "No,Yes"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " LCSNR , Last chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " RXDATA , SPI receive data"
|
|
rgroup.long (0x60+0x200)++0x03
|
|
line.long 0x00 "RXRAM, Multi-buffer RAM Receive Buffer Register 24"
|
|
bitfld.long 0x00 31. " RXEMPTY , Receive data buffer empty" "Not empty,Empty"
|
|
bitfld.long 0x00 30. " RXOVR , Receive data buffer overrun" "No overrun,Overrun"
|
|
newline
|
|
bitfld.long 0x00 29. " TXFULL , Transmit data buffer full" "Not full,Full"
|
|
bitfld.long 0x00 28. " BITERR , Bit error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 27. " DESYNC , Desynchronization of slave device" "No,Yes"
|
|
bitfld.long 0x00 26. " PARITYERR , Parity error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 25. " TIMEOUT , Time-out because of non-activation of ENA pin" "No timeout,Timeout"
|
|
bitfld.long 0x00 24. " DLENERR , Data length error flag" "No,Yes"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " LCSNR , Last chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " RXDATA , SPI receive data"
|
|
rgroup.long (0x64+0x200)++0x03
|
|
line.long 0x00 "RXRAM, Multi-buffer RAM Receive Buffer Register 25"
|
|
bitfld.long 0x00 31. " RXEMPTY , Receive data buffer empty" "Not empty,Empty"
|
|
bitfld.long 0x00 30. " RXOVR , Receive data buffer overrun" "No overrun,Overrun"
|
|
newline
|
|
bitfld.long 0x00 29. " TXFULL , Transmit data buffer full" "Not full,Full"
|
|
bitfld.long 0x00 28. " BITERR , Bit error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 27. " DESYNC , Desynchronization of slave device" "No,Yes"
|
|
bitfld.long 0x00 26. " PARITYERR , Parity error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 25. " TIMEOUT , Time-out because of non-activation of ENA pin" "No timeout,Timeout"
|
|
bitfld.long 0x00 24. " DLENERR , Data length error flag" "No,Yes"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " LCSNR , Last chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " RXDATA , SPI receive data"
|
|
rgroup.long (0x68+0x200)++0x03
|
|
line.long 0x00 "RXRAM, Multi-buffer RAM Receive Buffer Register 26"
|
|
bitfld.long 0x00 31. " RXEMPTY , Receive data buffer empty" "Not empty,Empty"
|
|
bitfld.long 0x00 30. " RXOVR , Receive data buffer overrun" "No overrun,Overrun"
|
|
newline
|
|
bitfld.long 0x00 29. " TXFULL , Transmit data buffer full" "Not full,Full"
|
|
bitfld.long 0x00 28. " BITERR , Bit error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 27. " DESYNC , Desynchronization of slave device" "No,Yes"
|
|
bitfld.long 0x00 26. " PARITYERR , Parity error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 25. " TIMEOUT , Time-out because of non-activation of ENA pin" "No timeout,Timeout"
|
|
bitfld.long 0x00 24. " DLENERR , Data length error flag" "No,Yes"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " LCSNR , Last chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " RXDATA , SPI receive data"
|
|
rgroup.long (0x6C+0x200)++0x03
|
|
line.long 0x00 "RXRAM, Multi-buffer RAM Receive Buffer Register 27"
|
|
bitfld.long 0x00 31. " RXEMPTY , Receive data buffer empty" "Not empty,Empty"
|
|
bitfld.long 0x00 30. " RXOVR , Receive data buffer overrun" "No overrun,Overrun"
|
|
newline
|
|
bitfld.long 0x00 29. " TXFULL , Transmit data buffer full" "Not full,Full"
|
|
bitfld.long 0x00 28. " BITERR , Bit error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 27. " DESYNC , Desynchronization of slave device" "No,Yes"
|
|
bitfld.long 0x00 26. " PARITYERR , Parity error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 25. " TIMEOUT , Time-out because of non-activation of ENA pin" "No timeout,Timeout"
|
|
bitfld.long 0x00 24. " DLENERR , Data length error flag" "No,Yes"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " LCSNR , Last chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " RXDATA , SPI receive data"
|
|
rgroup.long (0x70+0x200)++0x03
|
|
line.long 0x00 "RXRAM, Multi-buffer RAM Receive Buffer Register 28"
|
|
bitfld.long 0x00 31. " RXEMPTY , Receive data buffer empty" "Not empty,Empty"
|
|
bitfld.long 0x00 30. " RXOVR , Receive data buffer overrun" "No overrun,Overrun"
|
|
newline
|
|
bitfld.long 0x00 29. " TXFULL , Transmit data buffer full" "Not full,Full"
|
|
bitfld.long 0x00 28. " BITERR , Bit error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 27. " DESYNC , Desynchronization of slave device" "No,Yes"
|
|
bitfld.long 0x00 26. " PARITYERR , Parity error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 25. " TIMEOUT , Time-out because of non-activation of ENA pin" "No timeout,Timeout"
|
|
bitfld.long 0x00 24. " DLENERR , Data length error flag" "No,Yes"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " LCSNR , Last chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " RXDATA , SPI receive data"
|
|
rgroup.long (0x74+0x200)++0x03
|
|
line.long 0x00 "RXRAM, Multi-buffer RAM Receive Buffer Register 29"
|
|
bitfld.long 0x00 31. " RXEMPTY , Receive data buffer empty" "Not empty,Empty"
|
|
bitfld.long 0x00 30. " RXOVR , Receive data buffer overrun" "No overrun,Overrun"
|
|
newline
|
|
bitfld.long 0x00 29. " TXFULL , Transmit data buffer full" "Not full,Full"
|
|
bitfld.long 0x00 28. " BITERR , Bit error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 27. " DESYNC , Desynchronization of slave device" "No,Yes"
|
|
bitfld.long 0x00 26. " PARITYERR , Parity error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 25. " TIMEOUT , Time-out because of non-activation of ENA pin" "No timeout,Timeout"
|
|
bitfld.long 0x00 24. " DLENERR , Data length error flag" "No,Yes"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " LCSNR , Last chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " RXDATA , SPI receive data"
|
|
rgroup.long (0x78+0x200)++0x03
|
|
line.long 0x00 "RXRAM, Multi-buffer RAM Receive Buffer Register 30"
|
|
bitfld.long 0x00 31. " RXEMPTY , Receive data buffer empty" "Not empty,Empty"
|
|
bitfld.long 0x00 30. " RXOVR , Receive data buffer overrun" "No overrun,Overrun"
|
|
newline
|
|
bitfld.long 0x00 29. " TXFULL , Transmit data buffer full" "Not full,Full"
|
|
bitfld.long 0x00 28. " BITERR , Bit error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 27. " DESYNC , Desynchronization of slave device" "No,Yes"
|
|
bitfld.long 0x00 26. " PARITYERR , Parity error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 25. " TIMEOUT , Time-out because of non-activation of ENA pin" "No timeout,Timeout"
|
|
bitfld.long 0x00 24. " DLENERR , Data length error flag" "No,Yes"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " LCSNR , Last chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " RXDATA , SPI receive data"
|
|
rgroup.long (0x7C+0x200)++0x03
|
|
line.long 0x00 "RXRAM, Multi-buffer RAM Receive Buffer Register 31"
|
|
bitfld.long 0x00 31. " RXEMPTY , Receive data buffer empty" "Not empty,Empty"
|
|
bitfld.long 0x00 30. " RXOVR , Receive data buffer overrun" "No overrun,Overrun"
|
|
newline
|
|
bitfld.long 0x00 29. " TXFULL , Transmit data buffer full" "Not full,Full"
|
|
bitfld.long 0x00 28. " BITERR , Bit error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 27. " DESYNC , Desynchronization of slave device" "No,Yes"
|
|
bitfld.long 0x00 26. " PARITYERR , Parity error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 25. " TIMEOUT , Time-out because of non-activation of ENA pin" "No timeout,Timeout"
|
|
bitfld.long 0x00 24. " DLENERR , Data length error flag" "No,Yes"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " LCSNR , Last chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " RXDATA , SPI receive data"
|
|
rgroup.long (0x80+0x200)++0x03
|
|
line.long 0x00 "RXRAM, Multi-buffer RAM Receive Buffer Register 32"
|
|
bitfld.long 0x00 31. " RXEMPTY , Receive data buffer empty" "Not empty,Empty"
|
|
bitfld.long 0x00 30. " RXOVR , Receive data buffer overrun" "No overrun,Overrun"
|
|
newline
|
|
bitfld.long 0x00 29. " TXFULL , Transmit data buffer full" "Not full,Full"
|
|
bitfld.long 0x00 28. " BITERR , Bit error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 27. " DESYNC , Desynchronization of slave device" "No,Yes"
|
|
bitfld.long 0x00 26. " PARITYERR , Parity error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 25. " TIMEOUT , Time-out because of non-activation of ENA pin" "No timeout,Timeout"
|
|
bitfld.long 0x00 24. " DLENERR , Data length error flag" "No,Yes"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " LCSNR , Last chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " RXDATA , SPI receive data"
|
|
rgroup.long (0x84+0x200)++0x03
|
|
line.long 0x00 "RXRAM, Multi-buffer RAM Receive Buffer Register 33"
|
|
bitfld.long 0x00 31. " RXEMPTY , Receive data buffer empty" "Not empty,Empty"
|
|
bitfld.long 0x00 30. " RXOVR , Receive data buffer overrun" "No overrun,Overrun"
|
|
newline
|
|
bitfld.long 0x00 29. " TXFULL , Transmit data buffer full" "Not full,Full"
|
|
bitfld.long 0x00 28. " BITERR , Bit error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 27. " DESYNC , Desynchronization of slave device" "No,Yes"
|
|
bitfld.long 0x00 26. " PARITYERR , Parity error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 25. " TIMEOUT , Time-out because of non-activation of ENA pin" "No timeout,Timeout"
|
|
bitfld.long 0x00 24. " DLENERR , Data length error flag" "No,Yes"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " LCSNR , Last chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " RXDATA , SPI receive data"
|
|
rgroup.long (0x88+0x200)++0x03
|
|
line.long 0x00 "RXRAM, Multi-buffer RAM Receive Buffer Register 34"
|
|
bitfld.long 0x00 31. " RXEMPTY , Receive data buffer empty" "Not empty,Empty"
|
|
bitfld.long 0x00 30. " RXOVR , Receive data buffer overrun" "No overrun,Overrun"
|
|
newline
|
|
bitfld.long 0x00 29. " TXFULL , Transmit data buffer full" "Not full,Full"
|
|
bitfld.long 0x00 28. " BITERR , Bit error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 27. " DESYNC , Desynchronization of slave device" "No,Yes"
|
|
bitfld.long 0x00 26. " PARITYERR , Parity error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 25. " TIMEOUT , Time-out because of non-activation of ENA pin" "No timeout,Timeout"
|
|
bitfld.long 0x00 24. " DLENERR , Data length error flag" "No,Yes"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " LCSNR , Last chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " RXDATA , SPI receive data"
|
|
rgroup.long (0x8C+0x200)++0x03
|
|
line.long 0x00 "RXRAM, Multi-buffer RAM Receive Buffer Register 35"
|
|
bitfld.long 0x00 31. " RXEMPTY , Receive data buffer empty" "Not empty,Empty"
|
|
bitfld.long 0x00 30. " RXOVR , Receive data buffer overrun" "No overrun,Overrun"
|
|
newline
|
|
bitfld.long 0x00 29. " TXFULL , Transmit data buffer full" "Not full,Full"
|
|
bitfld.long 0x00 28. " BITERR , Bit error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 27. " DESYNC , Desynchronization of slave device" "No,Yes"
|
|
bitfld.long 0x00 26. " PARITYERR , Parity error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 25. " TIMEOUT , Time-out because of non-activation of ENA pin" "No timeout,Timeout"
|
|
bitfld.long 0x00 24. " DLENERR , Data length error flag" "No,Yes"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " LCSNR , Last chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " RXDATA , SPI receive data"
|
|
rgroup.long (0x90+0x200)++0x03
|
|
line.long 0x00 "RXRAM, Multi-buffer RAM Receive Buffer Register 36"
|
|
bitfld.long 0x00 31. " RXEMPTY , Receive data buffer empty" "Not empty,Empty"
|
|
bitfld.long 0x00 30. " RXOVR , Receive data buffer overrun" "No overrun,Overrun"
|
|
newline
|
|
bitfld.long 0x00 29. " TXFULL , Transmit data buffer full" "Not full,Full"
|
|
bitfld.long 0x00 28. " BITERR , Bit error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 27. " DESYNC , Desynchronization of slave device" "No,Yes"
|
|
bitfld.long 0x00 26. " PARITYERR , Parity error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 25. " TIMEOUT , Time-out because of non-activation of ENA pin" "No timeout,Timeout"
|
|
bitfld.long 0x00 24. " DLENERR , Data length error flag" "No,Yes"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " LCSNR , Last chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " RXDATA , SPI receive data"
|
|
rgroup.long (0x94+0x200)++0x03
|
|
line.long 0x00 "RXRAM, Multi-buffer RAM Receive Buffer Register 37"
|
|
bitfld.long 0x00 31. " RXEMPTY , Receive data buffer empty" "Not empty,Empty"
|
|
bitfld.long 0x00 30. " RXOVR , Receive data buffer overrun" "No overrun,Overrun"
|
|
newline
|
|
bitfld.long 0x00 29. " TXFULL , Transmit data buffer full" "Not full,Full"
|
|
bitfld.long 0x00 28. " BITERR , Bit error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 27. " DESYNC , Desynchronization of slave device" "No,Yes"
|
|
bitfld.long 0x00 26. " PARITYERR , Parity error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 25. " TIMEOUT , Time-out because of non-activation of ENA pin" "No timeout,Timeout"
|
|
bitfld.long 0x00 24. " DLENERR , Data length error flag" "No,Yes"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " LCSNR , Last chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " RXDATA , SPI receive data"
|
|
rgroup.long (0x98+0x200)++0x03
|
|
line.long 0x00 "RXRAM, Multi-buffer RAM Receive Buffer Register 38"
|
|
bitfld.long 0x00 31. " RXEMPTY , Receive data buffer empty" "Not empty,Empty"
|
|
bitfld.long 0x00 30. " RXOVR , Receive data buffer overrun" "No overrun,Overrun"
|
|
newline
|
|
bitfld.long 0x00 29. " TXFULL , Transmit data buffer full" "Not full,Full"
|
|
bitfld.long 0x00 28. " BITERR , Bit error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 27. " DESYNC , Desynchronization of slave device" "No,Yes"
|
|
bitfld.long 0x00 26. " PARITYERR , Parity error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 25. " TIMEOUT , Time-out because of non-activation of ENA pin" "No timeout,Timeout"
|
|
bitfld.long 0x00 24. " DLENERR , Data length error flag" "No,Yes"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " LCSNR , Last chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " RXDATA , SPI receive data"
|
|
rgroup.long (0x9C+0x200)++0x03
|
|
line.long 0x00 "RXRAM, Multi-buffer RAM Receive Buffer Register 39"
|
|
bitfld.long 0x00 31. " RXEMPTY , Receive data buffer empty" "Not empty,Empty"
|
|
bitfld.long 0x00 30. " RXOVR , Receive data buffer overrun" "No overrun,Overrun"
|
|
newline
|
|
bitfld.long 0x00 29. " TXFULL , Transmit data buffer full" "Not full,Full"
|
|
bitfld.long 0x00 28. " BITERR , Bit error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 27. " DESYNC , Desynchronization of slave device" "No,Yes"
|
|
bitfld.long 0x00 26. " PARITYERR , Parity error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 25. " TIMEOUT , Time-out because of non-activation of ENA pin" "No timeout,Timeout"
|
|
bitfld.long 0x00 24. " DLENERR , Data length error flag" "No,Yes"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " LCSNR , Last chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " RXDATA , SPI receive data"
|
|
rgroup.long (0xA0+0x200)++0x03
|
|
line.long 0x00 "RXRAM, Multi-buffer RAM Receive Buffer Register 40"
|
|
bitfld.long 0x00 31. " RXEMPTY , Receive data buffer empty" "Not empty,Empty"
|
|
bitfld.long 0x00 30. " RXOVR , Receive data buffer overrun" "No overrun,Overrun"
|
|
newline
|
|
bitfld.long 0x00 29. " TXFULL , Transmit data buffer full" "Not full,Full"
|
|
bitfld.long 0x00 28. " BITERR , Bit error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 27. " DESYNC , Desynchronization of slave device" "No,Yes"
|
|
bitfld.long 0x00 26. " PARITYERR , Parity error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 25. " TIMEOUT , Time-out because of non-activation of ENA pin" "No timeout,Timeout"
|
|
bitfld.long 0x00 24. " DLENERR , Data length error flag" "No,Yes"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " LCSNR , Last chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " RXDATA , SPI receive data"
|
|
rgroup.long (0xA4+0x200)++0x03
|
|
line.long 0x00 "RXRAM, Multi-buffer RAM Receive Buffer Register 41"
|
|
bitfld.long 0x00 31. " RXEMPTY , Receive data buffer empty" "Not empty,Empty"
|
|
bitfld.long 0x00 30. " RXOVR , Receive data buffer overrun" "No overrun,Overrun"
|
|
newline
|
|
bitfld.long 0x00 29. " TXFULL , Transmit data buffer full" "Not full,Full"
|
|
bitfld.long 0x00 28. " BITERR , Bit error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 27. " DESYNC , Desynchronization of slave device" "No,Yes"
|
|
bitfld.long 0x00 26. " PARITYERR , Parity error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 25. " TIMEOUT , Time-out because of non-activation of ENA pin" "No timeout,Timeout"
|
|
bitfld.long 0x00 24. " DLENERR , Data length error flag" "No,Yes"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " LCSNR , Last chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " RXDATA , SPI receive data"
|
|
rgroup.long (0xA8+0x200)++0x03
|
|
line.long 0x00 "RXRAM, Multi-buffer RAM Receive Buffer Register 42"
|
|
bitfld.long 0x00 31. " RXEMPTY , Receive data buffer empty" "Not empty,Empty"
|
|
bitfld.long 0x00 30. " RXOVR , Receive data buffer overrun" "No overrun,Overrun"
|
|
newline
|
|
bitfld.long 0x00 29. " TXFULL , Transmit data buffer full" "Not full,Full"
|
|
bitfld.long 0x00 28. " BITERR , Bit error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 27. " DESYNC , Desynchronization of slave device" "No,Yes"
|
|
bitfld.long 0x00 26. " PARITYERR , Parity error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 25. " TIMEOUT , Time-out because of non-activation of ENA pin" "No timeout,Timeout"
|
|
bitfld.long 0x00 24. " DLENERR , Data length error flag" "No,Yes"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " LCSNR , Last chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " RXDATA , SPI receive data"
|
|
rgroup.long (0xAC+0x200)++0x03
|
|
line.long 0x00 "RXRAM, Multi-buffer RAM Receive Buffer Register 43"
|
|
bitfld.long 0x00 31. " RXEMPTY , Receive data buffer empty" "Not empty,Empty"
|
|
bitfld.long 0x00 30. " RXOVR , Receive data buffer overrun" "No overrun,Overrun"
|
|
newline
|
|
bitfld.long 0x00 29. " TXFULL , Transmit data buffer full" "Not full,Full"
|
|
bitfld.long 0x00 28. " BITERR , Bit error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 27. " DESYNC , Desynchronization of slave device" "No,Yes"
|
|
bitfld.long 0x00 26. " PARITYERR , Parity error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 25. " TIMEOUT , Time-out because of non-activation of ENA pin" "No timeout,Timeout"
|
|
bitfld.long 0x00 24. " DLENERR , Data length error flag" "No,Yes"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " LCSNR , Last chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " RXDATA , SPI receive data"
|
|
rgroup.long (0xB0+0x200)++0x03
|
|
line.long 0x00 "RXRAM, Multi-buffer RAM Receive Buffer Register 44"
|
|
bitfld.long 0x00 31. " RXEMPTY , Receive data buffer empty" "Not empty,Empty"
|
|
bitfld.long 0x00 30. " RXOVR , Receive data buffer overrun" "No overrun,Overrun"
|
|
newline
|
|
bitfld.long 0x00 29. " TXFULL , Transmit data buffer full" "Not full,Full"
|
|
bitfld.long 0x00 28. " BITERR , Bit error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 27. " DESYNC , Desynchronization of slave device" "No,Yes"
|
|
bitfld.long 0x00 26. " PARITYERR , Parity error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 25. " TIMEOUT , Time-out because of non-activation of ENA pin" "No timeout,Timeout"
|
|
bitfld.long 0x00 24. " DLENERR , Data length error flag" "No,Yes"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " LCSNR , Last chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " RXDATA , SPI receive data"
|
|
rgroup.long (0xB4+0x200)++0x03
|
|
line.long 0x00 "RXRAM, Multi-buffer RAM Receive Buffer Register 45"
|
|
bitfld.long 0x00 31. " RXEMPTY , Receive data buffer empty" "Not empty,Empty"
|
|
bitfld.long 0x00 30. " RXOVR , Receive data buffer overrun" "No overrun,Overrun"
|
|
newline
|
|
bitfld.long 0x00 29. " TXFULL , Transmit data buffer full" "Not full,Full"
|
|
bitfld.long 0x00 28. " BITERR , Bit error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 27. " DESYNC , Desynchronization of slave device" "No,Yes"
|
|
bitfld.long 0x00 26. " PARITYERR , Parity error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 25. " TIMEOUT , Time-out because of non-activation of ENA pin" "No timeout,Timeout"
|
|
bitfld.long 0x00 24. " DLENERR , Data length error flag" "No,Yes"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " LCSNR , Last chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " RXDATA , SPI receive data"
|
|
rgroup.long (0xB8+0x200)++0x03
|
|
line.long 0x00 "RXRAM, Multi-buffer RAM Receive Buffer Register 46"
|
|
bitfld.long 0x00 31. " RXEMPTY , Receive data buffer empty" "Not empty,Empty"
|
|
bitfld.long 0x00 30. " RXOVR , Receive data buffer overrun" "No overrun,Overrun"
|
|
newline
|
|
bitfld.long 0x00 29. " TXFULL , Transmit data buffer full" "Not full,Full"
|
|
bitfld.long 0x00 28. " BITERR , Bit error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 27. " DESYNC , Desynchronization of slave device" "No,Yes"
|
|
bitfld.long 0x00 26. " PARITYERR , Parity error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 25. " TIMEOUT , Time-out because of non-activation of ENA pin" "No timeout,Timeout"
|
|
bitfld.long 0x00 24. " DLENERR , Data length error flag" "No,Yes"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " LCSNR , Last chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " RXDATA , SPI receive data"
|
|
rgroup.long (0xBC+0x200)++0x03
|
|
line.long 0x00 "RXRAM, Multi-buffer RAM Receive Buffer Register 47"
|
|
bitfld.long 0x00 31. " RXEMPTY , Receive data buffer empty" "Not empty,Empty"
|
|
bitfld.long 0x00 30. " RXOVR , Receive data buffer overrun" "No overrun,Overrun"
|
|
newline
|
|
bitfld.long 0x00 29. " TXFULL , Transmit data buffer full" "Not full,Full"
|
|
bitfld.long 0x00 28. " BITERR , Bit error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 27. " DESYNC , Desynchronization of slave device" "No,Yes"
|
|
bitfld.long 0x00 26. " PARITYERR , Parity error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 25. " TIMEOUT , Time-out because of non-activation of ENA pin" "No timeout,Timeout"
|
|
bitfld.long 0x00 24. " DLENERR , Data length error flag" "No,Yes"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " LCSNR , Last chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " RXDATA , SPI receive data"
|
|
rgroup.long (0xC0+0x200)++0x03
|
|
line.long 0x00 "RXRAM, Multi-buffer RAM Receive Buffer Register 48"
|
|
bitfld.long 0x00 31. " RXEMPTY , Receive data buffer empty" "Not empty,Empty"
|
|
bitfld.long 0x00 30. " RXOVR , Receive data buffer overrun" "No overrun,Overrun"
|
|
newline
|
|
bitfld.long 0x00 29. " TXFULL , Transmit data buffer full" "Not full,Full"
|
|
bitfld.long 0x00 28. " BITERR , Bit error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 27. " DESYNC , Desynchronization of slave device" "No,Yes"
|
|
bitfld.long 0x00 26. " PARITYERR , Parity error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 25. " TIMEOUT , Time-out because of non-activation of ENA pin" "No timeout,Timeout"
|
|
bitfld.long 0x00 24. " DLENERR , Data length error flag" "No,Yes"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " LCSNR , Last chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " RXDATA , SPI receive data"
|
|
rgroup.long (0xC4+0x200)++0x03
|
|
line.long 0x00 "RXRAM, Multi-buffer RAM Receive Buffer Register 49"
|
|
bitfld.long 0x00 31. " RXEMPTY , Receive data buffer empty" "Not empty,Empty"
|
|
bitfld.long 0x00 30. " RXOVR , Receive data buffer overrun" "No overrun,Overrun"
|
|
newline
|
|
bitfld.long 0x00 29. " TXFULL , Transmit data buffer full" "Not full,Full"
|
|
bitfld.long 0x00 28. " BITERR , Bit error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 27. " DESYNC , Desynchronization of slave device" "No,Yes"
|
|
bitfld.long 0x00 26. " PARITYERR , Parity error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 25. " TIMEOUT , Time-out because of non-activation of ENA pin" "No timeout,Timeout"
|
|
bitfld.long 0x00 24. " DLENERR , Data length error flag" "No,Yes"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " LCSNR , Last chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " RXDATA , SPI receive data"
|
|
rgroup.long (0xC8+0x200)++0x03
|
|
line.long 0x00 "RXRAM, Multi-buffer RAM Receive Buffer Register 50"
|
|
bitfld.long 0x00 31. " RXEMPTY , Receive data buffer empty" "Not empty,Empty"
|
|
bitfld.long 0x00 30. " RXOVR , Receive data buffer overrun" "No overrun,Overrun"
|
|
newline
|
|
bitfld.long 0x00 29. " TXFULL , Transmit data buffer full" "Not full,Full"
|
|
bitfld.long 0x00 28. " BITERR , Bit error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 27. " DESYNC , Desynchronization of slave device" "No,Yes"
|
|
bitfld.long 0x00 26. " PARITYERR , Parity error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 25. " TIMEOUT , Time-out because of non-activation of ENA pin" "No timeout,Timeout"
|
|
bitfld.long 0x00 24. " DLENERR , Data length error flag" "No,Yes"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " LCSNR , Last chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " RXDATA , SPI receive data"
|
|
rgroup.long (0xCC+0x200)++0x03
|
|
line.long 0x00 "RXRAM, Multi-buffer RAM Receive Buffer Register 51"
|
|
bitfld.long 0x00 31. " RXEMPTY , Receive data buffer empty" "Not empty,Empty"
|
|
bitfld.long 0x00 30. " RXOVR , Receive data buffer overrun" "No overrun,Overrun"
|
|
newline
|
|
bitfld.long 0x00 29. " TXFULL , Transmit data buffer full" "Not full,Full"
|
|
bitfld.long 0x00 28. " BITERR , Bit error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 27. " DESYNC , Desynchronization of slave device" "No,Yes"
|
|
bitfld.long 0x00 26. " PARITYERR , Parity error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 25. " TIMEOUT , Time-out because of non-activation of ENA pin" "No timeout,Timeout"
|
|
bitfld.long 0x00 24. " DLENERR , Data length error flag" "No,Yes"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " LCSNR , Last chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " RXDATA , SPI receive data"
|
|
rgroup.long (0xD0+0x200)++0x03
|
|
line.long 0x00 "RXRAM, Multi-buffer RAM Receive Buffer Register 52"
|
|
bitfld.long 0x00 31. " RXEMPTY , Receive data buffer empty" "Not empty,Empty"
|
|
bitfld.long 0x00 30. " RXOVR , Receive data buffer overrun" "No overrun,Overrun"
|
|
newline
|
|
bitfld.long 0x00 29. " TXFULL , Transmit data buffer full" "Not full,Full"
|
|
bitfld.long 0x00 28. " BITERR , Bit error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 27. " DESYNC , Desynchronization of slave device" "No,Yes"
|
|
bitfld.long 0x00 26. " PARITYERR , Parity error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 25. " TIMEOUT , Time-out because of non-activation of ENA pin" "No timeout,Timeout"
|
|
bitfld.long 0x00 24. " DLENERR , Data length error flag" "No,Yes"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " LCSNR , Last chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " RXDATA , SPI receive data"
|
|
rgroup.long (0xD4+0x200)++0x03
|
|
line.long 0x00 "RXRAM, Multi-buffer RAM Receive Buffer Register 53"
|
|
bitfld.long 0x00 31. " RXEMPTY , Receive data buffer empty" "Not empty,Empty"
|
|
bitfld.long 0x00 30. " RXOVR , Receive data buffer overrun" "No overrun,Overrun"
|
|
newline
|
|
bitfld.long 0x00 29. " TXFULL , Transmit data buffer full" "Not full,Full"
|
|
bitfld.long 0x00 28. " BITERR , Bit error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 27. " DESYNC , Desynchronization of slave device" "No,Yes"
|
|
bitfld.long 0x00 26. " PARITYERR , Parity error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 25. " TIMEOUT , Time-out because of non-activation of ENA pin" "No timeout,Timeout"
|
|
bitfld.long 0x00 24. " DLENERR , Data length error flag" "No,Yes"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " LCSNR , Last chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " RXDATA , SPI receive data"
|
|
rgroup.long (0xD8+0x200)++0x03
|
|
line.long 0x00 "RXRAM, Multi-buffer RAM Receive Buffer Register 54"
|
|
bitfld.long 0x00 31. " RXEMPTY , Receive data buffer empty" "Not empty,Empty"
|
|
bitfld.long 0x00 30. " RXOVR , Receive data buffer overrun" "No overrun,Overrun"
|
|
newline
|
|
bitfld.long 0x00 29. " TXFULL , Transmit data buffer full" "Not full,Full"
|
|
bitfld.long 0x00 28. " BITERR , Bit error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 27. " DESYNC , Desynchronization of slave device" "No,Yes"
|
|
bitfld.long 0x00 26. " PARITYERR , Parity error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 25. " TIMEOUT , Time-out because of non-activation of ENA pin" "No timeout,Timeout"
|
|
bitfld.long 0x00 24. " DLENERR , Data length error flag" "No,Yes"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " LCSNR , Last chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " RXDATA , SPI receive data"
|
|
rgroup.long (0xDC+0x200)++0x03
|
|
line.long 0x00 "RXRAM, Multi-buffer RAM Receive Buffer Register 55"
|
|
bitfld.long 0x00 31. " RXEMPTY , Receive data buffer empty" "Not empty,Empty"
|
|
bitfld.long 0x00 30. " RXOVR , Receive data buffer overrun" "No overrun,Overrun"
|
|
newline
|
|
bitfld.long 0x00 29. " TXFULL , Transmit data buffer full" "Not full,Full"
|
|
bitfld.long 0x00 28. " BITERR , Bit error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 27. " DESYNC , Desynchronization of slave device" "No,Yes"
|
|
bitfld.long 0x00 26. " PARITYERR , Parity error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 25. " TIMEOUT , Time-out because of non-activation of ENA pin" "No timeout,Timeout"
|
|
bitfld.long 0x00 24. " DLENERR , Data length error flag" "No,Yes"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " LCSNR , Last chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " RXDATA , SPI receive data"
|
|
rgroup.long (0xE0+0x200)++0x03
|
|
line.long 0x00 "RXRAM, Multi-buffer RAM Receive Buffer Register 56"
|
|
bitfld.long 0x00 31. " RXEMPTY , Receive data buffer empty" "Not empty,Empty"
|
|
bitfld.long 0x00 30. " RXOVR , Receive data buffer overrun" "No overrun,Overrun"
|
|
newline
|
|
bitfld.long 0x00 29. " TXFULL , Transmit data buffer full" "Not full,Full"
|
|
bitfld.long 0x00 28. " BITERR , Bit error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 27. " DESYNC , Desynchronization of slave device" "No,Yes"
|
|
bitfld.long 0x00 26. " PARITYERR , Parity error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 25. " TIMEOUT , Time-out because of non-activation of ENA pin" "No timeout,Timeout"
|
|
bitfld.long 0x00 24. " DLENERR , Data length error flag" "No,Yes"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " LCSNR , Last chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " RXDATA , SPI receive data"
|
|
rgroup.long (0xE4+0x200)++0x03
|
|
line.long 0x00 "RXRAM, Multi-buffer RAM Receive Buffer Register 57"
|
|
bitfld.long 0x00 31. " RXEMPTY , Receive data buffer empty" "Not empty,Empty"
|
|
bitfld.long 0x00 30. " RXOVR , Receive data buffer overrun" "No overrun,Overrun"
|
|
newline
|
|
bitfld.long 0x00 29. " TXFULL , Transmit data buffer full" "Not full,Full"
|
|
bitfld.long 0x00 28. " BITERR , Bit error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 27. " DESYNC , Desynchronization of slave device" "No,Yes"
|
|
bitfld.long 0x00 26. " PARITYERR , Parity error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 25. " TIMEOUT , Time-out because of non-activation of ENA pin" "No timeout,Timeout"
|
|
bitfld.long 0x00 24. " DLENERR , Data length error flag" "No,Yes"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " LCSNR , Last chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " RXDATA , SPI receive data"
|
|
rgroup.long (0xE8+0x200)++0x03
|
|
line.long 0x00 "RXRAM, Multi-buffer RAM Receive Buffer Register 58"
|
|
bitfld.long 0x00 31. " RXEMPTY , Receive data buffer empty" "Not empty,Empty"
|
|
bitfld.long 0x00 30. " RXOVR , Receive data buffer overrun" "No overrun,Overrun"
|
|
newline
|
|
bitfld.long 0x00 29. " TXFULL , Transmit data buffer full" "Not full,Full"
|
|
bitfld.long 0x00 28. " BITERR , Bit error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 27. " DESYNC , Desynchronization of slave device" "No,Yes"
|
|
bitfld.long 0x00 26. " PARITYERR , Parity error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 25. " TIMEOUT , Time-out because of non-activation of ENA pin" "No timeout,Timeout"
|
|
bitfld.long 0x00 24. " DLENERR , Data length error flag" "No,Yes"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " LCSNR , Last chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " RXDATA , SPI receive data"
|
|
rgroup.long (0xEC+0x200)++0x03
|
|
line.long 0x00 "RXRAM, Multi-buffer RAM Receive Buffer Register 59"
|
|
bitfld.long 0x00 31. " RXEMPTY , Receive data buffer empty" "Not empty,Empty"
|
|
bitfld.long 0x00 30. " RXOVR , Receive data buffer overrun" "No overrun,Overrun"
|
|
newline
|
|
bitfld.long 0x00 29. " TXFULL , Transmit data buffer full" "Not full,Full"
|
|
bitfld.long 0x00 28. " BITERR , Bit error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 27. " DESYNC , Desynchronization of slave device" "No,Yes"
|
|
bitfld.long 0x00 26. " PARITYERR , Parity error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 25. " TIMEOUT , Time-out because of non-activation of ENA pin" "No timeout,Timeout"
|
|
bitfld.long 0x00 24. " DLENERR , Data length error flag" "No,Yes"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " LCSNR , Last chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " RXDATA , SPI receive data"
|
|
rgroup.long (0xF0+0x200)++0x03
|
|
line.long 0x00 "RXRAM, Multi-buffer RAM Receive Buffer Register 60"
|
|
bitfld.long 0x00 31. " RXEMPTY , Receive data buffer empty" "Not empty,Empty"
|
|
bitfld.long 0x00 30. " RXOVR , Receive data buffer overrun" "No overrun,Overrun"
|
|
newline
|
|
bitfld.long 0x00 29. " TXFULL , Transmit data buffer full" "Not full,Full"
|
|
bitfld.long 0x00 28. " BITERR , Bit error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 27. " DESYNC , Desynchronization of slave device" "No,Yes"
|
|
bitfld.long 0x00 26. " PARITYERR , Parity error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 25. " TIMEOUT , Time-out because of non-activation of ENA pin" "No timeout,Timeout"
|
|
bitfld.long 0x00 24. " DLENERR , Data length error flag" "No,Yes"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " LCSNR , Last chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " RXDATA , SPI receive data"
|
|
rgroup.long (0xF4+0x200)++0x03
|
|
line.long 0x00 "RXRAM, Multi-buffer RAM Receive Buffer Register 61"
|
|
bitfld.long 0x00 31. " RXEMPTY , Receive data buffer empty" "Not empty,Empty"
|
|
bitfld.long 0x00 30. " RXOVR , Receive data buffer overrun" "No overrun,Overrun"
|
|
newline
|
|
bitfld.long 0x00 29. " TXFULL , Transmit data buffer full" "Not full,Full"
|
|
bitfld.long 0x00 28. " BITERR , Bit error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 27. " DESYNC , Desynchronization of slave device" "No,Yes"
|
|
bitfld.long 0x00 26. " PARITYERR , Parity error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 25. " TIMEOUT , Time-out because of non-activation of ENA pin" "No timeout,Timeout"
|
|
bitfld.long 0x00 24. " DLENERR , Data length error flag" "No,Yes"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " LCSNR , Last chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " RXDATA , SPI receive data"
|
|
rgroup.long (0xF8+0x200)++0x03
|
|
line.long 0x00 "RXRAM, Multi-buffer RAM Receive Buffer Register 62"
|
|
bitfld.long 0x00 31. " RXEMPTY , Receive data buffer empty" "Not empty,Empty"
|
|
bitfld.long 0x00 30. " RXOVR , Receive data buffer overrun" "No overrun,Overrun"
|
|
newline
|
|
bitfld.long 0x00 29. " TXFULL , Transmit data buffer full" "Not full,Full"
|
|
bitfld.long 0x00 28. " BITERR , Bit error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 27. " DESYNC , Desynchronization of slave device" "No,Yes"
|
|
bitfld.long 0x00 26. " PARITYERR , Parity error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 25. " TIMEOUT , Time-out because of non-activation of ENA pin" "No timeout,Timeout"
|
|
bitfld.long 0x00 24. " DLENERR , Data length error flag" "No,Yes"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " LCSNR , Last chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " RXDATA , SPI receive data"
|
|
rgroup.long (0xFC+0x200)++0x03
|
|
line.long 0x00 "RXRAM, Multi-buffer RAM Receive Buffer Register 63"
|
|
bitfld.long 0x00 31. " RXEMPTY , Receive data buffer empty" "Not empty,Empty"
|
|
bitfld.long 0x00 30. " RXOVR , Receive data buffer overrun" "No overrun,Overrun"
|
|
newline
|
|
bitfld.long 0x00 29. " TXFULL , Transmit data buffer full" "Not full,Full"
|
|
bitfld.long 0x00 28. " BITERR , Bit error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 27. " DESYNC , Desynchronization of slave device" "No,Yes"
|
|
bitfld.long 0x00 26. " PARITYERR , Parity error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 25. " TIMEOUT , Time-out because of non-activation of ENA pin" "No timeout,Timeout"
|
|
bitfld.long 0x00 24. " DLENERR , Data length error flag" "No,Yes"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " LCSNR , Last chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " RXDATA , SPI receive data"
|
|
rgroup.long (0x100+0x200)++0x03
|
|
line.long 0x00 "RXRAM, Multi-buffer RAM Receive Buffer Register 64"
|
|
bitfld.long 0x00 31. " RXEMPTY , Receive data buffer empty" "Not empty,Empty"
|
|
bitfld.long 0x00 30. " RXOVR , Receive data buffer overrun" "No overrun,Overrun"
|
|
newline
|
|
bitfld.long 0x00 29. " TXFULL , Transmit data buffer full" "Not full,Full"
|
|
bitfld.long 0x00 28. " BITERR , Bit error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 27. " DESYNC , Desynchronization of slave device" "No,Yes"
|
|
bitfld.long 0x00 26. " PARITYERR , Parity error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 25. " TIMEOUT , Time-out because of non-activation of ENA pin" "No timeout,Timeout"
|
|
bitfld.long 0x00 24. " DLENERR , Data length error flag" "No,Yes"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " LCSNR , Last chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " RXDATA , SPI receive data"
|
|
rgroup.long (0x104+0x200)++0x03
|
|
line.long 0x00 "RXRAM, Multi-buffer RAM Receive Buffer Register 65"
|
|
bitfld.long 0x00 31. " RXEMPTY , Receive data buffer empty" "Not empty,Empty"
|
|
bitfld.long 0x00 30. " RXOVR , Receive data buffer overrun" "No overrun,Overrun"
|
|
newline
|
|
bitfld.long 0x00 29. " TXFULL , Transmit data buffer full" "Not full,Full"
|
|
bitfld.long 0x00 28. " BITERR , Bit error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 27. " DESYNC , Desynchronization of slave device" "No,Yes"
|
|
bitfld.long 0x00 26. " PARITYERR , Parity error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 25. " TIMEOUT , Time-out because of non-activation of ENA pin" "No timeout,Timeout"
|
|
bitfld.long 0x00 24. " DLENERR , Data length error flag" "No,Yes"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " LCSNR , Last chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " RXDATA , SPI receive data"
|
|
rgroup.long (0x108+0x200)++0x03
|
|
line.long 0x00 "RXRAM, Multi-buffer RAM Receive Buffer Register 66"
|
|
bitfld.long 0x00 31. " RXEMPTY , Receive data buffer empty" "Not empty,Empty"
|
|
bitfld.long 0x00 30. " RXOVR , Receive data buffer overrun" "No overrun,Overrun"
|
|
newline
|
|
bitfld.long 0x00 29. " TXFULL , Transmit data buffer full" "Not full,Full"
|
|
bitfld.long 0x00 28. " BITERR , Bit error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 27. " DESYNC , Desynchronization of slave device" "No,Yes"
|
|
bitfld.long 0x00 26. " PARITYERR , Parity error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 25. " TIMEOUT , Time-out because of non-activation of ENA pin" "No timeout,Timeout"
|
|
bitfld.long 0x00 24. " DLENERR , Data length error flag" "No,Yes"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " LCSNR , Last chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " RXDATA , SPI receive data"
|
|
rgroup.long (0x10C+0x200)++0x03
|
|
line.long 0x00 "RXRAM, Multi-buffer RAM Receive Buffer Register 67"
|
|
bitfld.long 0x00 31. " RXEMPTY , Receive data buffer empty" "Not empty,Empty"
|
|
bitfld.long 0x00 30. " RXOVR , Receive data buffer overrun" "No overrun,Overrun"
|
|
newline
|
|
bitfld.long 0x00 29. " TXFULL , Transmit data buffer full" "Not full,Full"
|
|
bitfld.long 0x00 28. " BITERR , Bit error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 27. " DESYNC , Desynchronization of slave device" "No,Yes"
|
|
bitfld.long 0x00 26. " PARITYERR , Parity error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 25. " TIMEOUT , Time-out because of non-activation of ENA pin" "No timeout,Timeout"
|
|
bitfld.long 0x00 24. " DLENERR , Data length error flag" "No,Yes"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " LCSNR , Last chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " RXDATA , SPI receive data"
|
|
rgroup.long (0x110+0x200)++0x03
|
|
line.long 0x00 "RXRAM, Multi-buffer RAM Receive Buffer Register 68"
|
|
bitfld.long 0x00 31. " RXEMPTY , Receive data buffer empty" "Not empty,Empty"
|
|
bitfld.long 0x00 30. " RXOVR , Receive data buffer overrun" "No overrun,Overrun"
|
|
newline
|
|
bitfld.long 0x00 29. " TXFULL , Transmit data buffer full" "Not full,Full"
|
|
bitfld.long 0x00 28. " BITERR , Bit error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 27. " DESYNC , Desynchronization of slave device" "No,Yes"
|
|
bitfld.long 0x00 26. " PARITYERR , Parity error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 25. " TIMEOUT , Time-out because of non-activation of ENA pin" "No timeout,Timeout"
|
|
bitfld.long 0x00 24. " DLENERR , Data length error flag" "No,Yes"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " LCSNR , Last chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " RXDATA , SPI receive data"
|
|
rgroup.long (0x114+0x200)++0x03
|
|
line.long 0x00 "RXRAM, Multi-buffer RAM Receive Buffer Register 69"
|
|
bitfld.long 0x00 31. " RXEMPTY , Receive data buffer empty" "Not empty,Empty"
|
|
bitfld.long 0x00 30. " RXOVR , Receive data buffer overrun" "No overrun,Overrun"
|
|
newline
|
|
bitfld.long 0x00 29. " TXFULL , Transmit data buffer full" "Not full,Full"
|
|
bitfld.long 0x00 28. " BITERR , Bit error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 27. " DESYNC , Desynchronization of slave device" "No,Yes"
|
|
bitfld.long 0x00 26. " PARITYERR , Parity error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 25. " TIMEOUT , Time-out because of non-activation of ENA pin" "No timeout,Timeout"
|
|
bitfld.long 0x00 24. " DLENERR , Data length error flag" "No,Yes"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " LCSNR , Last chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " RXDATA , SPI receive data"
|
|
rgroup.long (0x118+0x200)++0x03
|
|
line.long 0x00 "RXRAM, Multi-buffer RAM Receive Buffer Register 70"
|
|
bitfld.long 0x00 31. " RXEMPTY , Receive data buffer empty" "Not empty,Empty"
|
|
bitfld.long 0x00 30. " RXOVR , Receive data buffer overrun" "No overrun,Overrun"
|
|
newline
|
|
bitfld.long 0x00 29. " TXFULL , Transmit data buffer full" "Not full,Full"
|
|
bitfld.long 0x00 28. " BITERR , Bit error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 27. " DESYNC , Desynchronization of slave device" "No,Yes"
|
|
bitfld.long 0x00 26. " PARITYERR , Parity error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 25. " TIMEOUT , Time-out because of non-activation of ENA pin" "No timeout,Timeout"
|
|
bitfld.long 0x00 24. " DLENERR , Data length error flag" "No,Yes"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " LCSNR , Last chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " RXDATA , SPI receive data"
|
|
rgroup.long (0x11C+0x200)++0x03
|
|
line.long 0x00 "RXRAM, Multi-buffer RAM Receive Buffer Register 71"
|
|
bitfld.long 0x00 31. " RXEMPTY , Receive data buffer empty" "Not empty,Empty"
|
|
bitfld.long 0x00 30. " RXOVR , Receive data buffer overrun" "No overrun,Overrun"
|
|
newline
|
|
bitfld.long 0x00 29. " TXFULL , Transmit data buffer full" "Not full,Full"
|
|
bitfld.long 0x00 28. " BITERR , Bit error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 27. " DESYNC , Desynchronization of slave device" "No,Yes"
|
|
bitfld.long 0x00 26. " PARITYERR , Parity error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 25. " TIMEOUT , Time-out because of non-activation of ENA pin" "No timeout,Timeout"
|
|
bitfld.long 0x00 24. " DLENERR , Data length error flag" "No,Yes"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " LCSNR , Last chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " RXDATA , SPI receive data"
|
|
rgroup.long (0x120+0x200)++0x03
|
|
line.long 0x00 "RXRAM, Multi-buffer RAM Receive Buffer Register 72"
|
|
bitfld.long 0x00 31. " RXEMPTY , Receive data buffer empty" "Not empty,Empty"
|
|
bitfld.long 0x00 30. " RXOVR , Receive data buffer overrun" "No overrun,Overrun"
|
|
newline
|
|
bitfld.long 0x00 29. " TXFULL , Transmit data buffer full" "Not full,Full"
|
|
bitfld.long 0x00 28. " BITERR , Bit error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 27. " DESYNC , Desynchronization of slave device" "No,Yes"
|
|
bitfld.long 0x00 26. " PARITYERR , Parity error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 25. " TIMEOUT , Time-out because of non-activation of ENA pin" "No timeout,Timeout"
|
|
bitfld.long 0x00 24. " DLENERR , Data length error flag" "No,Yes"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " LCSNR , Last chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " RXDATA , SPI receive data"
|
|
rgroup.long (0x124+0x200)++0x03
|
|
line.long 0x00 "RXRAM, Multi-buffer RAM Receive Buffer Register 73"
|
|
bitfld.long 0x00 31. " RXEMPTY , Receive data buffer empty" "Not empty,Empty"
|
|
bitfld.long 0x00 30. " RXOVR , Receive data buffer overrun" "No overrun,Overrun"
|
|
newline
|
|
bitfld.long 0x00 29. " TXFULL , Transmit data buffer full" "Not full,Full"
|
|
bitfld.long 0x00 28. " BITERR , Bit error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 27. " DESYNC , Desynchronization of slave device" "No,Yes"
|
|
bitfld.long 0x00 26. " PARITYERR , Parity error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 25. " TIMEOUT , Time-out because of non-activation of ENA pin" "No timeout,Timeout"
|
|
bitfld.long 0x00 24. " DLENERR , Data length error flag" "No,Yes"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " LCSNR , Last chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " RXDATA , SPI receive data"
|
|
rgroup.long (0x128+0x200)++0x03
|
|
line.long 0x00 "RXRAM, Multi-buffer RAM Receive Buffer Register 74"
|
|
bitfld.long 0x00 31. " RXEMPTY , Receive data buffer empty" "Not empty,Empty"
|
|
bitfld.long 0x00 30. " RXOVR , Receive data buffer overrun" "No overrun,Overrun"
|
|
newline
|
|
bitfld.long 0x00 29. " TXFULL , Transmit data buffer full" "Not full,Full"
|
|
bitfld.long 0x00 28. " BITERR , Bit error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 27. " DESYNC , Desynchronization of slave device" "No,Yes"
|
|
bitfld.long 0x00 26. " PARITYERR , Parity error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 25. " TIMEOUT , Time-out because of non-activation of ENA pin" "No timeout,Timeout"
|
|
bitfld.long 0x00 24. " DLENERR , Data length error flag" "No,Yes"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " LCSNR , Last chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " RXDATA , SPI receive data"
|
|
rgroup.long (0x12C+0x200)++0x03
|
|
line.long 0x00 "RXRAM, Multi-buffer RAM Receive Buffer Register 75"
|
|
bitfld.long 0x00 31. " RXEMPTY , Receive data buffer empty" "Not empty,Empty"
|
|
bitfld.long 0x00 30. " RXOVR , Receive data buffer overrun" "No overrun,Overrun"
|
|
newline
|
|
bitfld.long 0x00 29. " TXFULL , Transmit data buffer full" "Not full,Full"
|
|
bitfld.long 0x00 28. " BITERR , Bit error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 27. " DESYNC , Desynchronization of slave device" "No,Yes"
|
|
bitfld.long 0x00 26. " PARITYERR , Parity error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 25. " TIMEOUT , Time-out because of non-activation of ENA pin" "No timeout,Timeout"
|
|
bitfld.long 0x00 24. " DLENERR , Data length error flag" "No,Yes"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " LCSNR , Last chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " RXDATA , SPI receive data"
|
|
rgroup.long (0x130+0x200)++0x03
|
|
line.long 0x00 "RXRAM, Multi-buffer RAM Receive Buffer Register 76"
|
|
bitfld.long 0x00 31. " RXEMPTY , Receive data buffer empty" "Not empty,Empty"
|
|
bitfld.long 0x00 30. " RXOVR , Receive data buffer overrun" "No overrun,Overrun"
|
|
newline
|
|
bitfld.long 0x00 29. " TXFULL , Transmit data buffer full" "Not full,Full"
|
|
bitfld.long 0x00 28. " BITERR , Bit error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 27. " DESYNC , Desynchronization of slave device" "No,Yes"
|
|
bitfld.long 0x00 26. " PARITYERR , Parity error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 25. " TIMEOUT , Time-out because of non-activation of ENA pin" "No timeout,Timeout"
|
|
bitfld.long 0x00 24. " DLENERR , Data length error flag" "No,Yes"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " LCSNR , Last chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " RXDATA , SPI receive data"
|
|
rgroup.long (0x134+0x200)++0x03
|
|
line.long 0x00 "RXRAM, Multi-buffer RAM Receive Buffer Register 77"
|
|
bitfld.long 0x00 31. " RXEMPTY , Receive data buffer empty" "Not empty,Empty"
|
|
bitfld.long 0x00 30. " RXOVR , Receive data buffer overrun" "No overrun,Overrun"
|
|
newline
|
|
bitfld.long 0x00 29. " TXFULL , Transmit data buffer full" "Not full,Full"
|
|
bitfld.long 0x00 28. " BITERR , Bit error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 27. " DESYNC , Desynchronization of slave device" "No,Yes"
|
|
bitfld.long 0x00 26. " PARITYERR , Parity error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 25. " TIMEOUT , Time-out because of non-activation of ENA pin" "No timeout,Timeout"
|
|
bitfld.long 0x00 24. " DLENERR , Data length error flag" "No,Yes"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " LCSNR , Last chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " RXDATA , SPI receive data"
|
|
rgroup.long (0x138+0x200)++0x03
|
|
line.long 0x00 "RXRAM, Multi-buffer RAM Receive Buffer Register 78"
|
|
bitfld.long 0x00 31. " RXEMPTY , Receive data buffer empty" "Not empty,Empty"
|
|
bitfld.long 0x00 30. " RXOVR , Receive data buffer overrun" "No overrun,Overrun"
|
|
newline
|
|
bitfld.long 0x00 29. " TXFULL , Transmit data buffer full" "Not full,Full"
|
|
bitfld.long 0x00 28. " BITERR , Bit error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 27. " DESYNC , Desynchronization of slave device" "No,Yes"
|
|
bitfld.long 0x00 26. " PARITYERR , Parity error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 25. " TIMEOUT , Time-out because of non-activation of ENA pin" "No timeout,Timeout"
|
|
bitfld.long 0x00 24. " DLENERR , Data length error flag" "No,Yes"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " LCSNR , Last chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " RXDATA , SPI receive data"
|
|
rgroup.long (0x13C+0x200)++0x03
|
|
line.long 0x00 "RXRAM, Multi-buffer RAM Receive Buffer Register 79"
|
|
bitfld.long 0x00 31. " RXEMPTY , Receive data buffer empty" "Not empty,Empty"
|
|
bitfld.long 0x00 30. " RXOVR , Receive data buffer overrun" "No overrun,Overrun"
|
|
newline
|
|
bitfld.long 0x00 29. " TXFULL , Transmit data buffer full" "Not full,Full"
|
|
bitfld.long 0x00 28. " BITERR , Bit error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 27. " DESYNC , Desynchronization of slave device" "No,Yes"
|
|
bitfld.long 0x00 26. " PARITYERR , Parity error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 25. " TIMEOUT , Time-out because of non-activation of ENA pin" "No timeout,Timeout"
|
|
bitfld.long 0x00 24. " DLENERR , Data length error flag" "No,Yes"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " LCSNR , Last chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " RXDATA , SPI receive data"
|
|
else
|
|
tree "Transmit Buffers"
|
|
group.long 0x0++0x03
|
|
line.long 0x00 "BUFFER0,Buffer 0 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x4++0x03
|
|
line.long 0x00 "BUFFER1,Buffer 1 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x8++0x03
|
|
line.long 0x00 "BUFFER2,Buffer 2 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0xC++0x03
|
|
line.long 0x00 "BUFFER3,Buffer 3 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "BUFFER4,Buffer 4 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "BUFFER5,Buffer 5 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "BUFFER6,Buffer 6 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "BUFFER7,Buffer 7 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "BUFFER8,Buffer 8 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "BUFFER9,Buffer 9 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "BUFFER10,Buffer 10 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "BUFFER11,Buffer 11 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "BUFFER12,Buffer 12 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x34++0x03
|
|
line.long 0x00 "BUFFER13,Buffer 13 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x38++0x03
|
|
line.long 0x00 "BUFFER14,Buffer 14 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x3C++0x03
|
|
line.long 0x00 "BUFFER15,Buffer 15 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "BUFFER16,Buffer 16 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x44++0x03
|
|
line.long 0x00 "BUFFER17,Buffer 17 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x48++0x03
|
|
line.long 0x00 "BUFFER18,Buffer 18 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x4C++0x03
|
|
line.long 0x00 "BUFFER19,Buffer 19 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x50++0x03
|
|
line.long 0x00 "BUFFER20,Buffer 20 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x54++0x03
|
|
line.long 0x00 "BUFFER21,Buffer 21 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x58++0x03
|
|
line.long 0x00 "BUFFER22,Buffer 22 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x5C++0x03
|
|
line.long 0x00 "BUFFER23,Buffer 23 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x60++0x03
|
|
line.long 0x00 "BUFFER24,Buffer 24 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x64++0x03
|
|
line.long 0x00 "BUFFER25,Buffer 25 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x68++0x03
|
|
line.long 0x00 "BUFFER26,Buffer 26 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x6C++0x03
|
|
line.long 0x00 "BUFFER27,Buffer 27 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x70++0x03
|
|
line.long 0x00 "BUFFER28,Buffer 28 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x74++0x03
|
|
line.long 0x00 "BUFFER29,Buffer 29 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x78++0x03
|
|
line.long 0x00 "BUFFER30,Buffer 30 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x7C++0x03
|
|
line.long 0x00 "BUFFER31,Buffer 31 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x80++0x03
|
|
line.long 0x00 "BUFFER32,Buffer 32 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x84++0x03
|
|
line.long 0x00 "BUFFER33,Buffer 33 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x88++0x03
|
|
line.long 0x00 "BUFFER34,Buffer 34 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x8C++0x03
|
|
line.long 0x00 "BUFFER35,Buffer 35 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x90++0x03
|
|
line.long 0x00 "BUFFER36,Buffer 36 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x94++0x03
|
|
line.long 0x00 "BUFFER37,Buffer 37 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x98++0x03
|
|
line.long 0x00 "BUFFER38,Buffer 38 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x9C++0x03
|
|
line.long 0x00 "BUFFER39,Buffer 39 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0xA0++0x03
|
|
line.long 0x00 "BUFFER40,Buffer 40 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0xA4++0x03
|
|
line.long 0x00 "BUFFER41,Buffer 41 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0xA8++0x03
|
|
line.long 0x00 "BUFFER42,Buffer 42 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0xAC++0x03
|
|
line.long 0x00 "BUFFER43,Buffer 43 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0xB0++0x03
|
|
line.long 0x00 "BUFFER44,Buffer 44 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0xB4++0x03
|
|
line.long 0x00 "BUFFER45,Buffer 45 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0xB8++0x03
|
|
line.long 0x00 "BUFFER46,Buffer 46 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0xBC++0x03
|
|
line.long 0x00 "BUFFER47,Buffer 47 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0xC0++0x03
|
|
line.long 0x00 "BUFFER48,Buffer 48 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0xC4++0x03
|
|
line.long 0x00 "BUFFER49,Buffer 49 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0xC8++0x03
|
|
line.long 0x00 "BUFFER50,Buffer 50 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0xCC++0x03
|
|
line.long 0x00 "BUFFER51,Buffer 51 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0xD0++0x03
|
|
line.long 0x00 "BUFFER52,Buffer 52 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0xD4++0x03
|
|
line.long 0x00 "BUFFER53,Buffer 53 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0xD8++0x03
|
|
line.long 0x00 "BUFFER54,Buffer 54 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0xDC++0x03
|
|
line.long 0x00 "BUFFER55,Buffer 55 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0xE0++0x03
|
|
line.long 0x00 "BUFFER56,Buffer 56 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0xE4++0x03
|
|
line.long 0x00 "BUFFER57,Buffer 57 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0xE8++0x03
|
|
line.long 0x00 "BUFFER58,Buffer 58 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0xEC++0x03
|
|
line.long 0x00 "BUFFER59,Buffer 59 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0xF0++0x03
|
|
line.long 0x00 "BUFFER60,Buffer 60 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0xF4++0x03
|
|
line.long 0x00 "BUFFER61,Buffer 61 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0xF8++0x03
|
|
line.long 0x00 "BUFFER62,Buffer 62 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0xFC++0x03
|
|
line.long 0x00 "BUFFER63,Buffer 63 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x100++0x03
|
|
line.long 0x00 "BUFFER64,Buffer 64 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x104++0x03
|
|
line.long 0x00 "BUFFER65,Buffer 65 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x108++0x03
|
|
line.long 0x00 "BUFFER66,Buffer 66 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x10C++0x03
|
|
line.long 0x00 "BUFFER67,Buffer 67 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x110++0x03
|
|
line.long 0x00 "BUFFER68,Buffer 68 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x114++0x03
|
|
line.long 0x00 "BUFFER69,Buffer 69 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x118++0x03
|
|
line.long 0x00 "BUFFER70,Buffer 70 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x11C++0x03
|
|
line.long 0x00 "BUFFER71,Buffer 71 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x120++0x03
|
|
line.long 0x00 "BUFFER72,Buffer 72 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x124++0x03
|
|
line.long 0x00 "BUFFER73,Buffer 73 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x128++0x03
|
|
line.long 0x00 "BUFFER74,Buffer 74 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x12C++0x03
|
|
line.long 0x00 "BUFFER75,Buffer 75 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x130++0x03
|
|
line.long 0x00 "BUFFER76,Buffer 76 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x134++0x03
|
|
line.long 0x00 "BUFFER77,Buffer 77 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x138++0x03
|
|
line.long 0x00 "BUFFER78,Buffer 78 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x13C++0x03
|
|
line.long 0x00 "BUFFER79,Buffer 79 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x140++0x03
|
|
line.long 0x00 "BUFFER80,Buffer 80 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x144++0x03
|
|
line.long 0x00 "BUFFER81,Buffer 81 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x148++0x03
|
|
line.long 0x00 "BUFFER82,Buffer 82 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x14C++0x03
|
|
line.long 0x00 "BUFFER83,Buffer 83 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x150++0x03
|
|
line.long 0x00 "BUFFER84,Buffer 84 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x154++0x03
|
|
line.long 0x00 "BUFFER85,Buffer 85 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x158++0x03
|
|
line.long 0x00 "BUFFER86,Buffer 86 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x15C++0x03
|
|
line.long 0x00 "BUFFER87,Buffer 87 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x160++0x03
|
|
line.long 0x00 "BUFFER88,Buffer 88 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x164++0x03
|
|
line.long 0x00 "BUFFER89,Buffer 89 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x168++0x03
|
|
line.long 0x00 "BUFFER90,Buffer 90 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x16C++0x03
|
|
line.long 0x00 "BUFFER91,Buffer 91 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x170++0x03
|
|
line.long 0x00 "BUFFER92,Buffer 92 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x174++0x03
|
|
line.long 0x00 "BUFFER93,Buffer 93 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x178++0x03
|
|
line.long 0x00 "BUFFER94,Buffer 94 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x17C++0x03
|
|
line.long 0x00 "BUFFER95,Buffer 95 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x180++0x03
|
|
line.long 0x00 "BUFFER96,Buffer 96 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x184++0x03
|
|
line.long 0x00 "BUFFER97,Buffer 97 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x188++0x03
|
|
line.long 0x00 "BUFFER98,Buffer 98 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x18C++0x03
|
|
line.long 0x00 "BUFFER99,Buffer 99 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x190++0x03
|
|
line.long 0x00 "BUFFER100,Buffer 100 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x194++0x03
|
|
line.long 0x00 "BUFFER101,Buffer 101 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x198++0x03
|
|
line.long 0x00 "BUFFER102,Buffer 102 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x19C++0x03
|
|
line.long 0x00 "BUFFER103,Buffer 103 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x1A0++0x03
|
|
line.long 0x00 "BUFFER104,Buffer 104 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x1A4++0x03
|
|
line.long 0x00 "BUFFER105,Buffer 105 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x1A8++0x03
|
|
line.long 0x00 "BUFFER106,Buffer 106 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x1AC++0x03
|
|
line.long 0x00 "BUFFER107,Buffer 107 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x1B0++0x03
|
|
line.long 0x00 "BUFFER108,Buffer 108 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x1B4++0x03
|
|
line.long 0x00 "BUFFER109,Buffer 109 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x1B8++0x03
|
|
line.long 0x00 "BUFFER110,Buffer 110 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x1BC++0x03
|
|
line.long 0x00 "BUFFER111,Buffer 111 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x1C0++0x03
|
|
line.long 0x00 "BUFFER112,Buffer 112 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x1C4++0x03
|
|
line.long 0x00 "BUFFER113,Buffer 113 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x1C8++0x03
|
|
line.long 0x00 "BUFFER114,Buffer 114 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x1CC++0x03
|
|
line.long 0x00 "BUFFER115,Buffer 115 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x1D0++0x03
|
|
line.long 0x00 "BUFFER116,Buffer 116 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x1D4++0x03
|
|
line.long 0x00 "BUFFER117,Buffer 117 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x1D8++0x03
|
|
line.long 0x00 "BUFFER118,Buffer 118 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x1DC++0x03
|
|
line.long 0x00 "BUFFER119,Buffer 119 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x1E0++0x03
|
|
line.long 0x00 "BUFFER120,Buffer 120 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x1E4++0x03
|
|
line.long 0x00 "BUFFER121,Buffer 121 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x1E8++0x03
|
|
line.long 0x00 "BUFFER122,Buffer 122 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x1EC++0x03
|
|
line.long 0x00 "BUFFER123,Buffer 123 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x1F0++0x03
|
|
line.long 0x00 "BUFFER124,Buffer 124 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x1F4++0x03
|
|
line.long 0x00 "BUFFER125,Buffer 125 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x1F8++0x03
|
|
line.long 0x00 "BUFFER126,Buffer 126 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x1FC++0x03
|
|
line.long 0x00 "BUFFER127,Buffer 127 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
tree.end
|
|
tree "Receive Buffers"
|
|
hgroup.long (0x0+0x200)++0x03
|
|
hide.long 0x00 "BUFFER0,Buffer 0 Register"
|
|
in
|
|
hgroup.long (0x4+0x200)++0x03
|
|
hide.long 0x00 "BUFFER1,Buffer 1 Register"
|
|
in
|
|
hgroup.long (0x8+0x200)++0x03
|
|
hide.long 0x00 "BUFFER2,Buffer 2 Register"
|
|
in
|
|
hgroup.long (0xC+0x200)++0x03
|
|
hide.long 0x00 "BUFFER3,Buffer 3 Register"
|
|
in
|
|
hgroup.long (0x10+0x200)++0x03
|
|
hide.long 0x00 "BUFFER4,Buffer 4 Register"
|
|
in
|
|
hgroup.long (0x14+0x200)++0x03
|
|
hide.long 0x00 "BUFFER5,Buffer 5 Register"
|
|
in
|
|
hgroup.long (0x18+0x200)++0x03
|
|
hide.long 0x00 "BUFFER6,Buffer 6 Register"
|
|
in
|
|
hgroup.long (0x1C+0x200)++0x03
|
|
hide.long 0x00 "BUFFER7,Buffer 7 Register"
|
|
in
|
|
hgroup.long (0x20+0x200)++0x03
|
|
hide.long 0x00 "BUFFER8,Buffer 8 Register"
|
|
in
|
|
hgroup.long (0x24+0x200)++0x03
|
|
hide.long 0x00 "BUFFER9,Buffer 9 Register"
|
|
in
|
|
hgroup.long (0x28+0x200)++0x03
|
|
hide.long 0x00 "BUFFER10,Buffer 10 Register"
|
|
in
|
|
hgroup.long (0x2C+0x200)++0x03
|
|
hide.long 0x00 "BUFFER11,Buffer 11 Register"
|
|
in
|
|
hgroup.long (0x30+0x200)++0x03
|
|
hide.long 0x00 "BUFFER12,Buffer 12 Register"
|
|
in
|
|
hgroup.long (0x34+0x200)++0x03
|
|
hide.long 0x00 "BUFFER13,Buffer 13 Register"
|
|
in
|
|
hgroup.long (0x38+0x200)++0x03
|
|
hide.long 0x00 "BUFFER14,Buffer 14 Register"
|
|
in
|
|
hgroup.long (0x3C+0x200)++0x03
|
|
hide.long 0x00 "BUFFER15,Buffer 15 Register"
|
|
in
|
|
hgroup.long (0x40+0x200)++0x03
|
|
hide.long 0x00 "BUFFER16,Buffer 16 Register"
|
|
in
|
|
hgroup.long (0x44+0x200)++0x03
|
|
hide.long 0x00 "BUFFER17,Buffer 17 Register"
|
|
in
|
|
hgroup.long (0x48+0x200)++0x03
|
|
hide.long 0x00 "BUFFER18,Buffer 18 Register"
|
|
in
|
|
hgroup.long (0x4C+0x200)++0x03
|
|
hide.long 0x00 "BUFFER19,Buffer 19 Register"
|
|
in
|
|
hgroup.long (0x50+0x200)++0x03
|
|
hide.long 0x00 "BUFFER20,Buffer 20 Register"
|
|
in
|
|
hgroup.long (0x54+0x200)++0x03
|
|
hide.long 0x00 "BUFFER21,Buffer 21 Register"
|
|
in
|
|
hgroup.long (0x58+0x200)++0x03
|
|
hide.long 0x00 "BUFFER22,Buffer 22 Register"
|
|
in
|
|
hgroup.long (0x5C+0x200)++0x03
|
|
hide.long 0x00 "BUFFER23,Buffer 23 Register"
|
|
in
|
|
hgroup.long (0x60+0x200)++0x03
|
|
hide.long 0x00 "BUFFER24,Buffer 24 Register"
|
|
in
|
|
hgroup.long (0x64+0x200)++0x03
|
|
hide.long 0x00 "BUFFER25,Buffer 25 Register"
|
|
in
|
|
hgroup.long (0x68+0x200)++0x03
|
|
hide.long 0x00 "BUFFER26,Buffer 26 Register"
|
|
in
|
|
hgroup.long (0x6C+0x200)++0x03
|
|
hide.long 0x00 "BUFFER27,Buffer 27 Register"
|
|
in
|
|
hgroup.long (0x70+0x200)++0x03
|
|
hide.long 0x00 "BUFFER28,Buffer 28 Register"
|
|
in
|
|
hgroup.long (0x74+0x200)++0x03
|
|
hide.long 0x00 "BUFFER29,Buffer 29 Register"
|
|
in
|
|
hgroup.long (0x78+0x200)++0x03
|
|
hide.long 0x00 "BUFFER30,Buffer 30 Register"
|
|
in
|
|
hgroup.long (0x7C+0x200)++0x03
|
|
hide.long 0x00 "BUFFER31,Buffer 31 Register"
|
|
in
|
|
hgroup.long (0x80+0x200)++0x03
|
|
hide.long 0x00 "BUFFER32,Buffer 32 Register"
|
|
in
|
|
hgroup.long (0x84+0x200)++0x03
|
|
hide.long 0x00 "BUFFER33,Buffer 33 Register"
|
|
in
|
|
hgroup.long (0x88+0x200)++0x03
|
|
hide.long 0x00 "BUFFER34,Buffer 34 Register"
|
|
in
|
|
hgroup.long (0x8C+0x200)++0x03
|
|
hide.long 0x00 "BUFFER35,Buffer 35 Register"
|
|
in
|
|
hgroup.long (0x90+0x200)++0x03
|
|
hide.long 0x00 "BUFFER36,Buffer 36 Register"
|
|
in
|
|
hgroup.long (0x94+0x200)++0x03
|
|
hide.long 0x00 "BUFFER37,Buffer 37 Register"
|
|
in
|
|
hgroup.long (0x98+0x200)++0x03
|
|
hide.long 0x00 "BUFFER38,Buffer 38 Register"
|
|
in
|
|
hgroup.long (0x9C+0x200)++0x03
|
|
hide.long 0x00 "BUFFER39,Buffer 39 Register"
|
|
in
|
|
hgroup.long (0xA0+0x200)++0x03
|
|
hide.long 0x00 "BUFFER40,Buffer 40 Register"
|
|
in
|
|
hgroup.long (0xA4+0x200)++0x03
|
|
hide.long 0x00 "BUFFER41,Buffer 41 Register"
|
|
in
|
|
hgroup.long (0xA8+0x200)++0x03
|
|
hide.long 0x00 "BUFFER42,Buffer 42 Register"
|
|
in
|
|
hgroup.long (0xAC+0x200)++0x03
|
|
hide.long 0x00 "BUFFER43,Buffer 43 Register"
|
|
in
|
|
hgroup.long (0xB0+0x200)++0x03
|
|
hide.long 0x00 "BUFFER44,Buffer 44 Register"
|
|
in
|
|
hgroup.long (0xB4+0x200)++0x03
|
|
hide.long 0x00 "BUFFER45,Buffer 45 Register"
|
|
in
|
|
hgroup.long (0xB8+0x200)++0x03
|
|
hide.long 0x00 "BUFFER46,Buffer 46 Register"
|
|
in
|
|
hgroup.long (0xBC+0x200)++0x03
|
|
hide.long 0x00 "BUFFER47,Buffer 47 Register"
|
|
in
|
|
hgroup.long (0xC0+0x200)++0x03
|
|
hide.long 0x00 "BUFFER48,Buffer 48 Register"
|
|
in
|
|
hgroup.long (0xC4+0x200)++0x03
|
|
hide.long 0x00 "BUFFER49,Buffer 49 Register"
|
|
in
|
|
hgroup.long (0xC8+0x200)++0x03
|
|
hide.long 0x00 "BUFFER50,Buffer 50 Register"
|
|
in
|
|
hgroup.long (0xCC+0x200)++0x03
|
|
hide.long 0x00 "BUFFER51,Buffer 51 Register"
|
|
in
|
|
hgroup.long (0xD0+0x200)++0x03
|
|
hide.long 0x00 "BUFFER52,Buffer 52 Register"
|
|
in
|
|
hgroup.long (0xD4+0x200)++0x03
|
|
hide.long 0x00 "BUFFER53,Buffer 53 Register"
|
|
in
|
|
hgroup.long (0xD8+0x200)++0x03
|
|
hide.long 0x00 "BUFFER54,Buffer 54 Register"
|
|
in
|
|
hgroup.long (0xDC+0x200)++0x03
|
|
hide.long 0x00 "BUFFER55,Buffer 55 Register"
|
|
in
|
|
hgroup.long (0xE0+0x200)++0x03
|
|
hide.long 0x00 "BUFFER56,Buffer 56 Register"
|
|
in
|
|
hgroup.long (0xE4+0x200)++0x03
|
|
hide.long 0x00 "BUFFER57,Buffer 57 Register"
|
|
in
|
|
hgroup.long (0xE8+0x200)++0x03
|
|
hide.long 0x00 "BUFFER58,Buffer 58 Register"
|
|
in
|
|
hgroup.long (0xEC+0x200)++0x03
|
|
hide.long 0x00 "BUFFER59,Buffer 59 Register"
|
|
in
|
|
hgroup.long (0xF0+0x200)++0x03
|
|
hide.long 0x00 "BUFFER60,Buffer 60 Register"
|
|
in
|
|
hgroup.long (0xF4+0x200)++0x03
|
|
hide.long 0x00 "BUFFER61,Buffer 61 Register"
|
|
in
|
|
hgroup.long (0xF8+0x200)++0x03
|
|
hide.long 0x00 "BUFFER62,Buffer 62 Register"
|
|
in
|
|
hgroup.long (0xFC+0x200)++0x03
|
|
hide.long 0x00 "BUFFER63,Buffer 63 Register"
|
|
in
|
|
hgroup.long (0x100+0x200)++0x03
|
|
hide.long 0x00 "BUFFER64,Buffer 64 Register"
|
|
in
|
|
hgroup.long (0x104+0x200)++0x03
|
|
hide.long 0x00 "BUFFER65,Buffer 65 Register"
|
|
in
|
|
hgroup.long (0x108+0x200)++0x03
|
|
hide.long 0x00 "BUFFER66,Buffer 66 Register"
|
|
in
|
|
hgroup.long (0x10C+0x200)++0x03
|
|
hide.long 0x00 "BUFFER67,Buffer 67 Register"
|
|
in
|
|
hgroup.long (0x110+0x200)++0x03
|
|
hide.long 0x00 "BUFFER68,Buffer 68 Register"
|
|
in
|
|
hgroup.long (0x114+0x200)++0x03
|
|
hide.long 0x00 "BUFFER69,Buffer 69 Register"
|
|
in
|
|
hgroup.long (0x118+0x200)++0x03
|
|
hide.long 0x00 "BUFFER70,Buffer 70 Register"
|
|
in
|
|
hgroup.long (0x11C+0x200)++0x03
|
|
hide.long 0x00 "BUFFER71,Buffer 71 Register"
|
|
in
|
|
hgroup.long (0x120+0x200)++0x03
|
|
hide.long 0x00 "BUFFER72,Buffer 72 Register"
|
|
in
|
|
hgroup.long (0x124+0x200)++0x03
|
|
hide.long 0x00 "BUFFER73,Buffer 73 Register"
|
|
in
|
|
hgroup.long (0x128+0x200)++0x03
|
|
hide.long 0x00 "BUFFER74,Buffer 74 Register"
|
|
in
|
|
hgroup.long (0x12C+0x200)++0x03
|
|
hide.long 0x00 "BUFFER75,Buffer 75 Register"
|
|
in
|
|
hgroup.long (0x130+0x200)++0x03
|
|
hide.long 0x00 "BUFFER76,Buffer 76 Register"
|
|
in
|
|
hgroup.long (0x134+0x200)++0x03
|
|
hide.long 0x00 "BUFFER77,Buffer 77 Register"
|
|
in
|
|
hgroup.long (0x138+0x200)++0x03
|
|
hide.long 0x00 "BUFFER78,Buffer 78 Register"
|
|
in
|
|
hgroup.long (0x13C+0x200)++0x03
|
|
hide.long 0x00 "BUFFER79,Buffer 79 Register"
|
|
in
|
|
hgroup.long (0x140+0x200)++0x03
|
|
hide.long 0x00 "BUFFER80,Buffer 80 Register"
|
|
in
|
|
hgroup.long (0x144+0x200)++0x03
|
|
hide.long 0x00 "BUFFER81,Buffer 81 Register"
|
|
in
|
|
hgroup.long (0x148+0x200)++0x03
|
|
hide.long 0x00 "BUFFER82,Buffer 82 Register"
|
|
in
|
|
hgroup.long (0x14C+0x200)++0x03
|
|
hide.long 0x00 "BUFFER83,Buffer 83 Register"
|
|
in
|
|
hgroup.long (0x150+0x200)++0x03
|
|
hide.long 0x00 "BUFFER84,Buffer 84 Register"
|
|
in
|
|
hgroup.long (0x154+0x200)++0x03
|
|
hide.long 0x00 "BUFFER85,Buffer 85 Register"
|
|
in
|
|
hgroup.long (0x158+0x200)++0x03
|
|
hide.long 0x00 "BUFFER86,Buffer 86 Register"
|
|
in
|
|
hgroup.long (0x15C+0x200)++0x03
|
|
hide.long 0x00 "BUFFER87,Buffer 87 Register"
|
|
in
|
|
hgroup.long (0x160+0x200)++0x03
|
|
hide.long 0x00 "BUFFER88,Buffer 88 Register"
|
|
in
|
|
hgroup.long (0x164+0x200)++0x03
|
|
hide.long 0x00 "BUFFER89,Buffer 89 Register"
|
|
in
|
|
hgroup.long (0x168+0x200)++0x03
|
|
hide.long 0x00 "BUFFER90,Buffer 90 Register"
|
|
in
|
|
hgroup.long (0x16C+0x200)++0x03
|
|
hide.long 0x00 "BUFFER91,Buffer 91 Register"
|
|
in
|
|
hgroup.long (0x170+0x200)++0x03
|
|
hide.long 0x00 "BUFFER92,Buffer 92 Register"
|
|
in
|
|
hgroup.long (0x174+0x200)++0x03
|
|
hide.long 0x00 "BUFFER93,Buffer 93 Register"
|
|
in
|
|
hgroup.long (0x178+0x200)++0x03
|
|
hide.long 0x00 "BUFFER94,Buffer 94 Register"
|
|
in
|
|
hgroup.long (0x17C+0x200)++0x03
|
|
hide.long 0x00 "BUFFER95,Buffer 95 Register"
|
|
in
|
|
hgroup.long (0x180+0x200)++0x03
|
|
hide.long 0x00 "BUFFER96,Buffer 96 Register"
|
|
in
|
|
hgroup.long (0x184+0x200)++0x03
|
|
hide.long 0x00 "BUFFER97,Buffer 97 Register"
|
|
in
|
|
hgroup.long (0x188+0x200)++0x03
|
|
hide.long 0x00 "BUFFER98,Buffer 98 Register"
|
|
in
|
|
hgroup.long (0x18C+0x200)++0x03
|
|
hide.long 0x00 "BUFFER99,Buffer 99 Register"
|
|
in
|
|
hgroup.long (0x190+0x200)++0x03
|
|
hide.long 0x00 "BUFFER100,Buffer 100 Register"
|
|
in
|
|
hgroup.long (0x194+0x200)++0x03
|
|
hide.long 0x00 "BUFFER101,Buffer 101 Register"
|
|
in
|
|
hgroup.long (0x198+0x200)++0x03
|
|
hide.long 0x00 "BUFFER102,Buffer 102 Register"
|
|
in
|
|
hgroup.long (0x19C+0x200)++0x03
|
|
hide.long 0x00 "BUFFER103,Buffer 103 Register"
|
|
in
|
|
hgroup.long (0x1A0+0x200)++0x03
|
|
hide.long 0x00 "BUFFER104,Buffer 104 Register"
|
|
in
|
|
hgroup.long (0x1A4+0x200)++0x03
|
|
hide.long 0x00 "BUFFER105,Buffer 105 Register"
|
|
in
|
|
hgroup.long (0x1A8+0x200)++0x03
|
|
hide.long 0x00 "BUFFER106,Buffer 106 Register"
|
|
in
|
|
hgroup.long (0x1AC+0x200)++0x03
|
|
hide.long 0x00 "BUFFER107,Buffer 107 Register"
|
|
in
|
|
hgroup.long (0x1B0+0x200)++0x03
|
|
hide.long 0x00 "BUFFER108,Buffer 108 Register"
|
|
in
|
|
hgroup.long (0x1B4+0x200)++0x03
|
|
hide.long 0x00 "BUFFER109,Buffer 109 Register"
|
|
in
|
|
hgroup.long (0x1B8+0x200)++0x03
|
|
hide.long 0x00 "BUFFER110,Buffer 110 Register"
|
|
in
|
|
hgroup.long (0x1BC+0x200)++0x03
|
|
hide.long 0x00 "BUFFER111,Buffer 111 Register"
|
|
in
|
|
hgroup.long (0x1C0+0x200)++0x03
|
|
hide.long 0x00 "BUFFER112,Buffer 112 Register"
|
|
in
|
|
hgroup.long (0x1C4+0x200)++0x03
|
|
hide.long 0x00 "BUFFER113,Buffer 113 Register"
|
|
in
|
|
hgroup.long (0x1C8+0x200)++0x03
|
|
hide.long 0x00 "BUFFER114,Buffer 114 Register"
|
|
in
|
|
hgroup.long (0x1CC+0x200)++0x03
|
|
hide.long 0x00 "BUFFER115,Buffer 115 Register"
|
|
in
|
|
hgroup.long (0x1D0+0x200)++0x03
|
|
hide.long 0x00 "BUFFER116,Buffer 116 Register"
|
|
in
|
|
hgroup.long (0x1D4+0x200)++0x03
|
|
hide.long 0x00 "BUFFER117,Buffer 117 Register"
|
|
in
|
|
hgroup.long (0x1D8+0x200)++0x03
|
|
hide.long 0x00 "BUFFER118,Buffer 118 Register"
|
|
in
|
|
hgroup.long (0x1DC+0x200)++0x03
|
|
hide.long 0x00 "BUFFER119,Buffer 119 Register"
|
|
in
|
|
hgroup.long (0x1E0+0x200)++0x03
|
|
hide.long 0x00 "BUFFER120,Buffer 120 Register"
|
|
in
|
|
hgroup.long (0x1E4+0x200)++0x03
|
|
hide.long 0x00 "BUFFER121,Buffer 121 Register"
|
|
in
|
|
hgroup.long (0x1E8+0x200)++0x03
|
|
hide.long 0x00 "BUFFER122,Buffer 122 Register"
|
|
in
|
|
hgroup.long (0x1EC+0x200)++0x03
|
|
hide.long 0x00 "BUFFER123,Buffer 123 Register"
|
|
in
|
|
hgroup.long (0x1F0+0x200)++0x03
|
|
hide.long 0x00 "BUFFER124,Buffer 124 Register"
|
|
in
|
|
hgroup.long (0x1F4+0x200)++0x03
|
|
hide.long 0x00 "BUFFER125,Buffer 125 Register"
|
|
in
|
|
hgroup.long (0x1F8+0x200)++0x03
|
|
hide.long 0x00 "BUFFER126,Buffer 126 Register"
|
|
in
|
|
hgroup.long (0x1FC+0x200)++0x03
|
|
hide.long 0x00 "BUFFER127,Buffer 127 Register"
|
|
in
|
|
tree.end
|
|
endif
|
|
sif cpuis("TMS570LS0232")||cpuis("TMS570LS0714*")||cpuis("TMS570LS0914*")
|
|
endian.le
|
|
endif
|
|
width 0xB
|
|
tree.end
|
|
tree "SPI4"
|
|
base ad:0xFFF7FA00
|
|
width 17.
|
|
sif cpuis("TMS570LS0232")||cpuis("TMS570LS0714*")||cpuis("TMS570LS0914*")
|
|
endian.be
|
|
endif
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "SPIGCR0,SPI Global Control Register 0"
|
|
bitfld.long 0x00 0. " NRESET ,Reset bit for the module" "No reset,Reset"
|
|
group.long 0x04++0x0F
|
|
line.long 0x00 "SPIGCR1,SPI Global Control Register 1"
|
|
bitfld.long 0x00 24. " SPIEN ,SPI enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " LOOPBACK ,Internal loop-back test mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " POWERDOWN ,SPI state machine enters a power-down state" "No power-down,Power-down"
|
|
newline
|
|
bitfld.long 0x00 1. " CLKMOD ,Clock mode" "External,Internally"
|
|
bitfld.long 0x00 0. " MASTER ,SPISIMO/SPISOMI pin direction determination" "Input/output,Output/input"
|
|
line.long 0x04 "SPIINT0,SPI Interrupt Register"
|
|
bitfld.long 0x04 24. " ENABLEHIGHZ ,SPIENA pin high-impedance enable" "Inactive,Active"
|
|
bitfld.long 0x04 16. " DMAREQEN ,DMA request enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 9. " TXINTENA ,TX interrupt flag enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x04 8. " RXINTENA ,RX interrupt flag enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 6. " RXOVRNINTENA ,Overrun interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 4. " BITERRENA ,Enables interrupt on bit error" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x04 3. " DESYNCENA ,Enables interrupt on desynchronized slave" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " PARERRENA ,Enables interrupt-on-parity-error" "Disabled,Enabled"
|
|
bitfld.long 0x04 1. " TIMEOUTENA ,Enables interrupt on ENA signal time-out" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x04 0. " DLENERRENA ,Data length error interrupt enable" "Disabled,Enabled"
|
|
line.long 0x08 "SPILVL,SPI Interrupt Level Register"
|
|
bitfld.long 0x08 9. " TXINTLVL ,Transmit interrupt level" "INT0,INT1"
|
|
bitfld.long 0x08 8. " RXINTLVL ,Receive interrupt level" "INT0,INT1"
|
|
sif !cpuis("TMS570LS0232")
|
|
bitfld.long 0x08 6. " RXOVRNINTLVL ,Receive overrun interrupt level" "INT0,INT1"
|
|
endif
|
|
newline
|
|
bitfld.long 0x08 4. " BITERRLVL ,Bit error interrupt level" "INT0,INT1"
|
|
bitfld.long 0x08 3. " DESYNCLVL ,Desynchronized slave interrupt level (master mode only)" "INT0,INT1"
|
|
bitfld.long 0x08 2. " PARERRLVL ,Parity error interrupt level" "INT0,INT1"
|
|
newline
|
|
bitfld.long 0x08 1. " TIMEOUTLVL ,SPIENA pin time-out interrupt level" "INT0,INT1"
|
|
bitfld.long 0x08 0. " DLENERRLVL ,Data length error interrupt level (line) select" "INT0,INT1"
|
|
line.long 0x0C "SPIFLG,SPI Flag Register"
|
|
bitfld.long 0x0C 24. " BUFINITACTIVE ,Indicates the status of multi-buffer initialization process" "Completed,Not completed"
|
|
bitfld.long 0x0C 9. " TXINTFLG ,Transmitter-empty interrupt flag" "No interrupt,Interrupt"
|
|
eventfld.long 0x0C 8. " RXINTFLG ,Receiver-full interrupt flag" "No interrupt,Interrupt"
|
|
newline
|
|
eventfld.long 0x0C 6. " RXOVRNINTFLG ,Overrun interrupt enable" "Disabled,Enabled"
|
|
eventfld.long 0x0C 4. " BITERRFLG ,Enables interrupt on bit error" "Disabled,Enabled"
|
|
eventfld.long 0x0C 3. " DESYNCFLG ,Enables interrupt on desynchronized slave" "No interrupt,Interrupt"
|
|
newline
|
|
eventfld.long 0x0C 2. " PARITYERRFLG ,Enables interrupt-on-parity-error" "No error,Error"
|
|
eventfld.long 0x0C 1. " TIMEOUTFLG ,Enables interrupt on ENA signal time-out" "No interrupt,Interrupt"
|
|
eventfld.long 0x0C 0. " DLENERRFLG ,Data length error interrupt enable" "No interrupt,Interrupt"
|
|
group.long 0x14++0x23
|
|
line.long 0x00 "SPIPC0,SPI Pin Control Register 0"
|
|
sif !cpuis("TMS570LS0232")&&!cpuis("TMS570LS0332")&&!cpuis("TMS570LS0432")
|
|
bitfld.long 0x00 31. " SOMIFUN7 ,SPISOMI[7] pin function" "GIO,SPI"
|
|
bitfld.long 0x00 30. " SOMIFUN6 ,SPISOMI[6] pin function" "GIO,SPI"
|
|
bitfld.long 0x00 29. " SOMIFUN5 ,SPISOMI[5] pin function" "GIO,SPI"
|
|
newline
|
|
bitfld.long 0x00 28. " SOMIFUN4 ,SPISOMI[4] pin function" "GIO,SPI"
|
|
bitfld.long 0x00 27. " SOMIFUN3 ,SPISOMI[3] pin function" "GIO,SPI"
|
|
bitfld.long 0x00 26. " SOMIFUN2 ,SPISOMI[2] pin function" "GIO,SPI"
|
|
newline
|
|
bitfld.long 0x00 25. " SOMIFUN1 ,SPISOMI[1] pin function" "GIO,SPI"
|
|
bitfld.long 0x00 24. " SOMIFUN0 ,SPISOMI[0] pin function (mirror of bit 11)" "GIO,SPI"
|
|
bitfld.long 0x00 23. " SIMOFUN7 ,SPISIMO[7] pin function" "GIO,SPI"
|
|
newline
|
|
bitfld.long 0x00 22. " SIMOFUN6 ,SPISIMO[6] pin function" "GIO,SPI"
|
|
bitfld.long 0x00 21. " SIMOFUN5 ,SPISIMO[5] pin function" "GIO,SPI"
|
|
bitfld.long 0x00 20. " SIMOFUN4 ,SPISIMO[4] pin function" "GIO,SPI"
|
|
newline
|
|
bitfld.long 0x00 19. " SIMOFUN3 ,SPISIMO[3] pin function" "GIO,SPI"
|
|
bitfld.long 0x00 18. " SIMOFUN2 ,SPISIMO[2] pin function" "GIO,SPI"
|
|
bitfld.long 0x00 17. " SIMOFUN1 ,SPISIMO[1] pin function" "GIO,SPI"
|
|
newline
|
|
bitfld.long 0x00 16. " SIMOFUN0 ,SPISIMO[0] pin function (mirror of bit 10)" "GIO,SPI"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 11. " SOMIFUN0 ,SPISOMI[0] pin function" "GIO,SPI"
|
|
bitfld.long 0x00 10. " SIMOFUN0 ,SPISIMO[0] pin function" "GIO,SPI"
|
|
newline
|
|
bitfld.long 0x00 9. " CLKFUN ,SPI clock function" "GIO,SPI"
|
|
bitfld.long 0x00 8. " ENAFUN ,SPIENA function" "GIO,SPI"
|
|
bitfld.long 0x00 7. " SCSFUN7 ,SPISCS7 function 7" "GIO,SPI"
|
|
newline
|
|
bitfld.long 0x00 6. " SCSFUN6 ,SPISCS6 function 6" "GIO,SPI"
|
|
bitfld.long 0x00 5. " SCSFUN5 ,SPISCS5 function 5" "GIO,SPI"
|
|
bitfld.long 0x00 4. " SCSFUN4 ,SPISCS4 function 4" "GIO,SPI"
|
|
newline
|
|
bitfld.long 0x00 3. " SCSFUN3 ,SPISCS3 function 3" "GIO,SPI"
|
|
bitfld.long 0x00 2. " SCSFUN2 ,SPISCS2 function 2" "GIO,SPI"
|
|
bitfld.long 0x00 1. " SCSFUN1 ,SPISCS1 function 1" "GIO,SPI"
|
|
newline
|
|
bitfld.long 0x00 0. " SCSFUN0 ,SPISCS0 function 0" "GIO,SPI"
|
|
line.long 0x04 "SPIPC1,SPI Pin Control Register 1"
|
|
bitfld.long 0x04 31. " SOMIDIR7 ,SPISOMI[7] pin direction" "GIO,SPI"
|
|
bitfld.long 0x04 30. " SOMIDIR6 ,SPISOMI[6] pin direction" "GIO,SPI"
|
|
bitfld.long 0x04 29. " SOMIDIR5 ,SPISOMI[5] pin direction" "GIO,SPI"
|
|
newline
|
|
bitfld.long 0x04 28. " SOMIDIR4 ,SPISOMI[4] pin direction" "GIO,SPI"
|
|
bitfld.long 0x04 27. " SOMIDIR3 ,SPISOMI[3] pin direction" "GIO,SPI"
|
|
bitfld.long 0x04 26. " SOMIDIR2 ,SPISOMI[2] pin direction" "GIO,SPI"
|
|
newline
|
|
bitfld.long 0x04 25. " SOMIDIR1 ,SPISOMI[1] pin direction" "GIO,SPI"
|
|
bitfld.long 0x04 24. " SOMIDIR0 ,SPISOMI[0] pin direction (mirror of bit 11)" "GIO,SPI"
|
|
bitfld.long 0x04 23. " SIMODIR7 ,SPISIMO[7] pin direction" "GIO,SPI"
|
|
newline
|
|
bitfld.long 0x04 22. " SIMODIR6 ,SPISIMO[6] pin direction" "GIO,SPI"
|
|
bitfld.long 0x04 21. " SIMODIR5 ,SPISIMO[5] pin direction" "GIO,SPI"
|
|
bitfld.long 0x04 20. " SIMODIR4 ,SPISIMO[4] pin direction" "GIO,SPI"
|
|
newline
|
|
bitfld.long 0x04 19. " SIMODIR3 ,SPISIMO[3] pin direction" "GIO,SPI"
|
|
bitfld.long 0x04 18. " SIMODIR2 ,SPISIMO[2] pin direction" "GIO,SPI"
|
|
bitfld.long 0x04 17. " SIMODIR1 ,SPISIMO[1] pin direction" "GIO,SPI"
|
|
newline
|
|
bitfld.long 0x04 16. " SIMODIR0 ,SPISIMO[0] pin direction (mirror of bit 10)" "GIO,SPI"
|
|
bitfld.long 0x04 11. " SOMIDIR0 ,SPISOMI[0] pin direction" "GIO,SPI"
|
|
bitfld.long 0x04 10. " SIMODIR0 ,SPISIMO[0] pin direction" "GIO,SPI"
|
|
newline
|
|
bitfld.long 0x04 9. " CLKDIR ,SPI clock direction" "GIO,SPI"
|
|
bitfld.long 0x04 8. " ENADIR ,SPIENA direction" "GIO,SPI"
|
|
bitfld.long 0x04 7. " SCSDIR7 ,SPISCS7 direction 7" "GIO,SPI"
|
|
newline
|
|
bitfld.long 0x04 6. " SCSDIR6 ,SPISCS6 direction 6" "GIO,SPI"
|
|
bitfld.long 0x04 5. " SCSDIR5 ,SPISCS5 direction 5" "GIO,SPI"
|
|
bitfld.long 0x04 4. " SCSDIR4 ,SPISCS4 direction 4" "GIO,SPI"
|
|
newline
|
|
bitfld.long 0x04 3. " SCSDIR3 ,SPISCS3 direction 3" "GIO,SPI"
|
|
bitfld.long 0x04 2. " SCSDIR2 ,SPISCS2 direction 2" "GIO,SPI"
|
|
bitfld.long 0x04 1. " SCSDIR1 ,SPISCS1 direction 1" "GIO,SPI"
|
|
newline
|
|
bitfld.long 0x04 0. " SCSDIR0 ,SPISCS0 direction 0" "GIO,SPI"
|
|
line.long 0x08 "SPIPC2,SPI Pin Control Register 2"
|
|
bitfld.long 0x08 31. " SOMIDIN7 ,SPISOMI[7] data in" "0,1"
|
|
bitfld.long 0x08 30. " SOMIDIN6 ,SPISOMI[6] data in" "0,1"
|
|
bitfld.long 0x08 29. " SOMIDIN5 ,SPISOMI[5] data in" "0,1"
|
|
newline
|
|
bitfld.long 0x08 28. " SOMIDIN4 ,SPISOMI[4] data in" "0,1"
|
|
bitfld.long 0x08 27. " SOMIDIN3 ,SPISOMI[3] data in" "0,1"
|
|
bitfld.long 0x08 26. " SOMIDIN2 ,SPISOMI[2] data in" "0,1"
|
|
newline
|
|
bitfld.long 0x08 25. " SOMIDIN1 ,SPISOMI[1] data in" "0,1"
|
|
bitfld.long 0x08 24. " SOMIDIN0 ,SPISOMI[0] data in (mirror of bit 11)" "0,1"
|
|
bitfld.long 0x08 23. " SIMODIN7 ,SPISIMO[7] data in" "0,1"
|
|
newline
|
|
bitfld.long 0x08 22. " SIMODIN6 ,SPISIMO[6] data in" "0,1"
|
|
bitfld.long 0x08 21. " SIMODIN5 ,SPISIMO[5] data in" "0,1"
|
|
bitfld.long 0x08 20. " SIMODIN4 ,SPISIMO[4] data in" "0,1"
|
|
newline
|
|
bitfld.long 0x08 19. " SIMODIN3 ,SPISIMO[3] data in" "0,1"
|
|
bitfld.long 0x08 18. " SIMODIN2 ,SPISIMO[2] data in" "0,1"
|
|
bitfld.long 0x08 17. " SIMODIN1 ,SPISIMO[1] data in" "0,1"
|
|
newline
|
|
bitfld.long 0x08 16. " SIMODIN0 ,SPISIMO[0] data in (mirror of bit 10)" "0,1"
|
|
bitfld.long 0x08 11. " SOMIDIN0 ,SPISOMI[0] data in" "0,1"
|
|
bitfld.long 0x08 10. " SIMODIN0 ,SPISIMO[0] data in" "0,1"
|
|
newline
|
|
bitfld.long 0x08 9. " CLKDIN ,SPI clock data in" "0,1"
|
|
bitfld.long 0x08 8. " ENADIN ,SPIENA data in" "0,1"
|
|
bitfld.long 0x08 7. " SCSDIN7 ,SPISCS7 data in" "0,1"
|
|
newline
|
|
bitfld.long 0x08 6. " SCSDIN6 ,SPISCS6 data in" "0,1"
|
|
bitfld.long 0x08 5. " SCSDIN5 ,SPISCS5 data in" "0,1"
|
|
bitfld.long 0x08 4. " SCSDIN4 ,SPISCS4 data in" "0,1"
|
|
newline
|
|
bitfld.long 0x08 3. " SCSDIN3 ,SPISCS3 data in" "0,1"
|
|
bitfld.long 0x08 2. " SCSDIN2 ,SPISCS2 data in" "0,1"
|
|
bitfld.long 0x08 1. " SCSDIN1 ,SPISCS1 data in" "0,1"
|
|
newline
|
|
bitfld.long 0x08 0. " SCSDIN0 ,SPISCS0 direction 0" "0,1"
|
|
line.long 0x0C "SPIPC3,SPI Pin Control Register 3"
|
|
bitfld.long 0x0C 31. " SOMIDOUT7 ,SPISOMI[7] data out write" "0,1"
|
|
bitfld.long 0x0C 30. " SOMIDOUT6 ,SPISOMI[6] data out write" "0,1"
|
|
bitfld.long 0x0C 29. " SOMIDOUT5 ,SPISOMI[5] data out write" "0,1"
|
|
newline
|
|
bitfld.long 0x0C 28. " SOMIDOUT4 ,SPISOMI[4] data out write" "0,1"
|
|
bitfld.long 0x0C 27. " SOMIDOUT3 ,SPISOMI[3] data out write" "0,1"
|
|
bitfld.long 0x0C 26. " SOMIDOUT2 ,SPISOMI[2] data out write" "0,1"
|
|
newline
|
|
bitfld.long 0x0C 25. " SOMIDOUT1 ,SPISOMI[1] data out write" "0,1"
|
|
bitfld.long 0x0C 24. " SOMIDOUT0 ,SPISOMI[0] data out write (mirror of bit 11)" "0,1"
|
|
bitfld.long 0x0C 23. " SIMODOUT7 ,SPISIMO[7] data out write" "0,1"
|
|
newline
|
|
bitfld.long 0x0C 22. " SIMODOUT6 ,SPISIMO[6] data out write" "0,1"
|
|
bitfld.long 0x0C 21. " SIMODOUT5 ,SPISIMO[5] data out write" "0,1"
|
|
bitfld.long 0x0C 20. " SIMODOUT4 ,SPISIMO[4] data out write" "0,1"
|
|
newline
|
|
bitfld.long 0x0C 19. " SIMODOUT3 ,SPISIMO[3] data out write" "0,1"
|
|
bitfld.long 0x0C 18. " SIMODOUT2 ,SPISIMO[2] data out write" "0,1"
|
|
bitfld.long 0x0C 17. " SIMODOUT1 ,SPISIMO[1] data out write" "0,1"
|
|
newline
|
|
bitfld.long 0x0C 16. " SIMODOUT0 ,SPISIMO[0] data out write (mirror of bit 10)" "0,1"
|
|
bitfld.long 0x0C 11. " SOMIDOUT0 ,SPISOMI[0] data out write" "0,1"
|
|
bitfld.long 0x0C 10. " SIMODOUT0 ,SPISIMO[0] data out write" "0,1"
|
|
newline
|
|
bitfld.long 0x0C 9. " CLKDOUT ,SPI clock data out write" "0,1"
|
|
bitfld.long 0x0C 8. " ENADOUT ,SPIENA data out write" "0,1"
|
|
bitfld.long 0x0C 7. " SCSDOUT7 ,SPISCS7 data out write" "0,1"
|
|
newline
|
|
bitfld.long 0x0C 6. " SCSDOUT6 ,SPISCS6 data out write" "0,1"
|
|
bitfld.long 0x0C 5. " SCSDOUT5 ,SPISCS5 data out write" "0,1"
|
|
bitfld.long 0x0C 4. " SCSDOUT4 ,SPISCS4 data out write" "0,1"
|
|
newline
|
|
bitfld.long 0x0C 3. " SCSDOUT3 ,SPISCS3 data out write" "0,1"
|
|
bitfld.long 0x0C 2. " SCSDOUT2 ,SPISCS2 data out write" "0,1"
|
|
bitfld.long 0x0C 1. " SCSDOUT1 ,SPISCS1 data out write" "0,1"
|
|
newline
|
|
bitfld.long 0x0C 0. " SCSDOUT0 ,SPISCS0 data out write" "0,1"
|
|
line.long 0x10 "SPIPC4,SPI Pin Control Register 4"
|
|
bitfld.long 0x10 31. " SOMISET7 ,SPISOMI[7] data out set" "0,1"
|
|
bitfld.long 0x10 30. " SOMISET6 ,SPISOMI[6] data out set" "0,1"
|
|
bitfld.long 0x10 29. " SOMISET5 ,SPISOMI[5] data out set" "0,1"
|
|
newline
|
|
bitfld.long 0x10 28. " SOMISET4 ,SPISOMI[4] data out set" "0,1"
|
|
bitfld.long 0x10 27. " SOMISET3 ,SPISOMI[3] data out set" "0,1"
|
|
bitfld.long 0x10 26. " SOMISET2 ,SPISOMI[2] data out set" "0,1"
|
|
newline
|
|
bitfld.long 0x10 25. " SOMISET1 ,SPISOMI[1] data out set" "0,1"
|
|
bitfld.long 0x10 24. " SOMISET0 ,SPISOMI[0] data out set (mirror of bit 11)" "0,1"
|
|
bitfld.long 0x10 23. " SIMOSET7 ,SPISIMO[7] data out set" "0,1"
|
|
newline
|
|
bitfld.long 0x10 22. " SIMOSET6 ,SPISIMO[6] data out set" "0,1"
|
|
bitfld.long 0x10 21. " SIMOSET5 ,SPISIMO[5] data out set" "0,1"
|
|
bitfld.long 0x10 20. " SIMOSET4 ,SPISIMO[4] data out set" "0,1"
|
|
newline
|
|
bitfld.long 0x10 19. " SIMOSET3 ,SPISIMO[3] data out set" "0,1"
|
|
bitfld.long 0x10 18. " SIMOSET2 ,SPISIMO[2] data out set" "0,1"
|
|
bitfld.long 0x10 17. " SIMOSET1 ,SPISIMO[1] data out set" "0,1"
|
|
newline
|
|
bitfld.long 0x10 16. " SIMOSET0 ,SPISIMO[0] data out set (mirror of bit 10)" "0,1"
|
|
bitfld.long 0x10 11. " SOMISET0 ,SPISOMI[0] data out set" "0,1"
|
|
bitfld.long 0x10 10. " SIMOSET0 ,SPISIMO[0] data out set" "0,1"
|
|
newline
|
|
bitfld.long 0x10 9. " CLKSET ,SPI clock data out set" "0,1"
|
|
bitfld.long 0x10 8. " ENASET ,SPIENA data out set" "0,1"
|
|
bitfld.long 0x10 7. " SCSSET7 ,SPISCS7 data out set" "0,1"
|
|
newline
|
|
bitfld.long 0x10 6. " SCSSET6 ,SPISCS6 data out set" "0,1"
|
|
bitfld.long 0x10 5. " SCSSET5 ,SPISCS5 data out set" "0,1"
|
|
bitfld.long 0x10 4. " SCSSET4 ,SPISCS4 data out set" "0,1"
|
|
newline
|
|
bitfld.long 0x10 3. " SCSSET3 ,SPISCS3 data out set" "0,1"
|
|
bitfld.long 0x10 2. " SCSSET2 ,SPISCS2 data out set" "0,1"
|
|
bitfld.long 0x10 1. " SCSSET1 ,SPISCS1 data out set" "0,1"
|
|
newline
|
|
bitfld.long 0x10 0. " SCSSET0 ,SPISCS0 data out set" "0,1"
|
|
line.long 0x14 "SPIPC5,SPI Pin Control Register 5"
|
|
bitfld.long 0x14 31. " SOMICLR7 ,SPISOMI[7] data out clear" "0,1"
|
|
bitfld.long 0x14 30. " SOMICLR6 ,SPISOMI[6] data out clear" "0,1"
|
|
bitfld.long 0x14 29. " SOMICLR5 ,SPISOMI[5] data out clear" "0,1"
|
|
newline
|
|
bitfld.long 0x14 28. " SOMICLR4 ,SPISOMI[4] data out clear" "0,1"
|
|
bitfld.long 0x14 27. " SOMICLR3 ,SPISOMI[3] data out clear" "0,1"
|
|
bitfld.long 0x14 26. " SOMICLR2 ,SPISOMI[2] data out clear" "0,1"
|
|
newline
|
|
bitfld.long 0x14 25. " SOMICLR1 ,SPISOMI[1] data out clear" "0,1"
|
|
bitfld.long 0x14 24. " SOMICLR0 ,SPISOMI[0] data out clear (mirror of bit 11)" "0,1"
|
|
bitfld.long 0x14 23. " SIMOCLR7 ,SPISIMO[7] data out clear" "0,1"
|
|
newline
|
|
bitfld.long 0x14 22. " SIMOCLR6 ,SPISIMO[6] data out clear" "0,1"
|
|
bitfld.long 0x14 21. " SIMOCLR5 ,SPISIMO[5] data out clear" "0,1"
|
|
bitfld.long 0x14 20. " SIMOCLR4 ,SPISIMO[4] data out clear" "0,1"
|
|
newline
|
|
bitfld.long 0x14 19. " SIMOCLR3 ,SPISIMO[3] data out clear" "0,1"
|
|
bitfld.long 0x14 18. " SIMOCLR2 ,SPISIMO[2] data out clear" "0,1"
|
|
bitfld.long 0x14 17. " SIMOCLR1 ,SPISIMO[1] data out clear" "0,1"
|
|
newline
|
|
bitfld.long 0x14 16. " SIMOCLR0 ,SPISIMO[0] data out clear (mirror of bit 10)" "0,1"
|
|
bitfld.long 0x14 11. " SOMICLR0 ,SPISOMI[0] data out clear" "0,1"
|
|
bitfld.long 0x14 10. " SIMOCLR0 ,SPISIMO[0] data out clear" "0,1"
|
|
newline
|
|
bitfld.long 0x14 9. " CLKCLR ,SPI clock data out clear" "0,1"
|
|
bitfld.long 0x14 8. " ENACLR ,SPIENA data out clear" "0,1"
|
|
bitfld.long 0x14 7. " SCSCLR7 ,SPISCS7 data out clear" "0,1"
|
|
newline
|
|
bitfld.long 0x14 6. " SCSCLR6 ,SPISCS6 data out clear" "0,1"
|
|
bitfld.long 0x14 5. " SCSCLR5 ,SPISCS5 data out clear" "0,1"
|
|
bitfld.long 0x14 4. " SCSCLR4 ,SPISCS4 data out clear" "0,1"
|
|
newline
|
|
bitfld.long 0x14 3. " SCSCLR3 ,SPISCS3 data out clear" "0,1"
|
|
bitfld.long 0x14 2. " SCSCLR2 ,SPISCS2 data out clear" "0,1"
|
|
bitfld.long 0x14 1. " SCSCLR1 ,SPISCS1 data out clear" "0,1"
|
|
newline
|
|
bitfld.long 0x14 0. " SCSCLR0 ,SPISCS0 data out clear" "0,1"
|
|
line.long 0x18 "SPIPC6,SPI Pin Control Register 6"
|
|
bitfld.long 0x18 31. " SOMIPDR7 ,SPISOMI[7] open drain enable" "Disabled,Enabled"
|
|
bitfld.long 0x18 30. " SOMIPDR6 ,SPISOMI[6] open drain enable" "Disabled,Enabled"
|
|
bitfld.long 0x18 29. " SOMIPDR5 ,SPISOMI[5] open drain enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x18 28. " SOMIPDR4 ,SPISOMI[4] open drain enable" "Disabled,Enabled"
|
|
bitfld.long 0x18 27. " SOMIPDR3 ,SPISOMI[3] open drain enable" "Disabled,Enabled"
|
|
bitfld.long 0x18 26. " SOMIPDR2 ,SPISOMI[2] open drain enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x18 25. " SOMIPDR1 ,SPISOMI[1] open drain enable" "Disabled,Enabled"
|
|
bitfld.long 0x18 24. " SOMIPDR0 ,SPISOMI[0] open drain enable (mirror of bit 11)" "Disabled,Enabled"
|
|
bitfld.long 0x18 23. " SIMOPDR7 ,SPISIMO[7] open drain enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x18 22. " SIMOPDR6 ,SPISIMO[6] open drain enable" "Disabled,Enabled"
|
|
bitfld.long 0x18 21. " SIMOPDR5 ,SPISIMO[5] open drain enable" "Disabled,Enabled"
|
|
bitfld.long 0x18 20. " SIMOPDR4 ,SPISIMO[4] open drain enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x18 19. " SIMOPDR3 ,SPISIMO[3] open drain enable" "Disabled,Enabled"
|
|
bitfld.long 0x18 18. " SIMOPDR2 ,SPISIMO[2] open drain enable" "Disabled,Enabled"
|
|
bitfld.long 0x18 17. " SIMOPDR1 ,SPISIMO[1] open drain enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x18 16. " SIMOPDR0 ,SPISIMO[0] open drain enable (mirror of bit 10)" "Disabled,Enabled"
|
|
bitfld.long 0x18 11. " SOMIPDR0 ,SPISOMI[0] open drain enable" "Disabled,Enabled"
|
|
bitfld.long 0x18 10. " SIMOPDR0 ,SPISIMO[0] open drain enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x18 9. " CLKPDR ,SPI clock open drain enable" "Disabled,Enabled"
|
|
bitfld.long 0x18 8. " ENAPDR ,SPIENA open drain enable" "Disabled,Enabled"
|
|
bitfld.long 0x18 7. " SCSPDR7 ,SPISCS7 open drain enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x18 6. " SCSPDR6 ,SPISCS6 open drain enable" "Disabled,Enabled"
|
|
bitfld.long 0x18 5. " SCSPDR5 ,SPISCS5 open drain enable" "Disabled,Enabled"
|
|
bitfld.long 0x18 4. " SCSPDR4 ,SPISCS4 open drain enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x18 3. " SCSPDR3 ,SPISCS3 open drain enable" "Disabled,Enabled"
|
|
bitfld.long 0x18 2. " SCSPDR2 ,SPISCS2 open drain enable" "Disabled,Enabled"
|
|
bitfld.long 0x18 1. " SCSPDR1 ,SPISCS1 open drain enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x18 0. " SCSPDR0 ,SPISCS0 open drain enable" "Disabled,Enabled"
|
|
line.long 0x1C "SPIPC7,SPI Pin Control Register 7"
|
|
bitfld.long 0x1C 31. " SOMIPDIS7 ,SPISOMI[7] pull control enable/disable" "No,Yes"
|
|
bitfld.long 0x1C 30. " SOMIPDIS6 ,SPISOMI[6] pull control enable/disable" "No,Yes"
|
|
bitfld.long 0x1C 29. " SOMIPDIS5 ,SPISOMI[5] pull control enable/disable" "No,Yes"
|
|
newline
|
|
bitfld.long 0x1C 28. " SOMIPDIS4 ,SPISOMI[4] pull control enable/disable" "No,Yes"
|
|
bitfld.long 0x1C 27. " SOMIPDIS3 ,SPISOMI[3] pull control enable/disable" "No,Yes"
|
|
bitfld.long 0x1C 26. " SOMIPDIS2 ,SPISOMI[2] pull control enable/disable" "No,Yes"
|
|
newline
|
|
bitfld.long 0x1C 25. " SOMIPDIS1 ,SPISOMI[1] pull control enable/disable" "No,Yes"
|
|
bitfld.long 0x1C 24. " SOMIPDIS0 ,SPISOMI[0] pull control enable/disable (mirror of bit 11)" "No,Yes"
|
|
bitfld.long 0x1C 23. " SIMOPDIS7 ,SPISIMO[7] pull control enable/disable" "No,Yes"
|
|
newline
|
|
bitfld.long 0x1C 22. " SIMOPDIS6 ,SPISIMO[6] pull control enable/disable" "No,Yes"
|
|
bitfld.long 0x1C 21. " SIMOPDIS5 ,SPISIMO[5] pull control enable/disable" "No,Yes"
|
|
bitfld.long 0x1C 20. " SIMOPDIS4 ,SPISIMO[4] pull control enable/disable" "No,Yes"
|
|
newline
|
|
bitfld.long 0x1C 19. " SIMOPDIS3 ,SPISIMO[3] pull control enable/disable" "No,Yes"
|
|
bitfld.long 0x1C 18. " SIMOPDIS2 ,SPISIMO[2] pull control enable/disable" "No,Yes"
|
|
bitfld.long 0x1C 17. " SIMOPDIS1 ,SPISIMO[1] pull control enable/disable" "No,Yes"
|
|
newline
|
|
bitfld.long 0x1C 16. " SIMOPDIS0 ,SPISIMO[0] pull control enable/disable (mirror of bit 10)" "No,Yes"
|
|
bitfld.long 0x1C 11. " SOMIPDIS0 ,SPISOMI[0] pull control enable/disable" "No,Yes"
|
|
bitfld.long 0x1C 10. " SIMOPDIS0 ,SPISIMO[0] pull control enable/disable" "No,Yes"
|
|
newline
|
|
bitfld.long 0x1C 9. " CLKPDIS ,SPI clock pull control enable/disable" "No,Yes"
|
|
bitfld.long 0x1C 8. " ENAPDIS ,SPIENA pull control enable/disable" "No,Yes"
|
|
bitfld.long 0x1C 7. " SCSPDIS7 ,SPISCS7 pull control enable/disable" "No,Yes"
|
|
newline
|
|
bitfld.long 0x1C 6. " SCSPDIS6 ,SPISCS6 pull control enable/disable" "No,Yes"
|
|
bitfld.long 0x1C 5. " SCSPDIS5 ,SPISCS5 pull control enable/disable" "No,Yes"
|
|
bitfld.long 0x1C 4. " SCSPDIS4 ,SPISCS4 pull control enable/disable" "No,Yes"
|
|
newline
|
|
bitfld.long 0x1C 3. " SCSPDIS3 ,SPISCS3 pull control enable/disable" "No,Yes"
|
|
bitfld.long 0x1C 2. " SCSPDIS2 ,SPISCS2 pull control enable/disable" "No,Yes"
|
|
bitfld.long 0x1C 1. " SCSPDIS1 ,SPISCS1 pull control enable/disable" "No,Yes"
|
|
newline
|
|
bitfld.long 0x1C 0. " SCSPDIS0 ,SPISCS0 pull control enable/disable" "No,Yes"
|
|
line.long 0x20 "SPIPC8,SPI Pin Control Register 8"
|
|
bitfld.long 0x20 31. " SOMIPSEL7 ,SPISOMI[7] pull select" "Pull down,Pull up"
|
|
bitfld.long 0x20 30. " SOMIPSEL6 ,SPISOMI[6] pull select" "Pull down,Pull up"
|
|
bitfld.long 0x20 29. " SOMIPSEL5 ,SPISOMI[5] pull select" "Pull down,Pull up"
|
|
newline
|
|
bitfld.long 0x20 28. " SOMIPSEL4 ,SPISOMI[4] pull select" "Pull down,Pull up"
|
|
bitfld.long 0x20 27. " SOMIPSEL3 ,SPISOMI[3] pull select" "Pull down,Pull up"
|
|
bitfld.long 0x20 26. " SOMIPSEL2 ,SPISOMI[2] pull select" "Pull down,Pull up"
|
|
newline
|
|
bitfld.long 0x20 25. " SOMIPSEL1 ,SPISOMI[1] pull select" "Pull down,Pull up"
|
|
bitfld.long 0x20 24. " SOMIPSEL0 ,SPISOMI[0] pull select (mirror of bit 11)" "Pull down,Pull up"
|
|
bitfld.long 0x20 23. " SIMOPSEL7 ,SPISIMO[7] pull select" "Pull down,Pull up"
|
|
newline
|
|
bitfld.long 0x20 22. " SIMOPSEL6 ,SPISIMO[6] pull select" "Pull down,Pull up"
|
|
bitfld.long 0x20 21. " SIMOPSEL5 ,SPISIMO[5] pull select" "Pull down,Pull up"
|
|
bitfld.long 0x20 20. " SIMOPSEL4 ,SPISIMO[4] pull select" "Pull down,Pull up"
|
|
newline
|
|
bitfld.long 0x20 19. " SIMOPSEL3 ,SPISIMO[3] pull select" "Pull down,Pull up"
|
|
bitfld.long 0x20 18. " SIMOPSEL2 ,SPISIMO[2] pull select" "Pull down,Pull up"
|
|
bitfld.long 0x20 17. " SIMOPSEL1 ,SPISIMO[1] pull select" "Pull down,Pull up"
|
|
newline
|
|
bitfld.long 0x20 16. " SIMOPSEL0 ,SPISIMO[0] pull select (mirror of bit 10)" "Pull down,Pull up"
|
|
bitfld.long 0x20 11. " SOMIPSEL0 ,SPISOMI[0] pull select" "Pull down,Pull up"
|
|
bitfld.long 0x20 10. " SIMOPSEL0 ,SPISIMO[0] pull select" "Pull down,Pull up"
|
|
newline
|
|
bitfld.long 0x20 9. " CLKPSEL ,SPI clock pull select" "Pull down,Pull up"
|
|
bitfld.long 0x20 8. " ENAPSEL ,SPIENA pull select" "Pull down,Pull up"
|
|
bitfld.long 0x20 7. " SCSPSEL7 ,SPISCS7 pull select" "Pull down,Pull up"
|
|
newline
|
|
bitfld.long 0x20 6. " SCSPSEL6 ,SPISCS6 pull select" "Pull down,Pull up"
|
|
bitfld.long 0x20 5. " SCSPSEL5 ,SPISCS5 pull select" "Pull down,Pull up"
|
|
bitfld.long 0x20 4. " SCSPSEL4 ,SPISCS4 pull select" "Pull down,Pull up"
|
|
newline
|
|
bitfld.long 0x20 3. " SCSPSEL3 ,SPISCS3 pull select" "Pull down,Pull up"
|
|
bitfld.long 0x20 2. " SCSPSEL2 ,SPISCS2 pull select" "Pull down,Pull up"
|
|
bitfld.long 0x20 1. " SCSPSEL1 ,SPISCS1 pull select" "Pull down,Pull up"
|
|
newline
|
|
bitfld.long 0x20 0. " SCSPSEL0 ,SPISCS0 pull select" "Pull down,Pull up"
|
|
group.long 0x38++0x07
|
|
line.long 0x00 "SPIDAT0,SPI Transmit Data Register 0"
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,SPI transmit data"
|
|
line.long 0x04 "SPIDAT1,Transmit Data Register 1"
|
|
bitfld.long 0x04 28. " CSHOLD ,Chip select hold mode" "Inactive,Active"
|
|
bitfld.long 0x04 26. " WDEL ,Enable the delay counter at the end of the current transaction" "No delay,After transaction"
|
|
bitfld.long 0x04 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
newline
|
|
hexmask.long.byte 0x04 16.--23. 1. " CSNR ,Chip select number"
|
|
hexmask.long.word 0x04 0.--15. 1. " TXDATA ,Transfer data"
|
|
hgroup.long 0x40++0x03
|
|
hide.long 0x00 "SPIBUF,SPI Receive Buffer Register"
|
|
in
|
|
rgroup.long 0x44++0x03
|
|
line.long 0x00 "SPIEMU,SPI Emulation Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " EMU_RXDATA ,SPI receive data"
|
|
sif cpuis("TMS570LS0232")||cpuis("TMS570LS0714*")||cpuis("TMS570LS0914*")
|
|
group.long 0x48++0x03
|
|
line.long 0x00 "SPIDELAY,SPI Delay Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " C2TDELAY ,Chip-select-active to transmit-start delay"
|
|
hexmask.long.byte 0x00 16.--23. 1. " T2CDELAY ,Transmit-end-to-chip-select-inactive-delay"
|
|
hexmask.long.byte 0x00 8.--15. 1. " T2EDELAY ,Transmit-data-finished to ENA-pin-inactive time-out"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--7. 1. " C2EDELAY ,Chip-select-active to ENA-signal-active time-out"
|
|
else
|
|
rgroup.long 0x48++0x03
|
|
line.long 0x00 "SPIDELAY,SPI Delay Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " C2TDELAY ,Chip-select-active to transmit-start delay"
|
|
hexmask.long.byte 0x00 16.--23. 1. " T2CDELAY ,Transmit-end-to-chip-select-inactive-delay"
|
|
hexmask.long.byte 0x00 8.--15. 1. " T2EDELAY ,Transmit-data-finished to ENA-pin-inactive time-out"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--7. 1. " C2EDELAY ,Chip-select-active to ENA-signal-active time-out"
|
|
endif
|
|
group.long 0x4C++0x13
|
|
line.long 0x00 "SPIDEF,SPI Default Chip Select Register"
|
|
bitfld.long 0x00 7. " CSDEF7 ,Chip select default pattern 7" "0,1"
|
|
bitfld.long 0x00 6. " CSDEF6 ,Chip select default pattern 6" "0,1"
|
|
bitfld.long 0x00 5. " CSDEF5 ,Chip select default pattern 5" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. " CSDEF4 ,Chip select default pattern 4" "0,1"
|
|
bitfld.long 0x00 3. " CSDEF3 ,Chip select default pattern 3" "0,1"
|
|
bitfld.long 0x00 2. " CSDEF2 ,Chip select default pattern 2" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. " CSDEF1 ,Chip select default pattern 1" "0,1"
|
|
bitfld.long 0x00 0. " CSDEF0 ,Chip select default pattern 0" "0,1"
|
|
line.long 0x4 "SPIFMT0,SPI Data Format Register 0"
|
|
sif (cpuis("TMS570LS0332")||cpuis("TMS570LS0432")||cpuis("TMS570LS1114*")||cpuis("TMS570LS1115*")||cpuis("TMS570LS1224*")||cpuis("TMS570LS1225*")||cpuis("TMS570LS1227*")||cpuis("TMS570LS0232")||cpuis("TMS570LS0714*")||cpuis("TMS570LS0914*"))
|
|
hexmask.long.byte 0x4 24.--31. 1. " WDELAY ,Delay in between transmissions for data format 0"
|
|
else
|
|
bitfld.long 0x4 24.--29. " WDELAY ,Delay in between transmissions for data format 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
endif
|
|
bitfld.long 0x4 23. " PARPOL ,Parity polarity: even or odd" "Even,Odd"
|
|
newline
|
|
bitfld.long 0x4 22. " PARITYENA ,Parity enable for data format 0" "Disabled,Enabled"
|
|
bitfld.long 0x4 21. " WAITENA ,The master waits for the ENA signal from slave for data format 0" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x4 20. " SHIFTDIR ,Shift direction for data format $" "MSB,LSB"
|
|
sif (cpu()==("TMS570LS0332")||cpu()==("TMS570LS0432")||cpuis("TMS570LS1114*")||cpuis("TMS570LS1115*")||cpuis("TMS570LS1224*")||cpuis("TMS570LS1225*")||cpuis("TMS570LS1227*")||cpuis("TMS570LS0232")||cpuis("TMS570LS0714*")||cpuis("TMS570LS0914*"))
|
|
bitfld.long 0x4 19. " HDUPLEX_ENA0 ,Half Duplex transfer mode enable for Data Format 0" "Normal,RX/TX"
|
|
endif
|
|
newline
|
|
bitfld.long 0x4 18. " DISCSTIMERS ,Disable chip-select timers for this format" "No,Yes"
|
|
newline
|
|
bitfld.long 0x4 17. " POLARITY ,SPI data format 0 clock polarity" "Low,High"
|
|
bitfld.long 0x4 16. " PHASE ,SPI data format 0 clock delay" "Disabled,Enabled"
|
|
newline
|
|
hexmask.long.byte 0x4 8.--15. 1. " PRESCALE ,SPI data format 0 prescaler"
|
|
bitfld.long 0x4 0.--4. " CHARLEN ,SPI data format 0 data-word length" ",,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,?..."
|
|
line.long 0x8 "SPIFMT1,SPI Data Format Register 1"
|
|
sif (cpuis("TMS570LS0332")||cpuis("TMS570LS0432")||cpuis("TMS570LS1114*")||cpuis("TMS570LS1115*")||cpuis("TMS570LS1224*")||cpuis("TMS570LS1225*")||cpuis("TMS570LS1227*")||cpuis("TMS570LS0232")||cpuis("TMS570LS0714*")||cpuis("TMS570LS0914*"))
|
|
hexmask.long.byte 0x8 24.--31. 1. " WDELAY ,Delay in between transmissions for data format 1"
|
|
else
|
|
bitfld.long 0x8 24.--29. " WDELAY ,Delay in between transmissions for data format 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
endif
|
|
bitfld.long 0x8 23. " PARPOL ,Parity polarity: even or odd" "Even,Odd"
|
|
newline
|
|
bitfld.long 0x8 22. " PARITYENA ,Parity enable for data format 1" "Disabled,Enabled"
|
|
bitfld.long 0x8 21. " WAITENA ,The master waits for the ENA signal from slave for data format 1" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x8 20. " SHIFTDIR ,Shift direction for data format $" "MSB,LSB"
|
|
sif (cpu()==("TMS570LS0332")||cpu()==("TMS570LS0432")||cpuis("TMS570LS1114*")||cpuis("TMS570LS1115*")||cpuis("TMS570LS1224*")||cpuis("TMS570LS1225*")||cpuis("TMS570LS1227*")||cpuis("TMS570LS0232")||cpuis("TMS570LS0714*")||cpuis("TMS570LS0914*"))
|
|
bitfld.long 0x8 19. " HDUPLEX_ENA1 ,Half Duplex transfer mode enable for Data Format 1" "Normal,RX/TX"
|
|
endif
|
|
newline
|
|
bitfld.long 0x8 18. " DISCSTIMERS ,Disable chip-select timers for this format" "No,Yes"
|
|
newline
|
|
bitfld.long 0x8 17. " POLARITY ,SPI data format 1 clock polarity" "Low,High"
|
|
bitfld.long 0x8 16. " PHASE ,SPI data format 1 clock delay" "Disabled,Enabled"
|
|
newline
|
|
hexmask.long.byte 0x8 8.--15. 1. " PRESCALE ,SPI data format 1 prescaler"
|
|
bitfld.long 0x8 0.--4. " CHARLEN ,SPI data format 1 data-word length" ",,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,?..."
|
|
line.long 0xC "SPIFMT2,SPI Data Format Register 2"
|
|
sif (cpuis("TMS570LS0332")||cpuis("TMS570LS0432")||cpuis("TMS570LS1114*")||cpuis("TMS570LS1115*")||cpuis("TMS570LS1224*")||cpuis("TMS570LS1225*")||cpuis("TMS570LS1227*")||cpuis("TMS570LS0232")||cpuis("TMS570LS0714*")||cpuis("TMS570LS0914*"))
|
|
hexmask.long.byte 0xC 24.--31. 1. " WDELAY ,Delay in between transmissions for data format 2"
|
|
else
|
|
bitfld.long 0xC 24.--29. " WDELAY ,Delay in between transmissions for data format 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
endif
|
|
bitfld.long 0xC 23. " PARPOL ,Parity polarity: even or odd" "Even,Odd"
|
|
newline
|
|
bitfld.long 0xC 22. " PARITYENA ,Parity enable for data format 2" "Disabled,Enabled"
|
|
bitfld.long 0xC 21. " WAITENA ,The master waits for the ENA signal from slave for data format 2" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0xC 20. " SHIFTDIR ,Shift direction for data format $" "MSB,LSB"
|
|
sif (cpu()==("TMS570LS0332")||cpu()==("TMS570LS0432")||cpuis("TMS570LS1114*")||cpuis("TMS570LS1115*")||cpuis("TMS570LS1224*")||cpuis("TMS570LS1225*")||cpuis("TMS570LS1227*")||cpuis("TMS570LS0232")||cpuis("TMS570LS0714*")||cpuis("TMS570LS0914*"))
|
|
bitfld.long 0xC 19. " HDUPLEX_ENA2 ,Half Duplex transfer mode enable for Data Format 2" "Normal,RX/TX"
|
|
endif
|
|
newline
|
|
bitfld.long 0xC 18. " DISCSTIMERS ,Disable chip-select timers for this format" "No,Yes"
|
|
newline
|
|
bitfld.long 0xC 17. " POLARITY ,SPI data format 2 clock polarity" "Low,High"
|
|
bitfld.long 0xC 16. " PHASE ,SPI data format 2 clock delay" "Disabled,Enabled"
|
|
newline
|
|
hexmask.long.byte 0xC 8.--15. 1. " PRESCALE ,SPI data format 2 prescaler"
|
|
bitfld.long 0xC 0.--4. " CHARLEN ,SPI data format 2 data-word length" ",,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,?..."
|
|
line.long 0x10 "SPIFMT3,SPI Data Format Register 3"
|
|
sif (cpuis("TMS570LS0332")||cpuis("TMS570LS0432")||cpuis("TMS570LS1114*")||cpuis("TMS570LS1115*")||cpuis("TMS570LS1224*")||cpuis("TMS570LS1225*")||cpuis("TMS570LS1227*")||cpuis("TMS570LS0232")||cpuis("TMS570LS0714*")||cpuis("TMS570LS0914*"))
|
|
hexmask.long.byte 0x10 24.--31. 1. " WDELAY ,Delay in between transmissions for data format 3"
|
|
else
|
|
bitfld.long 0x10 24.--29. " WDELAY ,Delay in between transmissions for data format 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
endif
|
|
bitfld.long 0x10 23. " PARPOL ,Parity polarity: even or odd" "Even,Odd"
|
|
newline
|
|
bitfld.long 0x10 22. " PARITYENA ,Parity enable for data format 3" "Disabled,Enabled"
|
|
bitfld.long 0x10 21. " WAITENA ,The master waits for the ENA signal from slave for data format 3" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x10 20. " SHIFTDIR ,Shift direction for data format $" "MSB,LSB"
|
|
sif (cpu()==("TMS570LS0332")||cpu()==("TMS570LS0432")||cpuis("TMS570LS1114*")||cpuis("TMS570LS1115*")||cpuis("TMS570LS1224*")||cpuis("TMS570LS1225*")||cpuis("TMS570LS1227*")||cpuis("TMS570LS0232")||cpuis("TMS570LS0714*")||cpuis("TMS570LS0914*"))
|
|
bitfld.long 0x10 19. " HDUPLEX_ENA3 ,Half Duplex transfer mode enable for Data Format 3" "Normal,RX/TX"
|
|
endif
|
|
newline
|
|
bitfld.long 0x10 18. " DISCSTIMERS ,Disable chip-select timers for this format" "No,Yes"
|
|
newline
|
|
bitfld.long 0x10 17. " POLARITY ,SPI data format 3 clock polarity" "Low,High"
|
|
bitfld.long 0x10 16. " PHASE ,SPI data format 3 clock delay" "Disabled,Enabled"
|
|
newline
|
|
hexmask.long.byte 0x10 8.--15. 1. " PRESCALE ,SPI data format 3 prescaler"
|
|
bitfld.long 0x10 0.--4. " CHARLEN ,SPI data format 3 data-word length" ",,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,?..."
|
|
hgroup.long 0x60++0x03
|
|
hide.long 0x00 "TGINTVECT0,SPI Interrupt Vector Register 0 / MibSPI Transfer Group Interrupt Vector Register 0"
|
|
in
|
|
hgroup.long 0x64++0x03
|
|
hide.long 0x00 "TGINTVECT1,SPI Interrupt Vector Register 1 / MibSPI Transfer Group Interrupt Vector Register 1"
|
|
in
|
|
sif (cpu()!=("TMS570LS0332")&&cpu()!=("TMS570LS0432")&&!cpuis("TMS570LS0232"))
|
|
group.long 0x6C++0x07
|
|
line.long 0x00 "SPIPMCTRL,SPI Parallel/Modulo Mode Control Register"
|
|
bitfld.long 0x00 29. " MODCLKPOL3 ,Modulo mode SPICLK polarity" "Normal,Inverted"
|
|
bitfld.long 0x00 26.--28. " MMODE3 ,SPI/MibSPI data lines " "1,2,3,4,5,6,?..."
|
|
bitfld.long 0x00 24.--25. " PMODE3 ,Parallel mode data lines" "1,2,4,8"
|
|
newline
|
|
bitfld.long 0x00 21. " MODCLKPOL2 ,Modulo mode SPICLK polarity" "Normal,Inverted"
|
|
bitfld.long 0x00 18.--20. " MMODE2 ,SPI/MibSPI data lines " "1,2,3,4,5,6,?..."
|
|
bitfld.long 0x00 16.--17. " PMODE2 ,Parallel mode data lines" "1,2,4,8"
|
|
newline
|
|
bitfld.long 0x00 13. " MODCLKPOL1 ,Modulo mode SPICLK polarity" "Normal,Inverted"
|
|
bitfld.long 0x00 10.--12. " MMODE1 ,SPI/MibSPI data lines " "1,2,3,4,5,6,?..."
|
|
bitfld.long 0x00 8.--9. " PMODE1 ,Parallel mode data lines" "1,2,4,8"
|
|
newline
|
|
bitfld.long 0x00 5. " MODCLKPOL0 ,Modulo mode SPICLK polarity" "Normal,Inverted"
|
|
bitfld.long 0x00 2.--4. " MMODE0 ,SPI/MibSPI data lines " "1,2,3,4,5,6,?..."
|
|
bitfld.long 0x00 0.--1. " PMODE0 ,Parallel mode data lines" "1,2,4,8"
|
|
line.long 0x04 "MIBSPIE,MibSPI Enable Register"
|
|
bitfld.long 0x04 16. " RXRAMACCESS ,Receive-RAM access control" "Not writable,Accessible"
|
|
bitfld.long 0x04 0. " MIBSPIENA ,Multi-buffer mode enable" "Disabled,Enabled"
|
|
elif cpuis("TMS570LS0332")||cpuis("TMS570LS0432")||cpuis("TMS570LS0714*")||cpuis("TMS570LS0914*")||cpuis("TMS570LS0232")
|
|
group.long 0x70++0x03
|
|
line.long 0x00 "MIBSPIE,MibSPI Enable Register"
|
|
bitfld.long 0x00 16. " RXRAMACCESS ,Receive-RAM access control" "Not writable,Accessible"
|
|
bitfld.long 0x00 0. " MIBSPIENA ,Multi-buffer mode enable" "Disabled,Enabled"
|
|
endif
|
|
group.long 0x74++0x0F
|
|
line.long 0x00 "TGITENST,MibSPI Transfer Group Interrupt Enable Set Register"
|
|
bitfld.long 0x00 31. " SETINTENRDY15 ,TG interrupt set (enable) when transfer finished" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " SETINTENRDY14 ,TG interrupt set (enable) when transfer finished" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " SETINTENRDY13 ,TG interrupt set (enable) when transfer finished" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 28. " SETINTENRDY12 ,TG interrupt set (enable) when transfer finished" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " SETINTENRDY11 ,TG interrupt set (enable) when transfer finished" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " SETINTENRDY10 ,TG interrupt set (enable) when transfer finished" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 25. " SETINTENRDY9 ,TG interrupt set (enable) when transfer finished" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " SETINTENRDY8 ,TG interrupt set (enable) when transfer finished" "Disabled,Enabled"
|
|
bitfld.long 0x00 23. " SETINTENRDY7 ,TG interrupt set (enable) when transfer finished" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 22. " SETINTENRDY6 ,TG interrupt set (enable) when transfer finished" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " SETINTENRDY5 ,TG interrupt set (enable) when transfer finished" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " SETINTENRDY4 ,SETTG interrupt set (enable) when transfer finished" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 19. " SETINTENRDY3 ,TG interrupt set (enable) when transfer finished" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SETINTENRDY2 ,TG interrupt set (enable) when transfer finished" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SETINTENRDY1 ,TG interrupt set (enable) when transfer finished" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 16. " SETINTENRDY0 ,TG interrupt set (enable) when transfer finished" "Disabled,Enabled"
|
|
bitfld.long 0x00 15. " SETINTENSUS15 ,TG interrupt set (enabled) when transfer suspended" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " SETINTENSUS14 ,TG interrupt set (enabled) when transfer suspended" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 13. " SETINTENSUS13 ,TG interrupt set (enabled) when transfer suspended" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " SETINTENSUS12 ,TG interrupt set (enabled) when transfer suspended" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " SETINTENSUS11 ,TG interrupt set (enabled) when transfer suspended" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 10. " SETINTENSUS10 ,TG interrupt set (enabled) when transfer suspended" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " SETINTENSUS9 ,TG interrupt set (enabled) when transfer suspended" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " SETINTENSUS8 ,TG interrupt set (enabled) when transfer suspended" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 7. " SETINTENSUS7 ,TG interrupt set (enabled) when transfer suspended" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " SETINTENSUS6 ,TG interrupt set (enabled) when transfer suspended" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " SETINTENSUS5 ,TG interrupt set (enabled) when transfer suspended" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 4. " SETINTENSUS4 ,TG interrupt set (enabled) when transfer suspended" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " SETINTENSUS3 ,TG interrupt set (enabled) when transfer suspended" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " SETINTENSUS2 ,TG interrupt set (enabled) when transfer suspended" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 1. " SETINTENSUS1 ,TG interrupt set (enabled) when transfer suspended" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SETINTENSUS0 ,TG interrupt set (enabled) when transfer suspended" "Disabled,Enabled"
|
|
line.long 0x04 "TGITENCR,MibSPI Transfer Group Interrupt Enable Clear Register"
|
|
bitfld.long 0x04 31. " CLRINTENRDY15 ,TG interrupt clear (disabled) when transfer finished" "Disabled,Enabled"
|
|
bitfld.long 0x04 30. " CLRINTENRDY14 ,TG interrupt clear (disabled) when transfer finished" "Disabled,Enabled"
|
|
bitfld.long 0x04 29. " CLRINTENRDY13 ,TG interrupt clear (disabled) when transfer finished" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x04 28. " CLRINTENRDY12 ,TG interrupt clear (disabled) when transfer finished" "Disabled,Enabled"
|
|
bitfld.long 0x04 27. " CLRINTENRDY11 ,TG interrupt clear (disabled) when transfer finished" "Disabled,Enabled"
|
|
bitfld.long 0x04 26. " CLRINTENRDY10 ,TG interrupt clear (disabled) when transfer finished" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x04 25. " CLRINTENRDY9 ,TG interrupt clear (disabled) when transfer finished" "Disabled,Enabled"
|
|
bitfld.long 0x04 24. " CLRINTENRDY8 ,TG interrupt clear (disabled) when transfer finished" "Disabled,Enabled"
|
|
bitfld.long 0x04 23. " CLRINTENRDY7 ,TG interrupt clear (disabled) when transfer finished" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x04 22. " CLRINTENRDY6 ,TG interrupt clear (disabled) when transfer finished" "Disabled,Enabled"
|
|
bitfld.long 0x04 21. " CLRINTENRDY5 ,TG interrupt clear (disabled) when transfer finished" "Disabled,Enabled"
|
|
bitfld.long 0x04 20. " CLRINTENRDY4 ,TG interrupt clear (disabled) when transfer finished" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x04 19. " CLRINTENRDY3 ,TG interrupt clear (disabled) when transfer finished" "Disabled,Enabled"
|
|
bitfld.long 0x04 18. " CLRINTENRDY2 ,TG interrupt clear (disabled) when transfer finished" "Disabled,Enabled"
|
|
bitfld.long 0x04 17. " CLRINTENRDY1 ,TG interrupt clear (disabled) when transfer finished" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x04 16. " CLRINTENRDY0 ,TG interrupt clear (disabled) when transfer finished" "Disabled,Enabled"
|
|
bitfld.long 0x04 15. " CLRINTENSUS15 ,TG interrupt clear (disabled) when transfer suspended" "Disabled,Enabled"
|
|
bitfld.long 0x04 14. " CLRINTENSUS14 ,TG interrupt clear (disabled) when transfer suspended" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x04 13. " CLRINTENSUS13 ,TG interrupt clear (disabled) when transfer suspended" "Disabled,Enabled"
|
|
bitfld.long 0x04 12. " CLRINTENSUS12 ,TG interrupt clear (disabled) when transfer suspended" "Disabled,Enabled"
|
|
bitfld.long 0x04 11. " CLRINTENSUS11 ,TG interrupt clear (disabled) when transfer suspended" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x04 10. " CLRINTENSUS10 ,TG interrupt clear (disabled) when transfer suspended" "Disabled,Enabled"
|
|
bitfld.long 0x04 9. " CLRINTENSUS9 ,TG interrupt clear (disabled) when transfer suspended" "Disabled,Enabled"
|
|
bitfld.long 0x04 8. " CLRINTENSUS8 ,TG interrupt clear (disabled) when transfer suspended" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x04 7. " CLRINTENSUS7 ,TG interrupt clear (disabled) when transfer suspended" "Disabled,Enabled"
|
|
bitfld.long 0x04 6. " CLRINTENSUS6 ,TG interrupt clear (disabled) when transfer suspended" "Disabled,Enabled"
|
|
bitfld.long 0x04 5. " CLRINTENSUS5 ,TG interrupt clear (disabled) when transfer suspended" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x04 4. " CLRINTENSUS4 ,TG interrupt clear (disabled) when transfer suspended" "Disabled,Enabled"
|
|
bitfld.long 0x04 3. " CLRINTENSUS3 ,TG interrupt clear (disabled) when transfer suspended" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " CLRINTENSUS2 ,TG interrupt clear (disabled) when transfer suspended" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x04 1. " CLRINTENSUS1 ,TG interrupt clear (disabled) when transfer suspended" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " CLRINTENSUS0 ,TG interrupt clear (disabled) when transfer suspended" "Disabled,Enabled"
|
|
line.long 0x08 "TGITLVST,MibSPI Transfer Group Interrupt Level Set Register"
|
|
bitfld.long 0x08 31. " SETINTLVLRDY15 ,Transfer-group completed interrupt level set" "INT0,INT1"
|
|
bitfld.long 0x08 30. " SETINTLVLRDY14 ,Transfer-group completed interrupt level set" "INT0,INT1"
|
|
bitfld.long 0x08 29. " SETINTLVLRDY13 ,Transfer-group completed interrupt level set" "INT0,INT1"
|
|
newline
|
|
bitfld.long 0x08 28. " SETINTLVLRDY12 ,Transfer-group completed interrupt level set" "INT0,INT1"
|
|
bitfld.long 0x08 27. " SETINTLVLRDY11 ,Transfer-group completed interrupt level set" "INT0,INT1"
|
|
bitfld.long 0x08 26. " SETINTLVLRDY10 ,Transfer-group completed interrupt level set" "INT0,INT1"
|
|
newline
|
|
bitfld.long 0x08 25. " SETINTLVLRDY9 ,Transfer-group completed interrupt level set" "INT0,INT1"
|
|
bitfld.long 0x08 24. " SETINTLVLRDY8 ,Transfer-group completed interrupt level set" "INT0,INT1"
|
|
bitfld.long 0x08 23. " SETINTLVLRDY7 ,Transfer-group completed interrupt level set" "INT0,INT1"
|
|
newline
|
|
bitfld.long 0x08 22. " SETINTLVLRDY6 ,Transfer-group completed interrupt level set" "INT0,INT1"
|
|
bitfld.long 0x08 21. " SETINTLVLRDY5 ,Transfer-group completed interrupt level set" "INT0,INT1"
|
|
bitfld.long 0x08 20. " SETINTLVLRDY4 ,Transfer-group completed interrupt level set" "INT0,INT1"
|
|
newline
|
|
bitfld.long 0x08 19. " SETINTLVLRDY3 ,Transfer-group completed interrupt level set" "INT0,INT1"
|
|
bitfld.long 0x08 18. " SETINTLVLRDY2 ,Transfer-group completed interrupt level set" "INT0,INT1"
|
|
bitfld.long 0x08 17. " SETINTLVLRDY1 ,Transfer-group completed interrupt level set" "INT0,INT1"
|
|
newline
|
|
bitfld.long 0x08 16. " SETINTLVLRDY0 ,Transfer-group completed interrupt level set" "INT0,INT1"
|
|
bitfld.long 0x08 15. " SETINTLVLSUS15 ,Transfer-group suspended interrupt level set" "INT0,INT1"
|
|
bitfld.long 0x08 14. " SETINTLVLSUS14 ,Transfer-group suspended interrupt level set" "INT0,INT1"
|
|
newline
|
|
bitfld.long 0x08 13. " SETINTLVLSUS13 ,Transfer-group suspended interrupt level set" "INT0,INT1"
|
|
bitfld.long 0x08 12. " SETINTLVLSUS12 ,Transfer-group suspended interrupt level set" "INT0,INT1"
|
|
bitfld.long 0x08 11. " SETINTLVLSUS11 ,Transfer-group suspended interrupt level set" "INT0,INT1"
|
|
newline
|
|
bitfld.long 0x08 10. " SETINTLVLSUS10 ,Transfer-group suspended interrupt level set" "INT0,INT1"
|
|
bitfld.long 0x08 9. " SETINTLVLSUS9 ,Transfer-group suspended interrupt level set" "INT0,INT1"
|
|
bitfld.long 0x08 8. " SETINTLVLSUS8 ,Transfer-group suspended interrupt level set" "INT0,INT1"
|
|
newline
|
|
bitfld.long 0x08 7. " SETINTLVLSUS7 ,Transfer-group suspended interrupt level set" "INT0,INT1"
|
|
bitfld.long 0x08 6. " SETINTLVLSUS6 ,Transfer-group suspended interrupt level set" "INT0,INT1"
|
|
bitfld.long 0x08 5. " SETINTLVLSUS5 ,Transfer-group suspended interrupt level set" "INT0,INT1"
|
|
newline
|
|
bitfld.long 0x08 4. " SETINTLVLSUS4 ,Transfer-group suspended interrupt level set" "INT0,INT1"
|
|
bitfld.long 0x08 3. " SETINTLVLSUS3 ,Transfer-group suspended interrupt level set" "INT0,INT1"
|
|
bitfld.long 0x08 2. " SETINTLVLSUS2 ,Transfer-group suspended interrupt level set" "INT0,INT1"
|
|
newline
|
|
bitfld.long 0x08 1. " SETINTLVLSUS1 ,Transfer-group suspended interrupt level set" "INT0,INT1"
|
|
bitfld.long 0x08 0. " SETINTLVLSUS0 ,Transfer-group suspended interrupt level set" "INT0,INT1"
|
|
line.long 0x0C "TGITLVCR,MibSPI Transfer Group Interrupt Level Clear Register"
|
|
bitfld.long 0x0C 31. " CLRINTLVLRDY15 ,Transfer-group completed interrupt level clear" "INT0,INT1"
|
|
bitfld.long 0x0C 30. " CLRINTLVLRDY14 ,Transfer-group completed interrupt level clear" "INT0,INT1"
|
|
bitfld.long 0x0C 29. " CLRINTLVLRDY13 ,Transfer-group completed interrupt level clear" "INT0,INT1"
|
|
newline
|
|
bitfld.long 0x0C 28. " CLRINTLVLRDY12 ,Transfer-group completed interrupt level clear" "INT0,INT1"
|
|
bitfld.long 0x0C 27. " CLRINTLVLRDY11 ,Transfer-group completed interrupt level clear" "INT0,INT1"
|
|
bitfld.long 0x0C 26. " CLRINTLVLRDY10 ,Transfer-group completed interrupt level clear" "INT0,INT1"
|
|
newline
|
|
bitfld.long 0x0C 25. " CLRINTLVLRDY9 ,Transfer-group completed interrupt level clear" "INT0,INT1"
|
|
bitfld.long 0x0C 24. " CLRINTLVLRDY8 ,Transfer-group completed interrupt level clear" "INT0,INT1"
|
|
bitfld.long 0x0C 23. " CLRINTLVLRDY7 ,Transfer-group completed interrupt level clear" "INT0,INT1"
|
|
newline
|
|
bitfld.long 0x0C 22. " CLRINTLVLRDY6 ,Transfer-group completed interrupt level clear" "INT0,INT1"
|
|
bitfld.long 0x0C 21. " CLRINTLVLRDY5 ,Transfer-group completed interrupt level clear" "INT0,INT1"
|
|
bitfld.long 0x0C 20. " CLRINTLVLRDY4 ,Transfer-group completed interrupt level clear" "INT0,INT1"
|
|
newline
|
|
bitfld.long 0x0C 19. " CLRINTLVLRDY3 ,Transfer-group completed interrupt level clear" "INT0,INT1"
|
|
bitfld.long 0x0C 18. " CLRINTLVLRDY2 ,Transfer-group completed interrupt level clear" "INT0,INT1"
|
|
bitfld.long 0x0C 17. " CLRINTLVLRDY1 ,Transfer-group completed interrupt level clear" "INT0,INT1"
|
|
newline
|
|
bitfld.long 0x0C 16. " CLRINTLVLRDY0 ,Transfer-group completed interrupt level clear" "INT0,INT1"
|
|
bitfld.long 0x0C 15. " CLRINTLVLSUS15 ,Transfer group suspended interrupt level clear" "INT0,INT1"
|
|
bitfld.long 0x0C 14. " CLRINTLVLSUS14 ,Transfer group suspended interrupt level clear" "INT0,INT1"
|
|
newline
|
|
bitfld.long 0x0C 13. " CLRINTLVLSUS13 ,Transfer group suspended interrupt level clear" "INT0,INT1"
|
|
bitfld.long 0x0C 12. " CLRINTLVLSUS12 ,Transfer group suspended interrupt level clear" "INT0,INT1"
|
|
bitfld.long 0x0C 11. " CLRINTLVLSUS11 ,Transfer group suspended interrupt level clear" "INT0,INT1"
|
|
newline
|
|
bitfld.long 0x0C 10. " CLRINTLVLSUS10 ,Transfer group suspended interrupt level clear" "INT0,INT1"
|
|
bitfld.long 0x0C 9. " CLRINTLVLSUS9 ,Transfer group suspended interrupt level clear" "INT0,INT1"
|
|
bitfld.long 0x0C 8. " CLRINTLVLSUS8 ,Transfer group suspended interrupt level clear" "INT0,INT1"
|
|
newline
|
|
bitfld.long 0x0C 7. " CLRINTLVLSUS7 ,Transfer group suspended interrupt level clear" "INT0,INT1"
|
|
bitfld.long 0x0C 6. " CLRINTLVLSUS6 ,Transfer group suspended interrupt level clear" "INT0,INT1"
|
|
bitfld.long 0x0C 5. " CLRINTLVLSUS5 ,Transfer group suspended interrupt level clear" "INT0,INT1"
|
|
newline
|
|
bitfld.long 0x0C 4. " CLRINTLVLSUS4 ,Transfer group suspended interrupt level clear" "INT0,INT1"
|
|
bitfld.long 0x0C 3. " CLRINTLVLSUS3 ,Transfer group suspended interrupt level clear" "INT0,INT1"
|
|
bitfld.long 0x0C 2. " CLRINTLVLSUS2 ,Transfer group suspended interrupt level clear" "INT0,INT1"
|
|
newline
|
|
bitfld.long 0x0C 1. " CLRINTLVLSUS1 ,Transfer group suspended interrupt level clear" "INT0,INT1"
|
|
bitfld.long 0x0C 0. " CLRINTLVLSUS0 ,Transfer group suspended interrupt level clear" "INT0,INT1"
|
|
group.long 0x84++0x03
|
|
line.long 0x00 "TGITFLG,Transfer Group Interrupt Flag Register"
|
|
sif (cpu()==("TMS570LS0332")||cpu()==("TMS570LS0432")||cpuis("TMS570LS1114*")||cpuis("TMS570LS1115*")||cpuis("TMS570LS1224*")||cpuis("TMS570LS1225*")||cpuis("TMS570LS1227*")||cpuis("TMS570LS0232")||cpuis("TMS570LS0714*")||cpuis("TMS570LS0914*"))
|
|
bitfld.long 0x00 31. " INTFLGRDY[15] ,Transfer-group interrupt flag for a transfer-completed interrupt 15" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " INTFLGRDY[14] ,Transfer-group interrupt flag for a transfer-completed interrupt 14" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 29. " INTFLGRDY[13] ,Transfer-group interrupt flag for a transfer-completed interrupt 13" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " INTFLGRDY[12] ,Transfer-group interrupt flag for a transfer-completed interrupt 12" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 27. " INTFLGRDY[11] ,Transfer-group interrupt flag for a transfer-completed interrupt 11" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " INTFLGRDY[10] ,Transfer-group interrupt flag for a transfer-completed interrupt 10" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 25. " INTFLGRDY[9] ,Transfer-group interrupt flag for a transfer-completed interrupt 9" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " INTFLGRDY[8] ,Transfer-group interrupt flag for a transfer-completed interrupt 8" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 23. " INTFLGRDY[7] ,Transfer-group interrupt flag for a transfer-completed interrupt 7" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " INTFLGRDY[6] ,Transfer-group interrupt flag for a transfer-completed interrupt 6" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 21. " INTFLGRDY[5] ,Transfer-group interrupt flag for a transfer-completed interrupt 5" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " INTFLGRDY[4] ,Transfer-group interrupt flag for a transfer-completed interrupt 4" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 19. " INTFLGRDY[3] ,Transfer-group interrupt flag for a transfer-completed interrupt 3" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " INTFLGRDY[2] ,Transfer-group interrupt flag for a transfer-completed interrupt 2" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 17. " INTFLGRDY[1] ,Transfer-group interrupt flag for a transfer-completed interrupt 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " INTFLGRDY[0] ,Transfer-group interrupt flag for a transfer-completed interrupt 0" "Disabled,Enabled"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 15. " INTFLGSUS[15] ,Transfer-group interrupt flag for a transfer-suspend interrupt 15" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " INTFLGSUS[14] ,Transfer-group interrupt flag for a transfer-suspend interrupt 14" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 13. " INTFLGSUS[13] ,Transfer-group interrupt flag for a transfer-suspend interrupt 13" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " INTFLGSUS[12] ,Transfer-group interrupt flag for a transfer-suspend interrupt 12" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 11. " INTFLGSUS[11] ,Transfer-group interrupt flag for a transfer-suspend interrupt 11" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " INTFLGSUS[10] ,Transfer-group interrupt flag for a transfer-suspend interrupt 10" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 9. " INTFLGSUS[9] ,Transfer-group interrupt flag for a transfer-suspend interrupt 9" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " INTFLGSUS[8] ,Transfer-group interrupt flag for a transfer-suspend interrupt 8" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 7. " INTFLGSUS[7] ,Transfer-group interrupt flag for a transfer-suspend interrupt 7" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " INTFLGSUS[6] ,Transfer-group interrupt flag for a transfer-suspend interrupt 6" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 5. " INTFLGSUS[5] ,Transfer-group interrupt flag for a transfer-suspend interrupt 5" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " INTFLGSUS[4] ,Transfer-group interrupt flag for a transfer-suspend interrupt 4" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 3. " INTFLGSUS[3] ,Transfer-group interrupt flag for a transfer-suspend interrupt 3" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " INTFLGSUS[2] ,Transfer-group interrupt flag for a transfer-suspend interrupt 2" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 1. " INTFLGSUS[1] ,Transfer-group interrupt flag for a transfer-suspend interrupt 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " INTFLGSUS[0] ,Transfer-group interrupt flag for a transfer-suspend interrupt 0" "Disabled,Enabled"
|
|
group.long 0x90++0x47
|
|
line.long 0x00 "TICKCNT,Tick Count Register"
|
|
bitfld.long 0x00 31. " TICKENA ,Tick counter enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " RELOAD ,Pre-load the tick counter" "No effect,Reload"
|
|
bitfld.long 0x00 28.--29. " CLKCTRL ,Tick counter clock source control" "0,1,2,3"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TICKVALUE ,Initial value for the tick counter"
|
|
line.long 0x04 "LTGPEND,Last Transfer Group End Pointer Register"
|
|
bitfld.long 0x04 24.--28. " TGINSERVICE ,The TG number currently being serviced by the sequencer" "No TG,TG0,TG1,TG2,TG3,TG4,TG5,TG6,TG7,TG8,TG9,TG10,TG11,TG12,TG13,TG14,TG15,?..."
|
|
hexmask.long.byte 0x04 8.--14. 1. " LPEND ,Last TG end pointer"
|
|
line.long 0x8 "TG0CTRL,MibSPI Transfer Group Control Register 0"
|
|
bitfld.long 0x8 31. " TGENA ,TG enable" "Disabled,Enabled"
|
|
bitfld.long 0x8 30. " ONESHOT ,Single transfer for TG" "Disabled,Enabled"
|
|
bitfld.long 0x8 29. " PRST ,TG pointer reset mode" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x8 28. " TGTD ,TG triggered" "Not triggered,Triggered"
|
|
bitfld.long 0x8 20.--23. " TRGEVT ,Type of trigger event" "Never,Rising edge,Falling edge,Both edges,,High active,Low-active,Always,?..."
|
|
sif cpuis("TMS570LS0232")||cpuis("TMS570LS0714*")||cpuis("TMS570LS0914*")
|
|
bitfld.long 0x8 16.--19. " TRIGSRC ,Trigger source" "Disabled,EXT0,EXT1,EXT2,EXT3,EXT4,EXT5,EXT6,EXT7,EXT8,EXT9,EXT10,EXT11,EXT12,EXT13,TICK"
|
|
else
|
|
bitfld.long 0x8 16.--19. " TRIGSRC ,Trigger source" "Disabled,GIOA[0],GIOA[1],GIOA[2],GIOA[3],GIOA[4],GIOA[5],GIOA[6],GIOA[7],N2HET1[8],N2HET1[10],N2HET1[12],N2HET1[14],N2HET1[16],N2HET1[18],TICK"
|
|
endif
|
|
newline
|
|
hexmask.long.byte 0x8 8.--14. 0x01 " PSTART ,TG start address"
|
|
hexmask.long.byte 0x8 0.--6. 0x01 " PCURRENT ,Pointer to current buffer"
|
|
line.long 0xC "TG1CTRL,MibSPI Transfer Group Control Register 1"
|
|
bitfld.long 0xC 31. " TGENA ,TG enable" "Disabled,Enabled"
|
|
bitfld.long 0xC 30. " ONESHOT ,Single transfer for TG" "Disabled,Enabled"
|
|
bitfld.long 0xC 29. " PRST ,TG pointer reset mode" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0xC 28. " TGTD ,TG triggered" "Not triggered,Triggered"
|
|
bitfld.long 0xC 20.--23. " TRGEVT ,Type of trigger event" "Never,Rising edge,Falling edge,Both edges,,High active,Low-active,Always,?..."
|
|
sif cpuis("TMS570LS0232")||cpuis("TMS570LS0714*")||cpuis("TMS570LS0914*")
|
|
bitfld.long 0xC 16.--19. " TRIGSRC ,Trigger source" "Disabled,EXT0,EXT1,EXT2,EXT3,EXT4,EXT5,EXT6,EXT7,EXT8,EXT9,EXT10,EXT11,EXT12,EXT13,TICK"
|
|
else
|
|
bitfld.long 0xC 16.--19. " TRIGSRC ,Trigger source" "Disabled,GIOA[0],GIOA[1],GIOA[2],GIOA[3],GIOA[4],GIOA[5],GIOA[6],GIOA[7],N2HET1[8],N2HET1[10],N2HET1[12],N2HET1[14],N2HET1[16],N2HET1[18],TICK"
|
|
endif
|
|
newline
|
|
hexmask.long.byte 0xC 8.--14. 0x01 " PSTART ,TG start address"
|
|
hexmask.long.byte 0xC 0.--6. 0x01 " PCURRENT ,Pointer to current buffer"
|
|
line.long 0x10 "TG2CTRL,MibSPI Transfer Group Control Register 2"
|
|
bitfld.long 0x10 31. " TGENA ,TG enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 30. " ONESHOT ,Single transfer for TG" "Disabled,Enabled"
|
|
bitfld.long 0x10 29. " PRST ,TG pointer reset mode" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x10 28. " TGTD ,TG triggered" "Not triggered,Triggered"
|
|
bitfld.long 0x10 20.--23. " TRGEVT ,Type of trigger event" "Never,Rising edge,Falling edge,Both edges,,High active,Low-active,Always,?..."
|
|
sif cpuis("TMS570LS0232")||cpuis("TMS570LS0714*")||cpuis("TMS570LS0914*")
|
|
bitfld.long 0x10 16.--19. " TRIGSRC ,Trigger source" "Disabled,EXT0,EXT1,EXT2,EXT3,EXT4,EXT5,EXT6,EXT7,EXT8,EXT9,EXT10,EXT11,EXT12,EXT13,TICK"
|
|
else
|
|
bitfld.long 0x10 16.--19. " TRIGSRC ,Trigger source" "Disabled,GIOA[0],GIOA[1],GIOA[2],GIOA[3],GIOA[4],GIOA[5],GIOA[6],GIOA[7],N2HET1[8],N2HET1[10],N2HET1[12],N2HET1[14],N2HET1[16],N2HET1[18],TICK"
|
|
endif
|
|
newline
|
|
hexmask.long.byte 0x10 8.--14. 0x01 " PSTART ,TG start address"
|
|
hexmask.long.byte 0x10 0.--6. 0x01 " PCURRENT ,Pointer to current buffer"
|
|
line.long 0x14 "TG3CTRL,MibSPI Transfer Group Control Register 3"
|
|
bitfld.long 0x14 31. " TGENA ,TG enable" "Disabled,Enabled"
|
|
bitfld.long 0x14 30. " ONESHOT ,Single transfer for TG" "Disabled,Enabled"
|
|
bitfld.long 0x14 29. " PRST ,TG pointer reset mode" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x14 28. " TGTD ,TG triggered" "Not triggered,Triggered"
|
|
bitfld.long 0x14 20.--23. " TRGEVT ,Type of trigger event" "Never,Rising edge,Falling edge,Both edges,,High active,Low-active,Always,?..."
|
|
sif cpuis("TMS570LS0232")||cpuis("TMS570LS0714*")||cpuis("TMS570LS0914*")
|
|
bitfld.long 0x14 16.--19. " TRIGSRC ,Trigger source" "Disabled,EXT0,EXT1,EXT2,EXT3,EXT4,EXT5,EXT6,EXT7,EXT8,EXT9,EXT10,EXT11,EXT12,EXT13,TICK"
|
|
else
|
|
bitfld.long 0x14 16.--19. " TRIGSRC ,Trigger source" "Disabled,GIOA[0],GIOA[1],GIOA[2],GIOA[3],GIOA[4],GIOA[5],GIOA[6],GIOA[7],N2HET1[8],N2HET1[10],N2HET1[12],N2HET1[14],N2HET1[16],N2HET1[18],TICK"
|
|
endif
|
|
newline
|
|
hexmask.long.byte 0x14 8.--14. 0x01 " PSTART ,TG start address"
|
|
hexmask.long.byte 0x14 0.--6. 0x01 " PCURRENT ,Pointer to current buffer"
|
|
line.long 0x18 "TG4CTRL,MibSPI Transfer Group Control Register 4"
|
|
bitfld.long 0x18 31. " TGENA ,TG enable" "Disabled,Enabled"
|
|
bitfld.long 0x18 30. " ONESHOT ,Single transfer for TG" "Disabled,Enabled"
|
|
bitfld.long 0x18 29. " PRST ,TG pointer reset mode" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x18 28. " TGTD ,TG triggered" "Not triggered,Triggered"
|
|
bitfld.long 0x18 20.--23. " TRGEVT ,Type of trigger event" "Never,Rising edge,Falling edge,Both edges,,High active,Low-active,Always,?..."
|
|
sif cpuis("TMS570LS0232")||cpuis("TMS570LS0714*")||cpuis("TMS570LS0914*")
|
|
bitfld.long 0x18 16.--19. " TRIGSRC ,Trigger source" "Disabled,EXT0,EXT1,EXT2,EXT3,EXT4,EXT5,EXT6,EXT7,EXT8,EXT9,EXT10,EXT11,EXT12,EXT13,TICK"
|
|
else
|
|
bitfld.long 0x18 16.--19. " TRIGSRC ,Trigger source" "Disabled,GIOA[0],GIOA[1],GIOA[2],GIOA[3],GIOA[4],GIOA[5],GIOA[6],GIOA[7],N2HET1[8],N2HET1[10],N2HET1[12],N2HET1[14],N2HET1[16],N2HET1[18],TICK"
|
|
endif
|
|
newline
|
|
hexmask.long.byte 0x18 8.--14. 0x01 " PSTART ,TG start address"
|
|
hexmask.long.byte 0x18 0.--6. 0x01 " PCURRENT ,Pointer to current buffer"
|
|
line.long 0x1C "TG5CTRL,MibSPI Transfer Group Control Register 5"
|
|
bitfld.long 0x1C 31. " TGENA ,TG enable" "Disabled,Enabled"
|
|
bitfld.long 0x1C 30. " ONESHOT ,Single transfer for TG" "Disabled,Enabled"
|
|
bitfld.long 0x1C 29. " PRST ,TG pointer reset mode" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x1C 28. " TGTD ,TG triggered" "Not triggered,Triggered"
|
|
bitfld.long 0x1C 20.--23. " TRGEVT ,Type of trigger event" "Never,Rising edge,Falling edge,Both edges,,High active,Low-active,Always,?..."
|
|
sif cpuis("TMS570LS0232")||cpuis("TMS570LS0714*")||cpuis("TMS570LS0914*")
|
|
bitfld.long 0x1C 16.--19. " TRIGSRC ,Trigger source" "Disabled,EXT0,EXT1,EXT2,EXT3,EXT4,EXT5,EXT6,EXT7,EXT8,EXT9,EXT10,EXT11,EXT12,EXT13,TICK"
|
|
else
|
|
bitfld.long 0x1C 16.--19. " TRIGSRC ,Trigger source" "Disabled,GIOA[0],GIOA[1],GIOA[2],GIOA[3],GIOA[4],GIOA[5],GIOA[6],GIOA[7],N2HET1[8],N2HET1[10],N2HET1[12],N2HET1[14],N2HET1[16],N2HET1[18],TICK"
|
|
endif
|
|
newline
|
|
hexmask.long.byte 0x1C 8.--14. 0x01 " PSTART ,TG start address"
|
|
hexmask.long.byte 0x1C 0.--6. 0x01 " PCURRENT ,Pointer to current buffer"
|
|
line.long 0x20 "TG6CTRL,MibSPI Transfer Group Control Register 6"
|
|
bitfld.long 0x20 31. " TGENA ,TG enable" "Disabled,Enabled"
|
|
bitfld.long 0x20 30. " ONESHOT ,Single transfer for TG" "Disabled,Enabled"
|
|
bitfld.long 0x20 29. " PRST ,TG pointer reset mode" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x20 28. " TGTD ,TG triggered" "Not triggered,Triggered"
|
|
bitfld.long 0x20 20.--23. " TRGEVT ,Type of trigger event" "Never,Rising edge,Falling edge,Both edges,,High active,Low-active,Always,?..."
|
|
sif cpuis("TMS570LS0232")||cpuis("TMS570LS0714*")||cpuis("TMS570LS0914*")
|
|
bitfld.long 0x20 16.--19. " TRIGSRC ,Trigger source" "Disabled,EXT0,EXT1,EXT2,EXT3,EXT4,EXT5,EXT6,EXT7,EXT8,EXT9,EXT10,EXT11,EXT12,EXT13,TICK"
|
|
else
|
|
bitfld.long 0x20 16.--19. " TRIGSRC ,Trigger source" "Disabled,GIOA[0],GIOA[1],GIOA[2],GIOA[3],GIOA[4],GIOA[5],GIOA[6],GIOA[7],N2HET1[8],N2HET1[10],N2HET1[12],N2HET1[14],N2HET1[16],N2HET1[18],TICK"
|
|
endif
|
|
newline
|
|
hexmask.long.byte 0x20 8.--14. 0x01 " PSTART ,TG start address"
|
|
hexmask.long.byte 0x20 0.--6. 0x01 " PCURRENT ,Pointer to current buffer"
|
|
line.long 0x24 "TG7CTRL,MibSPI Transfer Group Control Register 7"
|
|
bitfld.long 0x24 31. " TGENA ,TG enable" "Disabled,Enabled"
|
|
bitfld.long 0x24 30. " ONESHOT ,Single transfer for TG" "Disabled,Enabled"
|
|
bitfld.long 0x24 29. " PRST ,TG pointer reset mode" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x24 28. " TGTD ,TG triggered" "Not triggered,Triggered"
|
|
bitfld.long 0x24 20.--23. " TRGEVT ,Type of trigger event" "Never,Rising edge,Falling edge,Both edges,,High active,Low-active,Always,?..."
|
|
sif cpuis("TMS570LS0232")||cpuis("TMS570LS0714*")||cpuis("TMS570LS0914*")
|
|
bitfld.long 0x24 16.--19. " TRIGSRC ,Trigger source" "Disabled,EXT0,EXT1,EXT2,EXT3,EXT4,EXT5,EXT6,EXT7,EXT8,EXT9,EXT10,EXT11,EXT12,EXT13,TICK"
|
|
else
|
|
bitfld.long 0x24 16.--19. " TRIGSRC ,Trigger source" "Disabled,GIOA[0],GIOA[1],GIOA[2],GIOA[3],GIOA[4],GIOA[5],GIOA[6],GIOA[7],N2HET1[8],N2HET1[10],N2HET1[12],N2HET1[14],N2HET1[16],N2HET1[18],TICK"
|
|
endif
|
|
newline
|
|
hexmask.long.byte 0x24 8.--14. 0x01 " PSTART ,TG start address"
|
|
hexmask.long.byte 0x24 0.--6. 0x01 " PCURRENT ,Pointer to current buffer"
|
|
line.long 0x28 "TG8CTRL,MibSPI Transfer Group Control Register 8"
|
|
bitfld.long 0x28 31. " TGENA ,TG enable" "Disabled,Enabled"
|
|
bitfld.long 0x28 30. " ONESHOT ,Single transfer for TG" "Disabled,Enabled"
|
|
bitfld.long 0x28 29. " PRST ,TG pointer reset mode" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x28 28. " TGTD ,TG triggered" "Not triggered,Triggered"
|
|
bitfld.long 0x28 20.--23. " TRGEVT ,Type of trigger event" "Never,Rising edge,Falling edge,Both edges,,High active,Low-active,Always,?..."
|
|
sif cpuis("TMS570LS0232")||cpuis("TMS570LS0714*")||cpuis("TMS570LS0914*")
|
|
bitfld.long 0x28 16.--19. " TRIGSRC ,Trigger source" "Disabled,EXT0,EXT1,EXT2,EXT3,EXT4,EXT5,EXT6,EXT7,EXT8,EXT9,EXT10,EXT11,EXT12,EXT13,TICK"
|
|
else
|
|
bitfld.long 0x28 16.--19. " TRIGSRC ,Trigger source" "Disabled,GIOA[0],GIOA[1],GIOA[2],GIOA[3],GIOA[4],GIOA[5],GIOA[6],GIOA[7],N2HET1[8],N2HET1[10],N2HET1[12],N2HET1[14],N2HET1[16],N2HET1[18],TICK"
|
|
endif
|
|
newline
|
|
hexmask.long.byte 0x28 8.--14. 0x01 " PSTART ,TG start address"
|
|
hexmask.long.byte 0x28 0.--6. 0x01 " PCURRENT ,Pointer to current buffer"
|
|
line.long 0x2C "TG9CTRL,MibSPI Transfer Group Control Register 9"
|
|
bitfld.long 0x2C 31. " TGENA ,TG enable" "Disabled,Enabled"
|
|
bitfld.long 0x2C 30. " ONESHOT ,Single transfer for TG" "Disabled,Enabled"
|
|
bitfld.long 0x2C 29. " PRST ,TG pointer reset mode" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x2C 28. " TGTD ,TG triggered" "Not triggered,Triggered"
|
|
bitfld.long 0x2C 20.--23. " TRGEVT ,Type of trigger event" "Never,Rising edge,Falling edge,Both edges,,High active,Low-active,Always,?..."
|
|
sif cpuis("TMS570LS0232")||cpuis("TMS570LS0714*")||cpuis("TMS570LS0914*")
|
|
bitfld.long 0x2C 16.--19. " TRIGSRC ,Trigger source" "Disabled,EXT0,EXT1,EXT2,EXT3,EXT4,EXT5,EXT6,EXT7,EXT8,EXT9,EXT10,EXT11,EXT12,EXT13,TICK"
|
|
else
|
|
bitfld.long 0x2C 16.--19. " TRIGSRC ,Trigger source" "Disabled,GIOA[0],GIOA[1],GIOA[2],GIOA[3],GIOA[4],GIOA[5],GIOA[6],GIOA[7],N2HET1[8],N2HET1[10],N2HET1[12],N2HET1[14],N2HET1[16],N2HET1[18],TICK"
|
|
endif
|
|
newline
|
|
hexmask.long.byte 0x2C 8.--14. 0x01 " PSTART ,TG start address"
|
|
hexmask.long.byte 0x2C 0.--6. 0x01 " PCURRENT ,Pointer to current buffer"
|
|
line.long 0x30 "TG10CTRL,MibSPI Transfer Group Control Register 10"
|
|
bitfld.long 0x30 31. " TGENA ,TG enable" "Disabled,Enabled"
|
|
bitfld.long 0x30 30. " ONESHOT ,Single transfer for TG" "Disabled,Enabled"
|
|
bitfld.long 0x30 29. " PRST ,TG pointer reset mode" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x30 28. " TGTD ,TG triggered" "Not triggered,Triggered"
|
|
bitfld.long 0x30 20.--23. " TRGEVT ,Type of trigger event" "Never,Rising edge,Falling edge,Both edges,,High active,Low-active,Always,?..."
|
|
sif cpuis("TMS570LS0232")||cpuis("TMS570LS0714*")||cpuis("TMS570LS0914*")
|
|
bitfld.long 0x30 16.--19. " TRIGSRC ,Trigger source" "Disabled,EXT0,EXT1,EXT2,EXT3,EXT4,EXT5,EXT6,EXT7,EXT8,EXT9,EXT10,EXT11,EXT12,EXT13,TICK"
|
|
else
|
|
bitfld.long 0x30 16.--19. " TRIGSRC ,Trigger source" "Disabled,GIOA[0],GIOA[1],GIOA[2],GIOA[3],GIOA[4],GIOA[5],GIOA[6],GIOA[7],N2HET1[8],N2HET1[10],N2HET1[12],N2HET1[14],N2HET1[16],N2HET1[18],TICK"
|
|
endif
|
|
newline
|
|
hexmask.long.byte 0x30 8.--14. 0x01 " PSTART ,TG start address"
|
|
hexmask.long.byte 0x30 0.--6. 0x01 " PCURRENT ,Pointer to current buffer"
|
|
line.long 0x34 "TG11CTRL,MibSPI Transfer Group Control Register 11"
|
|
bitfld.long 0x34 31. " TGENA ,TG enable" "Disabled,Enabled"
|
|
bitfld.long 0x34 30. " ONESHOT ,Single transfer for TG" "Disabled,Enabled"
|
|
bitfld.long 0x34 29. " PRST ,TG pointer reset mode" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x34 28. " TGTD ,TG triggered" "Not triggered,Triggered"
|
|
bitfld.long 0x34 20.--23. " TRGEVT ,Type of trigger event" "Never,Rising edge,Falling edge,Both edges,,High active,Low-active,Always,?..."
|
|
sif cpuis("TMS570LS0232")||cpuis("TMS570LS0714*")||cpuis("TMS570LS0914*")
|
|
bitfld.long 0x34 16.--19. " TRIGSRC ,Trigger source" "Disabled,EXT0,EXT1,EXT2,EXT3,EXT4,EXT5,EXT6,EXT7,EXT8,EXT9,EXT10,EXT11,EXT12,EXT13,TICK"
|
|
else
|
|
bitfld.long 0x34 16.--19. " TRIGSRC ,Trigger source" "Disabled,GIOA[0],GIOA[1],GIOA[2],GIOA[3],GIOA[4],GIOA[5],GIOA[6],GIOA[7],N2HET1[8],N2HET1[10],N2HET1[12],N2HET1[14],N2HET1[16],N2HET1[18],TICK"
|
|
endif
|
|
newline
|
|
hexmask.long.byte 0x34 8.--14. 0x01 " PSTART ,TG start address"
|
|
hexmask.long.byte 0x34 0.--6. 0x01 " PCURRENT ,Pointer to current buffer"
|
|
line.long 0x38 "TG12CTRL,MibSPI Transfer Group Control Register 12"
|
|
bitfld.long 0x38 31. " TGENA ,TG enable" "Disabled,Enabled"
|
|
bitfld.long 0x38 30. " ONESHOT ,Single transfer for TG" "Disabled,Enabled"
|
|
bitfld.long 0x38 29. " PRST ,TG pointer reset mode" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x38 28. " TGTD ,TG triggered" "Not triggered,Triggered"
|
|
bitfld.long 0x38 20.--23. " TRGEVT ,Type of trigger event" "Never,Rising edge,Falling edge,Both edges,,High active,Low-active,Always,?..."
|
|
sif cpuis("TMS570LS0232")||cpuis("TMS570LS0714*")||cpuis("TMS570LS0914*")
|
|
bitfld.long 0x38 16.--19. " TRIGSRC ,Trigger source" "Disabled,EXT0,EXT1,EXT2,EXT3,EXT4,EXT5,EXT6,EXT7,EXT8,EXT9,EXT10,EXT11,EXT12,EXT13,TICK"
|
|
else
|
|
bitfld.long 0x38 16.--19. " TRIGSRC ,Trigger source" "Disabled,GIOA[0],GIOA[1],GIOA[2],GIOA[3],GIOA[4],GIOA[5],GIOA[6],GIOA[7],N2HET1[8],N2HET1[10],N2HET1[12],N2HET1[14],N2HET1[16],N2HET1[18],TICK"
|
|
endif
|
|
newline
|
|
hexmask.long.byte 0x38 8.--14. 0x01 " PSTART ,TG start address"
|
|
hexmask.long.byte 0x38 0.--6. 0x01 " PCURRENT ,Pointer to current buffer"
|
|
line.long 0x3C "TG13CTRL,MibSPI Transfer Group Control Register 13"
|
|
bitfld.long 0x3C 31. " TGENA ,TG enable" "Disabled,Enabled"
|
|
bitfld.long 0x3C 30. " ONESHOT ,Single transfer for TG" "Disabled,Enabled"
|
|
bitfld.long 0x3C 29. " PRST ,TG pointer reset mode" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x3C 28. " TGTD ,TG triggered" "Not triggered,Triggered"
|
|
bitfld.long 0x3C 20.--23. " TRGEVT ,Type of trigger event" "Never,Rising edge,Falling edge,Both edges,,High active,Low-active,Always,?..."
|
|
sif cpuis("TMS570LS0232")||cpuis("TMS570LS0714*")||cpuis("TMS570LS0914*")
|
|
bitfld.long 0x3C 16.--19. " TRIGSRC ,Trigger source" "Disabled,EXT0,EXT1,EXT2,EXT3,EXT4,EXT5,EXT6,EXT7,EXT8,EXT9,EXT10,EXT11,EXT12,EXT13,TICK"
|
|
else
|
|
bitfld.long 0x3C 16.--19. " TRIGSRC ,Trigger source" "Disabled,GIOA[0],GIOA[1],GIOA[2],GIOA[3],GIOA[4],GIOA[5],GIOA[6],GIOA[7],N2HET1[8],N2HET1[10],N2HET1[12],N2HET1[14],N2HET1[16],N2HET1[18],TICK"
|
|
endif
|
|
newline
|
|
hexmask.long.byte 0x3C 8.--14. 0x01 " PSTART ,TG start address"
|
|
hexmask.long.byte 0x3C 0.--6. 0x01 " PCURRENT ,Pointer to current buffer"
|
|
line.long 0x40 "TG14CTRL,MibSPI Transfer Group Control Register 14"
|
|
bitfld.long 0x40 31. " TGENA ,TG enable" "Disabled,Enabled"
|
|
bitfld.long 0x40 30. " ONESHOT ,Single transfer for TG" "Disabled,Enabled"
|
|
bitfld.long 0x40 29. " PRST ,TG pointer reset mode" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x40 28. " TGTD ,TG triggered" "Not triggered,Triggered"
|
|
bitfld.long 0x40 20.--23. " TRGEVT ,Type of trigger event" "Never,Rising edge,Falling edge,Both edges,,High active,Low-active,Always,?..."
|
|
sif cpuis("TMS570LS0232")||cpuis("TMS570LS0714*")||cpuis("TMS570LS0914*")
|
|
bitfld.long 0x40 16.--19. " TRIGSRC ,Trigger source" "Disabled,EXT0,EXT1,EXT2,EXT3,EXT4,EXT5,EXT6,EXT7,EXT8,EXT9,EXT10,EXT11,EXT12,EXT13,TICK"
|
|
else
|
|
bitfld.long 0x40 16.--19. " TRIGSRC ,Trigger source" "Disabled,GIOA[0],GIOA[1],GIOA[2],GIOA[3],GIOA[4],GIOA[5],GIOA[6],GIOA[7],N2HET1[8],N2HET1[10],N2HET1[12],N2HET1[14],N2HET1[16],N2HET1[18],TICK"
|
|
endif
|
|
newline
|
|
hexmask.long.byte 0x40 8.--14. 0x01 " PSTART ,TG start address"
|
|
hexmask.long.byte 0x40 0.--6. 0x01 " PCURRENT ,Pointer to current buffer"
|
|
line.long 0x44 "TG15CTRL,MibSPI Transfer Group Control Register 15"
|
|
bitfld.long 0x44 31. " TGENA ,TG enable" "Disabled,Enabled"
|
|
bitfld.long 0x44 30. " ONESHOT ,Single transfer for TG" "Disabled,Enabled"
|
|
bitfld.long 0x44 29. " PRST ,TG pointer reset mode" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x44 28. " TGTD ,TG triggered" "Not triggered,Triggered"
|
|
bitfld.long 0x44 20.--23. " TRGEVT ,Type of trigger event" "Never,Rising edge,Falling edge,Both edges,,High active,Low-active,Always,?..."
|
|
sif cpuis("TMS570LS0232")||cpuis("TMS570LS0714*")||cpuis("TMS570LS0914*")
|
|
bitfld.long 0x44 16.--19. " TRIGSRC ,Trigger source" "Disabled,EXT0,EXT1,EXT2,EXT3,EXT4,EXT5,EXT6,EXT7,EXT8,EXT9,EXT10,EXT11,EXT12,EXT13,TICK"
|
|
else
|
|
bitfld.long 0x44 16.--19. " TRIGSRC ,Trigger source" "Disabled,GIOA[0],GIOA[1],GIOA[2],GIOA[3],GIOA[4],GIOA[5],GIOA[6],GIOA[7],N2HET1[8],N2HET1[10],N2HET1[12],N2HET1[14],N2HET1[16],N2HET1[18],TICK"
|
|
endif
|
|
newline
|
|
hexmask.long.byte 0x44 8.--14. 0x01 " PSTART ,TG start address"
|
|
hexmask.long.byte 0x44 0.--6. 0x01 " PCURRENT ,Pointer to current buffer"
|
|
sif (cpu()!=("TMS570LS0332")&&cpu()!=("TMS570LS0432")&&!cpuis("TMS570LS0232"))
|
|
group.long 0xD8++0x1F
|
|
line.long 0x0 "DMA0CTRL,MibSPI DMA Channel Control Register 1"
|
|
bitfld.long 0x0 31. " ONESHOT ,Auto-disable of DMA channel after ICOUNT+1 transfers" "0,1"
|
|
hexmask.long.byte 0x0 24.--30. 1. " BUFID ,Buffer utilized for DMA transfer"
|
|
bitfld.long 0x0 20.--23. " RXDMA_MAP ,Each MibSPI DMA channel can be linked to two physical DMA" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x0 16.--19. " TXDMA_MAP ,Each MibSPI DMA channel can be linked to two physical DMA" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x0 15. " RXDMAENA ,Receive data DMA channel enable" "Disabled,Enabled"
|
|
bitfld.long 0x0 14. " TXDMAENA ,Transmit data DMA channel enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x0 13. " NOBRK ,Non-interleaved DMA block transfer" "Not performed,Performed"
|
|
bitfld.long 0x0 8.--12. " ICOUNT ,Initial count of DMA transfers" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32"
|
|
bitfld.long 0x0 6. " COUNTBIT17 ,17th bit of the COUNT field of DMAxCOUNT register" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0.--5. " COUNT ,Actual number of remaining DMA transfers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
line.long 0x4 "DMA1CTRL,MibSPI DMA Channel Control Register 1"
|
|
bitfld.long 0x4 31. " ONESHOT ,Auto-disable of DMA channel after ICOUNT+1 transfers" "0,1"
|
|
hexmask.long.byte 0x4 24.--30. 1. " BUFID ,Buffer utilized for DMA transfer"
|
|
bitfld.long 0x4 20.--23. " RXDMA_MAP ,Each MibSPI DMA channel can be linked to two physical DMA" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x4 16.--19. " TXDMA_MAP ,Each MibSPI DMA channel can be linked to two physical DMA" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x4 15. " RXDMAENA ,Receive data DMA channel enable" "Disabled,Enabled"
|
|
bitfld.long 0x4 14. " TXDMAENA ,Transmit data DMA channel enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x4 13. " NOBRK ,Non-interleaved DMA block transfer" "Not performed,Performed"
|
|
bitfld.long 0x4 8.--12. " ICOUNT ,Initial count of DMA transfers" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32"
|
|
bitfld.long 0x4 6. " COUNTBIT17 ,17th bit of the COUNT field of DMAxCOUNT register" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0.--5. " COUNT ,Actual number of remaining DMA transfers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
line.long 0x8 "DMA2CTRL,MibSPI DMA Channel Control Register 1"
|
|
bitfld.long 0x8 31. " ONESHOT ,Auto-disable of DMA channel after ICOUNT+1 transfers" "0,1"
|
|
hexmask.long.byte 0x8 24.--30. 1. " BUFID ,Buffer utilized for DMA transfer"
|
|
bitfld.long 0x8 20.--23. " RXDMA_MAP ,Each MibSPI DMA channel can be linked to two physical DMA" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x8 16.--19. " TXDMA_MAP ,Each MibSPI DMA channel can be linked to two physical DMA" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x8 15. " RXDMAENA ,Receive data DMA channel enable" "Disabled,Enabled"
|
|
bitfld.long 0x8 14. " TXDMAENA ,Transmit data DMA channel enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x8 13. " NOBRK ,Non-interleaved DMA block transfer" "Not performed,Performed"
|
|
bitfld.long 0x8 8.--12. " ICOUNT ,Initial count of DMA transfers" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32"
|
|
bitfld.long 0x8 6. " COUNTBIT17 ,17th bit of the COUNT field of DMAxCOUNT register" "0,1"
|
|
newline
|
|
bitfld.long 0x8 0.--5. " COUNT ,Actual number of remaining DMA transfers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
line.long 0xC "DMA3CTRL,MibSPI DMA Channel Control Register 1"
|
|
bitfld.long 0xC 31. " ONESHOT ,Auto-disable of DMA channel after ICOUNT+1 transfers" "0,1"
|
|
hexmask.long.byte 0xC 24.--30. 1. " BUFID ,Buffer utilized for DMA transfer"
|
|
bitfld.long 0xC 20.--23. " RXDMA_MAP ,Each MibSPI DMA channel can be linked to two physical DMA" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0xC 16.--19. " TXDMA_MAP ,Each MibSPI DMA channel can be linked to two physical DMA" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0xC 15. " RXDMAENA ,Receive data DMA channel enable" "Disabled,Enabled"
|
|
bitfld.long 0xC 14. " TXDMAENA ,Transmit data DMA channel enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0xC 13. " NOBRK ,Non-interleaved DMA block transfer" "Not performed,Performed"
|
|
bitfld.long 0xC 8.--12. " ICOUNT ,Initial count of DMA transfers" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32"
|
|
bitfld.long 0xC 6. " COUNTBIT17 ,17th bit of the COUNT field of DMAxCOUNT register" "0,1"
|
|
newline
|
|
bitfld.long 0xC 0.--5. " COUNT ,Actual number of remaining DMA transfers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
line.long 0x10 "DMA4CTRL,MibSPI DMA Channel Control Register 1"
|
|
bitfld.long 0x10 31. " ONESHOT ,Auto-disable of DMA channel after ICOUNT+1 transfers" "0,1"
|
|
hexmask.long.byte 0x10 24.--30. 1. " BUFID ,Buffer utilized for DMA transfer"
|
|
bitfld.long 0x10 20.--23. " RXDMA_MAP ,Each MibSPI DMA channel can be linked to two physical DMA" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x10 16.--19. " TXDMA_MAP ,Each MibSPI DMA channel can be linked to two physical DMA" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x10 15. " RXDMAENA ,Receive data DMA channel enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 14. " TXDMAENA ,Transmit data DMA channel enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x10 13. " NOBRK ,Non-interleaved DMA block transfer" "Not performed,Performed"
|
|
bitfld.long 0x10 8.--12. " ICOUNT ,Initial count of DMA transfers" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32"
|
|
bitfld.long 0x10 6. " COUNTBIT17 ,17th bit of the COUNT field of DMAxCOUNT register" "0,1"
|
|
newline
|
|
bitfld.long 0x10 0.--5. " COUNT ,Actual number of remaining DMA transfers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
line.long 0x14 "DMA5CTRL,MibSPI DMA Channel Control Register 1"
|
|
bitfld.long 0x14 31. " ONESHOT ,Auto-disable of DMA channel after ICOUNT+1 transfers" "0,1"
|
|
hexmask.long.byte 0x14 24.--30. 1. " BUFID ,Buffer utilized for DMA transfer"
|
|
bitfld.long 0x14 20.--23. " RXDMA_MAP ,Each MibSPI DMA channel can be linked to two physical DMA" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x14 16.--19. " TXDMA_MAP ,Each MibSPI DMA channel can be linked to two physical DMA" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x14 15. " RXDMAENA ,Receive data DMA channel enable" "Disabled,Enabled"
|
|
bitfld.long 0x14 14. " TXDMAENA ,Transmit data DMA channel enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x14 13. " NOBRK ,Non-interleaved DMA block transfer" "Not performed,Performed"
|
|
bitfld.long 0x14 8.--12. " ICOUNT ,Initial count of DMA transfers" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32"
|
|
bitfld.long 0x14 6. " COUNTBIT17 ,17th bit of the COUNT field of DMAxCOUNT register" "0,1"
|
|
newline
|
|
bitfld.long 0x14 0.--5. " COUNT ,Actual number of remaining DMA transfers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
line.long 0x18 "DMA6CTRL,MibSPI DMA Channel Control Register 1"
|
|
bitfld.long 0x18 31. " ONESHOT ,Auto-disable of DMA channel after ICOUNT+1 transfers" "0,1"
|
|
hexmask.long.byte 0x18 24.--30. 1. " BUFID ,Buffer utilized for DMA transfer"
|
|
bitfld.long 0x18 20.--23. " RXDMA_MAP ,Each MibSPI DMA channel can be linked to two physical DMA" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x18 16.--19. " TXDMA_MAP ,Each MibSPI DMA channel can be linked to two physical DMA" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x18 15. " RXDMAENA ,Receive data DMA channel enable" "Disabled,Enabled"
|
|
bitfld.long 0x18 14. " TXDMAENA ,Transmit data DMA channel enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x18 13. " NOBRK ,Non-interleaved DMA block transfer" "Not performed,Performed"
|
|
bitfld.long 0x18 8.--12. " ICOUNT ,Initial count of DMA transfers" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32"
|
|
bitfld.long 0x18 6. " COUNTBIT17 ,17th bit of the COUNT field of DMAxCOUNT register" "0,1"
|
|
newline
|
|
bitfld.long 0x18 0.--5. " COUNT ,Actual number of remaining DMA transfers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
line.long 0x1C "DMA7CTRL,MibSPI DMA Channel Control Register 1"
|
|
bitfld.long 0x1C 31. " ONESHOT ,Auto-disable of DMA channel after ICOUNT+1 transfers" "0,1"
|
|
hexmask.long.byte 0x1C 24.--30. 1. " BUFID ,Buffer utilized for DMA transfer"
|
|
bitfld.long 0x1C 20.--23. " RXDMA_MAP ,Each MibSPI DMA channel can be linked to two physical DMA" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x1C 16.--19. " TXDMA_MAP ,Each MibSPI DMA channel can be linked to two physical DMA" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x1C 15. " RXDMAENA ,Receive data DMA channel enable" "Disabled,Enabled"
|
|
bitfld.long 0x1C 14. " TXDMAENA ,Transmit data DMA channel enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x1C 13. " NOBRK ,Non-interleaved DMA block transfer" "Not performed,Performed"
|
|
bitfld.long 0x1C 8.--12. " ICOUNT ,Initial count of DMA transfers" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32"
|
|
bitfld.long 0x1C 6. " COUNTBIT17 ,17th bit of the COUNT field of DMAxCOUNT register" "0,1"
|
|
newline
|
|
bitfld.long 0x1C 0.--5. " COUNT ,Actual number of remaining DMA transfers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
group.long 0xF8++0x1F
|
|
line.long 0x0 "DMA0 COUNT,MibSPI DMA0 COUNT Register"
|
|
hexmask.long.word 0x0 16.--31. 1. " ICOUNT0 ,Initial number of DMA transfers"
|
|
hexmask.long.word 0x0 0.--15. 1. " COUNT0 ,The actual number of remaining DMA transfers"
|
|
line.long 0x4 "DMA1 COUNT,MibSPI DMA1 COUNT Register"
|
|
hexmask.long.word 0x4 16.--31. 1. " ICOUNT1 ,Initial number of DMA transfers"
|
|
hexmask.long.word 0x4 0.--15. 1. " COUNT1 ,The actual number of remaining DMA transfers"
|
|
line.long 0x8 "DMA2 COUNT,MibSPI DMA2 COUNT Register"
|
|
hexmask.long.word 0x8 16.--31. 1. " ICOUNT2 ,Initial number of DMA transfers"
|
|
hexmask.long.word 0x8 0.--15. 1. " COUNT2 ,The actual number of remaining DMA transfers"
|
|
line.long 0xC "DMA3 COUNT,MibSPI DMA3 COUNT Register"
|
|
hexmask.long.word 0xC 16.--31. 1. " ICOUNT3 ,Initial number of DMA transfers"
|
|
hexmask.long.word 0xC 0.--15. 1. " COUNT3 ,The actual number of remaining DMA transfers"
|
|
line.long 0x10 "DMA4 COUNT,MibSPI DMA4 COUNT Register"
|
|
hexmask.long.word 0x10 16.--31. 1. " ICOUNT4 ,Initial number of DMA transfers"
|
|
hexmask.long.word 0x10 0.--15. 1. " COUNT4 ,The actual number of remaining DMA transfers"
|
|
line.long 0x14 "DMA5 COUNT,MibSPI DMA5 COUNT Register"
|
|
hexmask.long.word 0x14 16.--31. 1. " ICOUNT5 ,Initial number of DMA transfers"
|
|
hexmask.long.word 0x14 0.--15. 1. " COUNT5 ,The actual number of remaining DMA transfers"
|
|
line.long 0x18 "DMA6 COUNT,MibSPI DMA6 COUNT Register"
|
|
hexmask.long.word 0x18 16.--31. 1. " ICOUNT6 ,Initial number of DMA transfers"
|
|
hexmask.long.word 0x18 0.--15. 1. " COUNT6 ,The actual number of remaining DMA transfers"
|
|
line.long 0x1C "DMA7 COUNT,MibSPI DMA7 COUNT Register"
|
|
hexmask.long.word 0x1C 16.--31. 1. " ICOUNT7 ,Initial number of DMA transfers"
|
|
hexmask.long.word 0x1C 0.--15. 1. " COUNT7 ,The actual number of remaining DMA transfers"
|
|
group.long 0x118++0x03
|
|
line.long 0x00 "DMACNTLEN,MibSPI DMACNTLEN Register"
|
|
bitfld.long 0x00 0. " LARGECOUNT ,Counters select" "DMAxCTRL,DMAxCOUNT"
|
|
endif
|
|
group.long 0x120++0x03
|
|
line.long 0x00 "UERRCTRL,Uncorrectable Parity Error Control Register"
|
|
bitfld.long 0x00 8. " PTESTEN ,Parity memory test enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--3. " EDEN ,Error detection enable" "Enabled,Enabled,Enabled,Enabled,Enabled,Disabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled"
|
|
group.long 0x124++0x03
|
|
line.long 0x00 "UERRSTAT,Uncorrectable Parity Error Status Register"
|
|
eventfld.long 0x00 1. " EDFLG1 ,Uncorrectable parity error detection flag" "Not occurred,Occurred"
|
|
eventfld.long 0x00 0. " EDFLG0 ,Uncorrectable parity error detection flag" "Not occurred,Occurred"
|
|
hgroup.long 0x128++0x03
|
|
hide.long 0x00 "UERRADDR1,Uncorrectable Parity Error Address Register"
|
|
in
|
|
hgroup.long 0x12C++0x03
|
|
hide.long 0x00 "UERRADDR0,Uncorrectable Parity Error Address Register"
|
|
in
|
|
hgroup.long 0x130++0x03
|
|
hide.long 0x00 "RXOVRN_BUF_ADDR,Receive RAM Overrun Buffer Address Register"
|
|
in
|
|
sif cpuis("TMS570LS0714*")||cpuis("TMS570LS0914*")||cpuis("TMS570LS0232")
|
|
if (((per.l.be(ad:0xFFF7FA00+0x134))&0x2)==0x2)
|
|
group.long 0x134++0x03
|
|
line.long 0x00 "IOLPBKTSTCR,SPI IO Loopback Test Control Register"
|
|
bitfld.long 0x00 24. " SCSFAILFLG ,Failure on SPISCS pin compare during analog loopback" "Not occurred,Occurred"
|
|
bitfld.long 0x00 20. " CTRL_BITERR ,Controls inducing of BITERR during I/O loopback test mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " CTRL_DESYNC ,Controls inducing of the desync error during I/O loopback test mode" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 18. " CTRL_PARERR ,Controls inducing of parity errors during I/O loopback test mode" "No error,Error"
|
|
bitfld.long 0x00 17. " CTRL_TIMEOUT ,Controls inducing of the timeout error during I/O loopbacK test mode" "No error,Error"
|
|
bitfld.long 0x00 16. " CTRL_DLENERR ,Controls inducing of the data length error during I/O loopback test mode" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 8.--11. " IOLPBKTSTENA ,Module I/O loopback test enable key" "Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Enabled,Disabled,Disabled,Disabled,Disabled,Disabled"
|
|
sif cpuis("TMS570LS0232")
|
|
bitfld.long 0x00 3.--5. " ERRSCSPIN ,Inject error on chip-select pin number" "/SPISCS[0],/SPISCS[1],/SPISCS[2],/SPISCS[3],?..."
|
|
else
|
|
bitfld.long 0x00 3.--5. " ERRSCSPIN ,Inject error on chip-select pin number" "/SPISCS[0],/SPISCS[1],/SPISCS[2],/SPISCS[3],/SPISCS[4],/SPISCS[5],/SPISCS[6],/SPISCS[7]"
|
|
endif
|
|
bitfld.long 0x00 2. " CTRLSCSPINERR ,Enable/disable the injection of an error on the SPISCS[3:0] pins" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 1. " LPBK_TYPE ,Module I/O loopback type (analog/digital)" "Digital,Analog"
|
|
bitfld.long 0x00 0. " RXP_ENA ,Enable analog loopback through the receive pin" "Transmit,Receive"
|
|
else
|
|
group.long 0x134++0x03
|
|
line.long 0x00 "IOLPBKTSTCR,SPI IO Loopback Test Control Register"
|
|
bitfld.long 0x00 24. " SCSFAILFLG ,Failure on SPISCS pin compare during analog loopback" "Not occurred,Occurred"
|
|
bitfld.long 0x00 20. " CTRL_BITERR ,Controls inducing of BITERR during I/O loopback test mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " CTRL_DESYNC ,Controls inducing of the desync error during I/O loopback test mode" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 18. " CTRL_PARERR ,Controls inducing of parity errors during I/O loopback test mode" "No error,Error"
|
|
bitfld.long 0x00 17. " CTRL_TIMEOUT ,Controls inducing of the timeout error during I/O loopbacK test mode" "No error,Error"
|
|
bitfld.long 0x00 16. " CTRL_DLENERR ,Controls inducing of the data length error during I/O loopback test mode" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 8.--11. " IOLPBKTSTENA ,Module I/O loopback test enable key" "Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Enabled,Disabled,Disabled,Disabled,Disabled,Disabled"
|
|
sif cpuis("TMS570LS0232")
|
|
bitfld.long 0x00 3.--5. " ERRSCSPIN ,Inject error on chip-select pin number" "/SPISCS[0],/SPISCS[1],/SPISCS[2],/SPISCS[3],?..."
|
|
else
|
|
bitfld.long 0x00 3.--5. " ERRSCSPIN ,Inject error on chip-select pin number" "/SPISCS[0],/SPISCS[1],/SPISCS[2],/SPISCS[3],/SPISCS[4],/SPISCS[5],/SPISCS[6],/SPISCS[7]"
|
|
endif
|
|
bitfld.long 0x00 2. " CTRLSCSPINERR ,Enable/disable the injection of an error on the SPISCS[3:0] pins" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 1. " LPBK_TYPE ,Module I/O loopback type (analog/digital)" "Digital,Analog"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0xFFF7FA00+0x134))&0x2)==0x2)
|
|
group.long 0x134++0x03
|
|
line.long 0x00 "IOLPBKTSTCR,SPI IO Loopback Test Control Register"
|
|
bitfld.long 0x00 24. " SCSFAILFLG ,Failure on SPISCS pin compare during analog loopback" "Not occurred,Occurred"
|
|
bitfld.long 0x00 20. " CTRL_BITERR ,Controls inducing of BITERR during I/O loopback test mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " CTRL_DESYNC ,Controls inducing of the desync error during I/O loopback test mode" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 18. " CTRL_PARERR ,Controls inducing of parity errors during I/O loopback test mode" "No error,Error"
|
|
bitfld.long 0x00 17. " CTRL_TIMEOUT ,Controls inducing of the timeout error during I/O loopbacK test mode" "No error,Error"
|
|
bitfld.long 0x00 16. " CTRL_DLENERR ,Controls inducing of the data length error during I/O loopback test mode" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 8.--11. " IOLPBKTSTENA ,Module I/O loopback test enable key" "Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Enabled,Disabled,Disabled,Disabled,Disabled,Disabled"
|
|
bitfld.long 0x00 3.--5. " ERRSCSPIN ,Inject error on chip-select pin number" "/SPISCS[0],/SPISCS[1],/SPISCS[2],/SPISCS[3],/SPISCS[4],/SPISCS[5],/SPISCS[6],/SPISCS[7]"
|
|
bitfld.long 0x00 2. " CTRLSCSPINERR ,Enable/disable the injection of an error on the SPISCS[3:0] pins" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 1. " LPBK_TYPE ,Module I/O loopback type (analog/digital)" "Digital,Analog"
|
|
bitfld.long 0x00 0. " RXP_ENA ,Enable analog loopback through the receive pin" "Transmit,Receive"
|
|
else
|
|
group.long 0x134++0x03
|
|
line.long 0x00 "IOLPBKTSTCR,SPI IO Loopback Test Control Register"
|
|
bitfld.long 0x00 24. " SCSFAILFLG ,Failure on SPISCS pin compare during analog loopback" "Not occurred,Occurred"
|
|
bitfld.long 0x00 20. " CTRL_BITERR ,Controls inducing of BITERR during I/O loopback test mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " CTRL_DESYNC ,Controls inducing of the desync error during I/O loopback test mode" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 18. " CTRL_PARERR ,Controls inducing of parity errors during I/O loopback test mode" "No error,Error"
|
|
bitfld.long 0x00 17. " CTRL_TIMEOUT ,Controls inducing of the timeout error during I/O loopbacK test mode" "No error,Error"
|
|
bitfld.long 0x00 16. " CTRL_DLENERR ,Controls inducing of the data length error during I/O loopback test mode" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 8.--11. " IOLPBKTSTENA ,Module I/O loopback test enable key" "Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Enabled,Disabled,Disabled,Disabled,Disabled,Disabled"
|
|
bitfld.long 0x00 3.--5. " ERRSCSPIN ,Inject error on chip-select pin number" "/SPISCS[0],/SPISCS[1],/SPISCS[2],/SPISCS[3],/SPISCS[4],/SPISCS[5],/SPISCS[6],/SPISCS[7]"
|
|
bitfld.long 0x00 2. " CTRLSCSPINERR ,Enable/disable the injection of an error on the SPISCS[3:0] pins" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 1. " LPBK_TYPE ,Module I/O loopback type (analog/digital)" "Digital,Analog"
|
|
endif
|
|
endif
|
|
sif (cpu()=="TMS570LC4357"||cpu()==("TMS570LS0332")||cpu()==("TMS570LS0432")||cpuis("TMS570LS1114*")||cpuis("TMS570LS1115*")||cpuis("TMS570LS1224*")||cpuis("TMS570LS1225*")||cpuis("TMS570LS1227*")||cpuis("TMS570LS0232")||cpuis("TMS570LS0714*")||cpuis("TMS570LS0914*"))
|
|
width 21.
|
|
newline
|
|
group.long 0x138++0x07
|
|
line.long 0x00 "EXTENDED_PRESCALE_1, SPI Extended Prescale Register 1"
|
|
hexmask.long.word 0x00 16.--26. 1. " EPRESCALE_FMT1 , Extended Prescale value for SPIFMT1"
|
|
hexmask.long.word 0x00 0.--10. 1. " EPRESCALE_FMT0 , Extended Prescale value for SPIFMT0"
|
|
line.long 0x04 "EXTENDED_PRESCALE_2, SPI Extended Prescale Register 2"
|
|
hexmask.long.word 0x04 16.--26. 1. " EPRESCALE_FMT3 , Extended Prescale value for SPIFMT3"
|
|
hexmask.long.word 0x04 0.--10. 1. " EPRESCALE_FMT2 , Extended Prescale value for SPIFMT2"
|
|
endif
|
|
sif !cpuis("TMS570LS0232")&&!cpuis("TMS570LS0714*")&&!cpuis("TMS570LS0914*")
|
|
sif (cpu()=="TMS570LC4357"||cpu()==("TMS570LS0332")||cpu()==("TMS570LS0432")||cpuis("TMS570LS1114*")||cpuis("TMS570LS1115*")||cpuis("TMS570LS1224*")||cpuis("TMS570LS1225*")||cpuis("TMS570LS1227*"))
|
|
sif cpuis("TMS570LC4357")
|
|
group.long 0x140++0x03
|
|
line.long 0x00 "ECCDIAG_CTRL, ECC Diagnostic Control register"
|
|
bitfld.long 0x00 0.--3. " ECCDIAG_EN , ECC Diagnostic mode Enable Key bits" "Disabled,Disabled,Disabled,Disabled,Disabled,Enabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled"
|
|
endif
|
|
if ((per.l(ad:0xFFF7FA00+0x140)&0x5)==0x5)
|
|
group.long 0x144++0x03
|
|
line.long 0x00 "ECCDIAG_STAT, ECC Diagnostic Status register"
|
|
eventfld.long 0x00 17. " DEFLG[1] , Double bit Error is detected for RXRAM" "No error,Error"
|
|
eventfld.long 0x00 16. " DEFLG[0] , Double bit Error is detected for TXRAM" "No error,Error"
|
|
eventfld.long 0x00 1. " SEFLG[1] , Single bit Error is detected for RXRAM" "No error,Error"
|
|
eventfld.long 0x00 0. " SEFLG[0] , Single bit Error is detected for TXRAM" "No error,Error"
|
|
else
|
|
hgroup.long 0x144++0x03
|
|
hide.long 0x00 "ECCDIAG_STAT, ECC Diagnostic Status register"
|
|
in
|
|
endif
|
|
hgroup.long 0x148++0x03
|
|
hide.long 0x00 "SBERRADDR1, Single Bit Error Address Register - RXRAM"
|
|
in
|
|
hgroup.long 0x14C++0x03
|
|
hide.long 0x00 "SBERRADDR0, Single Bit Error Address Register - TXRAM"
|
|
in
|
|
endif
|
|
endif
|
|
sif cpuis("TMS570LS0232")||cpuis("TMS570LS0714*")||cpuis("TMS570LS0914*")
|
|
endian.be
|
|
endif
|
|
width 0xB
|
|
tree.end
|
|
tree "MibSPI5"
|
|
base ad:0xFFF7FC00
|
|
width 17.
|
|
sif cpuis("TMS570LS0232")||cpuis("TMS570LS0714*")||cpuis("TMS570LS0914*")
|
|
endian.be
|
|
endif
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "SPIGCR0,SPI Global Control Register 0"
|
|
bitfld.long 0x00 0. " NRESET ,Reset bit for the module" "No reset,Reset"
|
|
group.long 0x04++0x0F
|
|
line.long 0x00 "SPIGCR1,SPI Global Control Register 1"
|
|
bitfld.long 0x00 24. " SPIEN ,SPI enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " LOOPBACK ,Internal loop-back test mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " POWERDOWN ,SPI state machine enters a power-down state" "No power-down,Power-down"
|
|
newline
|
|
bitfld.long 0x00 1. " CLKMOD ,Clock mode" "External,Internally"
|
|
bitfld.long 0x00 0. " MASTER ,SPISIMO/SPISOMI pin direction determination" "Input/output,Output/input"
|
|
line.long 0x04 "SPIINT0,SPI Interrupt Register"
|
|
bitfld.long 0x04 24. " ENABLEHIGHZ ,SPIENA pin high-impedance enable" "Inactive,Active"
|
|
bitfld.long 0x04 16. " DMAREQEN ,DMA request enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 9. " TXINTENA ,TX interrupt flag enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x04 8. " RXINTENA ,RX interrupt flag enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 6. " RXOVRNINTENA ,Overrun interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 4. " BITERRENA ,Enables interrupt on bit error" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x04 3. " DESYNCENA ,Enables interrupt on desynchronized slave" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " PARERRENA ,Enables interrupt-on-parity-error" "Disabled,Enabled"
|
|
bitfld.long 0x04 1. " TIMEOUTENA ,Enables interrupt on ENA signal time-out" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x04 0. " DLENERRENA ,Data length error interrupt enable" "Disabled,Enabled"
|
|
line.long 0x08 "SPILVL,SPI Interrupt Level Register"
|
|
bitfld.long 0x08 9. " TXINTLVL ,Transmit interrupt level" "INT0,INT1"
|
|
bitfld.long 0x08 8. " RXINTLVL ,Receive interrupt level" "INT0,INT1"
|
|
sif !cpuis("TMS570LS0232")
|
|
bitfld.long 0x08 6. " RXOVRNINTLVL ,Receive overrun interrupt level" "INT0,INT1"
|
|
endif
|
|
newline
|
|
bitfld.long 0x08 4. " BITERRLVL ,Bit error interrupt level" "INT0,INT1"
|
|
bitfld.long 0x08 3. " DESYNCLVL ,Desynchronized slave interrupt level (master mode only)" "INT0,INT1"
|
|
bitfld.long 0x08 2. " PARERRLVL ,Parity error interrupt level" "INT0,INT1"
|
|
newline
|
|
bitfld.long 0x08 1. " TIMEOUTLVL ,SPIENA pin time-out interrupt level" "INT0,INT1"
|
|
bitfld.long 0x08 0. " DLENERRLVL ,Data length error interrupt level (line) select" "INT0,INT1"
|
|
line.long 0x0C "SPIFLG,SPI Flag Register"
|
|
bitfld.long 0x0C 24. " BUFINITACTIVE ,Indicates the status of multi-buffer initialization process" "Completed,Not completed"
|
|
bitfld.long 0x0C 9. " TXINTFLG ,Transmitter-empty interrupt flag" "No interrupt,Interrupt"
|
|
eventfld.long 0x0C 8. " RXINTFLG ,Receiver-full interrupt flag" "No interrupt,Interrupt"
|
|
newline
|
|
eventfld.long 0x0C 6. " RXOVRNINTFLG ,Overrun interrupt enable" "Disabled,Enabled"
|
|
eventfld.long 0x0C 4. " BITERRFLG ,Enables interrupt on bit error" "Disabled,Enabled"
|
|
eventfld.long 0x0C 3. " DESYNCFLG ,Enables interrupt on desynchronized slave" "No interrupt,Interrupt"
|
|
newline
|
|
eventfld.long 0x0C 2. " PARITYERRFLG ,Enables interrupt-on-parity-error" "No error,Error"
|
|
eventfld.long 0x0C 1. " TIMEOUTFLG ,Enables interrupt on ENA signal time-out" "No interrupt,Interrupt"
|
|
eventfld.long 0x0C 0. " DLENERRFLG ,Data length error interrupt enable" "No interrupt,Interrupt"
|
|
group.long 0x14++0x23
|
|
line.long 0x00 "SPIPC0,SPI Pin Control Register 0"
|
|
sif !cpuis("TMS570LS0232")&&!cpuis("TMS570LS0332")&&!cpuis("TMS570LS0432")
|
|
bitfld.long 0x00 31. " SOMIFUN7 ,SPISOMI[7] pin function" "GIO,SPI"
|
|
bitfld.long 0x00 30. " SOMIFUN6 ,SPISOMI[6] pin function" "GIO,SPI"
|
|
bitfld.long 0x00 29. " SOMIFUN5 ,SPISOMI[5] pin function" "GIO,SPI"
|
|
newline
|
|
bitfld.long 0x00 28. " SOMIFUN4 ,SPISOMI[4] pin function" "GIO,SPI"
|
|
bitfld.long 0x00 27. " SOMIFUN3 ,SPISOMI[3] pin function" "GIO,SPI"
|
|
bitfld.long 0x00 26. " SOMIFUN2 ,SPISOMI[2] pin function" "GIO,SPI"
|
|
newline
|
|
bitfld.long 0x00 25. " SOMIFUN1 ,SPISOMI[1] pin function" "GIO,SPI"
|
|
bitfld.long 0x00 24. " SOMIFUN0 ,SPISOMI[0] pin function (mirror of bit 11)" "GIO,SPI"
|
|
bitfld.long 0x00 23. " SIMOFUN7 ,SPISIMO[7] pin function" "GIO,SPI"
|
|
newline
|
|
bitfld.long 0x00 22. " SIMOFUN6 ,SPISIMO[6] pin function" "GIO,SPI"
|
|
bitfld.long 0x00 21. " SIMOFUN5 ,SPISIMO[5] pin function" "GIO,SPI"
|
|
bitfld.long 0x00 20. " SIMOFUN4 ,SPISIMO[4] pin function" "GIO,SPI"
|
|
newline
|
|
bitfld.long 0x00 19. " SIMOFUN3 ,SPISIMO[3] pin function" "GIO,SPI"
|
|
bitfld.long 0x00 18. " SIMOFUN2 ,SPISIMO[2] pin function" "GIO,SPI"
|
|
bitfld.long 0x00 17. " SIMOFUN1 ,SPISIMO[1] pin function" "GIO,SPI"
|
|
newline
|
|
bitfld.long 0x00 16. " SIMOFUN0 ,SPISIMO[0] pin function (mirror of bit 10)" "GIO,SPI"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 11. " SOMIFUN0 ,SPISOMI[0] pin function" "GIO,SPI"
|
|
bitfld.long 0x00 10. " SIMOFUN0 ,SPISIMO[0] pin function" "GIO,SPI"
|
|
newline
|
|
bitfld.long 0x00 9. " CLKFUN ,SPI clock function" "GIO,SPI"
|
|
bitfld.long 0x00 8. " ENAFUN ,SPIENA function" "GIO,SPI"
|
|
bitfld.long 0x00 7. " SCSFUN7 ,SPISCS7 function 7" "GIO,SPI"
|
|
newline
|
|
bitfld.long 0x00 6. " SCSFUN6 ,SPISCS6 function 6" "GIO,SPI"
|
|
bitfld.long 0x00 5. " SCSFUN5 ,SPISCS5 function 5" "GIO,SPI"
|
|
bitfld.long 0x00 4. " SCSFUN4 ,SPISCS4 function 4" "GIO,SPI"
|
|
newline
|
|
bitfld.long 0x00 3. " SCSFUN3 ,SPISCS3 function 3" "GIO,SPI"
|
|
bitfld.long 0x00 2. " SCSFUN2 ,SPISCS2 function 2" "GIO,SPI"
|
|
bitfld.long 0x00 1. " SCSFUN1 ,SPISCS1 function 1" "GIO,SPI"
|
|
newline
|
|
bitfld.long 0x00 0. " SCSFUN0 ,SPISCS0 function 0" "GIO,SPI"
|
|
line.long 0x04 "SPIPC1,SPI Pin Control Register 1"
|
|
bitfld.long 0x04 31. " SOMIDIR7 ,SPISOMI[7] pin direction" "GIO,SPI"
|
|
bitfld.long 0x04 30. " SOMIDIR6 ,SPISOMI[6] pin direction" "GIO,SPI"
|
|
bitfld.long 0x04 29. " SOMIDIR5 ,SPISOMI[5] pin direction" "GIO,SPI"
|
|
newline
|
|
bitfld.long 0x04 28. " SOMIDIR4 ,SPISOMI[4] pin direction" "GIO,SPI"
|
|
bitfld.long 0x04 27. " SOMIDIR3 ,SPISOMI[3] pin direction" "GIO,SPI"
|
|
bitfld.long 0x04 26. " SOMIDIR2 ,SPISOMI[2] pin direction" "GIO,SPI"
|
|
newline
|
|
bitfld.long 0x04 25. " SOMIDIR1 ,SPISOMI[1] pin direction" "GIO,SPI"
|
|
bitfld.long 0x04 24. " SOMIDIR0 ,SPISOMI[0] pin direction (mirror of bit 11)" "GIO,SPI"
|
|
bitfld.long 0x04 23. " SIMODIR7 ,SPISIMO[7] pin direction" "GIO,SPI"
|
|
newline
|
|
bitfld.long 0x04 22. " SIMODIR6 ,SPISIMO[6] pin direction" "GIO,SPI"
|
|
bitfld.long 0x04 21. " SIMODIR5 ,SPISIMO[5] pin direction" "GIO,SPI"
|
|
bitfld.long 0x04 20. " SIMODIR4 ,SPISIMO[4] pin direction" "GIO,SPI"
|
|
newline
|
|
bitfld.long 0x04 19. " SIMODIR3 ,SPISIMO[3] pin direction" "GIO,SPI"
|
|
bitfld.long 0x04 18. " SIMODIR2 ,SPISIMO[2] pin direction" "GIO,SPI"
|
|
bitfld.long 0x04 17. " SIMODIR1 ,SPISIMO[1] pin direction" "GIO,SPI"
|
|
newline
|
|
bitfld.long 0x04 16. " SIMODIR0 ,SPISIMO[0] pin direction (mirror of bit 10)" "GIO,SPI"
|
|
bitfld.long 0x04 11. " SOMIDIR0 ,SPISOMI[0] pin direction" "GIO,SPI"
|
|
bitfld.long 0x04 10. " SIMODIR0 ,SPISIMO[0] pin direction" "GIO,SPI"
|
|
newline
|
|
bitfld.long 0x04 9. " CLKDIR ,SPI clock direction" "GIO,SPI"
|
|
bitfld.long 0x04 8. " ENADIR ,SPIENA direction" "GIO,SPI"
|
|
bitfld.long 0x04 7. " SCSDIR7 ,SPISCS7 direction 7" "GIO,SPI"
|
|
newline
|
|
bitfld.long 0x04 6. " SCSDIR6 ,SPISCS6 direction 6" "GIO,SPI"
|
|
bitfld.long 0x04 5. " SCSDIR5 ,SPISCS5 direction 5" "GIO,SPI"
|
|
bitfld.long 0x04 4. " SCSDIR4 ,SPISCS4 direction 4" "GIO,SPI"
|
|
newline
|
|
bitfld.long 0x04 3. " SCSDIR3 ,SPISCS3 direction 3" "GIO,SPI"
|
|
bitfld.long 0x04 2. " SCSDIR2 ,SPISCS2 direction 2" "GIO,SPI"
|
|
bitfld.long 0x04 1. " SCSDIR1 ,SPISCS1 direction 1" "GIO,SPI"
|
|
newline
|
|
bitfld.long 0x04 0. " SCSDIR0 ,SPISCS0 direction 0" "GIO,SPI"
|
|
line.long 0x08 "SPIPC2,SPI Pin Control Register 2"
|
|
bitfld.long 0x08 31. " SOMIDIN7 ,SPISOMI[7] data in" "0,1"
|
|
bitfld.long 0x08 30. " SOMIDIN6 ,SPISOMI[6] data in" "0,1"
|
|
bitfld.long 0x08 29. " SOMIDIN5 ,SPISOMI[5] data in" "0,1"
|
|
newline
|
|
bitfld.long 0x08 28. " SOMIDIN4 ,SPISOMI[4] data in" "0,1"
|
|
bitfld.long 0x08 27. " SOMIDIN3 ,SPISOMI[3] data in" "0,1"
|
|
bitfld.long 0x08 26. " SOMIDIN2 ,SPISOMI[2] data in" "0,1"
|
|
newline
|
|
bitfld.long 0x08 25. " SOMIDIN1 ,SPISOMI[1] data in" "0,1"
|
|
bitfld.long 0x08 24. " SOMIDIN0 ,SPISOMI[0] data in (mirror of bit 11)" "0,1"
|
|
bitfld.long 0x08 23. " SIMODIN7 ,SPISIMO[7] data in" "0,1"
|
|
newline
|
|
bitfld.long 0x08 22. " SIMODIN6 ,SPISIMO[6] data in" "0,1"
|
|
bitfld.long 0x08 21. " SIMODIN5 ,SPISIMO[5] data in" "0,1"
|
|
bitfld.long 0x08 20. " SIMODIN4 ,SPISIMO[4] data in" "0,1"
|
|
newline
|
|
bitfld.long 0x08 19. " SIMODIN3 ,SPISIMO[3] data in" "0,1"
|
|
bitfld.long 0x08 18. " SIMODIN2 ,SPISIMO[2] data in" "0,1"
|
|
bitfld.long 0x08 17. " SIMODIN1 ,SPISIMO[1] data in" "0,1"
|
|
newline
|
|
bitfld.long 0x08 16. " SIMODIN0 ,SPISIMO[0] data in (mirror of bit 10)" "0,1"
|
|
bitfld.long 0x08 11. " SOMIDIN0 ,SPISOMI[0] data in" "0,1"
|
|
bitfld.long 0x08 10. " SIMODIN0 ,SPISIMO[0] data in" "0,1"
|
|
newline
|
|
bitfld.long 0x08 9. " CLKDIN ,SPI clock data in" "0,1"
|
|
bitfld.long 0x08 8. " ENADIN ,SPIENA data in" "0,1"
|
|
bitfld.long 0x08 7. " SCSDIN7 ,SPISCS7 data in" "0,1"
|
|
newline
|
|
bitfld.long 0x08 6. " SCSDIN6 ,SPISCS6 data in" "0,1"
|
|
bitfld.long 0x08 5. " SCSDIN5 ,SPISCS5 data in" "0,1"
|
|
bitfld.long 0x08 4. " SCSDIN4 ,SPISCS4 data in" "0,1"
|
|
newline
|
|
bitfld.long 0x08 3. " SCSDIN3 ,SPISCS3 data in" "0,1"
|
|
bitfld.long 0x08 2. " SCSDIN2 ,SPISCS2 data in" "0,1"
|
|
bitfld.long 0x08 1. " SCSDIN1 ,SPISCS1 data in" "0,1"
|
|
newline
|
|
bitfld.long 0x08 0. " SCSDIN0 ,SPISCS0 direction 0" "0,1"
|
|
line.long 0x0C "SPIPC3,SPI Pin Control Register 3"
|
|
bitfld.long 0x0C 31. " SOMIDOUT7 ,SPISOMI[7] data out write" "0,1"
|
|
bitfld.long 0x0C 30. " SOMIDOUT6 ,SPISOMI[6] data out write" "0,1"
|
|
bitfld.long 0x0C 29. " SOMIDOUT5 ,SPISOMI[5] data out write" "0,1"
|
|
newline
|
|
bitfld.long 0x0C 28. " SOMIDOUT4 ,SPISOMI[4] data out write" "0,1"
|
|
bitfld.long 0x0C 27. " SOMIDOUT3 ,SPISOMI[3] data out write" "0,1"
|
|
bitfld.long 0x0C 26. " SOMIDOUT2 ,SPISOMI[2] data out write" "0,1"
|
|
newline
|
|
bitfld.long 0x0C 25. " SOMIDOUT1 ,SPISOMI[1] data out write" "0,1"
|
|
bitfld.long 0x0C 24. " SOMIDOUT0 ,SPISOMI[0] data out write (mirror of bit 11)" "0,1"
|
|
bitfld.long 0x0C 23. " SIMODOUT7 ,SPISIMO[7] data out write" "0,1"
|
|
newline
|
|
bitfld.long 0x0C 22. " SIMODOUT6 ,SPISIMO[6] data out write" "0,1"
|
|
bitfld.long 0x0C 21. " SIMODOUT5 ,SPISIMO[5] data out write" "0,1"
|
|
bitfld.long 0x0C 20. " SIMODOUT4 ,SPISIMO[4] data out write" "0,1"
|
|
newline
|
|
bitfld.long 0x0C 19. " SIMODOUT3 ,SPISIMO[3] data out write" "0,1"
|
|
bitfld.long 0x0C 18. " SIMODOUT2 ,SPISIMO[2] data out write" "0,1"
|
|
bitfld.long 0x0C 17. " SIMODOUT1 ,SPISIMO[1] data out write" "0,1"
|
|
newline
|
|
bitfld.long 0x0C 16. " SIMODOUT0 ,SPISIMO[0] data out write (mirror of bit 10)" "0,1"
|
|
bitfld.long 0x0C 11. " SOMIDOUT0 ,SPISOMI[0] data out write" "0,1"
|
|
bitfld.long 0x0C 10. " SIMODOUT0 ,SPISIMO[0] data out write" "0,1"
|
|
newline
|
|
bitfld.long 0x0C 9. " CLKDOUT ,SPI clock data out write" "0,1"
|
|
bitfld.long 0x0C 8. " ENADOUT ,SPIENA data out write" "0,1"
|
|
bitfld.long 0x0C 7. " SCSDOUT7 ,SPISCS7 data out write" "0,1"
|
|
newline
|
|
bitfld.long 0x0C 6. " SCSDOUT6 ,SPISCS6 data out write" "0,1"
|
|
bitfld.long 0x0C 5. " SCSDOUT5 ,SPISCS5 data out write" "0,1"
|
|
bitfld.long 0x0C 4. " SCSDOUT4 ,SPISCS4 data out write" "0,1"
|
|
newline
|
|
bitfld.long 0x0C 3. " SCSDOUT3 ,SPISCS3 data out write" "0,1"
|
|
bitfld.long 0x0C 2. " SCSDOUT2 ,SPISCS2 data out write" "0,1"
|
|
bitfld.long 0x0C 1. " SCSDOUT1 ,SPISCS1 data out write" "0,1"
|
|
newline
|
|
bitfld.long 0x0C 0. " SCSDOUT0 ,SPISCS0 data out write" "0,1"
|
|
line.long 0x10 "SPIPC4,SPI Pin Control Register 4"
|
|
bitfld.long 0x10 31. " SOMISET7 ,SPISOMI[7] data out set" "0,1"
|
|
bitfld.long 0x10 30. " SOMISET6 ,SPISOMI[6] data out set" "0,1"
|
|
bitfld.long 0x10 29. " SOMISET5 ,SPISOMI[5] data out set" "0,1"
|
|
newline
|
|
bitfld.long 0x10 28. " SOMISET4 ,SPISOMI[4] data out set" "0,1"
|
|
bitfld.long 0x10 27. " SOMISET3 ,SPISOMI[3] data out set" "0,1"
|
|
bitfld.long 0x10 26. " SOMISET2 ,SPISOMI[2] data out set" "0,1"
|
|
newline
|
|
bitfld.long 0x10 25. " SOMISET1 ,SPISOMI[1] data out set" "0,1"
|
|
bitfld.long 0x10 24. " SOMISET0 ,SPISOMI[0] data out set (mirror of bit 11)" "0,1"
|
|
bitfld.long 0x10 23. " SIMOSET7 ,SPISIMO[7] data out set" "0,1"
|
|
newline
|
|
bitfld.long 0x10 22. " SIMOSET6 ,SPISIMO[6] data out set" "0,1"
|
|
bitfld.long 0x10 21. " SIMOSET5 ,SPISIMO[5] data out set" "0,1"
|
|
bitfld.long 0x10 20. " SIMOSET4 ,SPISIMO[4] data out set" "0,1"
|
|
newline
|
|
bitfld.long 0x10 19. " SIMOSET3 ,SPISIMO[3] data out set" "0,1"
|
|
bitfld.long 0x10 18. " SIMOSET2 ,SPISIMO[2] data out set" "0,1"
|
|
bitfld.long 0x10 17. " SIMOSET1 ,SPISIMO[1] data out set" "0,1"
|
|
newline
|
|
bitfld.long 0x10 16. " SIMOSET0 ,SPISIMO[0] data out set (mirror of bit 10)" "0,1"
|
|
bitfld.long 0x10 11. " SOMISET0 ,SPISOMI[0] data out set" "0,1"
|
|
bitfld.long 0x10 10. " SIMOSET0 ,SPISIMO[0] data out set" "0,1"
|
|
newline
|
|
bitfld.long 0x10 9. " CLKSET ,SPI clock data out set" "0,1"
|
|
bitfld.long 0x10 8. " ENASET ,SPIENA data out set" "0,1"
|
|
bitfld.long 0x10 7. " SCSSET7 ,SPISCS7 data out set" "0,1"
|
|
newline
|
|
bitfld.long 0x10 6. " SCSSET6 ,SPISCS6 data out set" "0,1"
|
|
bitfld.long 0x10 5. " SCSSET5 ,SPISCS5 data out set" "0,1"
|
|
bitfld.long 0x10 4. " SCSSET4 ,SPISCS4 data out set" "0,1"
|
|
newline
|
|
bitfld.long 0x10 3. " SCSSET3 ,SPISCS3 data out set" "0,1"
|
|
bitfld.long 0x10 2. " SCSSET2 ,SPISCS2 data out set" "0,1"
|
|
bitfld.long 0x10 1. " SCSSET1 ,SPISCS1 data out set" "0,1"
|
|
newline
|
|
bitfld.long 0x10 0. " SCSSET0 ,SPISCS0 data out set" "0,1"
|
|
line.long 0x14 "SPIPC5,SPI Pin Control Register 5"
|
|
bitfld.long 0x14 31. " SOMICLR7 ,SPISOMI[7] data out clear" "0,1"
|
|
bitfld.long 0x14 30. " SOMICLR6 ,SPISOMI[6] data out clear" "0,1"
|
|
bitfld.long 0x14 29. " SOMICLR5 ,SPISOMI[5] data out clear" "0,1"
|
|
newline
|
|
bitfld.long 0x14 28. " SOMICLR4 ,SPISOMI[4] data out clear" "0,1"
|
|
bitfld.long 0x14 27. " SOMICLR3 ,SPISOMI[3] data out clear" "0,1"
|
|
bitfld.long 0x14 26. " SOMICLR2 ,SPISOMI[2] data out clear" "0,1"
|
|
newline
|
|
bitfld.long 0x14 25. " SOMICLR1 ,SPISOMI[1] data out clear" "0,1"
|
|
bitfld.long 0x14 24. " SOMICLR0 ,SPISOMI[0] data out clear (mirror of bit 11)" "0,1"
|
|
bitfld.long 0x14 23. " SIMOCLR7 ,SPISIMO[7] data out clear" "0,1"
|
|
newline
|
|
bitfld.long 0x14 22. " SIMOCLR6 ,SPISIMO[6] data out clear" "0,1"
|
|
bitfld.long 0x14 21. " SIMOCLR5 ,SPISIMO[5] data out clear" "0,1"
|
|
bitfld.long 0x14 20. " SIMOCLR4 ,SPISIMO[4] data out clear" "0,1"
|
|
newline
|
|
bitfld.long 0x14 19. " SIMOCLR3 ,SPISIMO[3] data out clear" "0,1"
|
|
bitfld.long 0x14 18. " SIMOCLR2 ,SPISIMO[2] data out clear" "0,1"
|
|
bitfld.long 0x14 17. " SIMOCLR1 ,SPISIMO[1] data out clear" "0,1"
|
|
newline
|
|
bitfld.long 0x14 16. " SIMOCLR0 ,SPISIMO[0] data out clear (mirror of bit 10)" "0,1"
|
|
bitfld.long 0x14 11. " SOMICLR0 ,SPISOMI[0] data out clear" "0,1"
|
|
bitfld.long 0x14 10. " SIMOCLR0 ,SPISIMO[0] data out clear" "0,1"
|
|
newline
|
|
bitfld.long 0x14 9. " CLKCLR ,SPI clock data out clear" "0,1"
|
|
bitfld.long 0x14 8. " ENACLR ,SPIENA data out clear" "0,1"
|
|
bitfld.long 0x14 7. " SCSCLR7 ,SPISCS7 data out clear" "0,1"
|
|
newline
|
|
bitfld.long 0x14 6. " SCSCLR6 ,SPISCS6 data out clear" "0,1"
|
|
bitfld.long 0x14 5. " SCSCLR5 ,SPISCS5 data out clear" "0,1"
|
|
bitfld.long 0x14 4. " SCSCLR4 ,SPISCS4 data out clear" "0,1"
|
|
newline
|
|
bitfld.long 0x14 3. " SCSCLR3 ,SPISCS3 data out clear" "0,1"
|
|
bitfld.long 0x14 2. " SCSCLR2 ,SPISCS2 data out clear" "0,1"
|
|
bitfld.long 0x14 1. " SCSCLR1 ,SPISCS1 data out clear" "0,1"
|
|
newline
|
|
bitfld.long 0x14 0. " SCSCLR0 ,SPISCS0 data out clear" "0,1"
|
|
line.long 0x18 "SPIPC6,SPI Pin Control Register 6"
|
|
bitfld.long 0x18 31. " SOMIPDR7 ,SPISOMI[7] open drain enable" "Disabled,Enabled"
|
|
bitfld.long 0x18 30. " SOMIPDR6 ,SPISOMI[6] open drain enable" "Disabled,Enabled"
|
|
bitfld.long 0x18 29. " SOMIPDR5 ,SPISOMI[5] open drain enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x18 28. " SOMIPDR4 ,SPISOMI[4] open drain enable" "Disabled,Enabled"
|
|
bitfld.long 0x18 27. " SOMIPDR3 ,SPISOMI[3] open drain enable" "Disabled,Enabled"
|
|
bitfld.long 0x18 26. " SOMIPDR2 ,SPISOMI[2] open drain enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x18 25. " SOMIPDR1 ,SPISOMI[1] open drain enable" "Disabled,Enabled"
|
|
bitfld.long 0x18 24. " SOMIPDR0 ,SPISOMI[0] open drain enable (mirror of bit 11)" "Disabled,Enabled"
|
|
bitfld.long 0x18 23. " SIMOPDR7 ,SPISIMO[7] open drain enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x18 22. " SIMOPDR6 ,SPISIMO[6] open drain enable" "Disabled,Enabled"
|
|
bitfld.long 0x18 21. " SIMOPDR5 ,SPISIMO[5] open drain enable" "Disabled,Enabled"
|
|
bitfld.long 0x18 20. " SIMOPDR4 ,SPISIMO[4] open drain enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x18 19. " SIMOPDR3 ,SPISIMO[3] open drain enable" "Disabled,Enabled"
|
|
bitfld.long 0x18 18. " SIMOPDR2 ,SPISIMO[2] open drain enable" "Disabled,Enabled"
|
|
bitfld.long 0x18 17. " SIMOPDR1 ,SPISIMO[1] open drain enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x18 16. " SIMOPDR0 ,SPISIMO[0] open drain enable (mirror of bit 10)" "Disabled,Enabled"
|
|
bitfld.long 0x18 11. " SOMIPDR0 ,SPISOMI[0] open drain enable" "Disabled,Enabled"
|
|
bitfld.long 0x18 10. " SIMOPDR0 ,SPISIMO[0] open drain enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x18 9. " CLKPDR ,SPI clock open drain enable" "Disabled,Enabled"
|
|
bitfld.long 0x18 8. " ENAPDR ,SPIENA open drain enable" "Disabled,Enabled"
|
|
bitfld.long 0x18 7. " SCSPDR7 ,SPISCS7 open drain enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x18 6. " SCSPDR6 ,SPISCS6 open drain enable" "Disabled,Enabled"
|
|
bitfld.long 0x18 5. " SCSPDR5 ,SPISCS5 open drain enable" "Disabled,Enabled"
|
|
bitfld.long 0x18 4. " SCSPDR4 ,SPISCS4 open drain enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x18 3. " SCSPDR3 ,SPISCS3 open drain enable" "Disabled,Enabled"
|
|
bitfld.long 0x18 2. " SCSPDR2 ,SPISCS2 open drain enable" "Disabled,Enabled"
|
|
bitfld.long 0x18 1. " SCSPDR1 ,SPISCS1 open drain enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x18 0. " SCSPDR0 ,SPISCS0 open drain enable" "Disabled,Enabled"
|
|
line.long 0x1C "SPIPC7,SPI Pin Control Register 7"
|
|
bitfld.long 0x1C 31. " SOMIPDIS7 ,SPISOMI[7] pull control enable/disable" "No,Yes"
|
|
bitfld.long 0x1C 30. " SOMIPDIS6 ,SPISOMI[6] pull control enable/disable" "No,Yes"
|
|
bitfld.long 0x1C 29. " SOMIPDIS5 ,SPISOMI[5] pull control enable/disable" "No,Yes"
|
|
newline
|
|
bitfld.long 0x1C 28. " SOMIPDIS4 ,SPISOMI[4] pull control enable/disable" "No,Yes"
|
|
bitfld.long 0x1C 27. " SOMIPDIS3 ,SPISOMI[3] pull control enable/disable" "No,Yes"
|
|
bitfld.long 0x1C 26. " SOMIPDIS2 ,SPISOMI[2] pull control enable/disable" "No,Yes"
|
|
newline
|
|
bitfld.long 0x1C 25. " SOMIPDIS1 ,SPISOMI[1] pull control enable/disable" "No,Yes"
|
|
bitfld.long 0x1C 24. " SOMIPDIS0 ,SPISOMI[0] pull control enable/disable (mirror of bit 11)" "No,Yes"
|
|
bitfld.long 0x1C 23. " SIMOPDIS7 ,SPISIMO[7] pull control enable/disable" "No,Yes"
|
|
newline
|
|
bitfld.long 0x1C 22. " SIMOPDIS6 ,SPISIMO[6] pull control enable/disable" "No,Yes"
|
|
bitfld.long 0x1C 21. " SIMOPDIS5 ,SPISIMO[5] pull control enable/disable" "No,Yes"
|
|
bitfld.long 0x1C 20. " SIMOPDIS4 ,SPISIMO[4] pull control enable/disable" "No,Yes"
|
|
newline
|
|
bitfld.long 0x1C 19. " SIMOPDIS3 ,SPISIMO[3] pull control enable/disable" "No,Yes"
|
|
bitfld.long 0x1C 18. " SIMOPDIS2 ,SPISIMO[2] pull control enable/disable" "No,Yes"
|
|
bitfld.long 0x1C 17. " SIMOPDIS1 ,SPISIMO[1] pull control enable/disable" "No,Yes"
|
|
newline
|
|
bitfld.long 0x1C 16. " SIMOPDIS0 ,SPISIMO[0] pull control enable/disable (mirror of bit 10)" "No,Yes"
|
|
bitfld.long 0x1C 11. " SOMIPDIS0 ,SPISOMI[0] pull control enable/disable" "No,Yes"
|
|
bitfld.long 0x1C 10. " SIMOPDIS0 ,SPISIMO[0] pull control enable/disable" "No,Yes"
|
|
newline
|
|
bitfld.long 0x1C 9. " CLKPDIS ,SPI clock pull control enable/disable" "No,Yes"
|
|
bitfld.long 0x1C 8. " ENAPDIS ,SPIENA pull control enable/disable" "No,Yes"
|
|
bitfld.long 0x1C 7. " SCSPDIS7 ,SPISCS7 pull control enable/disable" "No,Yes"
|
|
newline
|
|
bitfld.long 0x1C 6. " SCSPDIS6 ,SPISCS6 pull control enable/disable" "No,Yes"
|
|
bitfld.long 0x1C 5. " SCSPDIS5 ,SPISCS5 pull control enable/disable" "No,Yes"
|
|
bitfld.long 0x1C 4. " SCSPDIS4 ,SPISCS4 pull control enable/disable" "No,Yes"
|
|
newline
|
|
bitfld.long 0x1C 3. " SCSPDIS3 ,SPISCS3 pull control enable/disable" "No,Yes"
|
|
bitfld.long 0x1C 2. " SCSPDIS2 ,SPISCS2 pull control enable/disable" "No,Yes"
|
|
bitfld.long 0x1C 1. " SCSPDIS1 ,SPISCS1 pull control enable/disable" "No,Yes"
|
|
newline
|
|
bitfld.long 0x1C 0. " SCSPDIS0 ,SPISCS0 pull control enable/disable" "No,Yes"
|
|
line.long 0x20 "SPIPC8,SPI Pin Control Register 8"
|
|
bitfld.long 0x20 31. " SOMIPSEL7 ,SPISOMI[7] pull select" "Pull down,Pull up"
|
|
bitfld.long 0x20 30. " SOMIPSEL6 ,SPISOMI[6] pull select" "Pull down,Pull up"
|
|
bitfld.long 0x20 29. " SOMIPSEL5 ,SPISOMI[5] pull select" "Pull down,Pull up"
|
|
newline
|
|
bitfld.long 0x20 28. " SOMIPSEL4 ,SPISOMI[4] pull select" "Pull down,Pull up"
|
|
bitfld.long 0x20 27. " SOMIPSEL3 ,SPISOMI[3] pull select" "Pull down,Pull up"
|
|
bitfld.long 0x20 26. " SOMIPSEL2 ,SPISOMI[2] pull select" "Pull down,Pull up"
|
|
newline
|
|
bitfld.long 0x20 25. " SOMIPSEL1 ,SPISOMI[1] pull select" "Pull down,Pull up"
|
|
bitfld.long 0x20 24. " SOMIPSEL0 ,SPISOMI[0] pull select (mirror of bit 11)" "Pull down,Pull up"
|
|
bitfld.long 0x20 23. " SIMOPSEL7 ,SPISIMO[7] pull select" "Pull down,Pull up"
|
|
newline
|
|
bitfld.long 0x20 22. " SIMOPSEL6 ,SPISIMO[6] pull select" "Pull down,Pull up"
|
|
bitfld.long 0x20 21. " SIMOPSEL5 ,SPISIMO[5] pull select" "Pull down,Pull up"
|
|
bitfld.long 0x20 20. " SIMOPSEL4 ,SPISIMO[4] pull select" "Pull down,Pull up"
|
|
newline
|
|
bitfld.long 0x20 19. " SIMOPSEL3 ,SPISIMO[3] pull select" "Pull down,Pull up"
|
|
bitfld.long 0x20 18. " SIMOPSEL2 ,SPISIMO[2] pull select" "Pull down,Pull up"
|
|
bitfld.long 0x20 17. " SIMOPSEL1 ,SPISIMO[1] pull select" "Pull down,Pull up"
|
|
newline
|
|
bitfld.long 0x20 16. " SIMOPSEL0 ,SPISIMO[0] pull select (mirror of bit 10)" "Pull down,Pull up"
|
|
bitfld.long 0x20 11. " SOMIPSEL0 ,SPISOMI[0] pull select" "Pull down,Pull up"
|
|
bitfld.long 0x20 10. " SIMOPSEL0 ,SPISIMO[0] pull select" "Pull down,Pull up"
|
|
newline
|
|
bitfld.long 0x20 9. " CLKPSEL ,SPI clock pull select" "Pull down,Pull up"
|
|
bitfld.long 0x20 8. " ENAPSEL ,SPIENA pull select" "Pull down,Pull up"
|
|
bitfld.long 0x20 7. " SCSPSEL7 ,SPISCS7 pull select" "Pull down,Pull up"
|
|
newline
|
|
bitfld.long 0x20 6. " SCSPSEL6 ,SPISCS6 pull select" "Pull down,Pull up"
|
|
bitfld.long 0x20 5. " SCSPSEL5 ,SPISCS5 pull select" "Pull down,Pull up"
|
|
bitfld.long 0x20 4. " SCSPSEL4 ,SPISCS4 pull select" "Pull down,Pull up"
|
|
newline
|
|
bitfld.long 0x20 3. " SCSPSEL3 ,SPISCS3 pull select" "Pull down,Pull up"
|
|
bitfld.long 0x20 2. " SCSPSEL2 ,SPISCS2 pull select" "Pull down,Pull up"
|
|
bitfld.long 0x20 1. " SCSPSEL1 ,SPISCS1 pull select" "Pull down,Pull up"
|
|
newline
|
|
bitfld.long 0x20 0. " SCSPSEL0 ,SPISCS0 pull select" "Pull down,Pull up"
|
|
group.long 0x38++0x07
|
|
line.long 0x00 "SPIDAT0,SPI Transmit Data Register 0"
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,SPI transmit data"
|
|
line.long 0x04 "SPIDAT1,Transmit Data Register 1"
|
|
bitfld.long 0x04 28. " CSHOLD ,Chip select hold mode" "Inactive,Active"
|
|
bitfld.long 0x04 26. " WDEL ,Enable the delay counter at the end of the current transaction" "No delay,After transaction"
|
|
bitfld.long 0x04 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
newline
|
|
hexmask.long.byte 0x04 16.--23. 1. " CSNR ,Chip select number"
|
|
hexmask.long.word 0x04 0.--15. 1. " TXDATA ,Transfer data"
|
|
hgroup.long 0x40++0x03
|
|
hide.long 0x00 "SPIBUF,SPI Receive Buffer Register"
|
|
in
|
|
rgroup.long 0x44++0x03
|
|
line.long 0x00 "SPIEMU,SPI Emulation Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " EMU_RXDATA ,SPI receive data"
|
|
sif cpuis("TMS570LS0232")||cpuis("TMS570LS0714*")||cpuis("TMS570LS0914*")
|
|
group.long 0x48++0x03
|
|
line.long 0x00 "SPIDELAY,SPI Delay Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " C2TDELAY ,Chip-select-active to transmit-start delay"
|
|
hexmask.long.byte 0x00 16.--23. 1. " T2CDELAY ,Transmit-end-to-chip-select-inactive-delay"
|
|
hexmask.long.byte 0x00 8.--15. 1. " T2EDELAY ,Transmit-data-finished to ENA-pin-inactive time-out"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--7. 1. " C2EDELAY ,Chip-select-active to ENA-signal-active time-out"
|
|
else
|
|
rgroup.long 0x48++0x03
|
|
line.long 0x00 "SPIDELAY,SPI Delay Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " C2TDELAY ,Chip-select-active to transmit-start delay"
|
|
hexmask.long.byte 0x00 16.--23. 1. " T2CDELAY ,Transmit-end-to-chip-select-inactive-delay"
|
|
hexmask.long.byte 0x00 8.--15. 1. " T2EDELAY ,Transmit-data-finished to ENA-pin-inactive time-out"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--7. 1. " C2EDELAY ,Chip-select-active to ENA-signal-active time-out"
|
|
endif
|
|
group.long 0x4C++0x13
|
|
line.long 0x00 "SPIDEF,SPI Default Chip Select Register"
|
|
bitfld.long 0x00 7. " CSDEF7 ,Chip select default pattern 7" "0,1"
|
|
bitfld.long 0x00 6. " CSDEF6 ,Chip select default pattern 6" "0,1"
|
|
bitfld.long 0x00 5. " CSDEF5 ,Chip select default pattern 5" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. " CSDEF4 ,Chip select default pattern 4" "0,1"
|
|
bitfld.long 0x00 3. " CSDEF3 ,Chip select default pattern 3" "0,1"
|
|
bitfld.long 0x00 2. " CSDEF2 ,Chip select default pattern 2" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. " CSDEF1 ,Chip select default pattern 1" "0,1"
|
|
bitfld.long 0x00 0. " CSDEF0 ,Chip select default pattern 0" "0,1"
|
|
line.long 0x4 "SPIFMT0,SPI Data Format Register 0"
|
|
sif (cpuis("TMS570LS0332")||cpuis("TMS570LS0432")||cpuis("TMS570LS1114*")||cpuis("TMS570LS1115*")||cpuis("TMS570LS1224*")||cpuis("TMS570LS1225*")||cpuis("TMS570LS1227*")||cpuis("TMS570LS0232")||cpuis("TMS570LS0714*")||cpuis("TMS570LS0914*"))
|
|
hexmask.long.byte 0x4 24.--31. 1. " WDELAY ,Delay in between transmissions for data format 0"
|
|
else
|
|
bitfld.long 0x4 24.--29. " WDELAY ,Delay in between transmissions for data format 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
endif
|
|
bitfld.long 0x4 23. " PARPOL ,Parity polarity: even or odd" "Even,Odd"
|
|
newline
|
|
bitfld.long 0x4 22. " PARITYENA ,Parity enable for data format 0" "Disabled,Enabled"
|
|
bitfld.long 0x4 21. " WAITENA ,The master waits for the ENA signal from slave for data format 0" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x4 20. " SHIFTDIR ,Shift direction for data format $" "MSB,LSB"
|
|
sif (cpu()==("TMS570LS0332")||cpu()==("TMS570LS0432")||cpuis("TMS570LS1114*")||cpuis("TMS570LS1115*")||cpuis("TMS570LS1224*")||cpuis("TMS570LS1225*")||cpuis("TMS570LS1227*")||cpuis("TMS570LS0232")||cpuis("TMS570LS0714*")||cpuis("TMS570LS0914*"))
|
|
bitfld.long 0x4 19. " HDUPLEX_ENA0 ,Half Duplex transfer mode enable for Data Format 0" "Normal,RX/TX"
|
|
endif
|
|
newline
|
|
bitfld.long 0x4 18. " DISCSTIMERS ,Disable chip-select timers for this format" "No,Yes"
|
|
newline
|
|
bitfld.long 0x4 17. " POLARITY ,SPI data format 0 clock polarity" "Low,High"
|
|
bitfld.long 0x4 16. " PHASE ,SPI data format 0 clock delay" "Disabled,Enabled"
|
|
newline
|
|
hexmask.long.byte 0x4 8.--15. 1. " PRESCALE ,SPI data format 0 prescaler"
|
|
bitfld.long 0x4 0.--4. " CHARLEN ,SPI data format 0 data-word length" ",,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,?..."
|
|
line.long 0x8 "SPIFMT1,SPI Data Format Register 1"
|
|
sif (cpuis("TMS570LS0332")||cpuis("TMS570LS0432")||cpuis("TMS570LS1114*")||cpuis("TMS570LS1115*")||cpuis("TMS570LS1224*")||cpuis("TMS570LS1225*")||cpuis("TMS570LS1227*")||cpuis("TMS570LS0232")||cpuis("TMS570LS0714*")||cpuis("TMS570LS0914*"))
|
|
hexmask.long.byte 0x8 24.--31. 1. " WDELAY ,Delay in between transmissions for data format 1"
|
|
else
|
|
bitfld.long 0x8 24.--29. " WDELAY ,Delay in between transmissions for data format 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
endif
|
|
bitfld.long 0x8 23. " PARPOL ,Parity polarity: even or odd" "Even,Odd"
|
|
newline
|
|
bitfld.long 0x8 22. " PARITYENA ,Parity enable for data format 1" "Disabled,Enabled"
|
|
bitfld.long 0x8 21. " WAITENA ,The master waits for the ENA signal from slave for data format 1" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x8 20. " SHIFTDIR ,Shift direction for data format $" "MSB,LSB"
|
|
sif (cpu()==("TMS570LS0332")||cpu()==("TMS570LS0432")||cpuis("TMS570LS1114*")||cpuis("TMS570LS1115*")||cpuis("TMS570LS1224*")||cpuis("TMS570LS1225*")||cpuis("TMS570LS1227*")||cpuis("TMS570LS0232")||cpuis("TMS570LS0714*")||cpuis("TMS570LS0914*"))
|
|
bitfld.long 0x8 19. " HDUPLEX_ENA1 ,Half Duplex transfer mode enable for Data Format 1" "Normal,RX/TX"
|
|
endif
|
|
newline
|
|
bitfld.long 0x8 18. " DISCSTIMERS ,Disable chip-select timers for this format" "No,Yes"
|
|
newline
|
|
bitfld.long 0x8 17. " POLARITY ,SPI data format 1 clock polarity" "Low,High"
|
|
bitfld.long 0x8 16. " PHASE ,SPI data format 1 clock delay" "Disabled,Enabled"
|
|
newline
|
|
hexmask.long.byte 0x8 8.--15. 1. " PRESCALE ,SPI data format 1 prescaler"
|
|
bitfld.long 0x8 0.--4. " CHARLEN ,SPI data format 1 data-word length" ",,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,?..."
|
|
line.long 0xC "SPIFMT2,SPI Data Format Register 2"
|
|
sif (cpuis("TMS570LS0332")||cpuis("TMS570LS0432")||cpuis("TMS570LS1114*")||cpuis("TMS570LS1115*")||cpuis("TMS570LS1224*")||cpuis("TMS570LS1225*")||cpuis("TMS570LS1227*")||cpuis("TMS570LS0232")||cpuis("TMS570LS0714*")||cpuis("TMS570LS0914*"))
|
|
hexmask.long.byte 0xC 24.--31. 1. " WDELAY ,Delay in between transmissions for data format 2"
|
|
else
|
|
bitfld.long 0xC 24.--29. " WDELAY ,Delay in between transmissions for data format 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
endif
|
|
bitfld.long 0xC 23. " PARPOL ,Parity polarity: even or odd" "Even,Odd"
|
|
newline
|
|
bitfld.long 0xC 22. " PARITYENA ,Parity enable for data format 2" "Disabled,Enabled"
|
|
bitfld.long 0xC 21. " WAITENA ,The master waits for the ENA signal from slave for data format 2" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0xC 20. " SHIFTDIR ,Shift direction for data format $" "MSB,LSB"
|
|
sif (cpu()==("TMS570LS0332")||cpu()==("TMS570LS0432")||cpuis("TMS570LS1114*")||cpuis("TMS570LS1115*")||cpuis("TMS570LS1224*")||cpuis("TMS570LS1225*")||cpuis("TMS570LS1227*")||cpuis("TMS570LS0232")||cpuis("TMS570LS0714*")||cpuis("TMS570LS0914*"))
|
|
bitfld.long 0xC 19. " HDUPLEX_ENA2 ,Half Duplex transfer mode enable for Data Format 2" "Normal,RX/TX"
|
|
endif
|
|
newline
|
|
bitfld.long 0xC 18. " DISCSTIMERS ,Disable chip-select timers for this format" "No,Yes"
|
|
newline
|
|
bitfld.long 0xC 17. " POLARITY ,SPI data format 2 clock polarity" "Low,High"
|
|
bitfld.long 0xC 16. " PHASE ,SPI data format 2 clock delay" "Disabled,Enabled"
|
|
newline
|
|
hexmask.long.byte 0xC 8.--15. 1. " PRESCALE ,SPI data format 2 prescaler"
|
|
bitfld.long 0xC 0.--4. " CHARLEN ,SPI data format 2 data-word length" ",,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,?..."
|
|
line.long 0x10 "SPIFMT3,SPI Data Format Register 3"
|
|
sif (cpuis("TMS570LS0332")||cpuis("TMS570LS0432")||cpuis("TMS570LS1114*")||cpuis("TMS570LS1115*")||cpuis("TMS570LS1224*")||cpuis("TMS570LS1225*")||cpuis("TMS570LS1227*")||cpuis("TMS570LS0232")||cpuis("TMS570LS0714*")||cpuis("TMS570LS0914*"))
|
|
hexmask.long.byte 0x10 24.--31. 1. " WDELAY ,Delay in between transmissions for data format 3"
|
|
else
|
|
bitfld.long 0x10 24.--29. " WDELAY ,Delay in between transmissions for data format 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
endif
|
|
bitfld.long 0x10 23. " PARPOL ,Parity polarity: even or odd" "Even,Odd"
|
|
newline
|
|
bitfld.long 0x10 22. " PARITYENA ,Parity enable for data format 3" "Disabled,Enabled"
|
|
bitfld.long 0x10 21. " WAITENA ,The master waits for the ENA signal from slave for data format 3" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x10 20. " SHIFTDIR ,Shift direction for data format $" "MSB,LSB"
|
|
sif (cpu()==("TMS570LS0332")||cpu()==("TMS570LS0432")||cpuis("TMS570LS1114*")||cpuis("TMS570LS1115*")||cpuis("TMS570LS1224*")||cpuis("TMS570LS1225*")||cpuis("TMS570LS1227*")||cpuis("TMS570LS0232")||cpuis("TMS570LS0714*")||cpuis("TMS570LS0914*"))
|
|
bitfld.long 0x10 19. " HDUPLEX_ENA3 ,Half Duplex transfer mode enable for Data Format 3" "Normal,RX/TX"
|
|
endif
|
|
newline
|
|
bitfld.long 0x10 18. " DISCSTIMERS ,Disable chip-select timers for this format" "No,Yes"
|
|
newline
|
|
bitfld.long 0x10 17. " POLARITY ,SPI data format 3 clock polarity" "Low,High"
|
|
bitfld.long 0x10 16. " PHASE ,SPI data format 3 clock delay" "Disabled,Enabled"
|
|
newline
|
|
hexmask.long.byte 0x10 8.--15. 1. " PRESCALE ,SPI data format 3 prescaler"
|
|
bitfld.long 0x10 0.--4. " CHARLEN ,SPI data format 3 data-word length" ",,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,?..."
|
|
hgroup.long 0x60++0x03
|
|
hide.long 0x00 "TGINTVECT0,SPI Interrupt Vector Register 0 / MibSPI Transfer Group Interrupt Vector Register 0"
|
|
in
|
|
hgroup.long 0x64++0x03
|
|
hide.long 0x00 "TGINTVECT1,SPI Interrupt Vector Register 1 / MibSPI Transfer Group Interrupt Vector Register 1"
|
|
in
|
|
sif (cpu()!=("TMS570LS0332")&&cpu()!=("TMS570LS0432")&&!cpuis("TMS570LS0232"))
|
|
group.long 0x6C++0x07
|
|
line.long 0x00 "SPIPMCTRL,SPI Parallel/Modulo Mode Control Register"
|
|
bitfld.long 0x00 29. " MODCLKPOL3 ,Modulo mode SPICLK polarity" "Normal,Inverted"
|
|
bitfld.long 0x00 26.--28. " MMODE3 ,SPI/MibSPI data lines " "1,2,3,4,5,6,?..."
|
|
bitfld.long 0x00 24.--25. " PMODE3 ,Parallel mode data lines" "1,2,4,8"
|
|
newline
|
|
bitfld.long 0x00 21. " MODCLKPOL2 ,Modulo mode SPICLK polarity" "Normal,Inverted"
|
|
bitfld.long 0x00 18.--20. " MMODE2 ,SPI/MibSPI data lines " "1,2,3,4,5,6,?..."
|
|
bitfld.long 0x00 16.--17. " PMODE2 ,Parallel mode data lines" "1,2,4,8"
|
|
newline
|
|
bitfld.long 0x00 13. " MODCLKPOL1 ,Modulo mode SPICLK polarity" "Normal,Inverted"
|
|
bitfld.long 0x00 10.--12. " MMODE1 ,SPI/MibSPI data lines " "1,2,3,4,5,6,?..."
|
|
bitfld.long 0x00 8.--9. " PMODE1 ,Parallel mode data lines" "1,2,4,8"
|
|
newline
|
|
bitfld.long 0x00 5. " MODCLKPOL0 ,Modulo mode SPICLK polarity" "Normal,Inverted"
|
|
bitfld.long 0x00 2.--4. " MMODE0 ,SPI/MibSPI data lines " "1,2,3,4,5,6,?..."
|
|
bitfld.long 0x00 0.--1. " PMODE0 ,Parallel mode data lines" "1,2,4,8"
|
|
line.long 0x04 "MIBSPIE,MibSPI Enable Register"
|
|
bitfld.long 0x04 16. " RXRAMACCESS ,Receive-RAM access control" "Not writable,Accessible"
|
|
bitfld.long 0x04 0. " MIBSPIENA ,Multi-buffer mode enable" "Disabled,Enabled"
|
|
elif cpuis("TMS570LS0332")||cpuis("TMS570LS0432")||cpuis("TMS570LS0714*")||cpuis("TMS570LS0914*")||cpuis("TMS570LS0232")
|
|
group.long 0x70++0x03
|
|
line.long 0x00 "MIBSPIE,MibSPI Enable Register"
|
|
bitfld.long 0x00 16. " RXRAMACCESS ,Receive-RAM access control" "Not writable,Accessible"
|
|
bitfld.long 0x00 0. " MIBSPIENA ,Multi-buffer mode enable" "Disabled,Enabled"
|
|
endif
|
|
group.long 0x74++0x0F
|
|
line.long 0x00 "TGITENST,MibSPI Transfer Group Interrupt Enable Set Register"
|
|
bitfld.long 0x00 31. " SETINTENRDY15 ,TG interrupt set (enable) when transfer finished" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " SETINTENRDY14 ,TG interrupt set (enable) when transfer finished" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " SETINTENRDY13 ,TG interrupt set (enable) when transfer finished" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 28. " SETINTENRDY12 ,TG interrupt set (enable) when transfer finished" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " SETINTENRDY11 ,TG interrupt set (enable) when transfer finished" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " SETINTENRDY10 ,TG interrupt set (enable) when transfer finished" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 25. " SETINTENRDY9 ,TG interrupt set (enable) when transfer finished" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " SETINTENRDY8 ,TG interrupt set (enable) when transfer finished" "Disabled,Enabled"
|
|
bitfld.long 0x00 23. " SETINTENRDY7 ,TG interrupt set (enable) when transfer finished" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 22. " SETINTENRDY6 ,TG interrupt set (enable) when transfer finished" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " SETINTENRDY5 ,TG interrupt set (enable) when transfer finished" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " SETINTENRDY4 ,SETTG interrupt set (enable) when transfer finished" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 19. " SETINTENRDY3 ,TG interrupt set (enable) when transfer finished" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SETINTENRDY2 ,TG interrupt set (enable) when transfer finished" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SETINTENRDY1 ,TG interrupt set (enable) when transfer finished" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 16. " SETINTENRDY0 ,TG interrupt set (enable) when transfer finished" "Disabled,Enabled"
|
|
bitfld.long 0x00 15. " SETINTENSUS15 ,TG interrupt set (enabled) when transfer suspended" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " SETINTENSUS14 ,TG interrupt set (enabled) when transfer suspended" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 13. " SETINTENSUS13 ,TG interrupt set (enabled) when transfer suspended" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " SETINTENSUS12 ,TG interrupt set (enabled) when transfer suspended" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " SETINTENSUS11 ,TG interrupt set (enabled) when transfer suspended" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 10. " SETINTENSUS10 ,TG interrupt set (enabled) when transfer suspended" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " SETINTENSUS9 ,TG interrupt set (enabled) when transfer suspended" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " SETINTENSUS8 ,TG interrupt set (enabled) when transfer suspended" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 7. " SETINTENSUS7 ,TG interrupt set (enabled) when transfer suspended" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " SETINTENSUS6 ,TG interrupt set (enabled) when transfer suspended" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " SETINTENSUS5 ,TG interrupt set (enabled) when transfer suspended" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 4. " SETINTENSUS4 ,TG interrupt set (enabled) when transfer suspended" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " SETINTENSUS3 ,TG interrupt set (enabled) when transfer suspended" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " SETINTENSUS2 ,TG interrupt set (enabled) when transfer suspended" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 1. " SETINTENSUS1 ,TG interrupt set (enabled) when transfer suspended" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SETINTENSUS0 ,TG interrupt set (enabled) when transfer suspended" "Disabled,Enabled"
|
|
line.long 0x04 "TGITENCR,MibSPI Transfer Group Interrupt Enable Clear Register"
|
|
bitfld.long 0x04 31. " CLRINTENRDY15 ,TG interrupt clear (disabled) when transfer finished" "Disabled,Enabled"
|
|
bitfld.long 0x04 30. " CLRINTENRDY14 ,TG interrupt clear (disabled) when transfer finished" "Disabled,Enabled"
|
|
bitfld.long 0x04 29. " CLRINTENRDY13 ,TG interrupt clear (disabled) when transfer finished" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x04 28. " CLRINTENRDY12 ,TG interrupt clear (disabled) when transfer finished" "Disabled,Enabled"
|
|
bitfld.long 0x04 27. " CLRINTENRDY11 ,TG interrupt clear (disabled) when transfer finished" "Disabled,Enabled"
|
|
bitfld.long 0x04 26. " CLRINTENRDY10 ,TG interrupt clear (disabled) when transfer finished" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x04 25. " CLRINTENRDY9 ,TG interrupt clear (disabled) when transfer finished" "Disabled,Enabled"
|
|
bitfld.long 0x04 24. " CLRINTENRDY8 ,TG interrupt clear (disabled) when transfer finished" "Disabled,Enabled"
|
|
bitfld.long 0x04 23. " CLRINTENRDY7 ,TG interrupt clear (disabled) when transfer finished" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x04 22. " CLRINTENRDY6 ,TG interrupt clear (disabled) when transfer finished" "Disabled,Enabled"
|
|
bitfld.long 0x04 21. " CLRINTENRDY5 ,TG interrupt clear (disabled) when transfer finished" "Disabled,Enabled"
|
|
bitfld.long 0x04 20. " CLRINTENRDY4 ,TG interrupt clear (disabled) when transfer finished" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x04 19. " CLRINTENRDY3 ,TG interrupt clear (disabled) when transfer finished" "Disabled,Enabled"
|
|
bitfld.long 0x04 18. " CLRINTENRDY2 ,TG interrupt clear (disabled) when transfer finished" "Disabled,Enabled"
|
|
bitfld.long 0x04 17. " CLRINTENRDY1 ,TG interrupt clear (disabled) when transfer finished" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x04 16. " CLRINTENRDY0 ,TG interrupt clear (disabled) when transfer finished" "Disabled,Enabled"
|
|
bitfld.long 0x04 15. " CLRINTENSUS15 ,TG interrupt clear (disabled) when transfer suspended" "Disabled,Enabled"
|
|
bitfld.long 0x04 14. " CLRINTENSUS14 ,TG interrupt clear (disabled) when transfer suspended" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x04 13. " CLRINTENSUS13 ,TG interrupt clear (disabled) when transfer suspended" "Disabled,Enabled"
|
|
bitfld.long 0x04 12. " CLRINTENSUS12 ,TG interrupt clear (disabled) when transfer suspended" "Disabled,Enabled"
|
|
bitfld.long 0x04 11. " CLRINTENSUS11 ,TG interrupt clear (disabled) when transfer suspended" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x04 10. " CLRINTENSUS10 ,TG interrupt clear (disabled) when transfer suspended" "Disabled,Enabled"
|
|
bitfld.long 0x04 9. " CLRINTENSUS9 ,TG interrupt clear (disabled) when transfer suspended" "Disabled,Enabled"
|
|
bitfld.long 0x04 8. " CLRINTENSUS8 ,TG interrupt clear (disabled) when transfer suspended" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x04 7. " CLRINTENSUS7 ,TG interrupt clear (disabled) when transfer suspended" "Disabled,Enabled"
|
|
bitfld.long 0x04 6. " CLRINTENSUS6 ,TG interrupt clear (disabled) when transfer suspended" "Disabled,Enabled"
|
|
bitfld.long 0x04 5. " CLRINTENSUS5 ,TG interrupt clear (disabled) when transfer suspended" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x04 4. " CLRINTENSUS4 ,TG interrupt clear (disabled) when transfer suspended" "Disabled,Enabled"
|
|
bitfld.long 0x04 3. " CLRINTENSUS3 ,TG interrupt clear (disabled) when transfer suspended" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " CLRINTENSUS2 ,TG interrupt clear (disabled) when transfer suspended" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x04 1. " CLRINTENSUS1 ,TG interrupt clear (disabled) when transfer suspended" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " CLRINTENSUS0 ,TG interrupt clear (disabled) when transfer suspended" "Disabled,Enabled"
|
|
line.long 0x08 "TGITLVST,MibSPI Transfer Group Interrupt Level Set Register"
|
|
bitfld.long 0x08 31. " SETINTLVLRDY15 ,Transfer-group completed interrupt level set" "INT0,INT1"
|
|
bitfld.long 0x08 30. " SETINTLVLRDY14 ,Transfer-group completed interrupt level set" "INT0,INT1"
|
|
bitfld.long 0x08 29. " SETINTLVLRDY13 ,Transfer-group completed interrupt level set" "INT0,INT1"
|
|
newline
|
|
bitfld.long 0x08 28. " SETINTLVLRDY12 ,Transfer-group completed interrupt level set" "INT0,INT1"
|
|
bitfld.long 0x08 27. " SETINTLVLRDY11 ,Transfer-group completed interrupt level set" "INT0,INT1"
|
|
bitfld.long 0x08 26. " SETINTLVLRDY10 ,Transfer-group completed interrupt level set" "INT0,INT1"
|
|
newline
|
|
bitfld.long 0x08 25. " SETINTLVLRDY9 ,Transfer-group completed interrupt level set" "INT0,INT1"
|
|
bitfld.long 0x08 24. " SETINTLVLRDY8 ,Transfer-group completed interrupt level set" "INT0,INT1"
|
|
bitfld.long 0x08 23. " SETINTLVLRDY7 ,Transfer-group completed interrupt level set" "INT0,INT1"
|
|
newline
|
|
bitfld.long 0x08 22. " SETINTLVLRDY6 ,Transfer-group completed interrupt level set" "INT0,INT1"
|
|
bitfld.long 0x08 21. " SETINTLVLRDY5 ,Transfer-group completed interrupt level set" "INT0,INT1"
|
|
bitfld.long 0x08 20. " SETINTLVLRDY4 ,Transfer-group completed interrupt level set" "INT0,INT1"
|
|
newline
|
|
bitfld.long 0x08 19. " SETINTLVLRDY3 ,Transfer-group completed interrupt level set" "INT0,INT1"
|
|
bitfld.long 0x08 18. " SETINTLVLRDY2 ,Transfer-group completed interrupt level set" "INT0,INT1"
|
|
bitfld.long 0x08 17. " SETINTLVLRDY1 ,Transfer-group completed interrupt level set" "INT0,INT1"
|
|
newline
|
|
bitfld.long 0x08 16. " SETINTLVLRDY0 ,Transfer-group completed interrupt level set" "INT0,INT1"
|
|
bitfld.long 0x08 15. " SETINTLVLSUS15 ,Transfer-group suspended interrupt level set" "INT0,INT1"
|
|
bitfld.long 0x08 14. " SETINTLVLSUS14 ,Transfer-group suspended interrupt level set" "INT0,INT1"
|
|
newline
|
|
bitfld.long 0x08 13. " SETINTLVLSUS13 ,Transfer-group suspended interrupt level set" "INT0,INT1"
|
|
bitfld.long 0x08 12. " SETINTLVLSUS12 ,Transfer-group suspended interrupt level set" "INT0,INT1"
|
|
bitfld.long 0x08 11. " SETINTLVLSUS11 ,Transfer-group suspended interrupt level set" "INT0,INT1"
|
|
newline
|
|
bitfld.long 0x08 10. " SETINTLVLSUS10 ,Transfer-group suspended interrupt level set" "INT0,INT1"
|
|
bitfld.long 0x08 9. " SETINTLVLSUS9 ,Transfer-group suspended interrupt level set" "INT0,INT1"
|
|
bitfld.long 0x08 8. " SETINTLVLSUS8 ,Transfer-group suspended interrupt level set" "INT0,INT1"
|
|
newline
|
|
bitfld.long 0x08 7. " SETINTLVLSUS7 ,Transfer-group suspended interrupt level set" "INT0,INT1"
|
|
bitfld.long 0x08 6. " SETINTLVLSUS6 ,Transfer-group suspended interrupt level set" "INT0,INT1"
|
|
bitfld.long 0x08 5. " SETINTLVLSUS5 ,Transfer-group suspended interrupt level set" "INT0,INT1"
|
|
newline
|
|
bitfld.long 0x08 4. " SETINTLVLSUS4 ,Transfer-group suspended interrupt level set" "INT0,INT1"
|
|
bitfld.long 0x08 3. " SETINTLVLSUS3 ,Transfer-group suspended interrupt level set" "INT0,INT1"
|
|
bitfld.long 0x08 2. " SETINTLVLSUS2 ,Transfer-group suspended interrupt level set" "INT0,INT1"
|
|
newline
|
|
bitfld.long 0x08 1. " SETINTLVLSUS1 ,Transfer-group suspended interrupt level set" "INT0,INT1"
|
|
bitfld.long 0x08 0. " SETINTLVLSUS0 ,Transfer-group suspended interrupt level set" "INT0,INT1"
|
|
line.long 0x0C "TGITLVCR,MibSPI Transfer Group Interrupt Level Clear Register"
|
|
bitfld.long 0x0C 31. " CLRINTLVLRDY15 ,Transfer-group completed interrupt level clear" "INT0,INT1"
|
|
bitfld.long 0x0C 30. " CLRINTLVLRDY14 ,Transfer-group completed interrupt level clear" "INT0,INT1"
|
|
bitfld.long 0x0C 29. " CLRINTLVLRDY13 ,Transfer-group completed interrupt level clear" "INT0,INT1"
|
|
newline
|
|
bitfld.long 0x0C 28. " CLRINTLVLRDY12 ,Transfer-group completed interrupt level clear" "INT0,INT1"
|
|
bitfld.long 0x0C 27. " CLRINTLVLRDY11 ,Transfer-group completed interrupt level clear" "INT0,INT1"
|
|
bitfld.long 0x0C 26. " CLRINTLVLRDY10 ,Transfer-group completed interrupt level clear" "INT0,INT1"
|
|
newline
|
|
bitfld.long 0x0C 25. " CLRINTLVLRDY9 ,Transfer-group completed interrupt level clear" "INT0,INT1"
|
|
bitfld.long 0x0C 24. " CLRINTLVLRDY8 ,Transfer-group completed interrupt level clear" "INT0,INT1"
|
|
bitfld.long 0x0C 23. " CLRINTLVLRDY7 ,Transfer-group completed interrupt level clear" "INT0,INT1"
|
|
newline
|
|
bitfld.long 0x0C 22. " CLRINTLVLRDY6 ,Transfer-group completed interrupt level clear" "INT0,INT1"
|
|
bitfld.long 0x0C 21. " CLRINTLVLRDY5 ,Transfer-group completed interrupt level clear" "INT0,INT1"
|
|
bitfld.long 0x0C 20. " CLRINTLVLRDY4 ,Transfer-group completed interrupt level clear" "INT0,INT1"
|
|
newline
|
|
bitfld.long 0x0C 19. " CLRINTLVLRDY3 ,Transfer-group completed interrupt level clear" "INT0,INT1"
|
|
bitfld.long 0x0C 18. " CLRINTLVLRDY2 ,Transfer-group completed interrupt level clear" "INT0,INT1"
|
|
bitfld.long 0x0C 17. " CLRINTLVLRDY1 ,Transfer-group completed interrupt level clear" "INT0,INT1"
|
|
newline
|
|
bitfld.long 0x0C 16. " CLRINTLVLRDY0 ,Transfer-group completed interrupt level clear" "INT0,INT1"
|
|
bitfld.long 0x0C 15. " CLRINTLVLSUS15 ,Transfer group suspended interrupt level clear" "INT0,INT1"
|
|
bitfld.long 0x0C 14. " CLRINTLVLSUS14 ,Transfer group suspended interrupt level clear" "INT0,INT1"
|
|
newline
|
|
bitfld.long 0x0C 13. " CLRINTLVLSUS13 ,Transfer group suspended interrupt level clear" "INT0,INT1"
|
|
bitfld.long 0x0C 12. " CLRINTLVLSUS12 ,Transfer group suspended interrupt level clear" "INT0,INT1"
|
|
bitfld.long 0x0C 11. " CLRINTLVLSUS11 ,Transfer group suspended interrupt level clear" "INT0,INT1"
|
|
newline
|
|
bitfld.long 0x0C 10. " CLRINTLVLSUS10 ,Transfer group suspended interrupt level clear" "INT0,INT1"
|
|
bitfld.long 0x0C 9. " CLRINTLVLSUS9 ,Transfer group suspended interrupt level clear" "INT0,INT1"
|
|
bitfld.long 0x0C 8. " CLRINTLVLSUS8 ,Transfer group suspended interrupt level clear" "INT0,INT1"
|
|
newline
|
|
bitfld.long 0x0C 7. " CLRINTLVLSUS7 ,Transfer group suspended interrupt level clear" "INT0,INT1"
|
|
bitfld.long 0x0C 6. " CLRINTLVLSUS6 ,Transfer group suspended interrupt level clear" "INT0,INT1"
|
|
bitfld.long 0x0C 5. " CLRINTLVLSUS5 ,Transfer group suspended interrupt level clear" "INT0,INT1"
|
|
newline
|
|
bitfld.long 0x0C 4. " CLRINTLVLSUS4 ,Transfer group suspended interrupt level clear" "INT0,INT1"
|
|
bitfld.long 0x0C 3. " CLRINTLVLSUS3 ,Transfer group suspended interrupt level clear" "INT0,INT1"
|
|
bitfld.long 0x0C 2. " CLRINTLVLSUS2 ,Transfer group suspended interrupt level clear" "INT0,INT1"
|
|
newline
|
|
bitfld.long 0x0C 1. " CLRINTLVLSUS1 ,Transfer group suspended interrupt level clear" "INT0,INT1"
|
|
bitfld.long 0x0C 0. " CLRINTLVLSUS0 ,Transfer group suspended interrupt level clear" "INT0,INT1"
|
|
group.long 0x84++0x03
|
|
line.long 0x00 "TGITFLG,Transfer Group Interrupt Flag Register"
|
|
sif (cpu()==("TMS570LS0332")||cpu()==("TMS570LS0432")||cpuis("TMS570LS1114*")||cpuis("TMS570LS1115*")||cpuis("TMS570LS1224*")||cpuis("TMS570LS1225*")||cpuis("TMS570LS1227*")||cpuis("TMS570LS0232")||cpuis("TMS570LS0714*")||cpuis("TMS570LS0914*"))
|
|
bitfld.long 0x00 31. " INTFLGRDY[15] ,Transfer-group interrupt flag for a transfer-completed interrupt 15" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " INTFLGRDY[14] ,Transfer-group interrupt flag for a transfer-completed interrupt 14" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 29. " INTFLGRDY[13] ,Transfer-group interrupt flag for a transfer-completed interrupt 13" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " INTFLGRDY[12] ,Transfer-group interrupt flag for a transfer-completed interrupt 12" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 27. " INTFLGRDY[11] ,Transfer-group interrupt flag for a transfer-completed interrupt 11" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " INTFLGRDY[10] ,Transfer-group interrupt flag for a transfer-completed interrupt 10" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 25. " INTFLGRDY[9] ,Transfer-group interrupt flag for a transfer-completed interrupt 9" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " INTFLGRDY[8] ,Transfer-group interrupt flag for a transfer-completed interrupt 8" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 23. " INTFLGRDY[7] ,Transfer-group interrupt flag for a transfer-completed interrupt 7" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " INTFLGRDY[6] ,Transfer-group interrupt flag for a transfer-completed interrupt 6" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 21. " INTFLGRDY[5] ,Transfer-group interrupt flag for a transfer-completed interrupt 5" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " INTFLGRDY[4] ,Transfer-group interrupt flag for a transfer-completed interrupt 4" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 19. " INTFLGRDY[3] ,Transfer-group interrupt flag for a transfer-completed interrupt 3" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " INTFLGRDY[2] ,Transfer-group interrupt flag for a transfer-completed interrupt 2" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 17. " INTFLGRDY[1] ,Transfer-group interrupt flag for a transfer-completed interrupt 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " INTFLGRDY[0] ,Transfer-group interrupt flag for a transfer-completed interrupt 0" "Disabled,Enabled"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 15. " INTFLGSUS[15] ,Transfer-group interrupt flag for a transfer-suspend interrupt 15" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " INTFLGSUS[14] ,Transfer-group interrupt flag for a transfer-suspend interrupt 14" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 13. " INTFLGSUS[13] ,Transfer-group interrupt flag for a transfer-suspend interrupt 13" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " INTFLGSUS[12] ,Transfer-group interrupt flag for a transfer-suspend interrupt 12" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 11. " INTFLGSUS[11] ,Transfer-group interrupt flag for a transfer-suspend interrupt 11" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " INTFLGSUS[10] ,Transfer-group interrupt flag for a transfer-suspend interrupt 10" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 9. " INTFLGSUS[9] ,Transfer-group interrupt flag for a transfer-suspend interrupt 9" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " INTFLGSUS[8] ,Transfer-group interrupt flag for a transfer-suspend interrupt 8" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 7. " INTFLGSUS[7] ,Transfer-group interrupt flag for a transfer-suspend interrupt 7" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " INTFLGSUS[6] ,Transfer-group interrupt flag for a transfer-suspend interrupt 6" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 5. " INTFLGSUS[5] ,Transfer-group interrupt flag for a transfer-suspend interrupt 5" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " INTFLGSUS[4] ,Transfer-group interrupt flag for a transfer-suspend interrupt 4" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 3. " INTFLGSUS[3] ,Transfer-group interrupt flag for a transfer-suspend interrupt 3" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " INTFLGSUS[2] ,Transfer-group interrupt flag for a transfer-suspend interrupt 2" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 1. " INTFLGSUS[1] ,Transfer-group interrupt flag for a transfer-suspend interrupt 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " INTFLGSUS[0] ,Transfer-group interrupt flag for a transfer-suspend interrupt 0" "Disabled,Enabled"
|
|
group.long 0x90++0x47
|
|
line.long 0x00 "TICKCNT,Tick Count Register"
|
|
bitfld.long 0x00 31. " TICKENA ,Tick counter enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " RELOAD ,Pre-load the tick counter" "No effect,Reload"
|
|
bitfld.long 0x00 28.--29. " CLKCTRL ,Tick counter clock source control" "0,1,2,3"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TICKVALUE ,Initial value for the tick counter"
|
|
line.long 0x04 "LTGPEND,Last Transfer Group End Pointer Register"
|
|
bitfld.long 0x04 24.--28. " TGINSERVICE ,The TG number currently being serviced by the sequencer" "No TG,TG0,TG1,TG2,TG3,TG4,TG5,TG6,TG7,TG8,TG9,TG10,TG11,TG12,TG13,TG14,TG15,?..."
|
|
hexmask.long.byte 0x04 8.--14. 1. " LPEND ,Last TG end pointer"
|
|
line.long 0x8 "TG0CTRL,MibSPI Transfer Group Control Register 0"
|
|
bitfld.long 0x8 31. " TGENA ,TG enable" "Disabled,Enabled"
|
|
bitfld.long 0x8 30. " ONESHOT ,Single transfer for TG" "Disabled,Enabled"
|
|
bitfld.long 0x8 29. " PRST ,TG pointer reset mode" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x8 28. " TGTD ,TG triggered" "Not triggered,Triggered"
|
|
bitfld.long 0x8 20.--23. " TRGEVT ,Type of trigger event" "Never,Rising edge,Falling edge,Both edges,,High active,Low-active,Always,?..."
|
|
sif cpuis("TMS570LS0232")||cpuis("TMS570LS0714*")||cpuis("TMS570LS0914*")
|
|
bitfld.long 0x8 16.--19. " TRIGSRC ,Trigger source" "Disabled,EXT0,EXT1,EXT2,EXT3,EXT4,EXT5,EXT6,EXT7,EXT8,EXT9,EXT10,EXT11,EXT12,EXT13,TICK"
|
|
else
|
|
bitfld.long 0x8 16.--19. " TRIGSRC ,Trigger source" "Disabled,GIOA[0],GIOA[1],GIOA[2],GIOA[3],GIOA[4],GIOA[5],GIOA[6],GIOA[7],N2HET1[8],N2HET1[10],N2HET1[12],N2HET1[14],N2HET1[16],N2HET1[18],TICK"
|
|
endif
|
|
newline
|
|
hexmask.long.byte 0x8 8.--14. 0x01 " PSTART ,TG start address"
|
|
hexmask.long.byte 0x8 0.--6. 0x01 " PCURRENT ,Pointer to current buffer"
|
|
line.long 0xC "TG1CTRL,MibSPI Transfer Group Control Register 1"
|
|
bitfld.long 0xC 31. " TGENA ,TG enable" "Disabled,Enabled"
|
|
bitfld.long 0xC 30. " ONESHOT ,Single transfer for TG" "Disabled,Enabled"
|
|
bitfld.long 0xC 29. " PRST ,TG pointer reset mode" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0xC 28. " TGTD ,TG triggered" "Not triggered,Triggered"
|
|
bitfld.long 0xC 20.--23. " TRGEVT ,Type of trigger event" "Never,Rising edge,Falling edge,Both edges,,High active,Low-active,Always,?..."
|
|
sif cpuis("TMS570LS0232")||cpuis("TMS570LS0714*")||cpuis("TMS570LS0914*")
|
|
bitfld.long 0xC 16.--19. " TRIGSRC ,Trigger source" "Disabled,EXT0,EXT1,EXT2,EXT3,EXT4,EXT5,EXT6,EXT7,EXT8,EXT9,EXT10,EXT11,EXT12,EXT13,TICK"
|
|
else
|
|
bitfld.long 0xC 16.--19. " TRIGSRC ,Trigger source" "Disabled,GIOA[0],GIOA[1],GIOA[2],GIOA[3],GIOA[4],GIOA[5],GIOA[6],GIOA[7],N2HET1[8],N2HET1[10],N2HET1[12],N2HET1[14],N2HET1[16],N2HET1[18],TICK"
|
|
endif
|
|
newline
|
|
hexmask.long.byte 0xC 8.--14. 0x01 " PSTART ,TG start address"
|
|
hexmask.long.byte 0xC 0.--6. 0x01 " PCURRENT ,Pointer to current buffer"
|
|
line.long 0x10 "TG2CTRL,MibSPI Transfer Group Control Register 2"
|
|
bitfld.long 0x10 31. " TGENA ,TG enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 30. " ONESHOT ,Single transfer for TG" "Disabled,Enabled"
|
|
bitfld.long 0x10 29. " PRST ,TG pointer reset mode" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x10 28. " TGTD ,TG triggered" "Not triggered,Triggered"
|
|
bitfld.long 0x10 20.--23. " TRGEVT ,Type of trigger event" "Never,Rising edge,Falling edge,Both edges,,High active,Low-active,Always,?..."
|
|
sif cpuis("TMS570LS0232")||cpuis("TMS570LS0714*")||cpuis("TMS570LS0914*")
|
|
bitfld.long 0x10 16.--19. " TRIGSRC ,Trigger source" "Disabled,EXT0,EXT1,EXT2,EXT3,EXT4,EXT5,EXT6,EXT7,EXT8,EXT9,EXT10,EXT11,EXT12,EXT13,TICK"
|
|
else
|
|
bitfld.long 0x10 16.--19. " TRIGSRC ,Trigger source" "Disabled,GIOA[0],GIOA[1],GIOA[2],GIOA[3],GIOA[4],GIOA[5],GIOA[6],GIOA[7],N2HET1[8],N2HET1[10],N2HET1[12],N2HET1[14],N2HET1[16],N2HET1[18],TICK"
|
|
endif
|
|
newline
|
|
hexmask.long.byte 0x10 8.--14. 0x01 " PSTART ,TG start address"
|
|
hexmask.long.byte 0x10 0.--6. 0x01 " PCURRENT ,Pointer to current buffer"
|
|
line.long 0x14 "TG3CTRL,MibSPI Transfer Group Control Register 3"
|
|
bitfld.long 0x14 31. " TGENA ,TG enable" "Disabled,Enabled"
|
|
bitfld.long 0x14 30. " ONESHOT ,Single transfer for TG" "Disabled,Enabled"
|
|
bitfld.long 0x14 29. " PRST ,TG pointer reset mode" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x14 28. " TGTD ,TG triggered" "Not triggered,Triggered"
|
|
bitfld.long 0x14 20.--23. " TRGEVT ,Type of trigger event" "Never,Rising edge,Falling edge,Both edges,,High active,Low-active,Always,?..."
|
|
sif cpuis("TMS570LS0232")||cpuis("TMS570LS0714*")||cpuis("TMS570LS0914*")
|
|
bitfld.long 0x14 16.--19. " TRIGSRC ,Trigger source" "Disabled,EXT0,EXT1,EXT2,EXT3,EXT4,EXT5,EXT6,EXT7,EXT8,EXT9,EXT10,EXT11,EXT12,EXT13,TICK"
|
|
else
|
|
bitfld.long 0x14 16.--19. " TRIGSRC ,Trigger source" "Disabled,GIOA[0],GIOA[1],GIOA[2],GIOA[3],GIOA[4],GIOA[5],GIOA[6],GIOA[7],N2HET1[8],N2HET1[10],N2HET1[12],N2HET1[14],N2HET1[16],N2HET1[18],TICK"
|
|
endif
|
|
newline
|
|
hexmask.long.byte 0x14 8.--14. 0x01 " PSTART ,TG start address"
|
|
hexmask.long.byte 0x14 0.--6. 0x01 " PCURRENT ,Pointer to current buffer"
|
|
line.long 0x18 "TG4CTRL,MibSPI Transfer Group Control Register 4"
|
|
bitfld.long 0x18 31. " TGENA ,TG enable" "Disabled,Enabled"
|
|
bitfld.long 0x18 30. " ONESHOT ,Single transfer for TG" "Disabled,Enabled"
|
|
bitfld.long 0x18 29. " PRST ,TG pointer reset mode" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x18 28. " TGTD ,TG triggered" "Not triggered,Triggered"
|
|
bitfld.long 0x18 20.--23. " TRGEVT ,Type of trigger event" "Never,Rising edge,Falling edge,Both edges,,High active,Low-active,Always,?..."
|
|
sif cpuis("TMS570LS0232")||cpuis("TMS570LS0714*")||cpuis("TMS570LS0914*")
|
|
bitfld.long 0x18 16.--19. " TRIGSRC ,Trigger source" "Disabled,EXT0,EXT1,EXT2,EXT3,EXT4,EXT5,EXT6,EXT7,EXT8,EXT9,EXT10,EXT11,EXT12,EXT13,TICK"
|
|
else
|
|
bitfld.long 0x18 16.--19. " TRIGSRC ,Trigger source" "Disabled,GIOA[0],GIOA[1],GIOA[2],GIOA[3],GIOA[4],GIOA[5],GIOA[6],GIOA[7],N2HET1[8],N2HET1[10],N2HET1[12],N2HET1[14],N2HET1[16],N2HET1[18],TICK"
|
|
endif
|
|
newline
|
|
hexmask.long.byte 0x18 8.--14. 0x01 " PSTART ,TG start address"
|
|
hexmask.long.byte 0x18 0.--6. 0x01 " PCURRENT ,Pointer to current buffer"
|
|
line.long 0x1C "TG5CTRL,MibSPI Transfer Group Control Register 5"
|
|
bitfld.long 0x1C 31. " TGENA ,TG enable" "Disabled,Enabled"
|
|
bitfld.long 0x1C 30. " ONESHOT ,Single transfer for TG" "Disabled,Enabled"
|
|
bitfld.long 0x1C 29. " PRST ,TG pointer reset mode" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x1C 28. " TGTD ,TG triggered" "Not triggered,Triggered"
|
|
bitfld.long 0x1C 20.--23. " TRGEVT ,Type of trigger event" "Never,Rising edge,Falling edge,Both edges,,High active,Low-active,Always,?..."
|
|
sif cpuis("TMS570LS0232")||cpuis("TMS570LS0714*")||cpuis("TMS570LS0914*")
|
|
bitfld.long 0x1C 16.--19. " TRIGSRC ,Trigger source" "Disabled,EXT0,EXT1,EXT2,EXT3,EXT4,EXT5,EXT6,EXT7,EXT8,EXT9,EXT10,EXT11,EXT12,EXT13,TICK"
|
|
else
|
|
bitfld.long 0x1C 16.--19. " TRIGSRC ,Trigger source" "Disabled,GIOA[0],GIOA[1],GIOA[2],GIOA[3],GIOA[4],GIOA[5],GIOA[6],GIOA[7],N2HET1[8],N2HET1[10],N2HET1[12],N2HET1[14],N2HET1[16],N2HET1[18],TICK"
|
|
endif
|
|
newline
|
|
hexmask.long.byte 0x1C 8.--14. 0x01 " PSTART ,TG start address"
|
|
hexmask.long.byte 0x1C 0.--6. 0x01 " PCURRENT ,Pointer to current buffer"
|
|
line.long 0x20 "TG6CTRL,MibSPI Transfer Group Control Register 6"
|
|
bitfld.long 0x20 31. " TGENA ,TG enable" "Disabled,Enabled"
|
|
bitfld.long 0x20 30. " ONESHOT ,Single transfer for TG" "Disabled,Enabled"
|
|
bitfld.long 0x20 29. " PRST ,TG pointer reset mode" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x20 28. " TGTD ,TG triggered" "Not triggered,Triggered"
|
|
bitfld.long 0x20 20.--23. " TRGEVT ,Type of trigger event" "Never,Rising edge,Falling edge,Both edges,,High active,Low-active,Always,?..."
|
|
sif cpuis("TMS570LS0232")||cpuis("TMS570LS0714*")||cpuis("TMS570LS0914*")
|
|
bitfld.long 0x20 16.--19. " TRIGSRC ,Trigger source" "Disabled,EXT0,EXT1,EXT2,EXT3,EXT4,EXT5,EXT6,EXT7,EXT8,EXT9,EXT10,EXT11,EXT12,EXT13,TICK"
|
|
else
|
|
bitfld.long 0x20 16.--19. " TRIGSRC ,Trigger source" "Disabled,GIOA[0],GIOA[1],GIOA[2],GIOA[3],GIOA[4],GIOA[5],GIOA[6],GIOA[7],N2HET1[8],N2HET1[10],N2HET1[12],N2HET1[14],N2HET1[16],N2HET1[18],TICK"
|
|
endif
|
|
newline
|
|
hexmask.long.byte 0x20 8.--14. 0x01 " PSTART ,TG start address"
|
|
hexmask.long.byte 0x20 0.--6. 0x01 " PCURRENT ,Pointer to current buffer"
|
|
line.long 0x24 "TG7CTRL,MibSPI Transfer Group Control Register 7"
|
|
bitfld.long 0x24 31. " TGENA ,TG enable" "Disabled,Enabled"
|
|
bitfld.long 0x24 30. " ONESHOT ,Single transfer for TG" "Disabled,Enabled"
|
|
bitfld.long 0x24 29. " PRST ,TG pointer reset mode" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x24 28. " TGTD ,TG triggered" "Not triggered,Triggered"
|
|
bitfld.long 0x24 20.--23. " TRGEVT ,Type of trigger event" "Never,Rising edge,Falling edge,Both edges,,High active,Low-active,Always,?..."
|
|
sif cpuis("TMS570LS0232")||cpuis("TMS570LS0714*")||cpuis("TMS570LS0914*")
|
|
bitfld.long 0x24 16.--19. " TRIGSRC ,Trigger source" "Disabled,EXT0,EXT1,EXT2,EXT3,EXT4,EXT5,EXT6,EXT7,EXT8,EXT9,EXT10,EXT11,EXT12,EXT13,TICK"
|
|
else
|
|
bitfld.long 0x24 16.--19. " TRIGSRC ,Trigger source" "Disabled,GIOA[0],GIOA[1],GIOA[2],GIOA[3],GIOA[4],GIOA[5],GIOA[6],GIOA[7],N2HET1[8],N2HET1[10],N2HET1[12],N2HET1[14],N2HET1[16],N2HET1[18],TICK"
|
|
endif
|
|
newline
|
|
hexmask.long.byte 0x24 8.--14. 0x01 " PSTART ,TG start address"
|
|
hexmask.long.byte 0x24 0.--6. 0x01 " PCURRENT ,Pointer to current buffer"
|
|
line.long 0x28 "TG8CTRL,MibSPI Transfer Group Control Register 8"
|
|
bitfld.long 0x28 31. " TGENA ,TG enable" "Disabled,Enabled"
|
|
bitfld.long 0x28 30. " ONESHOT ,Single transfer for TG" "Disabled,Enabled"
|
|
bitfld.long 0x28 29. " PRST ,TG pointer reset mode" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x28 28. " TGTD ,TG triggered" "Not triggered,Triggered"
|
|
bitfld.long 0x28 20.--23. " TRGEVT ,Type of trigger event" "Never,Rising edge,Falling edge,Both edges,,High active,Low-active,Always,?..."
|
|
sif cpuis("TMS570LS0232")||cpuis("TMS570LS0714*")||cpuis("TMS570LS0914*")
|
|
bitfld.long 0x28 16.--19. " TRIGSRC ,Trigger source" "Disabled,EXT0,EXT1,EXT2,EXT3,EXT4,EXT5,EXT6,EXT7,EXT8,EXT9,EXT10,EXT11,EXT12,EXT13,TICK"
|
|
else
|
|
bitfld.long 0x28 16.--19. " TRIGSRC ,Trigger source" "Disabled,GIOA[0],GIOA[1],GIOA[2],GIOA[3],GIOA[4],GIOA[5],GIOA[6],GIOA[7],N2HET1[8],N2HET1[10],N2HET1[12],N2HET1[14],N2HET1[16],N2HET1[18],TICK"
|
|
endif
|
|
newline
|
|
hexmask.long.byte 0x28 8.--14. 0x01 " PSTART ,TG start address"
|
|
hexmask.long.byte 0x28 0.--6. 0x01 " PCURRENT ,Pointer to current buffer"
|
|
line.long 0x2C "TG9CTRL,MibSPI Transfer Group Control Register 9"
|
|
bitfld.long 0x2C 31. " TGENA ,TG enable" "Disabled,Enabled"
|
|
bitfld.long 0x2C 30. " ONESHOT ,Single transfer for TG" "Disabled,Enabled"
|
|
bitfld.long 0x2C 29. " PRST ,TG pointer reset mode" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x2C 28. " TGTD ,TG triggered" "Not triggered,Triggered"
|
|
bitfld.long 0x2C 20.--23. " TRGEVT ,Type of trigger event" "Never,Rising edge,Falling edge,Both edges,,High active,Low-active,Always,?..."
|
|
sif cpuis("TMS570LS0232")||cpuis("TMS570LS0714*")||cpuis("TMS570LS0914*")
|
|
bitfld.long 0x2C 16.--19. " TRIGSRC ,Trigger source" "Disabled,EXT0,EXT1,EXT2,EXT3,EXT4,EXT5,EXT6,EXT7,EXT8,EXT9,EXT10,EXT11,EXT12,EXT13,TICK"
|
|
else
|
|
bitfld.long 0x2C 16.--19. " TRIGSRC ,Trigger source" "Disabled,GIOA[0],GIOA[1],GIOA[2],GIOA[3],GIOA[4],GIOA[5],GIOA[6],GIOA[7],N2HET1[8],N2HET1[10],N2HET1[12],N2HET1[14],N2HET1[16],N2HET1[18],TICK"
|
|
endif
|
|
newline
|
|
hexmask.long.byte 0x2C 8.--14. 0x01 " PSTART ,TG start address"
|
|
hexmask.long.byte 0x2C 0.--6. 0x01 " PCURRENT ,Pointer to current buffer"
|
|
line.long 0x30 "TG10CTRL,MibSPI Transfer Group Control Register 10"
|
|
bitfld.long 0x30 31. " TGENA ,TG enable" "Disabled,Enabled"
|
|
bitfld.long 0x30 30. " ONESHOT ,Single transfer for TG" "Disabled,Enabled"
|
|
bitfld.long 0x30 29. " PRST ,TG pointer reset mode" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x30 28. " TGTD ,TG triggered" "Not triggered,Triggered"
|
|
bitfld.long 0x30 20.--23. " TRGEVT ,Type of trigger event" "Never,Rising edge,Falling edge,Both edges,,High active,Low-active,Always,?..."
|
|
sif cpuis("TMS570LS0232")||cpuis("TMS570LS0714*")||cpuis("TMS570LS0914*")
|
|
bitfld.long 0x30 16.--19. " TRIGSRC ,Trigger source" "Disabled,EXT0,EXT1,EXT2,EXT3,EXT4,EXT5,EXT6,EXT7,EXT8,EXT9,EXT10,EXT11,EXT12,EXT13,TICK"
|
|
else
|
|
bitfld.long 0x30 16.--19. " TRIGSRC ,Trigger source" "Disabled,GIOA[0],GIOA[1],GIOA[2],GIOA[3],GIOA[4],GIOA[5],GIOA[6],GIOA[7],N2HET1[8],N2HET1[10],N2HET1[12],N2HET1[14],N2HET1[16],N2HET1[18],TICK"
|
|
endif
|
|
newline
|
|
hexmask.long.byte 0x30 8.--14. 0x01 " PSTART ,TG start address"
|
|
hexmask.long.byte 0x30 0.--6. 0x01 " PCURRENT ,Pointer to current buffer"
|
|
line.long 0x34 "TG11CTRL,MibSPI Transfer Group Control Register 11"
|
|
bitfld.long 0x34 31. " TGENA ,TG enable" "Disabled,Enabled"
|
|
bitfld.long 0x34 30. " ONESHOT ,Single transfer for TG" "Disabled,Enabled"
|
|
bitfld.long 0x34 29. " PRST ,TG pointer reset mode" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x34 28. " TGTD ,TG triggered" "Not triggered,Triggered"
|
|
bitfld.long 0x34 20.--23. " TRGEVT ,Type of trigger event" "Never,Rising edge,Falling edge,Both edges,,High active,Low-active,Always,?..."
|
|
sif cpuis("TMS570LS0232")||cpuis("TMS570LS0714*")||cpuis("TMS570LS0914*")
|
|
bitfld.long 0x34 16.--19. " TRIGSRC ,Trigger source" "Disabled,EXT0,EXT1,EXT2,EXT3,EXT4,EXT5,EXT6,EXT7,EXT8,EXT9,EXT10,EXT11,EXT12,EXT13,TICK"
|
|
else
|
|
bitfld.long 0x34 16.--19. " TRIGSRC ,Trigger source" "Disabled,GIOA[0],GIOA[1],GIOA[2],GIOA[3],GIOA[4],GIOA[5],GIOA[6],GIOA[7],N2HET1[8],N2HET1[10],N2HET1[12],N2HET1[14],N2HET1[16],N2HET1[18],TICK"
|
|
endif
|
|
newline
|
|
hexmask.long.byte 0x34 8.--14. 0x01 " PSTART ,TG start address"
|
|
hexmask.long.byte 0x34 0.--6. 0x01 " PCURRENT ,Pointer to current buffer"
|
|
line.long 0x38 "TG12CTRL,MibSPI Transfer Group Control Register 12"
|
|
bitfld.long 0x38 31. " TGENA ,TG enable" "Disabled,Enabled"
|
|
bitfld.long 0x38 30. " ONESHOT ,Single transfer for TG" "Disabled,Enabled"
|
|
bitfld.long 0x38 29. " PRST ,TG pointer reset mode" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x38 28. " TGTD ,TG triggered" "Not triggered,Triggered"
|
|
bitfld.long 0x38 20.--23. " TRGEVT ,Type of trigger event" "Never,Rising edge,Falling edge,Both edges,,High active,Low-active,Always,?..."
|
|
sif cpuis("TMS570LS0232")||cpuis("TMS570LS0714*")||cpuis("TMS570LS0914*")
|
|
bitfld.long 0x38 16.--19. " TRIGSRC ,Trigger source" "Disabled,EXT0,EXT1,EXT2,EXT3,EXT4,EXT5,EXT6,EXT7,EXT8,EXT9,EXT10,EXT11,EXT12,EXT13,TICK"
|
|
else
|
|
bitfld.long 0x38 16.--19. " TRIGSRC ,Trigger source" "Disabled,GIOA[0],GIOA[1],GIOA[2],GIOA[3],GIOA[4],GIOA[5],GIOA[6],GIOA[7],N2HET1[8],N2HET1[10],N2HET1[12],N2HET1[14],N2HET1[16],N2HET1[18],TICK"
|
|
endif
|
|
newline
|
|
hexmask.long.byte 0x38 8.--14. 0x01 " PSTART ,TG start address"
|
|
hexmask.long.byte 0x38 0.--6. 0x01 " PCURRENT ,Pointer to current buffer"
|
|
line.long 0x3C "TG13CTRL,MibSPI Transfer Group Control Register 13"
|
|
bitfld.long 0x3C 31. " TGENA ,TG enable" "Disabled,Enabled"
|
|
bitfld.long 0x3C 30. " ONESHOT ,Single transfer for TG" "Disabled,Enabled"
|
|
bitfld.long 0x3C 29. " PRST ,TG pointer reset mode" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x3C 28. " TGTD ,TG triggered" "Not triggered,Triggered"
|
|
bitfld.long 0x3C 20.--23. " TRGEVT ,Type of trigger event" "Never,Rising edge,Falling edge,Both edges,,High active,Low-active,Always,?..."
|
|
sif cpuis("TMS570LS0232")||cpuis("TMS570LS0714*")||cpuis("TMS570LS0914*")
|
|
bitfld.long 0x3C 16.--19. " TRIGSRC ,Trigger source" "Disabled,EXT0,EXT1,EXT2,EXT3,EXT4,EXT5,EXT6,EXT7,EXT8,EXT9,EXT10,EXT11,EXT12,EXT13,TICK"
|
|
else
|
|
bitfld.long 0x3C 16.--19. " TRIGSRC ,Trigger source" "Disabled,GIOA[0],GIOA[1],GIOA[2],GIOA[3],GIOA[4],GIOA[5],GIOA[6],GIOA[7],N2HET1[8],N2HET1[10],N2HET1[12],N2HET1[14],N2HET1[16],N2HET1[18],TICK"
|
|
endif
|
|
newline
|
|
hexmask.long.byte 0x3C 8.--14. 0x01 " PSTART ,TG start address"
|
|
hexmask.long.byte 0x3C 0.--6. 0x01 " PCURRENT ,Pointer to current buffer"
|
|
line.long 0x40 "TG14CTRL,MibSPI Transfer Group Control Register 14"
|
|
bitfld.long 0x40 31. " TGENA ,TG enable" "Disabled,Enabled"
|
|
bitfld.long 0x40 30. " ONESHOT ,Single transfer for TG" "Disabled,Enabled"
|
|
bitfld.long 0x40 29. " PRST ,TG pointer reset mode" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x40 28. " TGTD ,TG triggered" "Not triggered,Triggered"
|
|
bitfld.long 0x40 20.--23. " TRGEVT ,Type of trigger event" "Never,Rising edge,Falling edge,Both edges,,High active,Low-active,Always,?..."
|
|
sif cpuis("TMS570LS0232")||cpuis("TMS570LS0714*")||cpuis("TMS570LS0914*")
|
|
bitfld.long 0x40 16.--19. " TRIGSRC ,Trigger source" "Disabled,EXT0,EXT1,EXT2,EXT3,EXT4,EXT5,EXT6,EXT7,EXT8,EXT9,EXT10,EXT11,EXT12,EXT13,TICK"
|
|
else
|
|
bitfld.long 0x40 16.--19. " TRIGSRC ,Trigger source" "Disabled,GIOA[0],GIOA[1],GIOA[2],GIOA[3],GIOA[4],GIOA[5],GIOA[6],GIOA[7],N2HET1[8],N2HET1[10],N2HET1[12],N2HET1[14],N2HET1[16],N2HET1[18],TICK"
|
|
endif
|
|
newline
|
|
hexmask.long.byte 0x40 8.--14. 0x01 " PSTART ,TG start address"
|
|
hexmask.long.byte 0x40 0.--6. 0x01 " PCURRENT ,Pointer to current buffer"
|
|
line.long 0x44 "TG15CTRL,MibSPI Transfer Group Control Register 15"
|
|
bitfld.long 0x44 31. " TGENA ,TG enable" "Disabled,Enabled"
|
|
bitfld.long 0x44 30. " ONESHOT ,Single transfer for TG" "Disabled,Enabled"
|
|
bitfld.long 0x44 29. " PRST ,TG pointer reset mode" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x44 28. " TGTD ,TG triggered" "Not triggered,Triggered"
|
|
bitfld.long 0x44 20.--23. " TRGEVT ,Type of trigger event" "Never,Rising edge,Falling edge,Both edges,,High active,Low-active,Always,?..."
|
|
sif cpuis("TMS570LS0232")||cpuis("TMS570LS0714*")||cpuis("TMS570LS0914*")
|
|
bitfld.long 0x44 16.--19. " TRIGSRC ,Trigger source" "Disabled,EXT0,EXT1,EXT2,EXT3,EXT4,EXT5,EXT6,EXT7,EXT8,EXT9,EXT10,EXT11,EXT12,EXT13,TICK"
|
|
else
|
|
bitfld.long 0x44 16.--19. " TRIGSRC ,Trigger source" "Disabled,GIOA[0],GIOA[1],GIOA[2],GIOA[3],GIOA[4],GIOA[5],GIOA[6],GIOA[7],N2HET1[8],N2HET1[10],N2HET1[12],N2HET1[14],N2HET1[16],N2HET1[18],TICK"
|
|
endif
|
|
newline
|
|
hexmask.long.byte 0x44 8.--14. 0x01 " PSTART ,TG start address"
|
|
hexmask.long.byte 0x44 0.--6. 0x01 " PCURRENT ,Pointer to current buffer"
|
|
sif (cpu()!=("TMS570LS0332")&&cpu()!=("TMS570LS0432")&&!cpuis("TMS570LS0232"))
|
|
group.long 0xD8++0x1F
|
|
line.long 0x0 "DMA0CTRL,MibSPI DMA Channel Control Register 1"
|
|
bitfld.long 0x0 31. " ONESHOT ,Auto-disable of DMA channel after ICOUNT+1 transfers" "0,1"
|
|
hexmask.long.byte 0x0 24.--30. 1. " BUFID ,Buffer utilized for DMA transfer"
|
|
bitfld.long 0x0 20.--23. " RXDMA_MAP ,Each MibSPI DMA channel can be linked to two physical DMA" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x0 16.--19. " TXDMA_MAP ,Each MibSPI DMA channel can be linked to two physical DMA" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x0 15. " RXDMAENA ,Receive data DMA channel enable" "Disabled,Enabled"
|
|
bitfld.long 0x0 14. " TXDMAENA ,Transmit data DMA channel enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x0 13. " NOBRK ,Non-interleaved DMA block transfer" "Not performed,Performed"
|
|
bitfld.long 0x0 8.--12. " ICOUNT ,Initial count of DMA transfers" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32"
|
|
bitfld.long 0x0 6. " COUNTBIT17 ,17th bit of the COUNT field of DMAxCOUNT register" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0.--5. " COUNT ,Actual number of remaining DMA transfers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
line.long 0x4 "DMA1CTRL,MibSPI DMA Channel Control Register 1"
|
|
bitfld.long 0x4 31. " ONESHOT ,Auto-disable of DMA channel after ICOUNT+1 transfers" "0,1"
|
|
hexmask.long.byte 0x4 24.--30. 1. " BUFID ,Buffer utilized for DMA transfer"
|
|
bitfld.long 0x4 20.--23. " RXDMA_MAP ,Each MibSPI DMA channel can be linked to two physical DMA" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x4 16.--19. " TXDMA_MAP ,Each MibSPI DMA channel can be linked to two physical DMA" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x4 15. " RXDMAENA ,Receive data DMA channel enable" "Disabled,Enabled"
|
|
bitfld.long 0x4 14. " TXDMAENA ,Transmit data DMA channel enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x4 13. " NOBRK ,Non-interleaved DMA block transfer" "Not performed,Performed"
|
|
bitfld.long 0x4 8.--12. " ICOUNT ,Initial count of DMA transfers" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32"
|
|
bitfld.long 0x4 6. " COUNTBIT17 ,17th bit of the COUNT field of DMAxCOUNT register" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0.--5. " COUNT ,Actual number of remaining DMA transfers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
line.long 0x8 "DMA2CTRL,MibSPI DMA Channel Control Register 1"
|
|
bitfld.long 0x8 31. " ONESHOT ,Auto-disable of DMA channel after ICOUNT+1 transfers" "0,1"
|
|
hexmask.long.byte 0x8 24.--30. 1. " BUFID ,Buffer utilized for DMA transfer"
|
|
bitfld.long 0x8 20.--23. " RXDMA_MAP ,Each MibSPI DMA channel can be linked to two physical DMA" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x8 16.--19. " TXDMA_MAP ,Each MibSPI DMA channel can be linked to two physical DMA" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x8 15. " RXDMAENA ,Receive data DMA channel enable" "Disabled,Enabled"
|
|
bitfld.long 0x8 14. " TXDMAENA ,Transmit data DMA channel enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x8 13. " NOBRK ,Non-interleaved DMA block transfer" "Not performed,Performed"
|
|
bitfld.long 0x8 8.--12. " ICOUNT ,Initial count of DMA transfers" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32"
|
|
bitfld.long 0x8 6. " COUNTBIT17 ,17th bit of the COUNT field of DMAxCOUNT register" "0,1"
|
|
newline
|
|
bitfld.long 0x8 0.--5. " COUNT ,Actual number of remaining DMA transfers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
line.long 0xC "DMA3CTRL,MibSPI DMA Channel Control Register 1"
|
|
bitfld.long 0xC 31. " ONESHOT ,Auto-disable of DMA channel after ICOUNT+1 transfers" "0,1"
|
|
hexmask.long.byte 0xC 24.--30. 1. " BUFID ,Buffer utilized for DMA transfer"
|
|
bitfld.long 0xC 20.--23. " RXDMA_MAP ,Each MibSPI DMA channel can be linked to two physical DMA" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0xC 16.--19. " TXDMA_MAP ,Each MibSPI DMA channel can be linked to two physical DMA" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0xC 15. " RXDMAENA ,Receive data DMA channel enable" "Disabled,Enabled"
|
|
bitfld.long 0xC 14. " TXDMAENA ,Transmit data DMA channel enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0xC 13. " NOBRK ,Non-interleaved DMA block transfer" "Not performed,Performed"
|
|
bitfld.long 0xC 8.--12. " ICOUNT ,Initial count of DMA transfers" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32"
|
|
bitfld.long 0xC 6. " COUNTBIT17 ,17th bit of the COUNT field of DMAxCOUNT register" "0,1"
|
|
newline
|
|
bitfld.long 0xC 0.--5. " COUNT ,Actual number of remaining DMA transfers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
line.long 0x10 "DMA4CTRL,MibSPI DMA Channel Control Register 1"
|
|
bitfld.long 0x10 31. " ONESHOT ,Auto-disable of DMA channel after ICOUNT+1 transfers" "0,1"
|
|
hexmask.long.byte 0x10 24.--30. 1. " BUFID ,Buffer utilized for DMA transfer"
|
|
bitfld.long 0x10 20.--23. " RXDMA_MAP ,Each MibSPI DMA channel can be linked to two physical DMA" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x10 16.--19. " TXDMA_MAP ,Each MibSPI DMA channel can be linked to two physical DMA" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x10 15. " RXDMAENA ,Receive data DMA channel enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 14. " TXDMAENA ,Transmit data DMA channel enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x10 13. " NOBRK ,Non-interleaved DMA block transfer" "Not performed,Performed"
|
|
bitfld.long 0x10 8.--12. " ICOUNT ,Initial count of DMA transfers" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32"
|
|
bitfld.long 0x10 6. " COUNTBIT17 ,17th bit of the COUNT field of DMAxCOUNT register" "0,1"
|
|
newline
|
|
bitfld.long 0x10 0.--5. " COUNT ,Actual number of remaining DMA transfers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
line.long 0x14 "DMA5CTRL,MibSPI DMA Channel Control Register 1"
|
|
bitfld.long 0x14 31. " ONESHOT ,Auto-disable of DMA channel after ICOUNT+1 transfers" "0,1"
|
|
hexmask.long.byte 0x14 24.--30. 1. " BUFID ,Buffer utilized for DMA transfer"
|
|
bitfld.long 0x14 20.--23. " RXDMA_MAP ,Each MibSPI DMA channel can be linked to two physical DMA" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x14 16.--19. " TXDMA_MAP ,Each MibSPI DMA channel can be linked to two physical DMA" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x14 15. " RXDMAENA ,Receive data DMA channel enable" "Disabled,Enabled"
|
|
bitfld.long 0x14 14. " TXDMAENA ,Transmit data DMA channel enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x14 13. " NOBRK ,Non-interleaved DMA block transfer" "Not performed,Performed"
|
|
bitfld.long 0x14 8.--12. " ICOUNT ,Initial count of DMA transfers" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32"
|
|
bitfld.long 0x14 6. " COUNTBIT17 ,17th bit of the COUNT field of DMAxCOUNT register" "0,1"
|
|
newline
|
|
bitfld.long 0x14 0.--5. " COUNT ,Actual number of remaining DMA transfers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
line.long 0x18 "DMA6CTRL,MibSPI DMA Channel Control Register 1"
|
|
bitfld.long 0x18 31. " ONESHOT ,Auto-disable of DMA channel after ICOUNT+1 transfers" "0,1"
|
|
hexmask.long.byte 0x18 24.--30. 1. " BUFID ,Buffer utilized for DMA transfer"
|
|
bitfld.long 0x18 20.--23. " RXDMA_MAP ,Each MibSPI DMA channel can be linked to two physical DMA" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x18 16.--19. " TXDMA_MAP ,Each MibSPI DMA channel can be linked to two physical DMA" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x18 15. " RXDMAENA ,Receive data DMA channel enable" "Disabled,Enabled"
|
|
bitfld.long 0x18 14. " TXDMAENA ,Transmit data DMA channel enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x18 13. " NOBRK ,Non-interleaved DMA block transfer" "Not performed,Performed"
|
|
bitfld.long 0x18 8.--12. " ICOUNT ,Initial count of DMA transfers" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32"
|
|
bitfld.long 0x18 6. " COUNTBIT17 ,17th bit of the COUNT field of DMAxCOUNT register" "0,1"
|
|
newline
|
|
bitfld.long 0x18 0.--5. " COUNT ,Actual number of remaining DMA transfers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
line.long 0x1C "DMA7CTRL,MibSPI DMA Channel Control Register 1"
|
|
bitfld.long 0x1C 31. " ONESHOT ,Auto-disable of DMA channel after ICOUNT+1 transfers" "0,1"
|
|
hexmask.long.byte 0x1C 24.--30. 1. " BUFID ,Buffer utilized for DMA transfer"
|
|
bitfld.long 0x1C 20.--23. " RXDMA_MAP ,Each MibSPI DMA channel can be linked to two physical DMA" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x1C 16.--19. " TXDMA_MAP ,Each MibSPI DMA channel can be linked to two physical DMA" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x1C 15. " RXDMAENA ,Receive data DMA channel enable" "Disabled,Enabled"
|
|
bitfld.long 0x1C 14. " TXDMAENA ,Transmit data DMA channel enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x1C 13. " NOBRK ,Non-interleaved DMA block transfer" "Not performed,Performed"
|
|
bitfld.long 0x1C 8.--12. " ICOUNT ,Initial count of DMA transfers" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32"
|
|
bitfld.long 0x1C 6. " COUNTBIT17 ,17th bit of the COUNT field of DMAxCOUNT register" "0,1"
|
|
newline
|
|
bitfld.long 0x1C 0.--5. " COUNT ,Actual number of remaining DMA transfers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
group.long 0xF8++0x1F
|
|
line.long 0x0 "DMA0 COUNT,MibSPI DMA0 COUNT Register"
|
|
hexmask.long.word 0x0 16.--31. 1. " ICOUNT0 ,Initial number of DMA transfers"
|
|
hexmask.long.word 0x0 0.--15. 1. " COUNT0 ,The actual number of remaining DMA transfers"
|
|
line.long 0x4 "DMA1 COUNT,MibSPI DMA1 COUNT Register"
|
|
hexmask.long.word 0x4 16.--31. 1. " ICOUNT1 ,Initial number of DMA transfers"
|
|
hexmask.long.word 0x4 0.--15. 1. " COUNT1 ,The actual number of remaining DMA transfers"
|
|
line.long 0x8 "DMA2 COUNT,MibSPI DMA2 COUNT Register"
|
|
hexmask.long.word 0x8 16.--31. 1. " ICOUNT2 ,Initial number of DMA transfers"
|
|
hexmask.long.word 0x8 0.--15. 1. " COUNT2 ,The actual number of remaining DMA transfers"
|
|
line.long 0xC "DMA3 COUNT,MibSPI DMA3 COUNT Register"
|
|
hexmask.long.word 0xC 16.--31. 1. " ICOUNT3 ,Initial number of DMA transfers"
|
|
hexmask.long.word 0xC 0.--15. 1. " COUNT3 ,The actual number of remaining DMA transfers"
|
|
line.long 0x10 "DMA4 COUNT,MibSPI DMA4 COUNT Register"
|
|
hexmask.long.word 0x10 16.--31. 1. " ICOUNT4 ,Initial number of DMA transfers"
|
|
hexmask.long.word 0x10 0.--15. 1. " COUNT4 ,The actual number of remaining DMA transfers"
|
|
line.long 0x14 "DMA5 COUNT,MibSPI DMA5 COUNT Register"
|
|
hexmask.long.word 0x14 16.--31. 1. " ICOUNT5 ,Initial number of DMA transfers"
|
|
hexmask.long.word 0x14 0.--15. 1. " COUNT5 ,The actual number of remaining DMA transfers"
|
|
line.long 0x18 "DMA6 COUNT,MibSPI DMA6 COUNT Register"
|
|
hexmask.long.word 0x18 16.--31. 1. " ICOUNT6 ,Initial number of DMA transfers"
|
|
hexmask.long.word 0x18 0.--15. 1. " COUNT6 ,The actual number of remaining DMA transfers"
|
|
line.long 0x1C "DMA7 COUNT,MibSPI DMA7 COUNT Register"
|
|
hexmask.long.word 0x1C 16.--31. 1. " ICOUNT7 ,Initial number of DMA transfers"
|
|
hexmask.long.word 0x1C 0.--15. 1. " COUNT7 ,The actual number of remaining DMA transfers"
|
|
group.long 0x118++0x03
|
|
line.long 0x00 "DMACNTLEN,MibSPI DMACNTLEN Register"
|
|
bitfld.long 0x00 0. " LARGECOUNT ,Counters select" "DMAxCTRL,DMAxCOUNT"
|
|
endif
|
|
group.long 0x120++0x03
|
|
line.long 0x00 "UERRCTRL,Uncorrectable Parity Error Control Register"
|
|
bitfld.long 0x00 8. " PTESTEN ,Parity memory test enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--3. " EDEN ,Error detection enable" "Enabled,Enabled,Enabled,Enabled,Enabled,Disabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled"
|
|
group.long 0x124++0x03
|
|
line.long 0x00 "UERRSTAT,Uncorrectable Parity Error Status Register"
|
|
eventfld.long 0x00 1. " EDFLG1 ,Uncorrectable parity error detection flag" "Not occurred,Occurred"
|
|
eventfld.long 0x00 0. " EDFLG0 ,Uncorrectable parity error detection flag" "Not occurred,Occurred"
|
|
hgroup.long 0x128++0x03
|
|
hide.long 0x00 "UERRADDR1,Uncorrectable Parity Error Address Register"
|
|
in
|
|
hgroup.long 0x12C++0x03
|
|
hide.long 0x00 "UERRADDR0,Uncorrectable Parity Error Address Register"
|
|
in
|
|
hgroup.long 0x130++0x03
|
|
hide.long 0x00 "RXOVRN_BUF_ADDR,Receive RAM Overrun Buffer Address Register"
|
|
in
|
|
sif cpuis("TMS570LS0714*")||cpuis("TMS570LS0914*")||cpuis("TMS570LS0232")
|
|
if (((per.l.be(ad:0xFFF7FC00+0x134))&0x2)==0x2)
|
|
group.long 0x134++0x03
|
|
line.long 0x00 "IOLPBKTSTCR,SPI IO Loopback Test Control Register"
|
|
bitfld.long 0x00 24. " SCSFAILFLG ,Failure on SPISCS pin compare during analog loopback" "Not occurred,Occurred"
|
|
bitfld.long 0x00 20. " CTRL_BITERR ,Controls inducing of BITERR during I/O loopback test mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " CTRL_DESYNC ,Controls inducing of the desync error during I/O loopback test mode" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 18. " CTRL_PARERR ,Controls inducing of parity errors during I/O loopback test mode" "No error,Error"
|
|
bitfld.long 0x00 17. " CTRL_TIMEOUT ,Controls inducing of the timeout error during I/O loopbacK test mode" "No error,Error"
|
|
bitfld.long 0x00 16. " CTRL_DLENERR ,Controls inducing of the data length error during I/O loopback test mode" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 8.--11. " IOLPBKTSTENA ,Module I/O loopback test enable key" "Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Enabled,Disabled,Disabled,Disabled,Disabled,Disabled"
|
|
sif cpuis("TMS570LS0232")
|
|
bitfld.long 0x00 3.--5. " ERRSCSPIN ,Inject error on chip-select pin number" "/SPISCS[0],/SPISCS[1],/SPISCS[2],/SPISCS[3],?..."
|
|
else
|
|
bitfld.long 0x00 3.--5. " ERRSCSPIN ,Inject error on chip-select pin number" "/SPISCS[0],/SPISCS[1],/SPISCS[2],/SPISCS[3],/SPISCS[4],/SPISCS[5],/SPISCS[6],/SPISCS[7]"
|
|
endif
|
|
bitfld.long 0x00 2. " CTRLSCSPINERR ,Enable/disable the injection of an error on the SPISCS[3:0] pins" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 1. " LPBK_TYPE ,Module I/O loopback type (analog/digital)" "Digital,Analog"
|
|
bitfld.long 0x00 0. " RXP_ENA ,Enable analog loopback through the receive pin" "Transmit,Receive"
|
|
else
|
|
group.long 0x134++0x03
|
|
line.long 0x00 "IOLPBKTSTCR,SPI IO Loopback Test Control Register"
|
|
bitfld.long 0x00 24. " SCSFAILFLG ,Failure on SPISCS pin compare during analog loopback" "Not occurred,Occurred"
|
|
bitfld.long 0x00 20. " CTRL_BITERR ,Controls inducing of BITERR during I/O loopback test mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " CTRL_DESYNC ,Controls inducing of the desync error during I/O loopback test mode" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 18. " CTRL_PARERR ,Controls inducing of parity errors during I/O loopback test mode" "No error,Error"
|
|
bitfld.long 0x00 17. " CTRL_TIMEOUT ,Controls inducing of the timeout error during I/O loopbacK test mode" "No error,Error"
|
|
bitfld.long 0x00 16. " CTRL_DLENERR ,Controls inducing of the data length error during I/O loopback test mode" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 8.--11. " IOLPBKTSTENA ,Module I/O loopback test enable key" "Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Enabled,Disabled,Disabled,Disabled,Disabled,Disabled"
|
|
sif cpuis("TMS570LS0232")
|
|
bitfld.long 0x00 3.--5. " ERRSCSPIN ,Inject error on chip-select pin number" "/SPISCS[0],/SPISCS[1],/SPISCS[2],/SPISCS[3],?..."
|
|
else
|
|
bitfld.long 0x00 3.--5. " ERRSCSPIN ,Inject error on chip-select pin number" "/SPISCS[0],/SPISCS[1],/SPISCS[2],/SPISCS[3],/SPISCS[4],/SPISCS[5],/SPISCS[6],/SPISCS[7]"
|
|
endif
|
|
bitfld.long 0x00 2. " CTRLSCSPINERR ,Enable/disable the injection of an error on the SPISCS[3:0] pins" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 1. " LPBK_TYPE ,Module I/O loopback type (analog/digital)" "Digital,Analog"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0xFFF7FC00+0x134))&0x2)==0x2)
|
|
group.long 0x134++0x03
|
|
line.long 0x00 "IOLPBKTSTCR,SPI IO Loopback Test Control Register"
|
|
bitfld.long 0x00 24. " SCSFAILFLG ,Failure on SPISCS pin compare during analog loopback" "Not occurred,Occurred"
|
|
bitfld.long 0x00 20. " CTRL_BITERR ,Controls inducing of BITERR during I/O loopback test mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " CTRL_DESYNC ,Controls inducing of the desync error during I/O loopback test mode" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 18. " CTRL_PARERR ,Controls inducing of parity errors during I/O loopback test mode" "No error,Error"
|
|
bitfld.long 0x00 17. " CTRL_TIMEOUT ,Controls inducing of the timeout error during I/O loopbacK test mode" "No error,Error"
|
|
bitfld.long 0x00 16. " CTRL_DLENERR ,Controls inducing of the data length error during I/O loopback test mode" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 8.--11. " IOLPBKTSTENA ,Module I/O loopback test enable key" "Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Enabled,Disabled,Disabled,Disabled,Disabled,Disabled"
|
|
bitfld.long 0x00 3.--5. " ERRSCSPIN ,Inject error on chip-select pin number" "/SPISCS[0],/SPISCS[1],/SPISCS[2],/SPISCS[3],/SPISCS[4],/SPISCS[5],/SPISCS[6],/SPISCS[7]"
|
|
bitfld.long 0x00 2. " CTRLSCSPINERR ,Enable/disable the injection of an error on the SPISCS[3:0] pins" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 1. " LPBK_TYPE ,Module I/O loopback type (analog/digital)" "Digital,Analog"
|
|
bitfld.long 0x00 0. " RXP_ENA ,Enable analog loopback through the receive pin" "Transmit,Receive"
|
|
else
|
|
group.long 0x134++0x03
|
|
line.long 0x00 "IOLPBKTSTCR,SPI IO Loopback Test Control Register"
|
|
bitfld.long 0x00 24. " SCSFAILFLG ,Failure on SPISCS pin compare during analog loopback" "Not occurred,Occurred"
|
|
bitfld.long 0x00 20. " CTRL_BITERR ,Controls inducing of BITERR during I/O loopback test mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " CTRL_DESYNC ,Controls inducing of the desync error during I/O loopback test mode" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 18. " CTRL_PARERR ,Controls inducing of parity errors during I/O loopback test mode" "No error,Error"
|
|
bitfld.long 0x00 17. " CTRL_TIMEOUT ,Controls inducing of the timeout error during I/O loopbacK test mode" "No error,Error"
|
|
bitfld.long 0x00 16. " CTRL_DLENERR ,Controls inducing of the data length error during I/O loopback test mode" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 8.--11. " IOLPBKTSTENA ,Module I/O loopback test enable key" "Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Enabled,Disabled,Disabled,Disabled,Disabled,Disabled"
|
|
bitfld.long 0x00 3.--5. " ERRSCSPIN ,Inject error on chip-select pin number" "/SPISCS[0],/SPISCS[1],/SPISCS[2],/SPISCS[3],/SPISCS[4],/SPISCS[5],/SPISCS[6],/SPISCS[7]"
|
|
bitfld.long 0x00 2. " CTRLSCSPINERR ,Enable/disable the injection of an error on the SPISCS[3:0] pins" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 1. " LPBK_TYPE ,Module I/O loopback type (analog/digital)" "Digital,Analog"
|
|
endif
|
|
endif
|
|
sif (cpu()=="TMS570LC4357"||cpu()==("TMS570LS0332")||cpu()==("TMS570LS0432")||cpuis("TMS570LS1114*")||cpuis("TMS570LS1115*")||cpuis("TMS570LS1224*")||cpuis("TMS570LS1225*")||cpuis("TMS570LS1227*")||cpuis("TMS570LS0232")||cpuis("TMS570LS0714*")||cpuis("TMS570LS0914*"))
|
|
width 21.
|
|
newline
|
|
group.long 0x138++0x07
|
|
line.long 0x00 "EXTENDED_PRESCALE_1, SPI Extended Prescale Register 1"
|
|
hexmask.long.word 0x00 16.--26. 1. " EPRESCALE_FMT1 , Extended Prescale value for SPIFMT1"
|
|
hexmask.long.word 0x00 0.--10. 1. " EPRESCALE_FMT0 , Extended Prescale value for SPIFMT0"
|
|
line.long 0x04 "EXTENDED_PRESCALE_2, SPI Extended Prescale Register 2"
|
|
hexmask.long.word 0x04 16.--26. 1. " EPRESCALE_FMT3 , Extended Prescale value for SPIFMT3"
|
|
hexmask.long.word 0x04 0.--10. 1. " EPRESCALE_FMT2 , Extended Prescale value for SPIFMT2"
|
|
endif
|
|
sif !cpuis("TMS570LS0232")&&!cpuis("TMS570LS0714*")&&!cpuis("TMS570LS0914*")
|
|
sif (cpu()=="TMS570LC4357"||cpu()==("TMS570LS0332")||cpu()==("TMS570LS0432")||cpuis("TMS570LS1114*")||cpuis("TMS570LS1115*")||cpuis("TMS570LS1224*")||cpuis("TMS570LS1225*")||cpuis("TMS570LS1227*"))
|
|
sif cpuis("TMS570LC4357")
|
|
group.long 0x140++0x03
|
|
line.long 0x00 "ECCDIAG_CTRL, ECC Diagnostic Control register"
|
|
bitfld.long 0x00 0.--3. " ECCDIAG_EN , ECC Diagnostic mode Enable Key bits" "Disabled,Disabled,Disabled,Disabled,Disabled,Enabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled"
|
|
endif
|
|
if ((per.l(ad:0xFFF7FC00+0x140)&0x5)==0x5)
|
|
group.long 0x144++0x03
|
|
line.long 0x00 "ECCDIAG_STAT, ECC Diagnostic Status register"
|
|
eventfld.long 0x00 17. " DEFLG[1] , Double bit Error is detected for RXRAM" "No error,Error"
|
|
eventfld.long 0x00 16. " DEFLG[0] , Double bit Error is detected for TXRAM" "No error,Error"
|
|
eventfld.long 0x00 1. " SEFLG[1] , Single bit Error is detected for RXRAM" "No error,Error"
|
|
eventfld.long 0x00 0. " SEFLG[0] , Single bit Error is detected for TXRAM" "No error,Error"
|
|
else
|
|
hgroup.long 0x144++0x03
|
|
hide.long 0x00 "ECCDIAG_STAT, ECC Diagnostic Status register"
|
|
in
|
|
endif
|
|
hgroup.long 0x148++0x03
|
|
hide.long 0x00 "SBERRADDR1, Single Bit Error Address Register - RXRAM"
|
|
in
|
|
hgroup.long 0x14C++0x03
|
|
hide.long 0x00 "SBERRADDR0, Single Bit Error Address Register - TXRAM"
|
|
in
|
|
endif
|
|
endif
|
|
sif cpuis("TMS570LS0232")||cpuis("TMS570LS0714*")||cpuis("TMS570LS0914*")
|
|
endian.be
|
|
endif
|
|
width 0xB
|
|
tree.end
|
|
tree "MibSPI5 RAM"
|
|
base ad:0xFF0A0000
|
|
sif cpuis("TMS570LS0232")||cpuis("TMS570LS0714*")||cpuis("TMS570LS0914*")
|
|
endian.be
|
|
endif
|
|
width 11.
|
|
sif (cpu()==("TMS570LS0332")||cpu()==("TMS570LS0432")||cpuis("TMS570LS1114*")||cpuis("TMS570LS1115*")||cpuis("TMS570LS1224*")||cpuis("TMS570LS1225*")||cpuis("TMS570LS1227*"))
|
|
group.long 0x0++0x03
|
|
line.long 0x00 "TXRAM, Multi-buffer RAM Transmit Data Register 0"
|
|
bitfld.long 0x00 29.--31. " BUFMODE , Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip Single Transfer,Skip Overwrite,Skip ST-Overwrite,Continuous,Suspend Single Transfer,Suspend Overwrite,Suspend ST-Overwrite"
|
|
bitfld.long 0x00 28. " CSHOLD , Chip select hold mode" "Deactivated,Activated"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK , Lock two consecutive buffer words" "0,1"
|
|
bitfld.long 0x00 26. " WDEL , Enable the delay counter at the end of the current transaction" "Disable,Enable"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL , Data word format select" "Format 0,Format 1,Format 2,Format 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR , Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA , Transfer data"
|
|
group.long 0x4++0x03
|
|
line.long 0x00 "TXRAM, Multi-buffer RAM Transmit Data Register 1"
|
|
bitfld.long 0x00 29.--31. " BUFMODE , Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip Single Transfer,Skip Overwrite,Skip ST-Overwrite,Continuous,Suspend Single Transfer,Suspend Overwrite,Suspend ST-Overwrite"
|
|
bitfld.long 0x00 28. " CSHOLD , Chip select hold mode" "Deactivated,Activated"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK , Lock two consecutive buffer words" "0,1"
|
|
bitfld.long 0x00 26. " WDEL , Enable the delay counter at the end of the current transaction" "Disable,Enable"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL , Data word format select" "Format 0,Format 1,Format 2,Format 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR , Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA , Transfer data"
|
|
group.long 0x8++0x03
|
|
line.long 0x00 "TXRAM, Multi-buffer RAM Transmit Data Register 2"
|
|
bitfld.long 0x00 29.--31. " BUFMODE , Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip Single Transfer,Skip Overwrite,Skip ST-Overwrite,Continuous,Suspend Single Transfer,Suspend Overwrite,Suspend ST-Overwrite"
|
|
bitfld.long 0x00 28. " CSHOLD , Chip select hold mode" "Deactivated,Activated"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK , Lock two consecutive buffer words" "0,1"
|
|
bitfld.long 0x00 26. " WDEL , Enable the delay counter at the end of the current transaction" "Disable,Enable"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL , Data word format select" "Format 0,Format 1,Format 2,Format 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR , Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA , Transfer data"
|
|
group.long 0xC++0x03
|
|
line.long 0x00 "TXRAM, Multi-buffer RAM Transmit Data Register 3"
|
|
bitfld.long 0x00 29.--31. " BUFMODE , Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip Single Transfer,Skip Overwrite,Skip ST-Overwrite,Continuous,Suspend Single Transfer,Suspend Overwrite,Suspend ST-Overwrite"
|
|
bitfld.long 0x00 28. " CSHOLD , Chip select hold mode" "Deactivated,Activated"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK , Lock two consecutive buffer words" "0,1"
|
|
bitfld.long 0x00 26. " WDEL , Enable the delay counter at the end of the current transaction" "Disable,Enable"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL , Data word format select" "Format 0,Format 1,Format 2,Format 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR , Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA , Transfer data"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "TXRAM, Multi-buffer RAM Transmit Data Register 4"
|
|
bitfld.long 0x00 29.--31. " BUFMODE , Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip Single Transfer,Skip Overwrite,Skip ST-Overwrite,Continuous,Suspend Single Transfer,Suspend Overwrite,Suspend ST-Overwrite"
|
|
bitfld.long 0x00 28. " CSHOLD , Chip select hold mode" "Deactivated,Activated"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK , Lock two consecutive buffer words" "0,1"
|
|
bitfld.long 0x00 26. " WDEL , Enable the delay counter at the end of the current transaction" "Disable,Enable"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL , Data word format select" "Format 0,Format 1,Format 2,Format 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR , Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA , Transfer data"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "TXRAM, Multi-buffer RAM Transmit Data Register 5"
|
|
bitfld.long 0x00 29.--31. " BUFMODE , Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip Single Transfer,Skip Overwrite,Skip ST-Overwrite,Continuous,Suspend Single Transfer,Suspend Overwrite,Suspend ST-Overwrite"
|
|
bitfld.long 0x00 28. " CSHOLD , Chip select hold mode" "Deactivated,Activated"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK , Lock two consecutive buffer words" "0,1"
|
|
bitfld.long 0x00 26. " WDEL , Enable the delay counter at the end of the current transaction" "Disable,Enable"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL , Data word format select" "Format 0,Format 1,Format 2,Format 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR , Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA , Transfer data"
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "TXRAM, Multi-buffer RAM Transmit Data Register 6"
|
|
bitfld.long 0x00 29.--31. " BUFMODE , Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip Single Transfer,Skip Overwrite,Skip ST-Overwrite,Continuous,Suspend Single Transfer,Suspend Overwrite,Suspend ST-Overwrite"
|
|
bitfld.long 0x00 28. " CSHOLD , Chip select hold mode" "Deactivated,Activated"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK , Lock two consecutive buffer words" "0,1"
|
|
bitfld.long 0x00 26. " WDEL , Enable the delay counter at the end of the current transaction" "Disable,Enable"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL , Data word format select" "Format 0,Format 1,Format 2,Format 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR , Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA , Transfer data"
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "TXRAM, Multi-buffer RAM Transmit Data Register 7"
|
|
bitfld.long 0x00 29.--31. " BUFMODE , Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip Single Transfer,Skip Overwrite,Skip ST-Overwrite,Continuous,Suspend Single Transfer,Suspend Overwrite,Suspend ST-Overwrite"
|
|
bitfld.long 0x00 28. " CSHOLD , Chip select hold mode" "Deactivated,Activated"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK , Lock two consecutive buffer words" "0,1"
|
|
bitfld.long 0x00 26. " WDEL , Enable the delay counter at the end of the current transaction" "Disable,Enable"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL , Data word format select" "Format 0,Format 1,Format 2,Format 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR , Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA , Transfer data"
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "TXRAM, Multi-buffer RAM Transmit Data Register 8"
|
|
bitfld.long 0x00 29.--31. " BUFMODE , Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip Single Transfer,Skip Overwrite,Skip ST-Overwrite,Continuous,Suspend Single Transfer,Suspend Overwrite,Suspend ST-Overwrite"
|
|
bitfld.long 0x00 28. " CSHOLD , Chip select hold mode" "Deactivated,Activated"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK , Lock two consecutive buffer words" "0,1"
|
|
bitfld.long 0x00 26. " WDEL , Enable the delay counter at the end of the current transaction" "Disable,Enable"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL , Data word format select" "Format 0,Format 1,Format 2,Format 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR , Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA , Transfer data"
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "TXRAM, Multi-buffer RAM Transmit Data Register 9"
|
|
bitfld.long 0x00 29.--31. " BUFMODE , Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip Single Transfer,Skip Overwrite,Skip ST-Overwrite,Continuous,Suspend Single Transfer,Suspend Overwrite,Suspend ST-Overwrite"
|
|
bitfld.long 0x00 28. " CSHOLD , Chip select hold mode" "Deactivated,Activated"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK , Lock two consecutive buffer words" "0,1"
|
|
bitfld.long 0x00 26. " WDEL , Enable the delay counter at the end of the current transaction" "Disable,Enable"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL , Data word format select" "Format 0,Format 1,Format 2,Format 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR , Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA , Transfer data"
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "TXRAM, Multi-buffer RAM Transmit Data Register 10"
|
|
bitfld.long 0x00 29.--31. " BUFMODE , Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip Single Transfer,Skip Overwrite,Skip ST-Overwrite,Continuous,Suspend Single Transfer,Suspend Overwrite,Suspend ST-Overwrite"
|
|
bitfld.long 0x00 28. " CSHOLD , Chip select hold mode" "Deactivated,Activated"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK , Lock two consecutive buffer words" "0,1"
|
|
bitfld.long 0x00 26. " WDEL , Enable the delay counter at the end of the current transaction" "Disable,Enable"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL , Data word format select" "Format 0,Format 1,Format 2,Format 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR , Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA , Transfer data"
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "TXRAM, Multi-buffer RAM Transmit Data Register 11"
|
|
bitfld.long 0x00 29.--31. " BUFMODE , Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip Single Transfer,Skip Overwrite,Skip ST-Overwrite,Continuous,Suspend Single Transfer,Suspend Overwrite,Suspend ST-Overwrite"
|
|
bitfld.long 0x00 28. " CSHOLD , Chip select hold mode" "Deactivated,Activated"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK , Lock two consecutive buffer words" "0,1"
|
|
bitfld.long 0x00 26. " WDEL , Enable the delay counter at the end of the current transaction" "Disable,Enable"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL , Data word format select" "Format 0,Format 1,Format 2,Format 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR , Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA , Transfer data"
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "TXRAM, Multi-buffer RAM Transmit Data Register 12"
|
|
bitfld.long 0x00 29.--31. " BUFMODE , Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip Single Transfer,Skip Overwrite,Skip ST-Overwrite,Continuous,Suspend Single Transfer,Suspend Overwrite,Suspend ST-Overwrite"
|
|
bitfld.long 0x00 28. " CSHOLD , Chip select hold mode" "Deactivated,Activated"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK , Lock two consecutive buffer words" "0,1"
|
|
bitfld.long 0x00 26. " WDEL , Enable the delay counter at the end of the current transaction" "Disable,Enable"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL , Data word format select" "Format 0,Format 1,Format 2,Format 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR , Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA , Transfer data"
|
|
group.long 0x34++0x03
|
|
line.long 0x00 "TXRAM, Multi-buffer RAM Transmit Data Register 13"
|
|
bitfld.long 0x00 29.--31. " BUFMODE , Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip Single Transfer,Skip Overwrite,Skip ST-Overwrite,Continuous,Suspend Single Transfer,Suspend Overwrite,Suspend ST-Overwrite"
|
|
bitfld.long 0x00 28. " CSHOLD , Chip select hold mode" "Deactivated,Activated"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK , Lock two consecutive buffer words" "0,1"
|
|
bitfld.long 0x00 26. " WDEL , Enable the delay counter at the end of the current transaction" "Disable,Enable"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL , Data word format select" "Format 0,Format 1,Format 2,Format 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR , Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA , Transfer data"
|
|
group.long 0x38++0x03
|
|
line.long 0x00 "TXRAM, Multi-buffer RAM Transmit Data Register 14"
|
|
bitfld.long 0x00 29.--31. " BUFMODE , Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip Single Transfer,Skip Overwrite,Skip ST-Overwrite,Continuous,Suspend Single Transfer,Suspend Overwrite,Suspend ST-Overwrite"
|
|
bitfld.long 0x00 28. " CSHOLD , Chip select hold mode" "Deactivated,Activated"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK , Lock two consecutive buffer words" "0,1"
|
|
bitfld.long 0x00 26. " WDEL , Enable the delay counter at the end of the current transaction" "Disable,Enable"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL , Data word format select" "Format 0,Format 1,Format 2,Format 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR , Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA , Transfer data"
|
|
group.long 0x3C++0x03
|
|
line.long 0x00 "TXRAM, Multi-buffer RAM Transmit Data Register 15"
|
|
bitfld.long 0x00 29.--31. " BUFMODE , Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip Single Transfer,Skip Overwrite,Skip ST-Overwrite,Continuous,Suspend Single Transfer,Suspend Overwrite,Suspend ST-Overwrite"
|
|
bitfld.long 0x00 28. " CSHOLD , Chip select hold mode" "Deactivated,Activated"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK , Lock two consecutive buffer words" "0,1"
|
|
bitfld.long 0x00 26. " WDEL , Enable the delay counter at the end of the current transaction" "Disable,Enable"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL , Data word format select" "Format 0,Format 1,Format 2,Format 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR , Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA , Transfer data"
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "TXRAM, Multi-buffer RAM Transmit Data Register 16"
|
|
bitfld.long 0x00 29.--31. " BUFMODE , Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip Single Transfer,Skip Overwrite,Skip ST-Overwrite,Continuous,Suspend Single Transfer,Suspend Overwrite,Suspend ST-Overwrite"
|
|
bitfld.long 0x00 28. " CSHOLD , Chip select hold mode" "Deactivated,Activated"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK , Lock two consecutive buffer words" "0,1"
|
|
bitfld.long 0x00 26. " WDEL , Enable the delay counter at the end of the current transaction" "Disable,Enable"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL , Data word format select" "Format 0,Format 1,Format 2,Format 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR , Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA , Transfer data"
|
|
group.long 0x44++0x03
|
|
line.long 0x00 "TXRAM, Multi-buffer RAM Transmit Data Register 17"
|
|
bitfld.long 0x00 29.--31. " BUFMODE , Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip Single Transfer,Skip Overwrite,Skip ST-Overwrite,Continuous,Suspend Single Transfer,Suspend Overwrite,Suspend ST-Overwrite"
|
|
bitfld.long 0x00 28. " CSHOLD , Chip select hold mode" "Deactivated,Activated"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK , Lock two consecutive buffer words" "0,1"
|
|
bitfld.long 0x00 26. " WDEL , Enable the delay counter at the end of the current transaction" "Disable,Enable"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL , Data word format select" "Format 0,Format 1,Format 2,Format 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR , Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA , Transfer data"
|
|
group.long 0x48++0x03
|
|
line.long 0x00 "TXRAM, Multi-buffer RAM Transmit Data Register 18"
|
|
bitfld.long 0x00 29.--31. " BUFMODE , Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip Single Transfer,Skip Overwrite,Skip ST-Overwrite,Continuous,Suspend Single Transfer,Suspend Overwrite,Suspend ST-Overwrite"
|
|
bitfld.long 0x00 28. " CSHOLD , Chip select hold mode" "Deactivated,Activated"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK , Lock two consecutive buffer words" "0,1"
|
|
bitfld.long 0x00 26. " WDEL , Enable the delay counter at the end of the current transaction" "Disable,Enable"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL , Data word format select" "Format 0,Format 1,Format 2,Format 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR , Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA , Transfer data"
|
|
group.long 0x4C++0x03
|
|
line.long 0x00 "TXRAM, Multi-buffer RAM Transmit Data Register 19"
|
|
bitfld.long 0x00 29.--31. " BUFMODE , Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip Single Transfer,Skip Overwrite,Skip ST-Overwrite,Continuous,Suspend Single Transfer,Suspend Overwrite,Suspend ST-Overwrite"
|
|
bitfld.long 0x00 28. " CSHOLD , Chip select hold mode" "Deactivated,Activated"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK , Lock two consecutive buffer words" "0,1"
|
|
bitfld.long 0x00 26. " WDEL , Enable the delay counter at the end of the current transaction" "Disable,Enable"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL , Data word format select" "Format 0,Format 1,Format 2,Format 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR , Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA , Transfer data"
|
|
group.long 0x50++0x03
|
|
line.long 0x00 "TXRAM, Multi-buffer RAM Transmit Data Register 20"
|
|
bitfld.long 0x00 29.--31. " BUFMODE , Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip Single Transfer,Skip Overwrite,Skip ST-Overwrite,Continuous,Suspend Single Transfer,Suspend Overwrite,Suspend ST-Overwrite"
|
|
bitfld.long 0x00 28. " CSHOLD , Chip select hold mode" "Deactivated,Activated"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK , Lock two consecutive buffer words" "0,1"
|
|
bitfld.long 0x00 26. " WDEL , Enable the delay counter at the end of the current transaction" "Disable,Enable"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL , Data word format select" "Format 0,Format 1,Format 2,Format 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR , Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA , Transfer data"
|
|
group.long 0x54++0x03
|
|
line.long 0x00 "TXRAM, Multi-buffer RAM Transmit Data Register 21"
|
|
bitfld.long 0x00 29.--31. " BUFMODE , Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip Single Transfer,Skip Overwrite,Skip ST-Overwrite,Continuous,Suspend Single Transfer,Suspend Overwrite,Suspend ST-Overwrite"
|
|
bitfld.long 0x00 28. " CSHOLD , Chip select hold mode" "Deactivated,Activated"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK , Lock two consecutive buffer words" "0,1"
|
|
bitfld.long 0x00 26. " WDEL , Enable the delay counter at the end of the current transaction" "Disable,Enable"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL , Data word format select" "Format 0,Format 1,Format 2,Format 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR , Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA , Transfer data"
|
|
group.long 0x58++0x03
|
|
line.long 0x00 "TXRAM, Multi-buffer RAM Transmit Data Register 22"
|
|
bitfld.long 0x00 29.--31. " BUFMODE , Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip Single Transfer,Skip Overwrite,Skip ST-Overwrite,Continuous,Suspend Single Transfer,Suspend Overwrite,Suspend ST-Overwrite"
|
|
bitfld.long 0x00 28. " CSHOLD , Chip select hold mode" "Deactivated,Activated"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK , Lock two consecutive buffer words" "0,1"
|
|
bitfld.long 0x00 26. " WDEL , Enable the delay counter at the end of the current transaction" "Disable,Enable"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL , Data word format select" "Format 0,Format 1,Format 2,Format 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR , Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA , Transfer data"
|
|
group.long 0x5C++0x03
|
|
line.long 0x00 "TXRAM, Multi-buffer RAM Transmit Data Register 23"
|
|
bitfld.long 0x00 29.--31. " BUFMODE , Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip Single Transfer,Skip Overwrite,Skip ST-Overwrite,Continuous,Suspend Single Transfer,Suspend Overwrite,Suspend ST-Overwrite"
|
|
bitfld.long 0x00 28. " CSHOLD , Chip select hold mode" "Deactivated,Activated"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK , Lock two consecutive buffer words" "0,1"
|
|
bitfld.long 0x00 26. " WDEL , Enable the delay counter at the end of the current transaction" "Disable,Enable"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL , Data word format select" "Format 0,Format 1,Format 2,Format 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR , Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA , Transfer data"
|
|
group.long 0x60++0x03
|
|
line.long 0x00 "TXRAM, Multi-buffer RAM Transmit Data Register 24"
|
|
bitfld.long 0x00 29.--31. " BUFMODE , Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip Single Transfer,Skip Overwrite,Skip ST-Overwrite,Continuous,Suspend Single Transfer,Suspend Overwrite,Suspend ST-Overwrite"
|
|
bitfld.long 0x00 28. " CSHOLD , Chip select hold mode" "Deactivated,Activated"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK , Lock two consecutive buffer words" "0,1"
|
|
bitfld.long 0x00 26. " WDEL , Enable the delay counter at the end of the current transaction" "Disable,Enable"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL , Data word format select" "Format 0,Format 1,Format 2,Format 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR , Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA , Transfer data"
|
|
group.long 0x64++0x03
|
|
line.long 0x00 "TXRAM, Multi-buffer RAM Transmit Data Register 25"
|
|
bitfld.long 0x00 29.--31. " BUFMODE , Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip Single Transfer,Skip Overwrite,Skip ST-Overwrite,Continuous,Suspend Single Transfer,Suspend Overwrite,Suspend ST-Overwrite"
|
|
bitfld.long 0x00 28. " CSHOLD , Chip select hold mode" "Deactivated,Activated"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK , Lock two consecutive buffer words" "0,1"
|
|
bitfld.long 0x00 26. " WDEL , Enable the delay counter at the end of the current transaction" "Disable,Enable"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL , Data word format select" "Format 0,Format 1,Format 2,Format 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR , Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA , Transfer data"
|
|
group.long 0x68++0x03
|
|
line.long 0x00 "TXRAM, Multi-buffer RAM Transmit Data Register 26"
|
|
bitfld.long 0x00 29.--31. " BUFMODE , Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip Single Transfer,Skip Overwrite,Skip ST-Overwrite,Continuous,Suspend Single Transfer,Suspend Overwrite,Suspend ST-Overwrite"
|
|
bitfld.long 0x00 28. " CSHOLD , Chip select hold mode" "Deactivated,Activated"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK , Lock two consecutive buffer words" "0,1"
|
|
bitfld.long 0x00 26. " WDEL , Enable the delay counter at the end of the current transaction" "Disable,Enable"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL , Data word format select" "Format 0,Format 1,Format 2,Format 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR , Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA , Transfer data"
|
|
group.long 0x6C++0x03
|
|
line.long 0x00 "TXRAM, Multi-buffer RAM Transmit Data Register 27"
|
|
bitfld.long 0x00 29.--31. " BUFMODE , Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip Single Transfer,Skip Overwrite,Skip ST-Overwrite,Continuous,Suspend Single Transfer,Suspend Overwrite,Suspend ST-Overwrite"
|
|
bitfld.long 0x00 28. " CSHOLD , Chip select hold mode" "Deactivated,Activated"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK , Lock two consecutive buffer words" "0,1"
|
|
bitfld.long 0x00 26. " WDEL , Enable the delay counter at the end of the current transaction" "Disable,Enable"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL , Data word format select" "Format 0,Format 1,Format 2,Format 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR , Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA , Transfer data"
|
|
group.long 0x70++0x03
|
|
line.long 0x00 "TXRAM, Multi-buffer RAM Transmit Data Register 28"
|
|
bitfld.long 0x00 29.--31. " BUFMODE , Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip Single Transfer,Skip Overwrite,Skip ST-Overwrite,Continuous,Suspend Single Transfer,Suspend Overwrite,Suspend ST-Overwrite"
|
|
bitfld.long 0x00 28. " CSHOLD , Chip select hold mode" "Deactivated,Activated"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK , Lock two consecutive buffer words" "0,1"
|
|
bitfld.long 0x00 26. " WDEL , Enable the delay counter at the end of the current transaction" "Disable,Enable"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL , Data word format select" "Format 0,Format 1,Format 2,Format 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR , Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA , Transfer data"
|
|
group.long 0x74++0x03
|
|
line.long 0x00 "TXRAM, Multi-buffer RAM Transmit Data Register 29"
|
|
bitfld.long 0x00 29.--31. " BUFMODE , Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip Single Transfer,Skip Overwrite,Skip ST-Overwrite,Continuous,Suspend Single Transfer,Suspend Overwrite,Suspend ST-Overwrite"
|
|
bitfld.long 0x00 28. " CSHOLD , Chip select hold mode" "Deactivated,Activated"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK , Lock two consecutive buffer words" "0,1"
|
|
bitfld.long 0x00 26. " WDEL , Enable the delay counter at the end of the current transaction" "Disable,Enable"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL , Data word format select" "Format 0,Format 1,Format 2,Format 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR , Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA , Transfer data"
|
|
group.long 0x78++0x03
|
|
line.long 0x00 "TXRAM, Multi-buffer RAM Transmit Data Register 30"
|
|
bitfld.long 0x00 29.--31. " BUFMODE , Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip Single Transfer,Skip Overwrite,Skip ST-Overwrite,Continuous,Suspend Single Transfer,Suspend Overwrite,Suspend ST-Overwrite"
|
|
bitfld.long 0x00 28. " CSHOLD , Chip select hold mode" "Deactivated,Activated"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK , Lock two consecutive buffer words" "0,1"
|
|
bitfld.long 0x00 26. " WDEL , Enable the delay counter at the end of the current transaction" "Disable,Enable"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL , Data word format select" "Format 0,Format 1,Format 2,Format 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR , Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA , Transfer data"
|
|
group.long 0x7C++0x03
|
|
line.long 0x00 "TXRAM, Multi-buffer RAM Transmit Data Register 31"
|
|
bitfld.long 0x00 29.--31. " BUFMODE , Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip Single Transfer,Skip Overwrite,Skip ST-Overwrite,Continuous,Suspend Single Transfer,Suspend Overwrite,Suspend ST-Overwrite"
|
|
bitfld.long 0x00 28. " CSHOLD , Chip select hold mode" "Deactivated,Activated"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK , Lock two consecutive buffer words" "0,1"
|
|
bitfld.long 0x00 26. " WDEL , Enable the delay counter at the end of the current transaction" "Disable,Enable"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL , Data word format select" "Format 0,Format 1,Format 2,Format 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR , Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA , Transfer data"
|
|
group.long 0x80++0x03
|
|
line.long 0x00 "TXRAM, Multi-buffer RAM Transmit Data Register 32"
|
|
bitfld.long 0x00 29.--31. " BUFMODE , Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip Single Transfer,Skip Overwrite,Skip ST-Overwrite,Continuous,Suspend Single Transfer,Suspend Overwrite,Suspend ST-Overwrite"
|
|
bitfld.long 0x00 28. " CSHOLD , Chip select hold mode" "Deactivated,Activated"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK , Lock two consecutive buffer words" "0,1"
|
|
bitfld.long 0x00 26. " WDEL , Enable the delay counter at the end of the current transaction" "Disable,Enable"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL , Data word format select" "Format 0,Format 1,Format 2,Format 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR , Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA , Transfer data"
|
|
group.long 0x84++0x03
|
|
line.long 0x00 "TXRAM, Multi-buffer RAM Transmit Data Register 33"
|
|
bitfld.long 0x00 29.--31. " BUFMODE , Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip Single Transfer,Skip Overwrite,Skip ST-Overwrite,Continuous,Suspend Single Transfer,Suspend Overwrite,Suspend ST-Overwrite"
|
|
bitfld.long 0x00 28. " CSHOLD , Chip select hold mode" "Deactivated,Activated"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK , Lock two consecutive buffer words" "0,1"
|
|
bitfld.long 0x00 26. " WDEL , Enable the delay counter at the end of the current transaction" "Disable,Enable"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL , Data word format select" "Format 0,Format 1,Format 2,Format 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR , Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA , Transfer data"
|
|
group.long 0x88++0x03
|
|
line.long 0x00 "TXRAM, Multi-buffer RAM Transmit Data Register 34"
|
|
bitfld.long 0x00 29.--31. " BUFMODE , Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip Single Transfer,Skip Overwrite,Skip ST-Overwrite,Continuous,Suspend Single Transfer,Suspend Overwrite,Suspend ST-Overwrite"
|
|
bitfld.long 0x00 28. " CSHOLD , Chip select hold mode" "Deactivated,Activated"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK , Lock two consecutive buffer words" "0,1"
|
|
bitfld.long 0x00 26. " WDEL , Enable the delay counter at the end of the current transaction" "Disable,Enable"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL , Data word format select" "Format 0,Format 1,Format 2,Format 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR , Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA , Transfer data"
|
|
group.long 0x8C++0x03
|
|
line.long 0x00 "TXRAM, Multi-buffer RAM Transmit Data Register 35"
|
|
bitfld.long 0x00 29.--31. " BUFMODE , Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip Single Transfer,Skip Overwrite,Skip ST-Overwrite,Continuous,Suspend Single Transfer,Suspend Overwrite,Suspend ST-Overwrite"
|
|
bitfld.long 0x00 28. " CSHOLD , Chip select hold mode" "Deactivated,Activated"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK , Lock two consecutive buffer words" "0,1"
|
|
bitfld.long 0x00 26. " WDEL , Enable the delay counter at the end of the current transaction" "Disable,Enable"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL , Data word format select" "Format 0,Format 1,Format 2,Format 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR , Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA , Transfer data"
|
|
group.long 0x90++0x03
|
|
line.long 0x00 "TXRAM, Multi-buffer RAM Transmit Data Register 36"
|
|
bitfld.long 0x00 29.--31. " BUFMODE , Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip Single Transfer,Skip Overwrite,Skip ST-Overwrite,Continuous,Suspend Single Transfer,Suspend Overwrite,Suspend ST-Overwrite"
|
|
bitfld.long 0x00 28. " CSHOLD , Chip select hold mode" "Deactivated,Activated"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK , Lock two consecutive buffer words" "0,1"
|
|
bitfld.long 0x00 26. " WDEL , Enable the delay counter at the end of the current transaction" "Disable,Enable"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL , Data word format select" "Format 0,Format 1,Format 2,Format 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR , Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA , Transfer data"
|
|
group.long 0x94++0x03
|
|
line.long 0x00 "TXRAM, Multi-buffer RAM Transmit Data Register 37"
|
|
bitfld.long 0x00 29.--31. " BUFMODE , Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip Single Transfer,Skip Overwrite,Skip ST-Overwrite,Continuous,Suspend Single Transfer,Suspend Overwrite,Suspend ST-Overwrite"
|
|
bitfld.long 0x00 28. " CSHOLD , Chip select hold mode" "Deactivated,Activated"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK , Lock two consecutive buffer words" "0,1"
|
|
bitfld.long 0x00 26. " WDEL , Enable the delay counter at the end of the current transaction" "Disable,Enable"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL , Data word format select" "Format 0,Format 1,Format 2,Format 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR , Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA , Transfer data"
|
|
group.long 0x98++0x03
|
|
line.long 0x00 "TXRAM, Multi-buffer RAM Transmit Data Register 38"
|
|
bitfld.long 0x00 29.--31. " BUFMODE , Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip Single Transfer,Skip Overwrite,Skip ST-Overwrite,Continuous,Suspend Single Transfer,Suspend Overwrite,Suspend ST-Overwrite"
|
|
bitfld.long 0x00 28. " CSHOLD , Chip select hold mode" "Deactivated,Activated"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK , Lock two consecutive buffer words" "0,1"
|
|
bitfld.long 0x00 26. " WDEL , Enable the delay counter at the end of the current transaction" "Disable,Enable"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL , Data word format select" "Format 0,Format 1,Format 2,Format 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR , Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA , Transfer data"
|
|
group.long 0x9C++0x03
|
|
line.long 0x00 "TXRAM, Multi-buffer RAM Transmit Data Register 39"
|
|
bitfld.long 0x00 29.--31. " BUFMODE , Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip Single Transfer,Skip Overwrite,Skip ST-Overwrite,Continuous,Suspend Single Transfer,Suspend Overwrite,Suspend ST-Overwrite"
|
|
bitfld.long 0x00 28. " CSHOLD , Chip select hold mode" "Deactivated,Activated"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK , Lock two consecutive buffer words" "0,1"
|
|
bitfld.long 0x00 26. " WDEL , Enable the delay counter at the end of the current transaction" "Disable,Enable"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL , Data word format select" "Format 0,Format 1,Format 2,Format 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR , Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA , Transfer data"
|
|
group.long 0xA0++0x03
|
|
line.long 0x00 "TXRAM, Multi-buffer RAM Transmit Data Register 40"
|
|
bitfld.long 0x00 29.--31. " BUFMODE , Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip Single Transfer,Skip Overwrite,Skip ST-Overwrite,Continuous,Suspend Single Transfer,Suspend Overwrite,Suspend ST-Overwrite"
|
|
bitfld.long 0x00 28. " CSHOLD , Chip select hold mode" "Deactivated,Activated"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK , Lock two consecutive buffer words" "0,1"
|
|
bitfld.long 0x00 26. " WDEL , Enable the delay counter at the end of the current transaction" "Disable,Enable"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL , Data word format select" "Format 0,Format 1,Format 2,Format 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR , Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA , Transfer data"
|
|
group.long 0xA4++0x03
|
|
line.long 0x00 "TXRAM, Multi-buffer RAM Transmit Data Register 41"
|
|
bitfld.long 0x00 29.--31. " BUFMODE , Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip Single Transfer,Skip Overwrite,Skip ST-Overwrite,Continuous,Suspend Single Transfer,Suspend Overwrite,Suspend ST-Overwrite"
|
|
bitfld.long 0x00 28. " CSHOLD , Chip select hold mode" "Deactivated,Activated"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK , Lock two consecutive buffer words" "0,1"
|
|
bitfld.long 0x00 26. " WDEL , Enable the delay counter at the end of the current transaction" "Disable,Enable"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL , Data word format select" "Format 0,Format 1,Format 2,Format 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR , Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA , Transfer data"
|
|
group.long 0xA8++0x03
|
|
line.long 0x00 "TXRAM, Multi-buffer RAM Transmit Data Register 42"
|
|
bitfld.long 0x00 29.--31. " BUFMODE , Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip Single Transfer,Skip Overwrite,Skip ST-Overwrite,Continuous,Suspend Single Transfer,Suspend Overwrite,Suspend ST-Overwrite"
|
|
bitfld.long 0x00 28. " CSHOLD , Chip select hold mode" "Deactivated,Activated"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK , Lock two consecutive buffer words" "0,1"
|
|
bitfld.long 0x00 26. " WDEL , Enable the delay counter at the end of the current transaction" "Disable,Enable"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL , Data word format select" "Format 0,Format 1,Format 2,Format 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR , Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA , Transfer data"
|
|
group.long 0xAC++0x03
|
|
line.long 0x00 "TXRAM, Multi-buffer RAM Transmit Data Register 43"
|
|
bitfld.long 0x00 29.--31. " BUFMODE , Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip Single Transfer,Skip Overwrite,Skip ST-Overwrite,Continuous,Suspend Single Transfer,Suspend Overwrite,Suspend ST-Overwrite"
|
|
bitfld.long 0x00 28. " CSHOLD , Chip select hold mode" "Deactivated,Activated"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK , Lock two consecutive buffer words" "0,1"
|
|
bitfld.long 0x00 26. " WDEL , Enable the delay counter at the end of the current transaction" "Disable,Enable"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL , Data word format select" "Format 0,Format 1,Format 2,Format 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR , Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA , Transfer data"
|
|
group.long 0xB0++0x03
|
|
line.long 0x00 "TXRAM, Multi-buffer RAM Transmit Data Register 44"
|
|
bitfld.long 0x00 29.--31. " BUFMODE , Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip Single Transfer,Skip Overwrite,Skip ST-Overwrite,Continuous,Suspend Single Transfer,Suspend Overwrite,Suspend ST-Overwrite"
|
|
bitfld.long 0x00 28. " CSHOLD , Chip select hold mode" "Deactivated,Activated"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK , Lock two consecutive buffer words" "0,1"
|
|
bitfld.long 0x00 26. " WDEL , Enable the delay counter at the end of the current transaction" "Disable,Enable"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL , Data word format select" "Format 0,Format 1,Format 2,Format 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR , Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA , Transfer data"
|
|
group.long 0xB4++0x03
|
|
line.long 0x00 "TXRAM, Multi-buffer RAM Transmit Data Register 45"
|
|
bitfld.long 0x00 29.--31. " BUFMODE , Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip Single Transfer,Skip Overwrite,Skip ST-Overwrite,Continuous,Suspend Single Transfer,Suspend Overwrite,Suspend ST-Overwrite"
|
|
bitfld.long 0x00 28. " CSHOLD , Chip select hold mode" "Deactivated,Activated"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK , Lock two consecutive buffer words" "0,1"
|
|
bitfld.long 0x00 26. " WDEL , Enable the delay counter at the end of the current transaction" "Disable,Enable"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL , Data word format select" "Format 0,Format 1,Format 2,Format 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR , Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA , Transfer data"
|
|
group.long 0xB8++0x03
|
|
line.long 0x00 "TXRAM, Multi-buffer RAM Transmit Data Register 46"
|
|
bitfld.long 0x00 29.--31. " BUFMODE , Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip Single Transfer,Skip Overwrite,Skip ST-Overwrite,Continuous,Suspend Single Transfer,Suspend Overwrite,Suspend ST-Overwrite"
|
|
bitfld.long 0x00 28. " CSHOLD , Chip select hold mode" "Deactivated,Activated"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK , Lock two consecutive buffer words" "0,1"
|
|
bitfld.long 0x00 26. " WDEL , Enable the delay counter at the end of the current transaction" "Disable,Enable"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL , Data word format select" "Format 0,Format 1,Format 2,Format 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR , Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA , Transfer data"
|
|
group.long 0xBC++0x03
|
|
line.long 0x00 "TXRAM, Multi-buffer RAM Transmit Data Register 47"
|
|
bitfld.long 0x00 29.--31. " BUFMODE , Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip Single Transfer,Skip Overwrite,Skip ST-Overwrite,Continuous,Suspend Single Transfer,Suspend Overwrite,Suspend ST-Overwrite"
|
|
bitfld.long 0x00 28. " CSHOLD , Chip select hold mode" "Deactivated,Activated"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK , Lock two consecutive buffer words" "0,1"
|
|
bitfld.long 0x00 26. " WDEL , Enable the delay counter at the end of the current transaction" "Disable,Enable"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL , Data word format select" "Format 0,Format 1,Format 2,Format 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR , Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA , Transfer data"
|
|
group.long 0xC0++0x03
|
|
line.long 0x00 "TXRAM, Multi-buffer RAM Transmit Data Register 48"
|
|
bitfld.long 0x00 29.--31. " BUFMODE , Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip Single Transfer,Skip Overwrite,Skip ST-Overwrite,Continuous,Suspend Single Transfer,Suspend Overwrite,Suspend ST-Overwrite"
|
|
bitfld.long 0x00 28. " CSHOLD , Chip select hold mode" "Deactivated,Activated"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK , Lock two consecutive buffer words" "0,1"
|
|
bitfld.long 0x00 26. " WDEL , Enable the delay counter at the end of the current transaction" "Disable,Enable"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL , Data word format select" "Format 0,Format 1,Format 2,Format 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR , Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA , Transfer data"
|
|
group.long 0xC4++0x03
|
|
line.long 0x00 "TXRAM, Multi-buffer RAM Transmit Data Register 49"
|
|
bitfld.long 0x00 29.--31. " BUFMODE , Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip Single Transfer,Skip Overwrite,Skip ST-Overwrite,Continuous,Suspend Single Transfer,Suspend Overwrite,Suspend ST-Overwrite"
|
|
bitfld.long 0x00 28. " CSHOLD , Chip select hold mode" "Deactivated,Activated"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK , Lock two consecutive buffer words" "0,1"
|
|
bitfld.long 0x00 26. " WDEL , Enable the delay counter at the end of the current transaction" "Disable,Enable"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL , Data word format select" "Format 0,Format 1,Format 2,Format 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR , Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA , Transfer data"
|
|
group.long 0xC8++0x03
|
|
line.long 0x00 "TXRAM, Multi-buffer RAM Transmit Data Register 50"
|
|
bitfld.long 0x00 29.--31. " BUFMODE , Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip Single Transfer,Skip Overwrite,Skip ST-Overwrite,Continuous,Suspend Single Transfer,Suspend Overwrite,Suspend ST-Overwrite"
|
|
bitfld.long 0x00 28. " CSHOLD , Chip select hold mode" "Deactivated,Activated"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK , Lock two consecutive buffer words" "0,1"
|
|
bitfld.long 0x00 26. " WDEL , Enable the delay counter at the end of the current transaction" "Disable,Enable"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL , Data word format select" "Format 0,Format 1,Format 2,Format 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR , Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA , Transfer data"
|
|
group.long 0xCC++0x03
|
|
line.long 0x00 "TXRAM, Multi-buffer RAM Transmit Data Register 51"
|
|
bitfld.long 0x00 29.--31. " BUFMODE , Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip Single Transfer,Skip Overwrite,Skip ST-Overwrite,Continuous,Suspend Single Transfer,Suspend Overwrite,Suspend ST-Overwrite"
|
|
bitfld.long 0x00 28. " CSHOLD , Chip select hold mode" "Deactivated,Activated"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK , Lock two consecutive buffer words" "0,1"
|
|
bitfld.long 0x00 26. " WDEL , Enable the delay counter at the end of the current transaction" "Disable,Enable"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL , Data word format select" "Format 0,Format 1,Format 2,Format 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR , Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA , Transfer data"
|
|
group.long 0xD0++0x03
|
|
line.long 0x00 "TXRAM, Multi-buffer RAM Transmit Data Register 52"
|
|
bitfld.long 0x00 29.--31. " BUFMODE , Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip Single Transfer,Skip Overwrite,Skip ST-Overwrite,Continuous,Suspend Single Transfer,Suspend Overwrite,Suspend ST-Overwrite"
|
|
bitfld.long 0x00 28. " CSHOLD , Chip select hold mode" "Deactivated,Activated"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK , Lock two consecutive buffer words" "0,1"
|
|
bitfld.long 0x00 26. " WDEL , Enable the delay counter at the end of the current transaction" "Disable,Enable"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL , Data word format select" "Format 0,Format 1,Format 2,Format 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR , Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA , Transfer data"
|
|
group.long 0xD4++0x03
|
|
line.long 0x00 "TXRAM, Multi-buffer RAM Transmit Data Register 53"
|
|
bitfld.long 0x00 29.--31. " BUFMODE , Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip Single Transfer,Skip Overwrite,Skip ST-Overwrite,Continuous,Suspend Single Transfer,Suspend Overwrite,Suspend ST-Overwrite"
|
|
bitfld.long 0x00 28. " CSHOLD , Chip select hold mode" "Deactivated,Activated"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK , Lock two consecutive buffer words" "0,1"
|
|
bitfld.long 0x00 26. " WDEL , Enable the delay counter at the end of the current transaction" "Disable,Enable"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL , Data word format select" "Format 0,Format 1,Format 2,Format 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR , Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA , Transfer data"
|
|
group.long 0xD8++0x03
|
|
line.long 0x00 "TXRAM, Multi-buffer RAM Transmit Data Register 54"
|
|
bitfld.long 0x00 29.--31. " BUFMODE , Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip Single Transfer,Skip Overwrite,Skip ST-Overwrite,Continuous,Suspend Single Transfer,Suspend Overwrite,Suspend ST-Overwrite"
|
|
bitfld.long 0x00 28. " CSHOLD , Chip select hold mode" "Deactivated,Activated"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK , Lock two consecutive buffer words" "0,1"
|
|
bitfld.long 0x00 26. " WDEL , Enable the delay counter at the end of the current transaction" "Disable,Enable"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL , Data word format select" "Format 0,Format 1,Format 2,Format 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR , Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA , Transfer data"
|
|
group.long 0xDC++0x03
|
|
line.long 0x00 "TXRAM, Multi-buffer RAM Transmit Data Register 55"
|
|
bitfld.long 0x00 29.--31. " BUFMODE , Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip Single Transfer,Skip Overwrite,Skip ST-Overwrite,Continuous,Suspend Single Transfer,Suspend Overwrite,Suspend ST-Overwrite"
|
|
bitfld.long 0x00 28. " CSHOLD , Chip select hold mode" "Deactivated,Activated"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK , Lock two consecutive buffer words" "0,1"
|
|
bitfld.long 0x00 26. " WDEL , Enable the delay counter at the end of the current transaction" "Disable,Enable"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL , Data word format select" "Format 0,Format 1,Format 2,Format 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR , Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA , Transfer data"
|
|
group.long 0xE0++0x03
|
|
line.long 0x00 "TXRAM, Multi-buffer RAM Transmit Data Register 56"
|
|
bitfld.long 0x00 29.--31. " BUFMODE , Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip Single Transfer,Skip Overwrite,Skip ST-Overwrite,Continuous,Suspend Single Transfer,Suspend Overwrite,Suspend ST-Overwrite"
|
|
bitfld.long 0x00 28. " CSHOLD , Chip select hold mode" "Deactivated,Activated"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK , Lock two consecutive buffer words" "0,1"
|
|
bitfld.long 0x00 26. " WDEL , Enable the delay counter at the end of the current transaction" "Disable,Enable"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL , Data word format select" "Format 0,Format 1,Format 2,Format 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR , Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA , Transfer data"
|
|
group.long 0xE4++0x03
|
|
line.long 0x00 "TXRAM, Multi-buffer RAM Transmit Data Register 57"
|
|
bitfld.long 0x00 29.--31. " BUFMODE , Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip Single Transfer,Skip Overwrite,Skip ST-Overwrite,Continuous,Suspend Single Transfer,Suspend Overwrite,Suspend ST-Overwrite"
|
|
bitfld.long 0x00 28. " CSHOLD , Chip select hold mode" "Deactivated,Activated"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK , Lock two consecutive buffer words" "0,1"
|
|
bitfld.long 0x00 26. " WDEL , Enable the delay counter at the end of the current transaction" "Disable,Enable"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL , Data word format select" "Format 0,Format 1,Format 2,Format 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR , Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA , Transfer data"
|
|
group.long 0xE8++0x03
|
|
line.long 0x00 "TXRAM, Multi-buffer RAM Transmit Data Register 58"
|
|
bitfld.long 0x00 29.--31. " BUFMODE , Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip Single Transfer,Skip Overwrite,Skip ST-Overwrite,Continuous,Suspend Single Transfer,Suspend Overwrite,Suspend ST-Overwrite"
|
|
bitfld.long 0x00 28. " CSHOLD , Chip select hold mode" "Deactivated,Activated"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK , Lock two consecutive buffer words" "0,1"
|
|
bitfld.long 0x00 26. " WDEL , Enable the delay counter at the end of the current transaction" "Disable,Enable"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL , Data word format select" "Format 0,Format 1,Format 2,Format 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR , Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA , Transfer data"
|
|
group.long 0xEC++0x03
|
|
line.long 0x00 "TXRAM, Multi-buffer RAM Transmit Data Register 59"
|
|
bitfld.long 0x00 29.--31. " BUFMODE , Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip Single Transfer,Skip Overwrite,Skip ST-Overwrite,Continuous,Suspend Single Transfer,Suspend Overwrite,Suspend ST-Overwrite"
|
|
bitfld.long 0x00 28. " CSHOLD , Chip select hold mode" "Deactivated,Activated"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK , Lock two consecutive buffer words" "0,1"
|
|
bitfld.long 0x00 26. " WDEL , Enable the delay counter at the end of the current transaction" "Disable,Enable"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL , Data word format select" "Format 0,Format 1,Format 2,Format 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR , Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA , Transfer data"
|
|
group.long 0xF0++0x03
|
|
line.long 0x00 "TXRAM, Multi-buffer RAM Transmit Data Register 60"
|
|
bitfld.long 0x00 29.--31. " BUFMODE , Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip Single Transfer,Skip Overwrite,Skip ST-Overwrite,Continuous,Suspend Single Transfer,Suspend Overwrite,Suspend ST-Overwrite"
|
|
bitfld.long 0x00 28. " CSHOLD , Chip select hold mode" "Deactivated,Activated"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK , Lock two consecutive buffer words" "0,1"
|
|
bitfld.long 0x00 26. " WDEL , Enable the delay counter at the end of the current transaction" "Disable,Enable"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL , Data word format select" "Format 0,Format 1,Format 2,Format 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR , Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA , Transfer data"
|
|
group.long 0xF4++0x03
|
|
line.long 0x00 "TXRAM, Multi-buffer RAM Transmit Data Register 61"
|
|
bitfld.long 0x00 29.--31. " BUFMODE , Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip Single Transfer,Skip Overwrite,Skip ST-Overwrite,Continuous,Suspend Single Transfer,Suspend Overwrite,Suspend ST-Overwrite"
|
|
bitfld.long 0x00 28. " CSHOLD , Chip select hold mode" "Deactivated,Activated"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK , Lock two consecutive buffer words" "0,1"
|
|
bitfld.long 0x00 26. " WDEL , Enable the delay counter at the end of the current transaction" "Disable,Enable"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL , Data word format select" "Format 0,Format 1,Format 2,Format 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR , Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA , Transfer data"
|
|
group.long 0xF8++0x03
|
|
line.long 0x00 "TXRAM, Multi-buffer RAM Transmit Data Register 62"
|
|
bitfld.long 0x00 29.--31. " BUFMODE , Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip Single Transfer,Skip Overwrite,Skip ST-Overwrite,Continuous,Suspend Single Transfer,Suspend Overwrite,Suspend ST-Overwrite"
|
|
bitfld.long 0x00 28. " CSHOLD , Chip select hold mode" "Deactivated,Activated"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK , Lock two consecutive buffer words" "0,1"
|
|
bitfld.long 0x00 26. " WDEL , Enable the delay counter at the end of the current transaction" "Disable,Enable"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL , Data word format select" "Format 0,Format 1,Format 2,Format 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR , Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA , Transfer data"
|
|
group.long 0xFC++0x03
|
|
line.long 0x00 "TXRAM, Multi-buffer RAM Transmit Data Register 63"
|
|
bitfld.long 0x00 29.--31. " BUFMODE , Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip Single Transfer,Skip Overwrite,Skip ST-Overwrite,Continuous,Suspend Single Transfer,Suspend Overwrite,Suspend ST-Overwrite"
|
|
bitfld.long 0x00 28. " CSHOLD , Chip select hold mode" "Deactivated,Activated"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK , Lock two consecutive buffer words" "0,1"
|
|
bitfld.long 0x00 26. " WDEL , Enable the delay counter at the end of the current transaction" "Disable,Enable"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL , Data word format select" "Format 0,Format 1,Format 2,Format 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR , Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA , Transfer data"
|
|
group.long 0x100++0x03
|
|
line.long 0x00 "TXRAM, Multi-buffer RAM Transmit Data Register 64"
|
|
bitfld.long 0x00 29.--31. " BUFMODE , Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip Single Transfer,Skip Overwrite,Skip ST-Overwrite,Continuous,Suspend Single Transfer,Suspend Overwrite,Suspend ST-Overwrite"
|
|
bitfld.long 0x00 28. " CSHOLD , Chip select hold mode" "Deactivated,Activated"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK , Lock two consecutive buffer words" "0,1"
|
|
bitfld.long 0x00 26. " WDEL , Enable the delay counter at the end of the current transaction" "Disable,Enable"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL , Data word format select" "Format 0,Format 1,Format 2,Format 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR , Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA , Transfer data"
|
|
group.long 0x104++0x03
|
|
line.long 0x00 "TXRAM, Multi-buffer RAM Transmit Data Register 65"
|
|
bitfld.long 0x00 29.--31. " BUFMODE , Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip Single Transfer,Skip Overwrite,Skip ST-Overwrite,Continuous,Suspend Single Transfer,Suspend Overwrite,Suspend ST-Overwrite"
|
|
bitfld.long 0x00 28. " CSHOLD , Chip select hold mode" "Deactivated,Activated"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK , Lock two consecutive buffer words" "0,1"
|
|
bitfld.long 0x00 26. " WDEL , Enable the delay counter at the end of the current transaction" "Disable,Enable"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL , Data word format select" "Format 0,Format 1,Format 2,Format 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR , Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA , Transfer data"
|
|
group.long 0x108++0x03
|
|
line.long 0x00 "TXRAM, Multi-buffer RAM Transmit Data Register 66"
|
|
bitfld.long 0x00 29.--31. " BUFMODE , Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip Single Transfer,Skip Overwrite,Skip ST-Overwrite,Continuous,Suspend Single Transfer,Suspend Overwrite,Suspend ST-Overwrite"
|
|
bitfld.long 0x00 28. " CSHOLD , Chip select hold mode" "Deactivated,Activated"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK , Lock two consecutive buffer words" "0,1"
|
|
bitfld.long 0x00 26. " WDEL , Enable the delay counter at the end of the current transaction" "Disable,Enable"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL , Data word format select" "Format 0,Format 1,Format 2,Format 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR , Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA , Transfer data"
|
|
group.long 0x10C++0x03
|
|
line.long 0x00 "TXRAM, Multi-buffer RAM Transmit Data Register 67"
|
|
bitfld.long 0x00 29.--31. " BUFMODE , Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip Single Transfer,Skip Overwrite,Skip ST-Overwrite,Continuous,Suspend Single Transfer,Suspend Overwrite,Suspend ST-Overwrite"
|
|
bitfld.long 0x00 28. " CSHOLD , Chip select hold mode" "Deactivated,Activated"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK , Lock two consecutive buffer words" "0,1"
|
|
bitfld.long 0x00 26. " WDEL , Enable the delay counter at the end of the current transaction" "Disable,Enable"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL , Data word format select" "Format 0,Format 1,Format 2,Format 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR , Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA , Transfer data"
|
|
group.long 0x110++0x03
|
|
line.long 0x00 "TXRAM, Multi-buffer RAM Transmit Data Register 68"
|
|
bitfld.long 0x00 29.--31. " BUFMODE , Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip Single Transfer,Skip Overwrite,Skip ST-Overwrite,Continuous,Suspend Single Transfer,Suspend Overwrite,Suspend ST-Overwrite"
|
|
bitfld.long 0x00 28. " CSHOLD , Chip select hold mode" "Deactivated,Activated"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK , Lock two consecutive buffer words" "0,1"
|
|
bitfld.long 0x00 26. " WDEL , Enable the delay counter at the end of the current transaction" "Disable,Enable"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL , Data word format select" "Format 0,Format 1,Format 2,Format 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR , Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA , Transfer data"
|
|
group.long 0x114++0x03
|
|
line.long 0x00 "TXRAM, Multi-buffer RAM Transmit Data Register 69"
|
|
bitfld.long 0x00 29.--31. " BUFMODE , Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip Single Transfer,Skip Overwrite,Skip ST-Overwrite,Continuous,Suspend Single Transfer,Suspend Overwrite,Suspend ST-Overwrite"
|
|
bitfld.long 0x00 28. " CSHOLD , Chip select hold mode" "Deactivated,Activated"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK , Lock two consecutive buffer words" "0,1"
|
|
bitfld.long 0x00 26. " WDEL , Enable the delay counter at the end of the current transaction" "Disable,Enable"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL , Data word format select" "Format 0,Format 1,Format 2,Format 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR , Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA , Transfer data"
|
|
group.long 0x118++0x03
|
|
line.long 0x00 "TXRAM, Multi-buffer RAM Transmit Data Register 70"
|
|
bitfld.long 0x00 29.--31. " BUFMODE , Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip Single Transfer,Skip Overwrite,Skip ST-Overwrite,Continuous,Suspend Single Transfer,Suspend Overwrite,Suspend ST-Overwrite"
|
|
bitfld.long 0x00 28. " CSHOLD , Chip select hold mode" "Deactivated,Activated"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK , Lock two consecutive buffer words" "0,1"
|
|
bitfld.long 0x00 26. " WDEL , Enable the delay counter at the end of the current transaction" "Disable,Enable"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL , Data word format select" "Format 0,Format 1,Format 2,Format 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR , Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA , Transfer data"
|
|
group.long 0x11C++0x03
|
|
line.long 0x00 "TXRAM, Multi-buffer RAM Transmit Data Register 71"
|
|
bitfld.long 0x00 29.--31. " BUFMODE , Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip Single Transfer,Skip Overwrite,Skip ST-Overwrite,Continuous,Suspend Single Transfer,Suspend Overwrite,Suspend ST-Overwrite"
|
|
bitfld.long 0x00 28. " CSHOLD , Chip select hold mode" "Deactivated,Activated"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK , Lock two consecutive buffer words" "0,1"
|
|
bitfld.long 0x00 26. " WDEL , Enable the delay counter at the end of the current transaction" "Disable,Enable"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL , Data word format select" "Format 0,Format 1,Format 2,Format 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR , Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA , Transfer data"
|
|
group.long 0x120++0x03
|
|
line.long 0x00 "TXRAM, Multi-buffer RAM Transmit Data Register 72"
|
|
bitfld.long 0x00 29.--31. " BUFMODE , Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip Single Transfer,Skip Overwrite,Skip ST-Overwrite,Continuous,Suspend Single Transfer,Suspend Overwrite,Suspend ST-Overwrite"
|
|
bitfld.long 0x00 28. " CSHOLD , Chip select hold mode" "Deactivated,Activated"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK , Lock two consecutive buffer words" "0,1"
|
|
bitfld.long 0x00 26. " WDEL , Enable the delay counter at the end of the current transaction" "Disable,Enable"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL , Data word format select" "Format 0,Format 1,Format 2,Format 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR , Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA , Transfer data"
|
|
group.long 0x124++0x03
|
|
line.long 0x00 "TXRAM, Multi-buffer RAM Transmit Data Register 73"
|
|
bitfld.long 0x00 29.--31. " BUFMODE , Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip Single Transfer,Skip Overwrite,Skip ST-Overwrite,Continuous,Suspend Single Transfer,Suspend Overwrite,Suspend ST-Overwrite"
|
|
bitfld.long 0x00 28. " CSHOLD , Chip select hold mode" "Deactivated,Activated"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK , Lock two consecutive buffer words" "0,1"
|
|
bitfld.long 0x00 26. " WDEL , Enable the delay counter at the end of the current transaction" "Disable,Enable"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL , Data word format select" "Format 0,Format 1,Format 2,Format 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR , Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA , Transfer data"
|
|
group.long 0x128++0x03
|
|
line.long 0x00 "TXRAM, Multi-buffer RAM Transmit Data Register 74"
|
|
bitfld.long 0x00 29.--31. " BUFMODE , Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip Single Transfer,Skip Overwrite,Skip ST-Overwrite,Continuous,Suspend Single Transfer,Suspend Overwrite,Suspend ST-Overwrite"
|
|
bitfld.long 0x00 28. " CSHOLD , Chip select hold mode" "Deactivated,Activated"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK , Lock two consecutive buffer words" "0,1"
|
|
bitfld.long 0x00 26. " WDEL , Enable the delay counter at the end of the current transaction" "Disable,Enable"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL , Data word format select" "Format 0,Format 1,Format 2,Format 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR , Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA , Transfer data"
|
|
group.long 0x12C++0x03
|
|
line.long 0x00 "TXRAM, Multi-buffer RAM Transmit Data Register 75"
|
|
bitfld.long 0x00 29.--31. " BUFMODE , Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip Single Transfer,Skip Overwrite,Skip ST-Overwrite,Continuous,Suspend Single Transfer,Suspend Overwrite,Suspend ST-Overwrite"
|
|
bitfld.long 0x00 28. " CSHOLD , Chip select hold mode" "Deactivated,Activated"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK , Lock two consecutive buffer words" "0,1"
|
|
bitfld.long 0x00 26. " WDEL , Enable the delay counter at the end of the current transaction" "Disable,Enable"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL , Data word format select" "Format 0,Format 1,Format 2,Format 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR , Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA , Transfer data"
|
|
group.long 0x130++0x03
|
|
line.long 0x00 "TXRAM, Multi-buffer RAM Transmit Data Register 76"
|
|
bitfld.long 0x00 29.--31. " BUFMODE , Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip Single Transfer,Skip Overwrite,Skip ST-Overwrite,Continuous,Suspend Single Transfer,Suspend Overwrite,Suspend ST-Overwrite"
|
|
bitfld.long 0x00 28. " CSHOLD , Chip select hold mode" "Deactivated,Activated"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK , Lock two consecutive buffer words" "0,1"
|
|
bitfld.long 0x00 26. " WDEL , Enable the delay counter at the end of the current transaction" "Disable,Enable"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL , Data word format select" "Format 0,Format 1,Format 2,Format 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR , Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA , Transfer data"
|
|
group.long 0x134++0x03
|
|
line.long 0x00 "TXRAM, Multi-buffer RAM Transmit Data Register 77"
|
|
bitfld.long 0x00 29.--31. " BUFMODE , Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip Single Transfer,Skip Overwrite,Skip ST-Overwrite,Continuous,Suspend Single Transfer,Suspend Overwrite,Suspend ST-Overwrite"
|
|
bitfld.long 0x00 28. " CSHOLD , Chip select hold mode" "Deactivated,Activated"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK , Lock two consecutive buffer words" "0,1"
|
|
bitfld.long 0x00 26. " WDEL , Enable the delay counter at the end of the current transaction" "Disable,Enable"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL , Data word format select" "Format 0,Format 1,Format 2,Format 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR , Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA , Transfer data"
|
|
group.long 0x138++0x03
|
|
line.long 0x00 "TXRAM, Multi-buffer RAM Transmit Data Register 78"
|
|
bitfld.long 0x00 29.--31. " BUFMODE , Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip Single Transfer,Skip Overwrite,Skip ST-Overwrite,Continuous,Suspend Single Transfer,Suspend Overwrite,Suspend ST-Overwrite"
|
|
bitfld.long 0x00 28. " CSHOLD , Chip select hold mode" "Deactivated,Activated"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK , Lock two consecutive buffer words" "0,1"
|
|
bitfld.long 0x00 26. " WDEL , Enable the delay counter at the end of the current transaction" "Disable,Enable"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL , Data word format select" "Format 0,Format 1,Format 2,Format 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR , Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA , Transfer data"
|
|
group.long 0x13C++0x03
|
|
line.long 0x00 "TXRAM, Multi-buffer RAM Transmit Data Register 79"
|
|
bitfld.long 0x00 29.--31. " BUFMODE , Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip Single Transfer,Skip Overwrite,Skip ST-Overwrite,Continuous,Suspend Single Transfer,Suspend Overwrite,Suspend ST-Overwrite"
|
|
bitfld.long 0x00 28. " CSHOLD , Chip select hold mode" "Deactivated,Activated"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK , Lock two consecutive buffer words" "0,1"
|
|
bitfld.long 0x00 26. " WDEL , Enable the delay counter at the end of the current transaction" "Disable,Enable"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL , Data word format select" "Format 0,Format 1,Format 2,Format 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR , Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA , Transfer data"
|
|
rgroup.long (0x0+0x200)++0x03
|
|
line.long 0x00 "RXRAM, Multi-buffer RAM Receive Buffer Register 0"
|
|
bitfld.long 0x00 31. " RXEMPTY , Receive data buffer empty" "Not empty,Empty"
|
|
bitfld.long 0x00 30. " RXOVR , Receive data buffer overrun" "No overrun,Overrun"
|
|
newline
|
|
bitfld.long 0x00 29. " TXFULL , Transmit data buffer full" "Not full,Full"
|
|
bitfld.long 0x00 28. " BITERR , Bit error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 27. " DESYNC , Desynchronization of slave device" "No,Yes"
|
|
bitfld.long 0x00 26. " PARITYERR , Parity error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 25. " TIMEOUT , Time-out because of non-activation of ENA pin" "No timeout,Timeout"
|
|
bitfld.long 0x00 24. " DLENERR , Data length error flag" "No,Yes"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " LCSNR , Last chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " RXDATA , SPI receive data"
|
|
rgroup.long (0x4+0x200)++0x03
|
|
line.long 0x00 "RXRAM, Multi-buffer RAM Receive Buffer Register 1"
|
|
bitfld.long 0x00 31. " RXEMPTY , Receive data buffer empty" "Not empty,Empty"
|
|
bitfld.long 0x00 30. " RXOVR , Receive data buffer overrun" "No overrun,Overrun"
|
|
newline
|
|
bitfld.long 0x00 29. " TXFULL , Transmit data buffer full" "Not full,Full"
|
|
bitfld.long 0x00 28. " BITERR , Bit error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 27. " DESYNC , Desynchronization of slave device" "No,Yes"
|
|
bitfld.long 0x00 26. " PARITYERR , Parity error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 25. " TIMEOUT , Time-out because of non-activation of ENA pin" "No timeout,Timeout"
|
|
bitfld.long 0x00 24. " DLENERR , Data length error flag" "No,Yes"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " LCSNR , Last chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " RXDATA , SPI receive data"
|
|
rgroup.long (0x8+0x200)++0x03
|
|
line.long 0x00 "RXRAM, Multi-buffer RAM Receive Buffer Register 2"
|
|
bitfld.long 0x00 31. " RXEMPTY , Receive data buffer empty" "Not empty,Empty"
|
|
bitfld.long 0x00 30. " RXOVR , Receive data buffer overrun" "No overrun,Overrun"
|
|
newline
|
|
bitfld.long 0x00 29. " TXFULL , Transmit data buffer full" "Not full,Full"
|
|
bitfld.long 0x00 28. " BITERR , Bit error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 27. " DESYNC , Desynchronization of slave device" "No,Yes"
|
|
bitfld.long 0x00 26. " PARITYERR , Parity error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 25. " TIMEOUT , Time-out because of non-activation of ENA pin" "No timeout,Timeout"
|
|
bitfld.long 0x00 24. " DLENERR , Data length error flag" "No,Yes"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " LCSNR , Last chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " RXDATA , SPI receive data"
|
|
rgroup.long (0xC+0x200)++0x03
|
|
line.long 0x00 "RXRAM, Multi-buffer RAM Receive Buffer Register 3"
|
|
bitfld.long 0x00 31. " RXEMPTY , Receive data buffer empty" "Not empty,Empty"
|
|
bitfld.long 0x00 30. " RXOVR , Receive data buffer overrun" "No overrun,Overrun"
|
|
newline
|
|
bitfld.long 0x00 29. " TXFULL , Transmit data buffer full" "Not full,Full"
|
|
bitfld.long 0x00 28. " BITERR , Bit error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 27. " DESYNC , Desynchronization of slave device" "No,Yes"
|
|
bitfld.long 0x00 26. " PARITYERR , Parity error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 25. " TIMEOUT , Time-out because of non-activation of ENA pin" "No timeout,Timeout"
|
|
bitfld.long 0x00 24. " DLENERR , Data length error flag" "No,Yes"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " LCSNR , Last chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " RXDATA , SPI receive data"
|
|
rgroup.long (0x10+0x200)++0x03
|
|
line.long 0x00 "RXRAM, Multi-buffer RAM Receive Buffer Register 4"
|
|
bitfld.long 0x00 31. " RXEMPTY , Receive data buffer empty" "Not empty,Empty"
|
|
bitfld.long 0x00 30. " RXOVR , Receive data buffer overrun" "No overrun,Overrun"
|
|
newline
|
|
bitfld.long 0x00 29. " TXFULL , Transmit data buffer full" "Not full,Full"
|
|
bitfld.long 0x00 28. " BITERR , Bit error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 27. " DESYNC , Desynchronization of slave device" "No,Yes"
|
|
bitfld.long 0x00 26. " PARITYERR , Parity error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 25. " TIMEOUT , Time-out because of non-activation of ENA pin" "No timeout,Timeout"
|
|
bitfld.long 0x00 24. " DLENERR , Data length error flag" "No,Yes"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " LCSNR , Last chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " RXDATA , SPI receive data"
|
|
rgroup.long (0x14+0x200)++0x03
|
|
line.long 0x00 "RXRAM, Multi-buffer RAM Receive Buffer Register 5"
|
|
bitfld.long 0x00 31. " RXEMPTY , Receive data buffer empty" "Not empty,Empty"
|
|
bitfld.long 0x00 30. " RXOVR , Receive data buffer overrun" "No overrun,Overrun"
|
|
newline
|
|
bitfld.long 0x00 29. " TXFULL , Transmit data buffer full" "Not full,Full"
|
|
bitfld.long 0x00 28. " BITERR , Bit error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 27. " DESYNC , Desynchronization of slave device" "No,Yes"
|
|
bitfld.long 0x00 26. " PARITYERR , Parity error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 25. " TIMEOUT , Time-out because of non-activation of ENA pin" "No timeout,Timeout"
|
|
bitfld.long 0x00 24. " DLENERR , Data length error flag" "No,Yes"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " LCSNR , Last chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " RXDATA , SPI receive data"
|
|
rgroup.long (0x18+0x200)++0x03
|
|
line.long 0x00 "RXRAM, Multi-buffer RAM Receive Buffer Register 6"
|
|
bitfld.long 0x00 31. " RXEMPTY , Receive data buffer empty" "Not empty,Empty"
|
|
bitfld.long 0x00 30. " RXOVR , Receive data buffer overrun" "No overrun,Overrun"
|
|
newline
|
|
bitfld.long 0x00 29. " TXFULL , Transmit data buffer full" "Not full,Full"
|
|
bitfld.long 0x00 28. " BITERR , Bit error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 27. " DESYNC , Desynchronization of slave device" "No,Yes"
|
|
bitfld.long 0x00 26. " PARITYERR , Parity error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 25. " TIMEOUT , Time-out because of non-activation of ENA pin" "No timeout,Timeout"
|
|
bitfld.long 0x00 24. " DLENERR , Data length error flag" "No,Yes"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " LCSNR , Last chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " RXDATA , SPI receive data"
|
|
rgroup.long (0x1C+0x200)++0x03
|
|
line.long 0x00 "RXRAM, Multi-buffer RAM Receive Buffer Register 7"
|
|
bitfld.long 0x00 31. " RXEMPTY , Receive data buffer empty" "Not empty,Empty"
|
|
bitfld.long 0x00 30. " RXOVR , Receive data buffer overrun" "No overrun,Overrun"
|
|
newline
|
|
bitfld.long 0x00 29. " TXFULL , Transmit data buffer full" "Not full,Full"
|
|
bitfld.long 0x00 28. " BITERR , Bit error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 27. " DESYNC , Desynchronization of slave device" "No,Yes"
|
|
bitfld.long 0x00 26. " PARITYERR , Parity error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 25. " TIMEOUT , Time-out because of non-activation of ENA pin" "No timeout,Timeout"
|
|
bitfld.long 0x00 24. " DLENERR , Data length error flag" "No,Yes"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " LCSNR , Last chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " RXDATA , SPI receive data"
|
|
rgroup.long (0x20+0x200)++0x03
|
|
line.long 0x00 "RXRAM, Multi-buffer RAM Receive Buffer Register 8"
|
|
bitfld.long 0x00 31. " RXEMPTY , Receive data buffer empty" "Not empty,Empty"
|
|
bitfld.long 0x00 30. " RXOVR , Receive data buffer overrun" "No overrun,Overrun"
|
|
newline
|
|
bitfld.long 0x00 29. " TXFULL , Transmit data buffer full" "Not full,Full"
|
|
bitfld.long 0x00 28. " BITERR , Bit error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 27. " DESYNC , Desynchronization of slave device" "No,Yes"
|
|
bitfld.long 0x00 26. " PARITYERR , Parity error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 25. " TIMEOUT , Time-out because of non-activation of ENA pin" "No timeout,Timeout"
|
|
bitfld.long 0x00 24. " DLENERR , Data length error flag" "No,Yes"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " LCSNR , Last chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " RXDATA , SPI receive data"
|
|
rgroup.long (0x24+0x200)++0x03
|
|
line.long 0x00 "RXRAM, Multi-buffer RAM Receive Buffer Register 9"
|
|
bitfld.long 0x00 31. " RXEMPTY , Receive data buffer empty" "Not empty,Empty"
|
|
bitfld.long 0x00 30. " RXOVR , Receive data buffer overrun" "No overrun,Overrun"
|
|
newline
|
|
bitfld.long 0x00 29. " TXFULL , Transmit data buffer full" "Not full,Full"
|
|
bitfld.long 0x00 28. " BITERR , Bit error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 27. " DESYNC , Desynchronization of slave device" "No,Yes"
|
|
bitfld.long 0x00 26. " PARITYERR , Parity error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 25. " TIMEOUT , Time-out because of non-activation of ENA pin" "No timeout,Timeout"
|
|
bitfld.long 0x00 24. " DLENERR , Data length error flag" "No,Yes"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " LCSNR , Last chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " RXDATA , SPI receive data"
|
|
rgroup.long (0x28+0x200)++0x03
|
|
line.long 0x00 "RXRAM, Multi-buffer RAM Receive Buffer Register 10"
|
|
bitfld.long 0x00 31. " RXEMPTY , Receive data buffer empty" "Not empty,Empty"
|
|
bitfld.long 0x00 30. " RXOVR , Receive data buffer overrun" "No overrun,Overrun"
|
|
newline
|
|
bitfld.long 0x00 29. " TXFULL , Transmit data buffer full" "Not full,Full"
|
|
bitfld.long 0x00 28. " BITERR , Bit error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 27. " DESYNC , Desynchronization of slave device" "No,Yes"
|
|
bitfld.long 0x00 26. " PARITYERR , Parity error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 25. " TIMEOUT , Time-out because of non-activation of ENA pin" "No timeout,Timeout"
|
|
bitfld.long 0x00 24. " DLENERR , Data length error flag" "No,Yes"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " LCSNR , Last chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " RXDATA , SPI receive data"
|
|
rgroup.long (0x2C+0x200)++0x03
|
|
line.long 0x00 "RXRAM, Multi-buffer RAM Receive Buffer Register 11"
|
|
bitfld.long 0x00 31. " RXEMPTY , Receive data buffer empty" "Not empty,Empty"
|
|
bitfld.long 0x00 30. " RXOVR , Receive data buffer overrun" "No overrun,Overrun"
|
|
newline
|
|
bitfld.long 0x00 29. " TXFULL , Transmit data buffer full" "Not full,Full"
|
|
bitfld.long 0x00 28. " BITERR , Bit error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 27. " DESYNC , Desynchronization of slave device" "No,Yes"
|
|
bitfld.long 0x00 26. " PARITYERR , Parity error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 25. " TIMEOUT , Time-out because of non-activation of ENA pin" "No timeout,Timeout"
|
|
bitfld.long 0x00 24. " DLENERR , Data length error flag" "No,Yes"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " LCSNR , Last chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " RXDATA , SPI receive data"
|
|
rgroup.long (0x30+0x200)++0x03
|
|
line.long 0x00 "RXRAM, Multi-buffer RAM Receive Buffer Register 12"
|
|
bitfld.long 0x00 31. " RXEMPTY , Receive data buffer empty" "Not empty,Empty"
|
|
bitfld.long 0x00 30. " RXOVR , Receive data buffer overrun" "No overrun,Overrun"
|
|
newline
|
|
bitfld.long 0x00 29. " TXFULL , Transmit data buffer full" "Not full,Full"
|
|
bitfld.long 0x00 28. " BITERR , Bit error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 27. " DESYNC , Desynchronization of slave device" "No,Yes"
|
|
bitfld.long 0x00 26. " PARITYERR , Parity error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 25. " TIMEOUT , Time-out because of non-activation of ENA pin" "No timeout,Timeout"
|
|
bitfld.long 0x00 24. " DLENERR , Data length error flag" "No,Yes"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " LCSNR , Last chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " RXDATA , SPI receive data"
|
|
rgroup.long (0x34+0x200)++0x03
|
|
line.long 0x00 "RXRAM, Multi-buffer RAM Receive Buffer Register 13"
|
|
bitfld.long 0x00 31. " RXEMPTY , Receive data buffer empty" "Not empty,Empty"
|
|
bitfld.long 0x00 30. " RXOVR , Receive data buffer overrun" "No overrun,Overrun"
|
|
newline
|
|
bitfld.long 0x00 29. " TXFULL , Transmit data buffer full" "Not full,Full"
|
|
bitfld.long 0x00 28. " BITERR , Bit error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 27. " DESYNC , Desynchronization of slave device" "No,Yes"
|
|
bitfld.long 0x00 26. " PARITYERR , Parity error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 25. " TIMEOUT , Time-out because of non-activation of ENA pin" "No timeout,Timeout"
|
|
bitfld.long 0x00 24. " DLENERR , Data length error flag" "No,Yes"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " LCSNR , Last chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " RXDATA , SPI receive data"
|
|
rgroup.long (0x38+0x200)++0x03
|
|
line.long 0x00 "RXRAM, Multi-buffer RAM Receive Buffer Register 14"
|
|
bitfld.long 0x00 31. " RXEMPTY , Receive data buffer empty" "Not empty,Empty"
|
|
bitfld.long 0x00 30. " RXOVR , Receive data buffer overrun" "No overrun,Overrun"
|
|
newline
|
|
bitfld.long 0x00 29. " TXFULL , Transmit data buffer full" "Not full,Full"
|
|
bitfld.long 0x00 28. " BITERR , Bit error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 27. " DESYNC , Desynchronization of slave device" "No,Yes"
|
|
bitfld.long 0x00 26. " PARITYERR , Parity error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 25. " TIMEOUT , Time-out because of non-activation of ENA pin" "No timeout,Timeout"
|
|
bitfld.long 0x00 24. " DLENERR , Data length error flag" "No,Yes"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " LCSNR , Last chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " RXDATA , SPI receive data"
|
|
rgroup.long (0x3C+0x200)++0x03
|
|
line.long 0x00 "RXRAM, Multi-buffer RAM Receive Buffer Register 15"
|
|
bitfld.long 0x00 31. " RXEMPTY , Receive data buffer empty" "Not empty,Empty"
|
|
bitfld.long 0x00 30. " RXOVR , Receive data buffer overrun" "No overrun,Overrun"
|
|
newline
|
|
bitfld.long 0x00 29. " TXFULL , Transmit data buffer full" "Not full,Full"
|
|
bitfld.long 0x00 28. " BITERR , Bit error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 27. " DESYNC , Desynchronization of slave device" "No,Yes"
|
|
bitfld.long 0x00 26. " PARITYERR , Parity error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 25. " TIMEOUT , Time-out because of non-activation of ENA pin" "No timeout,Timeout"
|
|
bitfld.long 0x00 24. " DLENERR , Data length error flag" "No,Yes"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " LCSNR , Last chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " RXDATA , SPI receive data"
|
|
rgroup.long (0x40+0x200)++0x03
|
|
line.long 0x00 "RXRAM, Multi-buffer RAM Receive Buffer Register 16"
|
|
bitfld.long 0x00 31. " RXEMPTY , Receive data buffer empty" "Not empty,Empty"
|
|
bitfld.long 0x00 30. " RXOVR , Receive data buffer overrun" "No overrun,Overrun"
|
|
newline
|
|
bitfld.long 0x00 29. " TXFULL , Transmit data buffer full" "Not full,Full"
|
|
bitfld.long 0x00 28. " BITERR , Bit error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 27. " DESYNC , Desynchronization of slave device" "No,Yes"
|
|
bitfld.long 0x00 26. " PARITYERR , Parity error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 25. " TIMEOUT , Time-out because of non-activation of ENA pin" "No timeout,Timeout"
|
|
bitfld.long 0x00 24. " DLENERR , Data length error flag" "No,Yes"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " LCSNR , Last chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " RXDATA , SPI receive data"
|
|
rgroup.long (0x44+0x200)++0x03
|
|
line.long 0x00 "RXRAM, Multi-buffer RAM Receive Buffer Register 17"
|
|
bitfld.long 0x00 31. " RXEMPTY , Receive data buffer empty" "Not empty,Empty"
|
|
bitfld.long 0x00 30. " RXOVR , Receive data buffer overrun" "No overrun,Overrun"
|
|
newline
|
|
bitfld.long 0x00 29. " TXFULL , Transmit data buffer full" "Not full,Full"
|
|
bitfld.long 0x00 28. " BITERR , Bit error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 27. " DESYNC , Desynchronization of slave device" "No,Yes"
|
|
bitfld.long 0x00 26. " PARITYERR , Parity error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 25. " TIMEOUT , Time-out because of non-activation of ENA pin" "No timeout,Timeout"
|
|
bitfld.long 0x00 24. " DLENERR , Data length error flag" "No,Yes"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " LCSNR , Last chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " RXDATA , SPI receive data"
|
|
rgroup.long (0x48+0x200)++0x03
|
|
line.long 0x00 "RXRAM, Multi-buffer RAM Receive Buffer Register 18"
|
|
bitfld.long 0x00 31. " RXEMPTY , Receive data buffer empty" "Not empty,Empty"
|
|
bitfld.long 0x00 30. " RXOVR , Receive data buffer overrun" "No overrun,Overrun"
|
|
newline
|
|
bitfld.long 0x00 29. " TXFULL , Transmit data buffer full" "Not full,Full"
|
|
bitfld.long 0x00 28. " BITERR , Bit error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 27. " DESYNC , Desynchronization of slave device" "No,Yes"
|
|
bitfld.long 0x00 26. " PARITYERR , Parity error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 25. " TIMEOUT , Time-out because of non-activation of ENA pin" "No timeout,Timeout"
|
|
bitfld.long 0x00 24. " DLENERR , Data length error flag" "No,Yes"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " LCSNR , Last chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " RXDATA , SPI receive data"
|
|
rgroup.long (0x4C+0x200)++0x03
|
|
line.long 0x00 "RXRAM, Multi-buffer RAM Receive Buffer Register 19"
|
|
bitfld.long 0x00 31. " RXEMPTY , Receive data buffer empty" "Not empty,Empty"
|
|
bitfld.long 0x00 30. " RXOVR , Receive data buffer overrun" "No overrun,Overrun"
|
|
newline
|
|
bitfld.long 0x00 29. " TXFULL , Transmit data buffer full" "Not full,Full"
|
|
bitfld.long 0x00 28. " BITERR , Bit error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 27. " DESYNC , Desynchronization of slave device" "No,Yes"
|
|
bitfld.long 0x00 26. " PARITYERR , Parity error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 25. " TIMEOUT , Time-out because of non-activation of ENA pin" "No timeout,Timeout"
|
|
bitfld.long 0x00 24. " DLENERR , Data length error flag" "No,Yes"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " LCSNR , Last chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " RXDATA , SPI receive data"
|
|
rgroup.long (0x50+0x200)++0x03
|
|
line.long 0x00 "RXRAM, Multi-buffer RAM Receive Buffer Register 20"
|
|
bitfld.long 0x00 31. " RXEMPTY , Receive data buffer empty" "Not empty,Empty"
|
|
bitfld.long 0x00 30. " RXOVR , Receive data buffer overrun" "No overrun,Overrun"
|
|
newline
|
|
bitfld.long 0x00 29. " TXFULL , Transmit data buffer full" "Not full,Full"
|
|
bitfld.long 0x00 28. " BITERR , Bit error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 27. " DESYNC , Desynchronization of slave device" "No,Yes"
|
|
bitfld.long 0x00 26. " PARITYERR , Parity error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 25. " TIMEOUT , Time-out because of non-activation of ENA pin" "No timeout,Timeout"
|
|
bitfld.long 0x00 24. " DLENERR , Data length error flag" "No,Yes"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " LCSNR , Last chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " RXDATA , SPI receive data"
|
|
rgroup.long (0x54+0x200)++0x03
|
|
line.long 0x00 "RXRAM, Multi-buffer RAM Receive Buffer Register 21"
|
|
bitfld.long 0x00 31. " RXEMPTY , Receive data buffer empty" "Not empty,Empty"
|
|
bitfld.long 0x00 30. " RXOVR , Receive data buffer overrun" "No overrun,Overrun"
|
|
newline
|
|
bitfld.long 0x00 29. " TXFULL , Transmit data buffer full" "Not full,Full"
|
|
bitfld.long 0x00 28. " BITERR , Bit error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 27. " DESYNC , Desynchronization of slave device" "No,Yes"
|
|
bitfld.long 0x00 26. " PARITYERR , Parity error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 25. " TIMEOUT , Time-out because of non-activation of ENA pin" "No timeout,Timeout"
|
|
bitfld.long 0x00 24. " DLENERR , Data length error flag" "No,Yes"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " LCSNR , Last chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " RXDATA , SPI receive data"
|
|
rgroup.long (0x58+0x200)++0x03
|
|
line.long 0x00 "RXRAM, Multi-buffer RAM Receive Buffer Register 22"
|
|
bitfld.long 0x00 31. " RXEMPTY , Receive data buffer empty" "Not empty,Empty"
|
|
bitfld.long 0x00 30. " RXOVR , Receive data buffer overrun" "No overrun,Overrun"
|
|
newline
|
|
bitfld.long 0x00 29. " TXFULL , Transmit data buffer full" "Not full,Full"
|
|
bitfld.long 0x00 28. " BITERR , Bit error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 27. " DESYNC , Desynchronization of slave device" "No,Yes"
|
|
bitfld.long 0x00 26. " PARITYERR , Parity error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 25. " TIMEOUT , Time-out because of non-activation of ENA pin" "No timeout,Timeout"
|
|
bitfld.long 0x00 24. " DLENERR , Data length error flag" "No,Yes"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " LCSNR , Last chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " RXDATA , SPI receive data"
|
|
rgroup.long (0x5C+0x200)++0x03
|
|
line.long 0x00 "RXRAM, Multi-buffer RAM Receive Buffer Register 23"
|
|
bitfld.long 0x00 31. " RXEMPTY , Receive data buffer empty" "Not empty,Empty"
|
|
bitfld.long 0x00 30. " RXOVR , Receive data buffer overrun" "No overrun,Overrun"
|
|
newline
|
|
bitfld.long 0x00 29. " TXFULL , Transmit data buffer full" "Not full,Full"
|
|
bitfld.long 0x00 28. " BITERR , Bit error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 27. " DESYNC , Desynchronization of slave device" "No,Yes"
|
|
bitfld.long 0x00 26. " PARITYERR , Parity error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 25. " TIMEOUT , Time-out because of non-activation of ENA pin" "No timeout,Timeout"
|
|
bitfld.long 0x00 24. " DLENERR , Data length error flag" "No,Yes"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " LCSNR , Last chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " RXDATA , SPI receive data"
|
|
rgroup.long (0x60+0x200)++0x03
|
|
line.long 0x00 "RXRAM, Multi-buffer RAM Receive Buffer Register 24"
|
|
bitfld.long 0x00 31. " RXEMPTY , Receive data buffer empty" "Not empty,Empty"
|
|
bitfld.long 0x00 30. " RXOVR , Receive data buffer overrun" "No overrun,Overrun"
|
|
newline
|
|
bitfld.long 0x00 29. " TXFULL , Transmit data buffer full" "Not full,Full"
|
|
bitfld.long 0x00 28. " BITERR , Bit error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 27. " DESYNC , Desynchronization of slave device" "No,Yes"
|
|
bitfld.long 0x00 26. " PARITYERR , Parity error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 25. " TIMEOUT , Time-out because of non-activation of ENA pin" "No timeout,Timeout"
|
|
bitfld.long 0x00 24. " DLENERR , Data length error flag" "No,Yes"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " LCSNR , Last chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " RXDATA , SPI receive data"
|
|
rgroup.long (0x64+0x200)++0x03
|
|
line.long 0x00 "RXRAM, Multi-buffer RAM Receive Buffer Register 25"
|
|
bitfld.long 0x00 31. " RXEMPTY , Receive data buffer empty" "Not empty,Empty"
|
|
bitfld.long 0x00 30. " RXOVR , Receive data buffer overrun" "No overrun,Overrun"
|
|
newline
|
|
bitfld.long 0x00 29. " TXFULL , Transmit data buffer full" "Not full,Full"
|
|
bitfld.long 0x00 28. " BITERR , Bit error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 27. " DESYNC , Desynchronization of slave device" "No,Yes"
|
|
bitfld.long 0x00 26. " PARITYERR , Parity error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 25. " TIMEOUT , Time-out because of non-activation of ENA pin" "No timeout,Timeout"
|
|
bitfld.long 0x00 24. " DLENERR , Data length error flag" "No,Yes"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " LCSNR , Last chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " RXDATA , SPI receive data"
|
|
rgroup.long (0x68+0x200)++0x03
|
|
line.long 0x00 "RXRAM, Multi-buffer RAM Receive Buffer Register 26"
|
|
bitfld.long 0x00 31. " RXEMPTY , Receive data buffer empty" "Not empty,Empty"
|
|
bitfld.long 0x00 30. " RXOVR , Receive data buffer overrun" "No overrun,Overrun"
|
|
newline
|
|
bitfld.long 0x00 29. " TXFULL , Transmit data buffer full" "Not full,Full"
|
|
bitfld.long 0x00 28. " BITERR , Bit error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 27. " DESYNC , Desynchronization of slave device" "No,Yes"
|
|
bitfld.long 0x00 26. " PARITYERR , Parity error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 25. " TIMEOUT , Time-out because of non-activation of ENA pin" "No timeout,Timeout"
|
|
bitfld.long 0x00 24. " DLENERR , Data length error flag" "No,Yes"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " LCSNR , Last chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " RXDATA , SPI receive data"
|
|
rgroup.long (0x6C+0x200)++0x03
|
|
line.long 0x00 "RXRAM, Multi-buffer RAM Receive Buffer Register 27"
|
|
bitfld.long 0x00 31. " RXEMPTY , Receive data buffer empty" "Not empty,Empty"
|
|
bitfld.long 0x00 30. " RXOVR , Receive data buffer overrun" "No overrun,Overrun"
|
|
newline
|
|
bitfld.long 0x00 29. " TXFULL , Transmit data buffer full" "Not full,Full"
|
|
bitfld.long 0x00 28. " BITERR , Bit error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 27. " DESYNC , Desynchronization of slave device" "No,Yes"
|
|
bitfld.long 0x00 26. " PARITYERR , Parity error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 25. " TIMEOUT , Time-out because of non-activation of ENA pin" "No timeout,Timeout"
|
|
bitfld.long 0x00 24. " DLENERR , Data length error flag" "No,Yes"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " LCSNR , Last chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " RXDATA , SPI receive data"
|
|
rgroup.long (0x70+0x200)++0x03
|
|
line.long 0x00 "RXRAM, Multi-buffer RAM Receive Buffer Register 28"
|
|
bitfld.long 0x00 31. " RXEMPTY , Receive data buffer empty" "Not empty,Empty"
|
|
bitfld.long 0x00 30. " RXOVR , Receive data buffer overrun" "No overrun,Overrun"
|
|
newline
|
|
bitfld.long 0x00 29. " TXFULL , Transmit data buffer full" "Not full,Full"
|
|
bitfld.long 0x00 28. " BITERR , Bit error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 27. " DESYNC , Desynchronization of slave device" "No,Yes"
|
|
bitfld.long 0x00 26. " PARITYERR , Parity error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 25. " TIMEOUT , Time-out because of non-activation of ENA pin" "No timeout,Timeout"
|
|
bitfld.long 0x00 24. " DLENERR , Data length error flag" "No,Yes"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " LCSNR , Last chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " RXDATA , SPI receive data"
|
|
rgroup.long (0x74+0x200)++0x03
|
|
line.long 0x00 "RXRAM, Multi-buffer RAM Receive Buffer Register 29"
|
|
bitfld.long 0x00 31. " RXEMPTY , Receive data buffer empty" "Not empty,Empty"
|
|
bitfld.long 0x00 30. " RXOVR , Receive data buffer overrun" "No overrun,Overrun"
|
|
newline
|
|
bitfld.long 0x00 29. " TXFULL , Transmit data buffer full" "Not full,Full"
|
|
bitfld.long 0x00 28. " BITERR , Bit error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 27. " DESYNC , Desynchronization of slave device" "No,Yes"
|
|
bitfld.long 0x00 26. " PARITYERR , Parity error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 25. " TIMEOUT , Time-out because of non-activation of ENA pin" "No timeout,Timeout"
|
|
bitfld.long 0x00 24. " DLENERR , Data length error flag" "No,Yes"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " LCSNR , Last chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " RXDATA , SPI receive data"
|
|
rgroup.long (0x78+0x200)++0x03
|
|
line.long 0x00 "RXRAM, Multi-buffer RAM Receive Buffer Register 30"
|
|
bitfld.long 0x00 31. " RXEMPTY , Receive data buffer empty" "Not empty,Empty"
|
|
bitfld.long 0x00 30. " RXOVR , Receive data buffer overrun" "No overrun,Overrun"
|
|
newline
|
|
bitfld.long 0x00 29. " TXFULL , Transmit data buffer full" "Not full,Full"
|
|
bitfld.long 0x00 28. " BITERR , Bit error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 27. " DESYNC , Desynchronization of slave device" "No,Yes"
|
|
bitfld.long 0x00 26. " PARITYERR , Parity error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 25. " TIMEOUT , Time-out because of non-activation of ENA pin" "No timeout,Timeout"
|
|
bitfld.long 0x00 24. " DLENERR , Data length error flag" "No,Yes"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " LCSNR , Last chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " RXDATA , SPI receive data"
|
|
rgroup.long (0x7C+0x200)++0x03
|
|
line.long 0x00 "RXRAM, Multi-buffer RAM Receive Buffer Register 31"
|
|
bitfld.long 0x00 31. " RXEMPTY , Receive data buffer empty" "Not empty,Empty"
|
|
bitfld.long 0x00 30. " RXOVR , Receive data buffer overrun" "No overrun,Overrun"
|
|
newline
|
|
bitfld.long 0x00 29. " TXFULL , Transmit data buffer full" "Not full,Full"
|
|
bitfld.long 0x00 28. " BITERR , Bit error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 27. " DESYNC , Desynchronization of slave device" "No,Yes"
|
|
bitfld.long 0x00 26. " PARITYERR , Parity error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 25. " TIMEOUT , Time-out because of non-activation of ENA pin" "No timeout,Timeout"
|
|
bitfld.long 0x00 24. " DLENERR , Data length error flag" "No,Yes"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " LCSNR , Last chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " RXDATA , SPI receive data"
|
|
rgroup.long (0x80+0x200)++0x03
|
|
line.long 0x00 "RXRAM, Multi-buffer RAM Receive Buffer Register 32"
|
|
bitfld.long 0x00 31. " RXEMPTY , Receive data buffer empty" "Not empty,Empty"
|
|
bitfld.long 0x00 30. " RXOVR , Receive data buffer overrun" "No overrun,Overrun"
|
|
newline
|
|
bitfld.long 0x00 29. " TXFULL , Transmit data buffer full" "Not full,Full"
|
|
bitfld.long 0x00 28. " BITERR , Bit error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 27. " DESYNC , Desynchronization of slave device" "No,Yes"
|
|
bitfld.long 0x00 26. " PARITYERR , Parity error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 25. " TIMEOUT , Time-out because of non-activation of ENA pin" "No timeout,Timeout"
|
|
bitfld.long 0x00 24. " DLENERR , Data length error flag" "No,Yes"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " LCSNR , Last chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " RXDATA , SPI receive data"
|
|
rgroup.long (0x84+0x200)++0x03
|
|
line.long 0x00 "RXRAM, Multi-buffer RAM Receive Buffer Register 33"
|
|
bitfld.long 0x00 31. " RXEMPTY , Receive data buffer empty" "Not empty,Empty"
|
|
bitfld.long 0x00 30. " RXOVR , Receive data buffer overrun" "No overrun,Overrun"
|
|
newline
|
|
bitfld.long 0x00 29. " TXFULL , Transmit data buffer full" "Not full,Full"
|
|
bitfld.long 0x00 28. " BITERR , Bit error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 27. " DESYNC , Desynchronization of slave device" "No,Yes"
|
|
bitfld.long 0x00 26. " PARITYERR , Parity error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 25. " TIMEOUT , Time-out because of non-activation of ENA pin" "No timeout,Timeout"
|
|
bitfld.long 0x00 24. " DLENERR , Data length error flag" "No,Yes"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " LCSNR , Last chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " RXDATA , SPI receive data"
|
|
rgroup.long (0x88+0x200)++0x03
|
|
line.long 0x00 "RXRAM, Multi-buffer RAM Receive Buffer Register 34"
|
|
bitfld.long 0x00 31. " RXEMPTY , Receive data buffer empty" "Not empty,Empty"
|
|
bitfld.long 0x00 30. " RXOVR , Receive data buffer overrun" "No overrun,Overrun"
|
|
newline
|
|
bitfld.long 0x00 29. " TXFULL , Transmit data buffer full" "Not full,Full"
|
|
bitfld.long 0x00 28. " BITERR , Bit error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 27. " DESYNC , Desynchronization of slave device" "No,Yes"
|
|
bitfld.long 0x00 26. " PARITYERR , Parity error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 25. " TIMEOUT , Time-out because of non-activation of ENA pin" "No timeout,Timeout"
|
|
bitfld.long 0x00 24. " DLENERR , Data length error flag" "No,Yes"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " LCSNR , Last chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " RXDATA , SPI receive data"
|
|
rgroup.long (0x8C+0x200)++0x03
|
|
line.long 0x00 "RXRAM, Multi-buffer RAM Receive Buffer Register 35"
|
|
bitfld.long 0x00 31. " RXEMPTY , Receive data buffer empty" "Not empty,Empty"
|
|
bitfld.long 0x00 30. " RXOVR , Receive data buffer overrun" "No overrun,Overrun"
|
|
newline
|
|
bitfld.long 0x00 29. " TXFULL , Transmit data buffer full" "Not full,Full"
|
|
bitfld.long 0x00 28. " BITERR , Bit error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 27. " DESYNC , Desynchronization of slave device" "No,Yes"
|
|
bitfld.long 0x00 26. " PARITYERR , Parity error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 25. " TIMEOUT , Time-out because of non-activation of ENA pin" "No timeout,Timeout"
|
|
bitfld.long 0x00 24. " DLENERR , Data length error flag" "No,Yes"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " LCSNR , Last chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " RXDATA , SPI receive data"
|
|
rgroup.long (0x90+0x200)++0x03
|
|
line.long 0x00 "RXRAM, Multi-buffer RAM Receive Buffer Register 36"
|
|
bitfld.long 0x00 31. " RXEMPTY , Receive data buffer empty" "Not empty,Empty"
|
|
bitfld.long 0x00 30. " RXOVR , Receive data buffer overrun" "No overrun,Overrun"
|
|
newline
|
|
bitfld.long 0x00 29. " TXFULL , Transmit data buffer full" "Not full,Full"
|
|
bitfld.long 0x00 28. " BITERR , Bit error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 27. " DESYNC , Desynchronization of slave device" "No,Yes"
|
|
bitfld.long 0x00 26. " PARITYERR , Parity error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 25. " TIMEOUT , Time-out because of non-activation of ENA pin" "No timeout,Timeout"
|
|
bitfld.long 0x00 24. " DLENERR , Data length error flag" "No,Yes"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " LCSNR , Last chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " RXDATA , SPI receive data"
|
|
rgroup.long (0x94+0x200)++0x03
|
|
line.long 0x00 "RXRAM, Multi-buffer RAM Receive Buffer Register 37"
|
|
bitfld.long 0x00 31. " RXEMPTY , Receive data buffer empty" "Not empty,Empty"
|
|
bitfld.long 0x00 30. " RXOVR , Receive data buffer overrun" "No overrun,Overrun"
|
|
newline
|
|
bitfld.long 0x00 29. " TXFULL , Transmit data buffer full" "Not full,Full"
|
|
bitfld.long 0x00 28. " BITERR , Bit error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 27. " DESYNC , Desynchronization of slave device" "No,Yes"
|
|
bitfld.long 0x00 26. " PARITYERR , Parity error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 25. " TIMEOUT , Time-out because of non-activation of ENA pin" "No timeout,Timeout"
|
|
bitfld.long 0x00 24. " DLENERR , Data length error flag" "No,Yes"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " LCSNR , Last chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " RXDATA , SPI receive data"
|
|
rgroup.long (0x98+0x200)++0x03
|
|
line.long 0x00 "RXRAM, Multi-buffer RAM Receive Buffer Register 38"
|
|
bitfld.long 0x00 31. " RXEMPTY , Receive data buffer empty" "Not empty,Empty"
|
|
bitfld.long 0x00 30. " RXOVR , Receive data buffer overrun" "No overrun,Overrun"
|
|
newline
|
|
bitfld.long 0x00 29. " TXFULL , Transmit data buffer full" "Not full,Full"
|
|
bitfld.long 0x00 28. " BITERR , Bit error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 27. " DESYNC , Desynchronization of slave device" "No,Yes"
|
|
bitfld.long 0x00 26. " PARITYERR , Parity error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 25. " TIMEOUT , Time-out because of non-activation of ENA pin" "No timeout,Timeout"
|
|
bitfld.long 0x00 24. " DLENERR , Data length error flag" "No,Yes"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " LCSNR , Last chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " RXDATA , SPI receive data"
|
|
rgroup.long (0x9C+0x200)++0x03
|
|
line.long 0x00 "RXRAM, Multi-buffer RAM Receive Buffer Register 39"
|
|
bitfld.long 0x00 31. " RXEMPTY , Receive data buffer empty" "Not empty,Empty"
|
|
bitfld.long 0x00 30. " RXOVR , Receive data buffer overrun" "No overrun,Overrun"
|
|
newline
|
|
bitfld.long 0x00 29. " TXFULL , Transmit data buffer full" "Not full,Full"
|
|
bitfld.long 0x00 28. " BITERR , Bit error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 27. " DESYNC , Desynchronization of slave device" "No,Yes"
|
|
bitfld.long 0x00 26. " PARITYERR , Parity error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 25. " TIMEOUT , Time-out because of non-activation of ENA pin" "No timeout,Timeout"
|
|
bitfld.long 0x00 24. " DLENERR , Data length error flag" "No,Yes"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " LCSNR , Last chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " RXDATA , SPI receive data"
|
|
rgroup.long (0xA0+0x200)++0x03
|
|
line.long 0x00 "RXRAM, Multi-buffer RAM Receive Buffer Register 40"
|
|
bitfld.long 0x00 31. " RXEMPTY , Receive data buffer empty" "Not empty,Empty"
|
|
bitfld.long 0x00 30. " RXOVR , Receive data buffer overrun" "No overrun,Overrun"
|
|
newline
|
|
bitfld.long 0x00 29. " TXFULL , Transmit data buffer full" "Not full,Full"
|
|
bitfld.long 0x00 28. " BITERR , Bit error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 27. " DESYNC , Desynchronization of slave device" "No,Yes"
|
|
bitfld.long 0x00 26. " PARITYERR , Parity error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 25. " TIMEOUT , Time-out because of non-activation of ENA pin" "No timeout,Timeout"
|
|
bitfld.long 0x00 24. " DLENERR , Data length error flag" "No,Yes"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " LCSNR , Last chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " RXDATA , SPI receive data"
|
|
rgroup.long (0xA4+0x200)++0x03
|
|
line.long 0x00 "RXRAM, Multi-buffer RAM Receive Buffer Register 41"
|
|
bitfld.long 0x00 31. " RXEMPTY , Receive data buffer empty" "Not empty,Empty"
|
|
bitfld.long 0x00 30. " RXOVR , Receive data buffer overrun" "No overrun,Overrun"
|
|
newline
|
|
bitfld.long 0x00 29. " TXFULL , Transmit data buffer full" "Not full,Full"
|
|
bitfld.long 0x00 28. " BITERR , Bit error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 27. " DESYNC , Desynchronization of slave device" "No,Yes"
|
|
bitfld.long 0x00 26. " PARITYERR , Parity error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 25. " TIMEOUT , Time-out because of non-activation of ENA pin" "No timeout,Timeout"
|
|
bitfld.long 0x00 24. " DLENERR , Data length error flag" "No,Yes"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " LCSNR , Last chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " RXDATA , SPI receive data"
|
|
rgroup.long (0xA8+0x200)++0x03
|
|
line.long 0x00 "RXRAM, Multi-buffer RAM Receive Buffer Register 42"
|
|
bitfld.long 0x00 31. " RXEMPTY , Receive data buffer empty" "Not empty,Empty"
|
|
bitfld.long 0x00 30. " RXOVR , Receive data buffer overrun" "No overrun,Overrun"
|
|
newline
|
|
bitfld.long 0x00 29. " TXFULL , Transmit data buffer full" "Not full,Full"
|
|
bitfld.long 0x00 28. " BITERR , Bit error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 27. " DESYNC , Desynchronization of slave device" "No,Yes"
|
|
bitfld.long 0x00 26. " PARITYERR , Parity error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 25. " TIMEOUT , Time-out because of non-activation of ENA pin" "No timeout,Timeout"
|
|
bitfld.long 0x00 24. " DLENERR , Data length error flag" "No,Yes"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " LCSNR , Last chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " RXDATA , SPI receive data"
|
|
rgroup.long (0xAC+0x200)++0x03
|
|
line.long 0x00 "RXRAM, Multi-buffer RAM Receive Buffer Register 43"
|
|
bitfld.long 0x00 31. " RXEMPTY , Receive data buffer empty" "Not empty,Empty"
|
|
bitfld.long 0x00 30. " RXOVR , Receive data buffer overrun" "No overrun,Overrun"
|
|
newline
|
|
bitfld.long 0x00 29. " TXFULL , Transmit data buffer full" "Not full,Full"
|
|
bitfld.long 0x00 28. " BITERR , Bit error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 27. " DESYNC , Desynchronization of slave device" "No,Yes"
|
|
bitfld.long 0x00 26. " PARITYERR , Parity error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 25. " TIMEOUT , Time-out because of non-activation of ENA pin" "No timeout,Timeout"
|
|
bitfld.long 0x00 24. " DLENERR , Data length error flag" "No,Yes"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " LCSNR , Last chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " RXDATA , SPI receive data"
|
|
rgroup.long (0xB0+0x200)++0x03
|
|
line.long 0x00 "RXRAM, Multi-buffer RAM Receive Buffer Register 44"
|
|
bitfld.long 0x00 31. " RXEMPTY , Receive data buffer empty" "Not empty,Empty"
|
|
bitfld.long 0x00 30. " RXOVR , Receive data buffer overrun" "No overrun,Overrun"
|
|
newline
|
|
bitfld.long 0x00 29. " TXFULL , Transmit data buffer full" "Not full,Full"
|
|
bitfld.long 0x00 28. " BITERR , Bit error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 27. " DESYNC , Desynchronization of slave device" "No,Yes"
|
|
bitfld.long 0x00 26. " PARITYERR , Parity error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 25. " TIMEOUT , Time-out because of non-activation of ENA pin" "No timeout,Timeout"
|
|
bitfld.long 0x00 24. " DLENERR , Data length error flag" "No,Yes"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " LCSNR , Last chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " RXDATA , SPI receive data"
|
|
rgroup.long (0xB4+0x200)++0x03
|
|
line.long 0x00 "RXRAM, Multi-buffer RAM Receive Buffer Register 45"
|
|
bitfld.long 0x00 31. " RXEMPTY , Receive data buffer empty" "Not empty,Empty"
|
|
bitfld.long 0x00 30. " RXOVR , Receive data buffer overrun" "No overrun,Overrun"
|
|
newline
|
|
bitfld.long 0x00 29. " TXFULL , Transmit data buffer full" "Not full,Full"
|
|
bitfld.long 0x00 28. " BITERR , Bit error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 27. " DESYNC , Desynchronization of slave device" "No,Yes"
|
|
bitfld.long 0x00 26. " PARITYERR , Parity error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 25. " TIMEOUT , Time-out because of non-activation of ENA pin" "No timeout,Timeout"
|
|
bitfld.long 0x00 24. " DLENERR , Data length error flag" "No,Yes"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " LCSNR , Last chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " RXDATA , SPI receive data"
|
|
rgroup.long (0xB8+0x200)++0x03
|
|
line.long 0x00 "RXRAM, Multi-buffer RAM Receive Buffer Register 46"
|
|
bitfld.long 0x00 31. " RXEMPTY , Receive data buffer empty" "Not empty,Empty"
|
|
bitfld.long 0x00 30. " RXOVR , Receive data buffer overrun" "No overrun,Overrun"
|
|
newline
|
|
bitfld.long 0x00 29. " TXFULL , Transmit data buffer full" "Not full,Full"
|
|
bitfld.long 0x00 28. " BITERR , Bit error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 27. " DESYNC , Desynchronization of slave device" "No,Yes"
|
|
bitfld.long 0x00 26. " PARITYERR , Parity error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 25. " TIMEOUT , Time-out because of non-activation of ENA pin" "No timeout,Timeout"
|
|
bitfld.long 0x00 24. " DLENERR , Data length error flag" "No,Yes"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " LCSNR , Last chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " RXDATA , SPI receive data"
|
|
rgroup.long (0xBC+0x200)++0x03
|
|
line.long 0x00 "RXRAM, Multi-buffer RAM Receive Buffer Register 47"
|
|
bitfld.long 0x00 31. " RXEMPTY , Receive data buffer empty" "Not empty,Empty"
|
|
bitfld.long 0x00 30. " RXOVR , Receive data buffer overrun" "No overrun,Overrun"
|
|
newline
|
|
bitfld.long 0x00 29. " TXFULL , Transmit data buffer full" "Not full,Full"
|
|
bitfld.long 0x00 28. " BITERR , Bit error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 27. " DESYNC , Desynchronization of slave device" "No,Yes"
|
|
bitfld.long 0x00 26. " PARITYERR , Parity error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 25. " TIMEOUT , Time-out because of non-activation of ENA pin" "No timeout,Timeout"
|
|
bitfld.long 0x00 24. " DLENERR , Data length error flag" "No,Yes"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " LCSNR , Last chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " RXDATA , SPI receive data"
|
|
rgroup.long (0xC0+0x200)++0x03
|
|
line.long 0x00 "RXRAM, Multi-buffer RAM Receive Buffer Register 48"
|
|
bitfld.long 0x00 31. " RXEMPTY , Receive data buffer empty" "Not empty,Empty"
|
|
bitfld.long 0x00 30. " RXOVR , Receive data buffer overrun" "No overrun,Overrun"
|
|
newline
|
|
bitfld.long 0x00 29. " TXFULL , Transmit data buffer full" "Not full,Full"
|
|
bitfld.long 0x00 28. " BITERR , Bit error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 27. " DESYNC , Desynchronization of slave device" "No,Yes"
|
|
bitfld.long 0x00 26. " PARITYERR , Parity error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 25. " TIMEOUT , Time-out because of non-activation of ENA pin" "No timeout,Timeout"
|
|
bitfld.long 0x00 24. " DLENERR , Data length error flag" "No,Yes"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " LCSNR , Last chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " RXDATA , SPI receive data"
|
|
rgroup.long (0xC4+0x200)++0x03
|
|
line.long 0x00 "RXRAM, Multi-buffer RAM Receive Buffer Register 49"
|
|
bitfld.long 0x00 31. " RXEMPTY , Receive data buffer empty" "Not empty,Empty"
|
|
bitfld.long 0x00 30. " RXOVR , Receive data buffer overrun" "No overrun,Overrun"
|
|
newline
|
|
bitfld.long 0x00 29. " TXFULL , Transmit data buffer full" "Not full,Full"
|
|
bitfld.long 0x00 28. " BITERR , Bit error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 27. " DESYNC , Desynchronization of slave device" "No,Yes"
|
|
bitfld.long 0x00 26. " PARITYERR , Parity error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 25. " TIMEOUT , Time-out because of non-activation of ENA pin" "No timeout,Timeout"
|
|
bitfld.long 0x00 24. " DLENERR , Data length error flag" "No,Yes"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " LCSNR , Last chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " RXDATA , SPI receive data"
|
|
rgroup.long (0xC8+0x200)++0x03
|
|
line.long 0x00 "RXRAM, Multi-buffer RAM Receive Buffer Register 50"
|
|
bitfld.long 0x00 31. " RXEMPTY , Receive data buffer empty" "Not empty,Empty"
|
|
bitfld.long 0x00 30. " RXOVR , Receive data buffer overrun" "No overrun,Overrun"
|
|
newline
|
|
bitfld.long 0x00 29. " TXFULL , Transmit data buffer full" "Not full,Full"
|
|
bitfld.long 0x00 28. " BITERR , Bit error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 27. " DESYNC , Desynchronization of slave device" "No,Yes"
|
|
bitfld.long 0x00 26. " PARITYERR , Parity error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 25. " TIMEOUT , Time-out because of non-activation of ENA pin" "No timeout,Timeout"
|
|
bitfld.long 0x00 24. " DLENERR , Data length error flag" "No,Yes"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " LCSNR , Last chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " RXDATA , SPI receive data"
|
|
rgroup.long (0xCC+0x200)++0x03
|
|
line.long 0x00 "RXRAM, Multi-buffer RAM Receive Buffer Register 51"
|
|
bitfld.long 0x00 31. " RXEMPTY , Receive data buffer empty" "Not empty,Empty"
|
|
bitfld.long 0x00 30. " RXOVR , Receive data buffer overrun" "No overrun,Overrun"
|
|
newline
|
|
bitfld.long 0x00 29. " TXFULL , Transmit data buffer full" "Not full,Full"
|
|
bitfld.long 0x00 28. " BITERR , Bit error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 27. " DESYNC , Desynchronization of slave device" "No,Yes"
|
|
bitfld.long 0x00 26. " PARITYERR , Parity error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 25. " TIMEOUT , Time-out because of non-activation of ENA pin" "No timeout,Timeout"
|
|
bitfld.long 0x00 24. " DLENERR , Data length error flag" "No,Yes"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " LCSNR , Last chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " RXDATA , SPI receive data"
|
|
rgroup.long (0xD0+0x200)++0x03
|
|
line.long 0x00 "RXRAM, Multi-buffer RAM Receive Buffer Register 52"
|
|
bitfld.long 0x00 31. " RXEMPTY , Receive data buffer empty" "Not empty,Empty"
|
|
bitfld.long 0x00 30. " RXOVR , Receive data buffer overrun" "No overrun,Overrun"
|
|
newline
|
|
bitfld.long 0x00 29. " TXFULL , Transmit data buffer full" "Not full,Full"
|
|
bitfld.long 0x00 28. " BITERR , Bit error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 27. " DESYNC , Desynchronization of slave device" "No,Yes"
|
|
bitfld.long 0x00 26. " PARITYERR , Parity error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 25. " TIMEOUT , Time-out because of non-activation of ENA pin" "No timeout,Timeout"
|
|
bitfld.long 0x00 24. " DLENERR , Data length error flag" "No,Yes"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " LCSNR , Last chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " RXDATA , SPI receive data"
|
|
rgroup.long (0xD4+0x200)++0x03
|
|
line.long 0x00 "RXRAM, Multi-buffer RAM Receive Buffer Register 53"
|
|
bitfld.long 0x00 31. " RXEMPTY , Receive data buffer empty" "Not empty,Empty"
|
|
bitfld.long 0x00 30. " RXOVR , Receive data buffer overrun" "No overrun,Overrun"
|
|
newline
|
|
bitfld.long 0x00 29. " TXFULL , Transmit data buffer full" "Not full,Full"
|
|
bitfld.long 0x00 28. " BITERR , Bit error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 27. " DESYNC , Desynchronization of slave device" "No,Yes"
|
|
bitfld.long 0x00 26. " PARITYERR , Parity error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 25. " TIMEOUT , Time-out because of non-activation of ENA pin" "No timeout,Timeout"
|
|
bitfld.long 0x00 24. " DLENERR , Data length error flag" "No,Yes"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " LCSNR , Last chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " RXDATA , SPI receive data"
|
|
rgroup.long (0xD8+0x200)++0x03
|
|
line.long 0x00 "RXRAM, Multi-buffer RAM Receive Buffer Register 54"
|
|
bitfld.long 0x00 31. " RXEMPTY , Receive data buffer empty" "Not empty,Empty"
|
|
bitfld.long 0x00 30. " RXOVR , Receive data buffer overrun" "No overrun,Overrun"
|
|
newline
|
|
bitfld.long 0x00 29. " TXFULL , Transmit data buffer full" "Not full,Full"
|
|
bitfld.long 0x00 28. " BITERR , Bit error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 27. " DESYNC , Desynchronization of slave device" "No,Yes"
|
|
bitfld.long 0x00 26. " PARITYERR , Parity error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 25. " TIMEOUT , Time-out because of non-activation of ENA pin" "No timeout,Timeout"
|
|
bitfld.long 0x00 24. " DLENERR , Data length error flag" "No,Yes"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " LCSNR , Last chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " RXDATA , SPI receive data"
|
|
rgroup.long (0xDC+0x200)++0x03
|
|
line.long 0x00 "RXRAM, Multi-buffer RAM Receive Buffer Register 55"
|
|
bitfld.long 0x00 31. " RXEMPTY , Receive data buffer empty" "Not empty,Empty"
|
|
bitfld.long 0x00 30. " RXOVR , Receive data buffer overrun" "No overrun,Overrun"
|
|
newline
|
|
bitfld.long 0x00 29. " TXFULL , Transmit data buffer full" "Not full,Full"
|
|
bitfld.long 0x00 28. " BITERR , Bit error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 27. " DESYNC , Desynchronization of slave device" "No,Yes"
|
|
bitfld.long 0x00 26. " PARITYERR , Parity error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 25. " TIMEOUT , Time-out because of non-activation of ENA pin" "No timeout,Timeout"
|
|
bitfld.long 0x00 24. " DLENERR , Data length error flag" "No,Yes"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " LCSNR , Last chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " RXDATA , SPI receive data"
|
|
rgroup.long (0xE0+0x200)++0x03
|
|
line.long 0x00 "RXRAM, Multi-buffer RAM Receive Buffer Register 56"
|
|
bitfld.long 0x00 31. " RXEMPTY , Receive data buffer empty" "Not empty,Empty"
|
|
bitfld.long 0x00 30. " RXOVR , Receive data buffer overrun" "No overrun,Overrun"
|
|
newline
|
|
bitfld.long 0x00 29. " TXFULL , Transmit data buffer full" "Not full,Full"
|
|
bitfld.long 0x00 28. " BITERR , Bit error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 27. " DESYNC , Desynchronization of slave device" "No,Yes"
|
|
bitfld.long 0x00 26. " PARITYERR , Parity error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 25. " TIMEOUT , Time-out because of non-activation of ENA pin" "No timeout,Timeout"
|
|
bitfld.long 0x00 24. " DLENERR , Data length error flag" "No,Yes"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " LCSNR , Last chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " RXDATA , SPI receive data"
|
|
rgroup.long (0xE4+0x200)++0x03
|
|
line.long 0x00 "RXRAM, Multi-buffer RAM Receive Buffer Register 57"
|
|
bitfld.long 0x00 31. " RXEMPTY , Receive data buffer empty" "Not empty,Empty"
|
|
bitfld.long 0x00 30. " RXOVR , Receive data buffer overrun" "No overrun,Overrun"
|
|
newline
|
|
bitfld.long 0x00 29. " TXFULL , Transmit data buffer full" "Not full,Full"
|
|
bitfld.long 0x00 28. " BITERR , Bit error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 27. " DESYNC , Desynchronization of slave device" "No,Yes"
|
|
bitfld.long 0x00 26. " PARITYERR , Parity error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 25. " TIMEOUT , Time-out because of non-activation of ENA pin" "No timeout,Timeout"
|
|
bitfld.long 0x00 24. " DLENERR , Data length error flag" "No,Yes"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " LCSNR , Last chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " RXDATA , SPI receive data"
|
|
rgroup.long (0xE8+0x200)++0x03
|
|
line.long 0x00 "RXRAM, Multi-buffer RAM Receive Buffer Register 58"
|
|
bitfld.long 0x00 31. " RXEMPTY , Receive data buffer empty" "Not empty,Empty"
|
|
bitfld.long 0x00 30. " RXOVR , Receive data buffer overrun" "No overrun,Overrun"
|
|
newline
|
|
bitfld.long 0x00 29. " TXFULL , Transmit data buffer full" "Not full,Full"
|
|
bitfld.long 0x00 28. " BITERR , Bit error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 27. " DESYNC , Desynchronization of slave device" "No,Yes"
|
|
bitfld.long 0x00 26. " PARITYERR , Parity error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 25. " TIMEOUT , Time-out because of non-activation of ENA pin" "No timeout,Timeout"
|
|
bitfld.long 0x00 24. " DLENERR , Data length error flag" "No,Yes"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " LCSNR , Last chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " RXDATA , SPI receive data"
|
|
rgroup.long (0xEC+0x200)++0x03
|
|
line.long 0x00 "RXRAM, Multi-buffer RAM Receive Buffer Register 59"
|
|
bitfld.long 0x00 31. " RXEMPTY , Receive data buffer empty" "Not empty,Empty"
|
|
bitfld.long 0x00 30. " RXOVR , Receive data buffer overrun" "No overrun,Overrun"
|
|
newline
|
|
bitfld.long 0x00 29. " TXFULL , Transmit data buffer full" "Not full,Full"
|
|
bitfld.long 0x00 28. " BITERR , Bit error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 27. " DESYNC , Desynchronization of slave device" "No,Yes"
|
|
bitfld.long 0x00 26. " PARITYERR , Parity error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 25. " TIMEOUT , Time-out because of non-activation of ENA pin" "No timeout,Timeout"
|
|
bitfld.long 0x00 24. " DLENERR , Data length error flag" "No,Yes"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " LCSNR , Last chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " RXDATA , SPI receive data"
|
|
rgroup.long (0xF0+0x200)++0x03
|
|
line.long 0x00 "RXRAM, Multi-buffer RAM Receive Buffer Register 60"
|
|
bitfld.long 0x00 31. " RXEMPTY , Receive data buffer empty" "Not empty,Empty"
|
|
bitfld.long 0x00 30. " RXOVR , Receive data buffer overrun" "No overrun,Overrun"
|
|
newline
|
|
bitfld.long 0x00 29. " TXFULL , Transmit data buffer full" "Not full,Full"
|
|
bitfld.long 0x00 28. " BITERR , Bit error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 27. " DESYNC , Desynchronization of slave device" "No,Yes"
|
|
bitfld.long 0x00 26. " PARITYERR , Parity error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 25. " TIMEOUT , Time-out because of non-activation of ENA pin" "No timeout,Timeout"
|
|
bitfld.long 0x00 24. " DLENERR , Data length error flag" "No,Yes"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " LCSNR , Last chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " RXDATA , SPI receive data"
|
|
rgroup.long (0xF4+0x200)++0x03
|
|
line.long 0x00 "RXRAM, Multi-buffer RAM Receive Buffer Register 61"
|
|
bitfld.long 0x00 31. " RXEMPTY , Receive data buffer empty" "Not empty,Empty"
|
|
bitfld.long 0x00 30. " RXOVR , Receive data buffer overrun" "No overrun,Overrun"
|
|
newline
|
|
bitfld.long 0x00 29. " TXFULL , Transmit data buffer full" "Not full,Full"
|
|
bitfld.long 0x00 28. " BITERR , Bit error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 27. " DESYNC , Desynchronization of slave device" "No,Yes"
|
|
bitfld.long 0x00 26. " PARITYERR , Parity error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 25. " TIMEOUT , Time-out because of non-activation of ENA pin" "No timeout,Timeout"
|
|
bitfld.long 0x00 24. " DLENERR , Data length error flag" "No,Yes"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " LCSNR , Last chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " RXDATA , SPI receive data"
|
|
rgroup.long (0xF8+0x200)++0x03
|
|
line.long 0x00 "RXRAM, Multi-buffer RAM Receive Buffer Register 62"
|
|
bitfld.long 0x00 31. " RXEMPTY , Receive data buffer empty" "Not empty,Empty"
|
|
bitfld.long 0x00 30. " RXOVR , Receive data buffer overrun" "No overrun,Overrun"
|
|
newline
|
|
bitfld.long 0x00 29. " TXFULL , Transmit data buffer full" "Not full,Full"
|
|
bitfld.long 0x00 28. " BITERR , Bit error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 27. " DESYNC , Desynchronization of slave device" "No,Yes"
|
|
bitfld.long 0x00 26. " PARITYERR , Parity error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 25. " TIMEOUT , Time-out because of non-activation of ENA pin" "No timeout,Timeout"
|
|
bitfld.long 0x00 24. " DLENERR , Data length error flag" "No,Yes"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " LCSNR , Last chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " RXDATA , SPI receive data"
|
|
rgroup.long (0xFC+0x200)++0x03
|
|
line.long 0x00 "RXRAM, Multi-buffer RAM Receive Buffer Register 63"
|
|
bitfld.long 0x00 31. " RXEMPTY , Receive data buffer empty" "Not empty,Empty"
|
|
bitfld.long 0x00 30. " RXOVR , Receive data buffer overrun" "No overrun,Overrun"
|
|
newline
|
|
bitfld.long 0x00 29. " TXFULL , Transmit data buffer full" "Not full,Full"
|
|
bitfld.long 0x00 28. " BITERR , Bit error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 27. " DESYNC , Desynchronization of slave device" "No,Yes"
|
|
bitfld.long 0x00 26. " PARITYERR , Parity error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 25. " TIMEOUT , Time-out because of non-activation of ENA pin" "No timeout,Timeout"
|
|
bitfld.long 0x00 24. " DLENERR , Data length error flag" "No,Yes"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " LCSNR , Last chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " RXDATA , SPI receive data"
|
|
rgroup.long (0x100+0x200)++0x03
|
|
line.long 0x00 "RXRAM, Multi-buffer RAM Receive Buffer Register 64"
|
|
bitfld.long 0x00 31. " RXEMPTY , Receive data buffer empty" "Not empty,Empty"
|
|
bitfld.long 0x00 30. " RXOVR , Receive data buffer overrun" "No overrun,Overrun"
|
|
newline
|
|
bitfld.long 0x00 29. " TXFULL , Transmit data buffer full" "Not full,Full"
|
|
bitfld.long 0x00 28. " BITERR , Bit error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 27. " DESYNC , Desynchronization of slave device" "No,Yes"
|
|
bitfld.long 0x00 26. " PARITYERR , Parity error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 25. " TIMEOUT , Time-out because of non-activation of ENA pin" "No timeout,Timeout"
|
|
bitfld.long 0x00 24. " DLENERR , Data length error flag" "No,Yes"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " LCSNR , Last chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " RXDATA , SPI receive data"
|
|
rgroup.long (0x104+0x200)++0x03
|
|
line.long 0x00 "RXRAM, Multi-buffer RAM Receive Buffer Register 65"
|
|
bitfld.long 0x00 31. " RXEMPTY , Receive data buffer empty" "Not empty,Empty"
|
|
bitfld.long 0x00 30. " RXOVR , Receive data buffer overrun" "No overrun,Overrun"
|
|
newline
|
|
bitfld.long 0x00 29. " TXFULL , Transmit data buffer full" "Not full,Full"
|
|
bitfld.long 0x00 28. " BITERR , Bit error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 27. " DESYNC , Desynchronization of slave device" "No,Yes"
|
|
bitfld.long 0x00 26. " PARITYERR , Parity error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 25. " TIMEOUT , Time-out because of non-activation of ENA pin" "No timeout,Timeout"
|
|
bitfld.long 0x00 24. " DLENERR , Data length error flag" "No,Yes"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " LCSNR , Last chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " RXDATA , SPI receive data"
|
|
rgroup.long (0x108+0x200)++0x03
|
|
line.long 0x00 "RXRAM, Multi-buffer RAM Receive Buffer Register 66"
|
|
bitfld.long 0x00 31. " RXEMPTY , Receive data buffer empty" "Not empty,Empty"
|
|
bitfld.long 0x00 30. " RXOVR , Receive data buffer overrun" "No overrun,Overrun"
|
|
newline
|
|
bitfld.long 0x00 29. " TXFULL , Transmit data buffer full" "Not full,Full"
|
|
bitfld.long 0x00 28. " BITERR , Bit error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 27. " DESYNC , Desynchronization of slave device" "No,Yes"
|
|
bitfld.long 0x00 26. " PARITYERR , Parity error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 25. " TIMEOUT , Time-out because of non-activation of ENA pin" "No timeout,Timeout"
|
|
bitfld.long 0x00 24. " DLENERR , Data length error flag" "No,Yes"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " LCSNR , Last chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " RXDATA , SPI receive data"
|
|
rgroup.long (0x10C+0x200)++0x03
|
|
line.long 0x00 "RXRAM, Multi-buffer RAM Receive Buffer Register 67"
|
|
bitfld.long 0x00 31. " RXEMPTY , Receive data buffer empty" "Not empty,Empty"
|
|
bitfld.long 0x00 30. " RXOVR , Receive data buffer overrun" "No overrun,Overrun"
|
|
newline
|
|
bitfld.long 0x00 29. " TXFULL , Transmit data buffer full" "Not full,Full"
|
|
bitfld.long 0x00 28. " BITERR , Bit error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 27. " DESYNC , Desynchronization of slave device" "No,Yes"
|
|
bitfld.long 0x00 26. " PARITYERR , Parity error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 25. " TIMEOUT , Time-out because of non-activation of ENA pin" "No timeout,Timeout"
|
|
bitfld.long 0x00 24. " DLENERR , Data length error flag" "No,Yes"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " LCSNR , Last chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " RXDATA , SPI receive data"
|
|
rgroup.long (0x110+0x200)++0x03
|
|
line.long 0x00 "RXRAM, Multi-buffer RAM Receive Buffer Register 68"
|
|
bitfld.long 0x00 31. " RXEMPTY , Receive data buffer empty" "Not empty,Empty"
|
|
bitfld.long 0x00 30. " RXOVR , Receive data buffer overrun" "No overrun,Overrun"
|
|
newline
|
|
bitfld.long 0x00 29. " TXFULL , Transmit data buffer full" "Not full,Full"
|
|
bitfld.long 0x00 28. " BITERR , Bit error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 27. " DESYNC , Desynchronization of slave device" "No,Yes"
|
|
bitfld.long 0x00 26. " PARITYERR , Parity error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 25. " TIMEOUT , Time-out because of non-activation of ENA pin" "No timeout,Timeout"
|
|
bitfld.long 0x00 24. " DLENERR , Data length error flag" "No,Yes"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " LCSNR , Last chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " RXDATA , SPI receive data"
|
|
rgroup.long (0x114+0x200)++0x03
|
|
line.long 0x00 "RXRAM, Multi-buffer RAM Receive Buffer Register 69"
|
|
bitfld.long 0x00 31. " RXEMPTY , Receive data buffer empty" "Not empty,Empty"
|
|
bitfld.long 0x00 30. " RXOVR , Receive data buffer overrun" "No overrun,Overrun"
|
|
newline
|
|
bitfld.long 0x00 29. " TXFULL , Transmit data buffer full" "Not full,Full"
|
|
bitfld.long 0x00 28. " BITERR , Bit error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 27. " DESYNC , Desynchronization of slave device" "No,Yes"
|
|
bitfld.long 0x00 26. " PARITYERR , Parity error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 25. " TIMEOUT , Time-out because of non-activation of ENA pin" "No timeout,Timeout"
|
|
bitfld.long 0x00 24. " DLENERR , Data length error flag" "No,Yes"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " LCSNR , Last chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " RXDATA , SPI receive data"
|
|
rgroup.long (0x118+0x200)++0x03
|
|
line.long 0x00 "RXRAM, Multi-buffer RAM Receive Buffer Register 70"
|
|
bitfld.long 0x00 31. " RXEMPTY , Receive data buffer empty" "Not empty,Empty"
|
|
bitfld.long 0x00 30. " RXOVR , Receive data buffer overrun" "No overrun,Overrun"
|
|
newline
|
|
bitfld.long 0x00 29. " TXFULL , Transmit data buffer full" "Not full,Full"
|
|
bitfld.long 0x00 28. " BITERR , Bit error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 27. " DESYNC , Desynchronization of slave device" "No,Yes"
|
|
bitfld.long 0x00 26. " PARITYERR , Parity error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 25. " TIMEOUT , Time-out because of non-activation of ENA pin" "No timeout,Timeout"
|
|
bitfld.long 0x00 24. " DLENERR , Data length error flag" "No,Yes"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " LCSNR , Last chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " RXDATA , SPI receive data"
|
|
rgroup.long (0x11C+0x200)++0x03
|
|
line.long 0x00 "RXRAM, Multi-buffer RAM Receive Buffer Register 71"
|
|
bitfld.long 0x00 31. " RXEMPTY , Receive data buffer empty" "Not empty,Empty"
|
|
bitfld.long 0x00 30. " RXOVR , Receive data buffer overrun" "No overrun,Overrun"
|
|
newline
|
|
bitfld.long 0x00 29. " TXFULL , Transmit data buffer full" "Not full,Full"
|
|
bitfld.long 0x00 28. " BITERR , Bit error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 27. " DESYNC , Desynchronization of slave device" "No,Yes"
|
|
bitfld.long 0x00 26. " PARITYERR , Parity error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 25. " TIMEOUT , Time-out because of non-activation of ENA pin" "No timeout,Timeout"
|
|
bitfld.long 0x00 24. " DLENERR , Data length error flag" "No,Yes"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " LCSNR , Last chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " RXDATA , SPI receive data"
|
|
rgroup.long (0x120+0x200)++0x03
|
|
line.long 0x00 "RXRAM, Multi-buffer RAM Receive Buffer Register 72"
|
|
bitfld.long 0x00 31. " RXEMPTY , Receive data buffer empty" "Not empty,Empty"
|
|
bitfld.long 0x00 30. " RXOVR , Receive data buffer overrun" "No overrun,Overrun"
|
|
newline
|
|
bitfld.long 0x00 29. " TXFULL , Transmit data buffer full" "Not full,Full"
|
|
bitfld.long 0x00 28. " BITERR , Bit error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 27. " DESYNC , Desynchronization of slave device" "No,Yes"
|
|
bitfld.long 0x00 26. " PARITYERR , Parity error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 25. " TIMEOUT , Time-out because of non-activation of ENA pin" "No timeout,Timeout"
|
|
bitfld.long 0x00 24. " DLENERR , Data length error flag" "No,Yes"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " LCSNR , Last chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " RXDATA , SPI receive data"
|
|
rgroup.long (0x124+0x200)++0x03
|
|
line.long 0x00 "RXRAM, Multi-buffer RAM Receive Buffer Register 73"
|
|
bitfld.long 0x00 31. " RXEMPTY , Receive data buffer empty" "Not empty,Empty"
|
|
bitfld.long 0x00 30. " RXOVR , Receive data buffer overrun" "No overrun,Overrun"
|
|
newline
|
|
bitfld.long 0x00 29. " TXFULL , Transmit data buffer full" "Not full,Full"
|
|
bitfld.long 0x00 28. " BITERR , Bit error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 27. " DESYNC , Desynchronization of slave device" "No,Yes"
|
|
bitfld.long 0x00 26. " PARITYERR , Parity error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 25. " TIMEOUT , Time-out because of non-activation of ENA pin" "No timeout,Timeout"
|
|
bitfld.long 0x00 24. " DLENERR , Data length error flag" "No,Yes"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " LCSNR , Last chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " RXDATA , SPI receive data"
|
|
rgroup.long (0x128+0x200)++0x03
|
|
line.long 0x00 "RXRAM, Multi-buffer RAM Receive Buffer Register 74"
|
|
bitfld.long 0x00 31. " RXEMPTY , Receive data buffer empty" "Not empty,Empty"
|
|
bitfld.long 0x00 30. " RXOVR , Receive data buffer overrun" "No overrun,Overrun"
|
|
newline
|
|
bitfld.long 0x00 29. " TXFULL , Transmit data buffer full" "Not full,Full"
|
|
bitfld.long 0x00 28. " BITERR , Bit error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 27. " DESYNC , Desynchronization of slave device" "No,Yes"
|
|
bitfld.long 0x00 26. " PARITYERR , Parity error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 25. " TIMEOUT , Time-out because of non-activation of ENA pin" "No timeout,Timeout"
|
|
bitfld.long 0x00 24. " DLENERR , Data length error flag" "No,Yes"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " LCSNR , Last chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " RXDATA , SPI receive data"
|
|
rgroup.long (0x12C+0x200)++0x03
|
|
line.long 0x00 "RXRAM, Multi-buffer RAM Receive Buffer Register 75"
|
|
bitfld.long 0x00 31. " RXEMPTY , Receive data buffer empty" "Not empty,Empty"
|
|
bitfld.long 0x00 30. " RXOVR , Receive data buffer overrun" "No overrun,Overrun"
|
|
newline
|
|
bitfld.long 0x00 29. " TXFULL , Transmit data buffer full" "Not full,Full"
|
|
bitfld.long 0x00 28. " BITERR , Bit error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 27. " DESYNC , Desynchronization of slave device" "No,Yes"
|
|
bitfld.long 0x00 26. " PARITYERR , Parity error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 25. " TIMEOUT , Time-out because of non-activation of ENA pin" "No timeout,Timeout"
|
|
bitfld.long 0x00 24. " DLENERR , Data length error flag" "No,Yes"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " LCSNR , Last chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " RXDATA , SPI receive data"
|
|
rgroup.long (0x130+0x200)++0x03
|
|
line.long 0x00 "RXRAM, Multi-buffer RAM Receive Buffer Register 76"
|
|
bitfld.long 0x00 31. " RXEMPTY , Receive data buffer empty" "Not empty,Empty"
|
|
bitfld.long 0x00 30. " RXOVR , Receive data buffer overrun" "No overrun,Overrun"
|
|
newline
|
|
bitfld.long 0x00 29. " TXFULL , Transmit data buffer full" "Not full,Full"
|
|
bitfld.long 0x00 28. " BITERR , Bit error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 27. " DESYNC , Desynchronization of slave device" "No,Yes"
|
|
bitfld.long 0x00 26. " PARITYERR , Parity error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 25. " TIMEOUT , Time-out because of non-activation of ENA pin" "No timeout,Timeout"
|
|
bitfld.long 0x00 24. " DLENERR , Data length error flag" "No,Yes"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " LCSNR , Last chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " RXDATA , SPI receive data"
|
|
rgroup.long (0x134+0x200)++0x03
|
|
line.long 0x00 "RXRAM, Multi-buffer RAM Receive Buffer Register 77"
|
|
bitfld.long 0x00 31. " RXEMPTY , Receive data buffer empty" "Not empty,Empty"
|
|
bitfld.long 0x00 30. " RXOVR , Receive data buffer overrun" "No overrun,Overrun"
|
|
newline
|
|
bitfld.long 0x00 29. " TXFULL , Transmit data buffer full" "Not full,Full"
|
|
bitfld.long 0x00 28. " BITERR , Bit error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 27. " DESYNC , Desynchronization of slave device" "No,Yes"
|
|
bitfld.long 0x00 26. " PARITYERR , Parity error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 25. " TIMEOUT , Time-out because of non-activation of ENA pin" "No timeout,Timeout"
|
|
bitfld.long 0x00 24. " DLENERR , Data length error flag" "No,Yes"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " LCSNR , Last chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " RXDATA , SPI receive data"
|
|
rgroup.long (0x138+0x200)++0x03
|
|
line.long 0x00 "RXRAM, Multi-buffer RAM Receive Buffer Register 78"
|
|
bitfld.long 0x00 31. " RXEMPTY , Receive data buffer empty" "Not empty,Empty"
|
|
bitfld.long 0x00 30. " RXOVR , Receive data buffer overrun" "No overrun,Overrun"
|
|
newline
|
|
bitfld.long 0x00 29. " TXFULL , Transmit data buffer full" "Not full,Full"
|
|
bitfld.long 0x00 28. " BITERR , Bit error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 27. " DESYNC , Desynchronization of slave device" "No,Yes"
|
|
bitfld.long 0x00 26. " PARITYERR , Parity error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 25. " TIMEOUT , Time-out because of non-activation of ENA pin" "No timeout,Timeout"
|
|
bitfld.long 0x00 24. " DLENERR , Data length error flag" "No,Yes"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " LCSNR , Last chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " RXDATA , SPI receive data"
|
|
rgroup.long (0x13C+0x200)++0x03
|
|
line.long 0x00 "RXRAM, Multi-buffer RAM Receive Buffer Register 79"
|
|
bitfld.long 0x00 31. " RXEMPTY , Receive data buffer empty" "Not empty,Empty"
|
|
bitfld.long 0x00 30. " RXOVR , Receive data buffer overrun" "No overrun,Overrun"
|
|
newline
|
|
bitfld.long 0x00 29. " TXFULL , Transmit data buffer full" "Not full,Full"
|
|
bitfld.long 0x00 28. " BITERR , Bit error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 27. " DESYNC , Desynchronization of slave device" "No,Yes"
|
|
bitfld.long 0x00 26. " PARITYERR , Parity error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 25. " TIMEOUT , Time-out because of non-activation of ENA pin" "No timeout,Timeout"
|
|
bitfld.long 0x00 24. " DLENERR , Data length error flag" "No,Yes"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " LCSNR , Last chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " RXDATA , SPI receive data"
|
|
else
|
|
tree "Transmit Buffers"
|
|
group.long 0x0++0x03
|
|
line.long 0x00 "BUFFER0,Buffer 0 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x4++0x03
|
|
line.long 0x00 "BUFFER1,Buffer 1 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x8++0x03
|
|
line.long 0x00 "BUFFER2,Buffer 2 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0xC++0x03
|
|
line.long 0x00 "BUFFER3,Buffer 3 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "BUFFER4,Buffer 4 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "BUFFER5,Buffer 5 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "BUFFER6,Buffer 6 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "BUFFER7,Buffer 7 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "BUFFER8,Buffer 8 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "BUFFER9,Buffer 9 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "BUFFER10,Buffer 10 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "BUFFER11,Buffer 11 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "BUFFER12,Buffer 12 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x34++0x03
|
|
line.long 0x00 "BUFFER13,Buffer 13 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x38++0x03
|
|
line.long 0x00 "BUFFER14,Buffer 14 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x3C++0x03
|
|
line.long 0x00 "BUFFER15,Buffer 15 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "BUFFER16,Buffer 16 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x44++0x03
|
|
line.long 0x00 "BUFFER17,Buffer 17 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x48++0x03
|
|
line.long 0x00 "BUFFER18,Buffer 18 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x4C++0x03
|
|
line.long 0x00 "BUFFER19,Buffer 19 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x50++0x03
|
|
line.long 0x00 "BUFFER20,Buffer 20 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x54++0x03
|
|
line.long 0x00 "BUFFER21,Buffer 21 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x58++0x03
|
|
line.long 0x00 "BUFFER22,Buffer 22 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x5C++0x03
|
|
line.long 0x00 "BUFFER23,Buffer 23 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x60++0x03
|
|
line.long 0x00 "BUFFER24,Buffer 24 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x64++0x03
|
|
line.long 0x00 "BUFFER25,Buffer 25 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x68++0x03
|
|
line.long 0x00 "BUFFER26,Buffer 26 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x6C++0x03
|
|
line.long 0x00 "BUFFER27,Buffer 27 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x70++0x03
|
|
line.long 0x00 "BUFFER28,Buffer 28 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x74++0x03
|
|
line.long 0x00 "BUFFER29,Buffer 29 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x78++0x03
|
|
line.long 0x00 "BUFFER30,Buffer 30 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x7C++0x03
|
|
line.long 0x00 "BUFFER31,Buffer 31 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x80++0x03
|
|
line.long 0x00 "BUFFER32,Buffer 32 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x84++0x03
|
|
line.long 0x00 "BUFFER33,Buffer 33 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x88++0x03
|
|
line.long 0x00 "BUFFER34,Buffer 34 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x8C++0x03
|
|
line.long 0x00 "BUFFER35,Buffer 35 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x90++0x03
|
|
line.long 0x00 "BUFFER36,Buffer 36 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x94++0x03
|
|
line.long 0x00 "BUFFER37,Buffer 37 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x98++0x03
|
|
line.long 0x00 "BUFFER38,Buffer 38 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x9C++0x03
|
|
line.long 0x00 "BUFFER39,Buffer 39 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0xA0++0x03
|
|
line.long 0x00 "BUFFER40,Buffer 40 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0xA4++0x03
|
|
line.long 0x00 "BUFFER41,Buffer 41 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0xA8++0x03
|
|
line.long 0x00 "BUFFER42,Buffer 42 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0xAC++0x03
|
|
line.long 0x00 "BUFFER43,Buffer 43 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0xB0++0x03
|
|
line.long 0x00 "BUFFER44,Buffer 44 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0xB4++0x03
|
|
line.long 0x00 "BUFFER45,Buffer 45 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0xB8++0x03
|
|
line.long 0x00 "BUFFER46,Buffer 46 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0xBC++0x03
|
|
line.long 0x00 "BUFFER47,Buffer 47 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0xC0++0x03
|
|
line.long 0x00 "BUFFER48,Buffer 48 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0xC4++0x03
|
|
line.long 0x00 "BUFFER49,Buffer 49 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0xC8++0x03
|
|
line.long 0x00 "BUFFER50,Buffer 50 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0xCC++0x03
|
|
line.long 0x00 "BUFFER51,Buffer 51 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0xD0++0x03
|
|
line.long 0x00 "BUFFER52,Buffer 52 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0xD4++0x03
|
|
line.long 0x00 "BUFFER53,Buffer 53 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0xD8++0x03
|
|
line.long 0x00 "BUFFER54,Buffer 54 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0xDC++0x03
|
|
line.long 0x00 "BUFFER55,Buffer 55 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0xE0++0x03
|
|
line.long 0x00 "BUFFER56,Buffer 56 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0xE4++0x03
|
|
line.long 0x00 "BUFFER57,Buffer 57 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0xE8++0x03
|
|
line.long 0x00 "BUFFER58,Buffer 58 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0xEC++0x03
|
|
line.long 0x00 "BUFFER59,Buffer 59 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0xF0++0x03
|
|
line.long 0x00 "BUFFER60,Buffer 60 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0xF4++0x03
|
|
line.long 0x00 "BUFFER61,Buffer 61 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0xF8++0x03
|
|
line.long 0x00 "BUFFER62,Buffer 62 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0xFC++0x03
|
|
line.long 0x00 "BUFFER63,Buffer 63 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x100++0x03
|
|
line.long 0x00 "BUFFER64,Buffer 64 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x104++0x03
|
|
line.long 0x00 "BUFFER65,Buffer 65 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x108++0x03
|
|
line.long 0x00 "BUFFER66,Buffer 66 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x10C++0x03
|
|
line.long 0x00 "BUFFER67,Buffer 67 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x110++0x03
|
|
line.long 0x00 "BUFFER68,Buffer 68 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x114++0x03
|
|
line.long 0x00 "BUFFER69,Buffer 69 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x118++0x03
|
|
line.long 0x00 "BUFFER70,Buffer 70 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x11C++0x03
|
|
line.long 0x00 "BUFFER71,Buffer 71 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x120++0x03
|
|
line.long 0x00 "BUFFER72,Buffer 72 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x124++0x03
|
|
line.long 0x00 "BUFFER73,Buffer 73 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x128++0x03
|
|
line.long 0x00 "BUFFER74,Buffer 74 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x12C++0x03
|
|
line.long 0x00 "BUFFER75,Buffer 75 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x130++0x03
|
|
line.long 0x00 "BUFFER76,Buffer 76 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x134++0x03
|
|
line.long 0x00 "BUFFER77,Buffer 77 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x138++0x03
|
|
line.long 0x00 "BUFFER78,Buffer 78 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x13C++0x03
|
|
line.long 0x00 "BUFFER79,Buffer 79 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x140++0x03
|
|
line.long 0x00 "BUFFER80,Buffer 80 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x144++0x03
|
|
line.long 0x00 "BUFFER81,Buffer 81 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x148++0x03
|
|
line.long 0x00 "BUFFER82,Buffer 82 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x14C++0x03
|
|
line.long 0x00 "BUFFER83,Buffer 83 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x150++0x03
|
|
line.long 0x00 "BUFFER84,Buffer 84 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x154++0x03
|
|
line.long 0x00 "BUFFER85,Buffer 85 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x158++0x03
|
|
line.long 0x00 "BUFFER86,Buffer 86 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x15C++0x03
|
|
line.long 0x00 "BUFFER87,Buffer 87 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x160++0x03
|
|
line.long 0x00 "BUFFER88,Buffer 88 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x164++0x03
|
|
line.long 0x00 "BUFFER89,Buffer 89 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x168++0x03
|
|
line.long 0x00 "BUFFER90,Buffer 90 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x16C++0x03
|
|
line.long 0x00 "BUFFER91,Buffer 91 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x170++0x03
|
|
line.long 0x00 "BUFFER92,Buffer 92 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x174++0x03
|
|
line.long 0x00 "BUFFER93,Buffer 93 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x178++0x03
|
|
line.long 0x00 "BUFFER94,Buffer 94 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x17C++0x03
|
|
line.long 0x00 "BUFFER95,Buffer 95 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x180++0x03
|
|
line.long 0x00 "BUFFER96,Buffer 96 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x184++0x03
|
|
line.long 0x00 "BUFFER97,Buffer 97 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x188++0x03
|
|
line.long 0x00 "BUFFER98,Buffer 98 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x18C++0x03
|
|
line.long 0x00 "BUFFER99,Buffer 99 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x190++0x03
|
|
line.long 0x00 "BUFFER100,Buffer 100 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x194++0x03
|
|
line.long 0x00 "BUFFER101,Buffer 101 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x198++0x03
|
|
line.long 0x00 "BUFFER102,Buffer 102 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x19C++0x03
|
|
line.long 0x00 "BUFFER103,Buffer 103 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x1A0++0x03
|
|
line.long 0x00 "BUFFER104,Buffer 104 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x1A4++0x03
|
|
line.long 0x00 "BUFFER105,Buffer 105 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x1A8++0x03
|
|
line.long 0x00 "BUFFER106,Buffer 106 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x1AC++0x03
|
|
line.long 0x00 "BUFFER107,Buffer 107 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x1B0++0x03
|
|
line.long 0x00 "BUFFER108,Buffer 108 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x1B4++0x03
|
|
line.long 0x00 "BUFFER109,Buffer 109 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x1B8++0x03
|
|
line.long 0x00 "BUFFER110,Buffer 110 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x1BC++0x03
|
|
line.long 0x00 "BUFFER111,Buffer 111 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x1C0++0x03
|
|
line.long 0x00 "BUFFER112,Buffer 112 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x1C4++0x03
|
|
line.long 0x00 "BUFFER113,Buffer 113 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x1C8++0x03
|
|
line.long 0x00 "BUFFER114,Buffer 114 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x1CC++0x03
|
|
line.long 0x00 "BUFFER115,Buffer 115 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x1D0++0x03
|
|
line.long 0x00 "BUFFER116,Buffer 116 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x1D4++0x03
|
|
line.long 0x00 "BUFFER117,Buffer 117 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x1D8++0x03
|
|
line.long 0x00 "BUFFER118,Buffer 118 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x1DC++0x03
|
|
line.long 0x00 "BUFFER119,Buffer 119 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x1E0++0x03
|
|
line.long 0x00 "BUFFER120,Buffer 120 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x1E4++0x03
|
|
line.long 0x00 "BUFFER121,Buffer 121 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x1E8++0x03
|
|
line.long 0x00 "BUFFER122,Buffer 122 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x1EC++0x03
|
|
line.long 0x00 "BUFFER123,Buffer 123 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x1F0++0x03
|
|
line.long 0x00 "BUFFER124,Buffer 124 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x1F4++0x03
|
|
line.long 0x00 "BUFFER125,Buffer 125 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x1F8++0x03
|
|
line.long 0x00 "BUFFER126,Buffer 126 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x1FC++0x03
|
|
line.long 0x00 "BUFFER127,Buffer 127 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
tree.end
|
|
tree "Receive Buffers"
|
|
hgroup.long (0x0+0x200)++0x03
|
|
hide.long 0x00 "BUFFER0,Buffer 0 Register"
|
|
in
|
|
hgroup.long (0x4+0x200)++0x03
|
|
hide.long 0x00 "BUFFER1,Buffer 1 Register"
|
|
in
|
|
hgroup.long (0x8+0x200)++0x03
|
|
hide.long 0x00 "BUFFER2,Buffer 2 Register"
|
|
in
|
|
hgroup.long (0xC+0x200)++0x03
|
|
hide.long 0x00 "BUFFER3,Buffer 3 Register"
|
|
in
|
|
hgroup.long (0x10+0x200)++0x03
|
|
hide.long 0x00 "BUFFER4,Buffer 4 Register"
|
|
in
|
|
hgroup.long (0x14+0x200)++0x03
|
|
hide.long 0x00 "BUFFER5,Buffer 5 Register"
|
|
in
|
|
hgroup.long (0x18+0x200)++0x03
|
|
hide.long 0x00 "BUFFER6,Buffer 6 Register"
|
|
in
|
|
hgroup.long (0x1C+0x200)++0x03
|
|
hide.long 0x00 "BUFFER7,Buffer 7 Register"
|
|
in
|
|
hgroup.long (0x20+0x200)++0x03
|
|
hide.long 0x00 "BUFFER8,Buffer 8 Register"
|
|
in
|
|
hgroup.long (0x24+0x200)++0x03
|
|
hide.long 0x00 "BUFFER9,Buffer 9 Register"
|
|
in
|
|
hgroup.long (0x28+0x200)++0x03
|
|
hide.long 0x00 "BUFFER10,Buffer 10 Register"
|
|
in
|
|
hgroup.long (0x2C+0x200)++0x03
|
|
hide.long 0x00 "BUFFER11,Buffer 11 Register"
|
|
in
|
|
hgroup.long (0x30+0x200)++0x03
|
|
hide.long 0x00 "BUFFER12,Buffer 12 Register"
|
|
in
|
|
hgroup.long (0x34+0x200)++0x03
|
|
hide.long 0x00 "BUFFER13,Buffer 13 Register"
|
|
in
|
|
hgroup.long (0x38+0x200)++0x03
|
|
hide.long 0x00 "BUFFER14,Buffer 14 Register"
|
|
in
|
|
hgroup.long (0x3C+0x200)++0x03
|
|
hide.long 0x00 "BUFFER15,Buffer 15 Register"
|
|
in
|
|
hgroup.long (0x40+0x200)++0x03
|
|
hide.long 0x00 "BUFFER16,Buffer 16 Register"
|
|
in
|
|
hgroup.long (0x44+0x200)++0x03
|
|
hide.long 0x00 "BUFFER17,Buffer 17 Register"
|
|
in
|
|
hgroup.long (0x48+0x200)++0x03
|
|
hide.long 0x00 "BUFFER18,Buffer 18 Register"
|
|
in
|
|
hgroup.long (0x4C+0x200)++0x03
|
|
hide.long 0x00 "BUFFER19,Buffer 19 Register"
|
|
in
|
|
hgroup.long (0x50+0x200)++0x03
|
|
hide.long 0x00 "BUFFER20,Buffer 20 Register"
|
|
in
|
|
hgroup.long (0x54+0x200)++0x03
|
|
hide.long 0x00 "BUFFER21,Buffer 21 Register"
|
|
in
|
|
hgroup.long (0x58+0x200)++0x03
|
|
hide.long 0x00 "BUFFER22,Buffer 22 Register"
|
|
in
|
|
hgroup.long (0x5C+0x200)++0x03
|
|
hide.long 0x00 "BUFFER23,Buffer 23 Register"
|
|
in
|
|
hgroup.long (0x60+0x200)++0x03
|
|
hide.long 0x00 "BUFFER24,Buffer 24 Register"
|
|
in
|
|
hgroup.long (0x64+0x200)++0x03
|
|
hide.long 0x00 "BUFFER25,Buffer 25 Register"
|
|
in
|
|
hgroup.long (0x68+0x200)++0x03
|
|
hide.long 0x00 "BUFFER26,Buffer 26 Register"
|
|
in
|
|
hgroup.long (0x6C+0x200)++0x03
|
|
hide.long 0x00 "BUFFER27,Buffer 27 Register"
|
|
in
|
|
hgroup.long (0x70+0x200)++0x03
|
|
hide.long 0x00 "BUFFER28,Buffer 28 Register"
|
|
in
|
|
hgroup.long (0x74+0x200)++0x03
|
|
hide.long 0x00 "BUFFER29,Buffer 29 Register"
|
|
in
|
|
hgroup.long (0x78+0x200)++0x03
|
|
hide.long 0x00 "BUFFER30,Buffer 30 Register"
|
|
in
|
|
hgroup.long (0x7C+0x200)++0x03
|
|
hide.long 0x00 "BUFFER31,Buffer 31 Register"
|
|
in
|
|
hgroup.long (0x80+0x200)++0x03
|
|
hide.long 0x00 "BUFFER32,Buffer 32 Register"
|
|
in
|
|
hgroup.long (0x84+0x200)++0x03
|
|
hide.long 0x00 "BUFFER33,Buffer 33 Register"
|
|
in
|
|
hgroup.long (0x88+0x200)++0x03
|
|
hide.long 0x00 "BUFFER34,Buffer 34 Register"
|
|
in
|
|
hgroup.long (0x8C+0x200)++0x03
|
|
hide.long 0x00 "BUFFER35,Buffer 35 Register"
|
|
in
|
|
hgroup.long (0x90+0x200)++0x03
|
|
hide.long 0x00 "BUFFER36,Buffer 36 Register"
|
|
in
|
|
hgroup.long (0x94+0x200)++0x03
|
|
hide.long 0x00 "BUFFER37,Buffer 37 Register"
|
|
in
|
|
hgroup.long (0x98+0x200)++0x03
|
|
hide.long 0x00 "BUFFER38,Buffer 38 Register"
|
|
in
|
|
hgroup.long (0x9C+0x200)++0x03
|
|
hide.long 0x00 "BUFFER39,Buffer 39 Register"
|
|
in
|
|
hgroup.long (0xA0+0x200)++0x03
|
|
hide.long 0x00 "BUFFER40,Buffer 40 Register"
|
|
in
|
|
hgroup.long (0xA4+0x200)++0x03
|
|
hide.long 0x00 "BUFFER41,Buffer 41 Register"
|
|
in
|
|
hgroup.long (0xA8+0x200)++0x03
|
|
hide.long 0x00 "BUFFER42,Buffer 42 Register"
|
|
in
|
|
hgroup.long (0xAC+0x200)++0x03
|
|
hide.long 0x00 "BUFFER43,Buffer 43 Register"
|
|
in
|
|
hgroup.long (0xB0+0x200)++0x03
|
|
hide.long 0x00 "BUFFER44,Buffer 44 Register"
|
|
in
|
|
hgroup.long (0xB4+0x200)++0x03
|
|
hide.long 0x00 "BUFFER45,Buffer 45 Register"
|
|
in
|
|
hgroup.long (0xB8+0x200)++0x03
|
|
hide.long 0x00 "BUFFER46,Buffer 46 Register"
|
|
in
|
|
hgroup.long (0xBC+0x200)++0x03
|
|
hide.long 0x00 "BUFFER47,Buffer 47 Register"
|
|
in
|
|
hgroup.long (0xC0+0x200)++0x03
|
|
hide.long 0x00 "BUFFER48,Buffer 48 Register"
|
|
in
|
|
hgroup.long (0xC4+0x200)++0x03
|
|
hide.long 0x00 "BUFFER49,Buffer 49 Register"
|
|
in
|
|
hgroup.long (0xC8+0x200)++0x03
|
|
hide.long 0x00 "BUFFER50,Buffer 50 Register"
|
|
in
|
|
hgroup.long (0xCC+0x200)++0x03
|
|
hide.long 0x00 "BUFFER51,Buffer 51 Register"
|
|
in
|
|
hgroup.long (0xD0+0x200)++0x03
|
|
hide.long 0x00 "BUFFER52,Buffer 52 Register"
|
|
in
|
|
hgroup.long (0xD4+0x200)++0x03
|
|
hide.long 0x00 "BUFFER53,Buffer 53 Register"
|
|
in
|
|
hgroup.long (0xD8+0x200)++0x03
|
|
hide.long 0x00 "BUFFER54,Buffer 54 Register"
|
|
in
|
|
hgroup.long (0xDC+0x200)++0x03
|
|
hide.long 0x00 "BUFFER55,Buffer 55 Register"
|
|
in
|
|
hgroup.long (0xE0+0x200)++0x03
|
|
hide.long 0x00 "BUFFER56,Buffer 56 Register"
|
|
in
|
|
hgroup.long (0xE4+0x200)++0x03
|
|
hide.long 0x00 "BUFFER57,Buffer 57 Register"
|
|
in
|
|
hgroup.long (0xE8+0x200)++0x03
|
|
hide.long 0x00 "BUFFER58,Buffer 58 Register"
|
|
in
|
|
hgroup.long (0xEC+0x200)++0x03
|
|
hide.long 0x00 "BUFFER59,Buffer 59 Register"
|
|
in
|
|
hgroup.long (0xF0+0x200)++0x03
|
|
hide.long 0x00 "BUFFER60,Buffer 60 Register"
|
|
in
|
|
hgroup.long (0xF4+0x200)++0x03
|
|
hide.long 0x00 "BUFFER61,Buffer 61 Register"
|
|
in
|
|
hgroup.long (0xF8+0x200)++0x03
|
|
hide.long 0x00 "BUFFER62,Buffer 62 Register"
|
|
in
|
|
hgroup.long (0xFC+0x200)++0x03
|
|
hide.long 0x00 "BUFFER63,Buffer 63 Register"
|
|
in
|
|
hgroup.long (0x100+0x200)++0x03
|
|
hide.long 0x00 "BUFFER64,Buffer 64 Register"
|
|
in
|
|
hgroup.long (0x104+0x200)++0x03
|
|
hide.long 0x00 "BUFFER65,Buffer 65 Register"
|
|
in
|
|
hgroup.long (0x108+0x200)++0x03
|
|
hide.long 0x00 "BUFFER66,Buffer 66 Register"
|
|
in
|
|
hgroup.long (0x10C+0x200)++0x03
|
|
hide.long 0x00 "BUFFER67,Buffer 67 Register"
|
|
in
|
|
hgroup.long (0x110+0x200)++0x03
|
|
hide.long 0x00 "BUFFER68,Buffer 68 Register"
|
|
in
|
|
hgroup.long (0x114+0x200)++0x03
|
|
hide.long 0x00 "BUFFER69,Buffer 69 Register"
|
|
in
|
|
hgroup.long (0x118+0x200)++0x03
|
|
hide.long 0x00 "BUFFER70,Buffer 70 Register"
|
|
in
|
|
hgroup.long (0x11C+0x200)++0x03
|
|
hide.long 0x00 "BUFFER71,Buffer 71 Register"
|
|
in
|
|
hgroup.long (0x120+0x200)++0x03
|
|
hide.long 0x00 "BUFFER72,Buffer 72 Register"
|
|
in
|
|
hgroup.long (0x124+0x200)++0x03
|
|
hide.long 0x00 "BUFFER73,Buffer 73 Register"
|
|
in
|
|
hgroup.long (0x128+0x200)++0x03
|
|
hide.long 0x00 "BUFFER74,Buffer 74 Register"
|
|
in
|
|
hgroup.long (0x12C+0x200)++0x03
|
|
hide.long 0x00 "BUFFER75,Buffer 75 Register"
|
|
in
|
|
hgroup.long (0x130+0x200)++0x03
|
|
hide.long 0x00 "BUFFER76,Buffer 76 Register"
|
|
in
|
|
hgroup.long (0x134+0x200)++0x03
|
|
hide.long 0x00 "BUFFER77,Buffer 77 Register"
|
|
in
|
|
hgroup.long (0x138+0x200)++0x03
|
|
hide.long 0x00 "BUFFER78,Buffer 78 Register"
|
|
in
|
|
hgroup.long (0x13C+0x200)++0x03
|
|
hide.long 0x00 "BUFFER79,Buffer 79 Register"
|
|
in
|
|
hgroup.long (0x140+0x200)++0x03
|
|
hide.long 0x00 "BUFFER80,Buffer 80 Register"
|
|
in
|
|
hgroup.long (0x144+0x200)++0x03
|
|
hide.long 0x00 "BUFFER81,Buffer 81 Register"
|
|
in
|
|
hgroup.long (0x148+0x200)++0x03
|
|
hide.long 0x00 "BUFFER82,Buffer 82 Register"
|
|
in
|
|
hgroup.long (0x14C+0x200)++0x03
|
|
hide.long 0x00 "BUFFER83,Buffer 83 Register"
|
|
in
|
|
hgroup.long (0x150+0x200)++0x03
|
|
hide.long 0x00 "BUFFER84,Buffer 84 Register"
|
|
in
|
|
hgroup.long (0x154+0x200)++0x03
|
|
hide.long 0x00 "BUFFER85,Buffer 85 Register"
|
|
in
|
|
hgroup.long (0x158+0x200)++0x03
|
|
hide.long 0x00 "BUFFER86,Buffer 86 Register"
|
|
in
|
|
hgroup.long (0x15C+0x200)++0x03
|
|
hide.long 0x00 "BUFFER87,Buffer 87 Register"
|
|
in
|
|
hgroup.long (0x160+0x200)++0x03
|
|
hide.long 0x00 "BUFFER88,Buffer 88 Register"
|
|
in
|
|
hgroup.long (0x164+0x200)++0x03
|
|
hide.long 0x00 "BUFFER89,Buffer 89 Register"
|
|
in
|
|
hgroup.long (0x168+0x200)++0x03
|
|
hide.long 0x00 "BUFFER90,Buffer 90 Register"
|
|
in
|
|
hgroup.long (0x16C+0x200)++0x03
|
|
hide.long 0x00 "BUFFER91,Buffer 91 Register"
|
|
in
|
|
hgroup.long (0x170+0x200)++0x03
|
|
hide.long 0x00 "BUFFER92,Buffer 92 Register"
|
|
in
|
|
hgroup.long (0x174+0x200)++0x03
|
|
hide.long 0x00 "BUFFER93,Buffer 93 Register"
|
|
in
|
|
hgroup.long (0x178+0x200)++0x03
|
|
hide.long 0x00 "BUFFER94,Buffer 94 Register"
|
|
in
|
|
hgroup.long (0x17C+0x200)++0x03
|
|
hide.long 0x00 "BUFFER95,Buffer 95 Register"
|
|
in
|
|
hgroup.long (0x180+0x200)++0x03
|
|
hide.long 0x00 "BUFFER96,Buffer 96 Register"
|
|
in
|
|
hgroup.long (0x184+0x200)++0x03
|
|
hide.long 0x00 "BUFFER97,Buffer 97 Register"
|
|
in
|
|
hgroup.long (0x188+0x200)++0x03
|
|
hide.long 0x00 "BUFFER98,Buffer 98 Register"
|
|
in
|
|
hgroup.long (0x18C+0x200)++0x03
|
|
hide.long 0x00 "BUFFER99,Buffer 99 Register"
|
|
in
|
|
hgroup.long (0x190+0x200)++0x03
|
|
hide.long 0x00 "BUFFER100,Buffer 100 Register"
|
|
in
|
|
hgroup.long (0x194+0x200)++0x03
|
|
hide.long 0x00 "BUFFER101,Buffer 101 Register"
|
|
in
|
|
hgroup.long (0x198+0x200)++0x03
|
|
hide.long 0x00 "BUFFER102,Buffer 102 Register"
|
|
in
|
|
hgroup.long (0x19C+0x200)++0x03
|
|
hide.long 0x00 "BUFFER103,Buffer 103 Register"
|
|
in
|
|
hgroup.long (0x1A0+0x200)++0x03
|
|
hide.long 0x00 "BUFFER104,Buffer 104 Register"
|
|
in
|
|
hgroup.long (0x1A4+0x200)++0x03
|
|
hide.long 0x00 "BUFFER105,Buffer 105 Register"
|
|
in
|
|
hgroup.long (0x1A8+0x200)++0x03
|
|
hide.long 0x00 "BUFFER106,Buffer 106 Register"
|
|
in
|
|
hgroup.long (0x1AC+0x200)++0x03
|
|
hide.long 0x00 "BUFFER107,Buffer 107 Register"
|
|
in
|
|
hgroup.long (0x1B0+0x200)++0x03
|
|
hide.long 0x00 "BUFFER108,Buffer 108 Register"
|
|
in
|
|
hgroup.long (0x1B4+0x200)++0x03
|
|
hide.long 0x00 "BUFFER109,Buffer 109 Register"
|
|
in
|
|
hgroup.long (0x1B8+0x200)++0x03
|
|
hide.long 0x00 "BUFFER110,Buffer 110 Register"
|
|
in
|
|
hgroup.long (0x1BC+0x200)++0x03
|
|
hide.long 0x00 "BUFFER111,Buffer 111 Register"
|
|
in
|
|
hgroup.long (0x1C0+0x200)++0x03
|
|
hide.long 0x00 "BUFFER112,Buffer 112 Register"
|
|
in
|
|
hgroup.long (0x1C4+0x200)++0x03
|
|
hide.long 0x00 "BUFFER113,Buffer 113 Register"
|
|
in
|
|
hgroup.long (0x1C8+0x200)++0x03
|
|
hide.long 0x00 "BUFFER114,Buffer 114 Register"
|
|
in
|
|
hgroup.long (0x1CC+0x200)++0x03
|
|
hide.long 0x00 "BUFFER115,Buffer 115 Register"
|
|
in
|
|
hgroup.long (0x1D0+0x200)++0x03
|
|
hide.long 0x00 "BUFFER116,Buffer 116 Register"
|
|
in
|
|
hgroup.long (0x1D4+0x200)++0x03
|
|
hide.long 0x00 "BUFFER117,Buffer 117 Register"
|
|
in
|
|
hgroup.long (0x1D8+0x200)++0x03
|
|
hide.long 0x00 "BUFFER118,Buffer 118 Register"
|
|
in
|
|
hgroup.long (0x1DC+0x200)++0x03
|
|
hide.long 0x00 "BUFFER119,Buffer 119 Register"
|
|
in
|
|
hgroup.long (0x1E0+0x200)++0x03
|
|
hide.long 0x00 "BUFFER120,Buffer 120 Register"
|
|
in
|
|
hgroup.long (0x1E4+0x200)++0x03
|
|
hide.long 0x00 "BUFFER121,Buffer 121 Register"
|
|
in
|
|
hgroup.long (0x1E8+0x200)++0x03
|
|
hide.long 0x00 "BUFFER122,Buffer 122 Register"
|
|
in
|
|
hgroup.long (0x1EC+0x200)++0x03
|
|
hide.long 0x00 "BUFFER123,Buffer 123 Register"
|
|
in
|
|
hgroup.long (0x1F0+0x200)++0x03
|
|
hide.long 0x00 "BUFFER124,Buffer 124 Register"
|
|
in
|
|
hgroup.long (0x1F4+0x200)++0x03
|
|
hide.long 0x00 "BUFFER125,Buffer 125 Register"
|
|
in
|
|
hgroup.long (0x1F8+0x200)++0x03
|
|
hide.long 0x00 "BUFFER126,Buffer 126 Register"
|
|
in
|
|
hgroup.long (0x1FC+0x200)++0x03
|
|
hide.long 0x00 "BUFFER127,Buffer 127 Register"
|
|
in
|
|
tree.end
|
|
endif
|
|
sif cpuis("TMS570LS0232")||cpuis("TMS570LS0714*")||cpuis("TMS570LS0914*")
|
|
endian.le
|
|
endif
|
|
width 0xB
|
|
tree.end
|
|
tree.end
|
|
elif cpuis("TMS570LS0232")
|
|
tree.open "MibSPI (Multi-Buffered Serial Peripheral Interface Module)"
|
|
tree "MibSPI1"
|
|
base ad:0xFFF7F400
|
|
width 17.
|
|
sif cpuis("TMS570LS0232")||cpuis("TMS570LS0714*")||cpuis("TMS570LS0914*")
|
|
endian.be
|
|
endif
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "SPIGCR0,SPI Global Control Register 0"
|
|
bitfld.long 0x00 0. " NRESET ,Reset bit for the module" "No reset,Reset"
|
|
group.long 0x04++0x0F
|
|
line.long 0x00 "SPIGCR1,SPI Global Control Register 1"
|
|
bitfld.long 0x00 24. " SPIEN ,SPI enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " LOOPBACK ,Internal loop-back test mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " POWERDOWN ,SPI state machine enters a power-down state" "No power-down,Power-down"
|
|
newline
|
|
bitfld.long 0x00 1. " CLKMOD ,Clock mode" "External,Internally"
|
|
bitfld.long 0x00 0. " MASTER ,SPISIMO/SPISOMI pin direction determination" "Input/output,Output/input"
|
|
line.long 0x04 "SPIINT0,SPI Interrupt Register"
|
|
bitfld.long 0x04 24. " ENABLEHIGHZ ,SPIENA pin high-impedance enable" "Inactive,Active"
|
|
bitfld.long 0x04 16. " DMAREQEN ,DMA request enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 9. " TXINTENA ,TX interrupt flag enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x04 8. " RXINTENA ,RX interrupt flag enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 6. " RXOVRNINTENA ,Overrun interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 4. " BITERRENA ,Enables interrupt on bit error" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x04 3. " DESYNCENA ,Enables interrupt on desynchronized slave" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " PARERRENA ,Enables interrupt-on-parity-error" "Disabled,Enabled"
|
|
bitfld.long 0x04 1. " TIMEOUTENA ,Enables interrupt on ENA signal time-out" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x04 0. " DLENERRENA ,Data length error interrupt enable" "Disabled,Enabled"
|
|
line.long 0x08 "SPILVL,SPI Interrupt Level Register"
|
|
bitfld.long 0x08 9. " TXINTLVL ,Transmit interrupt level" "INT0,INT1"
|
|
bitfld.long 0x08 8. " RXINTLVL ,Receive interrupt level" "INT0,INT1"
|
|
sif !cpuis("TMS570LS0232")
|
|
bitfld.long 0x08 6. " RXOVRNINTLVL ,Receive overrun interrupt level" "INT0,INT1"
|
|
endif
|
|
newline
|
|
bitfld.long 0x08 4. " BITERRLVL ,Bit error interrupt level" "INT0,INT1"
|
|
bitfld.long 0x08 3. " DESYNCLVL ,Desynchronized slave interrupt level (master mode only)" "INT0,INT1"
|
|
bitfld.long 0x08 2. " PARERRLVL ,Parity error interrupt level" "INT0,INT1"
|
|
newline
|
|
bitfld.long 0x08 1. " TIMEOUTLVL ,SPIENA pin time-out interrupt level" "INT0,INT1"
|
|
bitfld.long 0x08 0. " DLENERRLVL ,Data length error interrupt level (line) select" "INT0,INT1"
|
|
line.long 0x0C "SPIFLG,SPI Flag Register"
|
|
bitfld.long 0x0C 24. " BUFINITACTIVE ,Indicates the status of multi-buffer initialization process" "Completed,Not completed"
|
|
bitfld.long 0x0C 9. " TXINTFLG ,Transmitter-empty interrupt flag" "No interrupt,Interrupt"
|
|
eventfld.long 0x0C 8. " RXINTFLG ,Receiver-full interrupt flag" "No interrupt,Interrupt"
|
|
newline
|
|
eventfld.long 0x0C 6. " RXOVRNINTFLG ,Overrun interrupt enable" "Disabled,Enabled"
|
|
eventfld.long 0x0C 4. " BITERRFLG ,Enables interrupt on bit error" "Disabled,Enabled"
|
|
eventfld.long 0x0C 3. " DESYNCFLG ,Enables interrupt on desynchronized slave" "No interrupt,Interrupt"
|
|
newline
|
|
eventfld.long 0x0C 2. " PARITYERRFLG ,Enables interrupt-on-parity-error" "No error,Error"
|
|
eventfld.long 0x0C 1. " TIMEOUTFLG ,Enables interrupt on ENA signal time-out" "No interrupt,Interrupt"
|
|
eventfld.long 0x0C 0. " DLENERRFLG ,Data length error interrupt enable" "No interrupt,Interrupt"
|
|
group.long 0x14++0x23
|
|
line.long 0x00 "SPIPC0,SPI Pin Control Register 0"
|
|
sif !cpuis("TMS570LS0232")&&!cpuis("TMS570LS0332")&&!cpuis("TMS570LS0432")
|
|
bitfld.long 0x00 31. " SOMIFUN7 ,SPISOMI[7] pin function" "GIO,SPI"
|
|
bitfld.long 0x00 30. " SOMIFUN6 ,SPISOMI[6] pin function" "GIO,SPI"
|
|
bitfld.long 0x00 29. " SOMIFUN5 ,SPISOMI[5] pin function" "GIO,SPI"
|
|
newline
|
|
bitfld.long 0x00 28. " SOMIFUN4 ,SPISOMI[4] pin function" "GIO,SPI"
|
|
bitfld.long 0x00 27. " SOMIFUN3 ,SPISOMI[3] pin function" "GIO,SPI"
|
|
bitfld.long 0x00 26. " SOMIFUN2 ,SPISOMI[2] pin function" "GIO,SPI"
|
|
newline
|
|
bitfld.long 0x00 25. " SOMIFUN1 ,SPISOMI[1] pin function" "GIO,SPI"
|
|
bitfld.long 0x00 24. " SOMIFUN0 ,SPISOMI[0] pin function (mirror of bit 11)" "GIO,SPI"
|
|
bitfld.long 0x00 23. " SIMOFUN7 ,SPISIMO[7] pin function" "GIO,SPI"
|
|
newline
|
|
bitfld.long 0x00 22. " SIMOFUN6 ,SPISIMO[6] pin function" "GIO,SPI"
|
|
bitfld.long 0x00 21. " SIMOFUN5 ,SPISIMO[5] pin function" "GIO,SPI"
|
|
bitfld.long 0x00 20. " SIMOFUN4 ,SPISIMO[4] pin function" "GIO,SPI"
|
|
newline
|
|
bitfld.long 0x00 19. " SIMOFUN3 ,SPISIMO[3] pin function" "GIO,SPI"
|
|
bitfld.long 0x00 18. " SIMOFUN2 ,SPISIMO[2] pin function" "GIO,SPI"
|
|
bitfld.long 0x00 17. " SIMOFUN1 ,SPISIMO[1] pin function" "GIO,SPI"
|
|
newline
|
|
bitfld.long 0x00 16. " SIMOFUN0 ,SPISIMO[0] pin function (mirror of bit 10)" "GIO,SPI"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 11. " SOMIFUN0 ,SPISOMI[0] pin function" "GIO,SPI"
|
|
bitfld.long 0x00 10. " SIMOFUN0 ,SPISIMO[0] pin function" "GIO,SPI"
|
|
newline
|
|
bitfld.long 0x00 9. " CLKFUN ,SPI clock function" "GIO,SPI"
|
|
bitfld.long 0x00 8. " ENAFUN ,SPIENA function" "GIO,SPI"
|
|
bitfld.long 0x00 7. " SCSFUN7 ,SPISCS7 function 7" "GIO,SPI"
|
|
newline
|
|
bitfld.long 0x00 6. " SCSFUN6 ,SPISCS6 function 6" "GIO,SPI"
|
|
bitfld.long 0x00 5. " SCSFUN5 ,SPISCS5 function 5" "GIO,SPI"
|
|
bitfld.long 0x00 4. " SCSFUN4 ,SPISCS4 function 4" "GIO,SPI"
|
|
newline
|
|
bitfld.long 0x00 3. " SCSFUN3 ,SPISCS3 function 3" "GIO,SPI"
|
|
bitfld.long 0x00 2. " SCSFUN2 ,SPISCS2 function 2" "GIO,SPI"
|
|
bitfld.long 0x00 1. " SCSFUN1 ,SPISCS1 function 1" "GIO,SPI"
|
|
newline
|
|
bitfld.long 0x00 0. " SCSFUN0 ,SPISCS0 function 0" "GIO,SPI"
|
|
line.long 0x04 "SPIPC1,SPI Pin Control Register 1"
|
|
bitfld.long 0x04 31. " SOMIDIR7 ,SPISOMI[7] pin direction" "GIO,SPI"
|
|
bitfld.long 0x04 30. " SOMIDIR6 ,SPISOMI[6] pin direction" "GIO,SPI"
|
|
bitfld.long 0x04 29. " SOMIDIR5 ,SPISOMI[5] pin direction" "GIO,SPI"
|
|
newline
|
|
bitfld.long 0x04 28. " SOMIDIR4 ,SPISOMI[4] pin direction" "GIO,SPI"
|
|
bitfld.long 0x04 27. " SOMIDIR3 ,SPISOMI[3] pin direction" "GIO,SPI"
|
|
bitfld.long 0x04 26. " SOMIDIR2 ,SPISOMI[2] pin direction" "GIO,SPI"
|
|
newline
|
|
bitfld.long 0x04 25. " SOMIDIR1 ,SPISOMI[1] pin direction" "GIO,SPI"
|
|
bitfld.long 0x04 24. " SOMIDIR0 ,SPISOMI[0] pin direction (mirror of bit 11)" "GIO,SPI"
|
|
bitfld.long 0x04 23. " SIMODIR7 ,SPISIMO[7] pin direction" "GIO,SPI"
|
|
newline
|
|
bitfld.long 0x04 22. " SIMODIR6 ,SPISIMO[6] pin direction" "GIO,SPI"
|
|
bitfld.long 0x04 21. " SIMODIR5 ,SPISIMO[5] pin direction" "GIO,SPI"
|
|
bitfld.long 0x04 20. " SIMODIR4 ,SPISIMO[4] pin direction" "GIO,SPI"
|
|
newline
|
|
bitfld.long 0x04 19. " SIMODIR3 ,SPISIMO[3] pin direction" "GIO,SPI"
|
|
bitfld.long 0x04 18. " SIMODIR2 ,SPISIMO[2] pin direction" "GIO,SPI"
|
|
bitfld.long 0x04 17. " SIMODIR1 ,SPISIMO[1] pin direction" "GIO,SPI"
|
|
newline
|
|
bitfld.long 0x04 16. " SIMODIR0 ,SPISIMO[0] pin direction (mirror of bit 10)" "GIO,SPI"
|
|
bitfld.long 0x04 11. " SOMIDIR0 ,SPISOMI[0] pin direction" "GIO,SPI"
|
|
bitfld.long 0x04 10. " SIMODIR0 ,SPISIMO[0] pin direction" "GIO,SPI"
|
|
newline
|
|
bitfld.long 0x04 9. " CLKDIR ,SPI clock direction" "GIO,SPI"
|
|
bitfld.long 0x04 8. " ENADIR ,SPIENA direction" "GIO,SPI"
|
|
bitfld.long 0x04 7. " SCSDIR7 ,SPISCS7 direction 7" "GIO,SPI"
|
|
newline
|
|
bitfld.long 0x04 6. " SCSDIR6 ,SPISCS6 direction 6" "GIO,SPI"
|
|
bitfld.long 0x04 5. " SCSDIR5 ,SPISCS5 direction 5" "GIO,SPI"
|
|
bitfld.long 0x04 4. " SCSDIR4 ,SPISCS4 direction 4" "GIO,SPI"
|
|
newline
|
|
bitfld.long 0x04 3. " SCSDIR3 ,SPISCS3 direction 3" "GIO,SPI"
|
|
bitfld.long 0x04 2. " SCSDIR2 ,SPISCS2 direction 2" "GIO,SPI"
|
|
bitfld.long 0x04 1. " SCSDIR1 ,SPISCS1 direction 1" "GIO,SPI"
|
|
newline
|
|
bitfld.long 0x04 0. " SCSDIR0 ,SPISCS0 direction 0" "GIO,SPI"
|
|
line.long 0x08 "SPIPC2,SPI Pin Control Register 2"
|
|
bitfld.long 0x08 31. " SOMIDIN7 ,SPISOMI[7] data in" "0,1"
|
|
bitfld.long 0x08 30. " SOMIDIN6 ,SPISOMI[6] data in" "0,1"
|
|
bitfld.long 0x08 29. " SOMIDIN5 ,SPISOMI[5] data in" "0,1"
|
|
newline
|
|
bitfld.long 0x08 28. " SOMIDIN4 ,SPISOMI[4] data in" "0,1"
|
|
bitfld.long 0x08 27. " SOMIDIN3 ,SPISOMI[3] data in" "0,1"
|
|
bitfld.long 0x08 26. " SOMIDIN2 ,SPISOMI[2] data in" "0,1"
|
|
newline
|
|
bitfld.long 0x08 25. " SOMIDIN1 ,SPISOMI[1] data in" "0,1"
|
|
bitfld.long 0x08 24. " SOMIDIN0 ,SPISOMI[0] data in (mirror of bit 11)" "0,1"
|
|
bitfld.long 0x08 23. " SIMODIN7 ,SPISIMO[7] data in" "0,1"
|
|
newline
|
|
bitfld.long 0x08 22. " SIMODIN6 ,SPISIMO[6] data in" "0,1"
|
|
bitfld.long 0x08 21. " SIMODIN5 ,SPISIMO[5] data in" "0,1"
|
|
bitfld.long 0x08 20. " SIMODIN4 ,SPISIMO[4] data in" "0,1"
|
|
newline
|
|
bitfld.long 0x08 19. " SIMODIN3 ,SPISIMO[3] data in" "0,1"
|
|
bitfld.long 0x08 18. " SIMODIN2 ,SPISIMO[2] data in" "0,1"
|
|
bitfld.long 0x08 17. " SIMODIN1 ,SPISIMO[1] data in" "0,1"
|
|
newline
|
|
bitfld.long 0x08 16. " SIMODIN0 ,SPISIMO[0] data in (mirror of bit 10)" "0,1"
|
|
bitfld.long 0x08 11. " SOMIDIN0 ,SPISOMI[0] data in" "0,1"
|
|
bitfld.long 0x08 10. " SIMODIN0 ,SPISIMO[0] data in" "0,1"
|
|
newline
|
|
bitfld.long 0x08 9. " CLKDIN ,SPI clock data in" "0,1"
|
|
bitfld.long 0x08 8. " ENADIN ,SPIENA data in" "0,1"
|
|
bitfld.long 0x08 7. " SCSDIN7 ,SPISCS7 data in" "0,1"
|
|
newline
|
|
bitfld.long 0x08 6. " SCSDIN6 ,SPISCS6 data in" "0,1"
|
|
bitfld.long 0x08 5. " SCSDIN5 ,SPISCS5 data in" "0,1"
|
|
bitfld.long 0x08 4. " SCSDIN4 ,SPISCS4 data in" "0,1"
|
|
newline
|
|
bitfld.long 0x08 3. " SCSDIN3 ,SPISCS3 data in" "0,1"
|
|
bitfld.long 0x08 2. " SCSDIN2 ,SPISCS2 data in" "0,1"
|
|
bitfld.long 0x08 1. " SCSDIN1 ,SPISCS1 data in" "0,1"
|
|
newline
|
|
bitfld.long 0x08 0. " SCSDIN0 ,SPISCS0 direction 0" "0,1"
|
|
line.long 0x0C "SPIPC3,SPI Pin Control Register 3"
|
|
bitfld.long 0x0C 31. " SOMIDOUT7 ,SPISOMI[7] data out write" "0,1"
|
|
bitfld.long 0x0C 30. " SOMIDOUT6 ,SPISOMI[6] data out write" "0,1"
|
|
bitfld.long 0x0C 29. " SOMIDOUT5 ,SPISOMI[5] data out write" "0,1"
|
|
newline
|
|
bitfld.long 0x0C 28. " SOMIDOUT4 ,SPISOMI[4] data out write" "0,1"
|
|
bitfld.long 0x0C 27. " SOMIDOUT3 ,SPISOMI[3] data out write" "0,1"
|
|
bitfld.long 0x0C 26. " SOMIDOUT2 ,SPISOMI[2] data out write" "0,1"
|
|
newline
|
|
bitfld.long 0x0C 25. " SOMIDOUT1 ,SPISOMI[1] data out write" "0,1"
|
|
bitfld.long 0x0C 24. " SOMIDOUT0 ,SPISOMI[0] data out write (mirror of bit 11)" "0,1"
|
|
bitfld.long 0x0C 23. " SIMODOUT7 ,SPISIMO[7] data out write" "0,1"
|
|
newline
|
|
bitfld.long 0x0C 22. " SIMODOUT6 ,SPISIMO[6] data out write" "0,1"
|
|
bitfld.long 0x0C 21. " SIMODOUT5 ,SPISIMO[5] data out write" "0,1"
|
|
bitfld.long 0x0C 20. " SIMODOUT4 ,SPISIMO[4] data out write" "0,1"
|
|
newline
|
|
bitfld.long 0x0C 19. " SIMODOUT3 ,SPISIMO[3] data out write" "0,1"
|
|
bitfld.long 0x0C 18. " SIMODOUT2 ,SPISIMO[2] data out write" "0,1"
|
|
bitfld.long 0x0C 17. " SIMODOUT1 ,SPISIMO[1] data out write" "0,1"
|
|
newline
|
|
bitfld.long 0x0C 16. " SIMODOUT0 ,SPISIMO[0] data out write (mirror of bit 10)" "0,1"
|
|
bitfld.long 0x0C 11. " SOMIDOUT0 ,SPISOMI[0] data out write" "0,1"
|
|
bitfld.long 0x0C 10. " SIMODOUT0 ,SPISIMO[0] data out write" "0,1"
|
|
newline
|
|
bitfld.long 0x0C 9. " CLKDOUT ,SPI clock data out write" "0,1"
|
|
bitfld.long 0x0C 8. " ENADOUT ,SPIENA data out write" "0,1"
|
|
bitfld.long 0x0C 7. " SCSDOUT7 ,SPISCS7 data out write" "0,1"
|
|
newline
|
|
bitfld.long 0x0C 6. " SCSDOUT6 ,SPISCS6 data out write" "0,1"
|
|
bitfld.long 0x0C 5. " SCSDOUT5 ,SPISCS5 data out write" "0,1"
|
|
bitfld.long 0x0C 4. " SCSDOUT4 ,SPISCS4 data out write" "0,1"
|
|
newline
|
|
bitfld.long 0x0C 3. " SCSDOUT3 ,SPISCS3 data out write" "0,1"
|
|
bitfld.long 0x0C 2. " SCSDOUT2 ,SPISCS2 data out write" "0,1"
|
|
bitfld.long 0x0C 1. " SCSDOUT1 ,SPISCS1 data out write" "0,1"
|
|
newline
|
|
bitfld.long 0x0C 0. " SCSDOUT0 ,SPISCS0 data out write" "0,1"
|
|
line.long 0x10 "SPIPC4,SPI Pin Control Register 4"
|
|
bitfld.long 0x10 31. " SOMISET7 ,SPISOMI[7] data out set" "0,1"
|
|
bitfld.long 0x10 30. " SOMISET6 ,SPISOMI[6] data out set" "0,1"
|
|
bitfld.long 0x10 29. " SOMISET5 ,SPISOMI[5] data out set" "0,1"
|
|
newline
|
|
bitfld.long 0x10 28. " SOMISET4 ,SPISOMI[4] data out set" "0,1"
|
|
bitfld.long 0x10 27. " SOMISET3 ,SPISOMI[3] data out set" "0,1"
|
|
bitfld.long 0x10 26. " SOMISET2 ,SPISOMI[2] data out set" "0,1"
|
|
newline
|
|
bitfld.long 0x10 25. " SOMISET1 ,SPISOMI[1] data out set" "0,1"
|
|
bitfld.long 0x10 24. " SOMISET0 ,SPISOMI[0] data out set (mirror of bit 11)" "0,1"
|
|
bitfld.long 0x10 23. " SIMOSET7 ,SPISIMO[7] data out set" "0,1"
|
|
newline
|
|
bitfld.long 0x10 22. " SIMOSET6 ,SPISIMO[6] data out set" "0,1"
|
|
bitfld.long 0x10 21. " SIMOSET5 ,SPISIMO[5] data out set" "0,1"
|
|
bitfld.long 0x10 20. " SIMOSET4 ,SPISIMO[4] data out set" "0,1"
|
|
newline
|
|
bitfld.long 0x10 19. " SIMOSET3 ,SPISIMO[3] data out set" "0,1"
|
|
bitfld.long 0x10 18. " SIMOSET2 ,SPISIMO[2] data out set" "0,1"
|
|
bitfld.long 0x10 17. " SIMOSET1 ,SPISIMO[1] data out set" "0,1"
|
|
newline
|
|
bitfld.long 0x10 16. " SIMOSET0 ,SPISIMO[0] data out set (mirror of bit 10)" "0,1"
|
|
bitfld.long 0x10 11. " SOMISET0 ,SPISOMI[0] data out set" "0,1"
|
|
bitfld.long 0x10 10. " SIMOSET0 ,SPISIMO[0] data out set" "0,1"
|
|
newline
|
|
bitfld.long 0x10 9. " CLKSET ,SPI clock data out set" "0,1"
|
|
bitfld.long 0x10 8. " ENASET ,SPIENA data out set" "0,1"
|
|
bitfld.long 0x10 7. " SCSSET7 ,SPISCS7 data out set" "0,1"
|
|
newline
|
|
bitfld.long 0x10 6. " SCSSET6 ,SPISCS6 data out set" "0,1"
|
|
bitfld.long 0x10 5. " SCSSET5 ,SPISCS5 data out set" "0,1"
|
|
bitfld.long 0x10 4. " SCSSET4 ,SPISCS4 data out set" "0,1"
|
|
newline
|
|
bitfld.long 0x10 3. " SCSSET3 ,SPISCS3 data out set" "0,1"
|
|
bitfld.long 0x10 2. " SCSSET2 ,SPISCS2 data out set" "0,1"
|
|
bitfld.long 0x10 1. " SCSSET1 ,SPISCS1 data out set" "0,1"
|
|
newline
|
|
bitfld.long 0x10 0. " SCSSET0 ,SPISCS0 data out set" "0,1"
|
|
line.long 0x14 "SPIPC5,SPI Pin Control Register 5"
|
|
bitfld.long 0x14 31. " SOMICLR7 ,SPISOMI[7] data out clear" "0,1"
|
|
bitfld.long 0x14 30. " SOMICLR6 ,SPISOMI[6] data out clear" "0,1"
|
|
bitfld.long 0x14 29. " SOMICLR5 ,SPISOMI[5] data out clear" "0,1"
|
|
newline
|
|
bitfld.long 0x14 28. " SOMICLR4 ,SPISOMI[4] data out clear" "0,1"
|
|
bitfld.long 0x14 27. " SOMICLR3 ,SPISOMI[3] data out clear" "0,1"
|
|
bitfld.long 0x14 26. " SOMICLR2 ,SPISOMI[2] data out clear" "0,1"
|
|
newline
|
|
bitfld.long 0x14 25. " SOMICLR1 ,SPISOMI[1] data out clear" "0,1"
|
|
bitfld.long 0x14 24. " SOMICLR0 ,SPISOMI[0] data out clear (mirror of bit 11)" "0,1"
|
|
bitfld.long 0x14 23. " SIMOCLR7 ,SPISIMO[7] data out clear" "0,1"
|
|
newline
|
|
bitfld.long 0x14 22. " SIMOCLR6 ,SPISIMO[6] data out clear" "0,1"
|
|
bitfld.long 0x14 21. " SIMOCLR5 ,SPISIMO[5] data out clear" "0,1"
|
|
bitfld.long 0x14 20. " SIMOCLR4 ,SPISIMO[4] data out clear" "0,1"
|
|
newline
|
|
bitfld.long 0x14 19. " SIMOCLR3 ,SPISIMO[3] data out clear" "0,1"
|
|
bitfld.long 0x14 18. " SIMOCLR2 ,SPISIMO[2] data out clear" "0,1"
|
|
bitfld.long 0x14 17. " SIMOCLR1 ,SPISIMO[1] data out clear" "0,1"
|
|
newline
|
|
bitfld.long 0x14 16. " SIMOCLR0 ,SPISIMO[0] data out clear (mirror of bit 10)" "0,1"
|
|
bitfld.long 0x14 11. " SOMICLR0 ,SPISOMI[0] data out clear" "0,1"
|
|
bitfld.long 0x14 10. " SIMOCLR0 ,SPISIMO[0] data out clear" "0,1"
|
|
newline
|
|
bitfld.long 0x14 9. " CLKCLR ,SPI clock data out clear" "0,1"
|
|
bitfld.long 0x14 8. " ENACLR ,SPIENA data out clear" "0,1"
|
|
bitfld.long 0x14 7. " SCSCLR7 ,SPISCS7 data out clear" "0,1"
|
|
newline
|
|
bitfld.long 0x14 6. " SCSCLR6 ,SPISCS6 data out clear" "0,1"
|
|
bitfld.long 0x14 5. " SCSCLR5 ,SPISCS5 data out clear" "0,1"
|
|
bitfld.long 0x14 4. " SCSCLR4 ,SPISCS4 data out clear" "0,1"
|
|
newline
|
|
bitfld.long 0x14 3. " SCSCLR3 ,SPISCS3 data out clear" "0,1"
|
|
bitfld.long 0x14 2. " SCSCLR2 ,SPISCS2 data out clear" "0,1"
|
|
bitfld.long 0x14 1. " SCSCLR1 ,SPISCS1 data out clear" "0,1"
|
|
newline
|
|
bitfld.long 0x14 0. " SCSCLR0 ,SPISCS0 data out clear" "0,1"
|
|
line.long 0x18 "SPIPC6,SPI Pin Control Register 6"
|
|
bitfld.long 0x18 31. " SOMIPDR7 ,SPISOMI[7] open drain enable" "Disabled,Enabled"
|
|
bitfld.long 0x18 30. " SOMIPDR6 ,SPISOMI[6] open drain enable" "Disabled,Enabled"
|
|
bitfld.long 0x18 29. " SOMIPDR5 ,SPISOMI[5] open drain enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x18 28. " SOMIPDR4 ,SPISOMI[4] open drain enable" "Disabled,Enabled"
|
|
bitfld.long 0x18 27. " SOMIPDR3 ,SPISOMI[3] open drain enable" "Disabled,Enabled"
|
|
bitfld.long 0x18 26. " SOMIPDR2 ,SPISOMI[2] open drain enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x18 25. " SOMIPDR1 ,SPISOMI[1] open drain enable" "Disabled,Enabled"
|
|
bitfld.long 0x18 24. " SOMIPDR0 ,SPISOMI[0] open drain enable (mirror of bit 11)" "Disabled,Enabled"
|
|
bitfld.long 0x18 23. " SIMOPDR7 ,SPISIMO[7] open drain enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x18 22. " SIMOPDR6 ,SPISIMO[6] open drain enable" "Disabled,Enabled"
|
|
bitfld.long 0x18 21. " SIMOPDR5 ,SPISIMO[5] open drain enable" "Disabled,Enabled"
|
|
bitfld.long 0x18 20. " SIMOPDR4 ,SPISIMO[4] open drain enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x18 19. " SIMOPDR3 ,SPISIMO[3] open drain enable" "Disabled,Enabled"
|
|
bitfld.long 0x18 18. " SIMOPDR2 ,SPISIMO[2] open drain enable" "Disabled,Enabled"
|
|
bitfld.long 0x18 17. " SIMOPDR1 ,SPISIMO[1] open drain enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x18 16. " SIMOPDR0 ,SPISIMO[0] open drain enable (mirror of bit 10)" "Disabled,Enabled"
|
|
bitfld.long 0x18 11. " SOMIPDR0 ,SPISOMI[0] open drain enable" "Disabled,Enabled"
|
|
bitfld.long 0x18 10. " SIMOPDR0 ,SPISIMO[0] open drain enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x18 9. " CLKPDR ,SPI clock open drain enable" "Disabled,Enabled"
|
|
bitfld.long 0x18 8. " ENAPDR ,SPIENA open drain enable" "Disabled,Enabled"
|
|
bitfld.long 0x18 7. " SCSPDR7 ,SPISCS7 open drain enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x18 6. " SCSPDR6 ,SPISCS6 open drain enable" "Disabled,Enabled"
|
|
bitfld.long 0x18 5. " SCSPDR5 ,SPISCS5 open drain enable" "Disabled,Enabled"
|
|
bitfld.long 0x18 4. " SCSPDR4 ,SPISCS4 open drain enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x18 3. " SCSPDR3 ,SPISCS3 open drain enable" "Disabled,Enabled"
|
|
bitfld.long 0x18 2. " SCSPDR2 ,SPISCS2 open drain enable" "Disabled,Enabled"
|
|
bitfld.long 0x18 1. " SCSPDR1 ,SPISCS1 open drain enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x18 0. " SCSPDR0 ,SPISCS0 open drain enable" "Disabled,Enabled"
|
|
line.long 0x1C "SPIPC7,SPI Pin Control Register 7"
|
|
bitfld.long 0x1C 31. " SOMIPDIS7 ,SPISOMI[7] pull control enable/disable" "No,Yes"
|
|
bitfld.long 0x1C 30. " SOMIPDIS6 ,SPISOMI[6] pull control enable/disable" "No,Yes"
|
|
bitfld.long 0x1C 29. " SOMIPDIS5 ,SPISOMI[5] pull control enable/disable" "No,Yes"
|
|
newline
|
|
bitfld.long 0x1C 28. " SOMIPDIS4 ,SPISOMI[4] pull control enable/disable" "No,Yes"
|
|
bitfld.long 0x1C 27. " SOMIPDIS3 ,SPISOMI[3] pull control enable/disable" "No,Yes"
|
|
bitfld.long 0x1C 26. " SOMIPDIS2 ,SPISOMI[2] pull control enable/disable" "No,Yes"
|
|
newline
|
|
bitfld.long 0x1C 25. " SOMIPDIS1 ,SPISOMI[1] pull control enable/disable" "No,Yes"
|
|
bitfld.long 0x1C 24. " SOMIPDIS0 ,SPISOMI[0] pull control enable/disable (mirror of bit 11)" "No,Yes"
|
|
bitfld.long 0x1C 23. " SIMOPDIS7 ,SPISIMO[7] pull control enable/disable" "No,Yes"
|
|
newline
|
|
bitfld.long 0x1C 22. " SIMOPDIS6 ,SPISIMO[6] pull control enable/disable" "No,Yes"
|
|
bitfld.long 0x1C 21. " SIMOPDIS5 ,SPISIMO[5] pull control enable/disable" "No,Yes"
|
|
bitfld.long 0x1C 20. " SIMOPDIS4 ,SPISIMO[4] pull control enable/disable" "No,Yes"
|
|
newline
|
|
bitfld.long 0x1C 19. " SIMOPDIS3 ,SPISIMO[3] pull control enable/disable" "No,Yes"
|
|
bitfld.long 0x1C 18. " SIMOPDIS2 ,SPISIMO[2] pull control enable/disable" "No,Yes"
|
|
bitfld.long 0x1C 17. " SIMOPDIS1 ,SPISIMO[1] pull control enable/disable" "No,Yes"
|
|
newline
|
|
bitfld.long 0x1C 16. " SIMOPDIS0 ,SPISIMO[0] pull control enable/disable (mirror of bit 10)" "No,Yes"
|
|
bitfld.long 0x1C 11. " SOMIPDIS0 ,SPISOMI[0] pull control enable/disable" "No,Yes"
|
|
bitfld.long 0x1C 10. " SIMOPDIS0 ,SPISIMO[0] pull control enable/disable" "No,Yes"
|
|
newline
|
|
bitfld.long 0x1C 9. " CLKPDIS ,SPI clock pull control enable/disable" "No,Yes"
|
|
bitfld.long 0x1C 8. " ENAPDIS ,SPIENA pull control enable/disable" "No,Yes"
|
|
bitfld.long 0x1C 7. " SCSPDIS7 ,SPISCS7 pull control enable/disable" "No,Yes"
|
|
newline
|
|
bitfld.long 0x1C 6. " SCSPDIS6 ,SPISCS6 pull control enable/disable" "No,Yes"
|
|
bitfld.long 0x1C 5. " SCSPDIS5 ,SPISCS5 pull control enable/disable" "No,Yes"
|
|
bitfld.long 0x1C 4. " SCSPDIS4 ,SPISCS4 pull control enable/disable" "No,Yes"
|
|
newline
|
|
bitfld.long 0x1C 3. " SCSPDIS3 ,SPISCS3 pull control enable/disable" "No,Yes"
|
|
bitfld.long 0x1C 2. " SCSPDIS2 ,SPISCS2 pull control enable/disable" "No,Yes"
|
|
bitfld.long 0x1C 1. " SCSPDIS1 ,SPISCS1 pull control enable/disable" "No,Yes"
|
|
newline
|
|
bitfld.long 0x1C 0. " SCSPDIS0 ,SPISCS0 pull control enable/disable" "No,Yes"
|
|
line.long 0x20 "SPIPC8,SPI Pin Control Register 8"
|
|
bitfld.long 0x20 31. " SOMIPSEL7 ,SPISOMI[7] pull select" "Pull down,Pull up"
|
|
bitfld.long 0x20 30. " SOMIPSEL6 ,SPISOMI[6] pull select" "Pull down,Pull up"
|
|
bitfld.long 0x20 29. " SOMIPSEL5 ,SPISOMI[5] pull select" "Pull down,Pull up"
|
|
newline
|
|
bitfld.long 0x20 28. " SOMIPSEL4 ,SPISOMI[4] pull select" "Pull down,Pull up"
|
|
bitfld.long 0x20 27. " SOMIPSEL3 ,SPISOMI[3] pull select" "Pull down,Pull up"
|
|
bitfld.long 0x20 26. " SOMIPSEL2 ,SPISOMI[2] pull select" "Pull down,Pull up"
|
|
newline
|
|
bitfld.long 0x20 25. " SOMIPSEL1 ,SPISOMI[1] pull select" "Pull down,Pull up"
|
|
bitfld.long 0x20 24. " SOMIPSEL0 ,SPISOMI[0] pull select (mirror of bit 11)" "Pull down,Pull up"
|
|
bitfld.long 0x20 23. " SIMOPSEL7 ,SPISIMO[7] pull select" "Pull down,Pull up"
|
|
newline
|
|
bitfld.long 0x20 22. " SIMOPSEL6 ,SPISIMO[6] pull select" "Pull down,Pull up"
|
|
bitfld.long 0x20 21. " SIMOPSEL5 ,SPISIMO[5] pull select" "Pull down,Pull up"
|
|
bitfld.long 0x20 20. " SIMOPSEL4 ,SPISIMO[4] pull select" "Pull down,Pull up"
|
|
newline
|
|
bitfld.long 0x20 19. " SIMOPSEL3 ,SPISIMO[3] pull select" "Pull down,Pull up"
|
|
bitfld.long 0x20 18. " SIMOPSEL2 ,SPISIMO[2] pull select" "Pull down,Pull up"
|
|
bitfld.long 0x20 17. " SIMOPSEL1 ,SPISIMO[1] pull select" "Pull down,Pull up"
|
|
newline
|
|
bitfld.long 0x20 16. " SIMOPSEL0 ,SPISIMO[0] pull select (mirror of bit 10)" "Pull down,Pull up"
|
|
bitfld.long 0x20 11. " SOMIPSEL0 ,SPISOMI[0] pull select" "Pull down,Pull up"
|
|
bitfld.long 0x20 10. " SIMOPSEL0 ,SPISIMO[0] pull select" "Pull down,Pull up"
|
|
newline
|
|
bitfld.long 0x20 9. " CLKPSEL ,SPI clock pull select" "Pull down,Pull up"
|
|
bitfld.long 0x20 8. " ENAPSEL ,SPIENA pull select" "Pull down,Pull up"
|
|
bitfld.long 0x20 7. " SCSPSEL7 ,SPISCS7 pull select" "Pull down,Pull up"
|
|
newline
|
|
bitfld.long 0x20 6. " SCSPSEL6 ,SPISCS6 pull select" "Pull down,Pull up"
|
|
bitfld.long 0x20 5. " SCSPSEL5 ,SPISCS5 pull select" "Pull down,Pull up"
|
|
bitfld.long 0x20 4. " SCSPSEL4 ,SPISCS4 pull select" "Pull down,Pull up"
|
|
newline
|
|
bitfld.long 0x20 3. " SCSPSEL3 ,SPISCS3 pull select" "Pull down,Pull up"
|
|
bitfld.long 0x20 2. " SCSPSEL2 ,SPISCS2 pull select" "Pull down,Pull up"
|
|
bitfld.long 0x20 1. " SCSPSEL1 ,SPISCS1 pull select" "Pull down,Pull up"
|
|
newline
|
|
bitfld.long 0x20 0. " SCSPSEL0 ,SPISCS0 pull select" "Pull down,Pull up"
|
|
group.long 0x38++0x07
|
|
line.long 0x00 "SPIDAT0,SPI Transmit Data Register 0"
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,SPI transmit data"
|
|
line.long 0x04 "SPIDAT1,Transmit Data Register 1"
|
|
bitfld.long 0x04 28. " CSHOLD ,Chip select hold mode" "Inactive,Active"
|
|
bitfld.long 0x04 26. " WDEL ,Enable the delay counter at the end of the current transaction" "No delay,After transaction"
|
|
bitfld.long 0x04 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
newline
|
|
hexmask.long.byte 0x04 16.--23. 1. " CSNR ,Chip select number"
|
|
hexmask.long.word 0x04 0.--15. 1. " TXDATA ,Transfer data"
|
|
hgroup.long 0x40++0x03
|
|
hide.long 0x00 "SPIBUF,SPI Receive Buffer Register"
|
|
in
|
|
rgroup.long 0x44++0x03
|
|
line.long 0x00 "SPIEMU,SPI Emulation Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " EMU_RXDATA ,SPI receive data"
|
|
sif cpuis("TMS570LS0232")||cpuis("TMS570LS0714*")||cpuis("TMS570LS0914*")
|
|
group.long 0x48++0x03
|
|
line.long 0x00 "SPIDELAY,SPI Delay Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " C2TDELAY ,Chip-select-active to transmit-start delay"
|
|
hexmask.long.byte 0x00 16.--23. 1. " T2CDELAY ,Transmit-end-to-chip-select-inactive-delay"
|
|
hexmask.long.byte 0x00 8.--15. 1. " T2EDELAY ,Transmit-data-finished to ENA-pin-inactive time-out"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--7. 1. " C2EDELAY ,Chip-select-active to ENA-signal-active time-out"
|
|
else
|
|
rgroup.long 0x48++0x03
|
|
line.long 0x00 "SPIDELAY,SPI Delay Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " C2TDELAY ,Chip-select-active to transmit-start delay"
|
|
hexmask.long.byte 0x00 16.--23. 1. " T2CDELAY ,Transmit-end-to-chip-select-inactive-delay"
|
|
hexmask.long.byte 0x00 8.--15. 1. " T2EDELAY ,Transmit-data-finished to ENA-pin-inactive time-out"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--7. 1. " C2EDELAY ,Chip-select-active to ENA-signal-active time-out"
|
|
endif
|
|
group.long 0x4C++0x13
|
|
line.long 0x00 "SPIDEF,SPI Default Chip Select Register"
|
|
bitfld.long 0x00 7. " CSDEF7 ,Chip select default pattern 7" "0,1"
|
|
bitfld.long 0x00 6. " CSDEF6 ,Chip select default pattern 6" "0,1"
|
|
bitfld.long 0x00 5. " CSDEF5 ,Chip select default pattern 5" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. " CSDEF4 ,Chip select default pattern 4" "0,1"
|
|
bitfld.long 0x00 3. " CSDEF3 ,Chip select default pattern 3" "0,1"
|
|
bitfld.long 0x00 2. " CSDEF2 ,Chip select default pattern 2" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. " CSDEF1 ,Chip select default pattern 1" "0,1"
|
|
bitfld.long 0x00 0. " CSDEF0 ,Chip select default pattern 0" "0,1"
|
|
line.long 0x4 "SPIFMT0,SPI Data Format Register 0"
|
|
sif (cpuis("TMS570LS0332")||cpuis("TMS570LS0432")||cpuis("TMS570LS1114*")||cpuis("TMS570LS1115*")||cpuis("TMS570LS1224*")||cpuis("TMS570LS1225*")||cpuis("TMS570LS1227*")||cpuis("TMS570LS0232")||cpuis("TMS570LS0714*")||cpuis("TMS570LS0914*"))
|
|
hexmask.long.byte 0x4 24.--31. 1. " WDELAY ,Delay in between transmissions for data format 0"
|
|
else
|
|
bitfld.long 0x4 24.--29. " WDELAY ,Delay in between transmissions for data format 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
endif
|
|
bitfld.long 0x4 23. " PARPOL ,Parity polarity: even or odd" "Even,Odd"
|
|
newline
|
|
bitfld.long 0x4 22. " PARITYENA ,Parity enable for data format 0" "Disabled,Enabled"
|
|
bitfld.long 0x4 21. " WAITENA ,The master waits for the ENA signal from slave for data format 0" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x4 20. " SHIFTDIR ,Shift direction for data format $" "MSB,LSB"
|
|
sif (cpu()==("TMS570LS0332")||cpu()==("TMS570LS0432")||cpuis("TMS570LS1114*")||cpuis("TMS570LS1115*")||cpuis("TMS570LS1224*")||cpuis("TMS570LS1225*")||cpuis("TMS570LS1227*")||cpuis("TMS570LS0232")||cpuis("TMS570LS0714*")||cpuis("TMS570LS0914*"))
|
|
bitfld.long 0x4 19. " HDUPLEX_ENA0 ,Half Duplex transfer mode enable for Data Format 0" "Normal,RX/TX"
|
|
endif
|
|
newline
|
|
bitfld.long 0x4 18. " DISCSTIMERS ,Disable chip-select timers for this format" "No,Yes"
|
|
newline
|
|
bitfld.long 0x4 17. " POLARITY ,SPI data format 0 clock polarity" "Low,High"
|
|
bitfld.long 0x4 16. " PHASE ,SPI data format 0 clock delay" "Disabled,Enabled"
|
|
newline
|
|
hexmask.long.byte 0x4 8.--15. 1. " PRESCALE ,SPI data format 0 prescaler"
|
|
bitfld.long 0x4 0.--4. " CHARLEN ,SPI data format 0 data-word length" ",,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,?..."
|
|
line.long 0x8 "SPIFMT1,SPI Data Format Register 1"
|
|
sif (cpuis("TMS570LS0332")||cpuis("TMS570LS0432")||cpuis("TMS570LS1114*")||cpuis("TMS570LS1115*")||cpuis("TMS570LS1224*")||cpuis("TMS570LS1225*")||cpuis("TMS570LS1227*")||cpuis("TMS570LS0232")||cpuis("TMS570LS0714*")||cpuis("TMS570LS0914*"))
|
|
hexmask.long.byte 0x8 24.--31. 1. " WDELAY ,Delay in between transmissions for data format 1"
|
|
else
|
|
bitfld.long 0x8 24.--29. " WDELAY ,Delay in between transmissions for data format 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
endif
|
|
bitfld.long 0x8 23. " PARPOL ,Parity polarity: even or odd" "Even,Odd"
|
|
newline
|
|
bitfld.long 0x8 22. " PARITYENA ,Parity enable for data format 1" "Disabled,Enabled"
|
|
bitfld.long 0x8 21. " WAITENA ,The master waits for the ENA signal from slave for data format 1" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x8 20. " SHIFTDIR ,Shift direction for data format $" "MSB,LSB"
|
|
sif (cpu()==("TMS570LS0332")||cpu()==("TMS570LS0432")||cpuis("TMS570LS1114*")||cpuis("TMS570LS1115*")||cpuis("TMS570LS1224*")||cpuis("TMS570LS1225*")||cpuis("TMS570LS1227*")||cpuis("TMS570LS0232")||cpuis("TMS570LS0714*")||cpuis("TMS570LS0914*"))
|
|
bitfld.long 0x8 19. " HDUPLEX_ENA1 ,Half Duplex transfer mode enable for Data Format 1" "Normal,RX/TX"
|
|
endif
|
|
newline
|
|
bitfld.long 0x8 18. " DISCSTIMERS ,Disable chip-select timers for this format" "No,Yes"
|
|
newline
|
|
bitfld.long 0x8 17. " POLARITY ,SPI data format 1 clock polarity" "Low,High"
|
|
bitfld.long 0x8 16. " PHASE ,SPI data format 1 clock delay" "Disabled,Enabled"
|
|
newline
|
|
hexmask.long.byte 0x8 8.--15. 1. " PRESCALE ,SPI data format 1 prescaler"
|
|
bitfld.long 0x8 0.--4. " CHARLEN ,SPI data format 1 data-word length" ",,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,?..."
|
|
line.long 0xC "SPIFMT2,SPI Data Format Register 2"
|
|
sif (cpuis("TMS570LS0332")||cpuis("TMS570LS0432")||cpuis("TMS570LS1114*")||cpuis("TMS570LS1115*")||cpuis("TMS570LS1224*")||cpuis("TMS570LS1225*")||cpuis("TMS570LS1227*")||cpuis("TMS570LS0232")||cpuis("TMS570LS0714*")||cpuis("TMS570LS0914*"))
|
|
hexmask.long.byte 0xC 24.--31. 1. " WDELAY ,Delay in between transmissions for data format 2"
|
|
else
|
|
bitfld.long 0xC 24.--29. " WDELAY ,Delay in between transmissions for data format 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
endif
|
|
bitfld.long 0xC 23. " PARPOL ,Parity polarity: even or odd" "Even,Odd"
|
|
newline
|
|
bitfld.long 0xC 22. " PARITYENA ,Parity enable for data format 2" "Disabled,Enabled"
|
|
bitfld.long 0xC 21. " WAITENA ,The master waits for the ENA signal from slave for data format 2" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0xC 20. " SHIFTDIR ,Shift direction for data format $" "MSB,LSB"
|
|
sif (cpu()==("TMS570LS0332")||cpu()==("TMS570LS0432")||cpuis("TMS570LS1114*")||cpuis("TMS570LS1115*")||cpuis("TMS570LS1224*")||cpuis("TMS570LS1225*")||cpuis("TMS570LS1227*")||cpuis("TMS570LS0232")||cpuis("TMS570LS0714*")||cpuis("TMS570LS0914*"))
|
|
bitfld.long 0xC 19. " HDUPLEX_ENA2 ,Half Duplex transfer mode enable for Data Format 2" "Normal,RX/TX"
|
|
endif
|
|
newline
|
|
bitfld.long 0xC 18. " DISCSTIMERS ,Disable chip-select timers for this format" "No,Yes"
|
|
newline
|
|
bitfld.long 0xC 17. " POLARITY ,SPI data format 2 clock polarity" "Low,High"
|
|
bitfld.long 0xC 16. " PHASE ,SPI data format 2 clock delay" "Disabled,Enabled"
|
|
newline
|
|
hexmask.long.byte 0xC 8.--15. 1. " PRESCALE ,SPI data format 2 prescaler"
|
|
bitfld.long 0xC 0.--4. " CHARLEN ,SPI data format 2 data-word length" ",,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,?..."
|
|
line.long 0x10 "SPIFMT3,SPI Data Format Register 3"
|
|
sif (cpuis("TMS570LS0332")||cpuis("TMS570LS0432")||cpuis("TMS570LS1114*")||cpuis("TMS570LS1115*")||cpuis("TMS570LS1224*")||cpuis("TMS570LS1225*")||cpuis("TMS570LS1227*")||cpuis("TMS570LS0232")||cpuis("TMS570LS0714*")||cpuis("TMS570LS0914*"))
|
|
hexmask.long.byte 0x10 24.--31. 1. " WDELAY ,Delay in between transmissions for data format 3"
|
|
else
|
|
bitfld.long 0x10 24.--29. " WDELAY ,Delay in between transmissions for data format 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
endif
|
|
bitfld.long 0x10 23. " PARPOL ,Parity polarity: even or odd" "Even,Odd"
|
|
newline
|
|
bitfld.long 0x10 22. " PARITYENA ,Parity enable for data format 3" "Disabled,Enabled"
|
|
bitfld.long 0x10 21. " WAITENA ,The master waits for the ENA signal from slave for data format 3" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x10 20. " SHIFTDIR ,Shift direction for data format $" "MSB,LSB"
|
|
sif (cpu()==("TMS570LS0332")||cpu()==("TMS570LS0432")||cpuis("TMS570LS1114*")||cpuis("TMS570LS1115*")||cpuis("TMS570LS1224*")||cpuis("TMS570LS1225*")||cpuis("TMS570LS1227*")||cpuis("TMS570LS0232")||cpuis("TMS570LS0714*")||cpuis("TMS570LS0914*"))
|
|
bitfld.long 0x10 19. " HDUPLEX_ENA3 ,Half Duplex transfer mode enable for Data Format 3" "Normal,RX/TX"
|
|
endif
|
|
newline
|
|
bitfld.long 0x10 18. " DISCSTIMERS ,Disable chip-select timers for this format" "No,Yes"
|
|
newline
|
|
bitfld.long 0x10 17. " POLARITY ,SPI data format 3 clock polarity" "Low,High"
|
|
bitfld.long 0x10 16. " PHASE ,SPI data format 3 clock delay" "Disabled,Enabled"
|
|
newline
|
|
hexmask.long.byte 0x10 8.--15. 1. " PRESCALE ,SPI data format 3 prescaler"
|
|
bitfld.long 0x10 0.--4. " CHARLEN ,SPI data format 3 data-word length" ",,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,?..."
|
|
hgroup.long 0x60++0x03
|
|
hide.long 0x00 "TGINTVECT0,SPI Interrupt Vector Register 0 / MibSPI Transfer Group Interrupt Vector Register 0"
|
|
in
|
|
hgroup.long 0x64++0x03
|
|
hide.long 0x00 "TGINTVECT1,SPI Interrupt Vector Register 1 / MibSPI Transfer Group Interrupt Vector Register 1"
|
|
in
|
|
sif (cpu()!=("TMS570LS0332")&&cpu()!=("TMS570LS0432")&&!cpuis("TMS570LS0232"))
|
|
group.long 0x6C++0x07
|
|
line.long 0x00 "SPIPMCTRL,SPI Parallel/Modulo Mode Control Register"
|
|
bitfld.long 0x00 29. " MODCLKPOL3 ,Modulo mode SPICLK polarity" "Normal,Inverted"
|
|
bitfld.long 0x00 26.--28. " MMODE3 ,SPI/MibSPI data lines " "1,2,3,4,5,6,?..."
|
|
bitfld.long 0x00 24.--25. " PMODE3 ,Parallel mode data lines" "1,2,4,8"
|
|
newline
|
|
bitfld.long 0x00 21. " MODCLKPOL2 ,Modulo mode SPICLK polarity" "Normal,Inverted"
|
|
bitfld.long 0x00 18.--20. " MMODE2 ,SPI/MibSPI data lines " "1,2,3,4,5,6,?..."
|
|
bitfld.long 0x00 16.--17. " PMODE2 ,Parallel mode data lines" "1,2,4,8"
|
|
newline
|
|
bitfld.long 0x00 13. " MODCLKPOL1 ,Modulo mode SPICLK polarity" "Normal,Inverted"
|
|
bitfld.long 0x00 10.--12. " MMODE1 ,SPI/MibSPI data lines " "1,2,3,4,5,6,?..."
|
|
bitfld.long 0x00 8.--9. " PMODE1 ,Parallel mode data lines" "1,2,4,8"
|
|
newline
|
|
bitfld.long 0x00 5. " MODCLKPOL0 ,Modulo mode SPICLK polarity" "Normal,Inverted"
|
|
bitfld.long 0x00 2.--4. " MMODE0 ,SPI/MibSPI data lines " "1,2,3,4,5,6,?..."
|
|
bitfld.long 0x00 0.--1. " PMODE0 ,Parallel mode data lines" "1,2,4,8"
|
|
line.long 0x04 "MIBSPIE,MibSPI Enable Register"
|
|
bitfld.long 0x04 16. " RXRAMACCESS ,Receive-RAM access control" "Not writable,Accessible"
|
|
bitfld.long 0x04 0. " MIBSPIENA ,Multi-buffer mode enable" "Disabled,Enabled"
|
|
elif cpuis("TMS570LS0332")||cpuis("TMS570LS0432")||cpuis("TMS570LS0714*")||cpuis("TMS570LS0914*")||cpuis("TMS570LS0232")
|
|
group.long 0x70++0x03
|
|
line.long 0x00 "MIBSPIE,MibSPI Enable Register"
|
|
bitfld.long 0x00 16. " RXRAMACCESS ,Receive-RAM access control" "Not writable,Accessible"
|
|
bitfld.long 0x00 0. " MIBSPIENA ,Multi-buffer mode enable" "Disabled,Enabled"
|
|
endif
|
|
group.long 0x74++0x0F
|
|
line.long 0x00 "TGITENST,MibSPI Transfer Group Interrupt Enable Set Register"
|
|
bitfld.long 0x00 31. " SETINTENRDY15 ,TG interrupt set (enable) when transfer finished" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " SETINTENRDY14 ,TG interrupt set (enable) when transfer finished" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " SETINTENRDY13 ,TG interrupt set (enable) when transfer finished" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 28. " SETINTENRDY12 ,TG interrupt set (enable) when transfer finished" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " SETINTENRDY11 ,TG interrupt set (enable) when transfer finished" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " SETINTENRDY10 ,TG interrupt set (enable) when transfer finished" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 25. " SETINTENRDY9 ,TG interrupt set (enable) when transfer finished" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " SETINTENRDY8 ,TG interrupt set (enable) when transfer finished" "Disabled,Enabled"
|
|
bitfld.long 0x00 23. " SETINTENRDY7 ,TG interrupt set (enable) when transfer finished" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 22. " SETINTENRDY6 ,TG interrupt set (enable) when transfer finished" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " SETINTENRDY5 ,TG interrupt set (enable) when transfer finished" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " SETINTENRDY4 ,SETTG interrupt set (enable) when transfer finished" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 19. " SETINTENRDY3 ,TG interrupt set (enable) when transfer finished" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SETINTENRDY2 ,TG interrupt set (enable) when transfer finished" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SETINTENRDY1 ,TG interrupt set (enable) when transfer finished" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 16. " SETINTENRDY0 ,TG interrupt set (enable) when transfer finished" "Disabled,Enabled"
|
|
bitfld.long 0x00 15. " SETINTENSUS15 ,TG interrupt set (enabled) when transfer suspended" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " SETINTENSUS14 ,TG interrupt set (enabled) when transfer suspended" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 13. " SETINTENSUS13 ,TG interrupt set (enabled) when transfer suspended" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " SETINTENSUS12 ,TG interrupt set (enabled) when transfer suspended" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " SETINTENSUS11 ,TG interrupt set (enabled) when transfer suspended" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 10. " SETINTENSUS10 ,TG interrupt set (enabled) when transfer suspended" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " SETINTENSUS9 ,TG interrupt set (enabled) when transfer suspended" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " SETINTENSUS8 ,TG interrupt set (enabled) when transfer suspended" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 7. " SETINTENSUS7 ,TG interrupt set (enabled) when transfer suspended" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " SETINTENSUS6 ,TG interrupt set (enabled) when transfer suspended" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " SETINTENSUS5 ,TG interrupt set (enabled) when transfer suspended" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 4. " SETINTENSUS4 ,TG interrupt set (enabled) when transfer suspended" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " SETINTENSUS3 ,TG interrupt set (enabled) when transfer suspended" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " SETINTENSUS2 ,TG interrupt set (enabled) when transfer suspended" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 1. " SETINTENSUS1 ,TG interrupt set (enabled) when transfer suspended" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SETINTENSUS0 ,TG interrupt set (enabled) when transfer suspended" "Disabled,Enabled"
|
|
line.long 0x04 "TGITENCR,MibSPI Transfer Group Interrupt Enable Clear Register"
|
|
bitfld.long 0x04 31. " CLRINTENRDY15 ,TG interrupt clear (disabled) when transfer finished" "Disabled,Enabled"
|
|
bitfld.long 0x04 30. " CLRINTENRDY14 ,TG interrupt clear (disabled) when transfer finished" "Disabled,Enabled"
|
|
bitfld.long 0x04 29. " CLRINTENRDY13 ,TG interrupt clear (disabled) when transfer finished" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x04 28. " CLRINTENRDY12 ,TG interrupt clear (disabled) when transfer finished" "Disabled,Enabled"
|
|
bitfld.long 0x04 27. " CLRINTENRDY11 ,TG interrupt clear (disabled) when transfer finished" "Disabled,Enabled"
|
|
bitfld.long 0x04 26. " CLRINTENRDY10 ,TG interrupt clear (disabled) when transfer finished" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x04 25. " CLRINTENRDY9 ,TG interrupt clear (disabled) when transfer finished" "Disabled,Enabled"
|
|
bitfld.long 0x04 24. " CLRINTENRDY8 ,TG interrupt clear (disabled) when transfer finished" "Disabled,Enabled"
|
|
bitfld.long 0x04 23. " CLRINTENRDY7 ,TG interrupt clear (disabled) when transfer finished" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x04 22. " CLRINTENRDY6 ,TG interrupt clear (disabled) when transfer finished" "Disabled,Enabled"
|
|
bitfld.long 0x04 21. " CLRINTENRDY5 ,TG interrupt clear (disabled) when transfer finished" "Disabled,Enabled"
|
|
bitfld.long 0x04 20. " CLRINTENRDY4 ,TG interrupt clear (disabled) when transfer finished" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x04 19. " CLRINTENRDY3 ,TG interrupt clear (disabled) when transfer finished" "Disabled,Enabled"
|
|
bitfld.long 0x04 18. " CLRINTENRDY2 ,TG interrupt clear (disabled) when transfer finished" "Disabled,Enabled"
|
|
bitfld.long 0x04 17. " CLRINTENRDY1 ,TG interrupt clear (disabled) when transfer finished" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x04 16. " CLRINTENRDY0 ,TG interrupt clear (disabled) when transfer finished" "Disabled,Enabled"
|
|
bitfld.long 0x04 15. " CLRINTENSUS15 ,TG interrupt clear (disabled) when transfer suspended" "Disabled,Enabled"
|
|
bitfld.long 0x04 14. " CLRINTENSUS14 ,TG interrupt clear (disabled) when transfer suspended" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x04 13. " CLRINTENSUS13 ,TG interrupt clear (disabled) when transfer suspended" "Disabled,Enabled"
|
|
bitfld.long 0x04 12. " CLRINTENSUS12 ,TG interrupt clear (disabled) when transfer suspended" "Disabled,Enabled"
|
|
bitfld.long 0x04 11. " CLRINTENSUS11 ,TG interrupt clear (disabled) when transfer suspended" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x04 10. " CLRINTENSUS10 ,TG interrupt clear (disabled) when transfer suspended" "Disabled,Enabled"
|
|
bitfld.long 0x04 9. " CLRINTENSUS9 ,TG interrupt clear (disabled) when transfer suspended" "Disabled,Enabled"
|
|
bitfld.long 0x04 8. " CLRINTENSUS8 ,TG interrupt clear (disabled) when transfer suspended" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x04 7. " CLRINTENSUS7 ,TG interrupt clear (disabled) when transfer suspended" "Disabled,Enabled"
|
|
bitfld.long 0x04 6. " CLRINTENSUS6 ,TG interrupt clear (disabled) when transfer suspended" "Disabled,Enabled"
|
|
bitfld.long 0x04 5. " CLRINTENSUS5 ,TG interrupt clear (disabled) when transfer suspended" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x04 4. " CLRINTENSUS4 ,TG interrupt clear (disabled) when transfer suspended" "Disabled,Enabled"
|
|
bitfld.long 0x04 3. " CLRINTENSUS3 ,TG interrupt clear (disabled) when transfer suspended" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " CLRINTENSUS2 ,TG interrupt clear (disabled) when transfer suspended" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x04 1. " CLRINTENSUS1 ,TG interrupt clear (disabled) when transfer suspended" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " CLRINTENSUS0 ,TG interrupt clear (disabled) when transfer suspended" "Disabled,Enabled"
|
|
line.long 0x08 "TGITLVST,MibSPI Transfer Group Interrupt Level Set Register"
|
|
bitfld.long 0x08 31. " SETINTLVLRDY15 ,Transfer-group completed interrupt level set" "INT0,INT1"
|
|
bitfld.long 0x08 30. " SETINTLVLRDY14 ,Transfer-group completed interrupt level set" "INT0,INT1"
|
|
bitfld.long 0x08 29. " SETINTLVLRDY13 ,Transfer-group completed interrupt level set" "INT0,INT1"
|
|
newline
|
|
bitfld.long 0x08 28. " SETINTLVLRDY12 ,Transfer-group completed interrupt level set" "INT0,INT1"
|
|
bitfld.long 0x08 27. " SETINTLVLRDY11 ,Transfer-group completed interrupt level set" "INT0,INT1"
|
|
bitfld.long 0x08 26. " SETINTLVLRDY10 ,Transfer-group completed interrupt level set" "INT0,INT1"
|
|
newline
|
|
bitfld.long 0x08 25. " SETINTLVLRDY9 ,Transfer-group completed interrupt level set" "INT0,INT1"
|
|
bitfld.long 0x08 24. " SETINTLVLRDY8 ,Transfer-group completed interrupt level set" "INT0,INT1"
|
|
bitfld.long 0x08 23. " SETINTLVLRDY7 ,Transfer-group completed interrupt level set" "INT0,INT1"
|
|
newline
|
|
bitfld.long 0x08 22. " SETINTLVLRDY6 ,Transfer-group completed interrupt level set" "INT0,INT1"
|
|
bitfld.long 0x08 21. " SETINTLVLRDY5 ,Transfer-group completed interrupt level set" "INT0,INT1"
|
|
bitfld.long 0x08 20. " SETINTLVLRDY4 ,Transfer-group completed interrupt level set" "INT0,INT1"
|
|
newline
|
|
bitfld.long 0x08 19. " SETINTLVLRDY3 ,Transfer-group completed interrupt level set" "INT0,INT1"
|
|
bitfld.long 0x08 18. " SETINTLVLRDY2 ,Transfer-group completed interrupt level set" "INT0,INT1"
|
|
bitfld.long 0x08 17. " SETINTLVLRDY1 ,Transfer-group completed interrupt level set" "INT0,INT1"
|
|
newline
|
|
bitfld.long 0x08 16. " SETINTLVLRDY0 ,Transfer-group completed interrupt level set" "INT0,INT1"
|
|
bitfld.long 0x08 15. " SETINTLVLSUS15 ,Transfer-group suspended interrupt level set" "INT0,INT1"
|
|
bitfld.long 0x08 14. " SETINTLVLSUS14 ,Transfer-group suspended interrupt level set" "INT0,INT1"
|
|
newline
|
|
bitfld.long 0x08 13. " SETINTLVLSUS13 ,Transfer-group suspended interrupt level set" "INT0,INT1"
|
|
bitfld.long 0x08 12. " SETINTLVLSUS12 ,Transfer-group suspended interrupt level set" "INT0,INT1"
|
|
bitfld.long 0x08 11. " SETINTLVLSUS11 ,Transfer-group suspended interrupt level set" "INT0,INT1"
|
|
newline
|
|
bitfld.long 0x08 10. " SETINTLVLSUS10 ,Transfer-group suspended interrupt level set" "INT0,INT1"
|
|
bitfld.long 0x08 9. " SETINTLVLSUS9 ,Transfer-group suspended interrupt level set" "INT0,INT1"
|
|
bitfld.long 0x08 8. " SETINTLVLSUS8 ,Transfer-group suspended interrupt level set" "INT0,INT1"
|
|
newline
|
|
bitfld.long 0x08 7. " SETINTLVLSUS7 ,Transfer-group suspended interrupt level set" "INT0,INT1"
|
|
bitfld.long 0x08 6. " SETINTLVLSUS6 ,Transfer-group suspended interrupt level set" "INT0,INT1"
|
|
bitfld.long 0x08 5. " SETINTLVLSUS5 ,Transfer-group suspended interrupt level set" "INT0,INT1"
|
|
newline
|
|
bitfld.long 0x08 4. " SETINTLVLSUS4 ,Transfer-group suspended interrupt level set" "INT0,INT1"
|
|
bitfld.long 0x08 3. " SETINTLVLSUS3 ,Transfer-group suspended interrupt level set" "INT0,INT1"
|
|
bitfld.long 0x08 2. " SETINTLVLSUS2 ,Transfer-group suspended interrupt level set" "INT0,INT1"
|
|
newline
|
|
bitfld.long 0x08 1. " SETINTLVLSUS1 ,Transfer-group suspended interrupt level set" "INT0,INT1"
|
|
bitfld.long 0x08 0. " SETINTLVLSUS0 ,Transfer-group suspended interrupt level set" "INT0,INT1"
|
|
line.long 0x0C "TGITLVCR,MibSPI Transfer Group Interrupt Level Clear Register"
|
|
bitfld.long 0x0C 31. " CLRINTLVLRDY15 ,Transfer-group completed interrupt level clear" "INT0,INT1"
|
|
bitfld.long 0x0C 30. " CLRINTLVLRDY14 ,Transfer-group completed interrupt level clear" "INT0,INT1"
|
|
bitfld.long 0x0C 29. " CLRINTLVLRDY13 ,Transfer-group completed interrupt level clear" "INT0,INT1"
|
|
newline
|
|
bitfld.long 0x0C 28. " CLRINTLVLRDY12 ,Transfer-group completed interrupt level clear" "INT0,INT1"
|
|
bitfld.long 0x0C 27. " CLRINTLVLRDY11 ,Transfer-group completed interrupt level clear" "INT0,INT1"
|
|
bitfld.long 0x0C 26. " CLRINTLVLRDY10 ,Transfer-group completed interrupt level clear" "INT0,INT1"
|
|
newline
|
|
bitfld.long 0x0C 25. " CLRINTLVLRDY9 ,Transfer-group completed interrupt level clear" "INT0,INT1"
|
|
bitfld.long 0x0C 24. " CLRINTLVLRDY8 ,Transfer-group completed interrupt level clear" "INT0,INT1"
|
|
bitfld.long 0x0C 23. " CLRINTLVLRDY7 ,Transfer-group completed interrupt level clear" "INT0,INT1"
|
|
newline
|
|
bitfld.long 0x0C 22. " CLRINTLVLRDY6 ,Transfer-group completed interrupt level clear" "INT0,INT1"
|
|
bitfld.long 0x0C 21. " CLRINTLVLRDY5 ,Transfer-group completed interrupt level clear" "INT0,INT1"
|
|
bitfld.long 0x0C 20. " CLRINTLVLRDY4 ,Transfer-group completed interrupt level clear" "INT0,INT1"
|
|
newline
|
|
bitfld.long 0x0C 19. " CLRINTLVLRDY3 ,Transfer-group completed interrupt level clear" "INT0,INT1"
|
|
bitfld.long 0x0C 18. " CLRINTLVLRDY2 ,Transfer-group completed interrupt level clear" "INT0,INT1"
|
|
bitfld.long 0x0C 17. " CLRINTLVLRDY1 ,Transfer-group completed interrupt level clear" "INT0,INT1"
|
|
newline
|
|
bitfld.long 0x0C 16. " CLRINTLVLRDY0 ,Transfer-group completed interrupt level clear" "INT0,INT1"
|
|
bitfld.long 0x0C 15. " CLRINTLVLSUS15 ,Transfer group suspended interrupt level clear" "INT0,INT1"
|
|
bitfld.long 0x0C 14. " CLRINTLVLSUS14 ,Transfer group suspended interrupt level clear" "INT0,INT1"
|
|
newline
|
|
bitfld.long 0x0C 13. " CLRINTLVLSUS13 ,Transfer group suspended interrupt level clear" "INT0,INT1"
|
|
bitfld.long 0x0C 12. " CLRINTLVLSUS12 ,Transfer group suspended interrupt level clear" "INT0,INT1"
|
|
bitfld.long 0x0C 11. " CLRINTLVLSUS11 ,Transfer group suspended interrupt level clear" "INT0,INT1"
|
|
newline
|
|
bitfld.long 0x0C 10. " CLRINTLVLSUS10 ,Transfer group suspended interrupt level clear" "INT0,INT1"
|
|
bitfld.long 0x0C 9. " CLRINTLVLSUS9 ,Transfer group suspended interrupt level clear" "INT0,INT1"
|
|
bitfld.long 0x0C 8. " CLRINTLVLSUS8 ,Transfer group suspended interrupt level clear" "INT0,INT1"
|
|
newline
|
|
bitfld.long 0x0C 7. " CLRINTLVLSUS7 ,Transfer group suspended interrupt level clear" "INT0,INT1"
|
|
bitfld.long 0x0C 6. " CLRINTLVLSUS6 ,Transfer group suspended interrupt level clear" "INT0,INT1"
|
|
bitfld.long 0x0C 5. " CLRINTLVLSUS5 ,Transfer group suspended interrupt level clear" "INT0,INT1"
|
|
newline
|
|
bitfld.long 0x0C 4. " CLRINTLVLSUS4 ,Transfer group suspended interrupt level clear" "INT0,INT1"
|
|
bitfld.long 0x0C 3. " CLRINTLVLSUS3 ,Transfer group suspended interrupt level clear" "INT0,INT1"
|
|
bitfld.long 0x0C 2. " CLRINTLVLSUS2 ,Transfer group suspended interrupt level clear" "INT0,INT1"
|
|
newline
|
|
bitfld.long 0x0C 1. " CLRINTLVLSUS1 ,Transfer group suspended interrupt level clear" "INT0,INT1"
|
|
bitfld.long 0x0C 0. " CLRINTLVLSUS0 ,Transfer group suspended interrupt level clear" "INT0,INT1"
|
|
group.long 0x84++0x03
|
|
line.long 0x00 "TGITFLG,Transfer Group Interrupt Flag Register"
|
|
sif (cpu()==("TMS570LS0332")||cpu()==("TMS570LS0432")||cpuis("TMS570LS1114*")||cpuis("TMS570LS1115*")||cpuis("TMS570LS1224*")||cpuis("TMS570LS1225*")||cpuis("TMS570LS1227*")||cpuis("TMS570LS0232")||cpuis("TMS570LS0714*")||cpuis("TMS570LS0914*"))
|
|
bitfld.long 0x00 31. " INTFLGRDY[15] ,Transfer-group interrupt flag for a transfer-completed interrupt 15" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " INTFLGRDY[14] ,Transfer-group interrupt flag for a transfer-completed interrupt 14" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 29. " INTFLGRDY[13] ,Transfer-group interrupt flag for a transfer-completed interrupt 13" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " INTFLGRDY[12] ,Transfer-group interrupt flag for a transfer-completed interrupt 12" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 27. " INTFLGRDY[11] ,Transfer-group interrupt flag for a transfer-completed interrupt 11" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " INTFLGRDY[10] ,Transfer-group interrupt flag for a transfer-completed interrupt 10" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 25. " INTFLGRDY[9] ,Transfer-group interrupt flag for a transfer-completed interrupt 9" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " INTFLGRDY[8] ,Transfer-group interrupt flag for a transfer-completed interrupt 8" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 23. " INTFLGRDY[7] ,Transfer-group interrupt flag for a transfer-completed interrupt 7" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " INTFLGRDY[6] ,Transfer-group interrupt flag for a transfer-completed interrupt 6" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 21. " INTFLGRDY[5] ,Transfer-group interrupt flag for a transfer-completed interrupt 5" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " INTFLGRDY[4] ,Transfer-group interrupt flag for a transfer-completed interrupt 4" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 19. " INTFLGRDY[3] ,Transfer-group interrupt flag for a transfer-completed interrupt 3" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " INTFLGRDY[2] ,Transfer-group interrupt flag for a transfer-completed interrupt 2" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 17. " INTFLGRDY[1] ,Transfer-group interrupt flag for a transfer-completed interrupt 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " INTFLGRDY[0] ,Transfer-group interrupt flag for a transfer-completed interrupt 0" "Disabled,Enabled"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 15. " INTFLGSUS[15] ,Transfer-group interrupt flag for a transfer-suspend interrupt 15" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " INTFLGSUS[14] ,Transfer-group interrupt flag for a transfer-suspend interrupt 14" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 13. " INTFLGSUS[13] ,Transfer-group interrupt flag for a transfer-suspend interrupt 13" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " INTFLGSUS[12] ,Transfer-group interrupt flag for a transfer-suspend interrupt 12" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 11. " INTFLGSUS[11] ,Transfer-group interrupt flag for a transfer-suspend interrupt 11" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " INTFLGSUS[10] ,Transfer-group interrupt flag for a transfer-suspend interrupt 10" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 9. " INTFLGSUS[9] ,Transfer-group interrupt flag for a transfer-suspend interrupt 9" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " INTFLGSUS[8] ,Transfer-group interrupt flag for a transfer-suspend interrupt 8" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 7. " INTFLGSUS[7] ,Transfer-group interrupt flag for a transfer-suspend interrupt 7" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " INTFLGSUS[6] ,Transfer-group interrupt flag for a transfer-suspend interrupt 6" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 5. " INTFLGSUS[5] ,Transfer-group interrupt flag for a transfer-suspend interrupt 5" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " INTFLGSUS[4] ,Transfer-group interrupt flag for a transfer-suspend interrupt 4" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 3. " INTFLGSUS[3] ,Transfer-group interrupt flag for a transfer-suspend interrupt 3" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " INTFLGSUS[2] ,Transfer-group interrupt flag for a transfer-suspend interrupt 2" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 1. " INTFLGSUS[1] ,Transfer-group interrupt flag for a transfer-suspend interrupt 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " INTFLGSUS[0] ,Transfer-group interrupt flag for a transfer-suspend interrupt 0" "Disabled,Enabled"
|
|
group.long 0x90++0x47
|
|
line.long 0x00 "TICKCNT,Tick Count Register"
|
|
bitfld.long 0x00 31. " TICKENA ,Tick counter enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " RELOAD ,Pre-load the tick counter" "No effect,Reload"
|
|
bitfld.long 0x00 28.--29. " CLKCTRL ,Tick counter clock source control" "0,1,2,3"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TICKVALUE ,Initial value for the tick counter"
|
|
line.long 0x04 "LTGPEND,Last Transfer Group End Pointer Register"
|
|
bitfld.long 0x04 24.--28. " TGINSERVICE ,The TG number currently being serviced by the sequencer" "No TG,TG0,TG1,TG2,TG3,TG4,TG5,TG6,TG7,TG8,TG9,TG10,TG11,TG12,TG13,TG14,TG15,?..."
|
|
hexmask.long.byte 0x04 8.--14. 1. " LPEND ,Last TG end pointer"
|
|
line.long 0x8 "TG0CTRL,MibSPI Transfer Group Control Register 0"
|
|
bitfld.long 0x8 31. " TGENA ,TG enable" "Disabled,Enabled"
|
|
bitfld.long 0x8 30. " ONESHOT ,Single transfer for TG" "Disabled,Enabled"
|
|
bitfld.long 0x8 29. " PRST ,TG pointer reset mode" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x8 28. " TGTD ,TG triggered" "Not triggered,Triggered"
|
|
bitfld.long 0x8 20.--23. " TRGEVT ,Type of trigger event" "Never,Rising edge,Falling edge,Both edges,,High active,Low-active,Always,?..."
|
|
sif cpuis("TMS570LS0232")||cpuis("TMS570LS0714*")||cpuis("TMS570LS0914*")
|
|
bitfld.long 0x8 16.--19. " TRIGSRC ,Trigger source" "Disabled,EXT0,EXT1,EXT2,EXT3,EXT4,EXT5,EXT6,EXT7,EXT8,EXT9,EXT10,EXT11,EXT12,EXT13,TICK"
|
|
else
|
|
bitfld.long 0x8 16.--19. " TRIGSRC ,Trigger source" "Disabled,GIOA[0],GIOA[1],GIOA[2],GIOA[3],GIOA[4],GIOA[5],GIOA[6],GIOA[7],N2HET1[8],N2HET1[10],N2HET1[12],N2HET1[14],N2HET1[16],N2HET1[18],TICK"
|
|
endif
|
|
newline
|
|
hexmask.long.byte 0x8 8.--14. 0x01 " PSTART ,TG start address"
|
|
hexmask.long.byte 0x8 0.--6. 0x01 " PCURRENT ,Pointer to current buffer"
|
|
line.long 0xC "TG1CTRL,MibSPI Transfer Group Control Register 1"
|
|
bitfld.long 0xC 31. " TGENA ,TG enable" "Disabled,Enabled"
|
|
bitfld.long 0xC 30. " ONESHOT ,Single transfer for TG" "Disabled,Enabled"
|
|
bitfld.long 0xC 29. " PRST ,TG pointer reset mode" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0xC 28. " TGTD ,TG triggered" "Not triggered,Triggered"
|
|
bitfld.long 0xC 20.--23. " TRGEVT ,Type of trigger event" "Never,Rising edge,Falling edge,Both edges,,High active,Low-active,Always,?..."
|
|
sif cpuis("TMS570LS0232")||cpuis("TMS570LS0714*")||cpuis("TMS570LS0914*")
|
|
bitfld.long 0xC 16.--19. " TRIGSRC ,Trigger source" "Disabled,EXT0,EXT1,EXT2,EXT3,EXT4,EXT5,EXT6,EXT7,EXT8,EXT9,EXT10,EXT11,EXT12,EXT13,TICK"
|
|
else
|
|
bitfld.long 0xC 16.--19. " TRIGSRC ,Trigger source" "Disabled,GIOA[0],GIOA[1],GIOA[2],GIOA[3],GIOA[4],GIOA[5],GIOA[6],GIOA[7],N2HET1[8],N2HET1[10],N2HET1[12],N2HET1[14],N2HET1[16],N2HET1[18],TICK"
|
|
endif
|
|
newline
|
|
hexmask.long.byte 0xC 8.--14. 0x01 " PSTART ,TG start address"
|
|
hexmask.long.byte 0xC 0.--6. 0x01 " PCURRENT ,Pointer to current buffer"
|
|
line.long 0x10 "TG2CTRL,MibSPI Transfer Group Control Register 2"
|
|
bitfld.long 0x10 31. " TGENA ,TG enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 30. " ONESHOT ,Single transfer for TG" "Disabled,Enabled"
|
|
bitfld.long 0x10 29. " PRST ,TG pointer reset mode" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x10 28. " TGTD ,TG triggered" "Not triggered,Triggered"
|
|
bitfld.long 0x10 20.--23. " TRGEVT ,Type of trigger event" "Never,Rising edge,Falling edge,Both edges,,High active,Low-active,Always,?..."
|
|
sif cpuis("TMS570LS0232")||cpuis("TMS570LS0714*")||cpuis("TMS570LS0914*")
|
|
bitfld.long 0x10 16.--19. " TRIGSRC ,Trigger source" "Disabled,EXT0,EXT1,EXT2,EXT3,EXT4,EXT5,EXT6,EXT7,EXT8,EXT9,EXT10,EXT11,EXT12,EXT13,TICK"
|
|
else
|
|
bitfld.long 0x10 16.--19. " TRIGSRC ,Trigger source" "Disabled,GIOA[0],GIOA[1],GIOA[2],GIOA[3],GIOA[4],GIOA[5],GIOA[6],GIOA[7],N2HET1[8],N2HET1[10],N2HET1[12],N2HET1[14],N2HET1[16],N2HET1[18],TICK"
|
|
endif
|
|
newline
|
|
hexmask.long.byte 0x10 8.--14. 0x01 " PSTART ,TG start address"
|
|
hexmask.long.byte 0x10 0.--6. 0x01 " PCURRENT ,Pointer to current buffer"
|
|
line.long 0x14 "TG3CTRL,MibSPI Transfer Group Control Register 3"
|
|
bitfld.long 0x14 31. " TGENA ,TG enable" "Disabled,Enabled"
|
|
bitfld.long 0x14 30. " ONESHOT ,Single transfer for TG" "Disabled,Enabled"
|
|
bitfld.long 0x14 29. " PRST ,TG pointer reset mode" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x14 28. " TGTD ,TG triggered" "Not triggered,Triggered"
|
|
bitfld.long 0x14 20.--23. " TRGEVT ,Type of trigger event" "Never,Rising edge,Falling edge,Both edges,,High active,Low-active,Always,?..."
|
|
sif cpuis("TMS570LS0232")||cpuis("TMS570LS0714*")||cpuis("TMS570LS0914*")
|
|
bitfld.long 0x14 16.--19. " TRIGSRC ,Trigger source" "Disabled,EXT0,EXT1,EXT2,EXT3,EXT4,EXT5,EXT6,EXT7,EXT8,EXT9,EXT10,EXT11,EXT12,EXT13,TICK"
|
|
else
|
|
bitfld.long 0x14 16.--19. " TRIGSRC ,Trigger source" "Disabled,GIOA[0],GIOA[1],GIOA[2],GIOA[3],GIOA[4],GIOA[5],GIOA[6],GIOA[7],N2HET1[8],N2HET1[10],N2HET1[12],N2HET1[14],N2HET1[16],N2HET1[18],TICK"
|
|
endif
|
|
newline
|
|
hexmask.long.byte 0x14 8.--14. 0x01 " PSTART ,TG start address"
|
|
hexmask.long.byte 0x14 0.--6. 0x01 " PCURRENT ,Pointer to current buffer"
|
|
line.long 0x18 "TG4CTRL,MibSPI Transfer Group Control Register 4"
|
|
bitfld.long 0x18 31. " TGENA ,TG enable" "Disabled,Enabled"
|
|
bitfld.long 0x18 30. " ONESHOT ,Single transfer for TG" "Disabled,Enabled"
|
|
bitfld.long 0x18 29. " PRST ,TG pointer reset mode" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x18 28. " TGTD ,TG triggered" "Not triggered,Triggered"
|
|
bitfld.long 0x18 20.--23. " TRGEVT ,Type of trigger event" "Never,Rising edge,Falling edge,Both edges,,High active,Low-active,Always,?..."
|
|
sif cpuis("TMS570LS0232")||cpuis("TMS570LS0714*")||cpuis("TMS570LS0914*")
|
|
bitfld.long 0x18 16.--19. " TRIGSRC ,Trigger source" "Disabled,EXT0,EXT1,EXT2,EXT3,EXT4,EXT5,EXT6,EXT7,EXT8,EXT9,EXT10,EXT11,EXT12,EXT13,TICK"
|
|
else
|
|
bitfld.long 0x18 16.--19. " TRIGSRC ,Trigger source" "Disabled,GIOA[0],GIOA[1],GIOA[2],GIOA[3],GIOA[4],GIOA[5],GIOA[6],GIOA[7],N2HET1[8],N2HET1[10],N2HET1[12],N2HET1[14],N2HET1[16],N2HET1[18],TICK"
|
|
endif
|
|
newline
|
|
hexmask.long.byte 0x18 8.--14. 0x01 " PSTART ,TG start address"
|
|
hexmask.long.byte 0x18 0.--6. 0x01 " PCURRENT ,Pointer to current buffer"
|
|
line.long 0x1C "TG5CTRL,MibSPI Transfer Group Control Register 5"
|
|
bitfld.long 0x1C 31. " TGENA ,TG enable" "Disabled,Enabled"
|
|
bitfld.long 0x1C 30. " ONESHOT ,Single transfer for TG" "Disabled,Enabled"
|
|
bitfld.long 0x1C 29. " PRST ,TG pointer reset mode" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x1C 28. " TGTD ,TG triggered" "Not triggered,Triggered"
|
|
bitfld.long 0x1C 20.--23. " TRGEVT ,Type of trigger event" "Never,Rising edge,Falling edge,Both edges,,High active,Low-active,Always,?..."
|
|
sif cpuis("TMS570LS0232")||cpuis("TMS570LS0714*")||cpuis("TMS570LS0914*")
|
|
bitfld.long 0x1C 16.--19. " TRIGSRC ,Trigger source" "Disabled,EXT0,EXT1,EXT2,EXT3,EXT4,EXT5,EXT6,EXT7,EXT8,EXT9,EXT10,EXT11,EXT12,EXT13,TICK"
|
|
else
|
|
bitfld.long 0x1C 16.--19. " TRIGSRC ,Trigger source" "Disabled,GIOA[0],GIOA[1],GIOA[2],GIOA[3],GIOA[4],GIOA[5],GIOA[6],GIOA[7],N2HET1[8],N2HET1[10],N2HET1[12],N2HET1[14],N2HET1[16],N2HET1[18],TICK"
|
|
endif
|
|
newline
|
|
hexmask.long.byte 0x1C 8.--14. 0x01 " PSTART ,TG start address"
|
|
hexmask.long.byte 0x1C 0.--6. 0x01 " PCURRENT ,Pointer to current buffer"
|
|
line.long 0x20 "TG6CTRL,MibSPI Transfer Group Control Register 6"
|
|
bitfld.long 0x20 31. " TGENA ,TG enable" "Disabled,Enabled"
|
|
bitfld.long 0x20 30. " ONESHOT ,Single transfer for TG" "Disabled,Enabled"
|
|
bitfld.long 0x20 29. " PRST ,TG pointer reset mode" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x20 28. " TGTD ,TG triggered" "Not triggered,Triggered"
|
|
bitfld.long 0x20 20.--23. " TRGEVT ,Type of trigger event" "Never,Rising edge,Falling edge,Both edges,,High active,Low-active,Always,?..."
|
|
sif cpuis("TMS570LS0232")||cpuis("TMS570LS0714*")||cpuis("TMS570LS0914*")
|
|
bitfld.long 0x20 16.--19. " TRIGSRC ,Trigger source" "Disabled,EXT0,EXT1,EXT2,EXT3,EXT4,EXT5,EXT6,EXT7,EXT8,EXT9,EXT10,EXT11,EXT12,EXT13,TICK"
|
|
else
|
|
bitfld.long 0x20 16.--19. " TRIGSRC ,Trigger source" "Disabled,GIOA[0],GIOA[1],GIOA[2],GIOA[3],GIOA[4],GIOA[5],GIOA[6],GIOA[7],N2HET1[8],N2HET1[10],N2HET1[12],N2HET1[14],N2HET1[16],N2HET1[18],TICK"
|
|
endif
|
|
newline
|
|
hexmask.long.byte 0x20 8.--14. 0x01 " PSTART ,TG start address"
|
|
hexmask.long.byte 0x20 0.--6. 0x01 " PCURRENT ,Pointer to current buffer"
|
|
line.long 0x24 "TG7CTRL,MibSPI Transfer Group Control Register 7"
|
|
bitfld.long 0x24 31. " TGENA ,TG enable" "Disabled,Enabled"
|
|
bitfld.long 0x24 30. " ONESHOT ,Single transfer for TG" "Disabled,Enabled"
|
|
bitfld.long 0x24 29. " PRST ,TG pointer reset mode" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x24 28. " TGTD ,TG triggered" "Not triggered,Triggered"
|
|
bitfld.long 0x24 20.--23. " TRGEVT ,Type of trigger event" "Never,Rising edge,Falling edge,Both edges,,High active,Low-active,Always,?..."
|
|
sif cpuis("TMS570LS0232")||cpuis("TMS570LS0714*")||cpuis("TMS570LS0914*")
|
|
bitfld.long 0x24 16.--19. " TRIGSRC ,Trigger source" "Disabled,EXT0,EXT1,EXT2,EXT3,EXT4,EXT5,EXT6,EXT7,EXT8,EXT9,EXT10,EXT11,EXT12,EXT13,TICK"
|
|
else
|
|
bitfld.long 0x24 16.--19. " TRIGSRC ,Trigger source" "Disabled,GIOA[0],GIOA[1],GIOA[2],GIOA[3],GIOA[4],GIOA[5],GIOA[6],GIOA[7],N2HET1[8],N2HET1[10],N2HET1[12],N2HET1[14],N2HET1[16],N2HET1[18],TICK"
|
|
endif
|
|
newline
|
|
hexmask.long.byte 0x24 8.--14. 0x01 " PSTART ,TG start address"
|
|
hexmask.long.byte 0x24 0.--6. 0x01 " PCURRENT ,Pointer to current buffer"
|
|
line.long 0x28 "TG8CTRL,MibSPI Transfer Group Control Register 8"
|
|
bitfld.long 0x28 31. " TGENA ,TG enable" "Disabled,Enabled"
|
|
bitfld.long 0x28 30. " ONESHOT ,Single transfer for TG" "Disabled,Enabled"
|
|
bitfld.long 0x28 29. " PRST ,TG pointer reset mode" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x28 28. " TGTD ,TG triggered" "Not triggered,Triggered"
|
|
bitfld.long 0x28 20.--23. " TRGEVT ,Type of trigger event" "Never,Rising edge,Falling edge,Both edges,,High active,Low-active,Always,?..."
|
|
sif cpuis("TMS570LS0232")||cpuis("TMS570LS0714*")||cpuis("TMS570LS0914*")
|
|
bitfld.long 0x28 16.--19. " TRIGSRC ,Trigger source" "Disabled,EXT0,EXT1,EXT2,EXT3,EXT4,EXT5,EXT6,EXT7,EXT8,EXT9,EXT10,EXT11,EXT12,EXT13,TICK"
|
|
else
|
|
bitfld.long 0x28 16.--19. " TRIGSRC ,Trigger source" "Disabled,GIOA[0],GIOA[1],GIOA[2],GIOA[3],GIOA[4],GIOA[5],GIOA[6],GIOA[7],N2HET1[8],N2HET1[10],N2HET1[12],N2HET1[14],N2HET1[16],N2HET1[18],TICK"
|
|
endif
|
|
newline
|
|
hexmask.long.byte 0x28 8.--14. 0x01 " PSTART ,TG start address"
|
|
hexmask.long.byte 0x28 0.--6. 0x01 " PCURRENT ,Pointer to current buffer"
|
|
line.long 0x2C "TG9CTRL,MibSPI Transfer Group Control Register 9"
|
|
bitfld.long 0x2C 31. " TGENA ,TG enable" "Disabled,Enabled"
|
|
bitfld.long 0x2C 30. " ONESHOT ,Single transfer for TG" "Disabled,Enabled"
|
|
bitfld.long 0x2C 29. " PRST ,TG pointer reset mode" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x2C 28. " TGTD ,TG triggered" "Not triggered,Triggered"
|
|
bitfld.long 0x2C 20.--23. " TRGEVT ,Type of trigger event" "Never,Rising edge,Falling edge,Both edges,,High active,Low-active,Always,?..."
|
|
sif cpuis("TMS570LS0232")||cpuis("TMS570LS0714*")||cpuis("TMS570LS0914*")
|
|
bitfld.long 0x2C 16.--19. " TRIGSRC ,Trigger source" "Disabled,EXT0,EXT1,EXT2,EXT3,EXT4,EXT5,EXT6,EXT7,EXT8,EXT9,EXT10,EXT11,EXT12,EXT13,TICK"
|
|
else
|
|
bitfld.long 0x2C 16.--19. " TRIGSRC ,Trigger source" "Disabled,GIOA[0],GIOA[1],GIOA[2],GIOA[3],GIOA[4],GIOA[5],GIOA[6],GIOA[7],N2HET1[8],N2HET1[10],N2HET1[12],N2HET1[14],N2HET1[16],N2HET1[18],TICK"
|
|
endif
|
|
newline
|
|
hexmask.long.byte 0x2C 8.--14. 0x01 " PSTART ,TG start address"
|
|
hexmask.long.byte 0x2C 0.--6. 0x01 " PCURRENT ,Pointer to current buffer"
|
|
line.long 0x30 "TG10CTRL,MibSPI Transfer Group Control Register 10"
|
|
bitfld.long 0x30 31. " TGENA ,TG enable" "Disabled,Enabled"
|
|
bitfld.long 0x30 30. " ONESHOT ,Single transfer for TG" "Disabled,Enabled"
|
|
bitfld.long 0x30 29. " PRST ,TG pointer reset mode" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x30 28. " TGTD ,TG triggered" "Not triggered,Triggered"
|
|
bitfld.long 0x30 20.--23. " TRGEVT ,Type of trigger event" "Never,Rising edge,Falling edge,Both edges,,High active,Low-active,Always,?..."
|
|
sif cpuis("TMS570LS0232")||cpuis("TMS570LS0714*")||cpuis("TMS570LS0914*")
|
|
bitfld.long 0x30 16.--19. " TRIGSRC ,Trigger source" "Disabled,EXT0,EXT1,EXT2,EXT3,EXT4,EXT5,EXT6,EXT7,EXT8,EXT9,EXT10,EXT11,EXT12,EXT13,TICK"
|
|
else
|
|
bitfld.long 0x30 16.--19. " TRIGSRC ,Trigger source" "Disabled,GIOA[0],GIOA[1],GIOA[2],GIOA[3],GIOA[4],GIOA[5],GIOA[6],GIOA[7],N2HET1[8],N2HET1[10],N2HET1[12],N2HET1[14],N2HET1[16],N2HET1[18],TICK"
|
|
endif
|
|
newline
|
|
hexmask.long.byte 0x30 8.--14. 0x01 " PSTART ,TG start address"
|
|
hexmask.long.byte 0x30 0.--6. 0x01 " PCURRENT ,Pointer to current buffer"
|
|
line.long 0x34 "TG11CTRL,MibSPI Transfer Group Control Register 11"
|
|
bitfld.long 0x34 31. " TGENA ,TG enable" "Disabled,Enabled"
|
|
bitfld.long 0x34 30. " ONESHOT ,Single transfer for TG" "Disabled,Enabled"
|
|
bitfld.long 0x34 29. " PRST ,TG pointer reset mode" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x34 28. " TGTD ,TG triggered" "Not triggered,Triggered"
|
|
bitfld.long 0x34 20.--23. " TRGEVT ,Type of trigger event" "Never,Rising edge,Falling edge,Both edges,,High active,Low-active,Always,?..."
|
|
sif cpuis("TMS570LS0232")||cpuis("TMS570LS0714*")||cpuis("TMS570LS0914*")
|
|
bitfld.long 0x34 16.--19. " TRIGSRC ,Trigger source" "Disabled,EXT0,EXT1,EXT2,EXT3,EXT4,EXT5,EXT6,EXT7,EXT8,EXT9,EXT10,EXT11,EXT12,EXT13,TICK"
|
|
else
|
|
bitfld.long 0x34 16.--19. " TRIGSRC ,Trigger source" "Disabled,GIOA[0],GIOA[1],GIOA[2],GIOA[3],GIOA[4],GIOA[5],GIOA[6],GIOA[7],N2HET1[8],N2HET1[10],N2HET1[12],N2HET1[14],N2HET1[16],N2HET1[18],TICK"
|
|
endif
|
|
newline
|
|
hexmask.long.byte 0x34 8.--14. 0x01 " PSTART ,TG start address"
|
|
hexmask.long.byte 0x34 0.--6. 0x01 " PCURRENT ,Pointer to current buffer"
|
|
line.long 0x38 "TG12CTRL,MibSPI Transfer Group Control Register 12"
|
|
bitfld.long 0x38 31. " TGENA ,TG enable" "Disabled,Enabled"
|
|
bitfld.long 0x38 30. " ONESHOT ,Single transfer for TG" "Disabled,Enabled"
|
|
bitfld.long 0x38 29. " PRST ,TG pointer reset mode" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x38 28. " TGTD ,TG triggered" "Not triggered,Triggered"
|
|
bitfld.long 0x38 20.--23. " TRGEVT ,Type of trigger event" "Never,Rising edge,Falling edge,Both edges,,High active,Low-active,Always,?..."
|
|
sif cpuis("TMS570LS0232")||cpuis("TMS570LS0714*")||cpuis("TMS570LS0914*")
|
|
bitfld.long 0x38 16.--19. " TRIGSRC ,Trigger source" "Disabled,EXT0,EXT1,EXT2,EXT3,EXT4,EXT5,EXT6,EXT7,EXT8,EXT9,EXT10,EXT11,EXT12,EXT13,TICK"
|
|
else
|
|
bitfld.long 0x38 16.--19. " TRIGSRC ,Trigger source" "Disabled,GIOA[0],GIOA[1],GIOA[2],GIOA[3],GIOA[4],GIOA[5],GIOA[6],GIOA[7],N2HET1[8],N2HET1[10],N2HET1[12],N2HET1[14],N2HET1[16],N2HET1[18],TICK"
|
|
endif
|
|
newline
|
|
hexmask.long.byte 0x38 8.--14. 0x01 " PSTART ,TG start address"
|
|
hexmask.long.byte 0x38 0.--6. 0x01 " PCURRENT ,Pointer to current buffer"
|
|
line.long 0x3C "TG13CTRL,MibSPI Transfer Group Control Register 13"
|
|
bitfld.long 0x3C 31. " TGENA ,TG enable" "Disabled,Enabled"
|
|
bitfld.long 0x3C 30. " ONESHOT ,Single transfer for TG" "Disabled,Enabled"
|
|
bitfld.long 0x3C 29. " PRST ,TG pointer reset mode" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x3C 28. " TGTD ,TG triggered" "Not triggered,Triggered"
|
|
bitfld.long 0x3C 20.--23. " TRGEVT ,Type of trigger event" "Never,Rising edge,Falling edge,Both edges,,High active,Low-active,Always,?..."
|
|
sif cpuis("TMS570LS0232")||cpuis("TMS570LS0714*")||cpuis("TMS570LS0914*")
|
|
bitfld.long 0x3C 16.--19. " TRIGSRC ,Trigger source" "Disabled,EXT0,EXT1,EXT2,EXT3,EXT4,EXT5,EXT6,EXT7,EXT8,EXT9,EXT10,EXT11,EXT12,EXT13,TICK"
|
|
else
|
|
bitfld.long 0x3C 16.--19. " TRIGSRC ,Trigger source" "Disabled,GIOA[0],GIOA[1],GIOA[2],GIOA[3],GIOA[4],GIOA[5],GIOA[6],GIOA[7],N2HET1[8],N2HET1[10],N2HET1[12],N2HET1[14],N2HET1[16],N2HET1[18],TICK"
|
|
endif
|
|
newline
|
|
hexmask.long.byte 0x3C 8.--14. 0x01 " PSTART ,TG start address"
|
|
hexmask.long.byte 0x3C 0.--6. 0x01 " PCURRENT ,Pointer to current buffer"
|
|
line.long 0x40 "TG14CTRL,MibSPI Transfer Group Control Register 14"
|
|
bitfld.long 0x40 31. " TGENA ,TG enable" "Disabled,Enabled"
|
|
bitfld.long 0x40 30. " ONESHOT ,Single transfer for TG" "Disabled,Enabled"
|
|
bitfld.long 0x40 29. " PRST ,TG pointer reset mode" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x40 28. " TGTD ,TG triggered" "Not triggered,Triggered"
|
|
bitfld.long 0x40 20.--23. " TRGEVT ,Type of trigger event" "Never,Rising edge,Falling edge,Both edges,,High active,Low-active,Always,?..."
|
|
sif cpuis("TMS570LS0232")||cpuis("TMS570LS0714*")||cpuis("TMS570LS0914*")
|
|
bitfld.long 0x40 16.--19. " TRIGSRC ,Trigger source" "Disabled,EXT0,EXT1,EXT2,EXT3,EXT4,EXT5,EXT6,EXT7,EXT8,EXT9,EXT10,EXT11,EXT12,EXT13,TICK"
|
|
else
|
|
bitfld.long 0x40 16.--19. " TRIGSRC ,Trigger source" "Disabled,GIOA[0],GIOA[1],GIOA[2],GIOA[3],GIOA[4],GIOA[5],GIOA[6],GIOA[7],N2HET1[8],N2HET1[10],N2HET1[12],N2HET1[14],N2HET1[16],N2HET1[18],TICK"
|
|
endif
|
|
newline
|
|
hexmask.long.byte 0x40 8.--14. 0x01 " PSTART ,TG start address"
|
|
hexmask.long.byte 0x40 0.--6. 0x01 " PCURRENT ,Pointer to current buffer"
|
|
line.long 0x44 "TG15CTRL,MibSPI Transfer Group Control Register 15"
|
|
bitfld.long 0x44 31. " TGENA ,TG enable" "Disabled,Enabled"
|
|
bitfld.long 0x44 30. " ONESHOT ,Single transfer for TG" "Disabled,Enabled"
|
|
bitfld.long 0x44 29. " PRST ,TG pointer reset mode" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x44 28. " TGTD ,TG triggered" "Not triggered,Triggered"
|
|
bitfld.long 0x44 20.--23. " TRGEVT ,Type of trigger event" "Never,Rising edge,Falling edge,Both edges,,High active,Low-active,Always,?..."
|
|
sif cpuis("TMS570LS0232")||cpuis("TMS570LS0714*")||cpuis("TMS570LS0914*")
|
|
bitfld.long 0x44 16.--19. " TRIGSRC ,Trigger source" "Disabled,EXT0,EXT1,EXT2,EXT3,EXT4,EXT5,EXT6,EXT7,EXT8,EXT9,EXT10,EXT11,EXT12,EXT13,TICK"
|
|
else
|
|
bitfld.long 0x44 16.--19. " TRIGSRC ,Trigger source" "Disabled,GIOA[0],GIOA[1],GIOA[2],GIOA[3],GIOA[4],GIOA[5],GIOA[6],GIOA[7],N2HET1[8],N2HET1[10],N2HET1[12],N2HET1[14],N2HET1[16],N2HET1[18],TICK"
|
|
endif
|
|
newline
|
|
hexmask.long.byte 0x44 8.--14. 0x01 " PSTART ,TG start address"
|
|
hexmask.long.byte 0x44 0.--6. 0x01 " PCURRENT ,Pointer to current buffer"
|
|
sif (cpu()!=("TMS570LS0332")&&cpu()!=("TMS570LS0432")&&!cpuis("TMS570LS0232"))
|
|
group.long 0xD8++0x1F
|
|
line.long 0x0 "DMA0CTRL,MibSPI DMA Channel Control Register 1"
|
|
bitfld.long 0x0 31. " ONESHOT ,Auto-disable of DMA channel after ICOUNT+1 transfers" "0,1"
|
|
hexmask.long.byte 0x0 24.--30. 1. " BUFID ,Buffer utilized for DMA transfer"
|
|
bitfld.long 0x0 20.--23. " RXDMA_MAP ,Each MibSPI DMA channel can be linked to two physical DMA" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x0 16.--19. " TXDMA_MAP ,Each MibSPI DMA channel can be linked to two physical DMA" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x0 15. " RXDMAENA ,Receive data DMA channel enable" "Disabled,Enabled"
|
|
bitfld.long 0x0 14. " TXDMAENA ,Transmit data DMA channel enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x0 13. " NOBRK ,Non-interleaved DMA block transfer" "Not performed,Performed"
|
|
bitfld.long 0x0 8.--12. " ICOUNT ,Initial count of DMA transfers" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32"
|
|
bitfld.long 0x0 6. " COUNTBIT17 ,17th bit of the COUNT field of DMAxCOUNT register" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0.--5. " COUNT ,Actual number of remaining DMA transfers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
line.long 0x4 "DMA1CTRL,MibSPI DMA Channel Control Register 1"
|
|
bitfld.long 0x4 31. " ONESHOT ,Auto-disable of DMA channel after ICOUNT+1 transfers" "0,1"
|
|
hexmask.long.byte 0x4 24.--30. 1. " BUFID ,Buffer utilized for DMA transfer"
|
|
bitfld.long 0x4 20.--23. " RXDMA_MAP ,Each MibSPI DMA channel can be linked to two physical DMA" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x4 16.--19. " TXDMA_MAP ,Each MibSPI DMA channel can be linked to two physical DMA" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x4 15. " RXDMAENA ,Receive data DMA channel enable" "Disabled,Enabled"
|
|
bitfld.long 0x4 14. " TXDMAENA ,Transmit data DMA channel enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x4 13. " NOBRK ,Non-interleaved DMA block transfer" "Not performed,Performed"
|
|
bitfld.long 0x4 8.--12. " ICOUNT ,Initial count of DMA transfers" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32"
|
|
bitfld.long 0x4 6. " COUNTBIT17 ,17th bit of the COUNT field of DMAxCOUNT register" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0.--5. " COUNT ,Actual number of remaining DMA transfers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
line.long 0x8 "DMA2CTRL,MibSPI DMA Channel Control Register 1"
|
|
bitfld.long 0x8 31. " ONESHOT ,Auto-disable of DMA channel after ICOUNT+1 transfers" "0,1"
|
|
hexmask.long.byte 0x8 24.--30. 1. " BUFID ,Buffer utilized for DMA transfer"
|
|
bitfld.long 0x8 20.--23. " RXDMA_MAP ,Each MibSPI DMA channel can be linked to two physical DMA" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x8 16.--19. " TXDMA_MAP ,Each MibSPI DMA channel can be linked to two physical DMA" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x8 15. " RXDMAENA ,Receive data DMA channel enable" "Disabled,Enabled"
|
|
bitfld.long 0x8 14. " TXDMAENA ,Transmit data DMA channel enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x8 13. " NOBRK ,Non-interleaved DMA block transfer" "Not performed,Performed"
|
|
bitfld.long 0x8 8.--12. " ICOUNT ,Initial count of DMA transfers" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32"
|
|
bitfld.long 0x8 6. " COUNTBIT17 ,17th bit of the COUNT field of DMAxCOUNT register" "0,1"
|
|
newline
|
|
bitfld.long 0x8 0.--5. " COUNT ,Actual number of remaining DMA transfers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
line.long 0xC "DMA3CTRL,MibSPI DMA Channel Control Register 1"
|
|
bitfld.long 0xC 31. " ONESHOT ,Auto-disable of DMA channel after ICOUNT+1 transfers" "0,1"
|
|
hexmask.long.byte 0xC 24.--30. 1. " BUFID ,Buffer utilized for DMA transfer"
|
|
bitfld.long 0xC 20.--23. " RXDMA_MAP ,Each MibSPI DMA channel can be linked to two physical DMA" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0xC 16.--19. " TXDMA_MAP ,Each MibSPI DMA channel can be linked to two physical DMA" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0xC 15. " RXDMAENA ,Receive data DMA channel enable" "Disabled,Enabled"
|
|
bitfld.long 0xC 14. " TXDMAENA ,Transmit data DMA channel enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0xC 13. " NOBRK ,Non-interleaved DMA block transfer" "Not performed,Performed"
|
|
bitfld.long 0xC 8.--12. " ICOUNT ,Initial count of DMA transfers" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32"
|
|
bitfld.long 0xC 6. " COUNTBIT17 ,17th bit of the COUNT field of DMAxCOUNT register" "0,1"
|
|
newline
|
|
bitfld.long 0xC 0.--5. " COUNT ,Actual number of remaining DMA transfers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
line.long 0x10 "DMA4CTRL,MibSPI DMA Channel Control Register 1"
|
|
bitfld.long 0x10 31. " ONESHOT ,Auto-disable of DMA channel after ICOUNT+1 transfers" "0,1"
|
|
hexmask.long.byte 0x10 24.--30. 1. " BUFID ,Buffer utilized for DMA transfer"
|
|
bitfld.long 0x10 20.--23. " RXDMA_MAP ,Each MibSPI DMA channel can be linked to two physical DMA" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x10 16.--19. " TXDMA_MAP ,Each MibSPI DMA channel can be linked to two physical DMA" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x10 15. " RXDMAENA ,Receive data DMA channel enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 14. " TXDMAENA ,Transmit data DMA channel enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x10 13. " NOBRK ,Non-interleaved DMA block transfer" "Not performed,Performed"
|
|
bitfld.long 0x10 8.--12. " ICOUNT ,Initial count of DMA transfers" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32"
|
|
bitfld.long 0x10 6. " COUNTBIT17 ,17th bit of the COUNT field of DMAxCOUNT register" "0,1"
|
|
newline
|
|
bitfld.long 0x10 0.--5. " COUNT ,Actual number of remaining DMA transfers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
line.long 0x14 "DMA5CTRL,MibSPI DMA Channel Control Register 1"
|
|
bitfld.long 0x14 31. " ONESHOT ,Auto-disable of DMA channel after ICOUNT+1 transfers" "0,1"
|
|
hexmask.long.byte 0x14 24.--30. 1. " BUFID ,Buffer utilized for DMA transfer"
|
|
bitfld.long 0x14 20.--23. " RXDMA_MAP ,Each MibSPI DMA channel can be linked to two physical DMA" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x14 16.--19. " TXDMA_MAP ,Each MibSPI DMA channel can be linked to two physical DMA" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x14 15. " RXDMAENA ,Receive data DMA channel enable" "Disabled,Enabled"
|
|
bitfld.long 0x14 14. " TXDMAENA ,Transmit data DMA channel enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x14 13. " NOBRK ,Non-interleaved DMA block transfer" "Not performed,Performed"
|
|
bitfld.long 0x14 8.--12. " ICOUNT ,Initial count of DMA transfers" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32"
|
|
bitfld.long 0x14 6. " COUNTBIT17 ,17th bit of the COUNT field of DMAxCOUNT register" "0,1"
|
|
newline
|
|
bitfld.long 0x14 0.--5. " COUNT ,Actual number of remaining DMA transfers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
line.long 0x18 "DMA6CTRL,MibSPI DMA Channel Control Register 1"
|
|
bitfld.long 0x18 31. " ONESHOT ,Auto-disable of DMA channel after ICOUNT+1 transfers" "0,1"
|
|
hexmask.long.byte 0x18 24.--30. 1. " BUFID ,Buffer utilized for DMA transfer"
|
|
bitfld.long 0x18 20.--23. " RXDMA_MAP ,Each MibSPI DMA channel can be linked to two physical DMA" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x18 16.--19. " TXDMA_MAP ,Each MibSPI DMA channel can be linked to two physical DMA" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x18 15. " RXDMAENA ,Receive data DMA channel enable" "Disabled,Enabled"
|
|
bitfld.long 0x18 14. " TXDMAENA ,Transmit data DMA channel enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x18 13. " NOBRK ,Non-interleaved DMA block transfer" "Not performed,Performed"
|
|
bitfld.long 0x18 8.--12. " ICOUNT ,Initial count of DMA transfers" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32"
|
|
bitfld.long 0x18 6. " COUNTBIT17 ,17th bit of the COUNT field of DMAxCOUNT register" "0,1"
|
|
newline
|
|
bitfld.long 0x18 0.--5. " COUNT ,Actual number of remaining DMA transfers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
line.long 0x1C "DMA7CTRL,MibSPI DMA Channel Control Register 1"
|
|
bitfld.long 0x1C 31. " ONESHOT ,Auto-disable of DMA channel after ICOUNT+1 transfers" "0,1"
|
|
hexmask.long.byte 0x1C 24.--30. 1. " BUFID ,Buffer utilized for DMA transfer"
|
|
bitfld.long 0x1C 20.--23. " RXDMA_MAP ,Each MibSPI DMA channel can be linked to two physical DMA" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x1C 16.--19. " TXDMA_MAP ,Each MibSPI DMA channel can be linked to two physical DMA" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x1C 15. " RXDMAENA ,Receive data DMA channel enable" "Disabled,Enabled"
|
|
bitfld.long 0x1C 14. " TXDMAENA ,Transmit data DMA channel enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x1C 13. " NOBRK ,Non-interleaved DMA block transfer" "Not performed,Performed"
|
|
bitfld.long 0x1C 8.--12. " ICOUNT ,Initial count of DMA transfers" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32"
|
|
bitfld.long 0x1C 6. " COUNTBIT17 ,17th bit of the COUNT field of DMAxCOUNT register" "0,1"
|
|
newline
|
|
bitfld.long 0x1C 0.--5. " COUNT ,Actual number of remaining DMA transfers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
group.long 0xF8++0x1F
|
|
line.long 0x0 "DMA0 COUNT,MibSPI DMA0 COUNT Register"
|
|
hexmask.long.word 0x0 16.--31. 1. " ICOUNT0 ,Initial number of DMA transfers"
|
|
hexmask.long.word 0x0 0.--15. 1. " COUNT0 ,The actual number of remaining DMA transfers"
|
|
line.long 0x4 "DMA1 COUNT,MibSPI DMA1 COUNT Register"
|
|
hexmask.long.word 0x4 16.--31. 1. " ICOUNT1 ,Initial number of DMA transfers"
|
|
hexmask.long.word 0x4 0.--15. 1. " COUNT1 ,The actual number of remaining DMA transfers"
|
|
line.long 0x8 "DMA2 COUNT,MibSPI DMA2 COUNT Register"
|
|
hexmask.long.word 0x8 16.--31. 1. " ICOUNT2 ,Initial number of DMA transfers"
|
|
hexmask.long.word 0x8 0.--15. 1. " COUNT2 ,The actual number of remaining DMA transfers"
|
|
line.long 0xC "DMA3 COUNT,MibSPI DMA3 COUNT Register"
|
|
hexmask.long.word 0xC 16.--31. 1. " ICOUNT3 ,Initial number of DMA transfers"
|
|
hexmask.long.word 0xC 0.--15. 1. " COUNT3 ,The actual number of remaining DMA transfers"
|
|
line.long 0x10 "DMA4 COUNT,MibSPI DMA4 COUNT Register"
|
|
hexmask.long.word 0x10 16.--31. 1. " ICOUNT4 ,Initial number of DMA transfers"
|
|
hexmask.long.word 0x10 0.--15. 1. " COUNT4 ,The actual number of remaining DMA transfers"
|
|
line.long 0x14 "DMA5 COUNT,MibSPI DMA5 COUNT Register"
|
|
hexmask.long.word 0x14 16.--31. 1. " ICOUNT5 ,Initial number of DMA transfers"
|
|
hexmask.long.word 0x14 0.--15. 1. " COUNT5 ,The actual number of remaining DMA transfers"
|
|
line.long 0x18 "DMA6 COUNT,MibSPI DMA6 COUNT Register"
|
|
hexmask.long.word 0x18 16.--31. 1. " ICOUNT6 ,Initial number of DMA transfers"
|
|
hexmask.long.word 0x18 0.--15. 1. " COUNT6 ,The actual number of remaining DMA transfers"
|
|
line.long 0x1C "DMA7 COUNT,MibSPI DMA7 COUNT Register"
|
|
hexmask.long.word 0x1C 16.--31. 1. " ICOUNT7 ,Initial number of DMA transfers"
|
|
hexmask.long.word 0x1C 0.--15. 1. " COUNT7 ,The actual number of remaining DMA transfers"
|
|
group.long 0x118++0x03
|
|
line.long 0x00 "DMACNTLEN,MibSPI DMACNTLEN Register"
|
|
bitfld.long 0x00 0. " LARGECOUNT ,Counters select" "DMAxCTRL,DMAxCOUNT"
|
|
endif
|
|
group.long 0x120++0x03
|
|
line.long 0x00 "UERRCTRL,Uncorrectable Parity Error Control Register"
|
|
bitfld.long 0x00 8. " PTESTEN ,Parity memory test enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--3. " EDEN ,Error detection enable" "Enabled,Enabled,Enabled,Enabled,Enabled,Disabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled"
|
|
group.long 0x124++0x03
|
|
line.long 0x00 "UERRSTAT,Uncorrectable Parity Error Status Register"
|
|
eventfld.long 0x00 1. " EDFLG1 ,Uncorrectable parity error detection flag" "Not occurred,Occurred"
|
|
eventfld.long 0x00 0. " EDFLG0 ,Uncorrectable parity error detection flag" "Not occurred,Occurred"
|
|
hgroup.long 0x128++0x03
|
|
hide.long 0x00 "UERRADDR1,Uncorrectable Parity Error Address Register"
|
|
in
|
|
hgroup.long 0x12C++0x03
|
|
hide.long 0x00 "UERRADDR0,Uncorrectable Parity Error Address Register"
|
|
in
|
|
hgroup.long 0x130++0x03
|
|
hide.long 0x00 "RXOVRN_BUF_ADDR,Receive RAM Overrun Buffer Address Register"
|
|
in
|
|
sif cpuis("TMS570LS0714*")||cpuis("TMS570LS0914*")||cpuis("TMS570LS0232")
|
|
if (((per.l.be(ad:0xFFF7F400+0x134))&0x2)==0x2)
|
|
group.long 0x134++0x03
|
|
line.long 0x00 "IOLPBKTSTCR,SPI IO Loopback Test Control Register"
|
|
bitfld.long 0x00 24. " SCSFAILFLG ,Failure on SPISCS pin compare during analog loopback" "Not occurred,Occurred"
|
|
bitfld.long 0x00 20. " CTRL_BITERR ,Controls inducing of BITERR during I/O loopback test mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " CTRL_DESYNC ,Controls inducing of the desync error during I/O loopback test mode" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 18. " CTRL_PARERR ,Controls inducing of parity errors during I/O loopback test mode" "No error,Error"
|
|
bitfld.long 0x00 17. " CTRL_TIMEOUT ,Controls inducing of the timeout error during I/O loopbacK test mode" "No error,Error"
|
|
bitfld.long 0x00 16. " CTRL_DLENERR ,Controls inducing of the data length error during I/O loopback test mode" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 8.--11. " IOLPBKTSTENA ,Module I/O loopback test enable key" "Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Enabled,Disabled,Disabled,Disabled,Disabled,Disabled"
|
|
sif cpuis("TMS570LS0232")
|
|
bitfld.long 0x00 3.--5. " ERRSCSPIN ,Inject error on chip-select pin number" "/SPISCS[0],/SPISCS[1],/SPISCS[2],/SPISCS[3],?..."
|
|
else
|
|
bitfld.long 0x00 3.--5. " ERRSCSPIN ,Inject error on chip-select pin number" "/SPISCS[0],/SPISCS[1],/SPISCS[2],/SPISCS[3],/SPISCS[4],/SPISCS[5],/SPISCS[6],/SPISCS[7]"
|
|
endif
|
|
bitfld.long 0x00 2. " CTRLSCSPINERR ,Enable/disable the injection of an error on the SPISCS[3:0] pins" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 1. " LPBK_TYPE ,Module I/O loopback type (analog/digital)" "Digital,Analog"
|
|
bitfld.long 0x00 0. " RXP_ENA ,Enable analog loopback through the receive pin" "Transmit,Receive"
|
|
else
|
|
group.long 0x134++0x03
|
|
line.long 0x00 "IOLPBKTSTCR,SPI IO Loopback Test Control Register"
|
|
bitfld.long 0x00 24. " SCSFAILFLG ,Failure on SPISCS pin compare during analog loopback" "Not occurred,Occurred"
|
|
bitfld.long 0x00 20. " CTRL_BITERR ,Controls inducing of BITERR during I/O loopback test mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " CTRL_DESYNC ,Controls inducing of the desync error during I/O loopback test mode" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 18. " CTRL_PARERR ,Controls inducing of parity errors during I/O loopback test mode" "No error,Error"
|
|
bitfld.long 0x00 17. " CTRL_TIMEOUT ,Controls inducing of the timeout error during I/O loopbacK test mode" "No error,Error"
|
|
bitfld.long 0x00 16. " CTRL_DLENERR ,Controls inducing of the data length error during I/O loopback test mode" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 8.--11. " IOLPBKTSTENA ,Module I/O loopback test enable key" "Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Enabled,Disabled,Disabled,Disabled,Disabled,Disabled"
|
|
sif cpuis("TMS570LS0232")
|
|
bitfld.long 0x00 3.--5. " ERRSCSPIN ,Inject error on chip-select pin number" "/SPISCS[0],/SPISCS[1],/SPISCS[2],/SPISCS[3],?..."
|
|
else
|
|
bitfld.long 0x00 3.--5. " ERRSCSPIN ,Inject error on chip-select pin number" "/SPISCS[0],/SPISCS[1],/SPISCS[2],/SPISCS[3],/SPISCS[4],/SPISCS[5],/SPISCS[6],/SPISCS[7]"
|
|
endif
|
|
bitfld.long 0x00 2. " CTRLSCSPINERR ,Enable/disable the injection of an error on the SPISCS[3:0] pins" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 1. " LPBK_TYPE ,Module I/O loopback type (analog/digital)" "Digital,Analog"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0xFFF7F400+0x134))&0x2)==0x2)
|
|
group.long 0x134++0x03
|
|
line.long 0x00 "IOLPBKTSTCR,SPI IO Loopback Test Control Register"
|
|
bitfld.long 0x00 24. " SCSFAILFLG ,Failure on SPISCS pin compare during analog loopback" "Not occurred,Occurred"
|
|
bitfld.long 0x00 20. " CTRL_BITERR ,Controls inducing of BITERR during I/O loopback test mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " CTRL_DESYNC ,Controls inducing of the desync error during I/O loopback test mode" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 18. " CTRL_PARERR ,Controls inducing of parity errors during I/O loopback test mode" "No error,Error"
|
|
bitfld.long 0x00 17. " CTRL_TIMEOUT ,Controls inducing of the timeout error during I/O loopbacK test mode" "No error,Error"
|
|
bitfld.long 0x00 16. " CTRL_DLENERR ,Controls inducing of the data length error during I/O loopback test mode" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 8.--11. " IOLPBKTSTENA ,Module I/O loopback test enable key" "Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Enabled,Disabled,Disabled,Disabled,Disabled,Disabled"
|
|
bitfld.long 0x00 3.--5. " ERRSCSPIN ,Inject error on chip-select pin number" "/SPISCS[0],/SPISCS[1],/SPISCS[2],/SPISCS[3],/SPISCS[4],/SPISCS[5],/SPISCS[6],/SPISCS[7]"
|
|
bitfld.long 0x00 2. " CTRLSCSPINERR ,Enable/disable the injection of an error on the SPISCS[3:0] pins" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 1. " LPBK_TYPE ,Module I/O loopback type (analog/digital)" "Digital,Analog"
|
|
bitfld.long 0x00 0. " RXP_ENA ,Enable analog loopback through the receive pin" "Transmit,Receive"
|
|
else
|
|
group.long 0x134++0x03
|
|
line.long 0x00 "IOLPBKTSTCR,SPI IO Loopback Test Control Register"
|
|
bitfld.long 0x00 24. " SCSFAILFLG ,Failure on SPISCS pin compare during analog loopback" "Not occurred,Occurred"
|
|
bitfld.long 0x00 20. " CTRL_BITERR ,Controls inducing of BITERR during I/O loopback test mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " CTRL_DESYNC ,Controls inducing of the desync error during I/O loopback test mode" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 18. " CTRL_PARERR ,Controls inducing of parity errors during I/O loopback test mode" "No error,Error"
|
|
bitfld.long 0x00 17. " CTRL_TIMEOUT ,Controls inducing of the timeout error during I/O loopbacK test mode" "No error,Error"
|
|
bitfld.long 0x00 16. " CTRL_DLENERR ,Controls inducing of the data length error during I/O loopback test mode" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 8.--11. " IOLPBKTSTENA ,Module I/O loopback test enable key" "Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Enabled,Disabled,Disabled,Disabled,Disabled,Disabled"
|
|
bitfld.long 0x00 3.--5. " ERRSCSPIN ,Inject error on chip-select pin number" "/SPISCS[0],/SPISCS[1],/SPISCS[2],/SPISCS[3],/SPISCS[4],/SPISCS[5],/SPISCS[6],/SPISCS[7]"
|
|
bitfld.long 0x00 2. " CTRLSCSPINERR ,Enable/disable the injection of an error on the SPISCS[3:0] pins" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 1. " LPBK_TYPE ,Module I/O loopback type (analog/digital)" "Digital,Analog"
|
|
endif
|
|
endif
|
|
sif (cpu()=="TMS570LC4357"||cpu()==("TMS570LS0332")||cpu()==("TMS570LS0432")||cpuis("TMS570LS1114*")||cpuis("TMS570LS1115*")||cpuis("TMS570LS1224*")||cpuis("TMS570LS1225*")||cpuis("TMS570LS1227*")||cpuis("TMS570LS0232")||cpuis("TMS570LS0714*")||cpuis("TMS570LS0914*"))
|
|
width 21.
|
|
newline
|
|
group.long 0x138++0x07
|
|
line.long 0x00 "EXTENDED_PRESCALE_1, SPI Extended Prescale Register 1"
|
|
hexmask.long.word 0x00 16.--26. 1. " EPRESCALE_FMT1 , Extended Prescale value for SPIFMT1"
|
|
hexmask.long.word 0x00 0.--10. 1. " EPRESCALE_FMT0 , Extended Prescale value for SPIFMT0"
|
|
line.long 0x04 "EXTENDED_PRESCALE_2, SPI Extended Prescale Register 2"
|
|
hexmask.long.word 0x04 16.--26. 1. " EPRESCALE_FMT3 , Extended Prescale value for SPIFMT3"
|
|
hexmask.long.word 0x04 0.--10. 1. " EPRESCALE_FMT2 , Extended Prescale value for SPIFMT2"
|
|
endif
|
|
sif !cpuis("TMS570LS0232")&&!cpuis("TMS570LS0714*")&&!cpuis("TMS570LS0914*")
|
|
sif (cpu()=="TMS570LC4357"||cpu()==("TMS570LS0332")||cpu()==("TMS570LS0432")||cpuis("TMS570LS1114*")||cpuis("TMS570LS1115*")||cpuis("TMS570LS1224*")||cpuis("TMS570LS1225*")||cpuis("TMS570LS1227*"))
|
|
sif cpuis("TMS570LC4357")
|
|
group.long 0x140++0x03
|
|
line.long 0x00 "ECCDIAG_CTRL, ECC Diagnostic Control register"
|
|
bitfld.long 0x00 0.--3. " ECCDIAG_EN , ECC Diagnostic mode Enable Key bits" "Disabled,Disabled,Disabled,Disabled,Disabled,Enabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled"
|
|
endif
|
|
if ((per.l(ad:0xFFF7F400+0x140)&0x5)==0x5)
|
|
group.long 0x144++0x03
|
|
line.long 0x00 "ECCDIAG_STAT, ECC Diagnostic Status register"
|
|
eventfld.long 0x00 17. " DEFLG[1] , Double bit Error is detected for RXRAM" "No error,Error"
|
|
eventfld.long 0x00 16. " DEFLG[0] , Double bit Error is detected for TXRAM" "No error,Error"
|
|
eventfld.long 0x00 1. " SEFLG[1] , Single bit Error is detected for RXRAM" "No error,Error"
|
|
eventfld.long 0x00 0. " SEFLG[0] , Single bit Error is detected for TXRAM" "No error,Error"
|
|
else
|
|
hgroup.long 0x144++0x03
|
|
hide.long 0x00 "ECCDIAG_STAT, ECC Diagnostic Status register"
|
|
in
|
|
endif
|
|
hgroup.long 0x148++0x03
|
|
hide.long 0x00 "SBERRADDR1, Single Bit Error Address Register - RXRAM"
|
|
in
|
|
hgroup.long 0x14C++0x03
|
|
hide.long 0x00 "SBERRADDR0, Single Bit Error Address Register - TXRAM"
|
|
in
|
|
endif
|
|
endif
|
|
sif cpuis("TMS570LS0232")||cpuis("TMS570LS0714*")||cpuis("TMS570LS0914*")
|
|
endian.be
|
|
endif
|
|
width 0xB
|
|
tree.end
|
|
tree "MibSPI1 RAM"
|
|
base ad:0xFF0E0000
|
|
sif cpuis("TMS570LS0232")||cpuis("TMS570LS0714*")||cpuis("TMS570LS0914*")
|
|
endian.be
|
|
endif
|
|
width 11.
|
|
sif (cpu()==("TMS570LS0332")||cpu()==("TMS570LS0432")||cpuis("TMS570LS1114*")||cpuis("TMS570LS1115*")||cpuis("TMS570LS1224*")||cpuis("TMS570LS1225*")||cpuis("TMS570LS1227*"))
|
|
group.long 0x0++0x03
|
|
line.long 0x00 "TXRAM, Multi-buffer RAM Transmit Data Register 0"
|
|
bitfld.long 0x00 29.--31. " BUFMODE , Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip Single Transfer,Skip Overwrite,Skip ST-Overwrite,Continuous,Suspend Single Transfer,Suspend Overwrite,Suspend ST-Overwrite"
|
|
bitfld.long 0x00 28. " CSHOLD , Chip select hold mode" "Deactivated,Activated"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK , Lock two consecutive buffer words" "0,1"
|
|
bitfld.long 0x00 26. " WDEL , Enable the delay counter at the end of the current transaction" "Disable,Enable"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL , Data word format select" "Format 0,Format 1,Format 2,Format 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR , Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA , Transfer data"
|
|
group.long 0x4++0x03
|
|
line.long 0x00 "TXRAM, Multi-buffer RAM Transmit Data Register 1"
|
|
bitfld.long 0x00 29.--31. " BUFMODE , Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip Single Transfer,Skip Overwrite,Skip ST-Overwrite,Continuous,Suspend Single Transfer,Suspend Overwrite,Suspend ST-Overwrite"
|
|
bitfld.long 0x00 28. " CSHOLD , Chip select hold mode" "Deactivated,Activated"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK , Lock two consecutive buffer words" "0,1"
|
|
bitfld.long 0x00 26. " WDEL , Enable the delay counter at the end of the current transaction" "Disable,Enable"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL , Data word format select" "Format 0,Format 1,Format 2,Format 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR , Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA , Transfer data"
|
|
group.long 0x8++0x03
|
|
line.long 0x00 "TXRAM, Multi-buffer RAM Transmit Data Register 2"
|
|
bitfld.long 0x00 29.--31. " BUFMODE , Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip Single Transfer,Skip Overwrite,Skip ST-Overwrite,Continuous,Suspend Single Transfer,Suspend Overwrite,Suspend ST-Overwrite"
|
|
bitfld.long 0x00 28. " CSHOLD , Chip select hold mode" "Deactivated,Activated"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK , Lock two consecutive buffer words" "0,1"
|
|
bitfld.long 0x00 26. " WDEL , Enable the delay counter at the end of the current transaction" "Disable,Enable"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL , Data word format select" "Format 0,Format 1,Format 2,Format 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR , Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA , Transfer data"
|
|
group.long 0xC++0x03
|
|
line.long 0x00 "TXRAM, Multi-buffer RAM Transmit Data Register 3"
|
|
bitfld.long 0x00 29.--31. " BUFMODE , Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip Single Transfer,Skip Overwrite,Skip ST-Overwrite,Continuous,Suspend Single Transfer,Suspend Overwrite,Suspend ST-Overwrite"
|
|
bitfld.long 0x00 28. " CSHOLD , Chip select hold mode" "Deactivated,Activated"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK , Lock two consecutive buffer words" "0,1"
|
|
bitfld.long 0x00 26. " WDEL , Enable the delay counter at the end of the current transaction" "Disable,Enable"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL , Data word format select" "Format 0,Format 1,Format 2,Format 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR , Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA , Transfer data"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "TXRAM, Multi-buffer RAM Transmit Data Register 4"
|
|
bitfld.long 0x00 29.--31. " BUFMODE , Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip Single Transfer,Skip Overwrite,Skip ST-Overwrite,Continuous,Suspend Single Transfer,Suspend Overwrite,Suspend ST-Overwrite"
|
|
bitfld.long 0x00 28. " CSHOLD , Chip select hold mode" "Deactivated,Activated"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK , Lock two consecutive buffer words" "0,1"
|
|
bitfld.long 0x00 26. " WDEL , Enable the delay counter at the end of the current transaction" "Disable,Enable"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL , Data word format select" "Format 0,Format 1,Format 2,Format 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR , Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA , Transfer data"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "TXRAM, Multi-buffer RAM Transmit Data Register 5"
|
|
bitfld.long 0x00 29.--31. " BUFMODE , Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip Single Transfer,Skip Overwrite,Skip ST-Overwrite,Continuous,Suspend Single Transfer,Suspend Overwrite,Suspend ST-Overwrite"
|
|
bitfld.long 0x00 28. " CSHOLD , Chip select hold mode" "Deactivated,Activated"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK , Lock two consecutive buffer words" "0,1"
|
|
bitfld.long 0x00 26. " WDEL , Enable the delay counter at the end of the current transaction" "Disable,Enable"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL , Data word format select" "Format 0,Format 1,Format 2,Format 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR , Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA , Transfer data"
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "TXRAM, Multi-buffer RAM Transmit Data Register 6"
|
|
bitfld.long 0x00 29.--31. " BUFMODE , Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip Single Transfer,Skip Overwrite,Skip ST-Overwrite,Continuous,Suspend Single Transfer,Suspend Overwrite,Suspend ST-Overwrite"
|
|
bitfld.long 0x00 28. " CSHOLD , Chip select hold mode" "Deactivated,Activated"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK , Lock two consecutive buffer words" "0,1"
|
|
bitfld.long 0x00 26. " WDEL , Enable the delay counter at the end of the current transaction" "Disable,Enable"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL , Data word format select" "Format 0,Format 1,Format 2,Format 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR , Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA , Transfer data"
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "TXRAM, Multi-buffer RAM Transmit Data Register 7"
|
|
bitfld.long 0x00 29.--31. " BUFMODE , Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip Single Transfer,Skip Overwrite,Skip ST-Overwrite,Continuous,Suspend Single Transfer,Suspend Overwrite,Suspend ST-Overwrite"
|
|
bitfld.long 0x00 28. " CSHOLD , Chip select hold mode" "Deactivated,Activated"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK , Lock two consecutive buffer words" "0,1"
|
|
bitfld.long 0x00 26. " WDEL , Enable the delay counter at the end of the current transaction" "Disable,Enable"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL , Data word format select" "Format 0,Format 1,Format 2,Format 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR , Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA , Transfer data"
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "TXRAM, Multi-buffer RAM Transmit Data Register 8"
|
|
bitfld.long 0x00 29.--31. " BUFMODE , Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip Single Transfer,Skip Overwrite,Skip ST-Overwrite,Continuous,Suspend Single Transfer,Suspend Overwrite,Suspend ST-Overwrite"
|
|
bitfld.long 0x00 28. " CSHOLD , Chip select hold mode" "Deactivated,Activated"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK , Lock two consecutive buffer words" "0,1"
|
|
bitfld.long 0x00 26. " WDEL , Enable the delay counter at the end of the current transaction" "Disable,Enable"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL , Data word format select" "Format 0,Format 1,Format 2,Format 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR , Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA , Transfer data"
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "TXRAM, Multi-buffer RAM Transmit Data Register 9"
|
|
bitfld.long 0x00 29.--31. " BUFMODE , Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip Single Transfer,Skip Overwrite,Skip ST-Overwrite,Continuous,Suspend Single Transfer,Suspend Overwrite,Suspend ST-Overwrite"
|
|
bitfld.long 0x00 28. " CSHOLD , Chip select hold mode" "Deactivated,Activated"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK , Lock two consecutive buffer words" "0,1"
|
|
bitfld.long 0x00 26. " WDEL , Enable the delay counter at the end of the current transaction" "Disable,Enable"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL , Data word format select" "Format 0,Format 1,Format 2,Format 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR , Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA , Transfer data"
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "TXRAM, Multi-buffer RAM Transmit Data Register 10"
|
|
bitfld.long 0x00 29.--31. " BUFMODE , Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip Single Transfer,Skip Overwrite,Skip ST-Overwrite,Continuous,Suspend Single Transfer,Suspend Overwrite,Suspend ST-Overwrite"
|
|
bitfld.long 0x00 28. " CSHOLD , Chip select hold mode" "Deactivated,Activated"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK , Lock two consecutive buffer words" "0,1"
|
|
bitfld.long 0x00 26. " WDEL , Enable the delay counter at the end of the current transaction" "Disable,Enable"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL , Data word format select" "Format 0,Format 1,Format 2,Format 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR , Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA , Transfer data"
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "TXRAM, Multi-buffer RAM Transmit Data Register 11"
|
|
bitfld.long 0x00 29.--31. " BUFMODE , Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip Single Transfer,Skip Overwrite,Skip ST-Overwrite,Continuous,Suspend Single Transfer,Suspend Overwrite,Suspend ST-Overwrite"
|
|
bitfld.long 0x00 28. " CSHOLD , Chip select hold mode" "Deactivated,Activated"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK , Lock two consecutive buffer words" "0,1"
|
|
bitfld.long 0x00 26. " WDEL , Enable the delay counter at the end of the current transaction" "Disable,Enable"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL , Data word format select" "Format 0,Format 1,Format 2,Format 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR , Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA , Transfer data"
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "TXRAM, Multi-buffer RAM Transmit Data Register 12"
|
|
bitfld.long 0x00 29.--31. " BUFMODE , Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip Single Transfer,Skip Overwrite,Skip ST-Overwrite,Continuous,Suspend Single Transfer,Suspend Overwrite,Suspend ST-Overwrite"
|
|
bitfld.long 0x00 28. " CSHOLD , Chip select hold mode" "Deactivated,Activated"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK , Lock two consecutive buffer words" "0,1"
|
|
bitfld.long 0x00 26. " WDEL , Enable the delay counter at the end of the current transaction" "Disable,Enable"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL , Data word format select" "Format 0,Format 1,Format 2,Format 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR , Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA , Transfer data"
|
|
group.long 0x34++0x03
|
|
line.long 0x00 "TXRAM, Multi-buffer RAM Transmit Data Register 13"
|
|
bitfld.long 0x00 29.--31. " BUFMODE , Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip Single Transfer,Skip Overwrite,Skip ST-Overwrite,Continuous,Suspend Single Transfer,Suspend Overwrite,Suspend ST-Overwrite"
|
|
bitfld.long 0x00 28. " CSHOLD , Chip select hold mode" "Deactivated,Activated"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK , Lock two consecutive buffer words" "0,1"
|
|
bitfld.long 0x00 26. " WDEL , Enable the delay counter at the end of the current transaction" "Disable,Enable"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL , Data word format select" "Format 0,Format 1,Format 2,Format 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR , Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA , Transfer data"
|
|
group.long 0x38++0x03
|
|
line.long 0x00 "TXRAM, Multi-buffer RAM Transmit Data Register 14"
|
|
bitfld.long 0x00 29.--31. " BUFMODE , Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip Single Transfer,Skip Overwrite,Skip ST-Overwrite,Continuous,Suspend Single Transfer,Suspend Overwrite,Suspend ST-Overwrite"
|
|
bitfld.long 0x00 28. " CSHOLD , Chip select hold mode" "Deactivated,Activated"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK , Lock two consecutive buffer words" "0,1"
|
|
bitfld.long 0x00 26. " WDEL , Enable the delay counter at the end of the current transaction" "Disable,Enable"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL , Data word format select" "Format 0,Format 1,Format 2,Format 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR , Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA , Transfer data"
|
|
group.long 0x3C++0x03
|
|
line.long 0x00 "TXRAM, Multi-buffer RAM Transmit Data Register 15"
|
|
bitfld.long 0x00 29.--31. " BUFMODE , Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip Single Transfer,Skip Overwrite,Skip ST-Overwrite,Continuous,Suspend Single Transfer,Suspend Overwrite,Suspend ST-Overwrite"
|
|
bitfld.long 0x00 28. " CSHOLD , Chip select hold mode" "Deactivated,Activated"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK , Lock two consecutive buffer words" "0,1"
|
|
bitfld.long 0x00 26. " WDEL , Enable the delay counter at the end of the current transaction" "Disable,Enable"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL , Data word format select" "Format 0,Format 1,Format 2,Format 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR , Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA , Transfer data"
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "TXRAM, Multi-buffer RAM Transmit Data Register 16"
|
|
bitfld.long 0x00 29.--31. " BUFMODE , Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip Single Transfer,Skip Overwrite,Skip ST-Overwrite,Continuous,Suspend Single Transfer,Suspend Overwrite,Suspend ST-Overwrite"
|
|
bitfld.long 0x00 28. " CSHOLD , Chip select hold mode" "Deactivated,Activated"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK , Lock two consecutive buffer words" "0,1"
|
|
bitfld.long 0x00 26. " WDEL , Enable the delay counter at the end of the current transaction" "Disable,Enable"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL , Data word format select" "Format 0,Format 1,Format 2,Format 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR , Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA , Transfer data"
|
|
group.long 0x44++0x03
|
|
line.long 0x00 "TXRAM, Multi-buffer RAM Transmit Data Register 17"
|
|
bitfld.long 0x00 29.--31. " BUFMODE , Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip Single Transfer,Skip Overwrite,Skip ST-Overwrite,Continuous,Suspend Single Transfer,Suspend Overwrite,Suspend ST-Overwrite"
|
|
bitfld.long 0x00 28. " CSHOLD , Chip select hold mode" "Deactivated,Activated"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK , Lock two consecutive buffer words" "0,1"
|
|
bitfld.long 0x00 26. " WDEL , Enable the delay counter at the end of the current transaction" "Disable,Enable"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL , Data word format select" "Format 0,Format 1,Format 2,Format 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR , Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA , Transfer data"
|
|
group.long 0x48++0x03
|
|
line.long 0x00 "TXRAM, Multi-buffer RAM Transmit Data Register 18"
|
|
bitfld.long 0x00 29.--31. " BUFMODE , Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip Single Transfer,Skip Overwrite,Skip ST-Overwrite,Continuous,Suspend Single Transfer,Suspend Overwrite,Suspend ST-Overwrite"
|
|
bitfld.long 0x00 28. " CSHOLD , Chip select hold mode" "Deactivated,Activated"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK , Lock two consecutive buffer words" "0,1"
|
|
bitfld.long 0x00 26. " WDEL , Enable the delay counter at the end of the current transaction" "Disable,Enable"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL , Data word format select" "Format 0,Format 1,Format 2,Format 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR , Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA , Transfer data"
|
|
group.long 0x4C++0x03
|
|
line.long 0x00 "TXRAM, Multi-buffer RAM Transmit Data Register 19"
|
|
bitfld.long 0x00 29.--31. " BUFMODE , Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip Single Transfer,Skip Overwrite,Skip ST-Overwrite,Continuous,Suspend Single Transfer,Suspend Overwrite,Suspend ST-Overwrite"
|
|
bitfld.long 0x00 28. " CSHOLD , Chip select hold mode" "Deactivated,Activated"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK , Lock two consecutive buffer words" "0,1"
|
|
bitfld.long 0x00 26. " WDEL , Enable the delay counter at the end of the current transaction" "Disable,Enable"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL , Data word format select" "Format 0,Format 1,Format 2,Format 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR , Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA , Transfer data"
|
|
group.long 0x50++0x03
|
|
line.long 0x00 "TXRAM, Multi-buffer RAM Transmit Data Register 20"
|
|
bitfld.long 0x00 29.--31. " BUFMODE , Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip Single Transfer,Skip Overwrite,Skip ST-Overwrite,Continuous,Suspend Single Transfer,Suspend Overwrite,Suspend ST-Overwrite"
|
|
bitfld.long 0x00 28. " CSHOLD , Chip select hold mode" "Deactivated,Activated"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK , Lock two consecutive buffer words" "0,1"
|
|
bitfld.long 0x00 26. " WDEL , Enable the delay counter at the end of the current transaction" "Disable,Enable"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL , Data word format select" "Format 0,Format 1,Format 2,Format 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR , Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA , Transfer data"
|
|
group.long 0x54++0x03
|
|
line.long 0x00 "TXRAM, Multi-buffer RAM Transmit Data Register 21"
|
|
bitfld.long 0x00 29.--31. " BUFMODE , Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip Single Transfer,Skip Overwrite,Skip ST-Overwrite,Continuous,Suspend Single Transfer,Suspend Overwrite,Suspend ST-Overwrite"
|
|
bitfld.long 0x00 28. " CSHOLD , Chip select hold mode" "Deactivated,Activated"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK , Lock two consecutive buffer words" "0,1"
|
|
bitfld.long 0x00 26. " WDEL , Enable the delay counter at the end of the current transaction" "Disable,Enable"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL , Data word format select" "Format 0,Format 1,Format 2,Format 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR , Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA , Transfer data"
|
|
group.long 0x58++0x03
|
|
line.long 0x00 "TXRAM, Multi-buffer RAM Transmit Data Register 22"
|
|
bitfld.long 0x00 29.--31. " BUFMODE , Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip Single Transfer,Skip Overwrite,Skip ST-Overwrite,Continuous,Suspend Single Transfer,Suspend Overwrite,Suspend ST-Overwrite"
|
|
bitfld.long 0x00 28. " CSHOLD , Chip select hold mode" "Deactivated,Activated"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK , Lock two consecutive buffer words" "0,1"
|
|
bitfld.long 0x00 26. " WDEL , Enable the delay counter at the end of the current transaction" "Disable,Enable"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL , Data word format select" "Format 0,Format 1,Format 2,Format 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR , Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA , Transfer data"
|
|
group.long 0x5C++0x03
|
|
line.long 0x00 "TXRAM, Multi-buffer RAM Transmit Data Register 23"
|
|
bitfld.long 0x00 29.--31. " BUFMODE , Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip Single Transfer,Skip Overwrite,Skip ST-Overwrite,Continuous,Suspend Single Transfer,Suspend Overwrite,Suspend ST-Overwrite"
|
|
bitfld.long 0x00 28. " CSHOLD , Chip select hold mode" "Deactivated,Activated"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK , Lock two consecutive buffer words" "0,1"
|
|
bitfld.long 0x00 26. " WDEL , Enable the delay counter at the end of the current transaction" "Disable,Enable"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL , Data word format select" "Format 0,Format 1,Format 2,Format 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR , Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA , Transfer data"
|
|
group.long 0x60++0x03
|
|
line.long 0x00 "TXRAM, Multi-buffer RAM Transmit Data Register 24"
|
|
bitfld.long 0x00 29.--31. " BUFMODE , Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip Single Transfer,Skip Overwrite,Skip ST-Overwrite,Continuous,Suspend Single Transfer,Suspend Overwrite,Suspend ST-Overwrite"
|
|
bitfld.long 0x00 28. " CSHOLD , Chip select hold mode" "Deactivated,Activated"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK , Lock two consecutive buffer words" "0,1"
|
|
bitfld.long 0x00 26. " WDEL , Enable the delay counter at the end of the current transaction" "Disable,Enable"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL , Data word format select" "Format 0,Format 1,Format 2,Format 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR , Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA , Transfer data"
|
|
group.long 0x64++0x03
|
|
line.long 0x00 "TXRAM, Multi-buffer RAM Transmit Data Register 25"
|
|
bitfld.long 0x00 29.--31. " BUFMODE , Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip Single Transfer,Skip Overwrite,Skip ST-Overwrite,Continuous,Suspend Single Transfer,Suspend Overwrite,Suspend ST-Overwrite"
|
|
bitfld.long 0x00 28. " CSHOLD , Chip select hold mode" "Deactivated,Activated"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK , Lock two consecutive buffer words" "0,1"
|
|
bitfld.long 0x00 26. " WDEL , Enable the delay counter at the end of the current transaction" "Disable,Enable"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL , Data word format select" "Format 0,Format 1,Format 2,Format 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR , Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA , Transfer data"
|
|
group.long 0x68++0x03
|
|
line.long 0x00 "TXRAM, Multi-buffer RAM Transmit Data Register 26"
|
|
bitfld.long 0x00 29.--31. " BUFMODE , Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip Single Transfer,Skip Overwrite,Skip ST-Overwrite,Continuous,Suspend Single Transfer,Suspend Overwrite,Suspend ST-Overwrite"
|
|
bitfld.long 0x00 28. " CSHOLD , Chip select hold mode" "Deactivated,Activated"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK , Lock two consecutive buffer words" "0,1"
|
|
bitfld.long 0x00 26. " WDEL , Enable the delay counter at the end of the current transaction" "Disable,Enable"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL , Data word format select" "Format 0,Format 1,Format 2,Format 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR , Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA , Transfer data"
|
|
group.long 0x6C++0x03
|
|
line.long 0x00 "TXRAM, Multi-buffer RAM Transmit Data Register 27"
|
|
bitfld.long 0x00 29.--31. " BUFMODE , Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip Single Transfer,Skip Overwrite,Skip ST-Overwrite,Continuous,Suspend Single Transfer,Suspend Overwrite,Suspend ST-Overwrite"
|
|
bitfld.long 0x00 28. " CSHOLD , Chip select hold mode" "Deactivated,Activated"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK , Lock two consecutive buffer words" "0,1"
|
|
bitfld.long 0x00 26. " WDEL , Enable the delay counter at the end of the current transaction" "Disable,Enable"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL , Data word format select" "Format 0,Format 1,Format 2,Format 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR , Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA , Transfer data"
|
|
group.long 0x70++0x03
|
|
line.long 0x00 "TXRAM, Multi-buffer RAM Transmit Data Register 28"
|
|
bitfld.long 0x00 29.--31. " BUFMODE , Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip Single Transfer,Skip Overwrite,Skip ST-Overwrite,Continuous,Suspend Single Transfer,Suspend Overwrite,Suspend ST-Overwrite"
|
|
bitfld.long 0x00 28. " CSHOLD , Chip select hold mode" "Deactivated,Activated"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK , Lock two consecutive buffer words" "0,1"
|
|
bitfld.long 0x00 26. " WDEL , Enable the delay counter at the end of the current transaction" "Disable,Enable"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL , Data word format select" "Format 0,Format 1,Format 2,Format 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR , Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA , Transfer data"
|
|
group.long 0x74++0x03
|
|
line.long 0x00 "TXRAM, Multi-buffer RAM Transmit Data Register 29"
|
|
bitfld.long 0x00 29.--31. " BUFMODE , Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip Single Transfer,Skip Overwrite,Skip ST-Overwrite,Continuous,Suspend Single Transfer,Suspend Overwrite,Suspend ST-Overwrite"
|
|
bitfld.long 0x00 28. " CSHOLD , Chip select hold mode" "Deactivated,Activated"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK , Lock two consecutive buffer words" "0,1"
|
|
bitfld.long 0x00 26. " WDEL , Enable the delay counter at the end of the current transaction" "Disable,Enable"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL , Data word format select" "Format 0,Format 1,Format 2,Format 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR , Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA , Transfer data"
|
|
group.long 0x78++0x03
|
|
line.long 0x00 "TXRAM, Multi-buffer RAM Transmit Data Register 30"
|
|
bitfld.long 0x00 29.--31. " BUFMODE , Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip Single Transfer,Skip Overwrite,Skip ST-Overwrite,Continuous,Suspend Single Transfer,Suspend Overwrite,Suspend ST-Overwrite"
|
|
bitfld.long 0x00 28. " CSHOLD , Chip select hold mode" "Deactivated,Activated"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK , Lock two consecutive buffer words" "0,1"
|
|
bitfld.long 0x00 26. " WDEL , Enable the delay counter at the end of the current transaction" "Disable,Enable"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL , Data word format select" "Format 0,Format 1,Format 2,Format 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR , Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA , Transfer data"
|
|
group.long 0x7C++0x03
|
|
line.long 0x00 "TXRAM, Multi-buffer RAM Transmit Data Register 31"
|
|
bitfld.long 0x00 29.--31. " BUFMODE , Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip Single Transfer,Skip Overwrite,Skip ST-Overwrite,Continuous,Suspend Single Transfer,Suspend Overwrite,Suspend ST-Overwrite"
|
|
bitfld.long 0x00 28. " CSHOLD , Chip select hold mode" "Deactivated,Activated"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK , Lock two consecutive buffer words" "0,1"
|
|
bitfld.long 0x00 26. " WDEL , Enable the delay counter at the end of the current transaction" "Disable,Enable"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL , Data word format select" "Format 0,Format 1,Format 2,Format 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR , Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA , Transfer data"
|
|
group.long 0x80++0x03
|
|
line.long 0x00 "TXRAM, Multi-buffer RAM Transmit Data Register 32"
|
|
bitfld.long 0x00 29.--31. " BUFMODE , Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip Single Transfer,Skip Overwrite,Skip ST-Overwrite,Continuous,Suspend Single Transfer,Suspend Overwrite,Suspend ST-Overwrite"
|
|
bitfld.long 0x00 28. " CSHOLD , Chip select hold mode" "Deactivated,Activated"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK , Lock two consecutive buffer words" "0,1"
|
|
bitfld.long 0x00 26. " WDEL , Enable the delay counter at the end of the current transaction" "Disable,Enable"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL , Data word format select" "Format 0,Format 1,Format 2,Format 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR , Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA , Transfer data"
|
|
group.long 0x84++0x03
|
|
line.long 0x00 "TXRAM, Multi-buffer RAM Transmit Data Register 33"
|
|
bitfld.long 0x00 29.--31. " BUFMODE , Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip Single Transfer,Skip Overwrite,Skip ST-Overwrite,Continuous,Suspend Single Transfer,Suspend Overwrite,Suspend ST-Overwrite"
|
|
bitfld.long 0x00 28. " CSHOLD , Chip select hold mode" "Deactivated,Activated"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK , Lock two consecutive buffer words" "0,1"
|
|
bitfld.long 0x00 26. " WDEL , Enable the delay counter at the end of the current transaction" "Disable,Enable"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL , Data word format select" "Format 0,Format 1,Format 2,Format 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR , Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA , Transfer data"
|
|
group.long 0x88++0x03
|
|
line.long 0x00 "TXRAM, Multi-buffer RAM Transmit Data Register 34"
|
|
bitfld.long 0x00 29.--31. " BUFMODE , Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip Single Transfer,Skip Overwrite,Skip ST-Overwrite,Continuous,Suspend Single Transfer,Suspend Overwrite,Suspend ST-Overwrite"
|
|
bitfld.long 0x00 28. " CSHOLD , Chip select hold mode" "Deactivated,Activated"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK , Lock two consecutive buffer words" "0,1"
|
|
bitfld.long 0x00 26. " WDEL , Enable the delay counter at the end of the current transaction" "Disable,Enable"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL , Data word format select" "Format 0,Format 1,Format 2,Format 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR , Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA , Transfer data"
|
|
group.long 0x8C++0x03
|
|
line.long 0x00 "TXRAM, Multi-buffer RAM Transmit Data Register 35"
|
|
bitfld.long 0x00 29.--31. " BUFMODE , Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip Single Transfer,Skip Overwrite,Skip ST-Overwrite,Continuous,Suspend Single Transfer,Suspend Overwrite,Suspend ST-Overwrite"
|
|
bitfld.long 0x00 28. " CSHOLD , Chip select hold mode" "Deactivated,Activated"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK , Lock two consecutive buffer words" "0,1"
|
|
bitfld.long 0x00 26. " WDEL , Enable the delay counter at the end of the current transaction" "Disable,Enable"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL , Data word format select" "Format 0,Format 1,Format 2,Format 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR , Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA , Transfer data"
|
|
group.long 0x90++0x03
|
|
line.long 0x00 "TXRAM, Multi-buffer RAM Transmit Data Register 36"
|
|
bitfld.long 0x00 29.--31. " BUFMODE , Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip Single Transfer,Skip Overwrite,Skip ST-Overwrite,Continuous,Suspend Single Transfer,Suspend Overwrite,Suspend ST-Overwrite"
|
|
bitfld.long 0x00 28. " CSHOLD , Chip select hold mode" "Deactivated,Activated"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK , Lock two consecutive buffer words" "0,1"
|
|
bitfld.long 0x00 26. " WDEL , Enable the delay counter at the end of the current transaction" "Disable,Enable"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL , Data word format select" "Format 0,Format 1,Format 2,Format 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR , Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA , Transfer data"
|
|
group.long 0x94++0x03
|
|
line.long 0x00 "TXRAM, Multi-buffer RAM Transmit Data Register 37"
|
|
bitfld.long 0x00 29.--31. " BUFMODE , Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip Single Transfer,Skip Overwrite,Skip ST-Overwrite,Continuous,Suspend Single Transfer,Suspend Overwrite,Suspend ST-Overwrite"
|
|
bitfld.long 0x00 28. " CSHOLD , Chip select hold mode" "Deactivated,Activated"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK , Lock two consecutive buffer words" "0,1"
|
|
bitfld.long 0x00 26. " WDEL , Enable the delay counter at the end of the current transaction" "Disable,Enable"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL , Data word format select" "Format 0,Format 1,Format 2,Format 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR , Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA , Transfer data"
|
|
group.long 0x98++0x03
|
|
line.long 0x00 "TXRAM, Multi-buffer RAM Transmit Data Register 38"
|
|
bitfld.long 0x00 29.--31. " BUFMODE , Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip Single Transfer,Skip Overwrite,Skip ST-Overwrite,Continuous,Suspend Single Transfer,Suspend Overwrite,Suspend ST-Overwrite"
|
|
bitfld.long 0x00 28. " CSHOLD , Chip select hold mode" "Deactivated,Activated"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK , Lock two consecutive buffer words" "0,1"
|
|
bitfld.long 0x00 26. " WDEL , Enable the delay counter at the end of the current transaction" "Disable,Enable"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL , Data word format select" "Format 0,Format 1,Format 2,Format 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR , Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA , Transfer data"
|
|
group.long 0x9C++0x03
|
|
line.long 0x00 "TXRAM, Multi-buffer RAM Transmit Data Register 39"
|
|
bitfld.long 0x00 29.--31. " BUFMODE , Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip Single Transfer,Skip Overwrite,Skip ST-Overwrite,Continuous,Suspend Single Transfer,Suspend Overwrite,Suspend ST-Overwrite"
|
|
bitfld.long 0x00 28. " CSHOLD , Chip select hold mode" "Deactivated,Activated"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK , Lock two consecutive buffer words" "0,1"
|
|
bitfld.long 0x00 26. " WDEL , Enable the delay counter at the end of the current transaction" "Disable,Enable"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL , Data word format select" "Format 0,Format 1,Format 2,Format 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR , Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA , Transfer data"
|
|
group.long 0xA0++0x03
|
|
line.long 0x00 "TXRAM, Multi-buffer RAM Transmit Data Register 40"
|
|
bitfld.long 0x00 29.--31. " BUFMODE , Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip Single Transfer,Skip Overwrite,Skip ST-Overwrite,Continuous,Suspend Single Transfer,Suspend Overwrite,Suspend ST-Overwrite"
|
|
bitfld.long 0x00 28. " CSHOLD , Chip select hold mode" "Deactivated,Activated"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK , Lock two consecutive buffer words" "0,1"
|
|
bitfld.long 0x00 26. " WDEL , Enable the delay counter at the end of the current transaction" "Disable,Enable"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL , Data word format select" "Format 0,Format 1,Format 2,Format 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR , Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA , Transfer data"
|
|
group.long 0xA4++0x03
|
|
line.long 0x00 "TXRAM, Multi-buffer RAM Transmit Data Register 41"
|
|
bitfld.long 0x00 29.--31. " BUFMODE , Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip Single Transfer,Skip Overwrite,Skip ST-Overwrite,Continuous,Suspend Single Transfer,Suspend Overwrite,Suspend ST-Overwrite"
|
|
bitfld.long 0x00 28. " CSHOLD , Chip select hold mode" "Deactivated,Activated"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK , Lock two consecutive buffer words" "0,1"
|
|
bitfld.long 0x00 26. " WDEL , Enable the delay counter at the end of the current transaction" "Disable,Enable"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL , Data word format select" "Format 0,Format 1,Format 2,Format 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR , Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA , Transfer data"
|
|
group.long 0xA8++0x03
|
|
line.long 0x00 "TXRAM, Multi-buffer RAM Transmit Data Register 42"
|
|
bitfld.long 0x00 29.--31. " BUFMODE , Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip Single Transfer,Skip Overwrite,Skip ST-Overwrite,Continuous,Suspend Single Transfer,Suspend Overwrite,Suspend ST-Overwrite"
|
|
bitfld.long 0x00 28. " CSHOLD , Chip select hold mode" "Deactivated,Activated"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK , Lock two consecutive buffer words" "0,1"
|
|
bitfld.long 0x00 26. " WDEL , Enable the delay counter at the end of the current transaction" "Disable,Enable"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL , Data word format select" "Format 0,Format 1,Format 2,Format 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR , Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA , Transfer data"
|
|
group.long 0xAC++0x03
|
|
line.long 0x00 "TXRAM, Multi-buffer RAM Transmit Data Register 43"
|
|
bitfld.long 0x00 29.--31. " BUFMODE , Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip Single Transfer,Skip Overwrite,Skip ST-Overwrite,Continuous,Suspend Single Transfer,Suspend Overwrite,Suspend ST-Overwrite"
|
|
bitfld.long 0x00 28. " CSHOLD , Chip select hold mode" "Deactivated,Activated"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK , Lock two consecutive buffer words" "0,1"
|
|
bitfld.long 0x00 26. " WDEL , Enable the delay counter at the end of the current transaction" "Disable,Enable"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL , Data word format select" "Format 0,Format 1,Format 2,Format 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR , Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA , Transfer data"
|
|
group.long 0xB0++0x03
|
|
line.long 0x00 "TXRAM, Multi-buffer RAM Transmit Data Register 44"
|
|
bitfld.long 0x00 29.--31. " BUFMODE , Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip Single Transfer,Skip Overwrite,Skip ST-Overwrite,Continuous,Suspend Single Transfer,Suspend Overwrite,Suspend ST-Overwrite"
|
|
bitfld.long 0x00 28. " CSHOLD , Chip select hold mode" "Deactivated,Activated"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK , Lock two consecutive buffer words" "0,1"
|
|
bitfld.long 0x00 26. " WDEL , Enable the delay counter at the end of the current transaction" "Disable,Enable"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL , Data word format select" "Format 0,Format 1,Format 2,Format 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR , Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA , Transfer data"
|
|
group.long 0xB4++0x03
|
|
line.long 0x00 "TXRAM, Multi-buffer RAM Transmit Data Register 45"
|
|
bitfld.long 0x00 29.--31. " BUFMODE , Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip Single Transfer,Skip Overwrite,Skip ST-Overwrite,Continuous,Suspend Single Transfer,Suspend Overwrite,Suspend ST-Overwrite"
|
|
bitfld.long 0x00 28. " CSHOLD , Chip select hold mode" "Deactivated,Activated"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK , Lock two consecutive buffer words" "0,1"
|
|
bitfld.long 0x00 26. " WDEL , Enable the delay counter at the end of the current transaction" "Disable,Enable"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL , Data word format select" "Format 0,Format 1,Format 2,Format 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR , Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA , Transfer data"
|
|
group.long 0xB8++0x03
|
|
line.long 0x00 "TXRAM, Multi-buffer RAM Transmit Data Register 46"
|
|
bitfld.long 0x00 29.--31. " BUFMODE , Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip Single Transfer,Skip Overwrite,Skip ST-Overwrite,Continuous,Suspend Single Transfer,Suspend Overwrite,Suspend ST-Overwrite"
|
|
bitfld.long 0x00 28. " CSHOLD , Chip select hold mode" "Deactivated,Activated"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK , Lock two consecutive buffer words" "0,1"
|
|
bitfld.long 0x00 26. " WDEL , Enable the delay counter at the end of the current transaction" "Disable,Enable"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL , Data word format select" "Format 0,Format 1,Format 2,Format 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR , Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA , Transfer data"
|
|
group.long 0xBC++0x03
|
|
line.long 0x00 "TXRAM, Multi-buffer RAM Transmit Data Register 47"
|
|
bitfld.long 0x00 29.--31. " BUFMODE , Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip Single Transfer,Skip Overwrite,Skip ST-Overwrite,Continuous,Suspend Single Transfer,Suspend Overwrite,Suspend ST-Overwrite"
|
|
bitfld.long 0x00 28. " CSHOLD , Chip select hold mode" "Deactivated,Activated"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK , Lock two consecutive buffer words" "0,1"
|
|
bitfld.long 0x00 26. " WDEL , Enable the delay counter at the end of the current transaction" "Disable,Enable"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL , Data word format select" "Format 0,Format 1,Format 2,Format 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR , Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA , Transfer data"
|
|
group.long 0xC0++0x03
|
|
line.long 0x00 "TXRAM, Multi-buffer RAM Transmit Data Register 48"
|
|
bitfld.long 0x00 29.--31. " BUFMODE , Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip Single Transfer,Skip Overwrite,Skip ST-Overwrite,Continuous,Suspend Single Transfer,Suspend Overwrite,Suspend ST-Overwrite"
|
|
bitfld.long 0x00 28. " CSHOLD , Chip select hold mode" "Deactivated,Activated"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK , Lock two consecutive buffer words" "0,1"
|
|
bitfld.long 0x00 26. " WDEL , Enable the delay counter at the end of the current transaction" "Disable,Enable"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL , Data word format select" "Format 0,Format 1,Format 2,Format 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR , Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA , Transfer data"
|
|
group.long 0xC4++0x03
|
|
line.long 0x00 "TXRAM, Multi-buffer RAM Transmit Data Register 49"
|
|
bitfld.long 0x00 29.--31. " BUFMODE , Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip Single Transfer,Skip Overwrite,Skip ST-Overwrite,Continuous,Suspend Single Transfer,Suspend Overwrite,Suspend ST-Overwrite"
|
|
bitfld.long 0x00 28. " CSHOLD , Chip select hold mode" "Deactivated,Activated"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK , Lock two consecutive buffer words" "0,1"
|
|
bitfld.long 0x00 26. " WDEL , Enable the delay counter at the end of the current transaction" "Disable,Enable"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL , Data word format select" "Format 0,Format 1,Format 2,Format 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR , Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA , Transfer data"
|
|
group.long 0xC8++0x03
|
|
line.long 0x00 "TXRAM, Multi-buffer RAM Transmit Data Register 50"
|
|
bitfld.long 0x00 29.--31. " BUFMODE , Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip Single Transfer,Skip Overwrite,Skip ST-Overwrite,Continuous,Suspend Single Transfer,Suspend Overwrite,Suspend ST-Overwrite"
|
|
bitfld.long 0x00 28. " CSHOLD , Chip select hold mode" "Deactivated,Activated"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK , Lock two consecutive buffer words" "0,1"
|
|
bitfld.long 0x00 26. " WDEL , Enable the delay counter at the end of the current transaction" "Disable,Enable"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL , Data word format select" "Format 0,Format 1,Format 2,Format 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR , Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA , Transfer data"
|
|
group.long 0xCC++0x03
|
|
line.long 0x00 "TXRAM, Multi-buffer RAM Transmit Data Register 51"
|
|
bitfld.long 0x00 29.--31. " BUFMODE , Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip Single Transfer,Skip Overwrite,Skip ST-Overwrite,Continuous,Suspend Single Transfer,Suspend Overwrite,Suspend ST-Overwrite"
|
|
bitfld.long 0x00 28. " CSHOLD , Chip select hold mode" "Deactivated,Activated"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK , Lock two consecutive buffer words" "0,1"
|
|
bitfld.long 0x00 26. " WDEL , Enable the delay counter at the end of the current transaction" "Disable,Enable"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL , Data word format select" "Format 0,Format 1,Format 2,Format 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR , Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA , Transfer data"
|
|
group.long 0xD0++0x03
|
|
line.long 0x00 "TXRAM, Multi-buffer RAM Transmit Data Register 52"
|
|
bitfld.long 0x00 29.--31. " BUFMODE , Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip Single Transfer,Skip Overwrite,Skip ST-Overwrite,Continuous,Suspend Single Transfer,Suspend Overwrite,Suspend ST-Overwrite"
|
|
bitfld.long 0x00 28. " CSHOLD , Chip select hold mode" "Deactivated,Activated"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK , Lock two consecutive buffer words" "0,1"
|
|
bitfld.long 0x00 26. " WDEL , Enable the delay counter at the end of the current transaction" "Disable,Enable"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL , Data word format select" "Format 0,Format 1,Format 2,Format 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR , Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA , Transfer data"
|
|
group.long 0xD4++0x03
|
|
line.long 0x00 "TXRAM, Multi-buffer RAM Transmit Data Register 53"
|
|
bitfld.long 0x00 29.--31. " BUFMODE , Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip Single Transfer,Skip Overwrite,Skip ST-Overwrite,Continuous,Suspend Single Transfer,Suspend Overwrite,Suspend ST-Overwrite"
|
|
bitfld.long 0x00 28. " CSHOLD , Chip select hold mode" "Deactivated,Activated"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK , Lock two consecutive buffer words" "0,1"
|
|
bitfld.long 0x00 26. " WDEL , Enable the delay counter at the end of the current transaction" "Disable,Enable"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL , Data word format select" "Format 0,Format 1,Format 2,Format 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR , Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA , Transfer data"
|
|
group.long 0xD8++0x03
|
|
line.long 0x00 "TXRAM, Multi-buffer RAM Transmit Data Register 54"
|
|
bitfld.long 0x00 29.--31. " BUFMODE , Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip Single Transfer,Skip Overwrite,Skip ST-Overwrite,Continuous,Suspend Single Transfer,Suspend Overwrite,Suspend ST-Overwrite"
|
|
bitfld.long 0x00 28. " CSHOLD , Chip select hold mode" "Deactivated,Activated"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK , Lock two consecutive buffer words" "0,1"
|
|
bitfld.long 0x00 26. " WDEL , Enable the delay counter at the end of the current transaction" "Disable,Enable"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL , Data word format select" "Format 0,Format 1,Format 2,Format 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR , Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA , Transfer data"
|
|
group.long 0xDC++0x03
|
|
line.long 0x00 "TXRAM, Multi-buffer RAM Transmit Data Register 55"
|
|
bitfld.long 0x00 29.--31. " BUFMODE , Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip Single Transfer,Skip Overwrite,Skip ST-Overwrite,Continuous,Suspend Single Transfer,Suspend Overwrite,Suspend ST-Overwrite"
|
|
bitfld.long 0x00 28. " CSHOLD , Chip select hold mode" "Deactivated,Activated"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK , Lock two consecutive buffer words" "0,1"
|
|
bitfld.long 0x00 26. " WDEL , Enable the delay counter at the end of the current transaction" "Disable,Enable"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL , Data word format select" "Format 0,Format 1,Format 2,Format 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR , Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA , Transfer data"
|
|
group.long 0xE0++0x03
|
|
line.long 0x00 "TXRAM, Multi-buffer RAM Transmit Data Register 56"
|
|
bitfld.long 0x00 29.--31. " BUFMODE , Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip Single Transfer,Skip Overwrite,Skip ST-Overwrite,Continuous,Suspend Single Transfer,Suspend Overwrite,Suspend ST-Overwrite"
|
|
bitfld.long 0x00 28. " CSHOLD , Chip select hold mode" "Deactivated,Activated"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK , Lock two consecutive buffer words" "0,1"
|
|
bitfld.long 0x00 26. " WDEL , Enable the delay counter at the end of the current transaction" "Disable,Enable"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL , Data word format select" "Format 0,Format 1,Format 2,Format 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR , Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA , Transfer data"
|
|
group.long 0xE4++0x03
|
|
line.long 0x00 "TXRAM, Multi-buffer RAM Transmit Data Register 57"
|
|
bitfld.long 0x00 29.--31. " BUFMODE , Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip Single Transfer,Skip Overwrite,Skip ST-Overwrite,Continuous,Suspend Single Transfer,Suspend Overwrite,Suspend ST-Overwrite"
|
|
bitfld.long 0x00 28. " CSHOLD , Chip select hold mode" "Deactivated,Activated"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK , Lock two consecutive buffer words" "0,1"
|
|
bitfld.long 0x00 26. " WDEL , Enable the delay counter at the end of the current transaction" "Disable,Enable"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL , Data word format select" "Format 0,Format 1,Format 2,Format 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR , Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA , Transfer data"
|
|
group.long 0xE8++0x03
|
|
line.long 0x00 "TXRAM, Multi-buffer RAM Transmit Data Register 58"
|
|
bitfld.long 0x00 29.--31. " BUFMODE , Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip Single Transfer,Skip Overwrite,Skip ST-Overwrite,Continuous,Suspend Single Transfer,Suspend Overwrite,Suspend ST-Overwrite"
|
|
bitfld.long 0x00 28. " CSHOLD , Chip select hold mode" "Deactivated,Activated"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK , Lock two consecutive buffer words" "0,1"
|
|
bitfld.long 0x00 26. " WDEL , Enable the delay counter at the end of the current transaction" "Disable,Enable"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL , Data word format select" "Format 0,Format 1,Format 2,Format 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR , Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA , Transfer data"
|
|
group.long 0xEC++0x03
|
|
line.long 0x00 "TXRAM, Multi-buffer RAM Transmit Data Register 59"
|
|
bitfld.long 0x00 29.--31. " BUFMODE , Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip Single Transfer,Skip Overwrite,Skip ST-Overwrite,Continuous,Suspend Single Transfer,Suspend Overwrite,Suspend ST-Overwrite"
|
|
bitfld.long 0x00 28. " CSHOLD , Chip select hold mode" "Deactivated,Activated"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK , Lock two consecutive buffer words" "0,1"
|
|
bitfld.long 0x00 26. " WDEL , Enable the delay counter at the end of the current transaction" "Disable,Enable"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL , Data word format select" "Format 0,Format 1,Format 2,Format 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR , Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA , Transfer data"
|
|
group.long 0xF0++0x03
|
|
line.long 0x00 "TXRAM, Multi-buffer RAM Transmit Data Register 60"
|
|
bitfld.long 0x00 29.--31. " BUFMODE , Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip Single Transfer,Skip Overwrite,Skip ST-Overwrite,Continuous,Suspend Single Transfer,Suspend Overwrite,Suspend ST-Overwrite"
|
|
bitfld.long 0x00 28. " CSHOLD , Chip select hold mode" "Deactivated,Activated"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK , Lock two consecutive buffer words" "0,1"
|
|
bitfld.long 0x00 26. " WDEL , Enable the delay counter at the end of the current transaction" "Disable,Enable"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL , Data word format select" "Format 0,Format 1,Format 2,Format 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR , Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA , Transfer data"
|
|
group.long 0xF4++0x03
|
|
line.long 0x00 "TXRAM, Multi-buffer RAM Transmit Data Register 61"
|
|
bitfld.long 0x00 29.--31. " BUFMODE , Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip Single Transfer,Skip Overwrite,Skip ST-Overwrite,Continuous,Suspend Single Transfer,Suspend Overwrite,Suspend ST-Overwrite"
|
|
bitfld.long 0x00 28. " CSHOLD , Chip select hold mode" "Deactivated,Activated"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK , Lock two consecutive buffer words" "0,1"
|
|
bitfld.long 0x00 26. " WDEL , Enable the delay counter at the end of the current transaction" "Disable,Enable"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL , Data word format select" "Format 0,Format 1,Format 2,Format 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR , Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA , Transfer data"
|
|
group.long 0xF8++0x03
|
|
line.long 0x00 "TXRAM, Multi-buffer RAM Transmit Data Register 62"
|
|
bitfld.long 0x00 29.--31. " BUFMODE , Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip Single Transfer,Skip Overwrite,Skip ST-Overwrite,Continuous,Suspend Single Transfer,Suspend Overwrite,Suspend ST-Overwrite"
|
|
bitfld.long 0x00 28. " CSHOLD , Chip select hold mode" "Deactivated,Activated"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK , Lock two consecutive buffer words" "0,1"
|
|
bitfld.long 0x00 26. " WDEL , Enable the delay counter at the end of the current transaction" "Disable,Enable"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL , Data word format select" "Format 0,Format 1,Format 2,Format 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR , Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA , Transfer data"
|
|
group.long 0xFC++0x03
|
|
line.long 0x00 "TXRAM, Multi-buffer RAM Transmit Data Register 63"
|
|
bitfld.long 0x00 29.--31. " BUFMODE , Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip Single Transfer,Skip Overwrite,Skip ST-Overwrite,Continuous,Suspend Single Transfer,Suspend Overwrite,Suspend ST-Overwrite"
|
|
bitfld.long 0x00 28. " CSHOLD , Chip select hold mode" "Deactivated,Activated"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK , Lock two consecutive buffer words" "0,1"
|
|
bitfld.long 0x00 26. " WDEL , Enable the delay counter at the end of the current transaction" "Disable,Enable"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL , Data word format select" "Format 0,Format 1,Format 2,Format 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR , Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA , Transfer data"
|
|
group.long 0x100++0x03
|
|
line.long 0x00 "TXRAM, Multi-buffer RAM Transmit Data Register 64"
|
|
bitfld.long 0x00 29.--31. " BUFMODE , Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip Single Transfer,Skip Overwrite,Skip ST-Overwrite,Continuous,Suspend Single Transfer,Suspend Overwrite,Suspend ST-Overwrite"
|
|
bitfld.long 0x00 28. " CSHOLD , Chip select hold mode" "Deactivated,Activated"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK , Lock two consecutive buffer words" "0,1"
|
|
bitfld.long 0x00 26. " WDEL , Enable the delay counter at the end of the current transaction" "Disable,Enable"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL , Data word format select" "Format 0,Format 1,Format 2,Format 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR , Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA , Transfer data"
|
|
group.long 0x104++0x03
|
|
line.long 0x00 "TXRAM, Multi-buffer RAM Transmit Data Register 65"
|
|
bitfld.long 0x00 29.--31. " BUFMODE , Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip Single Transfer,Skip Overwrite,Skip ST-Overwrite,Continuous,Suspend Single Transfer,Suspend Overwrite,Suspend ST-Overwrite"
|
|
bitfld.long 0x00 28. " CSHOLD , Chip select hold mode" "Deactivated,Activated"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK , Lock two consecutive buffer words" "0,1"
|
|
bitfld.long 0x00 26. " WDEL , Enable the delay counter at the end of the current transaction" "Disable,Enable"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL , Data word format select" "Format 0,Format 1,Format 2,Format 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR , Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA , Transfer data"
|
|
group.long 0x108++0x03
|
|
line.long 0x00 "TXRAM, Multi-buffer RAM Transmit Data Register 66"
|
|
bitfld.long 0x00 29.--31. " BUFMODE , Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip Single Transfer,Skip Overwrite,Skip ST-Overwrite,Continuous,Suspend Single Transfer,Suspend Overwrite,Suspend ST-Overwrite"
|
|
bitfld.long 0x00 28. " CSHOLD , Chip select hold mode" "Deactivated,Activated"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK , Lock two consecutive buffer words" "0,1"
|
|
bitfld.long 0x00 26. " WDEL , Enable the delay counter at the end of the current transaction" "Disable,Enable"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL , Data word format select" "Format 0,Format 1,Format 2,Format 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR , Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA , Transfer data"
|
|
group.long 0x10C++0x03
|
|
line.long 0x00 "TXRAM, Multi-buffer RAM Transmit Data Register 67"
|
|
bitfld.long 0x00 29.--31. " BUFMODE , Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip Single Transfer,Skip Overwrite,Skip ST-Overwrite,Continuous,Suspend Single Transfer,Suspend Overwrite,Suspend ST-Overwrite"
|
|
bitfld.long 0x00 28. " CSHOLD , Chip select hold mode" "Deactivated,Activated"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK , Lock two consecutive buffer words" "0,1"
|
|
bitfld.long 0x00 26. " WDEL , Enable the delay counter at the end of the current transaction" "Disable,Enable"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL , Data word format select" "Format 0,Format 1,Format 2,Format 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR , Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA , Transfer data"
|
|
group.long 0x110++0x03
|
|
line.long 0x00 "TXRAM, Multi-buffer RAM Transmit Data Register 68"
|
|
bitfld.long 0x00 29.--31. " BUFMODE , Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip Single Transfer,Skip Overwrite,Skip ST-Overwrite,Continuous,Suspend Single Transfer,Suspend Overwrite,Suspend ST-Overwrite"
|
|
bitfld.long 0x00 28. " CSHOLD , Chip select hold mode" "Deactivated,Activated"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK , Lock two consecutive buffer words" "0,1"
|
|
bitfld.long 0x00 26. " WDEL , Enable the delay counter at the end of the current transaction" "Disable,Enable"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL , Data word format select" "Format 0,Format 1,Format 2,Format 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR , Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA , Transfer data"
|
|
group.long 0x114++0x03
|
|
line.long 0x00 "TXRAM, Multi-buffer RAM Transmit Data Register 69"
|
|
bitfld.long 0x00 29.--31. " BUFMODE , Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip Single Transfer,Skip Overwrite,Skip ST-Overwrite,Continuous,Suspend Single Transfer,Suspend Overwrite,Suspend ST-Overwrite"
|
|
bitfld.long 0x00 28. " CSHOLD , Chip select hold mode" "Deactivated,Activated"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK , Lock two consecutive buffer words" "0,1"
|
|
bitfld.long 0x00 26. " WDEL , Enable the delay counter at the end of the current transaction" "Disable,Enable"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL , Data word format select" "Format 0,Format 1,Format 2,Format 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR , Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA , Transfer data"
|
|
group.long 0x118++0x03
|
|
line.long 0x00 "TXRAM, Multi-buffer RAM Transmit Data Register 70"
|
|
bitfld.long 0x00 29.--31. " BUFMODE , Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip Single Transfer,Skip Overwrite,Skip ST-Overwrite,Continuous,Suspend Single Transfer,Suspend Overwrite,Suspend ST-Overwrite"
|
|
bitfld.long 0x00 28. " CSHOLD , Chip select hold mode" "Deactivated,Activated"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK , Lock two consecutive buffer words" "0,1"
|
|
bitfld.long 0x00 26. " WDEL , Enable the delay counter at the end of the current transaction" "Disable,Enable"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL , Data word format select" "Format 0,Format 1,Format 2,Format 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR , Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA , Transfer data"
|
|
group.long 0x11C++0x03
|
|
line.long 0x00 "TXRAM, Multi-buffer RAM Transmit Data Register 71"
|
|
bitfld.long 0x00 29.--31. " BUFMODE , Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip Single Transfer,Skip Overwrite,Skip ST-Overwrite,Continuous,Suspend Single Transfer,Suspend Overwrite,Suspend ST-Overwrite"
|
|
bitfld.long 0x00 28. " CSHOLD , Chip select hold mode" "Deactivated,Activated"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK , Lock two consecutive buffer words" "0,1"
|
|
bitfld.long 0x00 26. " WDEL , Enable the delay counter at the end of the current transaction" "Disable,Enable"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL , Data word format select" "Format 0,Format 1,Format 2,Format 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR , Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA , Transfer data"
|
|
group.long 0x120++0x03
|
|
line.long 0x00 "TXRAM, Multi-buffer RAM Transmit Data Register 72"
|
|
bitfld.long 0x00 29.--31. " BUFMODE , Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip Single Transfer,Skip Overwrite,Skip ST-Overwrite,Continuous,Suspend Single Transfer,Suspend Overwrite,Suspend ST-Overwrite"
|
|
bitfld.long 0x00 28. " CSHOLD , Chip select hold mode" "Deactivated,Activated"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK , Lock two consecutive buffer words" "0,1"
|
|
bitfld.long 0x00 26. " WDEL , Enable the delay counter at the end of the current transaction" "Disable,Enable"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL , Data word format select" "Format 0,Format 1,Format 2,Format 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR , Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA , Transfer data"
|
|
group.long 0x124++0x03
|
|
line.long 0x00 "TXRAM, Multi-buffer RAM Transmit Data Register 73"
|
|
bitfld.long 0x00 29.--31. " BUFMODE , Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip Single Transfer,Skip Overwrite,Skip ST-Overwrite,Continuous,Suspend Single Transfer,Suspend Overwrite,Suspend ST-Overwrite"
|
|
bitfld.long 0x00 28. " CSHOLD , Chip select hold mode" "Deactivated,Activated"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK , Lock two consecutive buffer words" "0,1"
|
|
bitfld.long 0x00 26. " WDEL , Enable the delay counter at the end of the current transaction" "Disable,Enable"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL , Data word format select" "Format 0,Format 1,Format 2,Format 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR , Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA , Transfer data"
|
|
group.long 0x128++0x03
|
|
line.long 0x00 "TXRAM, Multi-buffer RAM Transmit Data Register 74"
|
|
bitfld.long 0x00 29.--31. " BUFMODE , Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip Single Transfer,Skip Overwrite,Skip ST-Overwrite,Continuous,Suspend Single Transfer,Suspend Overwrite,Suspend ST-Overwrite"
|
|
bitfld.long 0x00 28. " CSHOLD , Chip select hold mode" "Deactivated,Activated"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK , Lock two consecutive buffer words" "0,1"
|
|
bitfld.long 0x00 26. " WDEL , Enable the delay counter at the end of the current transaction" "Disable,Enable"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL , Data word format select" "Format 0,Format 1,Format 2,Format 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR , Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA , Transfer data"
|
|
group.long 0x12C++0x03
|
|
line.long 0x00 "TXRAM, Multi-buffer RAM Transmit Data Register 75"
|
|
bitfld.long 0x00 29.--31. " BUFMODE , Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip Single Transfer,Skip Overwrite,Skip ST-Overwrite,Continuous,Suspend Single Transfer,Suspend Overwrite,Suspend ST-Overwrite"
|
|
bitfld.long 0x00 28. " CSHOLD , Chip select hold mode" "Deactivated,Activated"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK , Lock two consecutive buffer words" "0,1"
|
|
bitfld.long 0x00 26. " WDEL , Enable the delay counter at the end of the current transaction" "Disable,Enable"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL , Data word format select" "Format 0,Format 1,Format 2,Format 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR , Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA , Transfer data"
|
|
group.long 0x130++0x03
|
|
line.long 0x00 "TXRAM, Multi-buffer RAM Transmit Data Register 76"
|
|
bitfld.long 0x00 29.--31. " BUFMODE , Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip Single Transfer,Skip Overwrite,Skip ST-Overwrite,Continuous,Suspend Single Transfer,Suspend Overwrite,Suspend ST-Overwrite"
|
|
bitfld.long 0x00 28. " CSHOLD , Chip select hold mode" "Deactivated,Activated"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK , Lock two consecutive buffer words" "0,1"
|
|
bitfld.long 0x00 26. " WDEL , Enable the delay counter at the end of the current transaction" "Disable,Enable"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL , Data word format select" "Format 0,Format 1,Format 2,Format 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR , Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA , Transfer data"
|
|
group.long 0x134++0x03
|
|
line.long 0x00 "TXRAM, Multi-buffer RAM Transmit Data Register 77"
|
|
bitfld.long 0x00 29.--31. " BUFMODE , Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip Single Transfer,Skip Overwrite,Skip ST-Overwrite,Continuous,Suspend Single Transfer,Suspend Overwrite,Suspend ST-Overwrite"
|
|
bitfld.long 0x00 28. " CSHOLD , Chip select hold mode" "Deactivated,Activated"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK , Lock two consecutive buffer words" "0,1"
|
|
bitfld.long 0x00 26. " WDEL , Enable the delay counter at the end of the current transaction" "Disable,Enable"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL , Data word format select" "Format 0,Format 1,Format 2,Format 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR , Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA , Transfer data"
|
|
group.long 0x138++0x03
|
|
line.long 0x00 "TXRAM, Multi-buffer RAM Transmit Data Register 78"
|
|
bitfld.long 0x00 29.--31. " BUFMODE , Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip Single Transfer,Skip Overwrite,Skip ST-Overwrite,Continuous,Suspend Single Transfer,Suspend Overwrite,Suspend ST-Overwrite"
|
|
bitfld.long 0x00 28. " CSHOLD , Chip select hold mode" "Deactivated,Activated"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK , Lock two consecutive buffer words" "0,1"
|
|
bitfld.long 0x00 26. " WDEL , Enable the delay counter at the end of the current transaction" "Disable,Enable"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL , Data word format select" "Format 0,Format 1,Format 2,Format 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR , Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA , Transfer data"
|
|
group.long 0x13C++0x03
|
|
line.long 0x00 "TXRAM, Multi-buffer RAM Transmit Data Register 79"
|
|
bitfld.long 0x00 29.--31. " BUFMODE , Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip Single Transfer,Skip Overwrite,Skip ST-Overwrite,Continuous,Suspend Single Transfer,Suspend Overwrite,Suspend ST-Overwrite"
|
|
bitfld.long 0x00 28. " CSHOLD , Chip select hold mode" "Deactivated,Activated"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK , Lock two consecutive buffer words" "0,1"
|
|
bitfld.long 0x00 26. " WDEL , Enable the delay counter at the end of the current transaction" "Disable,Enable"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL , Data word format select" "Format 0,Format 1,Format 2,Format 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR , Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA , Transfer data"
|
|
rgroup.long (0x0+0x200)++0x03
|
|
line.long 0x00 "RXRAM, Multi-buffer RAM Receive Buffer Register 0"
|
|
bitfld.long 0x00 31. " RXEMPTY , Receive data buffer empty" "Not empty,Empty"
|
|
bitfld.long 0x00 30. " RXOVR , Receive data buffer overrun" "No overrun,Overrun"
|
|
newline
|
|
bitfld.long 0x00 29. " TXFULL , Transmit data buffer full" "Not full,Full"
|
|
bitfld.long 0x00 28. " BITERR , Bit error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 27. " DESYNC , Desynchronization of slave device" "No,Yes"
|
|
bitfld.long 0x00 26. " PARITYERR , Parity error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 25. " TIMEOUT , Time-out because of non-activation of ENA pin" "No timeout,Timeout"
|
|
bitfld.long 0x00 24. " DLENERR , Data length error flag" "No,Yes"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " LCSNR , Last chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " RXDATA , SPI receive data"
|
|
rgroup.long (0x4+0x200)++0x03
|
|
line.long 0x00 "RXRAM, Multi-buffer RAM Receive Buffer Register 1"
|
|
bitfld.long 0x00 31. " RXEMPTY , Receive data buffer empty" "Not empty,Empty"
|
|
bitfld.long 0x00 30. " RXOVR , Receive data buffer overrun" "No overrun,Overrun"
|
|
newline
|
|
bitfld.long 0x00 29. " TXFULL , Transmit data buffer full" "Not full,Full"
|
|
bitfld.long 0x00 28. " BITERR , Bit error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 27. " DESYNC , Desynchronization of slave device" "No,Yes"
|
|
bitfld.long 0x00 26. " PARITYERR , Parity error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 25. " TIMEOUT , Time-out because of non-activation of ENA pin" "No timeout,Timeout"
|
|
bitfld.long 0x00 24. " DLENERR , Data length error flag" "No,Yes"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " LCSNR , Last chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " RXDATA , SPI receive data"
|
|
rgroup.long (0x8+0x200)++0x03
|
|
line.long 0x00 "RXRAM, Multi-buffer RAM Receive Buffer Register 2"
|
|
bitfld.long 0x00 31. " RXEMPTY , Receive data buffer empty" "Not empty,Empty"
|
|
bitfld.long 0x00 30. " RXOVR , Receive data buffer overrun" "No overrun,Overrun"
|
|
newline
|
|
bitfld.long 0x00 29. " TXFULL , Transmit data buffer full" "Not full,Full"
|
|
bitfld.long 0x00 28. " BITERR , Bit error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 27. " DESYNC , Desynchronization of slave device" "No,Yes"
|
|
bitfld.long 0x00 26. " PARITYERR , Parity error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 25. " TIMEOUT , Time-out because of non-activation of ENA pin" "No timeout,Timeout"
|
|
bitfld.long 0x00 24. " DLENERR , Data length error flag" "No,Yes"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " LCSNR , Last chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " RXDATA , SPI receive data"
|
|
rgroup.long (0xC+0x200)++0x03
|
|
line.long 0x00 "RXRAM, Multi-buffer RAM Receive Buffer Register 3"
|
|
bitfld.long 0x00 31. " RXEMPTY , Receive data buffer empty" "Not empty,Empty"
|
|
bitfld.long 0x00 30. " RXOVR , Receive data buffer overrun" "No overrun,Overrun"
|
|
newline
|
|
bitfld.long 0x00 29. " TXFULL , Transmit data buffer full" "Not full,Full"
|
|
bitfld.long 0x00 28. " BITERR , Bit error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 27. " DESYNC , Desynchronization of slave device" "No,Yes"
|
|
bitfld.long 0x00 26. " PARITYERR , Parity error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 25. " TIMEOUT , Time-out because of non-activation of ENA pin" "No timeout,Timeout"
|
|
bitfld.long 0x00 24. " DLENERR , Data length error flag" "No,Yes"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " LCSNR , Last chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " RXDATA , SPI receive data"
|
|
rgroup.long (0x10+0x200)++0x03
|
|
line.long 0x00 "RXRAM, Multi-buffer RAM Receive Buffer Register 4"
|
|
bitfld.long 0x00 31. " RXEMPTY , Receive data buffer empty" "Not empty,Empty"
|
|
bitfld.long 0x00 30. " RXOVR , Receive data buffer overrun" "No overrun,Overrun"
|
|
newline
|
|
bitfld.long 0x00 29. " TXFULL , Transmit data buffer full" "Not full,Full"
|
|
bitfld.long 0x00 28. " BITERR , Bit error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 27. " DESYNC , Desynchronization of slave device" "No,Yes"
|
|
bitfld.long 0x00 26. " PARITYERR , Parity error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 25. " TIMEOUT , Time-out because of non-activation of ENA pin" "No timeout,Timeout"
|
|
bitfld.long 0x00 24. " DLENERR , Data length error flag" "No,Yes"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " LCSNR , Last chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " RXDATA , SPI receive data"
|
|
rgroup.long (0x14+0x200)++0x03
|
|
line.long 0x00 "RXRAM, Multi-buffer RAM Receive Buffer Register 5"
|
|
bitfld.long 0x00 31. " RXEMPTY , Receive data buffer empty" "Not empty,Empty"
|
|
bitfld.long 0x00 30. " RXOVR , Receive data buffer overrun" "No overrun,Overrun"
|
|
newline
|
|
bitfld.long 0x00 29. " TXFULL , Transmit data buffer full" "Not full,Full"
|
|
bitfld.long 0x00 28. " BITERR , Bit error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 27. " DESYNC , Desynchronization of slave device" "No,Yes"
|
|
bitfld.long 0x00 26. " PARITYERR , Parity error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 25. " TIMEOUT , Time-out because of non-activation of ENA pin" "No timeout,Timeout"
|
|
bitfld.long 0x00 24. " DLENERR , Data length error flag" "No,Yes"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " LCSNR , Last chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " RXDATA , SPI receive data"
|
|
rgroup.long (0x18+0x200)++0x03
|
|
line.long 0x00 "RXRAM, Multi-buffer RAM Receive Buffer Register 6"
|
|
bitfld.long 0x00 31. " RXEMPTY , Receive data buffer empty" "Not empty,Empty"
|
|
bitfld.long 0x00 30. " RXOVR , Receive data buffer overrun" "No overrun,Overrun"
|
|
newline
|
|
bitfld.long 0x00 29. " TXFULL , Transmit data buffer full" "Not full,Full"
|
|
bitfld.long 0x00 28. " BITERR , Bit error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 27. " DESYNC , Desynchronization of slave device" "No,Yes"
|
|
bitfld.long 0x00 26. " PARITYERR , Parity error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 25. " TIMEOUT , Time-out because of non-activation of ENA pin" "No timeout,Timeout"
|
|
bitfld.long 0x00 24. " DLENERR , Data length error flag" "No,Yes"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " LCSNR , Last chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " RXDATA , SPI receive data"
|
|
rgroup.long (0x1C+0x200)++0x03
|
|
line.long 0x00 "RXRAM, Multi-buffer RAM Receive Buffer Register 7"
|
|
bitfld.long 0x00 31. " RXEMPTY , Receive data buffer empty" "Not empty,Empty"
|
|
bitfld.long 0x00 30. " RXOVR , Receive data buffer overrun" "No overrun,Overrun"
|
|
newline
|
|
bitfld.long 0x00 29. " TXFULL , Transmit data buffer full" "Not full,Full"
|
|
bitfld.long 0x00 28. " BITERR , Bit error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 27. " DESYNC , Desynchronization of slave device" "No,Yes"
|
|
bitfld.long 0x00 26. " PARITYERR , Parity error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 25. " TIMEOUT , Time-out because of non-activation of ENA pin" "No timeout,Timeout"
|
|
bitfld.long 0x00 24. " DLENERR , Data length error flag" "No,Yes"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " LCSNR , Last chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " RXDATA , SPI receive data"
|
|
rgroup.long (0x20+0x200)++0x03
|
|
line.long 0x00 "RXRAM, Multi-buffer RAM Receive Buffer Register 8"
|
|
bitfld.long 0x00 31. " RXEMPTY , Receive data buffer empty" "Not empty,Empty"
|
|
bitfld.long 0x00 30. " RXOVR , Receive data buffer overrun" "No overrun,Overrun"
|
|
newline
|
|
bitfld.long 0x00 29. " TXFULL , Transmit data buffer full" "Not full,Full"
|
|
bitfld.long 0x00 28. " BITERR , Bit error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 27. " DESYNC , Desynchronization of slave device" "No,Yes"
|
|
bitfld.long 0x00 26. " PARITYERR , Parity error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 25. " TIMEOUT , Time-out because of non-activation of ENA pin" "No timeout,Timeout"
|
|
bitfld.long 0x00 24. " DLENERR , Data length error flag" "No,Yes"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " LCSNR , Last chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " RXDATA , SPI receive data"
|
|
rgroup.long (0x24+0x200)++0x03
|
|
line.long 0x00 "RXRAM, Multi-buffer RAM Receive Buffer Register 9"
|
|
bitfld.long 0x00 31. " RXEMPTY , Receive data buffer empty" "Not empty,Empty"
|
|
bitfld.long 0x00 30. " RXOVR , Receive data buffer overrun" "No overrun,Overrun"
|
|
newline
|
|
bitfld.long 0x00 29. " TXFULL , Transmit data buffer full" "Not full,Full"
|
|
bitfld.long 0x00 28. " BITERR , Bit error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 27. " DESYNC , Desynchronization of slave device" "No,Yes"
|
|
bitfld.long 0x00 26. " PARITYERR , Parity error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 25. " TIMEOUT , Time-out because of non-activation of ENA pin" "No timeout,Timeout"
|
|
bitfld.long 0x00 24. " DLENERR , Data length error flag" "No,Yes"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " LCSNR , Last chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " RXDATA , SPI receive data"
|
|
rgroup.long (0x28+0x200)++0x03
|
|
line.long 0x00 "RXRAM, Multi-buffer RAM Receive Buffer Register 10"
|
|
bitfld.long 0x00 31. " RXEMPTY , Receive data buffer empty" "Not empty,Empty"
|
|
bitfld.long 0x00 30. " RXOVR , Receive data buffer overrun" "No overrun,Overrun"
|
|
newline
|
|
bitfld.long 0x00 29. " TXFULL , Transmit data buffer full" "Not full,Full"
|
|
bitfld.long 0x00 28. " BITERR , Bit error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 27. " DESYNC , Desynchronization of slave device" "No,Yes"
|
|
bitfld.long 0x00 26. " PARITYERR , Parity error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 25. " TIMEOUT , Time-out because of non-activation of ENA pin" "No timeout,Timeout"
|
|
bitfld.long 0x00 24. " DLENERR , Data length error flag" "No,Yes"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " LCSNR , Last chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " RXDATA , SPI receive data"
|
|
rgroup.long (0x2C+0x200)++0x03
|
|
line.long 0x00 "RXRAM, Multi-buffer RAM Receive Buffer Register 11"
|
|
bitfld.long 0x00 31. " RXEMPTY , Receive data buffer empty" "Not empty,Empty"
|
|
bitfld.long 0x00 30. " RXOVR , Receive data buffer overrun" "No overrun,Overrun"
|
|
newline
|
|
bitfld.long 0x00 29. " TXFULL , Transmit data buffer full" "Not full,Full"
|
|
bitfld.long 0x00 28. " BITERR , Bit error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 27. " DESYNC , Desynchronization of slave device" "No,Yes"
|
|
bitfld.long 0x00 26. " PARITYERR , Parity error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 25. " TIMEOUT , Time-out because of non-activation of ENA pin" "No timeout,Timeout"
|
|
bitfld.long 0x00 24. " DLENERR , Data length error flag" "No,Yes"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " LCSNR , Last chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " RXDATA , SPI receive data"
|
|
rgroup.long (0x30+0x200)++0x03
|
|
line.long 0x00 "RXRAM, Multi-buffer RAM Receive Buffer Register 12"
|
|
bitfld.long 0x00 31. " RXEMPTY , Receive data buffer empty" "Not empty,Empty"
|
|
bitfld.long 0x00 30. " RXOVR , Receive data buffer overrun" "No overrun,Overrun"
|
|
newline
|
|
bitfld.long 0x00 29. " TXFULL , Transmit data buffer full" "Not full,Full"
|
|
bitfld.long 0x00 28. " BITERR , Bit error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 27. " DESYNC , Desynchronization of slave device" "No,Yes"
|
|
bitfld.long 0x00 26. " PARITYERR , Parity error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 25. " TIMEOUT , Time-out because of non-activation of ENA pin" "No timeout,Timeout"
|
|
bitfld.long 0x00 24. " DLENERR , Data length error flag" "No,Yes"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " LCSNR , Last chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " RXDATA , SPI receive data"
|
|
rgroup.long (0x34+0x200)++0x03
|
|
line.long 0x00 "RXRAM, Multi-buffer RAM Receive Buffer Register 13"
|
|
bitfld.long 0x00 31. " RXEMPTY , Receive data buffer empty" "Not empty,Empty"
|
|
bitfld.long 0x00 30. " RXOVR , Receive data buffer overrun" "No overrun,Overrun"
|
|
newline
|
|
bitfld.long 0x00 29. " TXFULL , Transmit data buffer full" "Not full,Full"
|
|
bitfld.long 0x00 28. " BITERR , Bit error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 27. " DESYNC , Desynchronization of slave device" "No,Yes"
|
|
bitfld.long 0x00 26. " PARITYERR , Parity error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 25. " TIMEOUT , Time-out because of non-activation of ENA pin" "No timeout,Timeout"
|
|
bitfld.long 0x00 24. " DLENERR , Data length error flag" "No,Yes"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " LCSNR , Last chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " RXDATA , SPI receive data"
|
|
rgroup.long (0x38+0x200)++0x03
|
|
line.long 0x00 "RXRAM, Multi-buffer RAM Receive Buffer Register 14"
|
|
bitfld.long 0x00 31. " RXEMPTY , Receive data buffer empty" "Not empty,Empty"
|
|
bitfld.long 0x00 30. " RXOVR , Receive data buffer overrun" "No overrun,Overrun"
|
|
newline
|
|
bitfld.long 0x00 29. " TXFULL , Transmit data buffer full" "Not full,Full"
|
|
bitfld.long 0x00 28. " BITERR , Bit error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 27. " DESYNC , Desynchronization of slave device" "No,Yes"
|
|
bitfld.long 0x00 26. " PARITYERR , Parity error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 25. " TIMEOUT , Time-out because of non-activation of ENA pin" "No timeout,Timeout"
|
|
bitfld.long 0x00 24. " DLENERR , Data length error flag" "No,Yes"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " LCSNR , Last chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " RXDATA , SPI receive data"
|
|
rgroup.long (0x3C+0x200)++0x03
|
|
line.long 0x00 "RXRAM, Multi-buffer RAM Receive Buffer Register 15"
|
|
bitfld.long 0x00 31. " RXEMPTY , Receive data buffer empty" "Not empty,Empty"
|
|
bitfld.long 0x00 30. " RXOVR , Receive data buffer overrun" "No overrun,Overrun"
|
|
newline
|
|
bitfld.long 0x00 29. " TXFULL , Transmit data buffer full" "Not full,Full"
|
|
bitfld.long 0x00 28. " BITERR , Bit error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 27. " DESYNC , Desynchronization of slave device" "No,Yes"
|
|
bitfld.long 0x00 26. " PARITYERR , Parity error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 25. " TIMEOUT , Time-out because of non-activation of ENA pin" "No timeout,Timeout"
|
|
bitfld.long 0x00 24. " DLENERR , Data length error flag" "No,Yes"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " LCSNR , Last chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " RXDATA , SPI receive data"
|
|
rgroup.long (0x40+0x200)++0x03
|
|
line.long 0x00 "RXRAM, Multi-buffer RAM Receive Buffer Register 16"
|
|
bitfld.long 0x00 31. " RXEMPTY , Receive data buffer empty" "Not empty,Empty"
|
|
bitfld.long 0x00 30. " RXOVR , Receive data buffer overrun" "No overrun,Overrun"
|
|
newline
|
|
bitfld.long 0x00 29. " TXFULL , Transmit data buffer full" "Not full,Full"
|
|
bitfld.long 0x00 28. " BITERR , Bit error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 27. " DESYNC , Desynchronization of slave device" "No,Yes"
|
|
bitfld.long 0x00 26. " PARITYERR , Parity error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 25. " TIMEOUT , Time-out because of non-activation of ENA pin" "No timeout,Timeout"
|
|
bitfld.long 0x00 24. " DLENERR , Data length error flag" "No,Yes"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " LCSNR , Last chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " RXDATA , SPI receive data"
|
|
rgroup.long (0x44+0x200)++0x03
|
|
line.long 0x00 "RXRAM, Multi-buffer RAM Receive Buffer Register 17"
|
|
bitfld.long 0x00 31. " RXEMPTY , Receive data buffer empty" "Not empty,Empty"
|
|
bitfld.long 0x00 30. " RXOVR , Receive data buffer overrun" "No overrun,Overrun"
|
|
newline
|
|
bitfld.long 0x00 29. " TXFULL , Transmit data buffer full" "Not full,Full"
|
|
bitfld.long 0x00 28. " BITERR , Bit error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 27. " DESYNC , Desynchronization of slave device" "No,Yes"
|
|
bitfld.long 0x00 26. " PARITYERR , Parity error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 25. " TIMEOUT , Time-out because of non-activation of ENA pin" "No timeout,Timeout"
|
|
bitfld.long 0x00 24. " DLENERR , Data length error flag" "No,Yes"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " LCSNR , Last chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " RXDATA , SPI receive data"
|
|
rgroup.long (0x48+0x200)++0x03
|
|
line.long 0x00 "RXRAM, Multi-buffer RAM Receive Buffer Register 18"
|
|
bitfld.long 0x00 31. " RXEMPTY , Receive data buffer empty" "Not empty,Empty"
|
|
bitfld.long 0x00 30. " RXOVR , Receive data buffer overrun" "No overrun,Overrun"
|
|
newline
|
|
bitfld.long 0x00 29. " TXFULL , Transmit data buffer full" "Not full,Full"
|
|
bitfld.long 0x00 28. " BITERR , Bit error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 27. " DESYNC , Desynchronization of slave device" "No,Yes"
|
|
bitfld.long 0x00 26. " PARITYERR , Parity error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 25. " TIMEOUT , Time-out because of non-activation of ENA pin" "No timeout,Timeout"
|
|
bitfld.long 0x00 24. " DLENERR , Data length error flag" "No,Yes"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " LCSNR , Last chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " RXDATA , SPI receive data"
|
|
rgroup.long (0x4C+0x200)++0x03
|
|
line.long 0x00 "RXRAM, Multi-buffer RAM Receive Buffer Register 19"
|
|
bitfld.long 0x00 31. " RXEMPTY , Receive data buffer empty" "Not empty,Empty"
|
|
bitfld.long 0x00 30. " RXOVR , Receive data buffer overrun" "No overrun,Overrun"
|
|
newline
|
|
bitfld.long 0x00 29. " TXFULL , Transmit data buffer full" "Not full,Full"
|
|
bitfld.long 0x00 28. " BITERR , Bit error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 27. " DESYNC , Desynchronization of slave device" "No,Yes"
|
|
bitfld.long 0x00 26. " PARITYERR , Parity error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 25. " TIMEOUT , Time-out because of non-activation of ENA pin" "No timeout,Timeout"
|
|
bitfld.long 0x00 24. " DLENERR , Data length error flag" "No,Yes"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " LCSNR , Last chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " RXDATA , SPI receive data"
|
|
rgroup.long (0x50+0x200)++0x03
|
|
line.long 0x00 "RXRAM, Multi-buffer RAM Receive Buffer Register 20"
|
|
bitfld.long 0x00 31. " RXEMPTY , Receive data buffer empty" "Not empty,Empty"
|
|
bitfld.long 0x00 30. " RXOVR , Receive data buffer overrun" "No overrun,Overrun"
|
|
newline
|
|
bitfld.long 0x00 29. " TXFULL , Transmit data buffer full" "Not full,Full"
|
|
bitfld.long 0x00 28. " BITERR , Bit error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 27. " DESYNC , Desynchronization of slave device" "No,Yes"
|
|
bitfld.long 0x00 26. " PARITYERR , Parity error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 25. " TIMEOUT , Time-out because of non-activation of ENA pin" "No timeout,Timeout"
|
|
bitfld.long 0x00 24. " DLENERR , Data length error flag" "No,Yes"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " LCSNR , Last chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " RXDATA , SPI receive data"
|
|
rgroup.long (0x54+0x200)++0x03
|
|
line.long 0x00 "RXRAM, Multi-buffer RAM Receive Buffer Register 21"
|
|
bitfld.long 0x00 31. " RXEMPTY , Receive data buffer empty" "Not empty,Empty"
|
|
bitfld.long 0x00 30. " RXOVR , Receive data buffer overrun" "No overrun,Overrun"
|
|
newline
|
|
bitfld.long 0x00 29. " TXFULL , Transmit data buffer full" "Not full,Full"
|
|
bitfld.long 0x00 28. " BITERR , Bit error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 27. " DESYNC , Desynchronization of slave device" "No,Yes"
|
|
bitfld.long 0x00 26. " PARITYERR , Parity error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 25. " TIMEOUT , Time-out because of non-activation of ENA pin" "No timeout,Timeout"
|
|
bitfld.long 0x00 24. " DLENERR , Data length error flag" "No,Yes"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " LCSNR , Last chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " RXDATA , SPI receive data"
|
|
rgroup.long (0x58+0x200)++0x03
|
|
line.long 0x00 "RXRAM, Multi-buffer RAM Receive Buffer Register 22"
|
|
bitfld.long 0x00 31. " RXEMPTY , Receive data buffer empty" "Not empty,Empty"
|
|
bitfld.long 0x00 30. " RXOVR , Receive data buffer overrun" "No overrun,Overrun"
|
|
newline
|
|
bitfld.long 0x00 29. " TXFULL , Transmit data buffer full" "Not full,Full"
|
|
bitfld.long 0x00 28. " BITERR , Bit error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 27. " DESYNC , Desynchronization of slave device" "No,Yes"
|
|
bitfld.long 0x00 26. " PARITYERR , Parity error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 25. " TIMEOUT , Time-out because of non-activation of ENA pin" "No timeout,Timeout"
|
|
bitfld.long 0x00 24. " DLENERR , Data length error flag" "No,Yes"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " LCSNR , Last chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " RXDATA , SPI receive data"
|
|
rgroup.long (0x5C+0x200)++0x03
|
|
line.long 0x00 "RXRAM, Multi-buffer RAM Receive Buffer Register 23"
|
|
bitfld.long 0x00 31. " RXEMPTY , Receive data buffer empty" "Not empty,Empty"
|
|
bitfld.long 0x00 30. " RXOVR , Receive data buffer overrun" "No overrun,Overrun"
|
|
newline
|
|
bitfld.long 0x00 29. " TXFULL , Transmit data buffer full" "Not full,Full"
|
|
bitfld.long 0x00 28. " BITERR , Bit error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 27. " DESYNC , Desynchronization of slave device" "No,Yes"
|
|
bitfld.long 0x00 26. " PARITYERR , Parity error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 25. " TIMEOUT , Time-out because of non-activation of ENA pin" "No timeout,Timeout"
|
|
bitfld.long 0x00 24. " DLENERR , Data length error flag" "No,Yes"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " LCSNR , Last chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " RXDATA , SPI receive data"
|
|
rgroup.long (0x60+0x200)++0x03
|
|
line.long 0x00 "RXRAM, Multi-buffer RAM Receive Buffer Register 24"
|
|
bitfld.long 0x00 31. " RXEMPTY , Receive data buffer empty" "Not empty,Empty"
|
|
bitfld.long 0x00 30. " RXOVR , Receive data buffer overrun" "No overrun,Overrun"
|
|
newline
|
|
bitfld.long 0x00 29. " TXFULL , Transmit data buffer full" "Not full,Full"
|
|
bitfld.long 0x00 28. " BITERR , Bit error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 27. " DESYNC , Desynchronization of slave device" "No,Yes"
|
|
bitfld.long 0x00 26. " PARITYERR , Parity error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 25. " TIMEOUT , Time-out because of non-activation of ENA pin" "No timeout,Timeout"
|
|
bitfld.long 0x00 24. " DLENERR , Data length error flag" "No,Yes"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " LCSNR , Last chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " RXDATA , SPI receive data"
|
|
rgroup.long (0x64+0x200)++0x03
|
|
line.long 0x00 "RXRAM, Multi-buffer RAM Receive Buffer Register 25"
|
|
bitfld.long 0x00 31. " RXEMPTY , Receive data buffer empty" "Not empty,Empty"
|
|
bitfld.long 0x00 30. " RXOVR , Receive data buffer overrun" "No overrun,Overrun"
|
|
newline
|
|
bitfld.long 0x00 29. " TXFULL , Transmit data buffer full" "Not full,Full"
|
|
bitfld.long 0x00 28. " BITERR , Bit error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 27. " DESYNC , Desynchronization of slave device" "No,Yes"
|
|
bitfld.long 0x00 26. " PARITYERR , Parity error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 25. " TIMEOUT , Time-out because of non-activation of ENA pin" "No timeout,Timeout"
|
|
bitfld.long 0x00 24. " DLENERR , Data length error flag" "No,Yes"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " LCSNR , Last chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " RXDATA , SPI receive data"
|
|
rgroup.long (0x68+0x200)++0x03
|
|
line.long 0x00 "RXRAM, Multi-buffer RAM Receive Buffer Register 26"
|
|
bitfld.long 0x00 31. " RXEMPTY , Receive data buffer empty" "Not empty,Empty"
|
|
bitfld.long 0x00 30. " RXOVR , Receive data buffer overrun" "No overrun,Overrun"
|
|
newline
|
|
bitfld.long 0x00 29. " TXFULL , Transmit data buffer full" "Not full,Full"
|
|
bitfld.long 0x00 28. " BITERR , Bit error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 27. " DESYNC , Desynchronization of slave device" "No,Yes"
|
|
bitfld.long 0x00 26. " PARITYERR , Parity error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 25. " TIMEOUT , Time-out because of non-activation of ENA pin" "No timeout,Timeout"
|
|
bitfld.long 0x00 24. " DLENERR , Data length error flag" "No,Yes"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " LCSNR , Last chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " RXDATA , SPI receive data"
|
|
rgroup.long (0x6C+0x200)++0x03
|
|
line.long 0x00 "RXRAM, Multi-buffer RAM Receive Buffer Register 27"
|
|
bitfld.long 0x00 31. " RXEMPTY , Receive data buffer empty" "Not empty,Empty"
|
|
bitfld.long 0x00 30. " RXOVR , Receive data buffer overrun" "No overrun,Overrun"
|
|
newline
|
|
bitfld.long 0x00 29. " TXFULL , Transmit data buffer full" "Not full,Full"
|
|
bitfld.long 0x00 28. " BITERR , Bit error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 27. " DESYNC , Desynchronization of slave device" "No,Yes"
|
|
bitfld.long 0x00 26. " PARITYERR , Parity error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 25. " TIMEOUT , Time-out because of non-activation of ENA pin" "No timeout,Timeout"
|
|
bitfld.long 0x00 24. " DLENERR , Data length error flag" "No,Yes"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " LCSNR , Last chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " RXDATA , SPI receive data"
|
|
rgroup.long (0x70+0x200)++0x03
|
|
line.long 0x00 "RXRAM, Multi-buffer RAM Receive Buffer Register 28"
|
|
bitfld.long 0x00 31. " RXEMPTY , Receive data buffer empty" "Not empty,Empty"
|
|
bitfld.long 0x00 30. " RXOVR , Receive data buffer overrun" "No overrun,Overrun"
|
|
newline
|
|
bitfld.long 0x00 29. " TXFULL , Transmit data buffer full" "Not full,Full"
|
|
bitfld.long 0x00 28. " BITERR , Bit error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 27. " DESYNC , Desynchronization of slave device" "No,Yes"
|
|
bitfld.long 0x00 26. " PARITYERR , Parity error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 25. " TIMEOUT , Time-out because of non-activation of ENA pin" "No timeout,Timeout"
|
|
bitfld.long 0x00 24. " DLENERR , Data length error flag" "No,Yes"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " LCSNR , Last chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " RXDATA , SPI receive data"
|
|
rgroup.long (0x74+0x200)++0x03
|
|
line.long 0x00 "RXRAM, Multi-buffer RAM Receive Buffer Register 29"
|
|
bitfld.long 0x00 31. " RXEMPTY , Receive data buffer empty" "Not empty,Empty"
|
|
bitfld.long 0x00 30. " RXOVR , Receive data buffer overrun" "No overrun,Overrun"
|
|
newline
|
|
bitfld.long 0x00 29. " TXFULL , Transmit data buffer full" "Not full,Full"
|
|
bitfld.long 0x00 28. " BITERR , Bit error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 27. " DESYNC , Desynchronization of slave device" "No,Yes"
|
|
bitfld.long 0x00 26. " PARITYERR , Parity error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 25. " TIMEOUT , Time-out because of non-activation of ENA pin" "No timeout,Timeout"
|
|
bitfld.long 0x00 24. " DLENERR , Data length error flag" "No,Yes"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " LCSNR , Last chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " RXDATA , SPI receive data"
|
|
rgroup.long (0x78+0x200)++0x03
|
|
line.long 0x00 "RXRAM, Multi-buffer RAM Receive Buffer Register 30"
|
|
bitfld.long 0x00 31. " RXEMPTY , Receive data buffer empty" "Not empty,Empty"
|
|
bitfld.long 0x00 30. " RXOVR , Receive data buffer overrun" "No overrun,Overrun"
|
|
newline
|
|
bitfld.long 0x00 29. " TXFULL , Transmit data buffer full" "Not full,Full"
|
|
bitfld.long 0x00 28. " BITERR , Bit error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 27. " DESYNC , Desynchronization of slave device" "No,Yes"
|
|
bitfld.long 0x00 26. " PARITYERR , Parity error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 25. " TIMEOUT , Time-out because of non-activation of ENA pin" "No timeout,Timeout"
|
|
bitfld.long 0x00 24. " DLENERR , Data length error flag" "No,Yes"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " LCSNR , Last chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " RXDATA , SPI receive data"
|
|
rgroup.long (0x7C+0x200)++0x03
|
|
line.long 0x00 "RXRAM, Multi-buffer RAM Receive Buffer Register 31"
|
|
bitfld.long 0x00 31. " RXEMPTY , Receive data buffer empty" "Not empty,Empty"
|
|
bitfld.long 0x00 30. " RXOVR , Receive data buffer overrun" "No overrun,Overrun"
|
|
newline
|
|
bitfld.long 0x00 29. " TXFULL , Transmit data buffer full" "Not full,Full"
|
|
bitfld.long 0x00 28. " BITERR , Bit error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 27. " DESYNC , Desynchronization of slave device" "No,Yes"
|
|
bitfld.long 0x00 26. " PARITYERR , Parity error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 25. " TIMEOUT , Time-out because of non-activation of ENA pin" "No timeout,Timeout"
|
|
bitfld.long 0x00 24. " DLENERR , Data length error flag" "No,Yes"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " LCSNR , Last chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " RXDATA , SPI receive data"
|
|
rgroup.long (0x80+0x200)++0x03
|
|
line.long 0x00 "RXRAM, Multi-buffer RAM Receive Buffer Register 32"
|
|
bitfld.long 0x00 31. " RXEMPTY , Receive data buffer empty" "Not empty,Empty"
|
|
bitfld.long 0x00 30. " RXOVR , Receive data buffer overrun" "No overrun,Overrun"
|
|
newline
|
|
bitfld.long 0x00 29. " TXFULL , Transmit data buffer full" "Not full,Full"
|
|
bitfld.long 0x00 28. " BITERR , Bit error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 27. " DESYNC , Desynchronization of slave device" "No,Yes"
|
|
bitfld.long 0x00 26. " PARITYERR , Parity error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 25. " TIMEOUT , Time-out because of non-activation of ENA pin" "No timeout,Timeout"
|
|
bitfld.long 0x00 24. " DLENERR , Data length error flag" "No,Yes"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " LCSNR , Last chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " RXDATA , SPI receive data"
|
|
rgroup.long (0x84+0x200)++0x03
|
|
line.long 0x00 "RXRAM, Multi-buffer RAM Receive Buffer Register 33"
|
|
bitfld.long 0x00 31. " RXEMPTY , Receive data buffer empty" "Not empty,Empty"
|
|
bitfld.long 0x00 30. " RXOVR , Receive data buffer overrun" "No overrun,Overrun"
|
|
newline
|
|
bitfld.long 0x00 29. " TXFULL , Transmit data buffer full" "Not full,Full"
|
|
bitfld.long 0x00 28. " BITERR , Bit error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 27. " DESYNC , Desynchronization of slave device" "No,Yes"
|
|
bitfld.long 0x00 26. " PARITYERR , Parity error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 25. " TIMEOUT , Time-out because of non-activation of ENA pin" "No timeout,Timeout"
|
|
bitfld.long 0x00 24. " DLENERR , Data length error flag" "No,Yes"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " LCSNR , Last chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " RXDATA , SPI receive data"
|
|
rgroup.long (0x88+0x200)++0x03
|
|
line.long 0x00 "RXRAM, Multi-buffer RAM Receive Buffer Register 34"
|
|
bitfld.long 0x00 31. " RXEMPTY , Receive data buffer empty" "Not empty,Empty"
|
|
bitfld.long 0x00 30. " RXOVR , Receive data buffer overrun" "No overrun,Overrun"
|
|
newline
|
|
bitfld.long 0x00 29. " TXFULL , Transmit data buffer full" "Not full,Full"
|
|
bitfld.long 0x00 28. " BITERR , Bit error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 27. " DESYNC , Desynchronization of slave device" "No,Yes"
|
|
bitfld.long 0x00 26. " PARITYERR , Parity error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 25. " TIMEOUT , Time-out because of non-activation of ENA pin" "No timeout,Timeout"
|
|
bitfld.long 0x00 24. " DLENERR , Data length error flag" "No,Yes"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " LCSNR , Last chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " RXDATA , SPI receive data"
|
|
rgroup.long (0x8C+0x200)++0x03
|
|
line.long 0x00 "RXRAM, Multi-buffer RAM Receive Buffer Register 35"
|
|
bitfld.long 0x00 31. " RXEMPTY , Receive data buffer empty" "Not empty,Empty"
|
|
bitfld.long 0x00 30. " RXOVR , Receive data buffer overrun" "No overrun,Overrun"
|
|
newline
|
|
bitfld.long 0x00 29. " TXFULL , Transmit data buffer full" "Not full,Full"
|
|
bitfld.long 0x00 28. " BITERR , Bit error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 27. " DESYNC , Desynchronization of slave device" "No,Yes"
|
|
bitfld.long 0x00 26. " PARITYERR , Parity error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 25. " TIMEOUT , Time-out because of non-activation of ENA pin" "No timeout,Timeout"
|
|
bitfld.long 0x00 24. " DLENERR , Data length error flag" "No,Yes"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " LCSNR , Last chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " RXDATA , SPI receive data"
|
|
rgroup.long (0x90+0x200)++0x03
|
|
line.long 0x00 "RXRAM, Multi-buffer RAM Receive Buffer Register 36"
|
|
bitfld.long 0x00 31. " RXEMPTY , Receive data buffer empty" "Not empty,Empty"
|
|
bitfld.long 0x00 30. " RXOVR , Receive data buffer overrun" "No overrun,Overrun"
|
|
newline
|
|
bitfld.long 0x00 29. " TXFULL , Transmit data buffer full" "Not full,Full"
|
|
bitfld.long 0x00 28. " BITERR , Bit error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 27. " DESYNC , Desynchronization of slave device" "No,Yes"
|
|
bitfld.long 0x00 26. " PARITYERR , Parity error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 25. " TIMEOUT , Time-out because of non-activation of ENA pin" "No timeout,Timeout"
|
|
bitfld.long 0x00 24. " DLENERR , Data length error flag" "No,Yes"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " LCSNR , Last chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " RXDATA , SPI receive data"
|
|
rgroup.long (0x94+0x200)++0x03
|
|
line.long 0x00 "RXRAM, Multi-buffer RAM Receive Buffer Register 37"
|
|
bitfld.long 0x00 31. " RXEMPTY , Receive data buffer empty" "Not empty,Empty"
|
|
bitfld.long 0x00 30. " RXOVR , Receive data buffer overrun" "No overrun,Overrun"
|
|
newline
|
|
bitfld.long 0x00 29. " TXFULL , Transmit data buffer full" "Not full,Full"
|
|
bitfld.long 0x00 28. " BITERR , Bit error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 27. " DESYNC , Desynchronization of slave device" "No,Yes"
|
|
bitfld.long 0x00 26. " PARITYERR , Parity error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 25. " TIMEOUT , Time-out because of non-activation of ENA pin" "No timeout,Timeout"
|
|
bitfld.long 0x00 24. " DLENERR , Data length error flag" "No,Yes"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " LCSNR , Last chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " RXDATA , SPI receive data"
|
|
rgroup.long (0x98+0x200)++0x03
|
|
line.long 0x00 "RXRAM, Multi-buffer RAM Receive Buffer Register 38"
|
|
bitfld.long 0x00 31. " RXEMPTY , Receive data buffer empty" "Not empty,Empty"
|
|
bitfld.long 0x00 30. " RXOVR , Receive data buffer overrun" "No overrun,Overrun"
|
|
newline
|
|
bitfld.long 0x00 29. " TXFULL , Transmit data buffer full" "Not full,Full"
|
|
bitfld.long 0x00 28. " BITERR , Bit error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 27. " DESYNC , Desynchronization of slave device" "No,Yes"
|
|
bitfld.long 0x00 26. " PARITYERR , Parity error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 25. " TIMEOUT , Time-out because of non-activation of ENA pin" "No timeout,Timeout"
|
|
bitfld.long 0x00 24. " DLENERR , Data length error flag" "No,Yes"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " LCSNR , Last chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " RXDATA , SPI receive data"
|
|
rgroup.long (0x9C+0x200)++0x03
|
|
line.long 0x00 "RXRAM, Multi-buffer RAM Receive Buffer Register 39"
|
|
bitfld.long 0x00 31. " RXEMPTY , Receive data buffer empty" "Not empty,Empty"
|
|
bitfld.long 0x00 30. " RXOVR , Receive data buffer overrun" "No overrun,Overrun"
|
|
newline
|
|
bitfld.long 0x00 29. " TXFULL , Transmit data buffer full" "Not full,Full"
|
|
bitfld.long 0x00 28. " BITERR , Bit error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 27. " DESYNC , Desynchronization of slave device" "No,Yes"
|
|
bitfld.long 0x00 26. " PARITYERR , Parity error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 25. " TIMEOUT , Time-out because of non-activation of ENA pin" "No timeout,Timeout"
|
|
bitfld.long 0x00 24. " DLENERR , Data length error flag" "No,Yes"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " LCSNR , Last chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " RXDATA , SPI receive data"
|
|
rgroup.long (0xA0+0x200)++0x03
|
|
line.long 0x00 "RXRAM, Multi-buffer RAM Receive Buffer Register 40"
|
|
bitfld.long 0x00 31. " RXEMPTY , Receive data buffer empty" "Not empty,Empty"
|
|
bitfld.long 0x00 30. " RXOVR , Receive data buffer overrun" "No overrun,Overrun"
|
|
newline
|
|
bitfld.long 0x00 29. " TXFULL , Transmit data buffer full" "Not full,Full"
|
|
bitfld.long 0x00 28. " BITERR , Bit error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 27. " DESYNC , Desynchronization of slave device" "No,Yes"
|
|
bitfld.long 0x00 26. " PARITYERR , Parity error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 25. " TIMEOUT , Time-out because of non-activation of ENA pin" "No timeout,Timeout"
|
|
bitfld.long 0x00 24. " DLENERR , Data length error flag" "No,Yes"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " LCSNR , Last chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " RXDATA , SPI receive data"
|
|
rgroup.long (0xA4+0x200)++0x03
|
|
line.long 0x00 "RXRAM, Multi-buffer RAM Receive Buffer Register 41"
|
|
bitfld.long 0x00 31. " RXEMPTY , Receive data buffer empty" "Not empty,Empty"
|
|
bitfld.long 0x00 30. " RXOVR , Receive data buffer overrun" "No overrun,Overrun"
|
|
newline
|
|
bitfld.long 0x00 29. " TXFULL , Transmit data buffer full" "Not full,Full"
|
|
bitfld.long 0x00 28. " BITERR , Bit error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 27. " DESYNC , Desynchronization of slave device" "No,Yes"
|
|
bitfld.long 0x00 26. " PARITYERR , Parity error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 25. " TIMEOUT , Time-out because of non-activation of ENA pin" "No timeout,Timeout"
|
|
bitfld.long 0x00 24. " DLENERR , Data length error flag" "No,Yes"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " LCSNR , Last chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " RXDATA , SPI receive data"
|
|
rgroup.long (0xA8+0x200)++0x03
|
|
line.long 0x00 "RXRAM, Multi-buffer RAM Receive Buffer Register 42"
|
|
bitfld.long 0x00 31. " RXEMPTY , Receive data buffer empty" "Not empty,Empty"
|
|
bitfld.long 0x00 30. " RXOVR , Receive data buffer overrun" "No overrun,Overrun"
|
|
newline
|
|
bitfld.long 0x00 29. " TXFULL , Transmit data buffer full" "Not full,Full"
|
|
bitfld.long 0x00 28. " BITERR , Bit error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 27. " DESYNC , Desynchronization of slave device" "No,Yes"
|
|
bitfld.long 0x00 26. " PARITYERR , Parity error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 25. " TIMEOUT , Time-out because of non-activation of ENA pin" "No timeout,Timeout"
|
|
bitfld.long 0x00 24. " DLENERR , Data length error flag" "No,Yes"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " LCSNR , Last chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " RXDATA , SPI receive data"
|
|
rgroup.long (0xAC+0x200)++0x03
|
|
line.long 0x00 "RXRAM, Multi-buffer RAM Receive Buffer Register 43"
|
|
bitfld.long 0x00 31. " RXEMPTY , Receive data buffer empty" "Not empty,Empty"
|
|
bitfld.long 0x00 30. " RXOVR , Receive data buffer overrun" "No overrun,Overrun"
|
|
newline
|
|
bitfld.long 0x00 29. " TXFULL , Transmit data buffer full" "Not full,Full"
|
|
bitfld.long 0x00 28. " BITERR , Bit error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 27. " DESYNC , Desynchronization of slave device" "No,Yes"
|
|
bitfld.long 0x00 26. " PARITYERR , Parity error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 25. " TIMEOUT , Time-out because of non-activation of ENA pin" "No timeout,Timeout"
|
|
bitfld.long 0x00 24. " DLENERR , Data length error flag" "No,Yes"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " LCSNR , Last chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " RXDATA , SPI receive data"
|
|
rgroup.long (0xB0+0x200)++0x03
|
|
line.long 0x00 "RXRAM, Multi-buffer RAM Receive Buffer Register 44"
|
|
bitfld.long 0x00 31. " RXEMPTY , Receive data buffer empty" "Not empty,Empty"
|
|
bitfld.long 0x00 30. " RXOVR , Receive data buffer overrun" "No overrun,Overrun"
|
|
newline
|
|
bitfld.long 0x00 29. " TXFULL , Transmit data buffer full" "Not full,Full"
|
|
bitfld.long 0x00 28. " BITERR , Bit error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 27. " DESYNC , Desynchronization of slave device" "No,Yes"
|
|
bitfld.long 0x00 26. " PARITYERR , Parity error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 25. " TIMEOUT , Time-out because of non-activation of ENA pin" "No timeout,Timeout"
|
|
bitfld.long 0x00 24. " DLENERR , Data length error flag" "No,Yes"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " LCSNR , Last chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " RXDATA , SPI receive data"
|
|
rgroup.long (0xB4+0x200)++0x03
|
|
line.long 0x00 "RXRAM, Multi-buffer RAM Receive Buffer Register 45"
|
|
bitfld.long 0x00 31. " RXEMPTY , Receive data buffer empty" "Not empty,Empty"
|
|
bitfld.long 0x00 30. " RXOVR , Receive data buffer overrun" "No overrun,Overrun"
|
|
newline
|
|
bitfld.long 0x00 29. " TXFULL , Transmit data buffer full" "Not full,Full"
|
|
bitfld.long 0x00 28. " BITERR , Bit error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 27. " DESYNC , Desynchronization of slave device" "No,Yes"
|
|
bitfld.long 0x00 26. " PARITYERR , Parity error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 25. " TIMEOUT , Time-out because of non-activation of ENA pin" "No timeout,Timeout"
|
|
bitfld.long 0x00 24. " DLENERR , Data length error flag" "No,Yes"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " LCSNR , Last chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " RXDATA , SPI receive data"
|
|
rgroup.long (0xB8+0x200)++0x03
|
|
line.long 0x00 "RXRAM, Multi-buffer RAM Receive Buffer Register 46"
|
|
bitfld.long 0x00 31. " RXEMPTY , Receive data buffer empty" "Not empty,Empty"
|
|
bitfld.long 0x00 30. " RXOVR , Receive data buffer overrun" "No overrun,Overrun"
|
|
newline
|
|
bitfld.long 0x00 29. " TXFULL , Transmit data buffer full" "Not full,Full"
|
|
bitfld.long 0x00 28. " BITERR , Bit error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 27. " DESYNC , Desynchronization of slave device" "No,Yes"
|
|
bitfld.long 0x00 26. " PARITYERR , Parity error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 25. " TIMEOUT , Time-out because of non-activation of ENA pin" "No timeout,Timeout"
|
|
bitfld.long 0x00 24. " DLENERR , Data length error flag" "No,Yes"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " LCSNR , Last chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " RXDATA , SPI receive data"
|
|
rgroup.long (0xBC+0x200)++0x03
|
|
line.long 0x00 "RXRAM, Multi-buffer RAM Receive Buffer Register 47"
|
|
bitfld.long 0x00 31. " RXEMPTY , Receive data buffer empty" "Not empty,Empty"
|
|
bitfld.long 0x00 30. " RXOVR , Receive data buffer overrun" "No overrun,Overrun"
|
|
newline
|
|
bitfld.long 0x00 29. " TXFULL , Transmit data buffer full" "Not full,Full"
|
|
bitfld.long 0x00 28. " BITERR , Bit error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 27. " DESYNC , Desynchronization of slave device" "No,Yes"
|
|
bitfld.long 0x00 26. " PARITYERR , Parity error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 25. " TIMEOUT , Time-out because of non-activation of ENA pin" "No timeout,Timeout"
|
|
bitfld.long 0x00 24. " DLENERR , Data length error flag" "No,Yes"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " LCSNR , Last chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " RXDATA , SPI receive data"
|
|
rgroup.long (0xC0+0x200)++0x03
|
|
line.long 0x00 "RXRAM, Multi-buffer RAM Receive Buffer Register 48"
|
|
bitfld.long 0x00 31. " RXEMPTY , Receive data buffer empty" "Not empty,Empty"
|
|
bitfld.long 0x00 30. " RXOVR , Receive data buffer overrun" "No overrun,Overrun"
|
|
newline
|
|
bitfld.long 0x00 29. " TXFULL , Transmit data buffer full" "Not full,Full"
|
|
bitfld.long 0x00 28. " BITERR , Bit error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 27. " DESYNC , Desynchronization of slave device" "No,Yes"
|
|
bitfld.long 0x00 26. " PARITYERR , Parity error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 25. " TIMEOUT , Time-out because of non-activation of ENA pin" "No timeout,Timeout"
|
|
bitfld.long 0x00 24. " DLENERR , Data length error flag" "No,Yes"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " LCSNR , Last chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " RXDATA , SPI receive data"
|
|
rgroup.long (0xC4+0x200)++0x03
|
|
line.long 0x00 "RXRAM, Multi-buffer RAM Receive Buffer Register 49"
|
|
bitfld.long 0x00 31. " RXEMPTY , Receive data buffer empty" "Not empty,Empty"
|
|
bitfld.long 0x00 30. " RXOVR , Receive data buffer overrun" "No overrun,Overrun"
|
|
newline
|
|
bitfld.long 0x00 29. " TXFULL , Transmit data buffer full" "Not full,Full"
|
|
bitfld.long 0x00 28. " BITERR , Bit error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 27. " DESYNC , Desynchronization of slave device" "No,Yes"
|
|
bitfld.long 0x00 26. " PARITYERR , Parity error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 25. " TIMEOUT , Time-out because of non-activation of ENA pin" "No timeout,Timeout"
|
|
bitfld.long 0x00 24. " DLENERR , Data length error flag" "No,Yes"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " LCSNR , Last chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " RXDATA , SPI receive data"
|
|
rgroup.long (0xC8+0x200)++0x03
|
|
line.long 0x00 "RXRAM, Multi-buffer RAM Receive Buffer Register 50"
|
|
bitfld.long 0x00 31. " RXEMPTY , Receive data buffer empty" "Not empty,Empty"
|
|
bitfld.long 0x00 30. " RXOVR , Receive data buffer overrun" "No overrun,Overrun"
|
|
newline
|
|
bitfld.long 0x00 29. " TXFULL , Transmit data buffer full" "Not full,Full"
|
|
bitfld.long 0x00 28. " BITERR , Bit error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 27. " DESYNC , Desynchronization of slave device" "No,Yes"
|
|
bitfld.long 0x00 26. " PARITYERR , Parity error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 25. " TIMEOUT , Time-out because of non-activation of ENA pin" "No timeout,Timeout"
|
|
bitfld.long 0x00 24. " DLENERR , Data length error flag" "No,Yes"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " LCSNR , Last chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " RXDATA , SPI receive data"
|
|
rgroup.long (0xCC+0x200)++0x03
|
|
line.long 0x00 "RXRAM, Multi-buffer RAM Receive Buffer Register 51"
|
|
bitfld.long 0x00 31. " RXEMPTY , Receive data buffer empty" "Not empty,Empty"
|
|
bitfld.long 0x00 30. " RXOVR , Receive data buffer overrun" "No overrun,Overrun"
|
|
newline
|
|
bitfld.long 0x00 29. " TXFULL , Transmit data buffer full" "Not full,Full"
|
|
bitfld.long 0x00 28. " BITERR , Bit error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 27. " DESYNC , Desynchronization of slave device" "No,Yes"
|
|
bitfld.long 0x00 26. " PARITYERR , Parity error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 25. " TIMEOUT , Time-out because of non-activation of ENA pin" "No timeout,Timeout"
|
|
bitfld.long 0x00 24. " DLENERR , Data length error flag" "No,Yes"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " LCSNR , Last chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " RXDATA , SPI receive data"
|
|
rgroup.long (0xD0+0x200)++0x03
|
|
line.long 0x00 "RXRAM, Multi-buffer RAM Receive Buffer Register 52"
|
|
bitfld.long 0x00 31. " RXEMPTY , Receive data buffer empty" "Not empty,Empty"
|
|
bitfld.long 0x00 30. " RXOVR , Receive data buffer overrun" "No overrun,Overrun"
|
|
newline
|
|
bitfld.long 0x00 29. " TXFULL , Transmit data buffer full" "Not full,Full"
|
|
bitfld.long 0x00 28. " BITERR , Bit error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 27. " DESYNC , Desynchronization of slave device" "No,Yes"
|
|
bitfld.long 0x00 26. " PARITYERR , Parity error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 25. " TIMEOUT , Time-out because of non-activation of ENA pin" "No timeout,Timeout"
|
|
bitfld.long 0x00 24. " DLENERR , Data length error flag" "No,Yes"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " LCSNR , Last chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " RXDATA , SPI receive data"
|
|
rgroup.long (0xD4+0x200)++0x03
|
|
line.long 0x00 "RXRAM, Multi-buffer RAM Receive Buffer Register 53"
|
|
bitfld.long 0x00 31. " RXEMPTY , Receive data buffer empty" "Not empty,Empty"
|
|
bitfld.long 0x00 30. " RXOVR , Receive data buffer overrun" "No overrun,Overrun"
|
|
newline
|
|
bitfld.long 0x00 29. " TXFULL , Transmit data buffer full" "Not full,Full"
|
|
bitfld.long 0x00 28. " BITERR , Bit error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 27. " DESYNC , Desynchronization of slave device" "No,Yes"
|
|
bitfld.long 0x00 26. " PARITYERR , Parity error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 25. " TIMEOUT , Time-out because of non-activation of ENA pin" "No timeout,Timeout"
|
|
bitfld.long 0x00 24. " DLENERR , Data length error flag" "No,Yes"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " LCSNR , Last chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " RXDATA , SPI receive data"
|
|
rgroup.long (0xD8+0x200)++0x03
|
|
line.long 0x00 "RXRAM, Multi-buffer RAM Receive Buffer Register 54"
|
|
bitfld.long 0x00 31. " RXEMPTY , Receive data buffer empty" "Not empty,Empty"
|
|
bitfld.long 0x00 30. " RXOVR , Receive data buffer overrun" "No overrun,Overrun"
|
|
newline
|
|
bitfld.long 0x00 29. " TXFULL , Transmit data buffer full" "Not full,Full"
|
|
bitfld.long 0x00 28. " BITERR , Bit error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 27. " DESYNC , Desynchronization of slave device" "No,Yes"
|
|
bitfld.long 0x00 26. " PARITYERR , Parity error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 25. " TIMEOUT , Time-out because of non-activation of ENA pin" "No timeout,Timeout"
|
|
bitfld.long 0x00 24. " DLENERR , Data length error flag" "No,Yes"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " LCSNR , Last chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " RXDATA , SPI receive data"
|
|
rgroup.long (0xDC+0x200)++0x03
|
|
line.long 0x00 "RXRAM, Multi-buffer RAM Receive Buffer Register 55"
|
|
bitfld.long 0x00 31. " RXEMPTY , Receive data buffer empty" "Not empty,Empty"
|
|
bitfld.long 0x00 30. " RXOVR , Receive data buffer overrun" "No overrun,Overrun"
|
|
newline
|
|
bitfld.long 0x00 29. " TXFULL , Transmit data buffer full" "Not full,Full"
|
|
bitfld.long 0x00 28. " BITERR , Bit error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 27. " DESYNC , Desynchronization of slave device" "No,Yes"
|
|
bitfld.long 0x00 26. " PARITYERR , Parity error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 25. " TIMEOUT , Time-out because of non-activation of ENA pin" "No timeout,Timeout"
|
|
bitfld.long 0x00 24. " DLENERR , Data length error flag" "No,Yes"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " LCSNR , Last chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " RXDATA , SPI receive data"
|
|
rgroup.long (0xE0+0x200)++0x03
|
|
line.long 0x00 "RXRAM, Multi-buffer RAM Receive Buffer Register 56"
|
|
bitfld.long 0x00 31. " RXEMPTY , Receive data buffer empty" "Not empty,Empty"
|
|
bitfld.long 0x00 30. " RXOVR , Receive data buffer overrun" "No overrun,Overrun"
|
|
newline
|
|
bitfld.long 0x00 29. " TXFULL , Transmit data buffer full" "Not full,Full"
|
|
bitfld.long 0x00 28. " BITERR , Bit error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 27. " DESYNC , Desynchronization of slave device" "No,Yes"
|
|
bitfld.long 0x00 26. " PARITYERR , Parity error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 25. " TIMEOUT , Time-out because of non-activation of ENA pin" "No timeout,Timeout"
|
|
bitfld.long 0x00 24. " DLENERR , Data length error flag" "No,Yes"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " LCSNR , Last chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " RXDATA , SPI receive data"
|
|
rgroup.long (0xE4+0x200)++0x03
|
|
line.long 0x00 "RXRAM, Multi-buffer RAM Receive Buffer Register 57"
|
|
bitfld.long 0x00 31. " RXEMPTY , Receive data buffer empty" "Not empty,Empty"
|
|
bitfld.long 0x00 30. " RXOVR , Receive data buffer overrun" "No overrun,Overrun"
|
|
newline
|
|
bitfld.long 0x00 29. " TXFULL , Transmit data buffer full" "Not full,Full"
|
|
bitfld.long 0x00 28. " BITERR , Bit error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 27. " DESYNC , Desynchronization of slave device" "No,Yes"
|
|
bitfld.long 0x00 26. " PARITYERR , Parity error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 25. " TIMEOUT , Time-out because of non-activation of ENA pin" "No timeout,Timeout"
|
|
bitfld.long 0x00 24. " DLENERR , Data length error flag" "No,Yes"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " LCSNR , Last chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " RXDATA , SPI receive data"
|
|
rgroup.long (0xE8+0x200)++0x03
|
|
line.long 0x00 "RXRAM, Multi-buffer RAM Receive Buffer Register 58"
|
|
bitfld.long 0x00 31. " RXEMPTY , Receive data buffer empty" "Not empty,Empty"
|
|
bitfld.long 0x00 30. " RXOVR , Receive data buffer overrun" "No overrun,Overrun"
|
|
newline
|
|
bitfld.long 0x00 29. " TXFULL , Transmit data buffer full" "Not full,Full"
|
|
bitfld.long 0x00 28. " BITERR , Bit error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 27. " DESYNC , Desynchronization of slave device" "No,Yes"
|
|
bitfld.long 0x00 26. " PARITYERR , Parity error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 25. " TIMEOUT , Time-out because of non-activation of ENA pin" "No timeout,Timeout"
|
|
bitfld.long 0x00 24. " DLENERR , Data length error flag" "No,Yes"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " LCSNR , Last chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " RXDATA , SPI receive data"
|
|
rgroup.long (0xEC+0x200)++0x03
|
|
line.long 0x00 "RXRAM, Multi-buffer RAM Receive Buffer Register 59"
|
|
bitfld.long 0x00 31. " RXEMPTY , Receive data buffer empty" "Not empty,Empty"
|
|
bitfld.long 0x00 30. " RXOVR , Receive data buffer overrun" "No overrun,Overrun"
|
|
newline
|
|
bitfld.long 0x00 29. " TXFULL , Transmit data buffer full" "Not full,Full"
|
|
bitfld.long 0x00 28. " BITERR , Bit error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 27. " DESYNC , Desynchronization of slave device" "No,Yes"
|
|
bitfld.long 0x00 26. " PARITYERR , Parity error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 25. " TIMEOUT , Time-out because of non-activation of ENA pin" "No timeout,Timeout"
|
|
bitfld.long 0x00 24. " DLENERR , Data length error flag" "No,Yes"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " LCSNR , Last chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " RXDATA , SPI receive data"
|
|
rgroup.long (0xF0+0x200)++0x03
|
|
line.long 0x00 "RXRAM, Multi-buffer RAM Receive Buffer Register 60"
|
|
bitfld.long 0x00 31. " RXEMPTY , Receive data buffer empty" "Not empty,Empty"
|
|
bitfld.long 0x00 30. " RXOVR , Receive data buffer overrun" "No overrun,Overrun"
|
|
newline
|
|
bitfld.long 0x00 29. " TXFULL , Transmit data buffer full" "Not full,Full"
|
|
bitfld.long 0x00 28. " BITERR , Bit error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 27. " DESYNC , Desynchronization of slave device" "No,Yes"
|
|
bitfld.long 0x00 26. " PARITYERR , Parity error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 25. " TIMEOUT , Time-out because of non-activation of ENA pin" "No timeout,Timeout"
|
|
bitfld.long 0x00 24. " DLENERR , Data length error flag" "No,Yes"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " LCSNR , Last chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " RXDATA , SPI receive data"
|
|
rgroup.long (0xF4+0x200)++0x03
|
|
line.long 0x00 "RXRAM, Multi-buffer RAM Receive Buffer Register 61"
|
|
bitfld.long 0x00 31. " RXEMPTY , Receive data buffer empty" "Not empty,Empty"
|
|
bitfld.long 0x00 30. " RXOVR , Receive data buffer overrun" "No overrun,Overrun"
|
|
newline
|
|
bitfld.long 0x00 29. " TXFULL , Transmit data buffer full" "Not full,Full"
|
|
bitfld.long 0x00 28. " BITERR , Bit error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 27. " DESYNC , Desynchronization of slave device" "No,Yes"
|
|
bitfld.long 0x00 26. " PARITYERR , Parity error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 25. " TIMEOUT , Time-out because of non-activation of ENA pin" "No timeout,Timeout"
|
|
bitfld.long 0x00 24. " DLENERR , Data length error flag" "No,Yes"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " LCSNR , Last chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " RXDATA , SPI receive data"
|
|
rgroup.long (0xF8+0x200)++0x03
|
|
line.long 0x00 "RXRAM, Multi-buffer RAM Receive Buffer Register 62"
|
|
bitfld.long 0x00 31. " RXEMPTY , Receive data buffer empty" "Not empty,Empty"
|
|
bitfld.long 0x00 30. " RXOVR , Receive data buffer overrun" "No overrun,Overrun"
|
|
newline
|
|
bitfld.long 0x00 29. " TXFULL , Transmit data buffer full" "Not full,Full"
|
|
bitfld.long 0x00 28. " BITERR , Bit error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 27. " DESYNC , Desynchronization of slave device" "No,Yes"
|
|
bitfld.long 0x00 26. " PARITYERR , Parity error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 25. " TIMEOUT , Time-out because of non-activation of ENA pin" "No timeout,Timeout"
|
|
bitfld.long 0x00 24. " DLENERR , Data length error flag" "No,Yes"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " LCSNR , Last chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " RXDATA , SPI receive data"
|
|
rgroup.long (0xFC+0x200)++0x03
|
|
line.long 0x00 "RXRAM, Multi-buffer RAM Receive Buffer Register 63"
|
|
bitfld.long 0x00 31. " RXEMPTY , Receive data buffer empty" "Not empty,Empty"
|
|
bitfld.long 0x00 30. " RXOVR , Receive data buffer overrun" "No overrun,Overrun"
|
|
newline
|
|
bitfld.long 0x00 29. " TXFULL , Transmit data buffer full" "Not full,Full"
|
|
bitfld.long 0x00 28. " BITERR , Bit error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 27. " DESYNC , Desynchronization of slave device" "No,Yes"
|
|
bitfld.long 0x00 26. " PARITYERR , Parity error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 25. " TIMEOUT , Time-out because of non-activation of ENA pin" "No timeout,Timeout"
|
|
bitfld.long 0x00 24. " DLENERR , Data length error flag" "No,Yes"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " LCSNR , Last chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " RXDATA , SPI receive data"
|
|
rgroup.long (0x100+0x200)++0x03
|
|
line.long 0x00 "RXRAM, Multi-buffer RAM Receive Buffer Register 64"
|
|
bitfld.long 0x00 31. " RXEMPTY , Receive data buffer empty" "Not empty,Empty"
|
|
bitfld.long 0x00 30. " RXOVR , Receive data buffer overrun" "No overrun,Overrun"
|
|
newline
|
|
bitfld.long 0x00 29. " TXFULL , Transmit data buffer full" "Not full,Full"
|
|
bitfld.long 0x00 28. " BITERR , Bit error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 27. " DESYNC , Desynchronization of slave device" "No,Yes"
|
|
bitfld.long 0x00 26. " PARITYERR , Parity error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 25. " TIMEOUT , Time-out because of non-activation of ENA pin" "No timeout,Timeout"
|
|
bitfld.long 0x00 24. " DLENERR , Data length error flag" "No,Yes"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " LCSNR , Last chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " RXDATA , SPI receive data"
|
|
rgroup.long (0x104+0x200)++0x03
|
|
line.long 0x00 "RXRAM, Multi-buffer RAM Receive Buffer Register 65"
|
|
bitfld.long 0x00 31. " RXEMPTY , Receive data buffer empty" "Not empty,Empty"
|
|
bitfld.long 0x00 30. " RXOVR , Receive data buffer overrun" "No overrun,Overrun"
|
|
newline
|
|
bitfld.long 0x00 29. " TXFULL , Transmit data buffer full" "Not full,Full"
|
|
bitfld.long 0x00 28. " BITERR , Bit error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 27. " DESYNC , Desynchronization of slave device" "No,Yes"
|
|
bitfld.long 0x00 26. " PARITYERR , Parity error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 25. " TIMEOUT , Time-out because of non-activation of ENA pin" "No timeout,Timeout"
|
|
bitfld.long 0x00 24. " DLENERR , Data length error flag" "No,Yes"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " LCSNR , Last chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " RXDATA , SPI receive data"
|
|
rgroup.long (0x108+0x200)++0x03
|
|
line.long 0x00 "RXRAM, Multi-buffer RAM Receive Buffer Register 66"
|
|
bitfld.long 0x00 31. " RXEMPTY , Receive data buffer empty" "Not empty,Empty"
|
|
bitfld.long 0x00 30. " RXOVR , Receive data buffer overrun" "No overrun,Overrun"
|
|
newline
|
|
bitfld.long 0x00 29. " TXFULL , Transmit data buffer full" "Not full,Full"
|
|
bitfld.long 0x00 28. " BITERR , Bit error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 27. " DESYNC , Desynchronization of slave device" "No,Yes"
|
|
bitfld.long 0x00 26. " PARITYERR , Parity error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 25. " TIMEOUT , Time-out because of non-activation of ENA pin" "No timeout,Timeout"
|
|
bitfld.long 0x00 24. " DLENERR , Data length error flag" "No,Yes"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " LCSNR , Last chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " RXDATA , SPI receive data"
|
|
rgroup.long (0x10C+0x200)++0x03
|
|
line.long 0x00 "RXRAM, Multi-buffer RAM Receive Buffer Register 67"
|
|
bitfld.long 0x00 31. " RXEMPTY , Receive data buffer empty" "Not empty,Empty"
|
|
bitfld.long 0x00 30. " RXOVR , Receive data buffer overrun" "No overrun,Overrun"
|
|
newline
|
|
bitfld.long 0x00 29. " TXFULL , Transmit data buffer full" "Not full,Full"
|
|
bitfld.long 0x00 28. " BITERR , Bit error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 27. " DESYNC , Desynchronization of slave device" "No,Yes"
|
|
bitfld.long 0x00 26. " PARITYERR , Parity error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 25. " TIMEOUT , Time-out because of non-activation of ENA pin" "No timeout,Timeout"
|
|
bitfld.long 0x00 24. " DLENERR , Data length error flag" "No,Yes"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " LCSNR , Last chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " RXDATA , SPI receive data"
|
|
rgroup.long (0x110+0x200)++0x03
|
|
line.long 0x00 "RXRAM, Multi-buffer RAM Receive Buffer Register 68"
|
|
bitfld.long 0x00 31. " RXEMPTY , Receive data buffer empty" "Not empty,Empty"
|
|
bitfld.long 0x00 30. " RXOVR , Receive data buffer overrun" "No overrun,Overrun"
|
|
newline
|
|
bitfld.long 0x00 29. " TXFULL , Transmit data buffer full" "Not full,Full"
|
|
bitfld.long 0x00 28. " BITERR , Bit error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 27. " DESYNC , Desynchronization of slave device" "No,Yes"
|
|
bitfld.long 0x00 26. " PARITYERR , Parity error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 25. " TIMEOUT , Time-out because of non-activation of ENA pin" "No timeout,Timeout"
|
|
bitfld.long 0x00 24. " DLENERR , Data length error flag" "No,Yes"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " LCSNR , Last chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " RXDATA , SPI receive data"
|
|
rgroup.long (0x114+0x200)++0x03
|
|
line.long 0x00 "RXRAM, Multi-buffer RAM Receive Buffer Register 69"
|
|
bitfld.long 0x00 31. " RXEMPTY , Receive data buffer empty" "Not empty,Empty"
|
|
bitfld.long 0x00 30. " RXOVR , Receive data buffer overrun" "No overrun,Overrun"
|
|
newline
|
|
bitfld.long 0x00 29. " TXFULL , Transmit data buffer full" "Not full,Full"
|
|
bitfld.long 0x00 28. " BITERR , Bit error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 27. " DESYNC , Desynchronization of slave device" "No,Yes"
|
|
bitfld.long 0x00 26. " PARITYERR , Parity error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 25. " TIMEOUT , Time-out because of non-activation of ENA pin" "No timeout,Timeout"
|
|
bitfld.long 0x00 24. " DLENERR , Data length error flag" "No,Yes"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " LCSNR , Last chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " RXDATA , SPI receive data"
|
|
rgroup.long (0x118+0x200)++0x03
|
|
line.long 0x00 "RXRAM, Multi-buffer RAM Receive Buffer Register 70"
|
|
bitfld.long 0x00 31. " RXEMPTY , Receive data buffer empty" "Not empty,Empty"
|
|
bitfld.long 0x00 30. " RXOVR , Receive data buffer overrun" "No overrun,Overrun"
|
|
newline
|
|
bitfld.long 0x00 29. " TXFULL , Transmit data buffer full" "Not full,Full"
|
|
bitfld.long 0x00 28. " BITERR , Bit error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 27. " DESYNC , Desynchronization of slave device" "No,Yes"
|
|
bitfld.long 0x00 26. " PARITYERR , Parity error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 25. " TIMEOUT , Time-out because of non-activation of ENA pin" "No timeout,Timeout"
|
|
bitfld.long 0x00 24. " DLENERR , Data length error flag" "No,Yes"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " LCSNR , Last chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " RXDATA , SPI receive data"
|
|
rgroup.long (0x11C+0x200)++0x03
|
|
line.long 0x00 "RXRAM, Multi-buffer RAM Receive Buffer Register 71"
|
|
bitfld.long 0x00 31. " RXEMPTY , Receive data buffer empty" "Not empty,Empty"
|
|
bitfld.long 0x00 30. " RXOVR , Receive data buffer overrun" "No overrun,Overrun"
|
|
newline
|
|
bitfld.long 0x00 29. " TXFULL , Transmit data buffer full" "Not full,Full"
|
|
bitfld.long 0x00 28. " BITERR , Bit error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 27. " DESYNC , Desynchronization of slave device" "No,Yes"
|
|
bitfld.long 0x00 26. " PARITYERR , Parity error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 25. " TIMEOUT , Time-out because of non-activation of ENA pin" "No timeout,Timeout"
|
|
bitfld.long 0x00 24. " DLENERR , Data length error flag" "No,Yes"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " LCSNR , Last chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " RXDATA , SPI receive data"
|
|
rgroup.long (0x120+0x200)++0x03
|
|
line.long 0x00 "RXRAM, Multi-buffer RAM Receive Buffer Register 72"
|
|
bitfld.long 0x00 31. " RXEMPTY , Receive data buffer empty" "Not empty,Empty"
|
|
bitfld.long 0x00 30. " RXOVR , Receive data buffer overrun" "No overrun,Overrun"
|
|
newline
|
|
bitfld.long 0x00 29. " TXFULL , Transmit data buffer full" "Not full,Full"
|
|
bitfld.long 0x00 28. " BITERR , Bit error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 27. " DESYNC , Desynchronization of slave device" "No,Yes"
|
|
bitfld.long 0x00 26. " PARITYERR , Parity error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 25. " TIMEOUT , Time-out because of non-activation of ENA pin" "No timeout,Timeout"
|
|
bitfld.long 0x00 24. " DLENERR , Data length error flag" "No,Yes"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " LCSNR , Last chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " RXDATA , SPI receive data"
|
|
rgroup.long (0x124+0x200)++0x03
|
|
line.long 0x00 "RXRAM, Multi-buffer RAM Receive Buffer Register 73"
|
|
bitfld.long 0x00 31. " RXEMPTY , Receive data buffer empty" "Not empty,Empty"
|
|
bitfld.long 0x00 30. " RXOVR , Receive data buffer overrun" "No overrun,Overrun"
|
|
newline
|
|
bitfld.long 0x00 29. " TXFULL , Transmit data buffer full" "Not full,Full"
|
|
bitfld.long 0x00 28. " BITERR , Bit error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 27. " DESYNC , Desynchronization of slave device" "No,Yes"
|
|
bitfld.long 0x00 26. " PARITYERR , Parity error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 25. " TIMEOUT , Time-out because of non-activation of ENA pin" "No timeout,Timeout"
|
|
bitfld.long 0x00 24. " DLENERR , Data length error flag" "No,Yes"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " LCSNR , Last chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " RXDATA , SPI receive data"
|
|
rgroup.long (0x128+0x200)++0x03
|
|
line.long 0x00 "RXRAM, Multi-buffer RAM Receive Buffer Register 74"
|
|
bitfld.long 0x00 31. " RXEMPTY , Receive data buffer empty" "Not empty,Empty"
|
|
bitfld.long 0x00 30. " RXOVR , Receive data buffer overrun" "No overrun,Overrun"
|
|
newline
|
|
bitfld.long 0x00 29. " TXFULL , Transmit data buffer full" "Not full,Full"
|
|
bitfld.long 0x00 28. " BITERR , Bit error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 27. " DESYNC , Desynchronization of slave device" "No,Yes"
|
|
bitfld.long 0x00 26. " PARITYERR , Parity error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 25. " TIMEOUT , Time-out because of non-activation of ENA pin" "No timeout,Timeout"
|
|
bitfld.long 0x00 24. " DLENERR , Data length error flag" "No,Yes"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " LCSNR , Last chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " RXDATA , SPI receive data"
|
|
rgroup.long (0x12C+0x200)++0x03
|
|
line.long 0x00 "RXRAM, Multi-buffer RAM Receive Buffer Register 75"
|
|
bitfld.long 0x00 31. " RXEMPTY , Receive data buffer empty" "Not empty,Empty"
|
|
bitfld.long 0x00 30. " RXOVR , Receive data buffer overrun" "No overrun,Overrun"
|
|
newline
|
|
bitfld.long 0x00 29. " TXFULL , Transmit data buffer full" "Not full,Full"
|
|
bitfld.long 0x00 28. " BITERR , Bit error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 27. " DESYNC , Desynchronization of slave device" "No,Yes"
|
|
bitfld.long 0x00 26. " PARITYERR , Parity error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 25. " TIMEOUT , Time-out because of non-activation of ENA pin" "No timeout,Timeout"
|
|
bitfld.long 0x00 24. " DLENERR , Data length error flag" "No,Yes"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " LCSNR , Last chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " RXDATA , SPI receive data"
|
|
rgroup.long (0x130+0x200)++0x03
|
|
line.long 0x00 "RXRAM, Multi-buffer RAM Receive Buffer Register 76"
|
|
bitfld.long 0x00 31. " RXEMPTY , Receive data buffer empty" "Not empty,Empty"
|
|
bitfld.long 0x00 30. " RXOVR , Receive data buffer overrun" "No overrun,Overrun"
|
|
newline
|
|
bitfld.long 0x00 29. " TXFULL , Transmit data buffer full" "Not full,Full"
|
|
bitfld.long 0x00 28. " BITERR , Bit error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 27. " DESYNC , Desynchronization of slave device" "No,Yes"
|
|
bitfld.long 0x00 26. " PARITYERR , Parity error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 25. " TIMEOUT , Time-out because of non-activation of ENA pin" "No timeout,Timeout"
|
|
bitfld.long 0x00 24. " DLENERR , Data length error flag" "No,Yes"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " LCSNR , Last chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " RXDATA , SPI receive data"
|
|
rgroup.long (0x134+0x200)++0x03
|
|
line.long 0x00 "RXRAM, Multi-buffer RAM Receive Buffer Register 77"
|
|
bitfld.long 0x00 31. " RXEMPTY , Receive data buffer empty" "Not empty,Empty"
|
|
bitfld.long 0x00 30. " RXOVR , Receive data buffer overrun" "No overrun,Overrun"
|
|
newline
|
|
bitfld.long 0x00 29. " TXFULL , Transmit data buffer full" "Not full,Full"
|
|
bitfld.long 0x00 28. " BITERR , Bit error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 27. " DESYNC , Desynchronization of slave device" "No,Yes"
|
|
bitfld.long 0x00 26. " PARITYERR , Parity error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 25. " TIMEOUT , Time-out because of non-activation of ENA pin" "No timeout,Timeout"
|
|
bitfld.long 0x00 24. " DLENERR , Data length error flag" "No,Yes"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " LCSNR , Last chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " RXDATA , SPI receive data"
|
|
rgroup.long (0x138+0x200)++0x03
|
|
line.long 0x00 "RXRAM, Multi-buffer RAM Receive Buffer Register 78"
|
|
bitfld.long 0x00 31. " RXEMPTY , Receive data buffer empty" "Not empty,Empty"
|
|
bitfld.long 0x00 30. " RXOVR , Receive data buffer overrun" "No overrun,Overrun"
|
|
newline
|
|
bitfld.long 0x00 29. " TXFULL , Transmit data buffer full" "Not full,Full"
|
|
bitfld.long 0x00 28. " BITERR , Bit error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 27. " DESYNC , Desynchronization of slave device" "No,Yes"
|
|
bitfld.long 0x00 26. " PARITYERR , Parity error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 25. " TIMEOUT , Time-out because of non-activation of ENA pin" "No timeout,Timeout"
|
|
bitfld.long 0x00 24. " DLENERR , Data length error flag" "No,Yes"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " LCSNR , Last chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " RXDATA , SPI receive data"
|
|
rgroup.long (0x13C+0x200)++0x03
|
|
line.long 0x00 "RXRAM, Multi-buffer RAM Receive Buffer Register 79"
|
|
bitfld.long 0x00 31. " RXEMPTY , Receive data buffer empty" "Not empty,Empty"
|
|
bitfld.long 0x00 30. " RXOVR , Receive data buffer overrun" "No overrun,Overrun"
|
|
newline
|
|
bitfld.long 0x00 29. " TXFULL , Transmit data buffer full" "Not full,Full"
|
|
bitfld.long 0x00 28. " BITERR , Bit error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 27. " DESYNC , Desynchronization of slave device" "No,Yes"
|
|
bitfld.long 0x00 26. " PARITYERR , Parity error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 25. " TIMEOUT , Time-out because of non-activation of ENA pin" "No timeout,Timeout"
|
|
bitfld.long 0x00 24. " DLENERR , Data length error flag" "No,Yes"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " LCSNR , Last chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " RXDATA , SPI receive data"
|
|
else
|
|
tree "Transmit Buffers"
|
|
group.long 0x0++0x03
|
|
line.long 0x00 "BUFFER0,Buffer 0 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x4++0x03
|
|
line.long 0x00 "BUFFER1,Buffer 1 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x8++0x03
|
|
line.long 0x00 "BUFFER2,Buffer 2 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0xC++0x03
|
|
line.long 0x00 "BUFFER3,Buffer 3 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "BUFFER4,Buffer 4 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "BUFFER5,Buffer 5 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "BUFFER6,Buffer 6 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "BUFFER7,Buffer 7 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "BUFFER8,Buffer 8 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "BUFFER9,Buffer 9 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "BUFFER10,Buffer 10 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "BUFFER11,Buffer 11 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "BUFFER12,Buffer 12 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x34++0x03
|
|
line.long 0x00 "BUFFER13,Buffer 13 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x38++0x03
|
|
line.long 0x00 "BUFFER14,Buffer 14 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x3C++0x03
|
|
line.long 0x00 "BUFFER15,Buffer 15 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "BUFFER16,Buffer 16 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x44++0x03
|
|
line.long 0x00 "BUFFER17,Buffer 17 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x48++0x03
|
|
line.long 0x00 "BUFFER18,Buffer 18 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x4C++0x03
|
|
line.long 0x00 "BUFFER19,Buffer 19 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x50++0x03
|
|
line.long 0x00 "BUFFER20,Buffer 20 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x54++0x03
|
|
line.long 0x00 "BUFFER21,Buffer 21 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x58++0x03
|
|
line.long 0x00 "BUFFER22,Buffer 22 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x5C++0x03
|
|
line.long 0x00 "BUFFER23,Buffer 23 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x60++0x03
|
|
line.long 0x00 "BUFFER24,Buffer 24 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x64++0x03
|
|
line.long 0x00 "BUFFER25,Buffer 25 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x68++0x03
|
|
line.long 0x00 "BUFFER26,Buffer 26 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x6C++0x03
|
|
line.long 0x00 "BUFFER27,Buffer 27 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x70++0x03
|
|
line.long 0x00 "BUFFER28,Buffer 28 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x74++0x03
|
|
line.long 0x00 "BUFFER29,Buffer 29 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x78++0x03
|
|
line.long 0x00 "BUFFER30,Buffer 30 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x7C++0x03
|
|
line.long 0x00 "BUFFER31,Buffer 31 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x80++0x03
|
|
line.long 0x00 "BUFFER32,Buffer 32 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x84++0x03
|
|
line.long 0x00 "BUFFER33,Buffer 33 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x88++0x03
|
|
line.long 0x00 "BUFFER34,Buffer 34 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x8C++0x03
|
|
line.long 0x00 "BUFFER35,Buffer 35 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x90++0x03
|
|
line.long 0x00 "BUFFER36,Buffer 36 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x94++0x03
|
|
line.long 0x00 "BUFFER37,Buffer 37 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x98++0x03
|
|
line.long 0x00 "BUFFER38,Buffer 38 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x9C++0x03
|
|
line.long 0x00 "BUFFER39,Buffer 39 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0xA0++0x03
|
|
line.long 0x00 "BUFFER40,Buffer 40 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0xA4++0x03
|
|
line.long 0x00 "BUFFER41,Buffer 41 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0xA8++0x03
|
|
line.long 0x00 "BUFFER42,Buffer 42 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0xAC++0x03
|
|
line.long 0x00 "BUFFER43,Buffer 43 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0xB0++0x03
|
|
line.long 0x00 "BUFFER44,Buffer 44 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0xB4++0x03
|
|
line.long 0x00 "BUFFER45,Buffer 45 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0xB8++0x03
|
|
line.long 0x00 "BUFFER46,Buffer 46 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0xBC++0x03
|
|
line.long 0x00 "BUFFER47,Buffer 47 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0xC0++0x03
|
|
line.long 0x00 "BUFFER48,Buffer 48 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0xC4++0x03
|
|
line.long 0x00 "BUFFER49,Buffer 49 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0xC8++0x03
|
|
line.long 0x00 "BUFFER50,Buffer 50 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0xCC++0x03
|
|
line.long 0x00 "BUFFER51,Buffer 51 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0xD0++0x03
|
|
line.long 0x00 "BUFFER52,Buffer 52 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0xD4++0x03
|
|
line.long 0x00 "BUFFER53,Buffer 53 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0xD8++0x03
|
|
line.long 0x00 "BUFFER54,Buffer 54 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0xDC++0x03
|
|
line.long 0x00 "BUFFER55,Buffer 55 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0xE0++0x03
|
|
line.long 0x00 "BUFFER56,Buffer 56 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0xE4++0x03
|
|
line.long 0x00 "BUFFER57,Buffer 57 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0xE8++0x03
|
|
line.long 0x00 "BUFFER58,Buffer 58 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0xEC++0x03
|
|
line.long 0x00 "BUFFER59,Buffer 59 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0xF0++0x03
|
|
line.long 0x00 "BUFFER60,Buffer 60 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0xF4++0x03
|
|
line.long 0x00 "BUFFER61,Buffer 61 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0xF8++0x03
|
|
line.long 0x00 "BUFFER62,Buffer 62 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0xFC++0x03
|
|
line.long 0x00 "BUFFER63,Buffer 63 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x100++0x03
|
|
line.long 0x00 "BUFFER64,Buffer 64 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x104++0x03
|
|
line.long 0x00 "BUFFER65,Buffer 65 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x108++0x03
|
|
line.long 0x00 "BUFFER66,Buffer 66 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x10C++0x03
|
|
line.long 0x00 "BUFFER67,Buffer 67 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x110++0x03
|
|
line.long 0x00 "BUFFER68,Buffer 68 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x114++0x03
|
|
line.long 0x00 "BUFFER69,Buffer 69 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x118++0x03
|
|
line.long 0x00 "BUFFER70,Buffer 70 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x11C++0x03
|
|
line.long 0x00 "BUFFER71,Buffer 71 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x120++0x03
|
|
line.long 0x00 "BUFFER72,Buffer 72 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x124++0x03
|
|
line.long 0x00 "BUFFER73,Buffer 73 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x128++0x03
|
|
line.long 0x00 "BUFFER74,Buffer 74 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x12C++0x03
|
|
line.long 0x00 "BUFFER75,Buffer 75 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x130++0x03
|
|
line.long 0x00 "BUFFER76,Buffer 76 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x134++0x03
|
|
line.long 0x00 "BUFFER77,Buffer 77 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x138++0x03
|
|
line.long 0x00 "BUFFER78,Buffer 78 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x13C++0x03
|
|
line.long 0x00 "BUFFER79,Buffer 79 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x140++0x03
|
|
line.long 0x00 "BUFFER80,Buffer 80 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x144++0x03
|
|
line.long 0x00 "BUFFER81,Buffer 81 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x148++0x03
|
|
line.long 0x00 "BUFFER82,Buffer 82 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x14C++0x03
|
|
line.long 0x00 "BUFFER83,Buffer 83 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x150++0x03
|
|
line.long 0x00 "BUFFER84,Buffer 84 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x154++0x03
|
|
line.long 0x00 "BUFFER85,Buffer 85 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x158++0x03
|
|
line.long 0x00 "BUFFER86,Buffer 86 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x15C++0x03
|
|
line.long 0x00 "BUFFER87,Buffer 87 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x160++0x03
|
|
line.long 0x00 "BUFFER88,Buffer 88 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x164++0x03
|
|
line.long 0x00 "BUFFER89,Buffer 89 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x168++0x03
|
|
line.long 0x00 "BUFFER90,Buffer 90 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x16C++0x03
|
|
line.long 0x00 "BUFFER91,Buffer 91 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x170++0x03
|
|
line.long 0x00 "BUFFER92,Buffer 92 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x174++0x03
|
|
line.long 0x00 "BUFFER93,Buffer 93 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x178++0x03
|
|
line.long 0x00 "BUFFER94,Buffer 94 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x17C++0x03
|
|
line.long 0x00 "BUFFER95,Buffer 95 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x180++0x03
|
|
line.long 0x00 "BUFFER96,Buffer 96 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x184++0x03
|
|
line.long 0x00 "BUFFER97,Buffer 97 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x188++0x03
|
|
line.long 0x00 "BUFFER98,Buffer 98 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x18C++0x03
|
|
line.long 0x00 "BUFFER99,Buffer 99 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x190++0x03
|
|
line.long 0x00 "BUFFER100,Buffer 100 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x194++0x03
|
|
line.long 0x00 "BUFFER101,Buffer 101 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x198++0x03
|
|
line.long 0x00 "BUFFER102,Buffer 102 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x19C++0x03
|
|
line.long 0x00 "BUFFER103,Buffer 103 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x1A0++0x03
|
|
line.long 0x00 "BUFFER104,Buffer 104 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x1A4++0x03
|
|
line.long 0x00 "BUFFER105,Buffer 105 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x1A8++0x03
|
|
line.long 0x00 "BUFFER106,Buffer 106 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x1AC++0x03
|
|
line.long 0x00 "BUFFER107,Buffer 107 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x1B0++0x03
|
|
line.long 0x00 "BUFFER108,Buffer 108 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x1B4++0x03
|
|
line.long 0x00 "BUFFER109,Buffer 109 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x1B8++0x03
|
|
line.long 0x00 "BUFFER110,Buffer 110 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x1BC++0x03
|
|
line.long 0x00 "BUFFER111,Buffer 111 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x1C0++0x03
|
|
line.long 0x00 "BUFFER112,Buffer 112 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x1C4++0x03
|
|
line.long 0x00 "BUFFER113,Buffer 113 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x1C8++0x03
|
|
line.long 0x00 "BUFFER114,Buffer 114 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x1CC++0x03
|
|
line.long 0x00 "BUFFER115,Buffer 115 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x1D0++0x03
|
|
line.long 0x00 "BUFFER116,Buffer 116 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x1D4++0x03
|
|
line.long 0x00 "BUFFER117,Buffer 117 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x1D8++0x03
|
|
line.long 0x00 "BUFFER118,Buffer 118 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x1DC++0x03
|
|
line.long 0x00 "BUFFER119,Buffer 119 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x1E0++0x03
|
|
line.long 0x00 "BUFFER120,Buffer 120 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x1E4++0x03
|
|
line.long 0x00 "BUFFER121,Buffer 121 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x1E8++0x03
|
|
line.long 0x00 "BUFFER122,Buffer 122 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x1EC++0x03
|
|
line.long 0x00 "BUFFER123,Buffer 123 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x1F0++0x03
|
|
line.long 0x00 "BUFFER124,Buffer 124 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x1F4++0x03
|
|
line.long 0x00 "BUFFER125,Buffer 125 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x1F8++0x03
|
|
line.long 0x00 "BUFFER126,Buffer 126 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x1FC++0x03
|
|
line.long 0x00 "BUFFER127,Buffer 127 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
tree.end
|
|
tree "Receive Buffers"
|
|
hgroup.long (0x0+0x200)++0x03
|
|
hide.long 0x00 "BUFFER0,Buffer 0 Register"
|
|
in
|
|
hgroup.long (0x4+0x200)++0x03
|
|
hide.long 0x00 "BUFFER1,Buffer 1 Register"
|
|
in
|
|
hgroup.long (0x8+0x200)++0x03
|
|
hide.long 0x00 "BUFFER2,Buffer 2 Register"
|
|
in
|
|
hgroup.long (0xC+0x200)++0x03
|
|
hide.long 0x00 "BUFFER3,Buffer 3 Register"
|
|
in
|
|
hgroup.long (0x10+0x200)++0x03
|
|
hide.long 0x00 "BUFFER4,Buffer 4 Register"
|
|
in
|
|
hgroup.long (0x14+0x200)++0x03
|
|
hide.long 0x00 "BUFFER5,Buffer 5 Register"
|
|
in
|
|
hgroup.long (0x18+0x200)++0x03
|
|
hide.long 0x00 "BUFFER6,Buffer 6 Register"
|
|
in
|
|
hgroup.long (0x1C+0x200)++0x03
|
|
hide.long 0x00 "BUFFER7,Buffer 7 Register"
|
|
in
|
|
hgroup.long (0x20+0x200)++0x03
|
|
hide.long 0x00 "BUFFER8,Buffer 8 Register"
|
|
in
|
|
hgroup.long (0x24+0x200)++0x03
|
|
hide.long 0x00 "BUFFER9,Buffer 9 Register"
|
|
in
|
|
hgroup.long (0x28+0x200)++0x03
|
|
hide.long 0x00 "BUFFER10,Buffer 10 Register"
|
|
in
|
|
hgroup.long (0x2C+0x200)++0x03
|
|
hide.long 0x00 "BUFFER11,Buffer 11 Register"
|
|
in
|
|
hgroup.long (0x30+0x200)++0x03
|
|
hide.long 0x00 "BUFFER12,Buffer 12 Register"
|
|
in
|
|
hgroup.long (0x34+0x200)++0x03
|
|
hide.long 0x00 "BUFFER13,Buffer 13 Register"
|
|
in
|
|
hgroup.long (0x38+0x200)++0x03
|
|
hide.long 0x00 "BUFFER14,Buffer 14 Register"
|
|
in
|
|
hgroup.long (0x3C+0x200)++0x03
|
|
hide.long 0x00 "BUFFER15,Buffer 15 Register"
|
|
in
|
|
hgroup.long (0x40+0x200)++0x03
|
|
hide.long 0x00 "BUFFER16,Buffer 16 Register"
|
|
in
|
|
hgroup.long (0x44+0x200)++0x03
|
|
hide.long 0x00 "BUFFER17,Buffer 17 Register"
|
|
in
|
|
hgroup.long (0x48+0x200)++0x03
|
|
hide.long 0x00 "BUFFER18,Buffer 18 Register"
|
|
in
|
|
hgroup.long (0x4C+0x200)++0x03
|
|
hide.long 0x00 "BUFFER19,Buffer 19 Register"
|
|
in
|
|
hgroup.long (0x50+0x200)++0x03
|
|
hide.long 0x00 "BUFFER20,Buffer 20 Register"
|
|
in
|
|
hgroup.long (0x54+0x200)++0x03
|
|
hide.long 0x00 "BUFFER21,Buffer 21 Register"
|
|
in
|
|
hgroup.long (0x58+0x200)++0x03
|
|
hide.long 0x00 "BUFFER22,Buffer 22 Register"
|
|
in
|
|
hgroup.long (0x5C+0x200)++0x03
|
|
hide.long 0x00 "BUFFER23,Buffer 23 Register"
|
|
in
|
|
hgroup.long (0x60+0x200)++0x03
|
|
hide.long 0x00 "BUFFER24,Buffer 24 Register"
|
|
in
|
|
hgroup.long (0x64+0x200)++0x03
|
|
hide.long 0x00 "BUFFER25,Buffer 25 Register"
|
|
in
|
|
hgroup.long (0x68+0x200)++0x03
|
|
hide.long 0x00 "BUFFER26,Buffer 26 Register"
|
|
in
|
|
hgroup.long (0x6C+0x200)++0x03
|
|
hide.long 0x00 "BUFFER27,Buffer 27 Register"
|
|
in
|
|
hgroup.long (0x70+0x200)++0x03
|
|
hide.long 0x00 "BUFFER28,Buffer 28 Register"
|
|
in
|
|
hgroup.long (0x74+0x200)++0x03
|
|
hide.long 0x00 "BUFFER29,Buffer 29 Register"
|
|
in
|
|
hgroup.long (0x78+0x200)++0x03
|
|
hide.long 0x00 "BUFFER30,Buffer 30 Register"
|
|
in
|
|
hgroup.long (0x7C+0x200)++0x03
|
|
hide.long 0x00 "BUFFER31,Buffer 31 Register"
|
|
in
|
|
hgroup.long (0x80+0x200)++0x03
|
|
hide.long 0x00 "BUFFER32,Buffer 32 Register"
|
|
in
|
|
hgroup.long (0x84+0x200)++0x03
|
|
hide.long 0x00 "BUFFER33,Buffer 33 Register"
|
|
in
|
|
hgroup.long (0x88+0x200)++0x03
|
|
hide.long 0x00 "BUFFER34,Buffer 34 Register"
|
|
in
|
|
hgroup.long (0x8C+0x200)++0x03
|
|
hide.long 0x00 "BUFFER35,Buffer 35 Register"
|
|
in
|
|
hgroup.long (0x90+0x200)++0x03
|
|
hide.long 0x00 "BUFFER36,Buffer 36 Register"
|
|
in
|
|
hgroup.long (0x94+0x200)++0x03
|
|
hide.long 0x00 "BUFFER37,Buffer 37 Register"
|
|
in
|
|
hgroup.long (0x98+0x200)++0x03
|
|
hide.long 0x00 "BUFFER38,Buffer 38 Register"
|
|
in
|
|
hgroup.long (0x9C+0x200)++0x03
|
|
hide.long 0x00 "BUFFER39,Buffer 39 Register"
|
|
in
|
|
hgroup.long (0xA0+0x200)++0x03
|
|
hide.long 0x00 "BUFFER40,Buffer 40 Register"
|
|
in
|
|
hgroup.long (0xA4+0x200)++0x03
|
|
hide.long 0x00 "BUFFER41,Buffer 41 Register"
|
|
in
|
|
hgroup.long (0xA8+0x200)++0x03
|
|
hide.long 0x00 "BUFFER42,Buffer 42 Register"
|
|
in
|
|
hgroup.long (0xAC+0x200)++0x03
|
|
hide.long 0x00 "BUFFER43,Buffer 43 Register"
|
|
in
|
|
hgroup.long (0xB0+0x200)++0x03
|
|
hide.long 0x00 "BUFFER44,Buffer 44 Register"
|
|
in
|
|
hgroup.long (0xB4+0x200)++0x03
|
|
hide.long 0x00 "BUFFER45,Buffer 45 Register"
|
|
in
|
|
hgroup.long (0xB8+0x200)++0x03
|
|
hide.long 0x00 "BUFFER46,Buffer 46 Register"
|
|
in
|
|
hgroup.long (0xBC+0x200)++0x03
|
|
hide.long 0x00 "BUFFER47,Buffer 47 Register"
|
|
in
|
|
hgroup.long (0xC0+0x200)++0x03
|
|
hide.long 0x00 "BUFFER48,Buffer 48 Register"
|
|
in
|
|
hgroup.long (0xC4+0x200)++0x03
|
|
hide.long 0x00 "BUFFER49,Buffer 49 Register"
|
|
in
|
|
hgroup.long (0xC8+0x200)++0x03
|
|
hide.long 0x00 "BUFFER50,Buffer 50 Register"
|
|
in
|
|
hgroup.long (0xCC+0x200)++0x03
|
|
hide.long 0x00 "BUFFER51,Buffer 51 Register"
|
|
in
|
|
hgroup.long (0xD0+0x200)++0x03
|
|
hide.long 0x00 "BUFFER52,Buffer 52 Register"
|
|
in
|
|
hgroup.long (0xD4+0x200)++0x03
|
|
hide.long 0x00 "BUFFER53,Buffer 53 Register"
|
|
in
|
|
hgroup.long (0xD8+0x200)++0x03
|
|
hide.long 0x00 "BUFFER54,Buffer 54 Register"
|
|
in
|
|
hgroup.long (0xDC+0x200)++0x03
|
|
hide.long 0x00 "BUFFER55,Buffer 55 Register"
|
|
in
|
|
hgroup.long (0xE0+0x200)++0x03
|
|
hide.long 0x00 "BUFFER56,Buffer 56 Register"
|
|
in
|
|
hgroup.long (0xE4+0x200)++0x03
|
|
hide.long 0x00 "BUFFER57,Buffer 57 Register"
|
|
in
|
|
hgroup.long (0xE8+0x200)++0x03
|
|
hide.long 0x00 "BUFFER58,Buffer 58 Register"
|
|
in
|
|
hgroup.long (0xEC+0x200)++0x03
|
|
hide.long 0x00 "BUFFER59,Buffer 59 Register"
|
|
in
|
|
hgroup.long (0xF0+0x200)++0x03
|
|
hide.long 0x00 "BUFFER60,Buffer 60 Register"
|
|
in
|
|
hgroup.long (0xF4+0x200)++0x03
|
|
hide.long 0x00 "BUFFER61,Buffer 61 Register"
|
|
in
|
|
hgroup.long (0xF8+0x200)++0x03
|
|
hide.long 0x00 "BUFFER62,Buffer 62 Register"
|
|
in
|
|
hgroup.long (0xFC+0x200)++0x03
|
|
hide.long 0x00 "BUFFER63,Buffer 63 Register"
|
|
in
|
|
hgroup.long (0x100+0x200)++0x03
|
|
hide.long 0x00 "BUFFER64,Buffer 64 Register"
|
|
in
|
|
hgroup.long (0x104+0x200)++0x03
|
|
hide.long 0x00 "BUFFER65,Buffer 65 Register"
|
|
in
|
|
hgroup.long (0x108+0x200)++0x03
|
|
hide.long 0x00 "BUFFER66,Buffer 66 Register"
|
|
in
|
|
hgroup.long (0x10C+0x200)++0x03
|
|
hide.long 0x00 "BUFFER67,Buffer 67 Register"
|
|
in
|
|
hgroup.long (0x110+0x200)++0x03
|
|
hide.long 0x00 "BUFFER68,Buffer 68 Register"
|
|
in
|
|
hgroup.long (0x114+0x200)++0x03
|
|
hide.long 0x00 "BUFFER69,Buffer 69 Register"
|
|
in
|
|
hgroup.long (0x118+0x200)++0x03
|
|
hide.long 0x00 "BUFFER70,Buffer 70 Register"
|
|
in
|
|
hgroup.long (0x11C+0x200)++0x03
|
|
hide.long 0x00 "BUFFER71,Buffer 71 Register"
|
|
in
|
|
hgroup.long (0x120+0x200)++0x03
|
|
hide.long 0x00 "BUFFER72,Buffer 72 Register"
|
|
in
|
|
hgroup.long (0x124+0x200)++0x03
|
|
hide.long 0x00 "BUFFER73,Buffer 73 Register"
|
|
in
|
|
hgroup.long (0x128+0x200)++0x03
|
|
hide.long 0x00 "BUFFER74,Buffer 74 Register"
|
|
in
|
|
hgroup.long (0x12C+0x200)++0x03
|
|
hide.long 0x00 "BUFFER75,Buffer 75 Register"
|
|
in
|
|
hgroup.long (0x130+0x200)++0x03
|
|
hide.long 0x00 "BUFFER76,Buffer 76 Register"
|
|
in
|
|
hgroup.long (0x134+0x200)++0x03
|
|
hide.long 0x00 "BUFFER77,Buffer 77 Register"
|
|
in
|
|
hgroup.long (0x138+0x200)++0x03
|
|
hide.long 0x00 "BUFFER78,Buffer 78 Register"
|
|
in
|
|
hgroup.long (0x13C+0x200)++0x03
|
|
hide.long 0x00 "BUFFER79,Buffer 79 Register"
|
|
in
|
|
hgroup.long (0x140+0x200)++0x03
|
|
hide.long 0x00 "BUFFER80,Buffer 80 Register"
|
|
in
|
|
hgroup.long (0x144+0x200)++0x03
|
|
hide.long 0x00 "BUFFER81,Buffer 81 Register"
|
|
in
|
|
hgroup.long (0x148+0x200)++0x03
|
|
hide.long 0x00 "BUFFER82,Buffer 82 Register"
|
|
in
|
|
hgroup.long (0x14C+0x200)++0x03
|
|
hide.long 0x00 "BUFFER83,Buffer 83 Register"
|
|
in
|
|
hgroup.long (0x150+0x200)++0x03
|
|
hide.long 0x00 "BUFFER84,Buffer 84 Register"
|
|
in
|
|
hgroup.long (0x154+0x200)++0x03
|
|
hide.long 0x00 "BUFFER85,Buffer 85 Register"
|
|
in
|
|
hgroup.long (0x158+0x200)++0x03
|
|
hide.long 0x00 "BUFFER86,Buffer 86 Register"
|
|
in
|
|
hgroup.long (0x15C+0x200)++0x03
|
|
hide.long 0x00 "BUFFER87,Buffer 87 Register"
|
|
in
|
|
hgroup.long (0x160+0x200)++0x03
|
|
hide.long 0x00 "BUFFER88,Buffer 88 Register"
|
|
in
|
|
hgroup.long (0x164+0x200)++0x03
|
|
hide.long 0x00 "BUFFER89,Buffer 89 Register"
|
|
in
|
|
hgroup.long (0x168+0x200)++0x03
|
|
hide.long 0x00 "BUFFER90,Buffer 90 Register"
|
|
in
|
|
hgroup.long (0x16C+0x200)++0x03
|
|
hide.long 0x00 "BUFFER91,Buffer 91 Register"
|
|
in
|
|
hgroup.long (0x170+0x200)++0x03
|
|
hide.long 0x00 "BUFFER92,Buffer 92 Register"
|
|
in
|
|
hgroup.long (0x174+0x200)++0x03
|
|
hide.long 0x00 "BUFFER93,Buffer 93 Register"
|
|
in
|
|
hgroup.long (0x178+0x200)++0x03
|
|
hide.long 0x00 "BUFFER94,Buffer 94 Register"
|
|
in
|
|
hgroup.long (0x17C+0x200)++0x03
|
|
hide.long 0x00 "BUFFER95,Buffer 95 Register"
|
|
in
|
|
hgroup.long (0x180+0x200)++0x03
|
|
hide.long 0x00 "BUFFER96,Buffer 96 Register"
|
|
in
|
|
hgroup.long (0x184+0x200)++0x03
|
|
hide.long 0x00 "BUFFER97,Buffer 97 Register"
|
|
in
|
|
hgroup.long (0x188+0x200)++0x03
|
|
hide.long 0x00 "BUFFER98,Buffer 98 Register"
|
|
in
|
|
hgroup.long (0x18C+0x200)++0x03
|
|
hide.long 0x00 "BUFFER99,Buffer 99 Register"
|
|
in
|
|
hgroup.long (0x190+0x200)++0x03
|
|
hide.long 0x00 "BUFFER100,Buffer 100 Register"
|
|
in
|
|
hgroup.long (0x194+0x200)++0x03
|
|
hide.long 0x00 "BUFFER101,Buffer 101 Register"
|
|
in
|
|
hgroup.long (0x198+0x200)++0x03
|
|
hide.long 0x00 "BUFFER102,Buffer 102 Register"
|
|
in
|
|
hgroup.long (0x19C+0x200)++0x03
|
|
hide.long 0x00 "BUFFER103,Buffer 103 Register"
|
|
in
|
|
hgroup.long (0x1A0+0x200)++0x03
|
|
hide.long 0x00 "BUFFER104,Buffer 104 Register"
|
|
in
|
|
hgroup.long (0x1A4+0x200)++0x03
|
|
hide.long 0x00 "BUFFER105,Buffer 105 Register"
|
|
in
|
|
hgroup.long (0x1A8+0x200)++0x03
|
|
hide.long 0x00 "BUFFER106,Buffer 106 Register"
|
|
in
|
|
hgroup.long (0x1AC+0x200)++0x03
|
|
hide.long 0x00 "BUFFER107,Buffer 107 Register"
|
|
in
|
|
hgroup.long (0x1B0+0x200)++0x03
|
|
hide.long 0x00 "BUFFER108,Buffer 108 Register"
|
|
in
|
|
hgroup.long (0x1B4+0x200)++0x03
|
|
hide.long 0x00 "BUFFER109,Buffer 109 Register"
|
|
in
|
|
hgroup.long (0x1B8+0x200)++0x03
|
|
hide.long 0x00 "BUFFER110,Buffer 110 Register"
|
|
in
|
|
hgroup.long (0x1BC+0x200)++0x03
|
|
hide.long 0x00 "BUFFER111,Buffer 111 Register"
|
|
in
|
|
hgroup.long (0x1C0+0x200)++0x03
|
|
hide.long 0x00 "BUFFER112,Buffer 112 Register"
|
|
in
|
|
hgroup.long (0x1C4+0x200)++0x03
|
|
hide.long 0x00 "BUFFER113,Buffer 113 Register"
|
|
in
|
|
hgroup.long (0x1C8+0x200)++0x03
|
|
hide.long 0x00 "BUFFER114,Buffer 114 Register"
|
|
in
|
|
hgroup.long (0x1CC+0x200)++0x03
|
|
hide.long 0x00 "BUFFER115,Buffer 115 Register"
|
|
in
|
|
hgroup.long (0x1D0+0x200)++0x03
|
|
hide.long 0x00 "BUFFER116,Buffer 116 Register"
|
|
in
|
|
hgroup.long (0x1D4+0x200)++0x03
|
|
hide.long 0x00 "BUFFER117,Buffer 117 Register"
|
|
in
|
|
hgroup.long (0x1D8+0x200)++0x03
|
|
hide.long 0x00 "BUFFER118,Buffer 118 Register"
|
|
in
|
|
hgroup.long (0x1DC+0x200)++0x03
|
|
hide.long 0x00 "BUFFER119,Buffer 119 Register"
|
|
in
|
|
hgroup.long (0x1E0+0x200)++0x03
|
|
hide.long 0x00 "BUFFER120,Buffer 120 Register"
|
|
in
|
|
hgroup.long (0x1E4+0x200)++0x03
|
|
hide.long 0x00 "BUFFER121,Buffer 121 Register"
|
|
in
|
|
hgroup.long (0x1E8+0x200)++0x03
|
|
hide.long 0x00 "BUFFER122,Buffer 122 Register"
|
|
in
|
|
hgroup.long (0x1EC+0x200)++0x03
|
|
hide.long 0x00 "BUFFER123,Buffer 123 Register"
|
|
in
|
|
hgroup.long (0x1F0+0x200)++0x03
|
|
hide.long 0x00 "BUFFER124,Buffer 124 Register"
|
|
in
|
|
hgroup.long (0x1F4+0x200)++0x03
|
|
hide.long 0x00 "BUFFER125,Buffer 125 Register"
|
|
in
|
|
hgroup.long (0x1F8+0x200)++0x03
|
|
hide.long 0x00 "BUFFER126,Buffer 126 Register"
|
|
in
|
|
hgroup.long (0x1FC+0x200)++0x03
|
|
hide.long 0x00 "BUFFER127,Buffer 127 Register"
|
|
in
|
|
tree.end
|
|
endif
|
|
sif cpuis("TMS570LS0232")||cpuis("TMS570LS0714*")||cpuis("TMS570LS0914*")
|
|
endian.le
|
|
endif
|
|
width 0xB
|
|
tree.end
|
|
tree "SPI2"
|
|
base ad:0xFFF7F600
|
|
width 17.
|
|
sif cpuis("TMS570LS0232")||cpuis("TMS570LS0714*")||cpuis("TMS570LS0914*")
|
|
endian.be
|
|
endif
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "SPIGCR0,SPI Global Control Register 0"
|
|
bitfld.long 0x00 0. " NRESET ,Reset bit for the module" "No reset,Reset"
|
|
group.long 0x04++0x0F
|
|
line.long 0x00 "SPIGCR1,SPI Global Control Register 1"
|
|
bitfld.long 0x00 24. " SPIEN ,SPI enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " LOOPBACK ,Internal loop-back test mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " POWERDOWN ,SPI state machine enters a power-down state" "No power-down,Power-down"
|
|
newline
|
|
bitfld.long 0x00 1. " CLKMOD ,Clock mode" "External,Internally"
|
|
bitfld.long 0x00 0. " MASTER ,SPISIMO/SPISOMI pin direction determination" "Input/output,Output/input"
|
|
line.long 0x04 "SPIINT0,SPI Interrupt Register"
|
|
bitfld.long 0x04 24. " ENABLEHIGHZ ,SPIENA pin high-impedance enable" "Inactive,Active"
|
|
bitfld.long 0x04 16. " DMAREQEN ,DMA request enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 9. " TXINTENA ,TX interrupt flag enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x04 8. " RXINTENA ,RX interrupt flag enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 6. " RXOVRNINTENA ,Overrun interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 4. " BITERRENA ,Enables interrupt on bit error" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x04 3. " DESYNCENA ,Enables interrupt on desynchronized slave" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " PARERRENA ,Enables interrupt-on-parity-error" "Disabled,Enabled"
|
|
bitfld.long 0x04 1. " TIMEOUTENA ,Enables interrupt on ENA signal time-out" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x04 0. " DLENERRENA ,Data length error interrupt enable" "Disabled,Enabled"
|
|
line.long 0x08 "SPILVL,SPI Interrupt Level Register"
|
|
bitfld.long 0x08 9. " TXINTLVL ,Transmit interrupt level" "INT0,INT1"
|
|
bitfld.long 0x08 8. " RXINTLVL ,Receive interrupt level" "INT0,INT1"
|
|
sif !cpuis("TMS570LS0232")
|
|
bitfld.long 0x08 6. " RXOVRNINTLVL ,Receive overrun interrupt level" "INT0,INT1"
|
|
endif
|
|
newline
|
|
bitfld.long 0x08 4. " BITERRLVL ,Bit error interrupt level" "INT0,INT1"
|
|
bitfld.long 0x08 3. " DESYNCLVL ,Desynchronized slave interrupt level (master mode only)" "INT0,INT1"
|
|
bitfld.long 0x08 2. " PARERRLVL ,Parity error interrupt level" "INT0,INT1"
|
|
newline
|
|
bitfld.long 0x08 1. " TIMEOUTLVL ,SPIENA pin time-out interrupt level" "INT0,INT1"
|
|
bitfld.long 0x08 0. " DLENERRLVL ,Data length error interrupt level (line) select" "INT0,INT1"
|
|
line.long 0x0C "SPIFLG,SPI Flag Register"
|
|
bitfld.long 0x0C 24. " BUFINITACTIVE ,Indicates the status of multi-buffer initialization process" "Completed,Not completed"
|
|
bitfld.long 0x0C 9. " TXINTFLG ,Transmitter-empty interrupt flag" "No interrupt,Interrupt"
|
|
eventfld.long 0x0C 8. " RXINTFLG ,Receiver-full interrupt flag" "No interrupt,Interrupt"
|
|
newline
|
|
eventfld.long 0x0C 6. " RXOVRNINTFLG ,Overrun interrupt enable" "Disabled,Enabled"
|
|
eventfld.long 0x0C 4. " BITERRFLG ,Enables interrupt on bit error" "Disabled,Enabled"
|
|
eventfld.long 0x0C 3. " DESYNCFLG ,Enables interrupt on desynchronized slave" "No interrupt,Interrupt"
|
|
newline
|
|
eventfld.long 0x0C 2. " PARITYERRFLG ,Enables interrupt-on-parity-error" "No error,Error"
|
|
eventfld.long 0x0C 1. " TIMEOUTFLG ,Enables interrupt on ENA signal time-out" "No interrupt,Interrupt"
|
|
eventfld.long 0x0C 0. " DLENERRFLG ,Data length error interrupt enable" "No interrupt,Interrupt"
|
|
group.long 0x14++0x23
|
|
line.long 0x00 "SPIPC0,SPI Pin Control Register 0"
|
|
sif !cpuis("TMS570LS0232")&&!cpuis("TMS570LS0332")&&!cpuis("TMS570LS0432")
|
|
bitfld.long 0x00 31. " SOMIFUN7 ,SPISOMI[7] pin function" "GIO,SPI"
|
|
bitfld.long 0x00 30. " SOMIFUN6 ,SPISOMI[6] pin function" "GIO,SPI"
|
|
bitfld.long 0x00 29. " SOMIFUN5 ,SPISOMI[5] pin function" "GIO,SPI"
|
|
newline
|
|
bitfld.long 0x00 28. " SOMIFUN4 ,SPISOMI[4] pin function" "GIO,SPI"
|
|
bitfld.long 0x00 27. " SOMIFUN3 ,SPISOMI[3] pin function" "GIO,SPI"
|
|
bitfld.long 0x00 26. " SOMIFUN2 ,SPISOMI[2] pin function" "GIO,SPI"
|
|
newline
|
|
bitfld.long 0x00 25. " SOMIFUN1 ,SPISOMI[1] pin function" "GIO,SPI"
|
|
bitfld.long 0x00 24. " SOMIFUN0 ,SPISOMI[0] pin function (mirror of bit 11)" "GIO,SPI"
|
|
bitfld.long 0x00 23. " SIMOFUN7 ,SPISIMO[7] pin function" "GIO,SPI"
|
|
newline
|
|
bitfld.long 0x00 22. " SIMOFUN6 ,SPISIMO[6] pin function" "GIO,SPI"
|
|
bitfld.long 0x00 21. " SIMOFUN5 ,SPISIMO[5] pin function" "GIO,SPI"
|
|
bitfld.long 0x00 20. " SIMOFUN4 ,SPISIMO[4] pin function" "GIO,SPI"
|
|
newline
|
|
bitfld.long 0x00 19. " SIMOFUN3 ,SPISIMO[3] pin function" "GIO,SPI"
|
|
bitfld.long 0x00 18. " SIMOFUN2 ,SPISIMO[2] pin function" "GIO,SPI"
|
|
bitfld.long 0x00 17. " SIMOFUN1 ,SPISIMO[1] pin function" "GIO,SPI"
|
|
newline
|
|
bitfld.long 0x00 16. " SIMOFUN0 ,SPISIMO[0] pin function (mirror of bit 10)" "GIO,SPI"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 11. " SOMIFUN0 ,SPISOMI[0] pin function" "GIO,SPI"
|
|
bitfld.long 0x00 10. " SIMOFUN0 ,SPISIMO[0] pin function" "GIO,SPI"
|
|
newline
|
|
bitfld.long 0x00 9. " CLKFUN ,SPI clock function" "GIO,SPI"
|
|
bitfld.long 0x00 8. " ENAFUN ,SPIENA function" "GIO,SPI"
|
|
bitfld.long 0x00 7. " SCSFUN7 ,SPISCS7 function 7" "GIO,SPI"
|
|
newline
|
|
bitfld.long 0x00 6. " SCSFUN6 ,SPISCS6 function 6" "GIO,SPI"
|
|
bitfld.long 0x00 5. " SCSFUN5 ,SPISCS5 function 5" "GIO,SPI"
|
|
bitfld.long 0x00 4. " SCSFUN4 ,SPISCS4 function 4" "GIO,SPI"
|
|
newline
|
|
bitfld.long 0x00 3. " SCSFUN3 ,SPISCS3 function 3" "GIO,SPI"
|
|
bitfld.long 0x00 2. " SCSFUN2 ,SPISCS2 function 2" "GIO,SPI"
|
|
bitfld.long 0x00 1. " SCSFUN1 ,SPISCS1 function 1" "GIO,SPI"
|
|
newline
|
|
bitfld.long 0x00 0. " SCSFUN0 ,SPISCS0 function 0" "GIO,SPI"
|
|
line.long 0x04 "SPIPC1,SPI Pin Control Register 1"
|
|
bitfld.long 0x04 31. " SOMIDIR7 ,SPISOMI[7] pin direction" "GIO,SPI"
|
|
bitfld.long 0x04 30. " SOMIDIR6 ,SPISOMI[6] pin direction" "GIO,SPI"
|
|
bitfld.long 0x04 29. " SOMIDIR5 ,SPISOMI[5] pin direction" "GIO,SPI"
|
|
newline
|
|
bitfld.long 0x04 28. " SOMIDIR4 ,SPISOMI[4] pin direction" "GIO,SPI"
|
|
bitfld.long 0x04 27. " SOMIDIR3 ,SPISOMI[3] pin direction" "GIO,SPI"
|
|
bitfld.long 0x04 26. " SOMIDIR2 ,SPISOMI[2] pin direction" "GIO,SPI"
|
|
newline
|
|
bitfld.long 0x04 25. " SOMIDIR1 ,SPISOMI[1] pin direction" "GIO,SPI"
|
|
bitfld.long 0x04 24. " SOMIDIR0 ,SPISOMI[0] pin direction (mirror of bit 11)" "GIO,SPI"
|
|
bitfld.long 0x04 23. " SIMODIR7 ,SPISIMO[7] pin direction" "GIO,SPI"
|
|
newline
|
|
bitfld.long 0x04 22. " SIMODIR6 ,SPISIMO[6] pin direction" "GIO,SPI"
|
|
bitfld.long 0x04 21. " SIMODIR5 ,SPISIMO[5] pin direction" "GIO,SPI"
|
|
bitfld.long 0x04 20. " SIMODIR4 ,SPISIMO[4] pin direction" "GIO,SPI"
|
|
newline
|
|
bitfld.long 0x04 19. " SIMODIR3 ,SPISIMO[3] pin direction" "GIO,SPI"
|
|
bitfld.long 0x04 18. " SIMODIR2 ,SPISIMO[2] pin direction" "GIO,SPI"
|
|
bitfld.long 0x04 17. " SIMODIR1 ,SPISIMO[1] pin direction" "GIO,SPI"
|
|
newline
|
|
bitfld.long 0x04 16. " SIMODIR0 ,SPISIMO[0] pin direction (mirror of bit 10)" "GIO,SPI"
|
|
bitfld.long 0x04 11. " SOMIDIR0 ,SPISOMI[0] pin direction" "GIO,SPI"
|
|
bitfld.long 0x04 10. " SIMODIR0 ,SPISIMO[0] pin direction" "GIO,SPI"
|
|
newline
|
|
bitfld.long 0x04 9. " CLKDIR ,SPI clock direction" "GIO,SPI"
|
|
bitfld.long 0x04 8. " ENADIR ,SPIENA direction" "GIO,SPI"
|
|
bitfld.long 0x04 7. " SCSDIR7 ,SPISCS7 direction 7" "GIO,SPI"
|
|
newline
|
|
bitfld.long 0x04 6. " SCSDIR6 ,SPISCS6 direction 6" "GIO,SPI"
|
|
bitfld.long 0x04 5. " SCSDIR5 ,SPISCS5 direction 5" "GIO,SPI"
|
|
bitfld.long 0x04 4. " SCSDIR4 ,SPISCS4 direction 4" "GIO,SPI"
|
|
newline
|
|
bitfld.long 0x04 3. " SCSDIR3 ,SPISCS3 direction 3" "GIO,SPI"
|
|
bitfld.long 0x04 2. " SCSDIR2 ,SPISCS2 direction 2" "GIO,SPI"
|
|
bitfld.long 0x04 1. " SCSDIR1 ,SPISCS1 direction 1" "GIO,SPI"
|
|
newline
|
|
bitfld.long 0x04 0. " SCSDIR0 ,SPISCS0 direction 0" "GIO,SPI"
|
|
line.long 0x08 "SPIPC2,SPI Pin Control Register 2"
|
|
bitfld.long 0x08 31. " SOMIDIN7 ,SPISOMI[7] data in" "0,1"
|
|
bitfld.long 0x08 30. " SOMIDIN6 ,SPISOMI[6] data in" "0,1"
|
|
bitfld.long 0x08 29. " SOMIDIN5 ,SPISOMI[5] data in" "0,1"
|
|
newline
|
|
bitfld.long 0x08 28. " SOMIDIN4 ,SPISOMI[4] data in" "0,1"
|
|
bitfld.long 0x08 27. " SOMIDIN3 ,SPISOMI[3] data in" "0,1"
|
|
bitfld.long 0x08 26. " SOMIDIN2 ,SPISOMI[2] data in" "0,1"
|
|
newline
|
|
bitfld.long 0x08 25. " SOMIDIN1 ,SPISOMI[1] data in" "0,1"
|
|
bitfld.long 0x08 24. " SOMIDIN0 ,SPISOMI[0] data in (mirror of bit 11)" "0,1"
|
|
bitfld.long 0x08 23. " SIMODIN7 ,SPISIMO[7] data in" "0,1"
|
|
newline
|
|
bitfld.long 0x08 22. " SIMODIN6 ,SPISIMO[6] data in" "0,1"
|
|
bitfld.long 0x08 21. " SIMODIN5 ,SPISIMO[5] data in" "0,1"
|
|
bitfld.long 0x08 20. " SIMODIN4 ,SPISIMO[4] data in" "0,1"
|
|
newline
|
|
bitfld.long 0x08 19. " SIMODIN3 ,SPISIMO[3] data in" "0,1"
|
|
bitfld.long 0x08 18. " SIMODIN2 ,SPISIMO[2] data in" "0,1"
|
|
bitfld.long 0x08 17. " SIMODIN1 ,SPISIMO[1] data in" "0,1"
|
|
newline
|
|
bitfld.long 0x08 16. " SIMODIN0 ,SPISIMO[0] data in (mirror of bit 10)" "0,1"
|
|
bitfld.long 0x08 11. " SOMIDIN0 ,SPISOMI[0] data in" "0,1"
|
|
bitfld.long 0x08 10. " SIMODIN0 ,SPISIMO[0] data in" "0,1"
|
|
newline
|
|
bitfld.long 0x08 9. " CLKDIN ,SPI clock data in" "0,1"
|
|
bitfld.long 0x08 8. " ENADIN ,SPIENA data in" "0,1"
|
|
bitfld.long 0x08 7. " SCSDIN7 ,SPISCS7 data in" "0,1"
|
|
newline
|
|
bitfld.long 0x08 6. " SCSDIN6 ,SPISCS6 data in" "0,1"
|
|
bitfld.long 0x08 5. " SCSDIN5 ,SPISCS5 data in" "0,1"
|
|
bitfld.long 0x08 4. " SCSDIN4 ,SPISCS4 data in" "0,1"
|
|
newline
|
|
bitfld.long 0x08 3. " SCSDIN3 ,SPISCS3 data in" "0,1"
|
|
bitfld.long 0x08 2. " SCSDIN2 ,SPISCS2 data in" "0,1"
|
|
bitfld.long 0x08 1. " SCSDIN1 ,SPISCS1 data in" "0,1"
|
|
newline
|
|
bitfld.long 0x08 0. " SCSDIN0 ,SPISCS0 direction 0" "0,1"
|
|
line.long 0x0C "SPIPC3,SPI Pin Control Register 3"
|
|
bitfld.long 0x0C 31. " SOMIDOUT7 ,SPISOMI[7] data out write" "0,1"
|
|
bitfld.long 0x0C 30. " SOMIDOUT6 ,SPISOMI[6] data out write" "0,1"
|
|
bitfld.long 0x0C 29. " SOMIDOUT5 ,SPISOMI[5] data out write" "0,1"
|
|
newline
|
|
bitfld.long 0x0C 28. " SOMIDOUT4 ,SPISOMI[4] data out write" "0,1"
|
|
bitfld.long 0x0C 27. " SOMIDOUT3 ,SPISOMI[3] data out write" "0,1"
|
|
bitfld.long 0x0C 26. " SOMIDOUT2 ,SPISOMI[2] data out write" "0,1"
|
|
newline
|
|
bitfld.long 0x0C 25. " SOMIDOUT1 ,SPISOMI[1] data out write" "0,1"
|
|
bitfld.long 0x0C 24. " SOMIDOUT0 ,SPISOMI[0] data out write (mirror of bit 11)" "0,1"
|
|
bitfld.long 0x0C 23. " SIMODOUT7 ,SPISIMO[7] data out write" "0,1"
|
|
newline
|
|
bitfld.long 0x0C 22. " SIMODOUT6 ,SPISIMO[6] data out write" "0,1"
|
|
bitfld.long 0x0C 21. " SIMODOUT5 ,SPISIMO[5] data out write" "0,1"
|
|
bitfld.long 0x0C 20. " SIMODOUT4 ,SPISIMO[4] data out write" "0,1"
|
|
newline
|
|
bitfld.long 0x0C 19. " SIMODOUT3 ,SPISIMO[3] data out write" "0,1"
|
|
bitfld.long 0x0C 18. " SIMODOUT2 ,SPISIMO[2] data out write" "0,1"
|
|
bitfld.long 0x0C 17. " SIMODOUT1 ,SPISIMO[1] data out write" "0,1"
|
|
newline
|
|
bitfld.long 0x0C 16. " SIMODOUT0 ,SPISIMO[0] data out write (mirror of bit 10)" "0,1"
|
|
bitfld.long 0x0C 11. " SOMIDOUT0 ,SPISOMI[0] data out write" "0,1"
|
|
bitfld.long 0x0C 10. " SIMODOUT0 ,SPISIMO[0] data out write" "0,1"
|
|
newline
|
|
bitfld.long 0x0C 9. " CLKDOUT ,SPI clock data out write" "0,1"
|
|
bitfld.long 0x0C 8. " ENADOUT ,SPIENA data out write" "0,1"
|
|
bitfld.long 0x0C 7. " SCSDOUT7 ,SPISCS7 data out write" "0,1"
|
|
newline
|
|
bitfld.long 0x0C 6. " SCSDOUT6 ,SPISCS6 data out write" "0,1"
|
|
bitfld.long 0x0C 5. " SCSDOUT5 ,SPISCS5 data out write" "0,1"
|
|
bitfld.long 0x0C 4. " SCSDOUT4 ,SPISCS4 data out write" "0,1"
|
|
newline
|
|
bitfld.long 0x0C 3. " SCSDOUT3 ,SPISCS3 data out write" "0,1"
|
|
bitfld.long 0x0C 2. " SCSDOUT2 ,SPISCS2 data out write" "0,1"
|
|
bitfld.long 0x0C 1. " SCSDOUT1 ,SPISCS1 data out write" "0,1"
|
|
newline
|
|
bitfld.long 0x0C 0. " SCSDOUT0 ,SPISCS0 data out write" "0,1"
|
|
line.long 0x10 "SPIPC4,SPI Pin Control Register 4"
|
|
bitfld.long 0x10 31. " SOMISET7 ,SPISOMI[7] data out set" "0,1"
|
|
bitfld.long 0x10 30. " SOMISET6 ,SPISOMI[6] data out set" "0,1"
|
|
bitfld.long 0x10 29. " SOMISET5 ,SPISOMI[5] data out set" "0,1"
|
|
newline
|
|
bitfld.long 0x10 28. " SOMISET4 ,SPISOMI[4] data out set" "0,1"
|
|
bitfld.long 0x10 27. " SOMISET3 ,SPISOMI[3] data out set" "0,1"
|
|
bitfld.long 0x10 26. " SOMISET2 ,SPISOMI[2] data out set" "0,1"
|
|
newline
|
|
bitfld.long 0x10 25. " SOMISET1 ,SPISOMI[1] data out set" "0,1"
|
|
bitfld.long 0x10 24. " SOMISET0 ,SPISOMI[0] data out set (mirror of bit 11)" "0,1"
|
|
bitfld.long 0x10 23. " SIMOSET7 ,SPISIMO[7] data out set" "0,1"
|
|
newline
|
|
bitfld.long 0x10 22. " SIMOSET6 ,SPISIMO[6] data out set" "0,1"
|
|
bitfld.long 0x10 21. " SIMOSET5 ,SPISIMO[5] data out set" "0,1"
|
|
bitfld.long 0x10 20. " SIMOSET4 ,SPISIMO[4] data out set" "0,1"
|
|
newline
|
|
bitfld.long 0x10 19. " SIMOSET3 ,SPISIMO[3] data out set" "0,1"
|
|
bitfld.long 0x10 18. " SIMOSET2 ,SPISIMO[2] data out set" "0,1"
|
|
bitfld.long 0x10 17. " SIMOSET1 ,SPISIMO[1] data out set" "0,1"
|
|
newline
|
|
bitfld.long 0x10 16. " SIMOSET0 ,SPISIMO[0] data out set (mirror of bit 10)" "0,1"
|
|
bitfld.long 0x10 11. " SOMISET0 ,SPISOMI[0] data out set" "0,1"
|
|
bitfld.long 0x10 10. " SIMOSET0 ,SPISIMO[0] data out set" "0,1"
|
|
newline
|
|
bitfld.long 0x10 9. " CLKSET ,SPI clock data out set" "0,1"
|
|
bitfld.long 0x10 8. " ENASET ,SPIENA data out set" "0,1"
|
|
bitfld.long 0x10 7. " SCSSET7 ,SPISCS7 data out set" "0,1"
|
|
newline
|
|
bitfld.long 0x10 6. " SCSSET6 ,SPISCS6 data out set" "0,1"
|
|
bitfld.long 0x10 5. " SCSSET5 ,SPISCS5 data out set" "0,1"
|
|
bitfld.long 0x10 4. " SCSSET4 ,SPISCS4 data out set" "0,1"
|
|
newline
|
|
bitfld.long 0x10 3. " SCSSET3 ,SPISCS3 data out set" "0,1"
|
|
bitfld.long 0x10 2. " SCSSET2 ,SPISCS2 data out set" "0,1"
|
|
bitfld.long 0x10 1. " SCSSET1 ,SPISCS1 data out set" "0,1"
|
|
newline
|
|
bitfld.long 0x10 0. " SCSSET0 ,SPISCS0 data out set" "0,1"
|
|
line.long 0x14 "SPIPC5,SPI Pin Control Register 5"
|
|
bitfld.long 0x14 31. " SOMICLR7 ,SPISOMI[7] data out clear" "0,1"
|
|
bitfld.long 0x14 30. " SOMICLR6 ,SPISOMI[6] data out clear" "0,1"
|
|
bitfld.long 0x14 29. " SOMICLR5 ,SPISOMI[5] data out clear" "0,1"
|
|
newline
|
|
bitfld.long 0x14 28. " SOMICLR4 ,SPISOMI[4] data out clear" "0,1"
|
|
bitfld.long 0x14 27. " SOMICLR3 ,SPISOMI[3] data out clear" "0,1"
|
|
bitfld.long 0x14 26. " SOMICLR2 ,SPISOMI[2] data out clear" "0,1"
|
|
newline
|
|
bitfld.long 0x14 25. " SOMICLR1 ,SPISOMI[1] data out clear" "0,1"
|
|
bitfld.long 0x14 24. " SOMICLR0 ,SPISOMI[0] data out clear (mirror of bit 11)" "0,1"
|
|
bitfld.long 0x14 23. " SIMOCLR7 ,SPISIMO[7] data out clear" "0,1"
|
|
newline
|
|
bitfld.long 0x14 22. " SIMOCLR6 ,SPISIMO[6] data out clear" "0,1"
|
|
bitfld.long 0x14 21. " SIMOCLR5 ,SPISIMO[5] data out clear" "0,1"
|
|
bitfld.long 0x14 20. " SIMOCLR4 ,SPISIMO[4] data out clear" "0,1"
|
|
newline
|
|
bitfld.long 0x14 19. " SIMOCLR3 ,SPISIMO[3] data out clear" "0,1"
|
|
bitfld.long 0x14 18. " SIMOCLR2 ,SPISIMO[2] data out clear" "0,1"
|
|
bitfld.long 0x14 17. " SIMOCLR1 ,SPISIMO[1] data out clear" "0,1"
|
|
newline
|
|
bitfld.long 0x14 16. " SIMOCLR0 ,SPISIMO[0] data out clear (mirror of bit 10)" "0,1"
|
|
bitfld.long 0x14 11. " SOMICLR0 ,SPISOMI[0] data out clear" "0,1"
|
|
bitfld.long 0x14 10. " SIMOCLR0 ,SPISIMO[0] data out clear" "0,1"
|
|
newline
|
|
bitfld.long 0x14 9. " CLKCLR ,SPI clock data out clear" "0,1"
|
|
bitfld.long 0x14 8. " ENACLR ,SPIENA data out clear" "0,1"
|
|
bitfld.long 0x14 7. " SCSCLR7 ,SPISCS7 data out clear" "0,1"
|
|
newline
|
|
bitfld.long 0x14 6. " SCSCLR6 ,SPISCS6 data out clear" "0,1"
|
|
bitfld.long 0x14 5. " SCSCLR5 ,SPISCS5 data out clear" "0,1"
|
|
bitfld.long 0x14 4. " SCSCLR4 ,SPISCS4 data out clear" "0,1"
|
|
newline
|
|
bitfld.long 0x14 3. " SCSCLR3 ,SPISCS3 data out clear" "0,1"
|
|
bitfld.long 0x14 2. " SCSCLR2 ,SPISCS2 data out clear" "0,1"
|
|
bitfld.long 0x14 1. " SCSCLR1 ,SPISCS1 data out clear" "0,1"
|
|
newline
|
|
bitfld.long 0x14 0. " SCSCLR0 ,SPISCS0 data out clear" "0,1"
|
|
line.long 0x18 "SPIPC6,SPI Pin Control Register 6"
|
|
bitfld.long 0x18 31. " SOMIPDR7 ,SPISOMI[7] open drain enable" "Disabled,Enabled"
|
|
bitfld.long 0x18 30. " SOMIPDR6 ,SPISOMI[6] open drain enable" "Disabled,Enabled"
|
|
bitfld.long 0x18 29. " SOMIPDR5 ,SPISOMI[5] open drain enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x18 28. " SOMIPDR4 ,SPISOMI[4] open drain enable" "Disabled,Enabled"
|
|
bitfld.long 0x18 27. " SOMIPDR3 ,SPISOMI[3] open drain enable" "Disabled,Enabled"
|
|
bitfld.long 0x18 26. " SOMIPDR2 ,SPISOMI[2] open drain enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x18 25. " SOMIPDR1 ,SPISOMI[1] open drain enable" "Disabled,Enabled"
|
|
bitfld.long 0x18 24. " SOMIPDR0 ,SPISOMI[0] open drain enable (mirror of bit 11)" "Disabled,Enabled"
|
|
bitfld.long 0x18 23. " SIMOPDR7 ,SPISIMO[7] open drain enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x18 22. " SIMOPDR6 ,SPISIMO[6] open drain enable" "Disabled,Enabled"
|
|
bitfld.long 0x18 21. " SIMOPDR5 ,SPISIMO[5] open drain enable" "Disabled,Enabled"
|
|
bitfld.long 0x18 20. " SIMOPDR4 ,SPISIMO[4] open drain enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x18 19. " SIMOPDR3 ,SPISIMO[3] open drain enable" "Disabled,Enabled"
|
|
bitfld.long 0x18 18. " SIMOPDR2 ,SPISIMO[2] open drain enable" "Disabled,Enabled"
|
|
bitfld.long 0x18 17. " SIMOPDR1 ,SPISIMO[1] open drain enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x18 16. " SIMOPDR0 ,SPISIMO[0] open drain enable (mirror of bit 10)" "Disabled,Enabled"
|
|
bitfld.long 0x18 11. " SOMIPDR0 ,SPISOMI[0] open drain enable" "Disabled,Enabled"
|
|
bitfld.long 0x18 10. " SIMOPDR0 ,SPISIMO[0] open drain enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x18 9. " CLKPDR ,SPI clock open drain enable" "Disabled,Enabled"
|
|
bitfld.long 0x18 8. " ENAPDR ,SPIENA open drain enable" "Disabled,Enabled"
|
|
bitfld.long 0x18 7. " SCSPDR7 ,SPISCS7 open drain enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x18 6. " SCSPDR6 ,SPISCS6 open drain enable" "Disabled,Enabled"
|
|
bitfld.long 0x18 5. " SCSPDR5 ,SPISCS5 open drain enable" "Disabled,Enabled"
|
|
bitfld.long 0x18 4. " SCSPDR4 ,SPISCS4 open drain enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x18 3. " SCSPDR3 ,SPISCS3 open drain enable" "Disabled,Enabled"
|
|
bitfld.long 0x18 2. " SCSPDR2 ,SPISCS2 open drain enable" "Disabled,Enabled"
|
|
bitfld.long 0x18 1. " SCSPDR1 ,SPISCS1 open drain enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x18 0. " SCSPDR0 ,SPISCS0 open drain enable" "Disabled,Enabled"
|
|
line.long 0x1C "SPIPC7,SPI Pin Control Register 7"
|
|
bitfld.long 0x1C 31. " SOMIPDIS7 ,SPISOMI[7] pull control enable/disable" "No,Yes"
|
|
bitfld.long 0x1C 30. " SOMIPDIS6 ,SPISOMI[6] pull control enable/disable" "No,Yes"
|
|
bitfld.long 0x1C 29. " SOMIPDIS5 ,SPISOMI[5] pull control enable/disable" "No,Yes"
|
|
newline
|
|
bitfld.long 0x1C 28. " SOMIPDIS4 ,SPISOMI[4] pull control enable/disable" "No,Yes"
|
|
bitfld.long 0x1C 27. " SOMIPDIS3 ,SPISOMI[3] pull control enable/disable" "No,Yes"
|
|
bitfld.long 0x1C 26. " SOMIPDIS2 ,SPISOMI[2] pull control enable/disable" "No,Yes"
|
|
newline
|
|
bitfld.long 0x1C 25. " SOMIPDIS1 ,SPISOMI[1] pull control enable/disable" "No,Yes"
|
|
bitfld.long 0x1C 24. " SOMIPDIS0 ,SPISOMI[0] pull control enable/disable (mirror of bit 11)" "No,Yes"
|
|
bitfld.long 0x1C 23. " SIMOPDIS7 ,SPISIMO[7] pull control enable/disable" "No,Yes"
|
|
newline
|
|
bitfld.long 0x1C 22. " SIMOPDIS6 ,SPISIMO[6] pull control enable/disable" "No,Yes"
|
|
bitfld.long 0x1C 21. " SIMOPDIS5 ,SPISIMO[5] pull control enable/disable" "No,Yes"
|
|
bitfld.long 0x1C 20. " SIMOPDIS4 ,SPISIMO[4] pull control enable/disable" "No,Yes"
|
|
newline
|
|
bitfld.long 0x1C 19. " SIMOPDIS3 ,SPISIMO[3] pull control enable/disable" "No,Yes"
|
|
bitfld.long 0x1C 18. " SIMOPDIS2 ,SPISIMO[2] pull control enable/disable" "No,Yes"
|
|
bitfld.long 0x1C 17. " SIMOPDIS1 ,SPISIMO[1] pull control enable/disable" "No,Yes"
|
|
newline
|
|
bitfld.long 0x1C 16. " SIMOPDIS0 ,SPISIMO[0] pull control enable/disable (mirror of bit 10)" "No,Yes"
|
|
bitfld.long 0x1C 11. " SOMIPDIS0 ,SPISOMI[0] pull control enable/disable" "No,Yes"
|
|
bitfld.long 0x1C 10. " SIMOPDIS0 ,SPISIMO[0] pull control enable/disable" "No,Yes"
|
|
newline
|
|
bitfld.long 0x1C 9. " CLKPDIS ,SPI clock pull control enable/disable" "No,Yes"
|
|
bitfld.long 0x1C 8. " ENAPDIS ,SPIENA pull control enable/disable" "No,Yes"
|
|
bitfld.long 0x1C 7. " SCSPDIS7 ,SPISCS7 pull control enable/disable" "No,Yes"
|
|
newline
|
|
bitfld.long 0x1C 6. " SCSPDIS6 ,SPISCS6 pull control enable/disable" "No,Yes"
|
|
bitfld.long 0x1C 5. " SCSPDIS5 ,SPISCS5 pull control enable/disable" "No,Yes"
|
|
bitfld.long 0x1C 4. " SCSPDIS4 ,SPISCS4 pull control enable/disable" "No,Yes"
|
|
newline
|
|
bitfld.long 0x1C 3. " SCSPDIS3 ,SPISCS3 pull control enable/disable" "No,Yes"
|
|
bitfld.long 0x1C 2. " SCSPDIS2 ,SPISCS2 pull control enable/disable" "No,Yes"
|
|
bitfld.long 0x1C 1. " SCSPDIS1 ,SPISCS1 pull control enable/disable" "No,Yes"
|
|
newline
|
|
bitfld.long 0x1C 0. " SCSPDIS0 ,SPISCS0 pull control enable/disable" "No,Yes"
|
|
line.long 0x20 "SPIPC8,SPI Pin Control Register 8"
|
|
bitfld.long 0x20 31. " SOMIPSEL7 ,SPISOMI[7] pull select" "Pull down,Pull up"
|
|
bitfld.long 0x20 30. " SOMIPSEL6 ,SPISOMI[6] pull select" "Pull down,Pull up"
|
|
bitfld.long 0x20 29. " SOMIPSEL5 ,SPISOMI[5] pull select" "Pull down,Pull up"
|
|
newline
|
|
bitfld.long 0x20 28. " SOMIPSEL4 ,SPISOMI[4] pull select" "Pull down,Pull up"
|
|
bitfld.long 0x20 27. " SOMIPSEL3 ,SPISOMI[3] pull select" "Pull down,Pull up"
|
|
bitfld.long 0x20 26. " SOMIPSEL2 ,SPISOMI[2] pull select" "Pull down,Pull up"
|
|
newline
|
|
bitfld.long 0x20 25. " SOMIPSEL1 ,SPISOMI[1] pull select" "Pull down,Pull up"
|
|
bitfld.long 0x20 24. " SOMIPSEL0 ,SPISOMI[0] pull select (mirror of bit 11)" "Pull down,Pull up"
|
|
bitfld.long 0x20 23. " SIMOPSEL7 ,SPISIMO[7] pull select" "Pull down,Pull up"
|
|
newline
|
|
bitfld.long 0x20 22. " SIMOPSEL6 ,SPISIMO[6] pull select" "Pull down,Pull up"
|
|
bitfld.long 0x20 21. " SIMOPSEL5 ,SPISIMO[5] pull select" "Pull down,Pull up"
|
|
bitfld.long 0x20 20. " SIMOPSEL4 ,SPISIMO[4] pull select" "Pull down,Pull up"
|
|
newline
|
|
bitfld.long 0x20 19. " SIMOPSEL3 ,SPISIMO[3] pull select" "Pull down,Pull up"
|
|
bitfld.long 0x20 18. " SIMOPSEL2 ,SPISIMO[2] pull select" "Pull down,Pull up"
|
|
bitfld.long 0x20 17. " SIMOPSEL1 ,SPISIMO[1] pull select" "Pull down,Pull up"
|
|
newline
|
|
bitfld.long 0x20 16. " SIMOPSEL0 ,SPISIMO[0] pull select (mirror of bit 10)" "Pull down,Pull up"
|
|
bitfld.long 0x20 11. " SOMIPSEL0 ,SPISOMI[0] pull select" "Pull down,Pull up"
|
|
bitfld.long 0x20 10. " SIMOPSEL0 ,SPISIMO[0] pull select" "Pull down,Pull up"
|
|
newline
|
|
bitfld.long 0x20 9. " CLKPSEL ,SPI clock pull select" "Pull down,Pull up"
|
|
bitfld.long 0x20 8. " ENAPSEL ,SPIENA pull select" "Pull down,Pull up"
|
|
bitfld.long 0x20 7. " SCSPSEL7 ,SPISCS7 pull select" "Pull down,Pull up"
|
|
newline
|
|
bitfld.long 0x20 6. " SCSPSEL6 ,SPISCS6 pull select" "Pull down,Pull up"
|
|
bitfld.long 0x20 5. " SCSPSEL5 ,SPISCS5 pull select" "Pull down,Pull up"
|
|
bitfld.long 0x20 4. " SCSPSEL4 ,SPISCS4 pull select" "Pull down,Pull up"
|
|
newline
|
|
bitfld.long 0x20 3. " SCSPSEL3 ,SPISCS3 pull select" "Pull down,Pull up"
|
|
bitfld.long 0x20 2. " SCSPSEL2 ,SPISCS2 pull select" "Pull down,Pull up"
|
|
bitfld.long 0x20 1. " SCSPSEL1 ,SPISCS1 pull select" "Pull down,Pull up"
|
|
newline
|
|
bitfld.long 0x20 0. " SCSPSEL0 ,SPISCS0 pull select" "Pull down,Pull up"
|
|
group.long 0x38++0x07
|
|
line.long 0x00 "SPIDAT0,SPI Transmit Data Register 0"
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,SPI transmit data"
|
|
line.long 0x04 "SPIDAT1,Transmit Data Register 1"
|
|
bitfld.long 0x04 28. " CSHOLD ,Chip select hold mode" "Inactive,Active"
|
|
bitfld.long 0x04 26. " WDEL ,Enable the delay counter at the end of the current transaction" "No delay,After transaction"
|
|
bitfld.long 0x04 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
newline
|
|
hexmask.long.byte 0x04 16.--23. 1. " CSNR ,Chip select number"
|
|
hexmask.long.word 0x04 0.--15. 1. " TXDATA ,Transfer data"
|
|
hgroup.long 0x40++0x03
|
|
hide.long 0x00 "SPIBUF,SPI Receive Buffer Register"
|
|
in
|
|
rgroup.long 0x44++0x03
|
|
line.long 0x00 "SPIEMU,SPI Emulation Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " EMU_RXDATA ,SPI receive data"
|
|
sif cpuis("TMS570LS0232")||cpuis("TMS570LS0714*")||cpuis("TMS570LS0914*")
|
|
group.long 0x48++0x03
|
|
line.long 0x00 "SPIDELAY,SPI Delay Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " C2TDELAY ,Chip-select-active to transmit-start delay"
|
|
hexmask.long.byte 0x00 16.--23. 1. " T2CDELAY ,Transmit-end-to-chip-select-inactive-delay"
|
|
hexmask.long.byte 0x00 8.--15. 1. " T2EDELAY ,Transmit-data-finished to ENA-pin-inactive time-out"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--7. 1. " C2EDELAY ,Chip-select-active to ENA-signal-active time-out"
|
|
else
|
|
rgroup.long 0x48++0x03
|
|
line.long 0x00 "SPIDELAY,SPI Delay Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " C2TDELAY ,Chip-select-active to transmit-start delay"
|
|
hexmask.long.byte 0x00 16.--23. 1. " T2CDELAY ,Transmit-end-to-chip-select-inactive-delay"
|
|
hexmask.long.byte 0x00 8.--15. 1. " T2EDELAY ,Transmit-data-finished to ENA-pin-inactive time-out"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--7. 1. " C2EDELAY ,Chip-select-active to ENA-signal-active time-out"
|
|
endif
|
|
group.long 0x4C++0x13
|
|
line.long 0x00 "SPIDEF,SPI Default Chip Select Register"
|
|
bitfld.long 0x00 7. " CSDEF7 ,Chip select default pattern 7" "0,1"
|
|
bitfld.long 0x00 6. " CSDEF6 ,Chip select default pattern 6" "0,1"
|
|
bitfld.long 0x00 5. " CSDEF5 ,Chip select default pattern 5" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. " CSDEF4 ,Chip select default pattern 4" "0,1"
|
|
bitfld.long 0x00 3. " CSDEF3 ,Chip select default pattern 3" "0,1"
|
|
bitfld.long 0x00 2. " CSDEF2 ,Chip select default pattern 2" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. " CSDEF1 ,Chip select default pattern 1" "0,1"
|
|
bitfld.long 0x00 0. " CSDEF0 ,Chip select default pattern 0" "0,1"
|
|
line.long 0x4 "SPIFMT0,SPI Data Format Register 0"
|
|
sif (cpuis("TMS570LS0332")||cpuis("TMS570LS0432")||cpuis("TMS570LS1114*")||cpuis("TMS570LS1115*")||cpuis("TMS570LS1224*")||cpuis("TMS570LS1225*")||cpuis("TMS570LS1227*")||cpuis("TMS570LS0232")||cpuis("TMS570LS0714*")||cpuis("TMS570LS0914*"))
|
|
hexmask.long.byte 0x4 24.--31. 1. " WDELAY ,Delay in between transmissions for data format 0"
|
|
else
|
|
bitfld.long 0x4 24.--29. " WDELAY ,Delay in between transmissions for data format 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
endif
|
|
bitfld.long 0x4 23. " PARPOL ,Parity polarity: even or odd" "Even,Odd"
|
|
newline
|
|
bitfld.long 0x4 22. " PARITYENA ,Parity enable for data format 0" "Disabled,Enabled"
|
|
bitfld.long 0x4 21. " WAITENA ,The master waits for the ENA signal from slave for data format 0" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x4 20. " SHIFTDIR ,Shift direction for data format $" "MSB,LSB"
|
|
sif (cpu()==("TMS570LS0332")||cpu()==("TMS570LS0432")||cpuis("TMS570LS1114*")||cpuis("TMS570LS1115*")||cpuis("TMS570LS1224*")||cpuis("TMS570LS1225*")||cpuis("TMS570LS1227*")||cpuis("TMS570LS0232")||cpuis("TMS570LS0714*")||cpuis("TMS570LS0914*"))
|
|
bitfld.long 0x4 19. " HDUPLEX_ENA0 ,Half Duplex transfer mode enable for Data Format 0" "Normal,RX/TX"
|
|
endif
|
|
newline
|
|
bitfld.long 0x4 18. " DISCSTIMERS ,Disable chip-select timers for this format" "No,Yes"
|
|
newline
|
|
bitfld.long 0x4 17. " POLARITY ,SPI data format 0 clock polarity" "Low,High"
|
|
bitfld.long 0x4 16. " PHASE ,SPI data format 0 clock delay" "Disabled,Enabled"
|
|
newline
|
|
hexmask.long.byte 0x4 8.--15. 1. " PRESCALE ,SPI data format 0 prescaler"
|
|
bitfld.long 0x4 0.--4. " CHARLEN ,SPI data format 0 data-word length" ",,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,?..."
|
|
line.long 0x8 "SPIFMT1,SPI Data Format Register 1"
|
|
sif (cpuis("TMS570LS0332")||cpuis("TMS570LS0432")||cpuis("TMS570LS1114*")||cpuis("TMS570LS1115*")||cpuis("TMS570LS1224*")||cpuis("TMS570LS1225*")||cpuis("TMS570LS1227*")||cpuis("TMS570LS0232")||cpuis("TMS570LS0714*")||cpuis("TMS570LS0914*"))
|
|
hexmask.long.byte 0x8 24.--31. 1. " WDELAY ,Delay in between transmissions for data format 1"
|
|
else
|
|
bitfld.long 0x8 24.--29. " WDELAY ,Delay in between transmissions for data format 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
endif
|
|
bitfld.long 0x8 23. " PARPOL ,Parity polarity: even or odd" "Even,Odd"
|
|
newline
|
|
bitfld.long 0x8 22. " PARITYENA ,Parity enable for data format 1" "Disabled,Enabled"
|
|
bitfld.long 0x8 21. " WAITENA ,The master waits for the ENA signal from slave for data format 1" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x8 20. " SHIFTDIR ,Shift direction for data format $" "MSB,LSB"
|
|
sif (cpu()==("TMS570LS0332")||cpu()==("TMS570LS0432")||cpuis("TMS570LS1114*")||cpuis("TMS570LS1115*")||cpuis("TMS570LS1224*")||cpuis("TMS570LS1225*")||cpuis("TMS570LS1227*")||cpuis("TMS570LS0232")||cpuis("TMS570LS0714*")||cpuis("TMS570LS0914*"))
|
|
bitfld.long 0x8 19. " HDUPLEX_ENA1 ,Half Duplex transfer mode enable for Data Format 1" "Normal,RX/TX"
|
|
endif
|
|
newline
|
|
bitfld.long 0x8 18. " DISCSTIMERS ,Disable chip-select timers for this format" "No,Yes"
|
|
newline
|
|
bitfld.long 0x8 17. " POLARITY ,SPI data format 1 clock polarity" "Low,High"
|
|
bitfld.long 0x8 16. " PHASE ,SPI data format 1 clock delay" "Disabled,Enabled"
|
|
newline
|
|
hexmask.long.byte 0x8 8.--15. 1. " PRESCALE ,SPI data format 1 prescaler"
|
|
bitfld.long 0x8 0.--4. " CHARLEN ,SPI data format 1 data-word length" ",,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,?..."
|
|
line.long 0xC "SPIFMT2,SPI Data Format Register 2"
|
|
sif (cpuis("TMS570LS0332")||cpuis("TMS570LS0432")||cpuis("TMS570LS1114*")||cpuis("TMS570LS1115*")||cpuis("TMS570LS1224*")||cpuis("TMS570LS1225*")||cpuis("TMS570LS1227*")||cpuis("TMS570LS0232")||cpuis("TMS570LS0714*")||cpuis("TMS570LS0914*"))
|
|
hexmask.long.byte 0xC 24.--31. 1. " WDELAY ,Delay in between transmissions for data format 2"
|
|
else
|
|
bitfld.long 0xC 24.--29. " WDELAY ,Delay in between transmissions for data format 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
endif
|
|
bitfld.long 0xC 23. " PARPOL ,Parity polarity: even or odd" "Even,Odd"
|
|
newline
|
|
bitfld.long 0xC 22. " PARITYENA ,Parity enable for data format 2" "Disabled,Enabled"
|
|
bitfld.long 0xC 21. " WAITENA ,The master waits for the ENA signal from slave for data format 2" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0xC 20. " SHIFTDIR ,Shift direction for data format $" "MSB,LSB"
|
|
sif (cpu()==("TMS570LS0332")||cpu()==("TMS570LS0432")||cpuis("TMS570LS1114*")||cpuis("TMS570LS1115*")||cpuis("TMS570LS1224*")||cpuis("TMS570LS1225*")||cpuis("TMS570LS1227*")||cpuis("TMS570LS0232")||cpuis("TMS570LS0714*")||cpuis("TMS570LS0914*"))
|
|
bitfld.long 0xC 19. " HDUPLEX_ENA2 ,Half Duplex transfer mode enable for Data Format 2" "Normal,RX/TX"
|
|
endif
|
|
newline
|
|
bitfld.long 0xC 18. " DISCSTIMERS ,Disable chip-select timers for this format" "No,Yes"
|
|
newline
|
|
bitfld.long 0xC 17. " POLARITY ,SPI data format 2 clock polarity" "Low,High"
|
|
bitfld.long 0xC 16. " PHASE ,SPI data format 2 clock delay" "Disabled,Enabled"
|
|
newline
|
|
hexmask.long.byte 0xC 8.--15. 1. " PRESCALE ,SPI data format 2 prescaler"
|
|
bitfld.long 0xC 0.--4. " CHARLEN ,SPI data format 2 data-word length" ",,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,?..."
|
|
line.long 0x10 "SPIFMT3,SPI Data Format Register 3"
|
|
sif (cpuis("TMS570LS0332")||cpuis("TMS570LS0432")||cpuis("TMS570LS1114*")||cpuis("TMS570LS1115*")||cpuis("TMS570LS1224*")||cpuis("TMS570LS1225*")||cpuis("TMS570LS1227*")||cpuis("TMS570LS0232")||cpuis("TMS570LS0714*")||cpuis("TMS570LS0914*"))
|
|
hexmask.long.byte 0x10 24.--31. 1. " WDELAY ,Delay in between transmissions for data format 3"
|
|
else
|
|
bitfld.long 0x10 24.--29. " WDELAY ,Delay in between transmissions for data format 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
endif
|
|
bitfld.long 0x10 23. " PARPOL ,Parity polarity: even or odd" "Even,Odd"
|
|
newline
|
|
bitfld.long 0x10 22. " PARITYENA ,Parity enable for data format 3" "Disabled,Enabled"
|
|
bitfld.long 0x10 21. " WAITENA ,The master waits for the ENA signal from slave for data format 3" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x10 20. " SHIFTDIR ,Shift direction for data format $" "MSB,LSB"
|
|
sif (cpu()==("TMS570LS0332")||cpu()==("TMS570LS0432")||cpuis("TMS570LS1114*")||cpuis("TMS570LS1115*")||cpuis("TMS570LS1224*")||cpuis("TMS570LS1225*")||cpuis("TMS570LS1227*")||cpuis("TMS570LS0232")||cpuis("TMS570LS0714*")||cpuis("TMS570LS0914*"))
|
|
bitfld.long 0x10 19. " HDUPLEX_ENA3 ,Half Duplex transfer mode enable for Data Format 3" "Normal,RX/TX"
|
|
endif
|
|
newline
|
|
bitfld.long 0x10 18. " DISCSTIMERS ,Disable chip-select timers for this format" "No,Yes"
|
|
newline
|
|
bitfld.long 0x10 17. " POLARITY ,SPI data format 3 clock polarity" "Low,High"
|
|
bitfld.long 0x10 16. " PHASE ,SPI data format 3 clock delay" "Disabled,Enabled"
|
|
newline
|
|
hexmask.long.byte 0x10 8.--15. 1. " PRESCALE ,SPI data format 3 prescaler"
|
|
bitfld.long 0x10 0.--4. " CHARLEN ,SPI data format 3 data-word length" ",,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,?..."
|
|
hgroup.long 0x60++0x03
|
|
hide.long 0x00 "TGINTVECT0,SPI Interrupt Vector Register 0 / MibSPI Transfer Group Interrupt Vector Register 0"
|
|
in
|
|
hgroup.long 0x64++0x03
|
|
hide.long 0x00 "TGINTVECT1,SPI Interrupt Vector Register 1 / MibSPI Transfer Group Interrupt Vector Register 1"
|
|
in
|
|
group.long 0x68++0x03
|
|
line.long 0x00 "SPIPC9,SPI Pin Control Register 9"
|
|
bitfld.long 0x00 24. " SOMISRS0 ,SPI2 SOMI[0] slew control" "Fast mode,Slow mode"
|
|
bitfld.long 0x00 16. " SIMOSRS0 ,SPI2 SIMO[0] slew control" "Fast mode,Slow mode"
|
|
bitfld.long 0x00 11. " SOMISRS0 ,SPI2 SOMI[0] slew control" "Fast mode,Slow mode"
|
|
newline
|
|
bitfld.long 0x00 10. " SIMOSRS0 ,SPI2 SIMO[0] slew control" "Fast mode,Slow mode"
|
|
bitfld.long 0x00 9. " CLKSRS ,SPI2 Clock slew control" "Fast mode,Slow mode"
|
|
sif (cpu()!=("TMS570LS0332")&&cpu()!=("TMS570LS0432")&&!cpuis("TMS570LS0232"))
|
|
group.long 0x6C++0x07
|
|
line.long 0x00 "SPIPMCTRL,SPI Parallel/Modulo Mode Control Register"
|
|
bitfld.long 0x00 29. " MODCLKPOL3 ,Modulo mode SPICLK polarity" "Normal,Inverted"
|
|
bitfld.long 0x00 26.--28. " MMODE3 ,SPI/MibSPI data lines " "1,2,3,4,5,6,?..."
|
|
bitfld.long 0x00 24.--25. " PMODE3 ,Parallel mode data lines" "1,2,4,8"
|
|
newline
|
|
bitfld.long 0x00 21. " MODCLKPOL2 ,Modulo mode SPICLK polarity" "Normal,Inverted"
|
|
bitfld.long 0x00 18.--20. " MMODE2 ,SPI/MibSPI data lines " "1,2,3,4,5,6,?..."
|
|
bitfld.long 0x00 16.--17. " PMODE2 ,Parallel mode data lines" "1,2,4,8"
|
|
newline
|
|
bitfld.long 0x00 13. " MODCLKPOL1 ,Modulo mode SPICLK polarity" "Normal,Inverted"
|
|
bitfld.long 0x00 10.--12. " MMODE1 ,SPI/MibSPI data lines " "1,2,3,4,5,6,?..."
|
|
bitfld.long 0x00 8.--9. " PMODE1 ,Parallel mode data lines" "1,2,4,8"
|
|
newline
|
|
bitfld.long 0x00 5. " MODCLKPOL0 ,Modulo mode SPICLK polarity" "Normal,Inverted"
|
|
bitfld.long 0x00 2.--4. " MMODE0 ,SPI/MibSPI data lines " "1,2,3,4,5,6,?..."
|
|
bitfld.long 0x00 0.--1. " PMODE0 ,Parallel mode data lines" "1,2,4,8"
|
|
line.long 0x04 "MIBSPIE,MibSPI Enable Register"
|
|
bitfld.long 0x04 16. " RXRAMACCESS ,Receive-RAM access control" "Not writable,Accessible"
|
|
bitfld.long 0x04 0. " MIBSPIENA ,Multi-buffer mode enable" "Disabled,Enabled"
|
|
elif cpuis("TMS570LS0332")||cpuis("TMS570LS0432")||cpuis("TMS570LS0714*")||cpuis("TMS570LS0914*")||cpuis("TMS570LS0232")
|
|
group.long 0x70++0x03
|
|
line.long 0x00 "MIBSPIE,MibSPI Enable Register"
|
|
bitfld.long 0x00 16. " RXRAMACCESS ,Receive-RAM access control" "Not writable,Accessible"
|
|
bitfld.long 0x00 0. " MIBSPIENA ,Multi-buffer mode enable" "Disabled,Enabled"
|
|
endif
|
|
group.long 0x74++0x0F
|
|
line.long 0x00 "TGITENST,MibSPI Transfer Group Interrupt Enable Set Register"
|
|
bitfld.long 0x00 31. " SETINTENRDY15 ,TG interrupt set (enable) when transfer finished" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " SETINTENRDY14 ,TG interrupt set (enable) when transfer finished" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " SETINTENRDY13 ,TG interrupt set (enable) when transfer finished" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 28. " SETINTENRDY12 ,TG interrupt set (enable) when transfer finished" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " SETINTENRDY11 ,TG interrupt set (enable) when transfer finished" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " SETINTENRDY10 ,TG interrupt set (enable) when transfer finished" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 25. " SETINTENRDY9 ,TG interrupt set (enable) when transfer finished" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " SETINTENRDY8 ,TG interrupt set (enable) when transfer finished" "Disabled,Enabled"
|
|
bitfld.long 0x00 23. " SETINTENRDY7 ,TG interrupt set (enable) when transfer finished" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 22. " SETINTENRDY6 ,TG interrupt set (enable) when transfer finished" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " SETINTENRDY5 ,TG interrupt set (enable) when transfer finished" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " SETINTENRDY4 ,SETTG interrupt set (enable) when transfer finished" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 19. " SETINTENRDY3 ,TG interrupt set (enable) when transfer finished" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SETINTENRDY2 ,TG interrupt set (enable) when transfer finished" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SETINTENRDY1 ,TG interrupt set (enable) when transfer finished" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 16. " SETINTENRDY0 ,TG interrupt set (enable) when transfer finished" "Disabled,Enabled"
|
|
bitfld.long 0x00 15. " SETINTENSUS15 ,TG interrupt set (enabled) when transfer suspended" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " SETINTENSUS14 ,TG interrupt set (enabled) when transfer suspended" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 13. " SETINTENSUS13 ,TG interrupt set (enabled) when transfer suspended" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " SETINTENSUS12 ,TG interrupt set (enabled) when transfer suspended" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " SETINTENSUS11 ,TG interrupt set (enabled) when transfer suspended" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 10. " SETINTENSUS10 ,TG interrupt set (enabled) when transfer suspended" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " SETINTENSUS9 ,TG interrupt set (enabled) when transfer suspended" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " SETINTENSUS8 ,TG interrupt set (enabled) when transfer suspended" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 7. " SETINTENSUS7 ,TG interrupt set (enabled) when transfer suspended" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " SETINTENSUS6 ,TG interrupt set (enabled) when transfer suspended" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " SETINTENSUS5 ,TG interrupt set (enabled) when transfer suspended" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 4. " SETINTENSUS4 ,TG interrupt set (enabled) when transfer suspended" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " SETINTENSUS3 ,TG interrupt set (enabled) when transfer suspended" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " SETINTENSUS2 ,TG interrupt set (enabled) when transfer suspended" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 1. " SETINTENSUS1 ,TG interrupt set (enabled) when transfer suspended" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SETINTENSUS0 ,TG interrupt set (enabled) when transfer suspended" "Disabled,Enabled"
|
|
line.long 0x04 "TGITENCR,MibSPI Transfer Group Interrupt Enable Clear Register"
|
|
bitfld.long 0x04 31. " CLRINTENRDY15 ,TG interrupt clear (disabled) when transfer finished" "Disabled,Enabled"
|
|
bitfld.long 0x04 30. " CLRINTENRDY14 ,TG interrupt clear (disabled) when transfer finished" "Disabled,Enabled"
|
|
bitfld.long 0x04 29. " CLRINTENRDY13 ,TG interrupt clear (disabled) when transfer finished" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x04 28. " CLRINTENRDY12 ,TG interrupt clear (disabled) when transfer finished" "Disabled,Enabled"
|
|
bitfld.long 0x04 27. " CLRINTENRDY11 ,TG interrupt clear (disabled) when transfer finished" "Disabled,Enabled"
|
|
bitfld.long 0x04 26. " CLRINTENRDY10 ,TG interrupt clear (disabled) when transfer finished" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x04 25. " CLRINTENRDY9 ,TG interrupt clear (disabled) when transfer finished" "Disabled,Enabled"
|
|
bitfld.long 0x04 24. " CLRINTENRDY8 ,TG interrupt clear (disabled) when transfer finished" "Disabled,Enabled"
|
|
bitfld.long 0x04 23. " CLRINTENRDY7 ,TG interrupt clear (disabled) when transfer finished" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x04 22. " CLRINTENRDY6 ,TG interrupt clear (disabled) when transfer finished" "Disabled,Enabled"
|
|
bitfld.long 0x04 21. " CLRINTENRDY5 ,TG interrupt clear (disabled) when transfer finished" "Disabled,Enabled"
|
|
bitfld.long 0x04 20. " CLRINTENRDY4 ,TG interrupt clear (disabled) when transfer finished" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x04 19. " CLRINTENRDY3 ,TG interrupt clear (disabled) when transfer finished" "Disabled,Enabled"
|
|
bitfld.long 0x04 18. " CLRINTENRDY2 ,TG interrupt clear (disabled) when transfer finished" "Disabled,Enabled"
|
|
bitfld.long 0x04 17. " CLRINTENRDY1 ,TG interrupt clear (disabled) when transfer finished" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x04 16. " CLRINTENRDY0 ,TG interrupt clear (disabled) when transfer finished" "Disabled,Enabled"
|
|
bitfld.long 0x04 15. " CLRINTENSUS15 ,TG interrupt clear (disabled) when transfer suspended" "Disabled,Enabled"
|
|
bitfld.long 0x04 14. " CLRINTENSUS14 ,TG interrupt clear (disabled) when transfer suspended" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x04 13. " CLRINTENSUS13 ,TG interrupt clear (disabled) when transfer suspended" "Disabled,Enabled"
|
|
bitfld.long 0x04 12. " CLRINTENSUS12 ,TG interrupt clear (disabled) when transfer suspended" "Disabled,Enabled"
|
|
bitfld.long 0x04 11. " CLRINTENSUS11 ,TG interrupt clear (disabled) when transfer suspended" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x04 10. " CLRINTENSUS10 ,TG interrupt clear (disabled) when transfer suspended" "Disabled,Enabled"
|
|
bitfld.long 0x04 9. " CLRINTENSUS9 ,TG interrupt clear (disabled) when transfer suspended" "Disabled,Enabled"
|
|
bitfld.long 0x04 8. " CLRINTENSUS8 ,TG interrupt clear (disabled) when transfer suspended" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x04 7. " CLRINTENSUS7 ,TG interrupt clear (disabled) when transfer suspended" "Disabled,Enabled"
|
|
bitfld.long 0x04 6. " CLRINTENSUS6 ,TG interrupt clear (disabled) when transfer suspended" "Disabled,Enabled"
|
|
bitfld.long 0x04 5. " CLRINTENSUS5 ,TG interrupt clear (disabled) when transfer suspended" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x04 4. " CLRINTENSUS4 ,TG interrupt clear (disabled) when transfer suspended" "Disabled,Enabled"
|
|
bitfld.long 0x04 3. " CLRINTENSUS3 ,TG interrupt clear (disabled) when transfer suspended" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " CLRINTENSUS2 ,TG interrupt clear (disabled) when transfer suspended" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x04 1. " CLRINTENSUS1 ,TG interrupt clear (disabled) when transfer suspended" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " CLRINTENSUS0 ,TG interrupt clear (disabled) when transfer suspended" "Disabled,Enabled"
|
|
line.long 0x08 "TGITLVST,MibSPI Transfer Group Interrupt Level Set Register"
|
|
bitfld.long 0x08 31. " SETINTLVLRDY15 ,Transfer-group completed interrupt level set" "INT0,INT1"
|
|
bitfld.long 0x08 30. " SETINTLVLRDY14 ,Transfer-group completed interrupt level set" "INT0,INT1"
|
|
bitfld.long 0x08 29. " SETINTLVLRDY13 ,Transfer-group completed interrupt level set" "INT0,INT1"
|
|
newline
|
|
bitfld.long 0x08 28. " SETINTLVLRDY12 ,Transfer-group completed interrupt level set" "INT0,INT1"
|
|
bitfld.long 0x08 27. " SETINTLVLRDY11 ,Transfer-group completed interrupt level set" "INT0,INT1"
|
|
bitfld.long 0x08 26. " SETINTLVLRDY10 ,Transfer-group completed interrupt level set" "INT0,INT1"
|
|
newline
|
|
bitfld.long 0x08 25. " SETINTLVLRDY9 ,Transfer-group completed interrupt level set" "INT0,INT1"
|
|
bitfld.long 0x08 24. " SETINTLVLRDY8 ,Transfer-group completed interrupt level set" "INT0,INT1"
|
|
bitfld.long 0x08 23. " SETINTLVLRDY7 ,Transfer-group completed interrupt level set" "INT0,INT1"
|
|
newline
|
|
bitfld.long 0x08 22. " SETINTLVLRDY6 ,Transfer-group completed interrupt level set" "INT0,INT1"
|
|
bitfld.long 0x08 21. " SETINTLVLRDY5 ,Transfer-group completed interrupt level set" "INT0,INT1"
|
|
bitfld.long 0x08 20. " SETINTLVLRDY4 ,Transfer-group completed interrupt level set" "INT0,INT1"
|
|
newline
|
|
bitfld.long 0x08 19. " SETINTLVLRDY3 ,Transfer-group completed interrupt level set" "INT0,INT1"
|
|
bitfld.long 0x08 18. " SETINTLVLRDY2 ,Transfer-group completed interrupt level set" "INT0,INT1"
|
|
bitfld.long 0x08 17. " SETINTLVLRDY1 ,Transfer-group completed interrupt level set" "INT0,INT1"
|
|
newline
|
|
bitfld.long 0x08 16. " SETINTLVLRDY0 ,Transfer-group completed interrupt level set" "INT0,INT1"
|
|
bitfld.long 0x08 15. " SETINTLVLSUS15 ,Transfer-group suspended interrupt level set" "INT0,INT1"
|
|
bitfld.long 0x08 14. " SETINTLVLSUS14 ,Transfer-group suspended interrupt level set" "INT0,INT1"
|
|
newline
|
|
bitfld.long 0x08 13. " SETINTLVLSUS13 ,Transfer-group suspended interrupt level set" "INT0,INT1"
|
|
bitfld.long 0x08 12. " SETINTLVLSUS12 ,Transfer-group suspended interrupt level set" "INT0,INT1"
|
|
bitfld.long 0x08 11. " SETINTLVLSUS11 ,Transfer-group suspended interrupt level set" "INT0,INT1"
|
|
newline
|
|
bitfld.long 0x08 10. " SETINTLVLSUS10 ,Transfer-group suspended interrupt level set" "INT0,INT1"
|
|
bitfld.long 0x08 9. " SETINTLVLSUS9 ,Transfer-group suspended interrupt level set" "INT0,INT1"
|
|
bitfld.long 0x08 8. " SETINTLVLSUS8 ,Transfer-group suspended interrupt level set" "INT0,INT1"
|
|
newline
|
|
bitfld.long 0x08 7. " SETINTLVLSUS7 ,Transfer-group suspended interrupt level set" "INT0,INT1"
|
|
bitfld.long 0x08 6. " SETINTLVLSUS6 ,Transfer-group suspended interrupt level set" "INT0,INT1"
|
|
bitfld.long 0x08 5. " SETINTLVLSUS5 ,Transfer-group suspended interrupt level set" "INT0,INT1"
|
|
newline
|
|
bitfld.long 0x08 4. " SETINTLVLSUS4 ,Transfer-group suspended interrupt level set" "INT0,INT1"
|
|
bitfld.long 0x08 3. " SETINTLVLSUS3 ,Transfer-group suspended interrupt level set" "INT0,INT1"
|
|
bitfld.long 0x08 2. " SETINTLVLSUS2 ,Transfer-group suspended interrupt level set" "INT0,INT1"
|
|
newline
|
|
bitfld.long 0x08 1. " SETINTLVLSUS1 ,Transfer-group suspended interrupt level set" "INT0,INT1"
|
|
bitfld.long 0x08 0. " SETINTLVLSUS0 ,Transfer-group suspended interrupt level set" "INT0,INT1"
|
|
line.long 0x0C "TGITLVCR,MibSPI Transfer Group Interrupt Level Clear Register"
|
|
bitfld.long 0x0C 31. " CLRINTLVLRDY15 ,Transfer-group completed interrupt level clear" "INT0,INT1"
|
|
bitfld.long 0x0C 30. " CLRINTLVLRDY14 ,Transfer-group completed interrupt level clear" "INT0,INT1"
|
|
bitfld.long 0x0C 29. " CLRINTLVLRDY13 ,Transfer-group completed interrupt level clear" "INT0,INT1"
|
|
newline
|
|
bitfld.long 0x0C 28. " CLRINTLVLRDY12 ,Transfer-group completed interrupt level clear" "INT0,INT1"
|
|
bitfld.long 0x0C 27. " CLRINTLVLRDY11 ,Transfer-group completed interrupt level clear" "INT0,INT1"
|
|
bitfld.long 0x0C 26. " CLRINTLVLRDY10 ,Transfer-group completed interrupt level clear" "INT0,INT1"
|
|
newline
|
|
bitfld.long 0x0C 25. " CLRINTLVLRDY9 ,Transfer-group completed interrupt level clear" "INT0,INT1"
|
|
bitfld.long 0x0C 24. " CLRINTLVLRDY8 ,Transfer-group completed interrupt level clear" "INT0,INT1"
|
|
bitfld.long 0x0C 23. " CLRINTLVLRDY7 ,Transfer-group completed interrupt level clear" "INT0,INT1"
|
|
newline
|
|
bitfld.long 0x0C 22. " CLRINTLVLRDY6 ,Transfer-group completed interrupt level clear" "INT0,INT1"
|
|
bitfld.long 0x0C 21. " CLRINTLVLRDY5 ,Transfer-group completed interrupt level clear" "INT0,INT1"
|
|
bitfld.long 0x0C 20. " CLRINTLVLRDY4 ,Transfer-group completed interrupt level clear" "INT0,INT1"
|
|
newline
|
|
bitfld.long 0x0C 19. " CLRINTLVLRDY3 ,Transfer-group completed interrupt level clear" "INT0,INT1"
|
|
bitfld.long 0x0C 18. " CLRINTLVLRDY2 ,Transfer-group completed interrupt level clear" "INT0,INT1"
|
|
bitfld.long 0x0C 17. " CLRINTLVLRDY1 ,Transfer-group completed interrupt level clear" "INT0,INT1"
|
|
newline
|
|
bitfld.long 0x0C 16. " CLRINTLVLRDY0 ,Transfer-group completed interrupt level clear" "INT0,INT1"
|
|
bitfld.long 0x0C 15. " CLRINTLVLSUS15 ,Transfer group suspended interrupt level clear" "INT0,INT1"
|
|
bitfld.long 0x0C 14. " CLRINTLVLSUS14 ,Transfer group suspended interrupt level clear" "INT0,INT1"
|
|
newline
|
|
bitfld.long 0x0C 13. " CLRINTLVLSUS13 ,Transfer group suspended interrupt level clear" "INT0,INT1"
|
|
bitfld.long 0x0C 12. " CLRINTLVLSUS12 ,Transfer group suspended interrupt level clear" "INT0,INT1"
|
|
bitfld.long 0x0C 11. " CLRINTLVLSUS11 ,Transfer group suspended interrupt level clear" "INT0,INT1"
|
|
newline
|
|
bitfld.long 0x0C 10. " CLRINTLVLSUS10 ,Transfer group suspended interrupt level clear" "INT0,INT1"
|
|
bitfld.long 0x0C 9. " CLRINTLVLSUS9 ,Transfer group suspended interrupt level clear" "INT0,INT1"
|
|
bitfld.long 0x0C 8. " CLRINTLVLSUS8 ,Transfer group suspended interrupt level clear" "INT0,INT1"
|
|
newline
|
|
bitfld.long 0x0C 7. " CLRINTLVLSUS7 ,Transfer group suspended interrupt level clear" "INT0,INT1"
|
|
bitfld.long 0x0C 6. " CLRINTLVLSUS6 ,Transfer group suspended interrupt level clear" "INT0,INT1"
|
|
bitfld.long 0x0C 5. " CLRINTLVLSUS5 ,Transfer group suspended interrupt level clear" "INT0,INT1"
|
|
newline
|
|
bitfld.long 0x0C 4. " CLRINTLVLSUS4 ,Transfer group suspended interrupt level clear" "INT0,INT1"
|
|
bitfld.long 0x0C 3. " CLRINTLVLSUS3 ,Transfer group suspended interrupt level clear" "INT0,INT1"
|
|
bitfld.long 0x0C 2. " CLRINTLVLSUS2 ,Transfer group suspended interrupt level clear" "INT0,INT1"
|
|
newline
|
|
bitfld.long 0x0C 1. " CLRINTLVLSUS1 ,Transfer group suspended interrupt level clear" "INT0,INT1"
|
|
bitfld.long 0x0C 0. " CLRINTLVLSUS0 ,Transfer group suspended interrupt level clear" "INT0,INT1"
|
|
group.long 0x84++0x03
|
|
line.long 0x00 "TGITFLG,Transfer Group Interrupt Flag Register"
|
|
sif (cpu()==("TMS570LS0332")||cpu()==("TMS570LS0432")||cpuis("TMS570LS1114*")||cpuis("TMS570LS1115*")||cpuis("TMS570LS1224*")||cpuis("TMS570LS1225*")||cpuis("TMS570LS1227*")||cpuis("TMS570LS0232")||cpuis("TMS570LS0714*")||cpuis("TMS570LS0914*"))
|
|
bitfld.long 0x00 31. " INTFLGRDY[15] ,Transfer-group interrupt flag for a transfer-completed interrupt 15" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " INTFLGRDY[14] ,Transfer-group interrupt flag for a transfer-completed interrupt 14" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 29. " INTFLGRDY[13] ,Transfer-group interrupt flag for a transfer-completed interrupt 13" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " INTFLGRDY[12] ,Transfer-group interrupt flag for a transfer-completed interrupt 12" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 27. " INTFLGRDY[11] ,Transfer-group interrupt flag for a transfer-completed interrupt 11" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " INTFLGRDY[10] ,Transfer-group interrupt flag for a transfer-completed interrupt 10" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 25. " INTFLGRDY[9] ,Transfer-group interrupt flag for a transfer-completed interrupt 9" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " INTFLGRDY[8] ,Transfer-group interrupt flag for a transfer-completed interrupt 8" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 23. " INTFLGRDY[7] ,Transfer-group interrupt flag for a transfer-completed interrupt 7" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " INTFLGRDY[6] ,Transfer-group interrupt flag for a transfer-completed interrupt 6" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 21. " INTFLGRDY[5] ,Transfer-group interrupt flag for a transfer-completed interrupt 5" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " INTFLGRDY[4] ,Transfer-group interrupt flag for a transfer-completed interrupt 4" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 19. " INTFLGRDY[3] ,Transfer-group interrupt flag for a transfer-completed interrupt 3" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " INTFLGRDY[2] ,Transfer-group interrupt flag for a transfer-completed interrupt 2" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 17. " INTFLGRDY[1] ,Transfer-group interrupt flag for a transfer-completed interrupt 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " INTFLGRDY[0] ,Transfer-group interrupt flag for a transfer-completed interrupt 0" "Disabled,Enabled"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 15. " INTFLGSUS[15] ,Transfer-group interrupt flag for a transfer-suspend interrupt 15" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " INTFLGSUS[14] ,Transfer-group interrupt flag for a transfer-suspend interrupt 14" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 13. " INTFLGSUS[13] ,Transfer-group interrupt flag for a transfer-suspend interrupt 13" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " INTFLGSUS[12] ,Transfer-group interrupt flag for a transfer-suspend interrupt 12" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 11. " INTFLGSUS[11] ,Transfer-group interrupt flag for a transfer-suspend interrupt 11" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " INTFLGSUS[10] ,Transfer-group interrupt flag for a transfer-suspend interrupt 10" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 9. " INTFLGSUS[9] ,Transfer-group interrupt flag for a transfer-suspend interrupt 9" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " INTFLGSUS[8] ,Transfer-group interrupt flag for a transfer-suspend interrupt 8" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 7. " INTFLGSUS[7] ,Transfer-group interrupt flag for a transfer-suspend interrupt 7" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " INTFLGSUS[6] ,Transfer-group interrupt flag for a transfer-suspend interrupt 6" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 5. " INTFLGSUS[5] ,Transfer-group interrupt flag for a transfer-suspend interrupt 5" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " INTFLGSUS[4] ,Transfer-group interrupt flag for a transfer-suspend interrupt 4" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 3. " INTFLGSUS[3] ,Transfer-group interrupt flag for a transfer-suspend interrupt 3" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " INTFLGSUS[2] ,Transfer-group interrupt flag for a transfer-suspend interrupt 2" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 1. " INTFLGSUS[1] ,Transfer-group interrupt flag for a transfer-suspend interrupt 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " INTFLGSUS[0] ,Transfer-group interrupt flag for a transfer-suspend interrupt 0" "Disabled,Enabled"
|
|
group.long 0x90++0x47
|
|
line.long 0x00 "TICKCNT,Tick Count Register"
|
|
bitfld.long 0x00 31. " TICKENA ,Tick counter enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " RELOAD ,Pre-load the tick counter" "No effect,Reload"
|
|
bitfld.long 0x00 28.--29. " CLKCTRL ,Tick counter clock source control" "0,1,2,3"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TICKVALUE ,Initial value for the tick counter"
|
|
line.long 0x04 "LTGPEND,Last Transfer Group End Pointer Register"
|
|
bitfld.long 0x04 24.--28. " TGINSERVICE ,The TG number currently being serviced by the sequencer" "No TG,TG0,TG1,TG2,TG3,TG4,TG5,TG6,TG7,TG8,TG9,TG10,TG11,TG12,TG13,TG14,TG15,?..."
|
|
hexmask.long.byte 0x04 8.--14. 1. " LPEND ,Last TG end pointer"
|
|
line.long 0x8 "TG0CTRL,MibSPI Transfer Group Control Register 0"
|
|
bitfld.long 0x8 31. " TGENA ,TG enable" "Disabled,Enabled"
|
|
bitfld.long 0x8 30. " ONESHOT ,Single transfer for TG" "Disabled,Enabled"
|
|
bitfld.long 0x8 29. " PRST ,TG pointer reset mode" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x8 28. " TGTD ,TG triggered" "Not triggered,Triggered"
|
|
bitfld.long 0x8 20.--23. " TRGEVT ,Type of trigger event" "Never,Rising edge,Falling edge,Both edges,,High active,Low-active,Always,?..."
|
|
sif cpuis("TMS570LS0232")||cpuis("TMS570LS0714*")||cpuis("TMS570LS0914*")
|
|
bitfld.long 0x8 16.--19. " TRIGSRC ,Trigger source" "Disabled,EXT0,EXT1,EXT2,EXT3,EXT4,EXT5,EXT6,EXT7,EXT8,EXT9,EXT10,EXT11,EXT12,EXT13,TICK"
|
|
else
|
|
bitfld.long 0x8 16.--19. " TRIGSRC ,Trigger source" "Disabled,GIOA[0],GIOA[1],GIOA[2],GIOA[3],GIOA[4],GIOA[5],GIOA[6],GIOA[7],N2HET1[8],N2HET1[10],N2HET1[12],N2HET1[14],N2HET1[16],N2HET1[18],TICK"
|
|
endif
|
|
newline
|
|
hexmask.long.byte 0x8 8.--14. 0x01 " PSTART ,TG start address"
|
|
hexmask.long.byte 0x8 0.--6. 0x01 " PCURRENT ,Pointer to current buffer"
|
|
line.long 0xC "TG1CTRL,MibSPI Transfer Group Control Register 1"
|
|
bitfld.long 0xC 31. " TGENA ,TG enable" "Disabled,Enabled"
|
|
bitfld.long 0xC 30. " ONESHOT ,Single transfer for TG" "Disabled,Enabled"
|
|
bitfld.long 0xC 29. " PRST ,TG pointer reset mode" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0xC 28. " TGTD ,TG triggered" "Not triggered,Triggered"
|
|
bitfld.long 0xC 20.--23. " TRGEVT ,Type of trigger event" "Never,Rising edge,Falling edge,Both edges,,High active,Low-active,Always,?..."
|
|
sif cpuis("TMS570LS0232")||cpuis("TMS570LS0714*")||cpuis("TMS570LS0914*")
|
|
bitfld.long 0xC 16.--19. " TRIGSRC ,Trigger source" "Disabled,EXT0,EXT1,EXT2,EXT3,EXT4,EXT5,EXT6,EXT7,EXT8,EXT9,EXT10,EXT11,EXT12,EXT13,TICK"
|
|
else
|
|
bitfld.long 0xC 16.--19. " TRIGSRC ,Trigger source" "Disabled,GIOA[0],GIOA[1],GIOA[2],GIOA[3],GIOA[4],GIOA[5],GIOA[6],GIOA[7],N2HET1[8],N2HET1[10],N2HET1[12],N2HET1[14],N2HET1[16],N2HET1[18],TICK"
|
|
endif
|
|
newline
|
|
hexmask.long.byte 0xC 8.--14. 0x01 " PSTART ,TG start address"
|
|
hexmask.long.byte 0xC 0.--6. 0x01 " PCURRENT ,Pointer to current buffer"
|
|
line.long 0x10 "TG2CTRL,MibSPI Transfer Group Control Register 2"
|
|
bitfld.long 0x10 31. " TGENA ,TG enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 30. " ONESHOT ,Single transfer for TG" "Disabled,Enabled"
|
|
bitfld.long 0x10 29. " PRST ,TG pointer reset mode" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x10 28. " TGTD ,TG triggered" "Not triggered,Triggered"
|
|
bitfld.long 0x10 20.--23. " TRGEVT ,Type of trigger event" "Never,Rising edge,Falling edge,Both edges,,High active,Low-active,Always,?..."
|
|
sif cpuis("TMS570LS0232")||cpuis("TMS570LS0714*")||cpuis("TMS570LS0914*")
|
|
bitfld.long 0x10 16.--19. " TRIGSRC ,Trigger source" "Disabled,EXT0,EXT1,EXT2,EXT3,EXT4,EXT5,EXT6,EXT7,EXT8,EXT9,EXT10,EXT11,EXT12,EXT13,TICK"
|
|
else
|
|
bitfld.long 0x10 16.--19. " TRIGSRC ,Trigger source" "Disabled,GIOA[0],GIOA[1],GIOA[2],GIOA[3],GIOA[4],GIOA[5],GIOA[6],GIOA[7],N2HET1[8],N2HET1[10],N2HET1[12],N2HET1[14],N2HET1[16],N2HET1[18],TICK"
|
|
endif
|
|
newline
|
|
hexmask.long.byte 0x10 8.--14. 0x01 " PSTART ,TG start address"
|
|
hexmask.long.byte 0x10 0.--6. 0x01 " PCURRENT ,Pointer to current buffer"
|
|
line.long 0x14 "TG3CTRL,MibSPI Transfer Group Control Register 3"
|
|
bitfld.long 0x14 31. " TGENA ,TG enable" "Disabled,Enabled"
|
|
bitfld.long 0x14 30. " ONESHOT ,Single transfer for TG" "Disabled,Enabled"
|
|
bitfld.long 0x14 29. " PRST ,TG pointer reset mode" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x14 28. " TGTD ,TG triggered" "Not triggered,Triggered"
|
|
bitfld.long 0x14 20.--23. " TRGEVT ,Type of trigger event" "Never,Rising edge,Falling edge,Both edges,,High active,Low-active,Always,?..."
|
|
sif cpuis("TMS570LS0232")||cpuis("TMS570LS0714*")||cpuis("TMS570LS0914*")
|
|
bitfld.long 0x14 16.--19. " TRIGSRC ,Trigger source" "Disabled,EXT0,EXT1,EXT2,EXT3,EXT4,EXT5,EXT6,EXT7,EXT8,EXT9,EXT10,EXT11,EXT12,EXT13,TICK"
|
|
else
|
|
bitfld.long 0x14 16.--19. " TRIGSRC ,Trigger source" "Disabled,GIOA[0],GIOA[1],GIOA[2],GIOA[3],GIOA[4],GIOA[5],GIOA[6],GIOA[7],N2HET1[8],N2HET1[10],N2HET1[12],N2HET1[14],N2HET1[16],N2HET1[18],TICK"
|
|
endif
|
|
newline
|
|
hexmask.long.byte 0x14 8.--14. 0x01 " PSTART ,TG start address"
|
|
hexmask.long.byte 0x14 0.--6. 0x01 " PCURRENT ,Pointer to current buffer"
|
|
line.long 0x18 "TG4CTRL,MibSPI Transfer Group Control Register 4"
|
|
bitfld.long 0x18 31. " TGENA ,TG enable" "Disabled,Enabled"
|
|
bitfld.long 0x18 30. " ONESHOT ,Single transfer for TG" "Disabled,Enabled"
|
|
bitfld.long 0x18 29. " PRST ,TG pointer reset mode" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x18 28. " TGTD ,TG triggered" "Not triggered,Triggered"
|
|
bitfld.long 0x18 20.--23. " TRGEVT ,Type of trigger event" "Never,Rising edge,Falling edge,Both edges,,High active,Low-active,Always,?..."
|
|
sif cpuis("TMS570LS0232")||cpuis("TMS570LS0714*")||cpuis("TMS570LS0914*")
|
|
bitfld.long 0x18 16.--19. " TRIGSRC ,Trigger source" "Disabled,EXT0,EXT1,EXT2,EXT3,EXT4,EXT5,EXT6,EXT7,EXT8,EXT9,EXT10,EXT11,EXT12,EXT13,TICK"
|
|
else
|
|
bitfld.long 0x18 16.--19. " TRIGSRC ,Trigger source" "Disabled,GIOA[0],GIOA[1],GIOA[2],GIOA[3],GIOA[4],GIOA[5],GIOA[6],GIOA[7],N2HET1[8],N2HET1[10],N2HET1[12],N2HET1[14],N2HET1[16],N2HET1[18],TICK"
|
|
endif
|
|
newline
|
|
hexmask.long.byte 0x18 8.--14. 0x01 " PSTART ,TG start address"
|
|
hexmask.long.byte 0x18 0.--6. 0x01 " PCURRENT ,Pointer to current buffer"
|
|
line.long 0x1C "TG5CTRL,MibSPI Transfer Group Control Register 5"
|
|
bitfld.long 0x1C 31. " TGENA ,TG enable" "Disabled,Enabled"
|
|
bitfld.long 0x1C 30. " ONESHOT ,Single transfer for TG" "Disabled,Enabled"
|
|
bitfld.long 0x1C 29. " PRST ,TG pointer reset mode" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x1C 28. " TGTD ,TG triggered" "Not triggered,Triggered"
|
|
bitfld.long 0x1C 20.--23. " TRGEVT ,Type of trigger event" "Never,Rising edge,Falling edge,Both edges,,High active,Low-active,Always,?..."
|
|
sif cpuis("TMS570LS0232")||cpuis("TMS570LS0714*")||cpuis("TMS570LS0914*")
|
|
bitfld.long 0x1C 16.--19. " TRIGSRC ,Trigger source" "Disabled,EXT0,EXT1,EXT2,EXT3,EXT4,EXT5,EXT6,EXT7,EXT8,EXT9,EXT10,EXT11,EXT12,EXT13,TICK"
|
|
else
|
|
bitfld.long 0x1C 16.--19. " TRIGSRC ,Trigger source" "Disabled,GIOA[0],GIOA[1],GIOA[2],GIOA[3],GIOA[4],GIOA[5],GIOA[6],GIOA[7],N2HET1[8],N2HET1[10],N2HET1[12],N2HET1[14],N2HET1[16],N2HET1[18],TICK"
|
|
endif
|
|
newline
|
|
hexmask.long.byte 0x1C 8.--14. 0x01 " PSTART ,TG start address"
|
|
hexmask.long.byte 0x1C 0.--6. 0x01 " PCURRENT ,Pointer to current buffer"
|
|
line.long 0x20 "TG6CTRL,MibSPI Transfer Group Control Register 6"
|
|
bitfld.long 0x20 31. " TGENA ,TG enable" "Disabled,Enabled"
|
|
bitfld.long 0x20 30. " ONESHOT ,Single transfer for TG" "Disabled,Enabled"
|
|
bitfld.long 0x20 29. " PRST ,TG pointer reset mode" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x20 28. " TGTD ,TG triggered" "Not triggered,Triggered"
|
|
bitfld.long 0x20 20.--23. " TRGEVT ,Type of trigger event" "Never,Rising edge,Falling edge,Both edges,,High active,Low-active,Always,?..."
|
|
sif cpuis("TMS570LS0232")||cpuis("TMS570LS0714*")||cpuis("TMS570LS0914*")
|
|
bitfld.long 0x20 16.--19. " TRIGSRC ,Trigger source" "Disabled,EXT0,EXT1,EXT2,EXT3,EXT4,EXT5,EXT6,EXT7,EXT8,EXT9,EXT10,EXT11,EXT12,EXT13,TICK"
|
|
else
|
|
bitfld.long 0x20 16.--19. " TRIGSRC ,Trigger source" "Disabled,GIOA[0],GIOA[1],GIOA[2],GIOA[3],GIOA[4],GIOA[5],GIOA[6],GIOA[7],N2HET1[8],N2HET1[10],N2HET1[12],N2HET1[14],N2HET1[16],N2HET1[18],TICK"
|
|
endif
|
|
newline
|
|
hexmask.long.byte 0x20 8.--14. 0x01 " PSTART ,TG start address"
|
|
hexmask.long.byte 0x20 0.--6. 0x01 " PCURRENT ,Pointer to current buffer"
|
|
line.long 0x24 "TG7CTRL,MibSPI Transfer Group Control Register 7"
|
|
bitfld.long 0x24 31. " TGENA ,TG enable" "Disabled,Enabled"
|
|
bitfld.long 0x24 30. " ONESHOT ,Single transfer for TG" "Disabled,Enabled"
|
|
bitfld.long 0x24 29. " PRST ,TG pointer reset mode" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x24 28. " TGTD ,TG triggered" "Not triggered,Triggered"
|
|
bitfld.long 0x24 20.--23. " TRGEVT ,Type of trigger event" "Never,Rising edge,Falling edge,Both edges,,High active,Low-active,Always,?..."
|
|
sif cpuis("TMS570LS0232")||cpuis("TMS570LS0714*")||cpuis("TMS570LS0914*")
|
|
bitfld.long 0x24 16.--19. " TRIGSRC ,Trigger source" "Disabled,EXT0,EXT1,EXT2,EXT3,EXT4,EXT5,EXT6,EXT7,EXT8,EXT9,EXT10,EXT11,EXT12,EXT13,TICK"
|
|
else
|
|
bitfld.long 0x24 16.--19. " TRIGSRC ,Trigger source" "Disabled,GIOA[0],GIOA[1],GIOA[2],GIOA[3],GIOA[4],GIOA[5],GIOA[6],GIOA[7],N2HET1[8],N2HET1[10],N2HET1[12],N2HET1[14],N2HET1[16],N2HET1[18],TICK"
|
|
endif
|
|
newline
|
|
hexmask.long.byte 0x24 8.--14. 0x01 " PSTART ,TG start address"
|
|
hexmask.long.byte 0x24 0.--6. 0x01 " PCURRENT ,Pointer to current buffer"
|
|
line.long 0x28 "TG8CTRL,MibSPI Transfer Group Control Register 8"
|
|
bitfld.long 0x28 31. " TGENA ,TG enable" "Disabled,Enabled"
|
|
bitfld.long 0x28 30. " ONESHOT ,Single transfer for TG" "Disabled,Enabled"
|
|
bitfld.long 0x28 29. " PRST ,TG pointer reset mode" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x28 28. " TGTD ,TG triggered" "Not triggered,Triggered"
|
|
bitfld.long 0x28 20.--23. " TRGEVT ,Type of trigger event" "Never,Rising edge,Falling edge,Both edges,,High active,Low-active,Always,?..."
|
|
sif cpuis("TMS570LS0232")||cpuis("TMS570LS0714*")||cpuis("TMS570LS0914*")
|
|
bitfld.long 0x28 16.--19. " TRIGSRC ,Trigger source" "Disabled,EXT0,EXT1,EXT2,EXT3,EXT4,EXT5,EXT6,EXT7,EXT8,EXT9,EXT10,EXT11,EXT12,EXT13,TICK"
|
|
else
|
|
bitfld.long 0x28 16.--19. " TRIGSRC ,Trigger source" "Disabled,GIOA[0],GIOA[1],GIOA[2],GIOA[3],GIOA[4],GIOA[5],GIOA[6],GIOA[7],N2HET1[8],N2HET1[10],N2HET1[12],N2HET1[14],N2HET1[16],N2HET1[18],TICK"
|
|
endif
|
|
newline
|
|
hexmask.long.byte 0x28 8.--14. 0x01 " PSTART ,TG start address"
|
|
hexmask.long.byte 0x28 0.--6. 0x01 " PCURRENT ,Pointer to current buffer"
|
|
line.long 0x2C "TG9CTRL,MibSPI Transfer Group Control Register 9"
|
|
bitfld.long 0x2C 31. " TGENA ,TG enable" "Disabled,Enabled"
|
|
bitfld.long 0x2C 30. " ONESHOT ,Single transfer for TG" "Disabled,Enabled"
|
|
bitfld.long 0x2C 29. " PRST ,TG pointer reset mode" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x2C 28. " TGTD ,TG triggered" "Not triggered,Triggered"
|
|
bitfld.long 0x2C 20.--23. " TRGEVT ,Type of trigger event" "Never,Rising edge,Falling edge,Both edges,,High active,Low-active,Always,?..."
|
|
sif cpuis("TMS570LS0232")||cpuis("TMS570LS0714*")||cpuis("TMS570LS0914*")
|
|
bitfld.long 0x2C 16.--19. " TRIGSRC ,Trigger source" "Disabled,EXT0,EXT1,EXT2,EXT3,EXT4,EXT5,EXT6,EXT7,EXT8,EXT9,EXT10,EXT11,EXT12,EXT13,TICK"
|
|
else
|
|
bitfld.long 0x2C 16.--19. " TRIGSRC ,Trigger source" "Disabled,GIOA[0],GIOA[1],GIOA[2],GIOA[3],GIOA[4],GIOA[5],GIOA[6],GIOA[7],N2HET1[8],N2HET1[10],N2HET1[12],N2HET1[14],N2HET1[16],N2HET1[18],TICK"
|
|
endif
|
|
newline
|
|
hexmask.long.byte 0x2C 8.--14. 0x01 " PSTART ,TG start address"
|
|
hexmask.long.byte 0x2C 0.--6. 0x01 " PCURRENT ,Pointer to current buffer"
|
|
line.long 0x30 "TG10CTRL,MibSPI Transfer Group Control Register 10"
|
|
bitfld.long 0x30 31. " TGENA ,TG enable" "Disabled,Enabled"
|
|
bitfld.long 0x30 30. " ONESHOT ,Single transfer for TG" "Disabled,Enabled"
|
|
bitfld.long 0x30 29. " PRST ,TG pointer reset mode" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x30 28. " TGTD ,TG triggered" "Not triggered,Triggered"
|
|
bitfld.long 0x30 20.--23. " TRGEVT ,Type of trigger event" "Never,Rising edge,Falling edge,Both edges,,High active,Low-active,Always,?..."
|
|
sif cpuis("TMS570LS0232")||cpuis("TMS570LS0714*")||cpuis("TMS570LS0914*")
|
|
bitfld.long 0x30 16.--19. " TRIGSRC ,Trigger source" "Disabled,EXT0,EXT1,EXT2,EXT3,EXT4,EXT5,EXT6,EXT7,EXT8,EXT9,EXT10,EXT11,EXT12,EXT13,TICK"
|
|
else
|
|
bitfld.long 0x30 16.--19. " TRIGSRC ,Trigger source" "Disabled,GIOA[0],GIOA[1],GIOA[2],GIOA[3],GIOA[4],GIOA[5],GIOA[6],GIOA[7],N2HET1[8],N2HET1[10],N2HET1[12],N2HET1[14],N2HET1[16],N2HET1[18],TICK"
|
|
endif
|
|
newline
|
|
hexmask.long.byte 0x30 8.--14. 0x01 " PSTART ,TG start address"
|
|
hexmask.long.byte 0x30 0.--6. 0x01 " PCURRENT ,Pointer to current buffer"
|
|
line.long 0x34 "TG11CTRL,MibSPI Transfer Group Control Register 11"
|
|
bitfld.long 0x34 31. " TGENA ,TG enable" "Disabled,Enabled"
|
|
bitfld.long 0x34 30. " ONESHOT ,Single transfer for TG" "Disabled,Enabled"
|
|
bitfld.long 0x34 29. " PRST ,TG pointer reset mode" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x34 28. " TGTD ,TG triggered" "Not triggered,Triggered"
|
|
bitfld.long 0x34 20.--23. " TRGEVT ,Type of trigger event" "Never,Rising edge,Falling edge,Both edges,,High active,Low-active,Always,?..."
|
|
sif cpuis("TMS570LS0232")||cpuis("TMS570LS0714*")||cpuis("TMS570LS0914*")
|
|
bitfld.long 0x34 16.--19. " TRIGSRC ,Trigger source" "Disabled,EXT0,EXT1,EXT2,EXT3,EXT4,EXT5,EXT6,EXT7,EXT8,EXT9,EXT10,EXT11,EXT12,EXT13,TICK"
|
|
else
|
|
bitfld.long 0x34 16.--19. " TRIGSRC ,Trigger source" "Disabled,GIOA[0],GIOA[1],GIOA[2],GIOA[3],GIOA[4],GIOA[5],GIOA[6],GIOA[7],N2HET1[8],N2HET1[10],N2HET1[12],N2HET1[14],N2HET1[16],N2HET1[18],TICK"
|
|
endif
|
|
newline
|
|
hexmask.long.byte 0x34 8.--14. 0x01 " PSTART ,TG start address"
|
|
hexmask.long.byte 0x34 0.--6. 0x01 " PCURRENT ,Pointer to current buffer"
|
|
line.long 0x38 "TG12CTRL,MibSPI Transfer Group Control Register 12"
|
|
bitfld.long 0x38 31. " TGENA ,TG enable" "Disabled,Enabled"
|
|
bitfld.long 0x38 30. " ONESHOT ,Single transfer for TG" "Disabled,Enabled"
|
|
bitfld.long 0x38 29. " PRST ,TG pointer reset mode" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x38 28. " TGTD ,TG triggered" "Not triggered,Triggered"
|
|
bitfld.long 0x38 20.--23. " TRGEVT ,Type of trigger event" "Never,Rising edge,Falling edge,Both edges,,High active,Low-active,Always,?..."
|
|
sif cpuis("TMS570LS0232")||cpuis("TMS570LS0714*")||cpuis("TMS570LS0914*")
|
|
bitfld.long 0x38 16.--19. " TRIGSRC ,Trigger source" "Disabled,EXT0,EXT1,EXT2,EXT3,EXT4,EXT5,EXT6,EXT7,EXT8,EXT9,EXT10,EXT11,EXT12,EXT13,TICK"
|
|
else
|
|
bitfld.long 0x38 16.--19. " TRIGSRC ,Trigger source" "Disabled,GIOA[0],GIOA[1],GIOA[2],GIOA[3],GIOA[4],GIOA[5],GIOA[6],GIOA[7],N2HET1[8],N2HET1[10],N2HET1[12],N2HET1[14],N2HET1[16],N2HET1[18],TICK"
|
|
endif
|
|
newline
|
|
hexmask.long.byte 0x38 8.--14. 0x01 " PSTART ,TG start address"
|
|
hexmask.long.byte 0x38 0.--6. 0x01 " PCURRENT ,Pointer to current buffer"
|
|
line.long 0x3C "TG13CTRL,MibSPI Transfer Group Control Register 13"
|
|
bitfld.long 0x3C 31. " TGENA ,TG enable" "Disabled,Enabled"
|
|
bitfld.long 0x3C 30. " ONESHOT ,Single transfer for TG" "Disabled,Enabled"
|
|
bitfld.long 0x3C 29. " PRST ,TG pointer reset mode" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x3C 28. " TGTD ,TG triggered" "Not triggered,Triggered"
|
|
bitfld.long 0x3C 20.--23. " TRGEVT ,Type of trigger event" "Never,Rising edge,Falling edge,Both edges,,High active,Low-active,Always,?..."
|
|
sif cpuis("TMS570LS0232")||cpuis("TMS570LS0714*")||cpuis("TMS570LS0914*")
|
|
bitfld.long 0x3C 16.--19. " TRIGSRC ,Trigger source" "Disabled,EXT0,EXT1,EXT2,EXT3,EXT4,EXT5,EXT6,EXT7,EXT8,EXT9,EXT10,EXT11,EXT12,EXT13,TICK"
|
|
else
|
|
bitfld.long 0x3C 16.--19. " TRIGSRC ,Trigger source" "Disabled,GIOA[0],GIOA[1],GIOA[2],GIOA[3],GIOA[4],GIOA[5],GIOA[6],GIOA[7],N2HET1[8],N2HET1[10],N2HET1[12],N2HET1[14],N2HET1[16],N2HET1[18],TICK"
|
|
endif
|
|
newline
|
|
hexmask.long.byte 0x3C 8.--14. 0x01 " PSTART ,TG start address"
|
|
hexmask.long.byte 0x3C 0.--6. 0x01 " PCURRENT ,Pointer to current buffer"
|
|
line.long 0x40 "TG14CTRL,MibSPI Transfer Group Control Register 14"
|
|
bitfld.long 0x40 31. " TGENA ,TG enable" "Disabled,Enabled"
|
|
bitfld.long 0x40 30. " ONESHOT ,Single transfer for TG" "Disabled,Enabled"
|
|
bitfld.long 0x40 29. " PRST ,TG pointer reset mode" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x40 28. " TGTD ,TG triggered" "Not triggered,Triggered"
|
|
bitfld.long 0x40 20.--23. " TRGEVT ,Type of trigger event" "Never,Rising edge,Falling edge,Both edges,,High active,Low-active,Always,?..."
|
|
sif cpuis("TMS570LS0232")||cpuis("TMS570LS0714*")||cpuis("TMS570LS0914*")
|
|
bitfld.long 0x40 16.--19. " TRIGSRC ,Trigger source" "Disabled,EXT0,EXT1,EXT2,EXT3,EXT4,EXT5,EXT6,EXT7,EXT8,EXT9,EXT10,EXT11,EXT12,EXT13,TICK"
|
|
else
|
|
bitfld.long 0x40 16.--19. " TRIGSRC ,Trigger source" "Disabled,GIOA[0],GIOA[1],GIOA[2],GIOA[3],GIOA[4],GIOA[5],GIOA[6],GIOA[7],N2HET1[8],N2HET1[10],N2HET1[12],N2HET1[14],N2HET1[16],N2HET1[18],TICK"
|
|
endif
|
|
newline
|
|
hexmask.long.byte 0x40 8.--14. 0x01 " PSTART ,TG start address"
|
|
hexmask.long.byte 0x40 0.--6. 0x01 " PCURRENT ,Pointer to current buffer"
|
|
line.long 0x44 "TG15CTRL,MibSPI Transfer Group Control Register 15"
|
|
bitfld.long 0x44 31. " TGENA ,TG enable" "Disabled,Enabled"
|
|
bitfld.long 0x44 30. " ONESHOT ,Single transfer for TG" "Disabled,Enabled"
|
|
bitfld.long 0x44 29. " PRST ,TG pointer reset mode" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x44 28. " TGTD ,TG triggered" "Not triggered,Triggered"
|
|
bitfld.long 0x44 20.--23. " TRGEVT ,Type of trigger event" "Never,Rising edge,Falling edge,Both edges,,High active,Low-active,Always,?..."
|
|
sif cpuis("TMS570LS0232")||cpuis("TMS570LS0714*")||cpuis("TMS570LS0914*")
|
|
bitfld.long 0x44 16.--19. " TRIGSRC ,Trigger source" "Disabled,EXT0,EXT1,EXT2,EXT3,EXT4,EXT5,EXT6,EXT7,EXT8,EXT9,EXT10,EXT11,EXT12,EXT13,TICK"
|
|
else
|
|
bitfld.long 0x44 16.--19. " TRIGSRC ,Trigger source" "Disabled,GIOA[0],GIOA[1],GIOA[2],GIOA[3],GIOA[4],GIOA[5],GIOA[6],GIOA[7],N2HET1[8],N2HET1[10],N2HET1[12],N2HET1[14],N2HET1[16],N2HET1[18],TICK"
|
|
endif
|
|
newline
|
|
hexmask.long.byte 0x44 8.--14. 0x01 " PSTART ,TG start address"
|
|
hexmask.long.byte 0x44 0.--6. 0x01 " PCURRENT ,Pointer to current buffer"
|
|
sif (cpu()!=("TMS570LS0332")&&cpu()!=("TMS570LS0432")&&!cpuis("TMS570LS0232"))
|
|
group.long 0xD8++0x1F
|
|
line.long 0x0 "DMA0CTRL,MibSPI DMA Channel Control Register 1"
|
|
bitfld.long 0x0 31. " ONESHOT ,Auto-disable of DMA channel after ICOUNT+1 transfers" "0,1"
|
|
hexmask.long.byte 0x0 24.--30. 1. " BUFID ,Buffer utilized for DMA transfer"
|
|
bitfld.long 0x0 20.--23. " RXDMA_MAP ,Each MibSPI DMA channel can be linked to two physical DMA" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x0 16.--19. " TXDMA_MAP ,Each MibSPI DMA channel can be linked to two physical DMA" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x0 15. " RXDMAENA ,Receive data DMA channel enable" "Disabled,Enabled"
|
|
bitfld.long 0x0 14. " TXDMAENA ,Transmit data DMA channel enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x0 13. " NOBRK ,Non-interleaved DMA block transfer" "Not performed,Performed"
|
|
bitfld.long 0x0 8.--12. " ICOUNT ,Initial count of DMA transfers" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32"
|
|
bitfld.long 0x0 6. " COUNTBIT17 ,17th bit of the COUNT field of DMAxCOUNT register" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0.--5. " COUNT ,Actual number of remaining DMA transfers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
line.long 0x4 "DMA1CTRL,MibSPI DMA Channel Control Register 1"
|
|
bitfld.long 0x4 31. " ONESHOT ,Auto-disable of DMA channel after ICOUNT+1 transfers" "0,1"
|
|
hexmask.long.byte 0x4 24.--30. 1. " BUFID ,Buffer utilized for DMA transfer"
|
|
bitfld.long 0x4 20.--23. " RXDMA_MAP ,Each MibSPI DMA channel can be linked to two physical DMA" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x4 16.--19. " TXDMA_MAP ,Each MibSPI DMA channel can be linked to two physical DMA" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x4 15. " RXDMAENA ,Receive data DMA channel enable" "Disabled,Enabled"
|
|
bitfld.long 0x4 14. " TXDMAENA ,Transmit data DMA channel enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x4 13. " NOBRK ,Non-interleaved DMA block transfer" "Not performed,Performed"
|
|
bitfld.long 0x4 8.--12. " ICOUNT ,Initial count of DMA transfers" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32"
|
|
bitfld.long 0x4 6. " COUNTBIT17 ,17th bit of the COUNT field of DMAxCOUNT register" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0.--5. " COUNT ,Actual number of remaining DMA transfers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
line.long 0x8 "DMA2CTRL,MibSPI DMA Channel Control Register 1"
|
|
bitfld.long 0x8 31. " ONESHOT ,Auto-disable of DMA channel after ICOUNT+1 transfers" "0,1"
|
|
hexmask.long.byte 0x8 24.--30. 1. " BUFID ,Buffer utilized for DMA transfer"
|
|
bitfld.long 0x8 20.--23. " RXDMA_MAP ,Each MibSPI DMA channel can be linked to two physical DMA" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x8 16.--19. " TXDMA_MAP ,Each MibSPI DMA channel can be linked to two physical DMA" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x8 15. " RXDMAENA ,Receive data DMA channel enable" "Disabled,Enabled"
|
|
bitfld.long 0x8 14. " TXDMAENA ,Transmit data DMA channel enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x8 13. " NOBRK ,Non-interleaved DMA block transfer" "Not performed,Performed"
|
|
bitfld.long 0x8 8.--12. " ICOUNT ,Initial count of DMA transfers" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32"
|
|
bitfld.long 0x8 6. " COUNTBIT17 ,17th bit of the COUNT field of DMAxCOUNT register" "0,1"
|
|
newline
|
|
bitfld.long 0x8 0.--5. " COUNT ,Actual number of remaining DMA transfers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
line.long 0xC "DMA3CTRL,MibSPI DMA Channel Control Register 1"
|
|
bitfld.long 0xC 31. " ONESHOT ,Auto-disable of DMA channel after ICOUNT+1 transfers" "0,1"
|
|
hexmask.long.byte 0xC 24.--30. 1. " BUFID ,Buffer utilized for DMA transfer"
|
|
bitfld.long 0xC 20.--23. " RXDMA_MAP ,Each MibSPI DMA channel can be linked to two physical DMA" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0xC 16.--19. " TXDMA_MAP ,Each MibSPI DMA channel can be linked to two physical DMA" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0xC 15. " RXDMAENA ,Receive data DMA channel enable" "Disabled,Enabled"
|
|
bitfld.long 0xC 14. " TXDMAENA ,Transmit data DMA channel enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0xC 13. " NOBRK ,Non-interleaved DMA block transfer" "Not performed,Performed"
|
|
bitfld.long 0xC 8.--12. " ICOUNT ,Initial count of DMA transfers" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32"
|
|
bitfld.long 0xC 6. " COUNTBIT17 ,17th bit of the COUNT field of DMAxCOUNT register" "0,1"
|
|
newline
|
|
bitfld.long 0xC 0.--5. " COUNT ,Actual number of remaining DMA transfers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
line.long 0x10 "DMA4CTRL,MibSPI DMA Channel Control Register 1"
|
|
bitfld.long 0x10 31. " ONESHOT ,Auto-disable of DMA channel after ICOUNT+1 transfers" "0,1"
|
|
hexmask.long.byte 0x10 24.--30. 1. " BUFID ,Buffer utilized for DMA transfer"
|
|
bitfld.long 0x10 20.--23. " RXDMA_MAP ,Each MibSPI DMA channel can be linked to two physical DMA" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x10 16.--19. " TXDMA_MAP ,Each MibSPI DMA channel can be linked to two physical DMA" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x10 15. " RXDMAENA ,Receive data DMA channel enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 14. " TXDMAENA ,Transmit data DMA channel enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x10 13. " NOBRK ,Non-interleaved DMA block transfer" "Not performed,Performed"
|
|
bitfld.long 0x10 8.--12. " ICOUNT ,Initial count of DMA transfers" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32"
|
|
bitfld.long 0x10 6. " COUNTBIT17 ,17th bit of the COUNT field of DMAxCOUNT register" "0,1"
|
|
newline
|
|
bitfld.long 0x10 0.--5. " COUNT ,Actual number of remaining DMA transfers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
line.long 0x14 "DMA5CTRL,MibSPI DMA Channel Control Register 1"
|
|
bitfld.long 0x14 31. " ONESHOT ,Auto-disable of DMA channel after ICOUNT+1 transfers" "0,1"
|
|
hexmask.long.byte 0x14 24.--30. 1. " BUFID ,Buffer utilized for DMA transfer"
|
|
bitfld.long 0x14 20.--23. " RXDMA_MAP ,Each MibSPI DMA channel can be linked to two physical DMA" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x14 16.--19. " TXDMA_MAP ,Each MibSPI DMA channel can be linked to two physical DMA" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x14 15. " RXDMAENA ,Receive data DMA channel enable" "Disabled,Enabled"
|
|
bitfld.long 0x14 14. " TXDMAENA ,Transmit data DMA channel enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x14 13. " NOBRK ,Non-interleaved DMA block transfer" "Not performed,Performed"
|
|
bitfld.long 0x14 8.--12. " ICOUNT ,Initial count of DMA transfers" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32"
|
|
bitfld.long 0x14 6. " COUNTBIT17 ,17th bit of the COUNT field of DMAxCOUNT register" "0,1"
|
|
newline
|
|
bitfld.long 0x14 0.--5. " COUNT ,Actual number of remaining DMA transfers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
line.long 0x18 "DMA6CTRL,MibSPI DMA Channel Control Register 1"
|
|
bitfld.long 0x18 31. " ONESHOT ,Auto-disable of DMA channel after ICOUNT+1 transfers" "0,1"
|
|
hexmask.long.byte 0x18 24.--30. 1. " BUFID ,Buffer utilized for DMA transfer"
|
|
bitfld.long 0x18 20.--23. " RXDMA_MAP ,Each MibSPI DMA channel can be linked to two physical DMA" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x18 16.--19. " TXDMA_MAP ,Each MibSPI DMA channel can be linked to two physical DMA" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x18 15. " RXDMAENA ,Receive data DMA channel enable" "Disabled,Enabled"
|
|
bitfld.long 0x18 14. " TXDMAENA ,Transmit data DMA channel enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x18 13. " NOBRK ,Non-interleaved DMA block transfer" "Not performed,Performed"
|
|
bitfld.long 0x18 8.--12. " ICOUNT ,Initial count of DMA transfers" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32"
|
|
bitfld.long 0x18 6. " COUNTBIT17 ,17th bit of the COUNT field of DMAxCOUNT register" "0,1"
|
|
newline
|
|
bitfld.long 0x18 0.--5. " COUNT ,Actual number of remaining DMA transfers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
line.long 0x1C "DMA7CTRL,MibSPI DMA Channel Control Register 1"
|
|
bitfld.long 0x1C 31. " ONESHOT ,Auto-disable of DMA channel after ICOUNT+1 transfers" "0,1"
|
|
hexmask.long.byte 0x1C 24.--30. 1. " BUFID ,Buffer utilized for DMA transfer"
|
|
bitfld.long 0x1C 20.--23. " RXDMA_MAP ,Each MibSPI DMA channel can be linked to two physical DMA" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x1C 16.--19. " TXDMA_MAP ,Each MibSPI DMA channel can be linked to two physical DMA" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x1C 15. " RXDMAENA ,Receive data DMA channel enable" "Disabled,Enabled"
|
|
bitfld.long 0x1C 14. " TXDMAENA ,Transmit data DMA channel enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x1C 13. " NOBRK ,Non-interleaved DMA block transfer" "Not performed,Performed"
|
|
bitfld.long 0x1C 8.--12. " ICOUNT ,Initial count of DMA transfers" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32"
|
|
bitfld.long 0x1C 6. " COUNTBIT17 ,17th bit of the COUNT field of DMAxCOUNT register" "0,1"
|
|
newline
|
|
bitfld.long 0x1C 0.--5. " COUNT ,Actual number of remaining DMA transfers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
group.long 0xF8++0x1F
|
|
line.long 0x0 "DMA0 COUNT,MibSPI DMA0 COUNT Register"
|
|
hexmask.long.word 0x0 16.--31. 1. " ICOUNT0 ,Initial number of DMA transfers"
|
|
hexmask.long.word 0x0 0.--15. 1. " COUNT0 ,The actual number of remaining DMA transfers"
|
|
line.long 0x4 "DMA1 COUNT,MibSPI DMA1 COUNT Register"
|
|
hexmask.long.word 0x4 16.--31. 1. " ICOUNT1 ,Initial number of DMA transfers"
|
|
hexmask.long.word 0x4 0.--15. 1. " COUNT1 ,The actual number of remaining DMA transfers"
|
|
line.long 0x8 "DMA2 COUNT,MibSPI DMA2 COUNT Register"
|
|
hexmask.long.word 0x8 16.--31. 1. " ICOUNT2 ,Initial number of DMA transfers"
|
|
hexmask.long.word 0x8 0.--15. 1. " COUNT2 ,The actual number of remaining DMA transfers"
|
|
line.long 0xC "DMA3 COUNT,MibSPI DMA3 COUNT Register"
|
|
hexmask.long.word 0xC 16.--31. 1. " ICOUNT3 ,Initial number of DMA transfers"
|
|
hexmask.long.word 0xC 0.--15. 1. " COUNT3 ,The actual number of remaining DMA transfers"
|
|
line.long 0x10 "DMA4 COUNT,MibSPI DMA4 COUNT Register"
|
|
hexmask.long.word 0x10 16.--31. 1. " ICOUNT4 ,Initial number of DMA transfers"
|
|
hexmask.long.word 0x10 0.--15. 1. " COUNT4 ,The actual number of remaining DMA transfers"
|
|
line.long 0x14 "DMA5 COUNT,MibSPI DMA5 COUNT Register"
|
|
hexmask.long.word 0x14 16.--31. 1. " ICOUNT5 ,Initial number of DMA transfers"
|
|
hexmask.long.word 0x14 0.--15. 1. " COUNT5 ,The actual number of remaining DMA transfers"
|
|
line.long 0x18 "DMA6 COUNT,MibSPI DMA6 COUNT Register"
|
|
hexmask.long.word 0x18 16.--31. 1. " ICOUNT6 ,Initial number of DMA transfers"
|
|
hexmask.long.word 0x18 0.--15. 1. " COUNT6 ,The actual number of remaining DMA transfers"
|
|
line.long 0x1C "DMA7 COUNT,MibSPI DMA7 COUNT Register"
|
|
hexmask.long.word 0x1C 16.--31. 1. " ICOUNT7 ,Initial number of DMA transfers"
|
|
hexmask.long.word 0x1C 0.--15. 1. " COUNT7 ,The actual number of remaining DMA transfers"
|
|
group.long 0x118++0x03
|
|
line.long 0x00 "DMACNTLEN,MibSPI DMACNTLEN Register"
|
|
bitfld.long 0x00 0. " LARGECOUNT ,Counters select" "DMAxCTRL,DMAxCOUNT"
|
|
endif
|
|
group.long 0x120++0x03
|
|
line.long 0x00 "UERRCTRL,Uncorrectable Parity Error Control Register"
|
|
bitfld.long 0x00 8. " PTESTEN ,Parity memory test enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--3. " EDEN ,Error detection enable" "Enabled,Enabled,Enabled,Enabled,Enabled,Disabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled"
|
|
group.long 0x124++0x03
|
|
line.long 0x00 "UERRSTAT,Uncorrectable Parity Error Status Register"
|
|
eventfld.long 0x00 1. " EDFLG1 ,Uncorrectable parity error detection flag" "Not occurred,Occurred"
|
|
eventfld.long 0x00 0. " EDFLG0 ,Uncorrectable parity error detection flag" "Not occurred,Occurred"
|
|
hgroup.long 0x128++0x03
|
|
hide.long 0x00 "UERRADDR1,Uncorrectable Parity Error Address Register"
|
|
in
|
|
hgroup.long 0x12C++0x03
|
|
hide.long 0x00 "UERRADDR0,Uncorrectable Parity Error Address Register"
|
|
in
|
|
hgroup.long 0x130++0x03
|
|
hide.long 0x00 "RXOVRN_BUF_ADDR,Receive RAM Overrun Buffer Address Register"
|
|
in
|
|
sif cpuis("TMS570LS0714*")||cpuis("TMS570LS0914*")||cpuis("TMS570LS0232")
|
|
if (((per.l.be(ad:0xFFF7F600+0x134))&0x2)==0x2)
|
|
group.long 0x134++0x03
|
|
line.long 0x00 "IOLPBKTSTCR,SPI IO Loopback Test Control Register"
|
|
bitfld.long 0x00 24. " SCSFAILFLG ,Failure on SPISCS pin compare during analog loopback" "Not occurred,Occurred"
|
|
bitfld.long 0x00 20. " CTRL_BITERR ,Controls inducing of BITERR during I/O loopback test mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " CTRL_DESYNC ,Controls inducing of the desync error during I/O loopback test mode" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 18. " CTRL_PARERR ,Controls inducing of parity errors during I/O loopback test mode" "No error,Error"
|
|
bitfld.long 0x00 17. " CTRL_TIMEOUT ,Controls inducing of the timeout error during I/O loopbacK test mode" "No error,Error"
|
|
bitfld.long 0x00 16. " CTRL_DLENERR ,Controls inducing of the data length error during I/O loopback test mode" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 8.--11. " IOLPBKTSTENA ,Module I/O loopback test enable key" "Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Enabled,Disabled,Disabled,Disabled,Disabled,Disabled"
|
|
sif cpuis("TMS570LS0232")
|
|
bitfld.long 0x00 3.--5. " ERRSCSPIN ,Inject error on chip-select pin number" "/SPISCS[0],/SPISCS[1],/SPISCS[2],/SPISCS[3],?..."
|
|
else
|
|
bitfld.long 0x00 3.--5. " ERRSCSPIN ,Inject error on chip-select pin number" "/SPISCS[0],/SPISCS[1],/SPISCS[2],/SPISCS[3],/SPISCS[4],/SPISCS[5],/SPISCS[6],/SPISCS[7]"
|
|
endif
|
|
bitfld.long 0x00 2. " CTRLSCSPINERR ,Enable/disable the injection of an error on the SPISCS[3:0] pins" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 1. " LPBK_TYPE ,Module I/O loopback type (analog/digital)" "Digital,Analog"
|
|
bitfld.long 0x00 0. " RXP_ENA ,Enable analog loopback through the receive pin" "Transmit,Receive"
|
|
else
|
|
group.long 0x134++0x03
|
|
line.long 0x00 "IOLPBKTSTCR,SPI IO Loopback Test Control Register"
|
|
bitfld.long 0x00 24. " SCSFAILFLG ,Failure on SPISCS pin compare during analog loopback" "Not occurred,Occurred"
|
|
bitfld.long 0x00 20. " CTRL_BITERR ,Controls inducing of BITERR during I/O loopback test mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " CTRL_DESYNC ,Controls inducing of the desync error during I/O loopback test mode" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 18. " CTRL_PARERR ,Controls inducing of parity errors during I/O loopback test mode" "No error,Error"
|
|
bitfld.long 0x00 17. " CTRL_TIMEOUT ,Controls inducing of the timeout error during I/O loopbacK test mode" "No error,Error"
|
|
bitfld.long 0x00 16. " CTRL_DLENERR ,Controls inducing of the data length error during I/O loopback test mode" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 8.--11. " IOLPBKTSTENA ,Module I/O loopback test enable key" "Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Enabled,Disabled,Disabled,Disabled,Disabled,Disabled"
|
|
sif cpuis("TMS570LS0232")
|
|
bitfld.long 0x00 3.--5. " ERRSCSPIN ,Inject error on chip-select pin number" "/SPISCS[0],/SPISCS[1],/SPISCS[2],/SPISCS[3],?..."
|
|
else
|
|
bitfld.long 0x00 3.--5. " ERRSCSPIN ,Inject error on chip-select pin number" "/SPISCS[0],/SPISCS[1],/SPISCS[2],/SPISCS[3],/SPISCS[4],/SPISCS[5],/SPISCS[6],/SPISCS[7]"
|
|
endif
|
|
bitfld.long 0x00 2. " CTRLSCSPINERR ,Enable/disable the injection of an error on the SPISCS[3:0] pins" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 1. " LPBK_TYPE ,Module I/O loopback type (analog/digital)" "Digital,Analog"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0xFFF7F600+0x134))&0x2)==0x2)
|
|
group.long 0x134++0x03
|
|
line.long 0x00 "IOLPBKTSTCR,SPI IO Loopback Test Control Register"
|
|
bitfld.long 0x00 24. " SCSFAILFLG ,Failure on SPISCS pin compare during analog loopback" "Not occurred,Occurred"
|
|
bitfld.long 0x00 20. " CTRL_BITERR ,Controls inducing of BITERR during I/O loopback test mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " CTRL_DESYNC ,Controls inducing of the desync error during I/O loopback test mode" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 18. " CTRL_PARERR ,Controls inducing of parity errors during I/O loopback test mode" "No error,Error"
|
|
bitfld.long 0x00 17. " CTRL_TIMEOUT ,Controls inducing of the timeout error during I/O loopbacK test mode" "No error,Error"
|
|
bitfld.long 0x00 16. " CTRL_DLENERR ,Controls inducing of the data length error during I/O loopback test mode" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 8.--11. " IOLPBKTSTENA ,Module I/O loopback test enable key" "Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Enabled,Disabled,Disabled,Disabled,Disabled,Disabled"
|
|
bitfld.long 0x00 3.--5. " ERRSCSPIN ,Inject error on chip-select pin number" "/SPISCS[0],/SPISCS[1],/SPISCS[2],/SPISCS[3],/SPISCS[4],/SPISCS[5],/SPISCS[6],/SPISCS[7]"
|
|
bitfld.long 0x00 2. " CTRLSCSPINERR ,Enable/disable the injection of an error on the SPISCS[3:0] pins" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 1. " LPBK_TYPE ,Module I/O loopback type (analog/digital)" "Digital,Analog"
|
|
bitfld.long 0x00 0. " RXP_ENA ,Enable analog loopback through the receive pin" "Transmit,Receive"
|
|
else
|
|
group.long 0x134++0x03
|
|
line.long 0x00 "IOLPBKTSTCR,SPI IO Loopback Test Control Register"
|
|
bitfld.long 0x00 24. " SCSFAILFLG ,Failure on SPISCS pin compare during analog loopback" "Not occurred,Occurred"
|
|
bitfld.long 0x00 20. " CTRL_BITERR ,Controls inducing of BITERR during I/O loopback test mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " CTRL_DESYNC ,Controls inducing of the desync error during I/O loopback test mode" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 18. " CTRL_PARERR ,Controls inducing of parity errors during I/O loopback test mode" "No error,Error"
|
|
bitfld.long 0x00 17. " CTRL_TIMEOUT ,Controls inducing of the timeout error during I/O loopbacK test mode" "No error,Error"
|
|
bitfld.long 0x00 16. " CTRL_DLENERR ,Controls inducing of the data length error during I/O loopback test mode" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 8.--11. " IOLPBKTSTENA ,Module I/O loopback test enable key" "Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Enabled,Disabled,Disabled,Disabled,Disabled,Disabled"
|
|
bitfld.long 0x00 3.--5. " ERRSCSPIN ,Inject error on chip-select pin number" "/SPISCS[0],/SPISCS[1],/SPISCS[2],/SPISCS[3],/SPISCS[4],/SPISCS[5],/SPISCS[6],/SPISCS[7]"
|
|
bitfld.long 0x00 2. " CTRLSCSPINERR ,Enable/disable the injection of an error on the SPISCS[3:0] pins" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 1. " LPBK_TYPE ,Module I/O loopback type (analog/digital)" "Digital,Analog"
|
|
endif
|
|
endif
|
|
sif (cpu()=="TMS570LC4357"||cpu()==("TMS570LS0332")||cpu()==("TMS570LS0432")||cpuis("TMS570LS1114*")||cpuis("TMS570LS1115*")||cpuis("TMS570LS1224*")||cpuis("TMS570LS1225*")||cpuis("TMS570LS1227*")||cpuis("TMS570LS0232")||cpuis("TMS570LS0714*")||cpuis("TMS570LS0914*"))
|
|
width 21.
|
|
newline
|
|
group.long 0x138++0x07
|
|
line.long 0x00 "EXTENDED_PRESCALE_1, SPI Extended Prescale Register 1"
|
|
hexmask.long.word 0x00 16.--26. 1. " EPRESCALE_FMT1 , Extended Prescale value for SPIFMT1"
|
|
hexmask.long.word 0x00 0.--10. 1. " EPRESCALE_FMT0 , Extended Prescale value for SPIFMT0"
|
|
line.long 0x04 "EXTENDED_PRESCALE_2, SPI Extended Prescale Register 2"
|
|
hexmask.long.word 0x04 16.--26. 1. " EPRESCALE_FMT3 , Extended Prescale value for SPIFMT3"
|
|
hexmask.long.word 0x04 0.--10. 1. " EPRESCALE_FMT2 , Extended Prescale value for SPIFMT2"
|
|
endif
|
|
sif !cpuis("TMS570LS0232")&&!cpuis("TMS570LS0714*")&&!cpuis("TMS570LS0914*")
|
|
sif (cpu()=="TMS570LC4357"||cpu()==("TMS570LS0332")||cpu()==("TMS570LS0432")||cpuis("TMS570LS1114*")||cpuis("TMS570LS1115*")||cpuis("TMS570LS1224*")||cpuis("TMS570LS1225*")||cpuis("TMS570LS1227*"))
|
|
sif cpuis("TMS570LC4357")
|
|
group.long 0x140++0x03
|
|
line.long 0x00 "ECCDIAG_CTRL, ECC Diagnostic Control register"
|
|
bitfld.long 0x00 0.--3. " ECCDIAG_EN , ECC Diagnostic mode Enable Key bits" "Disabled,Disabled,Disabled,Disabled,Disabled,Enabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled"
|
|
endif
|
|
if ((per.l(ad:0xFFF7F600+0x140)&0x5)==0x5)
|
|
group.long 0x144++0x03
|
|
line.long 0x00 "ECCDIAG_STAT, ECC Diagnostic Status register"
|
|
eventfld.long 0x00 17. " DEFLG[1] , Double bit Error is detected for RXRAM" "No error,Error"
|
|
eventfld.long 0x00 16. " DEFLG[0] , Double bit Error is detected for TXRAM" "No error,Error"
|
|
eventfld.long 0x00 1. " SEFLG[1] , Single bit Error is detected for RXRAM" "No error,Error"
|
|
eventfld.long 0x00 0. " SEFLG[0] , Single bit Error is detected for TXRAM" "No error,Error"
|
|
else
|
|
hgroup.long 0x144++0x03
|
|
hide.long 0x00 "ECCDIAG_STAT, ECC Diagnostic Status register"
|
|
in
|
|
endif
|
|
hgroup.long 0x148++0x03
|
|
hide.long 0x00 "SBERRADDR1, Single Bit Error Address Register - RXRAM"
|
|
in
|
|
hgroup.long 0x14C++0x03
|
|
hide.long 0x00 "SBERRADDR0, Single Bit Error Address Register - TXRAM"
|
|
in
|
|
endif
|
|
endif
|
|
sif cpuis("TMS570LS0232")||cpuis("TMS570LS0714*")||cpuis("TMS570LS0914*")
|
|
endian.be
|
|
endif
|
|
width 0xB
|
|
tree.end
|
|
tree "SPI3"
|
|
base ad:0xFFF7F800
|
|
width 17.
|
|
sif cpuis("TMS570LS0232")||cpuis("TMS570LS0714*")||cpuis("TMS570LS0914*")
|
|
endian.be
|
|
endif
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "SPIGCR0,SPI Global Control Register 0"
|
|
bitfld.long 0x00 0. " NRESET ,Reset bit for the module" "No reset,Reset"
|
|
group.long 0x04++0x0F
|
|
line.long 0x00 "SPIGCR1,SPI Global Control Register 1"
|
|
bitfld.long 0x00 24. " SPIEN ,SPI enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " LOOPBACK ,Internal loop-back test mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " POWERDOWN ,SPI state machine enters a power-down state" "No power-down,Power-down"
|
|
newline
|
|
bitfld.long 0x00 1. " CLKMOD ,Clock mode" "External,Internally"
|
|
bitfld.long 0x00 0. " MASTER ,SPISIMO/SPISOMI pin direction determination" "Input/output,Output/input"
|
|
line.long 0x04 "SPIINT0,SPI Interrupt Register"
|
|
bitfld.long 0x04 24. " ENABLEHIGHZ ,SPIENA pin high-impedance enable" "Inactive,Active"
|
|
bitfld.long 0x04 16. " DMAREQEN ,DMA request enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 9. " TXINTENA ,TX interrupt flag enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x04 8. " RXINTENA ,RX interrupt flag enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 6. " RXOVRNINTENA ,Overrun interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 4. " BITERRENA ,Enables interrupt on bit error" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x04 3. " DESYNCENA ,Enables interrupt on desynchronized slave" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " PARERRENA ,Enables interrupt-on-parity-error" "Disabled,Enabled"
|
|
bitfld.long 0x04 1. " TIMEOUTENA ,Enables interrupt on ENA signal time-out" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x04 0. " DLENERRENA ,Data length error interrupt enable" "Disabled,Enabled"
|
|
line.long 0x08 "SPILVL,SPI Interrupt Level Register"
|
|
bitfld.long 0x08 9. " TXINTLVL ,Transmit interrupt level" "INT0,INT1"
|
|
bitfld.long 0x08 8. " RXINTLVL ,Receive interrupt level" "INT0,INT1"
|
|
sif !cpuis("TMS570LS0232")
|
|
bitfld.long 0x08 6. " RXOVRNINTLVL ,Receive overrun interrupt level" "INT0,INT1"
|
|
endif
|
|
newline
|
|
bitfld.long 0x08 4. " BITERRLVL ,Bit error interrupt level" "INT0,INT1"
|
|
bitfld.long 0x08 3. " DESYNCLVL ,Desynchronized slave interrupt level (master mode only)" "INT0,INT1"
|
|
bitfld.long 0x08 2. " PARERRLVL ,Parity error interrupt level" "INT0,INT1"
|
|
newline
|
|
bitfld.long 0x08 1. " TIMEOUTLVL ,SPIENA pin time-out interrupt level" "INT0,INT1"
|
|
bitfld.long 0x08 0. " DLENERRLVL ,Data length error interrupt level (line) select" "INT0,INT1"
|
|
line.long 0x0C "SPIFLG,SPI Flag Register"
|
|
bitfld.long 0x0C 24. " BUFINITACTIVE ,Indicates the status of multi-buffer initialization process" "Completed,Not completed"
|
|
bitfld.long 0x0C 9. " TXINTFLG ,Transmitter-empty interrupt flag" "No interrupt,Interrupt"
|
|
eventfld.long 0x0C 8. " RXINTFLG ,Receiver-full interrupt flag" "No interrupt,Interrupt"
|
|
newline
|
|
eventfld.long 0x0C 6. " RXOVRNINTFLG ,Overrun interrupt enable" "Disabled,Enabled"
|
|
eventfld.long 0x0C 4. " BITERRFLG ,Enables interrupt on bit error" "Disabled,Enabled"
|
|
eventfld.long 0x0C 3. " DESYNCFLG ,Enables interrupt on desynchronized slave" "No interrupt,Interrupt"
|
|
newline
|
|
eventfld.long 0x0C 2. " PARITYERRFLG ,Enables interrupt-on-parity-error" "No error,Error"
|
|
eventfld.long 0x0C 1. " TIMEOUTFLG ,Enables interrupt on ENA signal time-out" "No interrupt,Interrupt"
|
|
eventfld.long 0x0C 0. " DLENERRFLG ,Data length error interrupt enable" "No interrupt,Interrupt"
|
|
group.long 0x14++0x23
|
|
line.long 0x00 "SPIPC0,SPI Pin Control Register 0"
|
|
sif !cpuis("TMS570LS0232")&&!cpuis("TMS570LS0332")&&!cpuis("TMS570LS0432")
|
|
bitfld.long 0x00 31. " SOMIFUN7 ,SPISOMI[7] pin function" "GIO,SPI"
|
|
bitfld.long 0x00 30. " SOMIFUN6 ,SPISOMI[6] pin function" "GIO,SPI"
|
|
bitfld.long 0x00 29. " SOMIFUN5 ,SPISOMI[5] pin function" "GIO,SPI"
|
|
newline
|
|
bitfld.long 0x00 28. " SOMIFUN4 ,SPISOMI[4] pin function" "GIO,SPI"
|
|
bitfld.long 0x00 27. " SOMIFUN3 ,SPISOMI[3] pin function" "GIO,SPI"
|
|
bitfld.long 0x00 26. " SOMIFUN2 ,SPISOMI[2] pin function" "GIO,SPI"
|
|
newline
|
|
bitfld.long 0x00 25. " SOMIFUN1 ,SPISOMI[1] pin function" "GIO,SPI"
|
|
bitfld.long 0x00 24. " SOMIFUN0 ,SPISOMI[0] pin function (mirror of bit 11)" "GIO,SPI"
|
|
bitfld.long 0x00 23. " SIMOFUN7 ,SPISIMO[7] pin function" "GIO,SPI"
|
|
newline
|
|
bitfld.long 0x00 22. " SIMOFUN6 ,SPISIMO[6] pin function" "GIO,SPI"
|
|
bitfld.long 0x00 21. " SIMOFUN5 ,SPISIMO[5] pin function" "GIO,SPI"
|
|
bitfld.long 0x00 20. " SIMOFUN4 ,SPISIMO[4] pin function" "GIO,SPI"
|
|
newline
|
|
bitfld.long 0x00 19. " SIMOFUN3 ,SPISIMO[3] pin function" "GIO,SPI"
|
|
bitfld.long 0x00 18. " SIMOFUN2 ,SPISIMO[2] pin function" "GIO,SPI"
|
|
bitfld.long 0x00 17. " SIMOFUN1 ,SPISIMO[1] pin function" "GIO,SPI"
|
|
newline
|
|
bitfld.long 0x00 16. " SIMOFUN0 ,SPISIMO[0] pin function (mirror of bit 10)" "GIO,SPI"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 11. " SOMIFUN0 ,SPISOMI[0] pin function" "GIO,SPI"
|
|
bitfld.long 0x00 10. " SIMOFUN0 ,SPISIMO[0] pin function" "GIO,SPI"
|
|
newline
|
|
bitfld.long 0x00 9. " CLKFUN ,SPI clock function" "GIO,SPI"
|
|
bitfld.long 0x00 8. " ENAFUN ,SPIENA function" "GIO,SPI"
|
|
bitfld.long 0x00 7. " SCSFUN7 ,SPISCS7 function 7" "GIO,SPI"
|
|
newline
|
|
bitfld.long 0x00 6. " SCSFUN6 ,SPISCS6 function 6" "GIO,SPI"
|
|
bitfld.long 0x00 5. " SCSFUN5 ,SPISCS5 function 5" "GIO,SPI"
|
|
bitfld.long 0x00 4. " SCSFUN4 ,SPISCS4 function 4" "GIO,SPI"
|
|
newline
|
|
bitfld.long 0x00 3. " SCSFUN3 ,SPISCS3 function 3" "GIO,SPI"
|
|
bitfld.long 0x00 2. " SCSFUN2 ,SPISCS2 function 2" "GIO,SPI"
|
|
bitfld.long 0x00 1. " SCSFUN1 ,SPISCS1 function 1" "GIO,SPI"
|
|
newline
|
|
bitfld.long 0x00 0. " SCSFUN0 ,SPISCS0 function 0" "GIO,SPI"
|
|
line.long 0x04 "SPIPC1,SPI Pin Control Register 1"
|
|
bitfld.long 0x04 31. " SOMIDIR7 ,SPISOMI[7] pin direction" "GIO,SPI"
|
|
bitfld.long 0x04 30. " SOMIDIR6 ,SPISOMI[6] pin direction" "GIO,SPI"
|
|
bitfld.long 0x04 29. " SOMIDIR5 ,SPISOMI[5] pin direction" "GIO,SPI"
|
|
newline
|
|
bitfld.long 0x04 28. " SOMIDIR4 ,SPISOMI[4] pin direction" "GIO,SPI"
|
|
bitfld.long 0x04 27. " SOMIDIR3 ,SPISOMI[3] pin direction" "GIO,SPI"
|
|
bitfld.long 0x04 26. " SOMIDIR2 ,SPISOMI[2] pin direction" "GIO,SPI"
|
|
newline
|
|
bitfld.long 0x04 25. " SOMIDIR1 ,SPISOMI[1] pin direction" "GIO,SPI"
|
|
bitfld.long 0x04 24. " SOMIDIR0 ,SPISOMI[0] pin direction (mirror of bit 11)" "GIO,SPI"
|
|
bitfld.long 0x04 23. " SIMODIR7 ,SPISIMO[7] pin direction" "GIO,SPI"
|
|
newline
|
|
bitfld.long 0x04 22. " SIMODIR6 ,SPISIMO[6] pin direction" "GIO,SPI"
|
|
bitfld.long 0x04 21. " SIMODIR5 ,SPISIMO[5] pin direction" "GIO,SPI"
|
|
bitfld.long 0x04 20. " SIMODIR4 ,SPISIMO[4] pin direction" "GIO,SPI"
|
|
newline
|
|
bitfld.long 0x04 19. " SIMODIR3 ,SPISIMO[3] pin direction" "GIO,SPI"
|
|
bitfld.long 0x04 18. " SIMODIR2 ,SPISIMO[2] pin direction" "GIO,SPI"
|
|
bitfld.long 0x04 17. " SIMODIR1 ,SPISIMO[1] pin direction" "GIO,SPI"
|
|
newline
|
|
bitfld.long 0x04 16. " SIMODIR0 ,SPISIMO[0] pin direction (mirror of bit 10)" "GIO,SPI"
|
|
bitfld.long 0x04 11. " SOMIDIR0 ,SPISOMI[0] pin direction" "GIO,SPI"
|
|
bitfld.long 0x04 10. " SIMODIR0 ,SPISIMO[0] pin direction" "GIO,SPI"
|
|
newline
|
|
bitfld.long 0x04 9. " CLKDIR ,SPI clock direction" "GIO,SPI"
|
|
bitfld.long 0x04 8. " ENADIR ,SPIENA direction" "GIO,SPI"
|
|
bitfld.long 0x04 7. " SCSDIR7 ,SPISCS7 direction 7" "GIO,SPI"
|
|
newline
|
|
bitfld.long 0x04 6. " SCSDIR6 ,SPISCS6 direction 6" "GIO,SPI"
|
|
bitfld.long 0x04 5. " SCSDIR5 ,SPISCS5 direction 5" "GIO,SPI"
|
|
bitfld.long 0x04 4. " SCSDIR4 ,SPISCS4 direction 4" "GIO,SPI"
|
|
newline
|
|
bitfld.long 0x04 3. " SCSDIR3 ,SPISCS3 direction 3" "GIO,SPI"
|
|
bitfld.long 0x04 2. " SCSDIR2 ,SPISCS2 direction 2" "GIO,SPI"
|
|
bitfld.long 0x04 1. " SCSDIR1 ,SPISCS1 direction 1" "GIO,SPI"
|
|
newline
|
|
bitfld.long 0x04 0. " SCSDIR0 ,SPISCS0 direction 0" "GIO,SPI"
|
|
line.long 0x08 "SPIPC2,SPI Pin Control Register 2"
|
|
bitfld.long 0x08 31. " SOMIDIN7 ,SPISOMI[7] data in" "0,1"
|
|
bitfld.long 0x08 30. " SOMIDIN6 ,SPISOMI[6] data in" "0,1"
|
|
bitfld.long 0x08 29. " SOMIDIN5 ,SPISOMI[5] data in" "0,1"
|
|
newline
|
|
bitfld.long 0x08 28. " SOMIDIN4 ,SPISOMI[4] data in" "0,1"
|
|
bitfld.long 0x08 27. " SOMIDIN3 ,SPISOMI[3] data in" "0,1"
|
|
bitfld.long 0x08 26. " SOMIDIN2 ,SPISOMI[2] data in" "0,1"
|
|
newline
|
|
bitfld.long 0x08 25. " SOMIDIN1 ,SPISOMI[1] data in" "0,1"
|
|
bitfld.long 0x08 24. " SOMIDIN0 ,SPISOMI[0] data in (mirror of bit 11)" "0,1"
|
|
bitfld.long 0x08 23. " SIMODIN7 ,SPISIMO[7] data in" "0,1"
|
|
newline
|
|
bitfld.long 0x08 22. " SIMODIN6 ,SPISIMO[6] data in" "0,1"
|
|
bitfld.long 0x08 21. " SIMODIN5 ,SPISIMO[5] data in" "0,1"
|
|
bitfld.long 0x08 20. " SIMODIN4 ,SPISIMO[4] data in" "0,1"
|
|
newline
|
|
bitfld.long 0x08 19. " SIMODIN3 ,SPISIMO[3] data in" "0,1"
|
|
bitfld.long 0x08 18. " SIMODIN2 ,SPISIMO[2] data in" "0,1"
|
|
bitfld.long 0x08 17. " SIMODIN1 ,SPISIMO[1] data in" "0,1"
|
|
newline
|
|
bitfld.long 0x08 16. " SIMODIN0 ,SPISIMO[0] data in (mirror of bit 10)" "0,1"
|
|
bitfld.long 0x08 11. " SOMIDIN0 ,SPISOMI[0] data in" "0,1"
|
|
bitfld.long 0x08 10. " SIMODIN0 ,SPISIMO[0] data in" "0,1"
|
|
newline
|
|
bitfld.long 0x08 9. " CLKDIN ,SPI clock data in" "0,1"
|
|
bitfld.long 0x08 8. " ENADIN ,SPIENA data in" "0,1"
|
|
bitfld.long 0x08 7. " SCSDIN7 ,SPISCS7 data in" "0,1"
|
|
newline
|
|
bitfld.long 0x08 6. " SCSDIN6 ,SPISCS6 data in" "0,1"
|
|
bitfld.long 0x08 5. " SCSDIN5 ,SPISCS5 data in" "0,1"
|
|
bitfld.long 0x08 4. " SCSDIN4 ,SPISCS4 data in" "0,1"
|
|
newline
|
|
bitfld.long 0x08 3. " SCSDIN3 ,SPISCS3 data in" "0,1"
|
|
bitfld.long 0x08 2. " SCSDIN2 ,SPISCS2 data in" "0,1"
|
|
bitfld.long 0x08 1. " SCSDIN1 ,SPISCS1 data in" "0,1"
|
|
newline
|
|
bitfld.long 0x08 0. " SCSDIN0 ,SPISCS0 direction 0" "0,1"
|
|
line.long 0x0C "SPIPC3,SPI Pin Control Register 3"
|
|
bitfld.long 0x0C 31. " SOMIDOUT7 ,SPISOMI[7] data out write" "0,1"
|
|
bitfld.long 0x0C 30. " SOMIDOUT6 ,SPISOMI[6] data out write" "0,1"
|
|
bitfld.long 0x0C 29. " SOMIDOUT5 ,SPISOMI[5] data out write" "0,1"
|
|
newline
|
|
bitfld.long 0x0C 28. " SOMIDOUT4 ,SPISOMI[4] data out write" "0,1"
|
|
bitfld.long 0x0C 27. " SOMIDOUT3 ,SPISOMI[3] data out write" "0,1"
|
|
bitfld.long 0x0C 26. " SOMIDOUT2 ,SPISOMI[2] data out write" "0,1"
|
|
newline
|
|
bitfld.long 0x0C 25. " SOMIDOUT1 ,SPISOMI[1] data out write" "0,1"
|
|
bitfld.long 0x0C 24. " SOMIDOUT0 ,SPISOMI[0] data out write (mirror of bit 11)" "0,1"
|
|
bitfld.long 0x0C 23. " SIMODOUT7 ,SPISIMO[7] data out write" "0,1"
|
|
newline
|
|
bitfld.long 0x0C 22. " SIMODOUT6 ,SPISIMO[6] data out write" "0,1"
|
|
bitfld.long 0x0C 21. " SIMODOUT5 ,SPISIMO[5] data out write" "0,1"
|
|
bitfld.long 0x0C 20. " SIMODOUT4 ,SPISIMO[4] data out write" "0,1"
|
|
newline
|
|
bitfld.long 0x0C 19. " SIMODOUT3 ,SPISIMO[3] data out write" "0,1"
|
|
bitfld.long 0x0C 18. " SIMODOUT2 ,SPISIMO[2] data out write" "0,1"
|
|
bitfld.long 0x0C 17. " SIMODOUT1 ,SPISIMO[1] data out write" "0,1"
|
|
newline
|
|
bitfld.long 0x0C 16. " SIMODOUT0 ,SPISIMO[0] data out write (mirror of bit 10)" "0,1"
|
|
bitfld.long 0x0C 11. " SOMIDOUT0 ,SPISOMI[0] data out write" "0,1"
|
|
bitfld.long 0x0C 10. " SIMODOUT0 ,SPISIMO[0] data out write" "0,1"
|
|
newline
|
|
bitfld.long 0x0C 9. " CLKDOUT ,SPI clock data out write" "0,1"
|
|
bitfld.long 0x0C 8. " ENADOUT ,SPIENA data out write" "0,1"
|
|
bitfld.long 0x0C 7. " SCSDOUT7 ,SPISCS7 data out write" "0,1"
|
|
newline
|
|
bitfld.long 0x0C 6. " SCSDOUT6 ,SPISCS6 data out write" "0,1"
|
|
bitfld.long 0x0C 5. " SCSDOUT5 ,SPISCS5 data out write" "0,1"
|
|
bitfld.long 0x0C 4. " SCSDOUT4 ,SPISCS4 data out write" "0,1"
|
|
newline
|
|
bitfld.long 0x0C 3. " SCSDOUT3 ,SPISCS3 data out write" "0,1"
|
|
bitfld.long 0x0C 2. " SCSDOUT2 ,SPISCS2 data out write" "0,1"
|
|
bitfld.long 0x0C 1. " SCSDOUT1 ,SPISCS1 data out write" "0,1"
|
|
newline
|
|
bitfld.long 0x0C 0. " SCSDOUT0 ,SPISCS0 data out write" "0,1"
|
|
line.long 0x10 "SPIPC4,SPI Pin Control Register 4"
|
|
bitfld.long 0x10 31. " SOMISET7 ,SPISOMI[7] data out set" "0,1"
|
|
bitfld.long 0x10 30. " SOMISET6 ,SPISOMI[6] data out set" "0,1"
|
|
bitfld.long 0x10 29. " SOMISET5 ,SPISOMI[5] data out set" "0,1"
|
|
newline
|
|
bitfld.long 0x10 28. " SOMISET4 ,SPISOMI[4] data out set" "0,1"
|
|
bitfld.long 0x10 27. " SOMISET3 ,SPISOMI[3] data out set" "0,1"
|
|
bitfld.long 0x10 26. " SOMISET2 ,SPISOMI[2] data out set" "0,1"
|
|
newline
|
|
bitfld.long 0x10 25. " SOMISET1 ,SPISOMI[1] data out set" "0,1"
|
|
bitfld.long 0x10 24. " SOMISET0 ,SPISOMI[0] data out set (mirror of bit 11)" "0,1"
|
|
bitfld.long 0x10 23. " SIMOSET7 ,SPISIMO[7] data out set" "0,1"
|
|
newline
|
|
bitfld.long 0x10 22. " SIMOSET6 ,SPISIMO[6] data out set" "0,1"
|
|
bitfld.long 0x10 21. " SIMOSET5 ,SPISIMO[5] data out set" "0,1"
|
|
bitfld.long 0x10 20. " SIMOSET4 ,SPISIMO[4] data out set" "0,1"
|
|
newline
|
|
bitfld.long 0x10 19. " SIMOSET3 ,SPISIMO[3] data out set" "0,1"
|
|
bitfld.long 0x10 18. " SIMOSET2 ,SPISIMO[2] data out set" "0,1"
|
|
bitfld.long 0x10 17. " SIMOSET1 ,SPISIMO[1] data out set" "0,1"
|
|
newline
|
|
bitfld.long 0x10 16. " SIMOSET0 ,SPISIMO[0] data out set (mirror of bit 10)" "0,1"
|
|
bitfld.long 0x10 11. " SOMISET0 ,SPISOMI[0] data out set" "0,1"
|
|
bitfld.long 0x10 10. " SIMOSET0 ,SPISIMO[0] data out set" "0,1"
|
|
newline
|
|
bitfld.long 0x10 9. " CLKSET ,SPI clock data out set" "0,1"
|
|
bitfld.long 0x10 8. " ENASET ,SPIENA data out set" "0,1"
|
|
bitfld.long 0x10 7. " SCSSET7 ,SPISCS7 data out set" "0,1"
|
|
newline
|
|
bitfld.long 0x10 6. " SCSSET6 ,SPISCS6 data out set" "0,1"
|
|
bitfld.long 0x10 5. " SCSSET5 ,SPISCS5 data out set" "0,1"
|
|
bitfld.long 0x10 4. " SCSSET4 ,SPISCS4 data out set" "0,1"
|
|
newline
|
|
bitfld.long 0x10 3. " SCSSET3 ,SPISCS3 data out set" "0,1"
|
|
bitfld.long 0x10 2. " SCSSET2 ,SPISCS2 data out set" "0,1"
|
|
bitfld.long 0x10 1. " SCSSET1 ,SPISCS1 data out set" "0,1"
|
|
newline
|
|
bitfld.long 0x10 0. " SCSSET0 ,SPISCS0 data out set" "0,1"
|
|
line.long 0x14 "SPIPC5,SPI Pin Control Register 5"
|
|
bitfld.long 0x14 31. " SOMICLR7 ,SPISOMI[7] data out clear" "0,1"
|
|
bitfld.long 0x14 30. " SOMICLR6 ,SPISOMI[6] data out clear" "0,1"
|
|
bitfld.long 0x14 29. " SOMICLR5 ,SPISOMI[5] data out clear" "0,1"
|
|
newline
|
|
bitfld.long 0x14 28. " SOMICLR4 ,SPISOMI[4] data out clear" "0,1"
|
|
bitfld.long 0x14 27. " SOMICLR3 ,SPISOMI[3] data out clear" "0,1"
|
|
bitfld.long 0x14 26. " SOMICLR2 ,SPISOMI[2] data out clear" "0,1"
|
|
newline
|
|
bitfld.long 0x14 25. " SOMICLR1 ,SPISOMI[1] data out clear" "0,1"
|
|
bitfld.long 0x14 24. " SOMICLR0 ,SPISOMI[0] data out clear (mirror of bit 11)" "0,1"
|
|
bitfld.long 0x14 23. " SIMOCLR7 ,SPISIMO[7] data out clear" "0,1"
|
|
newline
|
|
bitfld.long 0x14 22. " SIMOCLR6 ,SPISIMO[6] data out clear" "0,1"
|
|
bitfld.long 0x14 21. " SIMOCLR5 ,SPISIMO[5] data out clear" "0,1"
|
|
bitfld.long 0x14 20. " SIMOCLR4 ,SPISIMO[4] data out clear" "0,1"
|
|
newline
|
|
bitfld.long 0x14 19. " SIMOCLR3 ,SPISIMO[3] data out clear" "0,1"
|
|
bitfld.long 0x14 18. " SIMOCLR2 ,SPISIMO[2] data out clear" "0,1"
|
|
bitfld.long 0x14 17. " SIMOCLR1 ,SPISIMO[1] data out clear" "0,1"
|
|
newline
|
|
bitfld.long 0x14 16. " SIMOCLR0 ,SPISIMO[0] data out clear (mirror of bit 10)" "0,1"
|
|
bitfld.long 0x14 11. " SOMICLR0 ,SPISOMI[0] data out clear" "0,1"
|
|
bitfld.long 0x14 10. " SIMOCLR0 ,SPISIMO[0] data out clear" "0,1"
|
|
newline
|
|
bitfld.long 0x14 9. " CLKCLR ,SPI clock data out clear" "0,1"
|
|
bitfld.long 0x14 8. " ENACLR ,SPIENA data out clear" "0,1"
|
|
bitfld.long 0x14 7. " SCSCLR7 ,SPISCS7 data out clear" "0,1"
|
|
newline
|
|
bitfld.long 0x14 6. " SCSCLR6 ,SPISCS6 data out clear" "0,1"
|
|
bitfld.long 0x14 5. " SCSCLR5 ,SPISCS5 data out clear" "0,1"
|
|
bitfld.long 0x14 4. " SCSCLR4 ,SPISCS4 data out clear" "0,1"
|
|
newline
|
|
bitfld.long 0x14 3. " SCSCLR3 ,SPISCS3 data out clear" "0,1"
|
|
bitfld.long 0x14 2. " SCSCLR2 ,SPISCS2 data out clear" "0,1"
|
|
bitfld.long 0x14 1. " SCSCLR1 ,SPISCS1 data out clear" "0,1"
|
|
newline
|
|
bitfld.long 0x14 0. " SCSCLR0 ,SPISCS0 data out clear" "0,1"
|
|
line.long 0x18 "SPIPC6,SPI Pin Control Register 6"
|
|
bitfld.long 0x18 31. " SOMIPDR7 ,SPISOMI[7] open drain enable" "Disabled,Enabled"
|
|
bitfld.long 0x18 30. " SOMIPDR6 ,SPISOMI[6] open drain enable" "Disabled,Enabled"
|
|
bitfld.long 0x18 29. " SOMIPDR5 ,SPISOMI[5] open drain enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x18 28. " SOMIPDR4 ,SPISOMI[4] open drain enable" "Disabled,Enabled"
|
|
bitfld.long 0x18 27. " SOMIPDR3 ,SPISOMI[3] open drain enable" "Disabled,Enabled"
|
|
bitfld.long 0x18 26. " SOMIPDR2 ,SPISOMI[2] open drain enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x18 25. " SOMIPDR1 ,SPISOMI[1] open drain enable" "Disabled,Enabled"
|
|
bitfld.long 0x18 24. " SOMIPDR0 ,SPISOMI[0] open drain enable (mirror of bit 11)" "Disabled,Enabled"
|
|
bitfld.long 0x18 23. " SIMOPDR7 ,SPISIMO[7] open drain enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x18 22. " SIMOPDR6 ,SPISIMO[6] open drain enable" "Disabled,Enabled"
|
|
bitfld.long 0x18 21. " SIMOPDR5 ,SPISIMO[5] open drain enable" "Disabled,Enabled"
|
|
bitfld.long 0x18 20. " SIMOPDR4 ,SPISIMO[4] open drain enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x18 19. " SIMOPDR3 ,SPISIMO[3] open drain enable" "Disabled,Enabled"
|
|
bitfld.long 0x18 18. " SIMOPDR2 ,SPISIMO[2] open drain enable" "Disabled,Enabled"
|
|
bitfld.long 0x18 17. " SIMOPDR1 ,SPISIMO[1] open drain enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x18 16. " SIMOPDR0 ,SPISIMO[0] open drain enable (mirror of bit 10)" "Disabled,Enabled"
|
|
bitfld.long 0x18 11. " SOMIPDR0 ,SPISOMI[0] open drain enable" "Disabled,Enabled"
|
|
bitfld.long 0x18 10. " SIMOPDR0 ,SPISIMO[0] open drain enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x18 9. " CLKPDR ,SPI clock open drain enable" "Disabled,Enabled"
|
|
bitfld.long 0x18 8. " ENAPDR ,SPIENA open drain enable" "Disabled,Enabled"
|
|
bitfld.long 0x18 7. " SCSPDR7 ,SPISCS7 open drain enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x18 6. " SCSPDR6 ,SPISCS6 open drain enable" "Disabled,Enabled"
|
|
bitfld.long 0x18 5. " SCSPDR5 ,SPISCS5 open drain enable" "Disabled,Enabled"
|
|
bitfld.long 0x18 4. " SCSPDR4 ,SPISCS4 open drain enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x18 3. " SCSPDR3 ,SPISCS3 open drain enable" "Disabled,Enabled"
|
|
bitfld.long 0x18 2. " SCSPDR2 ,SPISCS2 open drain enable" "Disabled,Enabled"
|
|
bitfld.long 0x18 1. " SCSPDR1 ,SPISCS1 open drain enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x18 0. " SCSPDR0 ,SPISCS0 open drain enable" "Disabled,Enabled"
|
|
line.long 0x1C "SPIPC7,SPI Pin Control Register 7"
|
|
bitfld.long 0x1C 31. " SOMIPDIS7 ,SPISOMI[7] pull control enable/disable" "No,Yes"
|
|
bitfld.long 0x1C 30. " SOMIPDIS6 ,SPISOMI[6] pull control enable/disable" "No,Yes"
|
|
bitfld.long 0x1C 29. " SOMIPDIS5 ,SPISOMI[5] pull control enable/disable" "No,Yes"
|
|
newline
|
|
bitfld.long 0x1C 28. " SOMIPDIS4 ,SPISOMI[4] pull control enable/disable" "No,Yes"
|
|
bitfld.long 0x1C 27. " SOMIPDIS3 ,SPISOMI[3] pull control enable/disable" "No,Yes"
|
|
bitfld.long 0x1C 26. " SOMIPDIS2 ,SPISOMI[2] pull control enable/disable" "No,Yes"
|
|
newline
|
|
bitfld.long 0x1C 25. " SOMIPDIS1 ,SPISOMI[1] pull control enable/disable" "No,Yes"
|
|
bitfld.long 0x1C 24. " SOMIPDIS0 ,SPISOMI[0] pull control enable/disable (mirror of bit 11)" "No,Yes"
|
|
bitfld.long 0x1C 23. " SIMOPDIS7 ,SPISIMO[7] pull control enable/disable" "No,Yes"
|
|
newline
|
|
bitfld.long 0x1C 22. " SIMOPDIS6 ,SPISIMO[6] pull control enable/disable" "No,Yes"
|
|
bitfld.long 0x1C 21. " SIMOPDIS5 ,SPISIMO[5] pull control enable/disable" "No,Yes"
|
|
bitfld.long 0x1C 20. " SIMOPDIS4 ,SPISIMO[4] pull control enable/disable" "No,Yes"
|
|
newline
|
|
bitfld.long 0x1C 19. " SIMOPDIS3 ,SPISIMO[3] pull control enable/disable" "No,Yes"
|
|
bitfld.long 0x1C 18. " SIMOPDIS2 ,SPISIMO[2] pull control enable/disable" "No,Yes"
|
|
bitfld.long 0x1C 17. " SIMOPDIS1 ,SPISIMO[1] pull control enable/disable" "No,Yes"
|
|
newline
|
|
bitfld.long 0x1C 16. " SIMOPDIS0 ,SPISIMO[0] pull control enable/disable (mirror of bit 10)" "No,Yes"
|
|
bitfld.long 0x1C 11. " SOMIPDIS0 ,SPISOMI[0] pull control enable/disable" "No,Yes"
|
|
bitfld.long 0x1C 10. " SIMOPDIS0 ,SPISIMO[0] pull control enable/disable" "No,Yes"
|
|
newline
|
|
bitfld.long 0x1C 9. " CLKPDIS ,SPI clock pull control enable/disable" "No,Yes"
|
|
bitfld.long 0x1C 8. " ENAPDIS ,SPIENA pull control enable/disable" "No,Yes"
|
|
bitfld.long 0x1C 7. " SCSPDIS7 ,SPISCS7 pull control enable/disable" "No,Yes"
|
|
newline
|
|
bitfld.long 0x1C 6. " SCSPDIS6 ,SPISCS6 pull control enable/disable" "No,Yes"
|
|
bitfld.long 0x1C 5. " SCSPDIS5 ,SPISCS5 pull control enable/disable" "No,Yes"
|
|
bitfld.long 0x1C 4. " SCSPDIS4 ,SPISCS4 pull control enable/disable" "No,Yes"
|
|
newline
|
|
bitfld.long 0x1C 3. " SCSPDIS3 ,SPISCS3 pull control enable/disable" "No,Yes"
|
|
bitfld.long 0x1C 2. " SCSPDIS2 ,SPISCS2 pull control enable/disable" "No,Yes"
|
|
bitfld.long 0x1C 1. " SCSPDIS1 ,SPISCS1 pull control enable/disable" "No,Yes"
|
|
newline
|
|
bitfld.long 0x1C 0. " SCSPDIS0 ,SPISCS0 pull control enable/disable" "No,Yes"
|
|
line.long 0x20 "SPIPC8,SPI Pin Control Register 8"
|
|
bitfld.long 0x20 31. " SOMIPSEL7 ,SPISOMI[7] pull select" "Pull down,Pull up"
|
|
bitfld.long 0x20 30. " SOMIPSEL6 ,SPISOMI[6] pull select" "Pull down,Pull up"
|
|
bitfld.long 0x20 29. " SOMIPSEL5 ,SPISOMI[5] pull select" "Pull down,Pull up"
|
|
newline
|
|
bitfld.long 0x20 28. " SOMIPSEL4 ,SPISOMI[4] pull select" "Pull down,Pull up"
|
|
bitfld.long 0x20 27. " SOMIPSEL3 ,SPISOMI[3] pull select" "Pull down,Pull up"
|
|
bitfld.long 0x20 26. " SOMIPSEL2 ,SPISOMI[2] pull select" "Pull down,Pull up"
|
|
newline
|
|
bitfld.long 0x20 25. " SOMIPSEL1 ,SPISOMI[1] pull select" "Pull down,Pull up"
|
|
bitfld.long 0x20 24. " SOMIPSEL0 ,SPISOMI[0] pull select (mirror of bit 11)" "Pull down,Pull up"
|
|
bitfld.long 0x20 23. " SIMOPSEL7 ,SPISIMO[7] pull select" "Pull down,Pull up"
|
|
newline
|
|
bitfld.long 0x20 22. " SIMOPSEL6 ,SPISIMO[6] pull select" "Pull down,Pull up"
|
|
bitfld.long 0x20 21. " SIMOPSEL5 ,SPISIMO[5] pull select" "Pull down,Pull up"
|
|
bitfld.long 0x20 20. " SIMOPSEL4 ,SPISIMO[4] pull select" "Pull down,Pull up"
|
|
newline
|
|
bitfld.long 0x20 19. " SIMOPSEL3 ,SPISIMO[3] pull select" "Pull down,Pull up"
|
|
bitfld.long 0x20 18. " SIMOPSEL2 ,SPISIMO[2] pull select" "Pull down,Pull up"
|
|
bitfld.long 0x20 17. " SIMOPSEL1 ,SPISIMO[1] pull select" "Pull down,Pull up"
|
|
newline
|
|
bitfld.long 0x20 16. " SIMOPSEL0 ,SPISIMO[0] pull select (mirror of bit 10)" "Pull down,Pull up"
|
|
bitfld.long 0x20 11. " SOMIPSEL0 ,SPISOMI[0] pull select" "Pull down,Pull up"
|
|
bitfld.long 0x20 10. " SIMOPSEL0 ,SPISIMO[0] pull select" "Pull down,Pull up"
|
|
newline
|
|
bitfld.long 0x20 9. " CLKPSEL ,SPI clock pull select" "Pull down,Pull up"
|
|
bitfld.long 0x20 8. " ENAPSEL ,SPIENA pull select" "Pull down,Pull up"
|
|
bitfld.long 0x20 7. " SCSPSEL7 ,SPISCS7 pull select" "Pull down,Pull up"
|
|
newline
|
|
bitfld.long 0x20 6. " SCSPSEL6 ,SPISCS6 pull select" "Pull down,Pull up"
|
|
bitfld.long 0x20 5. " SCSPSEL5 ,SPISCS5 pull select" "Pull down,Pull up"
|
|
bitfld.long 0x20 4. " SCSPSEL4 ,SPISCS4 pull select" "Pull down,Pull up"
|
|
newline
|
|
bitfld.long 0x20 3. " SCSPSEL3 ,SPISCS3 pull select" "Pull down,Pull up"
|
|
bitfld.long 0x20 2. " SCSPSEL2 ,SPISCS2 pull select" "Pull down,Pull up"
|
|
bitfld.long 0x20 1. " SCSPSEL1 ,SPISCS1 pull select" "Pull down,Pull up"
|
|
newline
|
|
bitfld.long 0x20 0. " SCSPSEL0 ,SPISCS0 pull select" "Pull down,Pull up"
|
|
group.long 0x38++0x07
|
|
line.long 0x00 "SPIDAT0,SPI Transmit Data Register 0"
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,SPI transmit data"
|
|
line.long 0x04 "SPIDAT1,Transmit Data Register 1"
|
|
bitfld.long 0x04 28. " CSHOLD ,Chip select hold mode" "Inactive,Active"
|
|
bitfld.long 0x04 26. " WDEL ,Enable the delay counter at the end of the current transaction" "No delay,After transaction"
|
|
bitfld.long 0x04 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
newline
|
|
hexmask.long.byte 0x04 16.--23. 1. " CSNR ,Chip select number"
|
|
hexmask.long.word 0x04 0.--15. 1. " TXDATA ,Transfer data"
|
|
hgroup.long 0x40++0x03
|
|
hide.long 0x00 "SPIBUF,SPI Receive Buffer Register"
|
|
in
|
|
rgroup.long 0x44++0x03
|
|
line.long 0x00 "SPIEMU,SPI Emulation Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " EMU_RXDATA ,SPI receive data"
|
|
sif cpuis("TMS570LS0232")||cpuis("TMS570LS0714*")||cpuis("TMS570LS0914*")
|
|
group.long 0x48++0x03
|
|
line.long 0x00 "SPIDELAY,SPI Delay Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " C2TDELAY ,Chip-select-active to transmit-start delay"
|
|
hexmask.long.byte 0x00 16.--23. 1. " T2CDELAY ,Transmit-end-to-chip-select-inactive-delay"
|
|
hexmask.long.byte 0x00 8.--15. 1. " T2EDELAY ,Transmit-data-finished to ENA-pin-inactive time-out"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--7. 1. " C2EDELAY ,Chip-select-active to ENA-signal-active time-out"
|
|
else
|
|
rgroup.long 0x48++0x03
|
|
line.long 0x00 "SPIDELAY,SPI Delay Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " C2TDELAY ,Chip-select-active to transmit-start delay"
|
|
hexmask.long.byte 0x00 16.--23. 1. " T2CDELAY ,Transmit-end-to-chip-select-inactive-delay"
|
|
hexmask.long.byte 0x00 8.--15. 1. " T2EDELAY ,Transmit-data-finished to ENA-pin-inactive time-out"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--7. 1. " C2EDELAY ,Chip-select-active to ENA-signal-active time-out"
|
|
endif
|
|
group.long 0x4C++0x13
|
|
line.long 0x00 "SPIDEF,SPI Default Chip Select Register"
|
|
bitfld.long 0x00 7. " CSDEF7 ,Chip select default pattern 7" "0,1"
|
|
bitfld.long 0x00 6. " CSDEF6 ,Chip select default pattern 6" "0,1"
|
|
bitfld.long 0x00 5. " CSDEF5 ,Chip select default pattern 5" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. " CSDEF4 ,Chip select default pattern 4" "0,1"
|
|
bitfld.long 0x00 3. " CSDEF3 ,Chip select default pattern 3" "0,1"
|
|
bitfld.long 0x00 2. " CSDEF2 ,Chip select default pattern 2" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. " CSDEF1 ,Chip select default pattern 1" "0,1"
|
|
bitfld.long 0x00 0. " CSDEF0 ,Chip select default pattern 0" "0,1"
|
|
line.long 0x4 "SPIFMT0,SPI Data Format Register 0"
|
|
sif (cpuis("TMS570LS0332")||cpuis("TMS570LS0432")||cpuis("TMS570LS1114*")||cpuis("TMS570LS1115*")||cpuis("TMS570LS1224*")||cpuis("TMS570LS1225*")||cpuis("TMS570LS1227*")||cpuis("TMS570LS0232")||cpuis("TMS570LS0714*")||cpuis("TMS570LS0914*"))
|
|
hexmask.long.byte 0x4 24.--31. 1. " WDELAY ,Delay in between transmissions for data format 0"
|
|
else
|
|
bitfld.long 0x4 24.--29. " WDELAY ,Delay in between transmissions for data format 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
endif
|
|
bitfld.long 0x4 23. " PARPOL ,Parity polarity: even or odd" "Even,Odd"
|
|
newline
|
|
bitfld.long 0x4 22. " PARITYENA ,Parity enable for data format 0" "Disabled,Enabled"
|
|
bitfld.long 0x4 21. " WAITENA ,The master waits for the ENA signal from slave for data format 0" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x4 20. " SHIFTDIR ,Shift direction for data format $" "MSB,LSB"
|
|
sif (cpu()==("TMS570LS0332")||cpu()==("TMS570LS0432")||cpuis("TMS570LS1114*")||cpuis("TMS570LS1115*")||cpuis("TMS570LS1224*")||cpuis("TMS570LS1225*")||cpuis("TMS570LS1227*")||cpuis("TMS570LS0232")||cpuis("TMS570LS0714*")||cpuis("TMS570LS0914*"))
|
|
bitfld.long 0x4 19. " HDUPLEX_ENA0 ,Half Duplex transfer mode enable for Data Format 0" "Normal,RX/TX"
|
|
endif
|
|
newline
|
|
bitfld.long 0x4 18. " DISCSTIMERS ,Disable chip-select timers for this format" "No,Yes"
|
|
newline
|
|
bitfld.long 0x4 17. " POLARITY ,SPI data format 0 clock polarity" "Low,High"
|
|
bitfld.long 0x4 16. " PHASE ,SPI data format 0 clock delay" "Disabled,Enabled"
|
|
newline
|
|
hexmask.long.byte 0x4 8.--15. 1. " PRESCALE ,SPI data format 0 prescaler"
|
|
bitfld.long 0x4 0.--4. " CHARLEN ,SPI data format 0 data-word length" ",,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,?..."
|
|
line.long 0x8 "SPIFMT1,SPI Data Format Register 1"
|
|
sif (cpuis("TMS570LS0332")||cpuis("TMS570LS0432")||cpuis("TMS570LS1114*")||cpuis("TMS570LS1115*")||cpuis("TMS570LS1224*")||cpuis("TMS570LS1225*")||cpuis("TMS570LS1227*")||cpuis("TMS570LS0232")||cpuis("TMS570LS0714*")||cpuis("TMS570LS0914*"))
|
|
hexmask.long.byte 0x8 24.--31. 1. " WDELAY ,Delay in between transmissions for data format 1"
|
|
else
|
|
bitfld.long 0x8 24.--29. " WDELAY ,Delay in between transmissions for data format 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
endif
|
|
bitfld.long 0x8 23. " PARPOL ,Parity polarity: even or odd" "Even,Odd"
|
|
newline
|
|
bitfld.long 0x8 22. " PARITYENA ,Parity enable for data format 1" "Disabled,Enabled"
|
|
bitfld.long 0x8 21. " WAITENA ,The master waits for the ENA signal from slave for data format 1" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x8 20. " SHIFTDIR ,Shift direction for data format $" "MSB,LSB"
|
|
sif (cpu()==("TMS570LS0332")||cpu()==("TMS570LS0432")||cpuis("TMS570LS1114*")||cpuis("TMS570LS1115*")||cpuis("TMS570LS1224*")||cpuis("TMS570LS1225*")||cpuis("TMS570LS1227*")||cpuis("TMS570LS0232")||cpuis("TMS570LS0714*")||cpuis("TMS570LS0914*"))
|
|
bitfld.long 0x8 19. " HDUPLEX_ENA1 ,Half Duplex transfer mode enable for Data Format 1" "Normal,RX/TX"
|
|
endif
|
|
newline
|
|
bitfld.long 0x8 18. " DISCSTIMERS ,Disable chip-select timers for this format" "No,Yes"
|
|
newline
|
|
bitfld.long 0x8 17. " POLARITY ,SPI data format 1 clock polarity" "Low,High"
|
|
bitfld.long 0x8 16. " PHASE ,SPI data format 1 clock delay" "Disabled,Enabled"
|
|
newline
|
|
hexmask.long.byte 0x8 8.--15. 1. " PRESCALE ,SPI data format 1 prescaler"
|
|
bitfld.long 0x8 0.--4. " CHARLEN ,SPI data format 1 data-word length" ",,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,?..."
|
|
line.long 0xC "SPIFMT2,SPI Data Format Register 2"
|
|
sif (cpuis("TMS570LS0332")||cpuis("TMS570LS0432")||cpuis("TMS570LS1114*")||cpuis("TMS570LS1115*")||cpuis("TMS570LS1224*")||cpuis("TMS570LS1225*")||cpuis("TMS570LS1227*")||cpuis("TMS570LS0232")||cpuis("TMS570LS0714*")||cpuis("TMS570LS0914*"))
|
|
hexmask.long.byte 0xC 24.--31. 1. " WDELAY ,Delay in between transmissions for data format 2"
|
|
else
|
|
bitfld.long 0xC 24.--29. " WDELAY ,Delay in between transmissions for data format 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
endif
|
|
bitfld.long 0xC 23. " PARPOL ,Parity polarity: even or odd" "Even,Odd"
|
|
newline
|
|
bitfld.long 0xC 22. " PARITYENA ,Parity enable for data format 2" "Disabled,Enabled"
|
|
bitfld.long 0xC 21. " WAITENA ,The master waits for the ENA signal from slave for data format 2" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0xC 20. " SHIFTDIR ,Shift direction for data format $" "MSB,LSB"
|
|
sif (cpu()==("TMS570LS0332")||cpu()==("TMS570LS0432")||cpuis("TMS570LS1114*")||cpuis("TMS570LS1115*")||cpuis("TMS570LS1224*")||cpuis("TMS570LS1225*")||cpuis("TMS570LS1227*")||cpuis("TMS570LS0232")||cpuis("TMS570LS0714*")||cpuis("TMS570LS0914*"))
|
|
bitfld.long 0xC 19. " HDUPLEX_ENA2 ,Half Duplex transfer mode enable for Data Format 2" "Normal,RX/TX"
|
|
endif
|
|
newline
|
|
bitfld.long 0xC 18. " DISCSTIMERS ,Disable chip-select timers for this format" "No,Yes"
|
|
newline
|
|
bitfld.long 0xC 17. " POLARITY ,SPI data format 2 clock polarity" "Low,High"
|
|
bitfld.long 0xC 16. " PHASE ,SPI data format 2 clock delay" "Disabled,Enabled"
|
|
newline
|
|
hexmask.long.byte 0xC 8.--15. 1. " PRESCALE ,SPI data format 2 prescaler"
|
|
bitfld.long 0xC 0.--4. " CHARLEN ,SPI data format 2 data-word length" ",,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,?..."
|
|
line.long 0x10 "SPIFMT3,SPI Data Format Register 3"
|
|
sif (cpuis("TMS570LS0332")||cpuis("TMS570LS0432")||cpuis("TMS570LS1114*")||cpuis("TMS570LS1115*")||cpuis("TMS570LS1224*")||cpuis("TMS570LS1225*")||cpuis("TMS570LS1227*")||cpuis("TMS570LS0232")||cpuis("TMS570LS0714*")||cpuis("TMS570LS0914*"))
|
|
hexmask.long.byte 0x10 24.--31. 1. " WDELAY ,Delay in between transmissions for data format 3"
|
|
else
|
|
bitfld.long 0x10 24.--29. " WDELAY ,Delay in between transmissions for data format 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
endif
|
|
bitfld.long 0x10 23. " PARPOL ,Parity polarity: even or odd" "Even,Odd"
|
|
newline
|
|
bitfld.long 0x10 22. " PARITYENA ,Parity enable for data format 3" "Disabled,Enabled"
|
|
bitfld.long 0x10 21. " WAITENA ,The master waits for the ENA signal from slave for data format 3" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x10 20. " SHIFTDIR ,Shift direction for data format $" "MSB,LSB"
|
|
sif (cpu()==("TMS570LS0332")||cpu()==("TMS570LS0432")||cpuis("TMS570LS1114*")||cpuis("TMS570LS1115*")||cpuis("TMS570LS1224*")||cpuis("TMS570LS1225*")||cpuis("TMS570LS1227*")||cpuis("TMS570LS0232")||cpuis("TMS570LS0714*")||cpuis("TMS570LS0914*"))
|
|
bitfld.long 0x10 19. " HDUPLEX_ENA3 ,Half Duplex transfer mode enable for Data Format 3" "Normal,RX/TX"
|
|
endif
|
|
newline
|
|
bitfld.long 0x10 18. " DISCSTIMERS ,Disable chip-select timers for this format" "No,Yes"
|
|
newline
|
|
bitfld.long 0x10 17. " POLARITY ,SPI data format 3 clock polarity" "Low,High"
|
|
bitfld.long 0x10 16. " PHASE ,SPI data format 3 clock delay" "Disabled,Enabled"
|
|
newline
|
|
hexmask.long.byte 0x10 8.--15. 1. " PRESCALE ,SPI data format 3 prescaler"
|
|
bitfld.long 0x10 0.--4. " CHARLEN ,SPI data format 3 data-word length" ",,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,?..."
|
|
hgroup.long 0x60++0x03
|
|
hide.long 0x00 "TGINTVECT0,SPI Interrupt Vector Register 0 / MibSPI Transfer Group Interrupt Vector Register 0"
|
|
in
|
|
hgroup.long 0x64++0x03
|
|
hide.long 0x00 "TGINTVECT1,SPI Interrupt Vector Register 1 / MibSPI Transfer Group Interrupt Vector Register 1"
|
|
in
|
|
sif (cpu()!=("TMS570LS0332")&&cpu()!=("TMS570LS0432")&&!cpuis("TMS570LS0232"))
|
|
group.long 0x6C++0x07
|
|
line.long 0x00 "SPIPMCTRL,SPI Parallel/Modulo Mode Control Register"
|
|
bitfld.long 0x00 29. " MODCLKPOL3 ,Modulo mode SPICLK polarity" "Normal,Inverted"
|
|
bitfld.long 0x00 26.--28. " MMODE3 ,SPI/MibSPI data lines " "1,2,3,4,5,6,?..."
|
|
bitfld.long 0x00 24.--25. " PMODE3 ,Parallel mode data lines" "1,2,4,8"
|
|
newline
|
|
bitfld.long 0x00 21. " MODCLKPOL2 ,Modulo mode SPICLK polarity" "Normal,Inverted"
|
|
bitfld.long 0x00 18.--20. " MMODE2 ,SPI/MibSPI data lines " "1,2,3,4,5,6,?..."
|
|
bitfld.long 0x00 16.--17. " PMODE2 ,Parallel mode data lines" "1,2,4,8"
|
|
newline
|
|
bitfld.long 0x00 13. " MODCLKPOL1 ,Modulo mode SPICLK polarity" "Normal,Inverted"
|
|
bitfld.long 0x00 10.--12. " MMODE1 ,SPI/MibSPI data lines " "1,2,3,4,5,6,?..."
|
|
bitfld.long 0x00 8.--9. " PMODE1 ,Parallel mode data lines" "1,2,4,8"
|
|
newline
|
|
bitfld.long 0x00 5. " MODCLKPOL0 ,Modulo mode SPICLK polarity" "Normal,Inverted"
|
|
bitfld.long 0x00 2.--4. " MMODE0 ,SPI/MibSPI data lines " "1,2,3,4,5,6,?..."
|
|
bitfld.long 0x00 0.--1. " PMODE0 ,Parallel mode data lines" "1,2,4,8"
|
|
line.long 0x04 "MIBSPIE,MibSPI Enable Register"
|
|
bitfld.long 0x04 16. " RXRAMACCESS ,Receive-RAM access control" "Not writable,Accessible"
|
|
bitfld.long 0x04 0. " MIBSPIENA ,Multi-buffer mode enable" "Disabled,Enabled"
|
|
elif cpuis("TMS570LS0332")||cpuis("TMS570LS0432")||cpuis("TMS570LS0714*")||cpuis("TMS570LS0914*")||cpuis("TMS570LS0232")
|
|
group.long 0x70++0x03
|
|
line.long 0x00 "MIBSPIE,MibSPI Enable Register"
|
|
bitfld.long 0x00 16. " RXRAMACCESS ,Receive-RAM access control" "Not writable,Accessible"
|
|
bitfld.long 0x00 0. " MIBSPIENA ,Multi-buffer mode enable" "Disabled,Enabled"
|
|
endif
|
|
group.long 0x74++0x0F
|
|
line.long 0x00 "TGITENST,MibSPI Transfer Group Interrupt Enable Set Register"
|
|
bitfld.long 0x00 31. " SETINTENRDY15 ,TG interrupt set (enable) when transfer finished" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " SETINTENRDY14 ,TG interrupt set (enable) when transfer finished" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " SETINTENRDY13 ,TG interrupt set (enable) when transfer finished" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 28. " SETINTENRDY12 ,TG interrupt set (enable) when transfer finished" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " SETINTENRDY11 ,TG interrupt set (enable) when transfer finished" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " SETINTENRDY10 ,TG interrupt set (enable) when transfer finished" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 25. " SETINTENRDY9 ,TG interrupt set (enable) when transfer finished" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " SETINTENRDY8 ,TG interrupt set (enable) when transfer finished" "Disabled,Enabled"
|
|
bitfld.long 0x00 23. " SETINTENRDY7 ,TG interrupt set (enable) when transfer finished" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 22. " SETINTENRDY6 ,TG interrupt set (enable) when transfer finished" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " SETINTENRDY5 ,TG interrupt set (enable) when transfer finished" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " SETINTENRDY4 ,SETTG interrupt set (enable) when transfer finished" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 19. " SETINTENRDY3 ,TG interrupt set (enable) when transfer finished" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SETINTENRDY2 ,TG interrupt set (enable) when transfer finished" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SETINTENRDY1 ,TG interrupt set (enable) when transfer finished" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 16. " SETINTENRDY0 ,TG interrupt set (enable) when transfer finished" "Disabled,Enabled"
|
|
bitfld.long 0x00 15. " SETINTENSUS15 ,TG interrupt set (enabled) when transfer suspended" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " SETINTENSUS14 ,TG interrupt set (enabled) when transfer suspended" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 13. " SETINTENSUS13 ,TG interrupt set (enabled) when transfer suspended" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " SETINTENSUS12 ,TG interrupt set (enabled) when transfer suspended" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " SETINTENSUS11 ,TG interrupt set (enabled) when transfer suspended" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 10. " SETINTENSUS10 ,TG interrupt set (enabled) when transfer suspended" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " SETINTENSUS9 ,TG interrupt set (enabled) when transfer suspended" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " SETINTENSUS8 ,TG interrupt set (enabled) when transfer suspended" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 7. " SETINTENSUS7 ,TG interrupt set (enabled) when transfer suspended" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " SETINTENSUS6 ,TG interrupt set (enabled) when transfer suspended" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " SETINTENSUS5 ,TG interrupt set (enabled) when transfer suspended" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 4. " SETINTENSUS4 ,TG interrupt set (enabled) when transfer suspended" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " SETINTENSUS3 ,TG interrupt set (enabled) when transfer suspended" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " SETINTENSUS2 ,TG interrupt set (enabled) when transfer suspended" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 1. " SETINTENSUS1 ,TG interrupt set (enabled) when transfer suspended" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SETINTENSUS0 ,TG interrupt set (enabled) when transfer suspended" "Disabled,Enabled"
|
|
line.long 0x04 "TGITENCR,MibSPI Transfer Group Interrupt Enable Clear Register"
|
|
bitfld.long 0x04 31. " CLRINTENRDY15 ,TG interrupt clear (disabled) when transfer finished" "Disabled,Enabled"
|
|
bitfld.long 0x04 30. " CLRINTENRDY14 ,TG interrupt clear (disabled) when transfer finished" "Disabled,Enabled"
|
|
bitfld.long 0x04 29. " CLRINTENRDY13 ,TG interrupt clear (disabled) when transfer finished" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x04 28. " CLRINTENRDY12 ,TG interrupt clear (disabled) when transfer finished" "Disabled,Enabled"
|
|
bitfld.long 0x04 27. " CLRINTENRDY11 ,TG interrupt clear (disabled) when transfer finished" "Disabled,Enabled"
|
|
bitfld.long 0x04 26. " CLRINTENRDY10 ,TG interrupt clear (disabled) when transfer finished" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x04 25. " CLRINTENRDY9 ,TG interrupt clear (disabled) when transfer finished" "Disabled,Enabled"
|
|
bitfld.long 0x04 24. " CLRINTENRDY8 ,TG interrupt clear (disabled) when transfer finished" "Disabled,Enabled"
|
|
bitfld.long 0x04 23. " CLRINTENRDY7 ,TG interrupt clear (disabled) when transfer finished" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x04 22. " CLRINTENRDY6 ,TG interrupt clear (disabled) when transfer finished" "Disabled,Enabled"
|
|
bitfld.long 0x04 21. " CLRINTENRDY5 ,TG interrupt clear (disabled) when transfer finished" "Disabled,Enabled"
|
|
bitfld.long 0x04 20. " CLRINTENRDY4 ,TG interrupt clear (disabled) when transfer finished" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x04 19. " CLRINTENRDY3 ,TG interrupt clear (disabled) when transfer finished" "Disabled,Enabled"
|
|
bitfld.long 0x04 18. " CLRINTENRDY2 ,TG interrupt clear (disabled) when transfer finished" "Disabled,Enabled"
|
|
bitfld.long 0x04 17. " CLRINTENRDY1 ,TG interrupt clear (disabled) when transfer finished" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x04 16. " CLRINTENRDY0 ,TG interrupt clear (disabled) when transfer finished" "Disabled,Enabled"
|
|
bitfld.long 0x04 15. " CLRINTENSUS15 ,TG interrupt clear (disabled) when transfer suspended" "Disabled,Enabled"
|
|
bitfld.long 0x04 14. " CLRINTENSUS14 ,TG interrupt clear (disabled) when transfer suspended" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x04 13. " CLRINTENSUS13 ,TG interrupt clear (disabled) when transfer suspended" "Disabled,Enabled"
|
|
bitfld.long 0x04 12. " CLRINTENSUS12 ,TG interrupt clear (disabled) when transfer suspended" "Disabled,Enabled"
|
|
bitfld.long 0x04 11. " CLRINTENSUS11 ,TG interrupt clear (disabled) when transfer suspended" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x04 10. " CLRINTENSUS10 ,TG interrupt clear (disabled) when transfer suspended" "Disabled,Enabled"
|
|
bitfld.long 0x04 9. " CLRINTENSUS9 ,TG interrupt clear (disabled) when transfer suspended" "Disabled,Enabled"
|
|
bitfld.long 0x04 8. " CLRINTENSUS8 ,TG interrupt clear (disabled) when transfer suspended" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x04 7. " CLRINTENSUS7 ,TG interrupt clear (disabled) when transfer suspended" "Disabled,Enabled"
|
|
bitfld.long 0x04 6. " CLRINTENSUS6 ,TG interrupt clear (disabled) when transfer suspended" "Disabled,Enabled"
|
|
bitfld.long 0x04 5. " CLRINTENSUS5 ,TG interrupt clear (disabled) when transfer suspended" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x04 4. " CLRINTENSUS4 ,TG interrupt clear (disabled) when transfer suspended" "Disabled,Enabled"
|
|
bitfld.long 0x04 3. " CLRINTENSUS3 ,TG interrupt clear (disabled) when transfer suspended" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " CLRINTENSUS2 ,TG interrupt clear (disabled) when transfer suspended" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x04 1. " CLRINTENSUS1 ,TG interrupt clear (disabled) when transfer suspended" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " CLRINTENSUS0 ,TG interrupt clear (disabled) when transfer suspended" "Disabled,Enabled"
|
|
line.long 0x08 "TGITLVST,MibSPI Transfer Group Interrupt Level Set Register"
|
|
bitfld.long 0x08 31. " SETINTLVLRDY15 ,Transfer-group completed interrupt level set" "INT0,INT1"
|
|
bitfld.long 0x08 30. " SETINTLVLRDY14 ,Transfer-group completed interrupt level set" "INT0,INT1"
|
|
bitfld.long 0x08 29. " SETINTLVLRDY13 ,Transfer-group completed interrupt level set" "INT0,INT1"
|
|
newline
|
|
bitfld.long 0x08 28. " SETINTLVLRDY12 ,Transfer-group completed interrupt level set" "INT0,INT1"
|
|
bitfld.long 0x08 27. " SETINTLVLRDY11 ,Transfer-group completed interrupt level set" "INT0,INT1"
|
|
bitfld.long 0x08 26. " SETINTLVLRDY10 ,Transfer-group completed interrupt level set" "INT0,INT1"
|
|
newline
|
|
bitfld.long 0x08 25. " SETINTLVLRDY9 ,Transfer-group completed interrupt level set" "INT0,INT1"
|
|
bitfld.long 0x08 24. " SETINTLVLRDY8 ,Transfer-group completed interrupt level set" "INT0,INT1"
|
|
bitfld.long 0x08 23. " SETINTLVLRDY7 ,Transfer-group completed interrupt level set" "INT0,INT1"
|
|
newline
|
|
bitfld.long 0x08 22. " SETINTLVLRDY6 ,Transfer-group completed interrupt level set" "INT0,INT1"
|
|
bitfld.long 0x08 21. " SETINTLVLRDY5 ,Transfer-group completed interrupt level set" "INT0,INT1"
|
|
bitfld.long 0x08 20. " SETINTLVLRDY4 ,Transfer-group completed interrupt level set" "INT0,INT1"
|
|
newline
|
|
bitfld.long 0x08 19. " SETINTLVLRDY3 ,Transfer-group completed interrupt level set" "INT0,INT1"
|
|
bitfld.long 0x08 18. " SETINTLVLRDY2 ,Transfer-group completed interrupt level set" "INT0,INT1"
|
|
bitfld.long 0x08 17. " SETINTLVLRDY1 ,Transfer-group completed interrupt level set" "INT0,INT1"
|
|
newline
|
|
bitfld.long 0x08 16. " SETINTLVLRDY0 ,Transfer-group completed interrupt level set" "INT0,INT1"
|
|
bitfld.long 0x08 15. " SETINTLVLSUS15 ,Transfer-group suspended interrupt level set" "INT0,INT1"
|
|
bitfld.long 0x08 14. " SETINTLVLSUS14 ,Transfer-group suspended interrupt level set" "INT0,INT1"
|
|
newline
|
|
bitfld.long 0x08 13. " SETINTLVLSUS13 ,Transfer-group suspended interrupt level set" "INT0,INT1"
|
|
bitfld.long 0x08 12. " SETINTLVLSUS12 ,Transfer-group suspended interrupt level set" "INT0,INT1"
|
|
bitfld.long 0x08 11. " SETINTLVLSUS11 ,Transfer-group suspended interrupt level set" "INT0,INT1"
|
|
newline
|
|
bitfld.long 0x08 10. " SETINTLVLSUS10 ,Transfer-group suspended interrupt level set" "INT0,INT1"
|
|
bitfld.long 0x08 9. " SETINTLVLSUS9 ,Transfer-group suspended interrupt level set" "INT0,INT1"
|
|
bitfld.long 0x08 8. " SETINTLVLSUS8 ,Transfer-group suspended interrupt level set" "INT0,INT1"
|
|
newline
|
|
bitfld.long 0x08 7. " SETINTLVLSUS7 ,Transfer-group suspended interrupt level set" "INT0,INT1"
|
|
bitfld.long 0x08 6. " SETINTLVLSUS6 ,Transfer-group suspended interrupt level set" "INT0,INT1"
|
|
bitfld.long 0x08 5. " SETINTLVLSUS5 ,Transfer-group suspended interrupt level set" "INT0,INT1"
|
|
newline
|
|
bitfld.long 0x08 4. " SETINTLVLSUS4 ,Transfer-group suspended interrupt level set" "INT0,INT1"
|
|
bitfld.long 0x08 3. " SETINTLVLSUS3 ,Transfer-group suspended interrupt level set" "INT0,INT1"
|
|
bitfld.long 0x08 2. " SETINTLVLSUS2 ,Transfer-group suspended interrupt level set" "INT0,INT1"
|
|
newline
|
|
bitfld.long 0x08 1. " SETINTLVLSUS1 ,Transfer-group suspended interrupt level set" "INT0,INT1"
|
|
bitfld.long 0x08 0. " SETINTLVLSUS0 ,Transfer-group suspended interrupt level set" "INT0,INT1"
|
|
line.long 0x0C "TGITLVCR,MibSPI Transfer Group Interrupt Level Clear Register"
|
|
bitfld.long 0x0C 31. " CLRINTLVLRDY15 ,Transfer-group completed interrupt level clear" "INT0,INT1"
|
|
bitfld.long 0x0C 30. " CLRINTLVLRDY14 ,Transfer-group completed interrupt level clear" "INT0,INT1"
|
|
bitfld.long 0x0C 29. " CLRINTLVLRDY13 ,Transfer-group completed interrupt level clear" "INT0,INT1"
|
|
newline
|
|
bitfld.long 0x0C 28. " CLRINTLVLRDY12 ,Transfer-group completed interrupt level clear" "INT0,INT1"
|
|
bitfld.long 0x0C 27. " CLRINTLVLRDY11 ,Transfer-group completed interrupt level clear" "INT0,INT1"
|
|
bitfld.long 0x0C 26. " CLRINTLVLRDY10 ,Transfer-group completed interrupt level clear" "INT0,INT1"
|
|
newline
|
|
bitfld.long 0x0C 25. " CLRINTLVLRDY9 ,Transfer-group completed interrupt level clear" "INT0,INT1"
|
|
bitfld.long 0x0C 24. " CLRINTLVLRDY8 ,Transfer-group completed interrupt level clear" "INT0,INT1"
|
|
bitfld.long 0x0C 23. " CLRINTLVLRDY7 ,Transfer-group completed interrupt level clear" "INT0,INT1"
|
|
newline
|
|
bitfld.long 0x0C 22. " CLRINTLVLRDY6 ,Transfer-group completed interrupt level clear" "INT0,INT1"
|
|
bitfld.long 0x0C 21. " CLRINTLVLRDY5 ,Transfer-group completed interrupt level clear" "INT0,INT1"
|
|
bitfld.long 0x0C 20. " CLRINTLVLRDY4 ,Transfer-group completed interrupt level clear" "INT0,INT1"
|
|
newline
|
|
bitfld.long 0x0C 19. " CLRINTLVLRDY3 ,Transfer-group completed interrupt level clear" "INT0,INT1"
|
|
bitfld.long 0x0C 18. " CLRINTLVLRDY2 ,Transfer-group completed interrupt level clear" "INT0,INT1"
|
|
bitfld.long 0x0C 17. " CLRINTLVLRDY1 ,Transfer-group completed interrupt level clear" "INT0,INT1"
|
|
newline
|
|
bitfld.long 0x0C 16. " CLRINTLVLRDY0 ,Transfer-group completed interrupt level clear" "INT0,INT1"
|
|
bitfld.long 0x0C 15. " CLRINTLVLSUS15 ,Transfer group suspended interrupt level clear" "INT0,INT1"
|
|
bitfld.long 0x0C 14. " CLRINTLVLSUS14 ,Transfer group suspended interrupt level clear" "INT0,INT1"
|
|
newline
|
|
bitfld.long 0x0C 13. " CLRINTLVLSUS13 ,Transfer group suspended interrupt level clear" "INT0,INT1"
|
|
bitfld.long 0x0C 12. " CLRINTLVLSUS12 ,Transfer group suspended interrupt level clear" "INT0,INT1"
|
|
bitfld.long 0x0C 11. " CLRINTLVLSUS11 ,Transfer group suspended interrupt level clear" "INT0,INT1"
|
|
newline
|
|
bitfld.long 0x0C 10. " CLRINTLVLSUS10 ,Transfer group suspended interrupt level clear" "INT0,INT1"
|
|
bitfld.long 0x0C 9. " CLRINTLVLSUS9 ,Transfer group suspended interrupt level clear" "INT0,INT1"
|
|
bitfld.long 0x0C 8. " CLRINTLVLSUS8 ,Transfer group suspended interrupt level clear" "INT0,INT1"
|
|
newline
|
|
bitfld.long 0x0C 7. " CLRINTLVLSUS7 ,Transfer group suspended interrupt level clear" "INT0,INT1"
|
|
bitfld.long 0x0C 6. " CLRINTLVLSUS6 ,Transfer group suspended interrupt level clear" "INT0,INT1"
|
|
bitfld.long 0x0C 5. " CLRINTLVLSUS5 ,Transfer group suspended interrupt level clear" "INT0,INT1"
|
|
newline
|
|
bitfld.long 0x0C 4. " CLRINTLVLSUS4 ,Transfer group suspended interrupt level clear" "INT0,INT1"
|
|
bitfld.long 0x0C 3. " CLRINTLVLSUS3 ,Transfer group suspended interrupt level clear" "INT0,INT1"
|
|
bitfld.long 0x0C 2. " CLRINTLVLSUS2 ,Transfer group suspended interrupt level clear" "INT0,INT1"
|
|
newline
|
|
bitfld.long 0x0C 1. " CLRINTLVLSUS1 ,Transfer group suspended interrupt level clear" "INT0,INT1"
|
|
bitfld.long 0x0C 0. " CLRINTLVLSUS0 ,Transfer group suspended interrupt level clear" "INT0,INT1"
|
|
group.long 0x84++0x03
|
|
line.long 0x00 "TGITFLG,Transfer Group Interrupt Flag Register"
|
|
sif (cpu()==("TMS570LS0332")||cpu()==("TMS570LS0432")||cpuis("TMS570LS1114*")||cpuis("TMS570LS1115*")||cpuis("TMS570LS1224*")||cpuis("TMS570LS1225*")||cpuis("TMS570LS1227*")||cpuis("TMS570LS0232")||cpuis("TMS570LS0714*")||cpuis("TMS570LS0914*"))
|
|
bitfld.long 0x00 31. " INTFLGRDY[15] ,Transfer-group interrupt flag for a transfer-completed interrupt 15" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " INTFLGRDY[14] ,Transfer-group interrupt flag for a transfer-completed interrupt 14" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 29. " INTFLGRDY[13] ,Transfer-group interrupt flag for a transfer-completed interrupt 13" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " INTFLGRDY[12] ,Transfer-group interrupt flag for a transfer-completed interrupt 12" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 27. " INTFLGRDY[11] ,Transfer-group interrupt flag for a transfer-completed interrupt 11" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " INTFLGRDY[10] ,Transfer-group interrupt flag for a transfer-completed interrupt 10" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 25. " INTFLGRDY[9] ,Transfer-group interrupt flag for a transfer-completed interrupt 9" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " INTFLGRDY[8] ,Transfer-group interrupt flag for a transfer-completed interrupt 8" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 23. " INTFLGRDY[7] ,Transfer-group interrupt flag for a transfer-completed interrupt 7" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " INTFLGRDY[6] ,Transfer-group interrupt flag for a transfer-completed interrupt 6" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 21. " INTFLGRDY[5] ,Transfer-group interrupt flag for a transfer-completed interrupt 5" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " INTFLGRDY[4] ,Transfer-group interrupt flag for a transfer-completed interrupt 4" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 19. " INTFLGRDY[3] ,Transfer-group interrupt flag for a transfer-completed interrupt 3" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " INTFLGRDY[2] ,Transfer-group interrupt flag for a transfer-completed interrupt 2" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 17. " INTFLGRDY[1] ,Transfer-group interrupt flag for a transfer-completed interrupt 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " INTFLGRDY[0] ,Transfer-group interrupt flag for a transfer-completed interrupt 0" "Disabled,Enabled"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 15. " INTFLGSUS[15] ,Transfer-group interrupt flag for a transfer-suspend interrupt 15" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " INTFLGSUS[14] ,Transfer-group interrupt flag for a transfer-suspend interrupt 14" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 13. " INTFLGSUS[13] ,Transfer-group interrupt flag for a transfer-suspend interrupt 13" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " INTFLGSUS[12] ,Transfer-group interrupt flag for a transfer-suspend interrupt 12" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 11. " INTFLGSUS[11] ,Transfer-group interrupt flag for a transfer-suspend interrupt 11" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " INTFLGSUS[10] ,Transfer-group interrupt flag for a transfer-suspend interrupt 10" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 9. " INTFLGSUS[9] ,Transfer-group interrupt flag for a transfer-suspend interrupt 9" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " INTFLGSUS[8] ,Transfer-group interrupt flag for a transfer-suspend interrupt 8" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 7. " INTFLGSUS[7] ,Transfer-group interrupt flag for a transfer-suspend interrupt 7" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " INTFLGSUS[6] ,Transfer-group interrupt flag for a transfer-suspend interrupt 6" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 5. " INTFLGSUS[5] ,Transfer-group interrupt flag for a transfer-suspend interrupt 5" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " INTFLGSUS[4] ,Transfer-group interrupt flag for a transfer-suspend interrupt 4" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 3. " INTFLGSUS[3] ,Transfer-group interrupt flag for a transfer-suspend interrupt 3" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " INTFLGSUS[2] ,Transfer-group interrupt flag for a transfer-suspend interrupt 2" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 1. " INTFLGSUS[1] ,Transfer-group interrupt flag for a transfer-suspend interrupt 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " INTFLGSUS[0] ,Transfer-group interrupt flag for a transfer-suspend interrupt 0" "Disabled,Enabled"
|
|
group.long 0x90++0x47
|
|
line.long 0x00 "TICKCNT,Tick Count Register"
|
|
bitfld.long 0x00 31. " TICKENA ,Tick counter enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " RELOAD ,Pre-load the tick counter" "No effect,Reload"
|
|
bitfld.long 0x00 28.--29. " CLKCTRL ,Tick counter clock source control" "0,1,2,3"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TICKVALUE ,Initial value for the tick counter"
|
|
line.long 0x04 "LTGPEND,Last Transfer Group End Pointer Register"
|
|
bitfld.long 0x04 24.--28. " TGINSERVICE ,The TG number currently being serviced by the sequencer" "No TG,TG0,TG1,TG2,TG3,TG4,TG5,TG6,TG7,TG8,TG9,TG10,TG11,TG12,TG13,TG14,TG15,?..."
|
|
hexmask.long.byte 0x04 8.--14. 1. " LPEND ,Last TG end pointer"
|
|
line.long 0x8 "TG0CTRL,MibSPI Transfer Group Control Register 0"
|
|
bitfld.long 0x8 31. " TGENA ,TG enable" "Disabled,Enabled"
|
|
bitfld.long 0x8 30. " ONESHOT ,Single transfer for TG" "Disabled,Enabled"
|
|
bitfld.long 0x8 29. " PRST ,TG pointer reset mode" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x8 28. " TGTD ,TG triggered" "Not triggered,Triggered"
|
|
bitfld.long 0x8 20.--23. " TRGEVT ,Type of trigger event" "Never,Rising edge,Falling edge,Both edges,,High active,Low-active,Always,?..."
|
|
sif cpuis("TMS570LS0232")||cpuis("TMS570LS0714*")||cpuis("TMS570LS0914*")
|
|
bitfld.long 0x8 16.--19. " TRIGSRC ,Trigger source" "Disabled,EXT0,EXT1,EXT2,EXT3,EXT4,EXT5,EXT6,EXT7,EXT8,EXT9,EXT10,EXT11,EXT12,EXT13,TICK"
|
|
else
|
|
bitfld.long 0x8 16.--19. " TRIGSRC ,Trigger source" "Disabled,GIOA[0],GIOA[1],GIOA[2],GIOA[3],GIOA[4],GIOA[5],GIOA[6],GIOA[7],N2HET1[8],N2HET1[10],N2HET1[12],N2HET1[14],N2HET1[16],N2HET1[18],TICK"
|
|
endif
|
|
newline
|
|
hexmask.long.byte 0x8 8.--14. 0x01 " PSTART ,TG start address"
|
|
hexmask.long.byte 0x8 0.--6. 0x01 " PCURRENT ,Pointer to current buffer"
|
|
line.long 0xC "TG1CTRL,MibSPI Transfer Group Control Register 1"
|
|
bitfld.long 0xC 31. " TGENA ,TG enable" "Disabled,Enabled"
|
|
bitfld.long 0xC 30. " ONESHOT ,Single transfer for TG" "Disabled,Enabled"
|
|
bitfld.long 0xC 29. " PRST ,TG pointer reset mode" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0xC 28. " TGTD ,TG triggered" "Not triggered,Triggered"
|
|
bitfld.long 0xC 20.--23. " TRGEVT ,Type of trigger event" "Never,Rising edge,Falling edge,Both edges,,High active,Low-active,Always,?..."
|
|
sif cpuis("TMS570LS0232")||cpuis("TMS570LS0714*")||cpuis("TMS570LS0914*")
|
|
bitfld.long 0xC 16.--19. " TRIGSRC ,Trigger source" "Disabled,EXT0,EXT1,EXT2,EXT3,EXT4,EXT5,EXT6,EXT7,EXT8,EXT9,EXT10,EXT11,EXT12,EXT13,TICK"
|
|
else
|
|
bitfld.long 0xC 16.--19. " TRIGSRC ,Trigger source" "Disabled,GIOA[0],GIOA[1],GIOA[2],GIOA[3],GIOA[4],GIOA[5],GIOA[6],GIOA[7],N2HET1[8],N2HET1[10],N2HET1[12],N2HET1[14],N2HET1[16],N2HET1[18],TICK"
|
|
endif
|
|
newline
|
|
hexmask.long.byte 0xC 8.--14. 0x01 " PSTART ,TG start address"
|
|
hexmask.long.byte 0xC 0.--6. 0x01 " PCURRENT ,Pointer to current buffer"
|
|
line.long 0x10 "TG2CTRL,MibSPI Transfer Group Control Register 2"
|
|
bitfld.long 0x10 31. " TGENA ,TG enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 30. " ONESHOT ,Single transfer for TG" "Disabled,Enabled"
|
|
bitfld.long 0x10 29. " PRST ,TG pointer reset mode" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x10 28. " TGTD ,TG triggered" "Not triggered,Triggered"
|
|
bitfld.long 0x10 20.--23. " TRGEVT ,Type of trigger event" "Never,Rising edge,Falling edge,Both edges,,High active,Low-active,Always,?..."
|
|
sif cpuis("TMS570LS0232")||cpuis("TMS570LS0714*")||cpuis("TMS570LS0914*")
|
|
bitfld.long 0x10 16.--19. " TRIGSRC ,Trigger source" "Disabled,EXT0,EXT1,EXT2,EXT3,EXT4,EXT5,EXT6,EXT7,EXT8,EXT9,EXT10,EXT11,EXT12,EXT13,TICK"
|
|
else
|
|
bitfld.long 0x10 16.--19. " TRIGSRC ,Trigger source" "Disabled,GIOA[0],GIOA[1],GIOA[2],GIOA[3],GIOA[4],GIOA[5],GIOA[6],GIOA[7],N2HET1[8],N2HET1[10],N2HET1[12],N2HET1[14],N2HET1[16],N2HET1[18],TICK"
|
|
endif
|
|
newline
|
|
hexmask.long.byte 0x10 8.--14. 0x01 " PSTART ,TG start address"
|
|
hexmask.long.byte 0x10 0.--6. 0x01 " PCURRENT ,Pointer to current buffer"
|
|
line.long 0x14 "TG3CTRL,MibSPI Transfer Group Control Register 3"
|
|
bitfld.long 0x14 31. " TGENA ,TG enable" "Disabled,Enabled"
|
|
bitfld.long 0x14 30. " ONESHOT ,Single transfer for TG" "Disabled,Enabled"
|
|
bitfld.long 0x14 29. " PRST ,TG pointer reset mode" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x14 28. " TGTD ,TG triggered" "Not triggered,Triggered"
|
|
bitfld.long 0x14 20.--23. " TRGEVT ,Type of trigger event" "Never,Rising edge,Falling edge,Both edges,,High active,Low-active,Always,?..."
|
|
sif cpuis("TMS570LS0232")||cpuis("TMS570LS0714*")||cpuis("TMS570LS0914*")
|
|
bitfld.long 0x14 16.--19. " TRIGSRC ,Trigger source" "Disabled,EXT0,EXT1,EXT2,EXT3,EXT4,EXT5,EXT6,EXT7,EXT8,EXT9,EXT10,EXT11,EXT12,EXT13,TICK"
|
|
else
|
|
bitfld.long 0x14 16.--19. " TRIGSRC ,Trigger source" "Disabled,GIOA[0],GIOA[1],GIOA[2],GIOA[3],GIOA[4],GIOA[5],GIOA[6],GIOA[7],N2HET1[8],N2HET1[10],N2HET1[12],N2HET1[14],N2HET1[16],N2HET1[18],TICK"
|
|
endif
|
|
newline
|
|
hexmask.long.byte 0x14 8.--14. 0x01 " PSTART ,TG start address"
|
|
hexmask.long.byte 0x14 0.--6. 0x01 " PCURRENT ,Pointer to current buffer"
|
|
line.long 0x18 "TG4CTRL,MibSPI Transfer Group Control Register 4"
|
|
bitfld.long 0x18 31. " TGENA ,TG enable" "Disabled,Enabled"
|
|
bitfld.long 0x18 30. " ONESHOT ,Single transfer for TG" "Disabled,Enabled"
|
|
bitfld.long 0x18 29. " PRST ,TG pointer reset mode" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x18 28. " TGTD ,TG triggered" "Not triggered,Triggered"
|
|
bitfld.long 0x18 20.--23. " TRGEVT ,Type of trigger event" "Never,Rising edge,Falling edge,Both edges,,High active,Low-active,Always,?..."
|
|
sif cpuis("TMS570LS0232")||cpuis("TMS570LS0714*")||cpuis("TMS570LS0914*")
|
|
bitfld.long 0x18 16.--19. " TRIGSRC ,Trigger source" "Disabled,EXT0,EXT1,EXT2,EXT3,EXT4,EXT5,EXT6,EXT7,EXT8,EXT9,EXT10,EXT11,EXT12,EXT13,TICK"
|
|
else
|
|
bitfld.long 0x18 16.--19. " TRIGSRC ,Trigger source" "Disabled,GIOA[0],GIOA[1],GIOA[2],GIOA[3],GIOA[4],GIOA[5],GIOA[6],GIOA[7],N2HET1[8],N2HET1[10],N2HET1[12],N2HET1[14],N2HET1[16],N2HET1[18],TICK"
|
|
endif
|
|
newline
|
|
hexmask.long.byte 0x18 8.--14. 0x01 " PSTART ,TG start address"
|
|
hexmask.long.byte 0x18 0.--6. 0x01 " PCURRENT ,Pointer to current buffer"
|
|
line.long 0x1C "TG5CTRL,MibSPI Transfer Group Control Register 5"
|
|
bitfld.long 0x1C 31. " TGENA ,TG enable" "Disabled,Enabled"
|
|
bitfld.long 0x1C 30. " ONESHOT ,Single transfer for TG" "Disabled,Enabled"
|
|
bitfld.long 0x1C 29. " PRST ,TG pointer reset mode" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x1C 28. " TGTD ,TG triggered" "Not triggered,Triggered"
|
|
bitfld.long 0x1C 20.--23. " TRGEVT ,Type of trigger event" "Never,Rising edge,Falling edge,Both edges,,High active,Low-active,Always,?..."
|
|
sif cpuis("TMS570LS0232")||cpuis("TMS570LS0714*")||cpuis("TMS570LS0914*")
|
|
bitfld.long 0x1C 16.--19. " TRIGSRC ,Trigger source" "Disabled,EXT0,EXT1,EXT2,EXT3,EXT4,EXT5,EXT6,EXT7,EXT8,EXT9,EXT10,EXT11,EXT12,EXT13,TICK"
|
|
else
|
|
bitfld.long 0x1C 16.--19. " TRIGSRC ,Trigger source" "Disabled,GIOA[0],GIOA[1],GIOA[2],GIOA[3],GIOA[4],GIOA[5],GIOA[6],GIOA[7],N2HET1[8],N2HET1[10],N2HET1[12],N2HET1[14],N2HET1[16],N2HET1[18],TICK"
|
|
endif
|
|
newline
|
|
hexmask.long.byte 0x1C 8.--14. 0x01 " PSTART ,TG start address"
|
|
hexmask.long.byte 0x1C 0.--6. 0x01 " PCURRENT ,Pointer to current buffer"
|
|
line.long 0x20 "TG6CTRL,MibSPI Transfer Group Control Register 6"
|
|
bitfld.long 0x20 31. " TGENA ,TG enable" "Disabled,Enabled"
|
|
bitfld.long 0x20 30. " ONESHOT ,Single transfer for TG" "Disabled,Enabled"
|
|
bitfld.long 0x20 29. " PRST ,TG pointer reset mode" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x20 28. " TGTD ,TG triggered" "Not triggered,Triggered"
|
|
bitfld.long 0x20 20.--23. " TRGEVT ,Type of trigger event" "Never,Rising edge,Falling edge,Both edges,,High active,Low-active,Always,?..."
|
|
sif cpuis("TMS570LS0232")||cpuis("TMS570LS0714*")||cpuis("TMS570LS0914*")
|
|
bitfld.long 0x20 16.--19. " TRIGSRC ,Trigger source" "Disabled,EXT0,EXT1,EXT2,EXT3,EXT4,EXT5,EXT6,EXT7,EXT8,EXT9,EXT10,EXT11,EXT12,EXT13,TICK"
|
|
else
|
|
bitfld.long 0x20 16.--19. " TRIGSRC ,Trigger source" "Disabled,GIOA[0],GIOA[1],GIOA[2],GIOA[3],GIOA[4],GIOA[5],GIOA[6],GIOA[7],N2HET1[8],N2HET1[10],N2HET1[12],N2HET1[14],N2HET1[16],N2HET1[18],TICK"
|
|
endif
|
|
newline
|
|
hexmask.long.byte 0x20 8.--14. 0x01 " PSTART ,TG start address"
|
|
hexmask.long.byte 0x20 0.--6. 0x01 " PCURRENT ,Pointer to current buffer"
|
|
line.long 0x24 "TG7CTRL,MibSPI Transfer Group Control Register 7"
|
|
bitfld.long 0x24 31. " TGENA ,TG enable" "Disabled,Enabled"
|
|
bitfld.long 0x24 30. " ONESHOT ,Single transfer for TG" "Disabled,Enabled"
|
|
bitfld.long 0x24 29. " PRST ,TG pointer reset mode" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x24 28. " TGTD ,TG triggered" "Not triggered,Triggered"
|
|
bitfld.long 0x24 20.--23. " TRGEVT ,Type of trigger event" "Never,Rising edge,Falling edge,Both edges,,High active,Low-active,Always,?..."
|
|
sif cpuis("TMS570LS0232")||cpuis("TMS570LS0714*")||cpuis("TMS570LS0914*")
|
|
bitfld.long 0x24 16.--19. " TRIGSRC ,Trigger source" "Disabled,EXT0,EXT1,EXT2,EXT3,EXT4,EXT5,EXT6,EXT7,EXT8,EXT9,EXT10,EXT11,EXT12,EXT13,TICK"
|
|
else
|
|
bitfld.long 0x24 16.--19. " TRIGSRC ,Trigger source" "Disabled,GIOA[0],GIOA[1],GIOA[2],GIOA[3],GIOA[4],GIOA[5],GIOA[6],GIOA[7],N2HET1[8],N2HET1[10],N2HET1[12],N2HET1[14],N2HET1[16],N2HET1[18],TICK"
|
|
endif
|
|
newline
|
|
hexmask.long.byte 0x24 8.--14. 0x01 " PSTART ,TG start address"
|
|
hexmask.long.byte 0x24 0.--6. 0x01 " PCURRENT ,Pointer to current buffer"
|
|
line.long 0x28 "TG8CTRL,MibSPI Transfer Group Control Register 8"
|
|
bitfld.long 0x28 31. " TGENA ,TG enable" "Disabled,Enabled"
|
|
bitfld.long 0x28 30. " ONESHOT ,Single transfer for TG" "Disabled,Enabled"
|
|
bitfld.long 0x28 29. " PRST ,TG pointer reset mode" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x28 28. " TGTD ,TG triggered" "Not triggered,Triggered"
|
|
bitfld.long 0x28 20.--23. " TRGEVT ,Type of trigger event" "Never,Rising edge,Falling edge,Both edges,,High active,Low-active,Always,?..."
|
|
sif cpuis("TMS570LS0232")||cpuis("TMS570LS0714*")||cpuis("TMS570LS0914*")
|
|
bitfld.long 0x28 16.--19. " TRIGSRC ,Trigger source" "Disabled,EXT0,EXT1,EXT2,EXT3,EXT4,EXT5,EXT6,EXT7,EXT8,EXT9,EXT10,EXT11,EXT12,EXT13,TICK"
|
|
else
|
|
bitfld.long 0x28 16.--19. " TRIGSRC ,Trigger source" "Disabled,GIOA[0],GIOA[1],GIOA[2],GIOA[3],GIOA[4],GIOA[5],GIOA[6],GIOA[7],N2HET1[8],N2HET1[10],N2HET1[12],N2HET1[14],N2HET1[16],N2HET1[18],TICK"
|
|
endif
|
|
newline
|
|
hexmask.long.byte 0x28 8.--14. 0x01 " PSTART ,TG start address"
|
|
hexmask.long.byte 0x28 0.--6. 0x01 " PCURRENT ,Pointer to current buffer"
|
|
line.long 0x2C "TG9CTRL,MibSPI Transfer Group Control Register 9"
|
|
bitfld.long 0x2C 31. " TGENA ,TG enable" "Disabled,Enabled"
|
|
bitfld.long 0x2C 30. " ONESHOT ,Single transfer for TG" "Disabled,Enabled"
|
|
bitfld.long 0x2C 29. " PRST ,TG pointer reset mode" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x2C 28. " TGTD ,TG triggered" "Not triggered,Triggered"
|
|
bitfld.long 0x2C 20.--23. " TRGEVT ,Type of trigger event" "Never,Rising edge,Falling edge,Both edges,,High active,Low-active,Always,?..."
|
|
sif cpuis("TMS570LS0232")||cpuis("TMS570LS0714*")||cpuis("TMS570LS0914*")
|
|
bitfld.long 0x2C 16.--19. " TRIGSRC ,Trigger source" "Disabled,EXT0,EXT1,EXT2,EXT3,EXT4,EXT5,EXT6,EXT7,EXT8,EXT9,EXT10,EXT11,EXT12,EXT13,TICK"
|
|
else
|
|
bitfld.long 0x2C 16.--19. " TRIGSRC ,Trigger source" "Disabled,GIOA[0],GIOA[1],GIOA[2],GIOA[3],GIOA[4],GIOA[5],GIOA[6],GIOA[7],N2HET1[8],N2HET1[10],N2HET1[12],N2HET1[14],N2HET1[16],N2HET1[18],TICK"
|
|
endif
|
|
newline
|
|
hexmask.long.byte 0x2C 8.--14. 0x01 " PSTART ,TG start address"
|
|
hexmask.long.byte 0x2C 0.--6. 0x01 " PCURRENT ,Pointer to current buffer"
|
|
line.long 0x30 "TG10CTRL,MibSPI Transfer Group Control Register 10"
|
|
bitfld.long 0x30 31. " TGENA ,TG enable" "Disabled,Enabled"
|
|
bitfld.long 0x30 30. " ONESHOT ,Single transfer for TG" "Disabled,Enabled"
|
|
bitfld.long 0x30 29. " PRST ,TG pointer reset mode" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x30 28. " TGTD ,TG triggered" "Not triggered,Triggered"
|
|
bitfld.long 0x30 20.--23. " TRGEVT ,Type of trigger event" "Never,Rising edge,Falling edge,Both edges,,High active,Low-active,Always,?..."
|
|
sif cpuis("TMS570LS0232")||cpuis("TMS570LS0714*")||cpuis("TMS570LS0914*")
|
|
bitfld.long 0x30 16.--19. " TRIGSRC ,Trigger source" "Disabled,EXT0,EXT1,EXT2,EXT3,EXT4,EXT5,EXT6,EXT7,EXT8,EXT9,EXT10,EXT11,EXT12,EXT13,TICK"
|
|
else
|
|
bitfld.long 0x30 16.--19. " TRIGSRC ,Trigger source" "Disabled,GIOA[0],GIOA[1],GIOA[2],GIOA[3],GIOA[4],GIOA[5],GIOA[6],GIOA[7],N2HET1[8],N2HET1[10],N2HET1[12],N2HET1[14],N2HET1[16],N2HET1[18],TICK"
|
|
endif
|
|
newline
|
|
hexmask.long.byte 0x30 8.--14. 0x01 " PSTART ,TG start address"
|
|
hexmask.long.byte 0x30 0.--6. 0x01 " PCURRENT ,Pointer to current buffer"
|
|
line.long 0x34 "TG11CTRL,MibSPI Transfer Group Control Register 11"
|
|
bitfld.long 0x34 31. " TGENA ,TG enable" "Disabled,Enabled"
|
|
bitfld.long 0x34 30. " ONESHOT ,Single transfer for TG" "Disabled,Enabled"
|
|
bitfld.long 0x34 29. " PRST ,TG pointer reset mode" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x34 28. " TGTD ,TG triggered" "Not triggered,Triggered"
|
|
bitfld.long 0x34 20.--23. " TRGEVT ,Type of trigger event" "Never,Rising edge,Falling edge,Both edges,,High active,Low-active,Always,?..."
|
|
sif cpuis("TMS570LS0232")||cpuis("TMS570LS0714*")||cpuis("TMS570LS0914*")
|
|
bitfld.long 0x34 16.--19. " TRIGSRC ,Trigger source" "Disabled,EXT0,EXT1,EXT2,EXT3,EXT4,EXT5,EXT6,EXT7,EXT8,EXT9,EXT10,EXT11,EXT12,EXT13,TICK"
|
|
else
|
|
bitfld.long 0x34 16.--19. " TRIGSRC ,Trigger source" "Disabled,GIOA[0],GIOA[1],GIOA[2],GIOA[3],GIOA[4],GIOA[5],GIOA[6],GIOA[7],N2HET1[8],N2HET1[10],N2HET1[12],N2HET1[14],N2HET1[16],N2HET1[18],TICK"
|
|
endif
|
|
newline
|
|
hexmask.long.byte 0x34 8.--14. 0x01 " PSTART ,TG start address"
|
|
hexmask.long.byte 0x34 0.--6. 0x01 " PCURRENT ,Pointer to current buffer"
|
|
line.long 0x38 "TG12CTRL,MibSPI Transfer Group Control Register 12"
|
|
bitfld.long 0x38 31. " TGENA ,TG enable" "Disabled,Enabled"
|
|
bitfld.long 0x38 30. " ONESHOT ,Single transfer for TG" "Disabled,Enabled"
|
|
bitfld.long 0x38 29. " PRST ,TG pointer reset mode" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x38 28. " TGTD ,TG triggered" "Not triggered,Triggered"
|
|
bitfld.long 0x38 20.--23. " TRGEVT ,Type of trigger event" "Never,Rising edge,Falling edge,Both edges,,High active,Low-active,Always,?..."
|
|
sif cpuis("TMS570LS0232")||cpuis("TMS570LS0714*")||cpuis("TMS570LS0914*")
|
|
bitfld.long 0x38 16.--19. " TRIGSRC ,Trigger source" "Disabled,EXT0,EXT1,EXT2,EXT3,EXT4,EXT5,EXT6,EXT7,EXT8,EXT9,EXT10,EXT11,EXT12,EXT13,TICK"
|
|
else
|
|
bitfld.long 0x38 16.--19. " TRIGSRC ,Trigger source" "Disabled,GIOA[0],GIOA[1],GIOA[2],GIOA[3],GIOA[4],GIOA[5],GIOA[6],GIOA[7],N2HET1[8],N2HET1[10],N2HET1[12],N2HET1[14],N2HET1[16],N2HET1[18],TICK"
|
|
endif
|
|
newline
|
|
hexmask.long.byte 0x38 8.--14. 0x01 " PSTART ,TG start address"
|
|
hexmask.long.byte 0x38 0.--6. 0x01 " PCURRENT ,Pointer to current buffer"
|
|
line.long 0x3C "TG13CTRL,MibSPI Transfer Group Control Register 13"
|
|
bitfld.long 0x3C 31. " TGENA ,TG enable" "Disabled,Enabled"
|
|
bitfld.long 0x3C 30. " ONESHOT ,Single transfer for TG" "Disabled,Enabled"
|
|
bitfld.long 0x3C 29. " PRST ,TG pointer reset mode" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x3C 28. " TGTD ,TG triggered" "Not triggered,Triggered"
|
|
bitfld.long 0x3C 20.--23. " TRGEVT ,Type of trigger event" "Never,Rising edge,Falling edge,Both edges,,High active,Low-active,Always,?..."
|
|
sif cpuis("TMS570LS0232")||cpuis("TMS570LS0714*")||cpuis("TMS570LS0914*")
|
|
bitfld.long 0x3C 16.--19. " TRIGSRC ,Trigger source" "Disabled,EXT0,EXT1,EXT2,EXT3,EXT4,EXT5,EXT6,EXT7,EXT8,EXT9,EXT10,EXT11,EXT12,EXT13,TICK"
|
|
else
|
|
bitfld.long 0x3C 16.--19. " TRIGSRC ,Trigger source" "Disabled,GIOA[0],GIOA[1],GIOA[2],GIOA[3],GIOA[4],GIOA[5],GIOA[6],GIOA[7],N2HET1[8],N2HET1[10],N2HET1[12],N2HET1[14],N2HET1[16],N2HET1[18],TICK"
|
|
endif
|
|
newline
|
|
hexmask.long.byte 0x3C 8.--14. 0x01 " PSTART ,TG start address"
|
|
hexmask.long.byte 0x3C 0.--6. 0x01 " PCURRENT ,Pointer to current buffer"
|
|
line.long 0x40 "TG14CTRL,MibSPI Transfer Group Control Register 14"
|
|
bitfld.long 0x40 31. " TGENA ,TG enable" "Disabled,Enabled"
|
|
bitfld.long 0x40 30. " ONESHOT ,Single transfer for TG" "Disabled,Enabled"
|
|
bitfld.long 0x40 29. " PRST ,TG pointer reset mode" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x40 28. " TGTD ,TG triggered" "Not triggered,Triggered"
|
|
bitfld.long 0x40 20.--23. " TRGEVT ,Type of trigger event" "Never,Rising edge,Falling edge,Both edges,,High active,Low-active,Always,?..."
|
|
sif cpuis("TMS570LS0232")||cpuis("TMS570LS0714*")||cpuis("TMS570LS0914*")
|
|
bitfld.long 0x40 16.--19. " TRIGSRC ,Trigger source" "Disabled,EXT0,EXT1,EXT2,EXT3,EXT4,EXT5,EXT6,EXT7,EXT8,EXT9,EXT10,EXT11,EXT12,EXT13,TICK"
|
|
else
|
|
bitfld.long 0x40 16.--19. " TRIGSRC ,Trigger source" "Disabled,GIOA[0],GIOA[1],GIOA[2],GIOA[3],GIOA[4],GIOA[5],GIOA[6],GIOA[7],N2HET1[8],N2HET1[10],N2HET1[12],N2HET1[14],N2HET1[16],N2HET1[18],TICK"
|
|
endif
|
|
newline
|
|
hexmask.long.byte 0x40 8.--14. 0x01 " PSTART ,TG start address"
|
|
hexmask.long.byte 0x40 0.--6. 0x01 " PCURRENT ,Pointer to current buffer"
|
|
line.long 0x44 "TG15CTRL,MibSPI Transfer Group Control Register 15"
|
|
bitfld.long 0x44 31. " TGENA ,TG enable" "Disabled,Enabled"
|
|
bitfld.long 0x44 30. " ONESHOT ,Single transfer for TG" "Disabled,Enabled"
|
|
bitfld.long 0x44 29. " PRST ,TG pointer reset mode" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x44 28. " TGTD ,TG triggered" "Not triggered,Triggered"
|
|
bitfld.long 0x44 20.--23. " TRGEVT ,Type of trigger event" "Never,Rising edge,Falling edge,Both edges,,High active,Low-active,Always,?..."
|
|
sif cpuis("TMS570LS0232")||cpuis("TMS570LS0714*")||cpuis("TMS570LS0914*")
|
|
bitfld.long 0x44 16.--19. " TRIGSRC ,Trigger source" "Disabled,EXT0,EXT1,EXT2,EXT3,EXT4,EXT5,EXT6,EXT7,EXT8,EXT9,EXT10,EXT11,EXT12,EXT13,TICK"
|
|
else
|
|
bitfld.long 0x44 16.--19. " TRIGSRC ,Trigger source" "Disabled,GIOA[0],GIOA[1],GIOA[2],GIOA[3],GIOA[4],GIOA[5],GIOA[6],GIOA[7],N2HET1[8],N2HET1[10],N2HET1[12],N2HET1[14],N2HET1[16],N2HET1[18],TICK"
|
|
endif
|
|
newline
|
|
hexmask.long.byte 0x44 8.--14. 0x01 " PSTART ,TG start address"
|
|
hexmask.long.byte 0x44 0.--6. 0x01 " PCURRENT ,Pointer to current buffer"
|
|
sif (cpu()!=("TMS570LS0332")&&cpu()!=("TMS570LS0432")&&!cpuis("TMS570LS0232"))
|
|
group.long 0xD8++0x1F
|
|
line.long 0x0 "DMA0CTRL,MibSPI DMA Channel Control Register 1"
|
|
bitfld.long 0x0 31. " ONESHOT ,Auto-disable of DMA channel after ICOUNT+1 transfers" "0,1"
|
|
hexmask.long.byte 0x0 24.--30. 1. " BUFID ,Buffer utilized for DMA transfer"
|
|
bitfld.long 0x0 20.--23. " RXDMA_MAP ,Each MibSPI DMA channel can be linked to two physical DMA" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x0 16.--19. " TXDMA_MAP ,Each MibSPI DMA channel can be linked to two physical DMA" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x0 15. " RXDMAENA ,Receive data DMA channel enable" "Disabled,Enabled"
|
|
bitfld.long 0x0 14. " TXDMAENA ,Transmit data DMA channel enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x0 13. " NOBRK ,Non-interleaved DMA block transfer" "Not performed,Performed"
|
|
bitfld.long 0x0 8.--12. " ICOUNT ,Initial count of DMA transfers" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32"
|
|
bitfld.long 0x0 6. " COUNTBIT17 ,17th bit of the COUNT field of DMAxCOUNT register" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0.--5. " COUNT ,Actual number of remaining DMA transfers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
line.long 0x4 "DMA1CTRL,MibSPI DMA Channel Control Register 1"
|
|
bitfld.long 0x4 31. " ONESHOT ,Auto-disable of DMA channel after ICOUNT+1 transfers" "0,1"
|
|
hexmask.long.byte 0x4 24.--30. 1. " BUFID ,Buffer utilized for DMA transfer"
|
|
bitfld.long 0x4 20.--23. " RXDMA_MAP ,Each MibSPI DMA channel can be linked to two physical DMA" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x4 16.--19. " TXDMA_MAP ,Each MibSPI DMA channel can be linked to two physical DMA" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x4 15. " RXDMAENA ,Receive data DMA channel enable" "Disabled,Enabled"
|
|
bitfld.long 0x4 14. " TXDMAENA ,Transmit data DMA channel enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x4 13. " NOBRK ,Non-interleaved DMA block transfer" "Not performed,Performed"
|
|
bitfld.long 0x4 8.--12. " ICOUNT ,Initial count of DMA transfers" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32"
|
|
bitfld.long 0x4 6. " COUNTBIT17 ,17th bit of the COUNT field of DMAxCOUNT register" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0.--5. " COUNT ,Actual number of remaining DMA transfers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
line.long 0x8 "DMA2CTRL,MibSPI DMA Channel Control Register 1"
|
|
bitfld.long 0x8 31. " ONESHOT ,Auto-disable of DMA channel after ICOUNT+1 transfers" "0,1"
|
|
hexmask.long.byte 0x8 24.--30. 1. " BUFID ,Buffer utilized for DMA transfer"
|
|
bitfld.long 0x8 20.--23. " RXDMA_MAP ,Each MibSPI DMA channel can be linked to two physical DMA" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x8 16.--19. " TXDMA_MAP ,Each MibSPI DMA channel can be linked to two physical DMA" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x8 15. " RXDMAENA ,Receive data DMA channel enable" "Disabled,Enabled"
|
|
bitfld.long 0x8 14. " TXDMAENA ,Transmit data DMA channel enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x8 13. " NOBRK ,Non-interleaved DMA block transfer" "Not performed,Performed"
|
|
bitfld.long 0x8 8.--12. " ICOUNT ,Initial count of DMA transfers" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32"
|
|
bitfld.long 0x8 6. " COUNTBIT17 ,17th bit of the COUNT field of DMAxCOUNT register" "0,1"
|
|
newline
|
|
bitfld.long 0x8 0.--5. " COUNT ,Actual number of remaining DMA transfers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
line.long 0xC "DMA3CTRL,MibSPI DMA Channel Control Register 1"
|
|
bitfld.long 0xC 31. " ONESHOT ,Auto-disable of DMA channel after ICOUNT+1 transfers" "0,1"
|
|
hexmask.long.byte 0xC 24.--30. 1. " BUFID ,Buffer utilized for DMA transfer"
|
|
bitfld.long 0xC 20.--23. " RXDMA_MAP ,Each MibSPI DMA channel can be linked to two physical DMA" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0xC 16.--19. " TXDMA_MAP ,Each MibSPI DMA channel can be linked to two physical DMA" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0xC 15. " RXDMAENA ,Receive data DMA channel enable" "Disabled,Enabled"
|
|
bitfld.long 0xC 14. " TXDMAENA ,Transmit data DMA channel enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0xC 13. " NOBRK ,Non-interleaved DMA block transfer" "Not performed,Performed"
|
|
bitfld.long 0xC 8.--12. " ICOUNT ,Initial count of DMA transfers" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32"
|
|
bitfld.long 0xC 6. " COUNTBIT17 ,17th bit of the COUNT field of DMAxCOUNT register" "0,1"
|
|
newline
|
|
bitfld.long 0xC 0.--5. " COUNT ,Actual number of remaining DMA transfers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
line.long 0x10 "DMA4CTRL,MibSPI DMA Channel Control Register 1"
|
|
bitfld.long 0x10 31. " ONESHOT ,Auto-disable of DMA channel after ICOUNT+1 transfers" "0,1"
|
|
hexmask.long.byte 0x10 24.--30. 1. " BUFID ,Buffer utilized for DMA transfer"
|
|
bitfld.long 0x10 20.--23. " RXDMA_MAP ,Each MibSPI DMA channel can be linked to two physical DMA" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x10 16.--19. " TXDMA_MAP ,Each MibSPI DMA channel can be linked to two physical DMA" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x10 15. " RXDMAENA ,Receive data DMA channel enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 14. " TXDMAENA ,Transmit data DMA channel enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x10 13. " NOBRK ,Non-interleaved DMA block transfer" "Not performed,Performed"
|
|
bitfld.long 0x10 8.--12. " ICOUNT ,Initial count of DMA transfers" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32"
|
|
bitfld.long 0x10 6. " COUNTBIT17 ,17th bit of the COUNT field of DMAxCOUNT register" "0,1"
|
|
newline
|
|
bitfld.long 0x10 0.--5. " COUNT ,Actual number of remaining DMA transfers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
line.long 0x14 "DMA5CTRL,MibSPI DMA Channel Control Register 1"
|
|
bitfld.long 0x14 31. " ONESHOT ,Auto-disable of DMA channel after ICOUNT+1 transfers" "0,1"
|
|
hexmask.long.byte 0x14 24.--30. 1. " BUFID ,Buffer utilized for DMA transfer"
|
|
bitfld.long 0x14 20.--23. " RXDMA_MAP ,Each MibSPI DMA channel can be linked to two physical DMA" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x14 16.--19. " TXDMA_MAP ,Each MibSPI DMA channel can be linked to two physical DMA" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x14 15. " RXDMAENA ,Receive data DMA channel enable" "Disabled,Enabled"
|
|
bitfld.long 0x14 14. " TXDMAENA ,Transmit data DMA channel enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x14 13. " NOBRK ,Non-interleaved DMA block transfer" "Not performed,Performed"
|
|
bitfld.long 0x14 8.--12. " ICOUNT ,Initial count of DMA transfers" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32"
|
|
bitfld.long 0x14 6. " COUNTBIT17 ,17th bit of the COUNT field of DMAxCOUNT register" "0,1"
|
|
newline
|
|
bitfld.long 0x14 0.--5. " COUNT ,Actual number of remaining DMA transfers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
line.long 0x18 "DMA6CTRL,MibSPI DMA Channel Control Register 1"
|
|
bitfld.long 0x18 31. " ONESHOT ,Auto-disable of DMA channel after ICOUNT+1 transfers" "0,1"
|
|
hexmask.long.byte 0x18 24.--30. 1. " BUFID ,Buffer utilized for DMA transfer"
|
|
bitfld.long 0x18 20.--23. " RXDMA_MAP ,Each MibSPI DMA channel can be linked to two physical DMA" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x18 16.--19. " TXDMA_MAP ,Each MibSPI DMA channel can be linked to two physical DMA" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x18 15. " RXDMAENA ,Receive data DMA channel enable" "Disabled,Enabled"
|
|
bitfld.long 0x18 14. " TXDMAENA ,Transmit data DMA channel enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x18 13. " NOBRK ,Non-interleaved DMA block transfer" "Not performed,Performed"
|
|
bitfld.long 0x18 8.--12. " ICOUNT ,Initial count of DMA transfers" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32"
|
|
bitfld.long 0x18 6. " COUNTBIT17 ,17th bit of the COUNT field of DMAxCOUNT register" "0,1"
|
|
newline
|
|
bitfld.long 0x18 0.--5. " COUNT ,Actual number of remaining DMA transfers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
line.long 0x1C "DMA7CTRL,MibSPI DMA Channel Control Register 1"
|
|
bitfld.long 0x1C 31. " ONESHOT ,Auto-disable of DMA channel after ICOUNT+1 transfers" "0,1"
|
|
hexmask.long.byte 0x1C 24.--30. 1. " BUFID ,Buffer utilized for DMA transfer"
|
|
bitfld.long 0x1C 20.--23. " RXDMA_MAP ,Each MibSPI DMA channel can be linked to two physical DMA" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x1C 16.--19. " TXDMA_MAP ,Each MibSPI DMA channel can be linked to two physical DMA" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x1C 15. " RXDMAENA ,Receive data DMA channel enable" "Disabled,Enabled"
|
|
bitfld.long 0x1C 14. " TXDMAENA ,Transmit data DMA channel enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x1C 13. " NOBRK ,Non-interleaved DMA block transfer" "Not performed,Performed"
|
|
bitfld.long 0x1C 8.--12. " ICOUNT ,Initial count of DMA transfers" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32"
|
|
bitfld.long 0x1C 6. " COUNTBIT17 ,17th bit of the COUNT field of DMAxCOUNT register" "0,1"
|
|
newline
|
|
bitfld.long 0x1C 0.--5. " COUNT ,Actual number of remaining DMA transfers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
group.long 0xF8++0x1F
|
|
line.long 0x0 "DMA0 COUNT,MibSPI DMA0 COUNT Register"
|
|
hexmask.long.word 0x0 16.--31. 1. " ICOUNT0 ,Initial number of DMA transfers"
|
|
hexmask.long.word 0x0 0.--15. 1. " COUNT0 ,The actual number of remaining DMA transfers"
|
|
line.long 0x4 "DMA1 COUNT,MibSPI DMA1 COUNT Register"
|
|
hexmask.long.word 0x4 16.--31. 1. " ICOUNT1 ,Initial number of DMA transfers"
|
|
hexmask.long.word 0x4 0.--15. 1. " COUNT1 ,The actual number of remaining DMA transfers"
|
|
line.long 0x8 "DMA2 COUNT,MibSPI DMA2 COUNT Register"
|
|
hexmask.long.word 0x8 16.--31. 1. " ICOUNT2 ,Initial number of DMA transfers"
|
|
hexmask.long.word 0x8 0.--15. 1. " COUNT2 ,The actual number of remaining DMA transfers"
|
|
line.long 0xC "DMA3 COUNT,MibSPI DMA3 COUNT Register"
|
|
hexmask.long.word 0xC 16.--31. 1. " ICOUNT3 ,Initial number of DMA transfers"
|
|
hexmask.long.word 0xC 0.--15. 1. " COUNT3 ,The actual number of remaining DMA transfers"
|
|
line.long 0x10 "DMA4 COUNT,MibSPI DMA4 COUNT Register"
|
|
hexmask.long.word 0x10 16.--31. 1. " ICOUNT4 ,Initial number of DMA transfers"
|
|
hexmask.long.word 0x10 0.--15. 1. " COUNT4 ,The actual number of remaining DMA transfers"
|
|
line.long 0x14 "DMA5 COUNT,MibSPI DMA5 COUNT Register"
|
|
hexmask.long.word 0x14 16.--31. 1. " ICOUNT5 ,Initial number of DMA transfers"
|
|
hexmask.long.word 0x14 0.--15. 1. " COUNT5 ,The actual number of remaining DMA transfers"
|
|
line.long 0x18 "DMA6 COUNT,MibSPI DMA6 COUNT Register"
|
|
hexmask.long.word 0x18 16.--31. 1. " ICOUNT6 ,Initial number of DMA transfers"
|
|
hexmask.long.word 0x18 0.--15. 1. " COUNT6 ,The actual number of remaining DMA transfers"
|
|
line.long 0x1C "DMA7 COUNT,MibSPI DMA7 COUNT Register"
|
|
hexmask.long.word 0x1C 16.--31. 1. " ICOUNT7 ,Initial number of DMA transfers"
|
|
hexmask.long.word 0x1C 0.--15. 1. " COUNT7 ,The actual number of remaining DMA transfers"
|
|
group.long 0x118++0x03
|
|
line.long 0x00 "DMACNTLEN,MibSPI DMACNTLEN Register"
|
|
bitfld.long 0x00 0. " LARGECOUNT ,Counters select" "DMAxCTRL,DMAxCOUNT"
|
|
endif
|
|
group.long 0x120++0x03
|
|
line.long 0x00 "UERRCTRL,Uncorrectable Parity Error Control Register"
|
|
bitfld.long 0x00 8. " PTESTEN ,Parity memory test enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--3. " EDEN ,Error detection enable" "Enabled,Enabled,Enabled,Enabled,Enabled,Disabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled"
|
|
group.long 0x124++0x03
|
|
line.long 0x00 "UERRSTAT,Uncorrectable Parity Error Status Register"
|
|
eventfld.long 0x00 1. " EDFLG1 ,Uncorrectable parity error detection flag" "Not occurred,Occurred"
|
|
eventfld.long 0x00 0. " EDFLG0 ,Uncorrectable parity error detection flag" "Not occurred,Occurred"
|
|
hgroup.long 0x128++0x03
|
|
hide.long 0x00 "UERRADDR1,Uncorrectable Parity Error Address Register"
|
|
in
|
|
hgroup.long 0x12C++0x03
|
|
hide.long 0x00 "UERRADDR0,Uncorrectable Parity Error Address Register"
|
|
in
|
|
hgroup.long 0x130++0x03
|
|
hide.long 0x00 "RXOVRN_BUF_ADDR,Receive RAM Overrun Buffer Address Register"
|
|
in
|
|
sif cpuis("TMS570LS0714*")||cpuis("TMS570LS0914*")||cpuis("TMS570LS0232")
|
|
if (((per.l.be(ad:0xFFF7F800+0x134))&0x2)==0x2)
|
|
group.long 0x134++0x03
|
|
line.long 0x00 "IOLPBKTSTCR,SPI IO Loopback Test Control Register"
|
|
bitfld.long 0x00 24. " SCSFAILFLG ,Failure on SPISCS pin compare during analog loopback" "Not occurred,Occurred"
|
|
bitfld.long 0x00 20. " CTRL_BITERR ,Controls inducing of BITERR during I/O loopback test mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " CTRL_DESYNC ,Controls inducing of the desync error during I/O loopback test mode" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 18. " CTRL_PARERR ,Controls inducing of parity errors during I/O loopback test mode" "No error,Error"
|
|
bitfld.long 0x00 17. " CTRL_TIMEOUT ,Controls inducing of the timeout error during I/O loopbacK test mode" "No error,Error"
|
|
bitfld.long 0x00 16. " CTRL_DLENERR ,Controls inducing of the data length error during I/O loopback test mode" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 8.--11. " IOLPBKTSTENA ,Module I/O loopback test enable key" "Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Enabled,Disabled,Disabled,Disabled,Disabled,Disabled"
|
|
sif cpuis("TMS570LS0232")
|
|
bitfld.long 0x00 3.--5. " ERRSCSPIN ,Inject error on chip-select pin number" "/SPISCS[0],/SPISCS[1],/SPISCS[2],/SPISCS[3],?..."
|
|
else
|
|
bitfld.long 0x00 3.--5. " ERRSCSPIN ,Inject error on chip-select pin number" "/SPISCS[0],/SPISCS[1],/SPISCS[2],/SPISCS[3],/SPISCS[4],/SPISCS[5],/SPISCS[6],/SPISCS[7]"
|
|
endif
|
|
bitfld.long 0x00 2. " CTRLSCSPINERR ,Enable/disable the injection of an error on the SPISCS[3:0] pins" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 1. " LPBK_TYPE ,Module I/O loopback type (analog/digital)" "Digital,Analog"
|
|
bitfld.long 0x00 0. " RXP_ENA ,Enable analog loopback through the receive pin" "Transmit,Receive"
|
|
else
|
|
group.long 0x134++0x03
|
|
line.long 0x00 "IOLPBKTSTCR,SPI IO Loopback Test Control Register"
|
|
bitfld.long 0x00 24. " SCSFAILFLG ,Failure on SPISCS pin compare during analog loopback" "Not occurred,Occurred"
|
|
bitfld.long 0x00 20. " CTRL_BITERR ,Controls inducing of BITERR during I/O loopback test mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " CTRL_DESYNC ,Controls inducing of the desync error during I/O loopback test mode" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 18. " CTRL_PARERR ,Controls inducing of parity errors during I/O loopback test mode" "No error,Error"
|
|
bitfld.long 0x00 17. " CTRL_TIMEOUT ,Controls inducing of the timeout error during I/O loopbacK test mode" "No error,Error"
|
|
bitfld.long 0x00 16. " CTRL_DLENERR ,Controls inducing of the data length error during I/O loopback test mode" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 8.--11. " IOLPBKTSTENA ,Module I/O loopback test enable key" "Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Enabled,Disabled,Disabled,Disabled,Disabled,Disabled"
|
|
sif cpuis("TMS570LS0232")
|
|
bitfld.long 0x00 3.--5. " ERRSCSPIN ,Inject error on chip-select pin number" "/SPISCS[0],/SPISCS[1],/SPISCS[2],/SPISCS[3],?..."
|
|
else
|
|
bitfld.long 0x00 3.--5. " ERRSCSPIN ,Inject error on chip-select pin number" "/SPISCS[0],/SPISCS[1],/SPISCS[2],/SPISCS[3],/SPISCS[4],/SPISCS[5],/SPISCS[6],/SPISCS[7]"
|
|
endif
|
|
bitfld.long 0x00 2. " CTRLSCSPINERR ,Enable/disable the injection of an error on the SPISCS[3:0] pins" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 1. " LPBK_TYPE ,Module I/O loopback type (analog/digital)" "Digital,Analog"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0xFFF7F800+0x134))&0x2)==0x2)
|
|
group.long 0x134++0x03
|
|
line.long 0x00 "IOLPBKTSTCR,SPI IO Loopback Test Control Register"
|
|
bitfld.long 0x00 24. " SCSFAILFLG ,Failure on SPISCS pin compare during analog loopback" "Not occurred,Occurred"
|
|
bitfld.long 0x00 20. " CTRL_BITERR ,Controls inducing of BITERR during I/O loopback test mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " CTRL_DESYNC ,Controls inducing of the desync error during I/O loopback test mode" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 18. " CTRL_PARERR ,Controls inducing of parity errors during I/O loopback test mode" "No error,Error"
|
|
bitfld.long 0x00 17. " CTRL_TIMEOUT ,Controls inducing of the timeout error during I/O loopbacK test mode" "No error,Error"
|
|
bitfld.long 0x00 16. " CTRL_DLENERR ,Controls inducing of the data length error during I/O loopback test mode" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 8.--11. " IOLPBKTSTENA ,Module I/O loopback test enable key" "Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Enabled,Disabled,Disabled,Disabled,Disabled,Disabled"
|
|
bitfld.long 0x00 3.--5. " ERRSCSPIN ,Inject error on chip-select pin number" "/SPISCS[0],/SPISCS[1],/SPISCS[2],/SPISCS[3],/SPISCS[4],/SPISCS[5],/SPISCS[6],/SPISCS[7]"
|
|
bitfld.long 0x00 2. " CTRLSCSPINERR ,Enable/disable the injection of an error on the SPISCS[3:0] pins" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 1. " LPBK_TYPE ,Module I/O loopback type (analog/digital)" "Digital,Analog"
|
|
bitfld.long 0x00 0. " RXP_ENA ,Enable analog loopback through the receive pin" "Transmit,Receive"
|
|
else
|
|
group.long 0x134++0x03
|
|
line.long 0x00 "IOLPBKTSTCR,SPI IO Loopback Test Control Register"
|
|
bitfld.long 0x00 24. " SCSFAILFLG ,Failure on SPISCS pin compare during analog loopback" "Not occurred,Occurred"
|
|
bitfld.long 0x00 20. " CTRL_BITERR ,Controls inducing of BITERR during I/O loopback test mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " CTRL_DESYNC ,Controls inducing of the desync error during I/O loopback test mode" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 18. " CTRL_PARERR ,Controls inducing of parity errors during I/O loopback test mode" "No error,Error"
|
|
bitfld.long 0x00 17. " CTRL_TIMEOUT ,Controls inducing of the timeout error during I/O loopbacK test mode" "No error,Error"
|
|
bitfld.long 0x00 16. " CTRL_DLENERR ,Controls inducing of the data length error during I/O loopback test mode" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 8.--11. " IOLPBKTSTENA ,Module I/O loopback test enable key" "Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Enabled,Disabled,Disabled,Disabled,Disabled,Disabled"
|
|
bitfld.long 0x00 3.--5. " ERRSCSPIN ,Inject error on chip-select pin number" "/SPISCS[0],/SPISCS[1],/SPISCS[2],/SPISCS[3],/SPISCS[4],/SPISCS[5],/SPISCS[6],/SPISCS[7]"
|
|
bitfld.long 0x00 2. " CTRLSCSPINERR ,Enable/disable the injection of an error on the SPISCS[3:0] pins" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 1. " LPBK_TYPE ,Module I/O loopback type (analog/digital)" "Digital,Analog"
|
|
endif
|
|
endif
|
|
sif (cpu()=="TMS570LC4357"||cpu()==("TMS570LS0332")||cpu()==("TMS570LS0432")||cpuis("TMS570LS1114*")||cpuis("TMS570LS1115*")||cpuis("TMS570LS1224*")||cpuis("TMS570LS1225*")||cpuis("TMS570LS1227*")||cpuis("TMS570LS0232")||cpuis("TMS570LS0714*")||cpuis("TMS570LS0914*"))
|
|
width 21.
|
|
newline
|
|
group.long 0x138++0x07
|
|
line.long 0x00 "EXTENDED_PRESCALE_1, SPI Extended Prescale Register 1"
|
|
hexmask.long.word 0x00 16.--26. 1. " EPRESCALE_FMT1 , Extended Prescale value for SPIFMT1"
|
|
hexmask.long.word 0x00 0.--10. 1. " EPRESCALE_FMT0 , Extended Prescale value for SPIFMT0"
|
|
line.long 0x04 "EXTENDED_PRESCALE_2, SPI Extended Prescale Register 2"
|
|
hexmask.long.word 0x04 16.--26. 1. " EPRESCALE_FMT3 , Extended Prescale value for SPIFMT3"
|
|
hexmask.long.word 0x04 0.--10. 1. " EPRESCALE_FMT2 , Extended Prescale value for SPIFMT2"
|
|
endif
|
|
sif !cpuis("TMS570LS0232")&&!cpuis("TMS570LS0714*")&&!cpuis("TMS570LS0914*")
|
|
sif (cpu()=="TMS570LC4357"||cpu()==("TMS570LS0332")||cpu()==("TMS570LS0432")||cpuis("TMS570LS1114*")||cpuis("TMS570LS1115*")||cpuis("TMS570LS1224*")||cpuis("TMS570LS1225*")||cpuis("TMS570LS1227*"))
|
|
sif cpuis("TMS570LC4357")
|
|
group.long 0x140++0x03
|
|
line.long 0x00 "ECCDIAG_CTRL, ECC Diagnostic Control register"
|
|
bitfld.long 0x00 0.--3. " ECCDIAG_EN , ECC Diagnostic mode Enable Key bits" "Disabled,Disabled,Disabled,Disabled,Disabled,Enabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled"
|
|
endif
|
|
if ((per.l(ad:0xFFF7F800+0x140)&0x5)==0x5)
|
|
group.long 0x144++0x03
|
|
line.long 0x00 "ECCDIAG_STAT, ECC Diagnostic Status register"
|
|
eventfld.long 0x00 17. " DEFLG[1] , Double bit Error is detected for RXRAM" "No error,Error"
|
|
eventfld.long 0x00 16. " DEFLG[0] , Double bit Error is detected for TXRAM" "No error,Error"
|
|
eventfld.long 0x00 1. " SEFLG[1] , Single bit Error is detected for RXRAM" "No error,Error"
|
|
eventfld.long 0x00 0. " SEFLG[0] , Single bit Error is detected for TXRAM" "No error,Error"
|
|
else
|
|
hgroup.long 0x144++0x03
|
|
hide.long 0x00 "ECCDIAG_STAT, ECC Diagnostic Status register"
|
|
in
|
|
endif
|
|
hgroup.long 0x148++0x03
|
|
hide.long 0x00 "SBERRADDR1, Single Bit Error Address Register - RXRAM"
|
|
in
|
|
hgroup.long 0x14C++0x03
|
|
hide.long 0x00 "SBERRADDR0, Single Bit Error Address Register - TXRAM"
|
|
in
|
|
endif
|
|
endif
|
|
sif cpuis("TMS570LS0232")||cpuis("TMS570LS0714*")||cpuis("TMS570LS0914*")
|
|
endian.be
|
|
endif
|
|
width 0xB
|
|
tree.end
|
|
tree.end
|
|
else
|
|
tree.open "MibSPI (Multi-Buffered Serial Peripheral Interface Module)"
|
|
tree "MibSPI"
|
|
base ad:0xFFF7F400
|
|
width 17.
|
|
sif cpuis("TMS570LS0232")||cpuis("TMS570LS0714*")||cpuis("TMS570LS0914*")
|
|
endian.be
|
|
endif
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "SPIGCR0,SPI Global Control Register 0"
|
|
bitfld.long 0x00 0. " NRESET ,Reset bit for the module" "No reset,Reset"
|
|
group.long 0x04++0x0F
|
|
line.long 0x00 "SPIGCR1,SPI Global Control Register 1"
|
|
bitfld.long 0x00 24. " SPIEN ,SPI enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " LOOPBACK ,Internal loop-back test mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " POWERDOWN ,SPI state machine enters a power-down state" "No power-down,Power-down"
|
|
newline
|
|
bitfld.long 0x00 1. " CLKMOD ,Clock mode" "External,Internally"
|
|
bitfld.long 0x00 0. " MASTER ,SPISIMO/SPISOMI pin direction determination" "Input/output,Output/input"
|
|
line.long 0x04 "SPIINT0,SPI Interrupt Register"
|
|
bitfld.long 0x04 24. " ENABLEHIGHZ ,SPIENA pin high-impedance enable" "Inactive,Active"
|
|
bitfld.long 0x04 16. " DMAREQEN ,DMA request enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 9. " TXINTENA ,TX interrupt flag enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x04 8. " RXINTENA ,RX interrupt flag enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 6. " RXOVRNINTENA ,Overrun interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 4. " BITERRENA ,Enables interrupt on bit error" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x04 3. " DESYNCENA ,Enables interrupt on desynchronized slave" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " PARERRENA ,Enables interrupt-on-parity-error" "Disabled,Enabled"
|
|
bitfld.long 0x04 1. " TIMEOUTENA ,Enables interrupt on ENA signal time-out" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x04 0. " DLENERRENA ,Data length error interrupt enable" "Disabled,Enabled"
|
|
line.long 0x08 "SPILVL,SPI Interrupt Level Register"
|
|
bitfld.long 0x08 9. " TXINTLVL ,Transmit interrupt level" "INT0,INT1"
|
|
bitfld.long 0x08 8. " RXINTLVL ,Receive interrupt level" "INT0,INT1"
|
|
sif !cpuis("TMS570LS0232")
|
|
bitfld.long 0x08 6. " RXOVRNINTLVL ,Receive overrun interrupt level" "INT0,INT1"
|
|
endif
|
|
newline
|
|
bitfld.long 0x08 4. " BITERRLVL ,Bit error interrupt level" "INT0,INT1"
|
|
bitfld.long 0x08 3. " DESYNCLVL ,Desynchronized slave interrupt level (master mode only)" "INT0,INT1"
|
|
bitfld.long 0x08 2. " PARERRLVL ,Parity error interrupt level" "INT0,INT1"
|
|
newline
|
|
bitfld.long 0x08 1. " TIMEOUTLVL ,SPIENA pin time-out interrupt level" "INT0,INT1"
|
|
bitfld.long 0x08 0. " DLENERRLVL ,Data length error interrupt level (line) select" "INT0,INT1"
|
|
line.long 0x0C "SPIFLG,SPI Flag Register"
|
|
bitfld.long 0x0C 24. " BUFINITACTIVE ,Indicates the status of multi-buffer initialization process" "Completed,Not completed"
|
|
bitfld.long 0x0C 9. " TXINTFLG ,Transmitter-empty interrupt flag" "No interrupt,Interrupt"
|
|
eventfld.long 0x0C 8. " RXINTFLG ,Receiver-full interrupt flag" "No interrupt,Interrupt"
|
|
newline
|
|
eventfld.long 0x0C 6. " RXOVRNINTFLG ,Overrun interrupt enable" "Disabled,Enabled"
|
|
eventfld.long 0x0C 4. " BITERRFLG ,Enables interrupt on bit error" "Disabled,Enabled"
|
|
eventfld.long 0x0C 3. " DESYNCFLG ,Enables interrupt on desynchronized slave" "No interrupt,Interrupt"
|
|
newline
|
|
eventfld.long 0x0C 2. " PARITYERRFLG ,Enables interrupt-on-parity-error" "No error,Error"
|
|
eventfld.long 0x0C 1. " TIMEOUTFLG ,Enables interrupt on ENA signal time-out" "No interrupt,Interrupt"
|
|
eventfld.long 0x0C 0. " DLENERRFLG ,Data length error interrupt enable" "No interrupt,Interrupt"
|
|
group.long 0x14++0x23
|
|
line.long 0x00 "SPIPC0,SPI Pin Control Register 0"
|
|
sif !cpuis("TMS570LS0232")&&!cpuis("TMS570LS0332")&&!cpuis("TMS570LS0432")
|
|
bitfld.long 0x00 31. " SOMIFUN7 ,SPISOMI[7] pin function" "GIO,SPI"
|
|
bitfld.long 0x00 30. " SOMIFUN6 ,SPISOMI[6] pin function" "GIO,SPI"
|
|
bitfld.long 0x00 29. " SOMIFUN5 ,SPISOMI[5] pin function" "GIO,SPI"
|
|
newline
|
|
bitfld.long 0x00 28. " SOMIFUN4 ,SPISOMI[4] pin function" "GIO,SPI"
|
|
bitfld.long 0x00 27. " SOMIFUN3 ,SPISOMI[3] pin function" "GIO,SPI"
|
|
bitfld.long 0x00 26. " SOMIFUN2 ,SPISOMI[2] pin function" "GIO,SPI"
|
|
newline
|
|
bitfld.long 0x00 25. " SOMIFUN1 ,SPISOMI[1] pin function" "GIO,SPI"
|
|
bitfld.long 0x00 24. " SOMIFUN0 ,SPISOMI[0] pin function (mirror of bit 11)" "GIO,SPI"
|
|
bitfld.long 0x00 23. " SIMOFUN7 ,SPISIMO[7] pin function" "GIO,SPI"
|
|
newline
|
|
bitfld.long 0x00 22. " SIMOFUN6 ,SPISIMO[6] pin function" "GIO,SPI"
|
|
bitfld.long 0x00 21. " SIMOFUN5 ,SPISIMO[5] pin function" "GIO,SPI"
|
|
bitfld.long 0x00 20. " SIMOFUN4 ,SPISIMO[4] pin function" "GIO,SPI"
|
|
newline
|
|
bitfld.long 0x00 19. " SIMOFUN3 ,SPISIMO[3] pin function" "GIO,SPI"
|
|
bitfld.long 0x00 18. " SIMOFUN2 ,SPISIMO[2] pin function" "GIO,SPI"
|
|
bitfld.long 0x00 17. " SIMOFUN1 ,SPISIMO[1] pin function" "GIO,SPI"
|
|
newline
|
|
bitfld.long 0x00 16. " SIMOFUN0 ,SPISIMO[0] pin function (mirror of bit 10)" "GIO,SPI"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 11. " SOMIFUN0 ,SPISOMI[0] pin function" "GIO,SPI"
|
|
bitfld.long 0x00 10. " SIMOFUN0 ,SPISIMO[0] pin function" "GIO,SPI"
|
|
newline
|
|
bitfld.long 0x00 9. " CLKFUN ,SPI clock function" "GIO,SPI"
|
|
bitfld.long 0x00 8. " ENAFUN ,SPIENA function" "GIO,SPI"
|
|
bitfld.long 0x00 7. " SCSFUN7 ,SPISCS7 function 7" "GIO,SPI"
|
|
newline
|
|
bitfld.long 0x00 6. " SCSFUN6 ,SPISCS6 function 6" "GIO,SPI"
|
|
bitfld.long 0x00 5. " SCSFUN5 ,SPISCS5 function 5" "GIO,SPI"
|
|
bitfld.long 0x00 4. " SCSFUN4 ,SPISCS4 function 4" "GIO,SPI"
|
|
newline
|
|
bitfld.long 0x00 3. " SCSFUN3 ,SPISCS3 function 3" "GIO,SPI"
|
|
bitfld.long 0x00 2. " SCSFUN2 ,SPISCS2 function 2" "GIO,SPI"
|
|
bitfld.long 0x00 1. " SCSFUN1 ,SPISCS1 function 1" "GIO,SPI"
|
|
newline
|
|
bitfld.long 0x00 0. " SCSFUN0 ,SPISCS0 function 0" "GIO,SPI"
|
|
line.long 0x04 "SPIPC1,SPI Pin Control Register 1"
|
|
bitfld.long 0x04 31. " SOMIDIR7 ,SPISOMI[7] pin direction" "GIO,SPI"
|
|
bitfld.long 0x04 30. " SOMIDIR6 ,SPISOMI[6] pin direction" "GIO,SPI"
|
|
bitfld.long 0x04 29. " SOMIDIR5 ,SPISOMI[5] pin direction" "GIO,SPI"
|
|
newline
|
|
bitfld.long 0x04 28. " SOMIDIR4 ,SPISOMI[4] pin direction" "GIO,SPI"
|
|
bitfld.long 0x04 27. " SOMIDIR3 ,SPISOMI[3] pin direction" "GIO,SPI"
|
|
bitfld.long 0x04 26. " SOMIDIR2 ,SPISOMI[2] pin direction" "GIO,SPI"
|
|
newline
|
|
bitfld.long 0x04 25. " SOMIDIR1 ,SPISOMI[1] pin direction" "GIO,SPI"
|
|
bitfld.long 0x04 24. " SOMIDIR0 ,SPISOMI[0] pin direction (mirror of bit 11)" "GIO,SPI"
|
|
bitfld.long 0x04 23. " SIMODIR7 ,SPISIMO[7] pin direction" "GIO,SPI"
|
|
newline
|
|
bitfld.long 0x04 22. " SIMODIR6 ,SPISIMO[6] pin direction" "GIO,SPI"
|
|
bitfld.long 0x04 21. " SIMODIR5 ,SPISIMO[5] pin direction" "GIO,SPI"
|
|
bitfld.long 0x04 20. " SIMODIR4 ,SPISIMO[4] pin direction" "GIO,SPI"
|
|
newline
|
|
bitfld.long 0x04 19. " SIMODIR3 ,SPISIMO[3] pin direction" "GIO,SPI"
|
|
bitfld.long 0x04 18. " SIMODIR2 ,SPISIMO[2] pin direction" "GIO,SPI"
|
|
bitfld.long 0x04 17. " SIMODIR1 ,SPISIMO[1] pin direction" "GIO,SPI"
|
|
newline
|
|
bitfld.long 0x04 16. " SIMODIR0 ,SPISIMO[0] pin direction (mirror of bit 10)" "GIO,SPI"
|
|
bitfld.long 0x04 11. " SOMIDIR0 ,SPISOMI[0] pin direction" "GIO,SPI"
|
|
bitfld.long 0x04 10. " SIMODIR0 ,SPISIMO[0] pin direction" "GIO,SPI"
|
|
newline
|
|
bitfld.long 0x04 9. " CLKDIR ,SPI clock direction" "GIO,SPI"
|
|
bitfld.long 0x04 8. " ENADIR ,SPIENA direction" "GIO,SPI"
|
|
bitfld.long 0x04 7. " SCSDIR7 ,SPISCS7 direction 7" "GIO,SPI"
|
|
newline
|
|
bitfld.long 0x04 6. " SCSDIR6 ,SPISCS6 direction 6" "GIO,SPI"
|
|
bitfld.long 0x04 5. " SCSDIR5 ,SPISCS5 direction 5" "GIO,SPI"
|
|
bitfld.long 0x04 4. " SCSDIR4 ,SPISCS4 direction 4" "GIO,SPI"
|
|
newline
|
|
bitfld.long 0x04 3. " SCSDIR3 ,SPISCS3 direction 3" "GIO,SPI"
|
|
bitfld.long 0x04 2. " SCSDIR2 ,SPISCS2 direction 2" "GIO,SPI"
|
|
bitfld.long 0x04 1. " SCSDIR1 ,SPISCS1 direction 1" "GIO,SPI"
|
|
newline
|
|
bitfld.long 0x04 0. " SCSDIR0 ,SPISCS0 direction 0" "GIO,SPI"
|
|
line.long 0x08 "SPIPC2,SPI Pin Control Register 2"
|
|
bitfld.long 0x08 31. " SOMIDIN7 ,SPISOMI[7] data in" "0,1"
|
|
bitfld.long 0x08 30. " SOMIDIN6 ,SPISOMI[6] data in" "0,1"
|
|
bitfld.long 0x08 29. " SOMIDIN5 ,SPISOMI[5] data in" "0,1"
|
|
newline
|
|
bitfld.long 0x08 28. " SOMIDIN4 ,SPISOMI[4] data in" "0,1"
|
|
bitfld.long 0x08 27. " SOMIDIN3 ,SPISOMI[3] data in" "0,1"
|
|
bitfld.long 0x08 26. " SOMIDIN2 ,SPISOMI[2] data in" "0,1"
|
|
newline
|
|
bitfld.long 0x08 25. " SOMIDIN1 ,SPISOMI[1] data in" "0,1"
|
|
bitfld.long 0x08 24. " SOMIDIN0 ,SPISOMI[0] data in (mirror of bit 11)" "0,1"
|
|
bitfld.long 0x08 23. " SIMODIN7 ,SPISIMO[7] data in" "0,1"
|
|
newline
|
|
bitfld.long 0x08 22. " SIMODIN6 ,SPISIMO[6] data in" "0,1"
|
|
bitfld.long 0x08 21. " SIMODIN5 ,SPISIMO[5] data in" "0,1"
|
|
bitfld.long 0x08 20. " SIMODIN4 ,SPISIMO[4] data in" "0,1"
|
|
newline
|
|
bitfld.long 0x08 19. " SIMODIN3 ,SPISIMO[3] data in" "0,1"
|
|
bitfld.long 0x08 18. " SIMODIN2 ,SPISIMO[2] data in" "0,1"
|
|
bitfld.long 0x08 17. " SIMODIN1 ,SPISIMO[1] data in" "0,1"
|
|
newline
|
|
bitfld.long 0x08 16. " SIMODIN0 ,SPISIMO[0] data in (mirror of bit 10)" "0,1"
|
|
bitfld.long 0x08 11. " SOMIDIN0 ,SPISOMI[0] data in" "0,1"
|
|
bitfld.long 0x08 10. " SIMODIN0 ,SPISIMO[0] data in" "0,1"
|
|
newline
|
|
bitfld.long 0x08 9. " CLKDIN ,SPI clock data in" "0,1"
|
|
bitfld.long 0x08 8. " ENADIN ,SPIENA data in" "0,1"
|
|
bitfld.long 0x08 7. " SCSDIN7 ,SPISCS7 data in" "0,1"
|
|
newline
|
|
bitfld.long 0x08 6. " SCSDIN6 ,SPISCS6 data in" "0,1"
|
|
bitfld.long 0x08 5. " SCSDIN5 ,SPISCS5 data in" "0,1"
|
|
bitfld.long 0x08 4. " SCSDIN4 ,SPISCS4 data in" "0,1"
|
|
newline
|
|
bitfld.long 0x08 3. " SCSDIN3 ,SPISCS3 data in" "0,1"
|
|
bitfld.long 0x08 2. " SCSDIN2 ,SPISCS2 data in" "0,1"
|
|
bitfld.long 0x08 1. " SCSDIN1 ,SPISCS1 data in" "0,1"
|
|
newline
|
|
bitfld.long 0x08 0. " SCSDIN0 ,SPISCS0 direction 0" "0,1"
|
|
line.long 0x0C "SPIPC3,SPI Pin Control Register 3"
|
|
bitfld.long 0x0C 31. " SOMIDOUT7 ,SPISOMI[7] data out write" "0,1"
|
|
bitfld.long 0x0C 30. " SOMIDOUT6 ,SPISOMI[6] data out write" "0,1"
|
|
bitfld.long 0x0C 29. " SOMIDOUT5 ,SPISOMI[5] data out write" "0,1"
|
|
newline
|
|
bitfld.long 0x0C 28. " SOMIDOUT4 ,SPISOMI[4] data out write" "0,1"
|
|
bitfld.long 0x0C 27. " SOMIDOUT3 ,SPISOMI[3] data out write" "0,1"
|
|
bitfld.long 0x0C 26. " SOMIDOUT2 ,SPISOMI[2] data out write" "0,1"
|
|
newline
|
|
bitfld.long 0x0C 25. " SOMIDOUT1 ,SPISOMI[1] data out write" "0,1"
|
|
bitfld.long 0x0C 24. " SOMIDOUT0 ,SPISOMI[0] data out write (mirror of bit 11)" "0,1"
|
|
bitfld.long 0x0C 23. " SIMODOUT7 ,SPISIMO[7] data out write" "0,1"
|
|
newline
|
|
bitfld.long 0x0C 22. " SIMODOUT6 ,SPISIMO[6] data out write" "0,1"
|
|
bitfld.long 0x0C 21. " SIMODOUT5 ,SPISIMO[5] data out write" "0,1"
|
|
bitfld.long 0x0C 20. " SIMODOUT4 ,SPISIMO[4] data out write" "0,1"
|
|
newline
|
|
bitfld.long 0x0C 19. " SIMODOUT3 ,SPISIMO[3] data out write" "0,1"
|
|
bitfld.long 0x0C 18. " SIMODOUT2 ,SPISIMO[2] data out write" "0,1"
|
|
bitfld.long 0x0C 17. " SIMODOUT1 ,SPISIMO[1] data out write" "0,1"
|
|
newline
|
|
bitfld.long 0x0C 16. " SIMODOUT0 ,SPISIMO[0] data out write (mirror of bit 10)" "0,1"
|
|
bitfld.long 0x0C 11. " SOMIDOUT0 ,SPISOMI[0] data out write" "0,1"
|
|
bitfld.long 0x0C 10. " SIMODOUT0 ,SPISIMO[0] data out write" "0,1"
|
|
newline
|
|
bitfld.long 0x0C 9. " CLKDOUT ,SPI clock data out write" "0,1"
|
|
bitfld.long 0x0C 8. " ENADOUT ,SPIENA data out write" "0,1"
|
|
bitfld.long 0x0C 7. " SCSDOUT7 ,SPISCS7 data out write" "0,1"
|
|
newline
|
|
bitfld.long 0x0C 6. " SCSDOUT6 ,SPISCS6 data out write" "0,1"
|
|
bitfld.long 0x0C 5. " SCSDOUT5 ,SPISCS5 data out write" "0,1"
|
|
bitfld.long 0x0C 4. " SCSDOUT4 ,SPISCS4 data out write" "0,1"
|
|
newline
|
|
bitfld.long 0x0C 3. " SCSDOUT3 ,SPISCS3 data out write" "0,1"
|
|
bitfld.long 0x0C 2. " SCSDOUT2 ,SPISCS2 data out write" "0,1"
|
|
bitfld.long 0x0C 1. " SCSDOUT1 ,SPISCS1 data out write" "0,1"
|
|
newline
|
|
bitfld.long 0x0C 0. " SCSDOUT0 ,SPISCS0 data out write" "0,1"
|
|
line.long 0x10 "SPIPC4,SPI Pin Control Register 4"
|
|
bitfld.long 0x10 31. " SOMISET7 ,SPISOMI[7] data out set" "0,1"
|
|
bitfld.long 0x10 30. " SOMISET6 ,SPISOMI[6] data out set" "0,1"
|
|
bitfld.long 0x10 29. " SOMISET5 ,SPISOMI[5] data out set" "0,1"
|
|
newline
|
|
bitfld.long 0x10 28. " SOMISET4 ,SPISOMI[4] data out set" "0,1"
|
|
bitfld.long 0x10 27. " SOMISET3 ,SPISOMI[3] data out set" "0,1"
|
|
bitfld.long 0x10 26. " SOMISET2 ,SPISOMI[2] data out set" "0,1"
|
|
newline
|
|
bitfld.long 0x10 25. " SOMISET1 ,SPISOMI[1] data out set" "0,1"
|
|
bitfld.long 0x10 24. " SOMISET0 ,SPISOMI[0] data out set (mirror of bit 11)" "0,1"
|
|
bitfld.long 0x10 23. " SIMOSET7 ,SPISIMO[7] data out set" "0,1"
|
|
newline
|
|
bitfld.long 0x10 22. " SIMOSET6 ,SPISIMO[6] data out set" "0,1"
|
|
bitfld.long 0x10 21. " SIMOSET5 ,SPISIMO[5] data out set" "0,1"
|
|
bitfld.long 0x10 20. " SIMOSET4 ,SPISIMO[4] data out set" "0,1"
|
|
newline
|
|
bitfld.long 0x10 19. " SIMOSET3 ,SPISIMO[3] data out set" "0,1"
|
|
bitfld.long 0x10 18. " SIMOSET2 ,SPISIMO[2] data out set" "0,1"
|
|
bitfld.long 0x10 17. " SIMOSET1 ,SPISIMO[1] data out set" "0,1"
|
|
newline
|
|
bitfld.long 0x10 16. " SIMOSET0 ,SPISIMO[0] data out set (mirror of bit 10)" "0,1"
|
|
bitfld.long 0x10 11. " SOMISET0 ,SPISOMI[0] data out set" "0,1"
|
|
bitfld.long 0x10 10. " SIMOSET0 ,SPISIMO[0] data out set" "0,1"
|
|
newline
|
|
bitfld.long 0x10 9. " CLKSET ,SPI clock data out set" "0,1"
|
|
bitfld.long 0x10 8. " ENASET ,SPIENA data out set" "0,1"
|
|
bitfld.long 0x10 7. " SCSSET7 ,SPISCS7 data out set" "0,1"
|
|
newline
|
|
bitfld.long 0x10 6. " SCSSET6 ,SPISCS6 data out set" "0,1"
|
|
bitfld.long 0x10 5. " SCSSET5 ,SPISCS5 data out set" "0,1"
|
|
bitfld.long 0x10 4. " SCSSET4 ,SPISCS4 data out set" "0,1"
|
|
newline
|
|
bitfld.long 0x10 3. " SCSSET3 ,SPISCS3 data out set" "0,1"
|
|
bitfld.long 0x10 2. " SCSSET2 ,SPISCS2 data out set" "0,1"
|
|
bitfld.long 0x10 1. " SCSSET1 ,SPISCS1 data out set" "0,1"
|
|
newline
|
|
bitfld.long 0x10 0. " SCSSET0 ,SPISCS0 data out set" "0,1"
|
|
line.long 0x14 "SPIPC5,SPI Pin Control Register 5"
|
|
bitfld.long 0x14 31. " SOMICLR7 ,SPISOMI[7] data out clear" "0,1"
|
|
bitfld.long 0x14 30. " SOMICLR6 ,SPISOMI[6] data out clear" "0,1"
|
|
bitfld.long 0x14 29. " SOMICLR5 ,SPISOMI[5] data out clear" "0,1"
|
|
newline
|
|
bitfld.long 0x14 28. " SOMICLR4 ,SPISOMI[4] data out clear" "0,1"
|
|
bitfld.long 0x14 27. " SOMICLR3 ,SPISOMI[3] data out clear" "0,1"
|
|
bitfld.long 0x14 26. " SOMICLR2 ,SPISOMI[2] data out clear" "0,1"
|
|
newline
|
|
bitfld.long 0x14 25. " SOMICLR1 ,SPISOMI[1] data out clear" "0,1"
|
|
bitfld.long 0x14 24. " SOMICLR0 ,SPISOMI[0] data out clear (mirror of bit 11)" "0,1"
|
|
bitfld.long 0x14 23. " SIMOCLR7 ,SPISIMO[7] data out clear" "0,1"
|
|
newline
|
|
bitfld.long 0x14 22. " SIMOCLR6 ,SPISIMO[6] data out clear" "0,1"
|
|
bitfld.long 0x14 21. " SIMOCLR5 ,SPISIMO[5] data out clear" "0,1"
|
|
bitfld.long 0x14 20. " SIMOCLR4 ,SPISIMO[4] data out clear" "0,1"
|
|
newline
|
|
bitfld.long 0x14 19. " SIMOCLR3 ,SPISIMO[3] data out clear" "0,1"
|
|
bitfld.long 0x14 18. " SIMOCLR2 ,SPISIMO[2] data out clear" "0,1"
|
|
bitfld.long 0x14 17. " SIMOCLR1 ,SPISIMO[1] data out clear" "0,1"
|
|
newline
|
|
bitfld.long 0x14 16. " SIMOCLR0 ,SPISIMO[0] data out clear (mirror of bit 10)" "0,1"
|
|
bitfld.long 0x14 11. " SOMICLR0 ,SPISOMI[0] data out clear" "0,1"
|
|
bitfld.long 0x14 10. " SIMOCLR0 ,SPISIMO[0] data out clear" "0,1"
|
|
newline
|
|
bitfld.long 0x14 9. " CLKCLR ,SPI clock data out clear" "0,1"
|
|
bitfld.long 0x14 8. " ENACLR ,SPIENA data out clear" "0,1"
|
|
bitfld.long 0x14 7. " SCSCLR7 ,SPISCS7 data out clear" "0,1"
|
|
newline
|
|
bitfld.long 0x14 6. " SCSCLR6 ,SPISCS6 data out clear" "0,1"
|
|
bitfld.long 0x14 5. " SCSCLR5 ,SPISCS5 data out clear" "0,1"
|
|
bitfld.long 0x14 4. " SCSCLR4 ,SPISCS4 data out clear" "0,1"
|
|
newline
|
|
bitfld.long 0x14 3. " SCSCLR3 ,SPISCS3 data out clear" "0,1"
|
|
bitfld.long 0x14 2. " SCSCLR2 ,SPISCS2 data out clear" "0,1"
|
|
bitfld.long 0x14 1. " SCSCLR1 ,SPISCS1 data out clear" "0,1"
|
|
newline
|
|
bitfld.long 0x14 0. " SCSCLR0 ,SPISCS0 data out clear" "0,1"
|
|
line.long 0x18 "SPIPC6,SPI Pin Control Register 6"
|
|
bitfld.long 0x18 31. " SOMIPDR7 ,SPISOMI[7] open drain enable" "Disabled,Enabled"
|
|
bitfld.long 0x18 30. " SOMIPDR6 ,SPISOMI[6] open drain enable" "Disabled,Enabled"
|
|
bitfld.long 0x18 29. " SOMIPDR5 ,SPISOMI[5] open drain enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x18 28. " SOMIPDR4 ,SPISOMI[4] open drain enable" "Disabled,Enabled"
|
|
bitfld.long 0x18 27. " SOMIPDR3 ,SPISOMI[3] open drain enable" "Disabled,Enabled"
|
|
bitfld.long 0x18 26. " SOMIPDR2 ,SPISOMI[2] open drain enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x18 25. " SOMIPDR1 ,SPISOMI[1] open drain enable" "Disabled,Enabled"
|
|
bitfld.long 0x18 24. " SOMIPDR0 ,SPISOMI[0] open drain enable (mirror of bit 11)" "Disabled,Enabled"
|
|
bitfld.long 0x18 23. " SIMOPDR7 ,SPISIMO[7] open drain enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x18 22. " SIMOPDR6 ,SPISIMO[6] open drain enable" "Disabled,Enabled"
|
|
bitfld.long 0x18 21. " SIMOPDR5 ,SPISIMO[5] open drain enable" "Disabled,Enabled"
|
|
bitfld.long 0x18 20. " SIMOPDR4 ,SPISIMO[4] open drain enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x18 19. " SIMOPDR3 ,SPISIMO[3] open drain enable" "Disabled,Enabled"
|
|
bitfld.long 0x18 18. " SIMOPDR2 ,SPISIMO[2] open drain enable" "Disabled,Enabled"
|
|
bitfld.long 0x18 17. " SIMOPDR1 ,SPISIMO[1] open drain enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x18 16. " SIMOPDR0 ,SPISIMO[0] open drain enable (mirror of bit 10)" "Disabled,Enabled"
|
|
bitfld.long 0x18 11. " SOMIPDR0 ,SPISOMI[0] open drain enable" "Disabled,Enabled"
|
|
bitfld.long 0x18 10. " SIMOPDR0 ,SPISIMO[0] open drain enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x18 9. " CLKPDR ,SPI clock open drain enable" "Disabled,Enabled"
|
|
bitfld.long 0x18 8. " ENAPDR ,SPIENA open drain enable" "Disabled,Enabled"
|
|
bitfld.long 0x18 7. " SCSPDR7 ,SPISCS7 open drain enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x18 6. " SCSPDR6 ,SPISCS6 open drain enable" "Disabled,Enabled"
|
|
bitfld.long 0x18 5. " SCSPDR5 ,SPISCS5 open drain enable" "Disabled,Enabled"
|
|
bitfld.long 0x18 4. " SCSPDR4 ,SPISCS4 open drain enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x18 3. " SCSPDR3 ,SPISCS3 open drain enable" "Disabled,Enabled"
|
|
bitfld.long 0x18 2. " SCSPDR2 ,SPISCS2 open drain enable" "Disabled,Enabled"
|
|
bitfld.long 0x18 1. " SCSPDR1 ,SPISCS1 open drain enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x18 0. " SCSPDR0 ,SPISCS0 open drain enable" "Disabled,Enabled"
|
|
line.long 0x1C "SPIPC7,SPI Pin Control Register 7"
|
|
bitfld.long 0x1C 31. " SOMIPDIS7 ,SPISOMI[7] pull control enable/disable" "No,Yes"
|
|
bitfld.long 0x1C 30. " SOMIPDIS6 ,SPISOMI[6] pull control enable/disable" "No,Yes"
|
|
bitfld.long 0x1C 29. " SOMIPDIS5 ,SPISOMI[5] pull control enable/disable" "No,Yes"
|
|
newline
|
|
bitfld.long 0x1C 28. " SOMIPDIS4 ,SPISOMI[4] pull control enable/disable" "No,Yes"
|
|
bitfld.long 0x1C 27. " SOMIPDIS3 ,SPISOMI[3] pull control enable/disable" "No,Yes"
|
|
bitfld.long 0x1C 26. " SOMIPDIS2 ,SPISOMI[2] pull control enable/disable" "No,Yes"
|
|
newline
|
|
bitfld.long 0x1C 25. " SOMIPDIS1 ,SPISOMI[1] pull control enable/disable" "No,Yes"
|
|
bitfld.long 0x1C 24. " SOMIPDIS0 ,SPISOMI[0] pull control enable/disable (mirror of bit 11)" "No,Yes"
|
|
bitfld.long 0x1C 23. " SIMOPDIS7 ,SPISIMO[7] pull control enable/disable" "No,Yes"
|
|
newline
|
|
bitfld.long 0x1C 22. " SIMOPDIS6 ,SPISIMO[6] pull control enable/disable" "No,Yes"
|
|
bitfld.long 0x1C 21. " SIMOPDIS5 ,SPISIMO[5] pull control enable/disable" "No,Yes"
|
|
bitfld.long 0x1C 20. " SIMOPDIS4 ,SPISIMO[4] pull control enable/disable" "No,Yes"
|
|
newline
|
|
bitfld.long 0x1C 19. " SIMOPDIS3 ,SPISIMO[3] pull control enable/disable" "No,Yes"
|
|
bitfld.long 0x1C 18. " SIMOPDIS2 ,SPISIMO[2] pull control enable/disable" "No,Yes"
|
|
bitfld.long 0x1C 17. " SIMOPDIS1 ,SPISIMO[1] pull control enable/disable" "No,Yes"
|
|
newline
|
|
bitfld.long 0x1C 16. " SIMOPDIS0 ,SPISIMO[0] pull control enable/disable (mirror of bit 10)" "No,Yes"
|
|
bitfld.long 0x1C 11. " SOMIPDIS0 ,SPISOMI[0] pull control enable/disable" "No,Yes"
|
|
bitfld.long 0x1C 10. " SIMOPDIS0 ,SPISIMO[0] pull control enable/disable" "No,Yes"
|
|
newline
|
|
bitfld.long 0x1C 9. " CLKPDIS ,SPI clock pull control enable/disable" "No,Yes"
|
|
bitfld.long 0x1C 8. " ENAPDIS ,SPIENA pull control enable/disable" "No,Yes"
|
|
bitfld.long 0x1C 7. " SCSPDIS7 ,SPISCS7 pull control enable/disable" "No,Yes"
|
|
newline
|
|
bitfld.long 0x1C 6. " SCSPDIS6 ,SPISCS6 pull control enable/disable" "No,Yes"
|
|
bitfld.long 0x1C 5. " SCSPDIS5 ,SPISCS5 pull control enable/disable" "No,Yes"
|
|
bitfld.long 0x1C 4. " SCSPDIS4 ,SPISCS4 pull control enable/disable" "No,Yes"
|
|
newline
|
|
bitfld.long 0x1C 3. " SCSPDIS3 ,SPISCS3 pull control enable/disable" "No,Yes"
|
|
bitfld.long 0x1C 2. " SCSPDIS2 ,SPISCS2 pull control enable/disable" "No,Yes"
|
|
bitfld.long 0x1C 1. " SCSPDIS1 ,SPISCS1 pull control enable/disable" "No,Yes"
|
|
newline
|
|
bitfld.long 0x1C 0. " SCSPDIS0 ,SPISCS0 pull control enable/disable" "No,Yes"
|
|
line.long 0x20 "SPIPC8,SPI Pin Control Register 8"
|
|
bitfld.long 0x20 31. " SOMIPSEL7 ,SPISOMI[7] pull select" "Pull down,Pull up"
|
|
bitfld.long 0x20 30. " SOMIPSEL6 ,SPISOMI[6] pull select" "Pull down,Pull up"
|
|
bitfld.long 0x20 29. " SOMIPSEL5 ,SPISOMI[5] pull select" "Pull down,Pull up"
|
|
newline
|
|
bitfld.long 0x20 28. " SOMIPSEL4 ,SPISOMI[4] pull select" "Pull down,Pull up"
|
|
bitfld.long 0x20 27. " SOMIPSEL3 ,SPISOMI[3] pull select" "Pull down,Pull up"
|
|
bitfld.long 0x20 26. " SOMIPSEL2 ,SPISOMI[2] pull select" "Pull down,Pull up"
|
|
newline
|
|
bitfld.long 0x20 25. " SOMIPSEL1 ,SPISOMI[1] pull select" "Pull down,Pull up"
|
|
bitfld.long 0x20 24. " SOMIPSEL0 ,SPISOMI[0] pull select (mirror of bit 11)" "Pull down,Pull up"
|
|
bitfld.long 0x20 23. " SIMOPSEL7 ,SPISIMO[7] pull select" "Pull down,Pull up"
|
|
newline
|
|
bitfld.long 0x20 22. " SIMOPSEL6 ,SPISIMO[6] pull select" "Pull down,Pull up"
|
|
bitfld.long 0x20 21. " SIMOPSEL5 ,SPISIMO[5] pull select" "Pull down,Pull up"
|
|
bitfld.long 0x20 20. " SIMOPSEL4 ,SPISIMO[4] pull select" "Pull down,Pull up"
|
|
newline
|
|
bitfld.long 0x20 19. " SIMOPSEL3 ,SPISIMO[3] pull select" "Pull down,Pull up"
|
|
bitfld.long 0x20 18. " SIMOPSEL2 ,SPISIMO[2] pull select" "Pull down,Pull up"
|
|
bitfld.long 0x20 17. " SIMOPSEL1 ,SPISIMO[1] pull select" "Pull down,Pull up"
|
|
newline
|
|
bitfld.long 0x20 16. " SIMOPSEL0 ,SPISIMO[0] pull select (mirror of bit 10)" "Pull down,Pull up"
|
|
bitfld.long 0x20 11. " SOMIPSEL0 ,SPISOMI[0] pull select" "Pull down,Pull up"
|
|
bitfld.long 0x20 10. " SIMOPSEL0 ,SPISIMO[0] pull select" "Pull down,Pull up"
|
|
newline
|
|
bitfld.long 0x20 9. " CLKPSEL ,SPI clock pull select" "Pull down,Pull up"
|
|
bitfld.long 0x20 8. " ENAPSEL ,SPIENA pull select" "Pull down,Pull up"
|
|
bitfld.long 0x20 7. " SCSPSEL7 ,SPISCS7 pull select" "Pull down,Pull up"
|
|
newline
|
|
bitfld.long 0x20 6. " SCSPSEL6 ,SPISCS6 pull select" "Pull down,Pull up"
|
|
bitfld.long 0x20 5. " SCSPSEL5 ,SPISCS5 pull select" "Pull down,Pull up"
|
|
bitfld.long 0x20 4. " SCSPSEL4 ,SPISCS4 pull select" "Pull down,Pull up"
|
|
newline
|
|
bitfld.long 0x20 3. " SCSPSEL3 ,SPISCS3 pull select" "Pull down,Pull up"
|
|
bitfld.long 0x20 2. " SCSPSEL2 ,SPISCS2 pull select" "Pull down,Pull up"
|
|
bitfld.long 0x20 1. " SCSPSEL1 ,SPISCS1 pull select" "Pull down,Pull up"
|
|
newline
|
|
bitfld.long 0x20 0. " SCSPSEL0 ,SPISCS0 pull select" "Pull down,Pull up"
|
|
group.long 0x38++0x07
|
|
line.long 0x00 "SPIDAT0,SPI Transmit Data Register 0"
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,SPI transmit data"
|
|
line.long 0x04 "SPIDAT1,Transmit Data Register 1"
|
|
bitfld.long 0x04 28. " CSHOLD ,Chip select hold mode" "Inactive,Active"
|
|
bitfld.long 0x04 26. " WDEL ,Enable the delay counter at the end of the current transaction" "No delay,After transaction"
|
|
bitfld.long 0x04 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
newline
|
|
hexmask.long.byte 0x04 16.--23. 1. " CSNR ,Chip select number"
|
|
hexmask.long.word 0x04 0.--15. 1. " TXDATA ,Transfer data"
|
|
hgroup.long 0x40++0x03
|
|
hide.long 0x00 "SPIBUF,SPI Receive Buffer Register"
|
|
in
|
|
rgroup.long 0x44++0x03
|
|
line.long 0x00 "SPIEMU,SPI Emulation Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " EMU_RXDATA ,SPI receive data"
|
|
sif cpuis("TMS570LS0232")||cpuis("TMS570LS0714*")||cpuis("TMS570LS0914*")
|
|
group.long 0x48++0x03
|
|
line.long 0x00 "SPIDELAY,SPI Delay Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " C2TDELAY ,Chip-select-active to transmit-start delay"
|
|
hexmask.long.byte 0x00 16.--23. 1. " T2CDELAY ,Transmit-end-to-chip-select-inactive-delay"
|
|
hexmask.long.byte 0x00 8.--15. 1. " T2EDELAY ,Transmit-data-finished to ENA-pin-inactive time-out"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--7. 1. " C2EDELAY ,Chip-select-active to ENA-signal-active time-out"
|
|
else
|
|
rgroup.long 0x48++0x03
|
|
line.long 0x00 "SPIDELAY,SPI Delay Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " C2TDELAY ,Chip-select-active to transmit-start delay"
|
|
hexmask.long.byte 0x00 16.--23. 1. " T2CDELAY ,Transmit-end-to-chip-select-inactive-delay"
|
|
hexmask.long.byte 0x00 8.--15. 1. " T2EDELAY ,Transmit-data-finished to ENA-pin-inactive time-out"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--7. 1. " C2EDELAY ,Chip-select-active to ENA-signal-active time-out"
|
|
endif
|
|
group.long 0x4C++0x13
|
|
line.long 0x00 "SPIDEF,SPI Default Chip Select Register"
|
|
bitfld.long 0x00 7. " CSDEF7 ,Chip select default pattern 7" "0,1"
|
|
bitfld.long 0x00 6. " CSDEF6 ,Chip select default pattern 6" "0,1"
|
|
bitfld.long 0x00 5. " CSDEF5 ,Chip select default pattern 5" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. " CSDEF4 ,Chip select default pattern 4" "0,1"
|
|
bitfld.long 0x00 3. " CSDEF3 ,Chip select default pattern 3" "0,1"
|
|
bitfld.long 0x00 2. " CSDEF2 ,Chip select default pattern 2" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. " CSDEF1 ,Chip select default pattern 1" "0,1"
|
|
bitfld.long 0x00 0. " CSDEF0 ,Chip select default pattern 0" "0,1"
|
|
line.long 0x4 "SPIFMT0,SPI Data Format Register 0"
|
|
sif (cpuis("TMS570LS0332")||cpuis("TMS570LS0432")||cpuis("TMS570LS1114*")||cpuis("TMS570LS1115*")||cpuis("TMS570LS1224*")||cpuis("TMS570LS1225*")||cpuis("TMS570LS1227*")||cpuis("TMS570LS0232")||cpuis("TMS570LS0714*")||cpuis("TMS570LS0914*"))
|
|
hexmask.long.byte 0x4 24.--31. 1. " WDELAY ,Delay in between transmissions for data format 0"
|
|
else
|
|
bitfld.long 0x4 24.--29. " WDELAY ,Delay in between transmissions for data format 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
endif
|
|
bitfld.long 0x4 23. " PARPOL ,Parity polarity: even or odd" "Even,Odd"
|
|
newline
|
|
bitfld.long 0x4 22. " PARITYENA ,Parity enable for data format 0" "Disabled,Enabled"
|
|
bitfld.long 0x4 21. " WAITENA ,The master waits for the ENA signal from slave for data format 0" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x4 20. " SHIFTDIR ,Shift direction for data format $" "MSB,LSB"
|
|
sif (cpu()==("TMS570LS0332")||cpu()==("TMS570LS0432")||cpuis("TMS570LS1114*")||cpuis("TMS570LS1115*")||cpuis("TMS570LS1224*")||cpuis("TMS570LS1225*")||cpuis("TMS570LS1227*")||cpuis("TMS570LS0232")||cpuis("TMS570LS0714*")||cpuis("TMS570LS0914*"))
|
|
bitfld.long 0x4 19. " HDUPLEX_ENA0 ,Half Duplex transfer mode enable for Data Format 0" "Normal,RX/TX"
|
|
endif
|
|
newline
|
|
bitfld.long 0x4 18. " DISCSTIMERS ,Disable chip-select timers for this format" "No,Yes"
|
|
newline
|
|
bitfld.long 0x4 17. " POLARITY ,SPI data format 0 clock polarity" "Low,High"
|
|
bitfld.long 0x4 16. " PHASE ,SPI data format 0 clock delay" "Disabled,Enabled"
|
|
newline
|
|
hexmask.long.byte 0x4 8.--15. 1. " PRESCALE ,SPI data format 0 prescaler"
|
|
bitfld.long 0x4 0.--4. " CHARLEN ,SPI data format 0 data-word length" ",,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,?..."
|
|
line.long 0x8 "SPIFMT1,SPI Data Format Register 1"
|
|
sif (cpuis("TMS570LS0332")||cpuis("TMS570LS0432")||cpuis("TMS570LS1114*")||cpuis("TMS570LS1115*")||cpuis("TMS570LS1224*")||cpuis("TMS570LS1225*")||cpuis("TMS570LS1227*")||cpuis("TMS570LS0232")||cpuis("TMS570LS0714*")||cpuis("TMS570LS0914*"))
|
|
hexmask.long.byte 0x8 24.--31. 1. " WDELAY ,Delay in between transmissions for data format 1"
|
|
else
|
|
bitfld.long 0x8 24.--29. " WDELAY ,Delay in between transmissions for data format 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
endif
|
|
bitfld.long 0x8 23. " PARPOL ,Parity polarity: even or odd" "Even,Odd"
|
|
newline
|
|
bitfld.long 0x8 22. " PARITYENA ,Parity enable for data format 1" "Disabled,Enabled"
|
|
bitfld.long 0x8 21. " WAITENA ,The master waits for the ENA signal from slave for data format 1" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x8 20. " SHIFTDIR ,Shift direction for data format $" "MSB,LSB"
|
|
sif (cpu()==("TMS570LS0332")||cpu()==("TMS570LS0432")||cpuis("TMS570LS1114*")||cpuis("TMS570LS1115*")||cpuis("TMS570LS1224*")||cpuis("TMS570LS1225*")||cpuis("TMS570LS1227*")||cpuis("TMS570LS0232")||cpuis("TMS570LS0714*")||cpuis("TMS570LS0914*"))
|
|
bitfld.long 0x8 19. " HDUPLEX_ENA1 ,Half Duplex transfer mode enable for Data Format 1" "Normal,RX/TX"
|
|
endif
|
|
newline
|
|
bitfld.long 0x8 18. " DISCSTIMERS ,Disable chip-select timers for this format" "No,Yes"
|
|
newline
|
|
bitfld.long 0x8 17. " POLARITY ,SPI data format 1 clock polarity" "Low,High"
|
|
bitfld.long 0x8 16. " PHASE ,SPI data format 1 clock delay" "Disabled,Enabled"
|
|
newline
|
|
hexmask.long.byte 0x8 8.--15. 1. " PRESCALE ,SPI data format 1 prescaler"
|
|
bitfld.long 0x8 0.--4. " CHARLEN ,SPI data format 1 data-word length" ",,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,?..."
|
|
line.long 0xC "SPIFMT2,SPI Data Format Register 2"
|
|
sif (cpuis("TMS570LS0332")||cpuis("TMS570LS0432")||cpuis("TMS570LS1114*")||cpuis("TMS570LS1115*")||cpuis("TMS570LS1224*")||cpuis("TMS570LS1225*")||cpuis("TMS570LS1227*")||cpuis("TMS570LS0232")||cpuis("TMS570LS0714*")||cpuis("TMS570LS0914*"))
|
|
hexmask.long.byte 0xC 24.--31. 1. " WDELAY ,Delay in between transmissions for data format 2"
|
|
else
|
|
bitfld.long 0xC 24.--29. " WDELAY ,Delay in between transmissions for data format 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
endif
|
|
bitfld.long 0xC 23. " PARPOL ,Parity polarity: even or odd" "Even,Odd"
|
|
newline
|
|
bitfld.long 0xC 22. " PARITYENA ,Parity enable for data format 2" "Disabled,Enabled"
|
|
bitfld.long 0xC 21. " WAITENA ,The master waits for the ENA signal from slave for data format 2" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0xC 20. " SHIFTDIR ,Shift direction for data format $" "MSB,LSB"
|
|
sif (cpu()==("TMS570LS0332")||cpu()==("TMS570LS0432")||cpuis("TMS570LS1114*")||cpuis("TMS570LS1115*")||cpuis("TMS570LS1224*")||cpuis("TMS570LS1225*")||cpuis("TMS570LS1227*")||cpuis("TMS570LS0232")||cpuis("TMS570LS0714*")||cpuis("TMS570LS0914*"))
|
|
bitfld.long 0xC 19. " HDUPLEX_ENA2 ,Half Duplex transfer mode enable for Data Format 2" "Normal,RX/TX"
|
|
endif
|
|
newline
|
|
bitfld.long 0xC 18. " DISCSTIMERS ,Disable chip-select timers for this format" "No,Yes"
|
|
newline
|
|
bitfld.long 0xC 17. " POLARITY ,SPI data format 2 clock polarity" "Low,High"
|
|
bitfld.long 0xC 16. " PHASE ,SPI data format 2 clock delay" "Disabled,Enabled"
|
|
newline
|
|
hexmask.long.byte 0xC 8.--15. 1. " PRESCALE ,SPI data format 2 prescaler"
|
|
bitfld.long 0xC 0.--4. " CHARLEN ,SPI data format 2 data-word length" ",,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,?..."
|
|
line.long 0x10 "SPIFMT3,SPI Data Format Register 3"
|
|
sif (cpuis("TMS570LS0332")||cpuis("TMS570LS0432")||cpuis("TMS570LS1114*")||cpuis("TMS570LS1115*")||cpuis("TMS570LS1224*")||cpuis("TMS570LS1225*")||cpuis("TMS570LS1227*")||cpuis("TMS570LS0232")||cpuis("TMS570LS0714*")||cpuis("TMS570LS0914*"))
|
|
hexmask.long.byte 0x10 24.--31. 1. " WDELAY ,Delay in between transmissions for data format 3"
|
|
else
|
|
bitfld.long 0x10 24.--29. " WDELAY ,Delay in between transmissions for data format 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
endif
|
|
bitfld.long 0x10 23. " PARPOL ,Parity polarity: even or odd" "Even,Odd"
|
|
newline
|
|
bitfld.long 0x10 22. " PARITYENA ,Parity enable for data format 3" "Disabled,Enabled"
|
|
bitfld.long 0x10 21. " WAITENA ,The master waits for the ENA signal from slave for data format 3" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x10 20. " SHIFTDIR ,Shift direction for data format $" "MSB,LSB"
|
|
sif (cpu()==("TMS570LS0332")||cpu()==("TMS570LS0432")||cpuis("TMS570LS1114*")||cpuis("TMS570LS1115*")||cpuis("TMS570LS1224*")||cpuis("TMS570LS1225*")||cpuis("TMS570LS1227*")||cpuis("TMS570LS0232")||cpuis("TMS570LS0714*")||cpuis("TMS570LS0914*"))
|
|
bitfld.long 0x10 19. " HDUPLEX_ENA3 ,Half Duplex transfer mode enable for Data Format 3" "Normal,RX/TX"
|
|
endif
|
|
newline
|
|
bitfld.long 0x10 18. " DISCSTIMERS ,Disable chip-select timers for this format" "No,Yes"
|
|
newline
|
|
bitfld.long 0x10 17. " POLARITY ,SPI data format 3 clock polarity" "Low,High"
|
|
bitfld.long 0x10 16. " PHASE ,SPI data format 3 clock delay" "Disabled,Enabled"
|
|
newline
|
|
hexmask.long.byte 0x10 8.--15. 1. " PRESCALE ,SPI data format 3 prescaler"
|
|
bitfld.long 0x10 0.--4. " CHARLEN ,SPI data format 3 data-word length" ",,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,?..."
|
|
hgroup.long 0x60++0x03
|
|
hide.long 0x00 "TGINTVECT0,SPI Interrupt Vector Register 0 / MibSPI Transfer Group Interrupt Vector Register 0"
|
|
in
|
|
hgroup.long 0x64++0x03
|
|
hide.long 0x00 "TGINTVECT1,SPI Interrupt Vector Register 1 / MibSPI Transfer Group Interrupt Vector Register 1"
|
|
in
|
|
sif (cpu()!=("TMS570LS0332")&&cpu()!=("TMS570LS0432")&&!cpuis("TMS570LS0232"))
|
|
group.long 0x6C++0x07
|
|
line.long 0x00 "SPIPMCTRL,SPI Parallel/Modulo Mode Control Register"
|
|
bitfld.long 0x00 29. " MODCLKPOL3 ,Modulo mode SPICLK polarity" "Normal,Inverted"
|
|
bitfld.long 0x00 26.--28. " MMODE3 ,SPI/MibSPI data lines " "1,2,3,4,5,6,?..."
|
|
bitfld.long 0x00 24.--25. " PMODE3 ,Parallel mode data lines" "1,2,4,8"
|
|
newline
|
|
bitfld.long 0x00 21. " MODCLKPOL2 ,Modulo mode SPICLK polarity" "Normal,Inverted"
|
|
bitfld.long 0x00 18.--20. " MMODE2 ,SPI/MibSPI data lines " "1,2,3,4,5,6,?..."
|
|
bitfld.long 0x00 16.--17. " PMODE2 ,Parallel mode data lines" "1,2,4,8"
|
|
newline
|
|
bitfld.long 0x00 13. " MODCLKPOL1 ,Modulo mode SPICLK polarity" "Normal,Inverted"
|
|
bitfld.long 0x00 10.--12. " MMODE1 ,SPI/MibSPI data lines " "1,2,3,4,5,6,?..."
|
|
bitfld.long 0x00 8.--9. " PMODE1 ,Parallel mode data lines" "1,2,4,8"
|
|
newline
|
|
bitfld.long 0x00 5. " MODCLKPOL0 ,Modulo mode SPICLK polarity" "Normal,Inverted"
|
|
bitfld.long 0x00 2.--4. " MMODE0 ,SPI/MibSPI data lines " "1,2,3,4,5,6,?..."
|
|
bitfld.long 0x00 0.--1. " PMODE0 ,Parallel mode data lines" "1,2,4,8"
|
|
line.long 0x04 "MIBSPIE,MibSPI Enable Register"
|
|
bitfld.long 0x04 16. " RXRAMACCESS ,Receive-RAM access control" "Not writable,Accessible"
|
|
bitfld.long 0x04 0. " MIBSPIENA ,Multi-buffer mode enable" "Disabled,Enabled"
|
|
elif cpuis("TMS570LS0332")||cpuis("TMS570LS0432")||cpuis("TMS570LS0714*")||cpuis("TMS570LS0914*")||cpuis("TMS570LS0232")
|
|
group.long 0x70++0x03
|
|
line.long 0x00 "MIBSPIE,MibSPI Enable Register"
|
|
bitfld.long 0x00 16. " RXRAMACCESS ,Receive-RAM access control" "Not writable,Accessible"
|
|
bitfld.long 0x00 0. " MIBSPIENA ,Multi-buffer mode enable" "Disabled,Enabled"
|
|
endif
|
|
group.long 0x74++0x0F
|
|
line.long 0x00 "TGITENST,MibSPI Transfer Group Interrupt Enable Set Register"
|
|
bitfld.long 0x00 31. " SETINTENRDY15 ,TG interrupt set (enable) when transfer finished" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " SETINTENRDY14 ,TG interrupt set (enable) when transfer finished" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " SETINTENRDY13 ,TG interrupt set (enable) when transfer finished" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 28. " SETINTENRDY12 ,TG interrupt set (enable) when transfer finished" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " SETINTENRDY11 ,TG interrupt set (enable) when transfer finished" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " SETINTENRDY10 ,TG interrupt set (enable) when transfer finished" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 25. " SETINTENRDY9 ,TG interrupt set (enable) when transfer finished" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " SETINTENRDY8 ,TG interrupt set (enable) when transfer finished" "Disabled,Enabled"
|
|
bitfld.long 0x00 23. " SETINTENRDY7 ,TG interrupt set (enable) when transfer finished" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 22. " SETINTENRDY6 ,TG interrupt set (enable) when transfer finished" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " SETINTENRDY5 ,TG interrupt set (enable) when transfer finished" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " SETINTENRDY4 ,SETTG interrupt set (enable) when transfer finished" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 19. " SETINTENRDY3 ,TG interrupt set (enable) when transfer finished" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SETINTENRDY2 ,TG interrupt set (enable) when transfer finished" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SETINTENRDY1 ,TG interrupt set (enable) when transfer finished" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 16. " SETINTENRDY0 ,TG interrupt set (enable) when transfer finished" "Disabled,Enabled"
|
|
bitfld.long 0x00 15. " SETINTENSUS15 ,TG interrupt set (enabled) when transfer suspended" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " SETINTENSUS14 ,TG interrupt set (enabled) when transfer suspended" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 13. " SETINTENSUS13 ,TG interrupt set (enabled) when transfer suspended" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " SETINTENSUS12 ,TG interrupt set (enabled) when transfer suspended" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " SETINTENSUS11 ,TG interrupt set (enabled) when transfer suspended" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 10. " SETINTENSUS10 ,TG interrupt set (enabled) when transfer suspended" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " SETINTENSUS9 ,TG interrupt set (enabled) when transfer suspended" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " SETINTENSUS8 ,TG interrupt set (enabled) when transfer suspended" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 7. " SETINTENSUS7 ,TG interrupt set (enabled) when transfer suspended" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " SETINTENSUS6 ,TG interrupt set (enabled) when transfer suspended" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " SETINTENSUS5 ,TG interrupt set (enabled) when transfer suspended" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 4. " SETINTENSUS4 ,TG interrupt set (enabled) when transfer suspended" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " SETINTENSUS3 ,TG interrupt set (enabled) when transfer suspended" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " SETINTENSUS2 ,TG interrupt set (enabled) when transfer suspended" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 1. " SETINTENSUS1 ,TG interrupt set (enabled) when transfer suspended" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SETINTENSUS0 ,TG interrupt set (enabled) when transfer suspended" "Disabled,Enabled"
|
|
line.long 0x04 "TGITENCR,MibSPI Transfer Group Interrupt Enable Clear Register"
|
|
bitfld.long 0x04 31. " CLRINTENRDY15 ,TG interrupt clear (disabled) when transfer finished" "Disabled,Enabled"
|
|
bitfld.long 0x04 30. " CLRINTENRDY14 ,TG interrupt clear (disabled) when transfer finished" "Disabled,Enabled"
|
|
bitfld.long 0x04 29. " CLRINTENRDY13 ,TG interrupt clear (disabled) when transfer finished" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x04 28. " CLRINTENRDY12 ,TG interrupt clear (disabled) when transfer finished" "Disabled,Enabled"
|
|
bitfld.long 0x04 27. " CLRINTENRDY11 ,TG interrupt clear (disabled) when transfer finished" "Disabled,Enabled"
|
|
bitfld.long 0x04 26. " CLRINTENRDY10 ,TG interrupt clear (disabled) when transfer finished" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x04 25. " CLRINTENRDY9 ,TG interrupt clear (disabled) when transfer finished" "Disabled,Enabled"
|
|
bitfld.long 0x04 24. " CLRINTENRDY8 ,TG interrupt clear (disabled) when transfer finished" "Disabled,Enabled"
|
|
bitfld.long 0x04 23. " CLRINTENRDY7 ,TG interrupt clear (disabled) when transfer finished" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x04 22. " CLRINTENRDY6 ,TG interrupt clear (disabled) when transfer finished" "Disabled,Enabled"
|
|
bitfld.long 0x04 21. " CLRINTENRDY5 ,TG interrupt clear (disabled) when transfer finished" "Disabled,Enabled"
|
|
bitfld.long 0x04 20. " CLRINTENRDY4 ,TG interrupt clear (disabled) when transfer finished" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x04 19. " CLRINTENRDY3 ,TG interrupt clear (disabled) when transfer finished" "Disabled,Enabled"
|
|
bitfld.long 0x04 18. " CLRINTENRDY2 ,TG interrupt clear (disabled) when transfer finished" "Disabled,Enabled"
|
|
bitfld.long 0x04 17. " CLRINTENRDY1 ,TG interrupt clear (disabled) when transfer finished" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x04 16. " CLRINTENRDY0 ,TG interrupt clear (disabled) when transfer finished" "Disabled,Enabled"
|
|
bitfld.long 0x04 15. " CLRINTENSUS15 ,TG interrupt clear (disabled) when transfer suspended" "Disabled,Enabled"
|
|
bitfld.long 0x04 14. " CLRINTENSUS14 ,TG interrupt clear (disabled) when transfer suspended" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x04 13. " CLRINTENSUS13 ,TG interrupt clear (disabled) when transfer suspended" "Disabled,Enabled"
|
|
bitfld.long 0x04 12. " CLRINTENSUS12 ,TG interrupt clear (disabled) when transfer suspended" "Disabled,Enabled"
|
|
bitfld.long 0x04 11. " CLRINTENSUS11 ,TG interrupt clear (disabled) when transfer suspended" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x04 10. " CLRINTENSUS10 ,TG interrupt clear (disabled) when transfer suspended" "Disabled,Enabled"
|
|
bitfld.long 0x04 9. " CLRINTENSUS9 ,TG interrupt clear (disabled) when transfer suspended" "Disabled,Enabled"
|
|
bitfld.long 0x04 8. " CLRINTENSUS8 ,TG interrupt clear (disabled) when transfer suspended" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x04 7. " CLRINTENSUS7 ,TG interrupt clear (disabled) when transfer suspended" "Disabled,Enabled"
|
|
bitfld.long 0x04 6. " CLRINTENSUS6 ,TG interrupt clear (disabled) when transfer suspended" "Disabled,Enabled"
|
|
bitfld.long 0x04 5. " CLRINTENSUS5 ,TG interrupt clear (disabled) when transfer suspended" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x04 4. " CLRINTENSUS4 ,TG interrupt clear (disabled) when transfer suspended" "Disabled,Enabled"
|
|
bitfld.long 0x04 3. " CLRINTENSUS3 ,TG interrupt clear (disabled) when transfer suspended" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " CLRINTENSUS2 ,TG interrupt clear (disabled) when transfer suspended" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x04 1. " CLRINTENSUS1 ,TG interrupt clear (disabled) when transfer suspended" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " CLRINTENSUS0 ,TG interrupt clear (disabled) when transfer suspended" "Disabled,Enabled"
|
|
line.long 0x08 "TGITLVST,MibSPI Transfer Group Interrupt Level Set Register"
|
|
bitfld.long 0x08 31. " SETINTLVLRDY15 ,Transfer-group completed interrupt level set" "INT0,INT1"
|
|
bitfld.long 0x08 30. " SETINTLVLRDY14 ,Transfer-group completed interrupt level set" "INT0,INT1"
|
|
bitfld.long 0x08 29. " SETINTLVLRDY13 ,Transfer-group completed interrupt level set" "INT0,INT1"
|
|
newline
|
|
bitfld.long 0x08 28. " SETINTLVLRDY12 ,Transfer-group completed interrupt level set" "INT0,INT1"
|
|
bitfld.long 0x08 27. " SETINTLVLRDY11 ,Transfer-group completed interrupt level set" "INT0,INT1"
|
|
bitfld.long 0x08 26. " SETINTLVLRDY10 ,Transfer-group completed interrupt level set" "INT0,INT1"
|
|
newline
|
|
bitfld.long 0x08 25. " SETINTLVLRDY9 ,Transfer-group completed interrupt level set" "INT0,INT1"
|
|
bitfld.long 0x08 24. " SETINTLVLRDY8 ,Transfer-group completed interrupt level set" "INT0,INT1"
|
|
bitfld.long 0x08 23. " SETINTLVLRDY7 ,Transfer-group completed interrupt level set" "INT0,INT1"
|
|
newline
|
|
bitfld.long 0x08 22. " SETINTLVLRDY6 ,Transfer-group completed interrupt level set" "INT0,INT1"
|
|
bitfld.long 0x08 21. " SETINTLVLRDY5 ,Transfer-group completed interrupt level set" "INT0,INT1"
|
|
bitfld.long 0x08 20. " SETINTLVLRDY4 ,Transfer-group completed interrupt level set" "INT0,INT1"
|
|
newline
|
|
bitfld.long 0x08 19. " SETINTLVLRDY3 ,Transfer-group completed interrupt level set" "INT0,INT1"
|
|
bitfld.long 0x08 18. " SETINTLVLRDY2 ,Transfer-group completed interrupt level set" "INT0,INT1"
|
|
bitfld.long 0x08 17. " SETINTLVLRDY1 ,Transfer-group completed interrupt level set" "INT0,INT1"
|
|
newline
|
|
bitfld.long 0x08 16. " SETINTLVLRDY0 ,Transfer-group completed interrupt level set" "INT0,INT1"
|
|
bitfld.long 0x08 15. " SETINTLVLSUS15 ,Transfer-group suspended interrupt level set" "INT0,INT1"
|
|
bitfld.long 0x08 14. " SETINTLVLSUS14 ,Transfer-group suspended interrupt level set" "INT0,INT1"
|
|
newline
|
|
bitfld.long 0x08 13. " SETINTLVLSUS13 ,Transfer-group suspended interrupt level set" "INT0,INT1"
|
|
bitfld.long 0x08 12. " SETINTLVLSUS12 ,Transfer-group suspended interrupt level set" "INT0,INT1"
|
|
bitfld.long 0x08 11. " SETINTLVLSUS11 ,Transfer-group suspended interrupt level set" "INT0,INT1"
|
|
newline
|
|
bitfld.long 0x08 10. " SETINTLVLSUS10 ,Transfer-group suspended interrupt level set" "INT0,INT1"
|
|
bitfld.long 0x08 9. " SETINTLVLSUS9 ,Transfer-group suspended interrupt level set" "INT0,INT1"
|
|
bitfld.long 0x08 8. " SETINTLVLSUS8 ,Transfer-group suspended interrupt level set" "INT0,INT1"
|
|
newline
|
|
bitfld.long 0x08 7. " SETINTLVLSUS7 ,Transfer-group suspended interrupt level set" "INT0,INT1"
|
|
bitfld.long 0x08 6. " SETINTLVLSUS6 ,Transfer-group suspended interrupt level set" "INT0,INT1"
|
|
bitfld.long 0x08 5. " SETINTLVLSUS5 ,Transfer-group suspended interrupt level set" "INT0,INT1"
|
|
newline
|
|
bitfld.long 0x08 4. " SETINTLVLSUS4 ,Transfer-group suspended interrupt level set" "INT0,INT1"
|
|
bitfld.long 0x08 3. " SETINTLVLSUS3 ,Transfer-group suspended interrupt level set" "INT0,INT1"
|
|
bitfld.long 0x08 2. " SETINTLVLSUS2 ,Transfer-group suspended interrupt level set" "INT0,INT1"
|
|
newline
|
|
bitfld.long 0x08 1. " SETINTLVLSUS1 ,Transfer-group suspended interrupt level set" "INT0,INT1"
|
|
bitfld.long 0x08 0. " SETINTLVLSUS0 ,Transfer-group suspended interrupt level set" "INT0,INT1"
|
|
line.long 0x0C "TGITLVCR,MibSPI Transfer Group Interrupt Level Clear Register"
|
|
bitfld.long 0x0C 31. " CLRINTLVLRDY15 ,Transfer-group completed interrupt level clear" "INT0,INT1"
|
|
bitfld.long 0x0C 30. " CLRINTLVLRDY14 ,Transfer-group completed interrupt level clear" "INT0,INT1"
|
|
bitfld.long 0x0C 29. " CLRINTLVLRDY13 ,Transfer-group completed interrupt level clear" "INT0,INT1"
|
|
newline
|
|
bitfld.long 0x0C 28. " CLRINTLVLRDY12 ,Transfer-group completed interrupt level clear" "INT0,INT1"
|
|
bitfld.long 0x0C 27. " CLRINTLVLRDY11 ,Transfer-group completed interrupt level clear" "INT0,INT1"
|
|
bitfld.long 0x0C 26. " CLRINTLVLRDY10 ,Transfer-group completed interrupt level clear" "INT0,INT1"
|
|
newline
|
|
bitfld.long 0x0C 25. " CLRINTLVLRDY9 ,Transfer-group completed interrupt level clear" "INT0,INT1"
|
|
bitfld.long 0x0C 24. " CLRINTLVLRDY8 ,Transfer-group completed interrupt level clear" "INT0,INT1"
|
|
bitfld.long 0x0C 23. " CLRINTLVLRDY7 ,Transfer-group completed interrupt level clear" "INT0,INT1"
|
|
newline
|
|
bitfld.long 0x0C 22. " CLRINTLVLRDY6 ,Transfer-group completed interrupt level clear" "INT0,INT1"
|
|
bitfld.long 0x0C 21. " CLRINTLVLRDY5 ,Transfer-group completed interrupt level clear" "INT0,INT1"
|
|
bitfld.long 0x0C 20. " CLRINTLVLRDY4 ,Transfer-group completed interrupt level clear" "INT0,INT1"
|
|
newline
|
|
bitfld.long 0x0C 19. " CLRINTLVLRDY3 ,Transfer-group completed interrupt level clear" "INT0,INT1"
|
|
bitfld.long 0x0C 18. " CLRINTLVLRDY2 ,Transfer-group completed interrupt level clear" "INT0,INT1"
|
|
bitfld.long 0x0C 17. " CLRINTLVLRDY1 ,Transfer-group completed interrupt level clear" "INT0,INT1"
|
|
newline
|
|
bitfld.long 0x0C 16. " CLRINTLVLRDY0 ,Transfer-group completed interrupt level clear" "INT0,INT1"
|
|
bitfld.long 0x0C 15. " CLRINTLVLSUS15 ,Transfer group suspended interrupt level clear" "INT0,INT1"
|
|
bitfld.long 0x0C 14. " CLRINTLVLSUS14 ,Transfer group suspended interrupt level clear" "INT0,INT1"
|
|
newline
|
|
bitfld.long 0x0C 13. " CLRINTLVLSUS13 ,Transfer group suspended interrupt level clear" "INT0,INT1"
|
|
bitfld.long 0x0C 12. " CLRINTLVLSUS12 ,Transfer group suspended interrupt level clear" "INT0,INT1"
|
|
bitfld.long 0x0C 11. " CLRINTLVLSUS11 ,Transfer group suspended interrupt level clear" "INT0,INT1"
|
|
newline
|
|
bitfld.long 0x0C 10. " CLRINTLVLSUS10 ,Transfer group suspended interrupt level clear" "INT0,INT1"
|
|
bitfld.long 0x0C 9. " CLRINTLVLSUS9 ,Transfer group suspended interrupt level clear" "INT0,INT1"
|
|
bitfld.long 0x0C 8. " CLRINTLVLSUS8 ,Transfer group suspended interrupt level clear" "INT0,INT1"
|
|
newline
|
|
bitfld.long 0x0C 7. " CLRINTLVLSUS7 ,Transfer group suspended interrupt level clear" "INT0,INT1"
|
|
bitfld.long 0x0C 6. " CLRINTLVLSUS6 ,Transfer group suspended interrupt level clear" "INT0,INT1"
|
|
bitfld.long 0x0C 5. " CLRINTLVLSUS5 ,Transfer group suspended interrupt level clear" "INT0,INT1"
|
|
newline
|
|
bitfld.long 0x0C 4. " CLRINTLVLSUS4 ,Transfer group suspended interrupt level clear" "INT0,INT1"
|
|
bitfld.long 0x0C 3. " CLRINTLVLSUS3 ,Transfer group suspended interrupt level clear" "INT0,INT1"
|
|
bitfld.long 0x0C 2. " CLRINTLVLSUS2 ,Transfer group suspended interrupt level clear" "INT0,INT1"
|
|
newline
|
|
bitfld.long 0x0C 1. " CLRINTLVLSUS1 ,Transfer group suspended interrupt level clear" "INT0,INT1"
|
|
bitfld.long 0x0C 0. " CLRINTLVLSUS0 ,Transfer group suspended interrupt level clear" "INT0,INT1"
|
|
group.long 0x84++0x03
|
|
line.long 0x00 "TGITFLG,Transfer Group Interrupt Flag Register"
|
|
sif (cpu()==("TMS570LS0332")||cpu()==("TMS570LS0432")||cpuis("TMS570LS1114*")||cpuis("TMS570LS1115*")||cpuis("TMS570LS1224*")||cpuis("TMS570LS1225*")||cpuis("TMS570LS1227*")||cpuis("TMS570LS0232")||cpuis("TMS570LS0714*")||cpuis("TMS570LS0914*"))
|
|
bitfld.long 0x00 31. " INTFLGRDY[15] ,Transfer-group interrupt flag for a transfer-completed interrupt 15" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " INTFLGRDY[14] ,Transfer-group interrupt flag for a transfer-completed interrupt 14" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 29. " INTFLGRDY[13] ,Transfer-group interrupt flag for a transfer-completed interrupt 13" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " INTFLGRDY[12] ,Transfer-group interrupt flag for a transfer-completed interrupt 12" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 27. " INTFLGRDY[11] ,Transfer-group interrupt flag for a transfer-completed interrupt 11" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " INTFLGRDY[10] ,Transfer-group interrupt flag for a transfer-completed interrupt 10" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 25. " INTFLGRDY[9] ,Transfer-group interrupt flag for a transfer-completed interrupt 9" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " INTFLGRDY[8] ,Transfer-group interrupt flag for a transfer-completed interrupt 8" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 23. " INTFLGRDY[7] ,Transfer-group interrupt flag for a transfer-completed interrupt 7" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " INTFLGRDY[6] ,Transfer-group interrupt flag for a transfer-completed interrupt 6" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 21. " INTFLGRDY[5] ,Transfer-group interrupt flag for a transfer-completed interrupt 5" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " INTFLGRDY[4] ,Transfer-group interrupt flag for a transfer-completed interrupt 4" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 19. " INTFLGRDY[3] ,Transfer-group interrupt flag for a transfer-completed interrupt 3" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " INTFLGRDY[2] ,Transfer-group interrupt flag for a transfer-completed interrupt 2" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 17. " INTFLGRDY[1] ,Transfer-group interrupt flag for a transfer-completed interrupt 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " INTFLGRDY[0] ,Transfer-group interrupt flag for a transfer-completed interrupt 0" "Disabled,Enabled"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 15. " INTFLGSUS[15] ,Transfer-group interrupt flag for a transfer-suspend interrupt 15" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " INTFLGSUS[14] ,Transfer-group interrupt flag for a transfer-suspend interrupt 14" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 13. " INTFLGSUS[13] ,Transfer-group interrupt flag for a transfer-suspend interrupt 13" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " INTFLGSUS[12] ,Transfer-group interrupt flag for a transfer-suspend interrupt 12" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 11. " INTFLGSUS[11] ,Transfer-group interrupt flag for a transfer-suspend interrupt 11" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " INTFLGSUS[10] ,Transfer-group interrupt flag for a transfer-suspend interrupt 10" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 9. " INTFLGSUS[9] ,Transfer-group interrupt flag for a transfer-suspend interrupt 9" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " INTFLGSUS[8] ,Transfer-group interrupt flag for a transfer-suspend interrupt 8" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 7. " INTFLGSUS[7] ,Transfer-group interrupt flag for a transfer-suspend interrupt 7" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " INTFLGSUS[6] ,Transfer-group interrupt flag for a transfer-suspend interrupt 6" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 5. " INTFLGSUS[5] ,Transfer-group interrupt flag for a transfer-suspend interrupt 5" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " INTFLGSUS[4] ,Transfer-group interrupt flag for a transfer-suspend interrupt 4" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 3. " INTFLGSUS[3] ,Transfer-group interrupt flag for a transfer-suspend interrupt 3" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " INTFLGSUS[2] ,Transfer-group interrupt flag for a transfer-suspend interrupt 2" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 1. " INTFLGSUS[1] ,Transfer-group interrupt flag for a transfer-suspend interrupt 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " INTFLGSUS[0] ,Transfer-group interrupt flag for a transfer-suspend interrupt 0" "Disabled,Enabled"
|
|
group.long 0x90++0x47
|
|
line.long 0x00 "TICKCNT,Tick Count Register"
|
|
bitfld.long 0x00 31. " TICKENA ,Tick counter enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " RELOAD ,Pre-load the tick counter" "No effect,Reload"
|
|
bitfld.long 0x00 28.--29. " CLKCTRL ,Tick counter clock source control" "0,1,2,3"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TICKVALUE ,Initial value for the tick counter"
|
|
line.long 0x04 "LTGPEND,Last Transfer Group End Pointer Register"
|
|
bitfld.long 0x04 24.--28. " TGINSERVICE ,The TG number currently being serviced by the sequencer" "No TG,TG0,TG1,TG2,TG3,TG4,TG5,TG6,TG7,TG8,TG9,TG10,TG11,TG12,TG13,TG14,TG15,?..."
|
|
hexmask.long.byte 0x04 8.--14. 1. " LPEND ,Last TG end pointer"
|
|
line.long 0x8 "TG0CTRL,MibSPI Transfer Group Control Register 0"
|
|
bitfld.long 0x8 31. " TGENA ,TG enable" "Disabled,Enabled"
|
|
bitfld.long 0x8 30. " ONESHOT ,Single transfer for TG" "Disabled,Enabled"
|
|
bitfld.long 0x8 29. " PRST ,TG pointer reset mode" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x8 28. " TGTD ,TG triggered" "Not triggered,Triggered"
|
|
bitfld.long 0x8 20.--23. " TRGEVT ,Type of trigger event" "Never,Rising edge,Falling edge,Both edges,,High active,Low-active,Always,?..."
|
|
sif cpuis("TMS570LS0232")||cpuis("TMS570LS0714*")||cpuis("TMS570LS0914*")
|
|
bitfld.long 0x8 16.--19. " TRIGSRC ,Trigger source" "Disabled,EXT0,EXT1,EXT2,EXT3,EXT4,EXT5,EXT6,EXT7,EXT8,EXT9,EXT10,EXT11,EXT12,EXT13,TICK"
|
|
else
|
|
bitfld.long 0x8 16.--19. " TRIGSRC ,Trigger source" "Disabled,GIOA[0],GIOA[1],GIOA[2],GIOA[3],GIOA[4],GIOA[5],GIOA[6],GIOA[7],N2HET1[8],N2HET1[10],N2HET1[12],N2HET1[14],N2HET1[16],N2HET1[18],TICK"
|
|
endif
|
|
newline
|
|
hexmask.long.byte 0x8 8.--14. 0x01 " PSTART ,TG start address"
|
|
hexmask.long.byte 0x8 0.--6. 0x01 " PCURRENT ,Pointer to current buffer"
|
|
line.long 0xC "TG1CTRL,MibSPI Transfer Group Control Register 1"
|
|
bitfld.long 0xC 31. " TGENA ,TG enable" "Disabled,Enabled"
|
|
bitfld.long 0xC 30. " ONESHOT ,Single transfer for TG" "Disabled,Enabled"
|
|
bitfld.long 0xC 29. " PRST ,TG pointer reset mode" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0xC 28. " TGTD ,TG triggered" "Not triggered,Triggered"
|
|
bitfld.long 0xC 20.--23. " TRGEVT ,Type of trigger event" "Never,Rising edge,Falling edge,Both edges,,High active,Low-active,Always,?..."
|
|
sif cpuis("TMS570LS0232")||cpuis("TMS570LS0714*")||cpuis("TMS570LS0914*")
|
|
bitfld.long 0xC 16.--19. " TRIGSRC ,Trigger source" "Disabled,EXT0,EXT1,EXT2,EXT3,EXT4,EXT5,EXT6,EXT7,EXT8,EXT9,EXT10,EXT11,EXT12,EXT13,TICK"
|
|
else
|
|
bitfld.long 0xC 16.--19. " TRIGSRC ,Trigger source" "Disabled,GIOA[0],GIOA[1],GIOA[2],GIOA[3],GIOA[4],GIOA[5],GIOA[6],GIOA[7],N2HET1[8],N2HET1[10],N2HET1[12],N2HET1[14],N2HET1[16],N2HET1[18],TICK"
|
|
endif
|
|
newline
|
|
hexmask.long.byte 0xC 8.--14. 0x01 " PSTART ,TG start address"
|
|
hexmask.long.byte 0xC 0.--6. 0x01 " PCURRENT ,Pointer to current buffer"
|
|
line.long 0x10 "TG2CTRL,MibSPI Transfer Group Control Register 2"
|
|
bitfld.long 0x10 31. " TGENA ,TG enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 30. " ONESHOT ,Single transfer for TG" "Disabled,Enabled"
|
|
bitfld.long 0x10 29. " PRST ,TG pointer reset mode" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x10 28. " TGTD ,TG triggered" "Not triggered,Triggered"
|
|
bitfld.long 0x10 20.--23. " TRGEVT ,Type of trigger event" "Never,Rising edge,Falling edge,Both edges,,High active,Low-active,Always,?..."
|
|
sif cpuis("TMS570LS0232")||cpuis("TMS570LS0714*")||cpuis("TMS570LS0914*")
|
|
bitfld.long 0x10 16.--19. " TRIGSRC ,Trigger source" "Disabled,EXT0,EXT1,EXT2,EXT3,EXT4,EXT5,EXT6,EXT7,EXT8,EXT9,EXT10,EXT11,EXT12,EXT13,TICK"
|
|
else
|
|
bitfld.long 0x10 16.--19. " TRIGSRC ,Trigger source" "Disabled,GIOA[0],GIOA[1],GIOA[2],GIOA[3],GIOA[4],GIOA[5],GIOA[6],GIOA[7],N2HET1[8],N2HET1[10],N2HET1[12],N2HET1[14],N2HET1[16],N2HET1[18],TICK"
|
|
endif
|
|
newline
|
|
hexmask.long.byte 0x10 8.--14. 0x01 " PSTART ,TG start address"
|
|
hexmask.long.byte 0x10 0.--6. 0x01 " PCURRENT ,Pointer to current buffer"
|
|
line.long 0x14 "TG3CTRL,MibSPI Transfer Group Control Register 3"
|
|
bitfld.long 0x14 31. " TGENA ,TG enable" "Disabled,Enabled"
|
|
bitfld.long 0x14 30. " ONESHOT ,Single transfer for TG" "Disabled,Enabled"
|
|
bitfld.long 0x14 29. " PRST ,TG pointer reset mode" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x14 28. " TGTD ,TG triggered" "Not triggered,Triggered"
|
|
bitfld.long 0x14 20.--23. " TRGEVT ,Type of trigger event" "Never,Rising edge,Falling edge,Both edges,,High active,Low-active,Always,?..."
|
|
sif cpuis("TMS570LS0232")||cpuis("TMS570LS0714*")||cpuis("TMS570LS0914*")
|
|
bitfld.long 0x14 16.--19. " TRIGSRC ,Trigger source" "Disabled,EXT0,EXT1,EXT2,EXT3,EXT4,EXT5,EXT6,EXT7,EXT8,EXT9,EXT10,EXT11,EXT12,EXT13,TICK"
|
|
else
|
|
bitfld.long 0x14 16.--19. " TRIGSRC ,Trigger source" "Disabled,GIOA[0],GIOA[1],GIOA[2],GIOA[3],GIOA[4],GIOA[5],GIOA[6],GIOA[7],N2HET1[8],N2HET1[10],N2HET1[12],N2HET1[14],N2HET1[16],N2HET1[18],TICK"
|
|
endif
|
|
newline
|
|
hexmask.long.byte 0x14 8.--14. 0x01 " PSTART ,TG start address"
|
|
hexmask.long.byte 0x14 0.--6. 0x01 " PCURRENT ,Pointer to current buffer"
|
|
line.long 0x18 "TG4CTRL,MibSPI Transfer Group Control Register 4"
|
|
bitfld.long 0x18 31. " TGENA ,TG enable" "Disabled,Enabled"
|
|
bitfld.long 0x18 30. " ONESHOT ,Single transfer for TG" "Disabled,Enabled"
|
|
bitfld.long 0x18 29. " PRST ,TG pointer reset mode" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x18 28. " TGTD ,TG triggered" "Not triggered,Triggered"
|
|
bitfld.long 0x18 20.--23. " TRGEVT ,Type of trigger event" "Never,Rising edge,Falling edge,Both edges,,High active,Low-active,Always,?..."
|
|
sif cpuis("TMS570LS0232")||cpuis("TMS570LS0714*")||cpuis("TMS570LS0914*")
|
|
bitfld.long 0x18 16.--19. " TRIGSRC ,Trigger source" "Disabled,EXT0,EXT1,EXT2,EXT3,EXT4,EXT5,EXT6,EXT7,EXT8,EXT9,EXT10,EXT11,EXT12,EXT13,TICK"
|
|
else
|
|
bitfld.long 0x18 16.--19. " TRIGSRC ,Trigger source" "Disabled,GIOA[0],GIOA[1],GIOA[2],GIOA[3],GIOA[4],GIOA[5],GIOA[6],GIOA[7],N2HET1[8],N2HET1[10],N2HET1[12],N2HET1[14],N2HET1[16],N2HET1[18],TICK"
|
|
endif
|
|
newline
|
|
hexmask.long.byte 0x18 8.--14. 0x01 " PSTART ,TG start address"
|
|
hexmask.long.byte 0x18 0.--6. 0x01 " PCURRENT ,Pointer to current buffer"
|
|
line.long 0x1C "TG5CTRL,MibSPI Transfer Group Control Register 5"
|
|
bitfld.long 0x1C 31. " TGENA ,TG enable" "Disabled,Enabled"
|
|
bitfld.long 0x1C 30. " ONESHOT ,Single transfer for TG" "Disabled,Enabled"
|
|
bitfld.long 0x1C 29. " PRST ,TG pointer reset mode" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x1C 28. " TGTD ,TG triggered" "Not triggered,Triggered"
|
|
bitfld.long 0x1C 20.--23. " TRGEVT ,Type of trigger event" "Never,Rising edge,Falling edge,Both edges,,High active,Low-active,Always,?..."
|
|
sif cpuis("TMS570LS0232")||cpuis("TMS570LS0714*")||cpuis("TMS570LS0914*")
|
|
bitfld.long 0x1C 16.--19. " TRIGSRC ,Trigger source" "Disabled,EXT0,EXT1,EXT2,EXT3,EXT4,EXT5,EXT6,EXT7,EXT8,EXT9,EXT10,EXT11,EXT12,EXT13,TICK"
|
|
else
|
|
bitfld.long 0x1C 16.--19. " TRIGSRC ,Trigger source" "Disabled,GIOA[0],GIOA[1],GIOA[2],GIOA[3],GIOA[4],GIOA[5],GIOA[6],GIOA[7],N2HET1[8],N2HET1[10],N2HET1[12],N2HET1[14],N2HET1[16],N2HET1[18],TICK"
|
|
endif
|
|
newline
|
|
hexmask.long.byte 0x1C 8.--14. 0x01 " PSTART ,TG start address"
|
|
hexmask.long.byte 0x1C 0.--6. 0x01 " PCURRENT ,Pointer to current buffer"
|
|
line.long 0x20 "TG6CTRL,MibSPI Transfer Group Control Register 6"
|
|
bitfld.long 0x20 31. " TGENA ,TG enable" "Disabled,Enabled"
|
|
bitfld.long 0x20 30. " ONESHOT ,Single transfer for TG" "Disabled,Enabled"
|
|
bitfld.long 0x20 29. " PRST ,TG pointer reset mode" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x20 28. " TGTD ,TG triggered" "Not triggered,Triggered"
|
|
bitfld.long 0x20 20.--23. " TRGEVT ,Type of trigger event" "Never,Rising edge,Falling edge,Both edges,,High active,Low-active,Always,?..."
|
|
sif cpuis("TMS570LS0232")||cpuis("TMS570LS0714*")||cpuis("TMS570LS0914*")
|
|
bitfld.long 0x20 16.--19. " TRIGSRC ,Trigger source" "Disabled,EXT0,EXT1,EXT2,EXT3,EXT4,EXT5,EXT6,EXT7,EXT8,EXT9,EXT10,EXT11,EXT12,EXT13,TICK"
|
|
else
|
|
bitfld.long 0x20 16.--19. " TRIGSRC ,Trigger source" "Disabled,GIOA[0],GIOA[1],GIOA[2],GIOA[3],GIOA[4],GIOA[5],GIOA[6],GIOA[7],N2HET1[8],N2HET1[10],N2HET1[12],N2HET1[14],N2HET1[16],N2HET1[18],TICK"
|
|
endif
|
|
newline
|
|
hexmask.long.byte 0x20 8.--14. 0x01 " PSTART ,TG start address"
|
|
hexmask.long.byte 0x20 0.--6. 0x01 " PCURRENT ,Pointer to current buffer"
|
|
line.long 0x24 "TG7CTRL,MibSPI Transfer Group Control Register 7"
|
|
bitfld.long 0x24 31. " TGENA ,TG enable" "Disabled,Enabled"
|
|
bitfld.long 0x24 30. " ONESHOT ,Single transfer for TG" "Disabled,Enabled"
|
|
bitfld.long 0x24 29. " PRST ,TG pointer reset mode" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x24 28. " TGTD ,TG triggered" "Not triggered,Triggered"
|
|
bitfld.long 0x24 20.--23. " TRGEVT ,Type of trigger event" "Never,Rising edge,Falling edge,Both edges,,High active,Low-active,Always,?..."
|
|
sif cpuis("TMS570LS0232")||cpuis("TMS570LS0714*")||cpuis("TMS570LS0914*")
|
|
bitfld.long 0x24 16.--19. " TRIGSRC ,Trigger source" "Disabled,EXT0,EXT1,EXT2,EXT3,EXT4,EXT5,EXT6,EXT7,EXT8,EXT9,EXT10,EXT11,EXT12,EXT13,TICK"
|
|
else
|
|
bitfld.long 0x24 16.--19. " TRIGSRC ,Trigger source" "Disabled,GIOA[0],GIOA[1],GIOA[2],GIOA[3],GIOA[4],GIOA[5],GIOA[6],GIOA[7],N2HET1[8],N2HET1[10],N2HET1[12],N2HET1[14],N2HET1[16],N2HET1[18],TICK"
|
|
endif
|
|
newline
|
|
hexmask.long.byte 0x24 8.--14. 0x01 " PSTART ,TG start address"
|
|
hexmask.long.byte 0x24 0.--6. 0x01 " PCURRENT ,Pointer to current buffer"
|
|
line.long 0x28 "TG8CTRL,MibSPI Transfer Group Control Register 8"
|
|
bitfld.long 0x28 31. " TGENA ,TG enable" "Disabled,Enabled"
|
|
bitfld.long 0x28 30. " ONESHOT ,Single transfer for TG" "Disabled,Enabled"
|
|
bitfld.long 0x28 29. " PRST ,TG pointer reset mode" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x28 28. " TGTD ,TG triggered" "Not triggered,Triggered"
|
|
bitfld.long 0x28 20.--23. " TRGEVT ,Type of trigger event" "Never,Rising edge,Falling edge,Both edges,,High active,Low-active,Always,?..."
|
|
sif cpuis("TMS570LS0232")||cpuis("TMS570LS0714*")||cpuis("TMS570LS0914*")
|
|
bitfld.long 0x28 16.--19. " TRIGSRC ,Trigger source" "Disabled,EXT0,EXT1,EXT2,EXT3,EXT4,EXT5,EXT6,EXT7,EXT8,EXT9,EXT10,EXT11,EXT12,EXT13,TICK"
|
|
else
|
|
bitfld.long 0x28 16.--19. " TRIGSRC ,Trigger source" "Disabled,GIOA[0],GIOA[1],GIOA[2],GIOA[3],GIOA[4],GIOA[5],GIOA[6],GIOA[7],N2HET1[8],N2HET1[10],N2HET1[12],N2HET1[14],N2HET1[16],N2HET1[18],TICK"
|
|
endif
|
|
newline
|
|
hexmask.long.byte 0x28 8.--14. 0x01 " PSTART ,TG start address"
|
|
hexmask.long.byte 0x28 0.--6. 0x01 " PCURRENT ,Pointer to current buffer"
|
|
line.long 0x2C "TG9CTRL,MibSPI Transfer Group Control Register 9"
|
|
bitfld.long 0x2C 31. " TGENA ,TG enable" "Disabled,Enabled"
|
|
bitfld.long 0x2C 30. " ONESHOT ,Single transfer for TG" "Disabled,Enabled"
|
|
bitfld.long 0x2C 29. " PRST ,TG pointer reset mode" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x2C 28. " TGTD ,TG triggered" "Not triggered,Triggered"
|
|
bitfld.long 0x2C 20.--23. " TRGEVT ,Type of trigger event" "Never,Rising edge,Falling edge,Both edges,,High active,Low-active,Always,?..."
|
|
sif cpuis("TMS570LS0232")||cpuis("TMS570LS0714*")||cpuis("TMS570LS0914*")
|
|
bitfld.long 0x2C 16.--19. " TRIGSRC ,Trigger source" "Disabled,EXT0,EXT1,EXT2,EXT3,EXT4,EXT5,EXT6,EXT7,EXT8,EXT9,EXT10,EXT11,EXT12,EXT13,TICK"
|
|
else
|
|
bitfld.long 0x2C 16.--19. " TRIGSRC ,Trigger source" "Disabled,GIOA[0],GIOA[1],GIOA[2],GIOA[3],GIOA[4],GIOA[5],GIOA[6],GIOA[7],N2HET1[8],N2HET1[10],N2HET1[12],N2HET1[14],N2HET1[16],N2HET1[18],TICK"
|
|
endif
|
|
newline
|
|
hexmask.long.byte 0x2C 8.--14. 0x01 " PSTART ,TG start address"
|
|
hexmask.long.byte 0x2C 0.--6. 0x01 " PCURRENT ,Pointer to current buffer"
|
|
line.long 0x30 "TG10CTRL,MibSPI Transfer Group Control Register 10"
|
|
bitfld.long 0x30 31. " TGENA ,TG enable" "Disabled,Enabled"
|
|
bitfld.long 0x30 30. " ONESHOT ,Single transfer for TG" "Disabled,Enabled"
|
|
bitfld.long 0x30 29. " PRST ,TG pointer reset mode" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x30 28. " TGTD ,TG triggered" "Not triggered,Triggered"
|
|
bitfld.long 0x30 20.--23. " TRGEVT ,Type of trigger event" "Never,Rising edge,Falling edge,Both edges,,High active,Low-active,Always,?..."
|
|
sif cpuis("TMS570LS0232")||cpuis("TMS570LS0714*")||cpuis("TMS570LS0914*")
|
|
bitfld.long 0x30 16.--19. " TRIGSRC ,Trigger source" "Disabled,EXT0,EXT1,EXT2,EXT3,EXT4,EXT5,EXT6,EXT7,EXT8,EXT9,EXT10,EXT11,EXT12,EXT13,TICK"
|
|
else
|
|
bitfld.long 0x30 16.--19. " TRIGSRC ,Trigger source" "Disabled,GIOA[0],GIOA[1],GIOA[2],GIOA[3],GIOA[4],GIOA[5],GIOA[6],GIOA[7],N2HET1[8],N2HET1[10],N2HET1[12],N2HET1[14],N2HET1[16],N2HET1[18],TICK"
|
|
endif
|
|
newline
|
|
hexmask.long.byte 0x30 8.--14. 0x01 " PSTART ,TG start address"
|
|
hexmask.long.byte 0x30 0.--6. 0x01 " PCURRENT ,Pointer to current buffer"
|
|
line.long 0x34 "TG11CTRL,MibSPI Transfer Group Control Register 11"
|
|
bitfld.long 0x34 31. " TGENA ,TG enable" "Disabled,Enabled"
|
|
bitfld.long 0x34 30. " ONESHOT ,Single transfer for TG" "Disabled,Enabled"
|
|
bitfld.long 0x34 29. " PRST ,TG pointer reset mode" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x34 28. " TGTD ,TG triggered" "Not triggered,Triggered"
|
|
bitfld.long 0x34 20.--23. " TRGEVT ,Type of trigger event" "Never,Rising edge,Falling edge,Both edges,,High active,Low-active,Always,?..."
|
|
sif cpuis("TMS570LS0232")||cpuis("TMS570LS0714*")||cpuis("TMS570LS0914*")
|
|
bitfld.long 0x34 16.--19. " TRIGSRC ,Trigger source" "Disabled,EXT0,EXT1,EXT2,EXT3,EXT4,EXT5,EXT6,EXT7,EXT8,EXT9,EXT10,EXT11,EXT12,EXT13,TICK"
|
|
else
|
|
bitfld.long 0x34 16.--19. " TRIGSRC ,Trigger source" "Disabled,GIOA[0],GIOA[1],GIOA[2],GIOA[3],GIOA[4],GIOA[5],GIOA[6],GIOA[7],N2HET1[8],N2HET1[10],N2HET1[12],N2HET1[14],N2HET1[16],N2HET1[18],TICK"
|
|
endif
|
|
newline
|
|
hexmask.long.byte 0x34 8.--14. 0x01 " PSTART ,TG start address"
|
|
hexmask.long.byte 0x34 0.--6. 0x01 " PCURRENT ,Pointer to current buffer"
|
|
line.long 0x38 "TG12CTRL,MibSPI Transfer Group Control Register 12"
|
|
bitfld.long 0x38 31. " TGENA ,TG enable" "Disabled,Enabled"
|
|
bitfld.long 0x38 30. " ONESHOT ,Single transfer for TG" "Disabled,Enabled"
|
|
bitfld.long 0x38 29. " PRST ,TG pointer reset mode" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x38 28. " TGTD ,TG triggered" "Not triggered,Triggered"
|
|
bitfld.long 0x38 20.--23. " TRGEVT ,Type of trigger event" "Never,Rising edge,Falling edge,Both edges,,High active,Low-active,Always,?..."
|
|
sif cpuis("TMS570LS0232")||cpuis("TMS570LS0714*")||cpuis("TMS570LS0914*")
|
|
bitfld.long 0x38 16.--19. " TRIGSRC ,Trigger source" "Disabled,EXT0,EXT1,EXT2,EXT3,EXT4,EXT5,EXT6,EXT7,EXT8,EXT9,EXT10,EXT11,EXT12,EXT13,TICK"
|
|
else
|
|
bitfld.long 0x38 16.--19. " TRIGSRC ,Trigger source" "Disabled,GIOA[0],GIOA[1],GIOA[2],GIOA[3],GIOA[4],GIOA[5],GIOA[6],GIOA[7],N2HET1[8],N2HET1[10],N2HET1[12],N2HET1[14],N2HET1[16],N2HET1[18],TICK"
|
|
endif
|
|
newline
|
|
hexmask.long.byte 0x38 8.--14. 0x01 " PSTART ,TG start address"
|
|
hexmask.long.byte 0x38 0.--6. 0x01 " PCURRENT ,Pointer to current buffer"
|
|
line.long 0x3C "TG13CTRL,MibSPI Transfer Group Control Register 13"
|
|
bitfld.long 0x3C 31. " TGENA ,TG enable" "Disabled,Enabled"
|
|
bitfld.long 0x3C 30. " ONESHOT ,Single transfer for TG" "Disabled,Enabled"
|
|
bitfld.long 0x3C 29. " PRST ,TG pointer reset mode" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x3C 28. " TGTD ,TG triggered" "Not triggered,Triggered"
|
|
bitfld.long 0x3C 20.--23. " TRGEVT ,Type of trigger event" "Never,Rising edge,Falling edge,Both edges,,High active,Low-active,Always,?..."
|
|
sif cpuis("TMS570LS0232")||cpuis("TMS570LS0714*")||cpuis("TMS570LS0914*")
|
|
bitfld.long 0x3C 16.--19. " TRIGSRC ,Trigger source" "Disabled,EXT0,EXT1,EXT2,EXT3,EXT4,EXT5,EXT6,EXT7,EXT8,EXT9,EXT10,EXT11,EXT12,EXT13,TICK"
|
|
else
|
|
bitfld.long 0x3C 16.--19. " TRIGSRC ,Trigger source" "Disabled,GIOA[0],GIOA[1],GIOA[2],GIOA[3],GIOA[4],GIOA[5],GIOA[6],GIOA[7],N2HET1[8],N2HET1[10],N2HET1[12],N2HET1[14],N2HET1[16],N2HET1[18],TICK"
|
|
endif
|
|
newline
|
|
hexmask.long.byte 0x3C 8.--14. 0x01 " PSTART ,TG start address"
|
|
hexmask.long.byte 0x3C 0.--6. 0x01 " PCURRENT ,Pointer to current buffer"
|
|
line.long 0x40 "TG14CTRL,MibSPI Transfer Group Control Register 14"
|
|
bitfld.long 0x40 31. " TGENA ,TG enable" "Disabled,Enabled"
|
|
bitfld.long 0x40 30. " ONESHOT ,Single transfer for TG" "Disabled,Enabled"
|
|
bitfld.long 0x40 29. " PRST ,TG pointer reset mode" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x40 28. " TGTD ,TG triggered" "Not triggered,Triggered"
|
|
bitfld.long 0x40 20.--23. " TRGEVT ,Type of trigger event" "Never,Rising edge,Falling edge,Both edges,,High active,Low-active,Always,?..."
|
|
sif cpuis("TMS570LS0232")||cpuis("TMS570LS0714*")||cpuis("TMS570LS0914*")
|
|
bitfld.long 0x40 16.--19. " TRIGSRC ,Trigger source" "Disabled,EXT0,EXT1,EXT2,EXT3,EXT4,EXT5,EXT6,EXT7,EXT8,EXT9,EXT10,EXT11,EXT12,EXT13,TICK"
|
|
else
|
|
bitfld.long 0x40 16.--19. " TRIGSRC ,Trigger source" "Disabled,GIOA[0],GIOA[1],GIOA[2],GIOA[3],GIOA[4],GIOA[5],GIOA[6],GIOA[7],N2HET1[8],N2HET1[10],N2HET1[12],N2HET1[14],N2HET1[16],N2HET1[18],TICK"
|
|
endif
|
|
newline
|
|
hexmask.long.byte 0x40 8.--14. 0x01 " PSTART ,TG start address"
|
|
hexmask.long.byte 0x40 0.--6. 0x01 " PCURRENT ,Pointer to current buffer"
|
|
line.long 0x44 "TG15CTRL,MibSPI Transfer Group Control Register 15"
|
|
bitfld.long 0x44 31. " TGENA ,TG enable" "Disabled,Enabled"
|
|
bitfld.long 0x44 30. " ONESHOT ,Single transfer for TG" "Disabled,Enabled"
|
|
bitfld.long 0x44 29. " PRST ,TG pointer reset mode" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x44 28. " TGTD ,TG triggered" "Not triggered,Triggered"
|
|
bitfld.long 0x44 20.--23. " TRGEVT ,Type of trigger event" "Never,Rising edge,Falling edge,Both edges,,High active,Low-active,Always,?..."
|
|
sif cpuis("TMS570LS0232")||cpuis("TMS570LS0714*")||cpuis("TMS570LS0914*")
|
|
bitfld.long 0x44 16.--19. " TRIGSRC ,Trigger source" "Disabled,EXT0,EXT1,EXT2,EXT3,EXT4,EXT5,EXT6,EXT7,EXT8,EXT9,EXT10,EXT11,EXT12,EXT13,TICK"
|
|
else
|
|
bitfld.long 0x44 16.--19. " TRIGSRC ,Trigger source" "Disabled,GIOA[0],GIOA[1],GIOA[2],GIOA[3],GIOA[4],GIOA[5],GIOA[6],GIOA[7],N2HET1[8],N2HET1[10],N2HET1[12],N2HET1[14],N2HET1[16],N2HET1[18],TICK"
|
|
endif
|
|
newline
|
|
hexmask.long.byte 0x44 8.--14. 0x01 " PSTART ,TG start address"
|
|
hexmask.long.byte 0x44 0.--6. 0x01 " PCURRENT ,Pointer to current buffer"
|
|
sif (cpu()!=("TMS570LS0332")&&cpu()!=("TMS570LS0432")&&!cpuis("TMS570LS0232"))
|
|
group.long 0xD8++0x1F
|
|
line.long 0x0 "DMA0CTRL,MibSPI DMA Channel Control Register 1"
|
|
bitfld.long 0x0 31. " ONESHOT ,Auto-disable of DMA channel after ICOUNT+1 transfers" "0,1"
|
|
hexmask.long.byte 0x0 24.--30. 1. " BUFID ,Buffer utilized for DMA transfer"
|
|
bitfld.long 0x0 20.--23. " RXDMA_MAP ,Each MibSPI DMA channel can be linked to two physical DMA" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x0 16.--19. " TXDMA_MAP ,Each MibSPI DMA channel can be linked to two physical DMA" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x0 15. " RXDMAENA ,Receive data DMA channel enable" "Disabled,Enabled"
|
|
bitfld.long 0x0 14. " TXDMAENA ,Transmit data DMA channel enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x0 13. " NOBRK ,Non-interleaved DMA block transfer" "Not performed,Performed"
|
|
bitfld.long 0x0 8.--12. " ICOUNT ,Initial count of DMA transfers" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32"
|
|
bitfld.long 0x0 6. " COUNTBIT17 ,17th bit of the COUNT field of DMAxCOUNT register" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0.--5. " COUNT ,Actual number of remaining DMA transfers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
line.long 0x4 "DMA1CTRL,MibSPI DMA Channel Control Register 1"
|
|
bitfld.long 0x4 31. " ONESHOT ,Auto-disable of DMA channel after ICOUNT+1 transfers" "0,1"
|
|
hexmask.long.byte 0x4 24.--30. 1. " BUFID ,Buffer utilized for DMA transfer"
|
|
bitfld.long 0x4 20.--23. " RXDMA_MAP ,Each MibSPI DMA channel can be linked to two physical DMA" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x4 16.--19. " TXDMA_MAP ,Each MibSPI DMA channel can be linked to two physical DMA" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x4 15. " RXDMAENA ,Receive data DMA channel enable" "Disabled,Enabled"
|
|
bitfld.long 0x4 14. " TXDMAENA ,Transmit data DMA channel enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x4 13. " NOBRK ,Non-interleaved DMA block transfer" "Not performed,Performed"
|
|
bitfld.long 0x4 8.--12. " ICOUNT ,Initial count of DMA transfers" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32"
|
|
bitfld.long 0x4 6. " COUNTBIT17 ,17th bit of the COUNT field of DMAxCOUNT register" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0.--5. " COUNT ,Actual number of remaining DMA transfers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
line.long 0x8 "DMA2CTRL,MibSPI DMA Channel Control Register 1"
|
|
bitfld.long 0x8 31. " ONESHOT ,Auto-disable of DMA channel after ICOUNT+1 transfers" "0,1"
|
|
hexmask.long.byte 0x8 24.--30. 1. " BUFID ,Buffer utilized for DMA transfer"
|
|
bitfld.long 0x8 20.--23. " RXDMA_MAP ,Each MibSPI DMA channel can be linked to two physical DMA" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x8 16.--19. " TXDMA_MAP ,Each MibSPI DMA channel can be linked to two physical DMA" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x8 15. " RXDMAENA ,Receive data DMA channel enable" "Disabled,Enabled"
|
|
bitfld.long 0x8 14. " TXDMAENA ,Transmit data DMA channel enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x8 13. " NOBRK ,Non-interleaved DMA block transfer" "Not performed,Performed"
|
|
bitfld.long 0x8 8.--12. " ICOUNT ,Initial count of DMA transfers" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32"
|
|
bitfld.long 0x8 6. " COUNTBIT17 ,17th bit of the COUNT field of DMAxCOUNT register" "0,1"
|
|
newline
|
|
bitfld.long 0x8 0.--5. " COUNT ,Actual number of remaining DMA transfers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
line.long 0xC "DMA3CTRL,MibSPI DMA Channel Control Register 1"
|
|
bitfld.long 0xC 31. " ONESHOT ,Auto-disable of DMA channel after ICOUNT+1 transfers" "0,1"
|
|
hexmask.long.byte 0xC 24.--30. 1. " BUFID ,Buffer utilized for DMA transfer"
|
|
bitfld.long 0xC 20.--23. " RXDMA_MAP ,Each MibSPI DMA channel can be linked to two physical DMA" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0xC 16.--19. " TXDMA_MAP ,Each MibSPI DMA channel can be linked to two physical DMA" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0xC 15. " RXDMAENA ,Receive data DMA channel enable" "Disabled,Enabled"
|
|
bitfld.long 0xC 14. " TXDMAENA ,Transmit data DMA channel enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0xC 13. " NOBRK ,Non-interleaved DMA block transfer" "Not performed,Performed"
|
|
bitfld.long 0xC 8.--12. " ICOUNT ,Initial count of DMA transfers" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32"
|
|
bitfld.long 0xC 6. " COUNTBIT17 ,17th bit of the COUNT field of DMAxCOUNT register" "0,1"
|
|
newline
|
|
bitfld.long 0xC 0.--5. " COUNT ,Actual number of remaining DMA transfers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
line.long 0x10 "DMA4CTRL,MibSPI DMA Channel Control Register 1"
|
|
bitfld.long 0x10 31. " ONESHOT ,Auto-disable of DMA channel after ICOUNT+1 transfers" "0,1"
|
|
hexmask.long.byte 0x10 24.--30. 1. " BUFID ,Buffer utilized for DMA transfer"
|
|
bitfld.long 0x10 20.--23. " RXDMA_MAP ,Each MibSPI DMA channel can be linked to two physical DMA" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x10 16.--19. " TXDMA_MAP ,Each MibSPI DMA channel can be linked to two physical DMA" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x10 15. " RXDMAENA ,Receive data DMA channel enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 14. " TXDMAENA ,Transmit data DMA channel enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x10 13. " NOBRK ,Non-interleaved DMA block transfer" "Not performed,Performed"
|
|
bitfld.long 0x10 8.--12. " ICOUNT ,Initial count of DMA transfers" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32"
|
|
bitfld.long 0x10 6. " COUNTBIT17 ,17th bit of the COUNT field of DMAxCOUNT register" "0,1"
|
|
newline
|
|
bitfld.long 0x10 0.--5. " COUNT ,Actual number of remaining DMA transfers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
line.long 0x14 "DMA5CTRL,MibSPI DMA Channel Control Register 1"
|
|
bitfld.long 0x14 31. " ONESHOT ,Auto-disable of DMA channel after ICOUNT+1 transfers" "0,1"
|
|
hexmask.long.byte 0x14 24.--30. 1. " BUFID ,Buffer utilized for DMA transfer"
|
|
bitfld.long 0x14 20.--23. " RXDMA_MAP ,Each MibSPI DMA channel can be linked to two physical DMA" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x14 16.--19. " TXDMA_MAP ,Each MibSPI DMA channel can be linked to two physical DMA" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x14 15. " RXDMAENA ,Receive data DMA channel enable" "Disabled,Enabled"
|
|
bitfld.long 0x14 14. " TXDMAENA ,Transmit data DMA channel enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x14 13. " NOBRK ,Non-interleaved DMA block transfer" "Not performed,Performed"
|
|
bitfld.long 0x14 8.--12. " ICOUNT ,Initial count of DMA transfers" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32"
|
|
bitfld.long 0x14 6. " COUNTBIT17 ,17th bit of the COUNT field of DMAxCOUNT register" "0,1"
|
|
newline
|
|
bitfld.long 0x14 0.--5. " COUNT ,Actual number of remaining DMA transfers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
line.long 0x18 "DMA6CTRL,MibSPI DMA Channel Control Register 1"
|
|
bitfld.long 0x18 31. " ONESHOT ,Auto-disable of DMA channel after ICOUNT+1 transfers" "0,1"
|
|
hexmask.long.byte 0x18 24.--30. 1. " BUFID ,Buffer utilized for DMA transfer"
|
|
bitfld.long 0x18 20.--23. " RXDMA_MAP ,Each MibSPI DMA channel can be linked to two physical DMA" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x18 16.--19. " TXDMA_MAP ,Each MibSPI DMA channel can be linked to two physical DMA" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x18 15. " RXDMAENA ,Receive data DMA channel enable" "Disabled,Enabled"
|
|
bitfld.long 0x18 14. " TXDMAENA ,Transmit data DMA channel enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x18 13. " NOBRK ,Non-interleaved DMA block transfer" "Not performed,Performed"
|
|
bitfld.long 0x18 8.--12. " ICOUNT ,Initial count of DMA transfers" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32"
|
|
bitfld.long 0x18 6. " COUNTBIT17 ,17th bit of the COUNT field of DMAxCOUNT register" "0,1"
|
|
newline
|
|
bitfld.long 0x18 0.--5. " COUNT ,Actual number of remaining DMA transfers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
line.long 0x1C "DMA7CTRL,MibSPI DMA Channel Control Register 1"
|
|
bitfld.long 0x1C 31. " ONESHOT ,Auto-disable of DMA channel after ICOUNT+1 transfers" "0,1"
|
|
hexmask.long.byte 0x1C 24.--30. 1. " BUFID ,Buffer utilized for DMA transfer"
|
|
bitfld.long 0x1C 20.--23. " RXDMA_MAP ,Each MibSPI DMA channel can be linked to two physical DMA" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x1C 16.--19. " TXDMA_MAP ,Each MibSPI DMA channel can be linked to two physical DMA" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x1C 15. " RXDMAENA ,Receive data DMA channel enable" "Disabled,Enabled"
|
|
bitfld.long 0x1C 14. " TXDMAENA ,Transmit data DMA channel enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x1C 13. " NOBRK ,Non-interleaved DMA block transfer" "Not performed,Performed"
|
|
bitfld.long 0x1C 8.--12. " ICOUNT ,Initial count of DMA transfers" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32"
|
|
bitfld.long 0x1C 6. " COUNTBIT17 ,17th bit of the COUNT field of DMAxCOUNT register" "0,1"
|
|
newline
|
|
bitfld.long 0x1C 0.--5. " COUNT ,Actual number of remaining DMA transfers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
group.long 0xF8++0x1F
|
|
line.long 0x0 "DMA0 COUNT,MibSPI DMA0 COUNT Register"
|
|
hexmask.long.word 0x0 16.--31. 1. " ICOUNT0 ,Initial number of DMA transfers"
|
|
hexmask.long.word 0x0 0.--15. 1. " COUNT0 ,The actual number of remaining DMA transfers"
|
|
line.long 0x4 "DMA1 COUNT,MibSPI DMA1 COUNT Register"
|
|
hexmask.long.word 0x4 16.--31. 1. " ICOUNT1 ,Initial number of DMA transfers"
|
|
hexmask.long.word 0x4 0.--15. 1. " COUNT1 ,The actual number of remaining DMA transfers"
|
|
line.long 0x8 "DMA2 COUNT,MibSPI DMA2 COUNT Register"
|
|
hexmask.long.word 0x8 16.--31. 1. " ICOUNT2 ,Initial number of DMA transfers"
|
|
hexmask.long.word 0x8 0.--15. 1. " COUNT2 ,The actual number of remaining DMA transfers"
|
|
line.long 0xC "DMA3 COUNT,MibSPI DMA3 COUNT Register"
|
|
hexmask.long.word 0xC 16.--31. 1. " ICOUNT3 ,Initial number of DMA transfers"
|
|
hexmask.long.word 0xC 0.--15. 1. " COUNT3 ,The actual number of remaining DMA transfers"
|
|
line.long 0x10 "DMA4 COUNT,MibSPI DMA4 COUNT Register"
|
|
hexmask.long.word 0x10 16.--31. 1. " ICOUNT4 ,Initial number of DMA transfers"
|
|
hexmask.long.word 0x10 0.--15. 1. " COUNT4 ,The actual number of remaining DMA transfers"
|
|
line.long 0x14 "DMA5 COUNT,MibSPI DMA5 COUNT Register"
|
|
hexmask.long.word 0x14 16.--31. 1. " ICOUNT5 ,Initial number of DMA transfers"
|
|
hexmask.long.word 0x14 0.--15. 1. " COUNT5 ,The actual number of remaining DMA transfers"
|
|
line.long 0x18 "DMA6 COUNT,MibSPI DMA6 COUNT Register"
|
|
hexmask.long.word 0x18 16.--31. 1. " ICOUNT6 ,Initial number of DMA transfers"
|
|
hexmask.long.word 0x18 0.--15. 1. " COUNT6 ,The actual number of remaining DMA transfers"
|
|
line.long 0x1C "DMA7 COUNT,MibSPI DMA7 COUNT Register"
|
|
hexmask.long.word 0x1C 16.--31. 1. " ICOUNT7 ,Initial number of DMA transfers"
|
|
hexmask.long.word 0x1C 0.--15. 1. " COUNT7 ,The actual number of remaining DMA transfers"
|
|
group.long 0x118++0x03
|
|
line.long 0x00 "DMACNTLEN,MibSPI DMACNTLEN Register"
|
|
bitfld.long 0x00 0. " LARGECOUNT ,Counters select" "DMAxCTRL,DMAxCOUNT"
|
|
endif
|
|
group.long 0x120++0x03
|
|
line.long 0x00 "UERRCTRL,Uncorrectable Parity Error Control Register"
|
|
bitfld.long 0x00 8. " PTESTEN ,Parity memory test enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--3. " EDEN ,Error detection enable" "Enabled,Enabled,Enabled,Enabled,Enabled,Disabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled"
|
|
group.long 0x124++0x03
|
|
line.long 0x00 "UERRSTAT,Uncorrectable Parity Error Status Register"
|
|
eventfld.long 0x00 1. " EDFLG1 ,Uncorrectable parity error detection flag" "Not occurred,Occurred"
|
|
eventfld.long 0x00 0. " EDFLG0 ,Uncorrectable parity error detection flag" "Not occurred,Occurred"
|
|
hgroup.long 0x128++0x03
|
|
hide.long 0x00 "UERRADDR1,Uncorrectable Parity Error Address Register"
|
|
in
|
|
hgroup.long 0x12C++0x03
|
|
hide.long 0x00 "UERRADDR0,Uncorrectable Parity Error Address Register"
|
|
in
|
|
hgroup.long 0x130++0x03
|
|
hide.long 0x00 "RXOVRN_BUF_ADDR,Receive RAM Overrun Buffer Address Register"
|
|
in
|
|
sif cpuis("TMS570LS0714*")||cpuis("TMS570LS0914*")||cpuis("TMS570LS0232")
|
|
if (((per.l.be(ad:0xFFF7F400+0x134))&0x2)==0x2)
|
|
group.long 0x134++0x03
|
|
line.long 0x00 "IOLPBKTSTCR,SPI IO Loopback Test Control Register"
|
|
bitfld.long 0x00 24. " SCSFAILFLG ,Failure on SPISCS pin compare during analog loopback" "Not occurred,Occurred"
|
|
bitfld.long 0x00 20. " CTRL_BITERR ,Controls inducing of BITERR during I/O loopback test mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " CTRL_DESYNC ,Controls inducing of the desync error during I/O loopback test mode" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 18. " CTRL_PARERR ,Controls inducing of parity errors during I/O loopback test mode" "No error,Error"
|
|
bitfld.long 0x00 17. " CTRL_TIMEOUT ,Controls inducing of the timeout error during I/O loopbacK test mode" "No error,Error"
|
|
bitfld.long 0x00 16. " CTRL_DLENERR ,Controls inducing of the data length error during I/O loopback test mode" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 8.--11. " IOLPBKTSTENA ,Module I/O loopback test enable key" "Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Enabled,Disabled,Disabled,Disabled,Disabled,Disabled"
|
|
sif cpuis("TMS570LS0232")
|
|
bitfld.long 0x00 3.--5. " ERRSCSPIN ,Inject error on chip-select pin number" "/SPISCS[0],/SPISCS[1],/SPISCS[2],/SPISCS[3],?..."
|
|
else
|
|
bitfld.long 0x00 3.--5. " ERRSCSPIN ,Inject error on chip-select pin number" "/SPISCS[0],/SPISCS[1],/SPISCS[2],/SPISCS[3],/SPISCS[4],/SPISCS[5],/SPISCS[6],/SPISCS[7]"
|
|
endif
|
|
bitfld.long 0x00 2. " CTRLSCSPINERR ,Enable/disable the injection of an error on the SPISCS[3:0] pins" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 1. " LPBK_TYPE ,Module I/O loopback type (analog/digital)" "Digital,Analog"
|
|
bitfld.long 0x00 0. " RXP_ENA ,Enable analog loopback through the receive pin" "Transmit,Receive"
|
|
else
|
|
group.long 0x134++0x03
|
|
line.long 0x00 "IOLPBKTSTCR,SPI IO Loopback Test Control Register"
|
|
bitfld.long 0x00 24. " SCSFAILFLG ,Failure on SPISCS pin compare during analog loopback" "Not occurred,Occurred"
|
|
bitfld.long 0x00 20. " CTRL_BITERR ,Controls inducing of BITERR during I/O loopback test mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " CTRL_DESYNC ,Controls inducing of the desync error during I/O loopback test mode" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 18. " CTRL_PARERR ,Controls inducing of parity errors during I/O loopback test mode" "No error,Error"
|
|
bitfld.long 0x00 17. " CTRL_TIMEOUT ,Controls inducing of the timeout error during I/O loopbacK test mode" "No error,Error"
|
|
bitfld.long 0x00 16. " CTRL_DLENERR ,Controls inducing of the data length error during I/O loopback test mode" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 8.--11. " IOLPBKTSTENA ,Module I/O loopback test enable key" "Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Enabled,Disabled,Disabled,Disabled,Disabled,Disabled"
|
|
sif cpuis("TMS570LS0232")
|
|
bitfld.long 0x00 3.--5. " ERRSCSPIN ,Inject error on chip-select pin number" "/SPISCS[0],/SPISCS[1],/SPISCS[2],/SPISCS[3],?..."
|
|
else
|
|
bitfld.long 0x00 3.--5. " ERRSCSPIN ,Inject error on chip-select pin number" "/SPISCS[0],/SPISCS[1],/SPISCS[2],/SPISCS[3],/SPISCS[4],/SPISCS[5],/SPISCS[6],/SPISCS[7]"
|
|
endif
|
|
bitfld.long 0x00 2. " CTRLSCSPINERR ,Enable/disable the injection of an error on the SPISCS[3:0] pins" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 1. " LPBK_TYPE ,Module I/O loopback type (analog/digital)" "Digital,Analog"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0xFFF7F400+0x134))&0x2)==0x2)
|
|
group.long 0x134++0x03
|
|
line.long 0x00 "IOLPBKTSTCR,SPI IO Loopback Test Control Register"
|
|
bitfld.long 0x00 24. " SCSFAILFLG ,Failure on SPISCS pin compare during analog loopback" "Not occurred,Occurred"
|
|
bitfld.long 0x00 20. " CTRL_BITERR ,Controls inducing of BITERR during I/O loopback test mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " CTRL_DESYNC ,Controls inducing of the desync error during I/O loopback test mode" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 18. " CTRL_PARERR ,Controls inducing of parity errors during I/O loopback test mode" "No error,Error"
|
|
bitfld.long 0x00 17. " CTRL_TIMEOUT ,Controls inducing of the timeout error during I/O loopbacK test mode" "No error,Error"
|
|
bitfld.long 0x00 16. " CTRL_DLENERR ,Controls inducing of the data length error during I/O loopback test mode" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 8.--11. " IOLPBKTSTENA ,Module I/O loopback test enable key" "Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Enabled,Disabled,Disabled,Disabled,Disabled,Disabled"
|
|
bitfld.long 0x00 3.--5. " ERRSCSPIN ,Inject error on chip-select pin number" "/SPISCS[0],/SPISCS[1],/SPISCS[2],/SPISCS[3],/SPISCS[4],/SPISCS[5],/SPISCS[6],/SPISCS[7]"
|
|
bitfld.long 0x00 2. " CTRLSCSPINERR ,Enable/disable the injection of an error on the SPISCS[3:0] pins" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 1. " LPBK_TYPE ,Module I/O loopback type (analog/digital)" "Digital,Analog"
|
|
bitfld.long 0x00 0. " RXP_ENA ,Enable analog loopback through the receive pin" "Transmit,Receive"
|
|
else
|
|
group.long 0x134++0x03
|
|
line.long 0x00 "IOLPBKTSTCR,SPI IO Loopback Test Control Register"
|
|
bitfld.long 0x00 24. " SCSFAILFLG ,Failure on SPISCS pin compare during analog loopback" "Not occurred,Occurred"
|
|
bitfld.long 0x00 20. " CTRL_BITERR ,Controls inducing of BITERR during I/O loopback test mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " CTRL_DESYNC ,Controls inducing of the desync error during I/O loopback test mode" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 18. " CTRL_PARERR ,Controls inducing of parity errors during I/O loopback test mode" "No error,Error"
|
|
bitfld.long 0x00 17. " CTRL_TIMEOUT ,Controls inducing of the timeout error during I/O loopbacK test mode" "No error,Error"
|
|
bitfld.long 0x00 16. " CTRL_DLENERR ,Controls inducing of the data length error during I/O loopback test mode" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 8.--11. " IOLPBKTSTENA ,Module I/O loopback test enable key" "Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Enabled,Disabled,Disabled,Disabled,Disabled,Disabled"
|
|
bitfld.long 0x00 3.--5. " ERRSCSPIN ,Inject error on chip-select pin number" "/SPISCS[0],/SPISCS[1],/SPISCS[2],/SPISCS[3],/SPISCS[4],/SPISCS[5],/SPISCS[6],/SPISCS[7]"
|
|
bitfld.long 0x00 2. " CTRLSCSPINERR ,Enable/disable the injection of an error on the SPISCS[3:0] pins" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 1. " LPBK_TYPE ,Module I/O loopback type (analog/digital)" "Digital,Analog"
|
|
endif
|
|
endif
|
|
sif (cpu()=="TMS570LC4357"||cpu()==("TMS570LS0332")||cpu()==("TMS570LS0432")||cpuis("TMS570LS1114*")||cpuis("TMS570LS1115*")||cpuis("TMS570LS1224*")||cpuis("TMS570LS1225*")||cpuis("TMS570LS1227*")||cpuis("TMS570LS0232")||cpuis("TMS570LS0714*")||cpuis("TMS570LS0914*"))
|
|
width 21.
|
|
newline
|
|
group.long 0x138++0x07
|
|
line.long 0x00 "EXTENDED_PRESCALE_1, SPI Extended Prescale Register 1"
|
|
hexmask.long.word 0x00 16.--26. 1. " EPRESCALE_FMT1 , Extended Prescale value for SPIFMT1"
|
|
hexmask.long.word 0x00 0.--10. 1. " EPRESCALE_FMT0 , Extended Prescale value for SPIFMT0"
|
|
line.long 0x04 "EXTENDED_PRESCALE_2, SPI Extended Prescale Register 2"
|
|
hexmask.long.word 0x04 16.--26. 1. " EPRESCALE_FMT3 , Extended Prescale value for SPIFMT3"
|
|
hexmask.long.word 0x04 0.--10. 1. " EPRESCALE_FMT2 , Extended Prescale value for SPIFMT2"
|
|
endif
|
|
sif !cpuis("TMS570LS0232")&&!cpuis("TMS570LS0714*")&&!cpuis("TMS570LS0914*")
|
|
sif (cpu()=="TMS570LC4357"||cpu()==("TMS570LS0332")||cpu()==("TMS570LS0432")||cpuis("TMS570LS1114*")||cpuis("TMS570LS1115*")||cpuis("TMS570LS1224*")||cpuis("TMS570LS1225*")||cpuis("TMS570LS1227*"))
|
|
sif cpuis("TMS570LC4357")
|
|
group.long 0x140++0x03
|
|
line.long 0x00 "ECCDIAG_CTRL, ECC Diagnostic Control register"
|
|
bitfld.long 0x00 0.--3. " ECCDIAG_EN , ECC Diagnostic mode Enable Key bits" "Disabled,Disabled,Disabled,Disabled,Disabled,Enabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled"
|
|
endif
|
|
if ((per.l(ad:0xFFF7F400+0x140)&0x5)==0x5)
|
|
group.long 0x144++0x03
|
|
line.long 0x00 "ECCDIAG_STAT, ECC Diagnostic Status register"
|
|
eventfld.long 0x00 17. " DEFLG[1] , Double bit Error is detected for RXRAM" "No error,Error"
|
|
eventfld.long 0x00 16. " DEFLG[0] , Double bit Error is detected for TXRAM" "No error,Error"
|
|
eventfld.long 0x00 1. " SEFLG[1] , Single bit Error is detected for RXRAM" "No error,Error"
|
|
eventfld.long 0x00 0. " SEFLG[0] , Single bit Error is detected for TXRAM" "No error,Error"
|
|
else
|
|
hgroup.long 0x144++0x03
|
|
hide.long 0x00 "ECCDIAG_STAT, ECC Diagnostic Status register"
|
|
in
|
|
endif
|
|
hgroup.long 0x148++0x03
|
|
hide.long 0x00 "SBERRADDR1, Single Bit Error Address Register - RXRAM"
|
|
in
|
|
hgroup.long 0x14C++0x03
|
|
hide.long 0x00 "SBERRADDR0, Single Bit Error Address Register - TXRAM"
|
|
in
|
|
endif
|
|
endif
|
|
sif cpuis("TMS570LS0232")||cpuis("TMS570LS0714*")||cpuis("TMS570LS0914*")
|
|
endian.be
|
|
endif
|
|
width 0xB
|
|
tree.end
|
|
tree "MibSPI RAM"
|
|
base ad:0xFF0E0000
|
|
sif cpuis("TMS570LS0232")||cpuis("TMS570LS0714*")||cpuis("TMS570LS0914*")
|
|
endian.be
|
|
endif
|
|
width 11.
|
|
sif (cpu()==("TMS570LS0332")||cpu()==("TMS570LS0432")||cpuis("TMS570LS1114*")||cpuis("TMS570LS1115*")||cpuis("TMS570LS1224*")||cpuis("TMS570LS1225*")||cpuis("TMS570LS1227*"))
|
|
group.long 0x0++0x03
|
|
line.long 0x00 "TXRAM, Multi-buffer RAM Transmit Data Register 0"
|
|
bitfld.long 0x00 29.--31. " BUFMODE , Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip Single Transfer,Skip Overwrite,Skip ST-Overwrite,Continuous,Suspend Single Transfer,Suspend Overwrite,Suspend ST-Overwrite"
|
|
bitfld.long 0x00 28. " CSHOLD , Chip select hold mode" "Deactivated,Activated"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK , Lock two consecutive buffer words" "0,1"
|
|
bitfld.long 0x00 26. " WDEL , Enable the delay counter at the end of the current transaction" "Disable,Enable"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL , Data word format select" "Format 0,Format 1,Format 2,Format 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR , Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA , Transfer data"
|
|
group.long 0x4++0x03
|
|
line.long 0x00 "TXRAM, Multi-buffer RAM Transmit Data Register 1"
|
|
bitfld.long 0x00 29.--31. " BUFMODE , Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip Single Transfer,Skip Overwrite,Skip ST-Overwrite,Continuous,Suspend Single Transfer,Suspend Overwrite,Suspend ST-Overwrite"
|
|
bitfld.long 0x00 28. " CSHOLD , Chip select hold mode" "Deactivated,Activated"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK , Lock two consecutive buffer words" "0,1"
|
|
bitfld.long 0x00 26. " WDEL , Enable the delay counter at the end of the current transaction" "Disable,Enable"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL , Data word format select" "Format 0,Format 1,Format 2,Format 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR , Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA , Transfer data"
|
|
group.long 0x8++0x03
|
|
line.long 0x00 "TXRAM, Multi-buffer RAM Transmit Data Register 2"
|
|
bitfld.long 0x00 29.--31. " BUFMODE , Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip Single Transfer,Skip Overwrite,Skip ST-Overwrite,Continuous,Suspend Single Transfer,Suspend Overwrite,Suspend ST-Overwrite"
|
|
bitfld.long 0x00 28. " CSHOLD , Chip select hold mode" "Deactivated,Activated"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK , Lock two consecutive buffer words" "0,1"
|
|
bitfld.long 0x00 26. " WDEL , Enable the delay counter at the end of the current transaction" "Disable,Enable"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL , Data word format select" "Format 0,Format 1,Format 2,Format 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR , Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA , Transfer data"
|
|
group.long 0xC++0x03
|
|
line.long 0x00 "TXRAM, Multi-buffer RAM Transmit Data Register 3"
|
|
bitfld.long 0x00 29.--31. " BUFMODE , Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip Single Transfer,Skip Overwrite,Skip ST-Overwrite,Continuous,Suspend Single Transfer,Suspend Overwrite,Suspend ST-Overwrite"
|
|
bitfld.long 0x00 28. " CSHOLD , Chip select hold mode" "Deactivated,Activated"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK , Lock two consecutive buffer words" "0,1"
|
|
bitfld.long 0x00 26. " WDEL , Enable the delay counter at the end of the current transaction" "Disable,Enable"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL , Data word format select" "Format 0,Format 1,Format 2,Format 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR , Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA , Transfer data"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "TXRAM, Multi-buffer RAM Transmit Data Register 4"
|
|
bitfld.long 0x00 29.--31. " BUFMODE , Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip Single Transfer,Skip Overwrite,Skip ST-Overwrite,Continuous,Suspend Single Transfer,Suspend Overwrite,Suspend ST-Overwrite"
|
|
bitfld.long 0x00 28. " CSHOLD , Chip select hold mode" "Deactivated,Activated"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK , Lock two consecutive buffer words" "0,1"
|
|
bitfld.long 0x00 26. " WDEL , Enable the delay counter at the end of the current transaction" "Disable,Enable"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL , Data word format select" "Format 0,Format 1,Format 2,Format 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR , Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA , Transfer data"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "TXRAM, Multi-buffer RAM Transmit Data Register 5"
|
|
bitfld.long 0x00 29.--31. " BUFMODE , Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip Single Transfer,Skip Overwrite,Skip ST-Overwrite,Continuous,Suspend Single Transfer,Suspend Overwrite,Suspend ST-Overwrite"
|
|
bitfld.long 0x00 28. " CSHOLD , Chip select hold mode" "Deactivated,Activated"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK , Lock two consecutive buffer words" "0,1"
|
|
bitfld.long 0x00 26. " WDEL , Enable the delay counter at the end of the current transaction" "Disable,Enable"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL , Data word format select" "Format 0,Format 1,Format 2,Format 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR , Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA , Transfer data"
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "TXRAM, Multi-buffer RAM Transmit Data Register 6"
|
|
bitfld.long 0x00 29.--31. " BUFMODE , Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip Single Transfer,Skip Overwrite,Skip ST-Overwrite,Continuous,Suspend Single Transfer,Suspend Overwrite,Suspend ST-Overwrite"
|
|
bitfld.long 0x00 28. " CSHOLD , Chip select hold mode" "Deactivated,Activated"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK , Lock two consecutive buffer words" "0,1"
|
|
bitfld.long 0x00 26. " WDEL , Enable the delay counter at the end of the current transaction" "Disable,Enable"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL , Data word format select" "Format 0,Format 1,Format 2,Format 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR , Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA , Transfer data"
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "TXRAM, Multi-buffer RAM Transmit Data Register 7"
|
|
bitfld.long 0x00 29.--31. " BUFMODE , Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip Single Transfer,Skip Overwrite,Skip ST-Overwrite,Continuous,Suspend Single Transfer,Suspend Overwrite,Suspend ST-Overwrite"
|
|
bitfld.long 0x00 28. " CSHOLD , Chip select hold mode" "Deactivated,Activated"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK , Lock two consecutive buffer words" "0,1"
|
|
bitfld.long 0x00 26. " WDEL , Enable the delay counter at the end of the current transaction" "Disable,Enable"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL , Data word format select" "Format 0,Format 1,Format 2,Format 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR , Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA , Transfer data"
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "TXRAM, Multi-buffer RAM Transmit Data Register 8"
|
|
bitfld.long 0x00 29.--31. " BUFMODE , Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip Single Transfer,Skip Overwrite,Skip ST-Overwrite,Continuous,Suspend Single Transfer,Suspend Overwrite,Suspend ST-Overwrite"
|
|
bitfld.long 0x00 28. " CSHOLD , Chip select hold mode" "Deactivated,Activated"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK , Lock two consecutive buffer words" "0,1"
|
|
bitfld.long 0x00 26. " WDEL , Enable the delay counter at the end of the current transaction" "Disable,Enable"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL , Data word format select" "Format 0,Format 1,Format 2,Format 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR , Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA , Transfer data"
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "TXRAM, Multi-buffer RAM Transmit Data Register 9"
|
|
bitfld.long 0x00 29.--31. " BUFMODE , Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip Single Transfer,Skip Overwrite,Skip ST-Overwrite,Continuous,Suspend Single Transfer,Suspend Overwrite,Suspend ST-Overwrite"
|
|
bitfld.long 0x00 28. " CSHOLD , Chip select hold mode" "Deactivated,Activated"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK , Lock two consecutive buffer words" "0,1"
|
|
bitfld.long 0x00 26. " WDEL , Enable the delay counter at the end of the current transaction" "Disable,Enable"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL , Data word format select" "Format 0,Format 1,Format 2,Format 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR , Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA , Transfer data"
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "TXRAM, Multi-buffer RAM Transmit Data Register 10"
|
|
bitfld.long 0x00 29.--31. " BUFMODE , Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip Single Transfer,Skip Overwrite,Skip ST-Overwrite,Continuous,Suspend Single Transfer,Suspend Overwrite,Suspend ST-Overwrite"
|
|
bitfld.long 0x00 28. " CSHOLD , Chip select hold mode" "Deactivated,Activated"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK , Lock two consecutive buffer words" "0,1"
|
|
bitfld.long 0x00 26. " WDEL , Enable the delay counter at the end of the current transaction" "Disable,Enable"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL , Data word format select" "Format 0,Format 1,Format 2,Format 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR , Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA , Transfer data"
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "TXRAM, Multi-buffer RAM Transmit Data Register 11"
|
|
bitfld.long 0x00 29.--31. " BUFMODE , Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip Single Transfer,Skip Overwrite,Skip ST-Overwrite,Continuous,Suspend Single Transfer,Suspend Overwrite,Suspend ST-Overwrite"
|
|
bitfld.long 0x00 28. " CSHOLD , Chip select hold mode" "Deactivated,Activated"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK , Lock two consecutive buffer words" "0,1"
|
|
bitfld.long 0x00 26. " WDEL , Enable the delay counter at the end of the current transaction" "Disable,Enable"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL , Data word format select" "Format 0,Format 1,Format 2,Format 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR , Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA , Transfer data"
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "TXRAM, Multi-buffer RAM Transmit Data Register 12"
|
|
bitfld.long 0x00 29.--31. " BUFMODE , Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip Single Transfer,Skip Overwrite,Skip ST-Overwrite,Continuous,Suspend Single Transfer,Suspend Overwrite,Suspend ST-Overwrite"
|
|
bitfld.long 0x00 28. " CSHOLD , Chip select hold mode" "Deactivated,Activated"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK , Lock two consecutive buffer words" "0,1"
|
|
bitfld.long 0x00 26. " WDEL , Enable the delay counter at the end of the current transaction" "Disable,Enable"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL , Data word format select" "Format 0,Format 1,Format 2,Format 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR , Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA , Transfer data"
|
|
group.long 0x34++0x03
|
|
line.long 0x00 "TXRAM, Multi-buffer RAM Transmit Data Register 13"
|
|
bitfld.long 0x00 29.--31. " BUFMODE , Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip Single Transfer,Skip Overwrite,Skip ST-Overwrite,Continuous,Suspend Single Transfer,Suspend Overwrite,Suspend ST-Overwrite"
|
|
bitfld.long 0x00 28. " CSHOLD , Chip select hold mode" "Deactivated,Activated"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK , Lock two consecutive buffer words" "0,1"
|
|
bitfld.long 0x00 26. " WDEL , Enable the delay counter at the end of the current transaction" "Disable,Enable"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL , Data word format select" "Format 0,Format 1,Format 2,Format 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR , Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA , Transfer data"
|
|
group.long 0x38++0x03
|
|
line.long 0x00 "TXRAM, Multi-buffer RAM Transmit Data Register 14"
|
|
bitfld.long 0x00 29.--31. " BUFMODE , Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip Single Transfer,Skip Overwrite,Skip ST-Overwrite,Continuous,Suspend Single Transfer,Suspend Overwrite,Suspend ST-Overwrite"
|
|
bitfld.long 0x00 28. " CSHOLD , Chip select hold mode" "Deactivated,Activated"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK , Lock two consecutive buffer words" "0,1"
|
|
bitfld.long 0x00 26. " WDEL , Enable the delay counter at the end of the current transaction" "Disable,Enable"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL , Data word format select" "Format 0,Format 1,Format 2,Format 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR , Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA , Transfer data"
|
|
group.long 0x3C++0x03
|
|
line.long 0x00 "TXRAM, Multi-buffer RAM Transmit Data Register 15"
|
|
bitfld.long 0x00 29.--31. " BUFMODE , Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip Single Transfer,Skip Overwrite,Skip ST-Overwrite,Continuous,Suspend Single Transfer,Suspend Overwrite,Suspend ST-Overwrite"
|
|
bitfld.long 0x00 28. " CSHOLD , Chip select hold mode" "Deactivated,Activated"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK , Lock two consecutive buffer words" "0,1"
|
|
bitfld.long 0x00 26. " WDEL , Enable the delay counter at the end of the current transaction" "Disable,Enable"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL , Data word format select" "Format 0,Format 1,Format 2,Format 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR , Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA , Transfer data"
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "TXRAM, Multi-buffer RAM Transmit Data Register 16"
|
|
bitfld.long 0x00 29.--31. " BUFMODE , Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip Single Transfer,Skip Overwrite,Skip ST-Overwrite,Continuous,Suspend Single Transfer,Suspend Overwrite,Suspend ST-Overwrite"
|
|
bitfld.long 0x00 28. " CSHOLD , Chip select hold mode" "Deactivated,Activated"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK , Lock two consecutive buffer words" "0,1"
|
|
bitfld.long 0x00 26. " WDEL , Enable the delay counter at the end of the current transaction" "Disable,Enable"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL , Data word format select" "Format 0,Format 1,Format 2,Format 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR , Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA , Transfer data"
|
|
group.long 0x44++0x03
|
|
line.long 0x00 "TXRAM, Multi-buffer RAM Transmit Data Register 17"
|
|
bitfld.long 0x00 29.--31. " BUFMODE , Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip Single Transfer,Skip Overwrite,Skip ST-Overwrite,Continuous,Suspend Single Transfer,Suspend Overwrite,Suspend ST-Overwrite"
|
|
bitfld.long 0x00 28. " CSHOLD , Chip select hold mode" "Deactivated,Activated"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK , Lock two consecutive buffer words" "0,1"
|
|
bitfld.long 0x00 26. " WDEL , Enable the delay counter at the end of the current transaction" "Disable,Enable"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL , Data word format select" "Format 0,Format 1,Format 2,Format 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR , Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA , Transfer data"
|
|
group.long 0x48++0x03
|
|
line.long 0x00 "TXRAM, Multi-buffer RAM Transmit Data Register 18"
|
|
bitfld.long 0x00 29.--31. " BUFMODE , Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip Single Transfer,Skip Overwrite,Skip ST-Overwrite,Continuous,Suspend Single Transfer,Suspend Overwrite,Suspend ST-Overwrite"
|
|
bitfld.long 0x00 28. " CSHOLD , Chip select hold mode" "Deactivated,Activated"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK , Lock two consecutive buffer words" "0,1"
|
|
bitfld.long 0x00 26. " WDEL , Enable the delay counter at the end of the current transaction" "Disable,Enable"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL , Data word format select" "Format 0,Format 1,Format 2,Format 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR , Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA , Transfer data"
|
|
group.long 0x4C++0x03
|
|
line.long 0x00 "TXRAM, Multi-buffer RAM Transmit Data Register 19"
|
|
bitfld.long 0x00 29.--31. " BUFMODE , Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip Single Transfer,Skip Overwrite,Skip ST-Overwrite,Continuous,Suspend Single Transfer,Suspend Overwrite,Suspend ST-Overwrite"
|
|
bitfld.long 0x00 28. " CSHOLD , Chip select hold mode" "Deactivated,Activated"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK , Lock two consecutive buffer words" "0,1"
|
|
bitfld.long 0x00 26. " WDEL , Enable the delay counter at the end of the current transaction" "Disable,Enable"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL , Data word format select" "Format 0,Format 1,Format 2,Format 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR , Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA , Transfer data"
|
|
group.long 0x50++0x03
|
|
line.long 0x00 "TXRAM, Multi-buffer RAM Transmit Data Register 20"
|
|
bitfld.long 0x00 29.--31. " BUFMODE , Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip Single Transfer,Skip Overwrite,Skip ST-Overwrite,Continuous,Suspend Single Transfer,Suspend Overwrite,Suspend ST-Overwrite"
|
|
bitfld.long 0x00 28. " CSHOLD , Chip select hold mode" "Deactivated,Activated"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK , Lock two consecutive buffer words" "0,1"
|
|
bitfld.long 0x00 26. " WDEL , Enable the delay counter at the end of the current transaction" "Disable,Enable"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL , Data word format select" "Format 0,Format 1,Format 2,Format 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR , Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA , Transfer data"
|
|
group.long 0x54++0x03
|
|
line.long 0x00 "TXRAM, Multi-buffer RAM Transmit Data Register 21"
|
|
bitfld.long 0x00 29.--31. " BUFMODE , Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip Single Transfer,Skip Overwrite,Skip ST-Overwrite,Continuous,Suspend Single Transfer,Suspend Overwrite,Suspend ST-Overwrite"
|
|
bitfld.long 0x00 28. " CSHOLD , Chip select hold mode" "Deactivated,Activated"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK , Lock two consecutive buffer words" "0,1"
|
|
bitfld.long 0x00 26. " WDEL , Enable the delay counter at the end of the current transaction" "Disable,Enable"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL , Data word format select" "Format 0,Format 1,Format 2,Format 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR , Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA , Transfer data"
|
|
group.long 0x58++0x03
|
|
line.long 0x00 "TXRAM, Multi-buffer RAM Transmit Data Register 22"
|
|
bitfld.long 0x00 29.--31. " BUFMODE , Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip Single Transfer,Skip Overwrite,Skip ST-Overwrite,Continuous,Suspend Single Transfer,Suspend Overwrite,Suspend ST-Overwrite"
|
|
bitfld.long 0x00 28. " CSHOLD , Chip select hold mode" "Deactivated,Activated"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK , Lock two consecutive buffer words" "0,1"
|
|
bitfld.long 0x00 26. " WDEL , Enable the delay counter at the end of the current transaction" "Disable,Enable"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL , Data word format select" "Format 0,Format 1,Format 2,Format 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR , Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA , Transfer data"
|
|
group.long 0x5C++0x03
|
|
line.long 0x00 "TXRAM, Multi-buffer RAM Transmit Data Register 23"
|
|
bitfld.long 0x00 29.--31. " BUFMODE , Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip Single Transfer,Skip Overwrite,Skip ST-Overwrite,Continuous,Suspend Single Transfer,Suspend Overwrite,Suspend ST-Overwrite"
|
|
bitfld.long 0x00 28. " CSHOLD , Chip select hold mode" "Deactivated,Activated"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK , Lock two consecutive buffer words" "0,1"
|
|
bitfld.long 0x00 26. " WDEL , Enable the delay counter at the end of the current transaction" "Disable,Enable"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL , Data word format select" "Format 0,Format 1,Format 2,Format 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR , Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA , Transfer data"
|
|
group.long 0x60++0x03
|
|
line.long 0x00 "TXRAM, Multi-buffer RAM Transmit Data Register 24"
|
|
bitfld.long 0x00 29.--31. " BUFMODE , Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip Single Transfer,Skip Overwrite,Skip ST-Overwrite,Continuous,Suspend Single Transfer,Suspend Overwrite,Suspend ST-Overwrite"
|
|
bitfld.long 0x00 28. " CSHOLD , Chip select hold mode" "Deactivated,Activated"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK , Lock two consecutive buffer words" "0,1"
|
|
bitfld.long 0x00 26. " WDEL , Enable the delay counter at the end of the current transaction" "Disable,Enable"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL , Data word format select" "Format 0,Format 1,Format 2,Format 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR , Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA , Transfer data"
|
|
group.long 0x64++0x03
|
|
line.long 0x00 "TXRAM, Multi-buffer RAM Transmit Data Register 25"
|
|
bitfld.long 0x00 29.--31. " BUFMODE , Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip Single Transfer,Skip Overwrite,Skip ST-Overwrite,Continuous,Suspend Single Transfer,Suspend Overwrite,Suspend ST-Overwrite"
|
|
bitfld.long 0x00 28. " CSHOLD , Chip select hold mode" "Deactivated,Activated"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK , Lock two consecutive buffer words" "0,1"
|
|
bitfld.long 0x00 26. " WDEL , Enable the delay counter at the end of the current transaction" "Disable,Enable"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL , Data word format select" "Format 0,Format 1,Format 2,Format 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR , Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA , Transfer data"
|
|
group.long 0x68++0x03
|
|
line.long 0x00 "TXRAM, Multi-buffer RAM Transmit Data Register 26"
|
|
bitfld.long 0x00 29.--31. " BUFMODE , Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip Single Transfer,Skip Overwrite,Skip ST-Overwrite,Continuous,Suspend Single Transfer,Suspend Overwrite,Suspend ST-Overwrite"
|
|
bitfld.long 0x00 28. " CSHOLD , Chip select hold mode" "Deactivated,Activated"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK , Lock two consecutive buffer words" "0,1"
|
|
bitfld.long 0x00 26. " WDEL , Enable the delay counter at the end of the current transaction" "Disable,Enable"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL , Data word format select" "Format 0,Format 1,Format 2,Format 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR , Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA , Transfer data"
|
|
group.long 0x6C++0x03
|
|
line.long 0x00 "TXRAM, Multi-buffer RAM Transmit Data Register 27"
|
|
bitfld.long 0x00 29.--31. " BUFMODE , Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip Single Transfer,Skip Overwrite,Skip ST-Overwrite,Continuous,Suspend Single Transfer,Suspend Overwrite,Suspend ST-Overwrite"
|
|
bitfld.long 0x00 28. " CSHOLD , Chip select hold mode" "Deactivated,Activated"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK , Lock two consecutive buffer words" "0,1"
|
|
bitfld.long 0x00 26. " WDEL , Enable the delay counter at the end of the current transaction" "Disable,Enable"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL , Data word format select" "Format 0,Format 1,Format 2,Format 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR , Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA , Transfer data"
|
|
group.long 0x70++0x03
|
|
line.long 0x00 "TXRAM, Multi-buffer RAM Transmit Data Register 28"
|
|
bitfld.long 0x00 29.--31. " BUFMODE , Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip Single Transfer,Skip Overwrite,Skip ST-Overwrite,Continuous,Suspend Single Transfer,Suspend Overwrite,Suspend ST-Overwrite"
|
|
bitfld.long 0x00 28. " CSHOLD , Chip select hold mode" "Deactivated,Activated"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK , Lock two consecutive buffer words" "0,1"
|
|
bitfld.long 0x00 26. " WDEL , Enable the delay counter at the end of the current transaction" "Disable,Enable"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL , Data word format select" "Format 0,Format 1,Format 2,Format 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR , Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA , Transfer data"
|
|
group.long 0x74++0x03
|
|
line.long 0x00 "TXRAM, Multi-buffer RAM Transmit Data Register 29"
|
|
bitfld.long 0x00 29.--31. " BUFMODE , Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip Single Transfer,Skip Overwrite,Skip ST-Overwrite,Continuous,Suspend Single Transfer,Suspend Overwrite,Suspend ST-Overwrite"
|
|
bitfld.long 0x00 28. " CSHOLD , Chip select hold mode" "Deactivated,Activated"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK , Lock two consecutive buffer words" "0,1"
|
|
bitfld.long 0x00 26. " WDEL , Enable the delay counter at the end of the current transaction" "Disable,Enable"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL , Data word format select" "Format 0,Format 1,Format 2,Format 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR , Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA , Transfer data"
|
|
group.long 0x78++0x03
|
|
line.long 0x00 "TXRAM, Multi-buffer RAM Transmit Data Register 30"
|
|
bitfld.long 0x00 29.--31. " BUFMODE , Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip Single Transfer,Skip Overwrite,Skip ST-Overwrite,Continuous,Suspend Single Transfer,Suspend Overwrite,Suspend ST-Overwrite"
|
|
bitfld.long 0x00 28. " CSHOLD , Chip select hold mode" "Deactivated,Activated"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK , Lock two consecutive buffer words" "0,1"
|
|
bitfld.long 0x00 26. " WDEL , Enable the delay counter at the end of the current transaction" "Disable,Enable"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL , Data word format select" "Format 0,Format 1,Format 2,Format 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR , Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA , Transfer data"
|
|
group.long 0x7C++0x03
|
|
line.long 0x00 "TXRAM, Multi-buffer RAM Transmit Data Register 31"
|
|
bitfld.long 0x00 29.--31. " BUFMODE , Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip Single Transfer,Skip Overwrite,Skip ST-Overwrite,Continuous,Suspend Single Transfer,Suspend Overwrite,Suspend ST-Overwrite"
|
|
bitfld.long 0x00 28. " CSHOLD , Chip select hold mode" "Deactivated,Activated"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK , Lock two consecutive buffer words" "0,1"
|
|
bitfld.long 0x00 26. " WDEL , Enable the delay counter at the end of the current transaction" "Disable,Enable"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL , Data word format select" "Format 0,Format 1,Format 2,Format 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR , Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA , Transfer data"
|
|
group.long 0x80++0x03
|
|
line.long 0x00 "TXRAM, Multi-buffer RAM Transmit Data Register 32"
|
|
bitfld.long 0x00 29.--31. " BUFMODE , Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip Single Transfer,Skip Overwrite,Skip ST-Overwrite,Continuous,Suspend Single Transfer,Suspend Overwrite,Suspend ST-Overwrite"
|
|
bitfld.long 0x00 28. " CSHOLD , Chip select hold mode" "Deactivated,Activated"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK , Lock two consecutive buffer words" "0,1"
|
|
bitfld.long 0x00 26. " WDEL , Enable the delay counter at the end of the current transaction" "Disable,Enable"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL , Data word format select" "Format 0,Format 1,Format 2,Format 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR , Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA , Transfer data"
|
|
group.long 0x84++0x03
|
|
line.long 0x00 "TXRAM, Multi-buffer RAM Transmit Data Register 33"
|
|
bitfld.long 0x00 29.--31. " BUFMODE , Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip Single Transfer,Skip Overwrite,Skip ST-Overwrite,Continuous,Suspend Single Transfer,Suspend Overwrite,Suspend ST-Overwrite"
|
|
bitfld.long 0x00 28. " CSHOLD , Chip select hold mode" "Deactivated,Activated"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK , Lock two consecutive buffer words" "0,1"
|
|
bitfld.long 0x00 26. " WDEL , Enable the delay counter at the end of the current transaction" "Disable,Enable"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL , Data word format select" "Format 0,Format 1,Format 2,Format 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR , Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA , Transfer data"
|
|
group.long 0x88++0x03
|
|
line.long 0x00 "TXRAM, Multi-buffer RAM Transmit Data Register 34"
|
|
bitfld.long 0x00 29.--31. " BUFMODE , Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip Single Transfer,Skip Overwrite,Skip ST-Overwrite,Continuous,Suspend Single Transfer,Suspend Overwrite,Suspend ST-Overwrite"
|
|
bitfld.long 0x00 28. " CSHOLD , Chip select hold mode" "Deactivated,Activated"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK , Lock two consecutive buffer words" "0,1"
|
|
bitfld.long 0x00 26. " WDEL , Enable the delay counter at the end of the current transaction" "Disable,Enable"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL , Data word format select" "Format 0,Format 1,Format 2,Format 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR , Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA , Transfer data"
|
|
group.long 0x8C++0x03
|
|
line.long 0x00 "TXRAM, Multi-buffer RAM Transmit Data Register 35"
|
|
bitfld.long 0x00 29.--31. " BUFMODE , Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip Single Transfer,Skip Overwrite,Skip ST-Overwrite,Continuous,Suspend Single Transfer,Suspend Overwrite,Suspend ST-Overwrite"
|
|
bitfld.long 0x00 28. " CSHOLD , Chip select hold mode" "Deactivated,Activated"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK , Lock two consecutive buffer words" "0,1"
|
|
bitfld.long 0x00 26. " WDEL , Enable the delay counter at the end of the current transaction" "Disable,Enable"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL , Data word format select" "Format 0,Format 1,Format 2,Format 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR , Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA , Transfer data"
|
|
group.long 0x90++0x03
|
|
line.long 0x00 "TXRAM, Multi-buffer RAM Transmit Data Register 36"
|
|
bitfld.long 0x00 29.--31. " BUFMODE , Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip Single Transfer,Skip Overwrite,Skip ST-Overwrite,Continuous,Suspend Single Transfer,Suspend Overwrite,Suspend ST-Overwrite"
|
|
bitfld.long 0x00 28. " CSHOLD , Chip select hold mode" "Deactivated,Activated"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK , Lock two consecutive buffer words" "0,1"
|
|
bitfld.long 0x00 26. " WDEL , Enable the delay counter at the end of the current transaction" "Disable,Enable"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL , Data word format select" "Format 0,Format 1,Format 2,Format 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR , Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA , Transfer data"
|
|
group.long 0x94++0x03
|
|
line.long 0x00 "TXRAM, Multi-buffer RAM Transmit Data Register 37"
|
|
bitfld.long 0x00 29.--31. " BUFMODE , Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip Single Transfer,Skip Overwrite,Skip ST-Overwrite,Continuous,Suspend Single Transfer,Suspend Overwrite,Suspend ST-Overwrite"
|
|
bitfld.long 0x00 28. " CSHOLD , Chip select hold mode" "Deactivated,Activated"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK , Lock two consecutive buffer words" "0,1"
|
|
bitfld.long 0x00 26. " WDEL , Enable the delay counter at the end of the current transaction" "Disable,Enable"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL , Data word format select" "Format 0,Format 1,Format 2,Format 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR , Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA , Transfer data"
|
|
group.long 0x98++0x03
|
|
line.long 0x00 "TXRAM, Multi-buffer RAM Transmit Data Register 38"
|
|
bitfld.long 0x00 29.--31. " BUFMODE , Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip Single Transfer,Skip Overwrite,Skip ST-Overwrite,Continuous,Suspend Single Transfer,Suspend Overwrite,Suspend ST-Overwrite"
|
|
bitfld.long 0x00 28. " CSHOLD , Chip select hold mode" "Deactivated,Activated"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK , Lock two consecutive buffer words" "0,1"
|
|
bitfld.long 0x00 26. " WDEL , Enable the delay counter at the end of the current transaction" "Disable,Enable"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL , Data word format select" "Format 0,Format 1,Format 2,Format 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR , Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA , Transfer data"
|
|
group.long 0x9C++0x03
|
|
line.long 0x00 "TXRAM, Multi-buffer RAM Transmit Data Register 39"
|
|
bitfld.long 0x00 29.--31. " BUFMODE , Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip Single Transfer,Skip Overwrite,Skip ST-Overwrite,Continuous,Suspend Single Transfer,Suspend Overwrite,Suspend ST-Overwrite"
|
|
bitfld.long 0x00 28. " CSHOLD , Chip select hold mode" "Deactivated,Activated"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK , Lock two consecutive buffer words" "0,1"
|
|
bitfld.long 0x00 26. " WDEL , Enable the delay counter at the end of the current transaction" "Disable,Enable"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL , Data word format select" "Format 0,Format 1,Format 2,Format 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR , Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA , Transfer data"
|
|
group.long 0xA0++0x03
|
|
line.long 0x00 "TXRAM, Multi-buffer RAM Transmit Data Register 40"
|
|
bitfld.long 0x00 29.--31. " BUFMODE , Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip Single Transfer,Skip Overwrite,Skip ST-Overwrite,Continuous,Suspend Single Transfer,Suspend Overwrite,Suspend ST-Overwrite"
|
|
bitfld.long 0x00 28. " CSHOLD , Chip select hold mode" "Deactivated,Activated"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK , Lock two consecutive buffer words" "0,1"
|
|
bitfld.long 0x00 26. " WDEL , Enable the delay counter at the end of the current transaction" "Disable,Enable"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL , Data word format select" "Format 0,Format 1,Format 2,Format 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR , Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA , Transfer data"
|
|
group.long 0xA4++0x03
|
|
line.long 0x00 "TXRAM, Multi-buffer RAM Transmit Data Register 41"
|
|
bitfld.long 0x00 29.--31. " BUFMODE , Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip Single Transfer,Skip Overwrite,Skip ST-Overwrite,Continuous,Suspend Single Transfer,Suspend Overwrite,Suspend ST-Overwrite"
|
|
bitfld.long 0x00 28. " CSHOLD , Chip select hold mode" "Deactivated,Activated"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK , Lock two consecutive buffer words" "0,1"
|
|
bitfld.long 0x00 26. " WDEL , Enable the delay counter at the end of the current transaction" "Disable,Enable"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL , Data word format select" "Format 0,Format 1,Format 2,Format 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR , Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA , Transfer data"
|
|
group.long 0xA8++0x03
|
|
line.long 0x00 "TXRAM, Multi-buffer RAM Transmit Data Register 42"
|
|
bitfld.long 0x00 29.--31. " BUFMODE , Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip Single Transfer,Skip Overwrite,Skip ST-Overwrite,Continuous,Suspend Single Transfer,Suspend Overwrite,Suspend ST-Overwrite"
|
|
bitfld.long 0x00 28. " CSHOLD , Chip select hold mode" "Deactivated,Activated"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK , Lock two consecutive buffer words" "0,1"
|
|
bitfld.long 0x00 26. " WDEL , Enable the delay counter at the end of the current transaction" "Disable,Enable"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL , Data word format select" "Format 0,Format 1,Format 2,Format 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR , Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA , Transfer data"
|
|
group.long 0xAC++0x03
|
|
line.long 0x00 "TXRAM, Multi-buffer RAM Transmit Data Register 43"
|
|
bitfld.long 0x00 29.--31. " BUFMODE , Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip Single Transfer,Skip Overwrite,Skip ST-Overwrite,Continuous,Suspend Single Transfer,Suspend Overwrite,Suspend ST-Overwrite"
|
|
bitfld.long 0x00 28. " CSHOLD , Chip select hold mode" "Deactivated,Activated"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK , Lock two consecutive buffer words" "0,1"
|
|
bitfld.long 0x00 26. " WDEL , Enable the delay counter at the end of the current transaction" "Disable,Enable"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL , Data word format select" "Format 0,Format 1,Format 2,Format 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR , Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA , Transfer data"
|
|
group.long 0xB0++0x03
|
|
line.long 0x00 "TXRAM, Multi-buffer RAM Transmit Data Register 44"
|
|
bitfld.long 0x00 29.--31. " BUFMODE , Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip Single Transfer,Skip Overwrite,Skip ST-Overwrite,Continuous,Suspend Single Transfer,Suspend Overwrite,Suspend ST-Overwrite"
|
|
bitfld.long 0x00 28. " CSHOLD , Chip select hold mode" "Deactivated,Activated"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK , Lock two consecutive buffer words" "0,1"
|
|
bitfld.long 0x00 26. " WDEL , Enable the delay counter at the end of the current transaction" "Disable,Enable"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL , Data word format select" "Format 0,Format 1,Format 2,Format 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR , Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA , Transfer data"
|
|
group.long 0xB4++0x03
|
|
line.long 0x00 "TXRAM, Multi-buffer RAM Transmit Data Register 45"
|
|
bitfld.long 0x00 29.--31. " BUFMODE , Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip Single Transfer,Skip Overwrite,Skip ST-Overwrite,Continuous,Suspend Single Transfer,Suspend Overwrite,Suspend ST-Overwrite"
|
|
bitfld.long 0x00 28. " CSHOLD , Chip select hold mode" "Deactivated,Activated"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK , Lock two consecutive buffer words" "0,1"
|
|
bitfld.long 0x00 26. " WDEL , Enable the delay counter at the end of the current transaction" "Disable,Enable"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL , Data word format select" "Format 0,Format 1,Format 2,Format 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR , Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA , Transfer data"
|
|
group.long 0xB8++0x03
|
|
line.long 0x00 "TXRAM, Multi-buffer RAM Transmit Data Register 46"
|
|
bitfld.long 0x00 29.--31. " BUFMODE , Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip Single Transfer,Skip Overwrite,Skip ST-Overwrite,Continuous,Suspend Single Transfer,Suspend Overwrite,Suspend ST-Overwrite"
|
|
bitfld.long 0x00 28. " CSHOLD , Chip select hold mode" "Deactivated,Activated"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK , Lock two consecutive buffer words" "0,1"
|
|
bitfld.long 0x00 26. " WDEL , Enable the delay counter at the end of the current transaction" "Disable,Enable"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL , Data word format select" "Format 0,Format 1,Format 2,Format 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR , Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA , Transfer data"
|
|
group.long 0xBC++0x03
|
|
line.long 0x00 "TXRAM, Multi-buffer RAM Transmit Data Register 47"
|
|
bitfld.long 0x00 29.--31. " BUFMODE , Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip Single Transfer,Skip Overwrite,Skip ST-Overwrite,Continuous,Suspend Single Transfer,Suspend Overwrite,Suspend ST-Overwrite"
|
|
bitfld.long 0x00 28. " CSHOLD , Chip select hold mode" "Deactivated,Activated"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK , Lock two consecutive buffer words" "0,1"
|
|
bitfld.long 0x00 26. " WDEL , Enable the delay counter at the end of the current transaction" "Disable,Enable"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL , Data word format select" "Format 0,Format 1,Format 2,Format 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR , Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA , Transfer data"
|
|
group.long 0xC0++0x03
|
|
line.long 0x00 "TXRAM, Multi-buffer RAM Transmit Data Register 48"
|
|
bitfld.long 0x00 29.--31. " BUFMODE , Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip Single Transfer,Skip Overwrite,Skip ST-Overwrite,Continuous,Suspend Single Transfer,Suspend Overwrite,Suspend ST-Overwrite"
|
|
bitfld.long 0x00 28. " CSHOLD , Chip select hold mode" "Deactivated,Activated"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK , Lock two consecutive buffer words" "0,1"
|
|
bitfld.long 0x00 26. " WDEL , Enable the delay counter at the end of the current transaction" "Disable,Enable"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL , Data word format select" "Format 0,Format 1,Format 2,Format 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR , Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA , Transfer data"
|
|
group.long 0xC4++0x03
|
|
line.long 0x00 "TXRAM, Multi-buffer RAM Transmit Data Register 49"
|
|
bitfld.long 0x00 29.--31. " BUFMODE , Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip Single Transfer,Skip Overwrite,Skip ST-Overwrite,Continuous,Suspend Single Transfer,Suspend Overwrite,Suspend ST-Overwrite"
|
|
bitfld.long 0x00 28. " CSHOLD , Chip select hold mode" "Deactivated,Activated"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK , Lock two consecutive buffer words" "0,1"
|
|
bitfld.long 0x00 26. " WDEL , Enable the delay counter at the end of the current transaction" "Disable,Enable"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL , Data word format select" "Format 0,Format 1,Format 2,Format 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR , Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA , Transfer data"
|
|
group.long 0xC8++0x03
|
|
line.long 0x00 "TXRAM, Multi-buffer RAM Transmit Data Register 50"
|
|
bitfld.long 0x00 29.--31. " BUFMODE , Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip Single Transfer,Skip Overwrite,Skip ST-Overwrite,Continuous,Suspend Single Transfer,Suspend Overwrite,Suspend ST-Overwrite"
|
|
bitfld.long 0x00 28. " CSHOLD , Chip select hold mode" "Deactivated,Activated"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK , Lock two consecutive buffer words" "0,1"
|
|
bitfld.long 0x00 26. " WDEL , Enable the delay counter at the end of the current transaction" "Disable,Enable"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL , Data word format select" "Format 0,Format 1,Format 2,Format 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR , Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA , Transfer data"
|
|
group.long 0xCC++0x03
|
|
line.long 0x00 "TXRAM, Multi-buffer RAM Transmit Data Register 51"
|
|
bitfld.long 0x00 29.--31. " BUFMODE , Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip Single Transfer,Skip Overwrite,Skip ST-Overwrite,Continuous,Suspend Single Transfer,Suspend Overwrite,Suspend ST-Overwrite"
|
|
bitfld.long 0x00 28. " CSHOLD , Chip select hold mode" "Deactivated,Activated"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK , Lock two consecutive buffer words" "0,1"
|
|
bitfld.long 0x00 26. " WDEL , Enable the delay counter at the end of the current transaction" "Disable,Enable"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL , Data word format select" "Format 0,Format 1,Format 2,Format 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR , Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA , Transfer data"
|
|
group.long 0xD0++0x03
|
|
line.long 0x00 "TXRAM, Multi-buffer RAM Transmit Data Register 52"
|
|
bitfld.long 0x00 29.--31. " BUFMODE , Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip Single Transfer,Skip Overwrite,Skip ST-Overwrite,Continuous,Suspend Single Transfer,Suspend Overwrite,Suspend ST-Overwrite"
|
|
bitfld.long 0x00 28. " CSHOLD , Chip select hold mode" "Deactivated,Activated"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK , Lock two consecutive buffer words" "0,1"
|
|
bitfld.long 0x00 26. " WDEL , Enable the delay counter at the end of the current transaction" "Disable,Enable"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL , Data word format select" "Format 0,Format 1,Format 2,Format 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR , Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA , Transfer data"
|
|
group.long 0xD4++0x03
|
|
line.long 0x00 "TXRAM, Multi-buffer RAM Transmit Data Register 53"
|
|
bitfld.long 0x00 29.--31. " BUFMODE , Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip Single Transfer,Skip Overwrite,Skip ST-Overwrite,Continuous,Suspend Single Transfer,Suspend Overwrite,Suspend ST-Overwrite"
|
|
bitfld.long 0x00 28. " CSHOLD , Chip select hold mode" "Deactivated,Activated"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK , Lock two consecutive buffer words" "0,1"
|
|
bitfld.long 0x00 26. " WDEL , Enable the delay counter at the end of the current transaction" "Disable,Enable"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL , Data word format select" "Format 0,Format 1,Format 2,Format 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR , Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA , Transfer data"
|
|
group.long 0xD8++0x03
|
|
line.long 0x00 "TXRAM, Multi-buffer RAM Transmit Data Register 54"
|
|
bitfld.long 0x00 29.--31. " BUFMODE , Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip Single Transfer,Skip Overwrite,Skip ST-Overwrite,Continuous,Suspend Single Transfer,Suspend Overwrite,Suspend ST-Overwrite"
|
|
bitfld.long 0x00 28. " CSHOLD , Chip select hold mode" "Deactivated,Activated"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK , Lock two consecutive buffer words" "0,1"
|
|
bitfld.long 0x00 26. " WDEL , Enable the delay counter at the end of the current transaction" "Disable,Enable"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL , Data word format select" "Format 0,Format 1,Format 2,Format 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR , Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA , Transfer data"
|
|
group.long 0xDC++0x03
|
|
line.long 0x00 "TXRAM, Multi-buffer RAM Transmit Data Register 55"
|
|
bitfld.long 0x00 29.--31. " BUFMODE , Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip Single Transfer,Skip Overwrite,Skip ST-Overwrite,Continuous,Suspend Single Transfer,Suspend Overwrite,Suspend ST-Overwrite"
|
|
bitfld.long 0x00 28. " CSHOLD , Chip select hold mode" "Deactivated,Activated"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK , Lock two consecutive buffer words" "0,1"
|
|
bitfld.long 0x00 26. " WDEL , Enable the delay counter at the end of the current transaction" "Disable,Enable"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL , Data word format select" "Format 0,Format 1,Format 2,Format 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR , Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA , Transfer data"
|
|
group.long 0xE0++0x03
|
|
line.long 0x00 "TXRAM, Multi-buffer RAM Transmit Data Register 56"
|
|
bitfld.long 0x00 29.--31. " BUFMODE , Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip Single Transfer,Skip Overwrite,Skip ST-Overwrite,Continuous,Suspend Single Transfer,Suspend Overwrite,Suspend ST-Overwrite"
|
|
bitfld.long 0x00 28. " CSHOLD , Chip select hold mode" "Deactivated,Activated"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK , Lock two consecutive buffer words" "0,1"
|
|
bitfld.long 0x00 26. " WDEL , Enable the delay counter at the end of the current transaction" "Disable,Enable"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL , Data word format select" "Format 0,Format 1,Format 2,Format 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR , Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA , Transfer data"
|
|
group.long 0xE4++0x03
|
|
line.long 0x00 "TXRAM, Multi-buffer RAM Transmit Data Register 57"
|
|
bitfld.long 0x00 29.--31. " BUFMODE , Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip Single Transfer,Skip Overwrite,Skip ST-Overwrite,Continuous,Suspend Single Transfer,Suspend Overwrite,Suspend ST-Overwrite"
|
|
bitfld.long 0x00 28. " CSHOLD , Chip select hold mode" "Deactivated,Activated"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK , Lock two consecutive buffer words" "0,1"
|
|
bitfld.long 0x00 26. " WDEL , Enable the delay counter at the end of the current transaction" "Disable,Enable"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL , Data word format select" "Format 0,Format 1,Format 2,Format 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR , Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA , Transfer data"
|
|
group.long 0xE8++0x03
|
|
line.long 0x00 "TXRAM, Multi-buffer RAM Transmit Data Register 58"
|
|
bitfld.long 0x00 29.--31. " BUFMODE , Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip Single Transfer,Skip Overwrite,Skip ST-Overwrite,Continuous,Suspend Single Transfer,Suspend Overwrite,Suspend ST-Overwrite"
|
|
bitfld.long 0x00 28. " CSHOLD , Chip select hold mode" "Deactivated,Activated"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK , Lock two consecutive buffer words" "0,1"
|
|
bitfld.long 0x00 26. " WDEL , Enable the delay counter at the end of the current transaction" "Disable,Enable"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL , Data word format select" "Format 0,Format 1,Format 2,Format 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR , Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA , Transfer data"
|
|
group.long 0xEC++0x03
|
|
line.long 0x00 "TXRAM, Multi-buffer RAM Transmit Data Register 59"
|
|
bitfld.long 0x00 29.--31. " BUFMODE , Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip Single Transfer,Skip Overwrite,Skip ST-Overwrite,Continuous,Suspend Single Transfer,Suspend Overwrite,Suspend ST-Overwrite"
|
|
bitfld.long 0x00 28. " CSHOLD , Chip select hold mode" "Deactivated,Activated"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK , Lock two consecutive buffer words" "0,1"
|
|
bitfld.long 0x00 26. " WDEL , Enable the delay counter at the end of the current transaction" "Disable,Enable"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL , Data word format select" "Format 0,Format 1,Format 2,Format 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR , Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA , Transfer data"
|
|
group.long 0xF0++0x03
|
|
line.long 0x00 "TXRAM, Multi-buffer RAM Transmit Data Register 60"
|
|
bitfld.long 0x00 29.--31. " BUFMODE , Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip Single Transfer,Skip Overwrite,Skip ST-Overwrite,Continuous,Suspend Single Transfer,Suspend Overwrite,Suspend ST-Overwrite"
|
|
bitfld.long 0x00 28. " CSHOLD , Chip select hold mode" "Deactivated,Activated"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK , Lock two consecutive buffer words" "0,1"
|
|
bitfld.long 0x00 26. " WDEL , Enable the delay counter at the end of the current transaction" "Disable,Enable"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL , Data word format select" "Format 0,Format 1,Format 2,Format 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR , Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA , Transfer data"
|
|
group.long 0xF4++0x03
|
|
line.long 0x00 "TXRAM, Multi-buffer RAM Transmit Data Register 61"
|
|
bitfld.long 0x00 29.--31. " BUFMODE , Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip Single Transfer,Skip Overwrite,Skip ST-Overwrite,Continuous,Suspend Single Transfer,Suspend Overwrite,Suspend ST-Overwrite"
|
|
bitfld.long 0x00 28. " CSHOLD , Chip select hold mode" "Deactivated,Activated"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK , Lock two consecutive buffer words" "0,1"
|
|
bitfld.long 0x00 26. " WDEL , Enable the delay counter at the end of the current transaction" "Disable,Enable"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL , Data word format select" "Format 0,Format 1,Format 2,Format 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR , Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA , Transfer data"
|
|
group.long 0xF8++0x03
|
|
line.long 0x00 "TXRAM, Multi-buffer RAM Transmit Data Register 62"
|
|
bitfld.long 0x00 29.--31. " BUFMODE , Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip Single Transfer,Skip Overwrite,Skip ST-Overwrite,Continuous,Suspend Single Transfer,Suspend Overwrite,Suspend ST-Overwrite"
|
|
bitfld.long 0x00 28. " CSHOLD , Chip select hold mode" "Deactivated,Activated"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK , Lock two consecutive buffer words" "0,1"
|
|
bitfld.long 0x00 26. " WDEL , Enable the delay counter at the end of the current transaction" "Disable,Enable"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL , Data word format select" "Format 0,Format 1,Format 2,Format 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR , Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA , Transfer data"
|
|
group.long 0xFC++0x03
|
|
line.long 0x00 "TXRAM, Multi-buffer RAM Transmit Data Register 63"
|
|
bitfld.long 0x00 29.--31. " BUFMODE , Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip Single Transfer,Skip Overwrite,Skip ST-Overwrite,Continuous,Suspend Single Transfer,Suspend Overwrite,Suspend ST-Overwrite"
|
|
bitfld.long 0x00 28. " CSHOLD , Chip select hold mode" "Deactivated,Activated"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK , Lock two consecutive buffer words" "0,1"
|
|
bitfld.long 0x00 26. " WDEL , Enable the delay counter at the end of the current transaction" "Disable,Enable"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL , Data word format select" "Format 0,Format 1,Format 2,Format 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR , Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA , Transfer data"
|
|
group.long 0x100++0x03
|
|
line.long 0x00 "TXRAM, Multi-buffer RAM Transmit Data Register 64"
|
|
bitfld.long 0x00 29.--31. " BUFMODE , Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip Single Transfer,Skip Overwrite,Skip ST-Overwrite,Continuous,Suspend Single Transfer,Suspend Overwrite,Suspend ST-Overwrite"
|
|
bitfld.long 0x00 28. " CSHOLD , Chip select hold mode" "Deactivated,Activated"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK , Lock two consecutive buffer words" "0,1"
|
|
bitfld.long 0x00 26. " WDEL , Enable the delay counter at the end of the current transaction" "Disable,Enable"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL , Data word format select" "Format 0,Format 1,Format 2,Format 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR , Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA , Transfer data"
|
|
group.long 0x104++0x03
|
|
line.long 0x00 "TXRAM, Multi-buffer RAM Transmit Data Register 65"
|
|
bitfld.long 0x00 29.--31. " BUFMODE , Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip Single Transfer,Skip Overwrite,Skip ST-Overwrite,Continuous,Suspend Single Transfer,Suspend Overwrite,Suspend ST-Overwrite"
|
|
bitfld.long 0x00 28. " CSHOLD , Chip select hold mode" "Deactivated,Activated"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK , Lock two consecutive buffer words" "0,1"
|
|
bitfld.long 0x00 26. " WDEL , Enable the delay counter at the end of the current transaction" "Disable,Enable"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL , Data word format select" "Format 0,Format 1,Format 2,Format 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR , Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA , Transfer data"
|
|
group.long 0x108++0x03
|
|
line.long 0x00 "TXRAM, Multi-buffer RAM Transmit Data Register 66"
|
|
bitfld.long 0x00 29.--31. " BUFMODE , Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip Single Transfer,Skip Overwrite,Skip ST-Overwrite,Continuous,Suspend Single Transfer,Suspend Overwrite,Suspend ST-Overwrite"
|
|
bitfld.long 0x00 28. " CSHOLD , Chip select hold mode" "Deactivated,Activated"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK , Lock two consecutive buffer words" "0,1"
|
|
bitfld.long 0x00 26. " WDEL , Enable the delay counter at the end of the current transaction" "Disable,Enable"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL , Data word format select" "Format 0,Format 1,Format 2,Format 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR , Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA , Transfer data"
|
|
group.long 0x10C++0x03
|
|
line.long 0x00 "TXRAM, Multi-buffer RAM Transmit Data Register 67"
|
|
bitfld.long 0x00 29.--31. " BUFMODE , Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip Single Transfer,Skip Overwrite,Skip ST-Overwrite,Continuous,Suspend Single Transfer,Suspend Overwrite,Suspend ST-Overwrite"
|
|
bitfld.long 0x00 28. " CSHOLD , Chip select hold mode" "Deactivated,Activated"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK , Lock two consecutive buffer words" "0,1"
|
|
bitfld.long 0x00 26. " WDEL , Enable the delay counter at the end of the current transaction" "Disable,Enable"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL , Data word format select" "Format 0,Format 1,Format 2,Format 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR , Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA , Transfer data"
|
|
group.long 0x110++0x03
|
|
line.long 0x00 "TXRAM, Multi-buffer RAM Transmit Data Register 68"
|
|
bitfld.long 0x00 29.--31. " BUFMODE , Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip Single Transfer,Skip Overwrite,Skip ST-Overwrite,Continuous,Suspend Single Transfer,Suspend Overwrite,Suspend ST-Overwrite"
|
|
bitfld.long 0x00 28. " CSHOLD , Chip select hold mode" "Deactivated,Activated"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK , Lock two consecutive buffer words" "0,1"
|
|
bitfld.long 0x00 26. " WDEL , Enable the delay counter at the end of the current transaction" "Disable,Enable"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL , Data word format select" "Format 0,Format 1,Format 2,Format 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR , Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA , Transfer data"
|
|
group.long 0x114++0x03
|
|
line.long 0x00 "TXRAM, Multi-buffer RAM Transmit Data Register 69"
|
|
bitfld.long 0x00 29.--31. " BUFMODE , Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip Single Transfer,Skip Overwrite,Skip ST-Overwrite,Continuous,Suspend Single Transfer,Suspend Overwrite,Suspend ST-Overwrite"
|
|
bitfld.long 0x00 28. " CSHOLD , Chip select hold mode" "Deactivated,Activated"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK , Lock two consecutive buffer words" "0,1"
|
|
bitfld.long 0x00 26. " WDEL , Enable the delay counter at the end of the current transaction" "Disable,Enable"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL , Data word format select" "Format 0,Format 1,Format 2,Format 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR , Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA , Transfer data"
|
|
group.long 0x118++0x03
|
|
line.long 0x00 "TXRAM, Multi-buffer RAM Transmit Data Register 70"
|
|
bitfld.long 0x00 29.--31. " BUFMODE , Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip Single Transfer,Skip Overwrite,Skip ST-Overwrite,Continuous,Suspend Single Transfer,Suspend Overwrite,Suspend ST-Overwrite"
|
|
bitfld.long 0x00 28. " CSHOLD , Chip select hold mode" "Deactivated,Activated"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK , Lock two consecutive buffer words" "0,1"
|
|
bitfld.long 0x00 26. " WDEL , Enable the delay counter at the end of the current transaction" "Disable,Enable"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL , Data word format select" "Format 0,Format 1,Format 2,Format 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR , Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA , Transfer data"
|
|
group.long 0x11C++0x03
|
|
line.long 0x00 "TXRAM, Multi-buffer RAM Transmit Data Register 71"
|
|
bitfld.long 0x00 29.--31. " BUFMODE , Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip Single Transfer,Skip Overwrite,Skip ST-Overwrite,Continuous,Suspend Single Transfer,Suspend Overwrite,Suspend ST-Overwrite"
|
|
bitfld.long 0x00 28. " CSHOLD , Chip select hold mode" "Deactivated,Activated"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK , Lock two consecutive buffer words" "0,1"
|
|
bitfld.long 0x00 26. " WDEL , Enable the delay counter at the end of the current transaction" "Disable,Enable"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL , Data word format select" "Format 0,Format 1,Format 2,Format 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR , Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA , Transfer data"
|
|
group.long 0x120++0x03
|
|
line.long 0x00 "TXRAM, Multi-buffer RAM Transmit Data Register 72"
|
|
bitfld.long 0x00 29.--31. " BUFMODE , Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip Single Transfer,Skip Overwrite,Skip ST-Overwrite,Continuous,Suspend Single Transfer,Suspend Overwrite,Suspend ST-Overwrite"
|
|
bitfld.long 0x00 28. " CSHOLD , Chip select hold mode" "Deactivated,Activated"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK , Lock two consecutive buffer words" "0,1"
|
|
bitfld.long 0x00 26. " WDEL , Enable the delay counter at the end of the current transaction" "Disable,Enable"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL , Data word format select" "Format 0,Format 1,Format 2,Format 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR , Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA , Transfer data"
|
|
group.long 0x124++0x03
|
|
line.long 0x00 "TXRAM, Multi-buffer RAM Transmit Data Register 73"
|
|
bitfld.long 0x00 29.--31. " BUFMODE , Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip Single Transfer,Skip Overwrite,Skip ST-Overwrite,Continuous,Suspend Single Transfer,Suspend Overwrite,Suspend ST-Overwrite"
|
|
bitfld.long 0x00 28. " CSHOLD , Chip select hold mode" "Deactivated,Activated"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK , Lock two consecutive buffer words" "0,1"
|
|
bitfld.long 0x00 26. " WDEL , Enable the delay counter at the end of the current transaction" "Disable,Enable"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL , Data word format select" "Format 0,Format 1,Format 2,Format 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR , Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA , Transfer data"
|
|
group.long 0x128++0x03
|
|
line.long 0x00 "TXRAM, Multi-buffer RAM Transmit Data Register 74"
|
|
bitfld.long 0x00 29.--31. " BUFMODE , Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip Single Transfer,Skip Overwrite,Skip ST-Overwrite,Continuous,Suspend Single Transfer,Suspend Overwrite,Suspend ST-Overwrite"
|
|
bitfld.long 0x00 28. " CSHOLD , Chip select hold mode" "Deactivated,Activated"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK , Lock two consecutive buffer words" "0,1"
|
|
bitfld.long 0x00 26. " WDEL , Enable the delay counter at the end of the current transaction" "Disable,Enable"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL , Data word format select" "Format 0,Format 1,Format 2,Format 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR , Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA , Transfer data"
|
|
group.long 0x12C++0x03
|
|
line.long 0x00 "TXRAM, Multi-buffer RAM Transmit Data Register 75"
|
|
bitfld.long 0x00 29.--31. " BUFMODE , Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip Single Transfer,Skip Overwrite,Skip ST-Overwrite,Continuous,Suspend Single Transfer,Suspend Overwrite,Suspend ST-Overwrite"
|
|
bitfld.long 0x00 28. " CSHOLD , Chip select hold mode" "Deactivated,Activated"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK , Lock two consecutive buffer words" "0,1"
|
|
bitfld.long 0x00 26. " WDEL , Enable the delay counter at the end of the current transaction" "Disable,Enable"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL , Data word format select" "Format 0,Format 1,Format 2,Format 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR , Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA , Transfer data"
|
|
group.long 0x130++0x03
|
|
line.long 0x00 "TXRAM, Multi-buffer RAM Transmit Data Register 76"
|
|
bitfld.long 0x00 29.--31. " BUFMODE , Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip Single Transfer,Skip Overwrite,Skip ST-Overwrite,Continuous,Suspend Single Transfer,Suspend Overwrite,Suspend ST-Overwrite"
|
|
bitfld.long 0x00 28. " CSHOLD , Chip select hold mode" "Deactivated,Activated"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK , Lock two consecutive buffer words" "0,1"
|
|
bitfld.long 0x00 26. " WDEL , Enable the delay counter at the end of the current transaction" "Disable,Enable"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL , Data word format select" "Format 0,Format 1,Format 2,Format 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR , Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA , Transfer data"
|
|
group.long 0x134++0x03
|
|
line.long 0x00 "TXRAM, Multi-buffer RAM Transmit Data Register 77"
|
|
bitfld.long 0x00 29.--31. " BUFMODE , Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip Single Transfer,Skip Overwrite,Skip ST-Overwrite,Continuous,Suspend Single Transfer,Suspend Overwrite,Suspend ST-Overwrite"
|
|
bitfld.long 0x00 28. " CSHOLD , Chip select hold mode" "Deactivated,Activated"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK , Lock two consecutive buffer words" "0,1"
|
|
bitfld.long 0x00 26. " WDEL , Enable the delay counter at the end of the current transaction" "Disable,Enable"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL , Data word format select" "Format 0,Format 1,Format 2,Format 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR , Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA , Transfer data"
|
|
group.long 0x138++0x03
|
|
line.long 0x00 "TXRAM, Multi-buffer RAM Transmit Data Register 78"
|
|
bitfld.long 0x00 29.--31. " BUFMODE , Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip Single Transfer,Skip Overwrite,Skip ST-Overwrite,Continuous,Suspend Single Transfer,Suspend Overwrite,Suspend ST-Overwrite"
|
|
bitfld.long 0x00 28. " CSHOLD , Chip select hold mode" "Deactivated,Activated"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK , Lock two consecutive buffer words" "0,1"
|
|
bitfld.long 0x00 26. " WDEL , Enable the delay counter at the end of the current transaction" "Disable,Enable"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL , Data word format select" "Format 0,Format 1,Format 2,Format 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR , Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA , Transfer data"
|
|
group.long 0x13C++0x03
|
|
line.long 0x00 "TXRAM, Multi-buffer RAM Transmit Data Register 79"
|
|
bitfld.long 0x00 29.--31. " BUFMODE , Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip Single Transfer,Skip Overwrite,Skip ST-Overwrite,Continuous,Suspend Single Transfer,Suspend Overwrite,Suspend ST-Overwrite"
|
|
bitfld.long 0x00 28. " CSHOLD , Chip select hold mode" "Deactivated,Activated"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK , Lock two consecutive buffer words" "0,1"
|
|
bitfld.long 0x00 26. " WDEL , Enable the delay counter at the end of the current transaction" "Disable,Enable"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL , Data word format select" "Format 0,Format 1,Format 2,Format 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR , Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA , Transfer data"
|
|
rgroup.long (0x0+0x200)++0x03
|
|
line.long 0x00 "RXRAM, Multi-buffer RAM Receive Buffer Register 0"
|
|
bitfld.long 0x00 31. " RXEMPTY , Receive data buffer empty" "Not empty,Empty"
|
|
bitfld.long 0x00 30. " RXOVR , Receive data buffer overrun" "No overrun,Overrun"
|
|
newline
|
|
bitfld.long 0x00 29. " TXFULL , Transmit data buffer full" "Not full,Full"
|
|
bitfld.long 0x00 28. " BITERR , Bit error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 27. " DESYNC , Desynchronization of slave device" "No,Yes"
|
|
bitfld.long 0x00 26. " PARITYERR , Parity error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 25. " TIMEOUT , Time-out because of non-activation of ENA pin" "No timeout,Timeout"
|
|
bitfld.long 0x00 24. " DLENERR , Data length error flag" "No,Yes"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " LCSNR , Last chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " RXDATA , SPI receive data"
|
|
rgroup.long (0x4+0x200)++0x03
|
|
line.long 0x00 "RXRAM, Multi-buffer RAM Receive Buffer Register 1"
|
|
bitfld.long 0x00 31. " RXEMPTY , Receive data buffer empty" "Not empty,Empty"
|
|
bitfld.long 0x00 30. " RXOVR , Receive data buffer overrun" "No overrun,Overrun"
|
|
newline
|
|
bitfld.long 0x00 29. " TXFULL , Transmit data buffer full" "Not full,Full"
|
|
bitfld.long 0x00 28. " BITERR , Bit error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 27. " DESYNC , Desynchronization of slave device" "No,Yes"
|
|
bitfld.long 0x00 26. " PARITYERR , Parity error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 25. " TIMEOUT , Time-out because of non-activation of ENA pin" "No timeout,Timeout"
|
|
bitfld.long 0x00 24. " DLENERR , Data length error flag" "No,Yes"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " LCSNR , Last chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " RXDATA , SPI receive data"
|
|
rgroup.long (0x8+0x200)++0x03
|
|
line.long 0x00 "RXRAM, Multi-buffer RAM Receive Buffer Register 2"
|
|
bitfld.long 0x00 31. " RXEMPTY , Receive data buffer empty" "Not empty,Empty"
|
|
bitfld.long 0x00 30. " RXOVR , Receive data buffer overrun" "No overrun,Overrun"
|
|
newline
|
|
bitfld.long 0x00 29. " TXFULL , Transmit data buffer full" "Not full,Full"
|
|
bitfld.long 0x00 28. " BITERR , Bit error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 27. " DESYNC , Desynchronization of slave device" "No,Yes"
|
|
bitfld.long 0x00 26. " PARITYERR , Parity error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 25. " TIMEOUT , Time-out because of non-activation of ENA pin" "No timeout,Timeout"
|
|
bitfld.long 0x00 24. " DLENERR , Data length error flag" "No,Yes"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " LCSNR , Last chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " RXDATA , SPI receive data"
|
|
rgroup.long (0xC+0x200)++0x03
|
|
line.long 0x00 "RXRAM, Multi-buffer RAM Receive Buffer Register 3"
|
|
bitfld.long 0x00 31. " RXEMPTY , Receive data buffer empty" "Not empty,Empty"
|
|
bitfld.long 0x00 30. " RXOVR , Receive data buffer overrun" "No overrun,Overrun"
|
|
newline
|
|
bitfld.long 0x00 29. " TXFULL , Transmit data buffer full" "Not full,Full"
|
|
bitfld.long 0x00 28. " BITERR , Bit error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 27. " DESYNC , Desynchronization of slave device" "No,Yes"
|
|
bitfld.long 0x00 26. " PARITYERR , Parity error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 25. " TIMEOUT , Time-out because of non-activation of ENA pin" "No timeout,Timeout"
|
|
bitfld.long 0x00 24. " DLENERR , Data length error flag" "No,Yes"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " LCSNR , Last chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " RXDATA , SPI receive data"
|
|
rgroup.long (0x10+0x200)++0x03
|
|
line.long 0x00 "RXRAM, Multi-buffer RAM Receive Buffer Register 4"
|
|
bitfld.long 0x00 31. " RXEMPTY , Receive data buffer empty" "Not empty,Empty"
|
|
bitfld.long 0x00 30. " RXOVR , Receive data buffer overrun" "No overrun,Overrun"
|
|
newline
|
|
bitfld.long 0x00 29. " TXFULL , Transmit data buffer full" "Not full,Full"
|
|
bitfld.long 0x00 28. " BITERR , Bit error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 27. " DESYNC , Desynchronization of slave device" "No,Yes"
|
|
bitfld.long 0x00 26. " PARITYERR , Parity error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 25. " TIMEOUT , Time-out because of non-activation of ENA pin" "No timeout,Timeout"
|
|
bitfld.long 0x00 24. " DLENERR , Data length error flag" "No,Yes"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " LCSNR , Last chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " RXDATA , SPI receive data"
|
|
rgroup.long (0x14+0x200)++0x03
|
|
line.long 0x00 "RXRAM, Multi-buffer RAM Receive Buffer Register 5"
|
|
bitfld.long 0x00 31. " RXEMPTY , Receive data buffer empty" "Not empty,Empty"
|
|
bitfld.long 0x00 30. " RXOVR , Receive data buffer overrun" "No overrun,Overrun"
|
|
newline
|
|
bitfld.long 0x00 29. " TXFULL , Transmit data buffer full" "Not full,Full"
|
|
bitfld.long 0x00 28. " BITERR , Bit error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 27. " DESYNC , Desynchronization of slave device" "No,Yes"
|
|
bitfld.long 0x00 26. " PARITYERR , Parity error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 25. " TIMEOUT , Time-out because of non-activation of ENA pin" "No timeout,Timeout"
|
|
bitfld.long 0x00 24. " DLENERR , Data length error flag" "No,Yes"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " LCSNR , Last chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " RXDATA , SPI receive data"
|
|
rgroup.long (0x18+0x200)++0x03
|
|
line.long 0x00 "RXRAM, Multi-buffer RAM Receive Buffer Register 6"
|
|
bitfld.long 0x00 31. " RXEMPTY , Receive data buffer empty" "Not empty,Empty"
|
|
bitfld.long 0x00 30. " RXOVR , Receive data buffer overrun" "No overrun,Overrun"
|
|
newline
|
|
bitfld.long 0x00 29. " TXFULL , Transmit data buffer full" "Not full,Full"
|
|
bitfld.long 0x00 28. " BITERR , Bit error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 27. " DESYNC , Desynchronization of slave device" "No,Yes"
|
|
bitfld.long 0x00 26. " PARITYERR , Parity error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 25. " TIMEOUT , Time-out because of non-activation of ENA pin" "No timeout,Timeout"
|
|
bitfld.long 0x00 24. " DLENERR , Data length error flag" "No,Yes"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " LCSNR , Last chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " RXDATA , SPI receive data"
|
|
rgroup.long (0x1C+0x200)++0x03
|
|
line.long 0x00 "RXRAM, Multi-buffer RAM Receive Buffer Register 7"
|
|
bitfld.long 0x00 31. " RXEMPTY , Receive data buffer empty" "Not empty,Empty"
|
|
bitfld.long 0x00 30. " RXOVR , Receive data buffer overrun" "No overrun,Overrun"
|
|
newline
|
|
bitfld.long 0x00 29. " TXFULL , Transmit data buffer full" "Not full,Full"
|
|
bitfld.long 0x00 28. " BITERR , Bit error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 27. " DESYNC , Desynchronization of slave device" "No,Yes"
|
|
bitfld.long 0x00 26. " PARITYERR , Parity error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 25. " TIMEOUT , Time-out because of non-activation of ENA pin" "No timeout,Timeout"
|
|
bitfld.long 0x00 24. " DLENERR , Data length error flag" "No,Yes"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " LCSNR , Last chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " RXDATA , SPI receive data"
|
|
rgroup.long (0x20+0x200)++0x03
|
|
line.long 0x00 "RXRAM, Multi-buffer RAM Receive Buffer Register 8"
|
|
bitfld.long 0x00 31. " RXEMPTY , Receive data buffer empty" "Not empty,Empty"
|
|
bitfld.long 0x00 30. " RXOVR , Receive data buffer overrun" "No overrun,Overrun"
|
|
newline
|
|
bitfld.long 0x00 29. " TXFULL , Transmit data buffer full" "Not full,Full"
|
|
bitfld.long 0x00 28. " BITERR , Bit error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 27. " DESYNC , Desynchronization of slave device" "No,Yes"
|
|
bitfld.long 0x00 26. " PARITYERR , Parity error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 25. " TIMEOUT , Time-out because of non-activation of ENA pin" "No timeout,Timeout"
|
|
bitfld.long 0x00 24. " DLENERR , Data length error flag" "No,Yes"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " LCSNR , Last chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " RXDATA , SPI receive data"
|
|
rgroup.long (0x24+0x200)++0x03
|
|
line.long 0x00 "RXRAM, Multi-buffer RAM Receive Buffer Register 9"
|
|
bitfld.long 0x00 31. " RXEMPTY , Receive data buffer empty" "Not empty,Empty"
|
|
bitfld.long 0x00 30. " RXOVR , Receive data buffer overrun" "No overrun,Overrun"
|
|
newline
|
|
bitfld.long 0x00 29. " TXFULL , Transmit data buffer full" "Not full,Full"
|
|
bitfld.long 0x00 28. " BITERR , Bit error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 27. " DESYNC , Desynchronization of slave device" "No,Yes"
|
|
bitfld.long 0x00 26. " PARITYERR , Parity error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 25. " TIMEOUT , Time-out because of non-activation of ENA pin" "No timeout,Timeout"
|
|
bitfld.long 0x00 24. " DLENERR , Data length error flag" "No,Yes"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " LCSNR , Last chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " RXDATA , SPI receive data"
|
|
rgroup.long (0x28+0x200)++0x03
|
|
line.long 0x00 "RXRAM, Multi-buffer RAM Receive Buffer Register 10"
|
|
bitfld.long 0x00 31. " RXEMPTY , Receive data buffer empty" "Not empty,Empty"
|
|
bitfld.long 0x00 30. " RXOVR , Receive data buffer overrun" "No overrun,Overrun"
|
|
newline
|
|
bitfld.long 0x00 29. " TXFULL , Transmit data buffer full" "Not full,Full"
|
|
bitfld.long 0x00 28. " BITERR , Bit error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 27. " DESYNC , Desynchronization of slave device" "No,Yes"
|
|
bitfld.long 0x00 26. " PARITYERR , Parity error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 25. " TIMEOUT , Time-out because of non-activation of ENA pin" "No timeout,Timeout"
|
|
bitfld.long 0x00 24. " DLENERR , Data length error flag" "No,Yes"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " LCSNR , Last chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " RXDATA , SPI receive data"
|
|
rgroup.long (0x2C+0x200)++0x03
|
|
line.long 0x00 "RXRAM, Multi-buffer RAM Receive Buffer Register 11"
|
|
bitfld.long 0x00 31. " RXEMPTY , Receive data buffer empty" "Not empty,Empty"
|
|
bitfld.long 0x00 30. " RXOVR , Receive data buffer overrun" "No overrun,Overrun"
|
|
newline
|
|
bitfld.long 0x00 29. " TXFULL , Transmit data buffer full" "Not full,Full"
|
|
bitfld.long 0x00 28. " BITERR , Bit error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 27. " DESYNC , Desynchronization of slave device" "No,Yes"
|
|
bitfld.long 0x00 26. " PARITYERR , Parity error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 25. " TIMEOUT , Time-out because of non-activation of ENA pin" "No timeout,Timeout"
|
|
bitfld.long 0x00 24. " DLENERR , Data length error flag" "No,Yes"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " LCSNR , Last chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " RXDATA , SPI receive data"
|
|
rgroup.long (0x30+0x200)++0x03
|
|
line.long 0x00 "RXRAM, Multi-buffer RAM Receive Buffer Register 12"
|
|
bitfld.long 0x00 31. " RXEMPTY , Receive data buffer empty" "Not empty,Empty"
|
|
bitfld.long 0x00 30. " RXOVR , Receive data buffer overrun" "No overrun,Overrun"
|
|
newline
|
|
bitfld.long 0x00 29. " TXFULL , Transmit data buffer full" "Not full,Full"
|
|
bitfld.long 0x00 28. " BITERR , Bit error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 27. " DESYNC , Desynchronization of slave device" "No,Yes"
|
|
bitfld.long 0x00 26. " PARITYERR , Parity error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 25. " TIMEOUT , Time-out because of non-activation of ENA pin" "No timeout,Timeout"
|
|
bitfld.long 0x00 24. " DLENERR , Data length error flag" "No,Yes"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " LCSNR , Last chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " RXDATA , SPI receive data"
|
|
rgroup.long (0x34+0x200)++0x03
|
|
line.long 0x00 "RXRAM, Multi-buffer RAM Receive Buffer Register 13"
|
|
bitfld.long 0x00 31. " RXEMPTY , Receive data buffer empty" "Not empty,Empty"
|
|
bitfld.long 0x00 30. " RXOVR , Receive data buffer overrun" "No overrun,Overrun"
|
|
newline
|
|
bitfld.long 0x00 29. " TXFULL , Transmit data buffer full" "Not full,Full"
|
|
bitfld.long 0x00 28. " BITERR , Bit error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 27. " DESYNC , Desynchronization of slave device" "No,Yes"
|
|
bitfld.long 0x00 26. " PARITYERR , Parity error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 25. " TIMEOUT , Time-out because of non-activation of ENA pin" "No timeout,Timeout"
|
|
bitfld.long 0x00 24. " DLENERR , Data length error flag" "No,Yes"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " LCSNR , Last chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " RXDATA , SPI receive data"
|
|
rgroup.long (0x38+0x200)++0x03
|
|
line.long 0x00 "RXRAM, Multi-buffer RAM Receive Buffer Register 14"
|
|
bitfld.long 0x00 31. " RXEMPTY , Receive data buffer empty" "Not empty,Empty"
|
|
bitfld.long 0x00 30. " RXOVR , Receive data buffer overrun" "No overrun,Overrun"
|
|
newline
|
|
bitfld.long 0x00 29. " TXFULL , Transmit data buffer full" "Not full,Full"
|
|
bitfld.long 0x00 28. " BITERR , Bit error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 27. " DESYNC , Desynchronization of slave device" "No,Yes"
|
|
bitfld.long 0x00 26. " PARITYERR , Parity error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 25. " TIMEOUT , Time-out because of non-activation of ENA pin" "No timeout,Timeout"
|
|
bitfld.long 0x00 24. " DLENERR , Data length error flag" "No,Yes"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " LCSNR , Last chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " RXDATA , SPI receive data"
|
|
rgroup.long (0x3C+0x200)++0x03
|
|
line.long 0x00 "RXRAM, Multi-buffer RAM Receive Buffer Register 15"
|
|
bitfld.long 0x00 31. " RXEMPTY , Receive data buffer empty" "Not empty,Empty"
|
|
bitfld.long 0x00 30. " RXOVR , Receive data buffer overrun" "No overrun,Overrun"
|
|
newline
|
|
bitfld.long 0x00 29. " TXFULL , Transmit data buffer full" "Not full,Full"
|
|
bitfld.long 0x00 28. " BITERR , Bit error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 27. " DESYNC , Desynchronization of slave device" "No,Yes"
|
|
bitfld.long 0x00 26. " PARITYERR , Parity error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 25. " TIMEOUT , Time-out because of non-activation of ENA pin" "No timeout,Timeout"
|
|
bitfld.long 0x00 24. " DLENERR , Data length error flag" "No,Yes"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " LCSNR , Last chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " RXDATA , SPI receive data"
|
|
rgroup.long (0x40+0x200)++0x03
|
|
line.long 0x00 "RXRAM, Multi-buffer RAM Receive Buffer Register 16"
|
|
bitfld.long 0x00 31. " RXEMPTY , Receive data buffer empty" "Not empty,Empty"
|
|
bitfld.long 0x00 30. " RXOVR , Receive data buffer overrun" "No overrun,Overrun"
|
|
newline
|
|
bitfld.long 0x00 29. " TXFULL , Transmit data buffer full" "Not full,Full"
|
|
bitfld.long 0x00 28. " BITERR , Bit error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 27. " DESYNC , Desynchronization of slave device" "No,Yes"
|
|
bitfld.long 0x00 26. " PARITYERR , Parity error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 25. " TIMEOUT , Time-out because of non-activation of ENA pin" "No timeout,Timeout"
|
|
bitfld.long 0x00 24. " DLENERR , Data length error flag" "No,Yes"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " LCSNR , Last chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " RXDATA , SPI receive data"
|
|
rgroup.long (0x44+0x200)++0x03
|
|
line.long 0x00 "RXRAM, Multi-buffer RAM Receive Buffer Register 17"
|
|
bitfld.long 0x00 31. " RXEMPTY , Receive data buffer empty" "Not empty,Empty"
|
|
bitfld.long 0x00 30. " RXOVR , Receive data buffer overrun" "No overrun,Overrun"
|
|
newline
|
|
bitfld.long 0x00 29. " TXFULL , Transmit data buffer full" "Not full,Full"
|
|
bitfld.long 0x00 28. " BITERR , Bit error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 27. " DESYNC , Desynchronization of slave device" "No,Yes"
|
|
bitfld.long 0x00 26. " PARITYERR , Parity error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 25. " TIMEOUT , Time-out because of non-activation of ENA pin" "No timeout,Timeout"
|
|
bitfld.long 0x00 24. " DLENERR , Data length error flag" "No,Yes"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " LCSNR , Last chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " RXDATA , SPI receive data"
|
|
rgroup.long (0x48+0x200)++0x03
|
|
line.long 0x00 "RXRAM, Multi-buffer RAM Receive Buffer Register 18"
|
|
bitfld.long 0x00 31. " RXEMPTY , Receive data buffer empty" "Not empty,Empty"
|
|
bitfld.long 0x00 30. " RXOVR , Receive data buffer overrun" "No overrun,Overrun"
|
|
newline
|
|
bitfld.long 0x00 29. " TXFULL , Transmit data buffer full" "Not full,Full"
|
|
bitfld.long 0x00 28. " BITERR , Bit error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 27. " DESYNC , Desynchronization of slave device" "No,Yes"
|
|
bitfld.long 0x00 26. " PARITYERR , Parity error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 25. " TIMEOUT , Time-out because of non-activation of ENA pin" "No timeout,Timeout"
|
|
bitfld.long 0x00 24. " DLENERR , Data length error flag" "No,Yes"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " LCSNR , Last chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " RXDATA , SPI receive data"
|
|
rgroup.long (0x4C+0x200)++0x03
|
|
line.long 0x00 "RXRAM, Multi-buffer RAM Receive Buffer Register 19"
|
|
bitfld.long 0x00 31. " RXEMPTY , Receive data buffer empty" "Not empty,Empty"
|
|
bitfld.long 0x00 30. " RXOVR , Receive data buffer overrun" "No overrun,Overrun"
|
|
newline
|
|
bitfld.long 0x00 29. " TXFULL , Transmit data buffer full" "Not full,Full"
|
|
bitfld.long 0x00 28. " BITERR , Bit error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 27. " DESYNC , Desynchronization of slave device" "No,Yes"
|
|
bitfld.long 0x00 26. " PARITYERR , Parity error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 25. " TIMEOUT , Time-out because of non-activation of ENA pin" "No timeout,Timeout"
|
|
bitfld.long 0x00 24. " DLENERR , Data length error flag" "No,Yes"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " LCSNR , Last chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " RXDATA , SPI receive data"
|
|
rgroup.long (0x50+0x200)++0x03
|
|
line.long 0x00 "RXRAM, Multi-buffer RAM Receive Buffer Register 20"
|
|
bitfld.long 0x00 31. " RXEMPTY , Receive data buffer empty" "Not empty,Empty"
|
|
bitfld.long 0x00 30. " RXOVR , Receive data buffer overrun" "No overrun,Overrun"
|
|
newline
|
|
bitfld.long 0x00 29. " TXFULL , Transmit data buffer full" "Not full,Full"
|
|
bitfld.long 0x00 28. " BITERR , Bit error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 27. " DESYNC , Desynchronization of slave device" "No,Yes"
|
|
bitfld.long 0x00 26. " PARITYERR , Parity error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 25. " TIMEOUT , Time-out because of non-activation of ENA pin" "No timeout,Timeout"
|
|
bitfld.long 0x00 24. " DLENERR , Data length error flag" "No,Yes"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " LCSNR , Last chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " RXDATA , SPI receive data"
|
|
rgroup.long (0x54+0x200)++0x03
|
|
line.long 0x00 "RXRAM, Multi-buffer RAM Receive Buffer Register 21"
|
|
bitfld.long 0x00 31. " RXEMPTY , Receive data buffer empty" "Not empty,Empty"
|
|
bitfld.long 0x00 30. " RXOVR , Receive data buffer overrun" "No overrun,Overrun"
|
|
newline
|
|
bitfld.long 0x00 29. " TXFULL , Transmit data buffer full" "Not full,Full"
|
|
bitfld.long 0x00 28. " BITERR , Bit error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 27. " DESYNC , Desynchronization of slave device" "No,Yes"
|
|
bitfld.long 0x00 26. " PARITYERR , Parity error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 25. " TIMEOUT , Time-out because of non-activation of ENA pin" "No timeout,Timeout"
|
|
bitfld.long 0x00 24. " DLENERR , Data length error flag" "No,Yes"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " LCSNR , Last chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " RXDATA , SPI receive data"
|
|
rgroup.long (0x58+0x200)++0x03
|
|
line.long 0x00 "RXRAM, Multi-buffer RAM Receive Buffer Register 22"
|
|
bitfld.long 0x00 31. " RXEMPTY , Receive data buffer empty" "Not empty,Empty"
|
|
bitfld.long 0x00 30. " RXOVR , Receive data buffer overrun" "No overrun,Overrun"
|
|
newline
|
|
bitfld.long 0x00 29. " TXFULL , Transmit data buffer full" "Not full,Full"
|
|
bitfld.long 0x00 28. " BITERR , Bit error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 27. " DESYNC , Desynchronization of slave device" "No,Yes"
|
|
bitfld.long 0x00 26. " PARITYERR , Parity error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 25. " TIMEOUT , Time-out because of non-activation of ENA pin" "No timeout,Timeout"
|
|
bitfld.long 0x00 24. " DLENERR , Data length error flag" "No,Yes"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " LCSNR , Last chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " RXDATA , SPI receive data"
|
|
rgroup.long (0x5C+0x200)++0x03
|
|
line.long 0x00 "RXRAM, Multi-buffer RAM Receive Buffer Register 23"
|
|
bitfld.long 0x00 31. " RXEMPTY , Receive data buffer empty" "Not empty,Empty"
|
|
bitfld.long 0x00 30. " RXOVR , Receive data buffer overrun" "No overrun,Overrun"
|
|
newline
|
|
bitfld.long 0x00 29. " TXFULL , Transmit data buffer full" "Not full,Full"
|
|
bitfld.long 0x00 28. " BITERR , Bit error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 27. " DESYNC , Desynchronization of slave device" "No,Yes"
|
|
bitfld.long 0x00 26. " PARITYERR , Parity error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 25. " TIMEOUT , Time-out because of non-activation of ENA pin" "No timeout,Timeout"
|
|
bitfld.long 0x00 24. " DLENERR , Data length error flag" "No,Yes"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " LCSNR , Last chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " RXDATA , SPI receive data"
|
|
rgroup.long (0x60+0x200)++0x03
|
|
line.long 0x00 "RXRAM, Multi-buffer RAM Receive Buffer Register 24"
|
|
bitfld.long 0x00 31. " RXEMPTY , Receive data buffer empty" "Not empty,Empty"
|
|
bitfld.long 0x00 30. " RXOVR , Receive data buffer overrun" "No overrun,Overrun"
|
|
newline
|
|
bitfld.long 0x00 29. " TXFULL , Transmit data buffer full" "Not full,Full"
|
|
bitfld.long 0x00 28. " BITERR , Bit error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 27. " DESYNC , Desynchronization of slave device" "No,Yes"
|
|
bitfld.long 0x00 26. " PARITYERR , Parity error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 25. " TIMEOUT , Time-out because of non-activation of ENA pin" "No timeout,Timeout"
|
|
bitfld.long 0x00 24. " DLENERR , Data length error flag" "No,Yes"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " LCSNR , Last chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " RXDATA , SPI receive data"
|
|
rgroup.long (0x64+0x200)++0x03
|
|
line.long 0x00 "RXRAM, Multi-buffer RAM Receive Buffer Register 25"
|
|
bitfld.long 0x00 31. " RXEMPTY , Receive data buffer empty" "Not empty,Empty"
|
|
bitfld.long 0x00 30. " RXOVR , Receive data buffer overrun" "No overrun,Overrun"
|
|
newline
|
|
bitfld.long 0x00 29. " TXFULL , Transmit data buffer full" "Not full,Full"
|
|
bitfld.long 0x00 28. " BITERR , Bit error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 27. " DESYNC , Desynchronization of slave device" "No,Yes"
|
|
bitfld.long 0x00 26. " PARITYERR , Parity error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 25. " TIMEOUT , Time-out because of non-activation of ENA pin" "No timeout,Timeout"
|
|
bitfld.long 0x00 24. " DLENERR , Data length error flag" "No,Yes"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " LCSNR , Last chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " RXDATA , SPI receive data"
|
|
rgroup.long (0x68+0x200)++0x03
|
|
line.long 0x00 "RXRAM, Multi-buffer RAM Receive Buffer Register 26"
|
|
bitfld.long 0x00 31. " RXEMPTY , Receive data buffer empty" "Not empty,Empty"
|
|
bitfld.long 0x00 30. " RXOVR , Receive data buffer overrun" "No overrun,Overrun"
|
|
newline
|
|
bitfld.long 0x00 29. " TXFULL , Transmit data buffer full" "Not full,Full"
|
|
bitfld.long 0x00 28. " BITERR , Bit error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 27. " DESYNC , Desynchronization of slave device" "No,Yes"
|
|
bitfld.long 0x00 26. " PARITYERR , Parity error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 25. " TIMEOUT , Time-out because of non-activation of ENA pin" "No timeout,Timeout"
|
|
bitfld.long 0x00 24. " DLENERR , Data length error flag" "No,Yes"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " LCSNR , Last chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " RXDATA , SPI receive data"
|
|
rgroup.long (0x6C+0x200)++0x03
|
|
line.long 0x00 "RXRAM, Multi-buffer RAM Receive Buffer Register 27"
|
|
bitfld.long 0x00 31. " RXEMPTY , Receive data buffer empty" "Not empty,Empty"
|
|
bitfld.long 0x00 30. " RXOVR , Receive data buffer overrun" "No overrun,Overrun"
|
|
newline
|
|
bitfld.long 0x00 29. " TXFULL , Transmit data buffer full" "Not full,Full"
|
|
bitfld.long 0x00 28. " BITERR , Bit error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 27. " DESYNC , Desynchronization of slave device" "No,Yes"
|
|
bitfld.long 0x00 26. " PARITYERR , Parity error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 25. " TIMEOUT , Time-out because of non-activation of ENA pin" "No timeout,Timeout"
|
|
bitfld.long 0x00 24. " DLENERR , Data length error flag" "No,Yes"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " LCSNR , Last chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " RXDATA , SPI receive data"
|
|
rgroup.long (0x70+0x200)++0x03
|
|
line.long 0x00 "RXRAM, Multi-buffer RAM Receive Buffer Register 28"
|
|
bitfld.long 0x00 31. " RXEMPTY , Receive data buffer empty" "Not empty,Empty"
|
|
bitfld.long 0x00 30. " RXOVR , Receive data buffer overrun" "No overrun,Overrun"
|
|
newline
|
|
bitfld.long 0x00 29. " TXFULL , Transmit data buffer full" "Not full,Full"
|
|
bitfld.long 0x00 28. " BITERR , Bit error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 27. " DESYNC , Desynchronization of slave device" "No,Yes"
|
|
bitfld.long 0x00 26. " PARITYERR , Parity error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 25. " TIMEOUT , Time-out because of non-activation of ENA pin" "No timeout,Timeout"
|
|
bitfld.long 0x00 24. " DLENERR , Data length error flag" "No,Yes"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " LCSNR , Last chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " RXDATA , SPI receive data"
|
|
rgroup.long (0x74+0x200)++0x03
|
|
line.long 0x00 "RXRAM, Multi-buffer RAM Receive Buffer Register 29"
|
|
bitfld.long 0x00 31. " RXEMPTY , Receive data buffer empty" "Not empty,Empty"
|
|
bitfld.long 0x00 30. " RXOVR , Receive data buffer overrun" "No overrun,Overrun"
|
|
newline
|
|
bitfld.long 0x00 29. " TXFULL , Transmit data buffer full" "Not full,Full"
|
|
bitfld.long 0x00 28. " BITERR , Bit error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 27. " DESYNC , Desynchronization of slave device" "No,Yes"
|
|
bitfld.long 0x00 26. " PARITYERR , Parity error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 25. " TIMEOUT , Time-out because of non-activation of ENA pin" "No timeout,Timeout"
|
|
bitfld.long 0x00 24. " DLENERR , Data length error flag" "No,Yes"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " LCSNR , Last chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " RXDATA , SPI receive data"
|
|
rgroup.long (0x78+0x200)++0x03
|
|
line.long 0x00 "RXRAM, Multi-buffer RAM Receive Buffer Register 30"
|
|
bitfld.long 0x00 31. " RXEMPTY , Receive data buffer empty" "Not empty,Empty"
|
|
bitfld.long 0x00 30. " RXOVR , Receive data buffer overrun" "No overrun,Overrun"
|
|
newline
|
|
bitfld.long 0x00 29. " TXFULL , Transmit data buffer full" "Not full,Full"
|
|
bitfld.long 0x00 28. " BITERR , Bit error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 27. " DESYNC , Desynchronization of slave device" "No,Yes"
|
|
bitfld.long 0x00 26. " PARITYERR , Parity error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 25. " TIMEOUT , Time-out because of non-activation of ENA pin" "No timeout,Timeout"
|
|
bitfld.long 0x00 24. " DLENERR , Data length error flag" "No,Yes"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " LCSNR , Last chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " RXDATA , SPI receive data"
|
|
rgroup.long (0x7C+0x200)++0x03
|
|
line.long 0x00 "RXRAM, Multi-buffer RAM Receive Buffer Register 31"
|
|
bitfld.long 0x00 31. " RXEMPTY , Receive data buffer empty" "Not empty,Empty"
|
|
bitfld.long 0x00 30. " RXOVR , Receive data buffer overrun" "No overrun,Overrun"
|
|
newline
|
|
bitfld.long 0x00 29. " TXFULL , Transmit data buffer full" "Not full,Full"
|
|
bitfld.long 0x00 28. " BITERR , Bit error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 27. " DESYNC , Desynchronization of slave device" "No,Yes"
|
|
bitfld.long 0x00 26. " PARITYERR , Parity error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 25. " TIMEOUT , Time-out because of non-activation of ENA pin" "No timeout,Timeout"
|
|
bitfld.long 0x00 24. " DLENERR , Data length error flag" "No,Yes"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " LCSNR , Last chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " RXDATA , SPI receive data"
|
|
rgroup.long (0x80+0x200)++0x03
|
|
line.long 0x00 "RXRAM, Multi-buffer RAM Receive Buffer Register 32"
|
|
bitfld.long 0x00 31. " RXEMPTY , Receive data buffer empty" "Not empty,Empty"
|
|
bitfld.long 0x00 30. " RXOVR , Receive data buffer overrun" "No overrun,Overrun"
|
|
newline
|
|
bitfld.long 0x00 29. " TXFULL , Transmit data buffer full" "Not full,Full"
|
|
bitfld.long 0x00 28. " BITERR , Bit error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 27. " DESYNC , Desynchronization of slave device" "No,Yes"
|
|
bitfld.long 0x00 26. " PARITYERR , Parity error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 25. " TIMEOUT , Time-out because of non-activation of ENA pin" "No timeout,Timeout"
|
|
bitfld.long 0x00 24. " DLENERR , Data length error flag" "No,Yes"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " LCSNR , Last chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " RXDATA , SPI receive data"
|
|
rgroup.long (0x84+0x200)++0x03
|
|
line.long 0x00 "RXRAM, Multi-buffer RAM Receive Buffer Register 33"
|
|
bitfld.long 0x00 31. " RXEMPTY , Receive data buffer empty" "Not empty,Empty"
|
|
bitfld.long 0x00 30. " RXOVR , Receive data buffer overrun" "No overrun,Overrun"
|
|
newline
|
|
bitfld.long 0x00 29. " TXFULL , Transmit data buffer full" "Not full,Full"
|
|
bitfld.long 0x00 28. " BITERR , Bit error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 27. " DESYNC , Desynchronization of slave device" "No,Yes"
|
|
bitfld.long 0x00 26. " PARITYERR , Parity error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 25. " TIMEOUT , Time-out because of non-activation of ENA pin" "No timeout,Timeout"
|
|
bitfld.long 0x00 24. " DLENERR , Data length error flag" "No,Yes"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " LCSNR , Last chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " RXDATA , SPI receive data"
|
|
rgroup.long (0x88+0x200)++0x03
|
|
line.long 0x00 "RXRAM, Multi-buffer RAM Receive Buffer Register 34"
|
|
bitfld.long 0x00 31. " RXEMPTY , Receive data buffer empty" "Not empty,Empty"
|
|
bitfld.long 0x00 30. " RXOVR , Receive data buffer overrun" "No overrun,Overrun"
|
|
newline
|
|
bitfld.long 0x00 29. " TXFULL , Transmit data buffer full" "Not full,Full"
|
|
bitfld.long 0x00 28. " BITERR , Bit error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 27. " DESYNC , Desynchronization of slave device" "No,Yes"
|
|
bitfld.long 0x00 26. " PARITYERR , Parity error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 25. " TIMEOUT , Time-out because of non-activation of ENA pin" "No timeout,Timeout"
|
|
bitfld.long 0x00 24. " DLENERR , Data length error flag" "No,Yes"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " LCSNR , Last chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " RXDATA , SPI receive data"
|
|
rgroup.long (0x8C+0x200)++0x03
|
|
line.long 0x00 "RXRAM, Multi-buffer RAM Receive Buffer Register 35"
|
|
bitfld.long 0x00 31. " RXEMPTY , Receive data buffer empty" "Not empty,Empty"
|
|
bitfld.long 0x00 30. " RXOVR , Receive data buffer overrun" "No overrun,Overrun"
|
|
newline
|
|
bitfld.long 0x00 29. " TXFULL , Transmit data buffer full" "Not full,Full"
|
|
bitfld.long 0x00 28. " BITERR , Bit error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 27. " DESYNC , Desynchronization of slave device" "No,Yes"
|
|
bitfld.long 0x00 26. " PARITYERR , Parity error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 25. " TIMEOUT , Time-out because of non-activation of ENA pin" "No timeout,Timeout"
|
|
bitfld.long 0x00 24. " DLENERR , Data length error flag" "No,Yes"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " LCSNR , Last chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " RXDATA , SPI receive data"
|
|
rgroup.long (0x90+0x200)++0x03
|
|
line.long 0x00 "RXRAM, Multi-buffer RAM Receive Buffer Register 36"
|
|
bitfld.long 0x00 31. " RXEMPTY , Receive data buffer empty" "Not empty,Empty"
|
|
bitfld.long 0x00 30. " RXOVR , Receive data buffer overrun" "No overrun,Overrun"
|
|
newline
|
|
bitfld.long 0x00 29. " TXFULL , Transmit data buffer full" "Not full,Full"
|
|
bitfld.long 0x00 28. " BITERR , Bit error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 27. " DESYNC , Desynchronization of slave device" "No,Yes"
|
|
bitfld.long 0x00 26. " PARITYERR , Parity error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 25. " TIMEOUT , Time-out because of non-activation of ENA pin" "No timeout,Timeout"
|
|
bitfld.long 0x00 24. " DLENERR , Data length error flag" "No,Yes"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " LCSNR , Last chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " RXDATA , SPI receive data"
|
|
rgroup.long (0x94+0x200)++0x03
|
|
line.long 0x00 "RXRAM, Multi-buffer RAM Receive Buffer Register 37"
|
|
bitfld.long 0x00 31. " RXEMPTY , Receive data buffer empty" "Not empty,Empty"
|
|
bitfld.long 0x00 30. " RXOVR , Receive data buffer overrun" "No overrun,Overrun"
|
|
newline
|
|
bitfld.long 0x00 29. " TXFULL , Transmit data buffer full" "Not full,Full"
|
|
bitfld.long 0x00 28. " BITERR , Bit error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 27. " DESYNC , Desynchronization of slave device" "No,Yes"
|
|
bitfld.long 0x00 26. " PARITYERR , Parity error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 25. " TIMEOUT , Time-out because of non-activation of ENA pin" "No timeout,Timeout"
|
|
bitfld.long 0x00 24. " DLENERR , Data length error flag" "No,Yes"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " LCSNR , Last chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " RXDATA , SPI receive data"
|
|
rgroup.long (0x98+0x200)++0x03
|
|
line.long 0x00 "RXRAM, Multi-buffer RAM Receive Buffer Register 38"
|
|
bitfld.long 0x00 31. " RXEMPTY , Receive data buffer empty" "Not empty,Empty"
|
|
bitfld.long 0x00 30. " RXOVR , Receive data buffer overrun" "No overrun,Overrun"
|
|
newline
|
|
bitfld.long 0x00 29. " TXFULL , Transmit data buffer full" "Not full,Full"
|
|
bitfld.long 0x00 28. " BITERR , Bit error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 27. " DESYNC , Desynchronization of slave device" "No,Yes"
|
|
bitfld.long 0x00 26. " PARITYERR , Parity error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 25. " TIMEOUT , Time-out because of non-activation of ENA pin" "No timeout,Timeout"
|
|
bitfld.long 0x00 24. " DLENERR , Data length error flag" "No,Yes"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " LCSNR , Last chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " RXDATA , SPI receive data"
|
|
rgroup.long (0x9C+0x200)++0x03
|
|
line.long 0x00 "RXRAM, Multi-buffer RAM Receive Buffer Register 39"
|
|
bitfld.long 0x00 31. " RXEMPTY , Receive data buffer empty" "Not empty,Empty"
|
|
bitfld.long 0x00 30. " RXOVR , Receive data buffer overrun" "No overrun,Overrun"
|
|
newline
|
|
bitfld.long 0x00 29. " TXFULL , Transmit data buffer full" "Not full,Full"
|
|
bitfld.long 0x00 28. " BITERR , Bit error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 27. " DESYNC , Desynchronization of slave device" "No,Yes"
|
|
bitfld.long 0x00 26. " PARITYERR , Parity error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 25. " TIMEOUT , Time-out because of non-activation of ENA pin" "No timeout,Timeout"
|
|
bitfld.long 0x00 24. " DLENERR , Data length error flag" "No,Yes"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " LCSNR , Last chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " RXDATA , SPI receive data"
|
|
rgroup.long (0xA0+0x200)++0x03
|
|
line.long 0x00 "RXRAM, Multi-buffer RAM Receive Buffer Register 40"
|
|
bitfld.long 0x00 31. " RXEMPTY , Receive data buffer empty" "Not empty,Empty"
|
|
bitfld.long 0x00 30. " RXOVR , Receive data buffer overrun" "No overrun,Overrun"
|
|
newline
|
|
bitfld.long 0x00 29. " TXFULL , Transmit data buffer full" "Not full,Full"
|
|
bitfld.long 0x00 28. " BITERR , Bit error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 27. " DESYNC , Desynchronization of slave device" "No,Yes"
|
|
bitfld.long 0x00 26. " PARITYERR , Parity error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 25. " TIMEOUT , Time-out because of non-activation of ENA pin" "No timeout,Timeout"
|
|
bitfld.long 0x00 24. " DLENERR , Data length error flag" "No,Yes"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " LCSNR , Last chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " RXDATA , SPI receive data"
|
|
rgroup.long (0xA4+0x200)++0x03
|
|
line.long 0x00 "RXRAM, Multi-buffer RAM Receive Buffer Register 41"
|
|
bitfld.long 0x00 31. " RXEMPTY , Receive data buffer empty" "Not empty,Empty"
|
|
bitfld.long 0x00 30. " RXOVR , Receive data buffer overrun" "No overrun,Overrun"
|
|
newline
|
|
bitfld.long 0x00 29. " TXFULL , Transmit data buffer full" "Not full,Full"
|
|
bitfld.long 0x00 28. " BITERR , Bit error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 27. " DESYNC , Desynchronization of slave device" "No,Yes"
|
|
bitfld.long 0x00 26. " PARITYERR , Parity error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 25. " TIMEOUT , Time-out because of non-activation of ENA pin" "No timeout,Timeout"
|
|
bitfld.long 0x00 24. " DLENERR , Data length error flag" "No,Yes"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " LCSNR , Last chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " RXDATA , SPI receive data"
|
|
rgroup.long (0xA8+0x200)++0x03
|
|
line.long 0x00 "RXRAM, Multi-buffer RAM Receive Buffer Register 42"
|
|
bitfld.long 0x00 31. " RXEMPTY , Receive data buffer empty" "Not empty,Empty"
|
|
bitfld.long 0x00 30. " RXOVR , Receive data buffer overrun" "No overrun,Overrun"
|
|
newline
|
|
bitfld.long 0x00 29. " TXFULL , Transmit data buffer full" "Not full,Full"
|
|
bitfld.long 0x00 28. " BITERR , Bit error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 27. " DESYNC , Desynchronization of slave device" "No,Yes"
|
|
bitfld.long 0x00 26. " PARITYERR , Parity error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 25. " TIMEOUT , Time-out because of non-activation of ENA pin" "No timeout,Timeout"
|
|
bitfld.long 0x00 24. " DLENERR , Data length error flag" "No,Yes"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " LCSNR , Last chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " RXDATA , SPI receive data"
|
|
rgroup.long (0xAC+0x200)++0x03
|
|
line.long 0x00 "RXRAM, Multi-buffer RAM Receive Buffer Register 43"
|
|
bitfld.long 0x00 31. " RXEMPTY , Receive data buffer empty" "Not empty,Empty"
|
|
bitfld.long 0x00 30. " RXOVR , Receive data buffer overrun" "No overrun,Overrun"
|
|
newline
|
|
bitfld.long 0x00 29. " TXFULL , Transmit data buffer full" "Not full,Full"
|
|
bitfld.long 0x00 28. " BITERR , Bit error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 27. " DESYNC , Desynchronization of slave device" "No,Yes"
|
|
bitfld.long 0x00 26. " PARITYERR , Parity error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 25. " TIMEOUT , Time-out because of non-activation of ENA pin" "No timeout,Timeout"
|
|
bitfld.long 0x00 24. " DLENERR , Data length error flag" "No,Yes"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " LCSNR , Last chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " RXDATA , SPI receive data"
|
|
rgroup.long (0xB0+0x200)++0x03
|
|
line.long 0x00 "RXRAM, Multi-buffer RAM Receive Buffer Register 44"
|
|
bitfld.long 0x00 31. " RXEMPTY , Receive data buffer empty" "Not empty,Empty"
|
|
bitfld.long 0x00 30. " RXOVR , Receive data buffer overrun" "No overrun,Overrun"
|
|
newline
|
|
bitfld.long 0x00 29. " TXFULL , Transmit data buffer full" "Not full,Full"
|
|
bitfld.long 0x00 28. " BITERR , Bit error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 27. " DESYNC , Desynchronization of slave device" "No,Yes"
|
|
bitfld.long 0x00 26. " PARITYERR , Parity error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 25. " TIMEOUT , Time-out because of non-activation of ENA pin" "No timeout,Timeout"
|
|
bitfld.long 0x00 24. " DLENERR , Data length error flag" "No,Yes"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " LCSNR , Last chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " RXDATA , SPI receive data"
|
|
rgroup.long (0xB4+0x200)++0x03
|
|
line.long 0x00 "RXRAM, Multi-buffer RAM Receive Buffer Register 45"
|
|
bitfld.long 0x00 31. " RXEMPTY , Receive data buffer empty" "Not empty,Empty"
|
|
bitfld.long 0x00 30. " RXOVR , Receive data buffer overrun" "No overrun,Overrun"
|
|
newline
|
|
bitfld.long 0x00 29. " TXFULL , Transmit data buffer full" "Not full,Full"
|
|
bitfld.long 0x00 28. " BITERR , Bit error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 27. " DESYNC , Desynchronization of slave device" "No,Yes"
|
|
bitfld.long 0x00 26. " PARITYERR , Parity error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 25. " TIMEOUT , Time-out because of non-activation of ENA pin" "No timeout,Timeout"
|
|
bitfld.long 0x00 24. " DLENERR , Data length error flag" "No,Yes"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " LCSNR , Last chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " RXDATA , SPI receive data"
|
|
rgroup.long (0xB8+0x200)++0x03
|
|
line.long 0x00 "RXRAM, Multi-buffer RAM Receive Buffer Register 46"
|
|
bitfld.long 0x00 31. " RXEMPTY , Receive data buffer empty" "Not empty,Empty"
|
|
bitfld.long 0x00 30. " RXOVR , Receive data buffer overrun" "No overrun,Overrun"
|
|
newline
|
|
bitfld.long 0x00 29. " TXFULL , Transmit data buffer full" "Not full,Full"
|
|
bitfld.long 0x00 28. " BITERR , Bit error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 27. " DESYNC , Desynchronization of slave device" "No,Yes"
|
|
bitfld.long 0x00 26. " PARITYERR , Parity error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 25. " TIMEOUT , Time-out because of non-activation of ENA pin" "No timeout,Timeout"
|
|
bitfld.long 0x00 24. " DLENERR , Data length error flag" "No,Yes"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " LCSNR , Last chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " RXDATA , SPI receive data"
|
|
rgroup.long (0xBC+0x200)++0x03
|
|
line.long 0x00 "RXRAM, Multi-buffer RAM Receive Buffer Register 47"
|
|
bitfld.long 0x00 31. " RXEMPTY , Receive data buffer empty" "Not empty,Empty"
|
|
bitfld.long 0x00 30. " RXOVR , Receive data buffer overrun" "No overrun,Overrun"
|
|
newline
|
|
bitfld.long 0x00 29. " TXFULL , Transmit data buffer full" "Not full,Full"
|
|
bitfld.long 0x00 28. " BITERR , Bit error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 27. " DESYNC , Desynchronization of slave device" "No,Yes"
|
|
bitfld.long 0x00 26. " PARITYERR , Parity error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 25. " TIMEOUT , Time-out because of non-activation of ENA pin" "No timeout,Timeout"
|
|
bitfld.long 0x00 24. " DLENERR , Data length error flag" "No,Yes"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " LCSNR , Last chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " RXDATA , SPI receive data"
|
|
rgroup.long (0xC0+0x200)++0x03
|
|
line.long 0x00 "RXRAM, Multi-buffer RAM Receive Buffer Register 48"
|
|
bitfld.long 0x00 31. " RXEMPTY , Receive data buffer empty" "Not empty,Empty"
|
|
bitfld.long 0x00 30. " RXOVR , Receive data buffer overrun" "No overrun,Overrun"
|
|
newline
|
|
bitfld.long 0x00 29. " TXFULL , Transmit data buffer full" "Not full,Full"
|
|
bitfld.long 0x00 28. " BITERR , Bit error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 27. " DESYNC , Desynchronization of slave device" "No,Yes"
|
|
bitfld.long 0x00 26. " PARITYERR , Parity error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 25. " TIMEOUT , Time-out because of non-activation of ENA pin" "No timeout,Timeout"
|
|
bitfld.long 0x00 24. " DLENERR , Data length error flag" "No,Yes"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " LCSNR , Last chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " RXDATA , SPI receive data"
|
|
rgroup.long (0xC4+0x200)++0x03
|
|
line.long 0x00 "RXRAM, Multi-buffer RAM Receive Buffer Register 49"
|
|
bitfld.long 0x00 31. " RXEMPTY , Receive data buffer empty" "Not empty,Empty"
|
|
bitfld.long 0x00 30. " RXOVR , Receive data buffer overrun" "No overrun,Overrun"
|
|
newline
|
|
bitfld.long 0x00 29. " TXFULL , Transmit data buffer full" "Not full,Full"
|
|
bitfld.long 0x00 28. " BITERR , Bit error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 27. " DESYNC , Desynchronization of slave device" "No,Yes"
|
|
bitfld.long 0x00 26. " PARITYERR , Parity error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 25. " TIMEOUT , Time-out because of non-activation of ENA pin" "No timeout,Timeout"
|
|
bitfld.long 0x00 24. " DLENERR , Data length error flag" "No,Yes"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " LCSNR , Last chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " RXDATA , SPI receive data"
|
|
rgroup.long (0xC8+0x200)++0x03
|
|
line.long 0x00 "RXRAM, Multi-buffer RAM Receive Buffer Register 50"
|
|
bitfld.long 0x00 31. " RXEMPTY , Receive data buffer empty" "Not empty,Empty"
|
|
bitfld.long 0x00 30. " RXOVR , Receive data buffer overrun" "No overrun,Overrun"
|
|
newline
|
|
bitfld.long 0x00 29. " TXFULL , Transmit data buffer full" "Not full,Full"
|
|
bitfld.long 0x00 28. " BITERR , Bit error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 27. " DESYNC , Desynchronization of slave device" "No,Yes"
|
|
bitfld.long 0x00 26. " PARITYERR , Parity error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 25. " TIMEOUT , Time-out because of non-activation of ENA pin" "No timeout,Timeout"
|
|
bitfld.long 0x00 24. " DLENERR , Data length error flag" "No,Yes"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " LCSNR , Last chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " RXDATA , SPI receive data"
|
|
rgroup.long (0xCC+0x200)++0x03
|
|
line.long 0x00 "RXRAM, Multi-buffer RAM Receive Buffer Register 51"
|
|
bitfld.long 0x00 31. " RXEMPTY , Receive data buffer empty" "Not empty,Empty"
|
|
bitfld.long 0x00 30. " RXOVR , Receive data buffer overrun" "No overrun,Overrun"
|
|
newline
|
|
bitfld.long 0x00 29. " TXFULL , Transmit data buffer full" "Not full,Full"
|
|
bitfld.long 0x00 28. " BITERR , Bit error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 27. " DESYNC , Desynchronization of slave device" "No,Yes"
|
|
bitfld.long 0x00 26. " PARITYERR , Parity error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 25. " TIMEOUT , Time-out because of non-activation of ENA pin" "No timeout,Timeout"
|
|
bitfld.long 0x00 24. " DLENERR , Data length error flag" "No,Yes"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " LCSNR , Last chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " RXDATA , SPI receive data"
|
|
rgroup.long (0xD0+0x200)++0x03
|
|
line.long 0x00 "RXRAM, Multi-buffer RAM Receive Buffer Register 52"
|
|
bitfld.long 0x00 31. " RXEMPTY , Receive data buffer empty" "Not empty,Empty"
|
|
bitfld.long 0x00 30. " RXOVR , Receive data buffer overrun" "No overrun,Overrun"
|
|
newline
|
|
bitfld.long 0x00 29. " TXFULL , Transmit data buffer full" "Not full,Full"
|
|
bitfld.long 0x00 28. " BITERR , Bit error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 27. " DESYNC , Desynchronization of slave device" "No,Yes"
|
|
bitfld.long 0x00 26. " PARITYERR , Parity error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 25. " TIMEOUT , Time-out because of non-activation of ENA pin" "No timeout,Timeout"
|
|
bitfld.long 0x00 24. " DLENERR , Data length error flag" "No,Yes"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " LCSNR , Last chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " RXDATA , SPI receive data"
|
|
rgroup.long (0xD4+0x200)++0x03
|
|
line.long 0x00 "RXRAM, Multi-buffer RAM Receive Buffer Register 53"
|
|
bitfld.long 0x00 31. " RXEMPTY , Receive data buffer empty" "Not empty,Empty"
|
|
bitfld.long 0x00 30. " RXOVR , Receive data buffer overrun" "No overrun,Overrun"
|
|
newline
|
|
bitfld.long 0x00 29. " TXFULL , Transmit data buffer full" "Not full,Full"
|
|
bitfld.long 0x00 28. " BITERR , Bit error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 27. " DESYNC , Desynchronization of slave device" "No,Yes"
|
|
bitfld.long 0x00 26. " PARITYERR , Parity error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 25. " TIMEOUT , Time-out because of non-activation of ENA pin" "No timeout,Timeout"
|
|
bitfld.long 0x00 24. " DLENERR , Data length error flag" "No,Yes"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " LCSNR , Last chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " RXDATA , SPI receive data"
|
|
rgroup.long (0xD8+0x200)++0x03
|
|
line.long 0x00 "RXRAM, Multi-buffer RAM Receive Buffer Register 54"
|
|
bitfld.long 0x00 31. " RXEMPTY , Receive data buffer empty" "Not empty,Empty"
|
|
bitfld.long 0x00 30. " RXOVR , Receive data buffer overrun" "No overrun,Overrun"
|
|
newline
|
|
bitfld.long 0x00 29. " TXFULL , Transmit data buffer full" "Not full,Full"
|
|
bitfld.long 0x00 28. " BITERR , Bit error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 27. " DESYNC , Desynchronization of slave device" "No,Yes"
|
|
bitfld.long 0x00 26. " PARITYERR , Parity error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 25. " TIMEOUT , Time-out because of non-activation of ENA pin" "No timeout,Timeout"
|
|
bitfld.long 0x00 24. " DLENERR , Data length error flag" "No,Yes"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " LCSNR , Last chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " RXDATA , SPI receive data"
|
|
rgroup.long (0xDC+0x200)++0x03
|
|
line.long 0x00 "RXRAM, Multi-buffer RAM Receive Buffer Register 55"
|
|
bitfld.long 0x00 31. " RXEMPTY , Receive data buffer empty" "Not empty,Empty"
|
|
bitfld.long 0x00 30. " RXOVR , Receive data buffer overrun" "No overrun,Overrun"
|
|
newline
|
|
bitfld.long 0x00 29. " TXFULL , Transmit data buffer full" "Not full,Full"
|
|
bitfld.long 0x00 28. " BITERR , Bit error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 27. " DESYNC , Desynchronization of slave device" "No,Yes"
|
|
bitfld.long 0x00 26. " PARITYERR , Parity error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 25. " TIMEOUT , Time-out because of non-activation of ENA pin" "No timeout,Timeout"
|
|
bitfld.long 0x00 24. " DLENERR , Data length error flag" "No,Yes"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " LCSNR , Last chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " RXDATA , SPI receive data"
|
|
rgroup.long (0xE0+0x200)++0x03
|
|
line.long 0x00 "RXRAM, Multi-buffer RAM Receive Buffer Register 56"
|
|
bitfld.long 0x00 31. " RXEMPTY , Receive data buffer empty" "Not empty,Empty"
|
|
bitfld.long 0x00 30. " RXOVR , Receive data buffer overrun" "No overrun,Overrun"
|
|
newline
|
|
bitfld.long 0x00 29. " TXFULL , Transmit data buffer full" "Not full,Full"
|
|
bitfld.long 0x00 28. " BITERR , Bit error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 27. " DESYNC , Desynchronization of slave device" "No,Yes"
|
|
bitfld.long 0x00 26. " PARITYERR , Parity error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 25. " TIMEOUT , Time-out because of non-activation of ENA pin" "No timeout,Timeout"
|
|
bitfld.long 0x00 24. " DLENERR , Data length error flag" "No,Yes"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " LCSNR , Last chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " RXDATA , SPI receive data"
|
|
rgroup.long (0xE4+0x200)++0x03
|
|
line.long 0x00 "RXRAM, Multi-buffer RAM Receive Buffer Register 57"
|
|
bitfld.long 0x00 31. " RXEMPTY , Receive data buffer empty" "Not empty,Empty"
|
|
bitfld.long 0x00 30. " RXOVR , Receive data buffer overrun" "No overrun,Overrun"
|
|
newline
|
|
bitfld.long 0x00 29. " TXFULL , Transmit data buffer full" "Not full,Full"
|
|
bitfld.long 0x00 28. " BITERR , Bit error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 27. " DESYNC , Desynchronization of slave device" "No,Yes"
|
|
bitfld.long 0x00 26. " PARITYERR , Parity error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 25. " TIMEOUT , Time-out because of non-activation of ENA pin" "No timeout,Timeout"
|
|
bitfld.long 0x00 24. " DLENERR , Data length error flag" "No,Yes"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " LCSNR , Last chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " RXDATA , SPI receive data"
|
|
rgroup.long (0xE8+0x200)++0x03
|
|
line.long 0x00 "RXRAM, Multi-buffer RAM Receive Buffer Register 58"
|
|
bitfld.long 0x00 31. " RXEMPTY , Receive data buffer empty" "Not empty,Empty"
|
|
bitfld.long 0x00 30. " RXOVR , Receive data buffer overrun" "No overrun,Overrun"
|
|
newline
|
|
bitfld.long 0x00 29. " TXFULL , Transmit data buffer full" "Not full,Full"
|
|
bitfld.long 0x00 28. " BITERR , Bit error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 27. " DESYNC , Desynchronization of slave device" "No,Yes"
|
|
bitfld.long 0x00 26. " PARITYERR , Parity error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 25. " TIMEOUT , Time-out because of non-activation of ENA pin" "No timeout,Timeout"
|
|
bitfld.long 0x00 24. " DLENERR , Data length error flag" "No,Yes"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " LCSNR , Last chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " RXDATA , SPI receive data"
|
|
rgroup.long (0xEC+0x200)++0x03
|
|
line.long 0x00 "RXRAM, Multi-buffer RAM Receive Buffer Register 59"
|
|
bitfld.long 0x00 31. " RXEMPTY , Receive data buffer empty" "Not empty,Empty"
|
|
bitfld.long 0x00 30. " RXOVR , Receive data buffer overrun" "No overrun,Overrun"
|
|
newline
|
|
bitfld.long 0x00 29. " TXFULL , Transmit data buffer full" "Not full,Full"
|
|
bitfld.long 0x00 28. " BITERR , Bit error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 27. " DESYNC , Desynchronization of slave device" "No,Yes"
|
|
bitfld.long 0x00 26. " PARITYERR , Parity error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 25. " TIMEOUT , Time-out because of non-activation of ENA pin" "No timeout,Timeout"
|
|
bitfld.long 0x00 24. " DLENERR , Data length error flag" "No,Yes"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " LCSNR , Last chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " RXDATA , SPI receive data"
|
|
rgroup.long (0xF0+0x200)++0x03
|
|
line.long 0x00 "RXRAM, Multi-buffer RAM Receive Buffer Register 60"
|
|
bitfld.long 0x00 31. " RXEMPTY , Receive data buffer empty" "Not empty,Empty"
|
|
bitfld.long 0x00 30. " RXOVR , Receive data buffer overrun" "No overrun,Overrun"
|
|
newline
|
|
bitfld.long 0x00 29. " TXFULL , Transmit data buffer full" "Not full,Full"
|
|
bitfld.long 0x00 28. " BITERR , Bit error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 27. " DESYNC , Desynchronization of slave device" "No,Yes"
|
|
bitfld.long 0x00 26. " PARITYERR , Parity error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 25. " TIMEOUT , Time-out because of non-activation of ENA pin" "No timeout,Timeout"
|
|
bitfld.long 0x00 24. " DLENERR , Data length error flag" "No,Yes"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " LCSNR , Last chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " RXDATA , SPI receive data"
|
|
rgroup.long (0xF4+0x200)++0x03
|
|
line.long 0x00 "RXRAM, Multi-buffer RAM Receive Buffer Register 61"
|
|
bitfld.long 0x00 31. " RXEMPTY , Receive data buffer empty" "Not empty,Empty"
|
|
bitfld.long 0x00 30. " RXOVR , Receive data buffer overrun" "No overrun,Overrun"
|
|
newline
|
|
bitfld.long 0x00 29. " TXFULL , Transmit data buffer full" "Not full,Full"
|
|
bitfld.long 0x00 28. " BITERR , Bit error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 27. " DESYNC , Desynchronization of slave device" "No,Yes"
|
|
bitfld.long 0x00 26. " PARITYERR , Parity error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 25. " TIMEOUT , Time-out because of non-activation of ENA pin" "No timeout,Timeout"
|
|
bitfld.long 0x00 24. " DLENERR , Data length error flag" "No,Yes"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " LCSNR , Last chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " RXDATA , SPI receive data"
|
|
rgroup.long (0xF8+0x200)++0x03
|
|
line.long 0x00 "RXRAM, Multi-buffer RAM Receive Buffer Register 62"
|
|
bitfld.long 0x00 31. " RXEMPTY , Receive data buffer empty" "Not empty,Empty"
|
|
bitfld.long 0x00 30. " RXOVR , Receive data buffer overrun" "No overrun,Overrun"
|
|
newline
|
|
bitfld.long 0x00 29. " TXFULL , Transmit data buffer full" "Not full,Full"
|
|
bitfld.long 0x00 28. " BITERR , Bit error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 27. " DESYNC , Desynchronization of slave device" "No,Yes"
|
|
bitfld.long 0x00 26. " PARITYERR , Parity error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 25. " TIMEOUT , Time-out because of non-activation of ENA pin" "No timeout,Timeout"
|
|
bitfld.long 0x00 24. " DLENERR , Data length error flag" "No,Yes"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " LCSNR , Last chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " RXDATA , SPI receive data"
|
|
rgroup.long (0xFC+0x200)++0x03
|
|
line.long 0x00 "RXRAM, Multi-buffer RAM Receive Buffer Register 63"
|
|
bitfld.long 0x00 31. " RXEMPTY , Receive data buffer empty" "Not empty,Empty"
|
|
bitfld.long 0x00 30. " RXOVR , Receive data buffer overrun" "No overrun,Overrun"
|
|
newline
|
|
bitfld.long 0x00 29. " TXFULL , Transmit data buffer full" "Not full,Full"
|
|
bitfld.long 0x00 28. " BITERR , Bit error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 27. " DESYNC , Desynchronization of slave device" "No,Yes"
|
|
bitfld.long 0x00 26. " PARITYERR , Parity error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 25. " TIMEOUT , Time-out because of non-activation of ENA pin" "No timeout,Timeout"
|
|
bitfld.long 0x00 24. " DLENERR , Data length error flag" "No,Yes"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " LCSNR , Last chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " RXDATA , SPI receive data"
|
|
rgroup.long (0x100+0x200)++0x03
|
|
line.long 0x00 "RXRAM, Multi-buffer RAM Receive Buffer Register 64"
|
|
bitfld.long 0x00 31. " RXEMPTY , Receive data buffer empty" "Not empty,Empty"
|
|
bitfld.long 0x00 30. " RXOVR , Receive data buffer overrun" "No overrun,Overrun"
|
|
newline
|
|
bitfld.long 0x00 29. " TXFULL , Transmit data buffer full" "Not full,Full"
|
|
bitfld.long 0x00 28. " BITERR , Bit error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 27. " DESYNC , Desynchronization of slave device" "No,Yes"
|
|
bitfld.long 0x00 26. " PARITYERR , Parity error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 25. " TIMEOUT , Time-out because of non-activation of ENA pin" "No timeout,Timeout"
|
|
bitfld.long 0x00 24. " DLENERR , Data length error flag" "No,Yes"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " LCSNR , Last chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " RXDATA , SPI receive data"
|
|
rgroup.long (0x104+0x200)++0x03
|
|
line.long 0x00 "RXRAM, Multi-buffer RAM Receive Buffer Register 65"
|
|
bitfld.long 0x00 31. " RXEMPTY , Receive data buffer empty" "Not empty,Empty"
|
|
bitfld.long 0x00 30. " RXOVR , Receive data buffer overrun" "No overrun,Overrun"
|
|
newline
|
|
bitfld.long 0x00 29. " TXFULL , Transmit data buffer full" "Not full,Full"
|
|
bitfld.long 0x00 28. " BITERR , Bit error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 27. " DESYNC , Desynchronization of slave device" "No,Yes"
|
|
bitfld.long 0x00 26. " PARITYERR , Parity error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 25. " TIMEOUT , Time-out because of non-activation of ENA pin" "No timeout,Timeout"
|
|
bitfld.long 0x00 24. " DLENERR , Data length error flag" "No,Yes"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " LCSNR , Last chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " RXDATA , SPI receive data"
|
|
rgroup.long (0x108+0x200)++0x03
|
|
line.long 0x00 "RXRAM, Multi-buffer RAM Receive Buffer Register 66"
|
|
bitfld.long 0x00 31. " RXEMPTY , Receive data buffer empty" "Not empty,Empty"
|
|
bitfld.long 0x00 30. " RXOVR , Receive data buffer overrun" "No overrun,Overrun"
|
|
newline
|
|
bitfld.long 0x00 29. " TXFULL , Transmit data buffer full" "Not full,Full"
|
|
bitfld.long 0x00 28. " BITERR , Bit error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 27. " DESYNC , Desynchronization of slave device" "No,Yes"
|
|
bitfld.long 0x00 26. " PARITYERR , Parity error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 25. " TIMEOUT , Time-out because of non-activation of ENA pin" "No timeout,Timeout"
|
|
bitfld.long 0x00 24. " DLENERR , Data length error flag" "No,Yes"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " LCSNR , Last chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " RXDATA , SPI receive data"
|
|
rgroup.long (0x10C+0x200)++0x03
|
|
line.long 0x00 "RXRAM, Multi-buffer RAM Receive Buffer Register 67"
|
|
bitfld.long 0x00 31. " RXEMPTY , Receive data buffer empty" "Not empty,Empty"
|
|
bitfld.long 0x00 30. " RXOVR , Receive data buffer overrun" "No overrun,Overrun"
|
|
newline
|
|
bitfld.long 0x00 29. " TXFULL , Transmit data buffer full" "Not full,Full"
|
|
bitfld.long 0x00 28. " BITERR , Bit error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 27. " DESYNC , Desynchronization of slave device" "No,Yes"
|
|
bitfld.long 0x00 26. " PARITYERR , Parity error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 25. " TIMEOUT , Time-out because of non-activation of ENA pin" "No timeout,Timeout"
|
|
bitfld.long 0x00 24. " DLENERR , Data length error flag" "No,Yes"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " LCSNR , Last chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " RXDATA , SPI receive data"
|
|
rgroup.long (0x110+0x200)++0x03
|
|
line.long 0x00 "RXRAM, Multi-buffer RAM Receive Buffer Register 68"
|
|
bitfld.long 0x00 31. " RXEMPTY , Receive data buffer empty" "Not empty,Empty"
|
|
bitfld.long 0x00 30. " RXOVR , Receive data buffer overrun" "No overrun,Overrun"
|
|
newline
|
|
bitfld.long 0x00 29. " TXFULL , Transmit data buffer full" "Not full,Full"
|
|
bitfld.long 0x00 28. " BITERR , Bit error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 27. " DESYNC , Desynchronization of slave device" "No,Yes"
|
|
bitfld.long 0x00 26. " PARITYERR , Parity error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 25. " TIMEOUT , Time-out because of non-activation of ENA pin" "No timeout,Timeout"
|
|
bitfld.long 0x00 24. " DLENERR , Data length error flag" "No,Yes"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " LCSNR , Last chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " RXDATA , SPI receive data"
|
|
rgroup.long (0x114+0x200)++0x03
|
|
line.long 0x00 "RXRAM, Multi-buffer RAM Receive Buffer Register 69"
|
|
bitfld.long 0x00 31. " RXEMPTY , Receive data buffer empty" "Not empty,Empty"
|
|
bitfld.long 0x00 30. " RXOVR , Receive data buffer overrun" "No overrun,Overrun"
|
|
newline
|
|
bitfld.long 0x00 29. " TXFULL , Transmit data buffer full" "Not full,Full"
|
|
bitfld.long 0x00 28. " BITERR , Bit error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 27. " DESYNC , Desynchronization of slave device" "No,Yes"
|
|
bitfld.long 0x00 26. " PARITYERR , Parity error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 25. " TIMEOUT , Time-out because of non-activation of ENA pin" "No timeout,Timeout"
|
|
bitfld.long 0x00 24. " DLENERR , Data length error flag" "No,Yes"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " LCSNR , Last chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " RXDATA , SPI receive data"
|
|
rgroup.long (0x118+0x200)++0x03
|
|
line.long 0x00 "RXRAM, Multi-buffer RAM Receive Buffer Register 70"
|
|
bitfld.long 0x00 31. " RXEMPTY , Receive data buffer empty" "Not empty,Empty"
|
|
bitfld.long 0x00 30. " RXOVR , Receive data buffer overrun" "No overrun,Overrun"
|
|
newline
|
|
bitfld.long 0x00 29. " TXFULL , Transmit data buffer full" "Not full,Full"
|
|
bitfld.long 0x00 28. " BITERR , Bit error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 27. " DESYNC , Desynchronization of slave device" "No,Yes"
|
|
bitfld.long 0x00 26. " PARITYERR , Parity error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 25. " TIMEOUT , Time-out because of non-activation of ENA pin" "No timeout,Timeout"
|
|
bitfld.long 0x00 24. " DLENERR , Data length error flag" "No,Yes"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " LCSNR , Last chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " RXDATA , SPI receive data"
|
|
rgroup.long (0x11C+0x200)++0x03
|
|
line.long 0x00 "RXRAM, Multi-buffer RAM Receive Buffer Register 71"
|
|
bitfld.long 0x00 31. " RXEMPTY , Receive data buffer empty" "Not empty,Empty"
|
|
bitfld.long 0x00 30. " RXOVR , Receive data buffer overrun" "No overrun,Overrun"
|
|
newline
|
|
bitfld.long 0x00 29. " TXFULL , Transmit data buffer full" "Not full,Full"
|
|
bitfld.long 0x00 28. " BITERR , Bit error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 27. " DESYNC , Desynchronization of slave device" "No,Yes"
|
|
bitfld.long 0x00 26. " PARITYERR , Parity error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 25. " TIMEOUT , Time-out because of non-activation of ENA pin" "No timeout,Timeout"
|
|
bitfld.long 0x00 24. " DLENERR , Data length error flag" "No,Yes"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " LCSNR , Last chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " RXDATA , SPI receive data"
|
|
rgroup.long (0x120+0x200)++0x03
|
|
line.long 0x00 "RXRAM, Multi-buffer RAM Receive Buffer Register 72"
|
|
bitfld.long 0x00 31. " RXEMPTY , Receive data buffer empty" "Not empty,Empty"
|
|
bitfld.long 0x00 30. " RXOVR , Receive data buffer overrun" "No overrun,Overrun"
|
|
newline
|
|
bitfld.long 0x00 29. " TXFULL , Transmit data buffer full" "Not full,Full"
|
|
bitfld.long 0x00 28. " BITERR , Bit error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 27. " DESYNC , Desynchronization of slave device" "No,Yes"
|
|
bitfld.long 0x00 26. " PARITYERR , Parity error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 25. " TIMEOUT , Time-out because of non-activation of ENA pin" "No timeout,Timeout"
|
|
bitfld.long 0x00 24. " DLENERR , Data length error flag" "No,Yes"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " LCSNR , Last chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " RXDATA , SPI receive data"
|
|
rgroup.long (0x124+0x200)++0x03
|
|
line.long 0x00 "RXRAM, Multi-buffer RAM Receive Buffer Register 73"
|
|
bitfld.long 0x00 31. " RXEMPTY , Receive data buffer empty" "Not empty,Empty"
|
|
bitfld.long 0x00 30. " RXOVR , Receive data buffer overrun" "No overrun,Overrun"
|
|
newline
|
|
bitfld.long 0x00 29. " TXFULL , Transmit data buffer full" "Not full,Full"
|
|
bitfld.long 0x00 28. " BITERR , Bit error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 27. " DESYNC , Desynchronization of slave device" "No,Yes"
|
|
bitfld.long 0x00 26. " PARITYERR , Parity error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 25. " TIMEOUT , Time-out because of non-activation of ENA pin" "No timeout,Timeout"
|
|
bitfld.long 0x00 24. " DLENERR , Data length error flag" "No,Yes"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " LCSNR , Last chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " RXDATA , SPI receive data"
|
|
rgroup.long (0x128+0x200)++0x03
|
|
line.long 0x00 "RXRAM, Multi-buffer RAM Receive Buffer Register 74"
|
|
bitfld.long 0x00 31. " RXEMPTY , Receive data buffer empty" "Not empty,Empty"
|
|
bitfld.long 0x00 30. " RXOVR , Receive data buffer overrun" "No overrun,Overrun"
|
|
newline
|
|
bitfld.long 0x00 29. " TXFULL , Transmit data buffer full" "Not full,Full"
|
|
bitfld.long 0x00 28. " BITERR , Bit error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 27. " DESYNC , Desynchronization of slave device" "No,Yes"
|
|
bitfld.long 0x00 26. " PARITYERR , Parity error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 25. " TIMEOUT , Time-out because of non-activation of ENA pin" "No timeout,Timeout"
|
|
bitfld.long 0x00 24. " DLENERR , Data length error flag" "No,Yes"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " LCSNR , Last chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " RXDATA , SPI receive data"
|
|
rgroup.long (0x12C+0x200)++0x03
|
|
line.long 0x00 "RXRAM, Multi-buffer RAM Receive Buffer Register 75"
|
|
bitfld.long 0x00 31. " RXEMPTY , Receive data buffer empty" "Not empty,Empty"
|
|
bitfld.long 0x00 30. " RXOVR , Receive data buffer overrun" "No overrun,Overrun"
|
|
newline
|
|
bitfld.long 0x00 29. " TXFULL , Transmit data buffer full" "Not full,Full"
|
|
bitfld.long 0x00 28. " BITERR , Bit error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 27. " DESYNC , Desynchronization of slave device" "No,Yes"
|
|
bitfld.long 0x00 26. " PARITYERR , Parity error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 25. " TIMEOUT , Time-out because of non-activation of ENA pin" "No timeout,Timeout"
|
|
bitfld.long 0x00 24. " DLENERR , Data length error flag" "No,Yes"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " LCSNR , Last chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " RXDATA , SPI receive data"
|
|
rgroup.long (0x130+0x200)++0x03
|
|
line.long 0x00 "RXRAM, Multi-buffer RAM Receive Buffer Register 76"
|
|
bitfld.long 0x00 31. " RXEMPTY , Receive data buffer empty" "Not empty,Empty"
|
|
bitfld.long 0x00 30. " RXOVR , Receive data buffer overrun" "No overrun,Overrun"
|
|
newline
|
|
bitfld.long 0x00 29. " TXFULL , Transmit data buffer full" "Not full,Full"
|
|
bitfld.long 0x00 28. " BITERR , Bit error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 27. " DESYNC , Desynchronization of slave device" "No,Yes"
|
|
bitfld.long 0x00 26. " PARITYERR , Parity error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 25. " TIMEOUT , Time-out because of non-activation of ENA pin" "No timeout,Timeout"
|
|
bitfld.long 0x00 24. " DLENERR , Data length error flag" "No,Yes"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " LCSNR , Last chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " RXDATA , SPI receive data"
|
|
rgroup.long (0x134+0x200)++0x03
|
|
line.long 0x00 "RXRAM, Multi-buffer RAM Receive Buffer Register 77"
|
|
bitfld.long 0x00 31. " RXEMPTY , Receive data buffer empty" "Not empty,Empty"
|
|
bitfld.long 0x00 30. " RXOVR , Receive data buffer overrun" "No overrun,Overrun"
|
|
newline
|
|
bitfld.long 0x00 29. " TXFULL , Transmit data buffer full" "Not full,Full"
|
|
bitfld.long 0x00 28. " BITERR , Bit error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 27. " DESYNC , Desynchronization of slave device" "No,Yes"
|
|
bitfld.long 0x00 26. " PARITYERR , Parity error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 25. " TIMEOUT , Time-out because of non-activation of ENA pin" "No timeout,Timeout"
|
|
bitfld.long 0x00 24. " DLENERR , Data length error flag" "No,Yes"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " LCSNR , Last chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " RXDATA , SPI receive data"
|
|
rgroup.long (0x138+0x200)++0x03
|
|
line.long 0x00 "RXRAM, Multi-buffer RAM Receive Buffer Register 78"
|
|
bitfld.long 0x00 31. " RXEMPTY , Receive data buffer empty" "Not empty,Empty"
|
|
bitfld.long 0x00 30. " RXOVR , Receive data buffer overrun" "No overrun,Overrun"
|
|
newline
|
|
bitfld.long 0x00 29. " TXFULL , Transmit data buffer full" "Not full,Full"
|
|
bitfld.long 0x00 28. " BITERR , Bit error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 27. " DESYNC , Desynchronization of slave device" "No,Yes"
|
|
bitfld.long 0x00 26. " PARITYERR , Parity error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 25. " TIMEOUT , Time-out because of non-activation of ENA pin" "No timeout,Timeout"
|
|
bitfld.long 0x00 24. " DLENERR , Data length error flag" "No,Yes"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " LCSNR , Last chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " RXDATA , SPI receive data"
|
|
rgroup.long (0x13C+0x200)++0x03
|
|
line.long 0x00 "RXRAM, Multi-buffer RAM Receive Buffer Register 79"
|
|
bitfld.long 0x00 31. " RXEMPTY , Receive data buffer empty" "Not empty,Empty"
|
|
bitfld.long 0x00 30. " RXOVR , Receive data buffer overrun" "No overrun,Overrun"
|
|
newline
|
|
bitfld.long 0x00 29. " TXFULL , Transmit data buffer full" "Not full,Full"
|
|
bitfld.long 0x00 28. " BITERR , Bit error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 27. " DESYNC , Desynchronization of slave device" "No,Yes"
|
|
bitfld.long 0x00 26. " PARITYERR , Parity error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 25. " TIMEOUT , Time-out because of non-activation of ENA pin" "No timeout,Timeout"
|
|
bitfld.long 0x00 24. " DLENERR , Data length error flag" "No,Yes"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " LCSNR , Last chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " RXDATA , SPI receive data"
|
|
else
|
|
tree "Transmit Buffers"
|
|
group.long 0x0++0x03
|
|
line.long 0x00 "BUFFER0,Buffer 0 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x4++0x03
|
|
line.long 0x00 "BUFFER1,Buffer 1 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x8++0x03
|
|
line.long 0x00 "BUFFER2,Buffer 2 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0xC++0x03
|
|
line.long 0x00 "BUFFER3,Buffer 3 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "BUFFER4,Buffer 4 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "BUFFER5,Buffer 5 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "BUFFER6,Buffer 6 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "BUFFER7,Buffer 7 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "BUFFER8,Buffer 8 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "BUFFER9,Buffer 9 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "BUFFER10,Buffer 10 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "BUFFER11,Buffer 11 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "BUFFER12,Buffer 12 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x34++0x03
|
|
line.long 0x00 "BUFFER13,Buffer 13 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x38++0x03
|
|
line.long 0x00 "BUFFER14,Buffer 14 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x3C++0x03
|
|
line.long 0x00 "BUFFER15,Buffer 15 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "BUFFER16,Buffer 16 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x44++0x03
|
|
line.long 0x00 "BUFFER17,Buffer 17 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x48++0x03
|
|
line.long 0x00 "BUFFER18,Buffer 18 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x4C++0x03
|
|
line.long 0x00 "BUFFER19,Buffer 19 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x50++0x03
|
|
line.long 0x00 "BUFFER20,Buffer 20 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x54++0x03
|
|
line.long 0x00 "BUFFER21,Buffer 21 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x58++0x03
|
|
line.long 0x00 "BUFFER22,Buffer 22 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x5C++0x03
|
|
line.long 0x00 "BUFFER23,Buffer 23 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x60++0x03
|
|
line.long 0x00 "BUFFER24,Buffer 24 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x64++0x03
|
|
line.long 0x00 "BUFFER25,Buffer 25 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x68++0x03
|
|
line.long 0x00 "BUFFER26,Buffer 26 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x6C++0x03
|
|
line.long 0x00 "BUFFER27,Buffer 27 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x70++0x03
|
|
line.long 0x00 "BUFFER28,Buffer 28 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x74++0x03
|
|
line.long 0x00 "BUFFER29,Buffer 29 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x78++0x03
|
|
line.long 0x00 "BUFFER30,Buffer 30 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x7C++0x03
|
|
line.long 0x00 "BUFFER31,Buffer 31 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x80++0x03
|
|
line.long 0x00 "BUFFER32,Buffer 32 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x84++0x03
|
|
line.long 0x00 "BUFFER33,Buffer 33 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x88++0x03
|
|
line.long 0x00 "BUFFER34,Buffer 34 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x8C++0x03
|
|
line.long 0x00 "BUFFER35,Buffer 35 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x90++0x03
|
|
line.long 0x00 "BUFFER36,Buffer 36 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x94++0x03
|
|
line.long 0x00 "BUFFER37,Buffer 37 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x98++0x03
|
|
line.long 0x00 "BUFFER38,Buffer 38 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x9C++0x03
|
|
line.long 0x00 "BUFFER39,Buffer 39 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0xA0++0x03
|
|
line.long 0x00 "BUFFER40,Buffer 40 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0xA4++0x03
|
|
line.long 0x00 "BUFFER41,Buffer 41 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0xA8++0x03
|
|
line.long 0x00 "BUFFER42,Buffer 42 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0xAC++0x03
|
|
line.long 0x00 "BUFFER43,Buffer 43 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0xB0++0x03
|
|
line.long 0x00 "BUFFER44,Buffer 44 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0xB4++0x03
|
|
line.long 0x00 "BUFFER45,Buffer 45 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0xB8++0x03
|
|
line.long 0x00 "BUFFER46,Buffer 46 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0xBC++0x03
|
|
line.long 0x00 "BUFFER47,Buffer 47 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0xC0++0x03
|
|
line.long 0x00 "BUFFER48,Buffer 48 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0xC4++0x03
|
|
line.long 0x00 "BUFFER49,Buffer 49 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0xC8++0x03
|
|
line.long 0x00 "BUFFER50,Buffer 50 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0xCC++0x03
|
|
line.long 0x00 "BUFFER51,Buffer 51 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0xD0++0x03
|
|
line.long 0x00 "BUFFER52,Buffer 52 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0xD4++0x03
|
|
line.long 0x00 "BUFFER53,Buffer 53 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0xD8++0x03
|
|
line.long 0x00 "BUFFER54,Buffer 54 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0xDC++0x03
|
|
line.long 0x00 "BUFFER55,Buffer 55 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0xE0++0x03
|
|
line.long 0x00 "BUFFER56,Buffer 56 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0xE4++0x03
|
|
line.long 0x00 "BUFFER57,Buffer 57 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0xE8++0x03
|
|
line.long 0x00 "BUFFER58,Buffer 58 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0xEC++0x03
|
|
line.long 0x00 "BUFFER59,Buffer 59 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0xF0++0x03
|
|
line.long 0x00 "BUFFER60,Buffer 60 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0xF4++0x03
|
|
line.long 0x00 "BUFFER61,Buffer 61 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0xF8++0x03
|
|
line.long 0x00 "BUFFER62,Buffer 62 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0xFC++0x03
|
|
line.long 0x00 "BUFFER63,Buffer 63 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x100++0x03
|
|
line.long 0x00 "BUFFER64,Buffer 64 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x104++0x03
|
|
line.long 0x00 "BUFFER65,Buffer 65 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x108++0x03
|
|
line.long 0x00 "BUFFER66,Buffer 66 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x10C++0x03
|
|
line.long 0x00 "BUFFER67,Buffer 67 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x110++0x03
|
|
line.long 0x00 "BUFFER68,Buffer 68 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x114++0x03
|
|
line.long 0x00 "BUFFER69,Buffer 69 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x118++0x03
|
|
line.long 0x00 "BUFFER70,Buffer 70 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x11C++0x03
|
|
line.long 0x00 "BUFFER71,Buffer 71 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x120++0x03
|
|
line.long 0x00 "BUFFER72,Buffer 72 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x124++0x03
|
|
line.long 0x00 "BUFFER73,Buffer 73 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x128++0x03
|
|
line.long 0x00 "BUFFER74,Buffer 74 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x12C++0x03
|
|
line.long 0x00 "BUFFER75,Buffer 75 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x130++0x03
|
|
line.long 0x00 "BUFFER76,Buffer 76 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x134++0x03
|
|
line.long 0x00 "BUFFER77,Buffer 77 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x138++0x03
|
|
line.long 0x00 "BUFFER78,Buffer 78 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x13C++0x03
|
|
line.long 0x00 "BUFFER79,Buffer 79 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x140++0x03
|
|
line.long 0x00 "BUFFER80,Buffer 80 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x144++0x03
|
|
line.long 0x00 "BUFFER81,Buffer 81 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x148++0x03
|
|
line.long 0x00 "BUFFER82,Buffer 82 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x14C++0x03
|
|
line.long 0x00 "BUFFER83,Buffer 83 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x150++0x03
|
|
line.long 0x00 "BUFFER84,Buffer 84 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x154++0x03
|
|
line.long 0x00 "BUFFER85,Buffer 85 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x158++0x03
|
|
line.long 0x00 "BUFFER86,Buffer 86 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x15C++0x03
|
|
line.long 0x00 "BUFFER87,Buffer 87 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x160++0x03
|
|
line.long 0x00 "BUFFER88,Buffer 88 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x164++0x03
|
|
line.long 0x00 "BUFFER89,Buffer 89 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x168++0x03
|
|
line.long 0x00 "BUFFER90,Buffer 90 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x16C++0x03
|
|
line.long 0x00 "BUFFER91,Buffer 91 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x170++0x03
|
|
line.long 0x00 "BUFFER92,Buffer 92 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x174++0x03
|
|
line.long 0x00 "BUFFER93,Buffer 93 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x178++0x03
|
|
line.long 0x00 "BUFFER94,Buffer 94 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x17C++0x03
|
|
line.long 0x00 "BUFFER95,Buffer 95 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x180++0x03
|
|
line.long 0x00 "BUFFER96,Buffer 96 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x184++0x03
|
|
line.long 0x00 "BUFFER97,Buffer 97 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x188++0x03
|
|
line.long 0x00 "BUFFER98,Buffer 98 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x18C++0x03
|
|
line.long 0x00 "BUFFER99,Buffer 99 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x190++0x03
|
|
line.long 0x00 "BUFFER100,Buffer 100 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x194++0x03
|
|
line.long 0x00 "BUFFER101,Buffer 101 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x198++0x03
|
|
line.long 0x00 "BUFFER102,Buffer 102 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x19C++0x03
|
|
line.long 0x00 "BUFFER103,Buffer 103 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x1A0++0x03
|
|
line.long 0x00 "BUFFER104,Buffer 104 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x1A4++0x03
|
|
line.long 0x00 "BUFFER105,Buffer 105 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x1A8++0x03
|
|
line.long 0x00 "BUFFER106,Buffer 106 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x1AC++0x03
|
|
line.long 0x00 "BUFFER107,Buffer 107 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x1B0++0x03
|
|
line.long 0x00 "BUFFER108,Buffer 108 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x1B4++0x03
|
|
line.long 0x00 "BUFFER109,Buffer 109 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x1B8++0x03
|
|
line.long 0x00 "BUFFER110,Buffer 110 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x1BC++0x03
|
|
line.long 0x00 "BUFFER111,Buffer 111 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x1C0++0x03
|
|
line.long 0x00 "BUFFER112,Buffer 112 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x1C4++0x03
|
|
line.long 0x00 "BUFFER113,Buffer 113 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x1C8++0x03
|
|
line.long 0x00 "BUFFER114,Buffer 114 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x1CC++0x03
|
|
line.long 0x00 "BUFFER115,Buffer 115 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x1D0++0x03
|
|
line.long 0x00 "BUFFER116,Buffer 116 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x1D4++0x03
|
|
line.long 0x00 "BUFFER117,Buffer 117 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x1D8++0x03
|
|
line.long 0x00 "BUFFER118,Buffer 118 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x1DC++0x03
|
|
line.long 0x00 "BUFFER119,Buffer 119 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x1E0++0x03
|
|
line.long 0x00 "BUFFER120,Buffer 120 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x1E4++0x03
|
|
line.long 0x00 "BUFFER121,Buffer 121 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x1E8++0x03
|
|
line.long 0x00 "BUFFER122,Buffer 122 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x1EC++0x03
|
|
line.long 0x00 "BUFFER123,Buffer 123 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x1F0++0x03
|
|
line.long 0x00 "BUFFER124,Buffer 124 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x1F4++0x03
|
|
line.long 0x00 "BUFFER125,Buffer 125 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x1F8++0x03
|
|
line.long 0x00 "BUFFER126,Buffer 126 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x1FC++0x03
|
|
line.long 0x00 "BUFFER127,Buffer 127 Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Buff Mode" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
tree.end
|
|
tree "Receive Buffers"
|
|
hgroup.long (0x0+0x200)++0x03
|
|
hide.long 0x00 "BUFFER0,Buffer 0 Register"
|
|
in
|
|
hgroup.long (0x4+0x200)++0x03
|
|
hide.long 0x00 "BUFFER1,Buffer 1 Register"
|
|
in
|
|
hgroup.long (0x8+0x200)++0x03
|
|
hide.long 0x00 "BUFFER2,Buffer 2 Register"
|
|
in
|
|
hgroup.long (0xC+0x200)++0x03
|
|
hide.long 0x00 "BUFFER3,Buffer 3 Register"
|
|
in
|
|
hgroup.long (0x10+0x200)++0x03
|
|
hide.long 0x00 "BUFFER4,Buffer 4 Register"
|
|
in
|
|
hgroup.long (0x14+0x200)++0x03
|
|
hide.long 0x00 "BUFFER5,Buffer 5 Register"
|
|
in
|
|
hgroup.long (0x18+0x200)++0x03
|
|
hide.long 0x00 "BUFFER6,Buffer 6 Register"
|
|
in
|
|
hgroup.long (0x1C+0x200)++0x03
|
|
hide.long 0x00 "BUFFER7,Buffer 7 Register"
|
|
in
|
|
hgroup.long (0x20+0x200)++0x03
|
|
hide.long 0x00 "BUFFER8,Buffer 8 Register"
|
|
in
|
|
hgroup.long (0x24+0x200)++0x03
|
|
hide.long 0x00 "BUFFER9,Buffer 9 Register"
|
|
in
|
|
hgroup.long (0x28+0x200)++0x03
|
|
hide.long 0x00 "BUFFER10,Buffer 10 Register"
|
|
in
|
|
hgroup.long (0x2C+0x200)++0x03
|
|
hide.long 0x00 "BUFFER11,Buffer 11 Register"
|
|
in
|
|
hgroup.long (0x30+0x200)++0x03
|
|
hide.long 0x00 "BUFFER12,Buffer 12 Register"
|
|
in
|
|
hgroup.long (0x34+0x200)++0x03
|
|
hide.long 0x00 "BUFFER13,Buffer 13 Register"
|
|
in
|
|
hgroup.long (0x38+0x200)++0x03
|
|
hide.long 0x00 "BUFFER14,Buffer 14 Register"
|
|
in
|
|
hgroup.long (0x3C+0x200)++0x03
|
|
hide.long 0x00 "BUFFER15,Buffer 15 Register"
|
|
in
|
|
hgroup.long (0x40+0x200)++0x03
|
|
hide.long 0x00 "BUFFER16,Buffer 16 Register"
|
|
in
|
|
hgroup.long (0x44+0x200)++0x03
|
|
hide.long 0x00 "BUFFER17,Buffer 17 Register"
|
|
in
|
|
hgroup.long (0x48+0x200)++0x03
|
|
hide.long 0x00 "BUFFER18,Buffer 18 Register"
|
|
in
|
|
hgroup.long (0x4C+0x200)++0x03
|
|
hide.long 0x00 "BUFFER19,Buffer 19 Register"
|
|
in
|
|
hgroup.long (0x50+0x200)++0x03
|
|
hide.long 0x00 "BUFFER20,Buffer 20 Register"
|
|
in
|
|
hgroup.long (0x54+0x200)++0x03
|
|
hide.long 0x00 "BUFFER21,Buffer 21 Register"
|
|
in
|
|
hgroup.long (0x58+0x200)++0x03
|
|
hide.long 0x00 "BUFFER22,Buffer 22 Register"
|
|
in
|
|
hgroup.long (0x5C+0x200)++0x03
|
|
hide.long 0x00 "BUFFER23,Buffer 23 Register"
|
|
in
|
|
hgroup.long (0x60+0x200)++0x03
|
|
hide.long 0x00 "BUFFER24,Buffer 24 Register"
|
|
in
|
|
hgroup.long (0x64+0x200)++0x03
|
|
hide.long 0x00 "BUFFER25,Buffer 25 Register"
|
|
in
|
|
hgroup.long (0x68+0x200)++0x03
|
|
hide.long 0x00 "BUFFER26,Buffer 26 Register"
|
|
in
|
|
hgroup.long (0x6C+0x200)++0x03
|
|
hide.long 0x00 "BUFFER27,Buffer 27 Register"
|
|
in
|
|
hgroup.long (0x70+0x200)++0x03
|
|
hide.long 0x00 "BUFFER28,Buffer 28 Register"
|
|
in
|
|
hgroup.long (0x74+0x200)++0x03
|
|
hide.long 0x00 "BUFFER29,Buffer 29 Register"
|
|
in
|
|
hgroup.long (0x78+0x200)++0x03
|
|
hide.long 0x00 "BUFFER30,Buffer 30 Register"
|
|
in
|
|
hgroup.long (0x7C+0x200)++0x03
|
|
hide.long 0x00 "BUFFER31,Buffer 31 Register"
|
|
in
|
|
hgroup.long (0x80+0x200)++0x03
|
|
hide.long 0x00 "BUFFER32,Buffer 32 Register"
|
|
in
|
|
hgroup.long (0x84+0x200)++0x03
|
|
hide.long 0x00 "BUFFER33,Buffer 33 Register"
|
|
in
|
|
hgroup.long (0x88+0x200)++0x03
|
|
hide.long 0x00 "BUFFER34,Buffer 34 Register"
|
|
in
|
|
hgroup.long (0x8C+0x200)++0x03
|
|
hide.long 0x00 "BUFFER35,Buffer 35 Register"
|
|
in
|
|
hgroup.long (0x90+0x200)++0x03
|
|
hide.long 0x00 "BUFFER36,Buffer 36 Register"
|
|
in
|
|
hgroup.long (0x94+0x200)++0x03
|
|
hide.long 0x00 "BUFFER37,Buffer 37 Register"
|
|
in
|
|
hgroup.long (0x98+0x200)++0x03
|
|
hide.long 0x00 "BUFFER38,Buffer 38 Register"
|
|
in
|
|
hgroup.long (0x9C+0x200)++0x03
|
|
hide.long 0x00 "BUFFER39,Buffer 39 Register"
|
|
in
|
|
hgroup.long (0xA0+0x200)++0x03
|
|
hide.long 0x00 "BUFFER40,Buffer 40 Register"
|
|
in
|
|
hgroup.long (0xA4+0x200)++0x03
|
|
hide.long 0x00 "BUFFER41,Buffer 41 Register"
|
|
in
|
|
hgroup.long (0xA8+0x200)++0x03
|
|
hide.long 0x00 "BUFFER42,Buffer 42 Register"
|
|
in
|
|
hgroup.long (0xAC+0x200)++0x03
|
|
hide.long 0x00 "BUFFER43,Buffer 43 Register"
|
|
in
|
|
hgroup.long (0xB0+0x200)++0x03
|
|
hide.long 0x00 "BUFFER44,Buffer 44 Register"
|
|
in
|
|
hgroup.long (0xB4+0x200)++0x03
|
|
hide.long 0x00 "BUFFER45,Buffer 45 Register"
|
|
in
|
|
hgroup.long (0xB8+0x200)++0x03
|
|
hide.long 0x00 "BUFFER46,Buffer 46 Register"
|
|
in
|
|
hgroup.long (0xBC+0x200)++0x03
|
|
hide.long 0x00 "BUFFER47,Buffer 47 Register"
|
|
in
|
|
hgroup.long (0xC0+0x200)++0x03
|
|
hide.long 0x00 "BUFFER48,Buffer 48 Register"
|
|
in
|
|
hgroup.long (0xC4+0x200)++0x03
|
|
hide.long 0x00 "BUFFER49,Buffer 49 Register"
|
|
in
|
|
hgroup.long (0xC8+0x200)++0x03
|
|
hide.long 0x00 "BUFFER50,Buffer 50 Register"
|
|
in
|
|
hgroup.long (0xCC+0x200)++0x03
|
|
hide.long 0x00 "BUFFER51,Buffer 51 Register"
|
|
in
|
|
hgroup.long (0xD0+0x200)++0x03
|
|
hide.long 0x00 "BUFFER52,Buffer 52 Register"
|
|
in
|
|
hgroup.long (0xD4+0x200)++0x03
|
|
hide.long 0x00 "BUFFER53,Buffer 53 Register"
|
|
in
|
|
hgroup.long (0xD8+0x200)++0x03
|
|
hide.long 0x00 "BUFFER54,Buffer 54 Register"
|
|
in
|
|
hgroup.long (0xDC+0x200)++0x03
|
|
hide.long 0x00 "BUFFER55,Buffer 55 Register"
|
|
in
|
|
hgroup.long (0xE0+0x200)++0x03
|
|
hide.long 0x00 "BUFFER56,Buffer 56 Register"
|
|
in
|
|
hgroup.long (0xE4+0x200)++0x03
|
|
hide.long 0x00 "BUFFER57,Buffer 57 Register"
|
|
in
|
|
hgroup.long (0xE8+0x200)++0x03
|
|
hide.long 0x00 "BUFFER58,Buffer 58 Register"
|
|
in
|
|
hgroup.long (0xEC+0x200)++0x03
|
|
hide.long 0x00 "BUFFER59,Buffer 59 Register"
|
|
in
|
|
hgroup.long (0xF0+0x200)++0x03
|
|
hide.long 0x00 "BUFFER60,Buffer 60 Register"
|
|
in
|
|
hgroup.long (0xF4+0x200)++0x03
|
|
hide.long 0x00 "BUFFER61,Buffer 61 Register"
|
|
in
|
|
hgroup.long (0xF8+0x200)++0x03
|
|
hide.long 0x00 "BUFFER62,Buffer 62 Register"
|
|
in
|
|
hgroup.long (0xFC+0x200)++0x03
|
|
hide.long 0x00 "BUFFER63,Buffer 63 Register"
|
|
in
|
|
hgroup.long (0x100+0x200)++0x03
|
|
hide.long 0x00 "BUFFER64,Buffer 64 Register"
|
|
in
|
|
hgroup.long (0x104+0x200)++0x03
|
|
hide.long 0x00 "BUFFER65,Buffer 65 Register"
|
|
in
|
|
hgroup.long (0x108+0x200)++0x03
|
|
hide.long 0x00 "BUFFER66,Buffer 66 Register"
|
|
in
|
|
hgroup.long (0x10C+0x200)++0x03
|
|
hide.long 0x00 "BUFFER67,Buffer 67 Register"
|
|
in
|
|
hgroup.long (0x110+0x200)++0x03
|
|
hide.long 0x00 "BUFFER68,Buffer 68 Register"
|
|
in
|
|
hgroup.long (0x114+0x200)++0x03
|
|
hide.long 0x00 "BUFFER69,Buffer 69 Register"
|
|
in
|
|
hgroup.long (0x118+0x200)++0x03
|
|
hide.long 0x00 "BUFFER70,Buffer 70 Register"
|
|
in
|
|
hgroup.long (0x11C+0x200)++0x03
|
|
hide.long 0x00 "BUFFER71,Buffer 71 Register"
|
|
in
|
|
hgroup.long (0x120+0x200)++0x03
|
|
hide.long 0x00 "BUFFER72,Buffer 72 Register"
|
|
in
|
|
hgroup.long (0x124+0x200)++0x03
|
|
hide.long 0x00 "BUFFER73,Buffer 73 Register"
|
|
in
|
|
hgroup.long (0x128+0x200)++0x03
|
|
hide.long 0x00 "BUFFER74,Buffer 74 Register"
|
|
in
|
|
hgroup.long (0x12C+0x200)++0x03
|
|
hide.long 0x00 "BUFFER75,Buffer 75 Register"
|
|
in
|
|
hgroup.long (0x130+0x200)++0x03
|
|
hide.long 0x00 "BUFFER76,Buffer 76 Register"
|
|
in
|
|
hgroup.long (0x134+0x200)++0x03
|
|
hide.long 0x00 "BUFFER77,Buffer 77 Register"
|
|
in
|
|
hgroup.long (0x138+0x200)++0x03
|
|
hide.long 0x00 "BUFFER78,Buffer 78 Register"
|
|
in
|
|
hgroup.long (0x13C+0x200)++0x03
|
|
hide.long 0x00 "BUFFER79,Buffer 79 Register"
|
|
in
|
|
hgroup.long (0x140+0x200)++0x03
|
|
hide.long 0x00 "BUFFER80,Buffer 80 Register"
|
|
in
|
|
hgroup.long (0x144+0x200)++0x03
|
|
hide.long 0x00 "BUFFER81,Buffer 81 Register"
|
|
in
|
|
hgroup.long (0x148+0x200)++0x03
|
|
hide.long 0x00 "BUFFER82,Buffer 82 Register"
|
|
in
|
|
hgroup.long (0x14C+0x200)++0x03
|
|
hide.long 0x00 "BUFFER83,Buffer 83 Register"
|
|
in
|
|
hgroup.long (0x150+0x200)++0x03
|
|
hide.long 0x00 "BUFFER84,Buffer 84 Register"
|
|
in
|
|
hgroup.long (0x154+0x200)++0x03
|
|
hide.long 0x00 "BUFFER85,Buffer 85 Register"
|
|
in
|
|
hgroup.long (0x158+0x200)++0x03
|
|
hide.long 0x00 "BUFFER86,Buffer 86 Register"
|
|
in
|
|
hgroup.long (0x15C+0x200)++0x03
|
|
hide.long 0x00 "BUFFER87,Buffer 87 Register"
|
|
in
|
|
hgroup.long (0x160+0x200)++0x03
|
|
hide.long 0x00 "BUFFER88,Buffer 88 Register"
|
|
in
|
|
hgroup.long (0x164+0x200)++0x03
|
|
hide.long 0x00 "BUFFER89,Buffer 89 Register"
|
|
in
|
|
hgroup.long (0x168+0x200)++0x03
|
|
hide.long 0x00 "BUFFER90,Buffer 90 Register"
|
|
in
|
|
hgroup.long (0x16C+0x200)++0x03
|
|
hide.long 0x00 "BUFFER91,Buffer 91 Register"
|
|
in
|
|
hgroup.long (0x170+0x200)++0x03
|
|
hide.long 0x00 "BUFFER92,Buffer 92 Register"
|
|
in
|
|
hgroup.long (0x174+0x200)++0x03
|
|
hide.long 0x00 "BUFFER93,Buffer 93 Register"
|
|
in
|
|
hgroup.long (0x178+0x200)++0x03
|
|
hide.long 0x00 "BUFFER94,Buffer 94 Register"
|
|
in
|
|
hgroup.long (0x17C+0x200)++0x03
|
|
hide.long 0x00 "BUFFER95,Buffer 95 Register"
|
|
in
|
|
hgroup.long (0x180+0x200)++0x03
|
|
hide.long 0x00 "BUFFER96,Buffer 96 Register"
|
|
in
|
|
hgroup.long (0x184+0x200)++0x03
|
|
hide.long 0x00 "BUFFER97,Buffer 97 Register"
|
|
in
|
|
hgroup.long (0x188+0x200)++0x03
|
|
hide.long 0x00 "BUFFER98,Buffer 98 Register"
|
|
in
|
|
hgroup.long (0x18C+0x200)++0x03
|
|
hide.long 0x00 "BUFFER99,Buffer 99 Register"
|
|
in
|
|
hgroup.long (0x190+0x200)++0x03
|
|
hide.long 0x00 "BUFFER100,Buffer 100 Register"
|
|
in
|
|
hgroup.long (0x194+0x200)++0x03
|
|
hide.long 0x00 "BUFFER101,Buffer 101 Register"
|
|
in
|
|
hgroup.long (0x198+0x200)++0x03
|
|
hide.long 0x00 "BUFFER102,Buffer 102 Register"
|
|
in
|
|
hgroup.long (0x19C+0x200)++0x03
|
|
hide.long 0x00 "BUFFER103,Buffer 103 Register"
|
|
in
|
|
hgroup.long (0x1A0+0x200)++0x03
|
|
hide.long 0x00 "BUFFER104,Buffer 104 Register"
|
|
in
|
|
hgroup.long (0x1A4+0x200)++0x03
|
|
hide.long 0x00 "BUFFER105,Buffer 105 Register"
|
|
in
|
|
hgroup.long (0x1A8+0x200)++0x03
|
|
hide.long 0x00 "BUFFER106,Buffer 106 Register"
|
|
in
|
|
hgroup.long (0x1AC+0x200)++0x03
|
|
hide.long 0x00 "BUFFER107,Buffer 107 Register"
|
|
in
|
|
hgroup.long (0x1B0+0x200)++0x03
|
|
hide.long 0x00 "BUFFER108,Buffer 108 Register"
|
|
in
|
|
hgroup.long (0x1B4+0x200)++0x03
|
|
hide.long 0x00 "BUFFER109,Buffer 109 Register"
|
|
in
|
|
hgroup.long (0x1B8+0x200)++0x03
|
|
hide.long 0x00 "BUFFER110,Buffer 110 Register"
|
|
in
|
|
hgroup.long (0x1BC+0x200)++0x03
|
|
hide.long 0x00 "BUFFER111,Buffer 111 Register"
|
|
in
|
|
hgroup.long (0x1C0+0x200)++0x03
|
|
hide.long 0x00 "BUFFER112,Buffer 112 Register"
|
|
in
|
|
hgroup.long (0x1C4+0x200)++0x03
|
|
hide.long 0x00 "BUFFER113,Buffer 113 Register"
|
|
in
|
|
hgroup.long (0x1C8+0x200)++0x03
|
|
hide.long 0x00 "BUFFER114,Buffer 114 Register"
|
|
in
|
|
hgroup.long (0x1CC+0x200)++0x03
|
|
hide.long 0x00 "BUFFER115,Buffer 115 Register"
|
|
in
|
|
hgroup.long (0x1D0+0x200)++0x03
|
|
hide.long 0x00 "BUFFER116,Buffer 116 Register"
|
|
in
|
|
hgroup.long (0x1D4+0x200)++0x03
|
|
hide.long 0x00 "BUFFER117,Buffer 117 Register"
|
|
in
|
|
hgroup.long (0x1D8+0x200)++0x03
|
|
hide.long 0x00 "BUFFER118,Buffer 118 Register"
|
|
in
|
|
hgroup.long (0x1DC+0x200)++0x03
|
|
hide.long 0x00 "BUFFER119,Buffer 119 Register"
|
|
in
|
|
hgroup.long (0x1E0+0x200)++0x03
|
|
hide.long 0x00 "BUFFER120,Buffer 120 Register"
|
|
in
|
|
hgroup.long (0x1E4+0x200)++0x03
|
|
hide.long 0x00 "BUFFER121,Buffer 121 Register"
|
|
in
|
|
hgroup.long (0x1E8+0x200)++0x03
|
|
hide.long 0x00 "BUFFER122,Buffer 122 Register"
|
|
in
|
|
hgroup.long (0x1EC+0x200)++0x03
|
|
hide.long 0x00 "BUFFER123,Buffer 123 Register"
|
|
in
|
|
hgroup.long (0x1F0+0x200)++0x03
|
|
hide.long 0x00 "BUFFER124,Buffer 124 Register"
|
|
in
|
|
hgroup.long (0x1F4+0x200)++0x03
|
|
hide.long 0x00 "BUFFER125,Buffer 125 Register"
|
|
in
|
|
hgroup.long (0x1F8+0x200)++0x03
|
|
hide.long 0x00 "BUFFER126,Buffer 126 Register"
|
|
in
|
|
hgroup.long (0x1FC+0x200)++0x03
|
|
hide.long 0x00 "BUFFER127,Buffer 127 Register"
|
|
in
|
|
tree.end
|
|
endif
|
|
sif cpuis("TMS570LS0232")||cpuis("TMS570LS0714*")||cpuis("TMS570LS0914*")
|
|
endian.le
|
|
endif
|
|
width 0xB
|
|
tree.end
|
|
tree.end
|
|
endif
|
|
sif cpuis("TMS570LS0714*")||cpuis("TMS570LS0914*")
|
|
tree.open "SCI/LIN (Serial Communications Interface/Local Interconnect Network Module)"
|
|
tree "SCI/LIN"
|
|
base ad:0xFFF7E400
|
|
width 19.
|
|
endian.be
|
|
group.long 0x00++0x3
|
|
line.long 0x0 "SCIGCR0,SCI Global Control Register 0"
|
|
bitfld.long 0x00 0. " RESET ,SCI Module Reset" "Under reset,Out of reset"
|
|
if ((per.l.be(ad:0xFFF7E400+0x4)&0x40)==0x40)
|
|
group.long 0x04++0x03
|
|
line.long 0x0 "SCIGCR1,SCI Global Control Register 1"
|
|
bitfld.long 0x00 25. " TXENA ,SCI Transmitter Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " RXENA ,SCI Receiver Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " CONT ,Continue on Suspend" "Frozen,Continued"
|
|
bitfld.long 0x00 16. " LOOP_BACK ,LOOP BACK Enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 13. " STOP_EXT_FRAME ,Stop Extended Frame Communication" "Not stopped,Stopped"
|
|
bitfld.long 0x00 12. " HGEN_CTRL ,LIN Mode Bit (Type of Mask Filtering Comparison)" "ID-Byte,ID-Slave task byte"
|
|
bitfld.long 0x00 11. " CTYPE ,LIN Mode Bit (Classic/Enhanced)" "Classic,Enhanced"
|
|
newline
|
|
bitfld.long 0x00 10. " MBUF_MODE ,Receive/Transmit Buffer Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " ADAPT ,LIN Mode Bit (Automatic Baudrate Adjustment)" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " SWNRESET ,Software Reset" "Reset,Ready"
|
|
newline
|
|
bitfld.long 0x00 6. " LIN_MODE ,Mode select" "SCI mode,LIN mode"
|
|
bitfld.long 0x00 5. " CLOCK ,SCI internal clock enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " PARITY_ENA ,ID-Parity Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " COMM_MODE ,SCI/LIN Communication Mode Bit ID4 and ID5 Use" "Not used,Used"
|
|
elif (((per.l.be((ad:0xFFF7E400+0x4)))&0x44)==0x04)
|
|
group.long 0x04++0x03
|
|
line.long 0x0 "SCIGCR1,SCI Global Control Register 1"
|
|
bitfld.long 0x00 25. " TXENA ,SCI Transmitter Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " RXENA ,SCI Receiver Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " CONT ,Continue on Suspend" "Frozen,Continued"
|
|
bitfld.long 0x00 16. " LOOP_BACK ,LOOP BACK Enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 10. " MBUF_MODE ,Receive/Transmit Buffer Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " SLEEP ,SCI Sleep Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " SWNRESET ,Software Reset" "Reset,Ready"
|
|
newline
|
|
newline
|
|
bitfld.long 0x00 6. " LIN_MODE ,Mode select" "SCI mode,LIN mode"
|
|
bitfld.long 0x00 5. " CLOCK ,SCI internal clock enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " STOP ,SCI Number of Stop Bits" "1 bit,2 bits"
|
|
bitfld.long 0x00 3. " PARITY ,SCI Parity Odd/Even Selection" "Odd,Even"
|
|
newline
|
|
bitfld.long 0x00 2. " PARITY_ENA ,Parity Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " TIMING_MODE ,SCI Timing Mode Bit" "Synchronous,Asynchronous"
|
|
bitfld.long 0x00 0. " COMM_MODE ,SCI/LIN Communication Mode Bit" "Idle-line,Address-bit"
|
|
elif (((per.l.be((ad:0xFFF7E400+0x4)))&0x44)==0x00)
|
|
group.long 0x04++0x03
|
|
line.long 0x0 "SCIGCR1,SCI Global Control Register 1"
|
|
bitfld.long 0x00 25. " TXENA ,SCI Transmitter Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " RXENA ,SCI Receiver Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " CONT ,Continue on Suspend" "Frozen,Continued"
|
|
newline
|
|
bitfld.long 0x00 16. " LOOP_BACK ,LOOP BACK Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " MBUF_MODE ,Receive/Transmit Buffer Enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 8. " SLEEP ,SCI Sleep Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " SWNRESET ,Software Reset" "Reset,Ready"
|
|
newline
|
|
bitfld.long 0x00 6. " LIN_MODE ,Mode select" "SCI mode,LIN mode"
|
|
bitfld.long 0x00 5. " CLOCK ,SCI internal clock enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " STOP ,SCI Number of Stop Bits" "1 bit,2 bits"
|
|
newline
|
|
bitfld.long 0x00 2. " PARITY_ENA ,Parity Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " TIMING_MODE ,SCI Timing Mode Bit" "Synchronous,Asynchronous"
|
|
bitfld.long 0x00 0. " COMM_MODE ,SCI/LIN Communication Mode Bit" "Idle-line,Address-bit"
|
|
endif
|
|
if ((per.l.be(ad:0xFFF7E400+0x4)&0x40)==0x40)
|
|
group.long 0x08++0x03
|
|
line.long 0x0 "SCIGCR2,SCI Global Control Register 2"
|
|
bitfld.long 0x00 17. " CC ,Compare Checksum" "No effect,Compared"
|
|
bitfld.long 0x00 16. " SC ,Send Checksum" "Not sent,Sent"
|
|
bitfld.long 0x00 8. " GEN_WU ,Generate Wakeup Signal" "No effect,Generated"
|
|
bitfld.long 0x00 0. " POWERDOWN ,POWERDOWN" "Normal,Local low-power"
|
|
else
|
|
group.long 0x08++0x03
|
|
line.long 0x0 "SCIGCR2,SCI Global Control Register 2"
|
|
rbitfld.long 0x00 17. " CC ,Compare Checksum" "No effect,Compared"
|
|
rbitfld.long 0x00 16. " SC ,Send Checksum" "Not sent,Sent"
|
|
bitfld.long 0x00 0. " POWERDOWN ,POWERDOWN" "Normal,Local low-power"
|
|
endif
|
|
newline
|
|
if ((per.l.be(ad:0xFFF7E400+0x4)&0x40)==0x40)
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "SCIINT_SET/CLR,SCI Set/Clear Interrupt Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x04 31. " BE_INT ,Bit Error Interrupt" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x04 30. " PBE_INT ,Physical Bus Error Interrupt" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x04 29. " CE_INT ,Checksum-Error Interrupt" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 28. 0x00 28. 0x04 28. " ISFE_INT ,Inconsistent-Synch-Field-Error Interrupt" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x04 27. " NRE_INT ,No-Response-Error Interrupt" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x04 26. " FE_INT ,Framing-Error Interrupt" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 25. 0x00 25. 0x04 25. " OE_INT ,Overrun-Error Interrupt" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x04 24. " PE_INT ,Parity Interrupt" "Disabled,Enabled"
|
|
newline
|
|
sif !cpuis("TMS570LS0232")
|
|
setclrfld.long 0x00 17. 0x00 17. 0x04 17. " RX_DMA ,Receive DMA" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x04 16. " TX_DMA ,Transmit DMA" "Disabled,Enabled"
|
|
newline
|
|
endif
|
|
setclrfld.long 0x00 13. 0x00 13. 0x04 13. " ID_INT ,ID Interrupt" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x04 9. " RX_INT ,Receiver Interrupt Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x04 8. " TX_INT ,Transmitter Interrupt" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 7. 0x00 7. 0x04 7. " TOA3WUS_INT ,Timeout After 3 Wakeup Signals Interrupt" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x04 6. " TOAWUS_INT ,Timeout After Wakeup Signal Interrupt" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 4. 0x00 4. 0x04 4. " TIMEOUT_INT ,Timeout Interrupt" "Disabled,Enabled"
|
|
setclrfld.long 0x00 1. 0x00 1. 0x04 1. " WAKEUP_INT ,Wake-up Interrupt" "Disabled,Enabled"
|
|
else
|
|
group.long 0x0C++0x03
|
|
line.long 0x0 "SCIINT_SET/CLR,SCI Set/Clear Interrupt Register"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x04 26. " FE_INT ,Framing-Error Interrupt" "Disabled,Enabled"
|
|
setclrfld.long 0x00 25. 0x00 25. 0x04 25. " OE_INT ,Overrun-Error Interrupt" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x04 24. " PE_INT ,Parity Interrupt" "Disabled,Enabled"
|
|
newline
|
|
sif !cpuis("TMS570LS0232")
|
|
setclrfld.long 0x00 18. 0x00 18. 0x04 18. " RX_DMA_ALL ,Receive DMA All" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x04 17. " RX_DMA ,Receive DMA" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x04 16. " TX_DMA ,Transmit DMA" "Disabled,Enabled"
|
|
newline
|
|
endif
|
|
setclrfld.long 0x00 9. 0x00 9. 0x04 9. " RX_INT ,Receiver Interrupt Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x04 8. " TX_INT ,Transmitter Interrupt" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 1. 0x00 1. 0x04 1. " WAKEUP_INT ,Wake-up Interrupt" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x04 0. " BRKDT_INT ,Break-detect Interrupt" "Disabled,Enabled"
|
|
endif
|
|
if ((per.l.be(ad:0xFFF7E400+0x4)&0x40)==0x40)
|
|
group.long 0x14++0x03
|
|
line.long 0x0 "SCIINTLVL_SET/CLR,SCI Set/Clear Interrupt Level Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x04 31. " BE_INT_LVL ,Bit Error Interrupt Level" "INT0,INT1"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x04 30. " PBE_INT_LVL ,Physical Bus Error Interrupt Level" "INT0,INT1"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x04 29. " CE_INT_LVL ,Checksum-Error Interrupt Level" "INT0,INT1"
|
|
newline
|
|
setclrfld.long 0x00 28. 0x00 28. 0x04 28. " ISFE_INT_LVL ,Inconsistent-Synch-Field-Error Interrupt Level" "INT0,INT1"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x04 27. " NRE_INT_LVL ,No-Response-Error Interrupt Level" "INT0,INT1"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x04 26. " FE_INT_LVL ,Framing-Error Interrupt Level" "INT0,INT1"
|
|
newline
|
|
setclrfld.long 0x00 25. 0x00 25. 0x04 25. " OE_INT_LVL ,Overrun-Error Interrupt Level" "INT0,INT1"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x04 24. " PE_INT_LVL ,Parity Error Interrupt Level" "INT0,INT1"
|
|
setclrfld.long 0x00 13. 0x00 13. 0x04 13. " ID_INT_LVL ,ID Interrupt Level" "INT0,INT1"
|
|
newline
|
|
setclrfld.long 0x00 9. 0x00 9. 0x04 9. " RX_INT_LVL ,Receiver Interrupt Level" "INT0,INT1"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x04 8. " TX_INT_LVL ,Transmitter Interrupt Level" "INT0,INT1"
|
|
setclrfld.long 0x00 7. 0x00 7. 0x04 7. " TOA3WUS_INT_LVL ,Timeout After 3 Wakeup Signals Interrupt" "INT0,INT1"
|
|
newline
|
|
setclrfld.long 0x00 6. 0x00 6. 0x04 6. " TOAWUS_INT_LVL ,Timeout After Wakeup Signal Interrupt Level" "INT0,INT1"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x04 4. " TIMEOUT_INT_LVL ,Timeout Interrupt Level" "INT0,INT1"
|
|
setclrfld.long 0x00 1. 0x00 1. 0x04 1. " WAKEUP_INT_LVL ,Wake-up Interrupt Level" "INT0,INT1"
|
|
else
|
|
group.long 0x14++0x3
|
|
line.long 0x0 "SCIINTLVL_SET/CLR,SCI Set/Clear Interrupt Level Register"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x04 26. " FE_INT_LVL ,Framing-Error Interrupt Level" "INT0,INT1"
|
|
setclrfld.long 0x00 25. 0x00 25. 0x04 25. " OE_INT_LVL ,Overrun-Error Interrupt Level" "INT0,INT1"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x04 24. " PE_INT_LVL ,Parity Error Interrupt Level" "INT0,INT1"
|
|
newline
|
|
setclrfld.long 0x00 18. 0x00 18. 0x04 18. " RX_DMA_ALL_INT_LVL ,Receive DMA All Interrupt Level" "INT0,INT1"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x04 9. " RX_INT_LVL ,Receiver Interrupt Level" "INT0,INT1"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x04 8. " TX_INT_LVL ,Transmitter Interrupt Level" "INT0,INT1"
|
|
newline
|
|
setclrfld.long 0x00 1. 0x00 1. 0x04 1. " WAKEUP_INT_LVL ,Wake-up Interrupt Level" "INT0,INT1"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x04 0. " BRKDT_INT ,Break-Detect Interrupt Level" "INT0,INT1"
|
|
endif
|
|
newline
|
|
if ((per.l.be(ad:0xFFF7E400+0x4)&0x40)==0x40)
|
|
group.long 0x1C++0x3
|
|
line.long 0x0 "SCIFLR,SCI Flags Register"
|
|
eventfld.long 0x00 31. " BE ,Bit Error Flag" "Not detected,Detected"
|
|
eventfld.long 0x00 30. " PBE ,Physical Bus Error Flag" "Not detected,Detected"
|
|
eventfld.long 0x00 29. " CE ,Checksum Error Flag" "Not detected,Detected"
|
|
eventfld.long 0x00 28. " ISFE ,Inconsistent Synch Field Error Flag" "Not detected,Detected"
|
|
newline
|
|
eventfld.long 0x00 27. " NRE ,No-Response Error Flag" "Not detected,Detected"
|
|
eventfld.long 0x00 26. " FE ,Framing Error Flag" "Not detected,Detected"
|
|
eventfld.long 0x00 25. " OE ,Overrun Error Flag" "Not detected,Detected"
|
|
eventfld.long 0x00 24. " PE ,Parity Error Flag" "Not detected,Detected"
|
|
newline
|
|
eventfld.long 0x00 14. " ID_RX_FLAG ,Identifier On Receive Flag" "Not received,Received"
|
|
eventfld.long 0x00 13. " ID_TX_FLAG ,Identifier On Transmit Flag" "Not received,Received"
|
|
bitfld.long 0x00 11. " TX_EMPTY ,Transmitter Empty Flag" "Not empty,Empty"
|
|
eventfld.long 0x00 9. " RXRDY ,Receiver Ready Flag" "Not ready,Ready"
|
|
newline
|
|
bitfld.long 0x00 8. " TXRDY ,Transmitter Buffer Register Ready Flag" "Full,Ready"
|
|
eventfld.long 0x00 7. " TOA3WUS ,Timeout After 3 Wakeup Signals Flag" "No timeout,Timeout"
|
|
eventfld.long 0x00 6. " TOAWUS ,Timeout After Wakeup Signal Flag" "No timeout,Timeout"
|
|
newline
|
|
eventfld.long 0x00 4. " TIMEOUT ,LIN Bus IDLE Timeout Flag" "Not detected,Detected"
|
|
bitfld.long 0x00 3. " BUSY_FLAG ,BUSY Flag" "Not busy,Busy"
|
|
eventfld.long 0x00 1. " WAKEUP ,Wake-up Flag" "No wake up,Wake up"
|
|
else
|
|
group.long 0x1C++0x3
|
|
line.long 0x0 "SCIFLR,SCI Flags Register"
|
|
eventfld.long 0x00 26. " FE ,Framing Error Flag" "Not detected,Detected"
|
|
eventfld.long 0x00 25. " OE ,Overrun Error Flag" "Not detected,Detected"
|
|
eventfld.long 0x00 24. " PE ,Parity Error Flag" "Not detected,Detected"
|
|
bitfld.long 0x00 12. " RXWAKE ,Receiver Wakeup Detect Flag" "Not address,Address"
|
|
newline
|
|
bitfld.long 0x00 11. " TX_EMPTY ,Transmitter Empty Flag" "Not empty,Empty"
|
|
bitfld.long 0x00 10. " TXWAKE ,SCI Transmitter Wakeup Method Select" "Data,Address"
|
|
eventfld.long 0x00 9. " RXRDY ,Receiver Ready Flag" "Not ready,Ready"
|
|
bitfld.long 0x00 8. " TXRDY ,Transmitter Buffer Register Ready Flag (SCITD)" "Full,Ready"
|
|
newline
|
|
bitfld.long 0x00 3. " BUSY_FLAG ,BUSY Flag" "Not busy,Busy"
|
|
rbitfld.long 0x00 2. " IDLE ,SCI Receiver in Idle State" "Not detected,Detected"
|
|
eventfld.long 0x00 1. " WAKEUP ,Wake-up Flag" "No wake up,Wake up"
|
|
eventfld.long 0x00 0. " BRKDT ,SCI Break-Detect Flag" "Not detected,Detected"
|
|
endif
|
|
hgroup.long 0x20++0x3
|
|
hide.long 0x0 "SCIINVECT0,SCI Interrupt Vector Offset 0"
|
|
in
|
|
hgroup.long 0x24++0x3
|
|
hide.long 0x0 "SCIINVECT1,SCI Interrupt Vector Offset 1"
|
|
in
|
|
if ((per.l.be(ad:0xFFF7E400+0x4)&0x40)==0x40)
|
|
group.long 0x28++0x3
|
|
line.long 0x0 "SCIFORMAT,SCI Format Control Register"
|
|
bitfld.long 0x00 16.--18. " LENGTH ,Frame Length Control Bits" "1 byte,2 bytes,3 bytes,4 bytes,5 bytes,6 bytes,7 bytes,8 bytes"
|
|
elif (((per.l.be(ad:0xFFF7E400+0x4)&0x440)==0x400))
|
|
group.long 0x28++0x3
|
|
line.long 0x0 "SCIFORMAT,SCI Format Control Register"
|
|
bitfld.long 0x00 16.--18. " LENGTH ,Frame Length Control Bits" "1 character,2 characters,3 characters,4 characters,5 characters,6 characters,7 characters,8 characters"
|
|
bitfld.long 0x00 0.--2. " CHAR ,Character Length Control Bits" "1 bit,2 bits,3 bits,4 bits,5 bits,6 bits,7 bits,8 bits"
|
|
else
|
|
group.long 0x28++0x3
|
|
line.long 0x0 "SCIFORMAT,SCI Format Control Register"
|
|
bitfld.long 0x00 0.--2. " CHAR ,Character Length Control Bits" "1 bit,2 bits,3 bits,4 bits,5 bits,6 bits,7 bits,8 bits"
|
|
endif
|
|
group.long 0x2C++0x3
|
|
line.long 0x0 "BRS,Baud Rate Selection Register"
|
|
bitfld.long 0x00 28.--30. " U ,SCI/BLIN Super Fractional Divider Selection" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 24.--27. " M ,SCI/BLIN 4-bit Fractional Divider Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " PRESCALER_P ,SCI/BLIN 24-bit Integer Prescaler Selection"
|
|
rgroup.long 0x30++0x3
|
|
line.long 0x0 "SCIED,SCI Data Buffer Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " ED ,Emulation Data"
|
|
hgroup.long 0x34++0x3
|
|
hide.long 0x0 "SCIRD,SCI Data Buffer Register"
|
|
in
|
|
group.long 0x38++0x3
|
|
line.long 0x0 "SCITD,SCI Data Buffer Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " TD ,Transmit Data"
|
|
tree "SCI Pin I/O Control Registers"
|
|
group.long 0x3C++0x07
|
|
line.long 0x0 "SCIPIO0,SCI Pin I/O Control Register 0"
|
|
bitfld.long 0x00 2. " TX_FUNC ,Defines the Function of Pin SCITX" "GPIO,SCI/LIN TX"
|
|
bitfld.long 0x00 1. " RX_FUNC ,Defines the Function of Pin SCIRX" "GPIO,SCI/LIN RX"
|
|
line.long 0x04 "SCIPIO1,SCI Pin I/O Control Register 1"
|
|
bitfld.long 0x04 2. " TX_DIR ,Transmit Direction" "Input,Output"
|
|
bitfld.long 0x04 1. " RX_DIR ,Receive Direction" "Input,Output"
|
|
rgroup.long 0x44++0x03
|
|
line.long 0x00 "SCIPIO2,SCI Pin I/O Control Register 2"
|
|
bitfld.long 0x00 2. " TX_IN ,Contains Current Value on the SCITX Pin" "Low,High"
|
|
bitfld.long 0x00 1. " RX_IN ,Contains Current Value on the SCIRX Pin" "Low,High"
|
|
group.long 0x48++0x03
|
|
line.long 0x00 "SCIPIO3-5_SET/CLR,SCI Pin I/O Control Set/Clear Register 3-5"
|
|
setclrfld.long 0x00 2. 0x04 2. 0x08 2. " TX_OUT ,SCITX Pin Data Output" "Low,High"
|
|
setclrfld.long 0x00 1. 0x04 1. 0x08 1. " RX_OUT ,SCIRX Pin Data Output" "Low,High"
|
|
group.long 0x54++0x0B
|
|
line.long 0x00 "SCIPIO6,SCI Pin I/O Control Register 6"
|
|
bitfld.long 0x00 2. " TX_PDR ,TX Open Drain Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " RX_PDR ,RX Open Drain Enable" "Disabled,Enabled"
|
|
line.long 0x04 "SCIPIO7,SCI Pin I/O Control Register 7"
|
|
bitfld.long 0x04 2. " TX_PD ,TX Pin Pull Control Disable" "Enabled,Disabled"
|
|
bitfld.long 0x04 1. " RX_PD ,RX Pin Pull Control Disable" "Enabled,Disabled"
|
|
line.long 0x08 "SCIPIO8,SCI Pin I/O Control Register 8"
|
|
bitfld.long 0x08 2. " TX_PSL ,TX Pin Pull Select" "Pull down,Pull up"
|
|
bitfld.long 0x08 1. " RX_PSL ,RX Pin Pull Select" "Pull down,Pull up"
|
|
tree.end
|
|
tree "LIN Registers"
|
|
if ((per.l.be(ad:0xFFF7E400+0x4)&0x40)==0x40)
|
|
group.long 0x60++0x3
|
|
line.long 0x0 "LINCOMP,BLINCOMPARE Register"
|
|
bitfld.long 0x00 8.--9. " SDEL ,2-bit Synch Delimiter Compare" "1 bit,2 bits,3 bits,4 bits"
|
|
bitfld.long 0x00 0.--2. " SBREAK ,3-bit Synch Break Extend" "Not extended,1 bit,2 bits,3 bits,4 bits,5 bits,6 bits,7 bits"
|
|
else
|
|
hgroup.long 0x60++0x3
|
|
hide.long 0x0 "LINCOMP,BLINCOMPARE Register"
|
|
endif
|
|
hgroup.long 0x64++0x3
|
|
hide.long 0x0 "LINRD0,LIN Receive Buffer 0 Register"
|
|
in
|
|
rgroup.long 0x68++0x3
|
|
line.long 0x0 "LINRD1,LIN Receive Buffer 1 Register"
|
|
hexmask.long.byte 0x00 24.--31. 0x01 " RD4 ,Receive Buffer 4"
|
|
hexmask.long.byte 0x00 16.--23. 0x01 " RD5 ,Receive Buffer 5"
|
|
hexmask.long.byte 0x00 8.--15. 0x01 " RD6 ,Receive Buffer 6"
|
|
hexmask.long.byte 0x00 0.--7. 0x01 " RD7 ,Receive Buffer 7"
|
|
newline
|
|
if ((per.l.be(ad:0xFFF7E400+0x4)&0x40)==0x40)
|
|
group.long 0x6C++0x3
|
|
line.long 0x0 "LINMASK,LIN Mask Register"
|
|
bitfld.long 0x00 23. " RX_ID_MASK7 ,RX ID Mask 7" "Not masked,Masked"
|
|
bitfld.long 0x00 22. " RX_ID_MASK6 ,RX ID Mask 6" "Not masked,Masked"
|
|
bitfld.long 0x00 21. " RX_ID_MASK5 ,RX ID Mask 5" "Not masked,Masked"
|
|
newline
|
|
bitfld.long 0x00 20. " RX_ID_MASK4 ,RX ID Mask 4" "Not masked,Masked"
|
|
bitfld.long 0x00 19. " RX_ID_MASK3 ,RX ID Mask 3" "Not masked,Masked"
|
|
bitfld.long 0x00 18. " RX_ID_MASK2 ,RX ID Mask 2" "Not masked,Masked"
|
|
newline
|
|
bitfld.long 0x00 17. " RX_ID_MASK1 ,RX ID Mask 1" "Not masked,Masked"
|
|
bitfld.long 0x00 16. " RX_ID_MASK0 ,RX ID Mask 0" "Not masked,Masked"
|
|
bitfld.long 0x00 7. " TX_ID_MASK7 ,TX ID Mask 7" "Not masked,Masked"
|
|
newline
|
|
bitfld.long 0x00 6. " TX_ID_MASK6 ,TX ID Mask 6" "Not masked,Masked"
|
|
bitfld.long 0x00 5. " TX_ID_MASK5 ,TX ID Mask 5" "Not masked,Masked"
|
|
bitfld.long 0x00 4. " TX_ID_MASK4 ,TX ID Mask 4" "Not masked,Masked"
|
|
newline
|
|
bitfld.long 0x00 3. " TX_ID_MASK3 ,TX ID Mask 3" "Not masked,Masked"
|
|
bitfld.long 0x00 2. " TX_ID_MASK2 ,TX ID Mask 2" "Not masked,Masked"
|
|
newline
|
|
bitfld.long 0x00 1. " TX_ID_MASK1 ,TX ID Mask 1" "Not masked,Masked"
|
|
bitfld.long 0x00 0. " TX_ID_MASK0 ,TX ID Mask 0" "Not masked,Masked"
|
|
else
|
|
hgroup.long 0x6C++0x3
|
|
hide.long 0x0 "LINMASK,LIN Mask Register"
|
|
endif
|
|
newline
|
|
if ((per.l.be(ad:0xFFF7E400+0x4)&0x40)==0x40)
|
|
group.long 0x70++0x3
|
|
line.long 0x0 "LINID,LIN Identification Register"
|
|
hexmask.long.byte 0x00 16.--23. 1. " RECEIVED_ID ,Received Identifier"
|
|
hexmask.long.byte 0x00 8.--15. 1. " ID_SLAVETASK_BYTE ,Identifier Slave Task Byte"
|
|
hexmask.long.byte 0x00 0.--7. 1. " ID_BYTE ,Identifier Byte"
|
|
else
|
|
hgroup.long 0x70++0x3
|
|
hide.long 0x0 "LINID,LIN Identification Register"
|
|
endif
|
|
group.long 0x74++0x07
|
|
line.long 0x0 "LINTD0,LIN Transmit Buffer 0 Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " TD0 ,8-bit Transmit Buffer 0"
|
|
hexmask.long.byte 0x00 16.--23. 1. " TD1 ,8-bit Transmit Buffer 1"
|
|
hexmask.long.byte 0x00 8.--15. 1. " TD2 ,8-bit Transmit Buffer 2"
|
|
hexmask.long.byte 0x00 0.--7. 1. " TD3 ,8-bit Transmit Buffer 3"
|
|
line.long 0x04 "LINTD1,LIN Transmit Buffer 1 Register"
|
|
hexmask.long.byte 0x04 24.--31. 1. " TD4 ,8-bit Transmit Buffer 4"
|
|
hexmask.long.byte 0x04 16.--23. 1. " TD5 ,8-bit Transmit Buffer 5"
|
|
hexmask.long.byte 0x04 8.--15. 1. " TD6 ,8-bit Transmit Buffer 6"
|
|
hexmask.long.byte 0x04 0.--7. 1. " TD7 ,8-bit Transmit Buffer 7"
|
|
tree.end
|
|
newline
|
|
if ((per.l.be(ad:0xFFF7E400+0x4)&0x40)==0x40)
|
|
group.long 0x7C++0x3
|
|
line.long 0x0 "MBRS,Maximum Baud Rate Selection Register"
|
|
hexmask.long.word 0x00 0.--12. 1. " MBR ,Maximum Baud Rate Prescaler"
|
|
else
|
|
hgroup.long 0x7C++0x3
|
|
hide.long 0x0 "MBRS,Maximum Baud Rate Selection Register"
|
|
endif
|
|
if ((per.l.be(ad:0xFFF7E400+0x4)&0x40)==0x40)
|
|
group.long 0x90++0x03
|
|
line.long 0x0 "IODFTCTRL,Input/Output Error Enable Register"
|
|
bitfld.long 0x00 31. " BEN ,Bit Error Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " PBEN ,Physical Bus Error Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " CEN ,Checksum Error Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " ISFE ,Inconsistent Synch Field Error Enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " FEN ,Frame Error Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 19.--20. " PSM ,PIN sample mask" "No mask,TBIT_CENTER,TBIT_CENTER + SCLK,TBIT_CENTER + 2 SCLK"
|
|
bitfld.long 0x00 16.--18. " TX_SHIFT ,Transmit Shift" "No delay,1 SCLK,2 SCLKs,3 SCLKs,4 SCLKs,5 SCLKs,6 SCLKs,7 SCLKs"
|
|
newline
|
|
bitfld.long 0x00 8.--11. " IODFTENA ,IO DFT Enable Key" "Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Enabled,Disabled,Disabled,Disabled,Disabled,Disabled"
|
|
bitfld.long 0x00 1. " LPBENA ,Module Loopback Enable" "Analog,Digital"
|
|
bitfld.long 0x00 0. " RXPENA ,Module Analog Loopback Through Receive/Transmit Pin Enable" "Transmit,Receive"
|
|
else
|
|
group.long 0x90++0x03
|
|
line.long 0x0 "IODFTCTRL,Input/Output Error Enable Register"
|
|
bitfld.long 0x00 26. " FEN ,Frame Error Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 25. " PEN ,Parity Error Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " BRKDTEN ,Break Detect Error Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 19.--20. " PSM ,PIN sample mask" "No mask,TBIT_CENTER,TBIT_CENTER + SCLK,TBIT_CENTER + 2 SCLK"
|
|
newline
|
|
bitfld.long 0x00 16.--18. " TX_SHIFT ,Transmit Shift" "No delay,1 SCLK,2 SCLKs,3 SCLKs,4 SCLKs,5 SCLKs,6 SCLKs,7 SCLKs"
|
|
bitfld.long 0x00 8.--11. " IODFTENA ,IO DFT Enable Key" "Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Enabled,Disabled,Disabled,Disabled,Disabled,Disabled"
|
|
bitfld.long 0x00 1. " LPBENA ,Module Loopback Enable" "Analog,Digital"
|
|
bitfld.long 0x00 0. " RXPENA ,Module Analog Loopback Through Receive/Transmit Pin Enable" "Transmit,Receive"
|
|
endif
|
|
endian.le
|
|
width 0x0B
|
|
tree.end
|
|
tree "SCI"
|
|
base ad:0xFFF7E500
|
|
width 19.
|
|
endian.be
|
|
group.long 0x00++0x3
|
|
line.long 0x0 "SCIGCR0,SCI Global Control Register 0"
|
|
bitfld.long 0x00 0. " RESET ,SCI Module Reset" "Under reset,Out of reset"
|
|
if (((per.l.be((ad:0xFFF7E400+0x04)))&0x04)==0x04)
|
|
group.long 0x04++0x03
|
|
line.long 0x0 "SCIGCR1,SCI Global Control Register 1"
|
|
bitfld.long 0x00 25. " TXENA ,SCI Transmitter Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " RXENA ,SCI Receiver Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " CONT ,Continue on Suspend" "Frozen,Continued"
|
|
bitfld.long 0x00 16. " LOOP_BACK ,LOOP BACK Enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 9. " PWR_DOWN ,Power down. Low power mode enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " SLEEP ,SCI Sleep Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " SWNRESET ,Software Reset" "Reset,Ready"
|
|
newline
|
|
bitfld.long 0x00 5. " CLOCK ,SCI internal clock enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " STOP ,SCI Number of Stop Bits" "1 bit,2 bits"
|
|
bitfld.long 0x00 3. " PARITY ,SCI Parity Odd/Even Selection" "Odd,Even"
|
|
newline
|
|
bitfld.long 0x00 2. " PARITY_ENA ,Parity Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " TIMING_MODE ,SCI Timing Mode Bit" "Synchronous,Asynchronous"
|
|
bitfld.long 0x00 0. " COMM_MODE ,SCI/LIN Communication Mode Bit" "Idle-line,Address-bit"
|
|
else
|
|
group.long 0x04++0x03
|
|
line.long 0x0 "SCIGCR1,SCI Global Control Register 1"
|
|
bitfld.long 0x00 25. " TXENA ,SCI Transmitter Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " RXENA ,SCI Receiver Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " CONT ,Continue on Suspend" "Frozen,Continued"
|
|
bitfld.long 0x00 16. " LOOP_BACK ,LOOP BACK Enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 9. " PWR_DOWN ,Power down. Low power mode enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " SLEEP ,SCI Sleep Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " SWNRESET ,Software Reset" "Reset,Ready"
|
|
bitfld.long 0x00 5. " CLOCK ,SCI internal clock enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 4. " STOP ,SCI Number of Stop Bits" "1 bit,2 bits"
|
|
bitfld.long 0x00 2. " PARITY_ENA ,Parity Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " TIMING_MODE ,SCI Timing Mode Bit" "Synchronous,Asynchronous"
|
|
bitfld.long 0x00 0. " COMM_MODE ,SCI/LIN Communication Mode Bit" "Idle-line,Address-bit"
|
|
endif
|
|
newline
|
|
group.long 0x0C++0x03
|
|
line.long 0x0 "SCIINT_SET/CLR,SCI Set/Clear Interrupt Register"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x04 26. " FE_INT ,Framing-Error Interrupt" "Disabled,Enabled"
|
|
setclrfld.long 0x00 25. 0x00 25. 0x04 25. " OE_INT ,Overrun-Error Interrupt" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x04 24. " PE_INT ,Parity Interrupt" "Disabled,Enabled"
|
|
newline
|
|
sif !cpuis("TMS570LS0232")
|
|
setclrfld.long 0x00 18. 0x00 18. 0x04 18. " RX_DMA_ALL ,Receive DMA All" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x04 17. " RX_DMA ,Receive DMA" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x04 16. " TX_DMA ,Transmit DMA" "Disabled,Enabled"
|
|
newline
|
|
endif
|
|
setclrfld.long 0x00 9. 0x00 9. 0x04 9. " RX_INT ,Receiver Interrupt Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x04 8. " TX_INT ,Transmitter Interrupt" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 1. 0x00 1. 0x04 1. " WAKEUP_INT ,Wake-up Interrupt" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x04 0. " BRKDT_INT ,Break-detect Interrupt" "Disabled,Enabled"
|
|
group.long 0x14++0x3
|
|
line.long 0x0 "SCIINTLVL_SET/CLR,SCI Set/Clear Interrupt Level Register"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x04 26. " FE_INT_LVL ,Framing-Error Interrupt Level" "INT0,INT1"
|
|
setclrfld.long 0x00 25. 0x00 25. 0x04 25. " OE_INT_LVL ,Overrun-Error Interrupt Level" "INT0,INT1"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x04 24. " PE_INT_LVL ,Parity Error Interrupt Level" "INT0,INT1"
|
|
newline
|
|
setclrfld.long 0x00 18. 0x00 18. 0x04 18. " RX_DMA_ALL_INT_LVL ,Receive DMA All Interrupt Level" "INT0,INT1"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x04 9. " RX_INT_LVL ,Receiver Interrupt Level" "INT0,INT1"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x04 8. " TX_INT_LVL ,Transmitter Interrupt Level" "INT0,INT1"
|
|
newline
|
|
setclrfld.long 0x00 1. 0x00 1. 0x04 1. " WAKEUP_INT_LVL ,Wake-up Interrupt Level" "INT0,INT1"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x04 0. " BRKDT_INT ,Break-Detect Interrupt Level" "INT0,INT1"
|
|
newline
|
|
group.long 0x1C++0x3
|
|
line.long 0x0 "SCIFLR,SCI Flags Register"
|
|
eventfld.long 0x00 26. " FE ,Framing Error Flag" "Not detected,Detected"
|
|
eventfld.long 0x00 25. " OE ,Overrun Error Flag" "Not detected,Detected"
|
|
eventfld.long 0x00 24. " PE ,Parity Error Flag" "Not detected,Detected"
|
|
bitfld.long 0x00 12. " RXWAKE ,Receiver Wakeup Detect Flag" "Not address,Address"
|
|
newline
|
|
bitfld.long 0x00 11. " TX_EMPTY ,Transmitter Empty Flag" "Not empty,Empty"
|
|
bitfld.long 0x00 10. " TXWAKE ,SCI Transmitter Wakeup Method Select" "Data,Address"
|
|
eventfld.long 0x00 9. " RXRDY ,Receiver Ready Flag" "Not ready,Ready"
|
|
bitfld.long 0x00 8. " TXRDY ,Transmitter Buffer Register Ready Flag (SCITD)" "Full,Ready"
|
|
newline
|
|
bitfld.long 0x00 3. " BUSY_FLAG ,BUSY Flag" "Not busy,Busy"
|
|
rbitfld.long 0x00 2. " IDLE ,SCI Receiver in Idle State" "Not detected,Detected"
|
|
eventfld.long 0x00 1. " WAKEUP ,Wake-up Flag" "No wake up,Wake up"
|
|
eventfld.long 0x00 0. " BRKDT ,SCI Break-Detect Flag" "Not detected,Detected"
|
|
hgroup.long 0x20++0x3
|
|
hide.long 0x0 "SCIINVECT0,SCI Interrupt Vector Offset 0"
|
|
in
|
|
hgroup.long 0x24++0x3
|
|
hide.long 0x0 "SCIINVECT1,SCI Interrupt Vector Offset 1"
|
|
in
|
|
group.long 0x28++0x3
|
|
line.long 0x0 "SCIFORMAT,SCI Format Control Register"
|
|
bitfld.long 0x00 16.--18. " LENGTH ,Frame Length Control Bits" "1 character,2 characters,3 characters,4 characters,5 characters,6 characters,7 characters,8 characters"
|
|
bitfld.long 0x00 0.--2. " CHAR ,Character Length Control Bits" "1 bit,2 bits,3 bits,4 bits,5 bits,6 bits,7 bits,8 bits"
|
|
group.long 0x2C++0x3
|
|
line.long 0x0 "BRS,Baud Rate Selection Register"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " PRESCALER_P ,SCI/BLIN 24-bit Integer Prescaler Selection"
|
|
rgroup.long 0x30++0x3
|
|
line.long 0x0 "SCIED,SCI Data Buffer Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " ED ,Emulation Data"
|
|
hgroup.long 0x34++0x3
|
|
hide.long 0x0 "SCIRD,SCI Data Buffer Register"
|
|
in
|
|
group.long 0x38++0x3
|
|
line.long 0x0 "SCITD,SCI Data Buffer Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " TD ,Transmit Data"
|
|
tree "SCI Pin I/O Control Registers"
|
|
group.long 0x3C++0x07
|
|
line.long 0x0 "SCIPIO0,SCI Pin I/O Control Register 0"
|
|
bitfld.long 0x00 2. " TX_FUNC ,Defines the Function of Pin SCITX" "GPIO,SCI/LIN TX"
|
|
bitfld.long 0x00 1. " RX_FUNC ,Defines the Function of Pin SCIRX" "GPIO,SCI/LIN RX"
|
|
line.long 0x04 "SCIPIO1,SCI Pin I/O Control Register 1"
|
|
bitfld.long 0x04 2. " TX_DIR ,Transmit Direction" "Input,Output"
|
|
bitfld.long 0x04 1. " RX_DIR ,Receive Direction" "Input,Output"
|
|
rgroup.long 0x44++0x03
|
|
line.long 0x00 "SCIPIO2,SCI Pin I/O Control Register 2"
|
|
bitfld.long 0x00 2. " TX_IN ,Contains Current Value on the SCITX Pin" "Low,High"
|
|
bitfld.long 0x00 1. " RX_IN ,Contains Current Value on the SCIRX Pin" "Low,High"
|
|
group.long 0x48++0x03
|
|
line.long 0x00 "SCIPIO3-5_SET/CLR,SCI Pin I/O Control Set/Clear Register 3-5"
|
|
setclrfld.long 0x00 2. 0x04 2. 0x08 2. " TX_OUT ,SCITX Pin Data Output" "Low,High"
|
|
setclrfld.long 0x00 1. 0x04 1. 0x08 1. " RX_OUT ,SCIRX Pin Data Output" "Low,High"
|
|
group.long 0x54++0x0B
|
|
line.long 0x00 "SCIPIO6,SCI Pin I/O Control Register 6"
|
|
bitfld.long 0x00 2. " TX_PDR ,TX Open Drain Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " RX_PDR ,RX Open Drain Enable" "Disabled,Enabled"
|
|
line.long 0x04 "SCIPIO7,SCI Pin I/O Control Register 7"
|
|
bitfld.long 0x04 2. " TX_PD ,TX Pin Pull Control Disable" "Enabled,Disabled"
|
|
bitfld.long 0x04 1. " RX_PD ,RX Pin Pull Control Disable" "Enabled,Disabled"
|
|
line.long 0x08 "SCIPIO8,SCI Pin I/O Control Register 8"
|
|
bitfld.long 0x08 2. " TX_PSL ,TX Pin Pull Select" "Pull down,Pull up"
|
|
bitfld.long 0x08 1. " RX_PSL ,RX Pin Pull Select" "Pull down,Pull up"
|
|
tree.end
|
|
group.long 0x90++0x03
|
|
line.long 0x0 "IODFTCTRL,Input/Output Error Enable Register"
|
|
bitfld.long 0x00 26. " FEN ,Frame Error Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 25. " PEN ,Parity Error Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " BRKDTEN ,Break Detect Error Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 19.--20. " PSM ,PIN sample mask" "No mask,TBIT_CENTER,TBIT_CENTER + SCLK,TBIT_CENTER + 2 SCLK"
|
|
newline
|
|
bitfld.long 0x00 16.--18. " TX_SHIFT ,Transmit Shift" "No delay,1 SCLK,2 SCLKs,3 SCLKs,4 SCLKs,5 SCLKs,6 SCLKs,7 SCLKs"
|
|
bitfld.long 0x00 8.--11. " IODFTENA ,IO DFT Enable Key" "Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Enabled,Disabled,Disabled,Disabled,Disabled,Disabled"
|
|
bitfld.long 0x00 1. " LPBENA ,Module Loopback Enable" "Analog,Digital"
|
|
bitfld.long 0x00 0. " RXPENA ,Module Analog Loopback Through Receive/Transmit Pin Enable" "Transmit,Receive"
|
|
endian.le
|
|
width 0x0B
|
|
tree.end
|
|
tree.end
|
|
elif cpuis("TMS570LS0232")
|
|
tree "SCI/LIN (Serial Communications Interface/Local Interconnect Network Module)"
|
|
base ad:0xFFF7E400
|
|
width 19.
|
|
endian.be
|
|
group.long 0x00++0x3
|
|
line.long 0x0 "SCIGCR0,SCI Global Control Register 0"
|
|
bitfld.long 0x00 0. " RESET ,SCI Module Reset" "Under reset,Out of reset"
|
|
if ((per.l.be(ad:0xFFF7E400+0x4)&0x40)==0x40)
|
|
group.long 0x04++0x03
|
|
line.long 0x0 "SCIGCR1,SCI Global Control Register 1"
|
|
bitfld.long 0x00 25. " TXENA ,SCI Transmitter Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " RXENA ,SCI Receiver Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " CONT ,Continue on Suspend" "Frozen,Continued"
|
|
bitfld.long 0x00 16. " LOOP_BACK ,LOOP BACK Enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 13. " STOP_EXT_FRAME ,Stop Extended Frame Communication" "Not stopped,Stopped"
|
|
bitfld.long 0x00 12. " HGEN_CTRL ,LIN Mode Bit (Type of Mask Filtering Comparison)" "ID-Byte,ID-Slave task byte"
|
|
bitfld.long 0x00 11. " CTYPE ,LIN Mode Bit (Classic/Enhanced)" "Classic,Enhanced"
|
|
newline
|
|
bitfld.long 0x00 10. " MBUF_MODE ,Receive/Transmit Buffer Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " ADAPT ,LIN Mode Bit (Automatic Baudrate Adjustment)" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " SWNRESET ,Software Reset" "Reset,Ready"
|
|
newline
|
|
bitfld.long 0x00 6. " LIN_MODE ,Mode select" "SCI mode,LIN mode"
|
|
bitfld.long 0x00 5. " CLOCK ,SCI internal clock enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " PARITY_ENA ,ID-Parity Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " COMM_MODE ,SCI/LIN Communication Mode Bit ID4 and ID5 Use" "Not used,Used"
|
|
elif (((per.l.be((ad:0xFFF7E400+0x4)))&0x44)==0x04)
|
|
group.long 0x04++0x03
|
|
line.long 0x0 "SCIGCR1,SCI Global Control Register 1"
|
|
bitfld.long 0x00 25. " TXENA ,SCI Transmitter Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " RXENA ,SCI Receiver Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " CONT ,Continue on Suspend" "Frozen,Continued"
|
|
bitfld.long 0x00 16. " LOOP_BACK ,LOOP BACK Enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 10. " MBUF_MODE ,Receive/Transmit Buffer Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " SLEEP ,SCI Sleep Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " SWNRESET ,Software Reset" "Reset,Ready"
|
|
newline
|
|
newline
|
|
bitfld.long 0x00 6. " LIN_MODE ,Mode select" "SCI mode,LIN mode"
|
|
bitfld.long 0x00 5. " CLOCK ,SCI internal clock enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " STOP ,SCI Number of Stop Bits" "1 bit,2 bits"
|
|
bitfld.long 0x00 3. " PARITY ,SCI Parity Odd/Even Selection" "Odd,Even"
|
|
newline
|
|
bitfld.long 0x00 2. " PARITY_ENA ,Parity Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " TIMING_MODE ,SCI Timing Mode Bit" "Synchronous,Asynchronous"
|
|
bitfld.long 0x00 0. " COMM_MODE ,SCI/LIN Communication Mode Bit" "Idle-line,Address-bit"
|
|
elif (((per.l.be((ad:0xFFF7E400+0x4)))&0x44)==0x00)
|
|
group.long 0x04++0x03
|
|
line.long 0x0 "SCIGCR1,SCI Global Control Register 1"
|
|
bitfld.long 0x00 25. " TXENA ,SCI Transmitter Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " RXENA ,SCI Receiver Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " CONT ,Continue on Suspend" "Frozen,Continued"
|
|
newline
|
|
bitfld.long 0x00 16. " LOOP_BACK ,LOOP BACK Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " MBUF_MODE ,Receive/Transmit Buffer Enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 8. " SLEEP ,SCI Sleep Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " SWNRESET ,Software Reset" "Reset,Ready"
|
|
newline
|
|
bitfld.long 0x00 6. " LIN_MODE ,Mode select" "SCI mode,LIN mode"
|
|
bitfld.long 0x00 5. " CLOCK ,SCI internal clock enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " STOP ,SCI Number of Stop Bits" "1 bit,2 bits"
|
|
newline
|
|
bitfld.long 0x00 2. " PARITY_ENA ,Parity Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " TIMING_MODE ,SCI Timing Mode Bit" "Synchronous,Asynchronous"
|
|
bitfld.long 0x00 0. " COMM_MODE ,SCI/LIN Communication Mode Bit" "Idle-line,Address-bit"
|
|
endif
|
|
if ((per.l.be(ad:0xFFF7E400+0x4)&0x40)==0x40)
|
|
group.long 0x08++0x03
|
|
line.long 0x0 "SCIGCR2,SCI Global Control Register 2"
|
|
bitfld.long 0x00 17. " CC ,Compare Checksum" "No effect,Compared"
|
|
bitfld.long 0x00 16. " SC ,Send Checksum" "Not sent,Sent"
|
|
bitfld.long 0x00 8. " GEN_WU ,Generate Wakeup Signal" "No effect,Generated"
|
|
bitfld.long 0x00 0. " POWERDOWN ,POWERDOWN" "Normal,Local low-power"
|
|
else
|
|
group.long 0x08++0x03
|
|
line.long 0x0 "SCIGCR2,SCI Global Control Register 2"
|
|
rbitfld.long 0x00 17. " CC ,Compare Checksum" "No effect,Compared"
|
|
rbitfld.long 0x00 16. " SC ,Send Checksum" "Not sent,Sent"
|
|
bitfld.long 0x00 0. " POWERDOWN ,POWERDOWN" "Normal,Local low-power"
|
|
endif
|
|
newline
|
|
if ((per.l.be(ad:0xFFF7E400+0x4)&0x40)==0x40)
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "SCIINT_SET/CLR,SCI Set/Clear Interrupt Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x04 31. " BE_INT ,Bit Error Interrupt" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x04 30. " PBE_INT ,Physical Bus Error Interrupt" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x04 29. " CE_INT ,Checksum-Error Interrupt" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 28. 0x00 28. 0x04 28. " ISFE_INT ,Inconsistent-Synch-Field-Error Interrupt" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x04 27. " NRE_INT ,No-Response-Error Interrupt" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x04 26. " FE_INT ,Framing-Error Interrupt" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 25. 0x00 25. 0x04 25. " OE_INT ,Overrun-Error Interrupt" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x04 24. " PE_INT ,Parity Interrupt" "Disabled,Enabled"
|
|
newline
|
|
sif !cpuis("TMS570LS0232")
|
|
setclrfld.long 0x00 17. 0x00 17. 0x04 17. " RX_DMA ,Receive DMA" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x04 16. " TX_DMA ,Transmit DMA" "Disabled,Enabled"
|
|
newline
|
|
endif
|
|
setclrfld.long 0x00 13. 0x00 13. 0x04 13. " ID_INT ,ID Interrupt" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x04 9. " RX_INT ,Receiver Interrupt Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x04 8. " TX_INT ,Transmitter Interrupt" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 7. 0x00 7. 0x04 7. " TOA3WUS_INT ,Timeout After 3 Wakeup Signals Interrupt" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x04 6. " TOAWUS_INT ,Timeout After Wakeup Signal Interrupt" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 4. 0x00 4. 0x04 4. " TIMEOUT_INT ,Timeout Interrupt" "Disabled,Enabled"
|
|
setclrfld.long 0x00 1. 0x00 1. 0x04 1. " WAKEUP_INT ,Wake-up Interrupt" "Disabled,Enabled"
|
|
else
|
|
group.long 0x0C++0x03
|
|
line.long 0x0 "SCIINT_SET/CLR,SCI Set/Clear Interrupt Register"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x04 26. " FE_INT ,Framing-Error Interrupt" "Disabled,Enabled"
|
|
setclrfld.long 0x00 25. 0x00 25. 0x04 25. " OE_INT ,Overrun-Error Interrupt" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x04 24. " PE_INT ,Parity Interrupt" "Disabled,Enabled"
|
|
newline
|
|
sif !cpuis("TMS570LS0232")
|
|
setclrfld.long 0x00 18. 0x00 18. 0x04 18. " RX_DMA_ALL ,Receive DMA All" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x04 17. " RX_DMA ,Receive DMA" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x04 16. " TX_DMA ,Transmit DMA" "Disabled,Enabled"
|
|
newline
|
|
endif
|
|
setclrfld.long 0x00 9. 0x00 9. 0x04 9. " RX_INT ,Receiver Interrupt Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x04 8. " TX_INT ,Transmitter Interrupt" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 1. 0x00 1. 0x04 1. " WAKEUP_INT ,Wake-up Interrupt" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x04 0. " BRKDT_INT ,Break-detect Interrupt" "Disabled,Enabled"
|
|
endif
|
|
if ((per.l.be(ad:0xFFF7E400+0x4)&0x40)==0x40)
|
|
group.long 0x14++0x03
|
|
line.long 0x0 "SCIINTLVL_SET/CLR,SCI Set/Clear Interrupt Level Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x04 31. " BE_INT_LVL ,Bit Error Interrupt Level" "INT0,INT1"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x04 30. " PBE_INT_LVL ,Physical Bus Error Interrupt Level" "INT0,INT1"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x04 29. " CE_INT_LVL ,Checksum-Error Interrupt Level" "INT0,INT1"
|
|
newline
|
|
setclrfld.long 0x00 28. 0x00 28. 0x04 28. " ISFE_INT_LVL ,Inconsistent-Synch-Field-Error Interrupt Level" "INT0,INT1"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x04 27. " NRE_INT_LVL ,No-Response-Error Interrupt Level" "INT0,INT1"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x04 26. " FE_INT_LVL ,Framing-Error Interrupt Level" "INT0,INT1"
|
|
newline
|
|
setclrfld.long 0x00 25. 0x00 25. 0x04 25. " OE_INT_LVL ,Overrun-Error Interrupt Level" "INT0,INT1"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x04 24. " PE_INT_LVL ,Parity Error Interrupt Level" "INT0,INT1"
|
|
setclrfld.long 0x00 13. 0x00 13. 0x04 13. " ID_INT_LVL ,ID Interrupt Level" "INT0,INT1"
|
|
newline
|
|
setclrfld.long 0x00 9. 0x00 9. 0x04 9. " RX_INT_LVL ,Receiver Interrupt Level" "INT0,INT1"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x04 8. " TX_INT_LVL ,Transmitter Interrupt Level" "INT0,INT1"
|
|
setclrfld.long 0x00 7. 0x00 7. 0x04 7. " TOA3WUS_INT_LVL ,Timeout After 3 Wakeup Signals Interrupt" "INT0,INT1"
|
|
newline
|
|
setclrfld.long 0x00 6. 0x00 6. 0x04 6. " TOAWUS_INT_LVL ,Timeout After Wakeup Signal Interrupt Level" "INT0,INT1"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x04 4. " TIMEOUT_INT_LVL ,Timeout Interrupt Level" "INT0,INT1"
|
|
setclrfld.long 0x00 1. 0x00 1. 0x04 1. " WAKEUP_INT_LVL ,Wake-up Interrupt Level" "INT0,INT1"
|
|
else
|
|
group.long 0x14++0x3
|
|
line.long 0x0 "SCIINTLVL_SET/CLR,SCI Set/Clear Interrupt Level Register"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x04 26. " FE_INT_LVL ,Framing-Error Interrupt Level" "INT0,INT1"
|
|
setclrfld.long 0x00 25. 0x00 25. 0x04 25. " OE_INT_LVL ,Overrun-Error Interrupt Level" "INT0,INT1"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x04 24. " PE_INT_LVL ,Parity Error Interrupt Level" "INT0,INT1"
|
|
newline
|
|
setclrfld.long 0x00 18. 0x00 18. 0x04 18. " RX_DMA_ALL_INT_LVL ,Receive DMA All Interrupt Level" "INT0,INT1"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x04 9. " RX_INT_LVL ,Receiver Interrupt Level" "INT0,INT1"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x04 8. " TX_INT_LVL ,Transmitter Interrupt Level" "INT0,INT1"
|
|
newline
|
|
setclrfld.long 0x00 1. 0x00 1. 0x04 1. " WAKEUP_INT_LVL ,Wake-up Interrupt Level" "INT0,INT1"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x04 0. " BRKDT_INT ,Break-Detect Interrupt Level" "INT0,INT1"
|
|
endif
|
|
newline
|
|
if ((per.l.be(ad:0xFFF7E400+0x4)&0x40)==0x40)
|
|
group.long 0x1C++0x3
|
|
line.long 0x0 "SCIFLR,SCI Flags Register"
|
|
eventfld.long 0x00 31. " BE ,Bit Error Flag" "Not detected,Detected"
|
|
eventfld.long 0x00 30. " PBE ,Physical Bus Error Flag" "Not detected,Detected"
|
|
eventfld.long 0x00 29. " CE ,Checksum Error Flag" "Not detected,Detected"
|
|
eventfld.long 0x00 28. " ISFE ,Inconsistent Synch Field Error Flag" "Not detected,Detected"
|
|
newline
|
|
eventfld.long 0x00 27. " NRE ,No-Response Error Flag" "Not detected,Detected"
|
|
eventfld.long 0x00 26. " FE ,Framing Error Flag" "Not detected,Detected"
|
|
eventfld.long 0x00 25. " OE ,Overrun Error Flag" "Not detected,Detected"
|
|
eventfld.long 0x00 24. " PE ,Parity Error Flag" "Not detected,Detected"
|
|
newline
|
|
eventfld.long 0x00 14. " ID_RX_FLAG ,Identifier On Receive Flag" "Not received,Received"
|
|
eventfld.long 0x00 13. " ID_TX_FLAG ,Identifier On Transmit Flag" "Not received,Received"
|
|
bitfld.long 0x00 11. " TX_EMPTY ,Transmitter Empty Flag" "Not empty,Empty"
|
|
eventfld.long 0x00 9. " RXRDY ,Receiver Ready Flag" "Not ready,Ready"
|
|
newline
|
|
bitfld.long 0x00 8. " TXRDY ,Transmitter Buffer Register Ready Flag" "Full,Ready"
|
|
eventfld.long 0x00 7. " TOA3WUS ,Timeout After 3 Wakeup Signals Flag" "No timeout,Timeout"
|
|
eventfld.long 0x00 6. " TOAWUS ,Timeout After Wakeup Signal Flag" "No timeout,Timeout"
|
|
newline
|
|
eventfld.long 0x00 4. " TIMEOUT ,LIN Bus IDLE Timeout Flag" "Not detected,Detected"
|
|
bitfld.long 0x00 3. " BUSY_FLAG ,BUSY Flag" "Not busy,Busy"
|
|
eventfld.long 0x00 1. " WAKEUP ,Wake-up Flag" "No wake up,Wake up"
|
|
else
|
|
group.long 0x1C++0x3
|
|
line.long 0x0 "SCIFLR,SCI Flags Register"
|
|
eventfld.long 0x00 26. " FE ,Framing Error Flag" "Not detected,Detected"
|
|
eventfld.long 0x00 25. " OE ,Overrun Error Flag" "Not detected,Detected"
|
|
eventfld.long 0x00 24. " PE ,Parity Error Flag" "Not detected,Detected"
|
|
bitfld.long 0x00 12. " RXWAKE ,Receiver Wakeup Detect Flag" "Not address,Address"
|
|
newline
|
|
bitfld.long 0x00 11. " TX_EMPTY ,Transmitter Empty Flag" "Not empty,Empty"
|
|
bitfld.long 0x00 10. " TXWAKE ,SCI Transmitter Wakeup Method Select" "Data,Address"
|
|
eventfld.long 0x00 9. " RXRDY ,Receiver Ready Flag" "Not ready,Ready"
|
|
bitfld.long 0x00 8. " TXRDY ,Transmitter Buffer Register Ready Flag (SCITD)" "Full,Ready"
|
|
newline
|
|
bitfld.long 0x00 3. " BUSY_FLAG ,BUSY Flag" "Not busy,Busy"
|
|
rbitfld.long 0x00 2. " IDLE ,SCI Receiver in Idle State" "Not detected,Detected"
|
|
eventfld.long 0x00 1. " WAKEUP ,Wake-up Flag" "No wake up,Wake up"
|
|
eventfld.long 0x00 0. " BRKDT ,SCI Break-Detect Flag" "Not detected,Detected"
|
|
endif
|
|
hgroup.long 0x20++0x3
|
|
hide.long 0x0 "SCIINVECT0,SCI Interrupt Vector Offset 0"
|
|
in
|
|
hgroup.long 0x24++0x3
|
|
hide.long 0x0 "SCIINVECT1,SCI Interrupt Vector Offset 1"
|
|
in
|
|
if ((per.l.be(ad:0xFFF7E400+0x4)&0x40)==0x40)
|
|
group.long 0x28++0x3
|
|
line.long 0x0 "SCIFORMAT,SCI Format Control Register"
|
|
bitfld.long 0x00 16.--18. " LENGTH ,Frame Length Control Bits" "1 byte,2 bytes,3 bytes,4 bytes,5 bytes,6 bytes,7 bytes,8 bytes"
|
|
elif (((per.l.be(ad:0xFFF7E400+0x4)&0x440)==0x400))
|
|
group.long 0x28++0x3
|
|
line.long 0x0 "SCIFORMAT,SCI Format Control Register"
|
|
bitfld.long 0x00 16.--18. " LENGTH ,Frame Length Control Bits" "1 character,2 characters,3 characters,4 characters,5 characters,6 characters,7 characters,8 characters"
|
|
bitfld.long 0x00 0.--2. " CHAR ,Character Length Control Bits" "1 bit,2 bits,3 bits,4 bits,5 bits,6 bits,7 bits,8 bits"
|
|
else
|
|
group.long 0x28++0x3
|
|
line.long 0x0 "SCIFORMAT,SCI Format Control Register"
|
|
bitfld.long 0x00 0.--2. " CHAR ,Character Length Control Bits" "1 bit,2 bits,3 bits,4 bits,5 bits,6 bits,7 bits,8 bits"
|
|
endif
|
|
group.long 0x2C++0x3
|
|
line.long 0x0 "BRS,Baud Rate Selection Register"
|
|
bitfld.long 0x00 28.--30. " U ,SCI/BLIN Super Fractional Divider Selection" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 24.--27. " M ,SCI/BLIN 4-bit Fractional Divider Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " PRESCALER_P ,SCI/BLIN 24-bit Integer Prescaler Selection"
|
|
rgroup.long 0x30++0x3
|
|
line.long 0x0 "SCIED,SCI Data Buffer Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " ED ,Emulation Data"
|
|
hgroup.long 0x34++0x3
|
|
hide.long 0x0 "SCIRD,SCI Data Buffer Register"
|
|
in
|
|
group.long 0x38++0x3
|
|
line.long 0x0 "SCITD,SCI Data Buffer Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " TD ,Transmit Data"
|
|
tree "SCI Pin I/O Control Registers"
|
|
group.long 0x3C++0x07
|
|
line.long 0x0 "SCIPIO0,SCI Pin I/O Control Register 0"
|
|
bitfld.long 0x00 2. " TX_FUNC ,Defines the Function of Pin SCITX" "GPIO,SCI/LIN TX"
|
|
bitfld.long 0x00 1. " RX_FUNC ,Defines the Function of Pin SCIRX" "GPIO,SCI/LIN RX"
|
|
line.long 0x04 "SCIPIO1,SCI Pin I/O Control Register 1"
|
|
bitfld.long 0x04 2. " TX_DIR ,Transmit Direction" "Input,Output"
|
|
bitfld.long 0x04 1. " RX_DIR ,Receive Direction" "Input,Output"
|
|
rgroup.long 0x44++0x03
|
|
line.long 0x00 "SCIPIO2,SCI Pin I/O Control Register 2"
|
|
bitfld.long 0x00 2. " TX_IN ,Contains Current Value on the SCITX Pin" "Low,High"
|
|
bitfld.long 0x00 1. " RX_IN ,Contains Current Value on the SCIRX Pin" "Low,High"
|
|
group.long 0x48++0x03
|
|
line.long 0x00 "SCIPIO3-5_SET/CLR,SCI Pin I/O Control Set/Clear Register 3-5"
|
|
setclrfld.long 0x00 2. 0x04 2. 0x08 2. " TX_OUT ,SCITX Pin Data Output" "Low,High"
|
|
setclrfld.long 0x00 1. 0x04 1. 0x08 1. " RX_OUT ,SCIRX Pin Data Output" "Low,High"
|
|
group.long 0x54++0x0B
|
|
line.long 0x00 "SCIPIO6,SCI Pin I/O Control Register 6"
|
|
bitfld.long 0x00 2. " TX_PDR ,TX Open Drain Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " RX_PDR ,RX Open Drain Enable" "Disabled,Enabled"
|
|
line.long 0x04 "SCIPIO7,SCI Pin I/O Control Register 7"
|
|
bitfld.long 0x04 2. " TX_PD ,TX Pin Pull Control Disable" "Enabled,Disabled"
|
|
bitfld.long 0x04 1. " RX_PD ,RX Pin Pull Control Disable" "Enabled,Disabled"
|
|
line.long 0x08 "SCIPIO8,SCI Pin I/O Control Register 8"
|
|
bitfld.long 0x08 2. " TX_PSL ,TX Pin Pull Select" "Pull down,Pull up"
|
|
bitfld.long 0x08 1. " RX_PSL ,RX Pin Pull Select" "Pull down,Pull up"
|
|
tree.end
|
|
tree "LIN Registers"
|
|
if ((per.l.be(ad:0xFFF7E400+0x4)&0x40)==0x40)
|
|
group.long 0x60++0x3
|
|
line.long 0x0 "LINCOMP,BLINCOMPARE Register"
|
|
bitfld.long 0x00 8.--9. " SDEL ,2-bit Synch Delimiter Compare" "1 bit,2 bits,3 bits,4 bits"
|
|
bitfld.long 0x00 0.--2. " SBREAK ,3-bit Synch Break Extend" "Not extended,1 bit,2 bits,3 bits,4 bits,5 bits,6 bits,7 bits"
|
|
else
|
|
hgroup.long 0x60++0x3
|
|
hide.long 0x0 "LINCOMP,BLINCOMPARE Register"
|
|
endif
|
|
hgroup.long 0x64++0x3
|
|
hide.long 0x0 "LINRD0,LIN Receive Buffer 0 Register"
|
|
in
|
|
rgroup.long 0x68++0x3
|
|
line.long 0x0 "LINRD1,LIN Receive Buffer 1 Register"
|
|
hexmask.long.byte 0x00 24.--31. 0x01 " RD4 ,Receive Buffer 4"
|
|
hexmask.long.byte 0x00 16.--23. 0x01 " RD5 ,Receive Buffer 5"
|
|
hexmask.long.byte 0x00 8.--15. 0x01 " RD6 ,Receive Buffer 6"
|
|
hexmask.long.byte 0x00 0.--7. 0x01 " RD7 ,Receive Buffer 7"
|
|
newline
|
|
if ((per.l.be(ad:0xFFF7E400+0x4)&0x40)==0x40)
|
|
group.long 0x6C++0x3
|
|
line.long 0x0 "LINMASK,LIN Mask Register"
|
|
bitfld.long 0x00 23. " RX_ID_MASK7 ,RX ID Mask 7" "Not masked,Masked"
|
|
bitfld.long 0x00 22. " RX_ID_MASK6 ,RX ID Mask 6" "Not masked,Masked"
|
|
bitfld.long 0x00 21. " RX_ID_MASK5 ,RX ID Mask 5" "Not masked,Masked"
|
|
newline
|
|
bitfld.long 0x00 20. " RX_ID_MASK4 ,RX ID Mask 4" "Not masked,Masked"
|
|
bitfld.long 0x00 19. " RX_ID_MASK3 ,RX ID Mask 3" "Not masked,Masked"
|
|
bitfld.long 0x00 18. " RX_ID_MASK2 ,RX ID Mask 2" "Not masked,Masked"
|
|
newline
|
|
bitfld.long 0x00 17. " RX_ID_MASK1 ,RX ID Mask 1" "Not masked,Masked"
|
|
bitfld.long 0x00 16. " RX_ID_MASK0 ,RX ID Mask 0" "Not masked,Masked"
|
|
bitfld.long 0x00 7. " TX_ID_MASK7 ,TX ID Mask 7" "Not masked,Masked"
|
|
newline
|
|
bitfld.long 0x00 6. " TX_ID_MASK6 ,TX ID Mask 6" "Not masked,Masked"
|
|
bitfld.long 0x00 5. " TX_ID_MASK5 ,TX ID Mask 5" "Not masked,Masked"
|
|
bitfld.long 0x00 4. " TX_ID_MASK4 ,TX ID Mask 4" "Not masked,Masked"
|
|
newline
|
|
bitfld.long 0x00 3. " TX_ID_MASK3 ,TX ID Mask 3" "Not masked,Masked"
|
|
bitfld.long 0x00 2. " TX_ID_MASK2 ,TX ID Mask 2" "Not masked,Masked"
|
|
newline
|
|
bitfld.long 0x00 1. " TX_ID_MASK1 ,TX ID Mask 1" "Not masked,Masked"
|
|
bitfld.long 0x00 0. " TX_ID_MASK0 ,TX ID Mask 0" "Not masked,Masked"
|
|
else
|
|
hgroup.long 0x6C++0x3
|
|
hide.long 0x0 "LINMASK,LIN Mask Register"
|
|
endif
|
|
newline
|
|
if ((per.l.be(ad:0xFFF7E400+0x4)&0x40)==0x40)
|
|
group.long 0x70++0x3
|
|
line.long 0x0 "LINID,LIN Identification Register"
|
|
hexmask.long.byte 0x00 16.--23. 1. " RECEIVED_ID ,Received Identifier"
|
|
hexmask.long.byte 0x00 8.--15. 1. " ID_SLAVETASK_BYTE ,Identifier Slave Task Byte"
|
|
hexmask.long.byte 0x00 0.--7. 1. " ID_BYTE ,Identifier Byte"
|
|
else
|
|
hgroup.long 0x70++0x3
|
|
hide.long 0x0 "LINID,LIN Identification Register"
|
|
endif
|
|
group.long 0x74++0x07
|
|
line.long 0x0 "LINTD0,LIN Transmit Buffer 0 Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " TD0 ,8-bit Transmit Buffer 0"
|
|
hexmask.long.byte 0x00 16.--23. 1. " TD1 ,8-bit Transmit Buffer 1"
|
|
hexmask.long.byte 0x00 8.--15. 1. " TD2 ,8-bit Transmit Buffer 2"
|
|
hexmask.long.byte 0x00 0.--7. 1. " TD3 ,8-bit Transmit Buffer 3"
|
|
line.long 0x04 "LINTD1,LIN Transmit Buffer 1 Register"
|
|
hexmask.long.byte 0x04 24.--31. 1. " TD4 ,8-bit Transmit Buffer 4"
|
|
hexmask.long.byte 0x04 16.--23. 1. " TD5 ,8-bit Transmit Buffer 5"
|
|
hexmask.long.byte 0x04 8.--15. 1. " TD6 ,8-bit Transmit Buffer 6"
|
|
hexmask.long.byte 0x04 0.--7. 1. " TD7 ,8-bit Transmit Buffer 7"
|
|
tree.end
|
|
newline
|
|
if ((per.l.be(ad:0xFFF7E400+0x4)&0x40)==0x40)
|
|
group.long 0x7C++0x3
|
|
line.long 0x0 "MBRS,Maximum Baud Rate Selection Register"
|
|
hexmask.long.word 0x00 0.--12. 1. " MBR ,Maximum Baud Rate Prescaler"
|
|
else
|
|
hgroup.long 0x7C++0x3
|
|
hide.long 0x0 "MBRS,Maximum Baud Rate Selection Register"
|
|
endif
|
|
if ((per.l.be(ad:0xFFF7E400+0x4)&0x40)==0x40)
|
|
group.long 0x90++0x03
|
|
line.long 0x0 "IODFTCTRL,Input/Output Error Enable Register"
|
|
bitfld.long 0x00 31. " BEN ,Bit Error Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " PBEN ,Physical Bus Error Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " CEN ,Checksum Error Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " ISFE ,Inconsistent Synch Field Error Enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " FEN ,Frame Error Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 19.--20. " PSM ,PIN sample mask" "No mask,TBIT_CENTER,TBIT_CENTER + SCLK,TBIT_CENTER + 2 SCLK"
|
|
bitfld.long 0x00 16.--18. " TX_SHIFT ,Transmit Shift" "No delay,1 SCLK,2 SCLKs,3 SCLKs,4 SCLKs,5 SCLKs,6 SCLKs,7 SCLKs"
|
|
newline
|
|
bitfld.long 0x00 8.--11. " IODFTENA ,IO DFT Enable Key" "Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Enabled,Disabled,Disabled,Disabled,Disabled,Disabled"
|
|
bitfld.long 0x00 1. " LPBENA ,Module Loopback Enable" "Analog,Digital"
|
|
bitfld.long 0x00 0. " RXPENA ,Module Analog Loopback Through Receive/Transmit Pin Enable" "Transmit,Receive"
|
|
else
|
|
group.long 0x90++0x03
|
|
line.long 0x0 "IODFTCTRL,Input/Output Error Enable Register"
|
|
bitfld.long 0x00 26. " FEN ,Frame Error Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 25. " PEN ,Parity Error Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " BRKDTEN ,Break Detect Error Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 19.--20. " PSM ,PIN sample mask" "No mask,TBIT_CENTER,TBIT_CENTER + SCLK,TBIT_CENTER + 2 SCLK"
|
|
newline
|
|
bitfld.long 0x00 16.--18. " TX_SHIFT ,Transmit Shift" "No delay,1 SCLK,2 SCLKs,3 SCLKs,4 SCLKs,5 SCLKs,6 SCLKs,7 SCLKs"
|
|
bitfld.long 0x00 8.--11. " IODFTENA ,IO DFT Enable Key" "Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Enabled,Disabled,Disabled,Disabled,Disabled,Disabled"
|
|
bitfld.long 0x00 1. " LPBENA ,Module Loopback Enable" "Analog,Digital"
|
|
bitfld.long 0x00 0. " RXPENA ,Module Analog Loopback Through Receive/Transmit Pin Enable" "Transmit,Receive"
|
|
endif
|
|
endian.le
|
|
width 0x0B
|
|
tree.end
|
|
else
|
|
tree "SCI/LIN (Serial Communications Interface/Local Interconnect Network Module)"
|
|
base ad:0xFFF7E400
|
|
width 8.
|
|
group.long 0x00++0x3
|
|
line.long 0x0 "GCR0,Global Control Register"
|
|
bitfld.long 0x00 0. " RESET ,SCI Module Reset" "Under reset,Out of reset"
|
|
if ((d.l(ad:0xFFF7E400+0x4)&0x44)==0x44)
|
|
group.long 0x04++0x3
|
|
line.long 0x0 "GCR1,Global Control Register"
|
|
bitfld.long 0x00 25. " TXENA ,SCI Transmitter Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " RXENA ,SCI Receiver Enable" "Prevented,Allowed"
|
|
textline " "
|
|
bitfld.long 0x00 17. " CONT ,Continue on Suspend" "Frozen,Continue"
|
|
bitfld.long 0x00 16. " LOOP_BACK ,LOOP BACK Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " STOP_EXT_FRAME ,Stop Extended Frame Communication" "Not stopped,Stopped"
|
|
bitfld.long 0x00 12. " HGEN_CTRL ,LIN Mode Bit (Type of Mask Filtering Comparison)" "ID-Byte,ID-Slave task byte"
|
|
textline " "
|
|
bitfld.long 0x00 11. " CTYPE ,LIN Mode Bit (Classic/Enhanced)" "Classic,Enhanced"
|
|
bitfld.long 0x00 10. " MBUF_MODE ,Receive/Transmit Buffer Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " ADAPT ,LIN Mode Bit (Automatic Baudrate Adjustment)" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " SLEEP ,SCI Sleep Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " SW_nRESET ,Software Reset" "Reset,Ready"
|
|
bitfld.long 0x00 6. " LIN_MODE ,LIN MODE Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " CLOCK ,SCI Internal Clock Enable" "Slave,Master"
|
|
sif (cpu()!=("TMS570LS10116-ZWT")&&cpu()!=("TMS570LS10216-ZWT")&&cpu()!=("TMS570LS10106-ZWT")&&cpu()!=("TMS570LS10206-ZWT")&&cpu()!=("TMS570LS10116-PGE")&&cpu()!=("TMS570LS10216-PGE")&&cpu()!=("TMS570LS10106-PGE")&&cpu()!=("TMS570LS10206-PGE")&&!cpuis("TMS570LS1114*")&&!cpuis("TMS570LS1115*")&&!cpuis("TMS570LS1224*")&&!cpuis("TMS570LS1225*")&&!cpuis("TMS570LS1227*")&&cpu()!=("TMS570LS0332")&&cpu()!=("TMS570LS0432"))
|
|
bitfld.long 0x00 4. " STOP ,SCI Number of Stop Bits" "1 bit,2 bits"
|
|
textline " "
|
|
bitfld.long 0x00 3. " PARITY ,SCI Parity Odd/Even Selection" "Odd,Even"
|
|
endif
|
|
bitfld.long 0x00 2. " PARITY_ENA ,ID-Parity Enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpu()!=("TMS570LS10116-ZWT")&&cpu()!=("TMS570LS10216-ZWT")&&cpu()!=("TMS570LS10106-ZWT")&&cpu()!=("TMS570LS10206-ZWT")&&cpu()!=("TMS570LS10116-PGE")&&cpu()!=("TMS570LS10216-PGE")&&cpu()!=("TMS570LS10106-PGE")&&cpu()!=("TMS570LS10206-PGE")&&!cpuis("TMS570LS1114*")&&!cpuis("TMS570LS1115*")&&!cpuis("TMS570LS1224*")&&!cpuis("TMS570LS1225*")&&!cpuis("TMS570LS1227*")&&cpu()!=("TMS570LS0332")&&cpu()!=("TMS570LS0432"))
|
|
bitfld.long 0x00 1. " TIMING_MODE ,SCI Timing Mode Bit" "Synchronous,Asynchronous"
|
|
endif
|
|
bitfld.long 0x00 0. " COMM_MODE ,SCI/BLIN Communication Mode Bit ID4 and ID5 Use" "Not used,Used"
|
|
elif ((d.l(ad:0xFFF7E400+0x4)&0x44)==0x40)
|
|
group.long 0x04++0x3
|
|
line.long 0x0 "GCR1,Global Control Register"
|
|
bitfld.long 0x00 25. " TXENA ,SCI Transmitter Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " RXENA ,SCI Receiver Enable" "Prevented,Allowed"
|
|
textline " "
|
|
bitfld.long 0x00 17. " CONT ,Continue on Suspend" "Frozen,Continue"
|
|
bitfld.long 0x00 16. " LOOP_BACK ,LOOP BACK Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " STOP_EXT_FRAME ,Stop Extended Frame Communication" "Not stopped,Stopped"
|
|
bitfld.long 0x00 12. " HGEN_CTRL ,LIN Mode Bit (Type of Mask Filtering Comparison)" "ID-Byte,ID-SlaveTask"
|
|
textline " "
|
|
bitfld.long 0x00 11. " CTYPE ,LIN Mode Bit (Classic/Enhanced)" "Classic,Enhanced"
|
|
bitfld.long 0x00 10. " MBUF_MODE ,Receive/Transmit Buffer Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " ADAPT ,LIN Mode Bit (Automatic Baudrate Adjustment)" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " SLEEP ,SCI Sleep Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " SW_nRESET ,Software Reset" "Reset,Ready"
|
|
bitfld.long 0x00 6. " LIN_MODE ,LIN MODE Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " CLOCK ,SCI Internal Clock Enable" "Slave,Master"
|
|
sif (cpu()!=("TMS570LS10116-ZWT")&&cpu()!=("TMS570LS10216-ZWT")&&cpu()!=("TMS570LS10106-ZWT")&&cpu()!=("TMS570LS10206-ZWT")&&cpu()!=("TMS570LS10116-PGE")&&cpu()!=("TMS570LS10216-PGE")&&cpu()!=("TMS570LS10106-PGE")&&cpu()!=("TMS570LS10206-PGE")&&!cpuis("TMS570LS1114*")&&!cpuis("TMS570LS1115*")&&!cpuis("TMS570LS1224*")&&!cpuis("TMS570LS1225*")&&!cpuis("TMS570LS1227*")&&cpu()!=("TMS570LS0332")&&cpu()!=("TMS570LS0432"))
|
|
bitfld.long 0x00 4. " STOP ,SCI Number of Stop Bits" "1 bit,2 bits"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " PARITY_ENA ,ID-Parity Enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpu()!=("TMS570LS10116-ZWT")&&cpu()!=("TMS570LS10216-ZWT")&&cpu()!=("TMS570LS10106-ZWT")&&cpu()!=("TMS570LS10206-ZWT")&&cpu()!=("TMS570LS10116-PGE")&&cpu()!=("TMS570LS10216-PGE")&&cpu()!=("TMS570LS10106-PGE")&&cpu()!=("TMS570LS10206-PGE")&&!cpuis("TMS570LS1114*")&&!cpuis("TMS570LS1115*")&&!cpuis("TMS570LS1224*")&&!cpuis("TMS570LS1225*")&&!cpuis("TMS570LS1227*")&&cpu()!=("TMS570LS0332")&&cpu()!=("TMS570LS0432"))
|
|
bitfld.long 0x00 1. " TIMING_MODE ,SCI Timing Mode Bit" "Synchronous,Asynchronous"
|
|
endif
|
|
bitfld.long 0x00 0. " COMM_MODE ,SCI/BLIN Communication Mode Bit ID4 and ID5 Use" "Not used,Used"
|
|
elif (((d.l((ad:0xFFF7E400+0x4)))&0x44)==0x04)
|
|
group.long 0x04++0x3
|
|
line.long 0x0 "GCR1,Global Control Register"
|
|
bitfld.long 0x00 25. " TXENA ,SCI Transmitter Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " RXENA ,SCI Receiver Enable" "Prevented,Allowed"
|
|
textline " "
|
|
bitfld.long 0x00 17. " CONT ,Continue on Suspend" "Frozen,Continue"
|
|
bitfld.long 0x00 16. " LOOP_BACK ,LOOP BACK Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 10. " MBUF_MODE ,Receive/Transmit Buffer Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " SLEEP ,SCI Sleep Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " SW_nRESET ,Software Reset" "Reset,Ready"
|
|
bitfld.long 0x00 6. " LIN_MODE ,LIN MODE Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " CLOCK ,SCI Internal Clock Enable" "External,Internal"
|
|
bitfld.long 0x00 4. " STOP ,SCI Number of Stop Bits" "1 bit,2 bits"
|
|
textline " "
|
|
bitfld.long 0x00 3. " PARITY ,SCI Parity Odd/Even Selection" "Odd,Even"
|
|
bitfld.long 0x00 2. " PARITY_ENA ,Parity Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " TIMING_MODE ,SCI Timing Mode Bit" "Synchronous,Asynchronous"
|
|
bitfld.long 0x00 0. " COMM_MODE ,SCI/BLIN Communication Mode Bit" "Idle-line,Address-bit"
|
|
else
|
|
group.long 0x04++0x3
|
|
line.long 0x0 "GCR1,Global Control Register"
|
|
bitfld.long 0x00 25. " TXENA ,SCI Transmitter Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " RXENA ,SCI Receiver Enable" "Prevented,Allowed"
|
|
textline " "
|
|
bitfld.long 0x00 17. " CONT ,Continue on Suspend" "Frozen,Continue"
|
|
bitfld.long 0x00 16. " LOOP_BACK ,LOOP BACK Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 10. " MBUF_MODE ,Receive/Transmit Buffer Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " SLEEP ,SCI Sleep Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " SW_nRESET ,Software Reset" "Reset,Ready"
|
|
bitfld.long 0x00 6. " LIN_MODE ,LIN MODE Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " CLOCK ,SCI Internal Clock Enable" "External,Internal"
|
|
bitfld.long 0x00 4. " STOP ,SCI Number of Stop Bits" "1 bit,2 bits"
|
|
textline " "
|
|
bitfld.long 0x00 2. " PARITY_ENA ,Parity Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " TIMING_MODE ,SCI Timing Mode Bit" "Synchronous,Asynchronous"
|
|
bitfld.long 0x00 0. " COMM_MODE ,SCI/BLIN Communication Mode Bit" "Idle-line,Address-bit"
|
|
endif
|
|
width 8.
|
|
if ((d.l(ad:0xFFF7E400+0x4)&0x40)==0x40)
|
|
group.long 0x08++0x3
|
|
line.long 0x0 "GCR2,Global Control Register"
|
|
bitfld.long 0x00 17. " CC ,Compare Checksum" "No effect,Compared"
|
|
bitfld.long 0x00 16. " SC ,Send Checksum" "No effect,Compared"
|
|
textline " "
|
|
bitfld.long 0x00 8. " GEN_WU ,Generate Wakeup Signal" "No effect,Generated"
|
|
bitfld.long 0x00 0. " POWERDOWN ,POWERDOWN" "Normal,Local low-power"
|
|
else
|
|
group.long 0x08++0x3
|
|
line.long 0x0 "GCR2,Global Control Register"
|
|
sif (cpu()!="TMS570PSFC61")&&(cpu()!="TMS470MF031")&&(cpu()!="TMS470MF042")&&(cpu()!="TMS470MF066")&&cpu()!=("TMS570LS10116-ZWT")&&cpu()!=("TMS570LS10216-ZWT")&&cpu()!=("TMS570LS10106-ZWT")&&cpu()!=("TMS570LS10206-ZWT")&&cpu()!=("TMS570LS10116-PGE")&&cpu()!=("TMS570LS10216-PGE")&&cpu()!=("TMS570LS10106-PGE")&&cpu()!=("TMS570LS10206-PGE")&&cpu()!=("TMS570LS0332")&&cpu()!=("TMS570LS0432")&&!cpuis("TMS570LS1114*")&&!cpuis("TMS570LS1115*")&&!cpuis("TMS570LS1224*")&&!cpuis("TMS570LS1225*")&&!cpuis("TMS570LS1227*")
|
|
bitfld.long 0x00 8. " GEN_WU ,Generate Wakeup Signal" "No effect,Generated"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 0. " POWERDOWN ,POWERDOWN" "Normal,Local low-power"
|
|
endif
|
|
width 11.
|
|
tree "SCI Interrupt Registers"
|
|
if ((d.l(ad:0xFFF7E400+0x4)&0x40)==0x40)
|
|
group.long 0x0C++0x3
|
|
line.long 0x0 "SETINT,Interrupt Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x04 31. " BE_INT_set/clr ,Bit Error Interrupt" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x04 30. " PBE_INT_set/clr ,Physical Bus Error Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 29. 0x00 29. 0x04 29. " CE_INT_set/clr ,Checksum-Error Interrupt" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x04 28. " ISFE_INT_set/clr ,Inconsistent-Synch-Field-Error Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 27. 0x00 27. 0x04 27. " NRE_INT_set/clr ,No-Reponse-Error Interrupt" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x04 26. " FE_INT_set/clr ,Framing-Error Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x04 25. " OE_INT_set/clr ,Overrun-Error Interrupt" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x04 24. " PE_INT_set/clr ,Parity Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpu()!=("TMS570LS0332")&&cpu()!=("TMS570LS0432"))
|
|
setclrfld.long 0x00 17. 0x00 17. 0x04 17. " RX_DMA_set/clr ,Receive DMA" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x04 16. " TX_DMA_set/clr ,Transmit DMA" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
setclrfld.long 0x00 13. 0x00 13. 0x04 13. " ID_INT_set/clr ,ID Interrupt" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x04 9. " RX_INT_set/clr ,Receiver Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 8. 0x00 8. 0x04 8. " TX_INT_set/clr ,Transmitter Interrupt" "Disabled,Enabled"
|
|
setclrfld.long 0x00 7. 0x00 7. 0x04 7. " TOA3WUS_INT_set/clr ,Timeout After 3 Wakeup Signals Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 6. 0x00 6. 0x04 6. " TOAWUS_INT_set/clr ,Timeout After Wakeup Signal Interrupt" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x04 4. " TIMEOUT_INT_set/clr ,Timeout Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x04 1. " WAKEUP_INT_set/clr ,Wake-up Interrupt" "Disabled,Enabled"
|
|
else
|
|
group.long 0x0C++0x3
|
|
line.long 0x0 "SETINT,Interrupt Register"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x04 26. " FE_INT_set/clr ,Framing-Error Interrupt" "Disabled,Enabled"
|
|
setclrfld.long 0x00 25. 0x00 25. 0x04 25. " OE_INT_set/clr ,Overrun-Error Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 24. 0x00 24. 0x04 24. " PE_INT_set/clr ,Parity Interrupt" "Disabled,Enabled"
|
|
sif (cpu()!=("TMS570LS0332")&&cpu()!=("TMS570LS0432"))
|
|
setclrfld.long 0x00 18. 0x00 18. 0x04 18. " RX_DMA_ALL_set/clr ,Receive DMA All" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 17. 0x00 17. 0x04 17. " RX_DMA_set/clr ,Receive DMA" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x04 16. " TX_DMA_set/clr ,Transmit DMA" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
setclrfld.long 0x00 9. 0x00 9. 0x04 9. " RX_INT_set/clr ,Receiver Interrupt Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x04 8. " TX_INT_set/clr ,Transmitter Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x04 1. " WAKEUP_INT_set/clr ,Wake-up Interrupt" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x04 0. " BRKDT_INT_set/clr ,Break-detect Interrupt" "Disabled,Enabled"
|
|
endif
|
|
width 11.
|
|
if ((d.l(ad:0xFFF7E400+0x4)&0x40)==0x40)
|
|
group.long 0x14++0x3
|
|
line.long 0x0 "SETINTLVL,Interrupt Level Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x04 31. " BE_INT_LVL_set/clr ,Bit Error Interrupt Level" "INT0,INT1"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x04 30. " PBE_INT_LVL_set/clr ,Physical Bus Error Interrupt Level" "INT0,INT1"
|
|
textline " "
|
|
setclrfld.long 0x00 29. 0x00 29. 0x04 29. " CE_INT_LVL_set/clr ,Checksum-Error Interrupt Level" "INT0,INT1"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x04 28. " ISFE_INT_LVL_set/clr ,Inconsistent-Synch-Field-Error Interrupt Level" "INT0,INT1"
|
|
textline " "
|
|
setclrfld.long 0x00 27. 0x00 27. 0x04 27. " NRE_INT_LVL_set/clr ,No-Reponse-Error Interrupt Level" "INT0,INT1"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x04 26. " FE_INT_LVL_set/clr ,Framing-Error Interrupt Level" "INT0,INT1"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x04 25. " OE_INT_LVL_set/clr ,Overrun-Error Interrupt Level" "INT0,INT1"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x04 24. " PE_INT_LVL_set/clr ,Parity Error Interrupt Level" "INT0,INT1"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x04 13. " ID_INT_LVL_set/clr ,ID Interrupt Level" "INT0,INT1"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x04 9. " RX_INT_LVL_set/clr ,Receiver Interrupt Level" "INT0,INT1"
|
|
textline " "
|
|
setclrfld.long 0x00 8. 0x00 8. 0x04 8. " TX_INT_LVL_set/clr ,Transmitter Interrupt Level" "INT0,INT1"
|
|
setclrfld.long 0x00 7. 0x00 7. 0x04 7. " TOA3WUS_INT_LVL_set/clr ,Timeout After 3 Wakeup Signals Interrupt" "INT0,INT1"
|
|
textline " "
|
|
setclrfld.long 0x00 6. 0x00 6. 0x04 6. " TOAWUS_INT_LVL_set/clr ,Timeout After Wakeup Signal Interrupt Level" "INT0,INT1"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x04 4. " TIMEOUT_INT_LVL_set/clr ,Timeout Interrupt Level" "INT0,INT1"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x04 1. " WAKEUP_INT_LVL_set/clr ,Wake-up Interrupt Level" "INT0,INT1"
|
|
else
|
|
group.long 0x14++0x3
|
|
line.long 0x0 "SETINTLVL,Interrupt Level Register"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x04 26. " FE_INT_LVL_set/clr ,Framing-Error Interrupt Level" "INT0,INT1"
|
|
setclrfld.long 0x00 25. 0x00 25. 0x04 25. " OE_INT_LVL_set/clr ,Overrun-Error Interrupt Level" "INT0,INT1"
|
|
textline " "
|
|
setclrfld.long 0x00 24. 0x00 24. 0x04 24. " PE_INT_LVL_set/clr ,Parity Error Interrupt Level" "INT0,INT1"
|
|
sif (cpu()!=("TMS570LS0332")&&cpu()!=("TMS570LS0432"))
|
|
setclrfld.long 0x00 18. 0x00 18. 0x04 18. " RX_DMA_ALL_INT_LVL_set/clr ,Receive DMA All Interrupt Level" "INT0,INT1"
|
|
endif
|
|
textline " "
|
|
setclrfld.long 0x00 9. 0x00 9. 0x04 9. " RX_INT_LVL_set/clr ,Receiver Interrupt Level" "INT0,INT1"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x04 8. " TX_INT_LVL_set/clr ,Transmitter Interrupt Level" "INT0,INT1"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x04 1. " WAKEUP_INT_LVL_set/clr ,Wake-up Interrupt Level" "INT0,INT1"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x04 0. " BRKDT_INT_set/clr ,Break-Detect Interrupt Level" "INT0,INT1"
|
|
endif
|
|
tree.end
|
|
width 8.
|
|
if ((d.l(ad:0xFFF7E400+0x4)&0x40)==0x40)
|
|
group.long 0x1C++0x3
|
|
line.long 0x0 "FLR,Flags Register"
|
|
eventfld.long 0x00 31. " BE ,Bit Error Flag" "Not detected,Detected"
|
|
eventfld.long 0x00 30. " PBE ,Physiscal Bus Error Flag" "Not detected,Detected"
|
|
textline " "
|
|
eventfld.long 0x00 29. " CE ,Checksum Error Flag" "Not detected,Detected"
|
|
eventfld.long 0x00 28. " ISFE ,Inconsistent Synch Field Error Flag" "Not detected,Detected"
|
|
textline " "
|
|
eventfld.long 0x00 27. " NRE ,No-Response Error Flag" "Not detected,Detected"
|
|
eventfld.long 0x00 26. " FE ,Framing Error Flag" "Not detected,Detected"
|
|
textline " "
|
|
eventfld.long 0x00 25. " OE ,Overrun Error Flag" "Not detected,Detected"
|
|
eventfld.long 0x00 24. " PE ,Parity Error Flag" "Not detected,Detected"
|
|
textline " "
|
|
eventfld.long 0x00 14. " ID_RX_FLAG ,Identifier On Receive Flag" "Not received,Received"
|
|
eventfld.long 0x00 13. " ID_TX_FLAG ,Identifier On Transmit Flag" "Not received,Received"
|
|
textline " "
|
|
bitfld.long 0x00 11. " TX_EMPTY ,Transmitter Empty Flag" "Not empty,Empty"
|
|
eventfld.long 0x00 9. " RXRDY ,Receiver Ready Flag" "Not ready,Ready"
|
|
textline " "
|
|
bitfld.long 0x00 8. " TXRDY ,Transmitter Buffer Register Ready Flag" "Full,Ready"
|
|
eventfld.long 0x00 7. " TOA3WUS ,Timeout After 3 Wakeup Signals Flag" "No timeout,Timeout"
|
|
textline " "
|
|
eventfld.long 0x00 6. " TOAWUS ,Timeout After Wakeup Signal Flag" "No timeout,Timeout"
|
|
eventfld.long 0x00 4. " TIMEOUT ,LIN Bus IDLE Timeout Flag" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 3. " BUSY_FLAG ,BUSY Flag" "Not busy,Busy"
|
|
eventfld.long 0x00 1. " WAKEUP ,Wake-up Flag" "No wake up,Wake up"
|
|
else
|
|
group.long 0x1C++0x3
|
|
line.long 0x0 "FLR,Flags Register"
|
|
sif (cpu()!="TMS570PSFC61")&&(cpu()!="TMS470MF031")&&(cpu()!="TMS470MF042")&&(cpu()!="TMS470MF066")&&cpu()!=("TMS570LS10116-ZWT")&&cpu()!=("TMS570LS10216-ZWT")&&cpu()!=("TMS570LS10106-ZWT")&&cpu()!=("TMS570LS10206-ZWT")&&cpu()!=("TMS570LS10116-PGE")&&cpu()!=("TMS570LS10216-PGE")&&cpu()!=("TMS570LS10106-PGE")&&cpu()!=("TMS570LS10206-PGE")&&cpu()!=("TMS570LS0332")&&cpu()!=("TMS570LS0432")&&!cpuis("TMS570LS1114*")&&!cpuis("TMS570LS1115*")&&!cpuis("TMS570LS1224*")&&!cpuis("TMS570LS1225*")&&!cpuis("TMS570LS1227*")
|
|
eventfld.long 0x00 31. " BE ,Bit Error Flag" "Not detected,Detected"
|
|
textline " "
|
|
endif
|
|
eventfld.long 0x00 26. " FE ,Framing Error Flag" "Not detected,Detected"
|
|
textline " "
|
|
eventfld.long 0x00 25. " OE ,Overrun Error Flag" "Not detected,Detected"
|
|
eventfld.long 0x00 24. " PE ,Parity Error Flag" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 12. " RXWAKE ,Receiver Wakeup Detect Flag" "Not address,Address"
|
|
bitfld.long 0x00 11. " TX_EMPTY ,Transmitter Empty Flag" "Not empty,Empty"
|
|
textline " "
|
|
bitfld.long 0x00 10. " TXWAKE ,SCI Transmitter Wakeup Method Select" "Data,Address"
|
|
eventfld.long 0x00 9. " RXRDY ,Receiver Ready Flag" "Not ready,Ready"
|
|
textline " "
|
|
bitfld.long 0x00 8. " TXRDY ,Transmitter Buffer Register Ready Flag (SCITD)" "Full,Ready"
|
|
bitfld.long 0x00 3. " BUSY_FLAG ,BUSY Flag" "Not busy,Busy"
|
|
textline " "
|
|
bitfld.long 0x00 2. " IDLE ,SCI Receiver in Idle State" "Not detected,Detected"
|
|
sif (cpu()!="TMS570PSFC61")&&(cpu()!="TMS470MF031")&&(cpu()!="TMS470MF042")&&(cpu()!="TMS470MF066")&&cpu()!=("TMS570LS10116-ZWT")&&cpu()!=("TMS570LS10216-ZWT")&&cpu()!=("TMS570LS10106-ZWT")&&cpu()!=("TMS570LS10206-ZWT")&&cpu()!=("TMS570LS10116-PGE")&&cpu()!=("TMS570LS10216-PGE")&&cpu()!=("TMS570LS10106-PGE")&&cpu()!=("TMS570LS10206-PGE")&&cpu()!=("TMS570LS0332")&&!cpuis("TMS570LS0432")&&!cpuis("TMS570LS1114*")&&!cpuis("TMS570LS1115*")&&!cpuis("TMS570LS1224*")&&!cpuis("TMS570LS1225*")&&!cpuis("TMS570LS1227*")
|
|
eventfld.long 0x00 1. " WAKEUP ,Wake-up Flag" "No wake up,Wake up"
|
|
endif
|
|
textline " "
|
|
eventfld.long 0x00 0. " BRKDT ,SCI Break-Detect Flag" "Not detected,Detected"
|
|
endif
|
|
width 9.
|
|
tree "SCI Interrupt Vector Offset Registers"
|
|
hgroup.long 0x20++0x3
|
|
hide.long 0x0 "INVECT0,Interrupt Vector Offset 0"
|
|
in
|
|
hgroup.long 0x24++0x3
|
|
hide.long 0x0 "INVECT1,Interrupt Vector Offset 1"
|
|
in
|
|
tree.end
|
|
width 8.
|
|
if ((d.l(ad:0xFFF7E400+0x4)&0x40)==0x40)
|
|
group.long 0x28++0x3
|
|
line.long 0x0 "FORMAT,Format Control Register"
|
|
bitfld.long 0x00 16.--18. " LENGTH ,Frame Length Control Bits" "1 byte,2 bytes,3 bytes,4 bytes,5 bytes,6 bytes,7 bytes,8 bytes"
|
|
elif (((d.l(ad:0xFFF7E400+0x4)&0x40)==0x0)&&(((d.l((ad:0xFFF7E400+0x04)))&0x0400)==0x0400))
|
|
group.long 0x28++0x3
|
|
line.long 0x0 "FORMAT,Format Control Register"
|
|
bitfld.long 0x00 16.--18. " LENGTH ,Frame Length Control Bits" "1 character,2 characters,3 characters,4 characters,5 characters,6 characters,7 characters,8 characters"
|
|
bitfld.long 0x00 0.--2. " CHAR ,Character Length Control Bits" "1 bit,2 bits,3 bits,4 bits,5 bits,6 bits,7 bits,8 bits"
|
|
else
|
|
group.long 0x28++0x3
|
|
line.long 0x0 "FORMAT,Format Control Register"
|
|
bitfld.long 0x00 0.--2. " CHAR ,Character Length Control Bits" "1 bit,2 bits,3 bits,4 bits,5 bits,6 bits,7 bits,8 bits"
|
|
endif
|
|
group.long 0x2C++0x3
|
|
line.long 0x0 "BRSR,Baud Rate Selection Register"
|
|
hexmask.long.byte 0x00 28.--30. 1. " U ,SCI/BLIN Super Fractional Divider Selection"
|
|
hexmask.long.byte 0x00 24.--27. 1. " M ,SCI/BLIN 4-bit Fractional Divider Selection"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " PRESCALER_P ,SCI/BLIN 24-bit Integer Prescaler Selection"
|
|
width 4.
|
|
tree "SCI Data Buffer Registers"
|
|
rgroup.long 0x30++0x3
|
|
line.long 0x0 "ED,SCI Data Buffer"
|
|
hexmask.long.byte 0x00 0.--7. 1. " ED ,Emulation Data"
|
|
hgroup.long 0x34++0x3
|
|
hide.long 0x0 "RD,SCI Data Buffer"
|
|
in
|
|
group.long 0x38++0x3
|
|
line.long 0x0 "TD,SCI Data Buffer"
|
|
hexmask.long.byte 0x00 0.--7. 1. " TD ,Transmit Data"
|
|
tree.end
|
|
tree "SCI Pin I/O Control Registers"
|
|
width 6.
|
|
if ((d.l(ad:0xFFF7E400+0x4)&0x40)==0x40)
|
|
group.long 0x3C++0x3
|
|
line.long 0x0 "PIO0,Pin I/O Control Register 0"
|
|
bitfld.long 0x00 2. " TX_FUNC ,Defines the Function of Pin SCITX" "GPIO,SCITX"
|
|
bitfld.long 0x00 1. " RX_FUNC ,Defines the Function of Pin SCIRX" "GPIO,SCIRX"
|
|
sif (cpu()!="TMS570PSFC61"&&cpu()!="TMS570LC4357"&&cpu()!=("TMS570LS0332")&&cpu()!=("TMS570LS0432")&&!cpuis("TMS570LS1114*")&&!cpuis("TMS570LS1115*")&&!cpuis("TMS570LS1224*")&&!cpuis("TMS570LS1225*")&&!cpuis("TMS570LS1227*")&&!cpuis("TMS570LS21*")&&!cpuis("TMS570LS31*"))
|
|
textline " "
|
|
bitfld.long 0x00 0. " CLK_FUNC ,Clock Function" "GPIO,?..."
|
|
endif
|
|
else
|
|
group.long 0x3C++0x3
|
|
line.long 0x0 "PIO0,Pin I/O Control Register 0"
|
|
bitfld.long 0x00 2. " TX_FUNC ,Defines the Function of Pin SCITX" "GPIO,SCITX"
|
|
bitfld.long 0x00 1. " RX_FUNC ,Defines the Function of Pin SCIRX" "GPIO,SCIRX"
|
|
sif (cpu()!="TMS570PSFC61"&&cpu()!="TMS570LC4357"&&cpu()!=("TMS570LS0332")&&cpu()!=("TMS570LS0432")&&!cpuis("TMS570LS1114*")&&!cpuis("TMS570LS1115*")&&!cpuis("TMS570LS1224*")&&!cpuis("TMS570LS1225*")&&!cpuis("TMS570LS1227*")&&!cpuis("TMS570LS21*")&&!cpuis("TMS570LS31*"))
|
|
textline " "
|
|
bitfld.long 0x00 0. " CLK_FUNC ,Clock Function" "GPIO,SCICLK"
|
|
endif
|
|
endif
|
|
sif (cpu()!="TMS570PSFC61"&&cpu()!="TMS570LC4357")
|
|
if ((d.l(ad:0xFFF7E400+0x3c)&0x1)==0x0)
|
|
group.long 0x40++0x3
|
|
line.long 0x0 "PIO1,Pin I/O Control Register 1"
|
|
bitfld.long 0x00 2. " TX_DIR ,Transmit Direction" "Input,Output"
|
|
bitfld.long 0x00 1. " RX_DIR ,Receive Direction" "Input,Output"
|
|
sif (cpu()!=("TMS570LS0332")&&cpu()!=("TMS570LS0432")&&!cpuis("TMS570LS1114*")&&!cpuis("TMS570LS1115*")&&!cpuis("TMS570LS1224*")&&!cpuis("TMS570LS1225*")&&!cpuis("TMS570LS1227*")&&!cpuis("TMS570LS21*")&&!cpuis("TMS570LS31*"))
|
|
textline " "
|
|
bitfld.long 0x00 0. " CLK_DIR ,Clock Data Direction" "Input,Output"
|
|
endif
|
|
elif (((d.l(ad:0xFFF7E400+0x3c)&0x1)==0x1)&&((d.l(ad:0xFFF7E400+0x4)&0x60)==0x20))
|
|
group.long 0x40++0x3
|
|
line.long 0x0 "PIO1,Pin I/O Control Register 1"
|
|
bitfld.long 0x00 2. " TX_DIR ,Transmit Direction" "Input,Output"
|
|
bitfld.long 0x00 1. " RX_DIR ,Receive Direction" "Input,Output"
|
|
sif (cpu()!=("TMS570LS0332")&&cpu()!=("TMS570LS0432")&&!cpuis("TMS570LS1114*")&&!cpuis("TMS570LS1115*")&&!cpuis("TMS570LS1224*")&&!cpuis("TMS570LS1225*")&&!cpuis("TMS570LS1227*")&&!cpuis("TMS570LS21*")&&!cpuis("TMS570LS31*"))
|
|
textline " "
|
|
bitfld.long 0x00 0. " CLK_DIR ,Clock Data Direction" "Not output,Output"
|
|
endif
|
|
elif (((d.l(ad:0xFFF7E400+0x3c)&0x1)==0x1)&&((d.l(ad:0xFFF7E400+0x4)&0x60)==0x0))
|
|
group.long 0x40++0x3
|
|
line.long 0x0 "PIO1,Pin I/O Control Register 1"
|
|
bitfld.long 0x00 2. " TX_DIR ,Transmit Direction" "Input,Output"
|
|
bitfld.long 0x00 1. " RX_DIR ,Receive Direction" "Input,Output"
|
|
sif (cpu()!=("TMS570LS0332")&&cpu()!=("TMS570LS0432")&&!cpuis("TMS570LS1114*")&&!cpuis("TMS570LS1115*")&&!cpuis("TMS570LS1224*")&&!cpuis("TMS570LS1225*")&&!cpuis("TMS570LS1227*")&&!cpuis("TMS570LS21*")&&!cpuis("TMS570LS31*"))
|
|
textline " "
|
|
bitfld.long 0x00 0. " CLK_DIR ,Clock Data Direction" "Input,Not input"
|
|
endif
|
|
else
|
|
group.long 0x40++0x3
|
|
line.long 0x0 "PIO1,Pin I/O Control Register 1"
|
|
bitfld.long 0x00 2. " TX_DIR ,Transmit Direction" "Input,Output"
|
|
bitfld.long 0x00 1. " RX_DIR ,Receive Direction" "Input,Output"
|
|
sif (cpu()!=("TMS570LS0332")&&cpu()!=("TMS570LS0432")&&!cpuis("TMS570LS1114*")&&!cpuis("TMS570LS1115*")&&!cpuis("TMS570LS1224*")&&!cpuis("TMS570LS1225*")&&!cpuis("TMS570LS1227*")&&!cpuis("TMS570LS21*")&&!cpuis("TMS570LS31*"))
|
|
textline " "
|
|
bitfld.long 0x00 0. " CLK_DIR ,Clock Data Direction" "Input,Output"
|
|
endif
|
|
endif
|
|
else
|
|
group.long 0x40++0x3
|
|
line.long 0x0 "PIO1,Pin I/O Control Register 1"
|
|
bitfld.long 0x00 2. " TX_DIR ,Transmit Direction" "Input,Output"
|
|
bitfld.long 0x00 1. " RX_DIR ,Receive Direction" "Input,Output"
|
|
endif
|
|
rgroup.long 0x44++0x3
|
|
line.long 0x0 "PIO2,Pin I/O Control Register 2"
|
|
bitfld.long 0x00 2. " TX_IN ,Contains Current Value on the SCITX Pin" "Low,High"
|
|
bitfld.long 0x00 1. " RX_IN ,Contains Current Value on the SCIRX Pin" "Low,High"
|
|
sif (cpu()!="TMS570PSFC61"&&cpu()!="TMS570LC4357"&&cpu()!=("TMS570LS0332")&&cpu()!=("TMS570LS0432")&&!cpuis("TMS570LS1114*")&&!cpuis("TMS570LS1115*")&&!cpuis("TMS570LS1224*")&&!cpuis("TMS570LS1225*")&&!cpuis("TMS570LS1227*"))
|
|
textline " "
|
|
bitfld.long 0x00 0. " CLK_IN ,Contains the Current Value on Pin SCICLK" "Low,High"
|
|
endif
|
|
width 6.
|
|
group.long 0x48++0x3
|
|
line.long 0x0 "PIO3,Pin I/O Control Register 3"
|
|
setclrfld.long 0x00 2. 0x04 2. 0x08 2. " TX_OUT_set/clr ,SCITX Pin Data Output" "Low,High"
|
|
setclrfld.long 0x00 1. 0x04 1. 0x08 1. " RX_OUT_set/clr ,SCIRX Pin Data Output" "Low,High"
|
|
sif (cpu()!="TMS570PSFC61"&&cpu()!="TMS570LC4357"&&cpu()!=("TMS570LS0332")&&cpu()!=("TMS570LS0432")&&!cpuis("TMS570LS1114*")&&!cpuis("TMS570LS1115*")&&!cpuis("TMS570LS1224*")&&!cpuis("TMS570LS1225*")&&!cpuis("TMS570LS1227*")&&!cpuis("TMS570LS21*")&&!cpuis("TMS570LS31*"))
|
|
textline " "
|
|
setclrfld.long 0x00 0. 0x00 0. 0x08 0. " CLK_OUT_set/clr ,SCICLK Pin Data Output" "Low,High"
|
|
endif
|
|
sif cpuis("TMS570LS21*")||cpuis("TMS570LS31*")
|
|
group.long 0x4C++0x3
|
|
line.long 0x0 "PIO4,Pin I/O Control Register 4"
|
|
bitfld.long 0x00 2. " TX_DIR ,Transmit Direction" "Input,Output"
|
|
bitfld.long 0x00 1. " RX_DIR ,Receive Direction" "Input,Output"
|
|
group.long 0x50++0x3
|
|
line.long 0x0 "PIO5,Pin I/O Control Register 5"
|
|
bitfld.long 0x00 2. " TX_DIR ,Transmit Direction" "Input,Output"
|
|
bitfld.long 0x00 1. " RX_DIR ,Receive Direction" "Input,Output"
|
|
endif
|
|
width 6.
|
|
group.long 0x54++0x3
|
|
line.long 0x0 "PIO6,Pin I/O Control Register 6"
|
|
bitfld.long 0x00 2. " TX_ODR ,TX Open Drain Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " RX_ODR ,RX Open Drain Enable" "Disabled,Enabled"
|
|
sif (cpu()!="TMS570PSFC61"&&cpu()!="TMS570LC4357"&&cpu()!=("TMS570LS0332")&&cpu()!=("TMS570LS0432")&&!cpuis("TMS570LS1114*")&&!cpuis("TMS570LS1115*")&&!cpuis("TMS570LS1224*")&&!cpuis("TMS570LS1225*")&&!cpuis("TMS570LS1227*")&&!cpuis("TMS570LS21*")&&!cpuis("TMS570LS31*"))
|
|
textline " "
|
|
bitfld.long 0x00 0. " CLK_ODR ,CLK Open Drain Enable" "Disabled,Enabled"
|
|
endif
|
|
group.long 0x58++0x3
|
|
line.long 0x0 "PIO7,Pin I/O Control Register 7"
|
|
bitfld.long 0x00 2. " TX_PD ,TX Pin Pull Control Disable" "No,Yes"
|
|
bitfld.long 0x00 1. " RX_PD ,RX Pin Pull Control Disable" "No,Yes"
|
|
sif (cpu()!="TMS570PSFC61"&&cpu()!="TMS570LC4357"&&cpu()!=("TMS570LS0332")&&cpu()!=("TMS570LS0432")&&cpu()!=("TMS570LS1114*")&&cpu()!=("TMS570LS1115*")&&cpu()!=("TMS570LS1224*")&&cpu()!=("TMS570LS1225*")&&cpu()!=("TMS570LS1227*")&&!cpuis("TMS570LS21*")&&!cpuis("TMS570LS31*"))
|
|
textline " "
|
|
bitfld.long 0x00 0. " CLK_PD ,CLK Pin Pull Control Disable" "No,Yes"
|
|
endif
|
|
group.long 0x5C++0x3
|
|
line.long 0x0 "PIO8,Pin I/O Control Register 8"
|
|
bitfld.long 0x00 2. " TX_PSL ,TX Pin Pull Select" "Pull down,Pull up"
|
|
bitfld.long 0x00 1. " RX_PSL ,RX Pin Pull Select" "Pull down,Pull up"
|
|
sif (cpu()!="TMS570PSFC61"&&cpu()!="TMS570LC4357"&&cpu()!=("TMS570LS0332")&&cpu()!=("TMS570LS0432")&&!cpuis("TMS570LS1114*")&&!cpuis("TMS570LS1115*")&&!cpuis("TMS570LS1224*")&&!cpuis("TMS570LS1225*")&&!cpuis("TMS570LS1227*")&&!cpuis("TMS570LS21*")&&!cpuis("TMS570LS31*"))
|
|
textline " "
|
|
bitfld.long 0x00 0. " CLK_PSL ,CLK Pin Pull Select" "Pull down,Pull up"
|
|
endif
|
|
tree.end
|
|
tree "BLIN Registers"
|
|
width 9.
|
|
if ((d.l(ad:0xFFF7E400+0x4)&0x40)==0x40)
|
|
group.long 0x60++0x3
|
|
line.long 0x0 "LINCOMP,BLINCOMPARE Register"
|
|
bitfld.long 0x00 8.--9. " SDEL ,2-bit Synch Delimiter Compare" "1 bit,2 bits,3 bits,4 bits"
|
|
bitfld.long 0x00 0.--2. " SBREAK ,3-bit Synch Break Extend" "Not extended,1 bit,2 bits,3 bits,4 bits,5 bits,6 bits,7 bits"
|
|
else
|
|
hgroup.long 0x60++0x3
|
|
hide.long 0x0 "LINCOMP,BLINCOMPARE Register"
|
|
endif
|
|
sif (cpu()!="TMS570LC4357"&&cpu()!=("TMS570LS0332")&&cpu()!=("TMS570LS0432"))
|
|
hgroup.long 0x64++0x3
|
|
hide.long 0x0 "LINRD0,LINRD0 Register"
|
|
in
|
|
hgroup.long 0x68++0x3
|
|
hide.long 0x0 "LINRD1,LINRD1 Register"
|
|
in
|
|
else
|
|
rgroup.long 0x64++0x3
|
|
line.long 0x0 "LINRD0,LINRD0 Register"
|
|
hexmask.long.byte 0x00 24.--31. 0x1 " RD0 ,Receive Buffer 0"
|
|
hexmask.long.byte 0x00 16.--23. 0x1 " RD1 ,Receive Buffer 1"
|
|
hexmask.long.byte 0x00 8.--15. 0x1 " RD2 ,Receive Buffer 2"
|
|
hexmask.long.byte 0x00 0.--7. 0x1 " RD3 ,Receive Buffer 3"
|
|
rgroup.long 0x68++0x3
|
|
line.long 0x0 "LINRD1,LINRD1 Register"
|
|
hexmask.long.byte 0x00 24.--31. 0x1 " RD4 ,Receive Buffer 4"
|
|
hexmask.long.byte 0x00 16.--23. 0x1 " RD5 , Receive Buffer 5"
|
|
hexmask.long.byte 0x00 8.--15. 0x1 " RD6 ,Receive Buffer 6"
|
|
hexmask.long.byte 0x00 0.--7. 0x1 " RD7 ,Receive Buffer 7"
|
|
endif
|
|
width 9.
|
|
if ((d.l(ad:0xFFF7E400+0x4)&0x40)==0x40)
|
|
group.long 0x6C++0x3
|
|
line.long 0x0 "LINMASK,LINMASK Register"
|
|
bitfld.long 0x00 23. " RX_ID_MASK7 ,RX ID Mask 7" "Not masked,Masked"
|
|
bitfld.long 0x00 22. " RX_ID_MASK6 ,RX ID Mask 6" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 21. " RX_ID_MASK5 ,RX ID Mask 5" "Not masked,Masked"
|
|
bitfld.long 0x00 20. " RX_ID_MASK4 ,RX ID Mask 4" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 19. " RX_ID_MASK3 ,RX ID Mask 3" "Not masked,Masked"
|
|
bitfld.long 0x00 18. " RX_ID_MASK2 ,RX ID Mask 2" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 17. " RX_ID_MASK1 ,RX ID Mask 1" "Not masked,Masked"
|
|
bitfld.long 0x00 16. " RX_ID_MASK0 ,RX ID Mask 0" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 7. " TX_ID_MASK7 ,TX ID Mask 7" "Not masked,Masked"
|
|
bitfld.long 0x00 6. " TX_ID_MASK6 ,TX ID Mask 6" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 5. " TX_ID_MASK5 ,TX ID Mask 5" "Not masked,Masked"
|
|
bitfld.long 0x00 4. " TX_ID_MASK4 ,TX ID Mask 4" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 3. " TX_ID_MASK3 ,TX ID Mask 3" "Not masked,Masked"
|
|
bitfld.long 0x00 2. " TX_ID_MASK2 ,TX ID Mask 2" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 1. " TX_ID_MASK1 ,TX ID Mask 1" "Not masked,Masked"
|
|
bitfld.long 0x00 0. " TX_ID_MASK0 ,TX ID Mask 0" "Not masked,Masked"
|
|
else
|
|
hgroup.long 0x6C++0x3
|
|
hide.long 0x0 "LINMASK,LINMASK Register"
|
|
endif
|
|
width 9.
|
|
if ((d.l(ad:0xFFF7E400+0x4)&0x40)==0x40)
|
|
group.long 0x70++0x3
|
|
line.long 0x0 "LINID,LINID Register"
|
|
hexmask.long.byte 0x00 16.--23. 1. " RECEIVED_ID ,Received Identifier"
|
|
hexmask.long.byte 0x00 8.--15. 1. " ID_SLAVETASK_BYTE ,Identifier Slave Task Byte"
|
|
hexmask.long.byte 0x00 0.--7. 1. " ID_BYTE ,Identifier Byte"
|
|
else
|
|
hgroup.long 0x70++0x3
|
|
hide.long 0x0 "LINID,LINID Register"
|
|
endif
|
|
width 9.
|
|
group.long 0x74++0x3
|
|
line.long 0x0 "LINTD0,LINTD0 Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " TD0 ,8-bit Transmit Buffer 0"
|
|
hexmask.long.byte 0x00 16.--23. 1. " TD1 ,8-bit Transmit Buffer 1"
|
|
hexmask.long.byte 0x00 8.--15. 1. " TD2 ,8-bit Transmit Buffer 2"
|
|
hexmask.long.byte 0x00 0.--7. 1. " TD3 ,8-bit Transmit Buffer 3"
|
|
group.long 0x78++0x3
|
|
line.long 0x0 "LINTD1,LINTD1 Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " TD4 ,8-bit Transmit Buffer 4"
|
|
hexmask.long.byte 0x00 16.--23. 1. " TD5 ,8-bit Transmit Buffer 5"
|
|
hexmask.long.byte 0x00 8.--15. 1. " TD6 ,8-bit Transmit Buffer 6"
|
|
hexmask.long.byte 0x00 0.--7. 1. " TD7 ,8-bit Transmit Buffer 7"
|
|
tree.end
|
|
width 11.
|
|
if ((d.l(ad:0xFFF7E400+0x4)&0x40)==0x40)
|
|
group.long 0x7C++0x3
|
|
line.long 0x0 "MBRSR,Maximum Baud Rate Selection Register"
|
|
hexmask.long.word 0x00 0.--12. 1. " MBR ,Maximum Baud Rate Prescaler"
|
|
else
|
|
hgroup.long 0x7C++0x3
|
|
hide.long 0x0 "MBRSR,Maximum Baud Rate Selection Register"
|
|
endif
|
|
sif (cpu()!="TMS470MF031")&&(cpu()!="TMS470MF042")&&(cpu()!="TMS470MF066")&&cpu()!=("TMS570LS10116-ZWT")&&cpu()!=("TMS570LS10216-ZWT")&&cpu()!=("TMS570LS10106-ZWT")&&cpu()!=("TMS570LS10206-ZWT")&&cpu()!=("TMS570LS10116-PGE")&&cpu()!=("TMS570LS10216-PGE")&&cpu()!=("TMS570LS10106-PGE")&&cpu()!=("TMS570LS10206-PGE")&&(cpu()!="TMS570LC4357")&&cpu()!=("TMS570LS0332")&&cpu()!=("TMS570LS0432")&&!cpuis("TMS570LS1114*")&&!cpuis("TMS570LS1115*")&&!cpuis("TMS570LS1224*")&&!cpuis("TMS570LS1225*")&&!cpuis("TMS570LS1227*")&&!cpuis("TMS570LS21*")&&!cpuis("TMS570LS31*")
|
|
group.long 0x80++0x3
|
|
line.long 0x0 "PIO9,Pin I/O Control Register 9"
|
|
bitfld.long 0x00 2. " TX_SL ,This Bit Controls the Slew Rate for the SCITX Pin" "Normal,Slew"
|
|
bitfld.long 0x00 1. " RX_SL ,This Bit Controls the Slew Rate for the SCIRX Pin" "Normal,Slew"
|
|
sif (cpu()!="TMS570PSFC61")
|
|
bitfld.long 0x00 0. " CLK_SL ,This Bit Controls the Slew Rate for the SCICLK Pin" "Normal,Slew"
|
|
endif
|
|
endif
|
|
width 11.
|
|
if ((d.l(ad:0xFFF7E400+0x4)&0x40)==0x40)
|
|
group.long 0x90++0x3
|
|
line.long 0x0 "IODFTCTRL,IODFT for BLIN Moduler"
|
|
bitfld.long 0x00 31. " BEEN ,Bit Error Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " PBEEN ,Physical Bus Error Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 29. " CEEN ,Checksum Error Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " ISFEEN ,Inconsistent Synch Field Error Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 26. " FEEN ,Frame Error Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 19.--20. " PSM ,PIN SAMPLE MASK" "No mask,TBIT_CENTER,TBIT_CENTER + SCLK,TBIT_CENTER + 2 SCLK"
|
|
textline " "
|
|
bitfld.long 0x00 16.--18. " TX_SHIFT ,Transmit Shift" "No delay,1 SCLK,2 SCLKs,3 SCLKs,4 SCLKs,5 SCLKs,6 SCLKs,7 SCLKs"
|
|
bitfld.long 0x00 8.--11. " IODFTENA ,IO DFT Enable Key" "Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Enabled,Disabled,Disabled,Disabled,Disabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " LPBENA ,Module Loopback Enable" "Analog,Digital"
|
|
bitfld.long 0x00 0. " RXPENA ,Module Analog Loopback Through Receive/Transmit Pin Enable" "Transmit,Receive"
|
|
else
|
|
group.long 0x90++0x3
|
|
line.long 0x0 "IODFTCTRL,IODFT for BLIN Moduler"
|
|
bitfld.long 0x00 26. " FEEN ,Frame Error Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 25. " PEEN ,Parity Error Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 24. " BDEEN ,Break Detect Error Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 19.--20. " PSM ,PIN SAMPLE MASK" "No mask,TBIT_CENTER,TBIT_CENTER + SCLK,TBIT_CENTER + 2 SCLK"
|
|
textline " "
|
|
bitfld.long 0x00 16.--18. " TX_SHIFT ,Transmit Shift" "No delay,1 SCLK,2 SCLKs,3 SCLKs,4 SCLKs,5 SCLKs,6 SCLKs,7 SCLKs"
|
|
bitfld.long 0x00 8.--11. " IODFTENA ,IO DFT Enable Key" "Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Enabled,Disabled,Disabled,Disabled,Disabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " LPBENA ,Module Loopback Enable" "Analog,Digital"
|
|
bitfld.long 0x00 0. " RXPENA ,Module Analog Loopback Through Receive/Transmit Pin Enable" "Transmit,Receive"
|
|
endif
|
|
width 0xb
|
|
tree.end
|
|
endif
|
|
sif cpuis("TMS570LS0714*")||cpuis("TMS570LS0914*")
|
|
tree "I2C (Inter-Integrated Circuit)"
|
|
base ad:0xFFF7D400
|
|
width 10.
|
|
endian.be
|
|
if (((per.w.be(ad:0xFFF7D400+0x24))&0x100)==0x100)
|
|
group.word 0x00++0x01
|
|
line.word 0x00 "I2COAR,I2C Own Address Manager"
|
|
hexmask.word 0x00 0.--9. 0x01 " OA(9-0) ,Own address"
|
|
else
|
|
group.word 0x00++0x01
|
|
line.word 0x00 "I2COAR,I2C Own Address Manager"
|
|
hexmask.word.byte 0x00 0.--6. 0x01 " OA(6-0) ,Own address"
|
|
endif
|
|
group.word 0x04++0x01
|
|
line.word 0x00 "I2CIMR,I2C Interrupt Mask Register"
|
|
bitfld.word 0x00 6. " AASEN ,Address as slave interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 5. " SCDEN ,Stop condition interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 4. " TXRDYEN ,Transmit data ready interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.word 0x00 3. " RXRDYEN ,Receive data ready interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 2. " ARDYEN ,Register access ready interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.word 0x00 1. " NACKEN ,No acknowledgement interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " ALEN ,Arbitration lost interrupt enable" "Disabled,Enabled"
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "I2CSTR,I2C Status Register"
|
|
eventfld.word 0x00 14. " SDIR ,Slave transmitter direction enable" "Disabled,Enabled"
|
|
eventfld.word 0x00 13. " NACKSNT ,No acknowledge sent" "Not sent,Sent"
|
|
rbitfld.word 0x00 12. " BB ,Bus busy" "Not busy,Busy"
|
|
newline
|
|
rbitfld.word 0x00 11. " RSFULL ,Receiver shift full" "Not full,Full"
|
|
bitfld.word 0x00 10. " XSMT ,Transmit shift empty not" "Empty,Not empty"
|
|
rbitfld.word 0x00 9. " AAS ,Address as slave" "Disabled,Enabled"
|
|
newline
|
|
rbitfld.word 0x00 8. " AD0 ,Address zero status" "Not detected,Detected"
|
|
eventfld.word 0x00 5. " SCD ,Stop condition detect interrupt flag" "No interrupt,Interrupt"
|
|
bitfld.word 0x00 4. " TXRDY ,Transmit data ready interrupt flag" "No interrupt,Interrupt"
|
|
newline
|
|
eventfld.word 0x00 3. " RXRDY ,Receive data ready interrupt flag" "No interrupt,Interrupt"
|
|
eventfld.word 0x00 2. " ARDY ,Register access ready interrupt flag" "No interrupt,Interrupt"
|
|
newline
|
|
eventfld.word 0x00 1. " NACK ,No acknowledgement interrupt" "No interrupt,Interrupt"
|
|
eventfld.word 0x00 0. " AL ,Arbitration lost interrupt flag" "No interrupt,Interrupt"
|
|
if (((per.w.be(ad:0xFFF7D400+0x24))&0x20)==0x20)
|
|
rgroup.word 0x0C++0x01
|
|
line.word 0x00 "I2CCKL,I2C Clock Divider Low Register"
|
|
rgroup.word 0x10++0x01
|
|
line.word 0x00 "I2CCKH,I2C Clock Control High Register"
|
|
else
|
|
group.word 0x0C++0x01
|
|
line.word 0x00 "I2CCKL,I2C Clock Divider Low Register"
|
|
group.word 0x10++0x01
|
|
line.word 0x00 "I2CCKH,I2C Clock Control High Register"
|
|
endif
|
|
group.word 0x14++0x01
|
|
line.word 0x00 "I2CCNT,I2C Data Count Register"
|
|
hgroup.word 0x18++0x01
|
|
hide.word 0x00 "I2CDRR,I2C Data Receive Register"
|
|
in
|
|
if (((per.w.be(ad:0xFFF7D400+0x24))&0x100)==0x100)
|
|
group.word 0x1C++0x01
|
|
line.word 0x00 "I2CSAR,I2C Slave Address Register"
|
|
hexmask.word 0x00 0.--9. 1. " SA ,Receive data"
|
|
else
|
|
group.word 0x1C++0x01
|
|
line.word 0x00 "I2CSAR,I2C Slave Address Register"
|
|
hexmask.word.byte 0x00 0.--6. 1. " SA ,Receive data"
|
|
endif
|
|
group.word 0x20++0x01
|
|
line.word 0x00 "I2CDXR,I2C Data Transmit Register"
|
|
hexmask.word.byte 0x00 0.--7. 1. " DATATX ,Transmit data"
|
|
if (((per.w.be(ad:0xFFF7D400+0x24))&0x408)==0x00)
|
|
group.word 0x24++0x01
|
|
line.word 0x00 "I2CMDR,I2C Mode Register"
|
|
bitfld.word 0x00 15. " NACKMOD ,No-acknowledge (Nack) mode" "Disabled,Enabled"
|
|
bitfld.word 0x00 14. " FREE ,Free running bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " MST ,Master/slave mode bit" "Slave,Master"
|
|
newline
|
|
bitfld.word 0x00 9. " TRX ,Transmit/receive bit" "Receive,Transmit"
|
|
bitfld.word 0x00 8. " XA ,Expand address enable bit" "7-bit addressing,10-bit addressing"
|
|
bitfld.word 0x00 5. " NIRS ,I2C reset enable bit" "Disabled,Enabled"
|
|
newline
|
|
bitfld.word 0x00 3. " FDF ,Free data format enable bit (Not supported in digital loop back mode [this.dlb = 1])" "Disabled,Enabled"
|
|
bitfld.word 0x00 0.--2. " BC[2-0] ,Bit count" "9,,3,4,5,6,7,8"
|
|
elif (((per.w.be(ad:0xFFF7D400+0x24))&0x608)==0x08)
|
|
group.word 0x24++0x01
|
|
line.word 0x00 "I2CMDR,I2C Mode Register"
|
|
bitfld.word 0x00 15. " NACKMOD ,No-acknowledge (Nack) mode" "Disabled,Enabled"
|
|
bitfld.word 0x00 14. " FREE ,Free running bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " MST ,Master/slave mode bit" "Slave,Master"
|
|
newline
|
|
bitfld.word 0x00 9. " TRX ,Transmit/receive bit" "Receive,Transmit"
|
|
bitfld.word 0x00 8. " XA ,Expand address enable bit" "7-bit addressing,10-bit addressing"
|
|
bitfld.word 0x00 5. " NIRS ,I2C reset enable bit" "Disabled,Enabled"
|
|
newline
|
|
bitfld.word 0x00 3. " FDF ,Free data format enable bit (Not supported in digital loop back mode [I2CMDR.dlb = 1])" "Disabled,Enabled"
|
|
bitfld.word 0x00 0.--2. " BC[2-0] ,Bit count" "8,,2,3,4,5,6,7"
|
|
elif (((per.w.be(ad:0xFFF7D400+0x24))&0x608)==0x408)
|
|
group.word 0x24++0x01
|
|
line.word 0x00 "I2CMDR,I2C Mode Register"
|
|
bitfld.word 0x00 15. " NACKMOD ,No-acknowledge (Nack) mode" "Disabled,Enabled"
|
|
bitfld.word 0x00 14. " FREE ,Free running bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 13. " STT ,Start condition" "Disabled,Enabled"
|
|
newline
|
|
bitfld.word 0x00 11. " STP ,Stop condition" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " MST ,Master/slave mode bit" "Slave,Master"
|
|
bitfld.word 0x00 9. " TRX ,Transmit/receive bit" "Receive,Transmit"
|
|
newline
|
|
bitfld.word 0x00 8. " XA ,Expand address enable bit" "7-bit addressing,10-bit addressing"
|
|
bitfld.word 0x00 7. " RM ,Repeat mode enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 5. " NIRS ,I2C reset enable bit" "Disabled,Enabled"
|
|
newline
|
|
bitfld.word 0x00 4. " STB ,Start byte mode enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 3. " FDF ,Free data format enable bit (Not supported in digital loop back mode [I2CMDR.dlb = 1])" "Disabled,Enabled"
|
|
bitfld.word 0x00 0.--2. " BC[2-0] ,Bit count" "8,,2,3,4,5,6,7"
|
|
elif (((per.w.be(ad:0xFFF7D400+0x24))&0x608)==0x400)
|
|
group.word 0x24++0x01
|
|
line.word 0x00 "I2CMDR,I2C Mode Register"
|
|
bitfld.word 0x00 15. " NACKMOD ,No-acknowledge (Nack) mode" "Disabled,Enabled"
|
|
bitfld.word 0x00 14. " FREE ,Free running bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 13. " STT ,Start condition" "Disabled,Enabled"
|
|
newline
|
|
bitfld.word 0x00 11. " STP ,Stop condition" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " MST ,Master/slave mode bit" "Slave,Master"
|
|
bitfld.word 0x00 9. " TRX ,Transmit/receive bit" "Receive,Transmit"
|
|
newline
|
|
bitfld.word 0x00 8. " XA ,Expand address enable bit" "7-bit addressing,10-bit addressing"
|
|
bitfld.word 0x00 7. " RM ,Repeat mode enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 5. " NIRS ,I2C reset enable bit" "Disabled,Enabled"
|
|
newline
|
|
bitfld.word 0x00 4. " STB ,Start byte mode enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 3. " FDF ,Free data format enable bit (Not supported in digital loop back mode [I2CMDR.dlb = 1])" "Disabled,Enabled"
|
|
bitfld.word 0x00 0.--2. " BC[2-0] ,Bit count" "9,,3,4,5,6,7,8"
|
|
elif (((per.w.be(ad:0xFFF7D400+0x24))&0x608)==0x600)
|
|
group.word 0x24++0x01
|
|
line.word 0x00 "I2CMDR,I2C Mode Register"
|
|
bitfld.word 0x00 14. " FREE ,Free running bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 13. " STT ,Start condition" "Disabled,Enabled"
|
|
bitfld.word 0x00 11. " STP ,Stop condition" "Disabled,Enabled"
|
|
newline
|
|
bitfld.word 0x00 10. " MST ,Master/slave mode bit" "Slave,Master"
|
|
bitfld.word 0x00 9. " TRX ,Transmit/receive bit" "Receive,Transmit"
|
|
bitfld.word 0x00 8. " XA ,Expand address enable bit" "7-bit addressing,10-bit addressing"
|
|
newline
|
|
bitfld.word 0x00 7. " RM ,Repeat mode enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 6. " DLB ,Digital loop back enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 5. " NIRS ,I2C reset enable bit" "Disabled,Enabled"
|
|
newline
|
|
bitfld.word 0x00 4. " STB ,Start byte mode enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 3. " FDF ,Free data format enable bit (Not supported in digital loop back mode [I2CMDR.dlb = 1])" "Disabled,Enabled"
|
|
bitfld.word 0x00 0.--2. " BC[2-0] ,Bit count" "9,,3,4,5,6,7,8"
|
|
elif (((per.w.be(ad:0xFFF7D400+0x24))&0x608)==0x608)
|
|
group.word 0x24++0x01
|
|
line.word 0x00 "I2CMDR,I2C Mode Register"
|
|
bitfld.word 0x00 14. " FREE ,Free running bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 13. " STT ,Start condition" "Disabled,Enabled"
|
|
bitfld.word 0x00 11. " STP ,Stop condition" "Disabled,Enabled"
|
|
newline
|
|
bitfld.word 0x00 10. " MST ,Master/slave mode bit" "Slave,Master"
|
|
bitfld.word 0x00 9. " TRX ,Transmit/receive bit" "Receive,Transmit"
|
|
bitfld.word 0x00 8. " XA ,Expand address enable bit" "7-bit addressing,10-bit addressing"
|
|
newline
|
|
bitfld.word 0x00 7. " RM ,Repeat mode enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 6. " DLB ,Digital loop back enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 5. " NIRS ,I2C reset enable bit" "Disabled,Enabled"
|
|
newline
|
|
bitfld.word 0x00 4. " STB ,Start byte mode enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 3. " FDF ,Free data format enable bit (Not supported in digital loop back mode [I2CMDR.dlb = 1])" "Disabled,Enabled"
|
|
bitfld.word 0x00 0.--2. " BC[2-0] ,Bit count" "8,,2,3,4,5,6,7"
|
|
elif (((per.w.be(ad:0xFFF7D400+0x24))&0x608)==0x208)
|
|
group.word 0x24++0x01
|
|
line.word 0x00 "I2CMDR,I2C Mode Register"
|
|
bitfld.word 0x00 14. " FREE ,Free running bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " MST ,Master/slave mode bit" "Slave,Master"
|
|
bitfld.word 0x00 9. " TRX ,Transmit/receive bit" "Receive,Transmit"
|
|
newline
|
|
bitfld.word 0x00 8. " XA ,Expand address enable bit" "7-bit addressing,10-bit addressing"
|
|
bitfld.word 0x00 5. " NIRS ,I2C reset enable bit" "Disabled,Enabled"
|
|
newline
|
|
bitfld.word 0x00 3. " FDF ,Free data format enable bit (Not supported in digital loop back mode [I2CMDR.dlb = 1])" "Disabled,Enabled"
|
|
bitfld.word 0x00 0.--2. " BC[2-0] ,Bit count" "8,,2,3,4,5,6,7"
|
|
endif
|
|
hgroup.word 0x28++0x01
|
|
hide.word 0x00 "I2CIVR,I2C Interrupt Vector Register"
|
|
in
|
|
group.word 0x2C++0x01
|
|
line.word 0x00 "I2CEMDR,I2C Extended Mode Register"
|
|
bitfld.word 0x00 1. " IGNACK ,Ignore NACK mode" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " BCM ,Backwards compatibility mode" "Disabled,Enabled"
|
|
group.word 0x30++0x01
|
|
line.word 0x00 "I2CPSC,I2C Prescale Register"
|
|
hexmask.word.byte 0x00 0.--7. 1. " PSC ,Prescale"
|
|
rgroup.word 0x34++0x01
|
|
line.word 0x00 "I2CPID1,I2C Peripheral ID Register 1"
|
|
hexmask.word.byte 0x00 8.--15. 1. " CLASS ,Peripheral class"
|
|
hexmask.word.byte 0x00 0.--7. 1. " REVISION ,Revision level of the I2C"
|
|
group.word 0x38++0x01
|
|
line.word 0x00 "I2CPID2,I2C Peripheral ID Register 2"
|
|
hexmask.word.byte 0x00 0.--7. 1. " TYPE ,Peripheral type"
|
|
group.word 0x3C++0x01
|
|
line.word 0x00 "I2CDMACR,I2C DMA Control Register"
|
|
bitfld.word 0x00 1. " TXDMAEN ,Transmitter DMA enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " RXDMAEN ,Receive DMA enable" "Disabled,Enabled"
|
|
group.word 0x48++0x01
|
|
line.word 0x00 "I2CPFNC,I2C Pin Function Register"
|
|
bitfld.word 0x00 0. " PINFUNC ,SDA and SCL pin function" "I2C,I/O"
|
|
group.word 0x4C++0x01
|
|
line.word 0x00 "I2CPDIR,I2C Pin Direction Register"
|
|
bitfld.word 0x00 1. " SDADIR ,SDA direction" "Input,Output"
|
|
bitfld.word 0x00 0. " SCLDIR ,SCL direction" "Input,Output"
|
|
rgroup.word 0x50++0x01
|
|
line.word 0x00 "I2CDIN,I2C Data Input Register"
|
|
bitfld.word 0x00 1. " SDAIN ,Serial data in" "Low,High"
|
|
bitfld.word 0x00 0. " SCLSIN ,Serial clock data in" "Low,High"
|
|
group.word 0x54++0x01
|
|
line.word 0x00 "I2CDOUT,I2C Data Output Register"
|
|
bitfld.word 0x00 1. " SDAOUT ,SDA data output" "Low,High"
|
|
bitfld.word 0x00 0. " SCLOUT ,SCL data output" "Low,High"
|
|
group.word 0x58++0x01
|
|
line.word 0x00 "I2CDSET,I2C Data Set Register"
|
|
bitfld.word 0x00 1. " SDASET ,Serial data set" "Low,High"
|
|
bitfld.word 0x00 0. " SCLSET ,Serial clock set" "Low,High"
|
|
group.word 0x5C++0x01
|
|
line.word 0x00 "I2CDCLR,I2C Data Clear Register"
|
|
bitfld.word 0x00 1. " SDACLR ,Serial data clear" "No effect,Cleared"
|
|
bitfld.word 0x00 0. " SCLCLR ,Serial clock clear" "No effect,Cleared"
|
|
group.word 0x60++0x01
|
|
line.word 0x00 "I2CPDR,I2C Pin Open Drain Register"
|
|
bitfld.word 0x00 1. " SDAPDR ,SDA pin open drain disable" "No,Yes"
|
|
bitfld.word 0x00 0. " SCLPDR ,SCL pin open drain disable" "No,Yes"
|
|
group.word 0x64++0x01
|
|
line.word 0x00 "I2CPDIS,I2C Pull Disable Register"
|
|
bitfld.word 0x00 1. " SDAPDIS ,SDA pull disable" "No,Yes"
|
|
bitfld.word 0x00 0. " SCLPDIS ,SCL pull disable" "No,Yes"
|
|
group.word 0x68++0x01
|
|
line.word 0x00 "I2CPSEL,I2C Pull Select Register"
|
|
bitfld.word 0x00 1. " SDAPSEL ,SDA pull select" "Pull down,Pull up"
|
|
bitfld.word 0x00 0. " SCLPSEL ,SCL pull select" "Pull down,Pull up"
|
|
group.word 0x6C++0x01
|
|
line.word 0x00 "I2CSRS,I2C Pins Slew Rate Select Register"
|
|
bitfld.word 0x00 1. " SDASRS ,SDA slew rate select" "Slow,Normal"
|
|
bitfld.word 0x00 0. " SCLSRS ,SCL slew rate select" "Slow,Normal"
|
|
endian.le
|
|
width 0x0B
|
|
tree.end
|
|
endif
|
|
tree "eFuse (Enhanced Fuse Controller)"
|
|
base ad:0xFFF8C000
|
|
sif cpuis("TMS570LS0232")||cpuis("TMS570LS0714*")||cpuis("TMS570LS0914*")
|
|
endian.be
|
|
endif
|
|
width 14.
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "EFCBOUND,EFC Boundary Control Register"
|
|
bitfld.long 0x00 21. " EFC_SELF_TEST_ERROR ,Self error test (If(self_test_error_oe is high))" "Low,High"
|
|
bitfld.long 0x00 20. " EFC_SINGLE_ERROR ,Single bit error (If(single_error_oe is high))" "Low,High"
|
|
bitfld.long 0x00 19. " EFC_INSTRUCTION_ERROR ,Instruction error (If(instruction_error_oe is high))" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 18. " EFC_AUTOLOAD_ERROR ,Autoload error (If(autoload_error_oe is high))" "Low,High"
|
|
bitfld.long 0x00 17. " SELF_TEST_ERROR_OE ,Self test error output enable" "Efuse controller,Boundary register"
|
|
bitfld.long 0x00 16. " SINGLE_ERROR_OE ,Single bit error output enable" "Efuse controller,Boundary register"
|
|
newline
|
|
bitfld.long 0x00 15. " INSTRUCTION_ERROR_OE ,Instruction error output enable" "Efuse controller,Boundary register"
|
|
bitfld.long 0x00 14. " AUTOLOAD_ERROR_OE ,Autoload error output enable" "Efuse controller,Boundary register"
|
|
bitfld.long 0x00 13. " EFC_ECC_SELFTEST_ENABLE ,Starts the selftest of the ECC logic (If EFCBOUND = 0xf)" "No action,Start ECC selftest"
|
|
newline
|
|
bitfld.long 0x00 0.--3. " EFCBOUND[3:0] ,Input enable" "Not started,Not started,Not started,Not started,Not started,Not started,Not started,Not started,Not started,Not started,Not started,Not started,Not started,Not started,Not started,Started"
|
|
rgroup.long 0x2C++0x03
|
|
line.long 0x00 "EFCPINS,EFC Pins Register"
|
|
bitfld.long 0x00 15. " EFC_SELFTEST_DONE ,Determine EFC ECC selftest complete" "Not done,Done"
|
|
bitfld.long 0x00 14. " EFC_SELFTEST_ERROR ,Determine EFC ECC selftest pass/fail" "No error,Error"
|
|
bitfld.long 0x00 12. " EFC_SINGLE_BIT_ERROR ,Determine single bit error" "No error,Error detected/corrected"
|
|
newline
|
|
bitfld.long 0x00 11. " EFC_INSTRUCTION_ERROR ,Error during factory test/program operation" "No error,Error"
|
|
bitfld.long 0x00 10. " EFC_AUTOLOAD_ERROR ,Non-Correctable error" "No error,Errors"
|
|
group.long 0x3C++0x03
|
|
line.long 0x00 "EFC_ERR_STAT,EFC Error Status Register"
|
|
bitfld.long 0x00 5. " INSTRUC_DONE ,Instruction done" "Not done,Done"
|
|
bitfld.long 0x00 0.--4. " ERROR_CODE ,Error status" "No error,,,,,Uncorrectable error,,,,,,,,,,,,,,,,Single bit error,,,Signature fail,?..."
|
|
group.long 0x48++0x07
|
|
line.long 0x00 "EFC_ST_CY,EFC Self Test Cycles Register"
|
|
line.long 0x04 "EFC_ST_SIG,EFC Self Test Signature Register"
|
|
sif cpuis("TMS570LS0232")||cpuis("TMS570LS0714*")||cpuis("TMS570LS0914*")
|
|
endian.le
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
newline
|