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woody d411edd9b4 add Trace32 File
2025-10-14 09:52:32 +09:00

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; --------------------------------------------------------------------------------
; @Title: TMS570LC4357 On-Chip Peripherals
; @Props: Released
; @Author: MKR, TPP, ZAK
; @Changelog: 2012-12-04
; @Manufacturer: TI - Texas Instruments
; @Doc: SPNU563_570LC43x_Draft.pdf (SPNU563 2012-10)
; SPNS195_LC4357_Draft_2012_11_14.pdf (SPNS195 2012-10)
; spnu563.pdf (SPNU563 2014-05)
; public_datasheet_spns165a.pdf (SPNS195A 2014-05)
; @Core: Cortex-R5
; @Copyright: (C) 1989-2016 Lauterbach GmbH, licensed for use with TRACE32(R) only
; --------------------------------------------------------------------------------
; $Id: pertms570lc4xx.per 13224 2021-04-28 12:54:48Z kwitkowski $
config 16. 8.
tree "Core Registers (Cortex-R5F)"
AUTOINDENT.PUSH
AUTOINDENT.OFF
width 0x8
; --------------------------------------------------------------------------------
; Identification registers
; --------------------------------------------------------------------------------
tree "ID Registers"
rgroup.long c15:0x00++0x00
line.long 0x00 "MIDR,Main ID Register"
hexmask.long.byte 0x0 24.--31. 0x1 " IMPL ,Implementer code"
bitfld.long 0x0 20.--23. " VAR ,Variant" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x0 16.--19. " ARCH ,Architecture" "Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,ARMv7"
textline " "
hexmask.long.word 0x0 4.--15. 0x1 " PART ,Primary Part Number"
bitfld.long 0x0 0.--3. " REV ,Revision Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
rgroup.long c15:0x100++0x00
line.long 0x00 "CTR,Cache Type Register"
bitfld.long 0x00 24.--27. " CWG ,Cache Write-back Granule" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x00 20.--23. " ERG ,Exclusives Reservation Granule" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x0 16.--19. " DMINLINE ,D-Cache Minimum Line Size" "1 word,2 words,4 words,8 words,16 words,32 words,64 words,128 words,256 words,512 words,1024 words,2048 words,4096 words,8192 words,16384 words,32768 words"
bitfld.long 0x0 14.--15. " L1POLICY ,L1 Instruction cache policy" "Reserved,ASID,Virtual,Physical"
textline " "
bitfld.long 0x0 0.--3. " IMINLINE ,I-Cache Minimum Line Size" "1 word,2 words,4 words,8 words,16 words,32 words,64 words,128 words,256 words,512 words,1024 words,2048 words,4096 words,8192 words,16384 words,32768 words"
rgroup.long c15:0x400--0x400
line.long 0x0 "MPUIR,MPU type register"
hexmask.long.byte 0x00 8.--15. 1. " REGNUM ,Number of regions"
bitfld.long 0x00 0. " TYPE ,Type of MPU regions" "Unified,Seperated"
rgroup.long c15:0x500++0x00
line.long 0x0 "MPIDR,Multiprocessor Affinity Register"
bitfld.long 0x00 30.--31. " MULT_EXT ,Multiprocessing extensions" "No extensions,Reserved,Reserved,Part of a uniprocessor system"
textline " "
hexmask.long.byte 0x00 16.--23. 1. " AFFL2 ,Affitnity Level 2"
hexmask.long.byte 0x00 8.--15. 1. " AFFL1 ,Affitnity Level 1"
hexmask.long.byte 0x00 0.--7. 1. " AFFL0 ,Affitnity Level 0"
textline " "
rgroup.long c15:0x0410++0x00
line.long 0x00 "MMFR0,Memory Model Feature Register 0"
bitfld.long 0x00 28.--31. " IT ,Instruction Type Support" "Reserved,Reserved,Reserved,Supported,?..."
bitfld.long 0x00 24.--27. " FCSE ,Fast Context Switch Memory Mappings Support" "Reserved,Supported,?..."
textline " "
bitfld.long 0x00 20.--23. " ACR ,Auxiliary Control Register Support" "Reserved,Supported,?..."
bitfld.long 0x00 16.--19. " TCM ,TCM and Associated DMA Support" "Not supported,?..."
textline " "
bitfld.long 0x00 12.--15. " SL ,Number of Shareability levels implemented" "1,?..."
bitfld.long 0x00 8.--11. " OS ,Outermost Shareability domain support" "Supported,?..."
textline " "
bitfld.long 0x00 4.--7. " PMSA ,Physical Memory System Architecture (PMSA) Support" "Not supported,?..."
bitfld.long 0x00 0.--3. " VMSA ,Virtual Memory System Architecture (VMSA) Support" "Reserved,Reserved,Reserved,Supported,?..."
rgroup.long c15:0x0510++0x00
line.long 0x00 "MMFR1,Memory Model Feature Register 1"
bitfld.long 0x00 28.--31. " BTB ,Branch Target Buffer Support" "Reserved,Reserved,Not required,?..."
bitfld.long 0x00 24.--27. " L1TCO ,Test and Clean Operations on Data Cache/Harvard/Unified Architecture Support" "Not supported,?..."
textline " "
bitfld.long 0x00 20.--23. " L1UCMO ,L1 Cache/All Maintenance Operations/Unified Architecture Support" "Not supported,?..."
bitfld.long 0x00 16.--19. " L1HCMO ,L1 Cache/All Maintenance Operations/Harvard Architecture Support" "Supported,?..."
textline " "
bitfld.long 0x00 12.--15. " L1UCLMOSW ,L1 Cache Line Maintenance Operations by Set and Way/Unified Architecture Support" "Not supported,?..."
bitfld.long 0x00 8.--11. " L1HCLMOSW ,L1 Cache Line Maintenance Operations by Set and Way/Harvard Architecture Support" "Supported,?..."
textline " "
bitfld.long 0x00 4.--7. " L1UCLMOMVA ,L1 Cache Line Maintenance Operations by MVA/Unified Architecture Support" "Not supported,?..."
bitfld.long 0x00 0.--3. " L1HCLMOMVA ,L1 Cache Line Maintenance Operations by MVA/Harvard Architecture" "Supported,?..."
rgroup.long c15:0x0610++0x00
line.long 0x00 "MMFR2,Memory Model Feature Register 2"
bitfld.long 0x00 28.--31. " HAF ,Hardware Access Flag Support" "Not supported,?..."
bitfld.long 0x00 24.--27. " WFI ,Wait for Interrupt Stalling Support" "Reserved,Supported,?..."
textline " "
bitfld.long 0x00 20.--23. " MBF ,Memory Barrier Operations Support" "Reserved,Reserved,Supported,?..."
bitfld.long 0x00 16.--19. " UTLBMO ,TLB Maintenance Operations/Unified Architecture Support" "Not supported,?..."
textline " "
bitfld.long 0x00 12.--15. " HTLBMO ,TLB Maintenance Operations/Harvard Architecture Support" "Reserved,Reserved,Supported,?..."
bitfld.long 0x00 8.--11. " HL1CMRO ,Cache Maintenance Range Operations/Harvard Architecture Support" "Not supported,?..."
textline " "
bitfld.long 0x00 4.--7. " HL1BPCRO ,Background Prefetch Cache Range Operations/Harvard Architecture Support" "Not supported,?..."
bitfld.long 0x00 0.--3. " HL1FPCRO ,Foreground Prefetch Cache Range Operations/Harvard Architecture Support" "Not supported,?..."
rgroup.long c15:0x0710++0x00
line.long 0x00 "MMFR3,Memory Model Feature Register 3"
bitfld.long 0x00 28.--31. " SS ,Supersection support" "Supported,?..."
bitfld.long 0x00 20.--23. " CW ,Coherent walk" "Supported,?..."
textline " "
bitfld.long 0x00 12.--15. " MB ,Invalidate broadcast Support" "Reserved,Reserved,Supported,?..."
textline " "
bitfld.long 0x00 4.--7. " HCMOSW ,Invalidate Cache by Set and Way/Clean by Set and Way/Invalidate and Clean by Set and Way Support" "Reserved,Supported,?..."
bitfld.long 0x00 0.--3. " HCMOMVA ,Invalidate Cache by MVA/Clean by MVA/Invalidate and Clean by MVA/Invalidate All Support" "Reserved,Supported,?..."
rgroup.long c15:0x020++0x00
line.long 0x00 "ISAR0,Instruction Set Attributes Register 0"
bitfld.long 0x00 24.--27. " DIVI ,Divide Instructions Support" "Not supported,?..."
bitfld.long 0x00 20.--23. " DEBI ,Debug Instructions Support" "Reserved,Supported,?..."
textline " "
bitfld.long 0x00 16.--19. " CI ,Coprocessor Instructions Support" "Not supported,?..."
bitfld.long 0x00 12.--15. " CBI ,Combined Compare and Branch Instructions Support" "Reserved,Supported,?..."
textline " "
bitfld.long 0x00 8.--11. " BI ,Bitfield Instructions Support" "Reserved,Supported,?..."
bitfld.long 0x00 4.--7. " BCI ,Bit Counting Instructions Support" "Reserved,Supported,?..."
textline " "
bitfld.long 0x00 0.--3. " SI ,Swap Instructions Support" "Reserved,Supported,?..."
rgroup.long c15:0x120++0x00
line.long 0x00 "ISAR1,Instruction Set Attributes Register 1"
bitfld.long 0x00 28.--31. " JI ,Jazelle Instructions Support" "Reserved,Supported,?..."
bitfld.long 0x00 24.--27. " INTI ,Instructions That Branch Between ARM and Thumb Code Support" "Reserved,Reserved,Supported,?..."
textline " "
bitfld.long 0x00 20.--23. " IMMI ,Immediate Instructions Support" "Reserved,Supported,?..."
bitfld.long 0x00 16.--19. " ITEI ,If Then Instructions Support" "Reserved,Supported,?..."
textline " "
bitfld.long 0x00 12.--15. " EXTI ,Sign or Zero Extend Instructions Support" "Reserved,Reserved,Supported,?..."
bitfld.long 0x00 8.--11. " E2I ,Exception 2 Instructions Support" "Reserved,Supported,?..."
textline " "
bitfld.long 0x00 4.--7. " E1I ,Exception 1 Instructions Support" "Reserved,Supported,?..."
bitfld.long 0x00 0.--3. " ENDI ,Endianness Control Instructions Support" "Reserved,Supported,?..."
rgroup.long c15:0x220++0x00
line.long 0x00 "ISAR2,Instruction Set Attributes Register 2"
bitfld.long 0x00 28.--31. " RI ,Reversal Instructions Support" "Reserved,Reserved,Supported,?..."
bitfld.long 0x00 24.--27. " PSRI ,PSR Instructions Support" "Reserved,Supported,?..."
textline " "
bitfld.long 0x00 20.--23. " UMI ,Advanced Unsigned Multiply Instructions Support" "Reserved,Reserved,Supported,?..."
bitfld.long 0x00 16.--19. " SMI ,Advanced Signed Multiply Instructions Support" "Reserved,Reserved,Reserved,Supported,?..."
textline " "
bitfld.long 0x00 12.--15. " MI ,Multiply Instructions Support" "Reserved,Reserved,Supported,?..."
bitfld.long 0x00 8.--11. " II ,Multi-Access Interruptible Instructions Support" "Supported,?..."
textline " "
bitfld.long 0x00 4.--7. " MHI ,Memory Hint Instructions Support" "Reserved,Reserved,Reserved,Supported,?..."
bitfld.long 0x00 0.--3. " LSI ,Load and Store Instructions Support" "Reserved,Supported,?..."
rgroup.long c15:0x320++0x00
line.long 0x00 "ISAR3,Instruction Set Attributes Register 3"
bitfld.long 0x00 28.--31. " T2E ,Thumb-2 Extensions Support" "Reserved,Supported,?..."
bitfld.long 0x00 24.--27. " NOPI ,True NOP Instructions Support" "Reserved,Supported,?..."
textline " "
bitfld.long 0x00 20.--23. " TCI ,Thumb Copy Instructions Support" "Reserved,Supported,?..."
bitfld.long 0x00 16.--19. " TBI ,Table Branch Instructions Support" "Reserved,Reserved,Supported,?..."
textline " "
bitfld.long 0x00 12.--15. " SPI ,Synchronization Primitive Instructions Support" "Reserved,Reserved,Supported,?..."
bitfld.long 0x00 8.--11. " SVCI ,SVC Instructions Support" "Reserved,Supported,?..."
textline " "
bitfld.long 0x00 4.--7. " SIMDI ,Single Instruction Multiple Data (SIMD) Instructions Support" "Reserved,Reserved,Reserved,Supported,?..."
bitfld.long 0x00 0.--3. " SI ,Saturate Instructions Support" "Reserved,Supported,?..."
rgroup.long c15:0x420++0x00
line.long 0x00 "ISAR4,Instruction Set Attributes Register 4"
bitfld.long 0x00 28.--31. " SWP_FRAC ,SWAP_frac" "Supported,?..."
bitfld.long 0x00 24.--27. " PSR_M_I ,PSR_M Instructions Support" "Not supported,?..."
textline " "
bitfld.long 0x00 20.--23. " EI ,Exclusive Instructions Support" "Reserved,Supported,?..."
bitfld.long 0x00 16.--19. " BI ,Barrier Instructions Support" "Reserved,Supported,?..."
textline " "
bitfld.long 0x00 12.--15. " SMII ,SMI Instructions Support" "Reserved,Supported,?..."
bitfld.long 0x00 8.--11. " WBI ,Write-Back Instructions Support" "Reserved,Supported,?..."
textline " "
bitfld.long 0x00 4.--7. " WSI ,With-Shift Instructions Support" "Reserved,Reserved,Reserved,Reserved,Supported,?..."
bitfld.long 0x00 0.--3. " UI ,Unprivileged Instructions Support" "Reserved,Reserved,Supported,?..."
rgroup.long c15:0x0520++0x00
line.long 0x00 "ISAR5,Instruction Set Attribute Registers 5 (Reserved)"
rgroup.long c15:0x0620++0x00
line.long 0x00 "ISAR6,Instruction Set Attribute Registers 6 (Reserved)"
rgroup.long c15:0x0720++0x00
line.long 0x00 "ISAR7,Instruction Set Attribute Registers 7 (Reserved)"
rgroup.long c15:0x010++0x00
line.long 0x00 "ID_PFR0,Processor Feature Register 0"
bitfld.long 0x00 12.--15. " STATE3 ,Thumb-2 Execution Environment (Thumb-2EE) Support" "Reserved,Supported,?..."
bitfld.long 0x00 8.--11. " STATE2 ,Java Extension Interface Support" "Not supported,?..."
bitfld.long 0x00 4.--7. " STATE1 ,Thumb Encoding Supported by the Processor Type" "Reserved,Reserved,Reserved,Supported,?..."
textline " "
bitfld.long 0x00 0.--3. " STATE0 ,ARM Instruction Set Support" "Reserved,Supported,?..."
rgroup.long c15:0x110++0x00
line.long 0x00 "ID_PFR1,Processor Feature Register 1"
bitfld.long 0x00 8.--11. " MPM ,Microcontroller Programmer's Model Support" "Supported,?..."
bitfld.long 0x00 4.--7. " SE ,Security Extensions Architecture v1 Support" "Reserved,Supported,?..."
bitfld.long 0x00 0.--3. " PM ,Standard ARMv4 Programmer's Model Support" "Reserved,Supported,?..."
textline " "
rgroup.long c15:0x210++0x00
line.long 0x00 "ID_DFR0,Debug Feature Register 0"
bitfld.long 0x00 20.--23. " MDM_MM ,Microcontroller Debug Model Support" "Not supported,?..."
bitfld.long 0x00 16.--19. " TDM_MM ,Trace Debug Model (Memory-Mapped) Support" "Reserved,Supported,?..."
bitfld.long 0x00 12.--15. " TDM_CB ,Coprocessor-Based Trace Debug Model Support" "Not supported,?..."
textline " "
bitfld.long 0x00 8.--11. " CDM_MM ,Memory-Mapped Debug Model Support" "Reserved,Reserved,Reserved,Reserved,Supported,?..."
bitfld.long 0x00 4.--7. " SDM_CB ,Secure Debug Model (Coprocessor) Support" "Not supported,?..."
bitfld.long 0x00 0.--3. " CDM_CB ,Coprocessor Debug Model Support" "Not supported,?..."
rgroup.long c15:0x310++0x00
line.long 0x00 "ID_AFR0,Auxiliary Feature Register 0"
rgroup.long c15:0x02f++0x00
line.long 0x00 "BO1R,Build Options 1 Register"
hexmask.long.long 0x00 12.--31. 0x1000 " TCM_HI_INIT_ADDR ,Default high address for the TCM"
bitfld.long 0x00 1. " FLOAT_PRECISION ,Indicate whether double-precision floating point is implemented" "Not implemented,Implemented"
textline " "
bitfld.long 0x00 0. " PP_BUS_ECC ,Indicate whether bus-ECC is implemented" "Not implemented,Implemented"
group.long c15:0x12f++0x00
line.long 0x00 "BO2R,Build Options 2 Register"
bitfld.long 0x00 31. " NUM_CPU ,Number of CPUs" "1,2"
bitfld.long 0x00 30. " LOCK_STEP ,Indicate whether the CPU has redundant logic running in lock step for checking purposes" "Not included,Included"
textline " "
bitfld.long 0x00 29. " NO_ICACHE ,Indicate whether the CPU contains instruction cache" "Yes,No"
bitfld.long 0x00 28. " NO_DCACHE ,Indicate whether the CPU contains data cache" "Yes,No"
textline " "
bitfld.long 0x00 26.--27. " ATCM_ES ,Indicate whether an error scheme is implemented on the ATCM interface" "No error scheme,32 bit error detection,Reserved,64 bit error detection"
bitfld.long 0x00 23.--25. " BTCM_ES ,Indicate whether an error scheme is implemented on the BTCM interface" "No error scheme,32 bit error detection,Reserved,64 bit error detection,?..."
textline " "
bitfld.long 0x00 23. " NO_IE ,Indicate whether the processor supports big-endian instructions" "Yes,No"
bitfld.long 0x00 22. " NO_FPU ,Indicate whether the CPU contains a floating point unit" "Yes,No"
textline " "
bitfld.long 0x00 20.--21. " MPU_REGIONS ,Indicates the number of regions in the included CPU MPU" "No region,Reserved,12 regions,16 regions"
bitfld.long 0x00 17.--19. " BREAK_POINTS ,Indicate the number of break points implemented in each CPU in the processor minus 1" "0,1,2,3,4,5,6,7"
textline " "
bitfld.long 0x00 14.--16. " WATCH_POINTS ,Indicate the number of watch points implemented in each CPU in the processor minus 1" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 13. " NO_A_TCM_INF ,Indicate whether the CPUs contain ATCM ports" "Yes,No"
textline " "
bitfld.long 0x00 12. " NO_B0_TCM_INF ,Indicate whether the CPUs contain B0TCM ports" "Yes,No"
bitfld.long 0x00 11. " NO_B1_TCM_INF ,Indicate whether the CPUs contain B1TCM ports" "Yes,No"
textline " "
bitfld.long 0x00 10. " TCMBUSPARITY ,Indicate whether the processor contains TCM address bus parity logic" "No,Yes"
bitfld.long 0x00 9. " NO_SLAVE ,Indicate whether the CPU contains an AXI slave port" "Yes,No"
textline " "
bitfld.long 0x00 7.--8. " ICACHE_ES ,Indicate whether an error scheme is implemented for the instruction cache" "No error scheme,8-bit parity,Reserved,64-bit ECC"
bitfld.long 0x00 5.--6. " DCACHE_ES ,Indicate whether an error scheme is implemented for the data cache" "No error scheme,8-bit parity,32-bit ECC,?..."
textline " "
bitfld.long 0x00 4. " NO_HARD_ERROR_CACHE ,Indicate whether the processor contains cache for corrected TCM errors" "Yes,No"
bitfld.long 0x00 3. " AXI_BUS_ECC ,Indicate whether the processor contains AXI bus ECC logic" "No,Yes"
textline " "
bitfld.long 0x00 2. " SL ,Indicate whether the processor has been built with split/lock logic" "No,Yes"
bitfld.long 0x00 1. " AHB_PP ,Indicate whether the CPU contain AHB peripheral interfaces" "No,Yes"
textline " "
bitfld.long 0x00 0. " MICRO_SCU ,Indicate whether the processor contain an ACP interface" "No,Yes"
group.long c15:0x72f++0x00
line.long 0x00 "POR,Pin Options Register"
bitfld.long 0x00 4. " DBGNOCLKSTOP ,Value of the DBGNOCLKSTOP pin" "Low,High"
bitfld.long 0x00 3. " INTSYNCEN ,Value of the INTSYNCEN pin" "Low,High"
textline " "
bitfld.long 0x00 2. " IRQADDRVSYNCEN ,Value of the IRQADDRVSYNCEN pin" "Low,High"
bitfld.long 0x00 1. " SLBTCMSB ,Value of the SLBTCMSBm pin" "Low,High"
textline " "
bitfld.long 0x00 0. " PARITYLEVEL ,Value of the PARITYLEVEL pin" "Low,High"
tree.end
width 0x8
tree "System Control and Configuration"
group.long c15:0x01++0x00
line.long 0x00 "SCTLR,Control Register"
bitfld.long 0x0 31. " IE ,Instruction endianness" "Little,Big"
bitfld.long 0x0 30. " TE ,Thumb exception enable" "ARM,Thumb"
bitfld.long 0x0 29. " AFE ,Access Flag Enable" "Disable,Enable"
bitfld.long 0x0 28. " TRE ,TEX remap enable" "Disable,Enable"
bitfld.long 0x0 27. " NMFI ,Nonmaskable Fast Interrupt enable" "Disable,Enable"
textline " "
bitfld.long 0x0 25. " EE ,Exception endianess" "Little,Big"
bitfld.long 0x0 24. " VE ,Vector Enable" "Disable,Vectored"
bitfld.long 0x0 21. " FI ,Fast Interrupts enable" "Disable,Enable"
textline " "
bitfld.long 0x0 19. " DZ ,Divide by Zero exception bit" "Disable,Enable"
bitfld.long 0x0 17. " BR ,MPU Background region enable" "Disable,Enable"
bitfld.long 0x0 14. " RR ,Round-Robin bit" "Random,RRobin"
bitfld.long 0x0 13. " V ,Base Location of Exception Registers" "0x00000000,0xFFFF0000"
textline " "
bitfld.long 0x0 12. " I ,Instruction Cache Enable" "Disable,Enable"
bitfld.long 0x0 11. " Z ,Branch Prediction Enable" "Disable,Enable"
bitfld.long 0x0 2. " C ,Enable data cache" "Disable,Enable"
bitfld.long 0x0 1. " A ,Strict Alignment" "Disable,Enable"
bitfld.long 0x0 0. " M ,MPU Enable" "Disable,Enable"
textline " "
group.long c15:0x101++0x00
line.long 0x0 "ACTLR,Auxiliary Control Register"
bitfld.long 0x00 31. " DICDI ,Disable Case C dual issue control" "Enable,Disable"
bitfld.long 0x00 30. " DIB2DI ,Disable Case B2 dual issue control" "Enable,Disable"
bitfld.long 0x00 29. " DIB1DI ,Disable Case B1 dual issue control" "Enable,Disable"
textline " "
bitfld.long 0x00 28. " DIADI ,Disable Case A dual issue control" "Enable,Disable"
bitfld.long 0x00 27. " B1TCMPCEN ,B1TCM parity or ECC check enable" "Disable,Enable"
bitfld.long 0x00 26. " B0TCMPCEN ,B1TCM parity or ECC check enable" "Disable,Enable"
textline " "
bitfld.long 0x00 25. " ATCMPCEN ,B1TCM parity or ECC check enable" "Disable,Enable"
bitfld.long 0x00 24. " AXISCEN ,AXI slave cache access enable" "Disable,Enable"
bitfld.long 0x00 23. " AXISCUEN ,AXI slave cache User mode access enable" "Disable,Enable"
textline " "
bitfld.long 0x00 22. " DILSM ,Disable LIL on load/store multiples" "Enable,Disable"
bitfld.long 0x00 21. " DEOLP ,Disable end of loop prediction" "Enable,Disable"
bitfld.long 0x00 20. " DBHE ,Disable BH extension" "Enable,Disable"
textline " "
bitfld.long 0x00 19. " FRCDIS ,Fetch rate control disable" "Enable,Disable"
bitfld.long 0x00 17. " RSDIS ,Return stack disable" "Enable,Disable"
bitfld.long 0x00 15.--16. " BP ,Control of the branch prediction policy" "Normal,Taken,Not taken,?..."
textline " "
bitfld.long 0x00 14. " DBWR ,Disable write_burst on AXI master" "Enable,Disable"
bitfld.long 0x00 13. " DLFO ,Disable linefill optimization in the AXI master" "Enable,Disable"
bitfld.long 0x00 12. " ERPEG ,Enable random parity error generation" "Disable,Enable"
textline " "
bitfld.long 0x00 11. " DNCH ,Disable data forwarding for Non-cacheable accesses in the AXI master" "Enable,Disable"
bitfld.long 0x00 10. " FORA ,Force outer read allocate (ORA) for outer write allocate (OWA) regions" "Not forced,Forced"
bitfld.long 0x00 9. " FWT ,Force write-through (WT) for write-back (WB) regions" "Not forced,Forced"
textline " "
bitfld.long 0x00 8. " FDSnS ,Force D-side to not-shared when MPU is off" "Not forced,Forced"
bitfld.long 0x00 7. " SMOV ,sMOV disabled" "Enabled,Disabled"
bitfld.long 0x0 6. " DILS ,Disable low interrupt latency on all load/store instructions" "Enable,Disable"
textline " "
bitfld.long 0x00 3.--5. " CEC ,Cache error control for cache parity and ECC errors" "Generate abort,Generate abort,Generate abort,Reserved,Disabled parity checking,Not generate abort,Not generate abort,?..."
textline " "
bitfld.long 0x00 2. " B1TCMECEN ,B1TCM external error enable" "Disable,Enable"
bitfld.long 0x00 1. " B0TCMECEN ,B0TCM external error enable" "Disable,Enable"
bitfld.long 0x00 0. " ATCMECEN ,ATCM external error enable" "Disable,Enable"
textline " "
group.long c15:0x0f++0x00
line.long 0x00 "SACTLR,Secondary Auxiliary Control Register"
bitfld.long 0x00 22. " DCHE ,Disable hard-error support in the caches" "Enable,Disable"
bitfld.long 0x00 21. " DR2B ,Enable random 2-bit error genration in cache RAMs" "Disable,Enable"
bitfld.long 0x00 20. " DF6DI ,F6 dual issue control" "Enable,Disable"
textline " "
bitfld.long 0x00 19. " DF2DI ,F2 dual issue control" "Enable,Disable"
bitfld.long 0x00 18. " DDI ,F1/F3/F4 dual issue control" "Enable,Disable"
bitfld.long 0x00 17. " DOODPFP ,Out-of-order Double Precision Floating-point control" "Enable,Disable"
textline " "
bitfld.long 0x00 16. " DOOFMACS ,Out-of-order FMACS control" "Enable,Disable"
bitfld.long 0x00 13. " IXC ,Floating-point inexact exception output mask" "Mask,Propagate"
bitfld.long 0x00 12. " OFC ,Floating-point overflow exception output mask" "Mask,Propagate"
textline " "
bitfld.long 0x00 11. " UFC ,Floating-point underflow exception output mask" "Mask,Propagate"
bitfld.long 0x00 10. " IOC ,Floating-point invalid operation exception output mask" "Mask,Propagate"
bitfld.long 0x00 9. " DZC ,Floating-point divide-by-zero exception output mask" "Mask,Propagate"
textline " "
bitfld.long 0x00 8. " IDC ,Floating-point input denormal exception output mask" "Mask,Propagate"
bitfld.long 0x00 3. " BTCMECC ,Correction for internal ECC logic on BTCM ports" "Enable,Disable"
bitfld.long 0x00 2. " ATCMECC ,Correction for internal ECC logic on ATCM port" "Enable,Disable"
textline " "
bitfld.long 0x00 1. " BTCMRMW ,Enable 64-bit stores on BTCMs" "Disable,Enable"
bitfld.long 0x00 0. " ATCMRMW ,Enable 64-bit stores on ATCM" "Disable,Enable"
textline " "
group.long c15:0x201++0x00
line.long 0x0 "CPACR,Coprocessor Access Control Register"
bitfld.long 0x0 31. " ASEDIS ,Disable Advanced SIMD Extension functionality" "No,Yes"
bitfld.long 0x0 30. " D32DIS ,Disable use of D16-D31 of the VFP register file" "No,Yes"
textline " "
bitfld.long 0x0 26.--27. " CP13 ,Coprocesor access control" "Denied,Privileged,Reserved,Full"
bitfld.long 0x0 24.--25. " CP12 ,Coprocesor access control" "Denied,Privileged,Reserved,Full"
textline " "
bitfld.long 0x0 22.--23. " CP11 ,Coprocesor access control" "Denied,Privileged,Reserved,Full"
bitfld.long 0x0 20.--21. " CP10 ,Coprocesor access control" "Denied,Privileged,Reserved,Full"
textline " "
bitfld.long 0x0 18.--19. " CP9 ,Coprocesor access control" "Denied,Privileged,Reserved,Full"
bitfld.long 0x0 16.--17. " CP8 ,Coprocesor access control" "Denied,Privileged,Reserved,Full"
textline " "
bitfld.long 0x0 14.--15. " CP7 ,Coprocesor access control" "Denied,Privileged,Reserved,Full"
bitfld.long 0x0 12.--13. " CP6 ,Coprocesor access control" "Denied,Privileged,Reserved,Full"
textline " "
bitfld.long 0x0 10.--11. " CP5 ,Coprocesor access control" "Denied,Privileged,Reserved,Full"
bitfld.long 0x0 8.--9. " CP4 ,Coprocesor access control" "Denied,Privileged,Reserved,Full"
textline " "
bitfld.long 0x0 6.--7. " CP3 ,Coprocesor access control" "Denied,Privileged,Reserved,Full"
bitfld.long 0x0 4.--5. " CP2 ,Coprocesor access control" "Denied,Privileged,Reserved,Full"
textline " "
bitfld.long 0x0 2.--3. " CP1 ,Coprocesor access control" "Denied,Privileged,Reserved,Full"
bitfld.long 0x0 0.--1. " CP0 ,Coprocesor access control" "Denied,Privileged,Reserved,Full"
textline " "
group.long c15:0x000b++0x00
line.long 0x00 "SPCR,Slave Port Control Register"
bitfld.long 0x00 1. " PRIV ,Privilege access only" "User/Privilege,Privilege only"
bitfld.long 0x00 0. " AXISLEN ,AXI slave port disable" "Enabled,Disabled"
tree.end
width 0x8
tree "MPU Control and Configuration"
group.long c15:0x01++0x00
line.long 0x00 "SCTLR,Control Register"
bitfld.long 0x0 31. " IE ,Instruction endianness" "Little,Big"
bitfld.long 0x0 30. " TE ,Thumb exception enable" "ARM,Thumb"
bitfld.long 0x0 29. " AFE ,Access Flag Enable" "Disable,Enable"
bitfld.long 0x0 28. " TRE ,TEX remap enable" "Disable,Enable"
bitfld.long 0x0 27. " NMFI ,Nonmaskable Fast Interrupt enable" "Disable,Enable"
textline " "
bitfld.long 0x0 25. " EE ,Exception endianess" "Little,Big"
bitfld.long 0x0 24. " VE ,Vector Enable" "Disable,Vectored"
bitfld.long 0x0 21. " FI ,Fast Interrupts enable" "Disable,Enable"
textline " "
bitfld.long 0x0 19. " DZ ,Divide by Zero exception bit" "Disable,Enable"
bitfld.long 0x0 17. " BR ,MPU Background region enable" "Disable,Enable"
bitfld.long 0x0 14. " RR ,Round-Robin bit" "Random,RRobin"
bitfld.long 0x0 13. " V ,Base Location of Exception Registers" "0x00000000,0xFFFF0000"
textline " "
bitfld.long 0x0 12. " I ,Instruction Cache Enable" "Disable,Enable"
bitfld.long 0x0 11. " Z ,Branch Prediction Enable" "Disable,Enable"
bitfld.long 0x0 2. " C ,Enable data cache" "Disable,Enable"
bitfld.long 0x0 1. " A ,Strict Alignment" "Disable,Enable"
bitfld.long 0x0 0. " M ,MPU Enable" "Disable,Enable"
textline " "
group.long c15:0x05++0x00
line.long 0x00 "DFSR,Data Fault Status Register"
bitfld.long 0x00 12. " EXT ,External Abort Qualifier" "DECERR,SLVERR"
bitfld.long 0x00 11. " RW ,Access Caused an Abort Type" "Read,Write"
textline " "
bitfld.long 0x00 4.--7. " DOMAIN ,Domain Accessed When a Data Fault Occurs" "D0,D1,D2,D3,D4,D5,D6,D7,D8,D9,D10,D11,D12,D13,D14,D15"
bitfld.long 0x00 0.--3. 10. " STATUS ,Generated Exception Type" "Reserved,Alignment,Debug,Access/section,Instruction,Translation/section,Access/page,Translation/page,Nontranslation/synchronous external,Domain/section,Reserved,Domain/page,L1/external,Permission/section,L2/external,Permission/page,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Asynchronous external,?..."
group.long c15:0x15++0x00
line.long 0x00 "ADFSR,Auxiliary Data Fault Status Register"
bitfld.long 0x00 24.--27. " CACHEWAY ,Cache way or ways in which the error occurred" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 22.--23. 20. " SIDE ,Source of the error" "Cache/AXIM,ATCM,BTCM,Reserved,Reserved,AXI,AHB,Reserved"
textline " "
bitfld.long 0x00 21. " REC_ERR ,Error recoverability indication" "Not recoverable,Recoverable"
bitfld.long 0x00 20. " SIDE_EXT ,Source of the error" "Internal,External"
textline " "
hexmask.long.word 0x00 5.--13. 1. " INDEX ,Index Value for The Access Giving the Error Register"
group.long c15:0x06++0x00
line.long 0x00 "DFAR,Data Fault Address Register"
textline " "
group.long c15:0x0105++0x00
line.long 0x00 "IFSR,Instruction Fault Status Register"
bitfld.long 0x00 12. " EXT ,External Abort Qualifier" "DECERR,SLVERR"
bitfld.long 0x00 0.--3. 10. " STATUS ,Generated Exception Type" "Reserved,Alignment,Debug,Access/section,Instruction,Translation/section,Access/page,Translation/page,Nontranslation/synchronous external,Domain/section,Reserved,Domain/page,L1/external,Permission/section,L2/external,Permission/page,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Asynchronous external,?..."
group.long c15:0x115++0x00
line.long 0x00 "AIFSR,Auxiliary Instruction Fault Status Register"
bitfld.long 0x00 24.--27. " CACHEWAY ,Cache way or ways in which the error occurred" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 22.--23. 20. " SIDE ,Source of the error" "Cache/AXIM,ATCM,BTCM,Reserved,Reserved,AXI,AHB,Reserved"
textline " "
bitfld.long 0x00 21. " REC_ERR ,Error recoverability indication" "Not recoverable,Recoverable"
bitfld.long 0x00 20. " SIDE_EXT ,Source of the error" "Internal,External"
textline " "
hexmask.long.word 0x00 5.--13. 1. " INDEX ,Index Value for The Access Giving the Error Register"
group.long c15:0x206++0x00
line.long 0x00 "IFAR,Instruction Fault Address Register"
textline " "
group.long c15:0x0016++0x00
line.long 0x00 "RBAR,Region Base Address Register"
hexmask.long 0x00 5.--31. 0x20 " BA ,Base address"
group.long c15:0x0216++0x00
line.long 0x00 "RSER,Region Size and Enable Register"
bitfld.long 0x00 15. " SD ,Subregion 7 disable" "-,D"
bitfld.long 0x00 14. " ,Subregion 6 disable" "-,D"
bitfld.long 0x00 13. " ,Subregion 5 disable" "-,D"
bitfld.long 0x00 12. " ,Subregion 4 disable" "-,D"
bitfld.long 0x00 11. " ,Subregion 3 disable" "-,D"
bitfld.long 0x00 10. " ,Subregion 2 disable" "-,D"
bitfld.long 0x00 9. " ,Subregion 1 disable" "-,D"
bitfld.long 0x00 8. " ,Subregion 0 disable" "-,D"
bitfld.long 0x00 1.--5. " RS ,Region size" "Unpredictable,Unpredictable,Unpredictable,Unpredictable,32 bytes,64 bytes,128 bytes,256 bytes,512 bytes,1KB,2KB,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB"
bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled"
group.long c15:0x0416++0x00
line.long 0x00 "RACR,Region Access Control Register"
bitfld.long 0x00 12. " XN ,Execute never" "-,NoExec"
bitfld.long 0x00 2. " S ,Share" "No,Yes"
bitfld.long 0x00 8.--10. " AP ,Access permission" "None,Privileged,User read-only,Full,Reserved,Privileged read,Read-only,Reserved"
bitfld.long 0x00 0.--1. 3.--5. " TYPE ,Region type" "Strongly-ordered,Shareable Device,Outer and Inner write-through/no write-allocate,Outer and Inner write-back/no write-allocate,Outer and Inner Non-cacheable,00101,00110,Outer and Inner write-back/write-allocate,Non-shareable Device,01001,01010,01011,01100,01101,01110,01111,O:Non-cacheable I:Non-cacheable,O:Non-cacheable I:Write-back/write-allocate,O:Non-cacheable I:Write-through/no write-allocate,O:Non-cacheable I:Write-back/no write-allocate,O:Write-back/write-allocate I:Non-cacheable,O:Write-back/write-allocate I:Write-back/write-allocate,O:Write-back/write-allocate I:Write-through/no write-allocate,O:Write-back/write-allocate I:Write-back/no write-allocate,O:Write-through/no write-allocate I:Non-cacheable,O:Write-through/no write-allocate I:Write-back/write-allocate,O:Write-through/no write-allocate I:Write-through/no write-allocate,O:Write-through/no write-allocate I:Write-back/no write-allocate,O:Write-back/no write-allocate I:Non-cacheable,O:Write-back/no write-allocate I:Write-back/write-allocate,O:Write-back/no write-allocate I:Write-through/no write-allocate,O:Write-back/no write-allocate I:Write-back/no write-allocate"
group.long c15:0x0026++0x00
line.long 0x00 "MRNR,Memory Region Number Register"
bitfld.long 0x00 0.--3. " REGION ,Defines the group of registers to be accessed" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
group.long c15:0x010d++0x00
line.long 0x00 "CIDR,Context ID Register"
group.long c15:0x20d++0x00
line.long 0x00 "TIDRURW,User read/write Thread and Process ID Register"
group.long c15:0x30d++0x00
line.long 0x00 "TIDRURO,User read only Thread and Process ID Register"
group.long c15:0x40d++0x00
line.long 0x00 "TIDRPRW,Privileged Only Thread and Process ID Register"
width 0x08
tree "MPU regions"
group c15:0x0016++0x00
saveout c15:0x26 %l 0x0
line.long 0x00 "RBAR0,Region Base Address Register 0"
hexmask.long 0x00 5.--31. 0x20 " BA ,Base address"
group c15:0x0216++0x00
saveout c15:0x26 %l 0x0
line.long 0x00 "RSER0,Region Size and Enable Register 0"
bitfld.long 0x00 15. " SD ,Subregion 7 disable" "-,D"
bitfld.long 0x00 14. " ,Subregion 6 disable" "-,D"
bitfld.long 0x00 13. " ,Subregion 5 disable" "-,D"
bitfld.long 0x00 12. " ,Subregion 4 disable" "-,D"
bitfld.long 0x00 11. " ,Subregion 3 disable" "-,D"
bitfld.long 0x00 10. " ,Subregion 2 disable" "-,D"
bitfld.long 0x00 9. " ,Subregion 1 disable" "-,D"
bitfld.long 0x00 8. " ,Subregion 0 disable" "-,D"
bitfld.long 0x00 1.--5. " RS ,Region size" "Unpredictable,Unpredictable,Unpredictable,Unpredictable,32 bytes,64 bytes,128 bytes,256 bytes,512 bytes,1KB,2KB,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB"
bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled"
group c15:0x0416++0x00
saveout c15:0x26 %l 0x0
line.long 0x00 "RACR0,Region Access Control Register 0"
bitfld.long 0x00 12. " XN ,Execute never" "-,NoExec"
bitfld.long 0x00 2. " S ,Share" "No,Yes"
bitfld.long 0x00 8.--10. " AP ,Access permission" "None,Privileged,User read-only,Full,Reserved,Privileged read,Read-only,Reserved"
bitfld.long 0x00 0.--1. 3.--5. " type ,Region type" "Strongly-ordered,Shareable Device,Outer and Inner write-through/no write-allocate,Outer and Inner write-back/no write-allocate,Outer and Inner Non-cacheable,00101,00110,Outer and Inner write-back/write-allocate,Non-shareable Device,01001,01010,01011,01100,01101,01110,01111,O:Non-cacheable I:Non-cacheable,O:Non-cacheable I:Write-back/write-allocate,O:Non-cacheable I:Write-through/no write-allocate,O:Non-cacheable I:Write-back/no write-allocate,O:Write-back/write-allocate I:Non-cacheable,O:Write-back/write-allocate I:Write-back/write-allocate,O:Write-back/write-allocate I:Write-through/no write-allocate,O:Write-back/write-allocate I:Write-back/no write-allocate,O:Write-through/no write-allocate I:Non-cacheable,O:Write-through/no write-allocate I:Write-back/write-allocate,O:Write-through/no write-allocate I:Write-through/no write-allocate,O:Write-through/no write-allocate I:Write-back/no write-allocate,O:Write-back/no write-allocate I:Non-cacheable,O:Write-back/no write-allocate I:Write-back/write-allocate,O:Write-back/no write-allocate I:Write-through/no write-allocate,O:Write-back/no write-allocate I:Write-back/no write-allocate"
textline " "
group c15:0x0016++0x00
saveout c15:0x26 %l 0x1
line.long 0x00 "RBAR1,Region Base Address Register 1"
hexmask.long 0x00 5.--31. 0x20 " BA ,Base address"
group c15:0x0216++0x00
saveout c15:0x26 %l 0x1
line.long 0x00 "RSER1,Region Size and Enable Register 1"
bitfld.long 0x00 15. " SD ,Subregion 7 disable" "-,D"
bitfld.long 0x00 14. " ,Subregion 6 disable" "-,D"
bitfld.long 0x00 13. " ,Subregion 5 disable" "-,D"
bitfld.long 0x00 12. " ,Subregion 4 disable" "-,D"
bitfld.long 0x00 11. " ,Subregion 3 disable" "-,D"
bitfld.long 0x00 10. " ,Subregion 2 disable" "-,D"
bitfld.long 0x00 9. " ,Subregion 1 disable" "-,D"
bitfld.long 0x00 8. " ,Subregion 0 disable" "-,D"
bitfld.long 0x00 1.--5. " RS ,Region size" "Unpredictable,Unpredictable,Unpredictable,Unpredictable,32 bytes,64 bytes,128 bytes,256 bytes,512 bytes,1KB,2KB,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB"
bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled"
group c15:0x0416++0x00
saveout c15:0x26 %l 0x1
line.long 0x00 "RACR1,Region Access Control Register 1"
bitfld.long 0x00 12. " XN ,Execute never" "-,NoExec"
bitfld.long 0x00 2. " S ,Share" "No,Yes"
bitfld.long 0x00 8.--10. " AP ,Access permission" "None,Privileged,User read-only,Full,Reserved,Privileged read,Read-only,Reserved"
bitfld.long 0x00 0.--1. 3.--5. " type ,Region type" "Strongly-ordered,Shareable Device,Outer and Inner write-through/no write-allocate,Outer and Inner write-back/no write-allocate,Outer and Inner Non-cacheable,00101,00110,Outer and Inner write-back/write-allocate,Non-shareable Device,01001,01010,01011,01100,01101,01110,01111,O:Non-cacheable I:Non-cacheable,O:Non-cacheable I:Write-back/write-allocate,O:Non-cacheable I:Write-through/no write-allocate,O:Non-cacheable I:Write-back/no write-allocate,O:Write-back/write-allocate I:Non-cacheable,O:Write-back/write-allocate I:Write-back/write-allocate,O:Write-back/write-allocate I:Write-through/no write-allocate,O:Write-back/write-allocate I:Write-back/no write-allocate,O:Write-through/no write-allocate I:Non-cacheable,O:Write-through/no write-allocate I:Write-back/write-allocate,O:Write-through/no write-allocate I:Write-through/no write-allocate,O:Write-through/no write-allocate I:Write-back/no write-allocate,O:Write-back/no write-allocate I:Non-cacheable,O:Write-back/no write-allocate I:Write-back/write-allocate,O:Write-back/no write-allocate I:Write-through/no write-allocate,O:Write-back/no write-allocate I:Write-back/no write-allocate"
textline " "
group c15:0x0016++0x00
saveout c15:0x26 %l 0x2
line.long 0x00 "RBAR2,Region Base Address Register 2"
hexmask.long 0x00 5.--31. 0x20 " BA ,Base address"
group c15:0x0216++0x00
saveout c15:0x26 %l 0x2
line.long 0x00 "RSER2,Region Size and Enable Register 2"
bitfld.long 0x00 15. " SD ,Subregion 7 disable" "-,D"
bitfld.long 0x00 14. " ,Subregion 6 disable" "-,D"
bitfld.long 0x00 13. " ,Subregion 5 disable" "-,D"
bitfld.long 0x00 12. " ,Subregion 4 disable" "-,D"
bitfld.long 0x00 11. " ,Subregion 3 disable" "-,D"
bitfld.long 0x00 10. " ,Subregion 2 disable" "-,D"
bitfld.long 0x00 9. " ,Subregion 1 disable" "-,D"
bitfld.long 0x00 8. " ,Subregion 0 disable" "-,D"
bitfld.long 0x00 1.--5. " RS ,Region size" "Unpredictable,Unpredictable,Unpredictable,Unpredictable,32 bytes,64 bytes,128 bytes,256 bytes,512 bytes,1KB,2KB,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB"
bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled"
group c15:0x0416++0x00
saveout c15:0x26 %l 0x2
line.long 0x00 "RACR2,Region Access Control Register 2"
bitfld.long 0x00 12. " XN ,Execute never" "-,NoExec"
bitfld.long 0x00 2. " S ,Share" "No,Yes"
bitfld.long 0x00 8.--10. " AP ,Access permission" "None,Privileged,User read-only,Full,Reserved,Privileged read,Read-only,Reserved"
bitfld.long 0x00 0.--1. 3.--5. " type ,Region type" "Strongly-ordered,Shareable Device,Outer and Inner write-through/no write-allocate,Outer and Inner write-back/no write-allocate,Outer and Inner Non-cacheable,00101,00110,Outer and Inner write-back/write-allocate,Non-shareable Device,01001,01010,01011,01100,01101,01110,01111,O:Non-cacheable I:Non-cacheable,O:Non-cacheable I:Write-back/write-allocate,O:Non-cacheable I:Write-through/no write-allocate,O:Non-cacheable I:Write-back/no write-allocate,O:Write-back/write-allocate I:Non-cacheable,O:Write-back/write-allocate I:Write-back/write-allocate,O:Write-back/write-allocate I:Write-through/no write-allocate,O:Write-back/write-allocate I:Write-back/no write-allocate,O:Write-through/no write-allocate I:Non-cacheable,O:Write-through/no write-allocate I:Write-back/write-allocate,O:Write-through/no write-allocate I:Write-through/no write-allocate,O:Write-through/no write-allocate I:Write-back/no write-allocate,O:Write-back/no write-allocate I:Non-cacheable,O:Write-back/no write-allocate I:Write-back/write-allocate,O:Write-back/no write-allocate I:Write-through/no write-allocate,O:Write-back/no write-allocate I:Write-back/no write-allocate"
textline " "
group c15:0x0016++0x00
saveout c15:0x26 %l 0x3
line.long 0x00 "RBAR3,Region Base Address Register 3"
hexmask.long 0x00 5.--31. 0x20 " BA ,Base address"
group c15:0x0216++0x00
saveout c15:0x26 %l 0x3
line.long 0x00 "RSER3,Region Size and Enable Register 3"
bitfld.long 0x00 15. " SD ,Subregion 7 disable" "-,D"
bitfld.long 0x00 14. " ,Subregion 6 disable" "-,D"
bitfld.long 0x00 13. " ,Subregion 5 disable" "-,D"
bitfld.long 0x00 12. " ,Subregion 4 disable" "-,D"
bitfld.long 0x00 11. " ,Subregion 3 disable" "-,D"
bitfld.long 0x00 10. " ,Subregion 2 disable" "-,D"
bitfld.long 0x00 9. " ,Subregion 1 disable" "-,D"
bitfld.long 0x00 8. " ,Subregion 0 disable" "-,D"
bitfld.long 0x00 1.--5. " RS ,Region size" "Unpredictable,Unpredictable,Unpredictable,Unpredictable,32 bytes,64 bytes,128 bytes,256 bytes,512 bytes,1KB,2KB,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB"
bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled"
group c15:0x0416++0x00
saveout c15:0x26 %l 0x3
line.long 0x00 "RACR3,Region Access Control Register 3"
bitfld.long 0x00 12. " XN ,Execute never" "-,NoExec"
bitfld.long 0x00 2. " S ,Share" "No,Yes"
bitfld.long 0x00 8.--10. " AP ,Access permission" "None,Privileged,User read-only,Full,Reserved,Privileged read,Read-only,Reserved"
bitfld.long 0x00 0.--1. 3.--5. " type ,Region type" "Strongly-ordered,Shareable Device,Outer and Inner write-through/no write-allocate,Outer and Inner write-back/no write-allocate,Outer and Inner Non-cacheable,00101,00110,Outer and Inner write-back/write-allocate,Non-shareable Device,01001,01010,01011,01100,01101,01110,01111,O:Non-cacheable I:Non-cacheable,O:Non-cacheable I:Write-back/write-allocate,O:Non-cacheable I:Write-through/no write-allocate,O:Non-cacheable I:Write-back/no write-allocate,O:Write-back/write-allocate I:Non-cacheable,O:Write-back/write-allocate I:Write-back/write-allocate,O:Write-back/write-allocate I:Write-through/no write-allocate,O:Write-back/write-allocate I:Write-back/no write-allocate,O:Write-through/no write-allocate I:Non-cacheable,O:Write-through/no write-allocate I:Write-back/write-allocate,O:Write-through/no write-allocate I:Write-through/no write-allocate,O:Write-through/no write-allocate I:Write-back/no write-allocate,O:Write-back/no write-allocate I:Non-cacheable,O:Write-back/no write-allocate I:Write-back/write-allocate,O:Write-back/no write-allocate I:Write-through/no write-allocate,O:Write-back/no write-allocate I:Write-back/no write-allocate"
textline " "
group c15:0x0016++0x00
saveout c15:0x26 %l 0x4
line.long 0x00 "RBAR4,Region Base Address Register 4"
hexmask.long 0x00 5.--31. 0x20 " BA ,Base address"
group c15:0x0216++0x00
saveout c15:0x26 %l 0x4
line.long 0x00 "RSER4,Region Size and Enable Register 4"
bitfld.long 0x00 15. " SD ,Subregion 7 disable" "-,D"
bitfld.long 0x00 14. " ,Subregion 6 disable" "-,D"
bitfld.long 0x00 13. " ,Subregion 5 disable" "-,D"
bitfld.long 0x00 12. " ,Subregion 4 disable" "-,D"
bitfld.long 0x00 11. " ,Subregion 3 disable" "-,D"
bitfld.long 0x00 10. " ,Subregion 2 disable" "-,D"
bitfld.long 0x00 9. " ,Subregion 1 disable" "-,D"
bitfld.long 0x00 8. " ,Subregion 0 disable" "-,D"
bitfld.long 0x00 1.--5. " RS ,Region size" "Unpredictable,Unpredictable,Unpredictable,Unpredictable,32 bytes,64 bytes,128 bytes,256 bytes,512 bytes,1KB,2KB,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB"
bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled"
group c15:0x0416++0x00
saveout c15:0x26 %l 0x4
line.long 0x00 "RACR4,Region Access Control Register 4"
bitfld.long 0x00 12. " XN ,Execute never" "-,NoExec"
bitfld.long 0x00 2. " S ,Share" "No,Yes"
bitfld.long 0x00 8.--10. " AP ,Access permission" "None,Privileged,User read-only,Full,Reserved,Privileged read,Read-only,Reserved"
bitfld.long 0x00 0.--1. 3.--5. " type ,Region type" "Strongly-ordered,Shareable Device,Outer and Inner write-through/no write-allocate,Outer and Inner write-back/no write-allocate,Outer and Inner Non-cacheable,00101,00110,Outer and Inner write-back/write-allocate,Non-shareable Device,01001,01010,01011,01100,01101,01110,01111,O:Non-cacheable I:Non-cacheable,O:Non-cacheable I:Write-back/write-allocate,O:Non-cacheable I:Write-through/no write-allocate,O:Non-cacheable I:Write-back/no write-allocate,O:Write-back/write-allocate I:Non-cacheable,O:Write-back/write-allocate I:Write-back/write-allocate,O:Write-back/write-allocate I:Write-through/no write-allocate,O:Write-back/write-allocate I:Write-back/no write-allocate,O:Write-through/no write-allocate I:Non-cacheable,O:Write-through/no write-allocate I:Write-back/write-allocate,O:Write-through/no write-allocate I:Write-through/no write-allocate,O:Write-through/no write-allocate I:Write-back/no write-allocate,O:Write-back/no write-allocate I:Non-cacheable,O:Write-back/no write-allocate I:Write-back/write-allocate,O:Write-back/no write-allocate I:Write-through/no write-allocate,O:Write-back/no write-allocate I:Write-back/no write-allocate"
textline " "
group c15:0x0016++0x00
saveout c15:0x26 %l 0x5
line.long 0x00 "RBAR5,Region Base Address Register 5"
hexmask.long 0x00 5.--31. 0x20 " BA ,Base address"
group c15:0x0216++0x00
saveout c15:0x26 %l 0x5
line.long 0x00 "RSER5,Region Size and Enable Register 5"
bitfld.long 0x00 15. " SD ,Subregion 7 disable" "-,D"
bitfld.long 0x00 14. " ,Subregion 6 disable" "-,D"
bitfld.long 0x00 13. " ,Subregion 5 disable" "-,D"
bitfld.long 0x00 12. " ,Subregion 4 disable" "-,D"
bitfld.long 0x00 11. " ,Subregion 3 disable" "-,D"
bitfld.long 0x00 10. " ,Subregion 2 disable" "-,D"
bitfld.long 0x00 9. " ,Subregion 1 disable" "-,D"
bitfld.long 0x00 8. " ,Subregion 0 disable" "-,D"
bitfld.long 0x00 1.--5. " RS ,Region size" "Unpredictable,Unpredictable,Unpredictable,Unpredictable,32 bytes,64 bytes,128 bytes,256 bytes,512 bytes,1KB,2KB,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB"
bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled"
group c15:0x0416++0x00
saveout c15:0x26 %l 0x5
line.long 0x00 "RACR5,Region Access Control Register 5"
bitfld.long 0x00 12. " XN ,Execute never" "-,NoExec"
bitfld.long 0x00 2. " S ,Share" "No,Yes"
bitfld.long 0x00 8.--10. " AP ,Access permission" "None,Privileged,User read-only,Full,Reserved,Privileged read,Read-only,Reserved"
bitfld.long 0x00 0.--1. 3.--5. " type ,Region type" "Strongly-ordered,Shareable Device,Outer and Inner write-through/no write-allocate,Outer and Inner write-back/no write-allocate,Outer and Inner Non-cacheable,00101,00110,Outer and Inner write-back/write-allocate,Non-shareable Device,01001,01010,01011,01100,01101,01110,01111,O:Non-cacheable I:Non-cacheable,O:Non-cacheable I:Write-back/write-allocate,O:Non-cacheable I:Write-through/no write-allocate,O:Non-cacheable I:Write-back/no write-allocate,O:Write-back/write-allocate I:Non-cacheable,O:Write-back/write-allocate I:Write-back/write-allocate,O:Write-back/write-allocate I:Write-through/no write-allocate,O:Write-back/write-allocate I:Write-back/no write-allocate,O:Write-through/no write-allocate I:Non-cacheable,O:Write-through/no write-allocate I:Write-back/write-allocate,O:Write-through/no write-allocate I:Write-through/no write-allocate,O:Write-through/no write-allocate I:Write-back/no write-allocate,O:Write-back/no write-allocate I:Non-cacheable,O:Write-back/no write-allocate I:Write-back/write-allocate,O:Write-back/no write-allocate I:Write-through/no write-allocate,O:Write-back/no write-allocate I:Write-back/no write-allocate"
textline " "
group c15:0x0016++0x00
saveout c15:0x26 %l 0x6
line.long 0x00 "RBAR6,Region Base Address Register 6"
hexmask.long 0x00 5.--31. 0x20 " BA ,Base address"
group c15:0x0216++0x00
saveout c15:0x26 %l 0x6
line.long 0x00 "RSER6,Region Size and Enable Register 6"
bitfld.long 0x00 15. " SD ,Subregion 7 disable" "-,D"
bitfld.long 0x00 14. " ,Subregion 6 disable" "-,D"
bitfld.long 0x00 13. " ,Subregion 5 disable" "-,D"
bitfld.long 0x00 12. " ,Subregion 4 disable" "-,D"
bitfld.long 0x00 11. " ,Subregion 3 disable" "-,D"
bitfld.long 0x00 10. " ,Subregion 2 disable" "-,D"
bitfld.long 0x00 9. " ,Subregion 1 disable" "-,D"
bitfld.long 0x00 8. " ,Subregion 0 disable" "-,D"
bitfld.long 0x00 1.--5. " RS ,Region size" "Unpredictable,Unpredictable,Unpredictable,Unpredictable,32 bytes,64 bytes,128 bytes,256 bytes,512 bytes,1KB,2KB,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB"
bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled"
group c15:0x0416++0x00
saveout c15:0x26 %l 0x6
line.long 0x00 "RACR6,Region Access Control Register 6"
bitfld.long 0x00 12. " XN ,Execute never" "-,NoExec"
bitfld.long 0x00 2. " S ,Share" "No,Yes"
bitfld.long 0x00 8.--10. " AP ,Access permission" "None,Privileged,User read-only,Full,Reserved,Privileged read,Read-only,Reserved"
bitfld.long 0x00 0.--1. 3.--5. " type ,Region type" "Strongly-ordered,Shareable Device,Outer and Inner write-through/no write-allocate,Outer and Inner write-back/no write-allocate,Outer and Inner Non-cacheable,00101,00110,Outer and Inner write-back/write-allocate,Non-shareable Device,01001,01010,01011,01100,01101,01110,01111,O:Non-cacheable I:Non-cacheable,O:Non-cacheable I:Write-back/write-allocate,O:Non-cacheable I:Write-through/no write-allocate,O:Non-cacheable I:Write-back/no write-allocate,O:Write-back/write-allocate I:Non-cacheable,O:Write-back/write-allocate I:Write-back/write-allocate,O:Write-back/write-allocate I:Write-through/no write-allocate,O:Write-back/write-allocate I:Write-back/no write-allocate,O:Write-through/no write-allocate I:Non-cacheable,O:Write-through/no write-allocate I:Write-back/write-allocate,O:Write-through/no write-allocate I:Write-through/no write-allocate,O:Write-through/no write-allocate I:Write-back/no write-allocate,O:Write-back/no write-allocate I:Non-cacheable,O:Write-back/no write-allocate I:Write-back/write-allocate,O:Write-back/no write-allocate I:Write-through/no write-allocate,O:Write-back/no write-allocate I:Write-back/no write-allocate"
textline " "
group c15:0x0016++0x00
saveout c15:0x26 %l 0x7
line.long 0x00 "RBAR7,Region Base Address Register 7"
hexmask.long 0x00 5.--31. 0x20 " BA ,Base address"
group c15:0x0216++0x00
saveout c15:0x26 %l 0x7
line.long 0x00 "RSER7,Region Size and Enable Register 7"
bitfld.long 0x00 15. " SD ,Subregion 7 disable" "-,D"
bitfld.long 0x00 14. " ,Subregion 6 disable" "-,D"
bitfld.long 0x00 13. " ,Subregion 5 disable" "-,D"
bitfld.long 0x00 12. " ,Subregion 4 disable" "-,D"
bitfld.long 0x00 11. " ,Subregion 3 disable" "-,D"
bitfld.long 0x00 10. " ,Subregion 2 disable" "-,D"
bitfld.long 0x00 9. " ,Subregion 1 disable" "-,D"
bitfld.long 0x00 8. " ,Subregion 0 disable" "-,D"
bitfld.long 0x00 1.--5. " RS ,Region size" "Unpredictable,Unpredictable,Unpredictable,Unpredictable,32 bytes,64 bytes,128 bytes,256 bytes,512 bytes,1KB,2KB,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB"
bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled"
group c15:0x0416++0x00
saveout c15:0x26 %l 0x7
line.long 0x00 "RACR7,Region Access Control Register 7"
bitfld.long 0x00 12. " XN ,Execute never" "-,NoExec"
bitfld.long 0x00 2. " S ,Share" "No,Yes"
bitfld.long 0x00 8.--10. " AP ,Access permission" "None,Privileged,User read-only,Full,Reserved,Privileged read,Read-only,Reserved"
bitfld.long 0x00 0.--1. 3.--5. " type ,Region type" "Strongly-ordered,Shareable Device,Outer and Inner write-through/no write-allocate,Outer and Inner write-back/no write-allocate,Outer and Inner Non-cacheable,00101,00110,Outer and Inner write-back/write-allocate,Non-shareable Device,01001,01010,01011,01100,01101,01110,01111,O:Non-cacheable I:Non-cacheable,O:Non-cacheable I:Write-back/write-allocate,O:Non-cacheable I:Write-through/no write-allocate,O:Non-cacheable I:Write-back/no write-allocate,O:Write-back/write-allocate I:Non-cacheable,O:Write-back/write-allocate I:Write-back/write-allocate,O:Write-back/write-allocate I:Write-through/no write-allocate,O:Write-back/write-allocate I:Write-back/no write-allocate,O:Write-through/no write-allocate I:Non-cacheable,O:Write-through/no write-allocate I:Write-back/write-allocate,O:Write-through/no write-allocate I:Write-through/no write-allocate,O:Write-through/no write-allocate I:Write-back/no write-allocate,O:Write-back/no write-allocate I:Non-cacheable,O:Write-back/no write-allocate I:Write-back/write-allocate,O:Write-back/no write-allocate I:Write-through/no write-allocate,O:Write-back/no write-allocate I:Write-back/no write-allocate"
textline " "
group c15:0x0016++0x00
saveout c15:0x26 %l 0x8
line.long 0x00 "RBAR8,Region Base Address Register 8"
hexmask.long 0x00 5.--31. 0x20 " BA ,Base address"
group c15:0x0216++0x00
saveout c15:0x26 %l 0x8
line.long 0x00 "RSER8,Region Size and Enable Register 8"
bitfld.long 0x00 15. " SD ,Subregion 7 disable" "-,D"
bitfld.long 0x00 14. " ,Subregion 6 disable" "-,D"
bitfld.long 0x00 13. " ,Subregion 5 disable" "-,D"
bitfld.long 0x00 12. " ,Subregion 4 disable" "-,D"
bitfld.long 0x00 11. " ,Subregion 3 disable" "-,D"
bitfld.long 0x00 10. " ,Subregion 2 disable" "-,D"
bitfld.long 0x00 9. " ,Subregion 1 disable" "-,D"
bitfld.long 0x00 8. " ,Subregion 0 disable" "-,D"
bitfld.long 0x00 1.--5. " RS ,Region size" "Unpredictable,Unpredictable,Unpredictable,Unpredictable,32 bytes,64 bytes,128 bytes,256 bytes,512 bytes,1KB,2KB,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB"
bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled"
group c15:0x0416++0x00
saveout c15:0x26 %l 0x8
line.long 0x00 "RACR8,Region Access Control Register 8"
bitfld.long 0x00 12. " XN ,Execute never" "-,NoExec"
bitfld.long 0x00 2. " S ,Share" "No,Yes"
bitfld.long 0x00 8.--10. " AP ,Access permission" "None,Privileged,User read-only,Full,Reserved,Privileged read,Read-only,Reserved"
bitfld.long 0x00 0.--1. 3.--5. " type ,Region type" "Strongly-ordered,Shareable Device,Outer and Inner write-through/no write-allocate,Outer and Inner write-back/no write-allocate,Outer and Inner Non-cacheable,00101,00110,Outer and Inner write-back/write-allocate,Non-shareable Device,01001,01010,01011,01100,01101,01110,01111,O:Non-cacheable I:Non-cacheable,O:Non-cacheable I:Write-back/write-allocate,O:Non-cacheable I:Write-through/no write-allocate,O:Non-cacheable I:Write-back/no write-allocate,O:Write-back/write-allocate I:Non-cacheable,O:Write-back/write-allocate I:Write-back/write-allocate,O:Write-back/write-allocate I:Write-through/no write-allocate,O:Write-back/write-allocate I:Write-back/no write-allocate,O:Write-through/no write-allocate I:Non-cacheable,O:Write-through/no write-allocate I:Write-back/write-allocate,O:Write-through/no write-allocate I:Write-through/no write-allocate,O:Write-through/no write-allocate I:Write-back/no write-allocate,O:Write-back/no write-allocate I:Non-cacheable,O:Write-back/no write-allocate I:Write-back/write-allocate,O:Write-back/no write-allocate I:Write-through/no write-allocate,O:Write-back/no write-allocate I:Write-back/no write-allocate"
textline " "
group c15:0x0016++0x00
saveout c15:0x26 %l 0x9
line.long 0x00 "RBAR9,Region Base Address Register 9"
hexmask.long 0x00 5.--31. 0x20 " BA ,Base address"
group c15:0x0216++0x00
saveout c15:0x26 %l 0x9
line.long 0x00 "RSER9,Region Size and Enable Register 9"
bitfld.long 0x00 15. " SD ,Subregion 7 disable" "-,D"
bitfld.long 0x00 14. " ,Subregion 6 disable" "-,D"
bitfld.long 0x00 13. " ,Subregion 5 disable" "-,D"
bitfld.long 0x00 12. " ,Subregion 4 disable" "-,D"
bitfld.long 0x00 11. " ,Subregion 3 disable" "-,D"
bitfld.long 0x00 10. " ,Subregion 2 disable" "-,D"
bitfld.long 0x00 9. " ,Subregion 1 disable" "-,D"
bitfld.long 0x00 8. " ,Subregion 0 disable" "-,D"
bitfld.long 0x00 1.--5. " RS ,Region size" "Unpredictable,Unpredictable,Unpredictable,Unpredictable,32 bytes,64 bytes,128 bytes,256 bytes,512 bytes,1KB,2KB,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB"
bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled"
group c15:0x0416++0x00
saveout c15:0x26 %l 0x9
line.long 0x00 "RACR9,Region Access Control Register 9"
bitfld.long 0x00 12. " XN ,Execute never" "-,NoExec"
bitfld.long 0x00 2. " S ,Share" "No,Yes"
bitfld.long 0x00 8.--10. " AP ,Access permission" "None,Privileged,User read-only,Full,Reserved,Privileged read,Read-only,Reserved"
bitfld.long 0x00 0.--1. 3.--5. " type ,Region type" "Strongly-ordered,Shareable Device,Outer and Inner write-through/no write-allocate,Outer and Inner write-back/no write-allocate,Outer and Inner Non-cacheable,00101,00110,Outer and Inner write-back/write-allocate,Non-shareable Device,01001,01010,01011,01100,01101,01110,01111,O:Non-cacheable I:Non-cacheable,O:Non-cacheable I:Write-back/write-allocate,O:Non-cacheable I:Write-through/no write-allocate,O:Non-cacheable I:Write-back/no write-allocate,O:Write-back/write-allocate I:Non-cacheable,O:Write-back/write-allocate I:Write-back/write-allocate,O:Write-back/write-allocate I:Write-through/no write-allocate,O:Write-back/write-allocate I:Write-back/no write-allocate,O:Write-through/no write-allocate I:Non-cacheable,O:Write-through/no write-allocate I:Write-back/write-allocate,O:Write-through/no write-allocate I:Write-through/no write-allocate,O:Write-through/no write-allocate I:Write-back/no write-allocate,O:Write-back/no write-allocate I:Non-cacheable,O:Write-back/no write-allocate I:Write-back/write-allocate,O:Write-back/no write-allocate I:Write-through/no write-allocate,O:Write-back/no write-allocate I:Write-back/no write-allocate"
textline " "
group c15:0x0016++0x00
saveout c15:0x26 %l 0xA
line.long 0x00 "RBAR10,Region Base Address Register 10"
hexmask.long 0x00 5.--31. 0x20 " BA ,Base address"
group c15:0x0216++0x00
saveout c15:0x26 %l 0xA
line.long 0x00 "RSER10,Region Size and Enable Register 10"
bitfld.long 0x00 15. " SD ,Subregion 7 disable" "-,D"
bitfld.long 0x00 14. " ,Subregion 6 disable" "-,D"
bitfld.long 0x00 13. " ,Subregion 5 disable" "-,D"
bitfld.long 0x00 12. " ,Subregion 4 disable" "-,D"
bitfld.long 0x00 11. " ,Subregion 3 disable" "-,D"
bitfld.long 0x00 10. " ,Subregion 2 disable" "-,D"
bitfld.long 0x00 9. " ,Subregion 1 disable" "-,D"
bitfld.long 0x00 8. " ,Subregion 0 disable" "-,D"
bitfld.long 0x00 1.--5. " RS ,Region size" "Unpredictable,Unpredictable,Unpredictable,Unpredictable,32 bytes,64 bytes,128 bytes,256 bytes,512 bytes,1KB,2KB,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB"
bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled"
group c15:0x0416++0x00
saveout c15:0x26 %l 0xA
line.long 0x00 "RACR10,Region Access Control Register 10"
bitfld.long 0x00 12. " XN ,Execute never" "-,NoExec"
bitfld.long 0x00 2. " S ,Share" "No,Yes"
bitfld.long 0x00 8.--10. " AP ,Access permission" "None,Privileged,User read-only,Full,Reserved,Privileged read,Read-only,Reserved"
bitfld.long 0x00 0.--1. 3.--5. " type ,Region type" "Strongly-ordered,Shareable Device,Outer and Inner write-through/no write-allocate,Outer and Inner write-back/no write-allocate,Outer and Inner Non-cacheable,00101,00110,Outer and Inner write-back/write-allocate,Non-shareable Device,01001,01010,01011,01100,01101,01110,01111,O:Non-cacheable I:Non-cacheable,O:Non-cacheable I:Write-back/write-allocate,O:Non-cacheable I:Write-through/no write-allocate,O:Non-cacheable I:Write-back/no write-allocate,O:Write-back/write-allocate I:Non-cacheable,O:Write-back/write-allocate I:Write-back/write-allocate,O:Write-back/write-allocate I:Write-through/no write-allocate,O:Write-back/write-allocate I:Write-back/no write-allocate,O:Write-through/no write-allocate I:Non-cacheable,O:Write-through/no write-allocate I:Write-back/write-allocate,O:Write-through/no write-allocate I:Write-through/no write-allocate,O:Write-through/no write-allocate I:Write-back/no write-allocate,O:Write-back/no write-allocate I:Non-cacheable,O:Write-back/no write-allocate I:Write-back/write-allocate,O:Write-back/no write-allocate I:Write-through/no write-allocate,O:Write-back/no write-allocate I:Write-back/no write-allocate"
textline " "
group c15:0x0016++0x00
saveout c15:0x26 %l 0xB
line.long 0x00 "RBAR11,Region Base Address Register 11"
hexmask.long 0x00 5.--31. 0x20 " BA ,Base address"
group c15:0x0216++0x00
saveout c15:0x26 %l 0xB
line.long 0x00 "RSER11,Region Size and Enable Register 11"
bitfld.long 0x00 15. " SD ,Subregion 7 disable" "-,D"
bitfld.long 0x00 14. " ,Subregion 6 disable" "-,D"
bitfld.long 0x00 13. " ,Subregion 5 disable" "-,D"
bitfld.long 0x00 12. " ,Subregion 4 disable" "-,D"
bitfld.long 0x00 11. " ,Subregion 3 disable" "-,D"
bitfld.long 0x00 10. " ,Subregion 2 disable" "-,D"
bitfld.long 0x00 9. " ,Subregion 1 disable" "-,D"
bitfld.long 0x00 8. " ,Subregion 0 disable" "-,D"
bitfld.long 0x00 1.--5. " RS ,Region size" "Unpredictable,Unpredictable,Unpredictable,Unpredictable,32 bytes,64 bytes,128 bytes,256 bytes,512 bytes,1KB,2KB,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB"
bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled"
group c15:0x0416++0x00
saveout c15:0x26 %l 0xB
line.long 0x00 "RACR11,Region Access Control Register 11"
bitfld.long 0x00 12. " XN ,Execute never" "-,NoExec"
bitfld.long 0x00 2. " S ,Share" "No,Yes"
bitfld.long 0x00 8.--10. " AP ,Access permission" "None,Privileged,User read-only,Full,Reserved,Privileged read,Read-only,Reserved"
bitfld.long 0x00 0.--1. 3.--5. " type ,Region type" "Strongly-ordered,Shareable Device,Outer and Inner write-through/no write-allocate,Outer and Inner write-back/no write-allocate,Outer and Inner Non-cacheable,00101,00110,Outer and Inner write-back/write-allocate,Non-shareable Device,01001,01010,01011,01100,01101,01110,01111,O:Non-cacheable I:Non-cacheable,O:Non-cacheable I:Write-back/write-allocate,O:Non-cacheable I:Write-through/no write-allocate,O:Non-cacheable I:Write-back/no write-allocate,O:Write-back/write-allocate I:Non-cacheable,O:Write-back/write-allocate I:Write-back/write-allocate,O:Write-back/write-allocate I:Write-through/no write-allocate,O:Write-back/write-allocate I:Write-back/no write-allocate,O:Write-through/no write-allocate I:Non-cacheable,O:Write-through/no write-allocate I:Write-back/write-allocate,O:Write-through/no write-allocate I:Write-through/no write-allocate,O:Write-through/no write-allocate I:Write-back/no write-allocate,O:Write-back/no write-allocate I:Non-cacheable,O:Write-back/no write-allocate I:Write-back/write-allocate,O:Write-back/no write-allocate I:Write-through/no write-allocate,O:Write-back/no write-allocate I:Write-back/no write-allocate"
textline " "
group c15:0x0016++0x00
saveout c15:0x26 %l 0xC
line.long 0x00 "RBAR12,Region Base Address Register 12"
hexmask.long 0x00 5.--31. 0x20 " BA ,Base address"
group c15:0x0216++0x00
saveout c15:0x26 %l 0xC
line.long 0x00 "RSER12,Region Size and Enable Register 12"
bitfld.long 0x00 15. " SD ,Subregion 7 disable" "-,D"
bitfld.long 0x00 14. " ,Subregion 6 disable" "-,D"
bitfld.long 0x00 13. " ,Subregion 5 disable" "-,D"
bitfld.long 0x00 12. " ,Subregion 4 disable" "-,D"
bitfld.long 0x00 11. " ,Subregion 3 disable" "-,D"
bitfld.long 0x00 10. " ,Subregion 2 disable" "-,D"
bitfld.long 0x00 9. " ,Subregion 1 disable" "-,D"
bitfld.long 0x00 8. " ,Subregion 0 disable" "-,D"
bitfld.long 0x00 1.--5. " RS ,Region size" "Unpredictable,Unpredictable,Unpredictable,Unpredictable,32 bytes,64 bytes,128 bytes,256 bytes,512 bytes,1KB,2KB,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB"
bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled"
group c15:0x0416++0x00
saveout c15:0x26 %l 0xC
line.long 0x00 "RACR12,Region Access Control Register 12"
bitfld.long 0x00 12. " XN ,Execute never" "-,NoExec"
bitfld.long 0x00 2. " S ,Share" "No,Yes"
bitfld.long 0x00 8.--10. " AP ,Access permission" "None,Privileged,User read-only,Full,Reserved,Privileged read,Read-only,Reserved"
bitfld.long 0x00 0.--1. 3.--5. " type ,Region type" "Strongly-ordered,Shareable Device,Outer and Inner write-through/no write-allocate,Outer and Inner write-back/no write-allocate,Outer and Inner Non-cacheable,00101,00110,Outer and Inner write-back/write-allocate,Non-shareable Device,01001,01010,01011,01100,01101,01110,01111,O:Non-cacheable I:Non-cacheable,O:Non-cacheable I:Write-back/write-allocate,O:Non-cacheable I:Write-through/no write-allocate,O:Non-cacheable I:Write-back/no write-allocate,O:Write-back/write-allocate I:Non-cacheable,O:Write-back/write-allocate I:Write-back/write-allocate,O:Write-back/write-allocate I:Write-through/no write-allocate,O:Write-back/write-allocate I:Write-back/no write-allocate,O:Write-through/no write-allocate I:Non-cacheable,O:Write-through/no write-allocate I:Write-back/write-allocate,O:Write-through/no write-allocate I:Write-through/no write-allocate,O:Write-through/no write-allocate I:Write-back/no write-allocate,O:Write-back/no write-allocate I:Non-cacheable,O:Write-back/no write-allocate I:Write-back/write-allocate,O:Write-back/no write-allocate I:Write-through/no write-allocate,O:Write-back/no write-allocate I:Write-back/no write-allocate"
textline " "
group c15:0x0016++0x00
saveout c15:0x26 %l 0xD
line.long 0x00 "RBAR13,Region Base Address Register 13"
hexmask.long 0x00 5.--31. 0x20 " BA ,Base address"
group c15:0x0216++0x00
saveout c15:0x26 %l 0xD
line.long 0x00 "RSER13,Region Size and Enable Register 13"
bitfld.long 0x00 15. " SD ,Subregion 7 disable" "-,D"
bitfld.long 0x00 14. " ,Subregion 6 disable" "-,D"
bitfld.long 0x00 13. " ,Subregion 5 disable" "-,D"
bitfld.long 0x00 12. " ,Subregion 4 disable" "-,D"
bitfld.long 0x00 11. " ,Subregion 3 disable" "-,D"
bitfld.long 0x00 10. " ,Subregion 2 disable" "-,D"
bitfld.long 0x00 9. " ,Subregion 1 disable" "-,D"
bitfld.long 0x00 8. " ,Subregion 0 disable" "-,D"
bitfld.long 0x00 1.--5. " RS ,Region size" "Unpredictable,Unpredictable,Unpredictable,Unpredictable,32 bytes,64 bytes,128 bytes,256 bytes,512 bytes,1KB,2KB,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB"
bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled"
group c15:0x0416++0x00
saveout c15:0x26 %l 0xD
line.long 0x00 "RACR13,Region Access Control Register 13"
bitfld.long 0x00 12. " XN ,Execute never" "-,NoExec"
bitfld.long 0x00 2. " S ,Share" "No,Yes"
bitfld.long 0x00 8.--10. " AP ,Access permission" "None,Privileged,User read-only,Full,Reserved,Privileged read,Read-only,Reserved"
bitfld.long 0x00 0.--1. 3.--5. " type ,Region type" "Strongly-ordered,Shareable Device,Outer and Inner write-through/no write-allocate,Outer and Inner write-back/no write-allocate,Outer and Inner Non-cacheable,00101,00110,Outer and Inner write-back/write-allocate,Non-shareable Device,01001,01010,01011,01100,01101,01110,01111,O:Non-cacheable I:Non-cacheable,O:Non-cacheable I:Write-back/write-allocate,O:Non-cacheable I:Write-through/no write-allocate,O:Non-cacheable I:Write-back/no write-allocate,O:Write-back/write-allocate I:Non-cacheable,O:Write-back/write-allocate I:Write-back/write-allocate,O:Write-back/write-allocate I:Write-through/no write-allocate,O:Write-back/write-allocate I:Write-back/no write-allocate,O:Write-through/no write-allocate I:Non-cacheable,O:Write-through/no write-allocate I:Write-back/write-allocate,O:Write-through/no write-allocate I:Write-through/no write-allocate,O:Write-through/no write-allocate I:Write-back/no write-allocate,O:Write-back/no write-allocate I:Non-cacheable,O:Write-back/no write-allocate I:Write-back/write-allocate,O:Write-back/no write-allocate I:Write-through/no write-allocate,O:Write-back/no write-allocate I:Write-back/no write-allocate"
textline " "
group c15:0x0016++0x00
saveout c15:0x26 %l 0xE
line.long 0x00 "RBAR14,Region Base Address Register 14"
hexmask.long 0x00 5.--31. 0x20 " BA ,Base address"
group c15:0x0216++0x00
saveout c15:0x26 %l 0xE
line.long 0x00 "RSER14,Region Size and Enable Register 14"
bitfld.long 0x00 15. " SD ,Subregion 7 disable" "-,D"
bitfld.long 0x00 14. " ,Subregion 6 disable" "-,D"
bitfld.long 0x00 13. " ,Subregion 5 disable" "-,D"
bitfld.long 0x00 12. " ,Subregion 4 disable" "-,D"
bitfld.long 0x00 11. " ,Subregion 3 disable" "-,D"
bitfld.long 0x00 10. " ,Subregion 2 disable" "-,D"
bitfld.long 0x00 9. " ,Subregion 1 disable" "-,D"
bitfld.long 0x00 8. " ,Subregion 0 disable" "-,D"
bitfld.long 0x00 1.--5. " RS ,Region size" "Unpredictable,Unpredictable,Unpredictable,Unpredictable,32 bytes,64 bytes,128 bytes,256 bytes,512 bytes,1KB,2KB,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB"
bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled"
group c15:0x0416++0x00
saveout c15:0x26 %l 0xE
line.long 0x00 "RACR14,Region Access Control Register 14"
bitfld.long 0x00 12. " XN ,Execute never" "-,NoExec"
bitfld.long 0x00 2. " S ,Share" "No,Yes"
bitfld.long 0x00 8.--10. " AP ,Access permission" "None,Privileged,User read-only,Full,Reserved,Privileged read,Read-only,Reserved"
bitfld.long 0x00 0.--1. 3.--5. " type ,Region type" "Strongly-ordered,Shareable Device,Outer and Inner write-through/no write-allocate,Outer and Inner write-back/no write-allocate,Outer and Inner Non-cacheable,00101,00110,Outer and Inner write-back/write-allocate,Non-shareable Device,01001,01010,01011,01100,01101,01110,01111,O:Non-cacheable I:Non-cacheable,O:Non-cacheable I:Write-back/write-allocate,O:Non-cacheable I:Write-through/no write-allocate,O:Non-cacheable I:Write-back/no write-allocate,O:Write-back/write-allocate I:Non-cacheable,O:Write-back/write-allocate I:Write-back/write-allocate,O:Write-back/write-allocate I:Write-through/no write-allocate,O:Write-back/write-allocate I:Write-back/no write-allocate,O:Write-through/no write-allocate I:Non-cacheable,O:Write-through/no write-allocate I:Write-back/write-allocate,O:Write-through/no write-allocate I:Write-through/no write-allocate,O:Write-through/no write-allocate I:Write-back/no write-allocate,O:Write-back/no write-allocate I:Non-cacheable,O:Write-back/no write-allocate I:Write-back/write-allocate,O:Write-back/no write-allocate I:Write-through/no write-allocate,O:Write-back/no write-allocate I:Write-back/no write-allocate"
textline " "
group c15:0x0016++0x00
saveout c15:0x26 %l 0xF
line.long 0x00 "RBAR15,Region Base Address Register 15"
hexmask.long 0x00 5.--31. 0x20 " BA ,Base address"
group c15:0x0216++0x00
saveout c15:0x26 %l 0xF
line.long 0x00 "RSER15,Region Size and Enable Register 15"
bitfld.long 0x00 15. " SD ,Subregion 7 disable" "-,D"
bitfld.long 0x00 14. " ,Subregion 6 disable" "-,D"
bitfld.long 0x00 13. " ,Subregion 5 disable" "-,D"
bitfld.long 0x00 12. " ,Subregion 4 disable" "-,D"
bitfld.long 0x00 11. " ,Subregion 3 disable" "-,D"
bitfld.long 0x00 10. " ,Subregion 2 disable" "-,D"
bitfld.long 0x00 9. " ,Subregion 1 disable" "-,D"
bitfld.long 0x00 8. " ,Subregion 0 disable" "-,D"
bitfld.long 0x00 1.--5. " RS ,Region size" "Unpredictable,Unpredictable,Unpredictable,Unpredictable,32 bytes,64 bytes,128 bytes,256 bytes,512 bytes,1KB,2KB,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB"
bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled"
group c15:0x0416++0x00
saveout c15:0x26 %l 0xF
line.long 0x00 "RACR15,Region Access Control Register 15"
bitfld.long 0x00 12. " XN ,Execute never" "-,NoExec"
bitfld.long 0x00 2. " S ,Share" "No,Yes"
bitfld.long 0x00 8.--10. " AP ,Access permission" "None,Privileged,User read-only,Full,Reserved,Privileged read,Read-only,Reserved"
bitfld.long 0x00 0.--1. 3.--5. " type ,Region type" "Strongly-ordered,Shareable Device,Outer and Inner write-through/no write-allocate,Outer and Inner write-back/no write-allocate,Outer and Inner Non-cacheable,00101,00110,Outer and Inner write-back/write-allocate,Non-shareable Device,01001,01010,01011,01100,01101,01110,01111,O:Non-cacheable I:Non-cacheable,O:Non-cacheable I:Write-back/write-allocate,O:Non-cacheable I:Write-through/no write-allocate,O:Non-cacheable I:Write-back/no write-allocate,O:Write-back/write-allocate I:Non-cacheable,O:Write-back/write-allocate I:Write-back/write-allocate,O:Write-back/write-allocate I:Write-through/no write-allocate,O:Write-back/write-allocate I:Write-back/no write-allocate,O:Write-through/no write-allocate I:Non-cacheable,O:Write-through/no write-allocate I:Write-back/write-allocate,O:Write-through/no write-allocate I:Write-through/no write-allocate,O:Write-through/no write-allocate I:Write-back/no write-allocate,O:Write-back/no write-allocate I:Non-cacheable,O:Write-back/no write-allocate I:Write-back/write-allocate,O:Write-back/no write-allocate I:Write-through/no write-allocate,O:Write-back/no write-allocate I:Write-back/no write-allocate"
textline " "
tree.end
tree.end
width 0x9
tree "TCM Control and Configuration"
rgroup.long c15:0x200++0x00
line.long 0x00 "TCMTR,TCM Type Register"
bitfld.long 0x00 16.--18. " BTCM ,Number of BTCMs implemented" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0.--2. " ATCM ,Number of ATCMs implemented" "0,1,2,3,4,5,6,7"
group.long c15:0x019++0x00
line.long 0x00 "BTCMRR,BTCM Region Register"
hexmask.long 0x00 12.--31. 0x1000 " BA ,Base address (physical address)"
bitfld.long 0x00 2.--6. " SIZE ,Size of instruction TCM on reads" "None,Reserved,Reserved,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16M,32M,64M,128M,256M,512M,1G,2G,4G,?..."
bitfld.long 0x00 0. " EN ,Enable instruction TCM" "Disabled,Enabled"
group.long c15:0x119++0x00
line.long 0x00 "ATCMRR,ATCM Region Register"
hexmask.long 0x00 12.--31. 0x1000 " BA ,Base address (physical address)"
bitfld.long 0x00 2.--6. " SIZE ,Size of instruction TCM on reads" "None,Reserved,Reserved,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16M,32M,64M,128M,256M,512M,1G,2G,4G,?..."
bitfld.long 0x00 0. " EN ,Enable instruction TCM" "Disabled,Enabled"
rgroup.long c15:0x29++0x00
line.long 0x00 "TCMSEL,TCM Selection Register"
textline " "
group.long c15:0x10f++0x00
line.long 0x00 "NAXIPIRR,Normal AXI Peripheral Interface Region Register"
hexmask.long 0x00 12.--31. 0x1000 " BA ,Base address of the interface"
bitfld.long 0x00 2.--6. " SIZE ,Size of the interface configured during integration" "None,Reserved,Reserved,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16M,32M,64M,128M,256M,512M,1G,2G,4G,?..."
bitfld.long 0x00 0. " EN ,Interface enable" "Disabled,Enabled"
group.long c15:0x20f++0x00
line.long 0x00 "VAXIPIRR,Virtual AXI Peripheral Interface Region Register"
hexmask.long 0x00 12.--31. 0x1000 " BA ,Base address of the interface"
bitfld.long 0x00 2.--6. " SIZE ,Size of the interface configured during integration" "None,Reserved,Reserved,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16M,32M,64M,128M,256M,512M,1G,2G,4G,?..."
bitfld.long 0x00 0. " EN ,Interface enable" "Disabled,Enabled"
group.long c15:0x30f++0x00
line.long 0x00 "AHBPIRR,AHB Peripheral Interface Region Register"
hexmask.long 0x00 12.--31. 0x1000 " BA ,Base address of the interface"
bitfld.long 0x00 2.--6. " SIZE ,Size of the interface configured during integration" "None,Reserved,Reserved,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16M,32M,64M,128M,256M,512M,1G,2G,4G,?..."
bitfld.long 0x00 0. " EN ,Interface enable" "Disabled,Enabled"
tree.end
width 0xC
tree "Cache Control and Configuration"
rgroup.long c15:0x1100++0x00
line.long 0x00 "CLIDR,Cache Level ID Register"
bitfld.long 0x00 27.--29. " LOU ,Level of Unification" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 24.--26. " LOC ,Level of Coherency" "Level 1,Level 2,Level 3,Level 4,Level 5,Level 6,Level 7,Level 8"
textline " "
bitfld.long 0x00 21.--23. " CL8 ,Cache Level (CL) 8" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 18.--20. " CL7 ,Cache Level (CL) 7" "0,1,2,3,4,5,6,7"
textline " "
bitfld.long 0x00 15.--17. " CL6 ,Cache Level (CL) 6" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. " CL5 ,Cache Level (CL) 5" "0,1,2,3,4,5,6,7"
textline " "
bitfld.long 0x00 9.--11. " CL4 ,Cache Level (CL) 4" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--8. " CL3 ,Cache Level (CL) 3" "0,1,2,3,4,5,6,7"
textline " "
bitfld.long 0x00 3.--5. " CL2 ,Cache Level (CL) 2" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0.--2. " CL1 ,Cache Level (CL) 1" "0,1,2,3,4,5,6,7"
rgroup.long c15:0x1700++0x00
line.long 0x00 "AIDR,Auxiliary ID Register"
rgroup.long c15:0x1000++0x00
line.long 0x00 "CCSIDR,Cache Size ID Register"
bitfld.long 0x00 31. " WT ,Write-Through" "Not supported,Supported"
bitfld.long 0x00 30. " WB ,Write-Back" "Not supported,Supported"
textline " "
bitfld.long 0x00 29. " RA ,Read-Allocate" "Not supported,Supported"
bitfld.long 0x00 28. " WA ,Write-Allocate" "Not supported,Supported"
textline " "
hexmask.long.word 0x00 13.--27. 1. " NUMSETS ,Number of sets"
hexmask.long.word 0x00 3.--12. 1. " ASSOCIATIVITY ,Associativity"
textline " "
bitfld.long 0x00 0.--2. " LINESIZE ,Number of words in each cache line" "0,1,2,3,4,5,6,7"
group.long c15:0x2000++0x00
line.long 0x0 "CSSELR,Cache Size Selection Register"
bitfld.long 0x00 1.--3. " LEVEL ,Cache level to select" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0. " IND ,Instruction or data or unified cache to use" "Data/unified,Instruction"
group.long c15:0x03f++0x00
line.long 0x00 "CFLR,Correctable Fault Location Register"
bitfld.long 0x00 26.--29. " WAY ,Way of the error" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 24.--25. " SIDE ,Source of the error" "0,1,2,3"
textline " "
hexmask.long.word 0x00 5.--13. 1. " INDEX ,index of the location where the error occurred"
bitfld.long 0x00 0.--1. " TYPE ,Type of access that caused the error" "Instruction cache,Data cache,Reserved,ACP"
group.long c15:0x5f++0x00
line.long 0x00 "IADCR,Invalidate All Data Cache Register"
bitfld.long 0x00 30.--31. " WAY ,Cache way to invalidate or clean" "0,1,2,3"
hexmask.long.byte 0x00 5.--10. 1. " SET ,Cache set to invalidate or clean"
group.long c15:0xef++0x00
line.long 0x00 "CSOR,Cache Size Override Register"
bitfld.long 0x00 4.--7. " Dcache ,Validation data cache size" "4kB,8kB,Reserved,16kB,Reserved,Reserved,Reserved,32kB,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,64kB"
bitfld.long 0x00 0.--3. " Icache ,Validation instruction cache size" "4kB,8kB,Reserved,16kB,Reserved,Reserved,Reserved,32kB,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,64kB"
tree.end
width 12.
tree "System Performance Monitor"
group.long c15:0xc9++0x00
line.long 0x00 "PMCR,Performance Monitor Control Register"
hexmask.long.byte 0x00 24.--31. 1. " IMP ,Implementer code"
hexmask.long.byte 0x00 16.--23. 1. " IDCODE ,Identification code"
bitfld.long 0x00 11.--15. " N ,Number of counters implemented" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 5. " DP ,Disable PMCCNTR when prohibited" "No,Yes"
textline " "
bitfld.long 0x00 4. " X ,Export enable" "Disabled,Enabled"
bitfld.long 0x00 3. " D ,Clock divider" "Every cycle,64th cycle"
bitfld.long 0x00 2. " C ,Clock counter reset" "No action,Reset"
bitfld.long 0x00 1. " P ,Event counter reset" "No action,Reset"
textline " "
bitfld.long 0x00 0. " E ,Enable" "Disabled,Enabled"
group.long c15:0x1c9++0x00
line.long 0x00 "PMCNTENSET,Count Enable Set Register"
eventfld.long 0x00 31. " C ,CCNT Enabled / Enable / Disable CCNT" "Disabled,Enabled"
eventfld.long 0x00 2. " P2 ,PMN2 Enabled / Enable / Disable counter" "Disabled,Enabled"
eventfld.long 0x00 1. " P1 ,PMN1 Enabled / Enable / Disable counter" "Disabled,Enabled"
eventfld.long 0x00 0. " P0 ,PMN0 Enabled / Enable / Disable counter" "Disabled,Enabled"
group.long c15:0x2c9++0x00
line.long 0x0 "PMCNTENCLR,Count Enable Clear Register"
eventfld.long 0x00 31. " C ,CCNT Enabled / Enable / Disable CCNT" "Disabled,Enabled"
eventfld.long 0x00 2. " P2 ,PMN2 Enabled / Enable / Disable counter" "Disabled,Enabled"
eventfld.long 0x00 1. " P1 ,PMN1 Enabled / Enable / Disable counter" "Disabled,Enabled"
eventfld.long 0x00 0. " P0 ,PMN0 Enabled / Enable / Disable counter" "Disabled,Enabled"
group.long c15:0x3c9++0x00
line.long 0x0 "PMOVSR,Overflow Flag Status Register"
eventfld.long 0x00 31. " C ,CCNT overflowed" "No overflow,Overflow"
eventfld.long 0x00 2. " P2 ,PMN2 overflowed" "No overflow,Overflow"
eventfld.long 0x00 1. " P1 ,PMN1 overflowed" "No overflow,Overflow"
eventfld.long 0x00 0. " P0 ,PMN0 overflowed" "No overflow,Overflow"
group.long c15:0x4c9++0x00
line.long 0x0 "PMSWINC,Software Increment Register"
eventfld.long 0x00 2. " P2 ,Increment PMN2" "No action,Increment"
eventfld.long 0x00 1. " P1 ,Increment PMN1" "No action,Increment"
eventfld.long 0x00 0. " P0 ,Increment PMN0" "No action,Increment"
group.long c15:0x01d9++0x00
line.long 0x00 "PMXEVTYPER,Event Type Selection Register"
hexmask.long.byte 0x00 0.--7. 1. " SEL ,Event number selected"
group.long c15:0x02d9++0x00
line.long 0x00 "PMXEVCNTR,Event Count Register"
group.long c15:0x5c9++0x00
line.long 0x00 "PMSELR,Performance Counter Selection Register"
bitfld.long 0x00 0.--4. " SEL ,Counter select" "0,1,2,?..."
group.long c15:0xd9++0x00
line.long 0x00 "PMCCNTR,Cycle Count Register"
group.long c15:0x01d9++0x00
saveout c15:0x5C9 %l 0x0
line.long 0x00 "ESR0,Event Selection Register 0"
hexmask.long.byte 0x00 0.--7. 1. " SEL ,Event Selection"
group.long c15:0x02d9++0x00
saveout c15:0x5C9 %l 0x0
line.long 0x00 "PMCR0,Performance Monitor Count Register 0"
hexmask.long 0x00 0.--31. 1. " PMC ,Performance Monitor Count"
group.long c15:0x01d9++0x00
saveout c15:0x5C9 %l 0x1
line.long 0x00 "ESR1,Event Selection Register 1"
hexmask.long.byte 0x00 0.--7. 1. " SEL ,Event Selection"
group.long c15:0x02d9++0x00
saveout c15:0x5C9 %l 0x1
line.long 0x00 "PMCR1,Performance Monitor Count Register 1"
hexmask.long 0x00 0.--31. 1. " PMC ,Performance Monitor Count"
group.long c15:0x01d9++0x00
saveout c15:0x5C9 %l 0x2
line.long 0x00 "ESR2,Event Selection Register 2"
hexmask.long.byte 0x00 0.--7. 1. " SEL ,Event Selection"
group.long c15:0x02d9++0x00
saveout c15:0x5C9 %l 0x2
line.long 0x00 "PMCR2,Performance Monitor Count Register 2"
hexmask.long 0x00 0.--31. 1. " PMC ,Performance Monitor Count"
group.long c15:0xe9++0x00
line.long 0x00 "PMUSERENR,User Enable Register"
bitfld.long 0x00 0. " EN ,User mode access to performance monitor and validation registers" "Not allowed,Allowed"
group.long c15:0x1e9++0x00
line.long 0x00 "PMINTENSET,Interrupt Enable Set Register"
eventfld.long 0x00 31. " C ,Interrupt on CCNT Overflow Enabled / Enable / Disable Interrupt" "Disabled,Enabled"
eventfld.long 0x00 2. " P2 ,Interrupt on PMN2 Overflow Enabled / Enable / Disable Interrupt" "Disabled,Enabled"
eventfld.long 0x00 1. " P1 ,Interrupt on PMN1 Overflow Enabled / Enable / Disable Interrupt" "Disabled,Enabled"
eventfld.long 0x00 0. " P0 ,Interrupt on PMN0 Overflow Enabled / Enable / Disable Interrupt" "Disabled,Enabled"
group.long c15:0x2e9++0x00
line.long 0x00 "PMINTENCLR,Interrupt Enable Clear Register"
eventfld.long 0x00 31. " C ,Interrupt on CCNT Overflow Enabled / Enable / Disable Interrupt" "Disabled,Enabled"
eventfld.long 0x00 2. " P2 ,Interrupt on PMN2 Overflow Enabled / Enable / Disable Interrupt" "Disabled,Enabled"
eventfld.long 0x00 1. " P1 ,Interrupt on PMN1 Overflow Enabled / Enable / Disable Interrupt" "Disabled,Enabled"
eventfld.long 0x00 0. " P0 ,Interrupt on PMN0 Overflow Enabled / Enable / Disable Interrupt" "Disabled,Enabled"
tree "Validation Registers"
group.long c15:0x01f++0x00
line.long 0x00 "IRQESR,nVAL IRQ Enable Set Register"
bitfld.long 0x00 31. " C ,CCNT overflow IRQ request" "Not requested,Requested"
bitfld.long 0x00 2. " P2 ,PMXEVCNTR2 overflow IRQ request" "Not requested,Requested"
bitfld.long 0x00 1. " P1 ,PMXEVCNTR1 overflow IRQ request" "Not requested,Requested"
bitfld.long 0x00 0. " P0 ,PMXEVCNTR0 overflow IRQ request" "Not requested,Requested"
group.long c15:0x11f++0x00
line.long 0x00 "FIQESR,nVAL FIQ Enable Set Register"
bitfld.long 0x00 31. " C ,CCNT overflow FIQ request" "Not requested,Requested"
bitfld.long 0x00 2. " P2 ,PMXEVCNTR2 overflow FIQ request" "Not requested,Requested"
bitfld.long 0x00 1. " P1 ,PMXEVCNTR1 overflow FIQ request" "Not requested,Requested"
bitfld.long 0x00 0. " P0 ,PMXEVCNTR0 overflow FIQ request" "Not requested,Requested"
group.long c15:0x21f++0x00
line.long 0x00 "RESR,nVAL Reset Enable Set Register"
bitfld.long 0x00 31. " C ,CCNT overflow reset request" "Not requested,Requested"
bitfld.long 0x00 2. " P2 ,PMXEVCNTR2 overflow reset request" "Not requested,Requested"
bitfld.long 0x00 1. " P1 ,PMXEVCNTR1 overflow reset request" "Not requested,Requested"
bitfld.long 0x00 0. " P0 ,PMXEVCNTR0 overflow reset request" "Not requested,Requested"
group.long c15:0x31f++0x00
line.long 0x00 "RESR,VAL Debug Request Enable Set Register"
bitfld.long 0x00 31. " C ,CCNT overflow debug request" "Not requested,Requested"
bitfld.long 0x00 2. " P2 ,PMXEVCNTR2 overflow debug request" "Not requested,Requested"
bitfld.long 0x00 1. " P1 ,PMXEVCNTR1 overflow debug request" "Not requested,Requested"
bitfld.long 0x00 0. " P0 ,PMXEVCNTR0 overflow debug request" "Not requested,Requested"
group.long c15:0x41f++0x00
line.long 0x00 "IRQECR,VAL IRQ Enable Clear Register"
eventfld.long 0x00 31. " C ,CCNT overflow IRQ request" "Not requested,Requested"
eventfld.long 0x00 2. " P2 ,PMXEVCNTR2 overflow IRQ request" "Not requested,Requested"
eventfld.long 0x00 1. " P1 ,PMXEVCNTR1 overflow IRQ request" "Not requested,Requested"
eventfld.long 0x00 0. " P0 ,PMXEVCNTR0 overflow IRQ request" "Not requested,Requested"
group.long c15:0x51f++0x00
line.long 0x00 "FIQECR,VAL FIQ Enable Clear Register"
eventfld.long 0x00 31. " C ,CCNT overflow FIQ request" "Not requested,Requested"
eventfld.long 0x00 2. " P2 ,PMXEVCNTR2 overflow FIQ request" "Not requested,Requested"
eventfld.long 0x00 1. " P1 ,PMXEVCNTR1 overflow FIQ request" "Not requested,Requested"
eventfld.long 0x00 0. " P0 ,PMXEVCNTR0 overflow FIQ request" "Not requested,Requested"
group.long c15:0x61f++0x00
line.long 0x00 "RECR,nVAL Reset Enable Clear Register"
eventfld.long 0x00 31. " C ,CCNT overflow reset request" "Not requested,Requested"
eventfld.long 0x00 2. " P2 ,PMXEVCNTR2 overflow reset request" "Not requested,Requested"
eventfld.long 0x00 1. " P1 ,PMXEVCNTR1 overflow reset request" "Not requested,Requested"
eventfld.long 0x00 0. " P0 ,PMXEVCNTR0 overflow reset request" "Not requested,Requested"
group.long c15:0x71f++0x00
line.long 0x00 "DRECR,VAL Debug Request Enable Clear Register"
eventfld.long 0x00 31. " C ,CCNT overflow debug request" "Not requested,Requested"
eventfld.long 0x00 2. " P2 ,PMXEVCNTR2 overflow debug request" "Not requested,Requested"
eventfld.long 0x00 1. " P1 ,PMXEVCNTR1 overflow debug request" "Not requested,Requested"
eventfld.long 0x00 0. " P0 ,PMXEVCNTR0 overflow debug request" "Not requested,Requested"
tree.end
tree.end
width 11.
width 18.
tree "Debug Registers"
tree "Processor Identifier Registers"
rgroup.long c14:832.++0x00
line.long 0x00 "MIDR,Main ID Register"
hexmask.long.byte 0x0 24.--31. 0x1 " IMPL ,Implementer code"
hexmask.long.byte 0x0 20.--23. 0x1 " SPECREV ,Variant number"
textline " "
hexmask.long.byte 0x0 16.--19. 0x1 " ARCH ,Architecture"
hexmask.long.word 0x0 4.--15. 0x1 " PARTNUM ,Part Number"
textline " "
hexmask.long.byte 0x0 0.--3. 0x1 " REV ,Layout Revision"
rgroup.long c14:833.++0x00
line.long 0x00 "CACHETYPE,Cache Type Register"
bitfld.long 0x00 16.--19. " DMINLINE ,Words of Smallest Line Length in L1 or L2 Data Cache Number" "Reserved,Reserved,Reserved,Reserved,16x32-bit words,?..."
bitfld.long 0x00 14.--15. " L1_IPOLICY ,VIPT Instruction Cache Support" "Reserved,Reserved,Supported,?..."
textline " "
bitfld.long 0x00 0.--3. " IMINLINE ,Words of Smallest Line Length in L1 or L2 Instruction Cache Number" "Reserved,Reserved,Reserved,Reserved,16x32-bit words,?..."
rgroup.long c14:834.++0x00
line.long 0x00 "TCMTR,TCM Type Register"
group.long c14:835.++0x00
line.long 0x00 "AMIDR,Alias of MIDR"
rgroup.long c14:836.++0x00
line.long 0x00 "MPUTR,MPU Type Register"
rgroup.long c14:837.++0x00
line.long 0x00 "MPIDR,Multiprocessor Affinity Register"
group.long c14:838.++0x00
line.long 0x00 "AMIDR0,Alias of MIDR"
group.long c14:839.++0x00
line.long 0x00 "AMIDR1,Alias of MIDR"
rgroup.long c14:840.++0x00
line.long 0x00 "ID_PFR0,Processor Feature Register 0"
bitfld.long 0x00 12.--15. " STATE3 ,Thumb-2 Execution Environment (Thumb-2EE) Support" "Reserved,Supported,?..."
bitfld.long 0x00 8.--11. " STATE2 ,Java Extension Interface Support" "Not supported,?..."
textline " "
bitfld.long 0x00 4.--7. " STATE1 ,Thumb Encoding Supported by the Processor Type" "Reserved,Reserved,Reserved,Supported,?..."
bitfld.long 0x00 0.--3. " STATE0 ,ARM Instruction Set Support" "Reserved,Supported,?..."
rgroup.long c14:841.++0x00
line.long 0x00 "ID_PFR1,Processor Feature Register 1"
bitfld.long 0x00 8.--11. " MPM ,Microcontroller Programmer's Model Support" "Supported,?..."
bitfld.long 0x00 4.--7. " SE ,Security Extensions Architecture v1 Support" "Reserved,Supported,?..."
textline " "
bitfld.long 0x00 0.--3. " PM ,Standard ARMv4 Programmer's Model Support" "Reserved,Supported,?..."
rgroup.long c14:842.++0x00
line.long 0x00 "ID_DFR0,Debug Feature Register 0"
bitfld.long 0x00 20.--23. " MDM_MM ,Microcontroller Debug Model Support" "Not supported,?..."
bitfld.long 0x00 16.--19. " TDM_MM ,Trace Debug Model (Memory-Mapped) Support" "Reserved,Supported,?..."
textline " "
bitfld.long 0x00 12.--15. " TDM_CB ,Coprocessor-Based Trace Debug Model Support" "Not supported,?..."
bitfld.long 0x00 8.--11. " CDM_MM ,Memory-Mapped Debug Model Support" "Reserved,Reserved,Reserved,Reserved,Supported,?..."
textline " "
bitfld.long 0x00 4.--7. " SDM_CB ,Secure Debug Model (Coprocessor) Support" "Not supported,?..."
bitfld.long 0x00 0.--3. " CDM_CB ,Coprocessor Debug Model Support" "Not supported,?..."
rgroup.long c14:843.++0x00
line.long 0x00 "ID_AFR0,Auxiliary Feature Register 0"
rgroup.long c14:844.++0x00
line.long 0x00 "ID_MMFR0,Processor Feature Register 0"
bitfld.long 0x00 28.--31. " IT ,Instruction Type Support" "Reserved,Reserved,Reserved,Supported,?..."
bitfld.long 0x00 24.--27. " FCSE ,Fast Context Switch Memory Mappings Support" "Reserved,Supported,?..."
textline " "
bitfld.long 0x00 20.--23. " ACR ,Auxiliary Control Register Support" "Reserved,Supported,?..."
bitfld.long 0x00 16.--19. " TCM ,TCM and Associated DMA Support" "Not supported,?..."
textline " "
bitfld.long 0x00 12.--15. " CC_PLEA ,Cache Coherency With PLE Agent/Shared Memory Support" "Not supported,?..."
bitfld.long 0x00 8.--11. " CC_CPUA ,Cache Coherency Support With CPU Agent/Shared Memory Support" "Not supported,?..."
textline " "
bitfld.long 0x00 4.--7. " PMSA ,Physical Memory System Architecture (PMSA) Support" "Not supported,?..."
bitfld.long 0x00 0.--3. " VMSA ,Virtual Memory System Architecture (VMSA) Support" "Reserved,Reserved,Reserved,Supported,?..."
rgroup.long c14:845.++0x00
line.long 0x00 "ID_MMFR1,Processor Feature Register 1"
bitfld.long 0x00 28.--31. " BTB ,Branch Target Buffer Support" "Reserved,Reserved,Not required,?..."
bitfld.long 0x00 24.--27. " L1TCO ,Test and Clean Operations on Data Cache/Harvard/Unified Architecture Support" "Not supported,?..."
textline " "
bitfld.long 0x00 20.--23. " L1UCMO ,L1 Cache/All Maintenance Operations/Unified Architecture Support" "Not supported,?..."
bitfld.long 0x00 16.--19. " L1HCMO ,L1 Cache/All Maintenance Operations/Harvard Architecture Support" "Supported,?..."
textline " "
bitfld.long 0x00 12.--15. " L1UCLMOSW ,L1 Cache Line Maintenance Operations by Set and Way/Unified Architecture Support" "Not supported,?..."
bitfld.long 0x00 8.--11. " L1HCLMOSW ,L1 Cache Line Maintenance Operations by Set and Way/Harvard Architecture Support" "Supported,?..."
textline " "
bitfld.long 0x00 4.--7. " L1UCLMOMVA ,L1 Cache Line Maintenance Operations by MVA/Unified Architecture Support" "Not supported,?..."
bitfld.long 0x00 0.--3. " L1HCLMOMVA ,L1 Cache Line Maintenance Operations by MVA/Harvard Architecture" "Supported,?..."
rgroup.long c14:846.++0x00
line.long 0x00 "ID_MMFR2,Processor Feature Register 2"
bitfld.long 0x00 28.--31. " HAF ,Hardware Access Flag Support" "Not supported,?..."
bitfld.long 0x00 24.--27. " WFI ,Wait for Interrupt Stalling Support" "Reserved,Supported,?..."
textline " "
bitfld.long 0x00 20.--23. " MBF ,Memory Barrier Operations Support" "Reserved,Reserved,Supported,?..."
bitfld.long 0x00 16.--19. " UTLBMO ,TLB Maintenance Operations/Unified Architecture Support" "Not supported,?..."
textline " "
bitfld.long 0x00 12.--15. " HTLBMO ,TLB Maintenance Operations/Harvard Architecture Support" "Reserved,Reserved,Supported,?..."
bitfld.long 0x00 8.--11. " HL1CMRO ,Cache Maintenance Range Operations/Harvard Architecture Support" "Not supported,?..."
textline " "
bitfld.long 0x00 4.--7. " HL1BPCRO ,Background Prefetch Cache Range Operations/Harvard Architecture Support" "Not supported,?..."
bitfld.long 0x00 0.--3. " HL1FPCRO ,Foreground Prefetch Cache Range Operations/Harvard Architecture Support" "Not supported,?..."
rgroup.long c14:847.++0x00
line.long 0x00 "ID_MMFR3,Processor Feature Register 3"
bitfld.long 0x00 4.--7. " HCMOSW ,Invalidate Cache by Set and Way/Clean by Set and Way/Invalidate and Clean by Set and Way Support" "Reserved,Supported,?..."
bitfld.long 0x00 0.--3. " HCMOMVA ,Invalidate Cache by MVA/Clean by MVA/Invalidate and Clean by MVA/Invalidate All Support" "Reserved,Supported,?..."
rgroup.long c14:848.++0x00
line.long 0x00 "ID_ISAR0,ISA Feature Register 0"
bitfld.long 0x00 24.--27. " DIVI ,Divide Instructions Support" "Not supported,?..."
bitfld.long 0x00 20.--23. " DEBI ,Debug Instructions Support" "Reserved,Supported,?..."
textline " "
bitfld.long 0x00 16.--19. " CI ,Coprocessor Instructions Support" "Not supported,?..."
bitfld.long 0x00 12.--15. " CBI ,Combined Compare and Branch Instructions Support" "Reserved,Supported,?..."
textline " "
bitfld.long 0x00 8.--11. " BI ,Bitfield Instructions Support" "Reserved,Supported,?..."
bitfld.long 0x00 4.--7. " BCI ,Bit Counting Instructions Support" "Reserved,Supported,?..."
textline " "
bitfld.long 0x00 0.--3. " AI ,Atomic Load and Store Instructions Support" "Reserved,Supported,?..."
rgroup.long c14:849.++0x00
line.long 0x00 "ID_ISAR1,ISA Feature Register 1"
bitfld.long 0x00 28.--31. " JI ,Jazelle Instructions Support" "Reserved,Supported,?..."
bitfld.long 0x00 24.--27. " INTI ,Instructions That Branch Between ARM and Thumb Code Support" "Reserved,Reserved,Supported,?..."
textline " "
bitfld.long 0x00 20.--23. " IMMI ,Immediate Instructions Support" "Reserved,Supported,?..."
bitfld.long 0x00 16.--19. " ITEI ,If Then Instructions Support" "Reserved,Supported,?..."
textline " "
bitfld.long 0x00 12.--15. " EXTI ,Sign or Zero Extend Instructions Support" "Reserved,Reserved,Supported,?..."
bitfld.long 0x00 8.--11. " E2I ,Exception 2 Instructions Support" "Reserved,Supported,?..."
textline " "
bitfld.long 0x00 4.--7. " E1I ,Exception 1 Instructions Support" "Reserved,Supported,?..."
bitfld.long 0x00 0.--3. " ENDI ,Endianness Control Instructions Support" "Reserved,Supported,?..."
rgroup.long c14:850.++0x00
line.long 0x00 "ID_ISAR2,ISA Feature Register 2"
bitfld.long 0x00 28.--31. " RI ,Reversal Instructions Support" "Reserved,Reserved,Supported,?..."
bitfld.long 0x00 24.--27. " PSRI ,PSR Instructions Support" "Reserved,Supported,?..."
textline " "
bitfld.long 0x00 20.--23. " UMI ,Advanced Unsigned Multiply Instructions Support" "Reserved,Reserved,Supported,?..."
bitfld.long 0x00 16.--19. " SMI ,Advanced Signed Multiply Instructions Support" "Reserved,Reserved,Reserved,Supported,?..."
textline " "
bitfld.long 0x00 12.--15. " MI ,Multiply Instructions Support" "Reserved,Reserved,Supported,?..."
bitfld.long 0x00 8.--11. " II ,Multi-Access Interruptible Instructions Support" "Supported,?..."
textline " "
bitfld.long 0x00 4.--7. " MHI ,Memory Hint Instructions Support" "Reserved,Reserved,Reserved,Supported,?..."
bitfld.long 0x00 0.--3. " LSI ,Load and Store Instructions Support" "Reserved,Supported,?..."
rgroup.long c14:851.++0x00
line.long 0x00 "ID_ISAR3,ISA Feature Register 3"
bitfld.long 0x00 28.--31. " T2E ,Thumb-2 Extensions Support" "Reserved,Supported,?..."
bitfld.long 0x00 24.--27. " NOPI ,True NOP Instructions Support" "Reserved,Supported,?..."
textline " "
bitfld.long 0x00 20.--23. " TCI ,Thumb Copy Instructions Support" "Reserved,Supported,?..."
bitfld.long 0x00 16.--19. " TBI ,Table Branch Instructions Support" "Reserved,Reserved,Supported,?..."
textline " "
bitfld.long 0x00 12.--15. " SPI ,Synchronization Primitive Instructions Support" "Reserved,Reserved,Supported,?..."
bitfld.long 0x00 8.--11. " SWII ,SWI Instructions Support" "Reserved,Supported,?..."
textline " "
bitfld.long 0x00 4.--7. " SIMDI ,Single Instruction Multiple Data (SIMD) Instructions Support" "Reserved,Reserved,Reserved,Supported,?..."
bitfld.long 0x00 0.--3. " SI ,Saturate Instructions Support" "Reserved,Supported,?..."
rgroup.long c14:852.++0x00
line.long 0x00 "ID_ISAR4,ISA Feature Register 4"
bitfld.long 0x00 20.--23. " EI ,Exclusive Instructions Support" "Reserved,Supported,?..."
bitfld.long 0x00 16.--19. " BI ,Barrier Instructions Support" "Reserved,Supported,?..."
textline " "
bitfld.long 0x00 12.--15. " SMII ,SMI Instructions Support" "Reserved,Supported,?..."
bitfld.long 0x00 8.--11. " WBI ,Write-Back Instructions Support" "Reserved,Supported,?..."
textline " "
bitfld.long 0x00 4.--7. " WSI ,With-Shift Instructions Support" "Reserved,Reserved,Reserved,Reserved,Supported,?..."
bitfld.long 0x00 0.--3. " UI ,Unprivileged Instructions Support" "Reserved,Reserved,Supported,?..."
rgroup.long c14:853.++0x00
line.long 0x00 "ID_ISAR5,ISA Feature Register 5"
tree.end
width 15.
tree "Coresight Management Registers"
group.long c14:960.++0x00
line.long 0x00 "DBGITCTRL,Integration Mode Control Register"
bitfld.long 0x00 0. " INTMODE ,Processor integration mode" "Normal,Integration"
group.long c14:1000.++0x00
line.long 0x00 "DBGCLAIMSET,Claim Tag Set Register"
hexmask.long.byte 0x00 0.--7. 1. " CTS ,Claim tag set"
group.long c14:1001.++0x00
line.long 0x00 "DBGCLAIMCLR,Claim Tag Clear Register"
hexmask.long.byte 0x00 0.--7. 1. " CTC ,Claim tag clear"
wgroup.long c14:1004.++0x00
line.long 0x00 "DBGLAR,Lock Access Register"
rgroup.long c14:1005.++0x00
line.long 0x00 "DBGLSR,Lock Status Register"
bitfld.long 0x00 2. " 32BA ,Indicate that a 32-bit access is required to write the key to the DBGLAR" "No,Yes"
textline " "
bitfld.long 0x00 1. " LB ,Lock bit" "Not locked,Locked"
bitfld.long 0x00 0. " LIB ,Lock implemented bit" "Not locked,Locked"
rgroup.long c14:1006.++0x00
line.long 0x00 "DBGAUTHSTATUS,Authentication Status Register"
bitfld.long 0x00 7. " SNDFI ,Secure non-invasive debug features implemented" "Not implemented,Implemented"
bitfld.long 0x00 6. " SNDFE ,Secure non-invasive debug features enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 5. " SIDFI ,Secure invasive debug features implemented" "Not implemented,Implemented"
bitfld.long 0x00 4. " SIDFE ,Secure invasive debug features enabled" "Disabled,Enabled"
rgroup.long c14:1011.++0x00
line.long 0x00 "DBGDEVTYPE,Device Type Register"
hexmask.long.byte 0x00 4.--7. 1. " SUBTYPE ,Subtype"
hexmask.long.byte 0x00 0.--3. 1. " MAIN_CLASS ,Main class"
tree.end
textline " "
width 12.
rgroup.long c14:0.++0x0
line.long 0x0 "DBGDIDR,Debug ID Register"
bitfld.long 0x0 28.--31. " WRP ,Number of Watchpoint Register Pairs" "1,2,3,4,5,6,7,8,?..."
bitfld.long 0x0 24.--27. " BRP ,Number of Breakpoint Register Pairs" "1,2,3,4,5,6,7,8,?..."
textline " "
bitfld.long 0x0 20.--23. " CTX_CMP ,Number of BRPs with Context ID Comparison Capability" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16"
hexmask.long.byte 0x0 16.--19. 1. " VERSION ,Debug Architecture Version"
textline " "
bitfld.long 0x0 15. " DEVID ,Debug Device ID" "Low,High"
bitfld.long 0x0 14. " NSUHD ,Secure User halting debug-mode" "Low,High"
textline " "
bitfld.long 0x0 13. " PCSR ,PC Sample register implemented" "Low,High"
bitfld.long 0x0 12. " SE ,Security Extensions implemented" "Low,High"
textline " "
hexmask.long.byte 0x0 4.--7. 1. " VARIANT ,Implementation-defined Variant Number"
hexmask.long.byte 0x0 0.--3. 1. " REVISION ,Implementation-defined Revision Number"
group.long c14:34.++0x0
line.long 0x00 "DBGDSCREXT,Debug Status and Control Register"
bitfld.long 0x00 30. " RXFULL ,DBGDTRRX Register full" "Empty,Full"
bitfld.long 0x00 29. " TXFULL ,DBGDTRTX Register full" "Empty,Full"
textline " "
bitfld.long 0x00 25. " PIPEADV ,PIPEADV Processor Idle flag" "Not idle,Idle"
bitfld.long 0x00 24. " INSTRCOMPL_L ,Latched instruction complete" "Not completed,Completed"
textline " "
bitfld.long 0x00 20.--21. " EXTDCCMODE ,External DCC access mode field" "Non-blocking,Stall,Fast,?..."
bitfld.long 0x00 19. " ADADISCARD ,Asynchronous Data Aborts Discarded bit" "Normal,Abort"
bitfld.long 0x00 18. " NS ,Non-secure status bit" "Secure,Non-secure"
textline " "
bitfld.long 0x00 17. " SPNIDDIS ,Secure Privileged Non-Invasive Debug Disable" "No,Yes"
bitfld.long 0x00 16. " SPIDDIS ,Secure Privileged Invasive Debug Disable" "No,Yes"
bitfld.long 0x00 15. " MDBGEN ,Monitor debug-mode enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 14. " HDBGEN ,Halting debug-mode" "Disabled,Enabled"
bitfld.long 0x00 13. " ITREN ,Execute ARM instruction enable" "Disabled,Enabled"
bitfld.long 0x00 12. " UDCCDIS ,User mode access to Communications Channel disable" "No,Yes"
textline " "
bitfld.long 0x00 11. " INTDIS ,Interrupt disable" "No,Yes"
bitfld.long 0x00 10. " DBGACK ,Force debug acknowledge" "Normal,Forced"
textline " "
bitfld.long 0x00 8. " UND_L ,Sticky undefined bit" "Not occurred,Occurred"
bitfld.long 0x00 7. " ADABORT ,Asynchronous data abort" "Not aborted,Aborted"
bitfld.long 0x00 6. " SDABORT ,Synchronous data abort" "Not aborted,Aborted"
textline " "
bitfld.long 0x00 2.--5. " MOE ,Method of debug entry field" "Halt Request,Breakpoint,Reserved,BKPT Instruction,External Debug Request,Reserved,Reserved,Reserved,Reserved,Reserved,Synchronous Watchpoint,?..."
bitfld.long 0x00 1. " RESTARTED ,Processor restarted" "Pending,Exited"
bitfld.long 0x00 0. " HALTED ,Processor halted" "Non-debug,Debug"
group.long c14:0x7++0x0
line.long 0x00 "DBGVCR,Debug Vector Catch register"
bitfld.long 0x00 7. " FIQVCE_S ,FIQ vector catch in Secure state" "Disabled,Enabled"
textline " "
bitfld.long 0x00 6. " IRQVCE_S ,IRQ vector catch in Secure state" "Disabled,Enabled"
bitfld.long 0x00 4. " DAVCE_S ,Data Abort vector catch in Secure state" "Disabled,Enabled"
textline " "
bitfld.long 0x00 3. " PAVCE_S ,Prefetch Abort vector catch in Secure state" "Disabled,Enabled"
bitfld.long 0x00 2. " SVCVCE_S ,SVC vector catch in Secure state" "Disabled,Enabled"
textline " "
bitfld.long 0x00 1. " UIVCE_S ,Undefined instruction vector catch in Secure state" "Disabled,Enabled"
bitfld.long 0x00 0. " RVCE ,Reset vector catch enable" "Disabled,Enabled"
hgroup.long c14:32.++0x0
hide.long 0x00 "DTRRX,Target -> Host Data Transfer Register"
in
group.long c14:35.++0x00
line.long 0x0 "DTRTX,Host -> Target Data Transfer Register"
hexmask.long 0x00 0.--31. 1. " HTD ,Host -> target data"
group.long c14:10.++0x0
line.long 0x00 "DBGDSCCR,Debug State Cache Control Register"
bitfld.long 0x00 2. " NWT ,Write through disable" "No,Yes"
bitfld.long 0x00 1. " NIL ,L1 instruction cache line-fills disable" "No,Yes"
textline " "
bitfld.long 0x00 0. " NDL ,L1 data cache line-fills disable" "No,Yes"
wgroup.long c14:33.++0x0
line.long 0x00 "DBGITR,Instruction Transfer Register"
wgroup.long c14:36.++0x0
line.long 0x00 "DBGDRCR,Debug Run Control Register"
bitfld.long 0x00 4. " CMR ,Cancel memory requests" "Not cancel,Cancel"
bitfld.long 0x00 3. " CSPA ,Clear Sticky Pipeline Advance bit" "No effect,Clear"
textline " "
bitfld.long 0x00 2. " CSE ,Clear Sticky Exceptions bits" "No effect,Clear"
bitfld.long 0x00 1. " RR ,Restart request" "No effect,Restart"
textline " "
bitfld.long 0x00 0. " HR ,Halt request" "No effect,Halt"
textline " "
rgroup.long c14:193.++0x0
line.long 0x00 "DBGOSLSR,Operating System Lock Status Register"
bitfld.long 0x00 1. " LOCK_IMP_BIT ,Indicate whether the OS lock functionality is implemented" "Not implemented,Implemented"
group.long c14:196.++0x0
line.long 0x00 "DBGPRCR,Device Power-down and Reset Control Register"
bitfld.long 0x00 2. " HCWR ,Hold core warm reset" "Not held,Held"
textline " "
bitfld.long 0x00 1. " CWRR ,Reset reguest" "Not requested,Requested"
bitfld.long 0x00 0. " CORENPDRQ ,Core no powerdown request" "Power-down,Emulate"
rgroup.long c14:197.++0x0
line.long 0x00 "DBGPRSR,Device Power-down and Reset Status Register"
bitfld.long 0x00 3. " SR ,Sticky Reset Status" "Not reset,Reset"
bitfld.long 0x00 2. " R ,Reset Status" "No reset,Reset"
textline " "
bitfld.long 0x00 1. " SPD ,Sticky Power-down Status" "Not reset,Reset"
bitfld.long 0x00 0. " PU ,Power-up Status" "Powered down,Powered up"
tree.end
width 7.
tree "Breakpoint Registers"
group.long c14:64.++0x0
line.long 0x00 "BVR0,Breakpoint Value 0 Register"
hexmask.long 0x00 0.--31. 1. " BV0 ,Breakpoint Value 0"
group.long c14:80.++0x0
line.long 0x00 "BCR0,Breakpoint Control 0 Register"
bitfld.long 0x00 24.--28. " BAM ,Breakpoint Address Mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF"
bitfld.long 0x00 20.--22. " M ,BVR Meaning" "IVA match,Linked IVA match,Unlinked ID,Linked ID,IVA mismatch,Linked IVA mismatch,?..."
bitfld.long 0x00 16.--19. " LBRP ,Linked BRP Number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15"
bitfld.long 0x00 14.--15. " SWAC ,Secure World Access Control" "Both,Nonsecure,Secure,?..."
textline " "
bitfld.long 0x0 8. " BAS ,Byte 3 address select" "0,1"
bitfld.long 0x0 7. ",Byte 2 address select" "0,1"
bitfld.long 0x0 6. ",Byte 1 address select" "0,1"
bitfld.long 0x0 5. ",Byte 0 address select" "0,1"
bitfld.long 0x00 1.--2. " S ,Supervisor Access Control" "User/system/supervisor,Privileged,User,Any"
bitfld.long 0x00 0. " B ,Breakpoint Enable" "Disabled,Enabled"
group.long c14:65.++0x0
line.long 0x00 "BVR1,Breakpoint Value 1 Register"
hexmask.long 0x00 0.--31. 1. " BV1 ,Breakpoint Value 1"
group.long c14:81.++0x0
line.long 0x00 "BCR1,Breakpoint Control 1 Register"
bitfld.long 0x00 24.--28. " BAM ,Breakpoint Address Mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF"
bitfld.long 0x00 20.--22. " M ,BVR Meaning" "IVA match,Linked IVA match,Unlinked ID,Linked ID,IVA mismatch,Linked IVA mismatch,?..."
bitfld.long 0x00 16.--19. " LBRP ,Linked BRP Number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15"
bitfld.long 0x00 14.--15. " SWAC ,Secure World Access Control" "Both,Nonsecure,Secure,?..."
textline " "
bitfld.long 0x0 8. " BAS ,Byte 3 address select" "0,1"
bitfld.long 0x0 7. ",Byte 2 address select" "0,1"
bitfld.long 0x0 6. ",Byte 1 address select" "0,1"
bitfld.long 0x0 5. ",Byte 0 address select" "0,1"
bitfld.long 0x00 1.--2. " S ,Supervisor Access Control" "User/system/supervisor,Privileged,User,Any"
bitfld.long 0x00 0. " B ,Breakpoint Enable" "Disabled,Enabled"
group.long c14:66.++0x0
line.long 0x00 "BVR2,Breakpoint Value 2 Register"
hexmask.long 0x00 0.--31. 1. " BV2 ,Breakpoint Value 2"
group.long c14:82.++0x0
line.long 0x00 "BCR2,Breakpoint Control 2 Register"
bitfld.long 0x00 24.--28. " BAM ,Breakpoint Address Mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF"
bitfld.long 0x00 20.--22. " M ,BVR Meaning" "IVA match,Linked IVA match,Unlinked ID,Linked ID,IVA mismatch,Linked IVA mismatch,?..."
bitfld.long 0x00 16.--19. " LBRP ,Linked BRP Number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15"
bitfld.long 0x00 14.--15. " SWAC ,Secure World Access Control" "Both,Nonsecure,Secure,?..."
textline " "
bitfld.long 0x0 8. " BAS ,Byte 3 address select" "0,1"
bitfld.long 0x0 7. ",Byte 2 address select" "0,1"
bitfld.long 0x0 6. ",Byte 1 address select" "0,1"
bitfld.long 0x0 5. ",Byte 0 address select" "0,1"
bitfld.long 0x00 1.--2. " S ,Supervisor Access Control" "User/system/supervisor,Privileged,User,Any"
bitfld.long 0x00 0. " B ,Breakpoint Enable" "Disabled,Enabled"
group.long c14:67.++0x0
line.long 0x00 "BVR3,Breakpoint Value 3 Register"
hexmask.long 0x00 0.--31. 1. " BV3 ,Breakpoint Value 3"
group.long c14:83.++0x0
line.long 0x00 "BCR3,Breakpoint Control 3 Register"
bitfld.long 0x00 24.--28. " BAM ,Breakpoint Address Mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF"
bitfld.long 0x00 20.--22. " M ,BVR Meaning" "IVA match,Linked IVA match,Unlinked ID,Linked ID,IVA mismatch,Linked IVA mismatch,?..."
bitfld.long 0x00 16.--19. " LBRP ,Linked BRP Number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15"
bitfld.long 0x00 14.--15. " SWAC ,Secure World Access Control" "Both,Nonsecure,Secure,?..."
textline " "
bitfld.long 0x0 8. " BAS ,Byte 3 address select" "0,1"
bitfld.long 0x0 7. ",Byte 2 address select" "0,1"
bitfld.long 0x0 6. ",Byte 1 address select" "0,1"
bitfld.long 0x0 5. ",Byte 0 address select" "0,1"
bitfld.long 0x00 1.--2. " S ,Supervisor Access Control" "User/system/supervisor,Privileged,User,Any"
bitfld.long 0x00 0. " B ,Breakpoint Enable" "Disabled,Enabled"
group.long c14:68.++0x0
line.long 0x00 "BVR4,Breakpoint Value 4 Register"
hexmask.long 0x00 0.--31. 1. " BV4 ,Breakpoint Value 4"
group.long c14:84.++0x0
line.long 0x00 "BCR4,Breakpoint Control 4 Register"
bitfld.long 0x00 24.--28. " BAM ,Breakpoint Address Mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF"
bitfld.long 0x00 20.--22. " M ,BVR Meaning" "IVA match,Linked IVA match,Unlinked ID,Linked ID,IVA mismatch,Linked IVA mismatch,?..."
bitfld.long 0x00 16.--19. " LBRP ,Linked BRP Number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15"
bitfld.long 0x00 14.--15. " SWAC ,Secure World Access Control" "Both,Nonsecure,Secure,?..."
textline " "
bitfld.long 0x0 8. " BAS ,Byte 3 address select" "0,1"
bitfld.long 0x0 7. ",Byte 2 address select" "0,1"
bitfld.long 0x0 6. ",Byte 1 address select" "0,1"
bitfld.long 0x0 5. ",Byte 0 address select" "0,1"
bitfld.long 0x00 1.--2. " S ,Supervisor Access Control" "User/system/supervisor,Privileged,User,Any"
bitfld.long 0x00 0. " B ,Breakpoint Enable" "Disabled,Enabled"
group.long c14:69.++0x0
line.long 0x00 "BVR5,Breakpoint Value 5 Register"
hexmask.long 0x00 0.--31. 1. " BV5 ,Breakpoint Value 5"
group.long c14:85.++0x0
line.long 0x00 "BCR5,Breakpoint Control 5 Register"
bitfld.long 0x00 24.--28. " BAM ,Breakpoint Address Mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF"
bitfld.long 0x00 20.--22. " M ,BVR Meaning" "IVA match,Linked IVA match,Unlinked ID,Linked ID,IVA mismatch,Linked IVA mismatch,?..."
bitfld.long 0x00 16.--19. " LBRP ,Linked BRP Number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15"
bitfld.long 0x00 14.--15. " SWAC ,Secure World Access Control" "Both,Nonsecure,Secure,?..."
textline " "
bitfld.long 0x0 8. " BAS ,Byte 3 address select" "0,1"
bitfld.long 0x0 7. ",Byte 2 address select" "0,1"
bitfld.long 0x0 6. ",Byte 1 address select" "0,1"
bitfld.long 0x0 5. ",Byte 0 address select" "0,1"
bitfld.long 0x00 1.--2. " S ,Supervisor Access Control" "User/system/supervisor,Privileged,User,Any"
bitfld.long 0x00 0. " B ,Breakpoint Enable" "Disabled,Enabled"
group.long c14:70.++0x0
line.long 0x00 "BVR6,Breakpoint Value 6 Register"
hexmask.long 0x00 0.--31. 1. " BV6 ,Breakpoint Value 6"
group.long c14:86.++0x0
line.long 0x00 "BCR6,Breakpoint Control 6 Register"
bitfld.long 0x00 24.--28. " BAM ,Breakpoint Address Mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF"
bitfld.long 0x00 20.--22. " M ,BVR Meaning" "IVA match,Linked IVA match,Unlinked ID,Linked ID,IVA mismatch,Linked IVA mismatch,?..."
bitfld.long 0x00 16.--19. " LBRP ,Linked BRP Number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15"
bitfld.long 0x00 14.--15. " SWAC ,Secure World Access Control" "Both,Nonsecure,Secure,?..."
textline " "
bitfld.long 0x0 8. " BAS ,Byte 3 address select" "0,1"
bitfld.long 0x0 7. ",Byte 2 address select" "0,1"
bitfld.long 0x0 6. ",Byte 1 address select" "0,1"
bitfld.long 0x0 5. ",Byte 0 address select" "0,1"
bitfld.long 0x00 1.--2. " S ,Supervisor Access Control" "User/system/supervisor,Privileged,User,Any"
bitfld.long 0x00 0. " B ,Breakpoint Enable" "Disabled,Enabled"
group.long c14:71.++0x0
line.long 0x00 "BVR7,Breakpoint Value 7 Register"
hexmask.long 0x00 0.--31. 1. " BV7 ,Breakpoint Value 7"
group.long c14:87.++0x0
line.long 0x00 "BCR7,Breakpoint Control 7 Register"
bitfld.long 0x00 24.--28. " BAM ,Breakpoint Address Mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF"
bitfld.long 0x00 20.--22. " M ,BVR Meaning" "IVA match,Linked IVA match,Unlinked ID,Linked ID,IVA mismatch,Linked IVA mismatch,?..."
bitfld.long 0x00 16.--19. " LBRP ,Linked BRP Number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15"
bitfld.long 0x00 14.--15. " SWAC ,Secure World Access Control" "Both,Nonsecure,Secure,?..."
textline " "
bitfld.long 0x0 8. " BAS ,Byte 3 address select" "0,1"
bitfld.long 0x0 7. ",Byte 2 address select" "0,1"
bitfld.long 0x0 6. ",Byte 1 address select" "0,1"
bitfld.long 0x0 5. ",Byte 0 address select" "0,1"
bitfld.long 0x00 1.--2. " S ,Supervisor Access Control" "User/system/supervisor,Privileged,User,Any"
bitfld.long 0x00 0. " B ,Breakpoint Enable" "Disabled,Enabled"
tree.end
tree "Watchpoint Control Registers"
group.long c14:96.++0x0
line.long 0x00 "WVR0,Watchpoint Value 0 Register"
hexmask.long 0x00 2.--31. 0x04 " WA0 ,Watchpoint Address 0"
group.long c14:112.++0x0
line.long 0x00 "WCR0,Watchpoint Control 0 Register"
bitfld.long 0x0 24.--28. " WAM ,Watchpoint address mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF"
bitfld.long 0x0 20. " EL ,Enable Linking" "Disabled,Enabled"
textline " "
bitfld.long 0x0 16.--19. " LBN ,Linked BRP number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15"
bitfld.long 0x0 14.--15. " SWAC ,Secure world access control" "Non-secure & Secure,Non-secure,Secure,?..."
textline " "
bitfld.long 0x0 12. " BAS ,Byte 7 address select" "0,1"
bitfld.long 0x0 11. ",Byte 6 address select" "0,1"
bitfld.long 0x0 10. ",Byte 5 address select" "0,1"
bitfld.long 0x0 9. ",Byte 4 address select" "0,1"
bitfld.long 0x0 8. ",Byte 3 address select" "0,1"
bitfld.long 0x0 7. ",Byte 2 address select" "0,1"
bitfld.long 0x0 6. ",Byte 1 address select" "0,1"
bitfld.long 0x0 5. ",Byte 0 address select" "0,1"
textline " "
bitfld.long 0x0 3.--4. " RD/WR ,Load/Store access control" "Reserved,Load,Store,Any"
bitfld.long 0x0 1.--2. " PAC ,Privileged access control" "Reserved,Privileged,USR,Any"
textline " "
bitfld.long 0x0 0. " WE ,Watchpoint enable" "Disabled,Enabled"
group.long c14:97.++0x0
line.long 0x00 "WVR1,Watchpoint Value 1 Register"
hexmask.long 0x00 2.--31. 0x04 " WA0 ,Watchpoint Address 0"
group.long c14:113.++0x0
line.long 0x00 "WCR1,Watchpoint Control 1 Register"
bitfld.long 0x0 24.--28. " WAM ,Watchpoint address mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF"
bitfld.long 0x0 20. " EL ,Enable Linking" "Disabled,Enabled"
textline " "
bitfld.long 0x0 16.--19. " LBN ,Linked BRP number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15"
bitfld.long 0x0 14.--15. " SWAC ,Secure world access control" "Non-secure & Secure,Non-secure,Secure,?..."
textline " "
bitfld.long 0x0 12. " BAS ,Byte 7 address select" "0,1"
bitfld.long 0x0 11. ",Byte 6 address select" "0,1"
bitfld.long 0x0 10. ",Byte 5 address select" "0,1"
bitfld.long 0x0 9. ",Byte 4 address select" "0,1"
bitfld.long 0x0 8. ",Byte 3 address select" "0,1"
bitfld.long 0x0 7. ",Byte 2 address select" "0,1"
bitfld.long 0x0 6. ",Byte 1 address select" "0,1"
bitfld.long 0x0 5. ",Byte 0 address select" "0,1"
textline " "
bitfld.long 0x0 3.--4. " RD/WR ,Load/Store access control" "Reserved,Load,Store,Any"
bitfld.long 0x0 1.--2. " PAC ,Privileged access control" "Reserved,Privileged,USR,Any"
textline " "
bitfld.long 0x0 0. " WE ,Watchpoint enable" "Disabled,Enabled"
group.long c14:98.++0x0
line.long 0x00 "WVR2,Watchpoint Value 2 Register"
hexmask.long 0x00 2.--31. 0x04 " WA0 ,Watchpoint Address 0"
group.long c14:114.++0x0
line.long 0x00 "WCR2,Watchpoint Control 2 Register"
bitfld.long 0x0 24.--28. " WAM ,Watchpoint address mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF"
bitfld.long 0x0 20. " EL ,Enable Linking" "Disabled,Enabled"
textline " "
bitfld.long 0x0 16.--19. " LBN ,Linked BRP number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15"
bitfld.long 0x0 14.--15. " SWAC ,Secure world access control" "Non-secure & Secure,Non-secure,Secure,?..."
textline " "
bitfld.long 0x0 12. " BAS ,Byte 7 address select" "0,1"
bitfld.long 0x0 11. ",Byte 6 address select" "0,1"
bitfld.long 0x0 10. ",Byte 5 address select" "0,1"
bitfld.long 0x0 9. ",Byte 4 address select" "0,1"
bitfld.long 0x0 8. ",Byte 3 address select" "0,1"
bitfld.long 0x0 7. ",Byte 2 address select" "0,1"
bitfld.long 0x0 6. ",Byte 1 address select" "0,1"
bitfld.long 0x0 5. ",Byte 0 address select" "0,1"
textline " "
bitfld.long 0x0 3.--4. " RD/WR ,Load/Store access control" "Reserved,Load,Store,Any"
bitfld.long 0x0 1.--2. " PAC ,Privileged access control" "Reserved,Privileged,USR,Any"
textline " "
bitfld.long 0x0 0. " WE ,Watchpoint enable" "Disabled,Enabled"
group.long c14:99.++0x0
line.long 0x00 "WVR3,Watchpoint Value 3 Register"
hexmask.long 0x00 2.--31. 0x04 " WA0 ,Watchpoint Address 0"
group.long c14:115.++0x0
line.long 0x00 "WCR3,Watchpoint Control 3 Register"
bitfld.long 0x0 24.--28. " WAM ,Watchpoint address mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF"
bitfld.long 0x0 20. " EL ,Enable Linking" "Disabled,Enabled"
textline " "
bitfld.long 0x0 16.--19. " LBN ,Linked BRP number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15"
bitfld.long 0x0 14.--15. " SWAC ,Secure world access control" "Non-secure & Secure,Non-secure,Secure,?..."
textline " "
bitfld.long 0x0 12. " BAS ,Byte 7 address select" "0,1"
bitfld.long 0x0 11. ",Byte 6 address select" "0,1"
bitfld.long 0x0 10. ",Byte 5 address select" "0,1"
bitfld.long 0x0 9. ",Byte 4 address select" "0,1"
bitfld.long 0x0 8. ",Byte 3 address select" "0,1"
bitfld.long 0x0 7. ",Byte 2 address select" "0,1"
bitfld.long 0x0 6. ",Byte 1 address select" "0,1"
bitfld.long 0x0 5. ",Byte 0 address select" "0,1"
textline " "
bitfld.long 0x0 3.--4. " RD/WR ,Load/Store access control" "Reserved,Load,Store,Any"
bitfld.long 0x0 1.--2. " PAC ,Privileged access control" "Reserved,Privileged,USR,Any"
textline " "
bitfld.long 0x0 0. " WE ,Watchpoint enable" "Disabled,Enabled"
group.long c14:100.++0x0
line.long 0x00 "WVR4,Watchpoint Value 4 Register"
hexmask.long 0x00 2.--31. 0x04 " WA0 ,Watchpoint Address 0"
group.long c14:116.++0x0
line.long 0x00 "WCR4,Watchpoint Control 4 Register"
bitfld.long 0x0 24.--28. " WAM ,Watchpoint address mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF"
bitfld.long 0x0 20. " EL ,Enable Linking" "Disabled,Enabled"
textline " "
bitfld.long 0x0 16.--19. " LBN ,Linked BRP number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15"
bitfld.long 0x0 14.--15. " SWAC ,Secure world access control" "Non-secure & Secure,Non-secure,Secure,?..."
textline " "
bitfld.long 0x0 12. " BAS ,Byte 7 address select" "0,1"
bitfld.long 0x0 11. ",Byte 6 address select" "0,1"
bitfld.long 0x0 10. ",Byte 5 address select" "0,1"
bitfld.long 0x0 9. ",Byte 4 address select" "0,1"
bitfld.long 0x0 8. ",Byte 3 address select" "0,1"
bitfld.long 0x0 7. ",Byte 2 address select" "0,1"
bitfld.long 0x0 6. ",Byte 1 address select" "0,1"
bitfld.long 0x0 5. ",Byte 0 address select" "0,1"
textline " "
bitfld.long 0x0 3.--4. " RD/WR ,Load/Store access control" "Reserved,Load,Store,Any"
bitfld.long 0x0 1.--2. " PAC ,Privileged access control" "Reserved,Privileged,USR,Any"
textline " "
bitfld.long 0x0 0. " WE ,Watchpoint enable" "Disabled,Enabled"
group.long c14:101.++0x0
line.long 0x00 "WVR5,Watchpoint Value 5 Register"
hexmask.long 0x00 2.--31. 0x04 " WA0 ,Watchpoint Address 0"
group.long c14:117.++0x0
line.long 0x00 "WCR5,Watchpoint Control 5 Register"
bitfld.long 0x0 24.--28. " WAM ,Watchpoint address mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF"
bitfld.long 0x0 20. " EL ,Enable Linking" "Disabled,Enabled"
textline " "
bitfld.long 0x0 16.--19. " LBN ,Linked BRP number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15"
bitfld.long 0x0 14.--15. " SWAC ,Secure world access control" "Non-secure & Secure,Non-secure,Secure,?..."
textline " "
bitfld.long 0x0 12. " BAS ,Byte 7 address select" "0,1"
bitfld.long 0x0 11. ",Byte 6 address select" "0,1"
bitfld.long 0x0 10. ",Byte 5 address select" "0,1"
bitfld.long 0x0 9. ",Byte 4 address select" "0,1"
bitfld.long 0x0 8. ",Byte 3 address select" "0,1"
bitfld.long 0x0 7. ",Byte 2 address select" "0,1"
bitfld.long 0x0 6. ",Byte 1 address select" "0,1"
bitfld.long 0x0 5. ",Byte 0 address select" "0,1"
textline " "
bitfld.long 0x0 3.--4. " RD/WR ,Load/Store access control" "Reserved,Load,Store,Any"
bitfld.long 0x0 1.--2. " PAC ,Privileged access control" "Reserved,Privileged,USR,Any"
textline " "
bitfld.long 0x0 0. " WE ,Watchpoint enable" "Disabled,Enabled"
group.long c14:102.++0x0
line.long 0x00 "WVR6,Watchpoint Value 6 Register"
hexmask.long 0x00 2.--31. 0x04 " WA0 ,Watchpoint Address 0"
group.long c14:118.++0x0
line.long 0x00 "WCR6,Watchpoint Control 6 Register"
bitfld.long 0x0 24.--28. " WAM ,Watchpoint address mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF"
bitfld.long 0x0 20. " EL ,Enable Linking" "Disabled,Enabled"
textline " "
bitfld.long 0x0 16.--19. " LBN ,Linked BRP number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15"
bitfld.long 0x0 14.--15. " SWAC ,Secure world access control" "Non-secure & Secure,Non-secure,Secure,?..."
textline " "
bitfld.long 0x0 12. " BAS ,Byte 7 address select" "0,1"
bitfld.long 0x0 11. ",Byte 6 address select" "0,1"
bitfld.long 0x0 10. ",Byte 5 address select" "0,1"
bitfld.long 0x0 9. ",Byte 4 address select" "0,1"
bitfld.long 0x0 8. ",Byte 3 address select" "0,1"
bitfld.long 0x0 7. ",Byte 2 address select" "0,1"
bitfld.long 0x0 6. ",Byte 1 address select" "0,1"
bitfld.long 0x0 5. ",Byte 0 address select" "0,1"
textline " "
bitfld.long 0x0 3.--4. " RD/WR ,Load/Store access control" "Reserved,Load,Store,Any"
bitfld.long 0x0 1.--2. " PAC ,Privileged access control" "Reserved,Privileged,USR,Any"
textline " "
bitfld.long 0x0 0. " WE ,Watchpoint enable" "Disabled,Enabled"
group.long c14:103.++0x0
line.long 0x00 "WVR7,Watchpoint Value 7 Register"
hexmask.long 0x00 2.--31. 0x04 " WA0 ,Watchpoint Address 0"
group.long c14:119.++0x0
line.long 0x00 "WCR7,Watchpoint Control 7 Register"
bitfld.long 0x0 24.--28. " WAM ,Watchpoint address mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF"
bitfld.long 0x0 20. " EL ,Enable Linking" "Disabled,Enabled"
textline " "
bitfld.long 0x0 16.--19. " LBN ,Linked BRP number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15"
bitfld.long 0x0 14.--15. " SWAC ,Secure world access control" "Non-secure & Secure,Non-secure,Secure,?..."
textline " "
bitfld.long 0x0 12. " BAS ,Byte 7 address select" "0,1"
bitfld.long 0x0 11. ",Byte 6 address select" "0,1"
bitfld.long 0x0 10. ",Byte 5 address select" "0,1"
bitfld.long 0x0 9. ",Byte 4 address select" "0,1"
bitfld.long 0x0 8. ",Byte 3 address select" "0,1"
bitfld.long 0x0 7. ",Byte 2 address select" "0,1"
bitfld.long 0x0 6. ",Byte 1 address select" "0,1"
bitfld.long 0x0 5. ",Byte 0 address select" "0,1"
textline " "
bitfld.long 0x0 3.--4. " RD/WR ,Load/Store access control" "Reserved,Load,Store,Any"
bitfld.long 0x0 1.--2. " PAC ,Privileged access control" "Reserved,Privileged,USR,Any"
textline " "
bitfld.long 0x0 0. " WE ,Watchpoint enable" "Disabled,Enabled"
group.long c14:6.++0x0
line.long 0x00 "WFAR ,Watchpoint Fault Address Register"
hexmask.long 0x00 1.--31. 0x2 " WFAR ,Address of the watchpointed instruction"
tree.end
width 11.
AUTOINDENT.POP
tree.end
tree "SYS (System and Peripheral Control Registers)"
tree "SYS1 (Primary System Registers)"
base ad:0xFFFFFF00
width 9.
tree "System Pin Control Registers"
group.long 0x00++0x7
line.long 0x0 "SYSPC1,SYS Pin Control Register 1"
bitfld.long 0x00 0. " ECPCLKFUN ,ECPCLK Function" "GIO,ECPCLK"
line.long 0x04 "SYSPC2,SYS Pin Control Register 2"
bitfld.long 0x04 0. " ECPCLKDIR ,ECPCLK Data Direction" "Input,Output"
rgroup.long 0x08++0x3
line.long 0x0 "SYSPC3,SYS Pin Control Register 3"
bitfld.long 0x00 0. " ECPCLKDIN ,ECPCLK Data In" "Low,High"
if ((((d.l(ad:0xFFFFFF00))&0x01)==0x00)&&(((d.l(ad:0xFFFFFF00+0x04))&0x01)==0x01))
group.long 0x0C++0x3
line.long 0x0 "SYSPC4,SYS Pin Control Register 4"
bitfld.long 0x00 0. " ECPCLKDOUT ,ECPCLK Data Out Write" "Low,High"
elif (((d.l(ad:0xFFFFFF00))&0x01)==0x00)
rgroup.long 0x0C++0x3
line.long 0x0 "SYSPC4,SYS Pin Control Register 4"
bitfld.long 0x00 0. " ECPCLKDOUT ,ECPCLK Data Out Write" "Low,High"
else
hgroup.long 0x0C++0x3
hide.long 0x0 "SYSPC4,SYS Pin Control Register 4"
endif
if ((((d.l(ad:0xFFFFFF00))&0x01)==0x00)&&(((d.l(ad:0xFFFFFF00+0x04))&0x01)==0x01))
group.long 0x10++0x7
line.long 0x0 "SYSPC5,SYS Pin Control Register 5"
bitfld.long 0x00 0. " ECPCLKSET ,ECPCLK Data Out Set" "Low,High"
line.long 0x04 "SYSPC6,SYS Pin Control Register 6"
bitfld.long 0x04 0. " ECPCLKCLR ,ECPCLK Data Out clear" "Low,High"
else
hgroup.long 0x10++0x7
hide.long 0x00 "SYSPC5,SYS Pin Control Register 5"
hide.long 0x04 "SYSPC6,SYS Pin Control Register 6"
endif
if (((d.l(ad:0xFFFFFF00))&0x01)==0x00)
group.long 0x18++0x3
line.long 0x0 "SYSPC7,SYS Pin Control Register 7"
bitfld.long 0x00 0. " ECPCLKODE ,ECPCLK Open Drain Enable" "Push/pull,Open drain"
else
hgroup.long 0x18++0x3
hide.long 0x0 "SYSPC7,SYS Pin Control Register 7"
endif
if ((((d.l(ad:0xFFFFFF00))&0x01)==0x00)&&(((d.l(ad:0xFFFFFF00+0x04))&0x01)==0x00))
group.long 0x1C++0x3
line.long 0x0 "SYSPC8,SYS Pin Control Register 8"
bitfld.long 0x00 0. " ECPCLKPUE ,ECPCLK Pull Enable" "Disabled,Enabled"
else
hgroup.long 0x1C++0x3
hide.long 0x0 "SYSPC8,SYS Pin Control Register 8"
endif
if ((((d.l(ad:0xFFFFFF00))&0x01)==0x00)&&(((d.l(ad:0xFFFFFF00+0x04))&0x01)==0x00)&&(((d.l(ad:0xFFFFFF00+0x1C))&0x01)==0x00))
group.long 0x20++0x3
line.long 0x0 "SYSPC9,SYS Pin Control Register 9"
bitfld.long 0x00 0. " ECPCLKPSEL ,ECPCLK Pull Up/Pull Down Select" "Down,Up"
else
hgroup.long 0x20++0x3
hide.long 0x0 "SYSPC9,SYS Pin Control Register 9"
endif
group.long 0x78++0x03
line.long 0x0 "SYSPC10,SYS Pin Control Register 10"
bitfld.long 0x00 0. " ECPCLK_SLEW ,ECPCLK slew control" "Fast mode,Slow mode"
tree.end
width 7.
tree "System Clock Source/Domain Disable Registers"
group.long 0x30++0x3
line.long 0x0 "CSDIS,Clock Source Disable Register"
setclrfld.long 0x00 7. 0x04 7. 0x08 7. " CLKSR7_OFF_set/clr ,Clock Source 7 (External Clock In 2) Off" "Enabled,Disabled"
setclrfld.long 0x00 6. 0x04 6. 0x08 6. " CLKSR6_OFF_set/clr ,Clock Source 6 (PLL2) Off" "Enabled,Disabled"
setclrfld.long 0x00 5. 0x04 5. 0x08 5. " CLKSR5_OFF_set/clr ,Clock Source 5 (LPO High Frequency Clock) Off" "Enabled,Disabled"
textline " "
setclrfld.long 0x00 4. 0x04 4. 0x08 4. " CLKSR4_OFF_set/clr ,Clock Source 4 (LPO Low Frequency Clock) Off" "Enabled,Disabled"
setclrfld.long 0x00 3. 0x04 3. 0x08 3. " CLKSR3_OFF_set/clr ,Clock Source 3 (External Clock In) Off" "Enabled,Disabled"
setclrfld.long 0x00 1. 0x04 1. 0x08 1. " CLKSR1_OFF_set/clr ,Clock Source 1 (PLL1) Off" "Enabled,Disabled"
textline " "
setclrfld.long 0x00 0. 0x04 0. 0x08 0. " CLKSR0_OFF_set/clr ,Clock Source 0 (Oscillator) Off" "Enabled,Disabled"
group.long 0x3C++0x3
line.long 0x0 "CDDIS,Clock Domain Disable Register"
setclrfld.long 0x00 11. 0x4 11. 0x8 11. " VCLKA4OFF_set/clr ,VCLKA4 Domain Off" "Enabled,Disabled"
setclrfld.long 0x00 8. 0x4 8. 0x8 8. " VCLK3OFF_set/clr ,VCLK3 Domain Off" "Enabled,Disabled"
setclrfld.long 0x00 6. 0x4 6. 0x8 6. " RTICLK1OFF_set/clr ,RTICLK1 Domain Off" "Enabled,Disabled"
textline " "
setclrfld.long 0x00 5. 0x4 5. 0x8 5. " VCLKA2OFF_set/clr ,VCLKA2 Domain Off" "Enabled,Disabled"
setclrfld.long 0x00 4. 0x4 4. 0x8 4. " VCLKA1OFF_set/clr ,VCLKA1 Domain Off" "Enabled,Disabled"
setclrfld.long 0x00 3. 0x4 3. 0x8 3. " VCLK2OFF_set/clr ,VCLK2 Domain Off" "Enabled,Disabled"
textline " "
setclrfld.long 0x00 2. 0x4 2. 0x8 2. " VCLKPOFF_set/clr ,VCLKP Domain Off" "Enabled,Disabled"
setclrfld.long 0x00 1. 0x4 1. 0x8 1. " HCLKOFF_set/clr ,HCLK Domain Off" "Enabled,Disabled"
setclrfld.long 0x00 0. 0x4 0. 0x8 0. " GCLKOFF_set/clr ,GCLK Domain Off" "Enabled,Disabled"
tree.end
width 13.
group.long 0x48++0x3
line.long 0x0 "GHVSRC,GCLK/HCLK/VCLK and VCLK2 Source Register"
bitfld.long 0x00 24.--27. " GHVWAKE ,GCLK/HCLK/VCLK Source on Wakeup" "Source 0,Source 1,Source 2,Source 3,Source 4,Source 5,Source 6,Source 7,?..."
bitfld.long 0x00 16.--19. " HVLPM ,HCLK/VCLK/VCLK2 Source on Wakeup (GCLK Turned Off)" "Source 0,Source 1,Source 2,Source 3,Source 4,Source 5,Source 6,Source 7,?..."
bitfld.long 0x00 0.--3. " GHVSRC ,GCLK/HCLK/VCLK/VCLK2 Current Source" "Source 0,Source 1,Source 2,Source 3,Source 4,Source 5,Source 6,Source 7,?..."
group.long 0x4C++0x3
line.long 0x0 "VCLKASRC,Peripheral Asynchronous Clock Source Register"
bitfld.long 0x00 8.--11. " VCLKA2S ,Peripheral Asynchronous Clock 2 Source" "Source 0,Source 1,Source 2,Source 3,Source 4,Source 5,Source 6,Source 7,VCLK,VCLK,VCLK,VCLK,VCLK,VCLK,VCLK,VCLK"
bitfld.long 0x00 0.--3. " VCLKA1S ,Peripheral Asynchronous Clock 1 Source" "Source 0,Source 1,Source 2,Source 3,Source 4,Source 5,Source 6,Source 7,VCLK,VCLK,VCLK,VCLK,VCLK,VCLK,VCLK,VCLK"
group.long 0x50++0x3
line.long 0x0 "RCLKSRC,RTI Clock Source Register"
bitfld.long 0x00 8.--9. " RTI1DIV ,RTI Clock 1 Divider" "RTICLK1,RTICLK1/2,RTICLK1/4,RTICLK1/8"
bitfld.long 0x00 0.--3. " RTI1SRC ,RTI Clock 1 Source" "Source 0,Source 1,Source 2,Source 3,Source 4,Source 5,Source 6,Source 7,VCLK,VCLK,VCLK,VCLK,VCLK,VCLK,VCLK,VCLK"
rgroup.long 0x54++0x3
line.long 0x0 "CSVSTAT,Clock Source Valid Status Register"
bitfld.long 0x00 7. " CLKSR7V ,Clock Source 7 Valid" "Not valid,Valid"
bitfld.long 0x00 6. " CLKSR6V ,Clock Source 6 Valid" "Not valid,Valid"
bitfld.long 0x00 5. " CLKSR5V ,Clock Source 5 Valid" "Not valid,Valid"
textline " "
bitfld.long 0x00 4. " CLKSR4V ,Clock Source 4 Valid" "Not valid,Valid"
bitfld.long 0x00 3. " CLKSR3V ,Clock Source 3 Valid" "Not valid,Valid"
bitfld.long 0x00 1. " CLKSR1V ,Clock Source 1 Valid" "Not valid,Valid"
textline " "
bitfld.long 0x00 0. " CLKSR0V ,Clock Source 0 Valid" "Not valid,Valid"
group.long 0x58++0x3
line.long 0x0 "MSTGCR,Memory Self-Test Global Control Register"
bitfld.long 0x00 8.--9. " ROM_DIV ,ROM Clock Source Prescaler Divider" "HCLK,HCLK/2,HCLK/4,HCLK/8"
bitfld.long 0x00 0.--3. " MSTGENA ,Memory Self-Test Controller Global Enable Key" "Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Enabled,Disabled,Disabled,Disabled,Disabled,Disabled"
group.long 0x5C++0x3
line.long 0x0 "MINITGCR,Memory Hardware Initialization Global Control Register"
bitfld.long 0x00 0.--3. " MINITGENA ,Memory Hardware Initialization Global Enable Key" "Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Enabled,Disabled,Disabled,Disabled,Disabled,Disabled"
width 13.
if ((d.l(ad:0xFFFFFF00+0x58)&0x0F)==0x0A)&&((d.l(ad:0xFFFFFF00+0x5C)&0x0F)!=0x0A)
group.long 0x60++0x3
line.long 0x0 "MSINENA,MBIST Controller/Memory Initialization Enable Register"
bitfld.long 0x00 20. " MSIENA [20] ,DCAN4 Memory BIST Enable" "Disabled,Enabled"
bitfld.long 0x00 19. " [19] ,MIBSPI4 RAM Memory BIST Enable" "Disabled,Enabled"
bitfld.long 0x00 18. " [18] ,MIBSPI2 RAM Memory BIST Enable" "Disabled,Enabled"
bitfld.long 0x00 16. " [16] ,NHET TU2 RAM Memory BIST Enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 15. " [15] ,NHET2 RAM Memory BIST Enable" "Disabled,Enabled"
bitfld.long 0x00 14. " [14] ,MIBADC2 RAM Memory BIST Enable" "Disabled,Enabled"
bitfld.long 0x00 13. " [13] ,FlexRay TU RAM Memory BIST Enable" "Disabled,Enabled"
bitfld.long 0x00 12. " [12] ,MIBSPI5 RAM Memory BIST Enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 11. " [11] ,MIBSPI3 RAM Memory BIST Enable" "Disabled,Enabled"
bitfld.long 0x00 10. " [10] ,DCAN3 RAM Memory BIST Enable" "Disabled,Enabled"
bitfld.long 0x00 8. " [8] ,MIBADC1 RAM Memory BIST Enable" "Disabled,Enabled"
bitfld.long 0x00 7. " [7] ,MIBSPI1 RAM Memory BIST Enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 6. " [6] ,DCAN2 RAM Memory BIST Enable" "Disabled,Enabled"
bitfld.long 0x00 5. " [5] ,DCAN1 RAM Memory BIST Enable" "Disabled,Enabled"
bitfld.long 0x00 4. " [4] ,NHET TU1 RAM Memory BIST Enable" "Disabled,Enabled"
bitfld.long 0x00 3. " [3] ,NHET1 RAM Memory BIST Enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 2. " [2] ,VIM RAM Memory BIST Enable" "Disabled,Enabled"
bitfld.long 0x00 1. " [1] ,DMA RAM Memory BIST Enable" "Disabled,Enabled"
bitfld.long 0x00 0. " [0] ,L2 SRAM Memory BIST Enable" "Disabled,Enabled"
elif ((d.l(ad:0xFFFFFF00+0x58)&0x0F)!=0x0A)&&((d.l(ad:0xFFFFFF00+0x5C)&0x0F)==0x0A)
group.long 0x60++0x3
line.long 0x0 "MSINENA,MBIST Controller/Memory Initialization Enable Register"
bitfld.long 0x00 20. " MSIENA [20] ,DCAN4 Memory Initialization Enable" "Disabled,Enabled"
bitfld.long 0x00 19. " [19] ,MIBSPI4 RAM Memory Initialization Enable" "Disabled,Enabled"
bitfld.long 0x00 18. " [18] ,MIBSPI2 RAM Memory Initialization Enable" "Disabled,Enabled"
bitfld.long 0x00 16. " [16] ,NHET TU2 RAM Memory Initialization Enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 15. " [15] ,NHET2 RAM Memory Initialization Enable" "Disabled,Enabled"
bitfld.long 0x00 14. " [14] ,MIBADC2 RAM Memory Initialization Enable" "Disabled,Enabled"
bitfld.long 0x00 13. " [13] ,FlexRay TU RAM Memory Initialization Enable" "Disabled,Enabled"
bitfld.long 0x00 12. " [12] ,MIBSPI5 RAM Memory Initialization Enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 11. " [11] ,MIBSPI3 RAM Memory Initialization Enable" "Disabled,Enabled"
bitfld.long 0x00 10. " [10] ,DCAN3 RAM Memory Initialization Enable" "Disabled,Enabled"
bitfld.long 0x00 8. " [8] ,MIBADC1 RAM Memory Initialization Enable" "Disabled,Enabled"
bitfld.long 0x00 7. " [7] ,MIBSPI1 RAM Memory Initialization Enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 6. " [6] ,DCAN2 RAM Memory Initialization Enable" "Disabled,Enabled"
bitfld.long 0x00 5. " [5] ,DCAN1 RAM Memory Initialization Enable" "Disabled,Enabled"
bitfld.long 0x00 4. " [4] ,NHET TU1 RAM Memory Initialization Enable" "Disabled,Enabled"
bitfld.long 0x00 3. " [3] ,NHET1 RAM Memory Initialization Enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 2. " [2] ,VIM RAM Memory Initialization Enable" "Disabled,Enabled"
bitfld.long 0x00 1. " [1] ,DMA RAM Memory Initialization Enable" "Disabled,Enabled"
bitfld.long 0x00 0. " [0] ,L2 SRAM Memory Initialization Enable" "Disabled,Enabled"
endif
group.long 0x68++0x3
line.long 0x0 "MSTCGSTAT,MSTC Global Status Register"
eventfld.long 0x00 8. " MINIDONE ,Memory Hardware Initililization Test Run Complete Status" "Not completed,Completed"
textline " "
eventfld.long 0x00 0. " MSTDONE ,Memory Self-Test Run Complete Status" "Not completed,Completed"
group.long 0x6C++0x3
line.long 0x0 "MINISTAT,Memory Hardware Initialization Status Register"
eventfld.long 0x00 20. " MIDONE [20] ,DCAN4 Memory Hardware Initialization Status" "Not completed,Completed"
eventfld.long 0x00 19. " [19] ,MIBSPI4 RAM Memory Hardware Initialization Status" "Not completed,Completed"
eventfld.long 0x00 18. " [18] ,MIBSPI2 RAM Memory Hardware Initialization Status" "Not completed,Completed"
eventfld.long 0x00 16. " [16] ,NHET TU2 RAM Memory Hardware Initialization Status" "Not completed,Completed"
textline " "
eventfld.long 0x00 15. " [15] ,NHET2 RAM Memory Hardware Initialization Status" "Not completed,Completed"
eventfld.long 0x00 14. " [14] ,MIBADC2 RAM Memory Hardware Initialization Status" "Not completed,Completed"
eventfld.long 0x00 13. " [13] ,FlexRay TU RAM Memory Hardware Initialization Status" "Not completed,Completed"
eventfld.long 0x00 12. " [12] ,MIBSPI5 RAM Memory Hardware Initialization Status" "Not completed,Completed"
textline " "
eventfld.long 0x00 11. " [11] ,MIBSPI3 RAM Memory Hardware Initialization Status" "Not completed,Completed"
eventfld.long 0x00 10. " [10] ,DCAN3 RAM Memory Hardware Initialization Status" "Not completed,Completed"
eventfld.long 0x00 8. " [8] ,MIBADC1 RAM Memory Hardware Initialization Status" "Not completed,Completed"
eventfld.long 0x00 7. " [7] ,MIBSPI1 RAM Memory Hardware Initialization Status" "Not completed,Completed"
textline " "
eventfld.long 0x00 6. " [6] ,DCAN2 RAM Memory Hardware Initialization Status" "Not completed,Completed"
eventfld.long 0x00 5. " [5] ,DCAN1 RAM Memory Hardware Initialization Status" "Not completed,Completed"
eventfld.long 0x00 4. " [4] ,NHET TU1 RAM Memory Hardware Initialization Status" "Not completed,Completed"
eventfld.long 0x00 3. " [3] ,NHET1 RAM Memory Hardware Initialization Status" "Not completed,Completed"
textline " "
eventfld.long 0x00 2. " [2] ,VIM RAM Memory Hardware Initialization Status" "Not completed,Completed"
eventfld.long 0x00 1. " [1] ,DMA RAM Memory Hardware Initialization Status" "Not completed,Completed"
eventfld.long 0x00 0. " [0] ,L2 SRAM Memory Hardware Initialization Status" "Not completed,Completed"
width 13.
if (d.l(ad:0xFFFFFF00+0x70)&0x60000000)!=0x40000000
group.long 0x70++0x3
line.long 0x0 "PLLCTL1,PLL Control Register 1"
bitfld.long 0x00 31. " ROS ,Reset on PLL Cycle Slip" "No reset,Reset"
textline " "
bitfld.long 0x00 29.--30. " BPOS ,Bypass of PLL Slip" "Enabled,Enabled,Disabled,Enabled"
bitfld.long 0x00 24.--28. " PLLDIV ,PLL Output Clock Divider" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32"
textline " "
bitfld.long 0x00 23. " ROF ,Reset on Oscillator Fail" "No reset,Reset"
bitfld.long 0x00 16.--21. " REFCLKDIV ,Reference Clock Divider" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64"
hexmask.long.word 0x00 0.--15. 1. " PLLMUL ,PLL Multiplication Factor"
else
group.long 0x70++0x3
line.long 0x0 "PLLCTL1,PLL Control Register 1"
bitfld.long 0x00 29.--30. " BPOS ,Bypass of PLL Slip" "Enabled,Enabled,Disabled,Enabled"
bitfld.long 0x00 24.--28. " PLLDIV ,PLL Output Clock Divider" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32"
textline " "
bitfld.long 0x00 23. " ROF ,Reset on Oscillator Fail" "No reset,Reset"
bitfld.long 0x00 16.--21. " REFCLKDIV ,Reference Clock Divider" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64"
hexmask.long.word 0x00 0.--15. 1. " PLLMUL ,PLL Multiplication Factor"
endif
group.long 0x74++0x3
line.long 0x0 "PLLCTL2,PLL Control Register 2"
bitfld.long 0x00 31. " FMENA ,Frequency Modulation Enable" "Disabled,Enabled"
hexmask.long.word 0x00 22.--30. 1. " SPREADINGRATE ,Spreadingrate"
hexmask.long.word 0x00 12.--20. 1. " MULMOD ,Multiplier Correction when Frequency Modulation is enabled"
textline " "
bitfld.long 0x00 9.--11. " ODPLL ,Internal PLL Output Divider" "/1,/2,/3,/4,/5,/6,/7,/8"
hexmask.long.word 0x00 0.--8. 1. " SPR_AMOUNT ,Spreading Amount"
width 13.
rgroup.long 0x7C++0x3
line.long 0x0 "DIEIDL,Die Identification Register Lower Word"
hexmask.long.word 0x00 22.--31. 1. " LOT ,Lower 10 bits of the device lot number"
bitfld.long 0x00 16.--21. " WAFER ,Wafer number of the device" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
textline " "
hexmask.long.byte 0x00 8.--15. 1. " Y_WAFER ,Y wafer coordinate of the device"
hexmask.long.byte 0x00 0.--7. 1. " X_WAFER ,X wafer coordinate of the device"
rgroup.long 0x80++0x3
line.long 0x0 "DIEIDH,Die Identification Register Upper Word"
hexmask.long.word 0x00 0.--13. 1. " LOT ,Upper 14 bits of the device lot number"
group.long 0x88++0x3
line.long 0x0 "LPOMONCTL,LPO/Clock Monitor Control Register"
bitfld.long 0x00 24. " BIAS_ENABLE ,Bias Enable" "Disabled,Enabled"
bitfld.long 0x00 16. " OSCFRQCONFIGCNT ,Configures the counter based on OSC frequency" "<= 20MHz,> 20MHz & <= 80MHz"
textline " "
bitfld.long 0x00 8.--12. " HFTRIM ,High frequency oscillator trim value" "29.52%,34.24%,38.85%,43.45%,47.99%,52.55%,57.02%,61.46%,65.92%,70.17%,74.55%,78.92%,83.17%,87.43%,91.75%,95.89%,100.00%,104.09%,108.17%,112.32%,116.41%,120.67%,124.42%,128.38%,132.24%,136.15%,140.15%,143.94%,148.02%,151.80%,155.50%,159.35%"
bitfld.long 0x00 0.--4. " LFTRIM ,Low frequency oscillator trim value" "20.67%,25.76%,30.84%,35.90%,40.93%,45.95%,50.97%,55.91%,60.86%,65.78%,70.75%,75.63%,80.61%,85.39%,90.23%,95.11%,100.00%,104.84%,109.51%,114.31%,119.01%,123.75%,128.62%,133.31%,138.03%,142.75%,147.32%,152.02%,156.63%,161.38%,165.90%,170.42%"
group.long 0x8C++0x3
line.long 0x0 "CLKTEST,Clock Test Register"
bitfld.long 0x00 24.--25. " RANGEDETCTRL ,Range Detection Control" "Hardware,Disabled,Hardware,Enabled"
bitfld.long 0x00 16.--19. " CLK_TEST_EN ,Clock Test Enable" "Disabled,Disabled,Disabled,Disabled,Disabled,Enabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled"
textline " "
bitfld.long 0x00 8.--11. " SEL_GIO_PIN ,Clock Source Valid Signal/Clock Source at Functional GIO Pin Select" "Oscillator,PLL,,,,High frequency clock LPO,Secondary PLL,,Low frequency clock LPO,Oscillator,Oscillator,Oscillator,Oscillator,Oscillator,Oscillator,Oscillator"
textline " "
bitfld.long 0x00 0.--3. " SEL_ECP_PIN ,Clock at ECP Pin Select" "Oscillator,PLL,,EXTCLKIN1,LPO low,LPO high,Secondary PLL,EXCLKIN2,GCLK,RTI Base,,VCLKA1,VCLKA2,VCLKA3_S,VCLKA4,Flash HD Pump Oscillator"
group.long 0x90++0x3
line.long 0x0 "DFTCTRLREG,DFT Control Register"
bitfld.long 0x00 12.--13. " DFTWRITE ,DFT Logic Access Mode" "Stress mode,Slow mode,Fast mode,Screen mode"
bitfld.long 0x00 8.--9. " DFTREAD ,DFT Logic Access" "Stress mode,Slow mode,Fast mode,Screen mode"
textline " "
bitfld.long 0x00 0.--3. " TEST_MODE_KEY ,Test Mode Key" "Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Enabled,Disabled,Disabled,Disabled,Disabled,Disabled"
width 13.
group.long 0x94++0x3
line.long 0x0 "DFTCTRLREG2,DFT Control Register"
bitfld.long 0x00 31. " IMPDF [27] ,DFT Implementation Defined Bit[27]" "Disabled,Enabled"
bitfld.long 0x00 30. " [26] ,DFT Implementation Defined Bit[26]" "Disabled,Enabled"
bitfld.long 0x00 29. " [25] ,DFT Implementation Defined Bit[25]" "Disabled,Enabled"
bitfld.long 0x00 28. " [24] ,DFT Implementation Defined Bit[24]" "Disabled,Enabled"
bitfld.long 0x00 27. " [23] ,DFT Implementation Defined Bit[23]" "Disabled,Enabled"
bitfld.long 0x00 26. " [22] ,DFT Implementation Defined Bit[22]" "Disabled,Enabled"
textline " "
bitfld.long 0x00 25. " [21] ,DFT Implementation Defined Bit[21]" "Disabled,Enabled"
bitfld.long 0x00 24. " [20] ,DFT Implementation Defined Bit[20]" "Disabled,Enabled"
bitfld.long 0x00 23. " [19] ,DFT Implementation Defined Bit[19]" "Disabled,Enabled"
bitfld.long 0x00 22. " [18] ,DFT Implementation Defined Bit[18]" "Disabled,Enabled"
bitfld.long 0x00 21. " [17] ,DFT Implementation Defined Bit[17]" "Disabled,Enabled"
bitfld.long 0x00 20. " [16] ,DFT Implementation Defined Bit[16]" "Disabled,Enabled"
textline " "
bitfld.long 0x00 19. " [15] ,DFT Implementation Defined Bit[15]" "Disabled,Enabled"
bitfld.long 0x00 18. " [14] ,DFT Implementation Defined Bit[14]" "Disabled,Enabled"
bitfld.long 0x00 17. " [13] ,DFT Implementation Defined Bit[13]" "Disabled,Enabled"
bitfld.long 0x00 16. " [12] ,DFT Implementation Defined Bit[12]" "Disabled,Enabled"
bitfld.long 0x00 15. " [11] ,DFT Implementation Defined Bit[11]" "Disabled,Enabled"
bitfld.long 0x00 14. " [10] ,DFT Implementation Defined Bit[10]" "Disabled,Enabled"
textline " "
bitfld.long 0x00 13. " [9] ,DFT Implementation Defined Bit[9]" "Disabled,Enabled"
bitfld.long 0x00 12. " [8] ,DFT Implementation Defined Bit[8]" "Disabled,Enabled"
bitfld.long 0x00 11. " [7] ,DFT Implementation Defined Bit[7]" "Disabled,Enabled"
bitfld.long 0x00 10. " [6] ,DFT Implementation Defined Bit[6]" "Disabled,Enabled"
bitfld.long 0x00 9. " [5] ,DFT Implementation Defined Bit[5]" "Disabled,Enabled"
bitfld.long 0x00 8. " [4] ,DFT Implementation Defined Bit[4]" "Disabled,Enabled"
textline " "
bitfld.long 0x00 7. " [3] ,DFT Implementation Defined Bit[3]" "Disabled,Enabled"
bitfld.long 0x00 6. " [2] ,DFT Implementation Defined Bit[2]" "Disabled,Enabled"
bitfld.long 0x00 5. " [1] ,DFT Implementation Defined Bit[1]" "Disabled,Enabled"
bitfld.long 0x00 4. " [0] ,DFT Implementation Defined Bit[0]" "Disabled,Enabled"
textline " "
bitfld.long 0x00 0.--3. " TEST_MODE_KEY ,Test Mode Key (Internal TI Use Only)" "Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Enabled,Disabled,Disabled,Disabled,Disabled,Disabled"
width 13.
group.long 0xA0++0x3
line.long 0x0 "GPREG1,General Purpose Register 1"
bitfld.long 0x00 20.--25. " PLL1_FBSLIP_FILTER_COUNT ,FBSLIP down counter programmed value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
textline " "
bitfld.long 0x00 16.--19. " PLL1_RFSLIP_FILTER_KEY ,Configures the system response when a FBSLIP is indicated by the PLL macro" ",,,,,Bypassed,,,,,One-stage synchronization,,,,,Two-stage synchronization"
width 13.
tree "System Software Interrupt Request Registers"
group.long 0xB0++0x3
line.long 0x0 "SSIR1,System Software Interrupt Request 1 Register"
hexmask.long.byte 0x00 8.--15. 1. " SSKEY1 ,System Software Interrupt Request Key"
hexmask.long.byte 0x00 0.--7. 1. " SSDATA1 ,System Software Interrupt Data"
group.long 0xB4++0x3
line.long 0x0 "SSIR2,System Software Interrupt Request 2 Register"
hexmask.long.byte 0x00 8.--15. 1. " SSKEY2 ,System Software Interrupt 2 Request Key"
hexmask.long.byte 0x00 0.--7. 1. " SSDATA2 ,System Software Interrupt 2 Data"
group.long 0xB8++0x3
line.long 0x0 "SSIR3,System Software Interrupt Request 3 Register"
hexmask.long.byte 0x00 8.--15. 1. " SSKEY3 ,System Software Interrupt 3 Request Key"
hexmask.long.byte 0x00 0.--7. 1. " SSDATA3 ,System Software Interrupt 3 Data"
group.long 0xBC++0x3
line.long 0x0 "SSIR4,System Software Interrupt Request 4 Register"
hexmask.long.byte 0x00 8.--15. 1. " SSKEY4 ,System Software Interrupt 4 Request Key"
hexmask.long.byte 0x00 0.--7. 1. " SSDATA4 ,System Software Interrupt 4 Data"
tree.end
width 10.
group.long 0xC0++0x3
line.long 0x0 "RAMGCR,RAM Control Register"
bitfld.long 0x00 16.--19. " RAM_DFT_EN ,Functional Mode RAM DFT Port Enable Key" "Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Enabled,Disabled,Disabled,Disabled,Disabled,Disabled"
group.long 0xC4++0x3
line.long 0x0 "BMMCR1,Bus Matrix Module Control Register1"
bitfld.long 0x00 0.--3. " MEMSW ,Memory Swap Bit Key" ",,,,,Swapped,,,,,Default,?..."
group.long 0xCC++0x3
line.long 0x0 "CPURSTCR,CPU Reset Control Register"
bitfld.long 0x00 0. " CPU0_RESET ,Cpu 0 reset" "No reset,Reset"
group.long 0xD0++0x3
line.long 0x0 "CLKCNTL,Clock Control Register"
bitfld.long 0x00 24.--27. " VCLKR2 ,VBUS Clock 2 Ratio" "HCLK,HCLK/2,HCLK/3,HCLK/4,HCLK/5,HCLK/6,HCLK/7,HCLK/8,HCLK/9,HCLK/10,HCLK/11,HCLK/12,HCLK/13,HCLK/14,HCLK/15,HCLK/16"
bitfld.long 0x00 16.--19. " VCLKR ,VBUS Clock Ratio" "HCLK,HCLK/2,HCLK/3,HCLK/4,HCLK/5,HCLK/6,HCLK/7,HCLK/8,HCLK/9,HCLK/10,HCLK/11,HCLK/12,HCLK/13,HCLK/14,HCLK/15,HCLK/16"
bitfld.long 0x00 8. " PENA ,Peripheral Enable" "Reset,No reset"
group.long 0xD4++0x3
line.long 0x0 "ECPCNTRL,ECP Control Register"
bitfld.long 0x00 24. " ECPSSEL ,ECP Source Clock Select for ECP Module" "VCLK,Oscillator"
bitfld.long 0x00 23. " ECPCOS ,ECP Continue on Suspend" "Disabled,Enabled"
textline " "
hexmask.long.word 0x00 0.--15. 1. " ECPDIV[15:0] ,ECP Divider Value"
group.long 0xDC++0x3
line.long 0x0 "DEVCR1,DEV Parity Control Register1"
bitfld.long 0x00 0.--3. " DEVPARSEL ,Device Parity Select Bit Key" ",,,,,Even,,,,,Odd,?..."
group.long 0xE0++0x3
line.long 0x0 "SYSECR,System Exception Control Register"
bitfld.long 0x00 14.--15. " RESET ,Software Reset" "Reset,No reset,Reset,Reset"
width 10.
group.long 0xE4++0x3
line.long 0x0 "SYSESR,System Exception Status Register"
eventfld.long 0x00 15. " PORST ,Power-Up Reset" "No reset,Reset"
eventfld.long 0x00 14. " OSCRST ,Oscillator Failure/PLL Cycle Slip Reset" "No reset,Reset"
eventfld.long 0x00 13. " WDRST ,Watchdog Reset Flag" "No reset,Reset"
textline " "
eventfld.long 0x00 12. " WD2RST ,Watchdog 2 reset" "No reset,Reset"
eventfld.long 0x00 11. " DBGRST ,Debug reset" "No reset,Reset"
textline " "
eventfld.long 0x00 7. " ICSTRST ,Interconnect reset" "No reset,Reset"
eventfld.long 0x00 6. " CPU1RST ,CPU1 reset" "No reset,Reset"
eventfld.long 0x00 5. " CPU0RST ,CPU0 reset" "No reset,Reset"
textline " "
eventfld.long 0x00 4. " SWRST ,Software Reset Flag" "No reset,Reset"
eventfld.long 0x00 3. " EXTRST ,External Reset Flag" "No reset,Reset"
textline " "
eventfld.long 0x00 0. " MPMODE ,This indicates the current memory protection unit (MPU) mode" "Disabled,Enabled"
group.long 0xE8++0x3
line.long 0x0 "SYSTASR,System Test Abort Status Register"
bitfld.long 0x00 0.--4. " EFUSE_ABORT ,Test Abort Status Flag" "Read: Last operation,Read: Controller times out,Read: Autoload/Not find FuseROM,Read: Autoload/Scan chain,Read: Autoload/Not completed operation,,,,,,,,,,,,,,,,,,,,,,,,,,,Write: Cleared"
width 10.
group.long 0xEC++0x3
line.long 0x0 "GLBSTAT,Global Status Register"
eventfld.long 0x00 9. " FBSLIP ,Over Cycle Slip Detection of PLL" "Not detected,Detected"
eventfld.long 0x00 8. " RFSLIP ,Under Cycle Slip Detection of PLL" "Not detected,Detected"
eventfld.long 0x00 0. " OSCFAIL ,Oscillator Fail Flag" "Not failed,Failed"
rgroup.long 0xF0++0x3
line.long 0x0 "DEVID,Device Identification Register"
bitfld.long 0x00 31. " CP15 ,CP15 CPU" "No CP15,CP15"
hexmask.long.word 0x00 17.--30. 1. " UNIQUE_ID ,Device ID"
bitfld.long 0x00 13.--16. " TECH ,Device Manufacture Process Technology" "C05,F05,C035,F035,C021,F021,?..."
textline " "
bitfld.long 0x00 12. " I/O_VOLTAGE ,Input/Output Voltage" "3.3 V,5 V"
bitfld.long 0x00 11. " PERIPHERAL_PARITY ,Peripheral Parity" "No parity,Parity"
bitfld.long 0x00 9.--10. " FLASH_ECC ,Program Memory Parity Present" "Not protected,Single bit,ECC,?..."
textline " "
bitfld.long 0x00 8. " RAM_RECC ,RAM ECC" "No ECC,ECC"
hexmask.long.byte 0x00 3.--7. 1. " VERSION ,Version"
hexmask.long.byte 0x00 0.--2. 1. " PLATFORM_ID ,The TMS570Px Platform ID"
hgroup.long 0xF4++0x3
hide.long 0x0 "SSIVEC,Software Interrupt Vector Register"
in
width 10.
group.long 0xF8++0x3
line.long 0x0 "SSIF,System Software Interrupt Flag Register"
eventfld.long 0x00 3. " SSI_FLAG4 ,System Software Interrupt Flag 4" "No interrupt,Interrupt"
eventfld.long 0x00 2. " SSI_FLAG3 ,System Software Interrupt Flag 3" "No interrupt,Interrupt"
textline " "
eventfld.long 0x00 1. " SSI_FLAG2 ,System Software Interrupt Flag 2" "No interrupt,Interrupt"
eventfld.long 0x00 0. " SSI_FLAG1 ,System Software Interrupt Flag 1" "No interrupt,Interrupt"
width 11.
tree.end
tree "SYS2 (Secondary System Registers)"
base ad:0xFFFFE100
width 15.
group.long 0x00++0x3
line.long 0x0 "PLLCTL3,PLL Control Register 3"
bitfld.long 0x00 29.--31. " ODPLL2 ,Internal PLL Output Divider" "/1,/2,/3,/4,/5,/6,/7,/8"
bitfld.long 0x00 24.--28. " PLLDIV2 ,PLL#2 Output Clock Divider" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32"
textline " "
bitfld.long 0x00 16.--21. " REFCLKDIV2 ,Reference Clock Divider" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64"
hexmask.long.word 0x00 0.--15. 1. " PLL_MUL2 ,PLL multiplication"
group.long 0x08++0x3
line.long 0x0 "STCLKDIV,CPU Logic BIST Clock Divider"
bitfld.long 0x00 24.--26. " CLKDIV ,Clock divider/prescaler for CPU clock during logic BIST" "/1,/2,/3,/4,/5,/6,/7,/8"
group.long 0x28++0x03
line.long 0x00 "ECPCNTL1,ECP Control Register 1"
bitfld.long 0x00 28.--31. " ECP_KEY ,Enable ECP clock logic for ECLK2" "Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Enabled,Disabled,Disabled,Disabled,Disabled,Disabled"
bitfld.long 0x00 24. " ECPSSEL ,Allows the selection between VCLK and OSCIN as the clock source for ECLK2" "VCLK,OSCIN"
textline " "
bitfld.long 0x00 23. " ECPCOS ,ECP continue on suspend" "Disabled,Enabled"
hexmask.long.word 0x00 0.--15. 1. " ECPDIV ,ECP divider value"
group.long 0x3C++0x3
line.long 0x0 "CLK2CNTRL,Clock 2 Control Register"
bitfld.long 0x00 0.--3. " VCLK3R[3:0] ,VBUS clock3 ratio" "HCLK,HCLK/2,HCLK/3,HCLK/4,HCLK/5,HCLK/6,HCLK/7,HCLK/8,HCLK/9,HCLK/10,HCLK/11,HCLK/12,HCLK/13,HCLK/14,HCLK/15,HCLK/16"
group.long 0x40++0x3
line.long 0x0 "VCLKACON1,Peripheral Asynchronous Clock Configuration 1 Register"
bitfld.long 0x00 24.--26. " VCLKA4R ,Clock divider for the VCLKA4 source" "VCLKA4,VCLKA4/2,VCLKA4/3,VCLKA4/4,VCLKA4/5,VCLKA4/6,VCLKA4/7,VCLKA4/8"
bitfld.long 0x00 20. " VCLKA4_DIV_CDDIS ,Disable the VCLKA4 divider output" "No,Yes"
textline " "
bitfld.long 0x00 16.--19. " VCLKA4S[3:0] ,Peripheral asynchronous clock4 source" "Source 0,Source 1,Source 2,Source 3,Source 4,Source 5,Source 6,Source 7,VCLK,VCLK,VCLK,VCLK,VCLK,VCLK,VCLK,VCLK"
bitfld.long 0x00 8.--10. " VCLKA3R ,Clock divider for the VCLKA3 source" "VCLKA3,VCLKA3/2,VCLKA3/3,VCLKA3/4,VCLKA3/5,VCLKA3/6,VCLKA3/7,VCLKA3/8"
textline " "
bitfld.long 0x00 4. " VCLKA3_DIV_CDDIS ,Disable the VCLKA3 divider output" "No,Yes"
bitfld.long 0x00 0.--3. " VCLKA3S[3:0] ,Peripheral asynchronous clock3 source" "Source 0,Source 1,Source 2,Source 3,Source 4,Source 5,Source 6,Source 7,VCLK,VCLK,VCLK,VCLK,VCLK,VCLK,VCLK,VCLK"
group.long 0x54++0x03
line.long 0x00 "HCLKCNTL,HCLK Control Register"
bitfld.long 0x00 0.--1. " HCLKR ,HCLK divider value" "/1,/2,/3,/4"
group.long 0x70++0x3
line.long 0x0 "CLKSLIP,Clock Slip Register"
bitfld.long 0x00 8.--13. " PLL1_SLIP_FILTER_COUNT ,Configure the count for the filtered PLL slip" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 0.--3. " PLL1_SLIP_FILTER_KEY ,Enable the PLL filtering" "Enabled,Enabled,Enabled,Enabled,Enabled,Disabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,?..."
group.long 0x78++0x03
line.long 0x00 "IP1ECCERREN,IP ECC Error Enable Register"
bitfld.long 0x00 8.--11. " IP2_ECC_KEY ,ECC Error Enable Key for PS_SCR_M master" "Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Enabled,Disabled,Disabled,Disabled,Disabled,Disabled"
bitfld.long 0x00 0.--3. " IP1_ECC_KEY ,ECC Error Enable Key for DMA Port A master" "Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Enabled,Disabled,Disabled,Disabled,Disabled,Disabled"
group.long 0xEC++0x3
line.long 0x0 "EFC_CTLREG,EFUSE Controller Control Register"
bitfld.long 0x00 0.--3. " EFC_INSTR_WEN ,Enable user write of 4 EFUSE controller instructions" "Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Enabled,Disabled,Disabled,Disabled,Disabled,Disabled"
rgroup.long 0xF0++0x3
line.long 0x0 "DIEIDL_REG0,Die Identification Register Lower Word"
rgroup.long 0xF4++0x3
line.long 0x0 "DIEIDH_REG1,Die Identification Register Upper Word"
rgroup.long 0xF8++0x3
line.long 0x0 "DIEIDH_REG2,Die Identification Register Lower Word"
rgroup.long 0xFC++0x3
line.long 0x0 "DIEIDH_REG3,Die Identification Register Upper Word"
width 11.
tree.end
tree.open "PCR (Peripheral Central Resource)"
tree "PCR 1 (Peripheral Central Resource)"
base ad:0xFFFF1000
width 13.
tree "PCR Power Down Registers"
group.long 0xC0++0x3
line.long 0x0 "PDPWRDWNSET,Debug Frame Powerdown Set Register"
setclrfld.long 0x00 0. 0x00 0. 0x04 0. " PDWRDWN_set/clr ,Debug Power Down" "No power down,Power down"
tree.end
width 15.
tree "MasterID Registers"
group.long 0x200++0x0B
line.long 0x00 "MSTIDWRENA,MasterID Protection Write Enable Register"
bitfld.long 0x00 0.--3. " MSTIDREG_WRENA ,MasterID Register Write Enable" "Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Enabled,Disabled,Disabled,Disabled,Disabled,Disabled"
line.long 0x04 "MSTIDENA,MasterID Enable Register"
bitfld.long 0x04 0.--3. " MSTID_CHK_ENA ,MasterID Check Enable" "Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Enabled,Disabled,Disabled,Disabled,Disabled,Disabled"
line.long 0x08 "MSTIDDIAGCTRL,MasterID Diagnostic Control Register"
bitfld.long 0x08 8.--11. " DIAG_CMP_VALUE ,Diagnostic Compare Value" "Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Enabled,Disabled,Disabled,Disabled,Disabled,Disabled"
bitfld.long 0x08 0.--3. " DIAG_MODE_ENA ,Diagnostic Mode Enable" "Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Enabled,Disabled,Disabled,Disabled,Disabled,Disabled"
tree.end
width 15.
tree "Protection Registers"
tree "Privileged Peripheral Frame MasterID Protection Registers"
group.long 0x400++0x07
line.long 0x00 "PPS0MSTID_L,System Module Frame 2 (PPS [0]) MasterID Protection Register_L"
bitfld.long 0x00 25. " PPS0_QUAD1_MSTID [9] ,DAP filtering for Quadrant 1 of PPS [0]" "Disabled,Enabled"
bitfld.long 0x00 23. " [7] ,DMM filtering for Quadrant 1 of PPS [0]" "Disabled,Enabled"
bitfld.long 0x00 18. " [2] ,DMA Port B filtering for Quadrant 1 of PPS [0]" "Disabled,Enabled"
bitfld.long 0x00 16. " [0] ,CPU Read/Write filtering for Quadrant 1 of PPS [0]" "Disabled,Enabled"
textline " "
bitfld.long 0x00 9. " PPS0_QUAD0_MSTID [9] ,DAP filtering for Quadrant 0 of PPS [0]" "Disabled,Enabled"
bitfld.long 0x00 7. " [7] ,DMM filtering for Quadrant 0 of PPS [0]" "Disabled,Enabled"
bitfld.long 0x00 2. " [2] ,DMA Port B filtering for Quadrant 0 of PPS [0]" "Disabled,Enabled"
bitfld.long 0x00 0. " [0] ,CPU Read/Write filtering for Quadrant 0 of PPS [0]" "Disabled,Enabled"
line.long 0x04 "PPS0MSTID_H,System Module Frame 2 (PPS [0]) MasterID Protection Register_H"
bitfld.long 0x04 25. " PPS0_QUAD3_MSTID [9] ,DAP filtering for Quadrant 3 of PPS [0]" "Disabled,Enabled"
bitfld.long 0x04 23. " [7] ,DMM filtering for Quadrant 3 of PPS [0]" "Disabled,Enabled"
bitfld.long 0x04 18. " [2] ,DMA Port B filtering for Quadrant 3 of PPS [0]" "Disabled,Enabled"
bitfld.long 0x04 16. " [0] ,CPU Read/Write filtering for Quadrant 3 of PPS [0]" "Disabled,Enabled"
textline " "
bitfld.long 0x04 9. " PPS0_QUAD2_MSTID [9] ,DAP filtering for Quadrant 2 of PPS [0]" "Disabled,Enabled"
bitfld.long 0x04 7. " [7] ,DMM filtering for Quadrant 2 of PPS [0]" "Disabled,Enabled"
bitfld.long 0x04 2. " [2] ,DMA Port B filtering for Quadrant 2 of PPS [0]" "Disabled,Enabled"
bitfld.long 0x04 0. " [0] ,CPU Read/Write filtering for Quadrant 2 of PPS [0]" "Disabled,Enabled"
group.long 0x408++0x07
line.long 0x00 "PPS1MSTID_L,PBIST/STC1 (PPS [1]) MasterID Protection Register_L"
bitfld.long 0x00 25. " PPS1_QUAD1_MSTID [9] ,DAP filtering for Quadrant 1 of PPS [1]" "Disabled,Enabled"
bitfld.long 0x00 23. " [7] ,DMM filtering for Quadrant 1 of PPS [1]" "Disabled,Enabled"
bitfld.long 0x00 18. " [2] ,DMA Port B filtering for Quadrant 1 of PPS [1]" "Disabled,Enabled"
bitfld.long 0x00 16. " [0] ,CPU Read/Write filtering for Quadrant 1 of PPS [1]" "Disabled,Enabled"
textline " "
bitfld.long 0x00 9. " PPS1_QUAD0_MSTID [9] ,DAP filtering for Quadrant 0 of PPS [1]" "Disabled,Enabled"
bitfld.long 0x00 7. " [7] ,DMM filtering for Quadrant 0 of PPS [1]" "Disabled,Enabled"
bitfld.long 0x00 2. " [2] ,DMA Port B filtering for Quadrant 0 of PPS [1]" "Disabled,Enabled"
bitfld.long 0x00 0. " [0] ,CPU Read/Write filtering for Quadrant 0 of PPS [1]" "Disabled,Enabled"
line.long 0x04 "PPS1MSTID_H,PBIST/STC1 (PPS [1]) MasterID Protection Register_H"
bitfld.long 0x04 25. " PPS1_QUAD3_MSTID [9] ,DAP filtering for Quadrant 3 of PPS [1]" "Disabled,Enabled"
bitfld.long 0x04 23. " [7] ,DMM filtering for Quadrant 3 of PPS [1]" "Disabled,Enabled"
bitfld.long 0x04 18. " [2] ,DMA Port B filtering for Quadrant 3 of PPS [1]" "Disabled,Enabled"
bitfld.long 0x04 16. " [0] ,CPU Read/Write filtering for Quadrant 3 of PPS [1]" "Disabled,Enabled"
textline " "
bitfld.long 0x04 9. " PPS1_QUAD2_MSTID [9] ,DAP filtering for Quadrant 2 of PPS [1]" "Disabled,Enabled"
bitfld.long 0x04 7. " [7] ,DMM filtering for Quadrant 2 of PPS [1]" "Disabled,Enabled"
bitfld.long 0x04 2. " [2] ,DMA Port B filtering for Quadrant 2 of PPS [1]" "Disabled,Enabled"
bitfld.long 0x04 0. " [0] ,CPU Read/Write filtering for Quadrant 2 of PPS [1]" "Disabled,Enabled"
group.long 0x418++0x07
line.long 0x00 "PPS3MSTID_L,DCC1 (PPS [3]) MasterID Protection Register_L"
bitfld.long 0x00 25. " PPS3_QUAD1_MSTID [9] ,DAP filtering for Quadrant 1 of PPS [3]" "Disabled,Enabled"
bitfld.long 0x00 23. " [7] ,DMM filtering for Quadrant 1 of PPS [3]" "Disabled,Enabled"
bitfld.long 0x00 18. " [2] ,DMA Port B filtering for Quadrant 1 of PPS [3]" "Disabled,Enabled"
bitfld.long 0x00 16. " [0] ,CPU Read/Write filtering for Quadrant 1 of PPS [3]" "Disabled,Enabled"
textline " "
bitfld.long 0x00 9. " PPS3_QUAD0_MSTID [9] ,DAP filtering for Quadrant 0 of PPS [3]" "Disabled,Enabled"
bitfld.long 0x00 7. " [7] ,DMM filtering for Quadrant 0 of PPS [3]" "Disabled,Enabled"
bitfld.long 0x00 2. " [2] ,DMA Port B filtering for Quadrant 0 of PPS [3]" "Disabled,Enabled"
bitfld.long 0x00 0. " [0] ,CPU Read/Write filtering for Quadrant 0 of PPS [3]" "Disabled,Enabled"
line.long 0x04 "PPS3MSTID_H,DCC1 (PPS [3]) MasterID Protection Register_H"
bitfld.long 0x04 25. " PPS3_QUAD3_MSTID [9] ,DAP filtering for Quadrant 3 of PPS [3]" "Disabled,Enabled"
bitfld.long 0x04 23. " [7] ,DMM filtering for Quadrant 3 of PPS [3]" "Disabled,Enabled"
bitfld.long 0x04 18. " [2] ,DMA Port B filtering for Quadrant 3 of PPS [3]" "Disabled,Enabled"
bitfld.long 0x04 16. " [0] ,CPU Read/Write filtering for Quadrant 3 of PPS [3]" "Disabled,Enabled"
textline " "
bitfld.long 0x04 9. " PPS3_QUAD2_MSTID [9] ,DAP filtering for Quadrant 2 of PPS [3]" "Disabled,Enabled"
bitfld.long 0x04 7. " [7] ,DMM filtering for Quadrant 2 of PPS [3]" "Disabled,Enabled"
bitfld.long 0x04 2. " [2] ,DMA Port B filtering for Quadrant 2 of PPS [3]" "Disabled,Enabled"
bitfld.long 0x04 0. " [0] ,CPU Read/Write filtering for Quadrant 2 of PPS [3]" "Disabled,Enabled"
group.long 0x420++0x07
line.long 0x00 "PPS4MSTID_L,DMA (PPS [4]) MasterID Protection Register_L"
bitfld.long 0x00 25. " PPS4_QUAD1_MSTID [9] ,DAP filtering for Quadrant 1 of PPS [4]" "Disabled,Enabled"
bitfld.long 0x00 23. " [7] ,DMM filtering for Quadrant 1 of PPS [4]" "Disabled,Enabled"
bitfld.long 0x00 18. " [2] ,DMA Port B filtering for Quadrant 1 of PPS [4]" "Disabled,Enabled"
bitfld.long 0x00 16. " [0] ,CPU Read/Write filtering for Quadrant 1 of PPS [4]" "Disabled,Enabled"
textline " "
bitfld.long 0x00 9. " PPS4_QUAD0_MSTID [9] ,DAP filtering for Quadrant 0 of PPS [4]" "Disabled,Enabled"
bitfld.long 0x00 7. " [7] ,DMM filtering for Quadrant 0 of PPS [4]" "Disabled,Enabled"
bitfld.long 0x00 2. " [2] ,DMA Port B filtering for Quadrant 0 of PPS [4]" "Disabled,Enabled"
bitfld.long 0x00 0. " [0] ,CPU Read/Write filtering for Quadrant 0 of PPS [4]" "Disabled,Enabled"
line.long 0x04 "PPS4MSTID_H,DMA (PPS [4]) MasterID Protection Register_H"
bitfld.long 0x04 25. " PPS4_QUAD3_MSTID [9] ,DAP filtering for Quadrant 3 of PPS [4]" "Disabled,Enabled"
bitfld.long 0x04 23. " [7] ,DMM filtering for Quadrant 3 of PPS [4]" "Disabled,Enabled"
bitfld.long 0x04 18. " [2] ,DMA Port B filtering for Quadrant 3 of PPS [4]" "Disabled,Enabled"
bitfld.long 0x04 16. " [0] ,CPU Read/Write filtering for Quadrant 3 of PPS [4]" "Disabled,Enabled"
textline " "
bitfld.long 0x04 9. " PPS4_QUAD2_MSTID [9] ,DAP filtering for Quadrant 2 of PPS [4]" "Disabled,Enabled"
bitfld.long 0x04 7. " [7] ,DMM filtering for Quadrant 2 of PPS [4]" "Disabled,Enabled"
bitfld.long 0x04 2. " [2] ,DMA Port B filtering for Quadrant 2 of PPS [4]" "Disabled,Enabled"
bitfld.long 0x04 0. " [0] ,CPU Read/Write filtering for Quadrant 2 of PPS [4]" "Disabled,Enabled"
group.long 0x428++0x07
line.long 0x00 "PPS5MSTID_L,DCC2/ESM/CCM-R5/DMM (PPS [5]) MasterID Protection Register_L"
bitfld.long 0x00 25. " PPS5_QUAD1_MSTID [9] ,DAP filtering for Quadrant 1 of PPS [5]" "Disabled,Enabled"
bitfld.long 0x00 23. " [7] ,DMM filtering for Quadrant 1 of PPS [5]" "Disabled,Enabled"
bitfld.long 0x00 18. " [2] ,DMA Port B filtering for Quadrant 1 of PPS [5]" "Disabled,Enabled"
bitfld.long 0x00 16. " [0] ,CPU Read/Write filtering for Quadrant 1 of PPS [5]" "Disabled,Enabled"
textline " "
bitfld.long 0x00 9. " PPS5_QUAD0_MSTID [9] ,DAP filtering for Quadrant 0 of PPS [5]" "Disabled,Enabled"
bitfld.long 0x00 7. " [7] ,DMM filtering for Quadrant 0 of PPS [5]" "Disabled,Enabled"
bitfld.long 0x00 2. " [2] ,DMA Port B filtering for Quadrant 0 of PPS [5]" "Disabled,Enabled"
bitfld.long 0x00 0. " [0] ,CPU Read/Write filtering for Quadrant 0 of PPS [5]" "Disabled,Enabled"
line.long 0x04 "PPS5MSTID_H,DCC2/ESM/CCM-R5/DMM (PPS [5]) MasterID Protection Register_H"
bitfld.long 0x04 25. " PPS5_QUAD3_MSTID [9] ,DAP filtering for Quadrant 3 of PPS [5]" "Disabled,Enabled"
bitfld.long 0x04 23. " [7] ,DMM filtering for Quadrant 3 of PPS [5]" "Disabled,Enabled"
bitfld.long 0x04 18. " [2] ,DMA Port B filtering for Quadrant 3 of PPS [5]" "Disabled,Enabled"
bitfld.long 0x04 16. " [0] ,CPU Read/Write filtering for Quadrant 3 of PPS [5]" "Disabled,Enabled"
textline " "
bitfld.long 0x04 9. " PPS5_QUAD2_MSTID [9] ,DAP filtering for Quadrant 2 of PPS [5]" "Disabled,Enabled"
bitfld.long 0x04 7. " [7] ,DMM filtering for Quadrant 2 of PPS [5]" "Disabled,Enabled"
bitfld.long 0x04 2. " [2] ,DMA Port B filtering for Quadrant 2 of PPS [5]" "Disabled,Enabled"
bitfld.long 0x04 0. " [0] ,CPU Read/Write filtering for Quadrant 2 of PPS [5]" "Disabled,Enabled"
group.long 0x430++0x07
line.long 0x00 "PPS6MSTID_L,L2RAMW/RTP (PPS [6]) MasterID Protection Register_L"
bitfld.long 0x00 25. " PPS6_QUAD1_MSTID [9] ,DAP filtering for Quadrant 1 of PPS [6]" "Disabled,Enabled"
bitfld.long 0x00 23. " [7] ,DMM filtering for Quadrant 1 of PPS [6]" "Disabled,Enabled"
bitfld.long 0x00 18. " [2] ,DMA Port B filtering for Quadrant 1 of PPS [6]" "Disabled,Enabled"
bitfld.long 0x00 16. " [0] ,CPU Read/Write filtering for Quadrant 1 of PPS [6]" "Disabled,Enabled"
textline " "
bitfld.long 0x00 9. " PPS6_QUAD0_MSTID [9] ,DAP filtering for Quadrant 0 of PPS [6]" "Disabled,Enabled"
bitfld.long 0x00 7. " [7] ,DMM filtering for Quadrant 0 of PPS [6]" "Disabled,Enabled"
bitfld.long 0x00 2. " [2] ,DMA Port B filtering for Quadrant 0 of PPS [6]" "Disabled,Enabled"
bitfld.long 0x00 0. " [0] ,CPU Read/Write filtering for Quadrant 0 of PPS [6]" "Disabled,Enabled"
line.long 0x04 "PPS6MSTID_H,L2RAMW/RTP (PPS [6]) MasterID Protection Register_H"
bitfld.long 0x04 25. " PPS6_QUAD3_MSTID [9] ,DAP filtering for Quadrant 3 of PPS [6]" "Disabled,Enabled"
bitfld.long 0x04 23. " [7] ,DMM filtering for Quadrant 3 of PPS [6]" "Disabled,Enabled"
bitfld.long 0x04 18. " [2] ,DMA Port B filtering for Quadrant 3 of PPS [6]" "Disabled,Enabled"
bitfld.long 0x04 16. " [0] ,CPU Read/Write filtering for Quadrant 3 of PPS [6]" "Disabled,Enabled"
textline " "
bitfld.long 0x04 9. " PPS6_QUAD2_MSTID [9] ,DAP filtering for Quadrant 2 of PPS [6]" "Disabled,Enabled"
bitfld.long 0x04 7. " [7] ,DMM filtering for Quadrant 2 of PPS [6]" "Disabled,Enabled"
bitfld.long 0x04 2. " [2] ,DMA Port B filtering for Quadrant 2 of PPS [6]" "Disabled,Enabled"
bitfld.long 0x04 0. " [0] ,CPU Read/Write filtering for Quadrant 2 of PPS [6]" "Disabled,Enabled"
group.long 0x438++0x07
line.long 0x00 "PPS7MSTID_L,RTI+DWWD/VIM/System Module Frame 1 (PPS [7]) MasterID Protection Register_L"
bitfld.long 0x00 25. " PPS7_QUAD1_MSTID [9] ,DAP filtering for Quadrant 1 of PPS [7]" "Disabled,Enabled"
bitfld.long 0x00 23. " [7] ,DMM filtering for Quadrant 1 of PPS [7]" "Disabled,Enabled"
bitfld.long 0x00 18. " [2] ,DMA Port B filtering for Quadrant 1 of PPS [7]" "Disabled,Enabled"
bitfld.long 0x00 16. " [0] ,CPU Read/Write filtering for Quadrant 1 of PPS [7]" "Disabled,Enabled"
textline " "
bitfld.long 0x00 9. " PPS7_QUAD0_MSTID [9] ,DAP filtering for Quadrant 0 of PPS [7]" "Disabled,Enabled"
bitfld.long 0x00 7. " [7] ,DMM filtering for Quadrant 0 of PPS [7]" "Disabled,Enabled"
bitfld.long 0x00 2. " [2] ,DMA Port B filtering for Quadrant 0 of PPS [7]" "Disabled,Enabled"
bitfld.long 0x00 0. " [0] ,CPU Read/Write filtering for Quadrant 0 of PPS [7]" "Disabled,Enabled"
line.long 0x04 "PPS7MSTID_H,RTI+DWWD/VIM/System Module Frame 1 (PPS [7]) MasterID Protection Register_H"
bitfld.long 0x04 25. " PPS7_QUAD3_MSTID [9] ,DAP filtering for Quadrant 3 of PPS [7]" "Disabled,Enabled"
bitfld.long 0x04 23. " [7] ,DMM filtering for Quadrant 3 of PPS [7]" "Disabled,Enabled"
bitfld.long 0x04 18. " [2] ,DMA Port B filtering for Quadrant 3 of PPS [7]" "Disabled,Enabled"
bitfld.long 0x04 16. " [0] ,CPU Read/Write filtering for Quadrant 3 of PPS [7]" "Disabled,Enabled"
textline " "
bitfld.long 0x04 9. " PPS7_QUAD2_MSTID [9] ,DAP filtering for Quadrant 2 of PPS [7]" "Disabled,Enabled"
bitfld.long 0x04 7. " [7] ,DMM filtering for Quadrant 2 of PPS [7]" "Disabled,Enabled"
bitfld.long 0x04 2. " [2] ,DMA Port B filtering for Quadrant 2 of PPS [7]" "Disabled,Enabled"
bitfld.long 0x04 0. " [0] ,CPU Read/Write filtering for Quadrant 2 of PPS [7]" "Disabled,Enabled"
tree.end
tree "Privileged Peripheral Extended Frame MasterID Protection Registers"
group.long 0x440++0x07
line.long 0x00 "PPSE0MSTID_L,Power Domain Control (PMM) (PPSE [0]) MasterID Protection Register_L"
bitfld.long 0x00 25. " PPSE0_QUAD1_MSTID [9] ,DAP filtering for Quadrant 1 of PPSE[0]" "Disabled,Enabled"
bitfld.long 0x00 23. " [7] ,DMM filtering for Quadrant 1 of PPSE [0]" "Disabled,Enabled"
bitfld.long 0x00 18. " [2] ,DMA Port B filtering for Quadrant 1 of PPSE [0]" "Disabled,Enabled"
bitfld.long 0x00 16. " [0] ,CPU Read/Write filtering for Quadrant 1 of PPSE [0]" "Disabled,Enabled"
textline " "
bitfld.long 0x00 9. " PPSE0_QUAD0_MSTID [9] ,DAP filtering for Quadrant 0 of PPSE[0]" "Disabled,Enabled"
bitfld.long 0x00 7. " [7] ,DMM filtering for Quadrant 0 of PPSE [0]" "Disabled,Enabled"
bitfld.long 0x00 2. " [2] ,DMA Port B filtering for Quadrant 0 of PPSE [0]" "Disabled,Enabled"
bitfld.long 0x00 0. " [0] ,CPU Read/Write filtering for Quadrant 0 of PPSE [0]" "Disabled,Enabled"
line.long 0x04 "PPSE0MSTID_H,Power Domain Control (PMM) (PPSE [0]) MasterID Protection Register_H"
bitfld.long 0x04 25. " PPSE0_QUAD3_MSTID [9] ,DAP filtering for Quadrant 3 of PPSE[0]" "Disabled,Enabled"
bitfld.long 0x04 23. " [7] ,DMM filtering for Quadrant 3 of PPSE [0]" "Disabled,Enabled"
bitfld.long 0x04 18. " [2] ,DMA Port B filtering for Quadrant 3 of PPSE [0]" "Disabled,Enabled"
bitfld.long 0x04 16. " [0] ,CPU Read/Write filtering for Quadrant 3 of PPSE [0]" "Disabled,Enabled"
textline " "
bitfld.long 0x04 9. " PPSE0_QUAD2_MSTID [9] ,DAP filtering for Quadrant 2 of PPSE[0]" "Disabled,Enabled"
bitfld.long 0x04 7. " [7] ,DMM filtering for Quadrant 2 of PPSE [0]" "Disabled,Enabled"
bitfld.long 0x04 2. " [2] ,DMA Port B filtering for Quadrant 2 of PPSE [0]" "Disabled,Enabled"
bitfld.long 0x04 0. " [0] ,CPU Read/Write filtering for Quadrant 2 of PPSE [0]" "Disabled,Enabled"
group.long 0x450++0x07
line.long 0x00 "PPSE2MSTID_L,STC2 (NHET1/2)/SCM (PPSE [2]) MasterID Protection Register_L"
bitfld.long 0x00 25. " PPSE2_QUAD1_MSTID [9] ,DAP filtering for Quadrant 1 of PPSE[2]" "Disabled,Enabled"
bitfld.long 0x00 23. " [7] ,DMM filtering for Quadrant 1 of PPSE [2]" "Disabled,Enabled"
bitfld.long 0x00 18. " [2] ,DMA Port B filtering for Quadrant 1 of PPSE [2]" "Disabled,Enabled"
bitfld.long 0x00 16. " [0] ,CPU Read/Write filtering for Quadrant 1 of PPSE [2]" "Disabled,Enabled"
textline " "
bitfld.long 0x00 9. " PPSE2_QUAD0_MSTID [9] ,DAP filtering for Quadrant 0 of PPSE[2]" "Disabled,Enabled"
bitfld.long 0x00 7. " [7] ,DMM filtering for Quadrant 0 of PPSE [2]" "Disabled,Enabled"
bitfld.long 0x00 2. " [2] ,DMA Port B filtering for Quadrant 0 of PPSE [2]" "Disabled,Enabled"
bitfld.long 0x00 0. " [0] ,CPU Read/Write filtering for Quadrant 0 of PPSE [2]" "Disabled,Enabled"
line.long 0x04 "PPSE2MSTID_H,STC2 (NHET1/2)/SCM (PPSE [2]) MasterID Protection Register_H"
bitfld.long 0x04 25. " PPSE2_QUAD3_MSTID [9] ,DAP filtering for Quadrant 3 of PPSE[2]" "Disabled,Enabled"
bitfld.long 0x04 23. " [7] ,DMM filtering for Quadrant 3 of PPSE [2]" "Disabled,Enabled"
bitfld.long 0x04 18. " [2] ,DMA Port B filtering for Quadrant 3 of PPSE [2]" "Disabled,Enabled"
bitfld.long 0x04 16. " [0] ,CPU Read/Write filtering for Quadrant 3 of PPSE [2]" "Disabled,Enabled"
textline " "
bitfld.long 0x04 9. " PPSE2_QUAD2_MSTID [9] ,DAP filtering for Quadrant 2 of PPSE[2]" "Disabled,Enabled"
bitfld.long 0x04 7. " [7] ,DMM filtering for Quadrant 2 of PPSE [2]" "Disabled,Enabled"
bitfld.long 0x04 2. " [2] ,DMA Port B filtering for Quadrant 2 of PPSE [2]" "Disabled,Enabled"
bitfld.long 0x04 0. " [0] ,CPU Read/Write filtering for Quadrant 2 of PPSE [2]" "Disabled,Enabled"
group.long 0x458++0x07
line.long 0x00 "PPSE3MSTID_L,EPC (PPSE [3]) MasterID Protection Register_L"
bitfld.long 0x00 25. " PPSE3_QUAD1_MSTID [9] ,DAP filtering for Quadrant 1 of PPSE[3]" "Disabled,Enabled"
bitfld.long 0x00 23. " [7] ,DMM filtering for Quadrant 1 of PPSE [3]" "Disabled,Enabled"
bitfld.long 0x00 18. " [2] ,DMA Port B filtering for Quadrant 1 of PPSE [3]" "Disabled,Enabled"
bitfld.long 0x00 16. " [0] ,CPU Read/Write filtering for Quadrant 1 of PPSE [3]" "Disabled,Enabled"
textline " "
bitfld.long 0x00 9. " PPSE3_QUAD0_MSTID [9] ,DAP filtering for Quadrant 0 of PPSE[3]" "Disabled,Enabled"
bitfld.long 0x00 7. " [7] ,DMM filtering for Quadrant 0 of PPSE [3]" "Disabled,Enabled"
bitfld.long 0x00 2. " [2] ,DMA Port B filtering for Quadrant 0 of PPSE [3]" "Disabled,Enabled"
bitfld.long 0x00 0. " [0] ,CPU Read/Write filtering for Quadrant 0 of PPSE [3]" "Disabled,Enabled"
line.long 0x04 "PPSE3MSTID_H,EPC (PPSE [3]) MasterID Protection Register_H"
bitfld.long 0x04 25. " PPSE3_QUAD3_MSTID [9] ,DAP filtering for Quadrant 3 of PPSE[3]" "Disabled,Enabled"
bitfld.long 0x04 23. " [7] ,DMM filtering for Quadrant 3 of PPSE [3]" "Disabled,Enabled"
bitfld.long 0x04 18. " [2] ,DMA Port B filtering for Quadrant 3 of PPSE [3]" "Disabled,Enabled"
bitfld.long 0x04 16. " [0] ,CPU Read/Write filtering for Quadrant 3 of PPSE [3]" "Disabled,Enabled"
textline " "
bitfld.long 0x04 9. " PPSE3_QUAD2_MSTID [9] ,DAP filtering for Quadrant 2 of PPSE[3]" "Disabled,Enabled"
bitfld.long 0x04 7. " [7] ,DMM filtering for Quadrant 2 of PPSE [3]" "Disabled,Enabled"
bitfld.long 0x04 2. " [2] ,DMA Port B filtering for Quadrant 2 of PPSE [3]" "Disabled,Enabled"
bitfld.long 0x04 0. " [0] ,CPU Read/Write filtering for Quadrant 2 of PPSE [3]" "Disabled,Enabled"
group.long 0x460++0x07
line.long 0x00 "PPSE4MSTID_L,PCR1 Registers (PPSE [4]) MasterID Protection Register_L"
bitfld.long 0x00 25. " PPSE4_QUAD1_MSTID [9] ,DAP filtering for Quadrant 1 of PPSE[4]" "Disabled,Enabled"
bitfld.long 0x00 23. " [7] ,DMM filtering for Quadrant 1 of PPSE [4]" "Disabled,Enabled"
bitfld.long 0x00 18. " [2] ,DMA Port B filtering for Quadrant 1 of PPSE [4]" "Disabled,Enabled"
bitfld.long 0x00 16. " [0] ,CPU Read/Write filtering for Quadrant 1 of PPSE [4]" "Disabled,Enabled"
textline " "
bitfld.long 0x00 9. " PPSE4_QUAD0_MSTID [9] ,DAP filtering for Quadrant 0 of PPSE[4]" "Disabled,Enabled"
bitfld.long 0x00 7. " [7] ,DMM filtering for Quadrant 0 of PPSE [4]" "Disabled,Enabled"
bitfld.long 0x00 2. " [2] ,DMA Port B filtering for Quadrant 0 of PPSE [4]" "Disabled,Enabled"
bitfld.long 0x00 0. " [0] ,CPU Read/Write filtering for Quadrant 0 of PPSE [4]" "Disabled,Enabled"
line.long 0x04 "PPSE4MSTID_H,PCR1 Registers (PPSE [4]) MasterID Protection Register_H"
bitfld.long 0x04 25. " PPSE4_QUAD3_MSTID [9] ,DAP filtering for Quadrant 3 of PPSE[4]" "Disabled,Enabled"
bitfld.long 0x04 23. " [7] ,DMM filtering for Quadrant 3 of PPSE [4]" "Disabled,Enabled"
bitfld.long 0x04 18. " [2] ,DMA Port B filtering for Quadrant 3 of PPSE [4]" "Disabled,Enabled"
bitfld.long 0x04 16. " [0] ,CPU Read/Write filtering for Quadrant 3 of PPSE [4]" "Disabled,Enabled"
textline " "
bitfld.long 0x04 9. " PPSE4_QUAD2_MSTID [9] ,DAP filtering for Quadrant 2 of PPSE[4]" "Disabled,Enabled"
bitfld.long 0x04 7. " [7] ,DMM filtering for Quadrant 2 of PPSE [4]" "Disabled,Enabled"
bitfld.long 0x04 2. " [2] ,DMA Port B filtering for Quadrant 2 of PPSE [4]" "Disabled,Enabled"
bitfld.long 0x04 0. " [0] ,CPU Read/Write filtering for Quadrant 2 of PPSE [4]" "Disabled,Enabled"
group.long 0x468++0x07
line.long 0x00 "PPSE5MSTID_L,PCR1 Registers (PPSE [5]) MasterID Protection Register_L"
bitfld.long 0x00 25. " PPSE5_QUAD1_MSTID [9] ,DAP filtering for Quadrant 1 of PPSE[5]" "Disabled,Enabled"
bitfld.long 0x00 23. " [7] ,DMM filtering for Quadrant 1 of PPSE [5]" "Disabled,Enabled"
bitfld.long 0x00 18. " [2] ,DMA Port B filtering for Quadrant 1 of PPSE [5]" "Disabled,Enabled"
bitfld.long 0x00 16. " [0] ,CPU Read/Write filtering for Quadrant 1 of PPSE [5]" "Disabled,Enabled"
textline " "
bitfld.long 0x00 9. " PPSE5_QUAD0_MSTID [9] ,DAP filtering for Quadrant 0 of PPSE[5]" "Disabled,Enabled"
bitfld.long 0x00 7. " [7] ,DMM filtering for Quadrant 0 of PPSE [5]" "Disabled,Enabled"
bitfld.long 0x00 2. " [2] ,DMA Port B filtering for Quadrant 0 of PPSE [5]" "Disabled,Enabled"
bitfld.long 0x00 0. " [0] ,CPU Read/Write filtering for Quadrant 0 of PPSE [5]" "Disabled,Enabled"
line.long 0x04 "PPSE5MSTID_H,PCR1 Registers (PPSE [5]) MasterID Protection Register_H"
bitfld.long 0x04 25. " PPSE5_QUAD3_MSTID [9] ,DAP filtering for Quadrant 3 of PPSE[5]" "Disabled,Enabled"
bitfld.long 0x04 23. " [7] ,DMM filtering for Quadrant 3 of PPSE [5]" "Disabled,Enabled"
bitfld.long 0x04 18. " [2] ,DMA Port B filtering for Quadrant 3 of PPSE [5]" "Disabled,Enabled"
bitfld.long 0x04 16. " [0] ,CPU Read/Write filtering for Quadrant 3 of PPSE [5]" "Disabled,Enabled"
textline " "
bitfld.long 0x04 9. " PPSE5_QUAD2_MSTID [9] ,DAP filtering for Quadrant 2 of PPSE[5]" "Disabled,Enabled"
bitfld.long 0x04 7. " [7] ,DMM filtering for Quadrant 2 of PPSE [5]" "Disabled,Enabled"
bitfld.long 0x04 2. " [2] ,DMA Port B filtering for Quadrant 2 of PPSE [5]" "Disabled,Enabled"
bitfld.long 0x04 0. " [0] ,CPU Read/Write filtering for Quadrant 2 of PPSE [5]" "Disabled,Enabled"
group.long 0x470++0x07
line.long 0x00 "PPSE6MSTID_L,NMPU (PS_SCR_S/DMA Port A) (PPSE [6]) MasterID Protection Register_L"
bitfld.long 0x00 25. " PPSE6_QUAD1_MSTID [9] ,DAP filtering for Quadrant 1 of PPSE[6]" "Disabled,Enabled"
bitfld.long 0x00 23. " [7] ,DMM filtering for Quadrant 1 of PPSE [6]" "Disabled,Enabled"
bitfld.long 0x00 18. " [2] ,DMA Port B filtering for Quadrant 1 of PPSE [6]" "Disabled,Enabled"
bitfld.long 0x00 16. " [0] ,CPU Read/Write filtering for Quadrant 1 of PPSE [6]" "Disabled,Enabled"
textline " "
bitfld.long 0x00 9. " PPSE6_QUAD0_MSTID [9] ,DAP filtering for Quadrant 0 of PPSE[6]" "Disabled,Enabled"
bitfld.long 0x00 7. " [7] ,DMM filtering for Quadrant 0 of PPSE [6]" "Disabled,Enabled"
bitfld.long 0x00 2. " [2] ,DMA Port B filtering for Quadrant 0 of PPSE [6]" "Disabled,Enabled"
bitfld.long 0x00 0. " [0] ,CPU Read/Write filtering for Quadrant 0 of PPSE [6]" "Disabled,Enabled"
line.long 0x04 "PPSE6MSTID_H,NMPU (PS_SCR_S/DMA Port A) (PPSE [6]) MasterID Protection Register_H"
bitfld.long 0x04 25. " PPSE6_QUAD3_MSTID [9] ,DAP filtering for Quadrant 3 of PPSE[6]" "Disabled,Enabled"
bitfld.long 0x04 23. " [7] ,DMM filtering for Quadrant 3 of PPSE [6]" "Disabled,Enabled"
bitfld.long 0x04 18. " [2] ,DMA Port B filtering for Quadrant 3 of PPSE [6]" "Disabled,Enabled"
bitfld.long 0x04 16. " [0] ,CPU Read/Write filtering for Quadrant 3 of PPSE [6]" "Disabled,Enabled"
textline " "
bitfld.long 0x04 9. " PPSE6_QUAD2_MSTID [9] ,DAP filtering for Quadrant 2 of PPSE[6]" "Disabled,Enabled"
bitfld.long 0x04 7. " [7] ,DMM filtering for Quadrant 2 of PPSE [6]" "Disabled,Enabled"
bitfld.long 0x04 2. " [2] ,DMA Port B filtering for Quadrant 2 of PPSE [6]" "Disabled,Enabled"
bitfld.long 0x04 0. " [0] ,CPU Read/Write filtering for Quadrant 2 of PPSE [6]" "Disabled,Enabled"
group.long 0x478++0x07
line.long 0x00 "PPSE7MSTID_L,Pin Mux Control (IOMM) (PPSE [7]) MasterID Protection Register_L"
bitfld.long 0x00 25. " PPSE7_QUAD1_MSTID [9] ,DAP filtering for Quadrant 1 of PPSE[7]" "Disabled,Enabled"
bitfld.long 0x00 23. " [7] ,DMM filtering for Quadrant 1 of PPSE [7]" "Disabled,Enabled"
bitfld.long 0x00 18. " [2] ,DMA Port B filtering for Quadrant 1 of PPSE [7]" "Disabled,Enabled"
bitfld.long 0x00 16. " [0] ,CPU Read/Write filtering for Quadrant 1 of PPSE [7]" "Disabled,Enabled"
textline " "
bitfld.long 0x00 9. " PPSE7_QUAD0_MSTID [9] ,DAP filtering for Quadrant 0 of PPSE[7]" "Disabled,Enabled"
bitfld.long 0x00 7. " [7] ,DMM filtering for Quadrant 0 of PPSE [7]" "Disabled,Enabled"
bitfld.long 0x00 2. " [2] ,DMA Port B filtering for Quadrant 0 of PPSE [7]" "Disabled,Enabled"
bitfld.long 0x00 0. " [0] ,CPU Read/Write filtering for Quadrant 0 of PPSE [7]" "Disabled,Enabled"
line.long 0x04 "PPSE7MSTID_H,Pin Mux Control (IOMM) (PPSE [7]) MasterID Protection Register_H"
bitfld.long 0x04 25. " PPSE7_QUAD3_MSTID [9] ,DAP filtering for Quadrant 3 of PPSE[7]" "Disabled,Enabled"
bitfld.long 0x04 23. " [7] ,DMM filtering for Quadrant 3 of PPSE [7]" "Disabled,Enabled"
bitfld.long 0x04 18. " [2] ,DMA Port B filtering for Quadrant 3 of PPSE [7]" "Disabled,Enabled"
bitfld.long 0x04 16. " [0] ,CPU Read/Write filtering for Quadrant 3 of PPSE [7]" "Disabled,Enabled"
textline " "
bitfld.long 0x04 9. " PPSE7_QUAD2_MSTID [9] ,DAP filtering for Quadrant 2 of PPSE[7]" "Disabled,Enabled"
bitfld.long 0x04 7. " [7] ,DMM filtering for Quadrant 2 of PPSE [7]" "Disabled,Enabled"
bitfld.long 0x04 2. " [2] ,DMA Port B filtering for Quadrant 2 of PPSE [7]" "Disabled,Enabled"
bitfld.long 0x04 0. " [0] ,CPU Read/Write filtering for Quadrant 2 of PPSE [7]" "Disabled,Enabled"
tree.end
width 13.
tree "Privileged Peripheral Memory Frame MasterID Protection Registers"
group.long 0x5C0++0x03
line.long 0x00 "PPCS0MSTID,Privileged Peripheral Memory Frame MasterID 0 Protection Register"
bitfld.long 0x00 9. " PPCS0_MSTID [9] ,DAP filtering for PPCS[0]" "Disabled,Enabled"
bitfld.long 0x00 7. " [7] ,DMM filtering for PPCS[0]" "Disabled,Enabled"
bitfld.long 0x00 2. " [2] ,DMA Port B filtering for PPCS[0]" "Disabled,Enabled"
bitfld.long 0x00 0. " [0] ,CPU Read/Write filtering for PPCS[0]" "Disabled,Enabled"
group.long 0x5C4++0x03
line.long 0x00 "PPCS1MSTID,Privileged Peripheral Memory Frame MasterID 0 Protection Register"
bitfld.long 0x00 25. " PPCS3_MSTID [9] ,DAP filtering for PPCS[3]" "Disabled,Enabled"
bitfld.long 0x00 23. " [7] ,DMM filtering for PPCS[3]" "Disabled,Enabled"
bitfld.long 0x00 18. " [2] ,DMA Port B filtering for PPCS[3]" "Disabled,Enabled"
bitfld.long 0x00 16. " [0] ,CPU Read/Write filtering for PPCS[3]" "Disabled,Enabled"
textline " "
bitfld.long 0x00 9. " PPCS2_MSTID [9] ,DAP filtering for PPCS[2]" "Disabled,Enabled"
bitfld.long 0x00 7. " [7] ,DMM filtering for PPCS[2]" "Disabled,Enabled"
bitfld.long 0x00 2. " [2] ,DMA Port B filtering for PPCS[2]" "Disabled,Enabled"
bitfld.long 0x00 0. " [0] ,CPU Read/Write filtering for PPCS[2]" "Disabled,Enabled"
group.long 0x5CC++0x03
line.long 0x00 "PPCS3MSTID,Privileged Peripheral Memory Frame MasterID 0 Protection Register"
bitfld.long 0x00 25. " PPCS7_MSTID [9] ,DAP filtering for PPCS[7]" "Disabled,Enabled"
bitfld.long 0x00 23. " [7] ,DMM filtering for PPCS[7]" "Disabled,Enabled"
bitfld.long 0x00 18. " [2] ,DMA Port B filtering for PPCS[7]" "Disabled,Enabled"
bitfld.long 0x00 16. " [0] ,CPU Read/Write filtering for PPCS[7]" "Disabled,Enabled"
group.long 0x5D8++0x03
line.long 0x00 "PPCS0MSTID,Privileged Peripheral Memory Frame MasterID 0 Protection Register"
bitfld.long 0x00 9. " PPCS12_MSTID [9] ,DAP filtering for PPCS[12]" "Disabled,Enabled"
bitfld.long 0x00 7. " [7] ,DMM filtering for PPCS[12]" "Disabled,Enabled"
bitfld.long 0x00 2. " [2] ,DMA Port B filtering for PPCS[12]" "Disabled,Enabled"
bitfld.long 0x00 0. " [0] ,CPU Read/Write filtering for PPCS[12]" "Disabled,Enabled"
tree.end
tree.end
width 0xb
tree.end
tree "PCR 2 (Peripheral Central Resource)"
base ad:0xFCFF1000
width 15.
tree "PCR Power Down Registers"
group.long 0xC0++0x3
line.long 0x0 "PDPWRDWNSET,Debug Frame Powerdown Set Register"
setclrfld.long 0x00 0. 0x00 0. 0x04 0. " PDWRDWN_set/clr ,Debug Power Down" "No power down,Power down"
tree.end
width 15.
tree "MasterID Registers"
group.long 0x200++0x0B
line.long 0x00 "MSTIDWRENA,MasterID Protection Write Enable Register"
bitfld.long 0x00 0.--3. " MSTIDREG_WRENA ,MasterID Register Write Enable" "Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Enabled,Disabled,Disabled,Disabled,Disabled,Disabled"
line.long 0x04 "MSTIDENA,MasterID Enable Register"
bitfld.long 0x04 0.--3. " MSTID_CHK_ENA ,MasterID Check Enable" "Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Enabled,Disabled,Disabled,Disabled,Disabled,Disabled"
line.long 0x08 "MSTIDDIAGCTRL,MasterID Diagnostic Control Register"
bitfld.long 0x08 8.--11. " DIAG_CMP_VALUE ,Diagnostic Compare Value" "Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Enabled,Disabled,Disabled,Disabled,Disabled,Disabled"
bitfld.long 0x08 0.--3. " DIAG_MODE_ENA ,Diagnostic Mode Enable" "Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Enabled,Disabled,Disabled,Disabled,Disabled,Disabled"
tree.end
width 15.
tree "Protection Registers"
tree "Privileged Peripheral Frame MasterID Protection Registers"
group.long 0x410++0x07
line.long 0x00 "PPS2MSTID_L,EMIF Registers (PPS[2]) MasterID Protection Register_L"
bitfld.long 0x00 26. " PPS3_QUAD1_MSTID [10] ,EMAC filtering for Quadrant 1 of PPS[2]" "Disabled,Enabled"
bitfld.long 0x00 25. " [9] ,DAP filtering for Quadrant 1 of PPS[2]" "Disabled,Enabled"
bitfld.long 0x00 23. " [7] ,DMM filtering for Quadrant 1 of PPS[2]" "Disabled,Enabled"
bitfld.long 0x00 18. " [2] ,DMA Port B filtering for Quadrant 1 of PPS[2]" "Disabled,Enabled"
bitfld.long 0x00 16. " [0] ,CPU Read/Write filtering for Quadrant 1 of PPS[2]" "Disabled,Enabled"
textline " "
bitfld.long 0x00 26. " PPS3_QUAD0_MSTID [10] ,EMAC filtering for Quadrant 0 of PPS[2]" "Disabled,Enabled"
bitfld.long 0x00 9. " [9] ,DAP filtering for Quadrant 0 of PPS[2]" "Disabled,Enabled"
bitfld.long 0x00 7. " [7] ,DMM filtering for Quadrant 0 of PPS[2]" "Disabled,Enabled"
bitfld.long 0x00 2. " [2] ,DMA Port B filtering for Quadrant 0 of PPS[2]" "Disabled,Enabled"
bitfld.long 0x00 0. " [0] ,CPU Read/Write filtering for Quadrant 0 of PPS[2]" "Disabled,Enabled"
line.long 0x04 "PPS2MSTID_H,DCC1 (PPS[2]) MasterID Protection Register_H"
bitfld.long 0x04 26. " PPS3_QUAD3_MSTID [10] ,EMAC filtering for Quadrant 3 of PPS[2]" "Disabled,Enabled"
bitfld.long 0x04 25. " [9] ,DAP filtering for Quadrant 3 of PPS[2]" "Disabled,Enabled"
bitfld.long 0x04 23. " [7] ,DMM filtering for Quadrant 3 of PPS[2]" "Disabled,Enabled"
bitfld.long 0x04 18. " [2] ,DMA Port B filtering for Quadrant 3 of PPS[2]" "Disabled,Enabled"
bitfld.long 0x04 16. " [0] ,CPU Read/Write filtering for Quadrant 3 of PPS[2]" "Disabled,Enabled"
textline " "
bitfld.long 0x04 10. " PPS3_QUAD2_MSTID [10] ,EMAC filtering for Quadrant 2 of PPS[2]" "Disabled,Enabled"
bitfld.long 0x04 9. " [9] ,DAP filtering for Quadrant 2 of PPS[2]" "Disabled,Enabled"
bitfld.long 0x04 7. " [7] ,DMM filtering for Quadrant 2 of PPS[2]" "Disabled,Enabled"
bitfld.long 0x04 2. " [2] ,DMA Port B filtering for Quadrant 2 of PPS[2]" "Disabled,Enabled"
bitfld.long 0x04 0. " [0] ,CPU Read/Write filtering for Quadrant 2 of PPS[2]" "Disabled,Enabled"
tree.end
tree "Privileged Peripheral Extended Frame MasterID Protection Registers"
group.long 0x460++0x07
line.long 0x00 "PPSE4MSTID_L,PCR2 Registers (PPSE[4]) MasterID Protection Register_L"
bitfld.long 0x00 26. " PPSE4_QUAD1_MSTID [10] ,EMAC filtering for Quadrant 1 of PPSE[4]" "Disabled,Enabled"
bitfld.long 0x00 25. " [9] ,DAP filtering for Quadrant 1 of PPSE[4]" "Disabled,Enabled"
bitfld.long 0x00 23. " [7] ,DMM filtering for Quadrant 1 of PPSE[4]" "Disabled,Enabled"
bitfld.long 0x00 18. " [2] ,DMA Port B filtering for Quadrant 1 of PPSE[4]" "Disabled,Enabled"
bitfld.long 0x00 16. " [0] ,CPU Read/Write filtering for Quadrant 1 of PPSE[4]" "Disabled,Enabled"
textline " "
bitfld.long 0x00 10. " PPSE4_QUAD0_MSTID [10] ,EMAC filtering for Quadrant 0 of PPSE[4]" "Disabled,Enabled"
bitfld.long 0x00 9. " [9] ,DAP filtering for Quadrant 0 of PPSE[4]" "Disabled,Enabled"
bitfld.long 0x00 7. " [7] ,DMM filtering for Quadrant 0 of PPSE[4]" "Disabled,Enabled"
bitfld.long 0x00 2. " [2] ,DMA Port B filtering for Quadrant 0 of PPSE[4]" "Disabled,Enabled"
bitfld.long 0x00 0. " [0] ,CPU Read/Write filtering for Quadrant 0 of PPSE[4]" "Disabled,Enabled"
line.long 0x04 "PPSE4MSTID_H,PCR2 Registers (PPSE[4]) MasterID Protection Register_H"
bitfld.long 0x04 26. " PPSE4_QUAD3_MSTID [10] ,EMAC filtering for Quadrant 3 of PPSE[4]" "Disabled,Enabled"
bitfld.long 0x04 25. " [9] ,DAP filtering for Quadrant 3 of PPSE[4]" "Disabled,Enabled"
bitfld.long 0x04 23. " [7] ,DMM filtering for Quadrant 3 of PPSE[4]" "Disabled,Enabled"
bitfld.long 0x04 18. " [2] ,DMA Port B filtering for Quadrant 3 of PPSE[4]" "Disabled,Enabled"
bitfld.long 0x04 16. " [0] ,CPU Read/Write filtering for Quadrant 3 of PPSE[4]" "Disabled,Enabled"
textline " "
bitfld.long 0x04 10. " PPSE4_QUAD2_MSTID [10] ,EMAC filtering for Quadrant 2 of PPSE[4]" "Disabled,Enabled"
bitfld.long 0x04 9. " [9] ,DAP filtering for Quadrant 2 of PPSE[4]" "Disabled,Enabled"
bitfld.long 0x04 7. " [7] ,DMM filtering for Quadrant 2 of PPSE[4]" "Disabled,Enabled"
bitfld.long 0x04 2. " [2] ,DMA Port B filtering for Quadrant 2 of PPSE[4]" "Disabled,Enabled"
bitfld.long 0x04 0. " [0] ,CPU Read/Write filtering for Quadrant 2 of PPSE[4]" "Disabled,Enabled"
group.long 0x468++0x07
line.long 0x00 "PPSE5MSTID_L,PCR2 Registers (PPSE[5]) MasterID Protection Register_L"
bitfld.long 0x00 26. " PPSE5_QUAD1_MSTID [10] ,EMAC filtering for Quadrant 1 of PPSE[5]" "Disabled,Enabled"
bitfld.long 0x00 25. " [9] ,DAP filtering for Quadrant 1 of PPSE[5]" "Disabled,Enabled"
bitfld.long 0x00 23. " [7] ,DMM filtering for Quadrant 1 of PPSE[5]" "Disabled,Enabled"
bitfld.long 0x00 18. " [2] ,DMA Port B filtering for Quadrant 1 of PPSE[5]" "Disabled,Enabled"
bitfld.long 0x00 16. " [0] ,CPU Read/Write filtering for Quadrant 1 of PPSE[5]" "Disabled,Enabled"
textline " "
bitfld.long 0x00 10. " PPSE5_QUAD0_MSTID [10] ,EMAC filtering for Quadrant 0 of PPSE[5]" "Disabled,Enabled"
bitfld.long 0x00 9. " [9] ,DAP filtering for Quadrant 0 of PPSE[5]" "Disabled,Enabled"
bitfld.long 0x00 7. " [7] ,DMM filtering for Quadrant 0 of PPSE[5]" "Disabled,Enabled"
bitfld.long 0x00 2. " [2] ,DMA Port B filtering for Quadrant 0 of PPSE[5]" "Disabled,Enabled"
bitfld.long 0x00 0. " [0] ,CPU Read/Write filtering for Quadrant 0 of PPSE[5]" "Disabled,Enabled"
line.long 0x04 "PPSE5MSTID_H,PCR2 Registers (PPSE[5]) MasterID Protection Register_H"
bitfld.long 0x04 26. " PPSE5_QUAD3_MSTID [10] ,EMAC filtering for Quadrant 3 of PPSE[5]" "Disabled,Enabled"
bitfld.long 0x04 25. " [9] ,DAP filtering for Quadrant 3 of PPSE[5]" "Disabled,Enabled"
bitfld.long 0x04 23. " [7] ,DMM filtering for Quadrant 3 of PPSE[5]" "Disabled,Enabled"
bitfld.long 0x04 18. " [2] ,DMA Port B filtering for Quadrant 3 of PPSE[5]" "Disabled,Enabled"
bitfld.long 0x04 16. " [0] ,CPU Read/Write filtering for Quadrant 3 of PPSE[5]" "Disabled,Enabled"
textline " "
bitfld.long 0x04 10. " PPSE5_QUAD2_MSTID [10] ,EMAC filtering for Quadrant 2 of PPSE[5]" "Disabled,Enabled"
bitfld.long 0x04 9. " [9] ,DAP filtering for Quadrant 2 of PPSE[5]" "Disabled,Enabled"
bitfld.long 0x04 7. " [7] ,DMM filtering for Quadrant 2 of PPSE[5]" "Disabled,Enabled"
bitfld.long 0x04 2. " [2] ,DMA Port B filtering for Quadrant 2 of PPSE[5]" "Disabled,Enabled"
bitfld.long 0x04 0. " [0] ,CPU Read/Write filtering for Quadrant 2 of PPSE[5]" "Disabled,Enabled"
group.long 0x470++0x07
line.long 0x00 "PPSE6MSTID_L,NMPU (EMAC) (PPSE[6]) MasterID Protection Register_L"
bitfld.long 0x00 26. " PPSE6_QUAD1_MSTID [10] ,EMAC filtering for Quadrant 1 of PPSE[6]" "Disabled,Enabled"
bitfld.long 0x00 25. " [9] ,DAP filtering for Quadrant 1 of PPSE[6]" "Disabled,Enabled"
bitfld.long 0x00 23. " [7] ,DMM filtering for Quadrant 1 of PPSE[6]" "Disabled,Enabled"
bitfld.long 0x00 18. " [2] ,DMA Port B filtering for Quadrant 1 of PPSE[6]" "Disabled,Enabled"
bitfld.long 0x00 16. " [0] ,CPU Read/Write filtering for Quadrant 1 of PPSE[6]" "Disabled,Enabled"
textline " "
bitfld.long 0x00 10. " PPSE6_QUAD0_MSTID [10] ,EMAC filtering for Quadrant 0 of PPSE[6]" "Disabled,Enabled"
bitfld.long 0x00 9. " [9] ,DAP filtering for Quadrant 0 of PPSE[6]" "Disabled,Enabled"
bitfld.long 0x00 7. " [7] ,DMM filtering for Quadrant 0 of PPSE[6]" "Disabled,Enabled"
bitfld.long 0x00 2. " [2] ,DMA Port B filtering for Quadrant 0 of PPSE[6]" "Disabled,Enabled"
bitfld.long 0x00 0. " [0] ,CPU Read/Write filtering for Quadrant 0 of PPSE[6]" "Disabled,Enabled"
line.long 0x04 "PPSE6MSTID_H,NMPU (EMAC) (PPSE[6]) MasterID Protection Register_H"
bitfld.long 0x04 26. " PPSE6_QUAD3_MSTID [10] ,EMAC filtering for Quadrant 3 of PPSE[6]" "Disabled,Enabled"
bitfld.long 0x04 25. " [9] ,DAP filtering for Quadrant 3 of PPSE[6]" "Disabled,Enabled"
bitfld.long 0x04 23. " [7] ,DMM filtering for Quadrant 3 of PPSE[6]" "Disabled,Enabled"
bitfld.long 0x04 18. " [2] ,DMA Port B filtering for Quadrant 3 of PPSE[6]" "Disabled,Enabled"
bitfld.long 0x04 16. " [0] ,CPU Read/Write filtering for Quadrant 3 of PPSE[6]" "Disabled,Enabled"
textline " "
bitfld.long 0x04 10. " PPSE6_QUAD2_MSTID [10] ,EMAC filtering for Quadrant 2 of PPSE[6]" "Disabled,Enabled"
bitfld.long 0x04 9. " [9] ,DAP filtering for Quadrant 2 of PPSE[6]" "Disabled,Enabled"
bitfld.long 0x04 7. " [7] ,DMM filtering for Quadrant 2 of PPSE[6]" "Disabled,Enabled"
bitfld.long 0x04 2. " [2] ,DMA Port B filtering for Quadrant 2 of PPSE[6]" "Disabled,Enabled"
bitfld.long 0x04 0. " [0] ,CPU Read/Write filtering for Quadrant 2 of PPSE[6]" "Disabled,Enabled"
tree.end
tree "Peripheral Power-Down Set Registers"
group.long 0x36C++0x07
line.long 0x00 "PS25MSTID_L,eQEP2/eQEP1/eCAP6 Peripheral Frame PS[25] MasterID Protection Register_L"
bitfld.long 0x00 26. " PS25_QUAD1_MSTID [10] ,EMAC filtering for Quadrant 1 of PS[25]" "Disabled,Enabled"
bitfld.long 0x00 25. " [9] ,DAP filtering for Quadrant 1 of PS[25]" "Disabled,Enabled"
bitfld.long 0x00 23. " [7] ,DMM filtering for Quadrant 1 of PS[25]" "Disabled,Enabled"
bitfld.long 0x00 18. " [2] ,DMA Port B filtering for Quadrant 1 of PS[25]" "Disabled,Enabled"
bitfld.long 0x00 16. " [0] ,CPU Read/Write filtering for Quadrant 1 of PS[25]" "Disabled,Enabled"
textline " "
bitfld.long 0x00 10. " PS25_QUAD0_MSTID [10] ,EMAC filtering for Quadrant 0 of PS[25]" "Disabled,Enabled"
bitfld.long 0x00 9. " [9] ,DAP filtering for Quadrant 0 of PS[25]" "Disabled,Enabled"
bitfld.long 0x00 7. " [7] ,DMM filtering for Quadrant 0 of PS[25]" "Disabled,Enabled"
bitfld.long 0x00 2. " [2] ,DMA Port B filtering for Quadrant 0 of PS[25]" "Disabled,Enabled"
bitfld.long 0x00 0. " [0] ,CPU Read/Write filtering for Quadrant 0 of PS[25]" "Disabled,Enabled"
line.long 0x04 "PS25MSTID_H,eQEP2/eQEP1/eCAP6 Peripheral Frame PS[25] MasterID Protection Register_H"
bitfld.long 0x04 26. " PS25_QUAD3_MSTID [10] ,EMAC filtering for Quadrant 3 of PS[25]" "Disabled,Enabled"
bitfld.long 0x04 25. " [9] ,DAP filtering for Quadrant 3 of PS[25]" "Disabled,Enabled"
bitfld.long 0x04 23. " [7] ,DMM filtering for Quadrant 3 of PS[25]" "Disabled,Enabled"
bitfld.long 0x04 18. " [2] ,DMA Port B filtering for Quadrant 3 of PS[25]" "Disabled,Enabled"
bitfld.long 0x04 16. " [0] ,CPU Read/Write filtering for Quadrant 3 of PS[25]" "Disabled,Enabled"
textline " "
bitfld.long 0x04 10. " PS25_QUAD2_MSTID [10] ,EMAC filtering for Quadrant 2 of PS[25]" "Disabled,Enabled"
bitfld.long 0x04 9. " [9] ,DAP filtering for Quadrant 2 of PS[25]" "Disabled,Enabled"
bitfld.long 0x04 7. " [7] ,DMM filtering for Quadrant 2 of PS[25]" "Disabled,Enabled"
bitfld.long 0x04 2. " [2] ,DMA Port B filtering for Quadrant 2 of PS[25]" "Disabled,Enabled"
bitfld.long 0x04 0. " [0] ,CPU Read/Write filtering for Quadrant 2 of PS[25]" "Disabled,Enabled"
group.long 0x374++0x07
line.long 0x00 "PS26MSTID_L,eCAP5/eCAP4/eCAP3/eCAP2 Peripheral Frame PS[26] MasterID Protection Register_L"
bitfld.long 0x00 26. " PS26_QUAD1_MSTID [10] ,EMAC filtering for Quadrant 1 of PS[26]" "Disabled,Enabled"
bitfld.long 0x00 25. " [9] ,DAP filtering for Quadrant 1 of PS[26]" "Disabled,Enabled"
bitfld.long 0x00 23. " [7] ,DMM filtering for Quadrant 1 of PS[26]" "Disabled,Enabled"
bitfld.long 0x00 18. " [2] ,DMA Port B filtering for Quadrant 1 of PS[26]" "Disabled,Enabled"
bitfld.long 0x00 16. " [0] ,CPU Read/Write filtering for Quadrant 1 of PS[26]" "Disabled,Enabled"
textline " "
bitfld.long 0x00 10. " PS26_QUAD0_MSTID [10] ,EMAC filtering for Quadrant 0 of PS[26]" "Disabled,Enabled"
bitfld.long 0x00 9. " [9] ,DAP filtering for Quadrant 0 of PS[26]" "Disabled,Enabled"
bitfld.long 0x00 7. " [7] ,DMM filtering for Quadrant 0 of PS[26]" "Disabled,Enabled"
bitfld.long 0x00 2. " [2] ,DMA Port B filtering for Quadrant 0 of PS[26]" "Disabled,Enabled"
bitfld.long 0x00 0. " [0] ,CPU Read/Write filtering for Quadrant 0 of PS[26]" "Disabled,Enabled"
line.long 0x04 "PS26MSTID_H,eCAP5/eCAP4/eCAP3/eCAP2 Peripheral Frame PS[26] MasterID Protection Register_H"
bitfld.long 0x04 26. " PS26_QUAD3_MSTID [10] ,EMAC filtering for Quadrant 3 of PS[26]" "Disabled,Enabled"
bitfld.long 0x04 25. " [9] ,DAP filtering for Quadrant 3 of PS[26]" "Disabled,Enabled"
bitfld.long 0x04 23. " [7] ,DMM filtering for Quadrant 3 of PS[26]" "Disabled,Enabled"
bitfld.long 0x04 18. " [2] ,DMA Port B filtering for Quadrant 3 of PS[26]" "Disabled,Enabled"
bitfld.long 0x04 16. " [0] ,CPU Read/Write filtering for Quadrant 3 of PS[26]" "Disabled,Enabled"
textline " "
bitfld.long 0x04 10. " PS26_QUAD2_MSTID [10] ,EMAC filtering for Quadrant 2 of PS[26]" "Disabled,Enabled"
bitfld.long 0x04 9. " [9] ,DAP filtering for Quadrant 2 of PS[26]" "Disabled,Enabled"
bitfld.long 0x04 7. " [7] ,DMM filtering for Quadrant 2 of PS[26]" "Disabled,Enabled"
bitfld.long 0x04 2. " [2] ,DMA Port B filtering for Quadrant 2 of PS[26]" "Disabled,Enabled"
bitfld.long 0x04 0. " [0] ,CPU Read/Write filtering for Quadrant 2 of PS[26]" "Disabled,Enabled"
group.long 0x37C++0x07
line.long 0x00 "PS27MSTID_L,eCAP1/ePWM7/ePWM6/ePWM5 Peripheral Frame PS[27] MasterID Protection Register_L"
bitfld.long 0x00 26. " PS27_QUAD1_MSTID [10] ,EMAC filtering for Quadrant 1 of PS[27]" "Disabled,Enabled"
bitfld.long 0x00 25. " [9] ,DAP filtering for Quadrant 1 of PS[27]" "Disabled,Enabled"
bitfld.long 0x00 23. " [7] ,DMM filtering for Quadrant 1 of PS[27]" "Disabled,Enabled"
bitfld.long 0x00 18. " [2] ,DMA Port B filtering for Quadrant 1 of PS[27]" "Disabled,Enabled"
bitfld.long 0x00 16. " [0] ,CPU Read/Write filtering for Quadrant 1 of PS[27]" "Disabled,Enabled"
textline " "
bitfld.long 0x00 10. " PS27_QUAD0_MSTID [10] ,EMAC filtering for Quadrant 0 of PS[27]" "Disabled,Enabled"
bitfld.long 0x00 9. " [9] ,DAP filtering for Quadrant 0 of PS[27]" "Disabled,Enabled"
bitfld.long 0x00 7. " [7] ,DMM filtering for Quadrant 0 of PS[27]" "Disabled,Enabled"
bitfld.long 0x00 2. " [2] ,DMA Port B filtering for Quadrant 0 of PS[27]" "Disabled,Enabled"
bitfld.long 0x00 0. " [0] ,CPU Read/Write filtering for Quadrant 0 of PS[27]" "Disabled,Enabled"
line.long 0x04 "PS27MSTID_H,eCAP1/ePWM7/ePWM6/ePWM5 Peripheral Frame PS[27] MasterID Protection Register_H"
bitfld.long 0x04 26. " PS27_QUAD3_MSTID [10] ,EMAC filtering for Quadrant 3 of PS[27]" "Disabled,Enabled"
bitfld.long 0x04 25. " [9] ,DAP filtering for Quadrant 3 of PS[27]" "Disabled,Enabled"
bitfld.long 0x04 23. " [7] ,DMM filtering for Quadrant 3 of PS[27]" "Disabled,Enabled"
bitfld.long 0x04 18. " [2] ,DMA Port B filtering for Quadrant 3 of PS[27]" "Disabled,Enabled"
bitfld.long 0x04 16. " [0] ,CPU Read/Write filtering for Quadrant 3 of PS[27]" "Disabled,Enabled"
textline " "
bitfld.long 0x04 10. " PS27_QUAD2_MSTID [10] ,EMAC filtering for Quadrant 2 of PS[27]" "Disabled,Enabled"
bitfld.long 0x04 9. " [9] ,DAP filtering for Quadrant 2 of PS[27]" "Disabled,Enabled"
bitfld.long 0x04 7. " [7] ,DMM filtering for Quadrant 2 of PS[27]" "Disabled,Enabled"
bitfld.long 0x04 2. " [2] ,DMA Port B filtering for Quadrant 2 of PS[27]" "Disabled,Enabled"
bitfld.long 0x04 0. " [0] ,CPU Read/Write filtering for Quadrant 2 of PS[27]" "Disabled,Enabled"
group.long 0x384++0x07
line.long 0x00 "PS28MSTID_L,ePWM4/ePWM3/ePWM2/ePWM1 Peripheral Frame PS[28] MasterID Protection Register_L"
bitfld.long 0x00 26. " PS28_QUAD1_MSTID [10] ,EMAC filtering for Quadrant 1 of PS[28]" "Disabled,Enabled"
bitfld.long 0x00 25. " [9] ,DAP filtering for Quadrant 1 of PS[28]" "Disabled,Enabled"
bitfld.long 0x00 23. " [7] ,DMM filtering for Quadrant 1 of PS[28]" "Disabled,Enabled"
bitfld.long 0x00 18. " [2] ,DMA Port B filtering for Quadrant 1 of PS[28]" "Disabled,Enabled"
bitfld.long 0x00 16. " [0] ,CPU Read/Write filtering for Quadrant 1 of PS[28]" "Disabled,Enabled"
textline " "
bitfld.long 0x00 10. " PS28_QUAD0_MSTID [10] ,EMAC filtering for Quadrant 0 of PS[28]" "Disabled,Enabled"
bitfld.long 0x00 9. " [9] ,DAP filtering for Quadrant 0 of PS[28]" "Disabled,Enabled"
bitfld.long 0x00 7. " [7] ,DMM filtering for Quadrant 0 of PS[28]" "Disabled,Enabled"
bitfld.long 0x00 2. " [2] ,DMA Port B filtering for Quadrant 0 of PS[28]" "Disabled,Enabled"
bitfld.long 0x00 0. " [0] ,CPU Read/Write filtering for Quadrant 0 of PS[28]" "Disabled,Enabled"
line.long 0x04 "PS28MSTID_H,ePWM4/ePWM3/ePWM2/ePWM1 Peripheral Frame PS[28] MasterID Protection Register_H"
bitfld.long 0x04 26. " PS28_QUAD3_MSTID [10] ,EMAC filtering for Quadrant 3 of PS[28]" "Disabled,Enabled"
bitfld.long 0x04 25. " [9] ,DAP filtering for Quadrant 3 of PS[28]" "Disabled,Enabled"
bitfld.long 0x04 23. " [7] ,DMM filtering for Quadrant 3 of PS[28]" "Disabled,Enabled"
bitfld.long 0x04 18. " [2] ,DMA Port B filtering for Quadrant 3 of PS[28]" "Disabled,Enabled"
bitfld.long 0x04 16. " [0] ,CPU Read/Write filtering for Quadrant 3 of PS[28]" "Disabled,Enabled"
textline " "
bitfld.long 0x04 10. " PS28_QUAD2_MSTID [10] ,EMAC filtering for Quadrant 2 of PS[28]" "Disabled,Enabled"
bitfld.long 0x04 9. " [9] ,DAP filtering for Quadrant 2 of PS[28]" "Disabled,Enabled"
bitfld.long 0x04 7. " [7] ,DMM filtering for Quadrant 2 of PS[28]" "Disabled,Enabled"
bitfld.long 0x04 2. " [2] ,DMA Port B filtering for Quadrant 2 of PS[28]" "Disabled,Enabled"
bitfld.long 0x04 0. " [0] ,CPU Read/Write filtering for Quadrant 2 of PS[28]" "Disabled,Enabled"
group.long 0x38C++0x07
line.long 0x00 "PS29MSTID_L,Ethernet MDIO/SPGMACSS Wrapper Interface Peripheral Frame PS[29] MasterID Protection Register_L"
bitfld.long 0x00 26. " PS29_QUAD1_MSTID [10] ,EMAC filtering for Quadrant 1 of PS[29]" "Disabled,Enabled"
bitfld.long 0x00 25. " [9] ,DAP filtering for Quadrant 1 of PS[29]" "Disabled,Enabled"
bitfld.long 0x00 23. " [7] ,DMM filtering for Quadrant 1 of PS[29]" "Disabled,Enabled"
bitfld.long 0x00 18. " [2] ,DMA Port B filtering for Quadrant 1 of PS[29]" "Disabled,Enabled"
bitfld.long 0x00 16. " [0] ,CPU Read/Write filtering for Quadrant 1 of PS[29]" "Disabled,Enabled"
textline " "
bitfld.long 0x00 10. " PS29_QUAD0_MSTID [10] ,EMAC filtering for Quadrant 0 of PS[29]" "Disabled,Enabled"
bitfld.long 0x00 9. " [9] ,DAP filtering for Quadrant 0 of PS[29]" "Disabled,Enabled"
bitfld.long 0x00 7. " [7] ,DMM filtering for Quadrant 0 of PS[29]" "Disabled,Enabled"
bitfld.long 0x00 2. " [2] ,DMA Port B filtering for Quadrant 0 of PS[29]" "Disabled,Enabled"
bitfld.long 0x00 0. " [0] ,CPU Read/Write filtering for Quadrant 0 of PS[29]" "Disabled,Enabled"
line.long 0x04 "PS29MSTID_H,Ethernet MDIO/SPGMACSS Wrapper Interface Peripheral Frame PS[29] MasterID Protection Register_H"
bitfld.long 0x04 26. " PS29_QUAD3_MSTID [10] ,EMAC filtering for Quadrant 3 of PS[29]" "Disabled,Enabled"
bitfld.long 0x04 25. " [9] ,DAP filtering for Quadrant 3 of PS[29]" "Disabled,Enabled"
bitfld.long 0x04 23. " [7] ,DMM filtering for Quadrant 3 of PS[29]" "Disabled,Enabled"
bitfld.long 0x04 18. " [2] ,DMA Port B filtering for Quadrant 3 of PS[29]" "Disabled,Enabled"
bitfld.long 0x04 16. " [0] ,CPU Read/Write filtering for Quadrant 3 of PS[29]" "Disabled,Enabled"
textline " "
bitfld.long 0x04 10. " PS29_QUAD2_MSTID [10] ,EMAC filtering for Quadrant 2 of PS[29]" "Disabled,Enabled"
bitfld.long 0x04 9. " [9] ,DAP filtering for Quadrant 2 of PS[29]" "Disabled,Enabled"
bitfld.long 0x04 7. " [7] ,DMM filtering for Quadrant 2 of PS[29]" "Disabled,Enabled"
bitfld.long 0x04 2. " [2] ,DMA Port B filtering for Quadrant 2 of PS[29]" "Disabled,Enabled"
bitfld.long 0x04 0. " [0] ,CPU Read/Write filtering for Quadrant 2 of PS[29]" "Disabled,Enabled"
group.long 0x394++0x07
line.long 0x00 "PS30MSTID_L,CPGMAC Slave Peripheral Frame PS[30] MasterID Protection Register_L"
bitfld.long 0x00 26. " PS30_QUAD1_MSTID [10] ,EMAC filtering for Quadrant 1 of PS[30]" "Disabled,Enabled"
bitfld.long 0x00 25. " [9] ,DAP filtering for Quadrant 1 of PS[30]" "Disabled,Enabled"
bitfld.long 0x00 23. " [7] ,DMM filtering for Quadrant 1 of PS[30]" "Disabled,Enabled"
bitfld.long 0x00 18. " [2] ,DMA Port B filtering for Quadrant 1 of PS[30]" "Disabled,Enabled"
bitfld.long 0x00 16. " [0] ,CPU Read/Write filtering for Quadrant 1 of PS[30]" "Disabled,Enabled"
textline " "
bitfld.long 0x00 10. " PS30_QUAD0_MSTID [10] ,EMAC filtering for Quadrant 0 of PS[30]" "Disabled,Enabled"
bitfld.long 0x00 9. " [9] ,DAP filtering for Quadrant 0 of PS[30]" "Disabled,Enabled"
bitfld.long 0x00 7. " [7] ,DMM filtering for Quadrant 0 of PS[30]" "Disabled,Enabled"
bitfld.long 0x00 2. " [2] ,DMA Port B filtering for Quadrant 0 of PS[30]" "Disabled,Enabled"
bitfld.long 0x00 0. " [0] ,CPU Read/Write filtering for Quadrant 0 of PS[30]" "Disabled,Enabled"
line.long 0x04 "PS30MSTID_H,CPGMAC Slave Peripheral Frame PS[30] MasterID Protection Register_H"
bitfld.long 0x04 26. " PS30_QUAD3_MSTID [10] ,EMAC filtering for Quadrant 3 of PS[30]" "Disabled,Enabled"
bitfld.long 0x04 25. " [9] ,DAP filtering for Quadrant 3 of PS[30]" "Disabled,Enabled"
bitfld.long 0x04 23. " [7] ,DMM filtering for Quadrant 3 of PS[30]" "Disabled,Enabled"
bitfld.long 0x04 18. " [2] ,DMA Port B filtering for Quadrant 3 of PS[30]" "Disabled,Enabled"
bitfld.long 0x04 16. " [0] ,CPU Read/Write filtering for Quadrant 3 of PS[30]" "Disabled,Enabled"
textline " "
bitfld.long 0x04 10. " PS30_QUAD2_MSTID [10] ,EMAC filtering for Quadrant 2 of PS[30]" "Disabled,Enabled"
bitfld.long 0x04 9. " [9] ,DAP filtering for Quadrant 2 of PS[30]" "Disabled,Enabled"
bitfld.long 0x04 7. " [7] ,DMM filtering for Quadrant 2 of PS[30]" "Disabled,Enabled"
bitfld.long 0x04 2. " [2] ,DMA Port B filtering for Quadrant 2 of PS[30]" "Disabled,Enabled"
bitfld.long 0x04 0. " [0] ,CPU Read/Write filtering for Quadrant 2 of PS[30]" "Disabled,Enabled"
group.long 0x39C++0x07
line.long 0x00 "PS31MSTID_L,CPGMAC Slave Peripheral Frame PS[31] MasterID Protection Register_L"
bitfld.long 0x00 26. " PS31_QUAD1_MSTID [10] ,EMAC filtering for Quadrant 1 of PS[31]" "Disabled,Enabled"
bitfld.long 0x00 25. " [9] ,DAP filtering for Quadrant 1 of PS[31]" "Disabled,Enabled"
bitfld.long 0x00 23. " [7] ,DMM filtering for Quadrant 1 of PS[31]" "Disabled,Enabled"
bitfld.long 0x00 18. " [2] ,DMA Port B filtering for Quadrant 1 of PS[31]" "Disabled,Enabled"
bitfld.long 0x00 16. " [0] ,CPU Read/Write filtering for Quadrant 1 of PS[31]" "Disabled,Enabled"
textline " "
bitfld.long 0x00 10. " PS31_QUAD0_MSTID [10] ,EMAC filtering for Quadrant 0 of PS[31]" "Disabled,Enabled"
bitfld.long 0x00 9. " [9] ,DAP filtering for Quadrant 0 of PS[31]" "Disabled,Enabled"
bitfld.long 0x00 7. " [7] ,DMM filtering for Quadrant 0 of PS[31]" "Disabled,Enabled"
bitfld.long 0x00 2. " [2] ,DMA Port B filtering for Quadrant 0 of PS[31]" "Disabled,Enabled"
bitfld.long 0x00 0. " [0] ,CPU Read/Write filtering for Quadrant 0 of PS[31]" "Disabled,Enabled"
line.long 0x04 "PS31MSTID_H,CPGMAC Slave Peripheral Frame PS[31] MasterID Protection Register_H"
bitfld.long 0x04 26. " PS31_QUAD3_MSTID [10] ,EMAC filtering for Quadrant 3 of PS[31]" "Disabled,Enabled"
bitfld.long 0x04 25. " [9] ,DAP filtering for Quadrant 3 of PS[31]" "Disabled,Enabled"
bitfld.long 0x04 23. " [7] ,DMM filtering for Quadrant 3 of PS[31]" "Disabled,Enabled"
bitfld.long 0x04 18. " [2] ,DMA Port B filtering for Quadrant 3 of PS[31]" "Disabled,Enabled"
bitfld.long 0x04 16. " [0] ,CPU Read/Write filtering for Quadrant 3 of PS[31]" "Disabled,Enabled"
textline " "
bitfld.long 0x04 10. " PS31_QUAD2_MSTID [10] ,EMAC filtering for Quadrant 2 of PS[31]" "Disabled,Enabled"
bitfld.long 0x04 9. " [9] ,DAP filtering for Quadrant 2 of PS[31]" "Disabled,Enabled"
bitfld.long 0x04 7. " [7] ,DMM filtering for Quadrant 2 of PS[31]" "Disabled,Enabled"
bitfld.long 0x04 2. " [2] ,DMA Port B filtering for Quadrant 2 of PS[31]" "Disabled,Enabled"
bitfld.long 0x04 0. " [0] ,CPU Read/Write filtering for Quadrant 2 of PS[31]" "Disabled,Enabled"
tree.end
width 13.
tree "Privileged Peripheral Memory Frame MasterID Protection Registers"
group.long 0xA40++0x03
line.long 0x00 "PPCS41MSTID,CPPI Memory Slave Privileged Peripheral Memory Frame MasterID 41 Protection Register"
bitfld.long 0x00 10. " PPCS41_MSTID [10] ,EMCA filtering for PPCS[41]" "Disabled,Enabled"
bitfld.long 0x00 9. " [9] ,DAP filtering for PPCS[41]" "Disabled,Enabled"
bitfld.long 0x00 7. " [7] ,DMM filtering for PPCS[41]" "Disabled,Enabled"
bitfld.long 0x00 2. " [2] ,DMA Port B filtering for PPCS[41]" "Disabled,Enabled"
bitfld.long 0x00 0. " [0] ,CPU Read/Write filtering for PPCS[41]" "Disabled,Enabled"
tree.end
tree.end
width 0xb
tree.end
tree "PCR 3 (Peripheral Central Resource)"
base ad:0xFFF78000
width 15.
tree "PCR Power Down Registers"
group.long 0xC0++0x3
line.long 0x0 "PDPWRDWNSET,Debug Frame Powerdown Set Register"
setclrfld.long 0x00 0. 0x00 0. 0x04 0. " PDWRDWN_set/clr ,Debug Power Down" "No power down,Power down"
tree.end
tree "MasterID Registers"
group.long 0x200++0x0B
line.long 0x00 "MSTIDWRENA,MasterID Protection Write Enable Register"
bitfld.long 0x00 0.--3. " MSTIDREG_WRENA ,MasterID Register Write Enable" "Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Enabled,Disabled,Disabled,Disabled,Disabled,Disabled"
line.long 0x04 "MSTIDENA,MasterID Enable Register"
bitfld.long 0x04 0.--3. " MSTID_CHK_ENA ,MasterID Check Enable" "Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Enabled,Disabled,Disabled,Disabled,Disabled,Disabled"
line.long 0x08 "MSTIDDIAGCTRL,MasterID Diagnostic Control Register"
bitfld.long 0x08 8.--11. " DIAG_CMP_VALUE ,Diagnostic Compare Value" "Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Enabled,Disabled,Disabled,Disabled,Disabled,Disabled"
bitfld.long 0x08 0.--3. " DIAG_MODE_ENA ,Diagnostic Mode Enable" "Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Enabled,Disabled,Disabled,Disabled,Disabled,Disabled"
tree.end
tree "Protection Registers"
width 15.
tree "PCR Memory Power Down Registers"
group.long 0x60++0x3
line.long 0x0 "PCSPWRDWNSET0,Peripheral Memory Power-Down Set Register 0"
setclrfld.long 0x00 31. 0x00 31. 0x10 31. " PCS_PWRDWN_set/clr [31] ,Peripheral Memory Power Down Enable 31" "No power down,Power down"
setclrfld.long 0x00 30. 0x00 30. 0x10 30. " [30] ,Peripheral Memory Power Down Enable 30" "No power down,Power down"
setclrfld.long 0x00 29. 0x00 29. 0x10 29. " [29] ,Peripheral Memory Power Down Enable 29" "No power down,Power down"
setclrfld.long 0x00 15. 0x00 15. 0x10 15. " [15] ,Peripheral Memory Power Down Enable 15" "No power down,Power down"
textline " "
setclrfld.long 0x00 14. 0x00 14. 0x10 14. " [14] ,Peripheral Memory Power Down Enable 14" "No power down,Power down"
setclrfld.long 0x00 13. 0x00 13. 0x10 13. " [13] ,Peripheral Memory Power Down Enable 13" "No power down,Power down"
setclrfld.long 0x00 12. 0x00 12. 0x10 12. " [12] ,Peripheral Memory Power Down Enable 12" "No power down,Power down"
setclrfld.long 0x00 7. 0x00 7. 0x10 7. " [7] ,Peripheral Memory Power Down Enable 7" "No power down,Power down"
textline " "
setclrfld.long 0x00 6. 0x00 6. 0x10 6. " [6] ,Peripheral Memory Power Down Enable 6" "No power down,Power down"
setclrfld.long 0x00 5. 0x00 5. 0x10 5. " [5] ,Peripheral Memory Power Down Enable 5" "No power down,Power down"
setclrfld.long 0x00 4. 0x00 4. 0x10 4. " [4] ,Peripheral Memory Power Down Enable 4" "No power down,Power down"
setclrfld.long 0x00 3. 0x00 3. 0x10 3. " [3] ,Peripheral Memory Power Down Enable 3" "No power down,Power down"
group.long 0x64++0x3
line.long 0x0 "PCSPWRDWNSET1,Peripheral Memory Power-Down Set Register 1"
setclrfld.long 0x00 8. 0x00 8. 0x10 8. " PCS_PWRDWN_set/clr [40] ,Peripheral Memory Power Down Enable 40" "No power down,Power down"
setclrfld.long 0x00 7. 0x00 7. 0x10 7. " [39] ,Peripheral Memory Power Down Enable 39" "No power down,Power down"
setclrfld.long 0x00 6. 0x00 6. 0x10 6. " [38] ,Peripheral Memory Power Down Enable 38" "No power down,Power down"
setclrfld.long 0x00 3. 0x00 3. 0x10 3. " [35] ,Peripheral Memory Power Down Enable 35" "No power down,Power down"
textline " "
setclrfld.long 0x00 2. 0x00 2. 0x10 2. " [34] ,Peripheral Memory Power Down Enable 34" "No power down,Power down"
tree.end
width 15.
tree "Peripheral Power-Down Set Registers"
group.long 0x300++0x07
line.long 0x00 "PS0MSTID_L,MibSPI5 Peripheral Frame PS[0] MasterID Protection Register_L"
bitfld.long 0x00 26. " PS0_QUAD1_MSTID [10] ,EMAC filtering for Quadrant 1 of PS[0]" "Disabled,Enabled"
bitfld.long 0x00 25. " [9] ,DAP filtering for Quadrant 1 of PS[0]" "Disabled,Enabled"
bitfld.long 0x00 23. " [7] ,DMM filtering for Quadrant 1 of PS[0]" "Disabled,Enabled"
bitfld.long 0x00 18. " [2] ,DMA Port B filtering for Quadrant 1 of PS[0]" "Disabled,Enabled"
bitfld.long 0x00 16. " [0] ,CPU Read/Write filtering for Quadrant 1 of PS[0]" "Disabled,Enabled"
textline " "
bitfld.long 0x00 10. " PS0_QUAD0_MSTID [10] ,EMAC filtering for Quadrant 0 of PS[0]" "Disabled,Enabled"
bitfld.long 0x00 9. " [9] ,DAP filtering for Quadrant 0 of PS[0]" "Disabled,Enabled"
bitfld.long 0x00 7. " [7] ,DMM filtering for Quadrant 0 of PS[0]" "Disabled,Enabled"
bitfld.long 0x00 2. " [2] ,DMA Port B filtering for Quadrant 0 of PS[0]" "Disabled,Enabled"
bitfld.long 0x00 0. " [0] ,CPU Read/Write filtering for Quadrant 0 of PS[0]" "Disabled,Enabled"
line.long 0x04 "PS0MSTID_H,MibSPI5 Peripheral Frame PS[0] MasterID Protection Register_H"
bitfld.long 0x04 26. " PS0_QUAD3_MSTID [10] ,EMAC filtering for Quadrant 3 of PS[0]" "Disabled,Enabled"
bitfld.long 0x04 25. " [9] ,DAP filtering for Quadrant 3 of PS[0]" "Disabled,Enabled"
bitfld.long 0x04 23. " [7] ,DMM filtering for Quadrant 3 of PS[0]" "Disabled,Enabled"
bitfld.long 0x04 18. " [2] ,DMA Port B filtering for Quadrant 3 of PS[0]" "Disabled,Enabled"
bitfld.long 0x04 16. " [0] ,CPU Read/Write filtering for Quadrant 3 of PS[0]" "Disabled,Enabled"
textline " "
bitfld.long 0x04 10. " PS0_QUAD2_MSTID [10] ,EMAC filtering for Quadrant 2 of PS[0]" "Disabled,Enabled"
bitfld.long 0x04 9. " [9] ,DAP filtering for Quadrant 2 of PS[0]" "Disabled,Enabled"
bitfld.long 0x04 7. " [7] ,DMM filtering for Quadrant 2 of PS[0]" "Disabled,Enabled"
bitfld.long 0x04 2. " [2] ,DMA Port B filtering for Quadrant 2 of PS[0]" "Disabled,Enabled"
bitfld.long 0x04 0. " [0] ,CPU Read/Write filtering for Quadrant 2 of PS[0]" "Disabled,Enabled"
group.long 0x308++0x07
line.long 0x00 "PS1MSTID_L,MibSPI4/MibSPI3 Peripheral Frame PS[1] MasterID Protection Register_L"
bitfld.long 0x00 26. " PS1_QUAD1_MSTID [10] ,EMAC filtering for Quadrant 1 of PS[1]" "Disabled,Enabled"
bitfld.long 0x00 25. " [9] ,DAP filtering for Quadrant 1 of PS[1]" "Disabled,Enabled"
bitfld.long 0x00 23. " [7] ,DMM filtering for Quadrant 1 of PS[1]" "Disabled,Enabled"
bitfld.long 0x00 18. " [2] ,DMA Port B filtering for Quadrant 1 of PS[1]" "Disabled,Enabled"
bitfld.long 0x00 16. " [0] ,CPU Read/Write filtering for Quadrant 1 of PS[1]" "Disabled,Enabled"
textline " "
bitfld.long 0x00 10. " PS1_QUAD0_MSTID [10] ,EMAC filtering for Quadrant 0 of PS[1]" "Disabled,Enabled"
bitfld.long 0x00 9. " [9] ,DAP filtering for Quadrant 0 of PS[1]" "Disabled,Enabled"
bitfld.long 0x00 7. " [7] ,DMM filtering for Quadrant 0 of PS[1]" "Disabled,Enabled"
bitfld.long 0x00 2. " [2] ,DMA Port B filtering for Quadrant 0 of PS[1]" "Disabled,Enabled"
bitfld.long 0x00 0. " [0] ,CPU Read/Write filtering for Quadrant 0 of PS[1]" "Disabled,Enabled"
line.long 0x04 "PS1MSTID_H,MibSPI4 / MibSPI3 Peripheral Frame PS[1] MasterID Protection Register_H"
bitfld.long 0x04 26. " PS1_QUAD3_MSTID [10] ,EMAC filtering for Quadrant 3 of PS[1]" "Disabled,Enabled"
bitfld.long 0x04 25. " [9] ,DAP filtering for Quadrant 3 of PS[1]" "Disabled,Enabled"
bitfld.long 0x04 23. " [7] ,DMM filtering for Quadrant 3 of PS[1]" "Disabled,Enabled"
bitfld.long 0x04 18. " [2] ,DMA Port B filtering for Quadrant 3 of PS[1]" "Disabled,Enabled"
bitfld.long 0x04 16. " [0] ,CPU Read/Write filtering for Quadrant 3 of PS[1]" "Disabled,Enabled"
textline " "
bitfld.long 0x04 10. " PS1_QUAD2_MSTID [10] ,EMAC filtering for Quadrant 2 of PS[1]" "Disabled,Enabled"
bitfld.long 0x04 9. " [9] ,DAP filtering for Quadrant 2 of PS[1]" "Disabled,Enabled"
bitfld.long 0x04 7. " [7] ,DMM filtering for Quadrant 2 of PS[1]" "Disabled,Enabled"
bitfld.long 0x04 2. " [2] ,DMA Port B filtering for Quadrant 2 of PS[1]" "Disabled,Enabled"
bitfld.long 0x04 0. " [0] ,CPU Read/Write filtering for Quadrant 2 of PS[1]" "Disabled,Enabled"
group.long 0x310++0x07
line.long 0x00 "PS2MSTID_L,MibSPI2/MibSPI1 Peripheral Frame PS[2] MasterID Protection Register_L"
bitfld.long 0x00 26. " PS2_QUAD1_MSTID [10] ,EMAC filtering for Quadrant 1 of PS[2]" "Disabled,Enabled"
bitfld.long 0x00 25. " [9] ,DAP filtering for Quadrant 1 of PS[2]" "Disabled,Enabled"
bitfld.long 0x00 23. " [7] ,DMM filtering for Quadrant 1 of PS[2]" "Disabled,Enabled"
bitfld.long 0x00 18. " [2] ,DMA Port B filtering for Quadrant 1 of PS[2]" "Disabled,Enabled"
bitfld.long 0x00 16. " [0] ,CPU Read/Write filtering for Quadrant 1 of PS[2]" "Disabled,Enabled"
textline " "
bitfld.long 0x00 10. " PS2_QUAD0_MSTID [10] ,EMAC filtering for Quadrant 0 of PS[2]" "Disabled,Enabled"
bitfld.long 0x00 9. " [9] ,DAP filtering for Quadrant 0 of PS[2]" "Disabled,Enabled"
bitfld.long 0x00 7. " [7] ,DMM filtering for Quadrant 0 of PS[2]" "Disabled,Enabled"
bitfld.long 0x00 2. " [2] ,DMA Port B filtering for Quadrant 0 of PS[2]" "Disabled,Enabled"
bitfld.long 0x00 0. " [0] ,CPU Read/Write filtering for Quadrant 0 of PS[2]" "Disabled,Enabled"
line.long 0x04 "PS2MSTID_H,MibSPI2 / MibSPI1 Peripheral Frame PS[2] MasterID Protection Register_H"
bitfld.long 0x04 26. " PS2_QUAD3_MSTID [10] ,EMAC filtering for Quadrant 3 of PS[2]" "Disabled,Enabled"
bitfld.long 0x04 25. " [9] ,DAP filtering for Quadrant 3 of PS[2]" "Disabled,Enabled"
bitfld.long 0x04 23. " [7] ,DMM filtering for Quadrant 3 of PS[2]" "Disabled,Enabled"
bitfld.long 0x04 18. " [2] ,DMA Port B filtering for Quadrant 3 of PS[2]" "Disabled,Enabled"
bitfld.long 0x04 16. " [0] ,CPU Read/Write filtering for Quadrant 3 of PS[2]" "Disabled,Enabled"
textline " "
bitfld.long 0x04 10. " PS2_QUAD2_MSTID [10] ,EMAC filtering for Quadrant 2 of PS[2]" "Disabled,Enabled"
bitfld.long 0x04 9. " [9] ,DAP filtering for Quadrant 2 of PS[2]" "Disabled,Enabled"
bitfld.long 0x04 7. " [7] ,DMM filtering for Quadrant 2 of PS[2]" "Disabled,Enabled"
bitfld.long 0x04 2. " [2] ,DMA Port B filtering for Quadrant 2 of PS[2]" "Disabled,Enabled"
bitfld.long 0x04 0. " [0] ,CPU Read/Write filtering for Quadrant 2 of PS[2]" "Disabled,Enabled"
group.long 0x330++0x07
line.long 0x00 "PS6MSTID_L,SCI4/LIN2/SCI3/LIN1 Peripheral Frame PS[6] MasterID Protection Register_L"
bitfld.long 0x00 26. " PS6_QUAD1_MSTID [10] ,EMAC filtering for Quadrant 1 of PS[6]" "Disabled,Enabled"
bitfld.long 0x00 25. " [9] ,DAP filtering for Quadrant 1 of PS[6]" "Disabled,Enabled"
bitfld.long 0x00 23. " [7] ,DMM filtering for Quadrant 1 of PS[6]" "Disabled,Enabled"
bitfld.long 0x00 18. " [2] ,DMA Port B filtering for Quadrant 1 of PS[6]" "Disabled,Enabled"
bitfld.long 0x00 16. " [0] ,CPU Read/Write filtering for Quadrant 1 of PS[6]" "Disabled,Enabled"
textline " "
bitfld.long 0x00 10. " PS6_QUAD0_MSTID [10] ,EMAC filtering for Quadrant 0 of PS[6]" "Disabled,Enabled"
bitfld.long 0x00 9. " [9] ,DAP filtering for Quadrant 0 of PS[6]" "Disabled,Enabled"
bitfld.long 0x00 7. " [7] ,DMM filtering for Quadrant 0 of PS[6]" "Disabled,Enabled"
bitfld.long 0x00 2. " [2] ,DMA Port B filtering for Quadrant 0 of PS[6]" "Disabled,Enabled"
bitfld.long 0x00 0. " [0] ,CPU Read/Write filtering for Quadrant 0 of PS[6]" "Disabled,Enabled"
line.long 0x04 "PS6MSTID_H,SCI4/LIN2/SCI3/LIN1 Peripheral Frame PS[6] MasterID Protection Register_H"
bitfld.long 0x04 26. " PS6_QUAD3_MSTID [10] ,EMAC filtering for Quadrant 3 of PS[6]" "Disabled,Enabled"
bitfld.long 0x04 25. " [9] ,DAP filtering for Quadrant 3 of PS[6]" "Disabled,Enabled"
bitfld.long 0x04 23. " [7] ,DMM filtering for Quadrant 3 of PS[6]" "Disabled,Enabled"
bitfld.long 0x04 18. " [2] ,DMA Port B filtering for Quadrant 3 of PS[6]" "Disabled,Enabled"
bitfld.long 0x04 16. " [0] ,CPU Read/Write filtering for Quadrant 3 of PS[6]" "Disabled,Enabled"
textline " "
bitfld.long 0x04 10. " PS6_QUAD2_MSTID [10] ,EMAC filtering for Quadrant 2 of PS[6]" "Disabled,Enabled"
bitfld.long 0x04 9. " [9] ,DAP filtering for Quadrant 2 of PS[6]" "Disabled,Enabled"
bitfld.long 0x04 7. " [7] ,DMM filtering for Quadrant 2 of PS[6]" "Disabled,Enabled"
bitfld.long 0x04 2. " [2] ,DMA Port B filtering for Quadrant 2 of PS[6]" "Disabled,Enabled"
bitfld.long 0x04 0. " [0] ,CPU Read/Write filtering for Quadrant 2 of PS[6]" "Disabled,Enabled"
group.long 0x338++0x07
line.long 0x00 "PS7MSTID_L,DCAN4/DCAN3 Peripheral Frame PS[7] MasterID Protection Register_L"
bitfld.long 0x00 26. " PS7_QUAD1_MSTID [10] ,EMAC filtering for Quadrant 1 of PS[7]" "Disabled,Enabled"
bitfld.long 0x00 25. " [9] ,DAP filtering for Quadrant 1 of PS[7]" "Disabled,Enabled"
bitfld.long 0x00 23. " [7] ,DMM filtering for Quadrant 1 of PS[7]" "Disabled,Enabled"
bitfld.long 0x00 18. " [2] ,DMA Port B filtering for Quadrant 1 of PS[7]" "Disabled,Enabled"
bitfld.long 0x00 16. " [0] ,CPU Read/Write filtering for Quadrant 1 of PS[7]" "Disabled,Enabled"
textline " "
bitfld.long 0x00 10. " PS7_QUAD0_MSTID [10] ,EMAC filtering for Quadrant 0 of PS[7]" "Disabled,Enabled"
bitfld.long 0x00 9. " [9] ,DAP filtering for Quadrant 0 of PS[7]" "Disabled,Enabled"
bitfld.long 0x00 7. " [7] ,DMM filtering for Quadrant 0 of PS[7]" "Disabled,Enabled"
bitfld.long 0x00 2. " [2] ,DMA Port B filtering for Quadrant 0 of PS[7]" "Disabled,Enabled"
bitfld.long 0x00 0. " [0] ,CPU Read/Write filtering for Quadrant 0 of PS[7]" "Disabled,Enabled"
line.long 0x04 "PS7MSTID_H,DCAN4/DCAN3 Peripheral Frame PS[7] MasterID Protection Register_H"
bitfld.long 0x04 26. " PS7_QUAD3_MSTID [10] ,EMAC filtering for Quadrant 3 of PS[7]" "Disabled,Enabled"
bitfld.long 0x04 25. " [9] ,DAP filtering for Quadrant 3 of PS[7]" "Disabled,Enabled"
bitfld.long 0x04 23. " [7] ,DMM filtering for Quadrant 3 of PS[7]" "Disabled,Enabled"
bitfld.long 0x04 18. " [2] ,DMA Port B filtering for Quadrant 3 of PS[7]" "Disabled,Enabled"
bitfld.long 0x04 16. " [0] ,CPU Read/Write filtering for Quadrant 3 of PS[7]" "Disabled,Enabled"
textline " "
bitfld.long 0x04 10. " PS7_QUAD2_MSTID [10] ,EMAC filtering for Quadrant 2 of PS[7]" "Disabled,Enabled"
bitfld.long 0x04 9. " [9] ,DAP filtering for Quadrant 2 of PS[7]" "Disabled,Enabled"
bitfld.long 0x04 7. " [7] ,DMM filtering for Quadrant 2 of PS[7]" "Disabled,Enabled"
bitfld.long 0x04 2. " [2] ,DMA Port B filtering for Quadrant 2 of PS[7]" "Disabled,Enabled"
bitfld.long 0x04 0. " [0] ,CPU Read/Write filtering for Quadrant 2 of PS[7]" "Disabled,Enabled"
group.long 0x340++0x07
line.long 0x00 "PS8MSTID_L,DCAN2/DCAN1 Peripheral Frame PS[8] MasterID Protection Register_L"
bitfld.long 0x00 26. " PS8_QUAD1_MSTID [10] ,EMAC filtering for Quadrant 1 of PS[8]" "Disabled,Enabled"
bitfld.long 0x00 25. " [9] ,DAP filtering for Quadrant 1 of PS[8]" "Disabled,Enabled"
bitfld.long 0x00 23. " [7] ,DMM filtering for Quadrant 1 of PS[8]" "Disabled,Enabled"
bitfld.long 0x00 18. " [2] ,DMA Port B filtering for Quadrant 1 of PS[8]" "Disabled,Enabled"
bitfld.long 0x00 16. " [0] ,CPU Read/Write filtering for Quadrant 1 of PS[8]" "Disabled,Enabled"
textline " "
bitfld.long 0x00 10. " PS8_QUAD0_MSTID [10] ,EMAC filtering for Quadrant 0 of PS[8]" "Disabled,Enabled"
bitfld.long 0x00 9. " [9] ,DAP filtering for Quadrant 0 of PS[8]" "Disabled,Enabled"
bitfld.long 0x00 7. " [7] ,DMM filtering for Quadrant 0 of PS[8]" "Disabled,Enabled"
bitfld.long 0x00 2. " [2] ,DMA Port B filtering for Quadrant 0 of PS[8]" "Disabled,Enabled"
bitfld.long 0x00 0. " [0] ,CPU Read/Write filtering for Quadrant 0 of PS[8]" "Disabled,Enabled"
line.long 0x04 "PS8MSTID_H,DCAN2/DCAN1 Peripheral Frame PS[8] MasterID Protection Register_H"
bitfld.long 0x04 26. " PS8_QUAD3_MSTID [10] ,EMAC filtering for Quadrant 3 of PS[8]" "Disabled,Enabled"
bitfld.long 0x04 25. " [9] ,DAP filtering for Quadrant 3 of PS[8]" "Disabled,Enabled"
bitfld.long 0x04 23. " [7] ,DMM filtering for Quadrant 3 of PS[8]" "Disabled,Enabled"
bitfld.long 0x04 18. " [2] ,DMA Port B filtering for Quadrant 3 of PS[8]" "Disabled,Enabled"
bitfld.long 0x04 16. " [0] ,CPU Read/Write filtering for Quadrant 3 of PS[8]" "Disabled,Enabled"
textline " "
bitfld.long 0x04 10. " PS8_QUAD2_MSTID [10] ,EMAC filtering for Quadrant 2 of PS[8]" "Disabled,Enabled"
bitfld.long 0x04 9. " [9] ,DAP filtering for Quadrant 2 of PS[8]" "Disabled,Enabled"
bitfld.long 0x04 7. " [7] ,DMM filtering for Quadrant 2 of PS[8]" "Disabled,Enabled"
bitfld.long 0x04 2. " [2] ,DMA Port B filtering for Quadrant 2 of PS[8]" "Disabled,Enabled"
bitfld.long 0x04 0. " [0] ,CPU Read/Write filtering for Quadrant 2 of PS[8]" "Disabled,Enabled"
group.long 0x350++0x07
line.long 0x00 "PS10MSTID_L,I2C1/I2C2 Peripheral Frame PS [10] MasterID Protection Register_L"
bitfld.long 0x00 26. " PS10_QUAD1_MSTID [10] ,EMAC filtering for Quadrant 1 of PS[10]" "Disabled,Enabled"
bitfld.long 0x00 25. " [9] ,DAP filtering for Quadrant 1 of PS [10]" "Disabled,Enabled"
bitfld.long 0x00 23. " [7] ,DMM filtering for Quadrant 1 of PS [10]" "Disabled,Enabled"
bitfld.long 0x00 18. " [2] ,DMA Port B filtering for Quadrant 1 of PS [10]" "Disabled,Enabled"
bitfld.long 0x00 16. " [0] ,CPU Read/Write filtering for Quadrant 1 of PS [10]" "Disabled,Enabled"
textline " "
bitfld.long 0x00 10. " PS10_QUAD0_MSTID [10] ,EMAC filtering for Quadrant 0 of PS[10]" "Disabled,Enabled"
bitfld.long 0x00 9. " [9] ,DAP filtering for Quadrant 0 of PS [10]" "Disabled,Enabled"
bitfld.long 0x00 7. " [7] ,DMM filtering for Quadrant 0 of PS [10]" "Disabled,Enabled"
bitfld.long 0x00 2. " [2] ,DMA Port B filtering for Quadrant 0 of PS [10]" "Disabled,Enabled"
bitfld.long 0x00 0. " [0] ,CPU Read/Write filtering for Quadrant 0 of PS [10]" "Disabled,Enabled"
line.long 0x04 "PS10MSTID_H,I2C1/I2C2 Peripheral Frame PS [10] MasterID Protection Register_H"
bitfld.long 0x04 26. " PS10_QUAD3_MSTID [10] ,EMAC filtering for Quadrant 3 of PS[10]" "Disabled,Enabled"
bitfld.long 0x04 25. " [9] ,DAP filtering for Quadrant 3 of PS [10]" "Disabled,Enabled"
bitfld.long 0x04 23. " [7] ,DMM filtering for Quadrant 3 of PS [10]" "Disabled,Enabled"
bitfld.long 0x04 18. " [2] ,DMA Port B filtering for Quadrant 3 of PS [10]" "Disabled,Enabled"
bitfld.long 0x04 16. " [0] ,CPU Read/Write filtering for Quadrant 3 of PS [10]" "Disabled,Enabled"
textline " "
bitfld.long 0x04 10. " PS10_QUAD2_MSTID [10] ,EMAC filtering for Quadrant 2 of PS[10]" "Disabled,Enabled"
bitfld.long 0x04 9. " [9] ,DAP filtering for Quadrant 2 of PS [10]" "Disabled,Enabled"
bitfld.long 0x04 7. " [7] ,DMM filtering for Quadrant 2 of PS [10]" "Disabled,Enabled"
bitfld.long 0x04 2. " [2] ,DMA Port B filtering for Quadrant 2 of PS [10]" "Disabled,Enabled"
bitfld.long 0x04 0. " [0] ,CPU Read/Write filtering for Quadrant 2 of PS [10]" "Disabled,Enabled"
group.long 0x360++0x07
line.long 0x00 "PS12MSTID_L,Flexray Peripheral Frame PS[12] MasterID Protection Register_L"
bitfld.long 0x00 26. " PS12_QUAD1_MSTID [10] ,EMAC filtering for Quadrant 1 of PS[12]" "Disabled,Enabled"
bitfld.long 0x00 25. " [9] ,DAP filtering for Quadrant 1 of PS[12]" "Disabled,Enabled"
bitfld.long 0x00 23. " [7] ,DMM filtering for Quadrant 1 of PS[12]" "Disabled,Enabled"
bitfld.long 0x00 18. " [2] ,DMA Port B filtering for Quadrant 1 of PS[12]" "Disabled,Enabled"
bitfld.long 0x00 16. " [0] ,CPU Read/Write filtering for Quadrant 1 of PS[12]" "Disabled,Enabled"
textline " "
bitfld.long 0x00 10. " PS12_QUAD0_MSTID [10] ,EMAC filtering for Quadrant 0 of PS[12]" "Disabled,Enabled"
bitfld.long 0x00 9. " [9] ,DAP filtering for Quadrant 0 of PS[12]" "Disabled,Enabled"
bitfld.long 0x00 7. " [7] ,DMM filtering for Quadrant 0 of PS[12]" "Disabled,Enabled"
bitfld.long 0x00 2. " [2] ,DMA Port B filtering for Quadrant 0 of PS[12]" "Disabled,Enabled"
bitfld.long 0x00 0. " [0] ,CPU Read/Write filtering for Quadrant 0 of PS[12]" "Disabled,Enabled"
line.long 0x04 "PS12MSTID_H,Flexray Peripheral Frame PS[12] MasterID Protection Register_H"
bitfld.long 0x04 26. " PS12_QUAD3_MSTID [10] ,EMAC filtering for Quadrant 3 of PS[12]" "Disabled,Enabled"
bitfld.long 0x04 25. " [9] ,DAP filtering for Quadrant 3 of PS[12]" "Disabled,Enabled"
bitfld.long 0x04 23. " [7] ,DMM filtering for Quadrant 3 of PS[12]" "Disabled,Enabled"
bitfld.long 0x04 18. " [2] ,DMA Port B filtering for Quadrant 3 of PS[12]" "Disabled,Enabled"
bitfld.long 0x04 16. " [0] ,CPU Read/Write filtering for Quadrant 3 of PS[12]" "Disabled,Enabled"
textline " "
bitfld.long 0x04 10. " PS12_QUAD2_MSTID [10] ,EMAC filtering for Quadrant 2 of PS[12]" "Disabled,Enabled"
bitfld.long 0x04 9. " [9] ,DAP filtering for Quadrant 2 of PS[12]" "Disabled,Enabled"
bitfld.long 0x04 7. " [7] ,DMM filtering for Quadrant 2 of PS[12]" "Disabled,Enabled"
bitfld.long 0x04 2. " [2] ,DMA Port B filtering for Quadrant 2 of PS[12]" "Disabled,Enabled"
bitfld.long 0x04 0. " [0] ,CPU Read/Write filtering for Quadrant 2 of PS[12]" "Disabled,Enabled"
group.long 0x368++0x07
line.long 0x00 "PS13MSTID_L,Flexray Peripheral Frame PS[13] MasterID Protection Register_L"
bitfld.long 0x00 26. " PS13_QUAD1_MSTID [10] ,EMAC filtering for Quadrant 1 of PS[13]" "Disabled,Enabled"
bitfld.long 0x00 25. " [9] ,DAP filtering for Quadrant 1 of PS[13]" "Disabled,Enabled"
bitfld.long 0x00 23. " [7] ,DMM filtering for Quadrant 1 of PS[13]" "Disabled,Enabled"
bitfld.long 0x00 18. " [2] ,DMA Port B filtering for Quadrant 1 of PS[13]" "Disabled,Enabled"
bitfld.long 0x00 16. " [0] ,CPU Read/Write filtering for Quadrant 1 of PS[13]" "Disabled,Enabled"
textline " "
bitfld.long 0x00 10. " PS13_QUAD0_MSTID [10] ,EMAC filtering for Quadrant 0 of PS[13]" "Disabled,Enabled"
bitfld.long 0x00 9. " [9] ,DAP filtering for Quadrant 0 of PS[13]" "Disabled,Enabled"
bitfld.long 0x00 7. " [7] ,DMM filtering for Quadrant 0 of PS[13]" "Disabled,Enabled"
bitfld.long 0x00 2. " [2] ,DMA Port B filtering for Quadrant 0 of PS[13]" "Disabled,Enabled"
bitfld.long 0x00 0. " [0] ,CPU Read/Write filtering for Quadrant 0 of PS[13]" "Disabled,Enabled"
line.long 0x04 "PS13MSTID_H,Flexray Peripheral Frame PS[13] MasterID Protection Register_H"
bitfld.long 0x04 26. " PS13_QUAD3_MSTID [10] ,EMAC filtering for Quadrant 3 of PS[13]" "Disabled,Enabled"
bitfld.long 0x04 25. " [9] ,DAP filtering for Quadrant 3 of PS[13]" "Disabled,Enabled"
bitfld.long 0x04 23. " [7] ,DMM filtering for Quadrant 3 of PS[13]" "Disabled,Enabled"
bitfld.long 0x04 18. " [2] ,DMA Port B filtering for Quadrant 3 of PS[13]" "Disabled,Enabled"
bitfld.long 0x04 16. " [0] ,CPU Read/Write filtering for Quadrant 3 of PS[13]" "Disabled,Enabled"
textline " "
bitfld.long 0x04 10. " PS13_QUAD2_MSTID [10] ,EMAC filtering for Quadrant 2 of PS[13]" "Disabled,Enabled"
bitfld.long 0x04 9. " [9] ,DAP filtering for Quadrant 2 of PS[13]" "Disabled,Enabled"
bitfld.long 0x04 7. " [7] ,DMM filtering for Quadrant 2 of PS[13]" "Disabled,Enabled"
bitfld.long 0x04 2. " [2] ,DMA Port B filtering for Quadrant 2 of PS[13]" "Disabled,Enabled"
bitfld.long 0x04 0. " [0] ,CPU Read/Write filtering for Quadrant 2 of PS[13]" "Disabled,Enabled"
group.long 0x378++0x07
line.long 0x00 "PS15MSTID_L,MIBADC2/MIBADC1 Peripheral Frame PS[15] MasterID Protection Register_L"
bitfld.long 0x00 26. " PS15_QUAD1_MSTID [10] ,EMAC filtering for Quadrant 1 of PS[15]" "Disabled,Enabled"
bitfld.long 0x00 25. " [9] ,DAP filtering for Quadrant 1 of PS[15]" "Disabled,Enabled"
bitfld.long 0x00 23. " [7] ,DMM filtering for Quadrant 1 of PS[15]" "Disabled,Enabled"
bitfld.long 0x00 18. " [2] ,DMA Port B filtering for Quadrant 1 of PS[15]" "Disabled,Enabled"
bitfld.long 0x00 16. " [0] ,CPU Read/Write filtering for Quadrant 1 of PS[15]" "Disabled,Enabled"
textline " "
bitfld.long 0x00 10. " PS15_QUAD0_MSTID [10] ,EMAC filtering for Quadrant 0 of PS[15]" "Disabled,Enabled"
bitfld.long 0x00 9. " [9] ,DAP filtering for Quadrant 0 of PS[15]" "Disabled,Enabled"
bitfld.long 0x00 7. " [7] ,DMM filtering for Quadrant 0 of PS[15]" "Disabled,Enabled"
bitfld.long 0x00 2. " [2] ,DMA Port B filtering for Quadrant 0 of PS[15]" "Disabled,Enabled"
bitfld.long 0x00 0. " [0] ,CPU Read/Write filtering for Quadrant 0 of PS[15]" "Disabled,Enabled"
line.long 0x04 "PS15MSTID_H,MIBADC2/MIBADC1 Peripheral Frame PS[15] MasterID Protection Register_H"
bitfld.long 0x04 26. " PS15_QUAD3_MSTID [10] ,EMAC filtering for Quadrant 3 of PS[15]" "Disabled,Enabled"
bitfld.long 0x04 25. " [9] ,DAP filtering for Quadrant 3 of PS[15]" "Disabled,Enabled"
bitfld.long 0x04 23. " [7] ,DMM filtering for Quadrant 3 of PS[15]" "Disabled,Enabled"
bitfld.long 0x04 18. " [2] ,DMA Port B filtering for Quadrant 3 of PS[15]" "Disabled,Enabled"
bitfld.long 0x04 16. " [0] ,CPU Read/Write filtering for Quadrant 3 of PS[15]" "Disabled,Enabled"
textline " "
bitfld.long 0x04 10. " PS15_QUAD2_MSTID [10] ,EMAC filtering for Quadrant 2 of PS[15]" "Disabled,Enabled"
bitfld.long 0x04 9. " [9] ,DAP filtering for Quadrant 2 of PS[15]" "Disabled,Enabled"
bitfld.long 0x04 7. " [7] ,DMM filtering for Quadrant 2 of PS[15]" "Disabled,Enabled"
bitfld.long 0x04 2. " [2] ,DMA Port B filtering for Quadrant 2 of PS[15]" "Disabled,Enabled"
bitfld.long 0x04 0. " [0] ,CPU Read/Write filtering for Quadrant 2 of PS[15]" "Disabled,Enabled"
group.long 0x380++0x07
line.long 0x00 "PS16MSTID_L,GIO Peripheral Frame PS[16] MasterID Protection Register_L"
bitfld.long 0x00 26. " PS16_QUAD1_MSTID [10] ,EMAC filtering for Quadrant 1 of PS[16]" "Disabled,Enabled"
bitfld.long 0x00 25. " [9] ,DAP filtering for Quadrant 1 of PS[16]" "Disabled,Enabled"
bitfld.long 0x00 23. " [7] ,DMM filtering for Quadrant 1 of PS[16]" "Disabled,Enabled"
bitfld.long 0x00 18. " [2] ,DMA Port B filtering for Quadrant 1 of PS[16]" "Disabled,Enabled"
bitfld.long 0x00 16. " [0] ,CPU Read/Write filtering for Quadrant 1 of PS[16]" "Disabled,Enabled"
textline " "
bitfld.long 0x00 10. " PS16_QUAD0_MSTID [10] ,EMAC filtering for Quadrant 0 of PS[16]" "Disabled,Enabled"
bitfld.long 0x00 9. " [9] ,DAP filtering for Quadrant 0 of PS[16]" "Disabled,Enabled"
bitfld.long 0x00 7. " [7] ,DMM filtering for Quadrant 0 of PS[16]" "Disabled,Enabled"
bitfld.long 0x00 2. " [2] ,DMA Port B filtering for Quadrant 0 of PS[16]" "Disabled,Enabled"
bitfld.long 0x00 0. " [0] ,CPU Read/Write filtering for Quadrant 0 of PS[16]" "Disabled,Enabled"
line.long 0x04 "PS16MSTID_H,GIO Peripheral Frame PS[16] MasterID Protection Register_H"
bitfld.long 0x04 26. " PS16_QUAD3_MSTID [10] ,EMAC filtering for Quadrant 3 of PS[16]" "Disabled,Enabled"
bitfld.long 0x04 25. " [9] ,DAP filtering for Quadrant 3 of PS[16]" "Disabled,Enabled"
bitfld.long 0x04 23. " [7] ,DMM filtering for Quadrant 3 of PS[16]" "Disabled,Enabled"
bitfld.long 0x04 18. " [2] ,DMA Port B filtering for Quadrant 3 of PS[16]" "Disabled,Enabled"
bitfld.long 0x04 16. " [0] ,CPU Read/Write filtering for Quadrant 3 of PS[16]" "Disabled,Enabled"
textline " "
bitfld.long 0x04 10. " PS16_QUAD2_MSTID [10] ,EMAC filtering for Quadrant 2 of PS[16]" "Disabled,Enabled"
bitfld.long 0x04 9. " [9] ,DAP filtering for Quadrant 2 of PS[16]" "Disabled,Enabled"
bitfld.long 0x04 7. " [7] ,DMM filtering for Quadrant 2 of PS[16]" "Disabled,Enabled"
bitfld.long 0x04 2. " [2] ,DMA Port B filtering for Quadrant 2 of PS[16]" "Disabled,Enabled"
bitfld.long 0x04 0. " [0] ,CPU Read/Write filtering for Quadrant 2 of PS[16]" "Disabled,Enabled"
group.long 0x388++0x07
line.long 0x00 "PS17MSTID_L,NHET2/NHET1 Peripheral Frame PS[17] MasterID Protection Register_L"
bitfld.long 0x00 26. " PS17_QUAD1_MSTID [10] ,EMAC filtering for Quadrant 1 of PS[17]" "Disabled,Enabled"
bitfld.long 0x00 25. " [9] ,DAP filtering for Quadrant 1 of PS[17]" "Disabled,Enabled"
bitfld.long 0x00 23. " [7] ,DMM filtering for Quadrant 1 of PS[17]" "Disabled,Enabled"
bitfld.long 0x00 18. " [2] ,DMA Port B filtering for Quadrant 1 of PS[17]" "Disabled,Enabled"
bitfld.long 0x00 16. " [0] ,CPU Read/Write filtering for Quadrant 1 of PS[17]" "Disabled,Enabled"
textline " "
bitfld.long 0x00 10. " PS17_QUAD0_MSTID [10] ,EMAC filtering for Quadrant 0 of PS[17]" "Disabled,Enabled"
bitfld.long 0x00 9. " [9] ,DAP filtering for Quadrant 0 of PS[17]" "Disabled,Enabled"
bitfld.long 0x00 7. " [7] ,DMM filtering for Quadrant 0 of PS[17]" "Disabled,Enabled"
bitfld.long 0x00 2. " [2] ,DMA Port B filtering for Quadrant 0 of PS[17]" "Disabled,Enabled"
bitfld.long 0x00 0. " [0] ,CPU Read/Write filtering for Quadrant 0 of PS[17]" "Disabled,Enabled"
line.long 0x04 "PS17MSTID_H,NHET2/NHET1 Peripheral Frame PS[17] MasterID Protection Register_H"
bitfld.long 0x04 26. " PS17_QUAD3_MSTID [10] ,EMAC filtering for Quadrant 3 of PS[17]" "Disabled,Enabled"
bitfld.long 0x04 25. " [9] ,DAP filtering for Quadrant 3 of PS[17]" "Disabled,Enabled"
bitfld.long 0x04 23. " [7] ,DMM filtering for Quadrant 3 of PS[17]" "Disabled,Enabled"
bitfld.long 0x04 18. " [2] ,DMA Port B filtering for Quadrant 3 of PS[17]" "Disabled,Enabled"
bitfld.long 0x04 16. " [0] ,CPU Read/Write filtering for Quadrant 3 of PS[17]" "Disabled,Enabled"
textline " "
bitfld.long 0x04 10. " PS17_QUAD2_MSTID [10] ,EMAC filtering for Quadrant 2 of PS[17]" "Disabled,Enabled"
bitfld.long 0x04 9. " [9] ,DAP filtering for Quadrant 2 of PS[17]" "Disabled,Enabled"
bitfld.long 0x04 7. " [7] ,DMM filtering for Quadrant 2 of PS[17]" "Disabled,Enabled"
bitfld.long 0x04 2. " [2] ,DMA Port B filtering for Quadrant 2 of PS[17]" "Disabled,Enabled"
bitfld.long 0x04 0. " [0] ,CPU Read/Write filtering for Quadrant 2 of PS[17]" "Disabled,Enabled"
group.long 0x400++0x07
line.long 0x00 "PS20MSTID_L,IMM Peripheral Frame PS[20] MasterID Protection Register_L"
bitfld.long 0x00 26. " PS20_QUAD1_MSTID [10] ,EMAC filtering for Quadrant 1 of PS[20]" "Disabled,Enabled"
bitfld.long 0x00 25. " [9] ,DAP filtering for Quadrant 1 of PS[20]" "Disabled,Enabled"
bitfld.long 0x00 23. " [7] ,DMM filtering for Quadrant 1 of PS[20]" "Disabled,Enabled"
bitfld.long 0x00 18. " [2] ,DMA Port B filtering for Quadrant 1 of PS[20]" "Disabled,Enabled"
bitfld.long 0x00 16. " [0] ,CPU Read/Write filtering for Quadrant 1 of PS[20]" "Disabled,Enabled"
textline " "
bitfld.long 0x00 10. " PS20_QUAD0_MSTID [10] ,EMAC filtering for Quadrant 0 of PS[20]" "Disabled,Enabled"
bitfld.long 0x00 9. " [9] ,DAP filtering for Quadrant 0 of PS[20]" "Disabled,Enabled"
bitfld.long 0x00 7. " [7] ,DMM filtering for Quadrant 0 of PS[20]" "Disabled,Enabled"
bitfld.long 0x00 2. " [2] ,DMA Port B filtering for Quadrant 0 of PS[20]" "Disabled,Enabled"
bitfld.long 0x00 0. " [0] ,CPU Read/Write filtering for Quadrant 0 of PS[20]" "Disabled,Enabled"
line.long 0x04 "PS20MSTID_H,IMM Peripheral Frame PS[20] MasterID Protection Register_H"
bitfld.long 0x04 26. " PS20_QUAD3_MSTID [10] ,EMAC filtering for Quadrant 3 of PS[20]" "Disabled,Enabled"
bitfld.long 0x04 25. " [9] ,DAP filtering for Quadrant 3 of PS[20]" "Disabled,Enabled"
bitfld.long 0x04 23. " [7] ,DMM filtering for Quadrant 3 of PS[20]" "Disabled,Enabled"
bitfld.long 0x04 18. " [2] ,DMA Port B filtering for Quadrant 3 of PS[20]" "Disabled,Enabled"
bitfld.long 0x04 16. " [0] ,CPU Read/Write filtering for Quadrant 3 of PS[20]" "Disabled,Enabled"
textline " "
bitfld.long 0x04 10. " PS20_QUAD2_MSTID [10] ,EMAC filtering for Quadrant 2 of PS[20]" "Disabled,Enabled"
bitfld.long 0x04 9. " [9] ,DAP filtering for Quadrant 2 of PS[20]" "Disabled,Enabled"
bitfld.long 0x04 7. " [7] ,DMM filtering for Quadrant 2 of PS[20]" "Disabled,Enabled"
bitfld.long 0x04 2. " [2] ,DMA Port B filtering for Quadrant 2 of PS[20]" "Disabled,Enabled"
bitfld.long 0x04 0. " [0] ,CPU Read/Write filtering for Quadrant 2 of PS[20]" "Disabled,Enabled"
group.long 0x410++0x07
line.long 0x00 "PS22MSTID_L,HTU1 Peripheral Frame PS[22] MasterID Protection Register_L"
bitfld.long 0x00 26. " PS22_QUAD1_MSTID [10] ,EMAC filtering for Quadrant 1 of PS[22]" "Disabled,Enabled"
bitfld.long 0x00 25. " [9] ,DAP filtering for Quadrant 1 of PS[22]" "Disabled,Enabled"
bitfld.long 0x00 23. " [7] ,DMM filtering for Quadrant 1 of PS[22]" "Disabled,Enabled"
bitfld.long 0x00 18. " [2] ,DMA Port B filtering for Quadrant 1 of PS[22]" "Disabled,Enabled"
bitfld.long 0x00 16. " [0] ,CPU Read/Write filtering for Quadrant 1 of PS[22]" "Disabled,Enabled"
textline " "
bitfld.long 0x00 10. " PS22_QUAD0_MSTID [10] ,EMAC filtering for Quadrant 0 of PS[22]" "Disabled,Enabled"
bitfld.long 0x00 9. " [9] ,DAP filtering for Quadrant 0 of PS[22]" "Disabled,Enabled"
bitfld.long 0x00 7. " [7] ,DMM filtering for Quadrant 0 of PS[22]" "Disabled,Enabled"
bitfld.long 0x00 2. " [2] ,DMA Port B filtering for Quadrant 0 of PS[22]" "Disabled,Enabled"
bitfld.long 0x00 0. " [0] ,CPU Read/Write filtering for Quadrant 0 of PS[22]" "Disabled,Enabled"
line.long 0x04 "PS22MSTID_H,HTU1 Peripheral Frame PS[22] MasterID Protection Register_H"
bitfld.long 0x04 26. " PS22_QUAD3_MSTID [10] ,EMAC filtering for Quadrant 3 of PS[22]" "Disabled,Enabled"
bitfld.long 0x04 25. " [9] ,DAP filtering for Quadrant 3 of PS[22]" "Disabled,Enabled"
bitfld.long 0x04 23. " [7] ,DMM filtering for Quadrant 3 of PS[22]" "Disabled,Enabled"
bitfld.long 0x04 18. " [2] ,DMA Port B filtering for Quadrant 3 of PS[22]" "Disabled,Enabled"
bitfld.long 0x04 16. " [0] ,CPU Read/Write filtering for Quadrant 3 of PS[22]" "Disabled,Enabled"
textline " "
bitfld.long 0x04 10. " PS22_QUAD2_MSTID [10] ,EMAC filtering for Quadrant 2 of PS[22]" "Disabled,Enabled"
bitfld.long 0x04 9. " [9] ,DAP filtering for Quadrant 2 of PS[22]" "Disabled,Enabled"
bitfld.long 0x04 7. " [7] ,DMM filtering for Quadrant 2 of PS[22]" "Disabled,Enabled"
bitfld.long 0x04 2. " [2] ,DMA Port B filtering for Quadrant 2 of PS[22]" "Disabled,Enabled"
bitfld.long 0x04 0. " [0] ,CPU Read/Write filtering for Quadrant 2 of PS[22]" "Disabled,Enabled"
group.long 0x418++0x07
line.long 0x00 "PS23MSTID_L,HTU2 Peripheral Frame PS[23] MasterID Protection Register_L"
bitfld.long 0x00 26. " PS23_QUAD1_MSTID [10] ,EMAC filtering for Quadrant 1 of PS[23]" "Disabled,Enabled"
bitfld.long 0x00 25. " [9] ,DAP filtering for Quadrant 1 of PS[23]" "Disabled,Enabled"
bitfld.long 0x00 23. " [7] ,DMM filtering for Quadrant 1 of PS[23]" "Disabled,Enabled"
bitfld.long 0x00 18. " [2] ,DMA Port B filtering for Quadrant 1 of PS[23]" "Disabled,Enabled"
bitfld.long 0x00 16. " [0] ,CPU Read/Write filtering for Quadrant 1 of PS[23]" "Disabled,Enabled"
textline " "
bitfld.long 0x00 10. " PS23_QUAD0_MSTID [10] ,EMAC filtering for Quadrant 0 of PS[23]" "Disabled,Enabled"
bitfld.long 0x00 9. " [9] ,DAP filtering for Quadrant 0 of PS[23]" "Disabled,Enabled"
bitfld.long 0x00 7. " [7] ,DMM filtering for Quadrant 0 of PS[23]" "Disabled,Enabled"
bitfld.long 0x00 2. " [2] ,DMA Port B filtering for Quadrant 0 of PS[23]" "Disabled,Enabled"
bitfld.long 0x00 0. " [0] ,CPU Read/Write filtering for Quadrant 0 of PS[23]" "Disabled,Enabled"
line.long 0x04 "PS23MSTID_H,HTU2 Peripheral Frame PS[23] MasterID Protection Register_H"
bitfld.long 0x04 26. " PS23_QUAD3_MSTID [10] ,EMAC filtering for Quadrant 3 of PS[23]" "Disabled,Enabled"
bitfld.long 0x04 25. " [9] ,DAP filtering for Quadrant 3 of PS[23]" "Disabled,Enabled"
bitfld.long 0x04 23. " [7] ,DMM filtering for Quadrant 3 of PS[23]" "Disabled,Enabled"
bitfld.long 0x04 18. " [2] ,DMA Port B filtering for Quadrant 3 of PS[23]" "Disabled,Enabled"
bitfld.long 0x04 16. " [0] ,CPU Read/Write filtering for Quadrant 3 of PS[23]" "Disabled,Enabled"
textline " "
bitfld.long 0x04 10. " PS23_QUAD2_MSTID [10] ,EMAC filtering for Quadrant 2 of PS[23]" "Disabled,Enabled"
bitfld.long 0x04 9. " [9] ,DAP filtering for Quadrant 2 of PS[23]" "Disabled,Enabled"
bitfld.long 0x04 7. " [7] ,DMM filtering for Quadrant 2 of PS[23]" "Disabled,Enabled"
bitfld.long 0x04 2. " [2] ,DMA Port B filtering for Quadrant 2 of PS[23]" "Disabled,Enabled"
bitfld.long 0x04 0. " [0] ,CPU Read/Write filtering for Quadrant 2 of PS[23]" "Disabled,Enabled"
group.long 0x450++0x07
line.long 0x00 "PS30MSTID_L,PCR3 Register Peripheral Frame PS[30] MasterID Protection Register_L"
bitfld.long 0x00 26. " PS30_QUAD1_MSTID [10] ,EMAC filtering for Quadrant 1 of PS[30]" "Disabled,Enabled"
bitfld.long 0x00 25. " [9] ,DAP filtering for Quadrant 1 of PS[30]" "Disabled,Enabled"
bitfld.long 0x00 23. " [7] ,DMM filtering for Quadrant 1 of PS[30]" "Disabled,Enabled"
bitfld.long 0x00 18. " [2] ,DMA Port B filtering for Quadrant 1 of PS[30]" "Disabled,Enabled"
bitfld.long 0x00 16. " [0] ,CPU Read/Write filtering for Quadrant 1 of PS[30]" "Disabled,Enabled"
textline " "
bitfld.long 0x00 10. " PS30_QUAD0_MSTID [10] ,EMAC filtering for Quadrant 0 of PS[30]" "Disabled,Enabled"
bitfld.long 0x00 9. " [9] ,DAP filtering for Quadrant 0 of PS[30]" "Disabled,Enabled"
bitfld.long 0x00 7. " [7] ,DMM filtering for Quadrant 0 of PS[30]" "Disabled,Enabled"
bitfld.long 0x00 2. " [2] ,DMA Port B filtering for Quadrant 0 of PS[30]" "Disabled,Enabled"
bitfld.long 0x00 0. " [0] ,CPU Read/Write filtering for Quadrant 0 of PS[30]" "Disabled,Enabled"
line.long 0x04 "PS30MSTID_H,HTU1 Peripheral Frame PS[30] MasterID Protection Register_H"
bitfld.long 0x04 26. " PS30_QUAD3_MSTID [10] ,EMAC filtering for Quadrant 3 of PS[30]" "Disabled,Enabled"
bitfld.long 0x04 25. " [9] ,DAP filtering for Quadrant 3 of PS[30]" "Disabled,Enabled"
bitfld.long 0x04 23. " [7] ,DMM filtering for Quadrant 3 of PS[30]" "Disabled,Enabled"
bitfld.long 0x04 18. " [2] ,DMA Port B filtering for Quadrant 3 of PS[30]" "Disabled,Enabled"
bitfld.long 0x04 16. " [0] ,CPU Read/Write filtering for Quadrant 3 of PS[30]" "Disabled,Enabled"
textline " "
bitfld.long 0x04 10. " PS30_QUAD2_MSTID [10] ,EMAC filtering for Quadrant 2 of PS[30]" "Disabled,Enabled"
bitfld.long 0x04 9. " [9] ,DAP filtering for Quadrant 2 of PS[30]" "Disabled,Enabled"
bitfld.long 0x04 7. " [7] ,DMM filtering for Quadrant 2 of PS[30]" "Disabled,Enabled"
bitfld.long 0x04 2. " [2] ,DMA Port B filtering for Quadrant 2 of PS[30]" "Disabled,Enabled"
bitfld.long 0x04 0. " [0] ,CPU Read/Write filtering for Quadrant 2 of PS[30]" "Disabled,Enabled"
group.long 0x458++0x07
line.long 0x00 "PS31MSTID_L,PCR3 Register Peripheral Frame PS[31] MasterID Protection Register_L"
bitfld.long 0x00 26. " PS31_QUAD1_MSTID [10] ,EMAC filtering for Quadrant 1 of PS[31]" "Disabled,Enabled"
bitfld.long 0x00 25. " [9] ,DAP filtering for Quadrant 1 of PS[31]" "Disabled,Enabled"
bitfld.long 0x00 23. " [7] ,DMM filtering for Quadrant 1 of PS[31]" "Disabled,Enabled"
bitfld.long 0x00 18. " [2] ,DMA Port B filtering for Quadrant 1 of PS[31]" "Disabled,Enabled"
bitfld.long 0x00 16. " [0] ,CPU Read/Write filtering for Quadrant 1 of PS[31]" "Disabled,Enabled"
textline " "
bitfld.long 0x00 10. " PS31_QUAD0_MSTID [10] ,EMAC filtering for Quadrant 0 of PS[31]" "Disabled,Enabled"
bitfld.long 0x00 9. " [9] ,DAP filtering for Quadrant 0 of PS[31]" "Disabled,Enabled"
bitfld.long 0x00 7. " [7] ,DMM filtering for Quadrant 0 of PS[31]" "Disabled,Enabled"
bitfld.long 0x00 2. " [2] ,DMA Port B filtering for Quadrant 0 of PS[31]" "Disabled,Enabled"
bitfld.long 0x00 0. " [0] ,CPU Read/Write filtering for Quadrant 0 of PS[31]" "Disabled,Enabled"
line.long 0x04 "PS31MSTID_H,HTU2 Peripheral Frame PS[31] MasterID Protection Register_H"
bitfld.long 0x04 26. " PS31_QUAD3_MSTID [10] ,EMAC filtering for Quadrant 3 of PS[31]" "Disabled,Enabled"
bitfld.long 0x04 25. " [9] ,DAP filtering for Quadrant 3 of PS[31]" "Disabled,Enabled"
bitfld.long 0x04 23. " [7] ,DMM filtering for Quadrant 3 of PS[31]" "Disabled,Enabled"
bitfld.long 0x04 18. " [2] ,DMA Port B filtering for Quadrant 3 of PS[31]" "Disabled,Enabled"
bitfld.long 0x04 16. " [0] ,CPU Read/Write filtering for Quadrant 3 of PS[31]" "Disabled,Enabled"
textline " "
bitfld.long 0x04 10. " PS31_QUAD2_MSTID [10] ,EMAC filtering for Quadrant 2 of PS[31]" "Disabled,Enabled"
bitfld.long 0x04 9. " [9] ,DAP filtering for Quadrant 2 of PS[31]" "Disabled,Enabled"
bitfld.long 0x04 7. " [7] ,DMM filtering for Quadrant 2 of PS[31]" "Disabled,Enabled"
bitfld.long 0x04 2. " [2] ,DMA Port B filtering for Quadrant 2 of PS[31]" "Disabled,Enabled"
bitfld.long 0x04 0. " [0] ,CPU Read/Write filtering for Quadrant 2 of PS[31]" "Disabled,Enabled"
tree.end
width 15.
tree "Peripheral Memory Frame MasterID Protection Register"
group.long 0x544++0x0B
line.long 0x00 "PCS1MSTID,MIBSPI4 RAM Peripheral Frame PCS[3] MasterID Protection Register"
bitfld.long 0x00 26. " PCS3_MSTID [10] ,EMAC filtering for PCS[3]" "Disabled,Enabled"
bitfld.long 0x00 25. " [9] ,DAP filtering for PCS[3]" "Disabled,Enabled"
bitfld.long 0x00 23. " [7] ,DMM filtering for PCS[3]" "Disabled,Enabled"
bitfld.long 0x00 18. " [2] ,DMA Port B filtering for PCS[3]" "Disabled,Enabled"
bitfld.long 0x00 16. " [0] ,CPU Read/Write filtering for PCS[3]" "Disabled,Enabled"
line.long 0x04 "PCS2MSTID,MIBSPI2 RAM/MIBSPI5 RAM Peripheral Frame PCS[4]/PCS[5] MasterID Protection Register"
bitfld.long 0x04 26. " PCS5_MSTID [10] ,EMAC filtering for PCS[5]" "Disabled,Enabled"
bitfld.long 0x04 25. " [9] ,DAP filtering for PCS[5]" "Disabled,Enabled"
bitfld.long 0x04 23. " [7] ,DMM filtering for PCS[5]" "Disabled,Enabled"
bitfld.long 0x04 18. " [2] ,DMA Port B filtering for PCS[5]" "Disabled,Enabled"
bitfld.long 0x04 16. " [0] ,CPU Read/Write filtering for PCS[5]" "Disabled,Enabled"
textline " "
bitfld.long 0x04 10. " PCS4_MSTID [10] ,EMAC filtering for PCS[4]" "Disabled,Enabled"
bitfld.long 0x04 9. " [9] ,DAP filtering for PCS[4]" "Disabled,Enabled"
bitfld.long 0x04 7. " [7] ,DMM filtering for PCS[4]" "Disabled,Enabled"
bitfld.long 0x04 2. " [2] ,DMA Port B filtering for PCS[4]" "Disabled,Enabled"
bitfld.long 0x04 0. " [0] ,CPU Read/Write filtering for PCS[4]" "Disabled,Enabled"
line.long 0x08 "PCS3MSTID,MIBSPI3 RAM/MIBSPI1 RAM Peripheral Frame PCS[6]/PCS[7] MasterID Protection Register"
bitfld.long 0x08 26. " PCS7_MSTID [10] ,EMAC filtering for PCS[7]" "Disabled,Enabled"
bitfld.long 0x08 25. " [9] ,DAP filtering for PCS[7]" "Disabled,Enabled"
bitfld.long 0x08 23. " [7] ,DMM filtering for PCS[7]" "Disabled,Enabled"
bitfld.long 0x08 18. " [2] ,DMA Port B filtering for PCS[7]" "Disabled,Enabled"
bitfld.long 0x08 16. " [0] ,CPU Read/Write filtering for PCS[7]" "Disabled,Enabled"
textline " "
bitfld.long 0x08 10. " PCS6_MSTID [10] ,EMAC filtering for PCS[6]" "Disabled,Enabled"
bitfld.long 0x08 9. " [9] ,DAP filtering for PCS[6]" "Disabled,Enabled"
bitfld.long 0x08 7. " [7] ,DMM filtering for PCS[6]" "Disabled,Enabled"
bitfld.long 0x08 2. " [2] ,DMA Port B filtering for PCS[6]" "Disabled,Enabled"
bitfld.long 0x08 0. " [0] ,CPU Read/Write filtering for PCS[6]" "Disabled,Enabled"
group.long 0x558++0x07
line.long 0x00 "PCS6MSTID,DCAN2 RAM/DCAN1 RAM Peripheral Frame PCS[12]/PCS[13] MasterID Protection Register"
bitfld.long 0x00 26. " PCS13_MSTID [10] ,EMAC filtering for PCS[13]" "Disabled,Enabled"
bitfld.long 0x00 25. " [9] ,DAP filtering for PCS[13]" "Disabled,Enabled"
bitfld.long 0x00 23. " [7] ,DMM filtering for PCS[13]" "Disabled,Enabled"
bitfld.long 0x00 18. " [2] ,DMA Port B filtering for PCS[13]" "Disabled,Enabled"
bitfld.long 0x00 16. " [0] ,CPU Read/Write filtering for PCS[13]" "Disabled,Enabled"
textline " "
bitfld.long 0x00 10. " PCS12_MSTID [10] ,EMAC filtering for PCS[12]" "Disabled,Enabled"
bitfld.long 0x00 9. " [9] ,DAP filtering for PCS[12]" "Disabled,Enabled"
bitfld.long 0x00 7. " [7] ,DMM filtering for PCS[12]" "Disabled,Enabled"
bitfld.long 0x00 2. " [2] ,DMA Port B filtering for PCS[12]" "Disabled,Enabled"
bitfld.long 0x00 0. " [0] ,CPU Read/Write filtering for PCS[12]" "Disabled,Enabled"
line.long 0x04 "PCS7MSTID,DCAN4 RAM/DCAN 3 RAM Peripheral Frame PCS[14]/PCS[15] MasterID Protection Register"
bitfld.long 0x04 26. " PCS15_MSTID [10] ,EMAC filtering for PCS[15]" "Disabled,Enabled"
bitfld.long 0x04 25. " [9] ,DAP filtering for PCS[15]" "Disabled,Enabled"
bitfld.long 0x04 23. " [7] ,DMM filtering for PCS[15]" "Disabled,Enabled"
bitfld.long 0x04 18. " [2] ,DMA Port B filtering for PCS[15]" "Disabled,Enabled"
bitfld.long 0x04 16. " [0] ,CPU Read/Write filtering for PCS[15]" "Disabled,Enabled"
textline " "
bitfld.long 0x04 10. " PCS14_MSTID [10] ,EMAC filtering for PCS[14]" "Disabled,Enabled"
bitfld.long 0x04 9. " [9] ,DAP filtering for PCS[14]" "Disabled,Enabled"
bitfld.long 0x04 7. " [7] ,DMM filtering for PCS[14]" "Disabled,Enabled"
bitfld.long 0x04 2. " [2] ,DMA Port B filtering for PCS[14]" "Disabled,Enabled"
bitfld.long 0x04 0. " [0] ,CPU Read/Write filtering for PCS[14]" "Disabled,Enabled"
group.long 0x590++0x07
line.long 0x00 "PCS14MSTID,MIBADC2 RAM Peripheral Frame PCS[29] MasterID Protection Register"
bitfld.long 0x00 26. " PCS29_MSTID [10] ,EMAC filtering for PCS[29]" "Disabled,Enabled"
bitfld.long 0x00 25. " [9] ,DAP filtering for PCS[29]" "Disabled,Enabled"
bitfld.long 0x00 23. " [7] ,DMM filtering for PCS[29]" "Disabled,Enabled"
bitfld.long 0x00 18. " [2] ,DMA Port B filtering for PCS[29]" "Disabled,Enabled"
bitfld.long 0x00 16. " [0] ,CPU Read/Write filtering for PCS[29]" "Disabled,Enabled"
line.long 0x04 "PCS15MSTID,MIBADC1 RAM Peripheral Frame PCS[31] MasterID Protection Register"
bitfld.long 0x04 26. " PCS31_MSTID [10] ,EMAC filtering for PCS[31]" "Disabled,Enabled"
bitfld.long 0x04 25. " [9] ,DAP filtering for PCS[31]" "Disabled,Enabled"
bitfld.long 0x04 23. " [7] ,DMM filtering for PCS[31]" "Disabled,Enabled"
bitfld.long 0x04 18. " [2] ,DMA Port B filtering for PCS[31]" "Disabled,Enabled"
bitfld.long 0x04 16. " [0] ,CPU Read/Write filtering for PCS[31]" "Disabled,Enabled"
group.long 0x59C++0x03
line.long 0x00 "PCS17MSTID,NHET2 RAM/NHET1 RAM Peripheral Frame PCS[34]/PCS[35] MasterID Protection Register"
bitfld.long 0x00 26. " PCS35_MSTID [10] ,EMAC filtering for PCS[35]" "Disabled,Enabled"
bitfld.long 0x00 25. " [9] ,DAP filtering for PCS[35]" "Disabled,Enabled"
bitfld.long 0x00 23. " [7] ,DMM filtering for PCS[35]" "Disabled,Enabled"
bitfld.long 0x00 18. " [2] ,DMA Port B filtering for PCS[35]" "Disabled,Enabled"
bitfld.long 0x00 16. " [0] ,CPU Read/Write filtering for PCS[35]" "Disabled,Enabled"
textline " "
bitfld.long 0x00 10. " PCS34_MSTID [10] ,EMAC filtering for PCS[34]" "Disabled,Enabled"
bitfld.long 0x00 9. " [9] ,DAP filtering for PCS[34]" "Disabled,Enabled"
bitfld.long 0x00 7. " [7] ,DMM filtering for PCS[34]" "Disabled,Enabled"
bitfld.long 0x00 2. " [2] ,DMA Port B filtering for PCS[34]" "Disabled,Enabled"
bitfld.long 0x00 0. " [0] ,CPU Read/Write filtering for PCS[34]" "Disabled,Enabled"
group.long 0x5A4++0x07
line.long 0x00 "PCS19MSTID,HET TU2 RAM/HET TU1 RAM Peripheral Frame PCS[38]/PCS[39] MasterID Protection Register"
bitfld.long 0x00 26. " PCS39_MSTID [10] ,EMAC filtering for PCS[39]" "Disabled,Enabled"
bitfld.long 0x00 25. " [9] ,DAP filtering for PCS[39]" "Disabled,Enabled"
bitfld.long 0x00 23. " [7] ,DMM filtering for PCS[39]" "Disabled,Enabled"
bitfld.long 0x00 18. " [2] ,DMA Port B filtering for PCS[39]" "Disabled,Enabled"
bitfld.long 0x00 16. " [0] ,CPU Read/Write filtering for PCS[39]" "Disabled,Enabled"
textline " "
bitfld.long 0x00 10. " PCS38_MSTID [10] ,EMAC filtering for PCS[38]" "Disabled,Enabled"
bitfld.long 0x00 9. " [9] ,DAP filtering for PCS[38]" "Disabled,Enabled"
bitfld.long 0x00 7. " [7] ,DMM filtering for PCS[38]" "Disabled,Enabled"
bitfld.long 0x00 2. " [2] ,DMA Port B filtering for PCS[38]" "Disabled,Enabled"
bitfld.long 0x00 0. " [0] ,CPU Read/Write filtering for PCS[38]" "Disabled,Enabled"
line.long 0x04 "PCS20MSTID,FlexRay TU RAM Peripheral Frame PCS[40] MasterID Protection Register"
bitfld.long 0x04 10. " PCS40_MSTID [10] ,EMAC filtering for PCS[40]" "Disabled,Enabled"
bitfld.long 0x04 9. " [9] ,DAP filtering for PCS[40]" "Disabled,Enabled"
bitfld.long 0x04 7. " [7] ,DMM filtering for PCS[40]" "Disabled,Enabled"
bitfld.long 0x04 2. " [2] ,DMA Port B filtering for PCS[40]" "Disabled,Enabled"
bitfld.long 0x04 0. " [0] ,CPU Read/Write filtering for PCS[40]" "Disabled,Enabled"
tree.end
tree.end
width 0xb
tree.end
tree.end
tree.end
tree "SCM (SCR Control Module)"
base ad:0xFFFF0A00
width 15.
rgroup.long 0x00++0x03
line.long 0x00 "SCMREVID,SCM REVID Register"
bitfld.long 0x00 30.--31. " SCHEME ,Identification scheme" "0,1,2,3"
hexmask.long.word 0x00 16.--27. 1. " FUNC ,Indicates functionally equivalent module family"
bitfld.long 0x00 11.--15. " RTL ,RTL version number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline " "
bitfld.long 0x00 8.--10. " MAJOR ,Major revision number" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--7. " CUSTOM ,Indicates device-specific implementation" "0,1,2,3"
bitfld.long 0x00 0.--5. " MINOR ,Minor revision number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x04++0x07
line.long 0x00 "SCMCNTRL,SCM Control Register"
bitfld.long 0x00 24.--27. " PAR_DIAG_EN ,Parity diagnostic [Read/WriteInPriviledge]" ",,,,,Sticky key/Reserved,,,,,Reserved/Enabled,?..."
bitfld.long 0x00 16.--19. " GLOBAL_ERROR_CLR ,Clear global error [Read/WriteInPriviledge]" ",,,,,Sticky key/Reserved,,,,,Reserved/Enabled,?..."
textline " "
bitfld.long 0x00 8.--11. " DTC_SOFT_RESET ,Diagnostic self-test error [Read/WriteInPriviledge]" ",,,,,Sticky key/Reserved,,,,,Reserved/Enabled,?..."
bitfld.long 0x00 0.--3. " TO_CLEAR ,Clear real time counters [Read/WriteInPriviledge]" ",,,,,Sticky key/Reserved,,,,,Reserved/Enabled,?..."
line.long 0x04 "SCMTHRESHOLD,SCM Compare Threshold Counter Register"
hexmask.long.word 0x04 16.--31. 1. " REQ2RESPONSE_MAX ,Request to response threshold values"
hexmask.long.word 0x04 0.--15. 1. " REQ2ACCEPT_MAX ,Request to accept threshold values"
textline " "
group.long 0x10++0x07
line.long 0x00 "SCMIAERR0STAT,SCM Initiator Error0 Status Register"
eventfld.long 0x00 7. " R2A[7] ,Request to acceptance timeout error happens on IA7" "Not requested,Requested"
eventfld.long 0x00 6. " [6] ,Request to acceptance timeout error happens on IA6" "Not requested,Requested"
eventfld.long 0x00 5. " [5] ,Request to acceptance timeout error happens on IA5" "Not requested,Requested"
eventfld.long 0x00 4. " [4] ,Request to acceptance timeout error happens on IA4" "Not requested,Requested"
textline " "
eventfld.long 0x00 3. " [3] ,Request to acceptance timeout error happens on IA3" "Not requested,Requested"
eventfld.long 0x00 2. " [2] ,Request to acceptance timeout error happens on IA2" "Not requested,Requested"
eventfld.long 0x00 1. " [1] ,Request to acceptance timeout error happens on IA1" "Not requested,Requested"
eventfld.long 0x00 0. " [0] ,Request to acceptance timeout error happens on IA0" "Not requested,Requested"
line.long 0x04 "SCMIAERR0STAT,SCM Initiator Error1 Status Register"
eventfld.long 0x04 7. " R2R[7] ,Request to response timeout error happens on IA7" "Not requested,Requested"
eventfld.long 0x04 6. " [6] ,Request to response timeout error happens on IA6" "Not requested,Requested"
eventfld.long 0x04 5. " [5] ,Request to response timeout error happens on IA5" "Not requested,Requested"
eventfld.long 0x04 4. " [4] ,Request to response timeout error happens on IA4" "Not requested,Requested"
textline " "
eventfld.long 0x04 3. " [3] ,Request to response timeout error happens on IA3" "Not requested,Requested"
eventfld.long 0x04 2. " [2] ,Request to response timeout error happens on IA2" "Not requested,Requested"
eventfld.long 0x04 1. " [1] ,Request to response timeout error happens on IA1" "Not requested,Requested"
eventfld.long 0x04 0. " [0] ,Request to response timeout error happens on IA0" "Not requested,Requested"
textline " "
rgroup.long 0x18++0x03
line.long 0x00 "SCMIASTAT,SCM Initiator Active Status Register"
bitfld.long 0x00 13. " IAST[13] ,Initiator agent 13 status" "Not pending,Pending"
bitfld.long 0x00 12. " [12] ,Initiator agent 12 status" "Not pending,Pending"
bitfld.long 0x00 11. " [11] ,Initiator agent 11 status" "Not pending,Pending"
bitfld.long 0x00 10. " [10] ,Initiator agent 10 status" "Not pending,Pending"
textline " "
bitfld.long 0x00 9. " [9] ,Initiator agent 9 status" "Not pending,Pending"
bitfld.long 0x00 8. " [8] ,Initiator agent 8 status" "Not pending,Pending"
bitfld.long 0x00 7. " [7] ,Initiator agent 7 status" "Not pending,Pending"
bitfld.long 0x00 6. " [6] ,Initiator agent 6 status" "Not pending,Pending"
textline " "
bitfld.long 0x00 5. " [5] ,Initiator agent 5 status" "Not pending,Pending"
bitfld.long 0x00 4. " [4] ,Initiator agent 4 status" "Not pending,Pending"
bitfld.long 0x00 3. " [3] ,Initiator agent 3 status" "Not pending,Pending"
bitfld.long 0x00 2. " [2] ,Initiator agent 2 status" "Not pending,Pending"
textline " "
bitfld.long 0x00 1. " [1] ,Initiator agent 1 status" "Not pending,Pending"
bitfld.long 0x00 0. " [0] ,Initiator agent 0 status" "Not pending,Pending"
rgroup.long 0x20++0x03
line.long 0x00 "SCMTASTAT,SCM Target Active Status Register"
bitfld.long 0x00 13. " TAST[13] ,Target agent 13 status" "Not pending,Pending"
bitfld.long 0x00 12. " [12] ,Target agent 12 status" "Not pending,Pending"
bitfld.long 0x00 11. " [11] ,Target agent 11 status" "Not pending,Pending"
bitfld.long 0x00 10. " [10] ,Target agent 10 status" "Not pending,Pending"
textline " "
bitfld.long 0x00 9. " [9] ,Target agent 9 status" "Not pending,Pending"
bitfld.long 0x00 8. " [8] ,Target agent 8 status" "Not pending,Pending"
bitfld.long 0x00 7. " [7] ,Target agent 7 status" "Not pending,Pending"
bitfld.long 0x00 6. " [6] ,Target agent 6 status" "Not pending,Pending"
textline " "
bitfld.long 0x00 5. " [5] ,Target agent 5 status" "Not pending,Pending"
bitfld.long 0x00 4. " [4] ,Target agent 4 status" "Not pending,Pending"
bitfld.long 0x00 3. " [3] ,Target agent 3 status" "Not pending,Pending"
bitfld.long 0x00 2. " [2] ,Target agent 2 status" "Not pending,Pending"
textline " "
bitfld.long 0x00 1. " [1] ,Target agent 1 status" "Not pending,Pending"
bitfld.long 0x00 0. " [0] ,Target agent 0 status" "Not pending,Pending"
width 0x0B
tree.end
tree "Interconnect (SDC MMR Registers)"
base ad:0xFA000000
width 22.
rgroup.long 0x00++0x03
line.long 0x00 "SDC_STATUS,SDC Status Register"
bitfld.long 0x00 4. " GLOBAL_ERROR ,One safety diagnostic checker has asserted an error" "No error,Error"
bitfld.long 0x00 3. " NT_OK ,Negative test OK status for self-test" "Failed,Passed"
bitfld.long 0x00 2. " NT_RUN ,Negative test on-going status" "Ended,On-going"
bitfld.long 0x00 1. " PT_OK ,Positive test OK status for self-test" "Failed,Passed"
bitfld.long 0x00 0. " PT_RUN ,Positive test on-going status" "Ended,On-going"
group.long 0x04++0x03
line.long 0x00 "SDC_CONTROL,SDC Control Register"
bitfld.long 0x00 0. " MASK_SOFT_RESET ,Enables or disables the self-test sequence to be launched by the SCM" "Enabled,Disabled"
textline " "
rgroup.long 0x08++0x17
line.long 0x00 "ERR_GENERIC_PARITY,Error Generic Parity Register"
bitfld.long 0x00 5. " ACP-M ,Error related to parity mismatch" "No error,Error"
bitfld.long 0x00 4. " R5F_CPU0 ,Error related to parity mismatch" "No error,Error"
bitfld.long 0x00 2. " DMA_PORTA ,Error related to parity mismatch" "No error,Error"
bitfld.long 0x00 1. " POM ,Error related to parity mismatch" "No error,Error"
bitfld.long 0x00 0. " PS_SCR_M ,Error related to parity mismatch" "No error,Error"
line.long 0x04 "ERR_UNEXPECTED_TRANS,Error Unexpected Transaction Register"
bitfld.long 0x04 5. " ACP-M ,Error related to unexpected transaction sent by the master" "No error,Error"
bitfld.long 0x04 4. " R5F_CPU0 ,Error related to unexpected transaction sent by the master" "No error,Error"
bitfld.long 0x04 2. " DMA_PORTA ,Error related to unexpected transaction sent by the master" "No error,Error"
bitfld.long 0x04 1. " POM ,Error related to unexpected transaction sent by the master" "No error,Error"
bitfld.long 0x04 0. " PS_SCR_M ,Error related to unexpected transaction sent by the master" "No error,Error"
line.long 0x08 "ERR_TRANS_ID,Error Transaction ID Register"
bitfld.long 0x08 5. " ACP-M ,Error related to mismatch on the transaction ID" "No error,Error"
bitfld.long 0x08 4. " R5F_CPU0 ,Error related to mismatch on the transaction ID" "No error,Error"
bitfld.long 0x08 2. " DMA_PORTA ,Error related to mismatch on the transaction ID" "No error,Error"
bitfld.long 0x08 1. " POM ,Error related to mismatch on the transaction ID" "No error,Error"
bitfld.long 0x08 0. " PS_SCR_M ,Error related to mismatch on the transaction ID" "No error,Error"
line.long 0x0C "ERR_TRANS_SIGNATURE,Error Transaction Signature Register"
bitfld.long 0x0C 5. " ACP-M ,Error related to mismatch on the transaction signature" "No error,Error"
bitfld.long 0x0C 4. " R5F_CPU0 ,Error related to mismatch on the transaction signature" "No error,Error"
bitfld.long 0x0C 2. " DMA_PORTA ,Error related to mismatch on the transaction signature" "No error,Error"
bitfld.long 0x0C 1. " POM ,Error related to mismatch on the transaction signature" "No error,Error"
bitfld.long 0x0C 0. " PS_SCR_M ,Error related to mismatch on the transaction signature" "No error,Error"
line.long 0x10 "ERR_TRANS_TYPE,Error Transaction Type Register"
bitfld.long 0x10 5. " ACP-M ,Error related to mismatch on the transaction type" "No error,Error"
bitfld.long 0x10 4. " R5F_CPU0 ,Error related to mismatch on the transaction type" "No error,Error"
bitfld.long 0x10 2. " DMA_PORTA ,Error related to mismatch on the transaction type" "No error,Error"
bitfld.long 0x10 1. " POM ,Error related to mismatch on the transaction type" "No error,Error"
bitfld.long 0x10 0. " PS_SCR_M ,Error related to mismatch on the transaction type" "No error,Error"
line.long 0x14 "ERR_USER_PARITY,Error User Parity Register"
bitfld.long 0x14 5. " ACP-M ,Error related to mismatch on the parity" "No error,Error"
bitfld.long 0x14 4. " R5F_CPU0 ,Error related to mismatch on the parity" "No error,Error"
bitfld.long 0x14 2. " DMA_PORTA ,Error related to mismatch on the parity" "No error,Error"
bitfld.long 0x14 1. " POM ,Error related to mismatch on the parity" "No error,Error"
bitfld.long 0x14 0. " PS_SCR_M ,Error related to mismatch on the parity" "No error,Error"
textline " "
rgroup.long 0x20++0x0B
line.long 0x00 "SERR_UNEXPECTED_MID,Slave Error Unexpected Master ID Register"
bitfld.long 0x00 6. " ACP-S_SLAVE ,Error related to mismatch on the master ID" "No error,Error"
bitfld.long 0x00 5. " R5F_CPU0_AXI_SLAVE ,Error related to mismatch on the master ID" "No error,Error"
bitfld.long 0x00 3. " EMIF_SLAVE ,Error related to mismatch on the master ID" "No error,Error"
textline " "
bitfld.long 0x00 2. " L2_FLASH_PORTA_SLAVE ,Error related to mismatch on the master ID" "No error,Error"
bitfld.long 0x00 1. " L2_FLASH_PORTB_SLAVE ,Error related to mismatch on the master ID" "No error,Error"
bitfld.long 0x00 0. " L2_SRAM_SLAVE ,Error related to mismatch on the master ID" "No error,Error"
line.long 0x04 "SERR_ADDR_DECODE,Slave Error Address Decode Register"
bitfld.long 0x04 6. " ACP-S_SLAVE ,Error related to mismatch on the most significant address bits" "No error,Error"
bitfld.long 0x04 5. " R5F_CPU0_AXI_SLAVE ,Error related to mismatch on the most significant address bits" "No error,Error"
bitfld.long 0x04 3. " EMIF_SLAVE ,Error related to mismatch on the most significant address bits" "No error,Error"
textline " "
bitfld.long 0x04 2. " L2_FLASH_PORTA_SLAVE ,Error related to mismatch on the most significant address bits" "No error,Error"
bitfld.long 0x04 1. " L2_FLASH_PORTB_SLAVE ,Error related to mismatch on the most significant address bits" "No error,Error"
bitfld.long 0x04 0. " L2_SRAM_SLAVE ,Error related to mismatch on the most significant address bits" "No error,Error"
line.long 0x08 "SERR_USER_PARITY,Slave Error User Parity Register"
bitfld.long 0x08 6. " ACP-S_SLAVE ,Error related to mismatch on the parity" "No error,Error"
bitfld.long 0x08 5. " R5F_CPU0_AXI_SLAVE ,Error related to mismatch on the parity" "No error,Error"
bitfld.long 0x08 3. " EMIF_SLAVE ,Error related to mismatch on the parity" "No error,Error"
textline " "
bitfld.long 0x08 2. " L2_FLASH_PORTA_SLAVE ,Error related to mismatch on the parity" "No error,Error"
bitfld.long 0x08 1. " L2_FLASH_PORTB_SLAVE ,Error related to mismatch on the parity" "No error,Error"
bitfld.long 0x08 0. " L2_SRAM_SLAVE ,Error related to mismatch on the parity" "No error,Error"
width 0x0B
tree.end
tree "PMM (Power Management Module)"
base ad:0xFFFF0000
width 18.
group.long 0x00++0x03
line.long 0x00 "LOGICPDPWRCTRL0,Logic Power Domain Control Register 0"
bitfld.long 0x00 24.--27. " LOGICPDON[0] ,Power domain PD2 state" "Active,Active,Active,Active,Active,Active,Active,Active,Active,,Off,Active,Active,Active,Active,Active"
bitfld.long 0x00 16.--19. " [1] ,Power domain PD3 state" "Active,Active,Active,Active,Active,Active,Active,Active,Active,,Off,Active,Active,Active,Active,Active"
bitfld.long 0x00 8.--11. " [2] ,Power domain PD4 state" "Active,Active,Active,Active,Active,Active,Active,Active,Active,,Off,Active,Active,Active,Active,Active"
bitfld.long 0x00 0.--3. " [3] ,Power domain PD5 state" "Active,Active,Active,Active,Active,Active,Active,Active,Active,,Off,Active,Active,Active,Active,Active"
group.long 0x04++0x03
line.long 0x00 "LOGICPDPWRCTRL1,Logic Power Domain Control Register 1"
bitfld.long 0x00 24.--27. " LOGICPDON[4] ,Power domain PD6 state" "Active,Active,Active,Active,Active,Active,Active,Active,Active,,Off,Active,Active,Active,Active,Active"
group.long 0x20++0x03
line.long 0x00 "PDCLKDISREG,Power Domain Clock Disable Register SET/CLR"
setclrfld.long 0x00 4. 0x04 4. 0x08 4. " PDCLK_DIS_SET/CLR[4] ,Clocks to logic power domain PD6 disable" "No,Yes"
setclrfld.long 0x00 3. 0x04 3. 0x08 3. " [3] ,Clocks to logic power domain PD5 disable" "No,Yes"
setclrfld.long 0x00 2. 0x04 2. 0x08 2. " [2] ,Clocks to logic power domain PD4 disable" "No,Yes"
setclrfld.long 0x00 1. 0x04 1. 0x08 1. " [1] ,Clocks to logic power domain PD3 disable" "No,Yes"
setclrfld.long 0x00 0. 0x04 0. 0x08 0. " [0] ,Clocks to logic power domain PD2 disable" "No,Yes"
textline " "
rgroup.long 0x40++0x03
line.long 0x00 "LOGICPDPWRSTAT0,Logic Power Domain PD2 Power Status Register 0"
bitfld.long 0x00 24. " LOGIC_IN_TRANS0 ,Logic in transition status for power domain PD2" "Active/off,Power-down/up"
bitfld.long 0x00 16. " MEM_IN_TRANS0 ,Memory in transition status for power domain PD2" "Active/off,Power-down/up"
bitfld.long 0x00 8. " DOMAIN_ON0 ,Current state of power domain PD2" "Off,Active"
bitfld.long 0x00 0.--1. " LOGICPDPWR_STAT0 ,Logic power domain PD2 power state" "Off,Idle,,Active"
rgroup.long 0x44++0x03
line.long 0x00 "LOGICPDPWRSTAT1,Logic Power Domain PD3 Power Status Register 1"
bitfld.long 0x00 24. " LOGIC_IN_TRANS1 ,Logic in transition status for power domain PD3" "Active/off,Power-down/up"
bitfld.long 0x00 16. " MEM_IN_TRANS1 ,Memory in transition status for power domain PD3" "Active/off,Power-down/up"
bitfld.long 0x00 8. " DOMAIN_ON1 ,Current state of power domain PD3" "Off,Active"
bitfld.long 0x00 0.--1. " LOGICPDPWR_STAT1 ,Logic power domain PD3 power state" "Off,Idle,,Active"
rgroup.long 0x48++0x03
line.long 0x00 "LOGICPDPWRSTAT2,Logic Power Domain PD4 Power Status Register 2"
bitfld.long 0x00 24. " LOGIC_IN_TRANS2 ,Logic in transition status for power domain PD4" "Active/off,Power-down/up"
bitfld.long 0x00 16. " MEM_IN_TRANS2 ,Memory in transition status for power domain PD4" "Active/off,Power-down/up"
bitfld.long 0x00 8. " DOMAIN_ON2 ,Current state of power domain PD4" "Off,Active"
bitfld.long 0x00 0.--1. " LOGICPDPWR_STAT2 ,Logic power domain PD4 power state" "Off,Idle,,Active"
rgroup.long 0x4C++0x03
line.long 0x00 "LOGICPDPWRSTAT3,Logic Power Domain PD5 Power Status Register 3"
bitfld.long 0x00 24. " LOGIC_IN_TRANS3 ,Logic in transition status for power domain PD5" "Active/off,Power-down/up"
bitfld.long 0x00 16. " MEM_IN_TRANS3 ,Memory in transition status for power domain PD5" "Active/off,Power-down/up"
bitfld.long 0x00 8. " DOMAIN_ON3 ,Current state of power domain PD5" "Off,Active"
bitfld.long 0x00 0.--1. " LOGICPDPWR_STAT3 ,Logic power domain PD5 power state" "Off,Idle,,Active"
rgroup.long 0x50++0x03
line.long 0x00 "LOGICPDPWRSTAT4,Logic Power Domain PD6 Power Status Register 4"
bitfld.long 0x00 24. " LOGIC_IN_TRANS4 ,Logic in transition status for power domain PD6" "Active/off,Power-down/up"
bitfld.long 0x00 16. " MEM_IN_TRANS4 ,Memory in transition status for power domain PD6" "Active/off,Power-down/up"
bitfld.long 0x00 8. " DOMAIN_ON4 ,Current state of power domain PD6" "Off,Active"
bitfld.long 0x00 0.--1. " LOGICPDPWR_STAT4 ,Logic power domain PD6 power state" "Off,Idle,,Active"
textline " "
group.long 0xA0++0x03
line.long 0x00 "GLOBALCTRL1,Global Control Register 1"
bitfld.long 0x00 8. " PMCTRL_PWRDN ,PMC/PSCON power down bit" "Powered up,Powered down"
bitfld.long 0x00 0. " AUTO_CLK_WAKE_ENA ,Automatic clock enable on wake up" "Disabled,Enabled"
rgroup.long 0xA8++0x03
line.long 0x00 "GLOBALSTAT,Global Status Register"
bitfld.long 0x00 0. " PMCTRL_IDLE ,State of PMC and all PSCONs" "Busy,Idle"
group.long 0xAC++0x03
line.long 0x00 "PRCKEYREG,PSCON Diagnostic Compare Key Register"
bitfld.long 0x00 0.--3. " MKEY ,Diagnostic PSCON mode key" "Lock step,Lock step,Lock step,Lock step,Lock step,Lock step,Self test,Lock step,Lock step,Error forcing,Lock step,Lock step,Lock step,Lock step,Lock step,Self test error forcing"
textline " "
group.long 0xB0++0x03
line.long 0x00 "LPDDCSTAT1,Logic PD PSCON Diagnostic Compare Status Register 1"
eventfld.long 0x00 20. " LCMPE[4] ,Logic power domain compare error for PD6" "No error,Error"
eventfld.long 0x00 19. " [3] ,Logic power domain compare error for PD5" "No error,Error"
eventfld.long 0x00 18. " [2] ,Logic power domain compare error for PD4" "No error,Error"
eventfld.long 0x00 17. " [1] ,Logic power domain compare error for PD3" "No error,Error"
eventfld.long 0x00 16. " [0] ,Logic power domain compare error for PD2" "No error,Error"
textline " "
rbitfld.long 0x00 4. " LSTC[4] ,Logic power domain self test complete for PD6" "Not completed,Completed"
rbitfld.long 0x00 3. " [3] ,Logic power domain self test complete for PD5" "Not completed,Completed"
rbitfld.long 0x00 2. " [2] ,Logic power domain self test complete for PD4" "Not completed,Completed"
rbitfld.long 0x00 1. " [1] ,Logic power domain self test complete for PD3" "Not completed,Completed"
rbitfld.long 0x00 0. " [0] ,Logic power domain self test complete for PD2" "Not completed,Completed"
rgroup.long 0xB4++0x03
line.long 0x00 "LPDDCSTAT2,Logic PD PSCON Diagnostic Compare Status Register 2"
bitfld.long 0x00 20. " LSTET[4] ,Logic power domain self test error type for PD6" "During match test,During mismatch test"
bitfld.long 0x00 19. " [3] ,Logic power domain self test error type for PD5" "During match test,During mismatch test"
bitfld.long 0x00 18. " [2] ,Logic power domain self test error type for PD4" "During match test,During mismatch test"
bitfld.long 0x00 17. " [1] ,Logic power domain self test error type for PD3" "During match test,During mismatch test"
bitfld.long 0x00 16. " [0] ,Logic power domain self test error type for PD2" "During match test,During mismatch test"
textline " "
bitfld.long 0x00 4. " LSTE[4] ,Logic power domain self test error for PD6" "Passed,Failed"
bitfld.long 0x00 3. " [3] ,Logic power domain self test error for PD5" "Passed,Failed"
bitfld.long 0x00 2. " [2] ,Logic power domain self test error for PD4" "Passed,Failed"
bitfld.long 0x00 1. " [1] ,Logic power domain self test error for PD3" "Passed,Failed"
bitfld.long 0x00 0. " [0] ,Logic power domain self test error for PD2" "Passed,Failed"
rgroup.long 0xC0++0x03
line.long 0x00 "ISODIAGSTAT,Isolation Diagnostic Status Register"
bitfld.long 0x00 4. " ISO_DIAG[4] ,Isolation diagnostic for PD6" "Enabled,Disabled"
bitfld.long 0x00 3. " [3] ,Isolation diagnostic for PD5" "Enabled,Disabled"
bitfld.long 0x00 2. " [2] ,Isolation diagnostic for PD4" "Enabled,Disabled"
bitfld.long 0x00 1. " [1] ,Isolation diagnostic for PD3" "Enabled,Disabled"
bitfld.long 0x00 0. " [0] ,Isolation diagnostic for PD2" "Enabled,Disabled"
width 0x0B
tree.end
tree "IOMM (I/O Multiplexing and Control Module)"
base ad:0xFFFF1C00
width 24.
rgroup.long 0x00++0x03
line.long 0x00 "REVISION_REG,Module Revision Register"
bitfld.long 0x00 30.--31. " REV_SCHEME ,Revision scheme" "0,1,2,3"
hexmask.long.word 0x00 16.--27. 1. " REV_MODULE ,Module id"
textline " "
bitfld.long 0x00 11.--15. " REV_RTL ,RTL revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 8.--10. " REV_MAJOR ,Major revision" "0,1,2,3,4,5,6,7"
textline " "
bitfld.long 0x00 6.--7. " REV_CUSTOM ,Custom revision" "0,1,2,3"
bitfld.long 0x00 0.--5. " REV_MINOR ,Minor revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
rgroup.long 0x20++0x03
line.long 0x00 "BOOT_REG,Boot Config Register 0"
bitfld.long 0x00 0. " ENDIAN ,Device endianness" "Little endian,Big endian"
group.long 0x38++0x03
line.long 0x00 "KICK_REG0,Kicker Register 0"
group.long 0x3C++0x03
line.long 0x00 "KICK_REG1,Kicker Register 1"
group.long 0xE0++0x03
line.long 0x00 "ERR_RAW_STATUS_REG,Error Raw Status/set Register"
bitfld.long 0x00 1. " ADDR_ERR ,Addressing error status and error signaling enable" "No error,Error"
bitfld.long 0x00 0. " PROT_ERR ,Protection error status and error signaling enable" "No error,Error"
group.long 0xE4++0x03
line.long 0x00 "ERR_ENABLED_STATUS_REG,Error Enabled Status/clear Register"
setclrfld.long 0x00 1. 0x04 1. 0x08 1. " ADDR_ERR_SET/CLR ,Addressing error signaling enable status and status clear" "Disabled,Enabled"
setclrfld.long 0x00 0. 0x04 0. 0x08 0. " PROT_ERR_SET/CLR ,Protection error signaling enable status and status clear" "Disabled,Enabled"
group.long 0xF4++0x03
line.long 0x00 "FAULT_ADDRESS_REG,Fault Address Register"
hexmask.long.word 0x00 0.--8. 1. " FAULT_ADDR ,Fault address"
rgroup.long 0xF8++0x03
line.long 0x00 "FAULT_STATUS_REG,Fault Status Register"
bitfld.long 0x00 24.--27. " FAULT_ID ,Faulting transaction ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.byte 0x00 16.--23. 1. " FAULT_MSTID ,Id of master that initiated the faulting transaction"
textline " "
bitfld.long 0x00 9.--12. " FAULT_PRIVID ,Faulting privilege id" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 7. " FAULT_NS ,Fault: Non-secure access detected" "Not detected,Detected"
textline " "
bitfld.long 0x00 0.--5. " FAULT_TYPE ,Type of fault detected" "No fault,User execute fault,User write fault,,User read fault,,,,Supervisor execute fault,,,,,,,,Supervisor write fault,,,,,,,,,,,,,,,,Supervisor read fault,?..."
group.long 0xFC++0x03
line.long 0x00 "FAULT_CLEAR_REG,Fault Clear Register"
bitfld.long 0x00 0. " FAULT_CLEAR ,Fault clear" "No effect,Clear"
width 10.
tree "Output Pin Multiplexing Control Registers"
group.long 0x110++0x13
line.long 0x00 "PINMMR0,PINMMR0 Control Register"
bitfld.long 0x00 24.--26. " C4 ,Pin function for C4" "EMIF_ADDR[06],EMIF_ADDR[06],RTP_DATA[13],,N2HET2[11],?..."
bitfld.long 0x00 16.--18. " D5 ,Pin function for D5" "EMIF_ADDR[01],EMIF_ADDR[01],,,N2HET2[03],?..."
bitfld.long 0x00 8.--10. " D4 ,Pin function for D4" "EMIF_ADDR[00],EMIF_ADDR[00],,,N2HET2[01],?..."
bitfld.long 0x00 0.--5. " N19 ,Pin function for N19" "AD1EVT,AD1EVT,,,MII_RX_ER,,,,RMII_RX_ER,,,,,,,,,,,,,,,,,,,,,,,,NTZ1_1,?..."
line.long 0x04 "PINMMR1,PINMMR1 Control Register"
bitfld.long 0x04 24.--25. " C8 ,Pin function for pin C8" "EMIF_ADDR[10],EMIF_ADDR[10],RTP_DATA[09],?..."
bitfld.long 0x04 16.--17. " C7 ,Pin function for pin C7" "EMIF_ADDR[09],EMIF_ADDR[09],RTP_DATA[10],?..."
bitfld.long 0x04 8.--10. " C6 ,Pin function for C6" "EMIF_ADDR[08],EMIF_ADDR[08],RTP_DATA[11],,N2HET2[15],?..."
bitfld.long 0x04 0.--2. " C5 ,Pin function for C5" "EMIF_ADDR[07],EMIF_ADDR[07],RTP_DATA[12],,N2HET2[13],?..."
line.long 0x08 "PINMMR2,PINMMR2 Control Register"
bitfld.long 0x08 24.--25. " C12 ,Pin function for pin C12" "EMIF_ADDR[14],EMIF_ADDR[14],RTP_DATA[04],?..."
bitfld.long 0x08 16.--17. " C11 ,Pin function for pin C11" "EMIF_ADDR[13],EMIF_ADDR[13],RTP_DATA[05],?..."
bitfld.long 0x08 8.--9. " C10 ,Pin function for pin C10" "EMIF_ADDR[12],EMIF_ADDR[12],RTP_DATA[06],?..."
bitfld.long 0x08 0.--1. " C9 ,Pin function for pin C9" "EMIF_ADDR[11],EMIF_ADDR[11],RTP_DATA[08],?..."
sif cpuis("RM57L843-ZWT")
line.long 0x0C "PINMMR3,PINMMR3 Control Register"
bitfld.long 0x0C 24.--25. " D15 ,Pin function for pin D15" "EMIF_ADDR[18],EMIF_ADDR[18],RTP_DATA[00],?..."
bitfld.long 0x0C 16.--17. " C14 ,Pin function for pin C14" "EMIF_ADDR[17],EMIF_ADDR[17],RTP_DATA[01],?..."
bitfld.long 0x0C 8.--9. " D14 ,Pin function for pin D14" "EMIF_ADDR[16],EMIF_ADDR[16],RTP_DATA[02],?..."
bitfld.long 0x0C 0.--1. " C13 ,Pin function for pin C13" "EMIF_ADDR[15],EMIF_ADDR[15],RTP_DATA[03],?..."
else
line.long 0x0C "PINMMR3,PINMMR3 Control Register"
bitfld.long 0x0C 24.--25. " C15 ,Pin function for pin C15" "EMIF_ADDR[18],EMIF_ADDR[18],RTP_DATA[00],?..."
bitfld.long 0x0C 16.--17. " C14 ,Pin function for pin C14" "EMIF_ADDR[17],EMIF_ADDR[17],RTP_DATA[01],?..."
bitfld.long 0x0C 8.--9. " C13 ,Pin function for pin C13" "EMIF_ADDR[16],EMIF_ADDR[16],RTP_DATA[02],?..."
bitfld.long 0x0C 0.--1. " C12 ,Pin function for pin C12" "EMIF_ADDR[15],EMIF_ADDR[15],RTP_DATA[03],?..."
endif
line.long 0x10 "PINMMR4,PINMMR4 Control Register"
bitfld.long 0x10 16.--17. " C17 ,Pin function for pin C17" "EMIF_ADDR[21],EMIF_ADDR[21],RTP_CLK,?..."
bitfld.long 0x10 8.--9. " C16 ,Pin function for pin C16" "EMIF_ADDR[20],EMIF_ADDR[20],RTP_NSYNC,?..."
bitfld.long 0x10 0.--1. " C15 ,Pin function for pin C15" "EMIF_ADDR[19],EMIF_ADDR[19],RTP_NENA,?..."
group.long 0x130++0x27
line.long 0x00 "PINMMR8,PINMMR8 Control Register"
bitfld.long 0x00 24.--26. " D16 ,Pin function for D16" "EMIF_BA[1],EMIF_BA[1],,,N2HET2[05],?..."
line.long 0x04 "PINMMR9,PINMMR9 Control Register"
bitfld.long 0x04 24.--26. " L17 ,Pin function for L17" "EMIF_NCS[2],EMIF_NCS[2],,,GIOB[4],?..."
bitfld.long 0x04 16.--18. " N17 ,Pin function for N17" "EMIF_NCS[0],EMIF_NCS[0],RTP_DATA[15],,N2HET2[07],?..."
bitfld.long 0x04 8.--10. " R4 ,Pin function for R4" "EMIF_NCAS,EMIF_NCAS,,,GIOB[3],?..."
bitfld.long 0x04 0.--2. " K3 ,Pin function for K3" ",,EMIF_CLK,,ECLK2,?..."
line.long 0x08 "PINMMR10,PINMMR1 Control Register"
bitfld.long 0x08 24.--26. " P3 ,Pin function for P3" "EMIF_NWAIT,EMIF_NWAIT,,,GIOB[7],?..."
bitfld.long 0x08 16.--18. " R3 ,Pin function for R3" "EMIF_NRAS,EMIF_NRAS,,,GIOB[6],?..."
bitfld.long 0x08 8.--10. " M17 ,Pin function for M17" "EMIF_NCSL[4],EMIF_NCSL[4],RTP_DATA[07],,GIOB[5],?..."
bitfld.long 0x08 0.--2. " K17 ,Pin function for K17" "EMIF_NCS[3],EMIF_NCS[3],RTP_DATA[14],,N2HET2[09],?..."
line.long 0x0C "PINMMR11,PINMMR11 Control Register"
bitfld.long 0x0C 24.--25. " E7 ,Pin function for pin E7" "ETMDATA[10],ETMDATA[10],EMIF_ADDR[03],?..."
bitfld.long 0x0C 16.--17. " E8 ,Pin function for pin E8" "ETMDATA[09],ETMDATA[09],EMIF_ADDR[04],?..."
bitfld.long 0x0C 8.--9. " E9 ,Pin function for pin E9" "ETMDATA[08],ETMDATA[08],EMIF_ADDR[05],?..."
bitfld.long 0x0C 0.--1. " D17 ,Pin function for pin D17" "EMIF_NWE,EMIF_NWE,EMIF_RNW,?..."
line.long 0x10 "PINMMR12,PINMMR12 Control Register"
bitfld.long 0x10 24.--25. " E11 ,Pin function for pin E11" "ETMDATA[14],ETMDATA[14],EMIF_NDQM[1],?..."
bitfld.long 0x10 16.--17. " E12 ,Pin function for pin E12" "ETMDATA[13],ETMDATA[13],EMIF_NOE,?..."
bitfld.long 0x10 8.--9. " E13 ,Pin function for pin E13" "ETMDATA[12],ETMDATA[12],EMIF_BA[0],?..."
bitfld.long 0x10 0.--1. " E6 ,Pin function for pin E6" "ETMDATA[11],ETMDATA[11],EMIF_ADDR[02],?..."
line.long 0x14 "PINMMR13,PINMMR13 Control Register"
bitfld.long 0x14 24.--25. " M15 ,Pin function for pin M15" "ETMDATA[18],ETMDATA[18],EMIF_DATA[02],?..."
bitfld.long 0x14 16.--17. " L15 ,Pin function for pin L15" "ETMDATA[17],ETMDATA[17],EMIF_DATA[01],?..."
bitfld.long 0x14 8.--9. " K15 ,Pin function for pin K15" "ETMDATA[16],ETMDATA[16],EMIF_DATA[00],?..."
bitfld.long 0x14 0.--1. " E10 ,Pin function for pin E10" "ETMDATA[15],ETMDATA[15],EMIF_NDQM[0],?..."
line.long 0x18 "PINMMR14,PINMMR14 Control Register"
bitfld.long 0x18 24.--25. " G5 ,Pin function for pin G5" "ETMDATA[22],ETMDATA[22],EMIF_DATA[06],?..."
bitfld.long 0x18 16.--17. " F5 ,Pin function for pin F5" "ETMDATA[21],ETMDATA[21],EMIF_DATA[05],?..."
bitfld.long 0x18 8.--9. " E5 ,Pin function for pin E5" "ETMDATA[20],ETMDATA[20],EMIF_DATA[04],?..."
bitfld.long 0x18 0.--1. " N15 ,Pin function for pin N15" "ETMDATA[19],ETMDATA[19],EMIF_DATA[03],?..."
sif cpuis("RM57L843-ZWT")
line.long 0x1C "PINMMR15,PINMMR15 Control Register"
bitfld.long 0x1C 24.--26. " N5 ,Pin function for N5" "ETMDATA[26],ETMDATA[26],EMIF_DATA[10],,N2HET2[26],?..."
bitfld.long 0x1C 16.--19. " M5 ,Pin function for M5" "ETMDATA[25],ETMDATA[25],EMIF_DATA[09],,N2HET2[25],,,,MIBSPI5ICS[5],?..."
bitfld.long 0x1C 8.--11. " L5 ,Pin function for L5" "ETMDATA[24],ETMDATA[24],EMIF_DATA[08],,N2HET2[24],,,,MIBSPI5ICS[4],?..."
bitfld.long 0x1C 0.--1. " K5 ,Pin function for pin K5" "ETMDATA[23],ETMDATA[23],EMIF_DATA[07],?..."
line.long 0x20 "PINMMR16,PINMMR16 Control Register"
bitfld.long 0x20 24.--27. " R7 ,Pin function for R7" "ETMDATA[30],ETMDATA[30],EMIF_DATA[14],,N2HET2[30],,,,GIOA[3],?..."
bitfld.long 0x20 16.--19. " R6 ,Pin function for R6" "ETMDATA[29],ETMDATA[29],EMIF_DATA[13],,N2HET2[29],,,,GIOA[1],?..."
bitfld.long 0x20 8.--11. " R5 ,Pin function for R5" "ETMDATA[28],ETMDATA[28],EMIF_DATA[12],,N2HET2[28],,,,GIOA[0],?..."
bitfld.long 0x20 0.--2. " P5 ,Pin function for P5" "ETMDATA[27],ETMDATA[27],EMIF_DATA[11],,N2HET2[27],?..."
else
line.long 0x1C "PINMMR15,PINMMR15 Control Register"
bitfld.long 0x1C 24.--26. " N5 ,Pin function for N5" "ETMDATA[26],ETMDATA[26],EMIF_DATA[10],,ETMDATA[26],?..."
bitfld.long 0x1C 16.--19. " M5 ,Pin function for M5" "ETMDATA[25],ETMDATA[25],EMIF_DATA[09],,ETMDATA[25],,,,MIBSPI5ICS[5],?..."
bitfld.long 0x1C 8.--11. " L5 ,Pin function for L5" "ETMDATA[24],ETMDATA[24],EMIF_DATA[08],,ETMDATA[24],,,,MIBSPI5ICS[4],?..."
bitfld.long 0x1C 0.--1. " K5 ,Pin function for pin K5" "ETMDATA[23],ETMDATA[23],EMIF_DATA[07],?..."
line.long 0x20 "PINMMR16,PINMMR16 Control Register"
bitfld.long 0x20 24.--27. " R7 ,Pin function for R7" "ETMDATA[30],ETMDATA[30],EMIF_DATA[14],,N2HET2[30],,,,GIO[3],?..."
bitfld.long 0x20 16.--19. " R6 ,Pin function for R6" "ETMDATA[29],ETMDATA[29],EMIF_DATA[13],,N2HET2[29],,,,GIO[1],?..."
bitfld.long 0x20 8.--11. " R5 ,Pin function for R5" "ETMDATA[28],ETMDATA[28],EMIF_DATA[12],,N2HET2[28],,,,GIO[0],?..."
bitfld.long 0x20 0.--2. " P5 ,Pin function for P5" "ETMDATA[27],ETMDATA[27],EMIF_DATA[11],,N2HET2[27],?..."
endif
line.long 0x24 "PINMMR17,PINMMR17 Control Register"
bitfld.long 0x24 24.--27. " R11 ,Pin function for R11" "ETMTRACECTL,ETMTRACECTL,,,,,,,GIOA[7],?..."
bitfld.long 0x24 16.--19. " R10 ,Pin function for R10" "ETMTRACECLKOUT,ETMTRACECLKOUT,,,,,,,GIOA[6],?..."
bitfld.long 0x24 8.--11. " R9 ,Pin function for R9" "ETMTRACECLKIN,ETMTRACECLKIN,EXTCLKIN2,,,,,,GIOA[5],?..."
bitfld.long 0x24 0.--3. " R8 ,Pin function for R8" "ETMDATA[31],ETMDATA[31],EMIF_DATA[15],,N2HET2[31],,,,GIOA[4],?..."
sif !cpuis("RM57L843-ZWT")
group.long 0x158++0x03
line.long 0x00 "PINMMR18,PINMMR18 Control Register"
bitfld.long 0x00 24.--27. " B9 ,Pin function for B9" "FRAYTXEN2,FRAYTXEN2,,,,,,,GIOB[2],?..."
bitfld.long 0x00 16.--19. " B16 ,Pin function for B16" "FRAYTXEN1,FRAYTXEN1,,,,,,,GIOB[1],?..."
bitfld.long 0x00 8.--11. " B8 ,Pin function for B8" "FRAYTX2,FRAYTX2,,,,,,,GIOB[0],?..."
bitfld.long 0x00 0.--3. " B15 ,Pin function for B15" "FRAYTX1,FRAYTX1,,,,,,,GIOA[2],?..."
endif
group.long 0x15C++0x4B
line.long 0x00 "PINMMR19,PINMMR19 Control Register"
bitfld.long 0x00 24.--29. " H3 ,Pin function for H3" "GIOA[6],GIOA[6],,,N2HET2[04],,,,,,,,,,,,,,,,,,,,,,,,,,,,EPWM1B,?..."
bitfld.long 0x00 16.--21. " B5 ,Pin function for B5" "GIOA[5],GIOA[5],,,,,,,EXTCLKIN,,,,,,,,,,,,,,,,,,,,,,,,EPWM1A,?..."
bitfld.long 0x00 8.--10. " E1 ,Pin function for E1" "GIOA[3],GIOA[3],,,N2HET2[02],?..."
bitfld.long 0x00 0.--5. " C1 ,Pin function for C1" "GIOA[2],GIOA[2],,,N2HET2[00],,,,,,,,,,,,,,,,,,,,,,,,,,,,EQEP2I,?..."
line.long 0x04 "PINMMR20,PINMMR20 Control Register"
bitfld.long 0x04 24.--25. " J2 ,Pin function for pin J2" "GIOB[6],GIOB[6],Nerror1,?..."
bitfld.long 0x04 16.--19. " W10 ,Pin function for W10" "GIOB[3],GIOB[3],,,,,,,DCAN4RX,?..."
bitfld.long 0x04 8.--11. " F2 ,Pin function for F2" "GIOB[2],GIOB[2],,,,,,,DCAN4TX,?..."
bitfld.long 0x04 0.--5. " M1 ,Pin function for M1" "GIOA[7],GIOA[7],,,N2HET2[06],,,,,,,,,,,,,,,,,,,,,,,,,,,,EPWM2A,?..."
line.long 0x08 "PINMMR21,PINMMR21 Control Register"
bitfld.long 0x08 24.--27. " G3 ,Pin function for G3" "MIBSPI1NCS[2],MIBSPI1NCS[2],,,MDIO,,,,N2HET1[19],?..."
bitfld.long 0x08 16.--21. " F3 ,Pin function for F3" "MIBSPI1NCS[1],MIBSPI1NCS[1],,,MII_COL,,,,N2HET1[17],,,,,,,,,,,,,,,,,,,,,,,,EQEP1S,?..."
bitfld.long 0x08 8.--13. " R2 ,Pin function for R2" "MIBSPI1NCS[0],MIBSPI1NCS[0],MIBSPI1SOMI[1],,MII_TXD[2],,,,,,,,,,,,,,,,,,,,,,,,,,,,ECAP6,?..."
sif cpuis("RM57L843-ZWT")
bitfld.long 0x08 0.--5. " F1 ,Pin function for F1" "GIOB[7],GIOB[7],,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,NTZ1_2,?..."
else
bitfld.long 0x08 0.--5. " F1 ,Pin function for F1" "GIOB[7],GIOB[7],NERROR2,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,NTZ1_2,?..."
endif
line.long 0x0C "PINMMR22,PINMMR22 Control Register"
bitfld.long 0x0C 24.--29. " V10 ,Pin function for V10" "MIBSPI3NCS[0],MIBSPI3NCS[0],AD2EVT,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,EQEP1I,?..."
sif cpuis("RM57L843-ZWT")
bitfld.long 0x0C 16.--21. " V9 ,Pin function for V9" "MIBSPI3CLK,MIBSPI3CLK,ADEXT_SEL[01],,,,,,,,,,,,,,,,,,,,,,,,,,,,,,EQEP1A,?..."
else
bitfld.long 0x0C 16.--21. " V9 ,Pin function for V9" "MIBSPI3CLK,MIBSPI3CLK,EXT_SEL[01],,,,,,,,,,,,,,,,,,,,,,,,,,,,,,EQEP1A,?..."
endif
textline " "
bitfld.long 0x0C 8.--13. " G19 ,Pin function for G19" "MIBSPI1NENA,MIBSPI1NENA,,,MII_RXD[2],,,,N2HET1[23],,,,,,,,,,,,,,,,,,,,,,,,ECAP4,?..."
bitfld.long 0x0C 0.--5. " J3 ,Pin function for J3" "MIBSPI1NCS[3],MIBSPI1NCS[3],,,,,,,N2HET1[21],,,,,,,,,,,,,,,,,,,,,,,,NTZ1_3,?..."
line.long 0x10 "PINMMR23,PINMMR23 Control Register"
bitfld.long 0x10 24.--29. " W9 ,Pin function for W9" "MIBSPI3NENA,MIBSPI3NENA,MIBSPI3NCS[5],,,,,,N2HET1[31],,,,,,,,,,,,,,,,,,,,,,,,EQEP1B,?..."
bitfld.long 0x10 16.--21. " C3 ,Pin function for C3" "MIBSPI3NCS[3],MIBSPI3NCS[3],I2C1_SCL,,,,,,N2HET1[29],,,,,,,,,,,,,,,,,,,,,,,,NTZ1_1,?..."
bitfld.long 0x10 8.--13. " B2 ,Pin function for B2" "MIBSPI3NCS[2],MIBSPI3NCS[2],I2C1_SDA,,,,,,N2HET1[27],,,,,,,,,,,,,,,,,,,,,,,,NTZ1_2,?..."
bitfld.long 0x10 0.--3. " V5 ,Pin function for V5" "MIBSPI3NCS[1],MIBSPI3NCS[1],,,MDCLK,,,,N2HET1[25],?..."
line.long 0x14 "PINMMR24,PINMMR24 Control Register"
bitfld.long 0x14 24.--29. " E19 ,Pin function for E19" "MIBSPI5NCS[0],MIBSPI5NCS[0],DMM_DATA[05],,,,,,,,,,,,,,,,,,,,,,,,,,,,,,EPWM4A,?..."
bitfld.long 0x14 16.--19. " H19 ,Pin function for H19" "MIBSPI5CLK,MIBSPI5CLK,DMM_DATA[04],,MII_TXEN,,,,RMII_TXEN,?..."
sif cpuis("RM57L843-ZWT")
bitfld.long 0x14 8.--13. " V8 ,Pin function for V8" "MIBSPI3SOMI,MIBSPI3SOMI,AD1EXT_ENA,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,ECAP2,?..."
bitfld.long 0x14 0.--5. " W8 ,Pin function for W8" "MIBSPI3SIMO,MIBSPI3SIMO,AD1EXT_SEL[00],,,,,,,,,,,,,,,,,,,,,,,,,,,,,,ECAP3,?..."
else
bitfld.long 0x14 8.--13. " V8 ,Pin function for V8" "MIBSPI3SOMI,MIBSPI3SOMI,EXT_ENA,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,ECAP2,?..."
bitfld.long 0x14 0.--5. " W8 ,Pin function for W8" "MIBSPI3SIMO,MIBSPI3SIMO,EXT_SEL[00],,,,,,,,,,,,,,,,,,,,,,,,,,,,,,ECAP3,?..."
endif
line.long 0x18 "PINMMR25,PINMMR25 Control Register"
bitfld.long 0x18 24.--29. " H18 ,Pin function for H18" "MIBSPI5NENA,MIBSPI5NENA,DMM_DATA[07],,MII_RXD[3],,,,,,,,,,,,,,,,,,,,,,,,,,,,ECAP5,?..."
bitfld.long 0x18 16.--17. " T12 ,Pin function for pin T12" "MIBSPI5NCS[3],MIBSPI5NCS[3],DMM_DATA[03],?..."
bitfld.long 0x18 8.--9. " W6 ,Pin function for pin W6" "MIBSPI5NCS[2],MIBSPI5NCS[2],DMM_DATA[02],?..."
bitfld.long 0x18 0.--1. " B6 ,Pin function for pin B6" "MIBSPI5NCS[1],MIBSPI5NCS[1],DMM_DATA[06],?..."
line.long 0x1C "PINMMR26,PINMMR26 Control Register"
sif cpuis("RM57L843-ZWT")
bitfld.long 0x1C 24.--28. " G17 ,Pin function for G17" "MIBSPI5SIMO[3],MIBSPI5SIMO[3],DMM_DATA[11],,I2C2_SDA,,,,,,,,,,,,AD1EXT_SEL[02],?..."
bitfld.long 0x1C 16.--20. " H17 ,Pin function for H17" "MIBSPI5SIMO[2],MIBSPI5SIMO[2],DMM_DATA[10],,,,,,,,,,,,,,AD1EXT_SEL[01],?..."
bitfld.long 0x1C 8.--12. " E16 ,Pin function for E16" "MIBSPI5SIMO[1],MIBSPI5SIMO[1],DMM_DATA[09],,,,,,,,,,,,,,AD1EXT_SEL[00],?..."
else
bitfld.long 0x1C 24.--28. " G17 ,Pin function for G17" "MIBSPI5SIMO[3],MIBSPI5SIMO[3],DMM_DATA[11],,I2C2_SDA,,,,,,,,,,,,EXT_SEL[02],?..."
bitfld.long 0x1C 16.--20. " H17 ,Pin function for H17" "MIBSPI5SIMO[2],MIBSPI5SIMO[2],DMM_DATA[10],,,,,,,,,,,,,,EXT_SEL[01],?..."
bitfld.long 0x1C 8.--12. " E16 ,Pin function for E16" "MIBSPI5SIMO[1],MIBSPI5SIMO[1],DMM_DATA[09],,,,,,,,,,,,,,EXT_SEL[00],?..."
endif
bitfld.long 0x1C 0.--3. " J19 ,Pin function for J19" "MIBSPI5SIMO[0],MIBSPI5SIMO[0],DMM_DATA[08],,MII_TXD[1],,,,RMII_TXD[1],?..."
line.long 0x20 "PINMMR27,PINMMR27 Control Register"
sif cpuis("RM57L843-ZWT")
bitfld.long 0x20 24.--28. " G16 ,Pin function for G16" "MIBSPI5SOMI[3],MIBSPI5SOMI[3],DMM_DATA[15],,I2C2_SCL,,,,,,,,,,,,AD1EXT_ENA,?..."
bitfld.long 0x20 16.--20. " H16 ,Pin function for H16" "MIBSPI5SOMI[2],MIBSPI5SOMI[2],DMM_DATA[14],,,,,,,,,,,,,,AD1EXT_SEL[04],?..."
bitfld.long 0x20 8.--12. " E17 ,Pin function for E17" "MIBSPI5SOMI[1],MIBSPI5SOMI[1],DMM_DATA[13],,,,,,,,,,,,,,AD1EXT_SEL[03],?..."
else
bitfld.long 0x20 24.--28. " G16 ,Pin function for G16" "MIBSPI5SOMI[3],MIBSPI5SOMI[3],DMM_DATA[15],,I2C2_SCL,,,,,,,,,,,,EXT_ENA,?..."
bitfld.long 0x20 16.--20. " H16 ,Pin function for H16" "MIBSPI5SOMI[2],MIBSPI5SOMI[2],DMM_DATA[14],,,,,,,,,,,,,,EXT_SEL[04],?..."
bitfld.long 0x20 8.--12. " E17 ,Pin function for E17" "MIBSPI5SOMI[1],MIBSPI5SOMI[1],DMM_DATA[13],,,,,,,,,,,,,,EXT_SEL[03],?..."
endif
bitfld.long 0x20 0.--3. " J18 ,Pin function for J18" "MIBSPI5SOMI[0],MIBSPI5SOMI[0],DMM_DATA[12],,MII_TXD[0],,,,RMII_TXD[0],?..."
line.long 0x24 "PINMMR28,PINMMR28 Control Register"
bitfld.long 0x24 24.--29. " U1 ,Pin function for U1" "N2HET1[03],N2HET1[03],MIBSPI4NCS[0],,,,,,N2HET2[10],,,,,,,,,,,,,,,,,,,,,,,,EQEP2B,?..."
bitfld.long 0x24 16.--21. " W5 ,Pin function for W5" "N2HET1[02],N2HET1[02],MIBSPI4SIMO,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,EPWM3A,?..."
bitfld.long 0x24 8.--13. " V2 ,Pin function for V2" "N2HET1[01],N2HET1[01],MIBSPI4NENA,,,,,,N2HET2[08],,,,,,,,,,,,,,,,,,,,,,,,EQEP2A,?..."
bitfld.long 0x24 0.--5. " K18 ,Pin function for K18" "N2HET1[00],N2HET1[00],MIBSPI4CLK,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,EPWM2B,?..."
line.long 0x28 "PINMMR29,PINMMR28 Control Register"
bitfld.long 0x28 24.--29. " T1 ,Pin function for T1" "N2HET1[07],N2HET1[07],MIBSPI4NCS[2],,,,,,N2HET2[14],,,,,,,,,,,,,,,,,,,,,,,,EPWM7B,?..."
bitfld.long 0x28 16.--21. " W3 ,Pin function for W3" "N2HET1[06],N2HET1[06],SCI3RX,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,EPWM5A,?..."
bitfld.long 0x28 8.--13. " V6 ,Pin function for V6" "N2HET1[05],N2HET1[05],MIBSPI4SOMI,,,,,,N2HET2[12],,,,,,,,,,,,,,,,,,,,,,,,EPWM3B,?..."
bitfld.long 0x28 0.--5. " B12 ,Pin function for B12" "N2HET1[04],N2HET1[04],MIBSPI4NCS[1],,,,,,,,,,,,,,,,,,,,,,,,,,,,,,EPWM4B,?..."
line.long 0x2C "PINMMR30,PINMMR30 Control Register"
bitfld.long 0x2C 24.--29. " E3 ,Pin function for E3" "N2HET1[11],N2HET1[11],MIBSPI3NCS[4],,,,,,N2HET2[18],,,,,,,,,,,,,,,,,,,,,,,,EPWM1SYNCO,?..."
bitfld.long 0x2C 16.--21. " D19 ,Pin function for D19" "N2HET1[10],N2HET1[10],MIBSPI4NCS[4],,MII_TX_CLK,,,,,,,,,,,,,,,,,,,,,,,,,,,,NTZ1_3,?..."
bitfld.long 0x2C 8.--13. " V7 ,Pin function for V7" "N2HET1[09],N2HET1[09],MIBSPI4NCS[3],,,,,,N2HET2[16],,,,,,,,,,,,,,,,,,,,,,,,EPWM7A,?..."
bitfld.long 0x2C 0.--2. " E18 ,Pin function for E18" "N2HET1[08],N2HET1[08],MIBSPI1SIMO[1],,MII_TXD[3],?..."
line.long 0x30 "PINMMR31,PINMMR31 Control Register"
bitfld.long 0x30 24.--29. " A4 ,Pin function for A4" "N2HET1[16],N2HET1[16],,,,,,,EPWM1SYNCI,,,,,,,,,,,,,,,,,,,,,,,,EPWM1SYNCO,?..."
bitfld.long 0x30 16.--21. " N1 ,Pin function for N1" "N2HET1[15],N2HET1[15],MIBSPI1NCS[4],,,,,,N2HET2[22],,,,,,,,,,,,,,,,,,,,,,,,ECAP1,?..."
bitfld.long 0x30 8.--13. " N2 ,Pin function for N2" "N2HET1[13],N2HET1[13],SCI3TX,,,,,,N2HET2[20],,,,,,,,,,,,,,,,,,,,,,,,EPWM5B,?..."
bitfld.long 0x30 0.--3. " B4 ,Pin function for B4" "N2HET1[12],N2HET1[12],MIBSPI4NCS[5],,MII_CRS,,,,RMII_CRS_DV,?..."
line.long 0x34 "PINMMR32,PINMMR32 Control Register"
bitfld.long 0x34 24.--29. " P2 ,Pin function for P2" "N2HET1[20],N2HET1[20],EMIF_NDQM[1],,,,,,,,,,,,,,,,,,,,,,,,,,,,,,EPWM6B,?..."
bitfld.long 0x34 16.--18. " B13 ,Pin function for B13" "N2HET1[19],N2HET1[19],EMIF_NDQM[0],,SCI4TX,?..."
bitfld.long 0x34 8.--13. " J1 ,Pin function for J1" "N2HET1[18],N2HET1[18],EMIF_RNW,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,EPWM6A,?..."
bitfld.long 0x34 0.--2. " A13 ,Pin function for A13" "N2HET1[17],N2HET1[17],EMIF_NOE,,SCI4RX,?..."
line.long 0x38 "PINMMR33,PINMMR33 Control Register"
bitfld.long 0x38 24.--27. " P1 ,Pin function for P1" "N2HET1[24],N2HET1[24],MIBSPI1NCS[5],,MII_RXD[0],,,,RMII_RXD[0],?..."
bitfld.long 0x38 16.--17. " J4 ,Pin function for pin J4" "N2HET1[23],N2HET1[23],EMIF_BA[0],?..."
bitfld.long 0x38 8.--9. " B3 ,Pin function for pin B3" "N2HET1[22],N2HET1[22],EMIF_NDQM[3],?..."
bitfld.long 0x38 0.--1. " H4 ,Pin function for pin H4" "N2HET1[21],N2HET1[21],EMIF_NDQM[2],?..."
line.long 0x3C "PINMMR34,PINMMR34 Control Register"
sif cpuis("RM57L843-ZWT")
bitfld.long 0x3C 24.--25. " D8 ,Pin function for pin D8" "N2HET2[01],N2HET2[01],N2HET1_NDIS,?..."
else
bitfld.long 0x3C 24. " D8 ,Pin function for pin D8" "N2HET2[01],N2HET2[01]"
endif
bitfld.long 0x3C 16.--21. " B11 ,Pin function for B11" "N2HET1[30],N2HET1[30],,,MII_RX_DV,,,,,,,,,,,,,,,,,,,,,,,,,,,,EQEP2S,?..."
bitfld.long 0x3C 8.--11. " K19 ,Pin function for K19" "N2HET1[28],N2HET1[28],,,MII_RXCLK,,,,RMII_REFCLK,?..."
bitfld.long 0x3C 0.--3. " A14 ,Pin function for A14" "N2HET1[26],N2HET1[26],,,MII_RXD[1],,,,RMII_RXD[1],?..."
line.long 0x40 "PINMMR35,PINMMR35 Control Register"
bitfld.long 0x40 24.--28. " D1 ,Pin function for D1" "N2HET2[14],N2HET2[14],,,,,,,,,,,,,,,MIBSPI2SIMO,?..."
bitfld.long 0x40 16.--20. " D2 ,Pin function for D2" "N2HET2[13],N2HET2[13],,,,,,,,,,,,,,,MIBSPI2SOMI,?..."
bitfld.long 0x40 8.--13. " D3 ,Pin function for D3" "N2HET2[12],N2HET2[12],,,,,,,,,,,,,,,MIBSPI2NENA,,,,,,,,,,,,,,,,MIBSPI2NCS[1],?..."
sif cpuis("RM57L843-ZWT")
bitfld.long 0x40 0.--1. " D7 ,Pin function for pin D7" "N2HET2[02],N2HET2[02],N2HET2_NDIS,?..."
else
bitfld.long 0x40 0. " D7 ,Pin function for pin D7" "N2HET2[02],N2HET2[02]"
endif
line.long 0x44 "PINMMR36,PINMMR36 Control Register"
bitfld.long 0x44 24. " U7 ,Pin function for pin U7" "MII_TX_CLK,MII_TX_CLK"
bitfld.long 0x44 16. " T4 ,Pin function for pin T4" "MII_RXCLK,MII_RXCLK"
bitfld.long 0x44 8.--9. " T5 ,Pin function for pin T5" "N2HET2[20],N2HET2[20],LIN2TX,?..."
bitfld.long 0x44 0.--1. " P4 ,Pin function for pin P4" "N2HET2[19],N2HET2[19],LIN2RX,?..."
line.long 0x48 "PINMMR37,PINMMR37 Control Register"
bitfld.long 0x48 8.--12. " N3 ,Pin function for N3" "N2HET2[07],N2HET2[07],,,,,,,,,,,,,,,MIBSPI2NCS[0],?..."
bitfld.long 0x48 0.--4. " E2 ,Pin function for E2" "N2HET2[03],N2HET2[03],,,,,,,,,,,,,,,MIBSPI2CLK,?..."
tree.end
width 10.
tree "Input Pin Multiplexing Control Registers"
sif cpuis("RM57L843-ZWT")
group.long 0x250++0x03
line.long 0x00 "PINMMR80,Pin Multiplexing Control Registers 80"
bitfld.long 0x00 0.--1. " AD2EVT ,AD2EVT terminal select" "Disabled,T10,V10,?..."
group.long 0x25C++0x03
line.long 0x00 "PINMMR83,Pin Multiplexing Control Register"
bitfld.long 0x00 24.--25. " GIOA[0] ,GIOA[0] terminal select" "Disabled,A5,R5,?..."
else
group.long 0x250++0x0F
line.long 0x00 "PINMMR80,Pin Multiplexing Control Registers 80"
bitfld.long 0x00 24.--25. " ECAP3 ,ECAP3 terminal select" "Disabled,,W8,?..."
bitfld.long 0x00 16.--17. " ECAP2 ,ECAP2 terminal select" "Disabled,,V8,?..."
bitfld.long 0x00 8.--9. " ECAP1 ,ECAP1 terminal select" "Disabled,,N1,?..."
bitfld.long 0x00 0.--1. " AD2EVT ,AD2EVT terminal select" "Disabled,T10,V10,?..."
line.long 0x04 "PINMMR81,Pin Multiplexing Control Register 81"
bitfld.long 0x04 24.--25. " EQEP1A ,Eqep1a terminal select" "Disabled,,V9,?..."
bitfld.long 0x04 16.--17. " ECAP6 ,ECAP6 terminal select" "Disabled,,R2,?..."
bitfld.long 0x04 8.--9. " ECAP5 ,ECAP5 terminal select" "Disabled,,H18,?..."
bitfld.long 0x04 0.--1. " ECAP4 ,ECAP4 terminal select" "Disabled,,G19,?..."
line.long 0x08 "PINMMR82,Pin Multiplexing Control Register 82"
bitfld.long 0x08 24.--25. " EQEP2A ,Eqep2a terminal select" "Disabled,,V2,?..."
bitfld.long 0x08 16.--17. " EQEP1S ,Eqep1s terminal select" "Disabled,,F3,?..."
bitfld.long 0x08 8.--9. " EQEP1I ,Eqep1i terminal select" "Disabled,,V10,?..."
bitfld.long 0x08 0.--1. " EQEP1B ,Eqep1b terminal select" "Disabled,,W9,?..."
line.long 0x0C "PINMMR83,Pin Multiplexing Control Register"
bitfld.long 0x0C 24.--25. " GIOA[0] ,GIOA[0] terminal select" "Disabled,A5,R5,?..."
bitfld.long 0x0C 16.--17. " EQEP2S ,Eqep2s terminal select" "Disabled,,B11,?..."
bitfld.long 0x0C 8.--9. " EQEP2I ,Eqep2i terminal select" "Disabled,,C1,?..."
bitfld.long 0x0C 0.--1. " EQEP2B ,Eqep2b terminal select" "Disabled,,U1,?..."
endif
group.long 0x260++0x3F
line.long 0x0 "PINMMR84,Pin Multiplexing Control Register"
bitfld.long 0x0 24.--25. " GIOA[4] ,GIOA[4] terminal select" "Disabled,A6,R8,?..."
bitfld.long 0x0 16.--17. " GIOA[3] ,GIOA[3] terminal select" "Disabled,E1,R7,?..."
bitfld.long 0x0 8.--9. " GIOA[2] ,GIOA[2] terminal select" "Disabled,C1,B15,?..."
bitfld.long 0x0 0.--1. " GIOA[1] ,GIOA[1] terminal select" "Disabled,C2,R6,?..."
line.long 0x4 "PINMMR85,Pin Multiplexing Control Register"
bitfld.long 0x4 24.--25. " GIOB[0] ,GIOB[0] terminal select" "Disabled,M2,B8,?..."
bitfld.long 0x4 16.--17. " GIOA[7] ,GIOA[7] terminal select" "Disabled,M1,R11,?..."
bitfld.long 0x4 8.--9. " GIOA[6] ,GIOA[6] terminal select" "Disabled,H3,R10,?..."
bitfld.long 0x4 0.--1. " GIOA[5] ,GIOA[5] terminal select" "Disabled,B5,R9,?..."
line.long 0x8 "PINMMR86,Pin Multiplexing Control Register"
bitfld.long 0x8 24.--25. " GIOB[4] ,GIOB[4] terminal select" "Disabled,G1,L17,?..."
bitfld.long 0x8 16.--17. " GIOB[3] ,GIOB[3] terminal select" "Disabled,W10,R4,?..."
bitfld.long 0x8 8.--9. " GIOB[2] ,GIOB[2] terminal select" "Disabled,F2,B9,?..."
bitfld.long 0x8 0.--1. " GIOB[1] ,GIOB[1] terminal select" "Disabled,K2,B16,?..."
line.long 0xC "PINMMR87,Pin Multiplexing Control Register"
bitfld.long 0xC 24.--25. " MDIO ,MDIO terminal select" "Disabled,F4,G3,?..."
bitfld.long 0xC 16.--17. " GIOB[7] ,GIOB[7] terminal select" "Disabled,F1,P3,?..."
bitfld.long 0xC 8.--9. " GIOB[6] ,GIOB[6] terminal select" "Disabled,J2,R3,?..."
bitfld.long 0xC 0.--1. " GIOB[5] ,GIOB[5] terminal select" "Disabled,G2,M17,?..."
line.long 0x10 "PINMMR88,Pin Multiplexing Control Register"
sif !cpuis("RM57L843-ZWT")
bitfld.long 0x10 16.--17. " MIBSPI2NCS[1] ,MIBSPI2NCS[1] terminal select" "Disabled,,D3,?..."
textline " "
endif
bitfld.long 0x10 8.--9. " MIBSPI1NCS[5] ,MIBSPI1NCS[5] terminal select" "Disabled,U9,P1,?..."
bitfld.long 0x10 0.--1. " MIBSPI1NCS[4] ,MIBSPI1NCS[4] terminal select" "Disabled,U10,N1,?..."
line.long 0x14 "PINMMR89,Pin Multiplexing Control Register"
bitfld.long 0x14 24.--25. " MII_CRS ,MII_CRS terminal select" "Disabled,V4,B4,?..."
bitfld.long 0x14 16.--17. " MII_COL ,MII_COL terminal select" "Disabled,W4,F3,?..."
line.long 0x18 "PINMMR90,Pin Multiplexing Control Register"
bitfld.long 0x18 24.--25. " MII_RXD[0] ,MII_RXD[0] terminal select" "Disabled,U4,P1,?..."
bitfld.long 0x18 16.--17. " MII_RXCLK ,MII_RXCLK terminal select" "Disabled,T4,K19,?..."
bitfld.long 0x18 8.--9. " MII_RX_ER ,MII_RX_ER terminal select" "Disabled,U5,N19,?..."
bitfld.long 0x18 0.--1. " MII_RX_DV ,MII_RX_DV terminal select" "Disabled,U6,B11,?..."
line.long 0x1C "PINMMR91,Pin Multiplexing Control Register"
bitfld.long 0x1C 24.--25. " MII_TX_CLK ,MII_TX_CLK terminal select" "Disabled,U7,D19,?..."
bitfld.long 0x1C 16.--17. " MII_RXD[3] ,MII_RXD[3] terminal select" "Disabled,V3,H18,?..."
bitfld.long 0x1C 8.--9. " MII_RXD[2] ,MII_RXD[2] terminal select" "Disabled,U3,G19,?..."
bitfld.long 0x1C 0.--1. " MII_RXD[1] ,MII_RXD[1] terminal select" "Disabled,T3,A14,?..."
line.long 0x20 "PINMMR92,Pin Multiplexing Control Register"
bitfld.long 0x20 24.--25. " N2HET1[23] ,N2HET1[23] terminal select" "Disabled,J4,G19,?..."
bitfld.long 0x20 16.--17. " N2HET1[21] ,N2HET1[21] terminal select" "Disabled,H4,J3,?..."
bitfld.long 0x20 8.--9. " N2HET1[19] ,N2HET1[19] terminal select" "Disabled,B13,G3,?..."
bitfld.long 0x20 0.--1. " N2HET1[17] ,N2HET1[17] terminal select" "Disabled,A13,F3,?..."
line.long 0x24 "PINMMR93,Pin Multiplexing Control Register"
bitfld.long 0x24 24.--25. " N2HET1[31] ,N2HET1[31] terminal select" "Disabled,J17,W9,?..."
bitfld.long 0x24 16.--17. " N2HET1[29] ,N2HET1[29] terminal select" "Disabled,A3,C3,?..."
bitfld.long 0x24 8.--9. " N2HET1[27] ,N2HET1[27] terminal select" "Disabled,A9,B2,?..."
bitfld.long 0x24 0.--1. " N2HET1[25] ,N2HET1[25] terminal select" "Disabled,M3,V5,?..."
line.long 0x28 "PINMMR94,Pin Multiplexing Control Register"
bitfld.long 0x28 24.--25. " N2HET2[03] ,N2HET2[03] terminal select" "Disabled,E2,D5,?..."
bitfld.long 0x28 16.--17. " N2HET2[02] ,N2HET2[02] terminal select" "Disabled,D7,E1,?..."
bitfld.long 0x28 8.--9. " N2HET2[01] ,N2HET2[01] terminal select" "Disabled,D8,D4,?..."
bitfld.long 0x28 0.--1. " N2HET2[00] ,N2HET2[00] terminal select" "Disabled,D6,C1,?..."
line.long 0x2C "PINMMR95,Pin Multiplexing Control Register"
bitfld.long 0x2C 24.--25. " N2HET2[07] ,N2HET2[07] terminal select" "Disabled,N3,N17,?..."
bitfld.long 0x2C 16.--17. " N2HET2[06] ,N2HET2[06] terminal select" "Disabled,D11,M1,?..."
bitfld.long 0x2C 8.--9. " N2HET2[05] ,N2HET2[05] terminal select" "Disabled,D12,D16,?..."
bitfld.long 0x2C 0.--1. " N2HET2[04] ,N2HET2[04] terminal select" "Disabled,D13,H3,?..."
line.long 0x30 "PINMMR96,Pin Multiplexing Control Register"
bitfld.long 0x30 24.--25. " N2HET2[11] ,N2HET2[11] terminal select" "Disabled,N16,C4,?..."
bitfld.long 0x30 16.--17. " N2HET2[10] ,N2HET2[10] terminal select" "Disabled,M16,U1,?..."
bitfld.long 0x30 8.--9. " N2HET2[09] ,N2HET2[09] terminal select" "Disabled,L16,K17,?..."
bitfld.long 0x30 0.--1. " N2HET2[08] ,N2HET2[08] terminal select" "Disabled,K16,V2,?..."
line.long 0x34 "PINMMR97,Pin Multiplexing Control Register"
bitfld.long 0x34 24.--25. " N2HET2[15] ,N2HET2[15] terminal select" "Disabled,K4,C6,?..."
bitfld.long 0x34 16.--17. " N2HET2[14] ,N2HET2[14] terminal select" "Disabled,D1,T1,?..."
bitfld.long 0x34 8.--9. " N2HET2[13] ,N2HET2[13] terminal select" "Disabled,D2,C5,?..."
bitfld.long 0x34 0.--1. " N2HET2[12] ,N2HET2[12] terminal select" "Disabled,D3,V6,?..."
line.long 0x38 "PINMMR98,Pin Multiplexing Control Register"
bitfld.long 0x38 24.--25. " N2HET2[22] ,N2HET2[22] terminal select" "Disabled,T7,N1,?..."
bitfld.long 0x38 16.--17. " N2HET2[20] ,N2HET2[20] terminal select" "Disabled,T5,N2,?..."
bitfld.long 0x38 8.--9. " N2HET2[18] ,N2HET2[18] terminal select" "Disabled,N4,E3,?..."
bitfld.long 0x38 0.--1. " N2HET2[16] ,N2HET2[16] terminal select" "Disabled,L4,V7,?..."
line.long 0x3C "PINMMR99,Pin Multiplexing Control Register"
bitfld.long 0x3C 16.--17. " NTZ1_3 ,Ntz1_3 terminal select" "Disabled,J3,D19,?..."
bitfld.long 0x3C 8.--9. " NTZ1_2 ,Ntz1_2 terminal select" "Disabled,F1,B2,?..."
bitfld.long 0x3C 0.--1. " NTZ1_1 ,Ntz1_1 terminal select" "Disabled,N19,C3,?..."
tree.end
width 11.
tree "Special Functionality Multiplexing Control Registers"
group.long 0x390++0x03
line.long 0x00 "PINMMR160,Special Functionality Multiplexing Control Register"
bitfld.long 0x00 24. " RMII_SEL ,MII/RMII select" "MII,RMII"
bitfld.long 0x00 16.--17. " GIOB[2]_SEL ,GIOB[2] select" "Disabled,N2HET2_NDIS,GIOB[2],?..."
if (d.l(ad:0xFFFF1C00+0x0394)&0x03)==0x01
group.long 0x394++0x0B
line.long 0x00 "PINMMR161,Special Functionality Multiplexing Control Register"
bitfld.long 0x00 24.--25. " ADC1_ALT_TRIG_SRC6 ,ADC1 alternate trigger source for trigger input 6" "N2HET1[14],N2HET1[14],N2HET1[14],N2HET1[14]"
bitfld.long 0x00 16.--17. " ADC1_ALT_TRIG_SRC4 ,ADC1 alternate trigger source for trigger input 4" "RTI1 COMP0,RTI1 COMP0,RTI1 COMP0,RTI1 COMP0"
textline " "
bitfld.long 0x00 8.--9. " ADC1_ALT_TRIG_SRC2 ,ADC1 alternate trigger source for trigger input 2" "N2HET1[8],N2HET1[8],N2HET1[8],N2HET1[8]"
bitfld.long 0x00 0.--1. " ADC_ALT_TRIG_TABLE ,ADC alternate trigger table select" ",Table 1,Table 2,?..."
line.long 0x04 "PINMMR162,Special Functionality Multiplexing Control Register"
bitfld.long 0x04 24.--25. " ADC2_ALT_TRIG_SRC4 ,ADC2 alternate trigger source for trigger input 4" "RTI1 COMP0,RTI1 COMP0,RTI1 COMP0,RTI1 COMP0"
bitfld.long 0x04 16.--17. " ADC2_ALT_TRIG_SRC2 ,ADC2 alternate trigger source for trigger input 2" "N2HET1[8],N2HET1[8],N2HET1[8],N2HET1[8]"
textline " "
bitfld.long 0x04 8.--9. " ADC1_ALT_TRIG_SRC8 ,ADC1 alternate trigger source for trigger input 8" "GIOB[1],GIOB[1],GIOB[1],GIOB[1]"
bitfld.long 0x04 0.--1. " ADC1_ALT_TRIG_SRC7 ,ADC1 alternate trigger source for trigger input 7" "GIOB[0],GIOB[0],GIOB[0],GIOB[0]"
line.long 0x08 "PINMMR163,Special Functionality Multiplexing Control Register"
bitfld.long 0x08 16.--17. " ADC2_ALT_TRIG_SRC8 ,ADC2 alternate trigger source for trigger input 8" "GIOB[1],GIOB[1],GIOB[1],GIOB[1]"
bitfld.long 0x08 8.--9. " ADC2_ALT_TRIG_SRC7 ,ADC2 alternate trigger source for trigger input 7" "GIOB[0],GIOB[0],GIOB[0],GIOB[0]"
textline " "
bitfld.long 0x08 0.--1. " ADC2_ALT_TRIG_SRC6 ,ADC2 alternate trigger source for trigger input 6" "N2HET1[14],N2HET1[14],N2HET1[14],N2HET1[14]"
elif (d.l(ad:0xFFFF1C00+0x0394)&0x03)==0x02
group.long 0x394++0x0B
line.long 0x00 "PINMMR161,Special Functionality Multiplexing Control Register"
bitfld.long 0x00 24.--25. " ADC1_ALT_TRIG_SRC6 ,ADC1 alternate trigger source for trigger input 6" ",N2HET1[19],N2HET2[1],?..."
bitfld.long 0x00 16.--17. " ADC1_ALT_TRIG_SRC4 ,ADC1 alternate trigger source for trigger input 4" ",RTI1 COMP0,EPWM_A1,?..."
textline " "
bitfld.long 0x00 8.--9. " ADC1_ALT_TRIG_SRC2 ,ADC1 alternate trigger source for trigger input 2" ",N2HET2[5],EPWM_B,?..."
bitfld.long 0x00 0.--1. " ADC_ALT_TRIG_TABLE ,ADC alternate trigger table select" ",Table 1,Table 2,?..."
line.long 0x04 "PINMMR162,Special Functionality Multiplexing Control Register"
bitfld.long 0x04 24.--25. " ADC2_ALT_TRIG_SRC4 ,ADC2 alternate trigger source for trigger input 4" ",RTI1 COMP0,EPWM_A1,?..."
bitfld.long 0x04 16.--17. " ADC2_ALT_TRIG_SRC2 ,ADC2 alternate trigger source for trigger input 2" ",N2HET2[5],EPWM_B,?..."
textline " "
bitfld.long 0x04 8.--9. " ADC1_ALT_TRIG_SRC8 ,ADC1 alternate trigger source for trigger input 8" ",N2HET2[13],EPWM_AB,?..."
bitfld.long 0x04 0.--1. " ADC1_ALT_TRIG_SRC7 ,ADC1 alternate trigger source for trigger input 7" ",N2HET1[11],EPWM_A2,?..."
line.long 0x08 "PINMMR163,Special Functionality Multiplexing Control Register"
bitfld.long 0x08 16.--17. " ADC2_ALT_TRIG_SRC8 ,ADC2 alternate trigger source for trigger input 8" ",N2HET2[13],EPWM_AB,?..."
bitfld.long 0x08 8.--9. " ADC2_ALT_TRIG_SRC7 ,ADC2 alternate trigger source for trigger input 7" ",N2HET1[11],EPWM_A2,?..."
textline " "
bitfld.long 0x08 0.--1. " ADC2_ALT_TRIG_SRC6 ,ADC2 alternate trigger source for trigger input 6" ",N2HET1[19],N2HET2[1],?..."
else
group.long 0x394++0x03
line.long 0x00 "PINMMR161,Special Functionality Multiplexing Control Register"
bitfld.long 0x00 0.--1. " ADC_ALT_TRIG_TABLE ,ADC alternate trigger table select" ",Table 1,Table 2,?..."
hgroup.long 0x398++0x07
hide.long 0x00 "PINMMR162,Special Functionality Multiplexing Control Register"
textline " "
hide.long 0x04 "PINMMR163,Special Functionality Multiplexing Control Register"
textline " "
endif
group.long 0x3A0++0x3F
line.long 0x00 "PINMMR164,Special Functionality Multiplexing Control Register"
bitfld.long 0x00 24. " SOC4A_SEL ,Selecting start of conversion (Soc4a) of epwm4" "EPWM_A1,EPWM_A2"
bitfld.long 0x00 16. " SOC3A_SEL ,Selecting start of conversion (Soc3a) of epwm3" "EPWM_A1,EPWM_A2"
textline " "
bitfld.long 0x00 8. " SOC2A_SEL ,Selecting start of conversion (Soc2a) of epwm2" "EPWM_A1,EPWM_A2"
bitfld.long 0x00 0. " SOC1A_SEL ,Selecting start of conversion (Soc1a) of epwm1" "EPWM_A1,EPWM_A2"
line.long 0x04 "PINMMR165,Special Functionality Multiplexing Control Register"
bitfld.long 0x04 24.--25. " SYNCI_SEL ,Selecting start of conversion (Soc7a) of epwm1" ",EPWM1_SYNCI,N2HET1_LOO_SYNC,?..."
bitfld.long 0x04 16. " SOC7A_SEL ,Selecting start of conversion (Soc7a) of epwm7" "EPWM_A1,EPWM_A2"
textline " "
bitfld.long 0x04 8. " SOC6A_SEL ,Selecting start of conversion (Soc6a) of epwm6" "EPWM_A1,EPWM_A2"
bitfld.long 0x04 0. " SOC5A_SEL ,Selecting start of conversion (Soc5a) of epwm5" "EPWM_A1,EPWM_A2"
line.long 0x08 "PINMMR166,Special Functionality Multiplexing Control Register"
bitfld.long 0x08 1. " TBCLKSYNC_EN ,Epwmx TBCLKSYNC enable" "Disabled,Enabled"
line.long 0x0C "PINMMR167,Special Functionality Multiplexing Control Register"
bitfld.long 0x0C 24.--27. " EPWM4_TZ4_SEL ,Epwm4 trip zone 4 select" ",EQEP1ERR NOR EQEP2ERR,NOT EQEP1ERR,,NOT EQEP2ERR,?..."
bitfld.long 0x0C 16.--18. " EPWM3_TZ4_SEL ,Epwm3 trip zone 4 select" ",EQEP1ERR NOR EQEP2ERR,NOT EQEP1ERR,,NOT EQEP2ERR,?..."
textline " "
bitfld.long 0x0C 8.--10. " EPWM2_TZ4_SEL ,Epwm2 trip zone 4 select" ",EQEP1ERR NOR EQEP2ERR,NOT EQEP1ERR,,NOT EQEP2ERR,?..."
bitfld.long 0x0C 0.--2. " EPWM1_TZ4_SEL ,Epwm1 trip zone 4 select" ",EQEP1ERR NOR EQEP2ERR,NOT EQEP1ERR,,NOT EQEP2ERR,?..."
line.long 0x10 "PINMMR168,Special Functionality Multiplexing Control Register"
bitfld.long 0x10 16.--18. " EPWM7_TZ4_SEL ,Epwm7 trip zone 4 select" ",EQEP1ERR NOR EQEP2ERR,NOT EQEP1ERR,,NOT EQEP2ERR,?..."
bitfld.long 0x10 8.--10. " EPWM6_TZ4_SEL ,Epwm6 trip zone 4 select" ",EQEP1ERR NOR EQEP2ERR,NOT EQEP1ERR,,NOT EQEP2ERR,?..."
textline " "
bitfld.long 0x10 0.--2. " EPWM5_TZ4_SEL ,Epwm5 trip zone 4 select" ",EQEP1ERR NOR EQEP2ERR,NOT EQEP1ERR,,NOT EQEP2ERR,?..."
line.long 0x14 "PINMMR169,Special Functionality Multiplexing Control Register"
bitfld.long 0x14 24.--25. " ECAP4_IN_FILT ,Ecap4 input filtering select" "Disabled,Double-sync,Double-sync + filter,?..."
bitfld.long 0x14 16.--17. " ECAP3_IN_FILT ,Ecap3 input filtering select" "Disabled,Double-sync,Double-sync + filter,?..."
textline " "
bitfld.long 0x14 8.--9. " ECAP2_IN_FILT ,Ecap2 input filtering select" "Disabled,Double-sync,Double-sync + filter,?..."
bitfld.long 0x14 0.--1. " ECAP1_IN_FILT ,Ecap1 input filtering select" "Disabled,Double-sync,Double-sync + filter,?..."
line.long 0x18 "PINMMR170,Special Functionality Multiplexing Control Register"
bitfld.long 0x18 24.--25. " EQEP1B_IN_FILT ,Eqep1b input filtering select" "Disabled,Double-sync,Double-sync + filter,?..."
bitfld.long 0x18 16.--17. " EQEP1A_IN_FILT ,Eqep1a input filtering select" "Disabled,Double-sync,Double-sync + filter,?..."
textline " "
bitfld.long 0x18 8.--9. " ECAP6_IN_FILT ,Ecap6 input filtering select" "Disabled,Double-sync,Double-sync + filter,?..."
bitfld.long 0x18 0.--1. " ECAP5_IN_FILT ,Ecap5 input filtering select" "Disabled,Double-sync,Double-sync + filter,?..."
line.long 0x1C "PINMMR171,Special Functionality Multiplexing Control Register"
bitfld.long 0x1C 24.--25. " EQEP2B_IN_FILT ,Eqep2b input filtering select" "Disabled,Double-sync,Double-sync + filter,?..."
bitfld.long 0x1C 16.--17. " EQEP2A_IN_FILT ,Eqep2a input filtering select" "Disabled,Double-sync,Double-sync + filter,?..."
textline " "
bitfld.long 0x1C 8.--9. " EQEP1S_IN_FILT ,Eqep1s input filtering select" "Disabled,Double-sync,Double-sync + filter,?..."
bitfld.long 0x1C 0.--1. " EQEP1I_IN_FILT ,Eqep1i input filtering select" "Disabled,Double-sync,Double-sync + filter,?..."
line.long 0x20 "PINMMR172,Special Functionality Multiplexing Control Register"
bitfld.long 0x20 24.--26. " EPWMX_TZ2N_IN_FILT ,Epwmx trip zone2 (Tz2n) input filtering select" "Disabled,ASYNC,Double-sync,,Double-sync + filter,?..."
bitfld.long 0x20 16.--18. " EPWMX_TZ1N_IN_FILT ,Epwmx trip zone1 (Tz1n) input filtering select" "Disabled,ASYNC,Double-sync,,Double-sync + filter,?..."
textline " "
bitfld.long 0x20 8.--9. " EQEP2S_IN_FILT ,Eqep2s input filtering select" "Disabled,Double-sync,Double-sync + filter,?..."
bitfld.long 0x20 0.--1. " EQEP2I_IN_FILT ,Eqep2i input filtering select" "Disabled,Double-sync,Double-sync + filter,?..."
line.long 0x24 "PINMMR173,Special Functionality Multiplexing Control Register"
bitfld.long 0x24 24.--25. " TSENS2_SEL ,Temperature sensor 2 select" "Disabled,AD2IN[31],Temp sensor 2,?..."
bitfld.long 0x24 16.--17. " TSENS1_SEL ,Temperature sensor 1 select" "Disabled,AD1IN[31],Temp sensor 1,?..."
textline " "
bitfld.long 0x24 8.--10. " EPWMX_SYNCI_IN_FILT ,Epwmx SYNCI input filtering select" "Disabled,ASYNC,Double-sync,,Double-sync + filter,?..."
bitfld.long 0x24 0.--2. " EPWMX_TZ3N_IN_FILT ,Epwmx trip zone3 (Tz3n) input filtering select" "Disabled,ASYNC,Double-sync,,Double-sync + filter,?..."
line.long 0x28 "PINMMR174,Special Functionality Multiplexing Control Register"
bitfld.long 0x28 24. " TSENS_PWRDWN_EN ,Temperature sensor power down enable" "Not powered down,Powered down"
bitfld.long 0x28 16.--17. " ESM_NERROR_SEL ,Nerror select (Esm1/esm2)" "NERROR/NERROR,NERROR1/NERROR,NERROR/NERROR2,NERROR1/NERROR2"
textline " "
bitfld.long 0x28 8.--9. " EMIF_OUT_EN ,EMIF output enable" ",Disabled,Enabled,?..."
bitfld.long 0x28 0.--1. " TSENS3_SEL ,Temperature sensor 3 select" "Disabled,AD2IN[30],Temp sensor 3,?..."
line.long 0x2C "PINMMR175,Special Functionality Multiplexing Control Register"
bitfld.long 0x2C 24. " GIOA[3]_DMA_REQ_SEL ,GIOA[3] DMA request select" "GIOA[3],Others"
bitfld.long 0x2C 16. " GIOA[2]_DMA_REQ_SEL ,GIOA[2] DMA request select" "GIOA[2],Others"
textline " "
bitfld.long 0x2C 8. " GIOA[1]_DMA_REQ_SEL ,GIOA[1] DMA request select" "GIOA[1],Others"
bitfld.long 0x2C 0. " GIOA[0]_DMA_REQ_SEL ,GIOA[0] DMA request select" "GIOA[0],Others"
line.long 0x30 "PINMMR176,Special Functionality Multiplexing Control Register"
bitfld.long 0x30 24. " GIOA[7]_DMA_REQ_SEL ,GIOA[7] DMA request select" "GIOA[7],Others"
bitfld.long 0x30 16. " GIOA[6]_DMA_REQ_SEL ,GIOA[6] DMA request select" "GIOA[6],Others"
textline " "
bitfld.long 0x30 8. " GIOA[5]_DMA_REQ_SEL ,GIOA[5] DMA request select" "GIOA[5],Others"
bitfld.long 0x30 0. " GIOA[4]_DMA_REQ_SEL ,GIOA[4] DMA request select" "GIOA[4],Others"
line.long 0x34 "PINMMR177,Special Functionality Multiplexing Control Register"
bitfld.long 0x34 24. " GIOB[3]_DMA_REQ_SEL ,GIOB[3] DMA request select" "GIOB[3],Others"
bitfld.long 0x34 16. " GIOB[2]_DMA_REQ_SEL ,GIOB[2] DMA request select" "GIOB[2],Others"
textline " "
bitfld.long 0x34 8. " GIOB[1]_DMA_REQ_SEL ,GIOB[1] DMA request select" "GIOB[1],Others"
bitfld.long 0x34 0. " GIOB[0]_DMA_REQ_SEL ,GIOB[0] DMA request select" "GIOB[0],Others"
line.long 0x38 "PINMMR178,Special Functionality Multiplexing Control Register"
bitfld.long 0x38 24. " GIOB[7]_DMA_REQ_SEL ,GIOB[7] DMA request select" "GIOB[7],Others"
bitfld.long 0x38 16. " GIOB[6]_DMA_REQ_SEL ,GIOB[6] DMA request select" "GIOB[6],Others"
textline " "
bitfld.long 0x38 8. " GIOB[5]_DMA_REQ_SEL ,GIOB[5] DMA request select" "GIOB[5],Others"
bitfld.long 0x38 0. " GIOB[4]_DMA_REQ_SEL ,GIOB[4] DMA request select" "GIOB[4],Others"
line.long 0x3C "PINMMR179,Special Functionality Multiplexing Control Register"
bitfld.long 0x3C 8.--9. " NHET1_PIN_DIS ,NHET1 pin disable select" ",Yes,No,?..."
bitfld.long 0x3C 0.--1. " NHET2_PIN_DIS ,NHET2 pin disable select" ",Yes,No,?..."
tree.end
width 11.
tree.end
tree.open "L2FMC (F021 Level 2 Flash Module Controller)"
tree "Flash Control Registers"
base ad:0xFFF87000
width 17.
group.long 0x00++0x03
line.long 0x00 "FRDCNTL,Flash Read Control Register"
bitfld.long 0x00 8.--11. " RWAIT ,Random/data read wait state" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 1. " PFUENB ,Prefetch enable for portb" "Disabled,Enabled"
bitfld.long 0x00 0. " PFUENA ,Prefetch enable for porta" "Disabled,Enabled"
group.long 0x08++0x03
line.long 0x00 "EE_FEDACCTRL1,EEPROM Error Correction Control Register"
bitfld.long 0x00 5. " EOCV ,One condition valid" "Not allowed,Allowed"
bitfld.long 0x00 4. " EZCV ,Zero condition valid" "Not allowed,Allowed"
hgroup.long 0x14++0x03
hide.long 0x00 "FEDAC_PASTATUS,Flash Porta Error And Status Register"
in
hgroup.long 0x18++0x03
hide.long 0x00 "FEDAC_PBSTATUS,Flash Portb Error And Status Register"
in
hgroup.long 0x1C++0x03
hide.long 0x00 "FEDAC_GBLSTATUS,Flash Global Error And Status Register"
in
group.long 0x24++0x03
line.long 0x00 "FEDACSDIS,Flash Error Detection And Correction Sector Disable Register"
bitfld.long 0x00 24.--29. " SECTORID1_INVERSE ,The sector ID inverse bits are used with the sector ID bits to determine which sector is disabled" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 16.--21. " SECTORID1 ,The sector ID bits are used with the sector ID inverse bits to determine which sector is disabled" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
textline " "
bitfld.long 0x00 8.--13. " SECTORID0_INVERSE ,The sector ID inverse bits are used with the sector ID bits to determine which sector is disabled" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 0.--5. " SECTORID0 ,The sector ID bits are used with the sector ID inverse bits to determine which sector is disabled" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
rgroup.long 0x28++0x07
line.long 0x00 "FPRIM_ADD_TAG,Primary Address Tag Register"
hexmask.long 0x00 5.--31. 0x20 " PRIM_ADD_TAG ,Primary address tag register"
line.long 0x04 "FDUP_ADD_TAG,Duplicate Address Tag Register"
hexmask.long 0x04 5.--31. 0x20 " DUP_ADD_TAG ,Primary address tag register"
textline " "
group.long 0x30++0x07
line.long 0x00 "FBPROT,Flash Bank Protection Register"
bitfld.long 0x00 0. " PROTL1DIS ,Level 1 protection disable bit" "No,Yes"
line.long 0x04 "FBSE,Flash Bank Sector Enable Register"
bitfld.long 0x04 15. " BSE[15] ,Bank sector 15 enable" "Disabled,Enabled"
bitfld.long 0x04 14. " [14] ,Bank sector 14 enable" "Disabled,Enabled"
bitfld.long 0x04 13. " [13] ,Bank sector 13 enable" "Disabled,Enabled"
bitfld.long 0x04 12. " [12] ,Bank sector 12 enable" "Disabled,Enabled"
textline " "
bitfld.long 0x04 11. " [11] ,Bank sector 11 enable" "Disabled,Enabled"
bitfld.long 0x04 10. " [10] ,Bank sector 10 enable" "Disabled,Enabled"
bitfld.long 0x04 9. " [9] ,Bank sector 9 enable" "Disabled,Enabled"
bitfld.long 0x04 8. " [8] ,Bank sector 8 enable" "Disabled,Enabled"
textline " "
bitfld.long 0x04 7. " [7] ,Bank sector 7 enable" "Disabled,Enabled"
bitfld.long 0x04 6. " [6] ,Bank sector 6 enable" "Disabled,Enabled"
bitfld.long 0x04 5. " [5] ,Bank sector 5 enable" "Disabled,Enabled"
bitfld.long 0x04 4. " [4] ,Bank sector 4 enable" "Disabled,Enabled"
textline " "
bitfld.long 0x04 3. " [3] ,Bank sector 3 enable" "Disabled,Enabled"
bitfld.long 0x04 2. " [2] ,Bank sector 2 enable" "Disabled,Enabled"
bitfld.long 0x04 1. " [1] ,Bank sector 1 enable" "Disabled,Enabled"
bitfld.long 0x04 0. " [0] ,Bank sector 0 enable" "Disabled,Enabled"
textline " "
sif cpu()=="RM57L843-ZWT"
rgroup.long 0x38++0x03
line.long 0x00 "FBBUSY,Flash Bank Busy Register"
bitfld.long 0x00 7. " BUSY[7] ,Bank 7 busy" "Not busy,Busy"
bitfld.long 0x00 6. " [6] ,Bank 6 busy" "Not busy,Busy"
bitfld.long 0x00 5. " [5] ,Bank 5 busy" "Not busy,Busy"
bitfld.long 0x00 4. " [4] ,Bank 4 busy" "Not busy,Busy"
textline " "
bitfld.long 0x00 3. " [3] ,Bank 3 busy" "Not busy,Busy"
bitfld.long 0x00 2. " [2] ,Bank 2 busy" "Not busy,Busy"
bitfld.long 0x00 1. " [1] ,Bank 1 busy" "Not busy,Busy"
bitfld.long 0x00 0. " [0] ,Bank 0 busy" "Not busy,Busy"
else
rgroup.long 0x38++0x03
line.long 0x00 "FBBUSY,Flash Bank Busy Register"
bitfld.long 0x00 7. " BUSY[7] ,Bank 7 busy" "Not busy,Busy"
bitfld.long 0x00 1. " [1] ,Bank 1 busy" "Not busy,Busy"
bitfld.long 0x00 0. " [0] ,Bank 0 busy" "Not busy,Busy"
endif
textline " "
group.long 0x3C++0x07
line.long 0x00 "FBAC,Flash Bank Access Control Register"
sif cpu()=="RM57L843-ZWT"
bitfld.long 0x00 23. " OTPPROTDIS[7] ,OTP sector 23 protection disable" "Yes,No"
bitfld.long 0x00 22. " [6] ,OTP sector 22 protection disable" "Yes,No"
bitfld.long 0x00 21. " [5] ,OTP sector 21 protection disable" "Yes,No"
bitfld.long 0x00 20. " [4] ,OTP sector 20 protection disable" "Yes,No"
textline " "
bitfld.long 0x00 19. " [3] ,OTP sector 19 protection disable" "Yes,No"
bitfld.long 0x00 18. " [2] ,OTP sector 18 protection disable" "Yes,No"
bitfld.long 0x00 17. " [1] ,OTP sector 17 protection disable" "Yes,No"
bitfld.long 0x00 16. " [0] ,OTP sector 16 protection disable" "Yes,No"
textline " "
hexmask.long.byte 0x00 0.--7. 1. " VREADST ,VREAD setup"
textline " "
else
bitfld.long 0x00 23. " OTPPROTDIS[7] ,OTP sector 7 protection disable" "Yes,No"
bitfld.long 0x00 17. " [1] ,OTP sector 1 protection disable" "Yes,No"
bitfld.long 0x00 16. " [0] ,OTP sector 0 protection disable" "Yes,No"
textline " "
hexmask.long.byte 0x00 0.--7. 1. " VREADST ,VREAD setup"
textline " "
endif
line.long 0x04 "FBPWRMODE,Flash Bank Power Mode Register"
bitfld.long 0x04 14.--15. " BANKPWR[7] ,Bank 7 power mode" "Sleep,Standby,,Active"
bitfld.long 0x04 2.--3. " [1] ,Bank 1 power mode" "Sleep,Standby,,Active"
bitfld.long 0x04 0.--1. " [0] ,Bank 0 power mode" "Sleep,Standby,,Active"
rgroup.long 0x44++0x03
line.long 0x00 "FBPRDY,Flash Bank/pump Ready Register"
bitfld.long 0x00 23. " BANKBUSY[7] ,Bank 7 busy status" "Not busy,Busy"
bitfld.long 0x00 17. " [1] ,Bank 1 busy status" "Not busy,Busy"
bitfld.long 0x00 16. " [0] ,Bank 0 busy status" "Not busy,Busy"
textline " "
bitfld.long 0x00 15. " PUMPRDY ,Pump ready" "Not ready,Ready"
textline " "
bitfld.long 0x00 7. " BANKRDY[7] ,Bank 7 ready status" "Not ready,Ready"
bitfld.long 0x00 1. " [1] ,Bank 1 ready status" "Not ready,Ready"
bitfld.long 0x00 0. " [0] ,Bank 0 ready status" "Not ready,Ready"
textline " "
group.long 0x48++0x07
line.long 0x00 "FPAC1,Flash Pump Access Control Register 1"
hexmask.long.word 0x00 16.--26. 1. " PSLEEP ,Pump sleep"
bitfld.long 0x00 0. " PUMPPWR ,Flash charge pump fallback power mode" "Sleep,Active"
sif cpu()=="RM57L843-ZWT"
line.long 0x04 "FMAC,Flash Module Access Control Register"
bitfld.long 0x04 0.--2. " BANK ,Bank enable" "Bank 0,Bank 1,Bank 2,Bank 3,Bank 4,Bank 5,Bank 6,Bank 7"
else
line.long 0x04 "FMAC,Flash Module Access Control Register"
bitfld.long 0x04 0.--2. " BANK ,Bank enable" "Bank 0,Bank 1,,,,,,Bank 7"
endif
rgroup.long 0x54++0x03
line.long 0x00 "FMSTAT,Flash Module Status Register"
bitfld.long 0x00 17. " RVSUSP ,Read verify suspend" "Not suspended,Suspended"
bitfld.long 0x00 16. " RVDER ,Read verify command currently underway" "Completed,In progress"
bitfld.long 0x00 15. " RVF ,Read verify failure" "Not failed,Failed"
textline " "
bitfld.long 0x00 14. " ILA ,Illegal address" "Not detected,Detected"
bitfld.long 0x00 13. " DBT ,Disturbance test fail" "Passed,Failed"
bitfld.long 0x00 12. " PGV ,Program verify" "Successful,Not successful"
textline " "
bitfld.long 0x00 11. " PCV ,Precondition verify" "Successful,Not successful"
bitfld.long 0x00 10. " EV ,Erase verify" "Successful,Not successful"
bitfld.long 0x00 9. " CV ,Compact verify" "Successful,Not successful"
textline " "
bitfld.long 0x00 8. " BUSY ,Program/erase or suspend operation is being process" "Not busy,Busy"
bitfld.long 0x00 7. " ERS ,Erase active" "Inactive,Active"
bitfld.long 0x00 6. " PGM ,Program active" "Inactive,Active"
textline " "
bitfld.long 0x00 5. " INVDAT ,Invalid data" "Valid,Invalid"
bitfld.long 0x00 4. " CSTAT ,Command status" "Not failed,Failed"
bitfld.long 0x00 3. " VOLTSTAT ,Core voltage status" "Not failed,Failed"
textline " "
bitfld.long 0x00 2. " ESUSP ,Erase suspend" "Not suspended,Suspended"
bitfld.long 0x00 1. " PSUSP ,Program suspend" "Not suspended,Suspended"
bitfld.long 0x00 0. " SLOCK ,Sector lock status" "Not locked,Locked"
textline " "
group.long 0x58++0x13
line.long 0x00 "FEMU_DMSW,EEPROM Emulation Data MSW Register"
line.long 0x04 "FEMU_DLSW,EEPROM Emulation Data LSW Register"
line.long 0x08 "FEMU_ECC,EEPROM Emulation ECC Register"
hexmask.long.byte 0x08 0.--7. 1. " EMU_ECC ,Mode 7 to XOR the ECC being delivered to the bus master"
line.long 0x0C "FLOCK,Flash Lock Register"
hexmask.long.word 0x0C 0.--15. 1. " ENCOM ,Enable writes to EE_FEDACCTRL1 register"
line.long 0x10 "FEMU_ADDR,EEPROM Emulation Address Register"
if (d.l(ad:0xFFF87000+0x6C)&0x07)==0x05
group.long 0x6C++0x03
line.long 0x00 "FDIAGCTRL,Diagnostic Control Register"
bitfld.long 0x00 24. " DIAG_TRIG ,Diagnostic trigger" "No effect,Trigger"
textline " "
bitfld.long 0x00 16.--19. " DIAG_EN_KEY ,Diagnostic enable key" "Disabled,Disabled,Disabled,Disabled,Disabled,Enabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled"
textline " "
bitfld.long 0x00 8.--10. " DIAG_BUF_SEL ,Diagnostic buffer select" "Port A buffer 0,Port A buffer 1,,,Port B buffer 0,Port B buffer 1,Port B buffer 2,Port B buffer 3"
textline " "
bitfld.long 0x00 0.--2. " DIAGMODE ,Diagnostic mode" "Disabled,,,,,Address tag register diagnostic mode,,ECC data correction diagnostic"
elif (d.l(ad:0xFFF87000+0x6C)&0x07)==0x07
group.long 0x6C++0x03
line.long 0x00 "FDIAGCTRL,Diagnostic Control Register"
bitfld.long 0x00 24. " DIAG_TRIG ,Diagnostic trigger" "No effect,Trigger"
textline " "
bitfld.long 0x00 16.--19. " DIAG_EN_KEY ,Diagnostic enable key" "Disabled,Disabled,Disabled,Disabled,Disabled,Enabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled"
textline " "
bitfld.long 0x00 8.--10. " DIAG_BUF_SEL ,Diagnostic buffer select (Diag mode 5/mode 7)" "Port A,,,,Port B,?..."
textline " "
bitfld.long 0x00 0.--2. " DIAGMODE ,Diagnostic mode" "Disabled,,,,,Address tag register diagnostic mode,,ECC data correction diagnostic"
else
group.long 0x6C++0x03
line.long 0x00 "FDIAGCTRL,Diagnostic Control Register"
bitfld.long 0x00 24. " DIAG_TRIG ,Diagnostic trigger" "No effect,Trigger"
textline " "
bitfld.long 0x00 16.--19. " DIAG_EN_KEY ,Diagnostic enable key" "Disabled,Disabled,Disabled,Disabled,Disabled,Enabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled"
textline " "
bitfld.long 0x00 0.--2. " DIAGMODE ,Diagnostic mode" "Disabled,,,,,Address tag register diagnostic mode,,ECC data correction diagnostic"
endif
group.long 0x74++0x03
line.long 0x00 "FRAW_ADDR,Raw Address Register"
hexmask.long 0x00 5.--31. 0x20 " RAW_DATA ,Raw address"
group.long 0x7C++0x03
line.long 0x00 "FPAR_OVR,Parity Override Register"
bitfld.long 0x00 16.--17. " PAR_OVR_SEL ,Select which parity checker to invert the polarity of the parity" "No effect,Idle state parity,Command parity,Internal address parity"
bitfld.long 0x00 12.--15. " PAR_DIS_KEY ,Disable access parity" "Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Disabled,Enabled,Enabled,Enabled,Enabled,Enabled"
textline " "
bitfld.long 0x00 9.--11. " PAR_OVR_KEY ,Parity override" "DEVCR1,DEVCR1,DEVCR1,DEVCR1,DEVCR1,SYS_ODD_PARITY,DEVCR1,DEVCR1"
rgroup.long 0xB4++0x03
line.long 0x00 "RCR_VALID,Reset Config Valid"
bitfld.long 0x00 1. " JSM_VALID ,L2FMC finishes the implicit read" "Not valid,Valid"
bitfld.long 0x00 0. " RCR_VALID ,L2FMC finishes the implicit read" "Not valid,Valid"
group.long 0xB8++0x03
line.long 0x00 "ACC_THRESHOLD,Crossbar Access Time Threshold Register"
hexmask.long.word 0x00 0.--11. 1. " ACC_THRESH_CNT ,Configures maximum number of clocks beyond which the L2FMC internal switch will timeout the NT access"
group.long 0xC0++0x03
line.long 0x00 "FEDACSDIS2,Flash Error Detection And Correction Sector Disable Register2"
bitfld.long 0x00 24.--29. " SECTORID3_INVERSE ,The sector ID inverse bits are used with the sector ID bits to determine which sector is disabled" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 16.--21. " SECTORID3 ,The sector ID bits are used with the sector ID inverse bits to determine which sector is disabled" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
textline " "
bitfld.long 0x00 8.--13. " SECTORID2_INVERSE ,The sector ID inverse bits are used with the sector ID bits to determine which sector is disabled" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 0.--5. " SECTORID2 ,The sector ID bits are used with the sector ID inverse bits to determine which sector is disabled" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
if (d.l(ad:0xFFF87000+0xB4)&0x01)==0x01
rgroup.long 0xD0++0x07
line.long 0x00 "RCR_VALUE0,Lower Word Of Reset Config Read"
line.long 0x04 "RCR_VALUE1,Upper Word Of Reset Config Read"
else
hgroup.long 0xD0++0x07
hide.long 0x00 "RCR_VALUE0,Lower Word Of Reset Config Read"
hide.long 0x04 "RCR_VALUE1,Upper Word Of Reset Config Read"
endif
group.long 0x110++0x03
line.long 0x00 "FADDR,Flash Address Register"
group.long 0x11C++0x03
line.long 0x00 "FTCTL,Flash ECC Autocalculation Register"
bitfld.long 0x00 24. " AUTOCALC_EN ,Automatic ECC Calculation" "Disabled,Enabled"
group.long 0x120++0x23
line.long 0x00 "FWPWRITE0,Flash Wide Programming Write Data Register 0"
line.long 0x04 "FWPWRITE1,Flash Wide Programming Write Data Register 1"
line.long 0x08 "FWPWRITE2,Flash Wide Programming Write Data Register 2"
line.long 0x0C "FWPWRITE3,Flash Wide Programming Write Data Register 3"
line.long 0x10 "FWPWRITE4,Flash Wide Programming Write Data Register 4"
line.long 0x14 "FWPWRITE5,Flash Wide Programming Write Data Register 5"
line.long 0x18 "FWPWRITE6,Flash Wide Programming Write Data Register 6"
line.long 0x1C "FWPWRITE7,Flash Wide Programming Write Data Register 7"
line.long 0x20 "FWPWRITE_ECC,Flash Wide Programming Write Data ECC Register"
group.long 0x20C++0x03
line.long 0x00 "FSM_COMMAND,Flash State Machine Command Register"
bitfld.long 0x00 1.--4. " COMMAND ,FSM Command" ",Program Data,,Erase Sector,Erase Bank,,,Validate Sector,Clear Status,,Program Resume,Erase Resume,Clear More,?..."
group.long 0x288++0x03
line.long 0x00 "FSM_WR_ENA,FSM Register Write Enable"
bitfld.long 0x00 0.--2. " WR_ENA ,FSM Write Enable" "Disabled,Disabled,Disabled,Disabled,Disabled,Enabled,Disabled,Disabled"
group.long 0x2B4++0x03
line.long 0x00 "FSM_EXECUTE,Flash State Machine Command Execute Register"
bitfld.long 0x00 16.--19. " SUSPEND_NOW ,Suspend Now" ",,,,,Suspended,,,,,Not suspended,?..."
bitfld.long 0x00 0.--4. " FSMEXECUTE ,FSM Execute" ",,,,,,,,,,Not executed,,,,,,,,,,,Executed,?..."
textline " "
group.long 0x2C0++0x07
line.long 0x00 "FSM_SECTOR1,FSM Sector Register 1"
bitfld.long 0x00 31. " SECT_ERASED[31] ,Sector 31 erased" "Erased,Not erased"
bitfld.long 0x00 30. " [30] ,Sector 30 erased" "Erased,Not erased"
bitfld.long 0x00 29. " [29] ,Sector 29 erased" "Erased,Not erased"
bitfld.long 0x00 28. " [28] ,Sector 28 erased" "Erased,Not erased"
textline " "
bitfld.long 0x00 27. " [27] ,Sector 27 erased" "Erased,Not erased"
bitfld.long 0x00 26. " [26] ,Sector 26 erased" "Erased,Not erased"
bitfld.long 0x00 25. " [25] ,Sector 25 erased" "Erased,Not erased"
bitfld.long 0x00 24. " [24] ,Sector 24 erased" "Erased,Not erased"
textline " "
bitfld.long 0x00 23. " [23] ,Sector 23 erased" "Erased,Not erased"
bitfld.long 0x00 22. " [22] ,Sector 22 erased" "Erased,Not erased"
bitfld.long 0x00 21. " [21] ,Sector 21 erased" "Erased,Not erased"
bitfld.long 0x00 20. " [20] ,Sector 20 erased" "Erased,Not erased"
textline " "
bitfld.long 0x00 19. " [19] ,Sector 19 erased" "Erased,Not erased"
bitfld.long 0x00 18. " [18] ,Sector 18 erased" "Erased,Not erased"
bitfld.long 0x00 17. " [17] ,Sector 17 erased" "Erased,Not erased"
bitfld.long 0x00 16. " [16] ,Sector 16 erased" "Erased,Not erased"
textline " "
bitfld.long 0x00 15. " [15] ,Sector 15 erased" "Erased,Not erased"
bitfld.long 0x00 14. " [14] ,Sector 14 erased" "Erased,Not erased"
bitfld.long 0x00 13. " [13] ,Sector 13 erased" "Erased,Not erased"
bitfld.long 0x00 12. " [12] ,Sector 12 erased" "Erased,Not erased"
textline " "
bitfld.long 0x00 11. " [11] ,Sector 11 erased" "Erased,Not erased"
bitfld.long 0x00 10. " [10] ,Sector 10 erased" "Erased,Not erased"
bitfld.long 0x00 9. " [9] ,Sector 9 erased" "Erased,Not erased"
bitfld.long 0x00 8. " [8] ,Sector 8 erased" "Erased,Not erased"
textline " "
bitfld.long 0x00 7. " [7] ,Sector 7 erased" "Erased,Not erased"
bitfld.long 0x00 6. " [6] ,Sector 6 erased" "Erased,Not erased"
bitfld.long 0x00 5. " [5] ,Sector 5 erased" "Erased,Not erased"
bitfld.long 0x00 4. " [4] ,Sector 4 erased" "Erased,Not erased"
textline " "
bitfld.long 0x00 3. " [3] ,Sector 3 erased" "Erased,Not erased"
bitfld.long 0x00 2. " [2] ,Sector 2 erased" "Erased,Not erased"
bitfld.long 0x00 1. " [1] ,Sector 1 erased" "Erased,Not erased"
bitfld.long 0x00 0. " [0] ,Sector 0 erased" "Erased,Not erased"
line.long 0x04 "FSM_SECTOR2,FSM Sector Register 2"
bitfld.long 0x04 31. " SECT_ERASED[63] ,Sector 63 erased" "Erased,Not erased"
bitfld.long 0x04 30. " [62] ,Sector 62 erased" "Erased,Not erased"
bitfld.long 0x04 29. " [61] ,Sector 61 erased" "Erased,Not erased"
bitfld.long 0x04 28. " [60] ,Sector 60 erased" "Erased,Not erased"
textline " "
bitfld.long 0x04 27. " [59] ,Sector 59 erased" "Erased,Not erased"
bitfld.long 0x04 26. " [58] ,Sector 58 erased" "Erased,Not erased"
bitfld.long 0x04 25. " [57] ,Sector 57 erased" "Erased,Not erased"
bitfld.long 0x04 24. " [56] ,Sector 56 erased" "Erased,Not erased"
textline " "
bitfld.long 0x04 23. " [55] ,Sector 55 erased" "Erased,Not erased"
bitfld.long 0x04 22. " [54] ,Sector 54 erased" "Erased,Not erased"
bitfld.long 0x04 21. " [53] ,Sector 53 erased" "Erased,Not erased"
bitfld.long 0x04 20. " [52] ,Sector 52 erased" "Erased,Not erased"
textline " "
bitfld.long 0x04 19. " [51] ,Sector 51 erased" "Erased,Not erased"
bitfld.long 0x04 18. " [50] ,Sector 50 erased" "Erased,Not erased"
bitfld.long 0x04 17. " [49] ,Sector 49 erased" "Erased,Not erased"
bitfld.long 0x04 16. " [48] ,Sector 48 erased" "Erased,Not erased"
textline " "
bitfld.long 0x04 15. " [47] ,Sector 47 erased" "Erased,Not erased"
bitfld.long 0x04 14. " [46] ,Sector 46 erased" "Erased,Not erased"
bitfld.long 0x04 13. " [45] ,Sector 45 erased" "Erased,Not erased"
bitfld.long 0x04 12. " [44] ,Sector 44 erased" "Erased,Not erased"
textline " "
bitfld.long 0x04 11. " [43] ,Sector 43 erased" "Erased,Not erased"
bitfld.long 0x04 10. " [42] ,Sector 42 erased" "Erased,Not erased"
bitfld.long 0x04 9. " [41] ,Sector 41 erased" "Erased,Not erased"
bitfld.long 0x04 8. " [40] ,Sector 40 erased" "Erased,Not erased"
textline " "
bitfld.long 0x04 7. " [39] ,Sector 39 erased" "Erased,Not erased"
bitfld.long 0x04 6. " [38] ,Sector 38 erased" "Erased,Not erased"
bitfld.long 0x04 5. " [37] ,Sector 37 erased" "Erased,Not erased"
bitfld.long 0x04 4. " [36] ,Sector 36 erased" "Erased,Not erased"
textline " "
bitfld.long 0x04 3. " [35] ,Sector 35 erased" "Erased,Not erased"
bitfld.long 0x04 2. " [34] ,Sector 34 erased" "Erased,Not erased"
bitfld.long 0x04 1. " [33] ,Sector 33 erased" "Erased,Not erased"
bitfld.long 0x04 0. " [32] ,Sector 32 erased" "Erased,Not erased"
textline " "
group.long 0x2B8++0x03
line.long 0x00 "EEPROM_CONFIG,EEPROM Emulation Configuration Register"
bitfld.long 0x00 16.--19. " EWAIT ,EEPROM wait state counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
rgroup.long 0x400++0x03
line.long 0x00 "FCFG_BANK,Flash Bank Configuration Register"
hexmask.long.word 0x00 20.--31. 1. " EE_BANK_WIDTH ,Bank 7 width"
hexmask.long.word 0x00 4.--15. 1. " MAIN_BANK_WIDTH ,Width of main flash banks"
width 0x0B
tree.end
tree "POM Control Registers"
base ad:0xFFA04000
width 15.
group.long 0x00++0x3
line.long 0x0 "GLBCTRL,Global Control Register"
hexmask.long.word 0x00 22.--31. 0x40 " OTADDR ,Overlay target Address"
bitfld.long 0x00 0.--3. " ON_OFF ,POM enable/disable" "Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Enabled,Disabled,Disabled,Disabled,Disabled,Disabled"
rgroup.long 0x04++0x3
line.long 0x0 "POMREV,Revision Id"
group.long 0x0C++0x3
line.long 0x0 "POMFLG,Flag Register"
eventfld.long 0x00 10. " PERR_SRESP_IDLE ,Idle response parity error on POM access" "Not occurred,Occurred"
eventfld.long 0x00 9. " PERR_PB ,Parity Error on POM access due to remapping request on PortB" "Not occurred,Occurred"
eventfld.long 0x00 8. " PERR_PA ,Parity Error on POM access due to remapping request on PortA" "Not occurred,Occurred"
width 13.
tree "Region Size/Start Address Registers"
group.long 0x200++0x0B
line.long 0x00 "PROGSTART0,Program Region Start Address Register 0"
hexmask.long.tbyte 0x00 6.--22. 0x40 " STARTADDRESS ,Defines the start address of the program memory region"
line.long 0x04 "OVLSTART0, Overlay Region Start Address Register 0"
hexmask.long.tbyte 0x04 6.--22. 0x40 " STARTADDRESS ,Defines the start address of the overlay memory region"
line.long 0x08 "REGSIZE0, Region Size Register 0"
bitfld.long 0x08 0.--3. " SIZE ,Region size" "Disabled,64 B,128 B,192 B,256 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,?..."
group.long 0x210++0x0B
line.long 0x00 "PROGSTART1,Program Region Start Address Register 1"
hexmask.long.tbyte 0x00 6.--22. 0x40 " STARTADDRESS ,Defines the start address of the program memory region"
line.long 0x04 "OVLSTART1, Overlay Region Start Address Register 1"
hexmask.long.tbyte 0x04 6.--22. 0x40 " STARTADDRESS ,Defines the start address of the overlay memory region"
line.long 0x08 "REGSIZE1, Region Size Register 1"
bitfld.long 0x08 0.--3. " SIZE ,Region size" "Disabled,64 B,128 B,192 B,256 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,?..."
group.long 0x220++0x0B
line.long 0x00 "PROGSTART2,Program Region Start Address Register 2"
hexmask.long.tbyte 0x00 6.--22. 0x40 " STARTADDRESS ,Defines the start address of the program memory region"
line.long 0x04 "OVLSTART2, Overlay Region Start Address Register 2"
hexmask.long.tbyte 0x04 6.--22. 0x40 " STARTADDRESS ,Defines the start address of the overlay memory region"
line.long 0x08 "REGSIZE2, Region Size Register 2"
bitfld.long 0x08 0.--3. " SIZE ,Region size" "Disabled,64 B,128 B,192 B,256 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,?..."
group.long 0x230++0x0B
line.long 0x00 "PROGSTART3,Program Region Start Address Register 3"
hexmask.long.tbyte 0x00 6.--22. 0x40 " STARTADDRESS ,Defines the start address of the program memory region"
line.long 0x04 "OVLSTART3, Overlay Region Start Address Register 3"
hexmask.long.tbyte 0x04 6.--22. 0x40 " STARTADDRESS ,Defines the start address of the overlay memory region"
line.long 0x08 "REGSIZE3, Region Size Register 3"
bitfld.long 0x08 0.--3. " SIZE ,Region size" "Disabled,64 B,128 B,192 B,256 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,?..."
group.long 0x240++0x0B
line.long 0x00 "PROGSTART4,Program Region Start Address Register 4"
hexmask.long.tbyte 0x00 6.--22. 0x40 " STARTADDRESS ,Defines the start address of the program memory region"
line.long 0x04 "OVLSTART4, Overlay Region Start Address Register 4"
hexmask.long.tbyte 0x04 6.--22. 0x40 " STARTADDRESS ,Defines the start address of the overlay memory region"
line.long 0x08 "REGSIZE4, Region Size Register 4"
bitfld.long 0x08 0.--3. " SIZE ,Region size" "Disabled,64 B,128 B,192 B,256 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,?..."
group.long 0x250++0x0B
line.long 0x00 "PROGSTART5,Program Region Start Address Register 5"
hexmask.long.tbyte 0x00 6.--22. 0x40 " STARTADDRESS ,Defines the start address of the program memory region"
line.long 0x04 "OVLSTART5, Overlay Region Start Address Register 5"
hexmask.long.tbyte 0x04 6.--22. 0x40 " STARTADDRESS ,Defines the start address of the overlay memory region"
line.long 0x08 "REGSIZE5, Region Size Register 5"
bitfld.long 0x08 0.--3. " SIZE ,Region size" "Disabled,64 B,128 B,192 B,256 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,?..."
group.long 0x260++0x0B
line.long 0x00 "PROGSTART6,Program Region Start Address Register 6"
hexmask.long.tbyte 0x00 6.--22. 0x40 " STARTADDRESS ,Defines the start address of the program memory region"
line.long 0x04 "OVLSTART6, Overlay Region Start Address Register 6"
hexmask.long.tbyte 0x04 6.--22. 0x40 " STARTADDRESS ,Defines the start address of the overlay memory region"
line.long 0x08 "REGSIZE6, Region Size Register 6"
bitfld.long 0x08 0.--3. " SIZE ,Region size" "Disabled,64 B,128 B,192 B,256 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,?..."
group.long 0x270++0x0B
line.long 0x00 "PROGSTART7,Program Region Start Address Register 7"
hexmask.long.tbyte 0x00 6.--22. 0x40 " STARTADDRESS ,Defines the start address of the program memory region"
line.long 0x04 "OVLSTART7, Overlay Region Start Address Register 7"
hexmask.long.tbyte 0x04 6.--22. 0x40 " STARTADDRESS ,Defines the start address of the overlay memory region"
line.long 0x08 "REGSIZE7, Region Size Register 7"
bitfld.long 0x08 0.--3. " SIZE ,Region size" "Disabled,64 B,128 B,192 B,256 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,?..."
group.long 0x280++0x0B
line.long 0x00 "PROGSTART8,Program Region Start Address Register 8"
hexmask.long.tbyte 0x00 6.--22. 0x40 " STARTADDRESS ,Defines the start address of the program memory region"
line.long 0x04 "OVLSTART8, Overlay Region Start Address Register 8"
hexmask.long.tbyte 0x04 6.--22. 0x40 " STARTADDRESS ,Defines the start address of the overlay memory region"
line.long 0x08 "REGSIZE8, Region Size Register 8"
bitfld.long 0x08 0.--3. " SIZE ,Region size" "Disabled,64 B,128 B,192 B,256 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,?..."
group.long 0x290++0x0B
line.long 0x00 "PROGSTART9,Program Region Start Address Register 9"
hexmask.long.tbyte 0x00 6.--22. 0x40 " STARTADDRESS ,Defines the start address of the program memory region"
line.long 0x04 "OVLSTART9, Overlay Region Start Address Register 9"
hexmask.long.tbyte 0x04 6.--22. 0x40 " STARTADDRESS ,Defines the start address of the overlay memory region"
line.long 0x08 "REGSIZE9, Region Size Register 9"
bitfld.long 0x08 0.--3. " SIZE ,Region size" "Disabled,64 B,128 B,192 B,256 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,?..."
group.long 0x2A0++0x0B
line.long 0x00 "PROGSTART10,Program Region Start Address Register 10"
hexmask.long.tbyte 0x00 6.--22. 0x40 " STARTADDRESS ,Defines the start address of the program memory region"
line.long 0x04 "OVLSTART10, Overlay Region Start Address Register 10"
hexmask.long.tbyte 0x04 6.--22. 0x40 " STARTADDRESS ,Defines the start address of the overlay memory region"
line.long 0x08 "REGSIZE10, Region Size Register 10"
bitfld.long 0x08 0.--3. " SIZE ,Region size" "Disabled,64 B,128 B,192 B,256 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,?..."
group.long 0x2B0++0x0B
line.long 0x00 "PROGSTART11,Program Region Start Address Register 11"
hexmask.long.tbyte 0x00 6.--22. 0x40 " STARTADDRESS ,Defines the start address of the program memory region"
line.long 0x04 "OVLSTART11, Overlay Region Start Address Register 11"
hexmask.long.tbyte 0x04 6.--22. 0x40 " STARTADDRESS ,Defines the start address of the overlay memory region"
line.long 0x08 "REGSIZE11, Region Size Register 11"
bitfld.long 0x08 0.--3. " SIZE ,Region size" "Disabled,64 B,128 B,192 B,256 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,?..."
group.long 0x2C0++0x0B
line.long 0x00 "PROGSTART12,Program Region Start Address Register 12"
hexmask.long.tbyte 0x00 6.--22. 0x40 " STARTADDRESS ,Defines the start address of the program memory region"
line.long 0x04 "OVLSTART12, Overlay Region Start Address Register 12"
hexmask.long.tbyte 0x04 6.--22. 0x40 " STARTADDRESS ,Defines the start address of the overlay memory region"
line.long 0x08 "REGSIZE12, Region Size Register 12"
bitfld.long 0x08 0.--3. " SIZE ,Region size" "Disabled,64 B,128 B,192 B,256 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,?..."
group.long 0x2D0++0x0B
line.long 0x00 "PROGSTART13,Program Region Start Address Register 13"
hexmask.long.tbyte 0x00 6.--22. 0x40 " STARTADDRESS ,Defines the start address of the program memory region"
line.long 0x04 "OVLSTART13, Overlay Region Start Address Register 13"
hexmask.long.tbyte 0x04 6.--22. 0x40 " STARTADDRESS ,Defines the start address of the overlay memory region"
line.long 0x08 "REGSIZE13, Region Size Register 13"
bitfld.long 0x08 0.--3. " SIZE ,Region size" "Disabled,64 B,128 B,192 B,256 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,?..."
group.long 0x2E0++0x0B
line.long 0x00 "PROGSTART14,Program Region Start Address Register 14"
hexmask.long.tbyte 0x00 6.--22. 0x40 " STARTADDRESS ,Defines the start address of the program memory region"
line.long 0x04 "OVLSTART14, Overlay Region Start Address Register 14"
hexmask.long.tbyte 0x04 6.--22. 0x40 " STARTADDRESS ,Defines the start address of the overlay memory region"
line.long 0x08 "REGSIZE14, Region Size Register 14"
bitfld.long 0x08 0.--3. " SIZE ,Region size" "Disabled,64 B,128 B,192 B,256 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,?..."
group.long 0x2F0++0x0B
line.long 0x00 "PROGSTART15,Program Region Start Address Register 15"
hexmask.long.tbyte 0x00 6.--22. 0x40 " STARTADDRESS ,Defines the start address of the program memory region"
line.long 0x04 "OVLSTART15, Overlay Region Start Address Register 15"
hexmask.long.tbyte 0x04 6.--22. 0x40 " STARTADDRESS ,Defines the start address of the overlay memory region"
line.long 0x08 "REGSIZE15, Region Size Register 15"
bitfld.long 0x08 0.--3. " SIZE ,Region size" "Disabled,64 B,128 B,192 B,256 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,?..."
group.long 0x300++0x0B
line.long 0x00 "PROGSTART16,Program Region Start Address Register 16"
hexmask.long.tbyte 0x00 6.--22. 0x40 " STARTADDRESS ,Defines the start address of the program memory region"
line.long 0x04 "OVLSTART16, Overlay Region Start Address Register 16"
hexmask.long.tbyte 0x04 6.--22. 0x40 " STARTADDRESS ,Defines the start address of the overlay memory region"
line.long 0x08 "REGSIZE16, Region Size Register 16"
bitfld.long 0x08 0.--3. " SIZE ,Region size" "Disabled,64 B,128 B,192 B,256 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,?..."
group.long 0x310++0x0B
line.long 0x00 "PROGSTART17,Program Region Start Address Register 17"
hexmask.long.tbyte 0x00 6.--22. 0x40 " STARTADDRESS ,Defines the start address of the program memory region"
line.long 0x04 "OVLSTART17, Overlay Region Start Address Register 17"
hexmask.long.tbyte 0x04 6.--22. 0x40 " STARTADDRESS ,Defines the start address of the overlay memory region"
line.long 0x08 "REGSIZE17, Region Size Register 17"
bitfld.long 0x08 0.--3. " SIZE ,Region size" "Disabled,64 B,128 B,192 B,256 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,?..."
group.long 0x320++0x0B
line.long 0x00 "PROGSTART18,Program Region Start Address Register 18"
hexmask.long.tbyte 0x00 6.--22. 0x40 " STARTADDRESS ,Defines the start address of the program memory region"
line.long 0x04 "OVLSTART18, Overlay Region Start Address Register 18"
hexmask.long.tbyte 0x04 6.--22. 0x40 " STARTADDRESS ,Defines the start address of the overlay memory region"
line.long 0x08 "REGSIZE18, Region Size Register 18"
bitfld.long 0x08 0.--3. " SIZE ,Region size" "Disabled,64 B,128 B,192 B,256 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,?..."
group.long 0x330++0x0B
line.long 0x00 "PROGSTART19,Program Region Start Address Register 19"
hexmask.long.tbyte 0x00 6.--22. 0x40 " STARTADDRESS ,Defines the start address of the program memory region"
line.long 0x04 "OVLSTART19, Overlay Region Start Address Register 19"
hexmask.long.tbyte 0x04 6.--22. 0x40 " STARTADDRESS ,Defines the start address of the overlay memory region"
line.long 0x08 "REGSIZE19, Region Size Register 19"
bitfld.long 0x08 0.--3. " SIZE ,Region size" "Disabled,64 B,128 B,192 B,256 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,?..."
group.long 0x340++0x0B
line.long 0x00 "PROGSTART20,Program Region Start Address Register 20"
hexmask.long.tbyte 0x00 6.--22. 0x40 " STARTADDRESS ,Defines the start address of the program memory region"
line.long 0x04 "OVLSTART20, Overlay Region Start Address Register 20"
hexmask.long.tbyte 0x04 6.--22. 0x40 " STARTADDRESS ,Defines the start address of the overlay memory region"
line.long 0x08 "REGSIZE20, Region Size Register 20"
bitfld.long 0x08 0.--3. " SIZE ,Region size" "Disabled,64 B,128 B,192 B,256 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,?..."
group.long 0x350++0x0B
line.long 0x00 "PROGSTART21,Program Region Start Address Register 21"
hexmask.long.tbyte 0x00 6.--22. 0x40 " STARTADDRESS ,Defines the start address of the program memory region"
line.long 0x04 "OVLSTART21, Overlay Region Start Address Register 21"
hexmask.long.tbyte 0x04 6.--22. 0x40 " STARTADDRESS ,Defines the start address of the overlay memory region"
line.long 0x08 "REGSIZE21, Region Size Register 21"
bitfld.long 0x08 0.--3. " SIZE ,Region size" "Disabled,64 B,128 B,192 B,256 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,?..."
group.long 0x360++0x0B
line.long 0x00 "PROGSTART22,Program Region Start Address Register 22"
hexmask.long.tbyte 0x00 6.--22. 0x40 " STARTADDRESS ,Defines the start address of the program memory region"
line.long 0x04 "OVLSTART22, Overlay Region Start Address Register 22"
hexmask.long.tbyte 0x04 6.--22. 0x40 " STARTADDRESS ,Defines the start address of the overlay memory region"
line.long 0x08 "REGSIZE22, Region Size Register 22"
bitfld.long 0x08 0.--3. " SIZE ,Region size" "Disabled,64 B,128 B,192 B,256 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,?..."
group.long 0x370++0x0B
line.long 0x00 "PROGSTART23,Program Region Start Address Register 23"
hexmask.long.tbyte 0x00 6.--22. 0x40 " STARTADDRESS ,Defines the start address of the program memory region"
line.long 0x04 "OVLSTART23, Overlay Region Start Address Register 23"
hexmask.long.tbyte 0x04 6.--22. 0x40 " STARTADDRESS ,Defines the start address of the overlay memory region"
line.long 0x08 "REGSIZE23, Region Size Register 23"
bitfld.long 0x08 0.--3. " SIZE ,Region size" "Disabled,64 B,128 B,192 B,256 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,?..."
group.long 0x380++0x0B
line.long 0x00 "PROGSTART24,Program Region Start Address Register 24"
hexmask.long.tbyte 0x00 6.--22. 0x40 " STARTADDRESS ,Defines the start address of the program memory region"
line.long 0x04 "OVLSTART24, Overlay Region Start Address Register 24"
hexmask.long.tbyte 0x04 6.--22. 0x40 " STARTADDRESS ,Defines the start address of the overlay memory region"
line.long 0x08 "REGSIZE24, Region Size Register 24"
bitfld.long 0x08 0.--3. " SIZE ,Region size" "Disabled,64 B,128 B,192 B,256 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,?..."
group.long 0x390++0x0B
line.long 0x00 "PROGSTART25,Program Region Start Address Register 25"
hexmask.long.tbyte 0x00 6.--22. 0x40 " STARTADDRESS ,Defines the start address of the program memory region"
line.long 0x04 "OVLSTART25, Overlay Region Start Address Register 25"
hexmask.long.tbyte 0x04 6.--22. 0x40 " STARTADDRESS ,Defines the start address of the overlay memory region"
line.long 0x08 "REGSIZE25, Region Size Register 25"
bitfld.long 0x08 0.--3. " SIZE ,Region size" "Disabled,64 B,128 B,192 B,256 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,?..."
group.long 0x3A0++0x0B
line.long 0x00 "PROGSTART26,Program Region Start Address Register 26"
hexmask.long.tbyte 0x00 6.--22. 0x40 " STARTADDRESS ,Defines the start address of the program memory region"
line.long 0x04 "OVLSTART26, Overlay Region Start Address Register 26"
hexmask.long.tbyte 0x04 6.--22. 0x40 " STARTADDRESS ,Defines the start address of the overlay memory region"
line.long 0x08 "REGSIZE26, Region Size Register 26"
bitfld.long 0x08 0.--3. " SIZE ,Region size" "Disabled,64 B,128 B,192 B,256 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,?..."
group.long 0x3B0++0x0B
line.long 0x00 "PROGSTART27,Program Region Start Address Register 27"
hexmask.long.tbyte 0x00 6.--22. 0x40 " STARTADDRESS ,Defines the start address of the program memory region"
line.long 0x04 "OVLSTART27, Overlay Region Start Address Register 27"
hexmask.long.tbyte 0x04 6.--22. 0x40 " STARTADDRESS ,Defines the start address of the overlay memory region"
line.long 0x08 "REGSIZE27, Region Size Register 27"
bitfld.long 0x08 0.--3. " SIZE ,Region size" "Disabled,64 B,128 B,192 B,256 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,?..."
group.long 0x3C0++0x0B
line.long 0x00 "PROGSTART28,Program Region Start Address Register 28"
hexmask.long.tbyte 0x00 6.--22. 0x40 " STARTADDRESS ,Defines the start address of the program memory region"
line.long 0x04 "OVLSTART28, Overlay Region Start Address Register 28"
hexmask.long.tbyte 0x04 6.--22. 0x40 " STARTADDRESS ,Defines the start address of the overlay memory region"
line.long 0x08 "REGSIZE28, Region Size Register 28"
bitfld.long 0x08 0.--3. " SIZE ,Region size" "Disabled,64 B,128 B,192 B,256 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,?..."
group.long 0x3D0++0x0B
line.long 0x00 "PROGSTART29,Program Region Start Address Register 29"
hexmask.long.tbyte 0x00 6.--22. 0x40 " STARTADDRESS ,Defines the start address of the program memory region"
line.long 0x04 "OVLSTART29, Overlay Region Start Address Register 29"
hexmask.long.tbyte 0x04 6.--22. 0x40 " STARTADDRESS ,Defines the start address of the overlay memory region"
line.long 0x08 "REGSIZE29, Region Size Register 29"
bitfld.long 0x08 0.--3. " SIZE ,Region size" "Disabled,64 B,128 B,192 B,256 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,?..."
group.long 0x3E0++0x0B
line.long 0x00 "PROGSTART30,Program Region Start Address Register 30"
hexmask.long.tbyte 0x00 6.--22. 0x40 " STARTADDRESS ,Defines the start address of the program memory region"
line.long 0x04 "OVLSTART30, Overlay Region Start Address Register 30"
hexmask.long.tbyte 0x04 6.--22. 0x40 " STARTADDRESS ,Defines the start address of the overlay memory region"
line.long 0x08 "REGSIZE30, Region Size Register 30"
bitfld.long 0x08 0.--3. " SIZE ,Region size" "Disabled,64 B,128 B,192 B,256 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,?..."
group.long 0x3F0++0x0B
line.long 0x00 "PROGSTART31,Program Region Start Address Register 31"
hexmask.long.tbyte 0x00 6.--22. 0x40 " STARTADDRESS ,Defines the start address of the program memory region"
line.long 0x04 "OVLSTART31, Overlay Region Start Address Register 31"
hexmask.long.tbyte 0x04 6.--22. 0x40 " STARTADDRESS ,Defines the start address of the overlay memory region"
line.long 0x08 "REGSIZE31, Region Size Register 31"
bitfld.long 0x08 0.--3. " SIZE ,Region size" "Disabled,64 B,128 B,192 B,256 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,?..."
tree.end
width 0x0B
tree.end
tree.end
tree "L2RAMW (Level 2 RAM)"
base ad:0xFFFFF900
width 20.
group.long 0x00++0x03
line.long 0x00 "RAMCTRL,Module Control Register"
bitfld.long 0x00 30. " EMU_TRACE_DIS ,Emulation mode trace disable" "No,Yes"
bitfld.long 0x00 24.--27. " ADDR_PARITY_OVERRIDE ,Address parity override" "Not inverted,Not inverted,Not inverted,Not inverted,Not inverted,Not inverted,Not inverted,Not inverted,Not inverted,Not inverted,Inverted,Not inverted,Not inverted,Not inverted,Not inverted,Not inverted"
bitfld.long 0x00 20. " MSE ,Memory scrubbing enable" "Disabled,Enabled"
bitfld.long 0x00 16.--19. " ADDR_PARITY_DISABLE ,Address/control bus parity detect disable" "No,No,No,No,No,No,No,No,No,No,Yes,No,No,No,No,No"
textline " "
bitfld.long 0x00 12. " EEMMS ,Enable ESM notification for write back during memory scrubbing" "Disabled,Enabled"
bitfld.long 0x00 8. " ECC_WR_EN ,ECC write enable" "Disabled,Enabled"
bitfld.long 0x00 4. " CPUWSC ,CPU write SERR capture" "Disabled,Enabled"
bitfld.long 0x00 0.--3. " ECC_DETECT_EN ,ECC detect enable" "Enabled,Enabled,Enabled,Enabled,Enabled,Disabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled"
textline " "
group.long 0x10++0x03
line.long 0x00 "RAMERRSTATUS,Error Status Register"
eventfld.long 0x00 22. " DRDE ,Diagnostic read Double-bit error" "Not occurred,Occurred"
eventfld.long 0x00 21. " DRSE ,Diagnostic read Single-bit error" "Not occurred,Occurred"
eventfld.long 0x00 20. " DWDE ,Diagnostic write Double-bit error" "Not occurred,Occurred"
eventfld.long 0x00 19. " DWSE ,Diagnostic write Single-bit error" "Not occurred,Occurred"
textline " "
eventfld.long 0x00 18. " MSSM ,Memory scrubbing write back SECDED malfunction" "Not occurred,Occurred"
eventfld.long 0x00 17. " MSRA ,Memory scrubbing write back redundant address decode error" "Not occurred,Occurred"
eventfld.long 0x00 16. " MSACP ,Memory scrubbing write back redundant address decode error" "Not occurred,Occurred"
eventfld.long 0x00 15. " CPEOI ,Command parity error on idle" "Not occurred,Occurred"
textline " "
eventfld.long 0x00 14. " EAE ,Exclusive access error" "Not occurred,Occurred"
eventfld.long 0x00 13. " MIE ,Memory initialization error" "Not occurred,Occurred"
eventfld.long 0x00 12. " MMDE ,Merged MUX diagnostic error" "Not occurred,Occurred"
eventfld.long 0x00 11. " WEMDE ,Write ECC malfunction diagnostic error" "Not occurred,Occurred"
textline " "
eventfld.long 0x00 10. " REMDE ,Read ECC malfunction diagnostic error" "Not occurred,Occurred"
eventfld.long 0x00 9. " MME ,Merged mux error" "Not occurred,Occurred"
eventfld.long 0x00 8. " PACE ,Parity address control error" "Not occurred,Occurred"
eventfld.long 0x00 7. " RMWDE ,Read-Modify-Write double bit error" "Not occurred,Occurred"
textline " "
eventfld.long 0x00 5. " DERR ,ECC uncorrectable (Double bit) error was detected during write access" "Not occurred,Occurred"
eventfld.long 0x00 3. " WEME ,Write ECC malfunction error" "Not occurred,Occurred"
eventfld.long 0x00 2. " ADE ,Address decode error" "Not occurred,Occurred"
eventfld.long 0x00 1. " REME ,Read ECC malfunction error" "Not occurred,Occurred"
textline " "
eventfld.long 0x00 0. " CPUWE ,CPU write single error" "Not occurred,Occurred"
group.long 0x24++0x0B
line.long 0x00 "DIAG_DATA_VECTOR_H,Diagnostic Data Vector High Register"
line.long 0x04 "DIAG_DATA_VECTOR_L,Diagnostic Data Vector Low Register"
line.long 0x08 "DIAG_ECC,Diagnostic ECC Vector Register"
hexmask.long.byte 0x08 0.--7. 1. " DIAG_ECC_VECTOR ,Diagnostic ECC vector"
group.long 0x30++0x03
line.long 0x00 "RAMTEST,L2RAMW Module Test Mode Control Register"
bitfld.long 0x00 8. " TRIGGER ,Test trigger" "No effect,Trigger"
bitfld.long 0x00 6.--7. " TEST_MODE ,Test mode" ",Inequality check is done,Equality check is done,?..."
bitfld.long 0x00 0.--3. " TEST_ENABLE ,Test enable" "Disabled,Disabled,Disabled,Disabled,Disabled,Enabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled"
group.long 0x38++0x03
line.long 0x00 "RAMADDRDEC_VECT,L2RAMW RAM Address Decode Vector Test Register"
bitfld.long 0x00 26. " DESV ,Diagnostic ECC select vector" "Not selected,Selected"
hexmask.long.word 0x00 0.--15. 1. " RAM_CHIP_SELECT ,RAM chip select"
textline " "
group.long 0x3C++0x03
line.long 0x00 "MEMINIT_DOMAIN,L2RAMW Memory Initialization Domain Register"
bitfld.long 0x00 7. " MEMINIT_ENA_[7] ,Enable bit for power domain 7" "Disabled,Enabled"
bitfld.long 0x00 6. " [6] ,Enable bit for power domain 6" "Disabled,Enabled"
bitfld.long 0x00 5. " [5] ,Enable bit for power domain 5" "Disabled,Enabled"
bitfld.long 0x00 4. " [4] ,Enable bit for power domain 4" "Disabled,Enabled"
textline " "
bitfld.long 0x00 3. " [3] ,Enable bit for power domain 3" "Disabled,Enabled"
bitfld.long 0x00 2. " [2] ,Enable bit for power domain 2" "Disabled,Enabled"
bitfld.long 0x00 1. " [1] ,Enable bit for power domain 1" "Disabled,Enabled"
bitfld.long 0x00 0. " [0] ,Enable bit for power domain 0" "Disabled,Enabled"
rgroup.long 0x44++0x07
line.long 0x00 "BANK_DOMAIN_MAP0,L2RAMW Bank To Domain Mapping Register0"
bitfld.long 0x00 28.--30. " BANK_MAP_[7] ,Allows the software to read the memory power domain number that bank 7 is associated" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 24.--26. " [6] ,Allows the software to read the memory power domain number that bank 6 is associated" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--22. " [5] ,Allows the software to read the memory power domain number that bank 5 is associated" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 16.--18. " [4] ,Allows the software to read the memory power domain number that bank 4 is associated" "0,1,2,3,4,5,6,7"
textline " "
bitfld.long 0x00 12.--14. " [3] ,Allows the software to read the memory power domain number that bank 3 is associated" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 8.--10. " [2] ,Allows the software to read the memory power domain number that bank 2 is associated" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 4.--6. " [1] ,Allows the software to read the memory power domain number that bank 1 is associated" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0.--2. " [0] ,Allows the software to read the memory power domain number that bank 0 is associated" "0,1,2,3,4,5,6,7"
line.long 0x04 "BANK_DOMAIN_MAP1,Bank To Domain Mapping Register1"
bitfld.long 0x04 28.--30. " BANK_MAP_[15] ,Allows the software to read the memory power domain number that bank 15 is associated" "0,1,2,3,4,5,6,7"
bitfld.long 0x04 24.--26. " [14] ,Allows the software to read the memory power domain number that bank 14 is associated" "0,1,2,3,4,5,6,7"
bitfld.long 0x04 20.--22. " [13] ,Allows the software to read the memory power domain number that bank 13 is associated" "0,1,2,3,4,5,6,7"
bitfld.long 0x04 16.--18. " [12] ,Allows the software to read the memory power domain number that bank 12 is associated" "0,1,2,3,4,5,6,7"
textline " "
bitfld.long 0x04 12.--14. " [11] ,Allows the software to read the memory power domain number that bank 11 is associated" "0,1,2,3,4,5,6,7"
bitfld.long 0x04 8.--10. " [10] ,Allows the software to read the memory power domain number that bank 10 is associated" "0,1,2,3,4,5,6,7"
bitfld.long 0x04 4.--6. " [9] ,Allows the software to read the memory power domain number that bank 9 is associated" "0,1,2,3,4,5,6,7"
bitfld.long 0x04 0.--2. " [8] ,Allows the software to read the memory power domain number that bank 8 is associated" "0,1,2,3,4,5,6,7"
width 0x0B
tree.end
tree "PBIST (Programmable Built-In Self-Test)"
base ad:0xFFFFE400
sif (cpuis("TMS570LS09*")||cpuis("TMS570LS07*")||cpuis("TMS570LS0232"))
endian.be
endif
width 9.
group.long 0x160++0x07
line.long 0x00 "RAMT,RAM Configuration Register"
hexmask.long.byte 0x00 24.--31. 1. " RGS ,Ram group select"
hexmask.long.byte 0x00 16.--23. 1. " RDS ,Return data select"
hexmask.long.byte 0x00 8.--15. 1. " DWR ,Data width register"
newline
bitfld.long 0x00 6.--7. " SMS ,Sense margin select register" "0,1,2,3"
bitfld.long 0x00 2.--5. " PLS ,Pipeline latency select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--1. " RLS ,RAM latency select" "0,1,2,3"
line.long 0x04 "DLR,Datalogger Register"
bitfld.long 0x04 4. " DLR4 ,Allow the host processor to configure the PBIST controller" "Not allowed,Allowed"
bitfld.long 0x04 2. " DLR2 ,Enable PBIST controller to execute test algorithms that are stored in the PBIST ROM" "Disabled,Enabled"
sif cpuis("TMS570LS0232")
group.long 0x16C++0x03
line.long 0x00 "PCR,Program Control Register"
bitfld.long 0x00 0.--4. " STR ,PBIST controller mode" ",Start/Time stamp mode restart,Resume/Emulation read,,Stop,,,,Step/Step for emulation mode,,Check MISR mode,?..."
endif
group.long 0x180++0x0B
line.long 0x00 "PACT,PBIST Activate/Clock Enable Register"
sif (!cpuis("TMS570LS09*")&&!cpuis("TMS570LS07*")&&!cpuis("TMS570LS0232"))
bitfld.long 0x00 1. " PACT1 ,PBIST activate" "Not activated,Activated"
newline
endif
sif (cpuis("TMS570LS09*")||cpuis("TMS570LS07*")||cpuis("TMS570LS0232"))
bitfld.long 0x00 0. " PACT0 ,PBIST internal clocks enable" "Disabled,Enabled"
else
bitfld.long 0x00 0. " PACT0 ,ROM clock enable register" "Disabled,Enabled"
endif
line.long 0x04 "PBISTID,PBIST ID Register"
hexmask.long.byte 0x04 0.--7. 1. " PBIST_ID ,Unique ID assigned to each PBIST controller in a device with multiple PBIST controllers"
line.long 0x08 "OVER,Override Register"
bitfld.long 0x08 0. " OVER0 ,RINFO override bit" "No override,Override"
rgroup.long 0x190++0x03
line.long 0x00 "FSRF0,Fail Status Fail Register 0"
bitfld.long 0x00 0. " FSRF0 ,Fail status 0" "Not occurred,Occurred"
sif (!cpuis("TMS570LS09*")&&!cpuis("TMS570LS07*")&&!cpuis("TMS570LS0232"))
rgroup.long 0x194++0x03
line.long 0x00 "FSRF1,Fail Status Fail Register 1"
bitfld.long 0x00 0. " FSRF1 ,Fail status 1" "Not occurred,Occurred"
endif
rgroup.long 0x198++0x13
line.long 0x00 "FSRC0,Fail Status Count 0 Register"
hexmask.long.byte 0x00 0.--7. 1. " FSRC0 ,Number of failures on port 0"
line.long 0x04 "FSRC1,Fail Status Count 1 Register"
hexmask.long.byte 0x04 0.--7. 1. " FSRC1 ,Number of failures on port 1"
line.long 0x08 "FSRA0,Fail Status Address 0 Registers"
hexmask.long.word 0x08 0.--15. 1. " FSRA0 ,Address of the first failure"
line.long 0x0C "FSRA1,Fail Status Address 1 Registers"
hexmask.long.word 0x0C 0.--15. 1. " FSRA1 ,Address of the first failure"
line.long 0x10 "FSRDL0,Fail Status Data Register 0"
sif (cpuis("TMS570LS09*")||cpuis("TMS570LS07*")||cpuis("TMS570LS0232"))
rgroup.long 0x1B0++0x03
line.long 0x00 "FSRDL1,Fail Status Data Register 1"
else
rgroup.long 0x1AC++0x03
line.long 0x00 "FSRDL1,Fail Status Data Register 1"
endif
group.long 0x1C0++0x07
line.long 0x00 "ROM,ROM Mask Register"
bitfld.long 0x00 0.--1. " ROM ,ROM mask" "No information,RAM group,Algorithm,Algorithm & RAM"
newline
line.long 0x04 "ALGO,ROM Algorithm Mask Register"
sif (cpuis("TMS570LS09*")||cpuis("TMS570LS07*")||cpuis("TMS570LS0232"))
bitfld.long 0x04 31. " ALGO_[31] ,Algorithm powerup_invpowerup - single_port" "Not selected,Selected"
bitfld.long 0x04 30. " [30] ,Algorithm powerup_invpowerup - two_port" "Not selected,Selected"
bitfld.long 0x04 29. " [29] ,Algorithm iddqrowstripe - single_port" "Not selected,Selected"
newline
bitfld.long 0x04 28. " [28] ,Algorithm iddqrowstripe - two_port" "Not selected,Selected"
bitfld.long 0x04 27. " [27] ,Algorithm iddqrowstripe - single_port" "Not selected,Selected"
bitfld.long 0x04 26. " [26] ,Algorithm iddqrowstripe - two_port" "Not selected,Selected"
newline
bitfld.long 0x04 25. " [25] ,Algorithm retention - single_port" "Not selected,Selected"
bitfld.long 0x04 24. " [24] ,Algorithm retention - two_port" "Not selected,Selected"
bitfld.long 0x04 23. " [23] ,Algorithm iddq - single_port" "Not selected,Selected"
newline
bitfld.long 0x04 22. " [22] ,Algorithm iddq - two_port" "Not selected,Selected"
bitfld.long 0x04 21. " [21] ,Algorithm retention - single_port" "Not selected,Selected"
bitfld.long 0x04 20. " [20] ,Algorithm retention - two_port" "Not selected,Selected"
newline
bitfld.long 0x04 19. " [19] ,Algorithm iddq - single_port" "Not selected,Selected"
bitfld.long 0x04 18. " [18] ,Algorithm iddq - two_port" "Not selected,Selected"
bitfld.long 0x04 17. " [17] ,Algorithm flip10 - single_port" "Not selected,Selected"
newline
bitfld.long 0x04 16. " [16] ,Algorithm flip10 - two_port" "Not selected,Selected"
bitfld.long 0x04 15. " [15] ,Algorithm pmos_open_slice2 - two_port" "Not selected,Selected"
bitfld.long 0x04 14. " [14] ,Algorithm pmos_open_slice1 - two_port" "Not selected,Selected"
newline
bitfld.long 0x04 13. " [13] ,Algorithm pmos_open - two_port" "Not selected,Selected"
bitfld.long 0x04 12. " [12] ,Algorithm pmos_open - two_port" "Not selected,Selected"
bitfld.long 0x04 11. " [11] ,Algorithm dtxn2 - single_port" "Not selected,Selected"
newline
bitfld.long 0x04 10. " [10] ,Algorithm dtxn2 - two_port" "Not selected,Selected"
bitfld.long 0x04 9. " [9] ,Algorithm precharge - single_port" "Not selected,Selected"
bitfld.long 0x04 8. " [8] ,Algorithm precharge - two_port" "Not selected,Selected"
newline
bitfld.long 0x04 7. " [7] ,Algorithm mapcolumn - single_port" "Not selected,Selected"
bitfld.long 0x04 6. " [6] ,Algorithm mapcolumn - two_port" "Not selected,Selected"
bitfld.long 0x04 5. " [5] ,Algorithm down2 - single_port" "Not selected,Selected"
newline
bitfld.long 0x04 4. " [4] ,Algorithm down2 - two_port" "Not selected,Selected"
newline
else
bitfld.long 0x04 24. " ALGO_[24] ,Algorithm pmos_open_slice2 - two_port" "Not selected,Selected"
bitfld.long 0x04 23. " [23] ,Algorithm pmos_open__slice1 - two_port" "Not selected,Selected"
bitfld.long 0x04 22. " [22] ,Algorithm pmos_open_slice1 - single_port" "Not selected,Selected"
newline
bitfld.long 0x04 21. " [21] ,Algorithm dtxn2 - two_port" "Not selected,Selected"
bitfld.long 0x04 20. " [20] ,Algorithm dtxn2 - single_port" "Not selected,Selected"
bitfld.long 0x04 19. " [19] ,Algorithm flip10 - two_port" "Not selected,Selected"
newline
bitfld.long 0x04 18. " [18] ,Algorithm flip10 - single_port" "Not selected,Selected"
bitfld.long 0x04 17. " [17] ,Algorithm precharge - two_port" "Not selected,Selected"
bitfld.long 0x04 16. " [16] ,Algorithm precharge - single_port" "Not selected,Selected"
newline
bitfld.long 0x04 15. " [15] ,Algorithm mapcolumn - two_port" "Not selected,Selected"
bitfld.long 0x04 14. " [14] ,Algorithm mapcolumn - single_port" "Not selected,Selected"
bitfld.long 0x04 13. " [13] ,Algorithm march_disturb_dec - two_port" "Not selected,Selected"
newline
bitfld.long 0x04 12. " [12] ,Algorithm march_disturb_dec - single_port" "Not selected,Selected"
bitfld.long 0x04 11. " [11] ,Algorithm march_disturb_inc - two_port" "Not selected,Selected"
bitfld.long 0x04 10. " [10] ,Algorithm march_disturb_inc - single_port" "Not selected,Selected"
newline
bitfld.long 0x04 9. " [9] ,Algorithm march_distur_dec - two_port" "Not selected,Selected"
bitfld.long 0x04 8. " [8] ,Algorithm march_disturb_dec - single_port" "Not selected,Selected"
bitfld.long 0x04 7. " [7] ,Algorithm march_disturb_inc - two_port" "Not selected,Selected"
newline
bitfld.long 0x04 6. " [6] ,Algorithm march_disturb_inc - single_port" "Not selected,Selected"
bitfld.long 0x04 5. " [5] ,Algorithm down2 - two_port" "Not selected,Selected"
bitfld.long 0x04 4. " [4] ,Algorithm down2 - single_port" "Not selected,Selected"
newline
endif
bitfld.long 0x04 3. " [3] ,Algorithm march13n - single_port" "Not selected,Selected"
bitfld.long 0x04 2. " [2] ,Algorithm march13n - two_port" "Not selected,Selected"
bitfld.long 0x04 1. " [1] ,Algorithm triple_read_fast_read - ROM" "Not selected,Selected"
newline
bitfld.long 0x04 0. " [0] ,Algorithm triple_read_slow_read - ROM" "Not selected,Selected"
newline
sif (cpuis("TMS570LS09*")||cpuis("TMS570LS07*")||cpuis("TMS570LS0232"))
if (((per.l.be(ad:0xFFFFE400+0x188))&0x01)==0x00)
group.long 0x1C8++0x03
line.long 0x00 "RINFOL,RAM Info Mask Lower Register"
sif cpuis("TMS570LS09*")||cpuis("TMS570LS07*")
bitfld.long 0x00 20. " ESRAM5 ,Ram group 21 select" "Not selected,Selected"
bitfld.long 0x00 19. " HET_TU2 ,Ram group 20 select" "Not selected,Selected"
newline
bitfld.long 0x00 18. " N2HET2 ,Ram group 19 select" "Not selected,Selected"
bitfld.long 0x00 17. " MIBADC2 ,Ram group 18 select" "Not selected,Selected"
newline
bitfld.long 0x00 13. " HET_TU1 ,Ram group 14 select" "Not selected,Selected"
bitfld.long 0x00 12. " N2HET1 ,Ram group 13 select" "Not selected,Selected"
newline
bitfld.long 0x00 11. " DMA ,Ram group 12 select" "Not selected,Selected"
bitfld.long 0x00 10. " MIBADC1 ,Ram group 11 select" "Not selected,Selected"
newline
else
bitfld.long 0x00 13. " HET_TU ,Ram group 14 select" "Not selected,Selected"
bitfld.long 0x00 12. " N2HET ,Ram group 13 select" "Not selected,Selected"
newline
bitfld.long 0x00 10. " MIBADC ,Ram group 11 select" "Not selected,Selected"
newline
endif
bitfld.long 0x00 9. " VIM ,Ram group 10 select" "Not selected,Selected"
newline
sif cpuis("TMS570LS09*")||cpuis("TMS570LS07*")
bitfld.long 0x00 8. " MIBSPI5 ,Ram group 9 select" "Not selected,Selected"
bitfld.long 0x00 7. " MIBSPI3 ,Ram group 8 select" "Not selected,Selected"
newline
endif
bitfld.long 0x00 6. " MIBSPI1 ,Ram group 7 select" "Not selected,Selected"
bitfld.long 0x00 5. " ESRAM1 ,Ram group 6 select" "Not selected,Selected"
newline
sif cpuis("TMS570LS09*")||cpuis("TMS570LS07*")
bitfld.long 0x00 4. " DCAN3 ,Ram group 5 select" "Not selected,Selected"
newline
endif
bitfld.long 0x00 3. " DCAN2 ,Ram group 4 select" "Not selected,Selected"
bitfld.long 0x00 2. " DCAN1 ,Ram group 3 select" "Not selected,Selected"
newline
bitfld.long 0x00 1. " STC_ROM ,Ram group 2 select" "Not selected,Selected"
bitfld.long 0x00 0. " PBIST_ROM ,Ram group 1 select" "Not selected,Selected"
else
hgroup.long 0x1C8++0x03
hide.long 0x00 "RINFOL,RAM Info Mask Lower Register"
endif
else
group.long 0x1C8++0x03
line.long 0x00 "RINFOL,RAM Info Mask Lower Register"
bitfld.long 0x00 31. " R5_DCACHE ,RAM group select" "Not selected,Selected"
bitfld.long 0x00 30. " R5_ICACHE ,RAM group select" "Not selected,Selected"
newline
bitfld.long 0x00 29. " L2RAMW ,RAM group select" "Not selected,Selected"
bitfld.long 0x00 28. " L2RAMW ,RAM group select" "Not selected,Selected"
newline
bitfld.long 0x00 27. " CPGMAC_STAT_FIFO ,RAM group select" "Not selected,Selected"
bitfld.long 0x00 26. " CPGMAC_STATE_RXA_DDR ,RAM group select" "Not selected,Selected"
newline
bitfld.long 0x00 25. " FRAY_INBUF_OUTBUF ,RAM group select" "Not selected,Selected"
bitfld.long 0x00 24. " FTU ,RAM group select" "Not selected,Selected"
newline
bitfld.long 0x00 23. " N2HET2 ,RAM group select" "Not selected,Selected"
bitfld.long 0x00 22. " MIBSPI5 ,RAM group select" "Not selected,Selected"
newline
bitfld.long 0x00 21. " MIBSPI4 ,RAM group select" "Not selected,Selected"
bitfld.long 0x00 20. " HTU2 ,RAM group select" "Not selected,Selected"
newline
bitfld.long 0x00 19. " DCAN4 ,RAM group select" "Not selected,Selected"
bitfld.long 0x00 18. " DCAN3 ,RAM group select" "Not selected,Selected"
newline
bitfld.long 0x00 17. " AWM2 ,RAM group select" "Not selected,Selected"
bitfld.long 0x00 16. " ATB ,RAM group select" "Not selected,Selected"
newline
bitfld.long 0x00 15. " RTP ,RAM group select" "Not selected,Selected"
bitfld.long 0x00 13. " VIM ,RAM group select" "Not selected,Selected"
newline
bitfld.long 0x00 12. " N2HET1 ,RAM group select" "Not selected,Selected"
bitfld.long 0x00 11. " MIBSPI3 ,RAM group select" "Not selected,Selected"
newline
bitfld.long 0x00 10. " MIBSPI2 ,RAM group select" "Not selected,Selected"
bitfld.long 0x00 9. " MIBSPI1 ,RAM group select" "Not selected,Selected"
newline
bitfld.long 0x00 8. " HTU1 ,RAM group select" "Not selected,Selected"
bitfld.long 0x00 7. " DMA ,RAM group select" "Not selected,Selected"
newline
bitfld.long 0x00 6. " DCAN2 ,RAM group select" "Not selected,Selected"
bitfld.long 0x00 5. " DCAN1 ,RAM group select" "Not selected,Selected"
newline
bitfld.long 0x00 4. " AWM1 ,RAM group select" "Not selected,Selected"
bitfld.long 0x00 3. " STC2_ROM_N2HET ,RAM group select" "Not selected,Selected"
newline
bitfld.long 0x00 2. " STC1_2_ROM_R5 ,RAM group select" "Not selected,Selected"
bitfld.long 0x00 1. " STC1_1_ROM_R5 ,RAM group select" "Not selected,Selected"
newline
bitfld.long 0x00 0. " PBIST_ROM ,RAM group select" "Not selected,Selected"
endif
sif (!cpuis("TMS570LS09*")&&!cpuis("TMS570LS07*")&&!cpuis("TMS570LS0232"))
newline
group.long 0x1CC++0x03
line.long 0x00 "RINFOU,RAM Info Mask Upper Register"
bitfld.long 0x00 4. " R5_DCACHE_DIRTY ,RAM group select" "Not selected,Selected"
bitfld.long 0x00 3. " CPGMAC_CPPI ,RAM group select" "Not selected,Selected"
newline
bitfld.long 0x00 2. " FRAY_TRBUF_MSGRA_M ,RAM group select" "Not selected,Selected"
endif
sif (cpuis("TMS570LS09*")||cpuis("TMS570LS07*")||cpuis("TMS570LS0232"))
endian.le
endif
width 0x0B
tree.end
tree "STC (Self-Test Controller)"
tree "STC 1"
base ad:0xFFFFE600
width 16.
group.long 0x00++0x0B
line.long 0x00 "GCR0,STC Global Control Register0"
hexmask.long.word 0x00 16.--31. 1. " INTCOUNT ,Number of intervals of selftest run"
bitfld.long 0x00 8.--10. " CAP_IDLE_CYCLE ,Idle cycle before and after the capture clock" "Disabled,Enabled,?..."
bitfld.long 0x00 0. " RS_CNT ,Restart or continue" "Continue,Restart"
line.long 0x04 "GCR1,STC Global Control Register1"
bitfld.long 0x04 8.--11. " SEG0_CORE_SEL ,Selects cores in segment 0 for self-test" "Both,Both,Both,Both,Both,Core1,Both,Both,Both,Both,Core2,Both,Both,Both,Both,Both"
bitfld.long 0x04 0.--3. " STC_ENA ,Self test run enable key" "Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Enabled,Disabled,Disabled,Disabled,Disabled,Disabled"
line.long 0x08 "TPR,Self-Test Run Timeout Counter Preload Register"
rgroup.long 0x0C++0x0F
line.long 0x00 "CADDR1,STC Current ROM Address Register - CORE1"
line.long 0x04 "CICR,Current Interval Count Register"
hexmask.long.word 0x04 16.--31. 1. " CORE2_ICOUNT ,Interval number for core2"
hexmask.long.word 0x04 0.--15. 1. " CORE1_ICOUNT ,Interval number for core1"
line.long 0x08 "GSTAT,Self-Test Global Status Register"
bitfld.long 0x08 8.--11. " ST_ACTIVE ,Self-Test active" "Inactive,Inactive,Inactive,Inactive,Inactive,Inactive,Inactive,Inactive,Inactive,Inactive,Active,Inactive,Inactive,Inactive,Inactive,Inactive"
bitfld.long 0x08 1. " TEST_FAIL ,Test fail" "Not failed,Failed"
bitfld.long 0x08 0. " TEST_DONE ,Test done" "Not completed,Completed"
line.long 0x0C "FSTAT,Self-Test Fail Status Register"
bitfld.long 0x0C 3.--4. " FSEG_ID ,Failed segment number" "Segment 0,Segment1,?..."
bitfld.long 0x0C 2. " TO_ERR ,Timeout error" "Not occurred,Occurred"
bitfld.long 0x0C 1. " CORE2_FAIL ,Core2 MISR mismatch for segment 0" "No mismatch,Mismatch"
bitfld.long 0x0C 0. " CORE1_FAIL ,Core1 MISR mismatch for segment 0" "No mismatch,Mismatch"
rgroup.long 0x1C++0x0F
line.long 0x00 "CORE1_CURMISR3,CORE1 Current MISR Register"
line.long 0x04 "CORE1_CURMISR2,CORE1 Current MISR Register"
line.long 0x08 "CORE1_CURMISR1,CORE1 Current MISR Register"
line.long 0x0C "CORE1_CURMISR0,CORE1 Current MISR Register"
rgroup.long 0x2C++0x0F
line.long 0x00 "CORE2_CURMISR3,CORE2 Current MISR Register"
line.long 0x04 "CORE2_CURMISR2,CORE2 Current MISR Register"
line.long 0x08 "CORE2_CURMISR1,CORE2 Current MISR Register"
line.long 0x0C "CORE2_CURMISR0,CORE2 Current MISR Register"
group.long 0x3C++0x03
line.long 0x00 "SCSCR,Signature Compare Self-Check Register"
bitfld.long 0x00 4. " FAULT_INS ,Insert stuck-at fault inside CPU" "Disabled,Enabled"
bitfld.long 0x00 0.--3. " SELF_CHECK_KEY ,Signature compare logic self-check enable key" "Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Enabled,Disabled,Disabled,Disabled,Disabled,Disabled"
rgroup.long 0x40++0x03
line.long 0x00 "CADDR2,STC Current ROM Address Register - CORE2"
group.long 0x44++0x03
line.long 0x00 "CLKDIV,STC Clock Prescaler"
bitfld.long 0x00 24.--26. " CLKDIV0 ,STCCLK divider for segment 0" "/1,/2,/3,/4,/5,/6,/7,/8"
bitfld.long 0x00 16.--18. " CLKDIV1 ,STCCLK divider for segment 1" "/1,/2,/3,/4,/5,/6,/7,/8"
group.long 0x48++0x03
line.long 0x00 "SEGPLR,Segment Interval Preload Register"
bitfld.long 0x00 0.--1. " SEGID_PLOAD ,First interval run segment number" "Segment 0,Segment 1,?..."
width 0x0B
tree.end
tree "STC 2"
base ad:0xFFFF0800
width 16.
group.long 0x00++0x0B
line.long 0x00 "GCR0,STC Global Control Register0"
hexmask.long.word 0x00 16.--31. 1. " INTCOUNT ,Number of intervals of selftest run"
bitfld.long 0x00 8.--10. " CAP_IDLE_CYCLE ,Idle cycle before and after the capture clock" "Disabled,Enabled,?..."
bitfld.long 0x00 0. " RS_CNT ,Restart or continue" "Continue,Restart"
line.long 0x04 "GCR1,STC Global Control Register1"
bitfld.long 0x04 8.--11. " SEG0_CORE_SEL ,Selects cores in segment 0 for self-test" "Both,Both,Both,Both,Both,Core1,Both,Both,Both,Both,Core2,Both,Both,Both,Both,Both"
bitfld.long 0x04 0.--3. " STC_ENA ,Self test run enable key" "Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Enabled,Disabled,Disabled,Disabled,Disabled,Disabled"
line.long 0x08 "TPR,Self-Test Run Timeout Counter Preload Register"
rgroup.long 0x0C++0x0F
line.long 0x00 "CADDR1,STC Current ROM Address Register - CORE1"
line.long 0x04 "CICR,Current Interval Count Register"
hexmask.long.word 0x04 16.--31. 1. " CORE2_ICOUNT ,Interval number for core2"
hexmask.long.word 0x04 0.--15. 1. " CORE1_ICOUNT ,Interval number for core1"
line.long 0x08 "GSTAT,Self-Test Global Status Register"
bitfld.long 0x08 8.--11. " ST_ACTIVE ,Self-Test active" "Inactive,Inactive,Inactive,Inactive,Inactive,Inactive,Inactive,Inactive,Inactive,Inactive,Active,Inactive,Inactive,Inactive,Inactive,Inactive"
bitfld.long 0x08 1. " TEST_FAIL ,Test fail" "Not failed,Failed"
bitfld.long 0x08 0. " TEST_DONE ,Test done" "Not completed,Completed"
line.long 0x0C "FSTAT,Self-Test Fail Status Register"
bitfld.long 0x0C 3.--4. " FSEG_ID ,Failed segment number" "Segment 0,Segment1,?..."
bitfld.long 0x0C 2. " TO_ERR ,Timeout error" "Not occurred,Occurred"
bitfld.long 0x0C 1. " CORE2_FAIL ,Core2 MISR mismatch for segment 0" "No mismatch,Mismatch"
bitfld.long 0x0C 0. " CORE1_FAIL ,Core1 MISR mismatch for segment 0" "No mismatch,Mismatch"
rgroup.long 0x1C++0x0F
line.long 0x00 "CORE1_CURMISR3,CORE1 Current MISR Register"
line.long 0x04 "CORE1_CURMISR2,CORE1 Current MISR Register"
line.long 0x08 "CORE1_CURMISR1,CORE1 Current MISR Register"
line.long 0x0C "CORE1_CURMISR0,CORE1 Current MISR Register"
rgroup.long 0x2C++0x0F
line.long 0x00 "CORE2_CURMISR3,CORE2 Current MISR Register"
line.long 0x04 "CORE2_CURMISR2,CORE2 Current MISR Register"
line.long 0x08 "CORE2_CURMISR1,CORE2 Current MISR Register"
line.long 0x0C "CORE2_CURMISR0,CORE2 Current MISR Register"
group.long 0x3C++0x03
line.long 0x00 "SCSCR,Signature Compare Self-Check Register"
bitfld.long 0x00 4. " FAULT_INS ,Insert stuck-at fault inside CPU" "Disabled,Enabled"
bitfld.long 0x00 0.--3. " SELF_CHECK_KEY ,Signature compare logic self-check enable key" "Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Enabled,Disabled,Disabled,Disabled,Disabled,Disabled"
rgroup.long 0x40++0x03
line.long 0x00 "CADDR2,STC Current ROM Address Register - CORE2"
group.long 0x44++0x03
line.long 0x00 "CLKDIV,STC Clock Prescaler"
bitfld.long 0x00 24.--26. " CLKDIV0 ,STCCLK divider for segment 0" "/1,/2,/3,/4,/5,/6,/7,/8"
bitfld.long 0x00 16.--18. " CLKDIV1 ,STCCLK divider for segment 1" "/1,/2,/3,/4,/5,/6,/7,/8"
group.long 0x48++0x03
line.long 0x00 "SEGPLR,Segment Interval Preload Register"
bitfld.long 0x00 0.--1. " SEGID_PLOAD ,First interval run segment number" "Segment 0,Segment 1,?..."
width 0x0B
tree.end
tree.end
tree.open "NMPU (System Memory Protection Unit)"
tree "CPGMAC"
base ad:0xFCFF1800
width 13.
rgroup.long 0x00++0x03
line.long 0x00 "MPUREV,MPU Revision ID Register"
bitfld.long 0x00 30.--31. " SCHEME ,Identification scheme" "0,1,2,3"
hexmask.long.word 0x00 16.--27. 1. " FUNC ,Module family"
hexmask.long.byte 0x00 11.--15. 1. " RTL ,RTL version number"
bitfld.long 0x00 8.--10. " MAJOR ,Major revision number" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--7. " CUSTOM ,Device-specific implementation" "0,1,2,3"
hexmask.long.byte 0x00 0.--5. 1. " MINOR ,Minor revision number"
group.long 0x04++0x03
line.long 0x00 "MPULOCK,MPU Lock Register"
bitfld.long 0x00 0.--3. " LOCK ,MPU register lock key" ",,,,,Locked,,,,,Not locked,?..."
if (((d.l(ad:0xFCFF1800+0x08))&0x100F0)==0xA0)
group.long 0x08++0x03
line.long 0x00 "MPUDIAGCTRL,MPU Diagnostics Control Register"
bitfld.long 0x00 18. " U_P ,Internal diagnostic mode user/privilege transaction" "User mode,Privilege mode"
bitfld.long 0x00 17. " R_W ,Internal diagnostic mode read/write transaction" "Read,Write"
bitfld.long 0x00 16. " INT_EXT ,Internal/external diagnostic mode" "Internal,External"
bitfld.long 0x00 4.--7. " DIAGKEY ,Diagnostic mode key" ",,,,,Disabled,,,,,Enabled,?..."
elif (((d.l(ad:0xFCFF1800+0x08))&0x100F0)==0x100A0)
group.long 0x08++0x03
line.long 0x00 "MPUDIAGCTRL,MPU Diagnostics Control Register"
bitfld.long 0x00 16. " INT_EXT ,Internal/external diagnostic mode" "Internal,External"
bitfld.long 0x00 4.--7. " DIAGKEY ,Diagnostic mode key" ",,,,,Disabled,,,,,Enabled,?..."
else
group.long 0x08++0x03
line.long 0x00 "MPUDIAGCTRL,MPU Diagnostics Control Register"
bitfld.long 0x00 18. " U_P ,Internal diagnostic mode user/privilege transaction" "User mode,Privilege mode"
bitfld.long 0x00 17. " R_W ,Internal diagnostic mode read/write transaction" "Read,Write"
bitfld.long 0x00 4.--7. " DIAGKEY ,Diagnostic mode key" ",,,,,Disabled,,,,,Enabled,?..."
endif
group.long 0x0C++0x03
line.long 0x00 "MPUDIAGADDR,MPU Diagnostic Address Register"
if ((d.l(ad:0xFCFF1800+0x10)&0x6000000)==0x6000000||(d.l(ad:0xFCFF1800+0x10)&0x6000000)==0x2000000)
group.long 0x10++0x03
line.long 0x00 "MPUERRSTAT,MPU Error Status Register"
rbitfld.long 0x00 28. " RERR ,Read error" "Not occurred,Occurred"
rbitfld.long 0x00 27. " WERR ,Write error" "Not occurred,Occurred"
rbitfld.long 0x00 26. " BGERR ,Background error" "Not occurred,Occurred"
rbitfld.long 0x00 25. " APERR ,Access permission error" "Not occurred,Occurred"
textline " "
rbitfld.long 0x00 16.--18. " REGION ,Access permission violation in region" "Region 0,Region 1,Region 2,Region 3,Region 4,Region 5,Region 6,Region 7"
hexmask.long.byte 0x00 8.--13. 0x01 " MASTERID ,Master ID for MPU compare fail"
bitfld.long 0x00 0. " ERRFLAG ,MPU compare error flag [R/WP]" "Not detected/Reserved,Detected/Clear"
elif (d.l(ad:0xFCFF1800+0x10)&0x6000000)==0x4000000
group.long 0x10++0x03
line.long 0x00 "MPUERRSTAT,MPU Error Status Register"
rbitfld.long 0x00 28. " RERR ,Read error" "Not occurred,Occurred"
rbitfld.long 0x00 27. " WERR ,Write error" "Not occurred,Occurred"
rbitfld.long 0x00 26. " BGERR ,Background error" "Not occurred,Occurred"
rbitfld.long 0x00 25. " APERR ,Access permission error" "Not occurred,Occurred"
textline " "
hexmask.long.byte 0x00 8.--13. 0x01 " MASTERID ,Master ID for MPU compare fail"
bitfld.long 0x00 0. " ERRFLAG ,MPU compare error flag [R/WP]" "Not detected/Reserved,Detected/Clear"
else
group.long 0x10++0x03
line.long 0x00 "MPUERRSTAT,MPU Error Status Register"
rbitfld.long 0x00 26. " BGERR ,Background error" "Not occurred,Occurred"
rbitfld.long 0x00 25. " APERR ,Access permission error" "Not occurred,Occurred"
textline " "
bitfld.long 0x00 0. " ERRFLAG ,MPU compare error flag [R/WP]" "Not detected/Reserved,Detected/Clear"
endif
rgroup.long 0x14++0x03
line.long 0x00 "MPUERRADDR,MPU Error Address Register"
group.long 0x20++0x03
line.long 0x00 "MPUCTRL1,MPU Control Register 1"
bitfld.long 0x00 0.--3. " MPUENA ,MPU enable key" ",,,,,Disabled,,,,,Enabled,?..."
group.long 0x24++0x03
line.long 0x00 "MPUCTRL2,MPU Control Register 2"
bitfld.long 0x00 0.--3. " ERRENA ,Error pulse to ESM enable" ",,,,,Disabled,,,,,Enabled,?..."
rgroup.long 0x2C++0x03
line.long 0x00 "MPUTYPE,MPU Type Register"
hexmask.long.byte 0x00 8.--15. 0x01 " NUMREG ,Number of MPU regions"
group.long 0x30++0x03
line.long 0x00 "MPUREGBASE,MPU Region Base Address Register"
hexmask.long 0x00 5.--31. 0x20 " BASE_ADDRESS ,Base address"
group.long 0x34++0x03
line.long 0x00 "MPUREGSENA,MPU Region Size And Enable Register"
bitfld.long 0x00 1.--5. " REG_SIZE ,MPU region size" ",,,,32B,64B,128B,256B,512B,1KB,2KB,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB"
bitfld.long 0x00 0. " REGENA ,MPU region enable" "Disabled,Enabled"
group.long 0x38++0x03
line.long 0x00 "MPUREGACR,MPU Region Access Control Register"
bitfld.long 0x00 8.--10. " AP ,MPU region access permission" "No access,P-RW U-No access,P-RW U-R,Read/write,No access,P-R U-No access,Read only,No access"
group.long 0x3C++0x03
line.long 0x00 "MPUREGNUM,MPU Region Number Register"
bitfld.long 0x00 0.--3. " REGION ,MPU region number" "Region 0,Region 1,Region 2,Region 3,Region 4,Region 5,Region 6,Region 7,?..."
width 0x0B
tree.end
tree "PS_SCR_S"
base ad:0xFFFF1800
width 13.
rgroup.long 0x00++0x03
line.long 0x00 "MPUREV,MPU Revision ID Register"
bitfld.long 0x00 30.--31. " SCHEME ,Identification scheme" "0,1,2,3"
hexmask.long.word 0x00 16.--27. 1. " FUNC ,Module family"
hexmask.long.byte 0x00 11.--15. 1. " RTL ,RTL version number"
bitfld.long 0x00 8.--10. " MAJOR ,Major revision number" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--7. " CUSTOM ,Device-specific implementation" "0,1,2,3"
hexmask.long.byte 0x00 0.--5. 1. " MINOR ,Minor revision number"
group.long 0x04++0x03
line.long 0x00 "MPULOCK,MPU Lock Register"
bitfld.long 0x00 0.--3. " LOCK ,MPU register lock key" ",,,,,Locked,,,,,Not locked,?..."
if (((d.l(ad:0xFFFF1800+0x08))&0x100F0)==0xA0)
group.long 0x08++0x03
line.long 0x00 "MPUDIAGCTRL,MPU Diagnostics Control Register"
bitfld.long 0x00 18. " U_P ,Internal diagnostic mode user/privilege transaction" "User mode,Privilege mode"
bitfld.long 0x00 17. " R_W ,Internal diagnostic mode read/write transaction" "Read,Write"
bitfld.long 0x00 16. " INT_EXT ,Internal/external diagnostic mode" "Internal,External"
bitfld.long 0x00 4.--7. " DIAGKEY ,Diagnostic mode key" ",,,,,Disabled,,,,,Enabled,?..."
elif (((d.l(ad:0xFFFF1800+0x08))&0x100F0)==0x100A0)
group.long 0x08++0x03
line.long 0x00 "MPUDIAGCTRL,MPU Diagnostics Control Register"
bitfld.long 0x00 16. " INT_EXT ,Internal/external diagnostic mode" "Internal,External"
bitfld.long 0x00 4.--7. " DIAGKEY ,Diagnostic mode key" ",,,,,Disabled,,,,,Enabled,?..."
else
group.long 0x08++0x03
line.long 0x00 "MPUDIAGCTRL,MPU Diagnostics Control Register"
bitfld.long 0x00 18. " U_P ,Internal diagnostic mode user/privilege transaction" "User mode,Privilege mode"
bitfld.long 0x00 17. " R_W ,Internal diagnostic mode read/write transaction" "Read,Write"
bitfld.long 0x00 4.--7. " DIAGKEY ,Diagnostic mode key" ",,,,,Disabled,,,,,Enabled,?..."
endif
group.long 0x0C++0x03
line.long 0x00 "MPUDIAGADDR,MPU Diagnostic Address Register"
if ((d.l(ad:0xFFFF1800+0x10)&0x6000000)==0x6000000||(d.l(ad:0xFFFF1800+0x10)&0x6000000)==0x2000000)
group.long 0x10++0x03
line.long 0x00 "MPUERRSTAT,MPU Error Status Register"
rbitfld.long 0x00 28. " RERR ,Read error" "Not occurred,Occurred"
rbitfld.long 0x00 27. " WERR ,Write error" "Not occurred,Occurred"
rbitfld.long 0x00 26. " BGERR ,Background error" "Not occurred,Occurred"
rbitfld.long 0x00 25. " APERR ,Access permission error" "Not occurred,Occurred"
textline " "
rbitfld.long 0x00 16.--18. " REGION ,Access permission violation in region" "Region 0,Region 1,Region 2,Region 3,Region 4,Region 5,Region 6,Region 7"
hexmask.long.byte 0x00 8.--13. 0x01 " MASTERID ,Master ID for MPU compare fail"
bitfld.long 0x00 0. " ERRFLAG ,MPU compare error flag [R/WP]" "Not detected/Reserved,Detected/Clear"
elif (d.l(ad:0xFFFF1800+0x10)&0x6000000)==0x4000000
group.long 0x10++0x03
line.long 0x00 "MPUERRSTAT,MPU Error Status Register"
rbitfld.long 0x00 28. " RERR ,Read error" "Not occurred,Occurred"
rbitfld.long 0x00 27. " WERR ,Write error" "Not occurred,Occurred"
rbitfld.long 0x00 26. " BGERR ,Background error" "Not occurred,Occurred"
rbitfld.long 0x00 25. " APERR ,Access permission error" "Not occurred,Occurred"
textline " "
hexmask.long.byte 0x00 8.--13. 0x01 " MASTERID ,Master ID for MPU compare fail"
bitfld.long 0x00 0. " ERRFLAG ,MPU compare error flag [R/WP]" "Not detected/Reserved,Detected/Clear"
else
group.long 0x10++0x03
line.long 0x00 "MPUERRSTAT,MPU Error Status Register"
rbitfld.long 0x00 26. " BGERR ,Background error" "Not occurred,Occurred"
rbitfld.long 0x00 25. " APERR ,Access permission error" "Not occurred,Occurred"
textline " "
bitfld.long 0x00 0. " ERRFLAG ,MPU compare error flag [R/WP]" "Not detected/Reserved,Detected/Clear"
endif
rgroup.long 0x14++0x03
line.long 0x00 "MPUERRADDR,MPU Error Address Register"
group.long 0x20++0x03
line.long 0x00 "MPUCTRL1,MPU Control Register 1"
bitfld.long 0x00 0.--3. " MPUENA ,MPU enable key" ",,,,,Disabled,,,,,Enabled,?..."
group.long 0x24++0x03
line.long 0x00 "MPUCTRL2,MPU Control Register 2"
bitfld.long 0x00 0.--3. " ERRENA ,Error pulse to ESM enable" ",,,,,Disabled,,,,,Enabled,?..."
rgroup.long 0x2C++0x03
line.long 0x00 "MPUTYPE,MPU Type Register"
hexmask.long.byte 0x00 8.--15. 0x01 " NUMREG ,Number of MPU regions"
group.long 0x30++0x03
line.long 0x00 "MPUREGBASE,MPU Region Base Address Register"
hexmask.long 0x00 5.--31. 0x20 " BASE_ADDRESS ,Base address"
group.long 0x34++0x03
line.long 0x00 "MPUREGSENA,MPU Region Size And Enable Register"
bitfld.long 0x00 1.--5. " REG_SIZE ,MPU region size" ",,,,32B,64B,128B,256B,512B,1KB,2KB,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB"
bitfld.long 0x00 0. " REGENA ,MPU region enable" "Disabled,Enabled"
group.long 0x38++0x03
line.long 0x00 "MPUREGACR,MPU Region Access Control Register"
bitfld.long 0x00 8.--10. " AP ,MPU region access permission" "No access,P-RW U-No access,P-RW U-R,Read/write,No access,P-R U-No access,Read only,No access"
group.long 0x3C++0x03
line.long 0x00 "MPUREGNUM,MPU Region Number Register"
bitfld.long 0x00 0.--3. " REGION ,MPU region number" "Region 0,Region 1,Region 2,Region 3,Region 4,Region 5,Region 6,Region 7,?..."
width 0x0B
tree.end
tree "DMA Port A"
base ad:0xFFFF1A00
width 13.
rgroup.long 0x00++0x03
line.long 0x00 "MPUREV,MPU Revision ID Register"
bitfld.long 0x00 30.--31. " SCHEME ,Identification scheme" "0,1,2,3"
hexmask.long.word 0x00 16.--27. 1. " FUNC ,Module family"
hexmask.long.byte 0x00 11.--15. 1. " RTL ,RTL version number"
bitfld.long 0x00 8.--10. " MAJOR ,Major revision number" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--7. " CUSTOM ,Device-specific implementation" "0,1,2,3"
hexmask.long.byte 0x00 0.--5. 1. " MINOR ,Minor revision number"
group.long 0x04++0x03
line.long 0x00 "MPULOCK,MPU Lock Register"
bitfld.long 0x00 0.--3. " LOCK ,MPU register lock key" ",,,,,Locked,,,,,Not locked,?..."
if (((d.l(ad:0xFFFF1A00+0x08))&0x100F0)==0xA0)
group.long 0x08++0x03
line.long 0x00 "MPUDIAGCTRL,MPU Diagnostics Control Register"
bitfld.long 0x00 18. " U_P ,Internal diagnostic mode user/privilege transaction" "User mode,Privilege mode"
bitfld.long 0x00 17. " R_W ,Internal diagnostic mode read/write transaction" "Read,Write"
bitfld.long 0x00 16. " INT_EXT ,Internal/external diagnostic mode" "Internal,External"
bitfld.long 0x00 4.--7. " DIAGKEY ,Diagnostic mode key" ",,,,,Disabled,,,,,Enabled,?..."
elif (((d.l(ad:0xFFFF1A00+0x08))&0x100F0)==0x100A0)
group.long 0x08++0x03
line.long 0x00 "MPUDIAGCTRL,MPU Diagnostics Control Register"
bitfld.long 0x00 16. " INT_EXT ,Internal/external diagnostic mode" "Internal,External"
bitfld.long 0x00 4.--7. " DIAGKEY ,Diagnostic mode key" ",,,,,Disabled,,,,,Enabled,?..."
else
group.long 0x08++0x03
line.long 0x00 "MPUDIAGCTRL,MPU Diagnostics Control Register"
bitfld.long 0x00 18. " U_P ,Internal diagnostic mode user/privilege transaction" "User mode,Privilege mode"
bitfld.long 0x00 17. " R_W ,Internal diagnostic mode read/write transaction" "Read,Write"
bitfld.long 0x00 4.--7. " DIAGKEY ,Diagnostic mode key" ",,,,,Disabled,,,,,Enabled,?..."
endif
group.long 0x0C++0x03
line.long 0x00 "MPUDIAGADDR,MPU Diagnostic Address Register"
if ((d.l(ad:0xFFFF1A00+0x10)&0x6000000)==0x6000000||(d.l(ad:0xFFFF1A00+0x10)&0x6000000)==0x2000000)
group.long 0x10++0x03
line.long 0x00 "MPUERRSTAT,MPU Error Status Register"
rbitfld.long 0x00 28. " RERR ,Read error" "Not occurred,Occurred"
rbitfld.long 0x00 27. " WERR ,Write error" "Not occurred,Occurred"
rbitfld.long 0x00 26. " BGERR ,Background error" "Not occurred,Occurred"
rbitfld.long 0x00 25. " APERR ,Access permission error" "Not occurred,Occurred"
textline " "
rbitfld.long 0x00 16.--18. " REGION ,Access permission violation in region" "Region 0,Region 1,Region 2,Region 3,Region 4,Region 5,Region 6,Region 7"
hexmask.long.byte 0x00 8.--13. 0x01 " MASTERID ,Master ID for MPU compare fail"
bitfld.long 0x00 0. " ERRFLAG ,MPU compare error flag [R/WP]" "Not detected/Reserved,Detected/Clear"
elif (d.l(ad:0xFFFF1A00+0x10)&0x6000000)==0x4000000
group.long 0x10++0x03
line.long 0x00 "MPUERRSTAT,MPU Error Status Register"
rbitfld.long 0x00 28. " RERR ,Read error" "Not occurred,Occurred"
rbitfld.long 0x00 27. " WERR ,Write error" "Not occurred,Occurred"
rbitfld.long 0x00 26. " BGERR ,Background error" "Not occurred,Occurred"
rbitfld.long 0x00 25. " APERR ,Access permission error" "Not occurred,Occurred"
textline " "
hexmask.long.byte 0x00 8.--13. 0x01 " MASTERID ,Master ID for MPU compare fail"
bitfld.long 0x00 0. " ERRFLAG ,MPU compare error flag [R/WP]" "Not detected/Reserved,Detected/Clear"
else
group.long 0x10++0x03
line.long 0x00 "MPUERRSTAT,MPU Error Status Register"
rbitfld.long 0x00 26. " BGERR ,Background error" "Not occurred,Occurred"
rbitfld.long 0x00 25. " APERR ,Access permission error" "Not occurred,Occurred"
textline " "
bitfld.long 0x00 0. " ERRFLAG ,MPU compare error flag [R/WP]" "Not detected/Reserved,Detected/Clear"
endif
rgroup.long 0x14++0x03
line.long 0x00 "MPUERRADDR,MPU Error Address Register"
group.long 0x20++0x03
line.long 0x00 "MPUCTRL1,MPU Control Register 1"
bitfld.long 0x00 0.--3. " MPUENA ,MPU enable key" ",,,,,Disabled,,,,,Enabled,?..."
group.long 0x24++0x03
line.long 0x00 "MPUCTRL2,MPU Control Register 2"
bitfld.long 0x00 0.--3. " ERRENA ,Error pulse to ESM enable" ",,,,,Disabled,,,,,Enabled,?..."
rgroup.long 0x2C++0x03
line.long 0x00 "MPUTYPE,MPU Type Register"
hexmask.long.byte 0x00 8.--15. 0x01 " NUMREG ,Number of MPU regions"
group.long 0x30++0x03
line.long 0x00 "MPUREGBASE,MPU Region Base Address Register"
hexmask.long 0x00 5.--31. 0x20 " BASE_ADDRESS ,Base address"
group.long 0x34++0x03
line.long 0x00 "MPUREGSENA,MPU Region Size And Enable Register"
bitfld.long 0x00 1.--5. " REG_SIZE ,MPU region size" ",,,,32B,64B,128B,256B,512B,1KB,2KB,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB"
bitfld.long 0x00 0. " REGENA ,MPU region enable" "Disabled,Enabled"
group.long 0x38++0x03
line.long 0x00 "MPUREGACR,MPU Region Access Control Register"
bitfld.long 0x00 8.--10. " AP ,MPU region access permission" "No access,P-RW U-No access,P-RW U-R,Read/write,No access,P-R U-No access,Read only,No access"
group.long 0x3C++0x03
line.long 0x00 "MPUREGNUM,MPU Region Number Register"
bitfld.long 0x00 0.--3. " REGION ,MPU region number" "Region 0,Region 1,Region 2,Region 3,Region 4,Region 5,Region 6,Region 7,?..."
width 0x0B
tree.end
tree.end
tree "EPC (Error Profiling Controller)"
base ad:0xFFFF0C00
width 14.
rgroup.long 0x00++0x03
line.long 0x00 "EPCREVID,EPC REVID Register"
bitfld.long 0x00 30.--31. " SCHEME ,Identification scheme" "0,1,2,3"
hexmask.long.word 0x00 16.--27. 1. " FUNC ,Module family"
hexmask.long.byte 0x00 11.--15. 1. " RTL ,RTL Version Number"
textline " "
bitfld.long 0x00 8.--10. " MAJOR ,Major revision number" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--7. " CUSTOM ,Device-specific implementation" "0,1,2,3"
hexmask.long.byte 0x00 0.--5. 1. " MINOR ,Minor revision number"
group.long 0x04++0x13
line.long 0x00 "EPCCNTRL,EPC Control Register"
bitfld.long 0x00 24. " CAM/FIFO_FULL_ENA ,CAM or FIFO full interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 8.--11. " DIA_ENA_KEY ,CAM Diagnostic Enable Key" ",,,,,Disabled,,,,,Enabled,?..."
bitfld.long 0x00 0.--3. " SERRENA ,Single (correctable) bit error event enable" ",,,,,Disabled,,,,,Enabled,?..."
line.long 0x04 "UERRSTAT,Uncorrectable Error Status Register"
bitfld.long 0x04 1. " UE1 ,Interface 1 Uncorrectable ECC Fault Status Bit" "Not occurred,Occurred"
bitfld.long 0x04 0. " UE0 ,Interface 0 Uncorrectable ECC Fault Status Bit" "Not occurred,Occurred"
line.long 0x08 "EPCERRSTAT,EPC Error Status Register"
bitfld.long 0x08 2. " CAM_FULL ,CAM full status bit" "Not full,Full"
bitfld.long 0x08 1. " BUS_ERR ,MMR interface bus error status bit" "No error,Error"
bitfld.long 0x08 0. " CAM_OVFLW ,CAM overflow status bit" "Not detected,Detected"
textline " "
line.long 0x0C "FIFOFULLSTAT,FIFO Full Status Register"
bitfld.long 0x0C 4. " FULL_[4] ,FIFO interface 4 is full" "Not full,Full"
bitfld.long 0x0C 3. " [3] ,FIFO interface 3 is full" "Not full,Full"
bitfld.long 0x0C 2. " [2] ,FIFO interface 2 is full" "Not full,Full"
bitfld.long 0x0C 1. " [1] ,FIFO interface 1 is full" "Not full,Full"
bitfld.long 0x0C 0. " [0] ,FIFO interface 0 is full" "Not full,Full"
line.long 0x10 "OVRFLWSTAT,IP Interface FIFO Overflow Status Register"
bitfld.long 0x10 4. " OVFL_[4] ,Correctable EPC-IP interface 4 FIFO overflow" "Not occurred,Occurred"
bitfld.long 0x10 3. " [3] ,Correctable EPC-IP interface 3 FIFO overflow" "Not occurred,Occurred"
bitfld.long 0x10 2. " [2] ,Correctable EPC-IP interface 2 FIFO overflow" "Not occurred,Occurred"
bitfld.long 0x10 1. " [1] ,Correctable EPC-IP interface 1 FIFO overflow" "Not occurred,Occurred"
bitfld.long 0x10 0. " [0] ,Correctable EPC-IP interface 0 FIFO overflow" "Not occurred,Occurred"
rgroup.long 0x18++0x03
line.long 0x00 "CAMAVAILSTAT,CAM Index Available Status Register"
bitfld.long 0x00 0.--5. " NUMCAMAVAIL ,Number of current available CAM index" ",1 CAM,2 CAM,3 CAM,4 CAM,5 CAM,6 CAM,7 CAM,8 CAM,9 CAM,10 CAM,11 CAM,12 CAM,13 CAM,14 CAM,15 CAM,16 CAM,17 CAM,18 CAM,19 CAM,20 CAM,21 CAM,22 CAM,23 CAM,24 CAM,25 CAM,26 CAM,27 CAM,28 CAM,29 CAM,30 CAM,31 CAM,32 CAM,?..."
hgroup.long 0x20++0x03
hide.long 0x00 "UERR_ADDR0,Uncorrectable Error Address Register 0"
in
hgroup.long 0x24++0x03
hide.long 0x00 "UERR_ADDR1,Uncorrectable Error Address Register 1"
in
tree "CAM Content Update Registers"
group.long 0xA0++0x03
line.long 0x00 "CAM_CONTENT0,CAM Content Update Register 0"
hexmask.long 0x00 3.--31. 1. " CAM_CONTENT ,CAM content register 0"
group.long 0xA4++0x03
line.long 0x00 "CAM_CONTENT1,CAM Content Update Register 1"
hexmask.long 0x00 3.--31. 1. " CAM_CONTENT ,CAM content register 1"
group.long 0xA8++0x03
line.long 0x00 "CAM_CONTENT2,CAM Content Update Register 2"
hexmask.long 0x00 3.--31. 1. " CAM_CONTENT ,CAM content register 2"
group.long 0xAC++0x03
line.long 0x00 "CAM_CONTENT3,CAM Content Update Register 3"
hexmask.long 0x00 3.--31. 1. " CAM_CONTENT ,CAM content register 3"
group.long 0xB0++0x03
line.long 0x00 "CAM_CONTENT4,CAM Content Update Register 4"
hexmask.long 0x00 3.--31. 1. " CAM_CONTENT ,CAM content register 4"
group.long 0xB4++0x03
line.long 0x00 "CAM_CONTENT5,CAM Content Update Register 5"
hexmask.long 0x00 3.--31. 1. " CAM_CONTENT ,CAM content register 5"
group.long 0xB8++0x03
line.long 0x00 "CAM_CONTENT6,CAM Content Update Register 6"
hexmask.long 0x00 3.--31. 1. " CAM_CONTENT ,CAM content register 6"
group.long 0xBC++0x03
line.long 0x00 "CAM_CONTENT7,CAM Content Update Register 7"
hexmask.long 0x00 3.--31. 1. " CAM_CONTENT ,CAM content register 7"
group.long 0xC0++0x03
line.long 0x00 "CAM_CONTENT8,CAM Content Update Register 8"
hexmask.long 0x00 3.--31. 1. " CAM_CONTENT ,CAM content register 8"
group.long 0xC4++0x03
line.long 0x00 "CAM_CONTENT9,CAM Content Update Register 9"
hexmask.long 0x00 3.--31. 1. " CAM_CONTENT ,CAM content register 9"
group.long 0xC8++0x03
line.long 0x00 "CAM_CONTENT10,CAM Content Update Register 10"
hexmask.long 0x00 3.--31. 1. " CAM_CONTENT ,CAM content register 10"
group.long 0xCC++0x03
line.long 0x00 "CAM_CONTENT11,CAM Content Update Register 11"
hexmask.long 0x00 3.--31. 1. " CAM_CONTENT ,CAM content register 11"
group.long 0xD0++0x03
line.long 0x00 "CAM_CONTENT12,CAM Content Update Register 12"
hexmask.long 0x00 3.--31. 1. " CAM_CONTENT ,CAM content register 12"
group.long 0xD4++0x03
line.long 0x00 "CAM_CONTENT13,CAM Content Update Register 13"
hexmask.long 0x00 3.--31. 1. " CAM_CONTENT ,CAM content register 13"
group.long 0xD8++0x03
line.long 0x00 "CAM_CONTENT14,CAM Content Update Register 14"
hexmask.long 0x00 3.--31. 1. " CAM_CONTENT ,CAM content register 14"
group.long 0xDC++0x03
line.long 0x00 "CAM_CONTENT15,CAM Content Update Register 15"
hexmask.long 0x00 3.--31. 1. " CAM_CONTENT ,CAM content register 15"
group.long 0xE0++0x03
line.long 0x00 "CAM_CONTENT16,CAM Content Update Register 16"
hexmask.long 0x00 3.--31. 1. " CAM_CONTENT ,CAM content register 16"
group.long 0xE4++0x03
line.long 0x00 "CAM_CONTENT17,CAM Content Update Register 17"
hexmask.long 0x00 3.--31. 1. " CAM_CONTENT ,CAM content register 17"
group.long 0xE8++0x03
line.long 0x00 "CAM_CONTENT18,CAM Content Update Register 18"
hexmask.long 0x00 3.--31. 1. " CAM_CONTENT ,CAM content register 18"
group.long 0xEC++0x03
line.long 0x00 "CAM_CONTENT19,CAM Content Update Register 19"
hexmask.long 0x00 3.--31. 1. " CAM_CONTENT ,CAM content register 19"
group.long 0xF0++0x03
line.long 0x00 "CAM_CONTENT20,CAM Content Update Register 20"
hexmask.long 0x00 3.--31. 1. " CAM_CONTENT ,CAM content register 20"
group.long 0xF4++0x03
line.long 0x00 "CAM_CONTENT21,CAM Content Update Register 21"
hexmask.long 0x00 3.--31. 1. " CAM_CONTENT ,CAM content register 21"
group.long 0xF8++0x03
line.long 0x00 "CAM_CONTENT22,CAM Content Update Register 22"
hexmask.long 0x00 3.--31. 1. " CAM_CONTENT ,CAM content register 22"
group.long 0xFC++0x03
line.long 0x00 "CAM_CONTENT23,CAM Content Update Register 23"
hexmask.long 0x00 3.--31. 1. " CAM_CONTENT ,CAM content register 23"
group.long 0x100++0x03
line.long 0x00 "CAM_CONTENT24,CAM Content Update Register 24"
hexmask.long 0x00 3.--31. 1. " CAM_CONTENT ,CAM content register 24"
group.long 0x104++0x03
line.long 0x00 "CAM_CONTENT25,CAM Content Update Register 25"
hexmask.long 0x00 3.--31. 1. " CAM_CONTENT ,CAM content register 25"
group.long 0x108++0x03
line.long 0x00 "CAM_CONTENT26,CAM Content Update Register 26"
hexmask.long 0x00 3.--31. 1. " CAM_CONTENT ,CAM content register 26"
group.long 0x10C++0x03
line.long 0x00 "CAM_CONTENT27,CAM Content Update Register 27"
hexmask.long 0x00 3.--31. 1. " CAM_CONTENT ,CAM content register 27"
group.long 0x110++0x03
line.long 0x00 "CAM_CONTENT28,CAM Content Update Register 28"
hexmask.long 0x00 3.--31. 1. " CAM_CONTENT ,CAM content register 28"
group.long 0x114++0x03
line.long 0x00 "CAM_CONTENT29,CAM Content Update Register 29"
hexmask.long 0x00 3.--31. 1. " CAM_CONTENT ,CAM content register 29"
group.long 0x118++0x03
line.long 0x00 "CAM_CONTENT30,CAM Content Update Register 30"
hexmask.long 0x00 3.--31. 1. " CAM_CONTENT ,CAM content register 30"
group.long 0x11C++0x03
line.long 0x00 "CAM_CONTENT31,CAM Content Update Register 31"
hexmask.long 0x00 3.--31. 1. " CAM_CONTENT ,CAM content register 31"
tree.end
textline " "
group.long 0x200++0x03
line.long 0x00 "CAM_INDEX0,CAM Index Register 0"
bitfld.long 0x00 24.--27. " INDEX_[3] ,Entry valid tag for index 3" ",,,,,Cleared,,,,,Occupied,?..."
bitfld.long 0x00 16.--19. " [2] ,Entry valid tag for index 2" ",,,,,Cleared,,,,,Occupied,?..."
bitfld.long 0x00 8.--11. " [1] ,Entry valid tag for index 1" ",,,,,Cleared,,,,,Occupied,?..."
bitfld.long 0x00 0.--3. " [0] ,Entry valid tag for index 0" ",,,,,Cleared,,,,,Occupied,?..."
group.long 0x204++0x03
line.long 0x00 "CAM_INDEX1,CAM Index Register 1"
bitfld.long 0x00 24.--27. " INDEX_[7] ,Entry valid tag for index 7" ",,,,,Cleared,,,,,Occupied,?..."
bitfld.long 0x00 16.--19. " [6] ,Entry valid tag for index 6" ",,,,,Cleared,,,,,Occupied,?..."
bitfld.long 0x00 8.--11. " [5] ,Entry valid tag for index 5" ",,,,,Cleared,,,,,Occupied,?..."
bitfld.long 0x00 0.--3. " [4] ,Entry valid tag for index 4" ",,,,,Cleared,,,,,Occupied,?..."
group.long 0x208++0x03
line.long 0x00 "CAM_INDEX2,CAM Index Register $2"
bitfld.long 0x00 24.--27. " INDEX_[11] ,Entry valid tag for index $3" ",,,,,Cleared,,,,,Occupied,?..."
bitfld.long 0x00 16.--19. " [10] ,Entry valid tag for index $4" ",,,,,Cleared,,,,,Occupied,?..."
bitfld.long 0x00 8.--11. " [9] ,Entry valid tag for index $5" ",,,,,Cleared,,,,,Occupied,?..."
bitfld.long 0x00 0.--3. " [8] ,Entry valid tag for index $6" ",,,,,Cleared,,,,,Occupied,?..."
group.long 0x20C++0x03
line.long 0x00 "CAM_INDEX3,CAM Index Register 3"
bitfld.long 0x00 24.--27. " INDEX_[15] ,Entry valid tag for index 15" ",,,,,Cleared,,,,,Occupied,?..."
bitfld.long 0x00 16.--19. " [14] ,Entry valid tag for index 14" ",,,,,Cleared,,,,,Occupied,?..."
bitfld.long 0x00 8.--11. " [13] ,Entry valid tag for index 13" ",,,,,Cleared,,,,,Occupied,?..."
bitfld.long 0x00 0.--3. " [12] ,Entry valid tag for index 12" ",,,,,Cleared,,,,,Occupied,?..."
group.long 0x210++0x03
line.long 0x00 "CAM_INDEX4,CAM Index Register 4"
bitfld.long 0x00 24.--27. " INDEX_[19] ,Entry valid tag for index 19" ",,,,,Cleared,,,,,Occupied,?..."
bitfld.long 0x00 16.--19. " [18] ,Entry valid tag for index 18" ",,,,,Cleared,,,,,Occupied,?..."
bitfld.long 0x00 8.--11. " [17] ,Entry valid tag for index 17" ",,,,,Cleared,,,,,Occupied,?..."
bitfld.long 0x00 0.--3. " [16] ,Entry valid tag for index 16" ",,,,,Cleared,,,,,Occupied,?..."
group.long 0x214++0x03
line.long 0x00 "CAM_INDEX5,CAM Index Register 5"
bitfld.long 0x00 24.--27. " INDEX_[23] ,Entry valid tag for index 23" ",,,,,Cleared,,,,,Occupied,?..."
bitfld.long 0x00 16.--19. " [22] ,Entry valid tag for index 22" ",,,,,Cleared,,,,,Occupied,?..."
bitfld.long 0x00 8.--11. " [21] ,Entry valid tag for index 21" ",,,,,Cleared,,,,,Occupied,?..."
bitfld.long 0x00 0.--3. " [20] ,Entry valid tag for index 20" ",,,,,Cleared,,,,,Occupied,?..."
group.long 0x218++0x03
line.long 0x00 "CAM_INDEX6,CAM Index Register 6"
bitfld.long 0x00 24.--27. " INDEX_[27] ,Entry valid tag for index 27" ",,,,,Cleared,,,,,Occupied,?..."
bitfld.long 0x00 16.--19. " [26] ,Entry valid tag for index 26" ",,,,,Cleared,,,,,Occupied,?..."
bitfld.long 0x00 8.--11. " [25] ,Entry valid tag for index 25" ",,,,,Cleared,,,,,Occupied,?..."
bitfld.long 0x00 0.--3. " [24] ,Entry valid tag for index 24" ",,,,,Cleared,,,,,Occupied,?..."
group.long 0x21C++0x03
line.long 0x00 "CAM_INDEX7,CAM Index Register 7"
bitfld.long 0x00 24.--27. " INDEX_[31] ,Entry valid tag for index 31" ",,,,,Cleared,,,,,Occupied,?..."
bitfld.long 0x00 16.--19. " [30] ,Entry valid tag for index 30" ",,,,,Cleared,,,,,Occupied,?..."
bitfld.long 0x00 8.--11. " [29] ,Entry valid tag for index 29" ",,,,,Cleared,,,,,Occupied,?..."
bitfld.long 0x00 0.--3. " [28] ,Entry valid tag for index 28" ",,,,,Cleared,,,,,Occupied,?..."
width 0xB
tree.end
tree "CCM-R5F (CPU Compare Module for Cortex-R5F)"
base ad:0xFFFFF600
width 13.
group.long 0x0++0x07
line.long 0x00 "CCMSR1,CCM-R5F Status Register 1"
eventfld.long 0x00 16. " CMPE1 ,CPU output signals compare error" "Identical,Mismatch"
rbitfld.long 0x00 8. " STC1 ,CPU output compare diagnostic Self-test complete" "On-going,Complete"
rbitfld.long 0x00 1. " STET1 ,CPU output compare Self-test error type" "Match test fail,Mismatch test fail"
rbitfld.long 0x00 0. " STE1 ,CPU output compare diagnostic status" "Passed,Failed"
line.long 0x04 "CCMKEYR1,CCM-R5F Key Register 1"
bitfld.long 0x04 0.--3. " MKEY1 ,CPU output compare diagnostic mode key" "Active compare lockstep,,,,,,Self-test,,,Error forcing,,,,,,Self-test error forcing"
group.long 0x8++0x07
line.long 0x00 "CCMSR2,CCM-R5F Status Register 2"
eventfld.long 0x00 16. " CMPE2 ,CPU output signals compare error" "Identical,Mismatch"
rbitfld.long 0x00 8. " STC2 ,CPU output compare diagnostic Self-test complete" "On-going,Complete"
rbitfld.long 0x00 1. " STET2 ,CPU output compare Self-test error type" "Match test fail,Mismatch test fail"
rbitfld.long 0x00 0. " STE2 ,CPU output compare diagnostic status" "Passed,Failed"
line.long 0x04 "CCMKEYR1,CCM-R5F Key Register 1"
bitfld.long 0x04 0.--3. " MKEY1 ,CPU output compare diagnostic mode key" "Active compare lockstep,,,,,,Self-test,,,Error forcing,,,,,,Self-test error forcing"
group.long 0x10++0x07
line.long 0x00 "CCMSR3,CCM-R5F Status Register 3"
eventfld.long 0x00 16. " CMPE3 ,CPU output signals compare error" "Identical,Mismatch"
rbitfld.long 0x00 8. " STC3 ,CPU output compare diagnostic Self-test complete" "On-going,Complete"
rbitfld.long 0x00 1. " STET3 ,CPU output compare Self-test error type" "Match test fail,Mismatch test fail"
rbitfld.long 0x00 0. " STE3 ,CPU output compare diagnostic status" "Passed,Failed"
line.long 0x04 "CCMKEYR1,CCM-R5F Key Register 1"
bitfld.long 0x04 0.--3. " MKEY1 ,CPU output compare diagnostic mode key" "Active compare lockstep,,,,,,Self-test,,,Error forcing,,,,,,Self-test error forcing"
textline " "
group.long 0x18++0x03
line.long 0x00 "CCMPOLCNTRL,CCM-R5F Polarity Control Register"
bitfld.long 0x00 7. " POLARITYINVERT ,Polarity inversion" "0,1"
bitfld.long 0x00 6. ",Polarity inversion" "0,1"
bitfld.long 0x00 5. ",Polarity inversion" "0,1"
bitfld.long 0x00 4. ",Polarity inversion" "0,1"
bitfld.long 0x00 3. ",Polarity inversion" "0,1"
bitfld.long 0x00 2. ",Polarity inversion" "0,1"
bitfld.long 0x00 1. ",Polarity inversion" "0,1"
bitfld.long 0x00 0. ",Polarity inversion" "0,1"
textline " "
group.long 0x1C++0x07
line.long 0x00 "CCMSR4,CCM-R5F Status Register 4"
eventfld.long 0x00 16. " CMPE4 ,Power domain inactivity monitor signals compare error" "Identical,Mismatch"
rbitfld.long 0x00 8. " STC4 ,Power domain inactivity monitor Self-test complete" "On-going,Complete"
rbitfld.long 0x00 1. " STET4 ,Power domain inactivity monitor Self-test error type" "Match test fail,Mismatch test fail"
rbitfld.long 0x00 0. " STE4 ,Power domain inactivity monitor diagnostic status" "Passed,Failed"
line.long 0x04 "CCMKEYR4,CCM-R5F Key Register 4"
bitfld.long 0x04 0.--3. " MKEY4 ,Power domain inactivity monitor diagnostic mode key" "Active compare lockstep,,,,,,Self-test,,,Error forcing,,,,,,Self-test error forcing"
rgroup.long 0x24++0x03
line.long 0x00 "CCMPDSTAT0,Power Domain Status Register 0"
bitfld.long 0x00 4.--5. " DMM_TRNS ,DMM transaction on master" "Not detected,Detected,Detected,Detected"
bitfld.long 0x00 2.--3. " HTU2_TRNS ,HTU2 transaction on master" "Not detected,Detected,Detected,Detected"
sif cpu()!="RM57L843-ZWT"
bitfld.long 0x00 0.--1. " FTU_TRNS ,FTU transaction on master" "Not detected,Detected,Detected,Detected"
endif
width 0x0B
tree.end
tree "PLL (Phase-Locked Loop)"
base ad:0xFFFFE100
sif (cpuis("TMS570LS09*")||cpuis("TMS570LS07*")||cpuis("TMS570LS0232"))
endian.be
endif
width 15.
sif (cpuis("RM57L843-ZWT")||cpuis("TMS570LS09*")||cpuis("TMS570LS07*")||cpuis("TMS570LS0232")||cpuis("TMS570LS3137-EP"))
group.long 0x1E30++0x03
line.long 0x00 "CSDIS_SET/CLR,Clock Source Disable Set/Clear Register"
sif !cpuis("TMS570LS0232")
setclrfld.long 0x00 7. 0x04 7. 0x08 7. " CLKSR7_OFF ,Clock source 7 (External clock in 2) disable" "No,Yes"
newline
endif
sif !cpuis("TMS570LS09*")&&!cpuis("TMS570LS07*")&&!cpuis("TMS570LS0232")
setclrfld.long 0x00 6. 0x04 6. 0x08 6. " CLKSR6_OFF ,Clock source 6 (Pll2) disable" "No,Yes"
newline
endif
setclrfld.long 0x00 5. 0x04 5. 0x08 5. " CLKSR5_OFF ,Clock source 5 (LPO high frequency clock) disable" "No,Yes"
setclrfld.long 0x00 4. 0x04 4. 0x08 4. " CLKSR4_OFF ,Clock source 4 (LPO low frequency clock) disable" "No,Yes"
setclrfld.long 0x00 3. 0x04 3. 0x08 3. " CLKSR3_OFF ,Clock source 3 (External clock in) disable" "No,Yes"
newline
setclrfld.long 0x00 1. 0x04 1. 0x08 1. " CLKSR1_OFF ,Clock source 1 (PLL1) disable" "No,Yes"
setclrfld.long 0x00 0. 0x04 0. 0x08 0. " CLKSR0_OFF ,Clock source 0 (Oscillator) disable" "No,Yes"
rgroup.long 0x1E54++0x03
line.long 0x00 "CSVSTAT,Clock Source Valid Status Register"
sif !cpuis("TMS570LS0232")
bitfld.long 0x00 7. " CLKSR7V ,Clock source 7 valid" "Not valid,Valid"
newline
endif
sif !cpuis("TMS570LS09*")&&!cpuis("TMS570LS07*")&&!cpuis("TMS570LS0232")
bitfld.long 0x00 6. " CLKSR6V ,Clock source 6 valid" "Not valid,Valid"
newline
endif
bitfld.long 0x00 5. " CLKSR5V ,Clock source 5 valid" "Not valid,Valid"
bitfld.long 0x00 4. " CLKSR4V ,Clock source 4 valid" "Not valid,Valid"
bitfld.long 0x00 3. " CLKSR3V ,Clock source 3 valid" "Not valid,Valid"
newline
bitfld.long 0x00 1. " CLKSR1V ,Clock source 1 valid" "Not valid,Valid"
bitfld.long 0x00 0. " CLKSR0V ,Clock source 0 valid" "Not valid,Valid"
endif
group.long 0x1E70++0x07
line.long 0x00 "PLLCTL1,PLL Control 1 Register"
bitfld.long 0x00 31. " ROS ,Reset on PLL slip" "No reset,Reset"
sif (cpuis("TMS570LS09*")||cpuis("TMS570LS07*")||cpuis("TMS570LS0232")||cpuis("TMS570LS3137-EP"))
bitfld.long 0x00 29.--30. " MASK_SLIP ,Bypass of PLL slip" "Bypassed,Bypassed,Not bypassed,Bypassed"
else
bitfld.long 0x00 29.--30. " BPOS ,Bypass of PLL slip" "Bypassed,Bypassed,Not bypassed,Bypassed"
endif
bitfld.long 0x00 24.--28. " PLLDIV ,PLL output clock divider" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32"
newline
bitfld.long 0x00 23. " ROF ,Reset on oscillator fail" "No reset,Reset"
sif (cpuis("TMS570LS09*")||cpuis("TMS570LS07*")||cpuis("TMS570LS0232")||cpuis("TMS570LS3137-EP"))
bitfld.long 0x00 16.--21. " REFCLKDIV ,Reference clock divider" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/50,/61,/62,/63,/64"
newline
else
bitfld.long 0x00 16.--21. " REFCLKDIV ,Reference clock divider" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/50,/61,/62,/63,?..."
newline
endif
hexmask.long.word 0x00 0.--15. 1. " PLLMUL ,PLL multiplication factor"
line.long 0x04 "PLLCTL2,PLL Control 2 Register"
bitfld.long 0x04 31. " FMENA ,Frequency modulation enable" "Disabled,Enabled"
hexmask.long.word 0x04 22.--30. 1. " SPREADINGRATE ,Spreading rate"
hexmask.long.word 0x04 12.--20. 1. " MULMOD ,Multiplier correction"
newline
bitfld.long 0x04 9.--11. " ODPLL ,Internal PLL output divider" "/1,/2,/3,/4,/5,/6,/7,/8"
hexmask.long.word 0x04 0.--8. 1. " SPR_AMOUNT ,Spreading amount"
sif (cpu()!=("TMS570LS0332")&&cpu()!=("TMS570LS0432"))&&!cpuis("TMS570LS09*")&&!cpuis("TMS570LS07*")&&!cpuis("TMS570LS0232")
group.long 0x00++0x03
line.long 0x00 "PLLCTL3,PLL Control 3 Register"
sif cpuis("TMS570LS3137-EP")
bitfld.long 0x00 29.--31. " ODPLL2 ,Internal PLL output divider" "/1,/2,/3,/4,/5,/6,/7,/8"
bitfld.long 0x00 24.--28. " PLLDIV2 ,PLL output clock divider" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32"
else
bitfld.long 0x00 29.--31. " ODPLL ,Internal PLL output divider" "/1,/2,/3,/4,/5,/6,/7,/8"
bitfld.long 0x00 24.--28. " PLLDIV ,PLL output clock divider" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32"
endif
sif !cpuis("TMS570LS3137-EP")
bitfld.long 0x00 16.--21. " REFCLKDIV ,Reference clock divider" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/50,/61,/62,/63,?..."
else
bitfld.long 0x00 16.--21. " REFCLKDIV2 ,Reference clock divider" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/50,/61,/62,/63,/64"
endif
newline
sif cpuis("TMS570LS3137-EP")
hexmask.long.word 0x00 0.--15. 1. " PLLMUL2 ,PLL multiplication factor"
else
hexmask.long.word 0x00 0.--15. 1. " PLLMUL ,PLL multiplication factor"
endif
group.long 0x70++0x03
line.long 0x00 "CLKSLIP,PLL Clock Slip Control Register"
bitfld.long 0x00 8.--13. " PLL1_RFSLIP_FILTER_COUNT ,Number of HFLPO cycles to be recognized by RFSLIP as a slip" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 0.--3. " PLL1_RFSLIP_FILTER_KEY ,PLL1 RFSLIP filtering enable key" "Enabled,Enabled,Enabled,Enabled,Enabled,Disabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,?..."
group.long 0x1EA0++0x03
line.long 0x00 "GPREG1,General Purpose Register 1"
sif cpuis("TMS570LS3137-EP")
bitfld.long 0x00 31. " EMIF_FUNC ,EMIF functions" "Disabled,Enabled"
endif
newline
bitfld.long 0x00 20.--25. " PLL1_FBSLIP_FILTER_COUNT ,Number of HFLPO cycles to be recognized by FBSLIP as a slip" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 16.--19. " PLL1_FBSLIP_FILTER_KEY ,PLL1 FBSLIP filtering enable key" "Enabled,Enabled,Enabled,Enabled,Enabled,Disabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,?..."
sif cpuis("TMS570LS3137-EP")
newline
bitfld.long 0x00 15. " OUTPUT_BUFFER_LOW_EMI_MODE[15] ,Control field for the low-EMI mode of output buffer for RTP" "Disabled,Enabled"
bitfld.long 0x00 14. " [14] ,Control field for the low-EMI mode of output buffer for ADEVT" "Disabled,Enabled"
bitfld.long 0x00 13. " [13] ,Control field for the low-EMI mode of output buffer for nERROR" "Disabled,Enabled"
newline
bitfld.long 0x00 12. " [12] ,Control field for the low-EMI mode of output buffer for TEST" "Disabled,Enabled"
bitfld.long 0x00 11. " [11] ,Control field for the low-EMI mode of output buffer for RTCK" "Disabled,Enabled"
bitfld.long 0x00 10. " [10] ,Control field for the low-EMI mode of output buffer for TDO" "Disabled,Enabled"
newline
bitfld.long 0x00 9. " [9] ,Control field for the low-EMI mode of output buffer for TDI" "Disabled,Enabled"
bitfld.long 0x00 8. " [8] ,Control field for the low-EMI mode of output buffer for TMS" "Disabled,Enabled"
bitfld.long 0x00 7. " [7] ,Control field for the low-EMI mode of output buffer for ETM" "Disabled,Enabled"
newline
bitfld.long 0x00 6. " [6] ,Control field for the low-EMI mode of output buffer for EMIF" "Disabled,Enabled"
bitfld.long 0x00 5. " [5] ,Control field for the low-EMI mode of output buffer for FlexRay" "Disabled,Enabled"
bitfld.long 0x00 4. " [4] ,Control field for the low-EMI mode of output buffer for MiBSPI5" "Disabled,Enabled"
newline
bitfld.long 0x00 3. " [3] ,Control field for the low-EMI mode of output buffer for SPI4" "Disabled,Enabled"
bitfld.long 0x00 2. " [2] ,Control field for the low-EMI mode of output buffer for MiBSPI3" "Disabled,Enabled"
bitfld.long 0x00 1. " [1] ,Control field for the low-EMI mode of output buffer for SPI2" "Disabled,Enabled"
newline
bitfld.long 0x00 0. " [0] ,Control field for the low-EMI mode of output buffer for MiBSPI1" "Disabled,Enabled"
endif
sif (cpuis("RM57L843-ZWT")||cpuis("TMS570LS3137-EP"))
group.long 0x1EEC++0x03
line.long 0x00 "GLBSTAT,Global Status Register"
eventfld.long 0x00 9. " FBSLIP ,Over cycle slip detection of PLL" "Not detected,Detected"
eventfld.long 0x00 8. " RFSLIP ,Under cycle slip detection of PLL" "Not detected,Detected"
eventfld.long 0x00 0. " OSCFAIL ,Oscillator fail flag" "Not failed,Failed"
endif
elif (cpuis("TMS570LS09*")||cpuis("TMS570LS07*")||cpuis("TMS570LS0232"))
group.long 0x1EA0++0x03
line.long 0x00 "GPREG1,General Purpose Register"
bitfld.long 0x00 20.--25. " PLL1_FBSLIP_FILTER_COUNT ,FBSLIP down counter programmed value" "Disabled,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles,16 cycles,17 cycles,18 cycles,19 cycles,20 cycles,21 cycles,22 cycles,23 cycles,24 cycles,25 cycles,26 cycles,27 cycles,28 cycles,29 cycles,30 cycles,31 cycles,32 cycles,33 cycles,34 cycles,35 cycles,36 cycles,37 cycles,38 cycles,39 cycles,40 cycles,41 cycles,42 cycles,43 cycles,44 cycles,45 cycles,46 cycles,47 cycles,48 cycles,49 cycles,50 cycles,51 cycles,52 cycles,53 cycles,54 cycles,55 cycles,56 cycles,57 cycles,58 cycles,59 cycles,60 cycles,61 cycles,62 cycles,63 cycles"
bitfld.long 0x00 16.--19. " PLL1_FBSLIP_FILTER_KEY ,Enable the FBSLIP filtering" "Enabled,Enabled,Enabled,Enabled,Enabled,Disabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,?..."
sif cpuis("TMS570LS09*")||cpuis("TMS570LS07*")
newline
bitfld.long 0x00 13. " OUTPUT_BUFFER_LOW_EMI_MODE[6] ,Control field for the low-EMI mode (signal nERROR)" "Disabled,Enabled"
bitfld.long 0x00 11. " [5] ,Control field for the low-EMI mode (signal RTC)" "Disabled,Enabled"
bitfld.long 0x00 10. " [4] ,Control field for the low-EMI mode (signal TDO)" "Disabled,Enabled"
newline
bitfld.long 0x00 8. " [3] ,Control field for the low-EMI mode (signal TMS)" "Disabled,Enabled"
bitfld.long 0x00 4. " [2] ,Control field for the low-EMI mode (MiBSPI5)" "Disabled,Enabled"
bitfld.long 0x00 2. " [1] ,Control field for the low-EMI mode (MiBSPI3)" "Disabled,Enabled"
newline
bitfld.long 0x00 0. " [0] ,Control field for the low-EMI mode (MiBSPI1)" "Disabled,Enabled"
endif
group.long 0x1EEC++0x03
line.long 0x00 "GLBSTAT,Global Status Register"
eventfld.long 0x00 9. " FBSLIP ,Over cycle slip detection of PLL" "Not detected,Detected"
eventfld.long 0x00 8. " RFSLIP ,Under cycle slip detection of PLL" "Not detected,Detected"
eventfld.long 0x00 0. " OSCFAIL ,Oscillator fail flag" "Not failed,Failed"
group.long 0x70++0x03
line.long 0x00 "CLKSLIP,PLL Clock Slip Control Register"
bitfld.long 0x00 8.--13. " PLL1_SLIP_FILTER_COUNT ,Number of HFLPO cycles to be recognized by RFSLIP as a slip" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 0.--3. " PLL1_SLIP_FILTER_KEY ,PLL1 RFSLIP filtering enable key" "Enabled,Enabled,Enabled,Enabled,Enabled,Disabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,?..."
endif
sif (cpuis("TMS570LS09*")||cpuis("TMS570LS07*")||cpuis("TMS570LS0232")||cpuis("TMS570LS3137-EP"))
if (per.l.be(ad:0xFFFFE100+0x1E24)&0x01)==0x01
group.long 0x1E24++0x03
line.long 0x00 "SSWPLL1,PLL Modulation Depth Measurement Control Register"
hexmask.long.byte 0x00 8.--15. 1. " CAPTURE_WINDOW_INDEX ,Count clock edges if phase capture window value is equal"
rbitfld.long 0x00 6. " COUNTER_READ_READY ,Counter read ready" "Not ready,Ready"
bitfld.long 0x00 5. " COUNTER_RESET ,Counter reset" "No reset,Reset"
newline
bitfld.long 0x00 4. " COUNTER_EN ,Counter enable" "Disabled,Enabled"
textfld " "
bitfld.long 0x00 0. " EXT_COUNTER_EN ,Measurement mode" "Modulation depth,Frequency"
else
group.long 0x1E24++0x03
line.long 0x00 "SSWPLL1,PLL Modulation Depth Measurement Control Register"
hexmask.long.byte 0x00 8.--15. 1. " CAPTURE_WINDOW_INDEX ,Count clock edges if phase capture window value is equal"
rbitfld.long 0x00 6. " COUNTER_READ_READY ,Counter read ready" "Not ready,Ready"
bitfld.long 0x00 5. " COUNTER_RESET ,Counter reset" "No reset,Reset"
newline
bitfld.long 0x00 4. " COUNTER_EN ,Counter status" "Inactive,Active"
bitfld.long 0x00 1.--3. " TAP_COUNTER_DIS ,CLKOUT bit select" "CLKOUT[16],CLKOUT[18],CLKOUT[20],CLKOUT[22],CLKOUT[24],CLKOUT[26],CLKOUT[28],CLKOUT[30]"
bitfld.long 0x00 0. " EXT_COUNTER_EN ,Measurement mode" "Modulation depth,Frequency"
endif
else
if (per.l(ad:0xFFFFE100+0x1E24)&0x01)==0x01
group.long 0x1E24++0x03
line.long 0x00 "SSWPLL1,PLL Modulation Depth Measurement Control Register"
hexmask.long.byte 0x00 8.--15. 1. " CAPTURE_WINDOW_INDEX ,Count clock edges if phase capture window value is equal"
rbitfld.long 0x00 6. " COUNTER_READ_READY ,Counter read ready" "Not ready,Ready"
bitfld.long 0x00 5. " COUNTER_RESET ,Counter reset" "No reset,Reset"
newline
bitfld.long 0x00 4. " COUNTER_EN ,Counter enable" "Disabled,Enabled"
textfld " "
bitfld.long 0x00 0. " EXT_COUNTER_EN ,Measurement mode" "Modulation depth,Frequency"
else
group.long 0x1E24++0x03
line.long 0x00 "SSWPLL1,PLL Modulation Depth Measurement Control Register"
hexmask.long.byte 0x00 8.--15. 1. " CAPTURE_WINDOW_INDEX ,Count clock edges if phase capture window value is equal"
rbitfld.long 0x00 6. " COUNTER_READ_READY ,Counter read ready" "Not ready,Ready"
bitfld.long 0x00 5. " COUNTER_RESET ,Counter reset" "No reset,Reset"
newline
bitfld.long 0x00 4. " COUNTER_EN ,Counter status" "Inactive,Active"
bitfld.long 0x00 1.--3. " TAP_COUNTER_DIS ,CLKOUT bit select" "CLKOUT[16],CLKOUT[18],CLKOUT[20],CLKOUT[22],CLKOUT[24],CLKOUT[26],CLKOUT[28],CLKOUT[30]"
bitfld.long 0x00 0. " EXT_COUNTER_EN ,Measurement mode" "Modulation depth,Frequency"
endif
endif
rgroup.long 0x1E28++0x07
line.long 0x00 "SSWPLL2,SSW PLL BIST Control Register 2"
line.long 0x04 "SSWPLL3,SSW PLL BIST Control Register 3"
sif (cpuis("TMS570LS09*")||cpuis("TMS570LS07*")||cpuis("TMS570LS0232"))
endian.le
endif
width 0x0B
tree.end
tree "LPOCLKDET (Low-Power Oscillator and Clock Detect)"
base ad:0xFFFFFF88
sif (cpuis("TMS570LS09*")||cpuis("TMS570LS07*")||cpuis("TMS570LS0232"))
endian.be
endif
width 11.
group.long 0x00++0x07
line.long 0x00 "LPOMONCTL,LPO/Clock Monitor Control Register"
bitfld.long 0x00 24. " BIAS_ENABLE ,Bias enable" "Disabled,Enabled"
bitfld.long 0x00 16. " OSCFRQCONFIGCNT ,OSC frequency based counter configuration" "OSC freq <= 20MHz,20MHz < OSC freq <= 80MHz"
newline
sif (cpuis("TMS570LS0332")||cpuis("TMS570LS0432"))
bitfld.long 0x00 8.--11. " HFTRIM ,High frequency oscillator trim value" "29.52%,38.85%,47.99%,57.02%,65.92%,74.55%,83.17%,91.75%,100%,108.17%,116.41%,124.42%,132.24%,140.15%,148.02%,155.50%"
bitfld.long 0x00 0.--3. " LFTRIM ,Low frequency oscillator trim value" "20.67%,30.84%,40.93%,50.97%,60.86%,70.75%,80.61%,90.23%,100%,109.51%,119.01%,128.62%,138.03%,147.32%,156.63%,165.90%"
else
bitfld.long 0x00 8.--12. " HFTRIM ,High frequency oscillator trim value" "29.52%,34.24%,38.85%,43.45%,47.99%,52.55%,57.02%,61.46%,65.92%,70.17%,74.55%,78.92%,83.17%,87.43%,91.75%,95.89%,100%,104.09%,108.17%,112.32%,116.41%,120.67%,124.42%,128.38%,132.24%,136.15%,140.15%,143.94%,148.02%,151.80%,155.50%,159.35%"
bitfld.long 0x00 0.--4. " LFTRIM ,Low frequency oscillator trim value" "20.67%,25.76%,30.84%,35.90%,40.93%,45.95%,50.97%,55.91%,60.86%,65.78%,70.75%,75.63%,80.61%,85.39%,90.23%,95.11%,100%,104.84%,109.51%,114.31%,119.01%,123.75%,128.62%,133.31%,138.03%,142.75%,147.32%,152.02%,156.63%,161.38%,165.90%,170.42%"
endif
line.long 0x04 "CLKTEST,Clock Test Register"
sif (cpuis("TMS570LS0332")||cpuis("TMS570LS0432"))||(cpuis("TMS570LS09*")||cpuis("TMS570LS07*")||cpuis("TMS570LS0232")||cpuis("TMS570LS3137-EP"))
bitfld.long 0x04 26. " ALTLIMPCLOCKENABLE ,Clock enable" "Disabled,Enabled"
else
bitfld.long 0x04 26. " TEST ,Bit used for test purposes" "0,1"
endif
newline
bitfld.long 0x04 25. " RANGEDETCTRL ,Range detection control" "Disabled,Enabled"
bitfld.long 0x04 24. " RANGEDETENASSEL ,Range detect enable select" "Clock monitor,RANGEDETCTRL"
newline
bitfld.long 0x04 16.--19. " CLK_TEST_EN ,Clock test enable" "Disabled,Disabled,Disabled,Disabled,Disabled,Enabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled"
sif (cpuis("TMS570LS0332")||cpuis("TMS570LS0432"))
newline
bitfld.long 0x04 8.--11. " SEL_GIO_PIN ,Select clock source or it's valid signal at functional GIO pin" "Oscillator valid status,Main PLL valid status,,,,HFLPO CLK10M valid status,,,LFLPO CLK80K valid status,Oscillator valid status,Oscillator valid status,Oscillator valid status,Oscillator valid status,Oscillator valid status,Oscillator valid status,Oscillator valid status"
bitfld.long 0x04 0.--3. " SEL_ECP_PIN ,Select clock at ECP pin" "Oscillator,PLL clock,,,LFLPO,HFLPO,,,GCLK,RTI Base,,VCLKA1,,,,Flash HDPO"
elif (cpuis("TMS570LS1114*")||cpuis("TMS570LS1115*")||cpuis("TMS570LS1224*")||cpuis("TMS570LS1225*")||cpuis("TMS570LS1227*"))
newline
bitfld.long 0x04 8.--11. " SEL_GIO_PIN ,Select clock source or it's valid signal at functional GIO pin" "Oscillator valid status,Main PLL valid status,,,,HFLPO valid status,PLL2 valid status,,LFLPO,Oscillator valid status,Oscillator valid status,Oscillator valid status,Oscillator valid status,,VCLKA4_S,Oscillator valid status"
bitfld.long 0x04 0.--3. " SEL_ECP_PIN ,Select clock at ECP pin" "Oscillator,PLL clock,,EXTCLKIN1,LFLPO,HFLPO,PLL2 clock,EXTCLKIN2,GCLK,RTI Base,,VCLKA1,VCLKA2,,VCLKA4_DIVR,?..."
elif cpuis("RM57L843-ZWT")
newline
bitfld.long 0x04 8.--11. " SEL_GIO_PIN ,Select clock source or it's valid signal at functional GIO pin" "Oscillator valid status,PLL clock status,,,,HFLPO valid status,SPLLFRCO valid status,,LFLPO valid status,Oscillator valid status,Oscillator valid status,Oscillator valid status,Oscillator valid status,Oscillator valid status,Oscillator valid status,Oscillator valid status"
bitfld.long 0x04 0.--3. " SEL_ECP_PIN ,Select clock at ECP pin" "Oscillator clock,PLL clock,,EXTCLKIN1,LFLPO,HFLPO,Secondary PLL,EXCLKIN2,GCLK,RTI Base,,VCLKA1,VCLKA2,VCLKA3_S,VCLKA4,Flash HDPO"
elif cpuis("TMS570LS0232")
newline
bitfld.long 0x04 8.--11. " SEL_N2HET_PIN ,Pin clock source valid or clock source select" "Oscillator valid status,PLL1 valid status,,,,HFLPO CLK10M valid status,,,LFLPO CLK80K valid status,Oscillator valid status,Oscillator valid status,Oscillator valid status,Oscillator valid status,Oscillator valid status,Oscillator valid status,Oscillator valid status"
bitfld.long 0x04 0.--3. " SEL_ECP_PIN ,ECLK pin clock source select" "Oscillator clock,PLL1 clock output,,,LFLPO CLK80K,HFLPO CLK10M,,,GCLK,RTI Base,,VCLKA1,,,,Flash HD pump oscillator"
elif cpuis("TMS570LS09*")||cpuis("TMS570LS07*")
newline
bitfld.long 0x04 8.--11. " SEL_GIO_PIN ,Pin clock source valid or clock source select" "Oscillator valid status,PLL1 valid status,,,,HFLPO clock valid status,,,LFLPO clock valid status,Oscillator valid status,Oscillator valid status,Oscillator valid status,Oscillator valid status,,,Oscillator valid status"
bitfld.long 0x04 0.--4. " SEL_ECP_PIN ,ECLK pin clock source select" "Oscillator clock,PLL1 free-running clock output,,EXTCLKIN1,LFLPO clock,HFLPO clock,,EXTCLKIN2,GCLK,RTI base,,VCLKA1,,,,,,HCLK1,VCLK1,VCLK2,,VCLK4,?..."
elif cpuis("TMS570LS3137-EP")
newline
bitfld.long 0x04 8.--11. " SEL_GIO_PIN ,GIOB[0] pin clock source valid/select" "Oscillator,PLL1,,,,HFLPO,PLL2,,LFLPO,?..."
bitfld.long 0x04 0.--3. " SEL_ECP_PIN ,ECLK pin clock source select" "Oscillator,PLL1,,EXTCLKIN1,LFLPO,HFLPO,PLL2,EXTCLKIN2,GCLK,RTI base,,VCLKA1,VCLKA2,,VCLKA4,?..."
else
newline
bitfld.long 0x04 8.--11. " SEL_GIO_PIN ,Select clock source or it's valid signal at functional GIO pin" "Oscillator Valid status,Main PLL Valid status,,,,HFLPO CLK10M Valid status,,,LFLPO CLK80K Valid status,Oscillator Valid status,Oscillator Valid status,Oscillator Valid status,Oscillator Valid status,,VCLKA4_S,Oscillator Valid status"
bitfld.long 0x04 0.--4. " SEL_ECP_PIN ,Select clock at ECP pin" "Oscillator,Main PLL free-running clock output,,EXTCLKIN1,LFLPO,HFLPO,Secondary PLL free-running clock output,EXTCLKIN2,GCLK,RTI1 Base,RTI2 Base,VCLKA1,VCLKA2,,VCLKA4,Flash HD Pump Oscillator,,HCLK,VCLK,VCLK2,VCLK3,,,EMAC Clock,?..."
endif
sif (cpuis("TMS570LS09*")||cpuis("TMS570LS07*")||cpuis("TMS570LS0232"))
endian.le
endif
width 0x0B
tree.end
tree.open "DCC (Dual-Clock Comparator)"
tree "DCC1"
base ad:0xFFFFEC00
width 12.
group.long 0x00++0x03
line.long 0x00 "GCTRL,Global Control Register"
bitfld.long 0x00 12.--15. " DONE_INT_ENA ,Done interrupt enable" "Enabled,Enabled,Enabled,Enabled,Enabled,Disabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled"
bitfld.long 0x00 8.--11. " SINGLE_SHOT ,Single-Shot mode enable" "Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Enabled,Enabled,Disabled,Disabled,Disabled,Disabled"
bitfld.long 0x00 4.--7. " ERR_ENA ,Error interrupt enable" "Enabled,Enabled,Enabled,Enabled,Enabled,Disabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled"
bitfld.long 0x00 0.--3. " DCC_ENA ,DCC enable" "Enabled,Enabled,Enabled,Enabled,Enabled,Disabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled"
rgroup.long 0x04++0x03
line.long 0x00 "REV,Revision ID"
bitfld.long 0x00 30.--31. " SCHEME ,Scheme" "0,1,2,3"
hexmask.long.word 0x00 16.--27. 1. " FUNC ,Functional release number"
bitfld.long 0x00 11.--15. " RTL ,Design release number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 8.--10. " MAJOR ,Major revision number" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--7. " CUSTOM ,Custom version number" "0,1,2,3"
bitfld.long 0x00 0.--5. " MINOR ,Minor revision number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x08++0x03
line.long 0x00 "CNTSEED0,DCC Counter0 Seed Register"
hexmask.long.tbyte 0x00 0.--19. 1. " COUNT0_SEED ,Seed value for DCC counter0"
group.long 0x0C++0x03
line.long 0x00 "VALIDSEED0,Valid0 Seed Value"
hexmask.long.word 0x00 0.--15. 1. " VALID0_SEED ,Seed value for DCC valid0"
group.long 0x10++0x03
line.long 0x00 "CNTSEED1,DCC Counter1 Seed Register"
hexmask.long.tbyte 0x00 0.--19. 1. " COUNT1_SEED ,Seed value for DCC counter1"
group.long 0x14++0x03
line.long 0x00 "STAT,Status Register"
eventfld.long 0x00 1. " DONE_FLG ,Single-Shot sequence done flag" "Not done,Done"
eventfld.long 0x00 0. " ERR_FLG ,Error flag" "No error,Error"
rgroup.long 0x18++0x03
line.long 0x00 "CNT0,DCC Counter0 Value Register"
hexmask.long.tbyte 0x00 0.--19. 1. " COUNT0 ,Value of DCC counter0"
rgroup.long 0x1C++0x03
line.long 0x00 "VALID0,Valid0 Value Register"
hexmask.long.word 0x00 0.--15. 1. " VALID0 ,Current value for DCC valid0"
group.long 0x20++0x03
line.long 0x00 "CNT1,DCC Counter1 Value Register"
hexmask.long.tbyte 0x00 0.--19. 1. " COUNT1 ,Value of DCC counter1"
if (((d.l(ad:0xFFFFEC00+0x24))&0xF000)==0xA000)
group.long 0x24++0x03
line.long 0x00 "CNT1CLKSRC,DCC Counter1 Clock Source Selection Register"
bitfld.long 0x00 12.--15. " KEY ,Key to enable clock source selection for counter1" "Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Enabled,Disabled,Disabled,Disabled,Disabled,Disabled"
bitfld.long 0x00 0.--3. " CNT1_CLKSRC ,Clock source for counter1" "PLL1 output,PLL2 output,LF LPO,HF LPO,,EXTCLKIN1,EXTCLKIN2,,VCLK,VCLK,VCLK,VCLK,VCLK,VCLK,VCLK,VCLK"
else
group.long 0x24++0x03
line.long 0x00 "CNT1CLKSRC,DCC Counter1 Clock Source Selection Register"
bitfld.long 0x00 12.--15. " KEY ,Key to enable clock source selection for counter1" "Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Enabled,Disabled,Disabled,Disabled,Disabled,Disabled"
bitfld.long 0x00 0.--3. " CNT1_CLKSRC ,Clock source for counter1" "N2HET1[31],N2HET1[31],N2HET1[31],N2HET1[31],N2HET1[31],N2HET1[31],N2HET1[31],N2HET1[31],N2HET1[31],N2HET1[31],N2HET1[31],N2HET1[31],N2HET1[31],N2HET1[31],N2HET1[31],N2HET1[31]"
endif
group.long 0x28++0x03
line.long 0x00 "CNT0CLKSRC,DCC Counter0 Clock Source Selection Register"
bitfld.long 0x00 0.--3. " CNT1_CLKSRC ,Clock source for counter1" "OSCIN,OSCIN,OSCIN,OSCIN,OSCIN,HF LPO,OSCIN,OSCIN,OSCIN,OSCIN,TCK,OSCIN,OSCIN,OSCIN,OSCIN,OSCIN"
width 0x0B
tree.end
tree "DCC2"
base ad:0xFFFFF400
width 12.
group.long 0x00++0x03
line.long 0x00 "GCTRL,Global Control Register"
bitfld.long 0x00 12.--15. " DONE_INT_ENA ,Done interrupt enable" "Enabled,Enabled,Enabled,Enabled,Enabled,Disabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled"
bitfld.long 0x00 8.--11. " SINGLE_SHOT ,Single-Shot mode enable" "Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Enabled,Enabled,Disabled,Disabled,Disabled,Disabled"
bitfld.long 0x00 4.--7. " ERR_ENA ,Error interrupt enable" "Enabled,Enabled,Enabled,Enabled,Enabled,Disabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled"
bitfld.long 0x00 0.--3. " DCC_ENA ,DCC enable" "Enabled,Enabled,Enabled,Enabled,Enabled,Disabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled"
rgroup.long 0x04++0x03
line.long 0x00 "REV,Revision ID"
bitfld.long 0x00 30.--31. " SCHEME ,Scheme" "0,1,2,3"
hexmask.long.word 0x00 16.--27. 1. " FUNC ,Functional release number"
bitfld.long 0x00 11.--15. " RTL ,Design release number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 8.--10. " MAJOR ,Major revision number" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--7. " CUSTOM ,Custom version number" "0,1,2,3"
bitfld.long 0x00 0.--5. " MINOR ,Minor revision number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x08++0x03
line.long 0x00 "CNTSEED0,DCC Counter0 Seed Register"
hexmask.long.tbyte 0x00 0.--19. 1. " COUNT0_SEED ,Seed value for DCC counter0"
group.long 0x0C++0x03
line.long 0x00 "VALIDSEED0,Valid0 Seed Value"
hexmask.long.word 0x00 0.--15. 1. " VALID0_SEED ,Seed value for DCC valid0"
group.long 0x10++0x03
line.long 0x00 "CNTSEED1,DCC Counter1 Seed Register"
hexmask.long.tbyte 0x00 0.--19. 1. " COUNT1_SEED ,Seed value for DCC counter1"
group.long 0x14++0x03
line.long 0x00 "STAT,Status Register"
eventfld.long 0x00 1. " DONE_FLG ,Single-Shot sequence done flag" "Not done,Done"
eventfld.long 0x00 0. " ERR_FLG ,Error flag" "No error,Error"
rgroup.long 0x18++0x03
line.long 0x00 "CNT0,DCC Counter0 Value Register"
hexmask.long.tbyte 0x00 0.--19. 1. " COUNT0 ,Value of DCC counter0"
rgroup.long 0x1C++0x03
line.long 0x00 "VALID0,Valid0 Value Register"
hexmask.long.word 0x00 0.--15. 1. " VALID0 ,Current value for DCC valid0"
group.long 0x20++0x03
line.long 0x00 "CNT1,DCC Counter1 Value Register"
hexmask.long.tbyte 0x00 0.--19. 1. " COUNT1 ,Value of DCC counter1"
if (((d.l(ad:0xFFFFF400+0x24))&0xF000)==0xA000)
group.long 0x24++0x03
line.long 0x00 "CNT1CLKSRC,DCC Counter1 Clock Source Selection Register"
bitfld.long 0x00 12.--15. " KEY ,Key to enable clock source selection for counter1" "Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Enabled,Disabled,Disabled,Disabled,Disabled,Disabled"
bitfld.long 0x00 0.--3. " CNT1_CLKSRC ,Clock source for counter1" ",Pll2_post_odclk/8,Pll2_post_odclk/16,,,,,,VCLK,VCLK,VCLK,VCLK,VCLK,VCLK,VCLK,VCLK"
else
group.long 0x24++0x03
line.long 0x00 "CNT1CLKSRC,DCC Counter1 Clock Source Selection Register"
bitfld.long 0x00 12.--15. " KEY ,Key to enable clock source selection for counter1" "Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Enabled,Disabled,Disabled,Disabled,Disabled,Disabled"
bitfld.long 0x00 0.--3. " CNT1_CLKSRC ,Clock source for counter1" "N2HET2[0],N2HET2[0],N2HET2[0],N2HET2[0],N2HET2[0],N2HET2[0],N2HET2[0],N2HET2[0],N2HET2[0],N2HET2[0],N2HET2[0],N2HET2[0],N2HET2[0],N2HET2[0],N2HET2[0],N2HET2[0]"
endif
group.long 0x28++0x03
line.long 0x00 "CNT0CLKSRC,DCC Counter0 Clock Source Selection Register"
bitfld.long 0x00 0.--3. " CNT1_CLKSRC ,Clock source for counter1" "OSCIN,OSCIN,OSCIN,OSCIN,OSCIN,OSCIN,OSCIN,OSCIN,OSCIN,OSCIN,TCK,OSCIN,OSCIN,OSCIN,OSCIN,OSCIN"
width 0x0B
tree.end
tree.end
tree "ESM (Error Signaling Module)"
base ad:0xFFFFF500
width 8.
group.long 0x00++0x03
line.long 0x00 "IEPSR1,Influence Error Pin Set/status Register 1"
setclrfld.long 0x00 31. 0x00 31. 0x04 31. " IEP_SET/CLR[31] ,Set/clear influence on error pin 31 (Ccm-r5f - selftest)" "No influence,Influence"
setclrfld.long 0x00 30. 0x00 30. 0x04 30. " [30] ,Set/clear influence on error pin 30 (Dcc1 - error)" "No influence,Influence"
setclrfld.long 0x00 27. 0x00 27. 0x04 27. " [27] ,Set/clear influence on error pin 27 (Cortex-r5f CPU - selftest)" "No influence,Influence"
setclrfld.long 0x00 26. 0x00 26. 0x04 26. " [26] ,Set/clear influence on error pin 26 (L2ramw - correctable error)" "No influence,Influence"
textline " "
setclrfld.long 0x00 24. 0x00 24. 0x04 24. " [24] ,Set/clear influence on error pin 24 (Mibspi5 - ECC uncorrectable error)" "No influence,Influence"
setclrfld.long 0x00 23. 0x00 23. 0x04 23. " [23] ,Set/clear influence on error pin 23 (Dcan2 - ECC uncorrectable error)" "No influence,Influence"
setclrfld.long 0x00 22. 0x00 22. 0x04 22. " [22] ,Set/clear influence on error pin 22 (Dcan3 - ECC uncorrectable error)" "No influence,Influence"
setclrfld.long 0x00 21. 0x00 21. 0x04 21. " [21] ,Set/clear influence on error pin 21 (Dcan1 - ECC uncorrectable error)" "No influence,Influence"
textline " "
setclrfld.long 0x00 20. 0x00 20. 0x04 20. " [20] ,Set/clear influence on error pin 20 (Dma - bus error)" "No influence,Influence"
setclrfld.long 0x00 19. 0x00 19. 0x04 19. " [19] ,Set/clear influence on error pin 19 (Mibadc1 - parity)" "No influence,Influence"
setclrfld.long 0x00 18. 0x00 18. 0x04 18. " [18] ,Set/clear influence on error pin 18 (Mibspi3 - ECC uncorrectable error)" "No influence,Influence"
setclrfld.long 0x00 17. 0x00 17. 0x04 17. " [17] ,Set/clear influence on error pin 17 (Mibspi1 - ECC uncorrectable error)" "No influence,Influence"
textline " "
setclrfld.long 0x00 16. 0x00 16. 0x04 16. " [16] ,Set/clear influence on error pin 16 (Flexray TU - MPU)" "No influence,Influence"
setclrfld.long 0x00 15. 0x00 15. 0x04 15. " [15] ,Set/clear influence on error pin 15 (Vim RAM - ECC uncorrectable error)" "No influence,Influence"
setclrfld.long 0x00 14. 0x00 14. 0x04 14. " [14] ,Set/clear influence on error pin 14 (Flexray TU RAM - ECC uncorrectable error)" "No influence,Influence"
setclrfld.long 0x00 12. 0x00 12. 0x04 12. " [12] ,Set/clear influence on error pin 12 (Flexray RAM - ECC uncorrectable error)" "No influence,Influence"
textline " "
setclrfld.long 0x00 11. 0x00 11. 0x04 11. " [11] ,Set/clear influence on error pin 11 (Lpo clock monitor - interrupt)" "No influence,Influence"
setclrfld.long 0x00 10. 0x00 10. 0x04 10. " [10] ,Set/clear influence on error pin 10 (Pll1 - slip)" "No influence,Influence"
setclrfld.long 0x00 9. 0x00 9. 0x04 9. " [9] ,Set/clear influence on error pin 9 (Het TU1/HET TU2 - MPU)" "No influence,Influence"
setclrfld.long 0x00 8. 0x00 8. 0x04 8. " [8] ,Set/clear influence on error pin 8 (Het TU1/HET TU2 - parity)" "No influence,Influence"
textline " "
setclrfld.long 0x00 7. 0x00 7. 0x04 7. " [7] ,Set/clear influence on error pin 7 (Nhet1 - parity)" "No influence,Influence"
setclrfld.long 0x00 6. 0x00 6. 0x04 6. " [6] ,Set/clear influence on error pin 6 (L2fmc - correctable error)" "No influence,Influence"
setclrfld.long 0x00 4. 0x00 4. 0x04 4. " [4] ,Set/clear influence on error pin 4 (Epc - correctable error)" "No influence,Influence"
setclrfld.long 0x00 3. 0x00 3. 0x04 3. " [3] ,Set/clear influence on error pin 3 (Dma - ECC uncorrectable error)" "No influence,Influence"
textline " "
setclrfld.long 0x00 2. 0x00 2. 0x04 2. " [2] ,Set/clear influence on error pin 2 (Dma - MPU error for CPU)" "No influence,Influence"
setclrfld.long 0x00 1. 0x00 1. 0x04 1. " [1] ,Set/clear influence on error pin 1 (Mibadc2 - parity)" "No influence,Influence"
group.long 0x08++0x03
line.long 0x00 "IESR1,Interrupt Enable Set/status Register 1"
setclrfld.long 0x00 31. 0x00 31. 0x04 31. " INTEN_SET/CLR[31] ,Set/clear interrupt enable 31 (Ccm-r5f - selftest)" "Disabled,Enabled"
setclrfld.long 0x00 30. 0x00 30. 0x04 30. " [30] ,Set/clear interrupt enable 30 (Dcc1 - error)" "Disabled,Enabled"
setclrfld.long 0x00 27. 0x00 27. 0x04 27. " [27] ,Set/clear interrupt enable 27 (Cortex-r5f CPU - selftest)" "Disabled,Enabled"
setclrfld.long 0x00 26. 0x00 26. 0x04 26. " [26] ,Set/clear interrupt enable 26 (L2ramw - correctable error)" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 24. 0x00 24. 0x04 24. " [24] ,Set/clear interrupt enable 24 (Mibspi5 - ECC uncorrectable error)" "Disabled,Enabled"
setclrfld.long 0x00 23. 0x00 23. 0x04 23. " [23] ,Set/clear interrupt enable 23 (Dcan2 - ECC uncorrectable error)" "Disabled,Enabled"
setclrfld.long 0x00 22. 0x00 22. 0x04 22. " [22] ,Set/clear interrupt enable 22 (Dcan3 - ECC uncorrectable error)" "Disabled,Enabled"
setclrfld.long 0x00 21. 0x00 21. 0x04 21. " [21] ,Set/clear interrupt enable 21 (Dcan1 - ECC uncorrectable error)" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 20. 0x00 20. 0x04 20. " [20] ,Set/clear interrupt enable 20 (Dma - bus error)" "Disabled,Enabled"
setclrfld.long 0x00 19. 0x00 19. 0x04 19. " [19] ,Set/clear interrupt enable 19 (Mibadc1 - parity)" "Disabled,Enabled"
setclrfld.long 0x00 18. 0x00 18. 0x04 18. " [18] ,Set/clear interrupt enable 18 (Mibspi3 - ECC uncorrectable error)" "Disabled,Enabled"
setclrfld.long 0x00 17. 0x00 17. 0x04 17. " [17] ,Set/clear interrupt enable 17 (Mibspi1 - ECC uncorrectable error)" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 16. 0x00 16. 0x04 16. " [16] ,Set/clear interrupt enable 16 (Flexray TU - MPU)" "Disabled,Enabled"
setclrfld.long 0x00 15. 0x00 15. 0x04 15. " [15] ,Set/clear interrupt enable 15 (Vim RAM - ECC uncorrectable error)" "Disabled,Enabled"
setclrfld.long 0x00 14. 0x00 14. 0x04 14. " [14] ,Set/clear interrupt enable 14 (Flexray TU RAM - ECC uncorrectable error)" "Disabled,Enabled"
setclrfld.long 0x00 12. 0x00 12. 0x04 12. " [12] ,Set/clear interrupt enable 12 (Flexray RAM - ECC uncorrectable error)" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 11. 0x00 11. 0x04 11. " [11] ,Set/clear interrupt enable 11 (Lpo clock monitor - interrupt)" "Disabled,Enabled"
setclrfld.long 0x00 10. 0x00 10. 0x04 10. " [10] ,Set/clear interrupt enable 10 (Pll1 - slip)" "Disabled,Enabled"
setclrfld.long 0x00 9. 0x00 9. 0x04 9. " [9] ,Set/clear interrupt enable 9 (Het TU1/HET TU2 - MPU)" "Disabled,Enabled"
setclrfld.long 0x00 8. 0x00 8. 0x04 8. " [8] ,Set/clear interrupt enable 8 (Het TU1/HET TU2 - parity)" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 7. 0x00 7. 0x04 7. " [7] ,Set/clear interrupt enable 7 (Nhet1 - parity)" "Disabled,Enabled"
setclrfld.long 0x00 6. 0x00 6. 0x04 6. " [6] ,Set/clear interrupt enable 6 (L2fmc - correctable error)" "Disabled,Enabled"
setclrfld.long 0x00 4. 0x00 4. 0x04 4. " [4] ,Set/clear interrupt enable 4 (Epc - correctable error)" "Disabled,Enabled"
setclrfld.long 0x00 3. 0x00 3. 0x04 3. " [3] ,Set/clear interrupt enable 3 (Dma - ECC uncorrectable error)" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 2. 0x00 2. 0x04 2. " [2] ,Set/clear interrupt enable 2 (Dma - MPU error for CPU)" "Disabled,Enabled"
setclrfld.long 0x00 1. 0x00 1. 0x04 1. " [1] ,Set/clear interrupt enable 1 (Mibadc2 - parity)" "Disabled,Enabled"
group.long 0x10++0x03
line.long 0x00 "ILSR1,Interrupt Level Set/status Register 1"
setclrfld.long 0x00 31. 0x00 31. 0x04 31. " INTLVL_SET/CLR[31] ,Set/clear interrupt level 31 (Ccm-r5f - selftest)" "Low,High"
setclrfld.long 0x00 30. 0x00 30. 0x04 30. " [30] ,Set/clear interrupt level 30 (Dcc1 - error)" "Low,High"
setclrfld.long 0x00 27. 0x00 27. 0x04 27. " [27] ,Set/clear interrupt level 27 (Cortex-r5f CPU - selftest)" "Low,High"
setclrfld.long 0x00 26. 0x00 26. 0x04 26. " [26] ,Set/clear interrupt level 26 (L2ramw - correctable error)" "Low,High"
textline " "
setclrfld.long 0x00 24. 0x00 24. 0x04 24. " [24] ,Set/clear interrupt level 24 (Mibspi5 - ECC uncorrectable error)" "Low,High"
setclrfld.long 0x00 23. 0x00 23. 0x04 23. " [23] ,Set/clear interrupt level 23 (Dcan2 - ECC uncorrectable error)" "Low,High"
setclrfld.long 0x00 22. 0x00 22. 0x04 22. " [22] ,Set/clear interrupt level 22 (Dcan3 - ECC uncorrectable error)" "Low,High"
setclrfld.long 0x00 21. 0x00 21. 0x04 21. " [21] ,Set/clear interrupt level 21 (Dcan1 - ECC uncorrectable error)" "Low,High"
textline " "
setclrfld.long 0x00 20. 0x00 20. 0x04 20. " [20] ,Set/clear interrupt level 20 (Dma - bus error)" "Low,High"
setclrfld.long 0x00 19. 0x00 19. 0x04 19. " [19] ,Set/clear interrupt level 19 (Mibadc1 - parity)" "Low,High"
setclrfld.long 0x00 18. 0x00 18. 0x04 18. " [18] ,Set/clear interrupt level 18 (Mibspi3 - ECC uncorrectable error)" "Low,High"
setclrfld.long 0x00 17. 0x00 17. 0x04 17. " [17] ,Set/clear interrupt level 17 (Mibspi1 - ECC uncorrectable error)" "Low,High"
textline " "
setclrfld.long 0x00 16. 0x00 16. 0x04 16. " [16] ,Set/clear interrupt level 16 (Flexray TU - MPU)" "Low,High"
setclrfld.long 0x00 15. 0x00 15. 0x04 15. " [15] ,Set/clear interrupt level 15 (Vim RAM - ECC uncorrectable error)" "Low,High"
setclrfld.long 0x00 14. 0x00 14. 0x04 14. " [14] ,Set/clear interrupt level 14 (Flexray TU RAM - ECC uncorrectable error)" "Low,High"
setclrfld.long 0x00 12. 0x00 12. 0x04 12. " [12] ,Set/clear interrupt level 12 (Flexray RAM - ECC uncorrectable error)" "Low,High"
textline " "
setclrfld.long 0x00 11. 0x00 11. 0x04 11. " [11] ,Set/clear interrupt level 11 (Lpo clock monitor - interrupt)" "Low,High"
setclrfld.long 0x00 10. 0x00 10. 0x04 10. " [10] ,Set/clear interrupt level 10 (Pll1 - slip)" "Low,High"
setclrfld.long 0x00 9. 0x00 9. 0x04 9. " [9] ,Set/clear interrupt level 9 (Het TU1/HET TU2 - MPU)" "Low,High"
setclrfld.long 0x00 8. 0x00 8. 0x04 8. " [8] ,Set/clear interrupt level 8 (Het TU1/HET TU2 - parity)" "Low,High"
textline " "
setclrfld.long 0x00 7. 0x00 7. 0x04 7. " [7] ,Set/clear interrupt level 7 (Nhet1 - parity)" "Low,High"
setclrfld.long 0x00 6. 0x00 6. 0x04 6. " [6] ,Set/clear interrupt level 6 (L2fmc - correctable error)" "Low,High"
setclrfld.long 0x00 4. 0x00 4. 0x04 4. " [4] ,Set/clear interrupt level 4 (Epc - correctable error)" "Low,High"
setclrfld.long 0x00 3. 0x00 3. 0x04 3. " [3] ,Set/clear interrupt level 3 (Dma - ECC uncorrectable error)" "Low,High"
textline " "
setclrfld.long 0x00 2. 0x00 2. 0x04 2. " [2] ,Set/clear interrupt level 2 (Dma - MPU error for CPU)" "Low,High"
setclrfld.long 0x00 1. 0x00 1. 0x04 1. " [1] ,Set/clear interrupt level 1 (Mibadc2 - parity)" "Low,High"
group.long 0x18++0x03
line.long 0x00 "SR1,Status Register 1"
eventfld.long 0x00 31. " ESF[31] ,Error status flag 31 (Ccm-r5f - selftest)" "No error,Error"
eventfld.long 0x00 30. " [30] ,Error status flag 30 (Dcc1 - error)" "No error,Error"
eventfld.long 0x00 27. " [27] ,Error status flag 27 (Cortex-r5f CPU - selftest)" "No error,Error"
eventfld.long 0x00 26. " [26] ,Error status flag 26 (L2ramw - correctable error)" "No error,Error"
textline " "
eventfld.long 0x00 24. " [24] ,Error status flag 24 (Mibspi5 - ECC uncorrectable error)" "No error,Error"
eventfld.long 0x00 23. " [23] ,Error status flag 23 (Dcan2 - ECC uncorrectable error)" "No error,Error"
eventfld.long 0x00 22. " [22] ,Error status flag 22 (Dcan3 - ECC uncorrectable error)" "No error,Error"
eventfld.long 0x00 21. " [21] ,Error status flag 21 (Dcan1 - ECC uncorrectable error)" "No error,Error"
textline " "
eventfld.long 0x00 20. " [20] ,Error status flag 20 (Dma - bus error)" "No error,Error"
eventfld.long 0x00 19. " [19] ,Error status flag 19 (Mibadc1 - parity)" "No error,Error"
eventfld.long 0x00 18. " [18] ,Error status flag 18 (Mibspi3 - ECC uncorrectable error)" "No error,Error"
eventfld.long 0x00 17. " [17] ,Error status flag 17 (Mibspi1 - ECC uncorrectable error)" "No error,Error"
textline " "
eventfld.long 0x00 16. " [16] ,Error status flag 16 (Flexray TU - MPU)" "No error,Error"
eventfld.long 0x00 15. " [15] ,Error status flag 15 (Vim RAM - ECC uncorrectable error)" "No error,Error"
eventfld.long 0x00 14. " [14] ,Error status flag 14 (Flexray TU RAM - ECC uncorrectable error)" "No error,Error"
eventfld.long 0x00 12. " [12] ,Error status flag 12 (Flexray RAM - ECC uncorrectable error)" "No error,Error"
textline " "
eventfld.long 0x00 11. " [11] ,Error status flag 11 (Lpo clock monitor - interrupt)" "No error,Error"
eventfld.long 0x00 10. " [10] ,Error status flag 10 (Pll1 - slip)" "No error,Error"
eventfld.long 0x00 9. " [9] ,Error status flag 9 (Het TU1/HET TU2 - MPU)" "No error,Error"
eventfld.long 0x00 8. " [8] ,Error status flag 8 (Het TU1/HET TU2 - parity)" "No error,Error"
textline " "
eventfld.long 0x00 7. " [7] ,Error status flag 7 (Nhet1 - parity)" "No error,Error"
eventfld.long 0x00 6. " [6] ,Error status flag 6 (L2fmc - correctable error)" "No error,Error"
eventfld.long 0x00 4. " [4] ,Error status flag 4 (Epc - correctable error)" "No error,Error"
eventfld.long 0x00 3. " [3] ,Error status flag 3 (Dma - ECC uncorrectable error)" "No error,Error"
textline " "
eventfld.long 0x00 2. " [2] ,Error status flag 2 (Dma - MPU error for CPU)" "No error,Error"
eventfld.long 0x00 1. " [1] ,Error status flag 1 (Mibadc2 - parity)" "No error,Error"
group.long 0x1C++0x03
line.long 0x00 "SR2,Status Register 2"
eventfld.long 0x00 28. " ESF2[28] ,Error status flag 28 (Ccm-r5f - power domain monitor error)" "No error,Error"
eventfld.long 0x00 26. " [26] ,Error status flag 26 (Cpu1 AXIM bus monitor failure)" "No error,Error"
eventfld.long 0x00 25. " [25] ,Error status flag 25 (Ccm-r5f VIM compare error)" "No error,Error"
eventfld.long 0x00 24. " [24] ,Error status flag 24 (Rti_wwd_nmi)" "No error,Error"
textline " "
eventfld.long 0x00 21. " [21] ,Error status flag 21 (Epc - uncorrectable error)" "No error,Error"
eventfld.long 0x00 19. " [19] ,Error status flag 19 (L2fmc - double bit ECC error)" "No error,Error"
eventfld.long 0x00 17. " [17] ,Error status flag 17 (L2fmc/mcmd/pom/port A/B parity error)" "No error,Error"
eventfld.long 0x00 7. " [7] ,Error status flag 7 (L2ramw - uncorrectable error type B)" "No error,Error"
textline " "
eventfld.long 0x00 3. " [3] ,Error status flag 3 (Cortex-r5f core - all fatal bus error events)" "No error,Error"
eventfld.long 0x00 2. " [2] ,Error status flag 2 (Ccm-r5f - CPU compare error)" "No error,Error"
group.long 0x20++0x03
line.long 0x00 "SR3,Status Register 3"
eventfld.long 0x00 15. " ESF3[15] ,Error status flag 15 (L2ramw - address/control parity error)" "No error,Error"
eventfld.long 0x00 14. " [14] ,Error status flag 14 (L2ramw - uncorrectable error type A)" "No error,Error"
eventfld.long 0x00 13. " [13] ,Error status flag 13 (L2fmc - uncorrectable error)" "No error,Error"
eventfld.long 0x00 12. " [12] ,Error status flag 12 (Cpu interconnect subsystem - diagnostic error)" "No error,Error"
textline " "
eventfld.long 0x00 9. " [9] ,Error status flag 9 (Cortex-r5f core - all fatal events)" "No error,Error"
eventfld.long 0x00 3. " [3] ,Error status flag 3 (L2ramw - double bit ECC uncorrectable error)" "No error,Error"
eventfld.long 0x00 1. " [1] ,Error status flag 1 (Efuse farm - autoload error)" "No error,Error"
width 8.
textline " "
rgroup.long 0x24++0x03
line.long 0x00 "EPSR,Error Pin Status Register"
bitfld.long 0x00 0. " EPSF ,Error pin status flag" "Active,Not active"
sif cpu()=="RM57L843-ZWT"
rgroup.long 0x28++0x03
line.long 0x00 "IOFFHR,Interrupt Offset High Register"
hexmask.long.byte 0x00 0.--7. 1. " INTOFFH ,Offset high level interrupt"
rgroup.long 0x2C++0x03
line.long 0x00 "IOFFLR,Interrupt Offset Low Register"
hexmask.long.byte 0x00 0.--7. 1. " INTOFFL ,Offset low level interrupt"
else
rgroup.long 0x28++0x03
line.long 0x00 "IOFFHR,Interrupt Offset High Register"
hexmask.long.byte 0x00 0.--6. 1. " INTOFFH ,Offset high level interrupt"
rgroup.long 0x2C++0x03
line.long 0x00 "IOFFLR,Interrupt Offset Low Register"
hexmask.long.byte 0x00 0.--6. 1. " INTOFFL ,Offset low level interrupt"
endif
rgroup.long 0x30++0x03
line.long 0x00 "LTCR,Low-Time Counter Register"
hexmask.long.word 0x00 0.--15. 1. " LTC ,Error pin Low-Time counter"
group.long 0x34++0x03
line.long 0x00 "LTCPR,Low-Time Counter Preload Register"
bitfld.long 0x00 14.--15. " LTCP[15:14] ,Low-Time counter Pre-load value [15:14]" "0,1,2,3"
hexmask.long.word 0x00 0.--13. 1. " LTCP[13:0] ,Low-Time counter Pre-load value [13:0]"
group.long 0x38++0x03
line.long 0x00 "EKR,Error Key Register"
bitfld.long 0x00 0.--3. " EKEY ,Error key" "Normal,Normal,Normal,Normal,Normal,LTC,Normal,Normal,Normal,Normal,Forced,Normal,Normal,Normal,Normal,Normal"
width 8.
textline " "
group.long 0x3C++0x03
line.long 0x00 "SSR2,Status Shadow Register"
eventfld.long 0x00 30. " ESF[62] ,Error status flag 62 (Dcc2 - error)" "No error,Error"
eventfld.long 0x00 29. " [61] ,Error status flag 61 (Nmpu - PS_SCR_S MPU error)" "No error,Error"
eventfld.long 0x00 23. " [55] ,Error status flag 55 (Nmpu - EMAC MPU error)" "No error,Error"
eventfld.long 0x00 22. " [54] ,Error status flag 54 (Nhet1/2 - selftest error)" "No error,Error"
textline " "
eventfld.long 0x00 21. " [53] ,Error status flag 53 (Cpu interconnect subsystem - global parity error)" "No error,Error"
eventfld.long 0x00 20. " [52] ,Error status flag 52 (Cpu interconnect subsystem - global error)" "No error,Error"
eventfld.long 0x00 19. " [51] ,Error status flag 51 (Dcan4 - ECC uncorrectable error)" "No error,Error"
eventfld.long 0x00 18. " [50] ,Error status flag 50 (Mibspi4 - ECC uncorrectable error)" "No error,Error"
textline " "
eventfld.long 0x00 17. " [49] ,Error status flag 49 (Mibspi2 - ECC uncorrectable error)" "No error,Error"
eventfld.long 0x00 15. " [47] ,Error status flag 47 (Acp d-cache invalidate)" "No error,Error"
eventfld.long 0x00 14. " [46] ,Error status flag 46 (Cortex-r5f core - cache correctable error event)" "No error,Error"
eventfld.long 0x00 11. " [43] ,Error status flag 43 (Ethernet controller master interface)" "No error,Error"
textline " "
eventfld.long 0x00 10. " [42] ,Error status flag 42 (Pll2 - slip)" "No error,Error"
eventfld.long 0x00 9. " [41] ,Error status flag 41 (Efuse farm - self test error)" "No error,Error"
eventfld.long 0x00 8. " [40] ,Error status flag 40 (Efuse farm - EFC error)" "No error,Error"
eventfld.long 0x00 7. " [39] ,Error status flag 39 (Power domain self-test error)" "No error,Error"
textline " "
eventfld.long 0x00 6. " [38] ,Error status flag 38 (Power domain compare error)" "No error,Error"
eventfld.long 0x00 5. " [37] ,Error status flag 37 (Iomm - mux configuration error)" "No error,Error"
eventfld.long 0x00 2. " [34] ,Error status flag 34 (Nhet2 - parity)" "No error,Error"
group.long 0x40++0x03
line.long 0x00 "IEPSR4,Influence Error Pin Set/status Register 4"
setclrfld.long 0x00 30. 0x00 30. 0x04 30. " IEP_SET/CLR[62] ,Set/clear influence on error pin 62 (Dcc2 - error)" "No influence,Influence"
setclrfld.long 0x00 29. 0x00 29. 0x04 29. " [61] ,Set/clear influence on error pin 61 (Nmpu - PS_SCR_S MPU error)" "No influence,Influence"
setclrfld.long 0x00 23. 0x00 23. 0x04 23. " [55] ,Set/clear influence on error pin 55 (Nmpu - EMAC MPU error)" "No influence,Influence"
setclrfld.long 0x00 22. 0x00 22. 0x04 22. " [54] ,Set/clear influence on error pin 54 (Nhet1/2 - selftest error)" "No influence,Influence"
textline " "
setclrfld.long 0x00 21. 0x00 21. 0x04 21. " [53] ,Set/clear influence on error pin 53 (Cpu interconnect subsystem - global parity error)" "No influence,Influence"
setclrfld.long 0x00 20. 0x00 20. 0x04 20. " [52] ,Set/clear influence on error pin 52 (Cpu interconnect subsystem - global error)" "No influence,Influence"
setclrfld.long 0x00 19. 0x00 19. 0x04 19. " [51] ,Set/clear influence on error pin 51 (Dcan4 - ECC uncorrectable error)" "No influence,Influence"
setclrfld.long 0x00 18. 0x00 18. 0x04 18. " [50] ,Set/clear influence on error pin 50 (Mibspi4 - ECC uncorrectable error)" "No influence,Influence"
textline " "
setclrfld.long 0x00 17. 0x00 17. 0x04 17. " [49] ,Set/clear influence on error pin 49 (Mibspi2 - ECC uncorrectable error)" "No influence,Influence"
setclrfld.long 0x00 15. 0x00 15. 0x04 15. " [47] ,Set/clear influence on error pin 47 (Acp d-cache invalidate)" "No influence,Influence"
setclrfld.long 0x00 14. 0x00 14. 0x04 14. " [46] ,Set/clear influence on error pin 46 (Cortex-r5f core - cache correctable error event)" "No influence,Influence"
setclrfld.long 0x00 11. 0x00 11. 0x04 11. " [43] ,Set/clear influence on error pin 43 (Ethernet controller master interface)" "No influence,Influence"
textline " "
setclrfld.long 0x00 10. 0x00 10. 0x04 10. " [42] ,Set/clear influence on error pin 42 (Pll2 - slip)" "No influence,Influence"
setclrfld.long 0x00 9. 0x00 9. 0x04 9. " [41] ,Set/clear influence on error pin 41 (Efuse farm - self test error)" "No influence,Influence"
setclrfld.long 0x00 8. 0x00 8. 0x04 8. " [40] ,Set/clear influence on error pin 40 (Efuse farm - EFC error)" "No influence,Influence"
setclrfld.long 0x00 7. 0x00 7. 0x04 7. " [39] ,Set/clear influence on error pin 39 (Power domain self-test error)" "No influence,Influence"
textline " "
setclrfld.long 0x00 6. 0x00 6. 0x04 6. " [38] ,Set/clear influence on error pin 38 (Power domain compare error)" "No influence,Influence"
setclrfld.long 0x00 5. 0x00 5. 0x04 5. " [37] ,Set/clear influence on error pin 37 (Iomm - mux configuration error)" "No influence,Influence"
setclrfld.long 0x00 2. 0x00 2. 0x04 2. " [34] ,Set/clear influence on error pin 34 (Nhet2 - parity)" "No influence,Influence"
group.long 0x48++0x03
line.long 0x00 "IESR4,Interrupt Enable Set/status Register 4"
setclrfld.long 0x00 30. 0x00 30. 0x04 30. " INTEN_SET/CLR[62] ,Set/clear interrupt enable 62 (Dcc2 - error)" "Disabled,Enabled"
setclrfld.long 0x00 29. 0x00 29. 0x04 29. " [61] ,Set/clear interrupt enable 61 (Nmpu - PS_SCR_S MPU error)" "Disabled,Enabled"
setclrfld.long 0x00 23. 0x00 23. 0x04 23. " [55] ,Set/clear interrupt enable 55 (Nmpu - EMAC MPU error)" "Disabled,Enabled"
setclrfld.long 0x00 22. 0x00 22. 0x04 22. " [54] ,Set/clear interrupt enable 54 (Nhet1/2 - selftest error)" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 21. 0x00 21. 0x04 21. " [53] ,Set/clear interrupt enable 53 (Cpu interconnect subsystem - global parity error)" "Disabled,Enabled"
setclrfld.long 0x00 20. 0x00 20. 0x04 20. " [52] ,Set/clear interrupt enable 52 (Cpu interconnect subsystem - global error)" "Disabled,Enabled"
setclrfld.long 0x00 19. 0x00 19. 0x04 19. " [51] ,Set/clear interrupt enable 51 (Dcan4 - ECC uncorrectable error)" "Disabled,Enabled"
setclrfld.long 0x00 18. 0x00 18. 0x04 18. " [50] ,Set/clear interrupt enable 50 (Mibspi4 - ECC uncorrectable error)" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 17. 0x00 17. 0x04 17. " [49] ,Set/clear interrupt enable 49 (Mibspi2 - ECC uncorrectable error)" "Disabled,Enabled"
setclrfld.long 0x00 15. 0x00 15. 0x04 15. " [47] ,Set/clear interrupt enable 47 (Acp d-cache invalidate)" "Disabled,Enabled"
setclrfld.long 0x00 14. 0x00 14. 0x04 14. " [46] ,Set/clear interrupt enable 46 (Cortex-r5f core - cache correctable error event)" "Disabled,Enabled"
setclrfld.long 0x00 11. 0x00 11. 0x04 11. " [43] ,Set/clear interrupt enable 43 (Ethernet controller master interface)" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 10. 0x00 10. 0x04 10. " [42] ,Set/clear interrupt enable 42 (Pll2 - slip)" "Disabled,Enabled"
setclrfld.long 0x00 9. 0x00 9. 0x04 9. " [41] ,Set/clear interrupt enable 41 (Efuse farm - self test error)" "Disabled,Enabled"
setclrfld.long 0x00 8. 0x00 8. 0x04 8. " [40] ,Set/clear interrupt enable 40 (Efuse farm - EFC error)" "Disabled,Enabled"
setclrfld.long 0x00 7. 0x00 7. 0x04 7. " [39] ,Set/clear interrupt enable 39 (Power domain self-test error)" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 6. 0x00 6. 0x04 6. " [38] ,Set/clear interrupt enable 38 (Power domain compare error)" "Disabled,Enabled"
setclrfld.long 0x00 5. 0x00 5. 0x04 5. " [37] ,Set/clear interrupt enable 37 (Iomm - mux configuration error)" "Disabled,Enabled"
setclrfld.long 0x00 2. 0x00 2. 0x04 2. " [34] ,Set/clear interrupt enable 34 (Nhet2 - parity)" "Disabled,Enabled"
group.long 0x50++0x03
line.long 0x00 "ILSR4,Interrupt Level Set/status Register 4"
setclrfld.long 0x00 30. 0x00 30. 0x04 30. " INTLVL_SET/CLR[62] ,Set/clear interrupt level 62 (Dcc2 - error)" "Low,High"
setclrfld.long 0x00 29. 0x00 29. 0x04 29. " [61] ,Set/clear interrupt level 61 (Nmpu - PS_SCR_S MPU error)" "Low,High"
setclrfld.long 0x00 23. 0x00 23. 0x04 23. " [55] ,Set/clear interrupt level 55 (Nmpu - EMAC MPU error)" "Low,High"
setclrfld.long 0x00 22. 0x00 22. 0x04 22. " [54] ,Set/clear interrupt level 54 (Nhet1/2 - selftest error)" "Low,High"
textline " "
setclrfld.long 0x00 21. 0x00 21. 0x04 21. " [53] ,Set/clear interrupt level 53 (Cpu interconnect subsystem - global parity error)" "Low,High"
setclrfld.long 0x00 20. 0x00 20. 0x04 20. " [52] ,Set/clear interrupt level 52 (Cpu interconnect subsystem - global error)" "Low,High"
setclrfld.long 0x00 19. 0x00 19. 0x04 19. " [51] ,Set/clear interrupt level 51 (Dcan4 - ECC uncorrectable error)" "Low,High"
setclrfld.long 0x00 18. 0x00 18. 0x04 18. " [50] ,Set/clear interrupt level 50 (Mibspi4 - ECC uncorrectable error)" "Low,High"
textline " "
setclrfld.long 0x00 17. 0x00 17. 0x04 17. " [49] ,Set/clear interrupt level 49 (Mibspi2 - ECC uncorrectable error)" "Low,High"
setclrfld.long 0x00 15. 0x00 15. 0x04 15. " [47] ,Set/clear interrupt level 47 (Acp d-cache invalidate)" "Low,High"
setclrfld.long 0x00 14. 0x00 14. 0x04 14. " [46] ,Set/clear interrupt level 46 (Cortex-r5f core - cache correctable error event)" "Low,High"
setclrfld.long 0x00 11. 0x00 11. 0x04 11. " [43] ,Set/clear interrupt level 43 (Ethernet controller master interface)" "Low,High"
textline " "
setclrfld.long 0x00 10. 0x00 10. 0x04 10. " [42] ,Set/clear interrupt level 42 (Pll2 - slip)" "Low,High"
setclrfld.long 0x00 9. 0x00 9. 0x04 9. " [41] ,Set/clear interrupt level 41 (Efuse farm - self test error)" "Low,High"
setclrfld.long 0x00 8. 0x00 8. 0x04 8. " [40] ,Set/clear interrupt level 40 (Efuse farm - EFC error)" "Low,High"
setclrfld.long 0x00 7. 0x00 7. 0x04 7. " [39] ,Set/clear interrupt level 39 (Power domain self-test error)" "Low,High"
textline " "
setclrfld.long 0x00 6. 0x00 6. 0x04 6. " [38] ,Set/clear interrupt level 38 (Power domain compare error)" "Low,High"
setclrfld.long 0x00 5. 0x00 5. 0x04 5. " [37] ,Set/clear interrupt level 37 (Iomm - mux configuration error)" "Low,High"
setclrfld.long 0x00 2. 0x00 2. 0x04 2. " [34] ,Set/clear interrupt level 34 (Nhet2 - parity)" "Low,High"
group.long 0x58++0x03
line.long 0x00 "SR4,Status Register 4"
eventfld.long 0x00 30. " ESF[62] ,Error status flag 62 (Dcc2 - error)" "No error,Error"
eventfld.long 0x00 29. " [61] ,Error status flag 61 (Nmpu - PS_SCR_S MPU error)" "No error,Error"
eventfld.long 0x00 23. " [55] ,Error status flag 55 (Nmpu - EMAC MPU error)" "No error,Error"
eventfld.long 0x00 22. " [54] ,Error status flag 54 (Nhet1/2 - selftest error)" "No error,Error"
textline " "
eventfld.long 0x00 21. " [53] ,Error status flag 53 (Cpu interconnect subsystem - global parity error)" "No error,Error"
eventfld.long 0x00 20. " [52] ,Error status flag 52 (Cpu interconnect subsystem - global error)" "No error,Error"
eventfld.long 0x00 19. " [51] ,Error status flag 51 (Dcan4 - ECC uncorrectable error)" "No error,Error"
eventfld.long 0x00 18. " [50] ,Error status flag 50 (Mibspi4 - ECC uncorrectable error)" "No error,Error"
textline " "
eventfld.long 0x00 17. " [49] ,Error status flag 49 (Mibspi2 - ECC uncorrectable error)" "No error,Error"
eventfld.long 0x00 15. " [47] ,Error status flag 47 (Acp d-cache invalidate)" "No error,Error"
eventfld.long 0x00 14. " [46] ,Error status flag 46 (Cortex-r5f core - cache correctable error event)" "No error,Error"
eventfld.long 0x00 11. " [43] ,Error status flag 43 (Ethernet controller master interface)" "No error,Error"
textline " "
eventfld.long 0x00 10. " [42] ,Error status flag 42 (Pll2 - slip)" "No error,Error"
eventfld.long 0x00 9. " [41] ,Error status flag 41 (Efuse farm - self test error)" "No error,Error"
eventfld.long 0x00 8. " [40] ,Error status flag 40 (Efuse farm - EFC error)" "No error,Error"
eventfld.long 0x00 7. " [39] ,Error status flag 39 (Power domain self-test error)" "No error,Error"
textline " "
eventfld.long 0x00 6. " [38] ,Error status flag 38 (Power domain compare error)" "No error,Error"
eventfld.long 0x00 5. " [37] ,Error status flag 37 (Iomm - mux configuration error)" "No error,Error"
eventfld.long 0x00 2. " [34] ,Error status flag 34 (Nhet2 - parity)" "No error,Error"
group.long 0x80++0x03
line.long 0x00 "IEPSR7,Influence Error Pin Set/status Register 7"
setclrfld.long 0x00 28. 0x00 28. 0x04 28. " IEP_SET/CLR[92] ,Set/clear influence on error pin 92 (Ccm-r5f - operating status)" "No influence,Influence"
setclrfld.long 0x00 27. 0x00 27. 0x04 27. " [91] ,Set/clear influence on error pin 91 (Scm - timeout error)" "No influence,Influence"
setclrfld.long 0x00 26. 0x00 26. 0x04 26. " [90] ,Set/clear influence on error pin 90 (Sys - register soft error)" "No influence,Influence"
setclrfld.long 0x00 25. 0x00 25. 0x04 25. " [89] ,Set/clear influence on error pin 89 (L2fmc - register soft error)" "No influence,Influence"
textline " "
setclrfld.long 0x00 24. 0x00 24. 0x04 24. " [88] ,Set/clear influence on error pin 88 (Dma - register soft error)" "No influence,Influence"
setclrfld.long 0x00 22. 0x00 22. 0x04 22. " [86] ,Set/clear influence on error pin 86 (Imm error)" "No influence,Influence"
setclrfld.long 0x00 21. 0x00 21. 0x04 21. " [85] ,Set/clear influence on error pin 85 (Emif 64-bit bridge I/F ECC single bit error)" "No influence,Influence"
setclrfld.long 0x00 20. 0x00 20. 0x04 20. " [84] ,Set/clear influence on error pin 84 (Emif 64-bit bridge I/F ECC uncorrectable error)" "No influence,Influence"
textline " "
setclrfld.long 0x00 19. 0x00 19. 0x04 19. " [83] ,Set/clear influence on error pin 83 (Vim - ECC single bit error)" "No influence,Influence"
setclrfld.long 0x00 18. 0x00 18. 0x04 18. " [82] ,Set/clear influence on error pin 82 (Dma - ECC single bit error)" "No influence,Influence"
setclrfld.long 0x00 17. 0x00 17. 0x04 17. " [81] ,Set/clear influence on error pin 81 (Mibspi5 - ECC single bit error)" "No influence,Influence"
setclrfld.long 0x00 16. 0x00 16. 0x04 16. " [80] ,Set/clear influence on error pin 90 (Mibspi4 - ECC single bit error)" "No influence,Influence"
textline " "
setclrfld.long 0x00 15. 0x00 15. 0x04 15. " [79] ,Set/clear influence on error pin 79 (Mibspi3 - ECC single bit error)" "No influence,Influence"
setclrfld.long 0x00 14. 0x00 14. 0x04 14. " [78] ,Set/clear influence on error pin 78 (Mibspi2 - ECC single bit error)" "No influence,Influence"
setclrfld.long 0x00 13. 0x00 13. 0x04 13. " [77] ,Set/clear influence on error pin 77 (Mibspi1 - ECC single bit error)" "No influence,Influence"
setclrfld.long 0x00 12. 0x00 12. 0x04 12. " [76] ,Set/clear influence on error pin 76 (Dcan4 - ECC single bit error)" "No influence,Influence"
textline " "
setclrfld.long 0x00 11. 0x00 11. 0x04 11. " [75] ,Set/clear influence on error pin 75 (Dcan3 - ECC single bit error)" "No influence,Influence"
setclrfld.long 0x00 10. 0x00 10. 0x04 10. " [74] ,Set/clear influence on error pin 74 (Dcan2 - ECC single bit error)" "No influence,Influence"
setclrfld.long 0x00 9. 0x00 9. 0x04 9. " [73] ,Set/clear influence on error pin 73 (Dcan1 - ECC single bit error)" "No influence,Influence"
setclrfld.long 0x00 8. 0x00 8. 0x04 8. " [72] ,Set/clear influence on error pin 72 (Flexray - ECC single bit error)" "No influence,Influence"
textline " "
setclrfld.long 0x00 7. 0x00 7. 0x04 7. " [71] ,Set/clear influence on error pin 71 (Flexray TU RAM- ECC single bit error)" "No influence,Influence"
setclrfld.long 0x00 6. 0x00 6. 0x04 6. " [70] ,Set/clear influence on error pin 70 (Dma - transaction bus parity error)" "No influence,Influence"
setclrfld.long 0x00 5. 0x00 5. 0x04 5. " [69] ,Set/clear influence on error pin 69 (Nmpu - DMA port A MPU error)" "No influence,Influence"
group.long 0x88++0x03
line.long 0x00 "IESR7,Interrupt Enable Set/status Register 7"
setclrfld.long 0x00 28. 0x00 28. 0x04 28. " INTEN_SET/CLR[92] ,Set/clear interrupt enable 92 (Ccm-r5f - operating status)" "Disabled,Enabled"
setclrfld.long 0x00 27. 0x00 27. 0x04 27. " [91] ,Set/clear interrupt enable 91 (Scm - timeout error)" "Disabled,Enabled"
setclrfld.long 0x00 26. 0x00 26. 0x04 26. " [90] ,Set/clear interrupt enable 90 (Sys - register soft error)" "Disabled,Enabled"
setclrfld.long 0x00 25. 0x00 25. 0x04 25. " [89] ,Set/clear interrupt enable 89 (L2fmc - register soft error)" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 24. 0x00 24. 0x04 24. " [88] ,Set/clear interrupt enable 88 (Dma - register soft error)" "Disabled,Enabled"
setclrfld.long 0x00 22. 0x00 22. 0x04 22. " [86] ,Set/clear interrupt enable 86 (Imm error)" "Disabled,Enabled"
setclrfld.long 0x00 21. 0x00 21. 0x04 21. " [85] ,Set/clear interrupt enable 85 (Emif 64-bit bridge I/F ECC single bit error)" "Disabled,Enabled"
setclrfld.long 0x00 20. 0x00 20. 0x04 20. " [84] ,Set/clear interrupt enable 84 (Emif 64-bit bridge I/F ECC uncorrectable error)" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 19. 0x00 19. 0x04 19. " [83] ,Set/clear interrupt enable 83 (Vim - ECC single bit error)" "Disabled,Enabled"
setclrfld.long 0x00 18. 0x00 18. 0x04 18. " [82] ,Set/clear interrupt enable 82 (Dma - ECC single bit error)" "Disabled,Enabled"
setclrfld.long 0x00 17. 0x00 17. 0x04 17. " [81] ,Set/clear interrupt enable 81 (Mibspi5 - ECC single bit error)" "Disabled,Enabled"
setclrfld.long 0x00 16. 0x00 16. 0x04 16. " [80] ,Set/clear interrupt enable 90 (Mibspi4 - ECC single bit error)" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 15. 0x00 15. 0x04 15. " [79] ,Set/clear interrupt enable 79 (Mibspi3 - ECC single bit error)" "Disabled,Enabled"
setclrfld.long 0x00 14. 0x00 14. 0x04 14. " [78] ,Set/clear interrupt enable 78 (Mibspi2 - ECC single bit error)" "Disabled,Enabled"
setclrfld.long 0x00 13. 0x00 13. 0x04 13. " [77] ,Set/clear interrupt enable 77 (Mibspi1 - ECC single bit error)" "Disabled,Enabled"
setclrfld.long 0x00 12. 0x00 12. 0x04 12. " [76] ,Set/clear interrupt enable 76 (Dcan4 - ECC single bit error)" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 11. 0x00 11. 0x04 11. " [75] ,Set/clear interrupt enable 75 (Dcan3 - ECC single bit error)" "Disabled,Enabled"
setclrfld.long 0x00 10. 0x00 10. 0x04 10. " [74] ,Set/clear interrupt enable 74 (Dcan2 - ECC single bit error)" "Disabled,Enabled"
setclrfld.long 0x00 9. 0x00 9. 0x04 9. " [73] ,Set/clear interrupt enable 73 (Dcan1 - ECC single bit error)" "Disabled,Enabled"
setclrfld.long 0x00 8. 0x00 8. 0x04 8. " [72] ,Set/clear interrupt enable 72 (Flexray - ECC single bit error)" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 7. 0x00 7. 0x04 7. " [71] ,Set/clear interrupt enable 71 (Flexray TU RAM- ECC single bit error)" "Disabled,Enabled"
setclrfld.long 0x00 6. 0x00 6. 0x04 6. " [70] ,Set/clear interrupt enable 70 (Dma - transaction bus parity error)" "Disabled,Enabled"
setclrfld.long 0x00 5. 0x00 5. 0x04 5. " [69] ,Set/clear interrupt enable 69 (Nmpu - DMA port A MPU error)" "Disabled,Enabled"
group.long 0x90++0x03
line.long 0x00 "ILSR7,Interrupt Level Set/status Register 7"
setclrfld.long 0x00 28. 0x00 28. 0x04 28. " INTLVL_SET/CLR[92] ,Set/clear interrupt level 92 (Ccm-r5f - operating status)" "Low,High"
setclrfld.long 0x00 27. 0x00 27. 0x04 27. " [91] ,Set/clear interrupt level 91 (Scm - timeout error)" "Low,High"
setclrfld.long 0x00 26. 0x00 26. 0x04 26. " [90] ,Set/clear interrupt level 90 (Sys - register soft error)" "Low,High"
setclrfld.long 0x00 25. 0x00 25. 0x04 25. " [89] ,Set/clear interrupt level 89 (L2fmc - register soft error)" "Low,High"
textline " "
setclrfld.long 0x00 24. 0x00 24. 0x04 24. " [88] ,Set/clear interrupt level 88 (Dma - register soft error)" "Low,High"
setclrfld.long 0x00 22. 0x00 22. 0x04 22. " [86] ,Set/clear interrupt level 86 (Imm error)" "Low,High"
setclrfld.long 0x00 21. 0x00 21. 0x04 21. " [85] ,Set/clear interrupt level 85 (Emif 64-bit bridge I/F ECC single bit error)" "Low,High"
setclrfld.long 0x00 20. 0x00 20. 0x04 20. " [84] ,Set/clear interrupt level 84 (Emif 64-bit bridge I/F ECC uncorrectable error)" "Low,High"
textline " "
setclrfld.long 0x00 19. 0x00 19. 0x04 19. " [83] ,Set/clear interrupt level 83 (Vim - ECC single bit error)" "Low,High"
setclrfld.long 0x00 18. 0x00 18. 0x04 18. " [82] ,Set/clear interrupt level 82 (Dma - ECC single bit error)" "Low,High"
setclrfld.long 0x00 17. 0x00 17. 0x04 17. " [81] ,Set/clear interrupt level 81 (Mibspi5 - ECC single bit error)" "Low,High"
setclrfld.long 0x00 16. 0x00 16. 0x04 16. " [80] ,Set/clear interrupt level 90 (Mibspi4 - ECC single bit error)" "Low,High"
textline " "
setclrfld.long 0x00 15. 0x00 15. 0x04 15. " [79] ,Set/clear interrupt level 79 (Mibspi3 - ECC single bit error)" "Low,High"
setclrfld.long 0x00 14. 0x00 14. 0x04 14. " [78] ,Set/clear interrupt level 78 (Mibspi2 - ECC single bit error)" "Low,High"
setclrfld.long 0x00 13. 0x00 13. 0x04 13. " [77] ,Set/clear interrupt level 77 (Mibspi1 - ECC single bit error)" "Low,High"
setclrfld.long 0x00 12. 0x00 12. 0x04 12. " [76] ,Set/clear interrupt level 76 (Dcan4 - ECC single bit error)" "Low,High"
textline " "
setclrfld.long 0x00 11. 0x00 11. 0x04 11. " [75] ,Set/clear interrupt level 75 (Dcan3 - ECC single bit error)" "Low,High"
setclrfld.long 0x00 10. 0x00 10. 0x04 10. " [74] ,Set/clear interrupt level 74 (Dcan2 - ECC single bit error)" "Low,High"
setclrfld.long 0x00 9. 0x00 9. 0x04 9. " [73] ,Set/clear interrupt level 73 (Dcan1 - ECC single bit error)" "Low,High"
setclrfld.long 0x00 8. 0x00 8. 0x04 8. " [72] ,Set/clear interrupt level 72 (Flexray - ECC single bit error)" "Low,High"
textline " "
setclrfld.long 0x00 7. 0x00 7. 0x04 7. " [71] ,Set/clear interrupt level 71 (Flexray TU RAM- ECC single bit error)" "Low,High"
setclrfld.long 0x00 6. 0x00 6. 0x04 6. " [70] ,Set/clear interrupt level 70 (Dma - transaction bus parity error)" "Low,High"
setclrfld.long 0x00 5. 0x00 5. 0x04 5. " [69] ,Set/clear interrupt level 69 (Nmpu - DMA port A MPU error)" "Low,High"
group.long 0x98++0x03
line.long 0x00 "SR7,Status Register 7"
eventfld.long 0x00 28. " ESF[92] ,Error status flag 92 (Ccm-r5f - operating status)" "No error,Error"
eventfld.long 0x00 27. " [91] ,Error status flag 91 (Scm - timeout error)" "No error,Error"
eventfld.long 0x00 26. " [90] ,Error status flag 90 (Sys - register soft error)" "No error,Error"
eventfld.long 0x00 25. " [89] ,Error status flag 89 (L2fmc - register soft error)" "No error,Error"
textline " "
eventfld.long 0x00 24. " [88] ,Error status flag 88 (Dma - register soft error)" "No error,Error"
eventfld.long 0x00 22. " [86] ,Error status flag 86 (Imm error)" "No error,Error"
eventfld.long 0x00 21. " [85] ,Error status flag 85 (Emif 64-bit bridge I/F ECC single bit error)" "No error,Error"
eventfld.long 0x00 20. " [84] ,Error status flag 84 (Emif 64-bit bridge I/F ECC uncorrectable error)" "No error,Error"
textline " "
eventfld.long 0x00 19. " [83] ,Error status flag 83 (Vim - ECC single bit error)" "No error,Error"
eventfld.long 0x00 18. " [82] ,Error status flag 82 (Dma - ECC single bit error)" "No error,Error"
eventfld.long 0x00 17. " [81] ,Error status flag 81 (Mibspi5 - ECC single bit error)" "No error,Error"
eventfld.long 0x00 16. " [80] ,Error status flag 90 (Mibspi4 - ECC single bit error)" "No error,Error"
textline " "
eventfld.long 0x00 15. " [79] ,Error status flag 79 (Mibspi3 - ECC single bit error)" "No error,Error"
eventfld.long 0x00 14. " [78] ,Error status flag 78 (Mibspi2 - ECC single bit error)" "No error,Error"
eventfld.long 0x00 13. " [77] ,Error status flag 77 (Mibspi1 - ECC single bit error)" "No error,Error"
eventfld.long 0x00 12. " [76] ,Error status flag 76 (Dcan4 - ECC single bit error)" "No error,Error"
textline " "
eventfld.long 0x00 11. " [75] ,Error status flag 75 (Dcan3 - ECC single bit error)" "No error,Error"
eventfld.long 0x00 10. " [74] ,Error status flag 74 (Dcan2 - ECC single bit error)" "No error,Error"
eventfld.long 0x00 9. " [73] ,Error status flag 73 (Dcan1 - ECC single bit error)" "No error,Error"
eventfld.long 0x00 8. " [72] ,Error status flag 72 (Flexray - ECC single bit error)" "No error,Error"
textline " "
eventfld.long 0x00 7. " [71] ,Error status flag 71 (Flexray TU RAM- ECC single bit error)" "No error,Error"
eventfld.long 0x00 6. " [70] ,Error status flag 70 (Dma - transaction bus parity error)" "No error,Error"
eventfld.long 0x00 5. " [69] ,Error status flag 69 (Nmpu - DMA port A MPU error)" "No error,Error"
width 0x0B
tree.end
tree "RTI (Real-Time Interrupt)"
base ad:0xFFFFFC00
width 10.
group.long 0x00++0x3
line.long 0x0 "GCTRL,Global Control Register"
bitfld.long 0x0 16.--19. " NTUSEL ,Select NTU Signal" "NTU0,Reserved,Reserved,Reserved,Reserved,NTU1,Reserved,Reserved,Reserved,Reserved,NTU2,Reserved,Reserved,Reserved,Reserved,NTU3"
bitfld.long 0x0 15. " COS ,Continue on Suspend" "Stopped,Running"
bitfld.long 0x0 1. " CNT1EN ,Counter 1 Enable" "Stopped,Started"
textline " "
bitfld.long 0x0 0. " CNT0EN ,Counter 0 Enable" "Stoppped,Started"
group.long 0x04++0x3
line.long 0x0 "TBCTRL,Timebase Control Register"
bitfld.long 0x0 1. " INC ,Increment Free Running Counter" "Not incremented,Incremented"
bitfld.long 0x0 0. " TBEXT ,Time Base External" "UC0,NTUx"
group.long 0x08++0x3
line.long 0x0 "CAPCTRL,Capture Control Register"
bitfld.long 0x0 1. " CAPCNTR1 ,Capture Counter 1" "CES 0,CES 1"
bitfld.long 0x0 0. " CAPCNTR0 ,Capture Counter 0" "CES 0,CES 1"
group.long 0x0C++0x3
line.long 0x0 "COMPCTRL,Compare Control Register"
bitfld.long 0x0 12. " COMPSEL3 ,Compare Select 3" "FRC 0,FRC 1"
bitfld.long 0x0 8. " COMPSEL2 ,Compare Select 2" "FRC 0,FRC 1"
bitfld.long 0x0 4. " COMPSEL1 ,Compare Select 1" "FRC 0,FRC 1"
textline " "
bitfld.long 0x0 0. " COMPSEL0 ,Compare Select 0" "FRC0,FRC1"
group.long 0x10++0x3
line.long 0x0 "FRC0,Free Running Counter 0 Register"
group.long 0x14++0x3
line.long 0x0 "UC0,Up Counter 0 Register"
group.long 0x18++0x3
line.long 0x0 "CPUC0,Compare Up Counter 0 Register"
rgroup.long 0x20++0x3
line.long 0x0 "CAFRC0,Capture Free Running Counter 0 Register"
rgroup.long 0x24++0x3
line.long 0x0 "CAUC0,Capture Up Counter 0 Register"
group.long 0x30++0x3
line.long 0x0 "FRC1,Free Running Counter 1 Register"
group.long 0x34++0x3
line.long 0x0 "UC1,Up Counter 1 Register"
group.long 0x38++0x3
line.long 0x0 "CPUC1,Up Counter 1 Register"
rgroup.long 0x40++0x3
line.long 0x0 "CAFRC1,Capture Free Running Counter 1 Register"
rgroup.long 0x44++0x3
line.long 0x0 "CAUC1,Capture Up Counter 1 Register"
group.long 0x50++0x3
line.long 0x0 "COMP0,Compare 0 Register"
group.long 0x54++0x3
line.long 0x0 "UDCP0,Update Compare 0 Register"
group.long 0x58++0x3
line.long 0x0 "COMP1,Compare 1 Register"
group.long 0x5C++0x3
line.long 0x0 "UDCP1,Update Compare 1 Register"
group.long 0x60++0x3
line.long 0x0 "COMP2,Compare 2 Register"
group.long 0x64++0x3
line.long 0x0 "UDCP2,Update Compare 2 Register"
group.long 0x68++0x3
line.long 0x0 "COMP3,Compare 3 Register"
group.long 0x6C++0x3
line.long 0x0 "UDCP3,Update Compare 3 Register"
group.long 0x70++0x3
line.long 0x0 "TBLCOMP,External Clock Timebase Low Compare Register"
group.long 0x74++0x3
line.long 0x0 "TBHCOMP,External Clock Timebase High Compare Register"
width 10.
group.long 0x80++0x3
line.long 0x0 "SETINT,Set/Status Interrupt Register"
setclrfld.long 0x00 18. 0x00 18. 0x04 18. " SETOVL1INT_set/clr ,Free Running Counter 1 Overflow Interrupt" "Disabled,Enabled"
setclrfld.long 0x00 17. 0x00 17. 0x04 17. " SETOVL0INT_set/clr ,Free Running Counter 0 Overflow Interrupt" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 16. 0x00 16. 0x04 16. " SETTBINT_set/clr ,Timebase Interrupt" "Disabled,Enabled"
setclrfld.long 0x00 11. 0x00 11. 0x04 11. " SETDMA3_set/clr ,Compare DMA Request 3" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 10. 0x00 10. 0x04 10. " SETDMA2_set/clr ,Compare DMA Request 2" "Disabled,Enabled"
setclrfld.long 0x00 9. 0x00 9. 0x04 9. " SETDMA1_set/clr ,Compare DMA Request 1" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 8. 0x00 8. 0x04 8. " SETDMA0_set/clr ,Compare DMA Request 0" "Disabled,Enabled"
setclrfld.long 0x00 3. 0x00 3. 0x04 3. " SETINT3_set/clr ,Compare Interrupt 3" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 2. 0x00 2. 0x04 2. " SETINT2_set/clr ,Compare Interrupt 2" "Disabled,Enabled"
setclrfld.long 0x00 1. 0x00 1. 0x04 1. " SETINT1_set/clr ,Compare Interrupt 1" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 0. 0x00 0. 0x04 0. " SETINT0_set/clr ,Compare Interrupt 0" "Disabled,Enabled"
width 10.
group.long 0x88++0x3
line.long 0x0 "INTFLAG,Interrupt Flag Register"
eventfld.long 0x00 18. " OVL1INT ,Free Running Counter 1 Overflow Interrupt Flag" "No interrupt,Interrupt"
eventfld.long 0x00 17. " OVL0INT ,Free Running Counter 0 Overflow Interrupt Flag" "No interrupt,Interrupt"
eventfld.long 0x00 16. " TBINT ,Timebase Interrupt Flag" "No interrupt,Interrupt"
textline " "
eventfld.long 0x00 3. " INT3 ,Interrupt Flag 3" "No interrupt,Interrupt"
eventfld.long 0x00 2. " INT2 ,Interrupt Flag 2" "No interrupt,Interrupt"
eventfld.long 0x00 1. " INT1 ,Interrupt Flag 1" "No interrupt,Interrupt"
textline " "
eventfld.long 0x00 0. " INT0 ,Interrupt Flag 0" "No interrupt,Interrupt"
group.long 0x90++0x3
line.long 0x0 "DWDCTRL,Digital Watchdog Control Register"
group.long 0x94++0x3
line.long 0x0 "DWDPRLD,Digital Watchdog Preload Register"
hexmask.long.word 0x00 0.--11. 1. " DWDPRLD ,Digital Watchdog Preload Value"
group.long 0x98++0x3
line.long 0x0 "WDSTATUS,Watchdog Status Register"
eventfld.long 0x00 5. " DWWD_ST ,Windowed Watchdog Status" "No reset,Reset"
eventfld.long 0x00 4. " END_TIME_VIOL ,Windowed Watchdog End Time Violation Status" "No reset,Reset"
eventfld.long 0x00 3. " START_TIME_VIOL ,Windowed Watchdog Start Time Violation Status" "No reset,Reset"
textline " "
eventfld.long 0x00 2. " KEYST ,Watchdog Key Status" "No reset,Reset"
eventfld.long 0x00 1. " DWDST ,Digital Watchdog Status" "No reset,Reset"
group.long 0x9C++0x3
line.long 0x0 "WDKEY,Watchdog Key Register"
hexmask.long.word 0x00 0.--15. 1. " WDKEY ,Watchdog Key"
rgroup.long 0xA0++0x3
line.long 0x0 "WDCNTR,Digital Watchdog Down Counter"
hexmask.long 0x00 0.--24. 1. " DWDCNTR ,Digital Watchdog Down Counter"
width 13.
group.long 0xA4++0x7
line.long 0x0 "WWDRXNCTRL,Digital Windowed Watchdog Reaction Control"
bitfld.long 0x00 0.--3. " DWDST ,The DWWD reaction" "Reset,Reset,Reset,Reset,Reset,Reset,Reset,Reset,Reset,Reset,Interrupt,Reset,Reset,Reset,Reset,Reset"
line.long 0x04 "WWDSIZECTRL,Digital Windowed Watchdog Window Size Control"
width 0xb
tree.end
tree.open "CRC (Cyclic Redundancy Check Controller Module)"
tree "CRC1"
base ad:0xFE000000
width 20.
group.long 0x00++0x03
line.long 0x00 "CRC_CTRL0,CRC Global Control Register 0"
bitfld.long 0x00 8. " CH2_PSA_SWREST ,Channel 2 PSA software reset" "No reset,Reset"
bitfld.long 0x00 0. " CH1_PSA_SWREST ,Channel 1 PSA software reset" "No reset,Reset"
group.long 0x08++0x03
line.long 0x00 "CRC_CTRL1,CRC Global Control Register 1"
bitfld.long 0x00 0. " PWDN ,Power down" "Not powered down,Powered down"
group.long 0x10++0x03
line.long 0x00 "CRC_CTRL2,CRC Global Control Register 2"
bitfld.long 0x00 8.--9. " CH2_MODE ,Channel 2 mode" "Data capture,Auto,,Full-cpu"
bitfld.long 0x00 0.--1. " CH1_MODE ,Channel 1 mode" "Data capture,Auto,,Full-cpu"
group.long 0x18++0x03
line.long 0x00 "CRC_INTS,Write One To A Bit To Enable A Interrupt"
bitfld.long 0x00 12. " CH2_TIMEOUTENS ,Channel 2 timeout interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 11. " CH2_UNDERENS ,Channel 2 underrun interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 10. " CH2_OVERENS ,Channel 2 overrun interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 9. " CH2_CRCFAILENS ,Channel 2 CRC fail interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 8. " CH2_CCITEN ,Channel 2 compression complete interrupt enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 4. " CH1_TIMEOUTENS ,Channel 1 timeout interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 3. " CH1_UNDERENS ,Channel 1 underrun interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 2. " CH1_OVERENS ,Channel 1 overrun interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 1. " CH1_CRCFAILENS ,Channel 1 CRC fail interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 0. " CH1_CCITEN ,Channel 1 compression complete interrupt enable" "Disabled,Enabled"
group.long 0x20++0x03
line.long 0x00 "CRC_INTR,Write One To A Bit To Disable A Interrupt"
bitfld.long 0x00 12. " CH2_TIMEOUTENR ,Channel 2 timeout interrupt disable" "No,Yes"
bitfld.long 0x00 11. " CH2_UNDERENR ,Channel 2 underrun interrupt disable" "No,Yes"
bitfld.long 0x00 10. " CH2_OVERENR ,Channel 2 overrun interrupt disable" "No,Yes"
bitfld.long 0x00 9. " CH2_CRCFAILENR ,Channel 2 CRC fail interrupt disable" "No,Yes"
bitfld.long 0x00 8. " CH2_CCITEN ,Channel 2 compression complete interrupt disable" "No,Yes"
textline " "
bitfld.long 0x00 4. " CH1_TIMEOUTENR ,Channel 1 timeout interrupt disable" "No,Yes"
bitfld.long 0x00 3. " CH1_UNDERENR ,Channel 1 underrun interrupt disable" "No,Yes"
bitfld.long 0x00 2. " CH1_OVERENR ,Channel 1 overrun interrupt disable" "No,Yes"
bitfld.long 0x00 1. " CH1_CRCFAILENR ,Channel 1 CRC fail interrupt disable" "No,Yes"
bitfld.long 0x00 0. " CH1_CCITEN ,Channel 1 compression complete interrupt disable" "No,Yes"
group.long 0x28++0x03
line.long 0x00 "CRC_STATUS,CRC Interrupt Status Register"
eventfld.long 0x00 12. " CH2_TIMEOUT ,Channel 2 CRC timeout status flag" "No interrupt,Interrupt"
eventfld.long 0x00 11. " CH2_UNDER ,Channel 2 CRC underrun status flag" "No interrupt,Interrupt"
eventfld.long 0x00 10. " CH2_OVER ,Channel 2 CRC overrun status flag" "No interrupt,Interrupt"
eventfld.long 0x00 9. " CH2_CRCFAIL ,Channel 2 CRC compare fail status flag" "No interrupt,Interrupt"
eventfld.long 0x00 8. " CH2_CCIT ,Channel 2 CRC pattern compression complete status flag" "No interrupt,Interrupt"
textline " "
eventfld.long 0x00 4. " CH1_TIMEOUT ,Channel 1 CRC timeout status flag" "No interrupt,Interrupt"
eventfld.long 0x00 3. " CH1_UNDER ,Channel 1 CRC underrun status flag" "No interrupt,Interrupt"
eventfld.long 0x00 2. " CH1_OVER ,Channel 1 CRC overrun status flag" "No interrupt,Interrupt"
eventfld.long 0x00 1. " CH1_CRCFAIL ,Channel 1 CRC compare fail status flag" "No interrupt,Interrupt"
eventfld.long 0x00 0. " CH1_CCIT ,Channel 1 CRC pattern compression complete status flag" "No interrupt,Interrupt"
rgroup.long 0x30++0x03
line.long 0x00 "CRC_INT_OFFSET_REG,CRC Interrupt Offset Register"
hexmask.long.byte 0x00 0.--7. 1. " OFSTREG ,CRC interrupt offset"
rgroup.long 0x38++0x03
line.long 0x00 "CRC_BUSY,CRC Busy Register"
bitfld.long 0x00 8. " CH2_BUSY ,Channel 2 busy flag" "Not busy,Busy"
bitfld.long 0x00 0. " CH1_BUSY ,Channel 1 busy flag" "Not busy,Busy"
width 17.
tree "CRC Channel 1 Registers"
group.long 0x40++0x03
line.long 0x00 "CRC_PCOUNT_REG1,CRC Pattern Counter Preload Register 1"
hexmask.long.tbyte 0x00 0.--19. 1. " CRC_PAT_COUNT1[19:0] ,Channel 1 pattern counter preload"
group.long 0x44++0x03
line.long 0x00 "CRC_SCOUNT_REG1,CRC Sector Counter Preload Register 1"
hexmask.long.word 0x00 0.--15. 1. " CRC_SEC_COUNT1[15:0] ,Channel 1 sector counter preload"
hgroup.long 0x48++0x03
hide.long 0x00 "CRC_CURSEC_REG1,CRC Current Sector Register 1"
in
group.long 0x4C++0x03
line.long 0x00 "CRC_WDTOPLD1,Watchdog Timeout Preload Register"
hexmask.long.tbyte 0x00 0.--23. 1. " CRC_WDTOPLD1[23:0] ,Channel 1 watchdog timeout counter preload"
group.long 0x50++0x03
line.long 0x00 "CRC_BCTOPLD1,CRC Channel 1 Block Complete Timeout Preload Register"
hexmask.long.tbyte 0x00 0.--23. 1. " CRC_BCTOPLD1[23:0] ,Channel 1 block complete timeout counter preload"
group.long 0x60++0x03
line.long 0x00 "PSA_SIGREGL1,Channel 1 PSA Signature Low Register"
group.long 0x64++0x03
line.long 0x00 "PSA_SIGREGH1,Channel 1 PSA Signature High Register"
group.long 0x68++0x03
line.long 0x00 "CRC_REGL1,Channel 1 CRC Value Low Register"
group.long 0x6C++0x03
line.long 0x00 "CRC_REGH1,Channel 1 CRC Value High Register"
rgroup.long 0x70++0x03
line.long 0x00 "PSA_SECSIGREGL1,PSA Sector Signature Low Register 1"
rgroup.long 0x74++0x03
line.long 0x00 "PSA_SECSIGREGH1,PSA Sector Signature High Register 1"
rgroup.long 0x78++0x03
line.long 0x00 "RAW_DATAREGL1,Raw Data Low Register 1"
rgroup.long 0x7C++0x03
line.long 0x00 "RAW_DATAREGH1,Raw Data High Register 1"
tree.end
width 17.
tree "CRC Channel 2 Registers"
group.long 0x80++0x03
line.long 0x00 "CRC_PCOUNT_REG2,CRC Pattern Counter Preload Register 2"
hexmask.long.tbyte 0x00 0.--19. 1. " CRC_PAT_COUNT2[19:0] ,Channel 2 pattern counter preload"
group.long 0x84++0x03
line.long 0x00 "CRC_SCOUNT_REG2,CRC Sector Counter Preload Register 2"
hexmask.long.word 0x00 0.--15. 1. " CRC_SEC_COUNT2[15:0] ,Channel 2 sector counter preload"
hgroup.long 0x88++0x03
hide.long 0x00 "CRC_CURSEC_REG2,CRC Current Sector Register 2"
in
group.long 0x8C++0x03
line.long 0x00 "CRC_WDTOPLD2,Watchdog Timeout Preload Register"
hexmask.long.tbyte 0x00 0.--23. 1. " CRC_WDTOPLD2[23:0] ,Channel 2 watchdog timeout counter preload"
group.long 0x90++0x03
line.long 0x00 "CRC_BCTOPLD2,CRC Channel 2 Block Complete Timeout Preload Register"
hexmask.long.tbyte 0x00 0.--23. 1. " CRC_BCTOPLD2[23:0] ,Channel 2 block complete timeout counter preload"
group.long 0xA0++0x03
line.long 0x00 "PSA_SIGREGL2,Channel 2 PSA Signature Low Register"
group.long 0xA4++0x03
line.long 0x00 "PSA_SIGREGH2,Channel 2 PSA Signature High Register"
group.long 0xA8++0x03
line.long 0x00 "CRC_REGL2,Channel 2 CRC Value Low Register"
group.long 0xAC++0x03
line.long 0x00 "CRC_REGH2,Channel 2 CRC Value High Register"
rgroup.long 0xB0++0x03
line.long 0x00 "PSA_SECSIGREGL2,PSA Sector Signature Low Register 2"
rgroup.long 0xB4++0x03
line.long 0x00 "PSA_SECSIGREGH2,PSA Sector Signature High Register 2"
rgroup.long 0xB8++0x03
line.long 0x00 "RAW_DATAREGL2,Raw Data Low Register 2"
rgroup.long 0xBC++0x03
line.long 0x00 "RAW_DATAREGH2,Raw Data High Register 2"
tree.end
width 0x0B
tree.end
tree "CRC2"
base ad:0xFB000000
width 20.
group.long 0x00++0x03
line.long 0x00 "CRC_CTRL0,CRC Global Control Register 0"
bitfld.long 0x00 8. " CH2_PSA_SWREST ,Channel 2 PSA software reset" "No reset,Reset"
bitfld.long 0x00 0. " CH1_PSA_SWREST ,Channel 1 PSA software reset" "No reset,Reset"
group.long 0x08++0x03
line.long 0x00 "CRC_CTRL1,CRC Global Control Register 1"
bitfld.long 0x00 0. " PWDN ,Power down" "Not powered down,Powered down"
group.long 0x10++0x03
line.long 0x00 "CRC_CTRL2,CRC Global Control Register 2"
bitfld.long 0x00 8.--9. " CH2_MODE ,Channel 2 mode" "Data capture,Auto,,Full-cpu"
bitfld.long 0x00 0.--1. " CH1_MODE ,Channel 1 mode" "Data capture,Auto,,Full-cpu"
group.long 0x18++0x03
line.long 0x00 "CRC_INTS,Write One To A Bit To Enable A Interrupt"
bitfld.long 0x00 12. " CH2_TIMEOUTENS ,Channel 2 timeout interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 11. " CH2_UNDERENS ,Channel 2 underrun interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 10. " CH2_OVERENS ,Channel 2 overrun interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 9. " CH2_CRCFAILENS ,Channel 2 CRC fail interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 8. " CH2_CCITEN ,Channel 2 compression complete interrupt enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 4. " CH1_TIMEOUTENS ,Channel 1 timeout interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 3. " CH1_UNDERENS ,Channel 1 underrun interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 2. " CH1_OVERENS ,Channel 1 overrun interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 1. " CH1_CRCFAILENS ,Channel 1 CRC fail interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 0. " CH1_CCITEN ,Channel 1 compression complete interrupt enable" "Disabled,Enabled"
group.long 0x20++0x03
line.long 0x00 "CRC_INTR,Write One To A Bit To Disable A Interrupt"
bitfld.long 0x00 12. " CH2_TIMEOUTENR ,Channel 2 timeout interrupt disable" "No,Yes"
bitfld.long 0x00 11. " CH2_UNDERENR ,Channel 2 underrun interrupt disable" "No,Yes"
bitfld.long 0x00 10. " CH2_OVERENR ,Channel 2 overrun interrupt disable" "No,Yes"
bitfld.long 0x00 9. " CH2_CRCFAILENR ,Channel 2 CRC fail interrupt disable" "No,Yes"
bitfld.long 0x00 8. " CH2_CCITEN ,Channel 2 compression complete interrupt disable" "No,Yes"
textline " "
bitfld.long 0x00 4. " CH1_TIMEOUTENR ,Channel 1 timeout interrupt disable" "No,Yes"
bitfld.long 0x00 3. " CH1_UNDERENR ,Channel 1 underrun interrupt disable" "No,Yes"
bitfld.long 0x00 2. " CH1_OVERENR ,Channel 1 overrun interrupt disable" "No,Yes"
bitfld.long 0x00 1. " CH1_CRCFAILENR ,Channel 1 CRC fail interrupt disable" "No,Yes"
bitfld.long 0x00 0. " CH1_CCITEN ,Channel 1 compression complete interrupt disable" "No,Yes"
group.long 0x28++0x03
line.long 0x00 "CRC_STATUS,CRC Interrupt Status Register"
eventfld.long 0x00 12. " CH2_TIMEOUT ,Channel 2 CRC timeout status flag" "No interrupt,Interrupt"
eventfld.long 0x00 11. " CH2_UNDER ,Channel 2 CRC underrun status flag" "No interrupt,Interrupt"
eventfld.long 0x00 10. " CH2_OVER ,Channel 2 CRC overrun status flag" "No interrupt,Interrupt"
eventfld.long 0x00 9. " CH2_CRCFAIL ,Channel 2 CRC compare fail status flag" "No interrupt,Interrupt"
eventfld.long 0x00 8. " CH2_CCIT ,Channel 2 CRC pattern compression complete status flag" "No interrupt,Interrupt"
textline " "
eventfld.long 0x00 4. " CH1_TIMEOUT ,Channel 1 CRC timeout status flag" "No interrupt,Interrupt"
eventfld.long 0x00 3. " CH1_UNDER ,Channel 1 CRC underrun status flag" "No interrupt,Interrupt"
eventfld.long 0x00 2. " CH1_OVER ,Channel 1 CRC overrun status flag" "No interrupt,Interrupt"
eventfld.long 0x00 1. " CH1_CRCFAIL ,Channel 1 CRC compare fail status flag" "No interrupt,Interrupt"
eventfld.long 0x00 0. " CH1_CCIT ,Channel 1 CRC pattern compression complete status flag" "No interrupt,Interrupt"
rgroup.long 0x30++0x03
line.long 0x00 "CRC_INT_OFFSET_REG,CRC Interrupt Offset Register"
hexmask.long.byte 0x00 0.--7. 1. " OFSTREG ,CRC interrupt offset"
rgroup.long 0x38++0x03
line.long 0x00 "CRC_BUSY,CRC Busy Register"
bitfld.long 0x00 8. " CH2_BUSY ,Channel 2 busy flag" "Not busy,Busy"
bitfld.long 0x00 0. " CH1_BUSY ,Channel 1 busy flag" "Not busy,Busy"
width 17.
tree "CRC Channel 1 Registers"
group.long 0x40++0x03
line.long 0x00 "CRC_PCOUNT_REG1,CRC Pattern Counter Preload Register 1"
hexmask.long.tbyte 0x00 0.--19. 1. " CRC_PAT_COUNT1[19:0] ,Channel 1 pattern counter preload"
group.long 0x44++0x03
line.long 0x00 "CRC_SCOUNT_REG1,CRC Sector Counter Preload Register 1"
hexmask.long.word 0x00 0.--15. 1. " CRC_SEC_COUNT1[15:0] ,Channel 1 sector counter preload"
hgroup.long 0x48++0x03
hide.long 0x00 "CRC_CURSEC_REG1,CRC Current Sector Register 1"
in
group.long 0x4C++0x03
line.long 0x00 "CRC_WDTOPLD1,Watchdog Timeout Preload Register"
hexmask.long.tbyte 0x00 0.--23. 1. " CRC_WDTOPLD1[23:0] ,Channel 1 watchdog timeout counter preload"
group.long 0x50++0x03
line.long 0x00 "CRC_BCTOPLD1,CRC Channel 1 Block Complete Timeout Preload Register"
hexmask.long.tbyte 0x00 0.--23. 1. " CRC_BCTOPLD1[23:0] ,Channel 1 block complete timeout counter preload"
group.long 0x60++0x03
line.long 0x00 "PSA_SIGREGL1,Channel 1 PSA Signature Low Register"
group.long 0x64++0x03
line.long 0x00 "PSA_SIGREGH1,Channel 1 PSA Signature High Register"
group.long 0x68++0x03
line.long 0x00 "CRC_REGL1,Channel 1 CRC Value Low Register"
group.long 0x6C++0x03
line.long 0x00 "CRC_REGH1,Channel 1 CRC Value High Register"
rgroup.long 0x70++0x03
line.long 0x00 "PSA_SECSIGREGL1,PSA Sector Signature Low Register 1"
rgroup.long 0x74++0x03
line.long 0x00 "PSA_SECSIGREGH1,PSA Sector Signature High Register 1"
rgroup.long 0x78++0x03
line.long 0x00 "RAW_DATAREGL1,Raw Data Low Register 1"
rgroup.long 0x7C++0x03
line.long 0x00 "RAW_DATAREGH1,Raw Data High Register 1"
tree.end
width 17.
tree "CRC Channel 2 Registers"
group.long 0x80++0x03
line.long 0x00 "CRC_PCOUNT_REG2,CRC Pattern Counter Preload Register 2"
hexmask.long.tbyte 0x00 0.--19. 1. " CRC_PAT_COUNT2[19:0] ,Channel 2 pattern counter preload"
group.long 0x84++0x03
line.long 0x00 "CRC_SCOUNT_REG2,CRC Sector Counter Preload Register 2"
hexmask.long.word 0x00 0.--15. 1. " CRC_SEC_COUNT2[15:0] ,Channel 2 sector counter preload"
hgroup.long 0x88++0x03
hide.long 0x00 "CRC_CURSEC_REG2,CRC Current Sector Register 2"
in
group.long 0x8C++0x03
line.long 0x00 "CRC_WDTOPLD2,Watchdog Timeout Preload Register"
hexmask.long.tbyte 0x00 0.--23. 1. " CRC_WDTOPLD2[23:0] ,Channel 2 watchdog timeout counter preload"
group.long 0x90++0x03
line.long 0x00 "CRC_BCTOPLD2,CRC Channel 2 Block Complete Timeout Preload Register"
hexmask.long.tbyte 0x00 0.--23. 1. " CRC_BCTOPLD2[23:0] ,Channel 2 block complete timeout counter preload"
group.long 0xA0++0x03
line.long 0x00 "PSA_SIGREGL2,Channel 2 PSA Signature Low Register"
group.long 0xA4++0x03
line.long 0x00 "PSA_SIGREGH2,Channel 2 PSA Signature High Register"
group.long 0xA8++0x03
line.long 0x00 "CRC_REGL2,Channel 2 CRC Value Low Register"
group.long 0xAC++0x03
line.long 0x00 "CRC_REGH2,Channel 2 CRC Value High Register"
rgroup.long 0xB0++0x03
line.long 0x00 "PSA_SECSIGREGL2,PSA Sector Signature Low Register 2"
rgroup.long 0xB4++0x03
line.long 0x00 "PSA_SECSIGREGH2,PSA Sector Signature High Register 2"
rgroup.long 0xB8++0x03
line.long 0x00 "RAW_DATAREGL2,Raw Data Low Register 2"
rgroup.long 0xBC++0x03
line.long 0x00 "RAW_DATAREGH2,Raw Data High Register 2"
tree.end
width 0x0B
tree.end
tree.end
tree "VIM (Vectored Interrupt Manager Module)"
base ad:0xFFFFFD00
width 11.
base ad:0xFFFFFDEC
tree "ECC-Related VIM Registers"
group.long 0x00++0x07
line.long 0x00 "ECCSTAT,Interrupt Vector Table ECC Status register"
eventfld.long 0x00 8. " SBERR ,Single Bit Error Has Been Detected" "No error,Error"
eventfld.long 0x00 0. " UERR ,Double Bit Error Has Been Detected" "No error,Error"
line.long 0x04 "ECCCTL,Interrupt Vector Table ECC control register"
bitfld.long 0x04 24.--27. " SBE_EVT_EN ,Generation of Error Signal" "Ignored,Ignored,Ignored,Ignored,Ignored,Disabled,Ignored,Ignored,Ignored,Ignored,Enabled,Ignored,Ignored,Ignored,Ignored,Ignored"
bitfld.long 0x04 16.--19. " EDAC_MODE ,Correction of SBE" "Ignored,Ignored,Ignored,Ignored,Ignored,Disabled,Ignored,Ignored,Ignored,Ignored,Enabled,Ignored,Ignored,Ignored,Ignored,Ignored"
textline " "
bitfld.long 0x04 8.--11. " TEST_DIAG_EN ,ECC maping into IVT" "Disabled,Disabled,Disabled,Disabled,Disabled,Enabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled"
bitfld.long 0x04 0.--3. " ECCENA ,VIM ECC Enable" "Enabled,Enabled,Enabled,Enabled,Enabled,Disabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled"
rgroup.long 0x08++0x03
line.long 0x00 "UERRADDR,Uncorrectable Error Address Register"
hexmask.long.tbyte 0x00 10.--31. 1. " INTERRUPT_VECTOR_TABLE_OFFSET ,Interrupt Vector Table Offset"
hexmask.long.word 0x00 2.--9. 0x04 " ADDERR ,Uncorrectable Error Address Register"
textline " "
bitfld.long 0x00 0.--1. " WORD_OFFSET ,Word offset (R/W)" "0/0,0/0,0/0,0/0"
group.long 0x0C++0x07
line.long 0x00 "FBVECADDR,Fallback Vector Address Register"
line.long 0x04 "SBERRADDR,Single Bit Error Address Register"
tree.end
base ad:0xFFFFFE00
width 9.
tree "VIM Offset Vector Registers"
rgroup.long 0x00++0x7
line.long 0x0 "IRQINDEX,IRQ Index Offset Vector Register"
hexmask.long.byte 0x00 0.--7. 1. " IRQINDEX ,IRQ index vector"
line.long 0x4 "FIQINDEX,FIQ Index Offset Vector Register"
hexmask.long.byte 0x04 0.--7. 1. " FIQINDEX ,FIQ index offset vector"
tree.end
textline " "
group.long 0x10++0xF
line.long 0x0 "FIRQPR0,Program Control Register"
bitfld.long 0x00 31. " FIRQPR_[31] ,FIQ/IRQ Program Control 31 (MIBADC1 magnitude compare interrupt)" "IRQ,FIQ"
bitfld.long 0x00 30. " [30] ,FIQ/IRQ Program Control (30 MIBSPI2 level 1 interrupt)" "IRQ,FIQ"
bitfld.long 0x00 29. " [29] ,FIQ/IRQ Program Control 29 (DCAN1 level 1 interrupt)" "IRQ,FIQ"
bitfld.long 0x00 28. " [28] ,FIQ/IRQ Program Control 28 (MIBADC1 sw group 2 interrupt)" "IRQ,FIQ"
textline " "
bitfld.long 0x00 27. " [27] ,FIQ/IRQ Program Control 27 (LIN1 level 1 interrupt)" "IRQ,FIQ"
bitfld.long 0x00 26. " [26] ,FIQ/IRQ Program Control 26 (MIBSPI1 level 1 interrupt)" "IRQ,FIQ"
bitfld.long 0x00 25. " [25] ,FIQ/IRQ Program Control 25 (HET TU1 level 1 interrupt)" "IRQ,FIQ"
bitfld.long 0x00 24. " [24] ,FIQ/IRQ Program Control 24 (NHET1 level 1 interrupt)" "IRQ,FIQ"
textline " "
bitfld.long 0x00 23. " [23] ,FIQ/IRQ Program Control 23 (GIO interrupt B)" "IRQ,FIQ"
bitfld.long 0x00 22. " [22] ,FIQ/IRQ Program Control 22 (Cortex-R5F PMU Interrupt)" "IRQ,FIQ"
bitfld.long 0x00 21. " [21] ,FIQ/IRQ Program Control 21 (Software interrupt for Cortex-R5F)" "IRQ,FIQ"
bitfld.long 0x00 20. " [20] ,FIQ/IRQ Program Control 20 (ESM Low level interrupt)" "IRQ,FIQ"
textline " "
bitfld.long 0x00 19. " [19] ,FIQ/IRQ Program Control 19 (CRC1 Interrupt)" "IRQ,FIQ"
bitfld.long 0x00 18. " [18] ,FIQ/IRQ Program Control 18 (Flexray level 0 interrupt)" "IRQ,FIQ"
bitfld.long 0x00 17. " [17] ,FIQ/IRQ Program Control 17 (MIBSPI2 level 0 interrupt)" "IRQ,FIQ"
bitfld.long 0x00 16. " [16] ,FIQ/IRQ Program Control 16 (DCAN1 level 0 interrupt)" "IRQ,FIQ"
textline " "
bitfld.long 0x00 15. " [15] ,FIQ/IRQ Program Control 15 (MIBADC1 sw group 1 interrupt)" "IRQ,FIQ"
bitfld.long 0x00 14. " [14] ,FIQ/IRQ Program Control 14 (MIBADC1 event group interrupt)" "IRQ,FIQ"
bitfld.long 0x00 13. " [13] ,FIQ/IRQ Program Control 13 (LIN1 level 0 interrupt)" "IRQ,FIQ"
bitfld.long 0x00 12. " [12] ,FIQ/IRQ Program Control 12 (MIBSPI1 level 0 interrupt)" "IRQ,FIQ"
textline " "
bitfld.long 0x00 11. " [11] ,FIQ/IRQ Program Control 11 (HET TU1 level 0 interrupt)" "IRQ,FIQ"
bitfld.long 0x00 10. " [10] ,FIQ/IRQ Program Control 10 (NHET1 level 0 interrupt)" "IRQ,FIQ"
bitfld.long 0x00 9. " [9] ,FIQ/IRQ Program Control 9 (GIO interrupt A)" "IRQ,FIQ"
bitfld.long 0x00 8. " [8] ,FIQ/IRQ Program Control 8 (RTI1 timebase)" "IRQ,FIQ"
textline " "
bitfld.long 0x00 7. " [7] ,FIQ/IRQ Program Control 7 (RTI1 overflow interrupt 1)" "IRQ,FIQ"
bitfld.long 0x00 6. " [6] ,FIQ/IRQ Program Control 6 (RTI1 overflow interrupt 0)" "IRQ,FIQ"
bitfld.long 0x00 5. " [5] ,FIQ/IRQ Program Control 5 (RTI1 compare interrupt 3)" "IRQ,FIQ"
bitfld.long 0x00 4. " [4] ,FIQ/IRQ Program Control 4 (RTI1 compare interrupt 2)" "IRQ,FIQ"
textline " "
bitfld.long 0x00 3. " [3] ,FIQ/IRQ Program Control 3 (RTI1 compare interrupt 1)" "IRQ,FIQ"
bitfld.long 0x00 2. " [2] ,FIQ/IRQ Program Control 2 (RTI1 compare interrupt 0)" "IRQ,FIQ"
bitfld.long 0x00 0. " [0] ,FIQ/IRQ Program Control 0 (ESM High level interrupt)" "IRQ,FIQ"
line.long 0x4 "FIRQPR1,Program Control Register"
bitfld.long 0x04 31. " FIRQPR_[63] ,FIQ/IRQ Program Control 63 (NHET2 level 0 interrupt)" "IRQ,FIQ"
bitfld.long 0x04 30. " [62] ,FIQ/IRQ Program Control 62 (Flexray T1C interrupt)" "IRQ,FIQ"
bitfld.long 0x04 29. " [61] ,FIQ/IRQ Program Control 61 (FSM_DONE interrupt)" "IRQ,FIQ"
bitfld.long 0x04 28. " [60] ,FIQ/IRQ Program Control 60 (DCAN3 IF3 interrupt)" "IRQ,FIQ"
textline " "
bitfld.long 0x04 27. " [59] ,FIQ/IRQ (Program Control 59 (MibADC2 magnitude compare interrupt)" "IRQ,FIQ"
bitfld.long 0x04 26. " [58] ,FIQ/IRQ Program Control 58 (Flexray TU Error interrupt)" "IRQ,FIQ"
bitfld.long 0x04 25. " [57] ,FIQ/IRQ Program Control 57 (MibADC2 sw group2 interrupt)" "IRQ,FIQ"
bitfld.long 0x04 24. " [56] ,FIQ/IRQ Program Control 56 (MIBSPI5 level 1 interrupt)" "IRQ,FIQ"
textline " "
bitfld.long 0x04 23. " [55] ,FIQ/IRQ Program Control 55 (DCAN3 level 1 interrupt)" "IRQ,FIQ"
bitfld.long 0x04 22. " [54] ,FIQ/IRQ Program Control 54 (MIBSPI4 level 1 interrupt)" "IRQ,FIQ"
bitfld.long 0x04 21. " [53] ,FIQ/IRQ Program Control 53 (MIBSPI5 level 0 interrupt)" "IRQ,FIQ"
bitfld.long 0x04 20. " [52] ,FIQ/IRQ Program Control 52 (Flexray T0C interrupt)" "IRQ,FIQ"
textline " "
bitfld.long 0x04 19. " [51] ,FIQ/IRQ Program Control 51 (MibADC2 sw group1 interrupt)" "IRQ,FIQ"
bitfld.long 0x04 18. " [50] ,FIQ/IRQ Program Control 50 (MibADC2 event group interrupt)" "IRQ,FIQ"
bitfld.long 0x04 17. " [49] ,FIQ/IRQ Program Control 49 (MIBSPI4 level 0 interrupt)" "IRQ,FIQ"
bitfld.long 0x04 16. " [48] ,FIQ/IRQ Program Control 48 (Flexray TU Transfer Status interrupt)" "IRQ,FIQ"
textline " "
bitfld.long 0x04 15. " [47] ,FIQ/IRQ Program Control 47 (FPU interrupt of Cortex-R5F)" "IRQ,FIQ"
bitfld.long 0x04 14. " [46] ,FIQ/IRQ Program Control 46 (DCAN2 IF3 interrupt)" "IRQ,FIQ"
bitfld.long 0x04 13. " [45] ,FIQ/IRQ Program Control 45 (DCAN3 level 0 interrupt)" "IRQ,FIQ"
bitfld.long 0x04 12. " [44] ,FIQ/IRQ Program Control 44 (DCAN1 IF3 interrupt)" "IRQ,FIQ"
textline " "
bitfld.long 0x04 11. " [43] ,FIQ/IRQ Program Control 43 (DMM level 1 interrupt)" "IRQ,FIQ"
bitfld.long 0x04 10. " [42] ,FIQ/IRQ Program Control 42 (DCAN2 level 1 interrupt)" "IRQ,FIQ"
bitfld.long 0x04 9. " [41] ,FIQ/IRQ Program Control 41 (AEMIFINT)" "IRQ,FIQ"
bitfld.long 0x04 8. " [40] ,FIQ/IRQ Program Control 40 (BTCA interrupt)" "IRQ,FIQ"
textline " "
bitfld.long 0x04 7. " [39] ,FIQ/IRQ Program Control 39 (HBCA interrupt)" "IRQ,FIQ"
bitfld.long 0x04 6. " [38] ,FIQ/IRQ Program Control 38 (MIBSPI3 level 1 interrupt)" "IRQ,FIQ"
bitfld.long 0x04 5. " [37] ,FIQ/IRQ Program Control 37 (MIBSPI3 level 0 interrupt)" "IRQ,FIQ"
bitfld.long 0x04 4. " [36] ,FIQ/IRQ Program Control 36 (DMM level 0 interrupt)" "IRQ,FIQ"
textline " "
bitfld.long 0x04 3. " [35] ,FIQ/IRQ Program Control 35 (DCAN2 level 0 interrupt)" "IRQ,FIQ"
bitfld.long 0x04 2. " [34] ,FIQ/IRQ Program Control 34 (LFSA interrupt)" "IRQ,FIQ"
bitfld.long 0x04 1. " [33] ,FIQ/IRQ Program Control 33 (FTCA interrupt)" "IRQ,FIQ"
bitfld.long 0x04 0. " [32] ,FIQ/IRQ Program Control 32 (Flexray level 1 interrupt)" "IRQ,FIQ"
line.long 0x08 "FIRQPR2,Program Control Register"
bitfld.long 0x08 31. " FIRQPR_[95] ,FIQ/IRQ Program Control 95 (eTPWM3 Trip Zone Interrupt)" "IRQ,FIQ"
bitfld.long 0x08 30. " [94] ,FIQ/IRQ Program Control 94 (eTPWM3 Interrupt)" "IRQ,FIQ"
bitfld.long 0x08 29. " [93] ,FIQ/IRQ Program Control 93 (eTPWM2 Trip Zone Interrupt)" "IRQ,FIQ"
bitfld.long 0x08 28. " [92] ,FIQ/IRQ Program Control 92 (eTPWM2 Interrupt)" "IRQ,FIQ"
textline " "
bitfld.long 0x08 27. " [91] ,FIQ/IRQ Program Control 91 (eTPWM1 Trip Zone Interrupt)" "IRQ,FIQ"
bitfld.long 0x08 26. " [90] ,FIQ/IRQ Program Control 90 (eTPWM1 Interrupt)" "IRQ,FIQ"
bitfld.long 0x08 25. " [89] ,FIQ/IRQ Program Control 89 (HWA_INT_REQ_L)" "IRQ,FIQ"
bitfld.long 0x08 24. " [88] ,FIQ/IRQ Program Control 88 (HWA_INT_REQ_L)" "IRQ,FIQ"
textline " "
bitfld.long 0x08 23. " [87] ,FIQ/IRQ Program Control 87 (IMM Interrupt 1)" "IRQ,FIQ"
bitfld.long 0x08 22. " [86] ,FIQ/IRQ Program Control 86 (IMM Interrupt 0)" "IRQ,FIQ"
bitfld.long 0x08 21. " [85] ,FIQ/IRQ Program Control 85 (PBIST Done)" "IRQ,FIQ"
textline " "
bitfld.long 0x08 19. " [83] ,FIQ/IRQ Program Control 83 (DCC2 done interrupt)" "IRQ,FIQ"
bitfld.long 0x08 18. " [82] ,FIQ/IRQ Program Control 82 (DCC1 done interrupt)" "IRQ,FIQ"
bitfld.long 0x08 17. " [81] ,FIQ/IRQ Program Control 81 (HWA_INT_REQ_H)" "IRQ,FIQ"
bitfld.long 0x08 16. " [80] ,FIQ/IRQ Program Control 80 (HWA_INT_REQ_H)" "IRQ,FIQ"
textline " "
bitfld.long 0x08 15. " [79] ,FIQ/IRQ Program Control 79 (C0_RX_PULSE)" "IRQ,FIQ"
bitfld.long 0x08 14. " [78] ,FIQ/IRQ Program Control 78 (C0_THRESH_PULSE)" "IRQ,FIQ"
bitfld.long 0x08 13. " [77] ,FIQ/IRQ Program Control 77 (C0_TX_PULSE)" "IRQ,FIQ"
bitfld.long 0x08 12. " [76] ,FIQ/IRQ Program Control 76 (C0_MISC_PULSE)" "IRQ,FIQ"
textline " "
bitfld.long 0x08 11. " [75] ,FIQ/IRQ Program Control 75 (NHET TU2 level 1 interrupt)" "IRQ,FIQ"
bitfld.long 0x08 10. " [74] ,FIQ/IRQ Program Control 74 (SCI3 level 1 interrupt)" "IRQ,FIQ"
bitfld.long 0x08 9. " [73] ,FIQ/IRQ Program Control 73 (NHET2 level 1 interrupt)" "IRQ,FIQ"
textline " "
bitfld.long 0x08 2. " [66] ,FIQ/IRQ Program Control 66 (I2C level 0 interrupt)" "IRQ,FIQ"
bitfld.long 0x08 1. " [65] ,FIQ/IRQ Program Control 65 (NHET TU2 level 0 interrupt)" "IRQ,FIQ"
bitfld.long 0x08 0. " [64] ,FIQ/IRQ Program Control 64 (SCI3 level 0 interrupt)" "IRQ,FIQ"
line.long 0x0C "FIRQPR3,Program Control Register"
bitfld.long 0x0C 28. " FIRQPR_[124] ,FIQ/IRQ Program Control 124 (EPC FIFO FULL or CAM FULL interrupt)" "IRQ,FIQ"
textline " "
bitfld.long 0x0C 25. " [121] ,FIQ/IRQ Program Control 121 (CRC2 Interrupt)" "IRQ,FIQ"
bitfld.long 0x0C 24. " [120] ,FIQ/IRQ Program Control 120 (DCAN4 IF3 Interrupt)" "IRQ,FIQ"
textline " "
bitfld.long 0x0C 23. " [119] ,FIQ/IRQ Program Control 119 (SCI4 level 1 interrupt)" "IRQ,FIQ"
bitfld.long 0x0C 22. " [118] ,FIQ/IRQ Program Control 118 (LIN2 level 1 interrupt)" "IRQ,FIQ"
bitfld.long 0x0C 21. " [117] ,FIQ/IRQ Program Control 117 (DCAN4 Level 1 interrupt)" "IRQ,FIQ"
bitfld.long 0x0C 20. " [116] ,FIQ/IRQ Program Control 116 (SCI4 level 0 interrupt)" "IRQ,FIQ"
textline " "
bitfld.long 0x0C 19. " [115] ,FIQ/IRQ Program Control 115 (LIN2 level 0 interrupt)" "IRQ,FIQ"
bitfld.long 0x0C 18. " [114] ,FIQ/IRQ Program Control 114 (I2C2 interrupt)" "IRQ,FIQ"
bitfld.long 0x0C 17. " [113] ,FIQ/IRQ Program Control 113 (DCAN4 Level 0 interrupt)" "IRQ,FIQ"
textline " "
bitfld.long 0x0C 15. " [111] ,FIQ/IRQ Program Control 111 (eQEP2 Interrupt)" "IRQ,FIQ"
bitfld.long 0x0C 14. " [110] ,FIQ/IRQ Program Control 110 (eQEP1 Interrupt)" "IRQ,FIQ"
bitfld.long 0x0C 13. " [109] ,FIQ/IRQ Program Control 109 (eCAP6 Interrupt)" "IRQ,FIQ"
bitfld.long 0x0C 12. " [108] ,FIQ/IRQ Program Control 108 (eCAP5 Interrupt)" "IRQ,FIQ"
textline " "
bitfld.long 0x0C 11. " [107] ,FIQ/IRQ Program Control 107 (eCAP4 Interrupt)" "IRQ,FIQ"
bitfld.long 0x0C 10. " [106] ,FIQ/IRQ Program Control 106 (eCAP3 Interrupt)" "IRQ,FIQ"
bitfld.long 0x0C 9. " [105] ,FIQ/IRQ Program Control 105 (eCAP2 Interrupt)" "IRQ,FIQ"
bitfld.long 0x0C 8. " [104] ,FIQ/IRQ Program Control 104 (eCAP1 Interrupt)" "IRQ,FIQ"
textline " "
bitfld.long 0x0C 7. " [103] ,FIQ/IRQ Program Control 103 (eTPWM7 Trip Zone Interrupt)" "IRQ,FIQ"
bitfld.long 0x0C 6. " [102] ,FIQ/IRQ Program Control 102 (eTPWM7 Interrupt)" "IRQ,FIQ"
bitfld.long 0x0C 5. " [101] ,FIQ/IRQ Program Control 101 (eTPWM6 Trip Zone Interrupt)" "IRQ,FIQ"
bitfld.long 0x0C 4. " [100] ,FIQ/IRQ Program Control 100 (eTPWM6 Interrupt)" "IRQ,FIQ"
textline " "
bitfld.long 0x0C 3. " [99] ,FIQ/IRQ Program Control 99 (eTPWM5 Trip Zone Interrupt)" "IRQ,FIQ"
bitfld.long 0x0C 2. " [98] ,FIQ/IRQ Program Control 98 (eTPWM5 Interrupt)" "IRQ,FIQ"
bitfld.long 0x0C 1. " [97] ,FIQ/IRQ Program Control 97 (eTPWM4 Trip Zone Interrupt)" "IRQ,FIQ"
bitfld.long 0x0C 0. " [96] ,FIQ/IRQ Program Control 96 (eTPWM4 Interrupt)" "IRQ,FIQ"
tree "VIM Pending Interrupt Read Location Registers"
group.long 0x20++0xF
line.long 0x0 "INTREQ0,Pending Interrupt Read Location"
bitfld.long 0x00 31. " INTREQ_[31] ,Interrupt Pending 31 (MIBADC1 magnitude compare interrupt)" "No interrupt,Interrupt"
bitfld.long 0x00 30. " [30] ,Interrupt Pending 30 (30 MIBSPI2 level 1 interrupt)" "No interrupt,Interrupt"
bitfld.long 0x00 29. " [29] ,Interrupt Pending 29 (DCAN1 level 1 interrupt)" "No interrupt,Interrupt"
bitfld.long 0x00 28. " [28] ,Interrupt Pending 28 (MIBADC1 sw group 2 interrupt)" "No interrupt,Interrupt"
textline " "
bitfld.long 0x00 27. " [27] ,Interrupt Pending 27 (LIN1 level 1 interrupt)" "No interrupt,Interrupt"
bitfld.long 0x00 26. " [26] ,Interrupt Pending 26 (MIBSPI1 level 1 interrupt)" "No interrupt,Interrupt"
bitfld.long 0x00 25. " [25] ,Interrupt Pending 25 (HET TU1 level 1 interrupt)" "No interrupt,Interrupt"
bitfld.long 0x00 24. " [24] ,Interrupt Pending 24 (NHET1 level 1 interrupt)" "No interrupt,Interrupt"
textline " "
bitfld.long 0x00 23. " [23] ,Interrupt Pending 23 (GIO interrupt B)" "No interrupt,Interrupt"
bitfld.long 0x00 22. " [22] ,Interrupt Pending 22 (Cortex-R5F PMU Interrupt)" "No interrupt,Interrupt"
bitfld.long 0x00 21. " [21] ,Interrupt Pending 21 (Software interrupt for Cortex-R5F)" "No interrupt,Interrupt"
bitfld.long 0x00 20. " [20] ,Interrupt Pending 20 (ESM Low level interrupt)" "No interrupt,Interrupt"
textline " "
bitfld.long 0x00 19. " [19] ,Interrupt Pending 19 (CRC1 Interrupt)" "No interrupt,Interrupt"
bitfld.long 0x00 18. " [18] ,Interrupt Pending 18 (Flexray level 0 interrupt)" "No interrupt,Interrupt"
bitfld.long 0x00 17. " [17] ,Interrupt Pending 17 (MIBSPI2 level 0 interrupt)" "No interrupt,Interrupt"
bitfld.long 0x00 16. " [16] ,Interrupt Pending 16 (DCAN1 level 0 interrupt)" "No interrupt,Interrupt"
textline " "
bitfld.long 0x00 15. " [15] ,Interrupt Pending 15 (MIBADC1 sw group 1 interrupt)" "No interrupt,Interrupt"
bitfld.long 0x00 14. " [14] ,Interrupt Pending 14 (MIBADC1 event group interrupt)" "No interrupt,Interrupt"
bitfld.long 0x00 13. " [13] ,Interrupt Pending 13 (LIN1 level 0 interrupt)" "No interrupt,Interrupt"
bitfld.long 0x00 12. " [12] ,Interrupt Pending 12 (MIBSPI1 level 0 interrupt)" "No interrupt,Interrupt"
textline " "
bitfld.long 0x00 11. " [11] ,Interrupt Pending 11 (HET TU1 level 0 interrupt)" "No interrupt,Interrupt"
bitfld.long 0x00 10. " [10] ,Interrupt Pending 10 (NHET1 level 0 interrupt)" "No interrupt,Interrupt"
bitfld.long 0x00 9. " [9] ,Interrupt Pending 9 (GIO interrupt A)" "No interrupt,Interrupt"
bitfld.long 0x00 8. " [8] ,Interrupt Pending 8 (RTI1 timebase)" "No interrupt,Interrupt"
textline " "
bitfld.long 0x00 7. " [7] ,Interrupt Pending 7 (RTI1 overflow interrupt 1)" "No interrupt,Interrupt"
bitfld.long 0x00 6. " [6] ,Interrupt Pending 6 (RTI1 overflow interrupt 0)" "No interrupt,Interrupt"
bitfld.long 0x00 5. " [5] ,Interrupt Pending 5 (RTI1 compare interrupt 3)" "No interrupt,Interrupt"
bitfld.long 0x00 4. " [4] ,Interrupt Pending 4 (RTI1 compare interrupt 2)" "No interrupt,Interrupt"
textline " "
bitfld.long 0x00 3. " [3] ,Interrupt Pending 3 (RTI1 compare interrupt 1)" "No interrupt,Interrupt"
bitfld.long 0x00 2. " [2] ,Interrupt Pending 2 (RTI1 compare interrupt 0)" "No interrupt,Interrupt"
bitfld.long 0x00 0. " [0] ,Interrupt Pending 0 (ESM High level interrupt)" "No interrupt,Interrupt"
line.long 0x4 "INTREQ1,Pending Interrupt Read Location"
bitfld.long 0x04 31. " INTREQ_[63] ,Interrupt Pending 63 (NHET2 level 0 interrupt)" "No interrupt,Interrupt"
bitfld.long 0x04 30. " [62] ,Interrupt Pending 62 (Flexray T1C interrupt)" "No interrupt,Interrupt"
bitfld.long 0x04 29. " [61] ,Interrupt Pending 61 (FSM_DONE interrupt)" "No interrupt,Interrupt"
bitfld.long 0x04 28. " [60] ,Interrupt Pending 60 (DCAN3 IF3 interrupt)" "No interrupt,Interrupt"
textline " "
bitfld.long 0x04 27. " [59] ,Interrupt Pending 59 (MibADC2 magnitude compare interrupt)" "No interrupt,Interrupt"
bitfld.long 0x04 26. " [58] ,Interrupt Pending 58 (Flexray TU Error interrupt)" "No interrupt,Interrupt"
bitfld.long 0x04 25. " [57] ,Interrupt Pending 57 (MibADC2 sw group2 interrupt)" "No interrupt,Interrupt"
bitfld.long 0x04 24. " [56] ,Interrupt Pending 56 (MIBSPI5 level 1 interrupt)" "No interrupt,Interrupt"
textline " "
bitfld.long 0x04 23. " [55] ,Interrupt Pending 55 (DCAN3 level 1 interrupt)" "No interrupt,Interrupt"
bitfld.long 0x04 22. " [54] ,Interrupt Pending 54 (MIBSPI4 level 1 interrupt)" "No interrupt,Interrupt"
bitfld.long 0x04 21. " [53] ,Interrupt Pending 53 (MIBSPI5 level 0 interrupt)" "No interrupt,Interrupt"
bitfld.long 0x04 20. " [52] ,Interrupt Pending 52 (Flexray T0C interrupt)" "No interrupt,Interrupt"
textline " "
bitfld.long 0x04 19. " [51] ,Interrupt Pending 51 (MibADC2 sw group1 interrupt)" "No interrupt,Interrupt"
bitfld.long 0x04 18. " [50] ,Interrupt Pending 50 (MibADC2 event group interrupt)" "No interrupt,Interrupt"
bitfld.long 0x04 17. " [49] ,Interrupt Pending 49 (MIBSPI4 level 0 interrupt)" "No interrupt,Interrupt"
bitfld.long 0x04 16. " [48] ,Interrupt Pending 48 (Flexray TU Transfer Status interrupt)" "No interrupt,Interrupt"
textline " "
bitfld.long 0x04 15. " [47] ,Interrupt Pending 47 (FPU interrupt of Cortex-R5F)" "No interrupt,Interrupt"
bitfld.long 0x04 14. " [46] ,Interrupt Pending 46 (DCAN2 IF3 interrupt)" "No interrupt,Interrupt"
bitfld.long 0x04 13. " [45] ,Interrupt Pending 45 (DCAN3 level 0 interrupt)" "No interrupt,Interrupt"
bitfld.long 0x04 12. " [44] ,Interrupt Pending 44 (DCAN1 IF3 interrupt)" "No interrupt,Interrupt"
textline " "
bitfld.long 0x04 11. " [43] ,Interrupt Pending 43 (DMM level 1 interrupt)" "No interrupt,Interrupt"
bitfld.long 0x04 10. " [42] ,Interrupt Pending 42 (DCAN2 level 1 interrupt)" "No interrupt,Interrupt"
bitfld.long 0x04 9. " [41] ,Interrupt Pending 41 (AEMIFINT)" "No interrupt,Interrupt"
bitfld.long 0x04 8. " [40] ,Interrupt Pending 40 (BTCA interrupt)" "No interrupt,Interrupt"
textline " "
bitfld.long 0x04 7. " [39] ,Interrupt Pending 39 (HBCA interrupt)" "No interrupt,Interrupt"
bitfld.long 0x04 6. " [38] ,Interrupt Pending 38 (MIBSPI3 level 1 interrupt)" "No interrupt,Interrupt"
bitfld.long 0x04 5. " [37] ,Interrupt Pending 37 (MIBSPI3 level 0 interrupt)" "No interrupt,Interrupt"
bitfld.long 0x04 4. " [36] ,Interrupt Pending 36 (DMM level 0 interrupt)" "No interrupt,Interrupt"
textline " "
bitfld.long 0x04 3. " [35] ,Interrupt Pending 35 (DCAN2 level 0 interrupt)" "No interrupt,Interrupt"
bitfld.long 0x04 2. " [34] ,Interrupt Pending 34 (LFSA interrupt)" "No interrupt,Interrupt"
bitfld.long 0x04 1. " [33] ,Interrupt Pending 33 (FTCA interrupt)" "No interrupt,Interrupt"
bitfld.long 0x04 0. " [32] ,Interrupt Pending 32 (Flexray level 1 interrupt)" "No interrupt,Interrupt"
line.long 0x8 "INTREQ2,Pending Interrupt Read Location"
bitfld.long 0x08 31. " INTREQ_[95] ,Interrupt Pending 95 (eTPWM3 Trip Zone Interrupt)" "No interrupt,Interrupt"
bitfld.long 0x08 30. " [94] ,Interrupt Pending 94 (eTPWM3 Interrupt)" "No interrupt,Interrupt"
bitfld.long 0x08 29. " [93] ,Interrupt Pending 93 (eTPWM2 Trip Zone Interrupt)" "No interrupt,Interrupt"
bitfld.long 0x08 28. " [92] ,Interrupt Pending 92 (eTPWM2 Interrupt)" "No interrupt,Interrupt"
textline " "
bitfld.long 0x08 27. " [91] ,Interrupt Pending 91 (eTPWM1 Trip Zone Interrupt)" "No interrupt,Interrupt"
bitfld.long 0x08 26. " [90] ,Interrupt Pending 90 (eTPWM1 Interrupt)" "No interrupt,Interrupt"
bitfld.long 0x08 25. " [89] ,Interrupt Pending 89 (HWA_INT_REQ_L)" "No interrupt,Interrupt"
bitfld.long 0x08 24. " [88] ,Interrupt Pending 88 (HWA_INT_REQ_L)" "No interrupt,Interrupt"
textline " "
bitfld.long 0x08 23. " [87] ,Interrupt Pending 87 (IMM Interrupt 1)" "No interrupt,Interrupt"
bitfld.long 0x08 22. " [86] ,Interrupt Pending 86 (IMM Interrupt 0)" "No interrupt,Interrupt"
bitfld.long 0x08 21. " [85] ,Interrupt Pending 85 (PBIST Done)" "No interrupt,Interrupt"
textline " "
bitfld.long 0x08 19. " [83] ,Interrupt Pending 83 (DCC2 done interrupt)" "No interrupt,Interrupt"
bitfld.long 0x08 18. " [82] ,Interrupt Pending 82 (DCC1 done interrupt)" "No interrupt,Interrupt"
bitfld.long 0x08 17. " [81] ,Interrupt Pending 81 (HWA_INT_REQ_H)" "No interrupt,Interrupt"
bitfld.long 0x08 16. " [80] ,Interrupt Pending 80 (HWA_INT_REQ_H)" "No interrupt,Interrupt"
textline " "
bitfld.long 0x08 15. " [79] ,Interrupt Pending 79 (C0_RX_PULSE)" "No interrupt,Interrupt"
bitfld.long 0x08 14. " [78] ,Interrupt Pending 78 (C0_THRESH_PULSE)" "No interrupt,Interrupt"
bitfld.long 0x08 13. " [77] ,Interrupt Pending 77 (C0_TX_PULSE)" "No interrupt,Interrupt"
bitfld.long 0x08 12. " [76] ,Interrupt Pending 76 (C0_MISC_PULSE)" "No interrupt,Interrupt"
textline " "
bitfld.long 0x08 11. " [75] ,Interrupt Pending 75 (NHET TU2 level 1 interrupt)" "No interrupt,Interrupt"
bitfld.long 0x08 10. " [74] ,Interrupt Pending 74 (SCI3 level 1 interrupt)" "No interrupt,Interrupt"
bitfld.long 0x08 9. " [73] ,Interrupt Pending 73 (NHET2 level 1 interrupt)" "No interrupt,Interrupt"
textline " "
bitfld.long 0x08 2. " [66] ,Interrupt Pending 66 (I2C level 0 interrupt)" "No interrupt,Interrupt"
bitfld.long 0x08 1. " [65] ,Interrupt Pending 65 (NHET TU2 level 0 interrupt)" "No interrupt,Interrupt"
bitfld.long 0x08 0. " [64] ,Interrupt Pending 64 (SCI3 level 0 interrupt)" "No interrupt,Interrupt"
line.long 0xC "INTREQ3,Pending Interrupt Read Location"
bitfld.long 0x0C 28. " INTREQ_[124] ,Interrupt Pending 124 (EPC FIFO FULL or CAM FULL interrupt)" "No interrupt,Interrupt"
textline " "
bitfld.long 0x0C 25. " [121] ,Interrupt Pending 121 (CRC2 Interrupt)" "No interrupt,Interrupt"
bitfld.long 0x0C 24. " [120] ,Interrupt Pending 120 (DCAN4 IF3 Interrupt)" "No interrupt,Interrupt"
textline " "
bitfld.long 0x0C 23. " [119] ,Interrupt Pending 119 (SCI4 level 1 interrupt)" "No interrupt,Interrupt"
bitfld.long 0x0C 22. " [118] ,Interrupt Pending 118 (LIN2 level 1 interrupt)" "No interrupt,Interrupt"
bitfld.long 0x0C 21. " [117] ,Interrupt Pending 117 (DCAN4 Level 1 interrupt)" "No interrupt,Interrupt"
bitfld.long 0x0C 20. " [116] ,Interrupt Pending 116 (SCI4 level 0 interrupt)" "No interrupt,Interrupt"
textline " "
bitfld.long 0x0C 19. " [115] ,Interrupt Pending 115 (LIN2 level 0 interrupt)" "No interrupt,Interrupt"
bitfld.long 0x0C 18. " [114] ,Interrupt Pending 114 (I2C2 interrupt)" "No interrupt,Interrupt"
bitfld.long 0x0C 17. " [113] ,Interrupt Pending 113 (DCAN4 Level 0 interrupt)" "No interrupt,Interrupt"
textline " "
bitfld.long 0x0C 15. " [111] ,Interrupt Pending 111 (eQEP2 Interrupt)" "No interrupt,Interrupt"
bitfld.long 0x0C 14. " [110] ,Interrupt Pending 110 (eQEP1 Interrupt)" "No interrupt,Interrupt"
bitfld.long 0x0C 13. " [109] ,Interrupt Pending 109 (eCAP6 Interrupt)" "No interrupt,Interrupt"
bitfld.long 0x0C 12. " [108] ,Interrupt Pending 108 (eCAP5 Interrupt)" "No interrupt,Interrupt"
textline " "
bitfld.long 0x0C 11. " [107] ,Interrupt Pending 107 (eCAP4 Interrupt)" "No interrupt,Interrupt"
bitfld.long 0x0C 10. " [106] ,Interrupt Pending 106 (eCAP3 Interrupt)" "No interrupt,Interrupt"
bitfld.long 0x0C 9. " [105] ,Interrupt Pending 105 (eCAP2 Interrupt)" "No interrupt,Interrupt"
bitfld.long 0x0C 8. " [104] ,Interrupt Pending 104 (eCAP1 Interrupt)" "No interrupt,Interrupt"
textline " "
bitfld.long 0x0C 7. " [103] ,Interrupt Pending 103 (eTPWM7 Trip Zone Interrupt)" "No interrupt,Interrupt"
bitfld.long 0x0C 6. " [102] ,Interrupt Pending 102 (eTPWM7 Interrupt)" "No interrupt,Interrupt"
bitfld.long 0x0C 5. " [101] ,Interrupt Pending 101 (eTPWM6 Trip Zone Interrupt)" "No interrupt,Interrupt"
bitfld.long 0x0C 4. " [100] ,Interrupt Pending 100 (eTPWM6 Interrupt)" "No interrupt,Interrupt"
textline " "
bitfld.long 0x0C 3. " [99] ,Interrupt Pending 99 (eTPWM5 Trip Zone Interrupt)" "No interrupt,Interrupt"
bitfld.long 0x0C 2. " [98] ,Interrupt Pending 98 (eTPWM5 Interrupt)" "No interrupt,Interrupt"
bitfld.long 0x0C 1. " [97] ,Interrupt Pending 97 (eTPWM4 Trip Zone Interrupt)" "No interrupt,Interrupt"
bitfld.long 0x0C 0. " [96] ,Interrupt Pending 96 (eTPWM4 Interrupt)" "No interrupt,Interrupt"
tree.end
width 13.
tree "VIM Interrupt Mask Registers"
group.long 0x30++0x3
line.long 0x0 "REQENASET0,Interrupt Mask Set Register"
setclrfld.long 0x00 31. 0x00 31. 0x10 31. " REQMASK_set/clr_[31] ,Request Mask 31 (MIBADC1 magnitude compare interrupt)" "Disabled,Enabled"
setclrfld.long 0x00 30. 0x00 30. 0x10 30. " [30] ,Request Mask 30 (30 MIBSPI2 level 1 interrupt)" "Disabled,Enabled"
setclrfld.long 0x00 29. 0x00 29. 0x10 29. " [29] ,Request Mask 29 (DCAN1 level 1 interrupt)" "Disabled,Enabled"
setclrfld.long 0x00 28. 0x00 28. 0x10 28. " [28] ,Request Mask 28 (MIBADC1 sw group 2 interrupt)" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 27. 0x00 27. 0x10 27. " [27] ,Request Mask 27 (LIN1 level 1 interrupt)" "Disabled,Enabled"
setclrfld.long 0x00 26. 0x00 26. 0x10 26. " [26] ,Request Mask 26 (MIBSPI1 level 1 interrupt)" "Disabled,Enabled"
setclrfld.long 0x00 25. 0x00 25. 0x10 25. " [25] ,Request Mask 25 (HET TU1 level 1 interrupt)" "Disabled,Enabled"
setclrfld.long 0x00 24. 0x00 24. 0x10 24. " [24] ,Request Mask 24 (NHET1 level 1 interrupt)" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 23. 0x00 23. 0x10 23. " [23] ,Request Mask 23 (GIO interrupt B)" "Disabled,Enabled"
setclrfld.long 0x00 22. 0x00 22. 0x10 22. " [22] ,Request Mask 22 (Cortex-R5F PMU Interrupt)" "Disabled,Enabled"
setclrfld.long 0x00 21. 0x00 21. 0x10 21. " [21] ,Request Mask 21 (Software interrupt for Cortex-R5F)" "Disabled,Enabled"
setclrfld.long 0x00 20. 0x00 20. 0x10 20. " [20] ,Request Mask 20 (ESM Low level interrupt)" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 19. 0x00 19. 0x10 19. " [19] ,Request Mask 19 (CRC1 Interrupt)" "Disabled,Enabled"
setclrfld.long 0x00 18. 0x00 18. 0x10 18. " [18] ,Request Mask 18 (Flexray level 0 interrupt)" "Disabled,Enabled"
setclrfld.long 0x00 17. 0x00 17. 0x10 17. " [17] ,Request Mask 17 (MIBSPI2 level 0 interrupt)" "Disabled,Enabled"
setclrfld.long 0x00 16. 0x00 16. 0x10 16. " [16] ,Request Mask 16 (DCAN1 level 0 interrupt)" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 15. 0x00 15. 0x10 15. " [15] ,Request Mask 15 (MIBADC1 sw group 1 interrupt)" "Disabled,Enabled"
setclrfld.long 0x00 14. 0x00 14. 0x10 14. " [14] ,Request Mask 14 (MIBADC1 event group interrupt)" "Disabled,Enabled"
setclrfld.long 0x00 13. 0x00 13. 0x10 13. " [13] ,Request Mask 13 (LIN1 level 0 interrupt)" "Disabled,Enabled"
setclrfld.long 0x00 12. 0x00 12. 0x10 12. " [12] ,Request Mask 12 (MIBSPI1 level 0 interrupt)" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 11. 0x00 11. 0x10 11. " [11] ,Request Mask 11 (HET TU1 level 0 interrupt)" "Disabled,Enabled"
setclrfld.long 0x00 10. 0x00 10. 0x10 10. " [10] ,Request Mask 10 (NHET1 level 0 interrupt)" "Disabled,Enabled"
setclrfld.long 0x00 9. 0x00 9. 0x10 9. " [9] ,Request Mask 9 (GIO interrupt A)" "Disabled,Enabled"
setclrfld.long 0x00 8. 0x00 8. 0x10 8. " [8] ,Request Mask 8 (RTI1 timebase)" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 7. 0x00 7. 0x10 7. " [7] ,Request Mask 7 (RTI1 overflow interrupt 1)" "Disabled,Enabled"
setclrfld.long 0x00 6. 0x00 6. 0x10 6. " [6] ,Request Mask 6 (RTI1 overflow interrupt 0)" "Disabled,Enabled"
setclrfld.long 0x00 5. 0x00 5. 0x10 5. " [5] ,Request Mask 5 (RTI1 compare interrupt 3)" "Disabled,Enabled"
setclrfld.long 0x00 4. 0x00 4. 0x10 4. " [4] ,Request Mask 4 (RTI1 compare interrupt 2)" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 3. 0x00 3. 0x10 3. " [3] ,Request Mask 3 (RTI1 compare interrupt 1)" "Disabled,Enabled"
setclrfld.long 0x00 2. 0x00 2. 0x10 2. " [2] ,Request Mask 2 (RTI1 compare interrupt 0)" "Disabled,Enabled"
setclrfld.long 0x00 0. 0x00 0. 0x10 0. " [0] ,Request Mask 0 (ESM High level interrupt)" "Disabled,Enabled"
group.long 0x34++0x3
line.long 0x0 "REQENASET1,Interrupt Mask Set Register"
setclrfld.long 0x00 31. 0x00 31. 0x10 31. " REQMASK_set/clr_[63] ,Request Mask 63 (NHET2 level 0 interrupt)" "Disabled,Enabled"
setclrfld.long 0x00 30. 0x00 30. 0x10 30. " [62] ,Request Mask 62 (Flexray T1C interrupt)" "Disabled,Enabled"
setclrfld.long 0x00 29. 0x00 29. 0x10 29. " [61] ,Request Mask 61 (FSM_DONE interrupt)" "Disabled,Enabled"
setclrfld.long 0x00 28. 0x00 28. 0x10 28. " [60] ,Request Mask 60 (DCAN3 IF3 interrupt)" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 27. 0x00 27. 0x10 27. " [59] ,Request Mask 59 (MibADC2 magnitude compare interrupt)" "Disabled,Enabled"
setclrfld.long 0x00 26. 0x00 26. 0x10 26. " [58] ,Request Mask 58 (Flexray TU Error interrupt)" "Disabled,Enabled"
setclrfld.long 0x00 25. 0x00 25. 0x10 25. " [57] ,Request Mask 57 (MibADC2 sw group2 interrupt)" "Disabled,Enabled"
setclrfld.long 0x00 24. 0x00 24. 0x10 24. " [56] ,Request Mask 56 (MIBSPI5 level 1 interrupt)" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 23. 0x00 23. 0x10 23. " [55] ,Request Mask 55 (DCAN3 level 1 interrupt)" "Disabled,Enabled"
setclrfld.long 0x00 22. 0x00 22. 0x10 22. " [54] ,Request Mask 54 (MIBSPI4 level 1 interrupt)" "Disabled,Enabled"
setclrfld.long 0x00 21. 0x00 21. 0x10 21. " [53] ,Request Mask 53 (MIBSPI5 level 0 interrupt)" "Disabled,Enabled"
setclrfld.long 0x00 20. 0x00 20. 0x10 20. " [52] ,Request Mask 52 (Flexray T0C interrupt)" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 19. 0x00 19. 0x10 19. " [51] ,Request Mask 51 (MibADC2 sw group1 interrupt)" "Disabled,Enabled"
setclrfld.long 0x00 18. 0x00 18. 0x10 18. " [50] ,Request Mask 50 (MibADC2 event group interrupt)" "Disabled,Enabled"
setclrfld.long 0x00 17. 0x00 17. 0x10 17. " [49] ,Request Mask 49 (MIBSPI4 level 0 interrupt)" "Disabled,Enabled"
setclrfld.long 0x00 16. 0x00 16. 0x10 16. " [48] ,Request Mask 48 (Flexray TU Transfer Status interrupt)" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 15. 0x00 15. 0x10 15. " [47] ,Request Mask 47 (FPU interrupt of Cortex-R5F)" "Disabled,Enabled"
setclrfld.long 0x00 14. 0x00 14. 0x10 14. " [46] ,Request Mask 46 (DCAN2 IF3 interrupt)" "Disabled,Enabled"
setclrfld.long 0x00 13. 0x00 13. 0x10 13. " [45] ,Request Mask 45 (DCAN3 level 0 interrupt)" "Disabled,Enabled"
setclrfld.long 0x00 12. 0x00 12. 0x10 12. " [44] ,Request Mask 44 (DCAN1 IF3 interrupt)" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 11. 0x00 11. 0x10 11. " [43] ,Request Mask 43 (DMM level 1 interrupt)" "Disabled,Enabled"
setclrfld.long 0x00 10. 0x00 10. 0x10 10. " [42] ,Request Mask 42 (DCAN2 level 1 interrupt)" "Disabled,Enabled"
setclrfld.long 0x00 9. 0x00 9. 0x10 9. " [41] ,Request Mask 41 (AEMIFINT)" "Disabled,Enabled"
setclrfld.long 0x00 8. 0x00 8. 0x10 8. " [40] ,Request Mask 40 (BTCA interrupt)" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 7. 0x00 7. 0x10 7. " [39] ,Request Mask 39 (HBCA interrupt)" "Disabled,Enabled"
setclrfld.long 0x00 6. 0x00 6. 0x10 6. " [38] ,Request Mask 38 (MIBSPI3 level 1 interrupt)" "Disabled,Enabled"
setclrfld.long 0x00 5. 0x00 5. 0x10 5. " [37] ,Request Mask 37 (MIBSPI3 level 0 interrupt)" "Disabled,Enabled"
setclrfld.long 0x00 4. 0x00 4. 0x10 4. " [36] ,Request Mask 36 (DMM level 0 interrupt)" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 3. 0x00 3. 0x10 3. " [35] ,Request Mask 35 (DCAN2 level 0 interrupt)" "Disabled,Enabled"
setclrfld.long 0x00 2. 0x00 2. 0x10 2. " [34] ,Request Mask 34 (LFSA interrupt)" "Disabled,Enabled"
setclrfld.long 0x00 1. 0x00 1. 0x10 1. " [33] ,Request Mask 33 (FTCA interrupt)" "Disabled,Enabled"
setclrfld.long 0x00 0. 0x00 0. 0x10 0. " [32] ,Request Mask 32 (Flexray level 1 interrupt)" "Disabled,Enabled"
group.long 0x38++0x3
line.long 0x0 "REQENASET2,Interrupt Mask Set Register"
setclrfld.long 0x00 31. 0x00 31. 0x10 31. " REQMASK_set/clr_[95] ,Request Mask 95 (eTPWM3 Trip Zone Interrupt)" "Disabled,Enabled"
setclrfld.long 0x00 30. 0x00 30. 0x10 30. " [94] ,Request Mask 94 (eTPWM3 Interrupt)" "Disabled,Enabled"
setclrfld.long 0x00 29. 0x00 29. 0x10 29. " [93] ,Request Mask 93 (eTPWM2 Trip Zone Interrupt)" "Disabled,Enabled"
setclrfld.long 0x00 28. 0x00 28. 0x10 28. " [92] ,Request Mask 92 (eTPWM2 Interrupt)" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 27. 0x00 27. 0x10 27. " [91] ,Request Mask 91 (eTPWM1 Trip Zone Interrupt)" "Disabled,Enabled"
setclrfld.long 0x00 26. 0x00 26. 0x10 26. " [90] ,Request Mask 90 (eTPWM1 Interrupt)" "Disabled,Enabled"
setclrfld.long 0x00 25. 0x00 25. 0x10 25. " [89] ,Request Mask 89 (HWA_INT_REQ_L)" "Disabled,Enabled"
setclrfld.long 0x00 24. 0x00 24. 0x10 24. " [88] ,Request Mask 88 (HWA_INT_REQ_L)" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 23. 0x00 23. 0x10 23. " [87] ,Request Mask 87 (IMM Interrupt 1)" "Disabled,Enabled"
setclrfld.long 0x00 22. 0x00 22. 0x10 22. " [86] ,Request Mask 86 (IMM Interrupt 0)" "Disabled,Enabled"
setclrfld.long 0x00 21. 0x00 21. 0x10 21. " [85] ,Request Mask 85 (PBIST Done)" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 19. 0x00 19. 0x10 19. " [83] ,Request Mask 83 (DCC2 done interrupt)" "Disabled,Enabled"
setclrfld.long 0x00 18. 0x00 18. 0x10 18. " [82] ,Request Mask 82 (DCC1 done interrupt)" "Disabled,Enabled"
setclrfld.long 0x00 17. 0x00 17. 0x10 17. " [81] ,Request Mask 81 (HWA_INT_REQ_H)" "Disabled,Enabled"
setclrfld.long 0x00 16. 0x00 16. 0x10 16. " [80] ,Request Mask 80 (HWA_INT_REQ_H)" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 15. 0x00 15. 0x10 15. " [79] ,Request Mask 79 (C0_RX_PULSE)" "Disabled,Enabled"
setclrfld.long 0x00 14. 0x00 14. 0x10 14. " [78] ,Request Mask 78 (C0_THRESH_PULSE)" "Disabled,Enabled"
setclrfld.long 0x00 13. 0x00 13. 0x10 13. " [77] ,Request Mask 77 (C0_TX_PULSE)" "Disabled,Enabled"
setclrfld.long 0x00 12. 0x00 12. 0x10 12. " [76] ,Request Mask 76 (C0_MISC_PULSE)" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 11. 0x00 11. 0x10 11. " [75] ,Request Mask 75 (NHET TU2 level 1 interrupt)" "Disabled,Enabled"
setclrfld.long 0x00 10. 0x00 10. 0x10 10. " [74] ,Request Mask 74 (SCI3 level 1 interrupt)" "Disabled,Enabled"
setclrfld.long 0x00 9. 0x00 9. 0x10 9. " [73] ,Request Mask 73 (NHET2 level 1 interrupt)" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 2. 0x00 2. 0x10 2. " [66] ,Request Mask 66 (I2C level 0 interrupt)" "Disabled,Enabled"
setclrfld.long 0x00 1. 0x00 1. 0x10 1. " [65] ,Request Mask 65 (NHET TU2 level 0 interrupt)" "Disabled,Enabled"
setclrfld.long 0x00 0. 0x00 0. 0x10 0. " [64] ,Request Mask 64 (SCI3 level 0 interrupt)" "Disabled,Enabled"
group.long 0x3C++0x3
line.long 0x0 "REQENASET3,Interrupt Mask Set Register"
setclrfld.long 0x00 28. 0x00 28. 0x10 28. " REQMASK_set/clr_[124] ,Request Mask 124 (EPC FIFO FULL or CAM FULL interrupt)" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 25. 0x00 25. 0x10 25. " [121] ,Request Mask 121 (CRC2 Interrupt)" "Disabled,Enabled"
setclrfld.long 0x00 24. 0x00 24. 0x10 24. " [120] ,Request Mask 120 (DCAN4 IF3 Interrupt)" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 23. 0x00 23. 0x10 23. " [119] ,Request Mask 119 (SCI4 level 1 interrupt)" "Disabled,Enabled"
setclrfld.long 0x00 22. 0x00 22. 0x10 22. " [118] ,Request Mask 118 (LIN2 level 1 interrupt)" "Disabled,Enabled"
setclrfld.long 0x00 21. 0x00 21. 0x10 21. " [117] ,Request Mask 117 (DCAN4 Level 1 interrupt)" "Disabled,Enabled"
setclrfld.long 0x00 20. 0x00 20. 0x10 20. " [116] ,Request Mask 116 (SCI4 level 0 interrupt)" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 19. 0x00 19. 0x10 19. " [115] ,Request Mask 115 (LIN2 level 0 interrupt)" "Disabled,Enabled"
setclrfld.long 0x00 18. 0x00 18. 0x10 18. " [114] ,Request Mask 114 (I2C2 interrupt)" "Disabled,Enabled"
setclrfld.long 0x00 17. 0x00 17. 0x10 17. " [113] ,Request Mask 113 (DCAN4 Level 0 interrupt)" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 15. 0x00 15. 0x10 15. " [111] ,Request Mask 111 (eQEP2 Interrupt)" "Disabled,Enabled"
setclrfld.long 0x00 14. 0x00 14. 0x10 14. " [110] ,Request Mask 110 (eQEP1 Interrupt)" "Disabled,Enabled"
setclrfld.long 0x00 13. 0x00 13. 0x10 13. " [109] ,Request Mask 109 (eCAP6 Interrupt)" "Disabled,Enabled"
setclrfld.long 0x00 12. 0x00 12. 0x10 12. " [108] ,Request Mask 108 (eCAP5 Interrupt)" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 11. 0x00 11. 0x10 11. " [107] ,Request Mask 107 (eCAP4 Interrupt)" "Disabled,Enabled"
setclrfld.long 0x00 10. 0x00 10. 0x10 10. " [106] ,Request Mask 106 (eCAP3 Interrupt)" "Disabled,Enabled"
setclrfld.long 0x00 9. 0x00 9. 0x10 9. " [105] ,Request Mask 105 (eCAP2 Interrupt)" "Disabled,Enabled"
setclrfld.long 0x00 8. 0x00 8. 0x10 8. " [104] ,Request Mask 104 (eCAP1 Interrupt)" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 7. 0x00 7. 0x10 7. " [103] ,Request Mask 103 (eTPWM7 Trip Zone Interrupt)" "Disabled,Enabled"
setclrfld.long 0x00 6. 0x00 6. 0x10 6. " [102] ,Request Mask 102 (eTPWM7 Interrupt)" "Disabled,Enabled"
setclrfld.long 0x00 5. 0x00 5. 0x10 5. " [101] ,Request Mask 101 (eTPWM6 Trip Zone Interrupt)" "Disabled,Enabled"
setclrfld.long 0x00 4. 0x00 4. 0x10 4. " [100] ,Request Mask 100 (eTPWM6 Interrupt)" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 3. 0x00 3. 0x10 3. " [99] ,Request Mask 99 (eTPWM5 Trip Zone Interrupt)" "Disabled,Enabled"
setclrfld.long 0x00 2. 0x00 2. 0x10 2. " [98] ,Request Mask 98 (eTPWM5 Interrupt)" "Disabled,Enabled"
setclrfld.long 0x00 1. 0x00 1. 0x10 1. " [97] ,Request Mask 97 (eTPWM4 Trip Zone Interrupt)" "Disabled,Enabled"
setclrfld.long 0x00 0. 0x00 0. 0x10 0. " [96] ,Request Mask 96 (eTPWM4 Interrupt)" "Disabled,Enabled"
tree.end
width 14.
tree "VIM Wake Up Mask Registers"
group.long 0x50++0x3
line.long 0x0 "WAKEENASET0,Wake-up Mask Set Register"
setclrfld.long 0x00 31. 0x00 31. 0x10 31. " WAKEMASK_set/clr_[31] ,Wake Up Mask 31 (MIBADC1 magnitude compare interrupt)" "Disabled,Enabled"
setclrfld.long 0x00 30. 0x00 30. 0x10 30. " [30] ,Wake Up Mask 30 (30 MIBSPI2 level 1 interrupt)" "Disabled,Enabled"
setclrfld.long 0x00 29. 0x00 29. 0x10 29. " [29] ,Wake Up Mask 29 (DCAN1 level 1 interrupt)" "Disabled,Enabled"
setclrfld.long 0x00 28. 0x00 28. 0x10 28. " [28] ,Wake Up Mask 28 (MIBADC1 sw group 2 interrupt)" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 27. 0x00 27. 0x10 27. " [27] ,Wake Up Mask 27 (LIN1 level 1 interrupt)" "Disabled,Enabled"
setclrfld.long 0x00 26. 0x00 26. 0x10 26. " [26] ,Wake Up Mask 26 (MIBSPI1 level 1 interrupt)" "Disabled,Enabled"
setclrfld.long 0x00 25. 0x00 25. 0x10 25. " [25] ,Wake Up Mask 25 (HET TU1 level 1 interrupt)" "Disabled,Enabled"
setclrfld.long 0x00 24. 0x00 24. 0x10 24. " [24] ,Wake Up Mask 24 (NHET1 level 1 interrupt)" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 23. 0x00 23. 0x10 23. " [23] ,Wake Up Mask 23 (GIO interrupt B)" "Disabled,Enabled"
setclrfld.long 0x00 22. 0x00 22. 0x10 22. " [22] ,Wake Up Mask 22 (Cortex-R5F PMU Interrupt)" "Disabled,Enabled"
setclrfld.long 0x00 21. 0x00 21. 0x10 21. " [21] ,Wake Up Mask 21 (Software interrupt for Cortex-R5F)" "Disabled,Enabled"
setclrfld.long 0x00 20. 0x00 20. 0x10 20. " [20] ,Wake Up Mask 20 (ESM Low level interrupt)" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 19. 0x00 19. 0x10 19. " [19] ,Wake Up Mask 19 (CRC1 Interrupt)" "Disabled,Enabled"
setclrfld.long 0x00 18. 0x00 18. 0x10 18. " [18] ,Wake Up Mask 18 (Flexray level 0 interrupt)" "Disabled,Enabled"
setclrfld.long 0x00 17. 0x00 17. 0x10 17. " [17] ,Wake Up Mask 17 (MIBSPI2 level 0 interrupt)" "Disabled,Enabled"
setclrfld.long 0x00 16. 0x00 16. 0x10 16. " [16] ,Wake Up Mask 16 (DCAN1 level 0 interrupt)" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 15. 0x00 15. 0x10 15. " [15] ,Wake Up Mask 15 (MIBADC1 sw group 1 interrupt)" "Disabled,Enabled"
setclrfld.long 0x00 14. 0x00 14. 0x10 14. " [14] ,Wake Up Mask 14 (MIBADC1 event group interrupt)" "Disabled,Enabled"
setclrfld.long 0x00 13. 0x00 13. 0x10 13. " [13] ,Wake Up Mask 13 (LIN1 level 0 interrupt)" "Disabled,Enabled"
setclrfld.long 0x00 12. 0x00 12. 0x10 12. " [12] ,Wake Up Mask 12 (MIBSPI1 level 0 interrupt)" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 11. 0x00 11. 0x10 11. " [11] ,Wake Up Mask 11 (HET TU1 level 0 interrupt)" "Disabled,Enabled"
setclrfld.long 0x00 10. 0x00 10. 0x10 10. " [10] ,Wake Up Mask 10 (NHET1 level 0 interrupt)" "Disabled,Enabled"
setclrfld.long 0x00 9. 0x00 9. 0x10 9. " [9] ,Wake Up Mask 9 (GIO interrupt A)" "Disabled,Enabled"
setclrfld.long 0x00 8. 0x00 8. 0x10 8. " [8] ,Wake Up Mask 8 (RTI1 timebase)" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 7. 0x00 7. 0x10 7. " [7] ,Wake Up Mask 7 (RTI1 overflow interrupt 1)" "Disabled,Enabled"
setclrfld.long 0x00 6. 0x00 6. 0x10 6. " [6] ,Wake Up Mask 6 (RTI1 overflow interrupt 0)" "Disabled,Enabled"
setclrfld.long 0x00 5. 0x00 5. 0x10 5. " [5] ,Wake Up Mask 5 (RTI1 compare interrupt 3)" "Disabled,Enabled"
setclrfld.long 0x00 4. 0x00 4. 0x10 4. " [4] ,Wake Up Mask 4 (RTI1 compare interrupt 2)" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 3. 0x00 3. 0x10 3. " [3] ,Wake Up Mask 3 (RTI1 compare interrupt 1)" "Disabled,Enabled"
setclrfld.long 0x00 2. 0x00 2. 0x10 2. " [2] ,Wake Up Mask 2 (RTI1 compare interrupt 0)" "Disabled,Enabled"
setclrfld.long 0x00 0. 0x00 0. 0x10 0. " [0] ,Wake Up Mask 0 (ESM High level interrupt)" "Disabled,Enabled"
group.long 0x54++0x3
line.long 0x0 "WAKEENASET1,Wake-up Mask Set Register"
setclrfld.long 0x00 31. 0x00 31. 0x10 31. " WAKEMASK_set/clr_[63] ,Wake Up Mask 63 (NHET2 level 0 interrupt)" "Disabled,Enabled"
setclrfld.long 0x00 30. 0x00 30. 0x10 30. " [62] ,Wake Up Mask 62 (Flexray T1C interrupt)" "Disabled,Enabled"
setclrfld.long 0x00 29. 0x00 29. 0x10 29. " [61] ,Wake Up Mask 61 (FSM_DONE interrupt)" "Disabled,Enabled"
setclrfld.long 0x00 28. 0x00 28. 0x10 28. " [60] ,Wake Up Mask 60 (DCAN3 IF3 interrupt)" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 27. 0x00 27. 0x10 27. " [59] ,Wake Up Mask 59 (MibADC2 magnitude compare interrupt)" "Disabled,Enabled"
setclrfld.long 0x00 26. 0x00 26. 0x10 26. " [58] ,Wake Up Mask 58 (Flexray TU Error interrupt)" "Disabled,Enabled"
setclrfld.long 0x00 25. 0x00 25. 0x10 25. " [57] ,Wake Up Mask 57 (MibADC2 sw group2 interrupt)" "Disabled,Enabled"
setclrfld.long 0x00 24. 0x00 24. 0x10 24. " [56] ,Wake Up Mask 56 (MIBSPI5 level 1 interrupt)" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 23. 0x00 23. 0x10 23. " [55] ,Wake Up Mask 55 (DCAN3 level 1 interrupt)" "Disabled,Enabled"
setclrfld.long 0x00 22. 0x00 22. 0x10 22. " [54] ,Wake Up Mask 54 (MIBSPI4 level 1 interrupt)" "Disabled,Enabled"
setclrfld.long 0x00 21. 0x00 21. 0x10 21. " [53] ,Wake Up Mask 53 (MIBSPI5 level 0 interrupt)" "Disabled,Enabled"
setclrfld.long 0x00 20. 0x00 20. 0x10 20. " [52] ,Wake Up Mask 52 (Flexray T0C interrupt)" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 19. 0x00 19. 0x10 19. " [51] ,Wake Up Mask 51 (MibADC2 sw group1 interrupt)" "Disabled,Enabled"
setclrfld.long 0x00 18. 0x00 18. 0x10 18. " [50] ,Wake Up Mask 50 (MibADC2 event group interrupt)" "Disabled,Enabled"
setclrfld.long 0x00 17. 0x00 17. 0x10 17. " [49] ,Wake Up Mask 49 (MIBSPI4 level 0 interrupt)" "Disabled,Enabled"
setclrfld.long 0x00 16. 0x00 16. 0x10 16. " [48] ,Wake Up Mask 48 (Flexray TU Transfer Status interrupt)" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 15. 0x00 15. 0x10 15. " [47] ,Wake Up Mask 47 (FPU interrupt of Cortex-R5F)" "Disabled,Enabled"
setclrfld.long 0x00 14. 0x00 14. 0x10 14. " [46] ,Wake Up Mask 46 (DCAN2 IF3 interrupt)" "Disabled,Enabled"
setclrfld.long 0x00 13. 0x00 13. 0x10 13. " [45] ,Wake Up Mask 45 (DCAN3 level 0 interrupt)" "Disabled,Enabled"
setclrfld.long 0x00 12. 0x00 12. 0x10 12. " [44] ,Wake Up Mask 44 (DCAN1 IF3 interrupt)" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 11. 0x00 11. 0x10 11. " [43] ,Wake Up Mask 43 (DMM level 1 interrupt)" "Disabled,Enabled"
setclrfld.long 0x00 10. 0x00 10. 0x10 10. " [42] ,Wake Up Mask 42 (DCAN2 level 1 interrupt)" "Disabled,Enabled"
setclrfld.long 0x00 9. 0x00 9. 0x10 9. " [41] ,Wake Up Mask 41 (AEMIFINT)" "Disabled,Enabled"
setclrfld.long 0x00 8. 0x00 8. 0x10 8. " [40] ,Wake Up Mask 40 (BTCA interrupt)" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 7. 0x00 7. 0x10 7. " [39] ,Wake Up Mask 39 (HBCA interrupt)" "Disabled,Enabled"
setclrfld.long 0x00 6. 0x00 6. 0x10 6. " [38] ,Wake Up Mask 38 (MIBSPI3 level 1 interrupt)" "Disabled,Enabled"
setclrfld.long 0x00 5. 0x00 5. 0x10 5. " [37] ,Wake Up Mask 37 (MIBSPI3 level 0 interrupt)" "Disabled,Enabled"
setclrfld.long 0x00 4. 0x00 4. 0x10 4. " [36] ,Wake Up Mask 36 (DMM level 0 interrupt)" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 3. 0x00 3. 0x10 3. " [35] ,Wake Up Mask 35 (DCAN2 level 0 interrupt)" "Disabled,Enabled"
setclrfld.long 0x00 2. 0x00 2. 0x10 2. " [34] ,Wake Up Mask 34 (LFSA interrupt)" "Disabled,Enabled"
setclrfld.long 0x00 1. 0x00 1. 0x10 1. " [33] ,Wake Up Mask 33 (FTCA interrupt)" "Disabled,Enabled"
setclrfld.long 0x00 0. 0x00 0. 0x10 0. " [32] ,Wake Up Mask 32 (Flexray level 1 interrupt)" "Disabled,Enabled"
group.long 0x58++0x3
line.long 0x0 "WAKEENASET2,Wake-up Mask Set Register"
setclrfld.long 0x00 31. 0x00 31. 0x10 31. " WAKEMASK_set/clr_[95] ,Wake Up Mask 95 (eTPWM3 Trip Zone Interrupt)" "Disabled,Enabled"
setclrfld.long 0x00 30. 0x00 30. 0x10 30. " [94] ,Wake Up Mask 94 (eTPWM3 Interrupt)" "Disabled,Enabled"
setclrfld.long 0x00 29. 0x00 29. 0x10 29. " [93] ,Wake Up Mask 93 (eTPWM2 Trip Zone Interrupt)" "Disabled,Enabled"
setclrfld.long 0x00 28. 0x00 28. 0x10 28. " [92] ,Wake Up Mask 92 (eTPWM2 Interrupt)" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 27. 0x00 27. 0x10 27. " [91] ,Wake Up Mask 91 (eTPWM1 Trip Zone Interrupt)" "Disabled,Enabled"
setclrfld.long 0x00 26. 0x00 26. 0x10 26. " [90] ,Wake Up Mask 90 (eTPWM1 Interrupt)" "Disabled,Enabled"
setclrfld.long 0x00 25. 0x00 25. 0x10 25. " [89] ,Wake Up Mask 89 (HWA_INT_REQ_L)" "Disabled,Enabled"
setclrfld.long 0x00 24. 0x00 24. 0x10 24. " [88] ,Wake Up Mask 88 (HWA_INT_REQ_L)" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 23. 0x00 23. 0x10 23. " [87] ,Wake Up Mask 87 (IMM Interrupt 1)" "Disabled,Enabled"
setclrfld.long 0x00 22. 0x00 22. 0x10 22. " [86] ,Wake Up Mask 86 (IMM Interrupt 0)" "Disabled,Enabled"
setclrfld.long 0x00 21. 0x00 21. 0x10 21. " [85] ,Wake Up Mask 85 (PBIST Done)" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 19. 0x00 19. 0x10 19. " [83] ,Wake Up Mask 83 (DCC2 done interrupt)" "Disabled,Enabled"
setclrfld.long 0x00 18. 0x00 18. 0x10 18. " [82] ,Wake Up Mask 82 (DCC1 done interrupt)" "Disabled,Enabled"
setclrfld.long 0x00 17. 0x00 17. 0x10 17. " [81] ,Wake Up Mask 81 (HWA_INT_REQ_H)" "Disabled,Enabled"
setclrfld.long 0x00 16. 0x00 16. 0x10 16. " [80] ,Wake Up Mask 80 (HWA_INT_REQ_H)" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 15. 0x00 15. 0x10 15. " [79] ,Wake Up Mask 79 (C0_RX_PULSE)" "Disabled,Enabled"
setclrfld.long 0x00 14. 0x00 14. 0x10 14. " [78] ,Wake Up Mask 78 (C0_THRESH_PULSE)" "Disabled,Enabled"
setclrfld.long 0x00 13. 0x00 13. 0x10 13. " [77] ,Wake Up Mask 77 (C0_TX_PULSE)" "Disabled,Enabled"
setclrfld.long 0x00 12. 0x00 12. 0x10 12. " [76] ,Wake Up Mask 76 (C0_MISC_PULSE)" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 11. 0x00 11. 0x10 11. " [75] ,Wake Up Mask 75 (NHET TU2 level 1 interrupt)" "Disabled,Enabled"
setclrfld.long 0x00 10. 0x00 10. 0x10 10. " [74] ,Wake Up Mask 74 (SCI3 level 1 interrupt)" "Disabled,Enabled"
setclrfld.long 0x00 9. 0x00 9. 0x10 9. " [73] ,Wake Up Mask 73 (NHET2 level 1 interrupt)" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 2. 0x00 2. 0x10 2. " [66] ,Wake Up Mask 66 (I2C level 0 interrupt)" "Disabled,Enabled"
setclrfld.long 0x00 1. 0x00 1. 0x10 1. " [65] ,Wake Up Mask 65 (NHET TU2 level 0 interrupt)" "Disabled,Enabled"
setclrfld.long 0x00 0. 0x00 0. 0x10 0. " [64] ,Wake Up Mask 64 (SCI3 level 0 interrupt)" "Disabled,Enabled"
group.long 0x5C++0x3
line.long 0x0 "WAKEENASET3,Wake-up Mask Set Register"
setclrfld.long 0x00 28. 0x00 28. 0x10 28. " WAKEMASK_set/clr_[124] ,Wake Up Mask 124 (EPC FIFO FULL or CAM FULL interrupt)" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 25. 0x00 25. 0x10 25. " [121] ,Wake Up Mask 121 (CRC2 Interrupt)" "Disabled,Enabled"
setclrfld.long 0x00 24. 0x00 24. 0x10 24. " [120] ,Wake Up Mask 120 (DCAN4 IF3 Interrupt)" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 23. 0x00 23. 0x10 23. " [119] ,Wake Up Mask 119 (SCI4 level 1 interrupt)" "Disabled,Enabled"
setclrfld.long 0x00 22. 0x00 22. 0x10 22. " [118] ,Wake Up Mask 118 (LIN2 level 1 interrupt)" "Disabled,Enabled"
setclrfld.long 0x00 21. 0x00 21. 0x10 21. " [117] ,Wake Up Mask 117 (DCAN4 Level 1 interrupt)" "Disabled,Enabled"
setclrfld.long 0x00 20. 0x00 20. 0x10 20. " [116] ,Wake Up Mask 116 (SCI4 level 0 interrupt)" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 19. 0x00 19. 0x10 19. " [115] ,Wake Up Mask 115 (LIN2 level 0 interrupt)" "Disabled,Enabled"
setclrfld.long 0x00 18. 0x00 18. 0x10 18. " [114] ,Wake Up Mask 114 (I2C2 interrupt)" "Disabled,Enabled"
setclrfld.long 0x00 17. 0x00 17. 0x10 17. " [113] ,Wake Up Mask 113 (DCAN4 Level 0 interrupt)" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 15. 0x00 15. 0x10 15. " [111] ,Wake Up Mask 111 (eQEP2 Interrupt)" "Disabled,Enabled"
setclrfld.long 0x00 14. 0x00 14. 0x10 14. " [110] ,Wake Up Mask 110 (eQEP1 Interrupt)" "Disabled,Enabled"
setclrfld.long 0x00 13. 0x00 13. 0x10 13. " [109] ,Wake Up Mask 109 (eCAP6 Interrupt)" "Disabled,Enabled"
setclrfld.long 0x00 12. 0x00 12. 0x10 12. " [108] ,Wake Up Mask 108 (eCAP5 Interrupt)" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 11. 0x00 11. 0x10 11. " [107] ,Wake Up Mask 107 (eCAP4 Interrupt)" "Disabled,Enabled"
setclrfld.long 0x00 10. 0x00 10. 0x10 10. " [106] ,Wake Up Mask 106 (eCAP3 Interrupt)" "Disabled,Enabled"
setclrfld.long 0x00 9. 0x00 9. 0x10 9. " [105] ,Wake Up Mask 105 (eCAP2 Interrupt)" "Disabled,Enabled"
setclrfld.long 0x00 8. 0x00 8. 0x10 8. " [104] ,Wake Up Mask 104 (eCAP1 Interrupt)" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 7. 0x00 7. 0x10 7. " [103] ,Wake Up Mask 103 (eTPWM7 Trip Zone Interrupt)" "Disabled,Enabled"
setclrfld.long 0x00 6. 0x00 6. 0x10 6. " [102] ,Wake Up Mask 102 (eTPWM7 Interrupt)" "Disabled,Enabled"
setclrfld.long 0x00 5. 0x00 5. 0x10 5. " [101] ,Wake Up Mask 101 (eTPWM6 Trip Zone Interrupt)" "Disabled,Enabled"
setclrfld.long 0x00 4. 0x00 4. 0x10 4. " [100] ,Wake Up Mask 100 (eTPWM6 Interrupt)" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 3. 0x00 3. 0x10 3. " [99] ,Wake Up Mask 99 (eTPWM5 Trip Zone Interrupt)" "Disabled,Enabled"
setclrfld.long 0x00 2. 0x00 2. 0x10 2. " [98] ,Wake Up Mask 98 (eTPWM5 Interrupt)" "Disabled,Enabled"
setclrfld.long 0x00 1. 0x00 1. 0x10 1. " [97] ,Wake Up Mask 97 (eTPWM4 Trip Zone Interrupt)" "Disabled,Enabled"
setclrfld.long 0x00 0. 0x00 0. 0x10 0. " [96] ,Wake Up Mask 96 (eTPWM4 Interrupt)" "Disabled,Enabled"
tree.end
width 11.
tree "VIM Interrupt Vector Registers"
rgroup.long 0x70++0x7
line.long 0x0 "IRQVECREG,IRQ Interrupt Vector Register"
line.long 0x4 "FIQVECREG,FIQ Interrupt Vector Register"
tree.end
textline " "
group.long 0x78++0x3
line.long 0x0 "CAPEVT,Capture Event register"
hexmask.long.byte 0x00 16.--22. 1. " CAPEVTSRC1[6:0] ,Capture Event Source 1 Mapping Control"
hexmask.long.byte 0x00 0.--6. 1. " CAPEVTSRC0[6:0] ,Capture Event Source 0 Mapping Control"
width 12.
tree "VIM Interrupt Control Registers"
group.long 0x80++0x7F
line.long 0x0 "CHANCTRL0,VIM Interrupt Control Register 0"
hexmask.long.byte 0x00 24.--30. 1. " CHANMAP0[6:0] ,Interrupt CHAN0 Mapping Control"
hexmask.long.byte 0x00 16.--22. 1. " CHANMAP1[6:0] ,Interrupt CHAN1 Mapping Control"
hexmask.long.byte 0x00 8.--14. 1. " CHANMAP2[6:0] ,Interrupt CHAN2 Mapping Control"
hexmask.long.byte 0x00 0.--6. 1. " CHANMAP3[6:0] ,Interrupt CHAN3 Mapping Control"
line.long 0x4 "CHANCTRL1,VIM Interrupt Control Register 1"
hexmask.long.byte 0x04 24.--30. 1. " CHANMAP4[6:0] ,Interrupt CHAN4 Mapping Control"
hexmask.long.byte 0x04 16.--22. 1. " CHANMAP5[6:0] ,Interrupt CHAN5 Mapping Control"
hexmask.long.byte 0x04 8.--14. 1. " CHANMAP6[6:0] ,Interrupt CHAN6 Mapping Control"
hexmask.long.byte 0x04 0.--6. 1. " CHANMAP7[6:0] ,Interrupt CHAN7 Mapping Control"
line.long 0x8 "CHANCTRL2,VIM Interrupt Control Register 2"
hexmask.long.byte 0x08 24.--30. 1. " CHANMAP8[6:0] ,Interrupt CHAN8 Mapping Control"
hexmask.long.byte 0x08 16.--22. 1. " CHANMAP9[6:0] ,Interrupt CHAN9 Mapping Control"
hexmask.long.byte 0x08 8.--14. 1. " CHANMAP10[6:0] ,Interrupt CHAN10 Mapping Control"
hexmask.long.byte 0x08 0.--6. 1. " CHANMAP11[6:0] ,Interrupt CHAN11 Mapping Control"
line.long 0xc "CHANCTRL3,VIM Interrupt Control Register 3"
hexmask.long.byte 0x0c 24.--30. 1. " CHANMAP12[6:0] ,Interrupt CHAN12 Mapping Control"
hexmask.long.byte 0x0c 16.--22. 1. " CHANMAP13[6:0] ,Interrupt CHAN13 Mapping Control"
hexmask.long.byte 0x0c 8.--14. 1. " CHANMAP14[6:0] ,Interrupt CHAN14 Mapping Control"
hexmask.long.byte 0x0c 0.--6. 1. " CHANMAP15[6:0] ,Interrupt CHAN15 Mapping Control"
line.long 0x10 "CHANCTRL4,VIM Interrupt Control Register 4"
hexmask.long.byte 0x10 24.--30. 1. " CHANMAP16[6:0] ,Interrupt CHAN16 Mapping Control"
hexmask.long.byte 0x10 16.--22. 1. " CHANMAP17[6:0] ,Interrupt CHAN17 Mapping Control"
hexmask.long.byte 0x10 8.--14. 1. " CHANMAP18[6:0] ,Interrupt CHAN18 Mapping Control"
hexmask.long.byte 0x10 0.--6. 1. " CHANMAP19[6:0] ,Interrupt CHAN19 Mapping Control"
line.long 0x14 "CHANCTRL5,VIM Interrupt Control Register 5"
hexmask.long.byte 0x14 24.--30. 1. " CHANMAP20[6:0] ,Interrupt CHAN20 Mapping Control"
hexmask.long.byte 0x14 16.--22. 1. " CHANMAP21[6:0] ,Interrupt CHAN21 Mapping Control"
hexmask.long.byte 0x14 8.--14. 1. " CHANMAP22[6:0] ,Interrupt CHAN22 Mapping Control"
hexmask.long.byte 0x14 0.--6. 1. " CHANMAP23[6:0] ,Interrupt CHAN23 Mapping Control"
line.long 0x18 "CHANCTRL6,VIM Interrupt Control Register 6"
hexmask.long.byte 0x18 24.--30. 1. " CHANMAP24[6:0] ,Interrupt CHAN24 Mapping Control"
hexmask.long.byte 0x18 16.--22. 1. " CHANMAP25[6:0] ,Interrupt CHAN25 Mapping Control"
hexmask.long.byte 0x18 8.--14. 1. " CHANMAP26[6:0] ,Interrupt CHAN26 Mapping Control"
hexmask.long.byte 0x18 0.--6. 1. " CHANMAP27[6:0] ,Interrupt CHAN27 Mapping Control"
line.long 0x1c "CHANCTRL7,VIM Interrupt Control Register 7"
hexmask.long.byte 0x1c 24.--30. 1. " CHANMAP28[6:0] ,Interrupt CHAN28 Mapping Control"
hexmask.long.byte 0x1c 16.--22. 1. " CHANMAP29[6:0] ,Interrupt CHAN29 Mapping Control"
hexmask.long.byte 0x1c 8.--14. 1. " CHANMAP30[6:0] ,Interrupt CHAN30 Mapping Control"
hexmask.long.byte 0x1c 0.--6. 1. " CHANMAP31[6:0] ,Interrupt CHAN31 Mapping Control"
line.long 0x20 "CHANCTRL8,VIM Interrupt Control Register 8"
hexmask.long.byte 0x20 24.--30. 1. " CHANMAP32[6:0] ,Interrupt CHAN32 Mapping Control"
hexmask.long.byte 0x20 16.--22. 1. " CHANMAP33[6:0] ,Interrupt CHAN33 Mapping Control"
hexmask.long.byte 0x20 8.--14. 1. " CHANMAP34[6:0] ,Interrupt CHAN34 Mapping Control"
hexmask.long.byte 0x20 0.--6. 1. " CHANMAP35[6:0] ,Interrupt CHAN35 Mapping Control"
line.long 0x24 "CHANCTRL9,VIM Interrupt Control Register 9"
hexmask.long.byte 0x24 24.--30. 1. " CHANMAP36[6:0] ,Interrupt CHAN36 Mapping Control"
hexmask.long.byte 0x24 16.--22. 1. " CHANMAP37[6:0] ,Interrupt CHAN37 Mapping Control"
hexmask.long.byte 0x24 8.--14. 1. " CHANMAP38[6:0] ,Interrupt CHAN38 Mapping Control"
hexmask.long.byte 0x24 0.--6. 1. " CHANMAP39[6:0] ,Interrupt CHAN39 Mapping Control"
line.long 0x28 "CHANCTRL10,VIM Interrupt Control Register 10"
hexmask.long.byte 0x28 24.--30. 1. " CHANMAP40[6:0] ,Interrupt CHAN40 Mapping Control"
hexmask.long.byte 0x28 16.--22. 1. " CHANMAP41[6:0] ,Interrupt CHAN41 Mapping Control"
hexmask.long.byte 0x28 8.--14. 1. " CHANMAP42[6:0] ,Interrupt CHAN42 Mapping Control"
hexmask.long.byte 0x28 0.--6. 1. " CHANMAP43[6:0] ,Interrupt CHAN43 Mapping Control"
line.long 0x2c "CHANCTRL11,VIM Interrupt Control Register 11"
hexmask.long.byte 0x2c 24.--30. 1. " CHANMAP44[6:0] ,Interrupt CHAN44 Mapping Control"
hexmask.long.byte 0x2c 16.--22. 1. " CHANMAP45[6:0] ,Interrupt CHAN45 Mapping Control"
hexmask.long.byte 0x2c 8.--14. 1. " CHANMAP46[6:0] ,Interrupt CHAN46 Mapping Control"
hexmask.long.byte 0x2c 0.--6. 1. " CHANMAP45[6:0] ,Interrupt CHAN45 Mapping Control"
line.long 0x30 "CHANCTRL12,VIM Interrupt Control Register 12"
hexmask.long.byte 0x30 24.--30. 1. " CHANMAP48[6:0] ,Interrupt CHAN48 Mapping Control"
hexmask.long.byte 0x30 16.--22. 1. " CHANMAP49[6:0] ,Interrupt CHAN49 Mapping Control"
hexmask.long.byte 0x30 8.--14. 1. " CHANMAP50[6:0] ,Interrupt CHAN50 Mapping Control"
hexmask.long.byte 0x30 0.--6. 1. " CHANMAP51[6:0] ,Interrupt CHAN51 Mapping Control"
line.long 0x34 "CHANCTRL13,VIM Interrupt Control Register 13"
hexmask.long.byte 0x34 24.--30. 1. " CHANMAP52[6:0] ,Interrupt CHAN52 Mapping Control"
hexmask.long.byte 0x34 16.--22. 1. " CHANMAP53[6:0] ,Interrupt CHAN53 Mapping Control"
hexmask.long.byte 0x34 8.--14. 1. " CHANMAP54[6:0] ,Interrupt CHAN54 Mapping Control"
hexmask.long.byte 0x34 0.--6. 1. " CHANMAP55[6:0] ,Interrupt CHAN55 Mapping Control"
line.long 0x38 "CHANCTRL14,VIM Interrupt Control Register 14"
hexmask.long.byte 0x38 24.--30. 1. " CHANMAP56[6:0] ,Interrupt CHAN56 Mapping Control"
hexmask.long.byte 0x38 16.--22. 1. " CHANMAP57[6:0] ,Interrupt CHAN57 Mapping Control"
hexmask.long.byte 0x38 8.--14. 1. " CHANMAP58[6:0] ,Interrupt CHAN58 Mapping Control"
hexmask.long.byte 0x38 0.--6. 1. " CHANMAP59[6:0] ,Interrupt CHAN59 Mapping Control"
line.long 0x3c "CHANCTRL15,VIM Interrupt Control Register 15"
hexmask.long.byte 0x3c 24.--30. 1. " CHANMAP60[6:0] ,Interrupt CHAN60 Mapping Control"
hexmask.long.byte 0x3c 16.--22. 1. " CHANMAP61[6:0] ,Interrupt CHAN61 Mapping Control"
hexmask.long.byte 0x3c 8.--14. 1. " CHANMAP62[6:0] ,Interrupt CHAN62 Mapping Control"
hexmask.long.byte 0x3c 0.--6. 1. " CHANMAP63[6:0] ,Interrupt CHAN63 Mapping Control"
line.long 0x40 "CHANCTRL16,VIM Interrupt Control Register 16"
hexmask.long.byte 0x40 24.--30. 1. " CHANMAP64[6:0] ,Interrupt CHAN64 Mapping Control"
hexmask.long.byte 0x40 16.--22. 1. " CHANMAP65[6:0] ,Interrupt CHAN65 Mapping Control"
hexmask.long.byte 0x40 8.--14. 1. " CHANMAP66[6:0] ,Interrupt CHAN66 Mapping Control"
hexmask.long.byte 0x40 0.--6. 1. " CHANMAP67[6:0] ,Interrupt CHAN67 Mapping Control"
line.long 0x44 "CHANCTRL17,VIM Interrupt Control Register 17"
hexmask.long.byte 0x44 24.--30. 1. " CHANMAP68[6:0] ,Interrupt CHAN68 Mapping Control"
hexmask.long.byte 0x44 16.--22. 1. " CHANMAP69[6:0] ,Interrupt CHAN69 Mapping Control"
hexmask.long.byte 0x44 8.--14. 1. " CHANMAP70[6:0] ,Interrupt CHAN70 Mapping Control"
hexmask.long.byte 0x44 0.--6. 1. " CHANMAP71[6:0] ,Interrupt CHAN71 Mapping Control"
line.long 0x48 "CHANCTRL18,VIM Interrupt Control Register 18"
hexmask.long.byte 0x48 24.--30. 1. " CHANMAP72[6:0] ,Interrupt CHAN72 Mapping Control"
hexmask.long.byte 0x48 16.--22. 1. " CHANMAP73[6:0] ,Interrupt CHAN73 Mapping Control"
hexmask.long.byte 0x48 8.--14. 1. " CHANMAP74[6:0] ,Interrupt CHAN74 Mapping Control"
hexmask.long.byte 0x48 0.--6. 1. " CHANMAP75[6:0] ,Interrupt CHAN75 Mapping Control"
line.long 0x4C "CHANCTRL19,VIM Interrupt Control Register 19"
hexmask.long.byte 0x4C 24.--30. 1. " CHANMAP76[6:0] ,Interrupt CHAN76 Mapping Control"
hexmask.long.byte 0x4C 16.--22. 1. " CHANMAP77[6:0] ,Interrupt CHAN77 Mapping Control"
hexmask.long.byte 0x4C 8.--14. 1. " CHANMAP78[6:0] ,Interrupt CHAN78 Mapping Control"
hexmask.long.byte 0x4C 0.--6. 1. " CHANMAP79[6:0] ,Interrupt CHAN79 Mapping Control"
line.long 0x50 "CHANCTRL20,VIM Interrupt Control Register 20"
hexmask.long.byte 0x50 24.--30. 1. " CHANMAP80[6:0] ,Interrupt CHAN80 Mapping Control"
hexmask.long.byte 0x50 16.--22. 1. " CHANMAP81[6:0] ,Interrupt CHAN81 Mapping Control"
hexmask.long.byte 0x50 8.--14. 1. " CHANMAP82[6:0] ,Interrupt CHAN82 Mapping Control"
hexmask.long.byte 0x50 0.--6. 1. " CHANMAP83[6:0] ,Interrupt CHAN83 Mapping Control"
line.long 0x54 "CHANCTRL21,VIM Interrupt Control Register 21"
hexmask.long.byte 0x54 24.--30. 1. " CHANMAP84[6:0] ,Interrupt CHAN84 Mapping Control"
hexmask.long.byte 0x54 16.--22. 1. " CHANMAP85[6:0] ,Interrupt CHAN85 Mapping Control"
hexmask.long.byte 0x54 8.--14. 1. " CHANMAP86[6:0] ,Interrupt CHAN86 Mapping Control"
hexmask.long.byte 0x54 0.--6. 1. " CHANMAP87[6:0] ,Interrupt CHAN87 Mapping Control"
line.long 0x58 "CHANCTRL22,VIM Interrupt Control Register 22"
hexmask.long.byte 0x58 24.--30. 1. " CHANMAP88[6:0] ,Interrupt CHAN88 Mapping Control"
hexmask.long.byte 0x58 16.--22. 1. " CHANMAP89[6:0] ,Interrupt CHAN89 Mapping Control"
hexmask.long.byte 0x58 8.--14. 1. " CHANMAP90[6:0] ,Interrupt CHAN90 Mapping Control"
hexmask.long.byte 0x58 0.--6. 1. " CHANMAP91[6:0] ,Interrupt CHAN91 Mapping Control"
line.long 0x5C "CHANCTRL23,VIM Interrupt Control Register 23"
hexmask.long.byte 0x5C 24.--30. 1. " CHANMAP92[6:0] ,Interrupt CHAN92 Mapping Control"
hexmask.long.byte 0x5C 16.--22. 1. " CHANMAP93[6:0] ,Interrupt CHAN93 Mapping Control"
hexmask.long.byte 0x5C 8.--14. 1. " CHANMAP94[6:0] ,Interrupt CHAN94 Mapping Control"
hexmask.long.byte 0x5C 0.--6. 1. " CHANMAP95[6:0] ,Interrupt CHAN95 Mapping Control"
line.long 0x60 "CHANCTRL24,VIM Interrupt Control Register 24"
hexmask.long.byte 0x60 24.--30. 1. " CHANMAP96[6:0] ,Interrupt CHAN96 Mapping Control"
hexmask.long.byte 0x60 16.--22. 1. " CHANMAP97[6:0] ,Interrupt CHAN97 Mapping Control"
hexmask.long.byte 0x60 8.--14. 1. " CHANMAP98[6:0] ,Interrupt CHAN98 Mapping Control"
hexmask.long.byte 0x60 0.--6. 1. " CHANMAP99[6:0] ,Interrupt CHAN99 Mapping Control"
line.long 0x64 "CHANCTRL25,VIM Interrupt Control Register 25"
hexmask.long.byte 0x64 24.--30. 1. " CHANMAP100[6:0] ,Interrupt CHAN100 Mapping Control"
hexmask.long.byte 0x64 16.--22. 1. " CHANMAP101[6:0] ,Interrupt CHAN101 Mapping Control"
hexmask.long.byte 0x64 8.--14. 1. " CHANMAP102[6:0] ,Interrupt CHAN102 Mapping Control"
hexmask.long.byte 0x64 0.--6. 1. " CHANMAP103[6:0] ,Interrupt CHAN103 Mapping Control"
line.long 0x68 "CHANCTRL26,VIM Interrupt Control Register 26"
hexmask.long.byte 0x68 24.--30. 1. " CHANMAP104[6:0] ,Interrupt CHAN104 Mapping Control"
hexmask.long.byte 0x68 16.--22. 1. " CHANMAP105[6:0] ,Interrupt CHAN105 Mapping Control"
hexmask.long.byte 0x68 8.--14. 1. " CHANMAP106[6:0] ,Interrupt CHAN106 Mapping Control"
hexmask.long.byte 0x68 0.--6. 1. " CHANMAP107[6:0] ,Interrupt CHAN107 Mapping Control"
line.long 0x6C "CHANCTRL27,VIM Interrupt Control Register 27"
hexmask.long.byte 0x6C 24.--30. 1. " CHANMAP108[6:0] ,Interrupt CHAN108 Mapping Control"
hexmask.long.byte 0x6C 16.--22. 1. " CHANMAP109[6:0] ,Interrupt CHAN109 Mapping Control"
hexmask.long.byte 0x6C 8.--14. 1. " CHANMAP110[6:0] ,Interrupt CHAN110 Mapping Control"
hexmask.long.byte 0x6C 0.--6. 1. " CHANMAP111[6:0] ,Interrupt CHAN111 Mapping Control"
line.long 0x70 "CHANCTRL28,VIM Interrupt Control Register 28"
hexmask.long.byte 0x70 24.--30. 1. " CHANMAP112[6:0] ,Interrupt CHAN112 Mapping Control"
hexmask.long.byte 0x70 16.--22. 1. " CHANMAP113[6:0] ,Interrupt CHAN113 Mapping Control"
hexmask.long.byte 0x70 8.--14. 1. " CHANMAP114[6:0] ,Interrupt CHAN114 Mapping Control"
hexmask.long.byte 0x70 0.--6. 1. " CHANMAP115[6:0] ,Interrupt CHAN115 Mapping Control"
line.long 0x74 "CHANCTRL29,VIM Interrupt Control Register 29"
hexmask.long.byte 0x74 24.--30. 1. " CHANMAP116[6:0] ,Interrupt CHAN116 Mapping Control"
hexmask.long.byte 0x74 16.--22. 1. " CHANMAP117[6:0] ,Interrupt CHAN117 Mapping Control"
hexmask.long.byte 0x74 8.--14. 1. " CHANMAP118[6:0] ,Interrupt CHAN118 Mapping Control"
hexmask.long.byte 0x74 0.--6. 1. " CHANMAP119[6:0] ,Interrupt CHAN119 Mapping Control"
line.long 0x78 "CHANCTRL30,VIM Interrupt Control Register 30"
hexmask.long.byte 0x78 24.--30. 1. " CHANMAP120[6:0] ,Interrupt CHAN120 Mapping Control"
hexmask.long.byte 0x78 16.--22. 1. " CHANMAP121[6:0] ,Interrupt CHAN121 Mapping Control"
hexmask.long.byte 0x78 8.--14. 1. " CHANMAP122[6:0] ,Interrupt CHAN122 Mapping Control"
hexmask.long.byte 0x78 0.--6. 1. " CHANMAP123[6:0] ,Interrupt CHAN123 Mapping Control"
line.long 0x7C "CHANCTRL31,VIM Interrupt Control Register 31"
hexmask.long.byte 0x7C 24.--30. 1. " CHANMAP124[6:0] ,Interrupt CHAN124 Mapping Control"
hexmask.long.byte 0x7C 16.--22. 1. " CHANMAP125[6:0] ,Interrupt CHAN125 Mapping Control"
hexmask.long.byte 0x7C 8.--14. 1. " CHANMAP126[6:0] ,Interrupt CHAN126 Mapping Control"
hexmask.long.byte 0x7C 0.--6. 1. " CHANMAP127[6:0] ,Interrupt CHAN127 Mapping Control"
tree.end
width 0x0B
tree.end
tree "DMA (Direct Memory Access Controller Module)"
base ad:0xFFFFF000
width 9.
group.long 0x00++0x03
line.long 0x00 "GCTRL,GLOBAL CONTROL Register"
bitfld.long 0x00 16. " DMA_EN ,DMA enable" "Disabled,Enabled"
rbitfld.long 0x00 14. " BUS_BUSY ,DMA external AHB bus status" "Not busy,Busy"
bitfld.long 0x00 8.--9. " DEBUG_MODE[1:0] ,Debug mode" "Suspend ignored,Block finished,Frame finished,Immediate stop"
textline " "
bitfld.long 0x00 0. " DMA_RES ,DMA software reset" "No reset,Reset"
textline " "
rgroup.long 0x04++0x03
line.long 0x00 "PEND,CHANNEL PENDING Register"
bitfld.long 0x00 31. " PEND_[31] ,Channel pending 31 register" "Inactive,Pending"
bitfld.long 0x00 30. " [30] ,Channel pending 30 register" "Inactive,Pending"
bitfld.long 0x00 29. " [29] ,Channel pending 29 register" "Inactive,Pending"
bitfld.long 0x00 28. " [28] ,Channel pending 28 register" "Inactive,Pending"
bitfld.long 0x00 27. " [27] ,Channel pending 27 register" "Inactive,Pending"
bitfld.long 0x00 26. " [26] ,Channel pending 26 register" "Inactive,Pending"
textline " "
bitfld.long 0x00 25. " [25] ,Channel pending 25 register" "Inactive,Pending"
bitfld.long 0x00 24. " [24] ,Channel pending 24 register" "Inactive,Pending"
bitfld.long 0x00 23. " [23] ,Channel pending 23 register" "Inactive,Pending"
bitfld.long 0x00 22. " [22] ,Channel pending 22 register" "Inactive,Pending"
bitfld.long 0x00 21. " [21] ,Channel pending 21 register" "Inactive,Pending"
bitfld.long 0x00 20. " [20] ,Channel pending 20 register" "Inactive,Pending"
textline " "
bitfld.long 0x00 19. " [19] ,Channel pending 19 register" "Inactive,Pending"
bitfld.long 0x00 18. " [18] ,Channel pending 18 register" "Inactive,Pending"
bitfld.long 0x00 17. " [17] ,Channel pending 17 register" "Inactive,Pending"
bitfld.long 0x00 16. " [16] ,Channel pending 16 register" "Inactive,Pending"
bitfld.long 0x00 15. " [15] ,Channel pending 15 register" "Inactive,Pending"
bitfld.long 0x00 14. " [14] ,Channel pending 14 register" "Inactive,Pending"
textline " "
bitfld.long 0x00 13. " [13] ,Channel pending 13 register" "Inactive,Pending"
bitfld.long 0x00 12. " [12] ,Channel pending 12 register" "Inactive,Pending"
bitfld.long 0x00 11. " [11] ,Channel pending 11 register" "Inactive,Pending"
bitfld.long 0x00 10. " [10] ,Channel pending 10 register" "Inactive,Pending"
bitfld.long 0x00 9. " [9] ,Channel pending 9 register" "Inactive,Pending"
bitfld.long 0x00 8. " [8] ,Channel pending 8 register" "Inactive,Pending"
textline " "
bitfld.long 0x00 7. " [7] ,Channel pending 7 register" "Inactive,Pending"
bitfld.long 0x00 6. " [6] ,Channel pending 6 register" "Inactive,Pending"
bitfld.long 0x00 5. " [5] ,Channel pending 5 register" "Inactive,Pending"
bitfld.long 0x00 4. " [4] ,Channel pending 4 register" "Inactive,Pending"
bitfld.long 0x00 3. " [3] ,Channel pending 3 register" "Inactive,Pending"
bitfld.long 0x00 2. " [2] ,Channel pending 2 register" "Inactive,Pending"
textline " "
bitfld.long 0x00 1. " [1] ,Channel pending 1 register" "Inactive,Pending"
bitfld.long 0x00 0. " [0] ,Channel pending 0 register" "Inactive,Pending"
rgroup.long 0x0C++0x03
line.long 0x00 "DMASTAT,DMA STATUS Register"
bitfld.long 0x00 31. " STCH_[31] ,Status of DMA channel 31" "Inactive,Active"
bitfld.long 0x00 30. " [30] ,Status of DMA channel 30" "Inactive,Active"
bitfld.long 0x00 29. " [29] ,Status of DMA channel 29" "Inactive,Active"
bitfld.long 0x00 28. " [28] ,Status of DMA channel 28" "Inactive,Active"
bitfld.long 0x00 27. " [27] ,Status of DMA channel 27" "Inactive,Active"
bitfld.long 0x00 26. " [26] ,Status of DMA channel 26" "Inactive,Active"
textline " "
bitfld.long 0x00 25. " [25] ,Status of DMA channel 25" "Inactive,Active"
bitfld.long 0x00 24. " [24] ,Status of DMA channel 24" "Inactive,Active"
bitfld.long 0x00 23. " [23] ,Status of DMA channel 23" "Inactive,Active"
bitfld.long 0x00 22. " [22] ,Status of DMA channel 22" "Inactive,Active"
bitfld.long 0x00 21. " [21] ,Status of DMA channel 21" "Inactive,Active"
bitfld.long 0x00 20. " [20] ,Status of DMA channel 20" "Inactive,Active"
textline " "
bitfld.long 0x00 19. " [19] ,Status of DMA channel 19" "Inactive,Active"
bitfld.long 0x00 18. " [18] ,Status of DMA channel 18" "Inactive,Active"
bitfld.long 0x00 17. " [17] ,Status of DMA channel 17" "Inactive,Active"
bitfld.long 0x00 16. " [16] ,Status of DMA channel 16" "Inactive,Active"
bitfld.long 0x00 15. " [15] ,Status of DMA channel 15" "Inactive,Active"
bitfld.long 0x00 14. " [14] ,Status of DMA channel 14" "Inactive,Active"
textline " "
bitfld.long 0x00 13. " [13] ,Status of DMA channel 13" "Inactive,Active"
bitfld.long 0x00 12. " [12] ,Status of DMA channel 12" "Inactive,Active"
bitfld.long 0x00 11. " [11] ,Status of DMA channel 11" "Inactive,Active"
bitfld.long 0x00 10. " [10] ,Status of DMA channel 10" "Inactive,Active"
bitfld.long 0x00 9. " [9] ,Status of DMA channel 9" "Inactive,Active"
bitfld.long 0x00 8. " [8] ,Status of DMA channel 8" "Inactive,Active"
textline " "
bitfld.long 0x00 7. " [7] ,Status of DMA channel 7" "Inactive,Active"
bitfld.long 0x00 6. " [6] ,Status of DMA channel 6" "Inactive,Active"
bitfld.long 0x00 5. " [5] ,Status of DMA channel 5" "Inactive,Active"
bitfld.long 0x00 4. " [4] ,Status of DMA channel 4" "Inactive,Active"
bitfld.long 0x00 3. " [3] ,Status of DMA channel 3" "Inactive,Active"
bitfld.long 0x00 2. " [2] ,Status of DMA channel 2" "Inactive,Active"
textline " "
bitfld.long 0x00 1. " [1] ,Status of DMA channel 1" "Inactive,Active"
bitfld.long 0x00 0. " [0] ,Status of DMA channel 0" "Inactive,Active"
textline " "
rgroup.long 0x10++0x03
line.long 0x00 "REVID,Revision ID Register"
bitfld.long 0x00 30.--31. " SCHEME ,Identification scheme" "0,1,2,3"
hexmask.long.word 0x00 16.--27. 1. " FUNC ,Module family"
bitfld.long 0x00 8.--10. " MAJOR ,Major revision number" "0,1,2,3,4,5,6,7"
textline " "
bitfld.long 0x00 0.--5. " MINOR ,Minor revision number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
width 9.
tree "Channel Enable Status Registers"
group.long 0x14++0x03
line.long 0x00 "HWCHENA,HWCHANNEL Enable Register"
setclrfld.long 0x00 31. 0x00 31. 0x08 31. " HWCHENA_SET/CLR_[31] ,HW channel 31 enable" "Disabled,Enabled"
setclrfld.long 0x00 30. 0x00 30. 0x08 30. " [30] ,HW channel 30 enable" "Disabled,Enabled"
setclrfld.long 0x00 29. 0x00 29. 0x08 29. " [29] ,HW channel 29 enable" "Disabled,Enabled"
setclrfld.long 0x00 28. 0x00 28. 0x08 28. " [28] ,HW channel 28 enable" "Disabled,Enabled"
setclrfld.long 0x00 27. 0x00 27. 0x08 27. " [27] ,HW channel 27 enable" "Disabled,Enabled"
setclrfld.long 0x00 26. 0x00 26. 0x08 26. " [26] ,HW channel 26 enable" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 25. 0x00 25. 0x08 25. " [25] ,HW channel 25 enable" "Disabled,Enabled"
setclrfld.long 0x00 24. 0x00 24. 0x08 24. " [24] ,HW channel 24 enable" "Disabled,Enabled"
setclrfld.long 0x00 23. 0x00 23. 0x08 23. " [23] ,HW channel 23 enable" "Disabled,Enabled"
setclrfld.long 0x00 22. 0x00 22. 0x08 22. " [22] ,HW channel 22 enable" "Disabled,Enabled"
setclrfld.long 0x00 21. 0x00 21. 0x08 21. " [21] ,HW channel 21 enable" "Disabled,Enabled"
setclrfld.long 0x00 20. 0x00 20. 0x08 20. " [20] ,HW channel 20 enable" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 19. 0x00 19. 0x08 19. " [19] ,HW channel 19 enable" "Disabled,Enabled"
setclrfld.long 0x00 18. 0x00 18. 0x08 18. " [18] ,HW channel 18 enable" "Disabled,Enabled"
setclrfld.long 0x00 17. 0x00 17. 0x08 17. " [17] ,HW channel 17 enable" "Disabled,Enabled"
setclrfld.long 0x00 16. 0x00 16. 0x08 16. " [16] ,HW channel 16 enable" "Disabled,Enabled"
setclrfld.long 0x00 15. 0x00 15. 0x08 15. " [15] ,HW channel 15 enable" "Disabled,Enabled"
setclrfld.long 0x00 14. 0x00 14. 0x08 14. " [14] ,HW channel 14 enable" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 13. 0x00 13. 0x08 13. " [13] ,HW channel 13 enable" "Disabled,Enabled"
setclrfld.long 0x00 12. 0x00 12. 0x08 12. " [12] ,HW channel 12 enable" "Disabled,Enabled"
setclrfld.long 0x00 11. 0x00 11. 0x08 11. " [11] ,HW channel 11 enable" "Disabled,Enabled"
setclrfld.long 0x00 10. 0x00 10. 0x08 10. " [10] ,HW channel 10 enable" "Disabled,Enabled"
setclrfld.long 0x00 9. 0x00 9. 0x08 9. " [9] ,HW channel 9 enable" "Disabled,Enabled"
setclrfld.long 0x00 8. 0x00 8. 0x08 8. " [8] ,HW channel 8 enable" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 7. 0x00 7. 0x08 7. " [7] ,HW channel 7 enable" "Disabled,Enabled"
setclrfld.long 0x00 6. 0x00 6. 0x08 6. " [6] ,HW channel 6 enable" "Disabled,Enabled"
setclrfld.long 0x00 5. 0x00 5. 0x08 5. " [5] ,HW channel 5 enable" "Disabled,Enabled"
setclrfld.long 0x00 4. 0x00 4. 0x08 4. " [4] ,HW channel 4 enable" "Disabled,Enabled"
setclrfld.long 0x00 3. 0x00 3. 0x08 3. " [3] ,HW channel 3 enable" "Disabled,Enabled"
setclrfld.long 0x00 2. 0x00 2. 0x08 2. " [2] ,HW channel 2 enable" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 1. 0x00 1. 0x08 1. " [1] ,HW channel 1 enable" "Disabled,Enabled"
setclrfld.long 0x00 0. 0x00 0. 0x08 0. " [0] ,HW channel 0 enable" "Disabled,Enabled"
group.long 0x24++0x03
line.long 0x00 "SWCHENA,SWCHANNEL Enable Register"
setclrfld.long 0x00 31. 0x00 31. 0x08 31. " SWCHENA_SET/CLR_[31] ,SW channel 31 enable" "Not triggered,Triggered"
setclrfld.long 0x00 30. 0x00 30. 0x08 30. " [30] ,SW channel 30 enable" "Not triggered,Triggered"
setclrfld.long 0x00 29. 0x00 29. 0x08 29. " [29] ,SW channel 29 enable" "Not triggered,Triggered"
setclrfld.long 0x00 28. 0x00 28. 0x08 28. " [28] ,SW channel 28 enable" "Not triggered,Triggered"
setclrfld.long 0x00 27. 0x00 27. 0x08 27. " [27] ,SW channel 27 enable" "Not triggered,Triggered"
setclrfld.long 0x00 26. 0x00 26. 0x08 26. " [26] ,SW channel 26 enable" "Not triggered,Triggered"
textline " "
setclrfld.long 0x00 25. 0x00 25. 0x08 25. " [25] ,SW channel 25 enable" "Not triggered,Triggered"
setclrfld.long 0x00 24. 0x00 24. 0x08 24. " [24] ,SW channel 24 enable" "Not triggered,Triggered"
setclrfld.long 0x00 23. 0x00 23. 0x08 23. " [23] ,SW channel 23 enable" "Not triggered,Triggered"
setclrfld.long 0x00 22. 0x00 22. 0x08 22. " [22] ,SW channel 22 enable" "Not triggered,Triggered"
setclrfld.long 0x00 21. 0x00 21. 0x08 21. " [21] ,SW channel 21 enable" "Not triggered,Triggered"
setclrfld.long 0x00 20. 0x00 20. 0x08 20. " [20] ,SW channel 20 enable" "Not triggered,Triggered"
textline " "
setclrfld.long 0x00 19. 0x00 19. 0x08 19. " [19] ,SW channel 19 enable" "Not triggered,Triggered"
setclrfld.long 0x00 18. 0x00 18. 0x08 18. " [18] ,SW channel 18 enable" "Not triggered,Triggered"
setclrfld.long 0x00 17. 0x00 17. 0x08 17. " [17] ,SW channel 17 enable" "Not triggered,Triggered"
setclrfld.long 0x00 16. 0x00 16. 0x08 16. " [16] ,SW channel 16 enable" "Not triggered,Triggered"
setclrfld.long 0x00 15. 0x00 15. 0x08 15. " [15] ,SW channel 15 enable" "Not triggered,Triggered"
setclrfld.long 0x00 14. 0x00 14. 0x08 14. " [14] ,SW channel 14 enable" "Not triggered,Triggered"
textline " "
setclrfld.long 0x00 13. 0x00 13. 0x08 13. " [13] ,SW channel 13 enable" "Not triggered,Triggered"
setclrfld.long 0x00 12. 0x00 12. 0x08 12. " [12] ,SW channel 12 enable" "Not triggered,Triggered"
setclrfld.long 0x00 11. 0x00 11. 0x08 11. " [11] ,SW channel 11 enable" "Not triggered,Triggered"
setclrfld.long 0x00 10. 0x00 10. 0x08 10. " [10] ,SW channel 10 enable" "Not triggered,Triggered"
setclrfld.long 0x00 9. 0x00 9. 0x08 9. " [9] ,SW channel 9 enable" "Not triggered,Triggered"
setclrfld.long 0x00 8. 0x00 8. 0x08 8. " [8] ,SW channel 8 enable" "Not triggered,Triggered"
textline " "
setclrfld.long 0x00 7. 0x00 7. 0x08 7. " [7] ,SW channel 7 enable" "Not triggered,Triggered"
setclrfld.long 0x00 6. 0x00 6. 0x08 6. " [6] ,SW channel 6 enable" "Not triggered,Triggered"
setclrfld.long 0x00 5. 0x00 5. 0x08 5. " [5] ,SW channel 5 enable" "Not triggered,Triggered"
setclrfld.long 0x00 4. 0x00 4. 0x08 4. " [4] ,SW channel 4 enable" "Not triggered,Triggered"
setclrfld.long 0x00 3. 0x00 3. 0x08 3. " [3] ,SW channel 3 enable" "Not triggered,Triggered"
setclrfld.long 0x00 2. 0x00 2. 0x08 2. " [2] ,SW channel 2 enable" "Not triggered,Triggered"
textline " "
setclrfld.long 0x00 1. 0x00 1. 0x08 1. " [1] ,SW channel 1 enable" "Not triggered,Triggered"
setclrfld.long 0x00 0. 0x00 0. 0x08 0. " [0] ,SW channel 0 enable" "Not triggered,Triggered"
tree.end
width 9.
textline " "
group.long 0x34++0x03
line.long 0x00 "CHPRIO,CHANNEL Prirority Register"
setclrfld.long 0x00 31. 0x00 31. 0x08 31. " CP_SET/CLR[31] ,Channel priority 31" "Low,High"
setclrfld.long 0x00 30. 0x00 30. 0x08 30. " [30] ,Channel priority 30" "Low,High"
setclrfld.long 0x00 29. 0x00 29. 0x08 29. " [29] ,Channel priority 29" "Low,High"
setclrfld.long 0x00 28. 0x00 28. 0x08 28. " [28] ,Channel priority 28" "Low,High"
setclrfld.long 0x00 27. 0x00 27. 0x08 27. " [27] ,Channel priority 27" "Low,High"
setclrfld.long 0x00 26. 0x00 26. 0x08 26. " [26] ,Channel priority 26" "Low,High"
textline " "
setclrfld.long 0x00 25. 0x00 25. 0x08 25. " [25] ,Channel priority 25" "Low,High"
setclrfld.long 0x00 24. 0x00 24. 0x08 24. " [24] ,Channel priority 24" "Low,High"
setclrfld.long 0x00 23. 0x00 23. 0x08 23. " [23] ,Channel priority 23" "Low,High"
setclrfld.long 0x00 22. 0x00 22. 0x08 22. " [22] ,Channel priority 22" "Low,High"
setclrfld.long 0x00 21. 0x00 21. 0x08 21. " [21] ,Channel priority 21" "Low,High"
setclrfld.long 0x00 20. 0x00 20. 0x08 20. " [20] ,Channel priority 20" "Low,High"
textline " "
setclrfld.long 0x00 19. 0x00 19. 0x08 19. " [19] ,Channel priority 19" "Low,High"
setclrfld.long 0x00 18. 0x00 18. 0x08 18. " [18] ,Channel priority 18" "Low,High"
setclrfld.long 0x00 17. 0x00 17. 0x08 17. " [17] ,Channel priority 17" "Low,High"
setclrfld.long 0x00 16. 0x00 16. 0x08 16. " [16] ,Channel priority 16" "Low,High"
setclrfld.long 0x00 15. 0x00 15. 0x08 15. " [15] ,Channel priority 15" "Low,High"
setclrfld.long 0x00 14. 0x00 14. 0x08 14. " [14] ,Channel priority 14" "Low,High"
textline " "
setclrfld.long 0x00 13. 0x00 13. 0x08 13. " [13] ,Channel priority 13" "Low,High"
setclrfld.long 0x00 12. 0x00 12. 0x08 12. " [12] ,Channel priority 12" "Low,High"
setclrfld.long 0x00 11. 0x00 11. 0x08 11. " [11] ,Channel priority 11" "Low,High"
setclrfld.long 0x00 10. 0x00 10. 0x08 10. " [10] ,Channel priority 10" "Low,High"
setclrfld.long 0x00 9. 0x00 9. 0x08 9. " [9] ,Channel priority 9" "Low,High"
setclrfld.long 0x00 8. 0x00 8. 0x08 8. " [8] ,Channel priority 8" "Low,High"
textline " "
setclrfld.long 0x00 7. 0x00 7. 0x08 7. " [7] ,Channel priority 7" "Low,High"
setclrfld.long 0x00 6. 0x00 6. 0x08 6. " [6] ,Channel priority 6" "Low,High"
setclrfld.long 0x00 5. 0x00 5. 0x08 5. " [5] ,Channel priority 5" "Low,High"
setclrfld.long 0x00 4. 0x00 4. 0x08 4. " [4] ,Channel priority 4" "Low,High"
setclrfld.long 0x00 3. 0x00 3. 0x08 3. " [3] ,Channel priority 3" "Low,High"
setclrfld.long 0x00 2. 0x00 2. 0x08 2. " [2] ,Channel priority 2" "Low,High"
textline " "
setclrfld.long 0x00 1. 0x00 1. 0x08 1. " [1] ,Channel priority 1" "Low,High"
setclrfld.long 0x00 0. 0x00 0. 0x08 0. " [0] ,Channel priority 0" "Low,High"
textline " "
group.long 0x44++0x03
line.long 0x00 "GCHIENA,GLOBAL CHANNEL INTERRUPT ENABLE"
setclrfld.long 0x00 31. 0x00 31. 0x08 31. " GCHIE_SET/CLR_[31] ,Global channel interrupt enable 31" "Disabled,Enabled"
setclrfld.long 0x00 30. 0x00 30. 0x08 30. " [30] ,Global channel interrupt enable 30" "Disabled,Enabled"
setclrfld.long 0x00 29. 0x00 29. 0x08 29. " [29] ,Global channel interrupt enable 29" "Disabled,Enabled"
setclrfld.long 0x00 28. 0x00 28. 0x08 28. " [28] ,Global channel interrupt enable 28" "Disabled,Enabled"
setclrfld.long 0x00 27. 0x00 27. 0x08 27. " [27] ,Global channel interrupt enable 27" "Disabled,Enabled"
setclrfld.long 0x00 26. 0x00 26. 0x08 26. " [26] ,Global channel interrupt enable 26" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 25. 0x00 25. 0x08 25. " [25] ,Global channel interrupt enable 25" "Disabled,Enabled"
setclrfld.long 0x00 24. 0x00 24. 0x08 24. " [24] ,Global channel interrupt enable 24" "Disabled,Enabled"
setclrfld.long 0x00 23. 0x00 23. 0x08 23. " [23] ,Global channel interrupt enable 23" "Disabled,Enabled"
setclrfld.long 0x00 22. 0x00 22. 0x08 22. " [22] ,Global channel interrupt enable 22" "Disabled,Enabled"
setclrfld.long 0x00 21. 0x00 21. 0x08 21. " [21] ,Global channel interrupt enable 21" "Disabled,Enabled"
setclrfld.long 0x00 20. 0x00 20. 0x08 20. " [20] ,Global channel interrupt enable 20" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 19. 0x00 19. 0x08 19. " [19] ,Global channel interrupt enable 19" "Disabled,Enabled"
setclrfld.long 0x00 18. 0x00 18. 0x08 18. " [18] ,Global channel interrupt enable 18" "Disabled,Enabled"
setclrfld.long 0x00 17. 0x00 17. 0x08 17. " [17] ,Global channel interrupt enable 17" "Disabled,Enabled"
setclrfld.long 0x00 16. 0x00 16. 0x08 16. " [16] ,Global channel interrupt enable 16" "Disabled,Enabled"
setclrfld.long 0x00 15. 0x00 15. 0x08 15. " [15] ,Global channel interrupt enable 15" "Disabled,Enabled"
setclrfld.long 0x00 14. 0x00 14. 0x08 14. " [14] ,Global channel interrupt enable 14" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 13. 0x00 13. 0x08 13. " [13] ,Global channel interrupt enable 13" "Disabled,Enabled"
setclrfld.long 0x00 12. 0x00 12. 0x08 12. " [12] ,Global channel interrupt enable 12" "Disabled,Enabled"
setclrfld.long 0x00 11. 0x00 11. 0x08 11. " [11] ,Global channel interrupt enable 11" "Disabled,Enabled"
setclrfld.long 0x00 10. 0x00 10. 0x08 10. " [10] ,Global channel interrupt enable 10" "Disabled,Enabled"
setclrfld.long 0x00 9. 0x00 9. 0x08 9. " [9] ,Global channel interrupt enable 9" "Disabled,Enabled"
setclrfld.long 0x00 8. 0x00 8. 0x08 8. " [8] ,Global channel interrupt enable 8" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 7. 0x00 7. 0x08 7. " [7] ,Global channel interrupt enable 7" "Disabled,Enabled"
setclrfld.long 0x00 6. 0x00 6. 0x08 6. " [6] ,Global channel interrupt enable 6" "Disabled,Enabled"
setclrfld.long 0x00 5. 0x00 5. 0x08 5. " [5] ,Global channel interrupt enable 5" "Disabled,Enabled"
setclrfld.long 0x00 4. 0x00 4. 0x08 4. " [4] ,Global channel interrupt enable 4" "Disabled,Enabled"
setclrfld.long 0x00 3. 0x00 3. 0x08 3. " [3] ,Global channel interrupt enable 3" "Disabled,Enabled"
setclrfld.long 0x00 2. 0x00 2. 0x08 2. " [2] ,Global channel interrupt enable 2" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 1. 0x00 1. 0x08 1. " [1] ,Global channel interrupt enable 1" "Disabled,Enabled"
setclrfld.long 0x00 0. 0x00 0. 0x08 0. " [0] ,Global channel interrupt enable 0" "Disabled,Enabled"
width 10.
tree "DMA Request Assignment Registers"
group.long 0x54++0x03
line.long 0x00 "DREQASI0,DMA REQUEST ASSIGNMENT Register 0"
bitfld.long 0x00 24.--29. " CHASI_[0] ,Channel 0 assignment" "Line 0,Line 1,Line 2,Line 3,Line 4,Line 5,Line 6,Line 7,Line 8,Line 9,Line 10,Line 11,Line 12,Line 13,Line 14,Line 15,Line 16,Line 17,Line 18,Line 19,Line 20,Line 21,Line 22,Line 23,Line 24,Line 25,Line 26,Line 27,Line 28,Line 29,Line 30,Line 31,?..."
bitfld.long 0x00 16.--21. " [1] ,Channel 1 assignment" "Line 0,Line 1,Line 2,Line 3,Line 4,Line 5,Line 6,Line 7,Line 8,Line 9,Line 10,Line 11,Line 12,Line 13,Line 14,Line 15,Line 16,Line 17,Line 18,Line 19,Line 20,Line 21,Line 22,Line 23,Line 24,Line 25,Line 26,Line 27,Line 28,Line 29,Line 30,Line 31,?..."
bitfld.long 0x00 8.--13. " [2] ,Channel 2 assignment" "Line 0,Line 1,Line 2,Line 3,Line 4,Line 5,Line 6,Line 7,Line 8,Line 9,Line 10,Line 11,Line 12,Line 13,Line 14,Line 15,Line 16,Line 17,Line 18,Line 19,Line 20,Line 21,Line 22,Line 23,Line 24,Line 25,Line 26,Line 27,Line 28,Line 29,Line 30,Line 31,?..."
bitfld.long 0x00 0.--5. " [3] ,Channel 3 assignment" "Line 0,Line 1,Line 2,Line 3,Line 4,Line 5,Line 6,Line 7,Line 8,Line 9,Line 10,Line 11,Line 12,Line 13,Line 14,Line 15,Line 16,Line 17,Line 18,Line 19,Line 20,Line 21,Line 22,Line 23,Line 24,Line 25,Line 26,Line 27,Line 28,Line 29,Line 30,Line 31,?..."
group.long 0x58++0x03
line.long 0x00 "DREQASI1,DMA REQUEST ASSIGNMENT Register 1"
bitfld.long 0x00 24.--29. " CHASI_[4] ,Channel 4 assignment" "Line 0,Line 1,Line 2,Line 3,Line 4,Line 5,Line 6,Line 7,Line 8,Line 9,Line 10,Line 11,Line 12,Line 13,Line 14,Line 15,Line 16,Line 17,Line 18,Line 19,Line 20,Line 21,Line 22,Line 23,Line 24,Line 25,Line 26,Line 27,Line 28,Line 29,Line 30,Line 31,?..."
bitfld.long 0x00 16.--21. " [5] ,Channel 5 assignment" "Line 0,Line 1,Line 2,Line 3,Line 4,Line 5,Line 6,Line 7,Line 8,Line 9,Line 10,Line 11,Line 12,Line 13,Line 14,Line 15,Line 16,Line 17,Line 18,Line 19,Line 20,Line 21,Line 22,Line 23,Line 24,Line 25,Line 26,Line 27,Line 28,Line 29,Line 30,Line 31,?..."
bitfld.long 0x00 8.--13. " [6] ,Channel 6 assignment" "Line 0,Line 1,Line 2,Line 3,Line 4,Line 5,Line 6,Line 7,Line 8,Line 9,Line 10,Line 11,Line 12,Line 13,Line 14,Line 15,Line 16,Line 17,Line 18,Line 19,Line 20,Line 21,Line 22,Line 23,Line 24,Line 25,Line 26,Line 27,Line 28,Line 29,Line 30,Line 31,?..."
bitfld.long 0x00 0.--5. " [7] ,Channel 7 assignment" "Line 0,Line 1,Line 2,Line 3,Line 4,Line 5,Line 6,Line 7,Line 8,Line 9,Line 10,Line 11,Line 12,Line 13,Line 14,Line 15,Line 16,Line 17,Line 18,Line 19,Line 20,Line 21,Line 22,Line 23,Line 24,Line 25,Line 26,Line 27,Line 28,Line 29,Line 30,Line 31,?..."
group.long 0x5C++0x03
line.long 0x00 "DREQASI2,DMA REQUEST ASSIGNMENT Register 2"
bitfld.long 0x00 24.--29. " CHASI_[8] ,Channel 8 assignment" "Line 0,Line 1,Line 2,Line 3,Line 4,Line 5,Line 6,Line 7,Line 8,Line 9,Line 10,Line 11,Line 12,Line 13,Line 14,Line 15,Line 16,Line 17,Line 18,Line 19,Line 20,Line 21,Line 22,Line 23,Line 24,Line 25,Line 26,Line 27,Line 28,Line 29,Line 30,Line 31,?..."
bitfld.long 0x00 16.--21. " [9] ,Channel 9 assignment" "Line 0,Line 1,Line 2,Line 3,Line 4,Line 5,Line 6,Line 7,Line 8,Line 9,Line 10,Line 11,Line 12,Line 13,Line 14,Line 15,Line 16,Line 17,Line 18,Line 19,Line 20,Line 21,Line 22,Line 23,Line 24,Line 25,Line 26,Line 27,Line 28,Line 29,Line 30,Line 31,?..."
bitfld.long 0x00 8.--13. " [10] ,Channel 10 assignment" "Line 0,Line 1,Line 2,Line 3,Line 4,Line 5,Line 6,Line 7,Line 8,Line 9,Line 10,Line 11,Line 12,Line 13,Line 14,Line 15,Line 16,Line 17,Line 18,Line 19,Line 20,Line 21,Line 22,Line 23,Line 24,Line 25,Line 26,Line 27,Line 28,Line 29,Line 30,Line 31,?..."
bitfld.long 0x00 0.--5. " [11] ,Channel 11 assignment" "Line 0,Line 1,Line 2,Line 3,Line 4,Line 5,Line 6,Line 7,Line 8,Line 9,Line 10,Line 11,Line 12,Line 13,Line 14,Line 15,Line 16,Line 17,Line 18,Line 19,Line 20,Line 21,Line 22,Line 23,Line 24,Line 25,Line 26,Line 27,Line 28,Line 29,Line 30,Line 31,?..."
group.long 0x60++0x03
line.long 0x00 "DREQASI3,DMA REQUEST ASSIGNMENT Register 3"
bitfld.long 0x00 24.--29. " CHASI_[12] ,Channel 12 assignment" "Line 0,Line 1,Line 2,Line 3,Line 4,Line 5,Line 6,Line 7,Line 8,Line 9,Line 10,Line 11,Line 12,Line 13,Line 14,Line 15,Line 16,Line 17,Line 18,Line 19,Line 20,Line 21,Line 22,Line 23,Line 24,Line 25,Line 26,Line 27,Line 28,Line 29,Line 30,Line 31,?..."
bitfld.long 0x00 16.--21. " [13] ,Channel 13 assignment" "Line 0,Line 1,Line 2,Line 3,Line 4,Line 5,Line 6,Line 7,Line 8,Line 9,Line 10,Line 11,Line 12,Line 13,Line 14,Line 15,Line 16,Line 17,Line 18,Line 19,Line 20,Line 21,Line 22,Line 23,Line 24,Line 25,Line 26,Line 27,Line 28,Line 29,Line 30,Line 31,?..."
bitfld.long 0x00 8.--13. " [14] ,Channel 14 assignment" "Line 0,Line 1,Line 2,Line 3,Line 4,Line 5,Line 6,Line 7,Line 8,Line 9,Line 10,Line 11,Line 12,Line 13,Line 14,Line 15,Line 16,Line 17,Line 18,Line 19,Line 20,Line 21,Line 22,Line 23,Line 24,Line 25,Line 26,Line 27,Line 28,Line 29,Line 30,Line 31,?..."
bitfld.long 0x00 0.--5. " [15] ,Channel 15 assignment" "Line 0,Line 1,Line 2,Line 3,Line 4,Line 5,Line 6,Line 7,Line 8,Line 9,Line 10,Line 11,Line 12,Line 13,Line 14,Line 15,Line 16,Line 17,Line 18,Line 19,Line 20,Line 21,Line 22,Line 23,Line 24,Line 25,Line 26,Line 27,Line 28,Line 29,Line 30,Line 31,?..."
group.long 0x64++0x03
line.long 0x00 "DREQASI4,DMA REQUEST ASSIGNMENT Register 4"
bitfld.long 0x00 24.--29. " CHASI_[16] ,Channel 16 assignment" "Line 0,Line 1,Line 2,Line 3,Line 4,Line 5,Line 6,Line 7,Line 8,Line 9,Line 10,Line 11,Line 12,Line 13,Line 14,Line 15,Line 16,Line 17,Line 18,Line 19,Line 20,Line 21,Line 22,Line 23,Line 24,Line 25,Line 26,Line 27,Line 28,Line 29,Line 30,Line 31,?..."
bitfld.long 0x00 16.--21. " [17] ,Channel 17 assignment" "Line 0,Line 1,Line 2,Line 3,Line 4,Line 5,Line 6,Line 7,Line 8,Line 9,Line 10,Line 11,Line 12,Line 13,Line 14,Line 15,Line 16,Line 17,Line 18,Line 19,Line 20,Line 21,Line 22,Line 23,Line 24,Line 25,Line 26,Line 27,Line 28,Line 29,Line 30,Line 31,?..."
bitfld.long 0x00 8.--13. " [18] ,Channel 18 assignment" "Line 0,Line 1,Line 2,Line 3,Line 4,Line 5,Line 6,Line 7,Line 8,Line 9,Line 10,Line 11,Line 12,Line 13,Line 14,Line 15,Line 16,Line 17,Line 18,Line 19,Line 20,Line 21,Line 22,Line 23,Line 24,Line 25,Line 26,Line 27,Line 28,Line 29,Line 30,Line 31,?..."
bitfld.long 0x00 0.--5. " [19] ,Channel 19 assignment" "Line 0,Line 1,Line 2,Line 3,Line 4,Line 5,Line 6,Line 7,Line 8,Line 9,Line 10,Line 11,Line 12,Line 13,Line 14,Line 15,Line 16,Line 17,Line 18,Line 19,Line 20,Line 21,Line 22,Line 23,Line 24,Line 25,Line 26,Line 27,Line 28,Line 29,Line 30,Line 31,?..."
group.long 0x68++0x03
line.long 0x00 "DREQASI5,DMA REQUEST ASSIGNMENT Register 5"
bitfld.long 0x00 24.--29. " CHASI_[20] ,Channel 20 assignment" "Line 0,Line 1,Line 2,Line 3,Line 4,Line 5,Line 6,Line 7,Line 8,Line 9,Line 10,Line 11,Line 12,Line 13,Line 14,Line 15,Line 16,Line 17,Line 18,Line 19,Line 20,Line 21,Line 22,Line 23,Line 24,Line 25,Line 26,Line 27,Line 28,Line 29,Line 30,Line 31,?..."
bitfld.long 0x00 16.--21. " [21] ,Channel 21 assignment" "Line 0,Line 1,Line 2,Line 3,Line 4,Line 5,Line 6,Line 7,Line 8,Line 9,Line 10,Line 11,Line 12,Line 13,Line 14,Line 15,Line 16,Line 17,Line 18,Line 19,Line 20,Line 21,Line 22,Line 23,Line 24,Line 25,Line 26,Line 27,Line 28,Line 29,Line 30,Line 31,?..."
bitfld.long 0x00 8.--13. " [22] ,Channel 22 assignment" "Line 0,Line 1,Line 2,Line 3,Line 4,Line 5,Line 6,Line 7,Line 8,Line 9,Line 10,Line 11,Line 12,Line 13,Line 14,Line 15,Line 16,Line 17,Line 18,Line 19,Line 20,Line 21,Line 22,Line 23,Line 24,Line 25,Line 26,Line 27,Line 28,Line 29,Line 30,Line 31,?..."
bitfld.long 0x00 0.--5. " [23] ,Channel 23 assignment" "Line 0,Line 1,Line 2,Line 3,Line 4,Line 5,Line 6,Line 7,Line 8,Line 9,Line 10,Line 11,Line 12,Line 13,Line 14,Line 15,Line 16,Line 17,Line 18,Line 19,Line 20,Line 21,Line 22,Line 23,Line 24,Line 25,Line 26,Line 27,Line 28,Line 29,Line 30,Line 31,?..."
group.long 0x6C++0x03
line.long 0x00 "DREQASI6,DMA REQUEST ASSIGNMENT Register 6"
bitfld.long 0x00 24.--29. " CHASI_[24] ,Channel 24 assignment" "Line 0,Line 1,Line 2,Line 3,Line 4,Line 5,Line 6,Line 7,Line 8,Line 9,Line 10,Line 11,Line 12,Line 13,Line 14,Line 15,Line 16,Line 17,Line 18,Line 19,Line 20,Line 21,Line 22,Line 23,Line 24,Line 25,Line 26,Line 27,Line 28,Line 29,Line 30,Line 31,?..."
bitfld.long 0x00 16.--21. " [25] ,Channel 25 assignment" "Line 0,Line 1,Line 2,Line 3,Line 4,Line 5,Line 6,Line 7,Line 8,Line 9,Line 10,Line 11,Line 12,Line 13,Line 14,Line 15,Line 16,Line 17,Line 18,Line 19,Line 20,Line 21,Line 22,Line 23,Line 24,Line 25,Line 26,Line 27,Line 28,Line 29,Line 30,Line 31,?..."
bitfld.long 0x00 8.--13. " [26] ,Channel 26 assignment" "Line 0,Line 1,Line 2,Line 3,Line 4,Line 5,Line 6,Line 7,Line 8,Line 9,Line 10,Line 11,Line 12,Line 13,Line 14,Line 15,Line 16,Line 17,Line 18,Line 19,Line 20,Line 21,Line 22,Line 23,Line 24,Line 25,Line 26,Line 27,Line 28,Line 29,Line 30,Line 31,?..."
bitfld.long 0x00 0.--5. " [27] ,Channel 27 assignment" "Line 0,Line 1,Line 2,Line 3,Line 4,Line 5,Line 6,Line 7,Line 8,Line 9,Line 10,Line 11,Line 12,Line 13,Line 14,Line 15,Line 16,Line 17,Line 18,Line 19,Line 20,Line 21,Line 22,Line 23,Line 24,Line 25,Line 26,Line 27,Line 28,Line 29,Line 30,Line 31,?..."
group.long 0x70++0x03
line.long 0x00 "DREQASI7,DMA REQUEST ASSIGNMENT Register 7"
bitfld.long 0x00 24.--29. " CHASI_[28] ,Channel 28 assignment" "Line 0,Line 1,Line 2,Line 3,Line 4,Line 5,Line 6,Line 7,Line 8,Line 9,Line 10,Line 11,Line 12,Line 13,Line 14,Line 15,Line 16,Line 17,Line 18,Line 19,Line 20,Line 21,Line 22,Line 23,Line 24,Line 25,Line 26,Line 27,Line 28,Line 29,Line 30,Line 31,?..."
bitfld.long 0x00 16.--21. " [29] ,Channel 29 assignment" "Line 0,Line 1,Line 2,Line 3,Line 4,Line 5,Line 6,Line 7,Line 8,Line 9,Line 10,Line 11,Line 12,Line 13,Line 14,Line 15,Line 16,Line 17,Line 18,Line 19,Line 20,Line 21,Line 22,Line 23,Line 24,Line 25,Line 26,Line 27,Line 28,Line 29,Line 30,Line 31,?..."
bitfld.long 0x00 8.--13. " [30] ,Channel 30 assignment" "Line 0,Line 1,Line 2,Line 3,Line 4,Line 5,Line 6,Line 7,Line 8,Line 9,Line 10,Line 11,Line 12,Line 13,Line 14,Line 15,Line 16,Line 17,Line 18,Line 19,Line 20,Line 21,Line 22,Line 23,Line 24,Line 25,Line 26,Line 27,Line 28,Line 29,Line 30,Line 31,?..."
bitfld.long 0x00 0.--5. " [31] ,Channel 31 assignment" "Line 0,Line 1,Line 2,Line 3,Line 4,Line 5,Line 6,Line 7,Line 8,Line 9,Line 10,Line 11,Line 12,Line 13,Line 14,Line 15,Line 16,Line 17,Line 18,Line 19,Line 20,Line 21,Line 22,Line 23,Line 24,Line 25,Line 26,Line 27,Line 28,Line 29,Line 30,Line 31,?..."
tree.end
width 6.
tree "Port Assignment Registers"
group.long 0x94++0x03
line.long 0x00 "PAR0,PORT Assignment Register 0"
bitfld.long 0x00 28.--30. " CHPA_[0] ,Port channel 0 assignment" "A write/b read,A read/b write,A only,B only,A write/b read,A write/b read,A write/b read,A write/b read"
bitfld.long 0x00 24.--26. " [1] ,Port channel 1 assignment" "A write/b read,A read/b write,A only,B only,A write/b read,A write/b read,A write/b read,A write/b read"
bitfld.long 0x00 20.--22. " [2] ,Port channel 2 assignment" "A write/b read,A read/b write,A only,B only,A write/b read,A write/b read,A write/b read,A write/b read"
bitfld.long 0x00 16.--18. " [3] ,Port channel 3 assignment" "A write/b read,A read/b write,A only,B only,A write/b read,A write/b read,A write/b read,A write/b read"
textline " "
bitfld.long 0x00 12.--14. " [4] ,Port channel 4 assignment" "A write/b read,A read/b write,A only,B only,A write/b read,A write/b read,A write/b read,A write/b read"
bitfld.long 0x00 8.--10. " [5] ,Port channel 5 assignment" "A write/b read,A read/b write,A only,B only,A write/b read,A write/b read,A write/b read,A write/b read"
bitfld.long 0x00 4.--6. " [6] ,Port channel 6 assignment" "A write/b read,A read/b write,A only,B only,A write/b read,A write/b read,A write/b read,A write/b read"
bitfld.long 0x00 0.--2. " [7] ,Port channel 7 assignment" "A write/b read,A read/b write,A only,B only,A write/b read,A write/b read,A write/b read,A write/b read"
group.long 0x98++0x03
line.long 0x00 "PAR1,PORT Assignment Register 1"
bitfld.long 0x00 28.--30. " CHPA_[8] ,Port channel 8 assignment" "A write/b read,A read/b write,A only,B only,A write/b read,A write/b read,A write/b read,A write/b read"
bitfld.long 0x00 24.--26. " [9] ,Port channel 9 assignment" "A write/b read,A read/b write,A only,B only,A write/b read,A write/b read,A write/b read,A write/b read"
bitfld.long 0x00 20.--22. " [10] ,Port channel 10 assignment" "A write/b read,A read/b write,A only,B only,A write/b read,A write/b read,A write/b read,A write/b read"
bitfld.long 0x00 16.--18. " [11] ,Port channel 11 assignment" "A write/b read,A read/b write,A only,B only,A write/b read,A write/b read,A write/b read,A write/b read"
textline " "
bitfld.long 0x00 12.--14. " [12] ,Port channel 12 assignment" "A write/b read,A read/b write,A only,B only,A write/b read,A write/b read,A write/b read,A write/b read"
bitfld.long 0x00 8.--10. " [13] ,Port channel 13 assignment" "A write/b read,A read/b write,A only,B only,A write/b read,A write/b read,A write/b read,A write/b read"
bitfld.long 0x00 4.--6. " [14] ,Port channel 14 assignment" "A write/b read,A read/b write,A only,B only,A write/b read,A write/b read,A write/b read,A write/b read"
bitfld.long 0x00 0.--2. " [15] ,Port channel 15 assignment" "A write/b read,A read/b write,A only,B only,A write/b read,A write/b read,A write/b read,A write/b read"
group.long 0x9C++0x03
line.long 0x00 "PAR2,PORT Assignment Register 2"
bitfld.long 0x00 28.--30. " CHPA_[16] ,Port channel 16 assignment" "A write/b read,A read/b write,A only,B only,A write/b read,A write/b read,A write/b read,A write/b read"
bitfld.long 0x00 24.--26. " [17] ,Port channel 17 assignment" "A write/b read,A read/b write,A only,B only,A write/b read,A write/b read,A write/b read,A write/b read"
bitfld.long 0x00 20.--22. " [18] ,Port channel 18 assignment" "A write/b read,A read/b write,A only,B only,A write/b read,A write/b read,A write/b read,A write/b read"
bitfld.long 0x00 16.--18. " [19] ,Port channel 19 assignment" "A write/b read,A read/b write,A only,B only,A write/b read,A write/b read,A write/b read,A write/b read"
textline " "
bitfld.long 0x00 12.--14. " [20] ,Port channel 20 assignment" "A write/b read,A read/b write,A only,B only,A write/b read,A write/b read,A write/b read,A write/b read"
bitfld.long 0x00 8.--10. " [21] ,Port channel 21 assignment" "A write/b read,A read/b write,A only,B only,A write/b read,A write/b read,A write/b read,A write/b read"
bitfld.long 0x00 4.--6. " [22] ,Port channel 22 assignment" "A write/b read,A read/b write,A only,B only,A write/b read,A write/b read,A write/b read,A write/b read"
bitfld.long 0x00 0.--2. " [23] ,Port channel 23 assignment" "A write/b read,A read/b write,A only,B only,A write/b read,A write/b read,A write/b read,A write/b read"
group.long 0xA0++0x03
line.long 0x00 "PAR3,PORT Assignment Register 3"
bitfld.long 0x00 28.--30. " CHPA_[24] ,Port channel 24 assignment" "A write/b read,A read/b write,A only,B only,A write/b read,A write/b read,A write/b read,A write/b read"
bitfld.long 0x00 24.--26. " [25] ,Port channel 25 assignment" "A write/b read,A read/b write,A only,B only,A write/b read,A write/b read,A write/b read,A write/b read"
bitfld.long 0x00 20.--22. " [26] ,Port channel 26 assignment" "A write/b read,A read/b write,A only,B only,A write/b read,A write/b read,A write/b read,A write/b read"
bitfld.long 0x00 16.--18. " [27] ,Port channel 27 assignment" "A write/b read,A read/b write,A only,B only,A write/b read,A write/b read,A write/b read,A write/b read"
textline " "
bitfld.long 0x00 12.--14. " [28] ,Port channel 28 assignment" "A write/b read,A read/b write,A only,B only,A write/b read,A write/b read,A write/b read,A write/b read"
bitfld.long 0x00 8.--10. " [29] ,Port channel 29 assignment" "A write/b read,A read/b write,A only,B only,A write/b read,A write/b read,A write/b read,A write/b read"
bitfld.long 0x00 4.--6. " [30] ,Port channel 30 assignment" "A write/b read,A read/b write,A only,B only,A write/b read,A write/b read,A write/b read,A write/b read"
bitfld.long 0x00 0.--2. " [31] ,Port channel 31 assignment" "A write/b read,A read/b write,A only,B only,A write/b read,A write/b read,A write/b read,A write/b read"
tree.end
width 8.
tree "Interrupt Mapping Registers"
group.long 0xB4++0x03
line.long 0x00 "FTCMAP,FTC Interrupt MAPPING Register"
bitfld.long 0x00 31. " FTCAB_[31] ,Frame transfer complete interrupt of channel 31 to group A/B" "A,B"
bitfld.long 0x00 30. " [30] ,Frame transfer complete interrupt of channel 30 to group A/B" "A,B"
bitfld.long 0x00 29. " [29] ,Frame transfer complete interrupt of channel 29 to group A/B" "A,B"
bitfld.long 0x00 28. " [28] ,Frame transfer complete interrupt of channel 28 to group A/B" "A,B"
bitfld.long 0x00 27. " [27] ,Frame transfer complete interrupt of channel 27 to group A/B" "A,B"
bitfld.long 0x00 26. " [26] ,Frame transfer complete interrupt of channel 26 to group A/B" "A,B"
bitfld.long 0x00 25. " [25] ,Frame transfer complete interrupt of channel 25 to group A/B" "A,B"
bitfld.long 0x00 24. " [24] ,Frame transfer complete interrupt of channel 24 to group A/B" "A,B"
textline " "
bitfld.long 0x00 23. " [23] ,Frame transfer complete interrupt of channel 23 to group A/B" "A,B"
bitfld.long 0x00 22. " [22] ,Frame transfer complete interrupt of channel 22 to group A/B" "A,B"
bitfld.long 0x00 21. " [21] ,Frame transfer complete interrupt of channel 21 to group A/B" "A,B"
bitfld.long 0x00 20. " [20] ,Frame transfer complete interrupt of channel 20 to group A/B" "A,B"
bitfld.long 0x00 19. " [19] ,Frame transfer complete interrupt of channel 19 to group A/B" "A,B"
bitfld.long 0x00 18. " [18] ,Frame transfer complete interrupt of channel 18 to group A/B" "A,B"
bitfld.long 0x00 17. " [17] ,Frame transfer complete interrupt of channel 17 to group A/B" "A,B"
bitfld.long 0x00 16. " [16] ,Frame transfer complete interrupt of channel 16 to group A/B" "A,B"
textline " "
bitfld.long 0x00 15. " [15] ,Frame transfer complete interrupt of channel 15 to group A/B" "A,B"
bitfld.long 0x00 14. " [14] ,Frame transfer complete interrupt of channel 14 to group A/B" "A,B"
bitfld.long 0x00 13. " [13] ,Frame transfer complete interrupt of channel 13 to group A/B" "A,B"
bitfld.long 0x00 12. " [12] ,Frame transfer complete interrupt of channel 12 to group A/B" "A,B"
bitfld.long 0x00 11. " [11] ,Frame transfer complete interrupt of channel 11 to group A/B" "A,B"
bitfld.long 0x00 10. " [10] ,Frame transfer complete interrupt of channel 10 to group A/B" "A,B"
bitfld.long 0x00 9. " [9] ,Frame transfer complete interrupt of channel 9 to group A/B" "A,B"
bitfld.long 0x00 8. " [8] ,Frame transfer complete interrupt of channel 8 to group A/B" "A,B"
textline " "
bitfld.long 0x00 7. " [7] ,Frame transfer complete interrupt of channel 7 to group A/B" "A,B"
bitfld.long 0x00 6. " [6] ,Frame transfer complete interrupt of channel 6 to group A/B" "A,B"
bitfld.long 0x00 5. " [5] ,Frame transfer complete interrupt of channel 5 to group A/B" "A,B"
bitfld.long 0x00 4. " [4] ,Frame transfer complete interrupt of channel 4 to group A/B" "A,B"
bitfld.long 0x00 3. " [3] ,Frame transfer complete interrupt of channel 3 to group A/B" "A,B"
bitfld.long 0x00 2. " [2] ,Frame transfer complete interrupt of channel 2 to group A/B" "A,B"
bitfld.long 0x00 1. " [1] ,Frame transfer complete interrupt of channel 1 to group A/B" "A,B"
bitfld.long 0x00 0. " [0] ,Frame transfer complete interrupt of channel 0 to group A/B" "A,B"
group.long 0xBC++0x03
line.long 0x00 "LFSMAP,LFS Interrupt MAPPING Register"
bitfld.long 0x00 31. " LFSAB_[31] ,Last frame started interrupt of channel 31 to group A/B" "A,B"
bitfld.long 0x00 30. " [30] ,Last frame started interrupt of channel 30 to group A/B" "A,B"
bitfld.long 0x00 29. " [29] ,Last frame started interrupt of channel 29 to group A/B" "A,B"
bitfld.long 0x00 28. " [28] ,Last frame started interrupt of channel 28 to group A/B" "A,B"
bitfld.long 0x00 27. " [27] ,Last frame started interrupt of channel 27 to group A/B" "A,B"
bitfld.long 0x00 26. " [26] ,Last frame started interrupt of channel 26 to group A/B" "A,B"
bitfld.long 0x00 25. " [25] ,Last frame started interrupt of channel 25 to group A/B" "A,B"
bitfld.long 0x00 24. " [24] ,Last frame started interrupt of channel 24 to group A/B" "A,B"
textline " "
bitfld.long 0x00 23. " [23] ,Last frame started interrupt of channel 23 to group A/B" "A,B"
bitfld.long 0x00 22. " [22] ,Last frame started interrupt of channel 22 to group A/B" "A,B"
bitfld.long 0x00 21. " [21] ,Last frame started interrupt of channel 21 to group A/B" "A,B"
bitfld.long 0x00 20. " [20] ,Last frame started interrupt of channel 20 to group A/B" "A,B"
bitfld.long 0x00 19. " [19] ,Last frame started interrupt of channel 19 to group A/B" "A,B"
bitfld.long 0x00 18. " [18] ,Last frame started interrupt of channel 18 to group A/B" "A,B"
bitfld.long 0x00 17. " [17] ,Last frame started interrupt of channel 17 to group A/B" "A,B"
bitfld.long 0x00 16. " [16] ,Last frame started interrupt of channel 16 to group A/B" "A,B"
textline " "
bitfld.long 0x00 15. " [15] ,Last frame started interrupt of channel 15 to group A/B" "A,B"
bitfld.long 0x00 14. " [14] ,Last frame started interrupt of channel 14 to group A/B" "A,B"
bitfld.long 0x00 13. " [13] ,Last frame started interrupt of channel 13 to group A/B" "A,B"
bitfld.long 0x00 12. " [12] ,Last frame started interrupt of channel 12 to group A/B" "A,B"
bitfld.long 0x00 11. " [11] ,Last frame started interrupt of channel 11 to group A/B" "A,B"
bitfld.long 0x00 10. " [10] ,Last frame started interrupt of channel 10 to group A/B" "A,B"
bitfld.long 0x00 9. " [9] ,Last frame started interrupt of channel 9 to group A/B" "A,B"
bitfld.long 0x00 8. " [8] ,Last frame started interrupt of channel 8 to group A/B" "A,B"
textline " "
bitfld.long 0x00 7. " [7] ,Last frame started interrupt of channel 7 to group A/B" "A,B"
bitfld.long 0x00 6. " [6] ,Last frame started interrupt of channel 6 to group A/B" "A,B"
bitfld.long 0x00 5. " [5] ,Last frame started interrupt of channel 5 to group A/B" "A,B"
bitfld.long 0x00 4. " [4] ,Last frame started interrupt of channel 4 to group A/B" "A,B"
bitfld.long 0x00 3. " [3] ,Last frame started interrupt of channel 3 to group A/B" "A,B"
bitfld.long 0x00 2. " [2] ,Last frame started interrupt of channel 2 to group A/B" "A,B"
bitfld.long 0x00 1. " [1] ,Last frame started interrupt of channel 1 to group A/B" "A,B"
bitfld.long 0x00 0. " [0] ,Last frame started interrupt of channel 0 to group A/B" "A,B"
group.long 0xC4++0x03
line.long 0x00 "HBCMAP,HBC Interrupt MAPPING Register"
bitfld.long 0x00 31. " HBCAB_[31] ,Half block complete interrupt of channel 31 to group A/B" "A,B"
bitfld.long 0x00 30. " [30] ,Half block complete interrupt of channel 30 to group A/B" "A,B"
bitfld.long 0x00 29. " [29] ,Half block complete interrupt of channel 29 to group A/B" "A,B"
bitfld.long 0x00 28. " [28] ,Half block complete interrupt of channel 28 to group A/B" "A,B"
bitfld.long 0x00 27. " [27] ,Half block complete interrupt of channel 27 to group A/B" "A,B"
bitfld.long 0x00 26. " [26] ,Half block complete interrupt of channel 26 to group A/B" "A,B"
bitfld.long 0x00 25. " [25] ,Half block complete interrupt of channel 25 to group A/B" "A,B"
bitfld.long 0x00 24. " [24] ,Half block complete interrupt of channel 24 to group A/B" "A,B"
textline " "
bitfld.long 0x00 23. " [23] ,Half block complete interrupt of channel 23 to group A/B" "A,B"
bitfld.long 0x00 22. " [22] ,Half block complete interrupt of channel 22 to group A/B" "A,B"
bitfld.long 0x00 21. " [21] ,Half block complete interrupt of channel 21 to group A/B" "A,B"
bitfld.long 0x00 20. " [20] ,Half block complete interrupt of channel 20 to group A/B" "A,B"
bitfld.long 0x00 19. " [19] ,Half block complete interrupt of channel 19 to group A/B" "A,B"
bitfld.long 0x00 18. " [18] ,Half block complete interrupt of channel 18 to group A/B" "A,B"
bitfld.long 0x00 17. " [17] ,Half block complete interrupt of channel 17 to group A/B" "A,B"
bitfld.long 0x00 16. " [16] ,Half block complete interrupt of channel 16 to group A/B" "A,B"
textline " "
bitfld.long 0x00 15. " [15] ,Half block complete interrupt of channel 15 to group A/B" "A,B"
bitfld.long 0x00 14. " [14] ,Half block complete interrupt of channel 14 to group A/B" "A,B"
bitfld.long 0x00 13. " [13] ,Half block complete interrupt of channel 13 to group A/B" "A,B"
bitfld.long 0x00 12. " [12] ,Half block complete interrupt of channel 12 to group A/B" "A,B"
bitfld.long 0x00 11. " [11] ,Half block complete interrupt of channel 11 to group A/B" "A,B"
bitfld.long 0x00 10. " [10] ,Half block complete interrupt of channel 10 to group A/B" "A,B"
bitfld.long 0x00 9. " [9] ,Half block complete interrupt of channel 9 to group A/B" "A,B"
bitfld.long 0x00 8. " [8] ,Half block complete interrupt of channel 8 to group A/B" "A,B"
textline " "
bitfld.long 0x00 7. " [7] ,Half block complete interrupt of channel 7 to group A/B" "A,B"
bitfld.long 0x00 6. " [6] ,Half block complete interrupt of channel 6 to group A/B" "A,B"
bitfld.long 0x00 5. " [5] ,Half block complete interrupt of channel 5 to group A/B" "A,B"
bitfld.long 0x00 4. " [4] ,Half block complete interrupt of channel 4 to group A/B" "A,B"
bitfld.long 0x00 3. " [3] ,Half block complete interrupt of channel 3 to group A/B" "A,B"
bitfld.long 0x00 2. " [2] ,Half block complete interrupt of channel 2 to group A/B" "A,B"
bitfld.long 0x00 1. " [1] ,Half block complete interrupt of channel 1 to group A/B" "A,B"
bitfld.long 0x00 0. " [0] ,Half block complete interrupt of channel 0 to group A/B" "A,B"
group.long 0xCC++0x03
line.long 0x00 "BTCMAP,BTC Interrupt MAPPING Register"
bitfld.long 0x00 31. " BTCAB_[31] ,Block transfer complete interrupt of channel 31 to group A/B" "A,B"
bitfld.long 0x00 30. " [30] ,Block transfer complete interrupt of channel 30 to group A/B" "A,B"
bitfld.long 0x00 29. " [29] ,Block transfer complete interrupt of channel 29 to group A/B" "A,B"
bitfld.long 0x00 28. " [28] ,Block transfer complete interrupt of channel 28 to group A/B" "A,B"
bitfld.long 0x00 27. " [27] ,Block transfer complete interrupt of channel 27 to group A/B" "A,B"
bitfld.long 0x00 26. " [26] ,Block transfer complete interrupt of channel 26 to group A/B" "A,B"
bitfld.long 0x00 25. " [25] ,Block transfer complete interrupt of channel 25 to group A/B" "A,B"
bitfld.long 0x00 24. " [24] ,Block transfer complete interrupt of channel 24 to group A/B" "A,B"
textline " "
bitfld.long 0x00 23. " [23] ,Block transfer complete interrupt of channel 23 to group A/B" "A,B"
bitfld.long 0x00 22. " [22] ,Block transfer complete interrupt of channel 22 to group A/B" "A,B"
bitfld.long 0x00 21. " [21] ,Block transfer complete interrupt of channel 21 to group A/B" "A,B"
bitfld.long 0x00 20. " [20] ,Block transfer complete interrupt of channel 20 to group A/B" "A,B"
bitfld.long 0x00 19. " [19] ,Block transfer complete interrupt of channel 19 to group A/B" "A,B"
bitfld.long 0x00 18. " [18] ,Block transfer complete interrupt of channel 18 to group A/B" "A,B"
bitfld.long 0x00 17. " [17] ,Block transfer complete interrupt of channel 17 to group A/B" "A,B"
bitfld.long 0x00 16. " [16] ,Block transfer complete interrupt of channel 16 to group A/B" "A,B"
textline " "
bitfld.long 0x00 15. " [15] ,Block transfer complete interrupt of channel 15 to group A/B" "A,B"
bitfld.long 0x00 14. " [14] ,Block transfer complete interrupt of channel 14 to group A/B" "A,B"
bitfld.long 0x00 13. " [13] ,Block transfer complete interrupt of channel 13 to group A/B" "A,B"
bitfld.long 0x00 12. " [12] ,Block transfer complete interrupt of channel 12 to group A/B" "A,B"
bitfld.long 0x00 11. " [11] ,Block transfer complete interrupt of channel 11 to group A/B" "A,B"
bitfld.long 0x00 10. " [10] ,Block transfer complete interrupt of channel 10 to group A/B" "A,B"
bitfld.long 0x00 9. " [9] ,Block transfer complete interrupt of channel 9 to group A/B" "A,B"
bitfld.long 0x00 8. " [8] ,Block transfer complete interrupt of channel 8 to group A/B" "A,B"
textline " "
bitfld.long 0x00 7. " [7] ,Block transfer complete interrupt of channel 7 to group A/B" "A,B"
bitfld.long 0x00 6. " [6] ,Block transfer complete interrupt of channel 6 to group A/B" "A,B"
bitfld.long 0x00 5. " [5] ,Block transfer complete interrupt of channel 5 to group A/B" "A,B"
bitfld.long 0x00 4. " [4] ,Block transfer complete interrupt of channel 4 to group A/B" "A,B"
bitfld.long 0x00 3. " [3] ,Block transfer complete interrupt of channel 3 to group A/B" "A,B"
bitfld.long 0x00 2. " [2] ,Block transfer complete interrupt of channel 2 to group A/B" "A,B"
bitfld.long 0x00 1. " [1] ,Block transfer complete interrupt of channel 1 to group A/B" "A,B"
bitfld.long 0x00 0. " [0] ,Block transfer complete interrupt of channel 0 to group A/B" "A,B"
group.long 0xD4++0x03
line.long 0x00 "BERMAP,BER INTERRUPT MAPPING Register"
bitfld.long 0x00 31. " BERAB_[31] ,Bus error interrupt of channel 31 to group A/B" "A,B"
bitfld.long 0x00 30. " [30] ,Bus error interrupt of channel 30 to group A/B" "A,B"
bitfld.long 0x00 29. " [29] ,Bus error interrupt of channel 29 to group A/B" "A,B"
bitfld.long 0x00 28. " [28] ,Bus error interrupt of channel 28 to group A/B" "A,B"
bitfld.long 0x00 27. " [27] ,Bus error interrupt of channel 27 to group A/B" "A,B"
bitfld.long 0x00 26. " [26] ,Bus error interrupt of channel 26 to group A/B" "A,B"
bitfld.long 0x00 25. " [25] ,Bus error interrupt of channel 25 to group A/B" "A,B"
bitfld.long 0x00 24. " [24] ,Bus error interrupt of channel 24 to group A/B" "A,B"
textline " "
bitfld.long 0x00 23. " [23] ,Bus error interrupt of channel 23 to group A/B" "A,B"
bitfld.long 0x00 22. " [22] ,Bus error interrupt of channel 22 to group A/B" "A,B"
bitfld.long 0x00 21. " [21] ,Bus error interrupt of channel 21 to group A/B" "A,B"
bitfld.long 0x00 20. " [20] ,Bus error interrupt of channel 20 to group A/B" "A,B"
bitfld.long 0x00 19. " [19] ,Bus error interrupt of channel 19 to group A/B" "A,B"
bitfld.long 0x00 18. " [18] ,Bus error interrupt of channel 18 to group A/B" "A,B"
bitfld.long 0x00 17. " [17] ,Bus error interrupt of channel 17 to group A/B" "A,B"
bitfld.long 0x00 16. " [16] ,Bus error interrupt of channel 16 to group A/B" "A,B"
textline " "
bitfld.long 0x00 15. " [15] ,Bus error interrupt of channel 15 to group A/B" "A,B"
bitfld.long 0x00 14. " [14] ,Bus error interrupt of channel 14 to group A/B" "A,B"
bitfld.long 0x00 13. " [13] ,Bus error interrupt of channel 13 to group A/B" "A,B"
bitfld.long 0x00 12. " [12] ,Bus error interrupt of channel 12 to group A/B" "A,B"
bitfld.long 0x00 11. " [11] ,Bus error interrupt of channel 11 to group A/B" "A,B"
bitfld.long 0x00 10. " [10] ,Bus error interrupt of channel 10 to group A/B" "A,B"
bitfld.long 0x00 9. " [9] ,Bus error interrupt of channel 9 to group A/B" "A,B"
bitfld.long 0x00 8. " [8] ,Bus error interrupt of channel 8 to group A/B" "A,B"
textline " "
bitfld.long 0x00 7. " [7] ,Bus error interrupt of channel 7 to group A/B" "A,B"
bitfld.long 0x00 6. " [6] ,Bus error interrupt of channel 6 to group A/B" "A,B"
bitfld.long 0x00 5. " [5] ,Bus error interrupt of channel 5 to group A/B" "A,B"
bitfld.long 0x00 4. " [4] ,Bus error interrupt of channel 4 to group A/B" "A,B"
bitfld.long 0x00 3. " [3] ,Bus error interrupt of channel 3 to group A/B" "A,B"
bitfld.long 0x00 2. " [2] ,Bus error interrupt of channel 2 to group A/B" "A,B"
bitfld.long 0x00 1. " [1] ,Bus error interrupt of channel 1 to group A/B" "A,B"
bitfld.long 0x00 0. " [0] ,Bus error interrupt of channel 0 to group A/B" "A,B"
tree.end
width 11.
tree "Interrupt Enable Registers"
group.long 0xDC++0x03
line.long 0x00 "FTCINTENA,FTC Interrupt Enable"
setclrfld.long 0x00 31. 0x00 31. 0x08 31. " FTCINTENA_SET/CLR_[31] ,FTC (Frame transfer complete) interrupt enable 31" "Disabled,Enabled"
setclrfld.long 0x00 30. 0x00 30. 0x08 30. " [30] ,FTC (Frame transfer complete) interrupt enable 30" "Disabled,Enabled"
setclrfld.long 0x00 29. 0x00 29. 0x08 29. " [29] ,FTC (Frame transfer complete) interrupt enable 29" "Disabled,Enabled"
setclrfld.long 0x00 28. 0x00 28. 0x08 28. " [28] ,FTC (Frame transfer complete) interrupt enable 28" "Disabled,Enabled"
setclrfld.long 0x00 27. 0x00 27. 0x08 27. " [27] ,FTC (Frame transfer complete) interrupt enable 27" "Disabled,Enabled"
setclrfld.long 0x00 26. 0x00 26. 0x08 26. " [26] ,FTC (Frame transfer complete) interrupt enable 26" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 25. 0x00 25. 0x08 25. " [25] ,FTC (Frame transfer complete) interrupt enable 25" "Disabled,Enabled"
setclrfld.long 0x00 24. 0x00 24. 0x08 24. " [24] ,FTC (Frame transfer complete) interrupt enable 24" "Disabled,Enabled"
setclrfld.long 0x00 23. 0x00 23. 0x08 23. " [23] ,FTC (Frame transfer complete) interrupt enable 23" "Disabled,Enabled"
setclrfld.long 0x00 22. 0x00 22. 0x08 22. " [22] ,FTC (Frame transfer complete) interrupt enable 22" "Disabled,Enabled"
setclrfld.long 0x00 21. 0x00 21. 0x08 21. " [21] ,FTC (Frame transfer complete) interrupt enable 21" "Disabled,Enabled"
setclrfld.long 0x00 20. 0x00 20. 0x08 20. " [20] ,FTC (Frame transfer complete) interrupt enable 20" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 19. 0x00 19. 0x08 19. " [19] ,FTC (Frame transfer complete) interrupt enable 19" "Disabled,Enabled"
setclrfld.long 0x00 18. 0x00 18. 0x08 18. " [18] ,FTC (Frame transfer complete) interrupt enable 18" "Disabled,Enabled"
setclrfld.long 0x00 17. 0x00 17. 0x08 17. " [17] ,FTC (Frame transfer complete) interrupt enable 17" "Disabled,Enabled"
setclrfld.long 0x00 16. 0x00 16. 0x08 16. " [16] ,FTC (Frame transfer complete) interrupt enable 16" "Disabled,Enabled"
setclrfld.long 0x00 15. 0x00 15. 0x08 15. " [15] ,FTC (Frame transfer complete) interrupt enable 15" "Disabled,Enabled"
setclrfld.long 0x00 14. 0x00 14. 0x08 14. " [14] ,FTC (Frame transfer complete) interrupt enable 14" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 13. 0x00 13. 0x08 13. " [13] ,FTC (Frame transfer complete) interrupt enable 13" "Disabled,Enabled"
setclrfld.long 0x00 12. 0x00 12. 0x08 12. " [12] ,FTC (Frame transfer complete) interrupt enable 12" "Disabled,Enabled"
setclrfld.long 0x00 11. 0x00 11. 0x08 11. " [11] ,FTC (Frame transfer complete) interrupt enable 11" "Disabled,Enabled"
setclrfld.long 0x00 10. 0x00 10. 0x08 10. " [10] ,FTC (Frame transfer complete) interrupt enable 10" "Disabled,Enabled"
setclrfld.long 0x00 9. 0x00 9. 0x08 9. " [9] ,FTC (Frame transfer complete) interrupt enable 9" "Disabled,Enabled"
setclrfld.long 0x00 8. 0x00 8. 0x08 8. " [8] ,FTC (Frame transfer complete) interrupt enable 8" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 7. 0x00 7. 0x08 7. " [7] ,FTC (Frame transfer complete) interrupt enable 7" "Disabled,Enabled"
setclrfld.long 0x00 6. 0x00 6. 0x08 6. " [6] ,FTC (Frame transfer complete) interrupt enable 6" "Disabled,Enabled"
setclrfld.long 0x00 5. 0x00 5. 0x08 5. " [5] ,FTC (Frame transfer complete) interrupt enable 5" "Disabled,Enabled"
setclrfld.long 0x00 4. 0x00 4. 0x08 4. " [4] ,FTC (Frame transfer complete) interrupt enable 4" "Disabled,Enabled"
setclrfld.long 0x00 3. 0x00 3. 0x08 3. " [3] ,FTC (Frame transfer complete) interrupt enable 3" "Disabled,Enabled"
setclrfld.long 0x00 2. 0x00 2. 0x08 2. " [2] ,FTC (Frame transfer complete) interrupt enable 2" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 1. 0x00 1. 0x08 1. " [1] ,FTC (Frame transfer complete) interrupt enable 1" "Disabled,Enabled"
setclrfld.long 0x00 0. 0x00 0. 0x08 0. " [0] ,FTC (Frame transfer complete) interrupt enable 0" "Disabled,Enabled"
group.long 0xEC++0x03
line.long 0x00 "LFSINTEN,LFS INTERRUPT ENABLE"
setclrfld.long 0x00 31. 0x00 31. 0x08 31. " LFSINTENA_SET/CLR_[31] ,LFS (Last frame started) interrupt enable 31" "Disabled,Enabled"
setclrfld.long 0x00 30. 0x00 30. 0x08 30. " [30] ,LFS (Last frame started) interrupt enable 30" "Disabled,Enabled"
setclrfld.long 0x00 29. 0x00 29. 0x08 29. " [29] ,LFS (Last frame started) interrupt enable 29" "Disabled,Enabled"
setclrfld.long 0x00 28. 0x00 28. 0x08 28. " [28] ,LFS (Last frame started) interrupt enable 28" "Disabled,Enabled"
setclrfld.long 0x00 27. 0x00 27. 0x08 27. " [27] ,LFS (Last frame started) interrupt enable 27" "Disabled,Enabled"
setclrfld.long 0x00 26. 0x00 26. 0x08 26. " [26] ,LFS (Last frame started) interrupt enable 26" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 25. 0x00 25. 0x08 25. " [25] ,LFS (Last frame started) interrupt enable 25" "Disabled,Enabled"
setclrfld.long 0x00 24. 0x00 24. 0x08 24. " [24] ,LFS (Last frame started) interrupt enable 24" "Disabled,Enabled"
setclrfld.long 0x00 23. 0x00 23. 0x08 23. " [23] ,LFS (Last frame started) interrupt enable 23" "Disabled,Enabled"
setclrfld.long 0x00 22. 0x00 22. 0x08 22. " [22] ,LFS (Last frame started) interrupt enable 22" "Disabled,Enabled"
setclrfld.long 0x00 21. 0x00 21. 0x08 21. " [21] ,LFS (Last frame started) interrupt enable 21" "Disabled,Enabled"
setclrfld.long 0x00 20. 0x00 20. 0x08 20. " [20] ,LFS (Last frame started) interrupt enable 20" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 19. 0x00 19. 0x08 19. " [19] ,LFS (Last frame started) interrupt enable 19" "Disabled,Enabled"
setclrfld.long 0x00 18. 0x00 18. 0x08 18. " [18] ,LFS (Last frame started) interrupt enable 18" "Disabled,Enabled"
setclrfld.long 0x00 17. 0x00 17. 0x08 17. " [17] ,LFS (Last frame started) interrupt enable 17" "Disabled,Enabled"
setclrfld.long 0x00 16. 0x00 16. 0x08 16. " [16] ,LFS (Last frame started) interrupt enable 16" "Disabled,Enabled"
setclrfld.long 0x00 15. 0x00 15. 0x08 15. " [15] ,LFS (Last frame started) interrupt enable 15" "Disabled,Enabled"
setclrfld.long 0x00 14. 0x00 14. 0x08 14. " [14] ,LFS (Last frame started) interrupt enable 14" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 13. 0x00 13. 0x08 13. " [13] ,LFS (Last frame started) interrupt enable 13" "Disabled,Enabled"
setclrfld.long 0x00 12. 0x00 12. 0x08 12. " [12] ,LFS (Last frame started) interrupt enable 12" "Disabled,Enabled"
setclrfld.long 0x00 11. 0x00 11. 0x08 11. " [11] ,LFS (Last frame started) interrupt enable 11" "Disabled,Enabled"
setclrfld.long 0x00 10. 0x00 10. 0x08 10. " [10] ,LFS (Last frame started) interrupt enable 10" "Disabled,Enabled"
setclrfld.long 0x00 9. 0x00 9. 0x08 9. " [9] ,LFS (Last frame started) interrupt enable 9" "Disabled,Enabled"
setclrfld.long 0x00 8. 0x00 8. 0x08 8. " [8] ,LFS (Last frame started) interrupt enable 8" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 7. 0x00 7. 0x08 7. " [7] ,LFS (Last frame started) interrupt enable 7" "Disabled,Enabled"
setclrfld.long 0x00 6. 0x00 6. 0x08 6. " [6] ,LFS (Last frame started) interrupt enable 6" "Disabled,Enabled"
setclrfld.long 0x00 5. 0x00 5. 0x08 5. " [5] ,LFS (Last frame started) interrupt enable 5" "Disabled,Enabled"
setclrfld.long 0x00 4. 0x00 4. 0x08 4. " [4] ,LFS (Last frame started) interrupt enable 4" "Disabled,Enabled"
setclrfld.long 0x00 3. 0x00 3. 0x08 3. " [3] ,LFS (Last frame started) interrupt enable 3" "Disabled,Enabled"
setclrfld.long 0x00 2. 0x00 2. 0x08 2. " [2] ,LFS (Last frame started) interrupt enable 2" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 1. 0x00 1. 0x08 1. " [1] ,LFS (Last frame started) interrupt enable 1" "Disabled,Enabled"
setclrfld.long 0x00 0. 0x00 0. 0x08 0. " [0] ,LFS (Last frame started) interrupt enable 0" "Disabled,Enabled"
group.long 0xFC++0x03
line.long 0x00 "HBCINTENA,HBC INTERRUPT ENABLE"
setclrfld.long 0x00 31. 0x00 31. 0x08 31. " HBCINTENA_SET/CLR_[31] ,HBC (Half block complete) interrupt enable 31" "Disabled,Enabled"
setclrfld.long 0x00 30. 0x00 30. 0x08 30. " [30] ,HBC (Half block complete) interrupt enable 30" "Disabled,Enabled"
setclrfld.long 0x00 29. 0x00 29. 0x08 29. " [29] ,HBC (Half block complete) interrupt enable 29" "Disabled,Enabled"
setclrfld.long 0x00 28. 0x00 28. 0x08 28. " [28] ,HBC (Half block complete) interrupt enable 28" "Disabled,Enabled"
setclrfld.long 0x00 27. 0x00 27. 0x08 27. " [27] ,HBC (Half block complete) interrupt enable 27" "Disabled,Enabled"
setclrfld.long 0x00 26. 0x00 26. 0x08 26. " [26] ,HBC (Half block complete) interrupt enable 26" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 25. 0x00 25. 0x08 25. " [25] ,HBC (Half block complete) interrupt enable 25" "Disabled,Enabled"
setclrfld.long 0x00 24. 0x00 24. 0x08 24. " [24] ,HBC (Half block complete) interrupt enable 24" "Disabled,Enabled"
setclrfld.long 0x00 23. 0x00 23. 0x08 23. " [23] ,HBC (Half block complete) interrupt enable 23" "Disabled,Enabled"
setclrfld.long 0x00 22. 0x00 22. 0x08 22. " [22] ,HBC (Half block complete) interrupt enable 22" "Disabled,Enabled"
setclrfld.long 0x00 21. 0x00 21. 0x08 21. " [21] ,HBC (Half block complete) interrupt enable 21" "Disabled,Enabled"
setclrfld.long 0x00 20. 0x00 20. 0x08 20. " [20] ,HBC (Half block complete) interrupt enable 20" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 19. 0x00 19. 0x08 19. " [19] ,HBC (Half block complete) interrupt enable 19" "Disabled,Enabled"
setclrfld.long 0x00 18. 0x00 18. 0x08 18. " [18] ,HBC (Half block complete) interrupt enable 18" "Disabled,Enabled"
setclrfld.long 0x00 17. 0x00 17. 0x08 17. " [17] ,HBC (Half block complete) interrupt enable 17" "Disabled,Enabled"
setclrfld.long 0x00 16. 0x00 16. 0x08 16. " [16] ,HBC (Half block complete) interrupt enable 16" "Disabled,Enabled"
setclrfld.long 0x00 15. 0x00 15. 0x08 15. " [15] ,HBC (Half block complete) interrupt enable 15" "Disabled,Enabled"
setclrfld.long 0x00 14. 0x00 14. 0x08 14. " [14] ,HBC (Half block complete) interrupt enable 14" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 13. 0x00 13. 0x08 13. " [13] ,HBC (Half block complete) interrupt enable 13" "Disabled,Enabled"
setclrfld.long 0x00 12. 0x00 12. 0x08 12. " [12] ,HBC (Half block complete) interrupt enable 12" "Disabled,Enabled"
setclrfld.long 0x00 11. 0x00 11. 0x08 11. " [11] ,HBC (Half block complete) interrupt enable 11" "Disabled,Enabled"
setclrfld.long 0x00 10. 0x00 10. 0x08 10. " [10] ,HBC (Half block complete) interrupt enable 10" "Disabled,Enabled"
setclrfld.long 0x00 9. 0x00 9. 0x08 9. " [9] ,HBC (Half block complete) interrupt enable 9" "Disabled,Enabled"
setclrfld.long 0x00 8. 0x00 8. 0x08 8. " [8] ,HBC (Half block complete) interrupt enable 8" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 7. 0x00 7. 0x08 7. " [7] ,HBC (Half block complete) interrupt enable 7" "Disabled,Enabled"
setclrfld.long 0x00 6. 0x00 6. 0x08 6. " [6] ,HBC (Half block complete) interrupt enable 6" "Disabled,Enabled"
setclrfld.long 0x00 5. 0x00 5. 0x08 5. " [5] ,HBC (Half block complete) interrupt enable 5" "Disabled,Enabled"
setclrfld.long 0x00 4. 0x00 4. 0x08 4. " [4] ,HBC (Half block complete) interrupt enable 4" "Disabled,Enabled"
setclrfld.long 0x00 3. 0x00 3. 0x08 3. " [3] ,HBC (Half block complete) interrupt enable 3" "Disabled,Enabled"
setclrfld.long 0x00 2. 0x00 2. 0x08 2. " [2] ,HBC (Half block complete) interrupt enable 2" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 1. 0x00 1. 0x08 1. " [1] ,HBC (Half block complete) interrupt enable 1" "Disabled,Enabled"
setclrfld.long 0x00 0. 0x00 0. 0x08 0. " [0] ,HBC (Half block complete) interrupt enable 0" "Disabled,Enabled"
group.long 0x10C++0x03
line.long 0x00 "BTCINTENA,BTC INTERRUPT ENABLE"
setclrfld.long 0x00 31. 0x00 31. 0x00 31. " BTCINTENA_SET/CLR_[31] ,BTC (Block transfer complete) interrupt enable 31" "Disabled,Enabled"
setclrfld.long 0x00 30. 0x00 30. 0x00 30. " [30] ,BTC (Block transfer complete) interrupt enable 30" "Disabled,Enabled"
setclrfld.long 0x00 29. 0x00 29. 0x00 29. " [29] ,BTC (Block transfer complete) interrupt enable 29" "Disabled,Enabled"
setclrfld.long 0x00 28. 0x00 28. 0x00 28. " [28] ,BTC (Block transfer complete) interrupt enable 28" "Disabled,Enabled"
setclrfld.long 0x00 27. 0x00 27. 0x00 27. " [27] ,BTC (Block transfer complete) interrupt enable 27" "Disabled,Enabled"
setclrfld.long 0x00 26. 0x00 26. 0x00 26. " [26] ,BTC (Block transfer complete) interrupt enable 26" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 25. 0x00 25. 0x00 25. " [25] ,BTC (Block transfer complete) interrupt enable 25" "Disabled,Enabled"
setclrfld.long 0x00 24. 0x00 24. 0x00 24. " [24] ,BTC (Block transfer complete) interrupt enable 24" "Disabled,Enabled"
setclrfld.long 0x00 23. 0x00 23. 0x00 23. " [23] ,BTC (Block transfer complete) interrupt enable 23" "Disabled,Enabled"
setclrfld.long 0x00 22. 0x00 22. 0x00 22. " [22] ,BTC (Block transfer complete) interrupt enable 22" "Disabled,Enabled"
setclrfld.long 0x00 21. 0x00 21. 0x00 21. " [21] ,BTC (Block transfer complete) interrupt enable 21" "Disabled,Enabled"
setclrfld.long 0x00 20. 0x00 20. 0x00 20. " [20] ,BTC (Block transfer complete) interrupt enable 20" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 19. 0x00 19. 0x00 19. " [19] ,BTC (Block transfer complete) interrupt enable 19" "Disabled,Enabled"
setclrfld.long 0x00 18. 0x00 18. 0x00 18. " [18] ,BTC (Block transfer complete) interrupt enable 18" "Disabled,Enabled"
setclrfld.long 0x00 17. 0x00 17. 0x00 17. " [17] ,BTC (Block transfer complete) interrupt enable 17" "Disabled,Enabled"
setclrfld.long 0x00 16. 0x00 16. 0x00 16. " [16] ,BTC (Block transfer complete) interrupt enable 16" "Disabled,Enabled"
setclrfld.long 0x00 15. 0x00 15. 0x00 15. " [15] ,BTC (Block transfer complete) interrupt enable 15" "Disabled,Enabled"
setclrfld.long 0x00 14. 0x00 14. 0x00 14. " [14] ,BTC (Block transfer complete) interrupt enable 14" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 13. 0x00 13. 0x00 13. " [13] ,BTC (Block transfer complete) interrupt enable 13" "Disabled,Enabled"
setclrfld.long 0x00 12. 0x00 12. 0x00 12. " [12] ,BTC (Block transfer complete) interrupt enable 12" "Disabled,Enabled"
setclrfld.long 0x00 11. 0x00 11. 0x00 11. " [11] ,BTC (Block transfer complete) interrupt enable 11" "Disabled,Enabled"
setclrfld.long 0x00 10. 0x00 10. 0x00 10. " [10] ,BTC (Block transfer complete) interrupt enable 10" "Disabled,Enabled"
setclrfld.long 0x00 9. 0x00 9. 0x00 9. " [9] ,BTC (Block transfer complete) interrupt enable 9" "Disabled,Enabled"
setclrfld.long 0x00 8. 0x00 8. 0x00 8. " [8] ,BTC (Block transfer complete) interrupt enable 8" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 7. 0x00 7. 0x00 7. " [7] ,BTC (Block transfer complete) interrupt enable 7" "Disabled,Enabled"
setclrfld.long 0x00 6. 0x00 6. 0x00 6. " [6] ,BTC (Block transfer complete) interrupt enable 6" "Disabled,Enabled"
setclrfld.long 0x00 5. 0x00 5. 0x00 5. " [5] ,BTC (Block transfer complete) interrupt enable 5" "Disabled,Enabled"
setclrfld.long 0x00 4. 0x00 4. 0x00 4. " [4] ,BTC (Block transfer complete) interrupt enable 4" "Disabled,Enabled"
setclrfld.long 0x00 3. 0x00 3. 0x00 3. " [3] ,BTC (Block transfer complete) interrupt enable 3" "Disabled,Enabled"
setclrfld.long 0x00 2. 0x00 2. 0x00 2. " [2] ,BTC (Block transfer complete) interrupt enable 2" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 1. 0x00 1. 0x00 1. " [1] ,BTC (Block transfer complete) interrupt enable 1" "Disabled,Enabled"
setclrfld.long 0x00 0. 0x00 0. 0x00 0. " [0] ,BTC (Block transfer complete) interrupt enable 0" "Disabled,Enabled"
tree.end
width 10.
tree "Interrupt Flag Registers"
group.long 0x11C++0x03
line.long 0x00 "GINTFLAG,GLOBAL INTERRUPT FLAG Register"
bitfld.long 0x00 31. " GINT_[31] ,Global interrupt flag 31" "Not pending,Pending"
bitfld.long 0x00 30. " [30] ,Global interrupt flag 30" "Not pending,Pending"
bitfld.long 0x00 29. " [29] ,Global interrupt flag 29" "Not pending,Pending"
bitfld.long 0x00 28. " [28] ,Global interrupt flag 28" "Not pending,Pending"
bitfld.long 0x00 27. " [27] ,Global interrupt flag 27" "Not pending,Pending"
bitfld.long 0x00 26. " [26] ,Global interrupt flag 26" "Not pending,Pending"
textline " "
bitfld.long 0x00 25. " [25] ,Global interrupt flag 25" "Not pending,Pending"
bitfld.long 0x00 24. " [24] ,Global interrupt flag 24" "Not pending,Pending"
bitfld.long 0x00 23. " [23] ,Global interrupt flag 23" "Not pending,Pending"
bitfld.long 0x00 22. " [22] ,Global interrupt flag 22" "Not pending,Pending"
bitfld.long 0x00 21. " [21] ,Global interrupt flag 21" "Not pending,Pending"
bitfld.long 0x00 20. " [20] ,Global interrupt flag 20" "Not pending,Pending"
textline " "
bitfld.long 0x00 19. " [19] ,Global interrupt flag 19" "Not pending,Pending"
bitfld.long 0x00 18. " [18] ,Global interrupt flag 18" "Not pending,Pending"
bitfld.long 0x00 17. " [17] ,Global interrupt flag 17" "Not pending,Pending"
bitfld.long 0x00 16. " [16] ,Global interrupt flag 16" "Not pending,Pending"
bitfld.long 0x00 15. " [15] ,Global interrupt flag 15" "Not pending,Pending"
bitfld.long 0x00 14. " [14] ,Global interrupt flag 14" "Not pending,Pending"
textline " "
bitfld.long 0x00 13. " [13] ,Global interrupt flag 13" "Not pending,Pending"
bitfld.long 0x00 12. " [12] ,Global interrupt flag 12" "Not pending,Pending"
bitfld.long 0x00 11. " [11] ,Global interrupt flag 11" "Not pending,Pending"
bitfld.long 0x00 10. " [10] ,Global interrupt flag 10" "Not pending,Pending"
bitfld.long 0x00 9. " [9] ,Global interrupt flag 9" "Not pending,Pending"
bitfld.long 0x00 8. " [8] ,Global interrupt flag 8" "Not pending,Pending"
textline " "
bitfld.long 0x00 7. " [7] ,Global interrupt flag 7" "Not pending,Pending"
bitfld.long 0x00 6. " [6] ,Global interrupt flag 6" "Not pending,Pending"
bitfld.long 0x00 5. " [5] ,Global interrupt flag 5" "Not pending,Pending"
bitfld.long 0x00 4. " [4] ,Global interrupt flag 4" "Not pending,Pending"
bitfld.long 0x00 3. " [3] ,Global interrupt flag 3" "Not pending,Pending"
bitfld.long 0x00 2. " [2] ,Global interrupt flag 2" "Not pending,Pending"
textline " "
bitfld.long 0x00 1. " [1] ,Global interrupt flag 1" "Not pending,Pending"
bitfld.long 0x00 0. " [0] ,Global interrupt flag 0" "Not pending,Pending"
group.long 0x124++0x03
line.long 0x00 "FTCFLAG,FTC INTERRUPT FLAG Register"
eventfld.long 0x00 31. " FTCI_[31] ,Frame transfer complete flag 31" "Not pending,Pending"
eventfld.long 0x00 30. " [30] ,Frame transfer complete flag 30" "Not pending,Pending"
eventfld.long 0x00 29. " [29] ,Frame transfer complete flag 29" "Not pending,Pending"
eventfld.long 0x00 28. " [28] ,Frame transfer complete flag 28" "Not pending,Pending"
eventfld.long 0x00 27. " [27] ,Frame transfer complete flag 27" "Not pending,Pending"
eventfld.long 0x00 26. " [26] ,Frame transfer complete flag 26" "Not pending,Pending"
textline " "
eventfld.long 0x00 25. " [25] ,Frame transfer complete flag 25" "Not pending,Pending"
eventfld.long 0x00 24. " [24] ,Frame transfer complete flag 24" "Not pending,Pending"
eventfld.long 0x00 23. " [23] ,Frame transfer complete flag 23" "Not pending,Pending"
eventfld.long 0x00 22. " [22] ,Frame transfer complete flag 22" "Not pending,Pending"
eventfld.long 0x00 21. " [21] ,Frame transfer complete flag 21" "Not pending,Pending"
eventfld.long 0x00 20. " [20] ,Frame transfer complete flag 20" "Not pending,Pending"
textline " "
eventfld.long 0x00 19. " [19] ,Frame transfer complete flag 19" "Not pending,Pending"
eventfld.long 0x00 18. " [18] ,Frame transfer complete flag 18" "Not pending,Pending"
eventfld.long 0x00 17. " [17] ,Frame transfer complete flag 17" "Not pending,Pending"
eventfld.long 0x00 16. " [16] ,Frame transfer complete flag 16" "Not pending,Pending"
eventfld.long 0x00 15. " [15] ,Frame transfer complete flag 15" "Not pending,Pending"
eventfld.long 0x00 14. " [14] ,Frame transfer complete flag 14" "Not pending,Pending"
textline " "
eventfld.long 0x00 13. " [13] ,Frame transfer complete flag 13" "Not pending,Pending"
eventfld.long 0x00 12. " [12] ,Frame transfer complete flag 12" "Not pending,Pending"
eventfld.long 0x00 11. " [11] ,Frame transfer complete flag 11" "Not pending,Pending"
eventfld.long 0x00 10. " [10] ,Frame transfer complete flag 10" "Not pending,Pending"
eventfld.long 0x00 9. " [9] ,Frame transfer complete flag 9" "Not pending,Pending"
eventfld.long 0x00 8. " [8] ,Frame transfer complete flag 8" "Not pending,Pending"
textline " "
eventfld.long 0x00 7. " [7] ,Frame transfer complete flag 7" "Not pending,Pending"
eventfld.long 0x00 6. " [6] ,Frame transfer complete flag 6" "Not pending,Pending"
eventfld.long 0x00 5. " [5] ,Frame transfer complete flag 5" "Not pending,Pending"
eventfld.long 0x00 4. " [4] ,Frame transfer complete flag 4" "Not pending,Pending"
eventfld.long 0x00 3. " [3] ,Frame transfer complete flag 3" "Not pending,Pending"
eventfld.long 0x00 2. " [2] ,Frame transfer complete flag 2" "Not pending,Pending"
textline " "
eventfld.long 0x00 1. " [1] ,Frame transfer complete flag 1" "Not pending,Pending"
eventfld.long 0x00 0. " [0] ,Frame transfer complete flag 0" "Not pending,Pending"
group.long 0x12C++0x03
line.long 0x00 "LFSFLAG,LFS INTERRUPT FLAG Register"
eventfld.long 0x00 31. " LFSI_[31] ,Last frame transfer started flag 31" "Not pending,Pending"
eventfld.long 0x00 30. " [30] ,Last frame transfer started flag 30" "Not pending,Pending"
eventfld.long 0x00 29. " [29] ,Last frame transfer started flag 29" "Not pending,Pending"
eventfld.long 0x00 28. " [28] ,Last frame transfer started flag 28" "Not pending,Pending"
eventfld.long 0x00 27. " [27] ,Last frame transfer started flag 27" "Not pending,Pending"
eventfld.long 0x00 26. " [26] ,Last frame transfer started flag 26" "Not pending,Pending"
textline " "
eventfld.long 0x00 25. " [25] ,Last frame transfer started flag 25" "Not pending,Pending"
eventfld.long 0x00 24. " [24] ,Last frame transfer started flag 24" "Not pending,Pending"
eventfld.long 0x00 23. " [23] ,Last frame transfer started flag 23" "Not pending,Pending"
eventfld.long 0x00 22. " [22] ,Last frame transfer started flag 22" "Not pending,Pending"
eventfld.long 0x00 21. " [21] ,Last frame transfer started flag 21" "Not pending,Pending"
eventfld.long 0x00 20. " [20] ,Last frame transfer started flag 20" "Not pending,Pending"
textline " "
eventfld.long 0x00 19. " [19] ,Last frame transfer started flag 19" "Not pending,Pending"
eventfld.long 0x00 18. " [18] ,Last frame transfer started flag 18" "Not pending,Pending"
eventfld.long 0x00 17. " [17] ,Last frame transfer started flag 17" "Not pending,Pending"
eventfld.long 0x00 16. " [16] ,Last frame transfer started flag 16" "Not pending,Pending"
eventfld.long 0x00 15. " [15] ,Last frame transfer started flag 15" "Not pending,Pending"
eventfld.long 0x00 14. " [14] ,Last frame transfer started flag 14" "Not pending,Pending"
textline " "
eventfld.long 0x00 13. " [13] ,Last frame transfer started flag 13" "Not pending,Pending"
eventfld.long 0x00 12. " [12] ,Last frame transfer started flag 12" "Not pending,Pending"
eventfld.long 0x00 11. " [11] ,Last frame transfer started flag 11" "Not pending,Pending"
eventfld.long 0x00 10. " [10] ,Last frame transfer started flag 10" "Not pending,Pending"
eventfld.long 0x00 9. " [9] ,Last frame transfer started flag 9" "Not pending,Pending"
eventfld.long 0x00 8. " [8] ,Last frame transfer started flag 8" "Not pending,Pending"
textline " "
eventfld.long 0x00 7. " [7] ,Last frame transfer started flag 7" "Not pending,Pending"
eventfld.long 0x00 6. " [6] ,Last frame transfer started flag 6" "Not pending,Pending"
eventfld.long 0x00 5. " [5] ,Last frame transfer started flag 5" "Not pending,Pending"
eventfld.long 0x00 4. " [4] ,Last frame transfer started flag 4" "Not pending,Pending"
eventfld.long 0x00 3. " [3] ,Last frame transfer started flag 3" "Not pending,Pending"
eventfld.long 0x00 2. " [2] ,Last frame transfer started flag 2" "Not pending,Pending"
textline " "
eventfld.long 0x00 1. " [1] ,Last frame transfer started flag 1" "Not pending,Pending"
eventfld.long 0x00 0. " [0] ,Last frame transfer started flag 0" "Not pending,Pending"
group.long 0x134++0x03
line.long 0x00 "HBCFLAG,HBC INTERRUPT FLAG Register"
eventfld.long 0x00 31. " HBCI_[31] ,Half of block transfer complete flag 31" "Not pending,Pending"
eventfld.long 0x00 30. " [30] ,Half of block transfer complete flag 30" "Not pending,Pending"
eventfld.long 0x00 29. " [29] ,Half of block transfer complete flag 29" "Not pending,Pending"
eventfld.long 0x00 28. " [28] ,Half of block transfer complete flag 28" "Not pending,Pending"
eventfld.long 0x00 27. " [27] ,Half of block transfer complete flag 27" "Not pending,Pending"
eventfld.long 0x00 26. " [26] ,Half of block transfer complete flag 26" "Not pending,Pending"
textline " "
eventfld.long 0x00 25. " [25] ,Half of block transfer complete flag 25" "Not pending,Pending"
eventfld.long 0x00 24. " [24] ,Half of block transfer complete flag 24" "Not pending,Pending"
eventfld.long 0x00 23. " [23] ,Half of block transfer complete flag 23" "Not pending,Pending"
eventfld.long 0x00 22. " [22] ,Half of block transfer complete flag 22" "Not pending,Pending"
eventfld.long 0x00 21. " [21] ,Half of block transfer complete flag 21" "Not pending,Pending"
eventfld.long 0x00 20. " [20] ,Half of block transfer complete flag 20" "Not pending,Pending"
textline " "
eventfld.long 0x00 19. " [19] ,Half of block transfer complete flag 19" "Not pending,Pending"
eventfld.long 0x00 18. " [18] ,Half of block transfer complete flag 18" "Not pending,Pending"
eventfld.long 0x00 17. " [17] ,Half of block transfer complete flag 17" "Not pending,Pending"
eventfld.long 0x00 16. " [16] ,Half of block transfer complete flag 16" "Not pending,Pending"
eventfld.long 0x00 15. " [15] ,Half of block transfer complete flag 15" "Not pending,Pending"
eventfld.long 0x00 14. " [14] ,Half of block transfer complete flag 14" "Not pending,Pending"
textline " "
eventfld.long 0x00 13. " [13] ,Half of block transfer complete flag 13" "Not pending,Pending"
eventfld.long 0x00 12. " [12] ,Half of block transfer complete flag 12" "Not pending,Pending"
eventfld.long 0x00 11. " [11] ,Half of block transfer complete flag 11" "Not pending,Pending"
eventfld.long 0x00 10. " [10] ,Half of block transfer complete flag 10" "Not pending,Pending"
eventfld.long 0x00 9. " [9] ,Half of block transfer complete flag 9" "Not pending,Pending"
eventfld.long 0x00 8. " [8] ,Half of block transfer complete flag 8" "Not pending,Pending"
textline " "
eventfld.long 0x00 7. " [7] ,Half of block transfer complete flag 7" "Not pending,Pending"
eventfld.long 0x00 6. " [6] ,Half of block transfer complete flag 6" "Not pending,Pending"
eventfld.long 0x00 5. " [5] ,Half of block transfer complete flag 5" "Not pending,Pending"
eventfld.long 0x00 4. " [4] ,Half of block transfer complete flag 4" "Not pending,Pending"
eventfld.long 0x00 3. " [3] ,Half of block transfer complete flag 3" "Not pending,Pending"
eventfld.long 0x00 2. " [2] ,Half of block transfer complete flag 2" "Not pending,Pending"
textline " "
eventfld.long 0x00 1. " [1] ,Half of block transfer complete flag 1" "Not pending,Pending"
eventfld.long 0x00 0. " [0] ,Half of block transfer complete flag 0" "Not pending,Pending"
group.long 0x13C++0x03
line.long 0x00 "BTCFLAG,BER INTERRUPT FLAG Register"
eventfld.long 0x00 31. " BTCI_[31] ,Block transfer complete flag 31" "Not pending,Pending"
eventfld.long 0x00 30. " [30] ,Block transfer complete flag 30" "Not pending,Pending"
eventfld.long 0x00 29. " [29] ,Block transfer complete flag 29" "Not pending,Pending"
eventfld.long 0x00 28. " [28] ,Block transfer complete flag 28" "Not pending,Pending"
eventfld.long 0x00 27. " [27] ,Block transfer complete flag 27" "Not pending,Pending"
eventfld.long 0x00 26. " [26] ,Block transfer complete flag 26" "Not pending,Pending"
textline " "
eventfld.long 0x00 25. " [25] ,Block transfer complete flag 25" "Not pending,Pending"
eventfld.long 0x00 24. " [24] ,Block transfer complete flag 24" "Not pending,Pending"
eventfld.long 0x00 23. " [23] ,Block transfer complete flag 23" "Not pending,Pending"
eventfld.long 0x00 22. " [22] ,Block transfer complete flag 22" "Not pending,Pending"
eventfld.long 0x00 21. " [21] ,Block transfer complete flag 21" "Not pending,Pending"
eventfld.long 0x00 20. " [20] ,Block transfer complete flag 20" "Not pending,Pending"
textline " "
eventfld.long 0x00 19. " [19] ,Block transfer complete flag 19" "Not pending,Pending"
eventfld.long 0x00 18. " [18] ,Block transfer complete flag 18" "Not pending,Pending"
eventfld.long 0x00 17. " [17] ,Block transfer complete flag 17" "Not pending,Pending"
eventfld.long 0x00 16. " [16] ,Block transfer complete flag 16" "Not pending,Pending"
eventfld.long 0x00 15. " [15] ,Block transfer complete flag 15" "Not pending,Pending"
eventfld.long 0x00 14. " [14] ,Block transfer complete flag 14" "Not pending,Pending"
textline " "
eventfld.long 0x00 13. " [13] ,Block transfer complete flag 13" "Not pending,Pending"
eventfld.long 0x00 12. " [12] ,Block transfer complete flag 12" "Not pending,Pending"
eventfld.long 0x00 11. " [11] ,Block transfer complete flag 11" "Not pending,Pending"
eventfld.long 0x00 10. " [10] ,Block transfer complete flag 10" "Not pending,Pending"
eventfld.long 0x00 9. " [9] ,Block transfer complete flag 9" "Not pending,Pending"
eventfld.long 0x00 8. " [8] ,Block transfer complete flag 8" "Not pending,Pending"
textline " "
eventfld.long 0x00 7. " [7] ,Block transfer complete flag 7" "Not pending,Pending"
eventfld.long 0x00 6. " [6] ,Block transfer complete flag 6" "Not pending,Pending"
eventfld.long 0x00 5. " [5] ,Block transfer complete flag 5" "Not pending,Pending"
eventfld.long 0x00 4. " [4] ,Block transfer complete flag 4" "Not pending,Pending"
eventfld.long 0x00 3. " [3] ,Block transfer complete flag 3" "Not pending,Pending"
eventfld.long 0x00 2. " [2] ,Block transfer complete flag 2" "Not pending,Pending"
textline " "
eventfld.long 0x00 1. " [1] ,Block transfer complete flag 1" "Not pending,Pending"
eventfld.long 0x00 0. " [0] ,Block transfer complete flag 0" "Not pending,Pending"
group.long 0x144++0x03
line.long 0x00 "BERFLAG,BER INTERRUPT FLAG Register"
eventfld.long 0x00 31. " BERI_[31] ,Bus error flag 31" "Not pending,Pending"
eventfld.long 0x00 30. " [30] ,Bus error flag 30" "Not pending,Pending"
eventfld.long 0x00 29. " [29] ,Bus error flag 29" "Not pending,Pending"
eventfld.long 0x00 28. " [28] ,Bus error flag 28" "Not pending,Pending"
eventfld.long 0x00 27. " [27] ,Bus error flag 27" "Not pending,Pending"
eventfld.long 0x00 26. " [26] ,Bus error flag 26" "Not pending,Pending"
textline " "
eventfld.long 0x00 25. " [25] ,Bus error flag 25" "Not pending,Pending"
eventfld.long 0x00 24. " [24] ,Bus error flag 24" "Not pending,Pending"
eventfld.long 0x00 23. " [23] ,Bus error flag 23" "Not pending,Pending"
eventfld.long 0x00 22. " [22] ,Bus error flag 22" "Not pending,Pending"
eventfld.long 0x00 21. " [21] ,Bus error flag 21" "Not pending,Pending"
eventfld.long 0x00 20. " [20] ,Bus error flag 20" "Not pending,Pending"
textline " "
eventfld.long 0x00 19. " [19] ,Bus error flag 19" "Not pending,Pending"
eventfld.long 0x00 18. " [18] ,Bus error flag 18" "Not pending,Pending"
eventfld.long 0x00 17. " [17] ,Bus error flag 17" "Not pending,Pending"
eventfld.long 0x00 16. " [16] ,Bus error flag 16" "Not pending,Pending"
eventfld.long 0x00 15. " [15] ,Bus error flag 15" "Not pending,Pending"
eventfld.long 0x00 14. " [14] ,Bus error flag 14" "Not pending,Pending"
textline " "
eventfld.long 0x00 13. " [13] ,Bus error flag 13" "Not pending,Pending"
eventfld.long 0x00 12. " [12] ,Bus error flag 12" "Not pending,Pending"
eventfld.long 0x00 11. " [11] ,Bus error flag 11" "Not pending,Pending"
eventfld.long 0x00 10. " [10] ,Bus error flag 10" "Not pending,Pending"
eventfld.long 0x00 9. " [9] ,Bus error flag 9" "Not pending,Pending"
eventfld.long 0x00 8. " [8] ,Bus error flag 8" "Not pending,Pending"
textline " "
eventfld.long 0x00 7. " [7] ,Bus error flag 7" "Not pending,Pending"
eventfld.long 0x00 6. " [6] ,Bus error flag 6" "Not pending,Pending"
eventfld.long 0x00 5. " [5] ,Bus error flag 5" "Not pending,Pending"
eventfld.long 0x00 4. " [4] ,Bus error flag 4" "Not pending,Pending"
eventfld.long 0x00 3. " [3] ,Bus error flag 3" "Not pending,Pending"
eventfld.long 0x00 2. " [2] ,Bus error flag 2" "Not pending,Pending"
textline " "
eventfld.long 0x00 1. " [1] ,Bus error flag 1" "Not pending,Pending"
eventfld.long 0x00 0. " [0] ,Bus error flag 0" "Not pending,Pending"
tree.end
width 12.
tree "Interrupt Channel Offset Registers"
hgroup.long 0x14C++0x03
hide.long 0x00 "FTCAOFFSET,FTCA INTERRUPT CHANNEL OFFSET Register"
in
hgroup.long 0x150++0x03
hide.long 0x00 "LFSAOFFSET,LFSA INTERRUPT CHANNEL OFFSET Register"
in
hgroup.long 0x154++0x03
hide.long 0x00 "HBCAOFFSET,HBCA INTERRUPT CHANNEL OFFSET Register"
in
hgroup.long 0x158++0x03
hide.long 0x00 "BTCAOFFSET,BTCA INTERRUPT CHANNEL OFFSET Register"
in
hgroup.long 0x15C++0x03
hide.long 0x00 "BERAOFFSET,BERA INTERRUPT CHANNEL OFFSET Register"
in
hgroup.long 0x160++0x03
hide.long 0x00 "FTCBOFFSET,FTCB INTERRUPT CHANNEL OFFSET Register"
in
hgroup.long 0x164++0x03
hide.long 0x00 "LSFBOFFSET,LFSB INTERRUPT CHANNEL OFFSET Register"
in
hgroup.long 0x168++0x03
hide.long 0x00 "HBCBOFFSET,HBCB INTERRUPT CHANNEL OFFSET Register"
in
hgroup.long 0x16C++0x03
hide.long 0x00 "BTCBOFFSET,BTCB INTERRUPT CHANNEL OFFSET Register"
in
hgroup.long 0x170++0x03
hide.long 0x00 "BERBOFFSET,BERB INTERRUPT CHANNEL OFFSET Register"
in
tree.end
width 8.
textline " "
group.long 0x178++0x03
line.long 0x00 "PTCRL,PORT CONTROL Register"
rbitfld.long 0x00 24. " PENDB ,Port B transactions pending" "Not pending,Pending"
bitfld.long 0x00 18. " BYB ,Bypass FIFO B" "Not limited,Limited"
rbitfld.long 0x00 8. " PENDA ,Port A transactions pending" "Not pending,Pending"
bitfld.long 0x00 2. " BYA ,Bypass FIFO A" "Not limited,Limited"
textline " "
bitfld.long 0x00 1. " PSFRHQ ,High priority queue priority scheme" "Fixed,Rotated"
bitfld.long 0x00 0. " PSFRLQ ,Low priority queue priority scheme" "Fixed,Rotated"
group.long 0x17C++0x03
line.long 0x00 "RTCTRL,RAM TEST CONTROL"
bitfld.long 0x00 0. " RTC ,RAM test control" "Disabled,Enabled"
group.long 0x180++0x03
line.long 0x00 "DCTRL,DEBUG CONTROL"
rbitfld.long 0x00 24.--28. " CHNUM ,Channel number" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,Channel 8,Channel 9,Channel 10,Channel 11,Channel 12,Channel 13,Channel 14,Channel 15,Channel 16,Channel 17,Channel 18,Channel 19,Channel 20,Channel 21,Channel 22,Channel 23,Channel 24,Channel 25,Channel 26,Channel 27,Channel 28,Channel 29,Channel 30,Channel 31"
eventfld.long 0x00 16. " DMADBGS ,DMA debug status" "Not detected,Detected"
bitfld.long 0x00 0. " DBGEN ,Debug enable" "Disabled,Enabled"
group.long 0x184++0x03
line.long 0x00 "WPR,Watch Point Register"
group.long 0x188++0x03
line.long 0x00 "WMR,WATCH MASK Register"
bitfld.long 0x00 31. " WM ,Watch mask 31" "0,1"
bitfld.long 0x00 30. ",Watch mask 30" "0,1"
bitfld.long 0x00 29. ",Watch mask 29" "0,1"
bitfld.long 0x00 28. ",Watch mask 28" "0,1"
bitfld.long 0x00 27. ",Watch mask 27" "0,1"
bitfld.long 0x00 26. ",Watch mask 26" "0,1"
bitfld.long 0x00 25. ",Watch mask 25" "0,1"
bitfld.long 0x00 24. ",Watch mask 24" "0,1"
bitfld.long 0x00 23. ",Watch mask 23" "0,1"
bitfld.long 0x00 22. ",Watch mask 22" "0,1"
bitfld.long 0x00 21. ",Watch mask 21" "0,1"
bitfld.long 0x00 20. ",Watch mask 20" "0,1"
bitfld.long 0x00 19. ",Watch mask 19" "0,1"
bitfld.long 0x00 18. ",Watch mask 18" "0,1"
bitfld.long 0x00 17. ",Watch mask 17" "0,1"
bitfld.long 0x00 16. ",Watch mask 16" "0,1"
bitfld.long 0x00 15. ",Watch mask 15" "0,1"
bitfld.long 0x00 14. ",Watch mask 14" "0,1"
bitfld.long 0x00 13. ",Watch mask 13" "0,1"
bitfld.long 0x00 12. ",Watch mask 12" "0,1"
bitfld.long 0x00 11. ",Watch mask 11" "0,1"
bitfld.long 0x00 10. ",Watch mask 10" "0,1"
bitfld.long 0x00 9. ",Watch mask 9" "0,1"
bitfld.long 0x00 8. ",Watch mask 8" "0,1"
bitfld.long 0x00 7. ",Watch mask 7" "0,1"
bitfld.long 0x00 6. ",Watch mask 6" "0,1"
bitfld.long 0x00 5. ",Watch mask 5" "0,1"
bitfld.long 0x00 4. ",Watch mask 4" "0,1"
bitfld.long 0x00 3. ",Watch mask 3" "0,1"
bitfld.long 0x00 2. ",Watch mask 2" "0,1"
bitfld.long 0x00 1. ",Watch mask 1" "0,1"
bitfld.long 0x00 0. ",Watch mask 0" "0,1"
width 11.
tree "Active Channel Registers"
rgroup.long 0x18C++0x0B
line.long 0x00 "FAACSADDR,FIFO A Active Channel Source Address Register"
line.long 0x04 "FAACDADDR,FIFO A Active Channel Destination Address Register"
line.long 0x08 "FAACTC,FIFO A Active Channel Transfer Count Register"
hexmask.long.word 0x08 16.--28. 1. " FAFTCOUNT ,FIFO A active channel frame count"
hexmask.long.word 0x08 0.--12. 1. " FAETCOUNT ,FIFO A active channel element count"
rgroup.long 0x198++0x0B
line.long 0x00 "FBACSADDR,FIFO B ACTIVE CHANNEL SOURCE ADDRESS Register"
line.long 0x04 "FBACDADDR,FIFO B ACTIVE CHANNEL DESTINATION ADDRESS Register"
line.long 0x08 "PBACTC,FIFO B ACTIVE CHANNEL TRANSFER COUNT Register"
hexmask.long.word 0x08 16.--28. 1. " FBFTCOUNT ,FIFO B active channel frame count"
hexmask.long.word 0x08 0.--12. 1. " FBETCOUNT ,FIFO B active channel element count"
tree.end
width 8.
textline " "
group.long 0x1A8++0x03
line.long 0x00 "DMAPCR,PARITY CONTROL Register"
bitfld.long 0x00 16. " ERRA ,Error action" "Unchanged,Disabled"
bitfld.long 0x00 8. " TEST ,Test - parity bits memory mapping" "Not mapped,Mapped"
sif cpu()=="RM57L843-ZWT"
bitfld.long 0x00 0.--3. " ECC_ENA ,ECC enable" "Enabled,Enabled,Enabled,Enabled,Enabled,Disabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled"
else
bitfld.long 0x00 0.--3. " PARITY_ENA ,Parity error detection enable" "Enabled,Enabled,Enabled,Enabled,Enabled,Disabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled"
endif
group.long 0x1AC++0x03
line.long 0x00 "DMAPAR,Parity Error Address Register"
eventfld.long 0x00 24. " EDFLG ,Parity error detection flag" "No error,Error"
hexmask.long.word 0x00 0.--11. 1. " ERROR_ADDRESS ,Error address"
width 12.
tree "DMA Memory Protection Registers"
group.long 0x1B0++0x03
line.long 0x00 "DMAMPCTRL,Memory Protection Control Register"
bitfld.long 0x00 28. " INT3AB ,Interrupt assignment of region 3 to group A/B" "A,B"
bitfld.long 0x00 27. " INT3ENA ,Interrupt enable of region 3" "Disabled,Enabled"
bitfld.long 0x00 25.--26. " REG3AP ,Region 3 access permission" "R/W,Read,Write,Not allowed"
bitfld.long 0x00 24. " REG3ENA ,Region 3 enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 20. " INT2AB ,Interrupt assignment of region 2 to group A/B" "A,B"
bitfld.long 0x00 19. " INT2ENA ,Interrupt enable of region 2" "Disabled,Enabled"
bitfld.long 0x00 17.--18. " REG2AP ,Region 2 access permission" "R/W,Read,Write,Not allowed"
bitfld.long 0x00 16. " REG2ENA ,Region 2 enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 12. " INT1AB ,Interrupt assignment of region 1 to group A/B" "A,B"
bitfld.long 0x00 11. " INT1ENA ,Interrupt enable of region 1" "Disabled,Enabled"
bitfld.long 0x00 9.--10. " REG1AP ,Region 1 access permission" "R/W,Read,Write,Not allowed"
bitfld.long 0x00 8. " REG1ENA ,Region 1 enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 4. " INT0AB ,Interrupt assignment of region 0 to group A/B" "A,B"
bitfld.long 0x00 3. " INT0ENA ,Interrupt enable of region 0" "Disabled,Enabled"
bitfld.long 0x00 1.--2. " REG0AP ,Region 0 access permission" "R/W,Read,Write,Not allowed"
bitfld.long 0x00 0. " REG0ENA ,Region 0 enable" "Disabled,Enabled"
group.long 0x1B4++0x03
line.long 0x00 "DMAMPST,Memory Protection Status Register"
eventfld.long 0x00 24. " REG3FT ,Region 3 fault" "Not detected,Detected"
eventfld.long 0x00 16. " REG2FT ,Region 2 fault" "Not detected,Detected"
eventfld.long 0x00 8. " REG1FT ,Region 1 fault" "Not detected,Detected"
eventfld.long 0x00 0. " REG0FT ,Region 0 fault" "Not detected,Detected"
group.long 0x1B8++0x03
line.long 0x00 "DMAPR0S,Defines Starting Address Of Region 0"
group.long 0x1BC++0x03
line.long 0x00 "DMAPR0E,Defines End Address Of Region 0"
group.long 0x1C0++0x03
line.long 0x00 "DMAPR1S,Defines Starting Address Of Region 1"
group.long 0x1C4++0x03
line.long 0x00 "DMAPR1E,Defines End Address Of Region 1"
group.long 0x1C8++0x03
line.long 0x00 "DMAPR2S,Defines Starting Address Of Region 2"
group.long 0x1CC++0x03
line.long 0x00 "DMAPR2E,Defines End Address Of Region 2"
group.long 0x1D0++0x03
line.long 0x00 "DMAPR3S,Defines Starting Address Of Region 3"
group.long 0x1D4++0x03
line.long 0x00 "DMAPR3E,Defines End Address Of Region 3"
group.long 0x1D8++0x03
line.long 0x00 "DMAMPCTRL2,Memory Protection Control Register"
bitfld.long 0x00 28. " INT7AB ,Interrupt assignment of region 7 to group A/B" "A,B"
bitfld.long 0x00 27. " INT7ENA ,Interrupt enable of region 7" "Disabled,Enabled"
bitfld.long 0x00 25.--26. " REG7AP ,Region 7 access permission" "R/W,Read,Write,Not allowed"
bitfld.long 0x00 24. " REG7ENA ,Region 7 enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 20. " INT6AB ,Interrupt assignment of region 6 to group A/B" "A,B"
bitfld.long 0x00 19. " INT6ENA ,Interrupt enable of region 6" "Disabled,Enabled"
bitfld.long 0x00 17.--18. " REG6AP ,Region 6 access permission" "R/W,Read,Write,Not allowed"
bitfld.long 0x00 16. " REG6ENA ,Region 6 enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 12. " INT5AB ,Interrupt assignment of region 5 to group A/B" "A,B"
bitfld.long 0x00 11. " INT5ENA ,Interrupt enable of region 5" "Disabled,Enabled"
bitfld.long 0x00 9.--10. " REG5AP ,Region 5 access permission" "R/W,Read,Write,Not allowed"
bitfld.long 0x00 8. " REG5ENA ,Region 5 enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 4. " INT4AB ,Interrupt assignment of region 4 to group A/B" "A,B"
bitfld.long 0x00 3. " INT4ENA ,Interrupt enable of region 4" "Disabled,Enabled"
bitfld.long 0x00 1.--2. " REG4AP ,Region 4 access permission" "R/W,Read,Write,Not allowed"
bitfld.long 0x00 0. " REG4ENA ,Region 4 enable" "Disabled,Enabled"
group.long 0x1DC++0x03
line.long 0x00 "DMAMPST2,Memory Protection Status Register"
eventfld.long 0x00 24. " REG7FT ,Region 7 fault" "Not detected,Detected"
eventfld.long 0x00 16. " REG6FT ,Region 6 fault" "Not detected,Detected"
eventfld.long 0x00 8. " REG5FT ,Region 5 fault" "Not detected,Detected"
eventfld.long 0x00 0. " REG4FT ,Region 4 fault" "Not detected,Detected"
group.long 0x1E0++0x03
line.long 0x00 "DMAPR4S,Defines Starting Address Of Region 4"
group.long 0x1E4++0x03
line.long 0x00 "DMAPR4E,Defines End Address Of Region 4"
group.long 0x1E8++0x03
line.long 0x00 "DMAPR5S,Defines Starting Address Of Region 5"
group.long 0x1EC++0x03
line.long 0x00 "DMAPR5E,Defines End Address Of Region 5"
group.long 0x1F0++0x03
line.long 0x00 "DMAPR6S,Defines Starting Address Of Region 6"
group.long 0x1F4++0x03
line.long 0x00 "DMAPR6E,Defines End Address Of Region 6"
group.long 0x1F8++0x03
line.long 0x00 "DMAPR7S,Defines Starting Address Of Region 7"
group.long 0x1FC++0x03
line.long 0x00 "DMAPR7E,Defines End Address Of Region 7"
tree.end
width 13.
textline " "
group.long 0x228++0x03
line.long 0x00 "DMASECCCTRL,DMA Single Bit ECC Control Register"
eventfld.long 0x00 16. " SBERR ,Error action" "No error,Error"
bitfld.long 0x00 8.--11. " SBE_EVT_EN ,Single bit error enable" ",,,,,Disabled,,,,,Enabled,?..."
bitfld.long 0x00 0.--3. " EDACMODE ,EDAC mode" ",,,,,Disabled,,,,,Enabled,?..."
if (d.l(ad:0xFFFFF000+0x228)&0x10000)==0x10000
group.long 0x230++0x03
line.long 0x00 "DMAECCSBE,DMA ECC Single Bit Error Address Register"
hexmask.long.word 0x00 0.--11. 1. " ERRORADDRESS ,ECC error location DMA RAM address"
else
hgroup.long 0x230++0x03
hide.long 0x00 "DMAECCSBE,DMA ECC Single Bit Error Address Register"
endif
rgroup.long 0x240++0x07
line.long 0x00 "FIFOASTAT,FIFO A Status Register"
bitfld.long 0x00 31. " FFACH[31] ,FIFO A DMA channel 31 status" "Not processed,Processed"
bitfld.long 0x00 30. " [30] ,FIFO A DMA channel 30 status" "Not processed,Processed"
bitfld.long 0x00 29. " [29] ,FIFO A DMA channel 29 status" "Not processed,Processed"
bitfld.long 0x00 28. " [28] ,FIFO A DMA channel 28 status" "Not processed,Processed"
bitfld.long 0x00 27. " [27] ,FIFO A DMA channel 27 status" "Not processed,Processed"
bitfld.long 0x00 26. " [26] ,FIFO A DMA channel 26 status" "Not processed,Processed"
textline " "
bitfld.long 0x00 25. " [25] ,FIFO A DMA channel 25 status" "Not processed,Processed"
bitfld.long 0x00 24. " [24] ,FIFO A DMA channel 24 status" "Not processed,Processed"
bitfld.long 0x00 23. " [23] ,FIFO A DMA channel 23 status" "Not processed,Processed"
bitfld.long 0x00 22. " [22] ,FIFO A DMA channel 22 status" "Not processed,Processed"
bitfld.long 0x00 21. " [21] ,FIFO A DMA channel 21 status" "Not processed,Processed"
bitfld.long 0x00 20. " [20] ,FIFO A DMA channel 20 status" "Not processed,Processed"
textline " "
bitfld.long 0x00 19. " [19] ,FIFO A DMA channel 19 status" "Not processed,Processed"
bitfld.long 0x00 18. " [18] ,FIFO A DMA channel 18 status" "Not processed,Processed"
bitfld.long 0x00 17. " [17] ,FIFO A DMA channel 17 status" "Not processed,Processed"
bitfld.long 0x00 16. " [16] ,FIFO A DMA channel 16 status" "Not processed,Processed"
bitfld.long 0x00 15. " [15] ,FIFO A DMA channel 15 status" "Not processed,Processed"
bitfld.long 0x00 14. " [14] ,FIFO A DMA channel 14 status" "Not processed,Processed"
textline " "
bitfld.long 0x00 13. " [13] ,FIFO A DMA channel 13 status" "Not processed,Processed"
bitfld.long 0x00 12. " [12] ,FIFO A DMA channel 12 status" "Not processed,Processed"
bitfld.long 0x00 11. " [11] ,FIFO A DMA channel 11 status" "Not processed,Processed"
bitfld.long 0x00 10. " [10] ,FIFO A DMA channel 10 status" "Not processed,Processed"
bitfld.long 0x00 9. " [9] ,FIFO A DMA channel 9 status" "Not processed,Processed"
bitfld.long 0x00 8. " [8] ,FIFO A DMA channel 8 status" "Not processed,Processed"
textline " "
bitfld.long 0x00 7. " [7] ,FIFO A DMA channel 7 status" "Not processed,Processed"
bitfld.long 0x00 6. " [6] ,FIFO A DMA channel 6 status" "Not processed,Processed"
bitfld.long 0x00 5. " [5] ,FIFO A DMA channel 5 status" "Not processed,Processed"
bitfld.long 0x00 4. " [4] ,FIFO A DMA channel 4 status" "Not processed,Processed"
bitfld.long 0x00 3. " [3] ,FIFO A DMA channel 3 status" "Not processed,Processed"
bitfld.long 0x00 2. " [2] ,FIFO A DMA channel 2 status" "Not processed,Processed"
textline " "
bitfld.long 0x00 1. " [1] ,FIFO A DMA channel 1 status" "Not processed,Processed"
bitfld.long 0x00 0. " [0] ,FIFO A DMA channel 0 status" "Not processed,Processed"
line.long 0x04 "FIFOBSTAT,FIFO B Status Register"
bitfld.long 0x04 31. " FFBCH[31] ,FIFO B DMA channel 31 status" "Not processed,Processed"
bitfld.long 0x04 30. " [30] ,FIFO B DMA channel 30 status" "Not processed,Processed"
bitfld.long 0x04 29. " [29] ,FIFO B DMA channel 29 status" "Not processed,Processed"
bitfld.long 0x04 28. " [28] ,FIFO B DMA channel 28 status" "Not processed,Processed"
bitfld.long 0x04 27. " [27] ,FIFO B DMA channel 27 status" "Not processed,Processed"
bitfld.long 0x04 26. " [26] ,FIFO B DMA channel 26 status" "Not processed,Processed"
textline " "
bitfld.long 0x04 25. " [25] ,FIFO B DMA channel 25 status" "Not processed,Processed"
bitfld.long 0x04 24. " [24] ,FIFO B DMA channel 24 status" "Not processed,Processed"
bitfld.long 0x04 23. " [23] ,FIFO B DMA channel 23 status" "Not processed,Processed"
bitfld.long 0x04 22. " [22] ,FIFO B DMA channel 22 status" "Not processed,Processed"
bitfld.long 0x04 21. " [21] ,FIFO B DMA channel 21 status" "Not processed,Processed"
bitfld.long 0x04 20. " [20] ,FIFO B DMA channel 20 status" "Not processed,Processed"
textline " "
bitfld.long 0x04 19. " [19] ,FIFO B DMA channel 19 status" "Not processed,Processed"
bitfld.long 0x04 18. " [18] ,FIFO B DMA channel 18 status" "Not processed,Processed"
bitfld.long 0x04 17. " [17] ,FIFO B DMA channel 17 status" "Not processed,Processed"
bitfld.long 0x04 16. " [16] ,FIFO B DMA channel 16 status" "Not processed,Processed"
bitfld.long 0x04 15. " [15] ,FIFO B DMA channel 15 status" "Not processed,Processed"
bitfld.long 0x04 14. " [14] ,FIFO B DMA channel 14 status" "Not processed,Processed"
textline " "
bitfld.long 0x04 13. " [13] ,FIFO B DMA channel 13 status" "Not processed,Processed"
bitfld.long 0x04 12. " [12] ,FIFO B DMA channel 12 status" "Not processed,Processed"
bitfld.long 0x04 11. " [11] ,FIFO B DMA channel 11 status" "Not processed,Processed"
bitfld.long 0x04 10. " [10] ,FIFO B DMA channel 10 status" "Not processed,Processed"
bitfld.long 0x04 9. " [9] ,FIFO B DMA channel 9 status" "Not processed,Processed"
bitfld.long 0x04 8. " [8] ,FIFO B DMA channel 8 status" "Not processed,Processed"
textline " "
bitfld.long 0x04 7. " [7] ,FIFO B DMA channel 7 status" "Not processed,Processed"
bitfld.long 0x04 6. " [6] ,FIFO B DMA channel 6 status" "Not processed,Processed"
bitfld.long 0x04 5. " [5] ,FIFO B DMA channel 5 status" "Not processed,Processed"
bitfld.long 0x04 4. " [4] ,FIFO B DMA channel 4 status" "Not processed,Processed"
bitfld.long 0x04 3. " [3] ,FIFO B DMA channel 3 status" "Not processed,Processed"
bitfld.long 0x04 2. " [2] ,FIFO B DMA channel 2 status" "Not processed,Processed"
textline " "
bitfld.long 0x04 1. " [1] ,FIFO B DMA channel 1 status" "Not processed,Processed"
bitfld.long 0x04 0. " [0] ,FIFO B DMA channel 0 status" "Not processed,Processed"
textline " "
group.long 0x330++0x07
line.long 0x00 "DMAREQPS1,DMA Request Polarity Select Register 1"
bitfld.long 0x00 15. " DMAREQPS_[47] ,Polarity selection for DMA request line 47" "Active high,Active low"
bitfld.long 0x00 14. " [46] ,Polarity selection for DMA request line 46" "Active high,Active low"
bitfld.long 0x00 13. " [45] ,Polarity selection for DMA request line 45" "Active high,Active low"
bitfld.long 0x00 12. " [44] ,Polarity selection for DMA request line 44" "Active high,Active low"
bitfld.long 0x00 11. " [43] ,Polarity selection for DMA request line 43" "Active high,Active low"
bitfld.long 0x00 10. " [42] ,Polarity selection for DMA request line 42" "Active high,Active low"
textline " "
bitfld.long 0x00 9. " [41] ,Polarity selection for DMA request line 41" "Active high,Active low"
bitfld.long 0x00 8. " [40] ,Polarity selection for DMA request line 40" "Active high,Active low"
bitfld.long 0x00 7. " [39] ,Polarity selection for DMA request line 39" "Active high,Active low"
bitfld.long 0x00 6. " [38] ,Polarity selection for DMA request line 38" "Active high,Active low"
bitfld.long 0x00 5. " [37] ,Polarity selection for DMA request line 37" "Active high,Active low"
bitfld.long 0x00 4. " [36] ,Polarity selection for DMA request line 36" "Active high,Active low"
textline " "
bitfld.long 0x00 3. " [35] ,Polarity selection for DMA request line 35" "Active high,Active low"
bitfld.long 0x00 2. " [34] ,Polarity selection for DMA request line 34" "Active high,Active low"
bitfld.long 0x00 1. " [33] ,Polarity selection for DMA request line 33" "Active high,Active low"
bitfld.long 0x00 0. " [32] ,Polarity selection for DMA request line 32" "Active high,Active low"
line.long 0x04 "DMAREQPS0,DMA Request Polarity Select Register 0"
bitfld.long 0x04 31. " DMAREQPS_[31] ,Polarity selection for DMA request line 31" "Active high,Active low"
bitfld.long 0x04 30. " [30] ,Polarity selection for DMA request line 30" "Active high,Active low"
bitfld.long 0x04 29. " [29] ,Polarity selection for DMA request line 29" "Active high,Active low"
bitfld.long 0x04 28. " [28] ,Polarity selection for DMA request line 28" "Active high,Active low"
bitfld.long 0x04 27. " [27] ,Polarity selection for DMA request line 27" "Active high,Active low"
bitfld.long 0x04 26. " [26] ,Polarity selection for DMA request line 26" "Active high,Active low"
textline " "
bitfld.long 0x04 25. " [25] ,Polarity selection for DMA request line 25" "Active high,Active low"
bitfld.long 0x04 24. " [24] ,Polarity selection for DMA request line 24" "Active high,Active low"
bitfld.long 0x04 23. " [23] ,Polarity selection for DMA request line 23" "Active high,Active low"
bitfld.long 0x04 22. " [22] ,Polarity selection for DMA request line 22" "Active high,Active low"
bitfld.long 0x04 21. " [21] ,Polarity selection for DMA request line 21" "Active high,Active low"
bitfld.long 0x04 20. " [20] ,Polarity selection for DMA request line 20" "Active high,Active low"
textline " "
bitfld.long 0x04 19. " [19] ,Polarity selection for DMA request line 19" "Active high,Active low"
bitfld.long 0x04 18. " [18] ,Polarity selection for DMA request line 18" "Active high,Active low"
bitfld.long 0x04 17. " [17] ,Polarity selection for DMA request line 17" "Active high,Active low"
bitfld.long 0x04 16. " [16] ,Polarity selection for DMA request line 16" "Active high,Active low"
bitfld.long 0x04 15. " [15] ,Polarity selection for DMA request line 15" "Active high,Active low"
bitfld.long 0x04 14. " [14] ,Polarity selection for DMA request line 14" "Active high,Active low"
textline " "
bitfld.long 0x04 13. " [13] ,Polarity selection for DMA request line 13" "Active high,Active low"
bitfld.long 0x04 12. " [12] ,Polarity selection for DMA request line 12" "Active high,Active low"
bitfld.long 0x04 11. " [11] ,Polarity selection for DMA request line 11" "Active high,Active low"
bitfld.long 0x04 10. " [10] ,Polarity selection for DMA request line 10" "Active high,Active low"
bitfld.long 0x04 9. " [9] ,Polarity selection for DMA request line 9" "Active high,Active low"
bitfld.long 0x04 8. " [8] ,Polarity selection for DMA request line 8" "Active high,Active low"
textline " "
bitfld.long 0x04 7. " [7] ,Polarity selection for DMA request line 7" "Active high,Active low"
bitfld.long 0x04 6. " [6] ,Polarity selection for DMA request line 6" "Active high,Active low"
bitfld.long 0x04 5. " [5] ,Polarity selection for DMA request line 5" "Active high,Active low"
bitfld.long 0x04 4. " [4] ,Polarity selection for DMA request line 4" "Active high,Active low"
bitfld.long 0x04 3. " [3] ,Polarity selection for DMA request line 3" "Active high,Active low"
bitfld.long 0x04 2. " [2] ,Polarity selection for DMA request line 2" "Active high,Active low"
textline " "
bitfld.long 0x04 1. " [1] ,Polarity selection for DMA request line 1" "Active high,Active low"
bitfld.long 0x04 0. " [0] ,Polarity selection for DMA request line 0" "Active high,Active low"
textline " "
group.long 0x340++0x07
line.long 0x00 "TERECTRL,Transaction Parity Error Event Control Register"
eventfld.long 0x00 16. " TER_ERR ,Transactions parity error status" "No error,Error"
bitfld.long 0x00 0.--3. " TER_EN ,Transaction error event detection enable" ",,,,,Disabled,,,,,Enabled,?..."
textline " "
line.long 0x04 "TERFLAG,TER Event Flag Register"
eventfld.long 0x04 31. " TERE_[31] ,Transaction parity error event pending channel 31" "Not pending,Pending"
eventfld.long 0x04 30. " [30] ,Transaction parity error event pending channel 30" "Not pending,Pending"
eventfld.long 0x04 29. " [29] ,Transaction parity error event pending channel 29" "Not pending,Pending"
eventfld.long 0x04 28. " [28] ,Transaction parity error event pending channel 28" "Not pending,Pending"
eventfld.long 0x04 27. " [27] ,Transaction parity error event pending channel 27" "Not pending,Pending"
eventfld.long 0x04 26. " [26] ,Transaction parity error event pending channel 26" "Not pending,Pending"
textline " "
eventfld.long 0x04 25. " [25] ,Transaction parity error event pending channel 25" "Not pending,Pending"
eventfld.long 0x04 24. " [24] ,Transaction parity error event pending channel 24" "Not pending,Pending"
eventfld.long 0x04 23. " [23] ,Transaction parity error event pending channel 23" "Not pending,Pending"
eventfld.long 0x04 22. " [22] ,Transaction parity error event pending channel 22" "Not pending,Pending"
eventfld.long 0x04 21. " [21] ,Transaction parity error event pending channel 21" "Not pending,Pending"
eventfld.long 0x04 20. " [20] ,Transaction parity error event pending channel 20" "Not pending,Pending"
textline " "
eventfld.long 0x04 19. " [19] ,Transaction parity error event pending channel 19" "Not pending,Pending"
eventfld.long 0x04 18. " [18] ,Transaction parity error event pending channel 18" "Not pending,Pending"
eventfld.long 0x04 17. " [17] ,Transaction parity error event pending channel 17" "Not pending,Pending"
eventfld.long 0x04 16. " [16] ,Transaction parity error event pending channel 16" "Not pending,Pending"
eventfld.long 0x04 15. " [15] ,Transaction parity error event pending channel 15" "Not pending,Pending"
eventfld.long 0x04 14. " [14] ,Transaction parity error event pending channel 14" "Not pending,Pending"
textline " "
eventfld.long 0x04 13. " [13] ,Transaction parity error event pending channel 13" "Not pending,Pending"
eventfld.long 0x04 12. " [12] ,Transaction parity error event pending channel 12" "Not pending,Pending"
eventfld.long 0x04 11. " [11] ,Transaction parity error event pending channel 11" "Not pending,Pending"
eventfld.long 0x04 10. " [10] ,Transaction parity error event pending channel 10" "Not pending,Pending"
eventfld.long 0x04 9. " [9] ,Transaction parity error event pending channel 9" "Not pending,Pending"
eventfld.long 0x04 8. " [8] ,Transaction parity error event pending channel 8" "Not pending,Pending"
textline " "
eventfld.long 0x04 7. " [7] ,Transaction parity error event pending channel 7" "Not pending,Pending"
eventfld.long 0x04 6. " [6] ,Transaction parity error event pending channel 6" "Not pending,Pending"
eventfld.long 0x04 5. " [5] ,Transaction parity error event pending channel 5" "Not pending,Pending"
eventfld.long 0x04 4. " [4] ,Transaction parity error event pending channel 4" "Not pending,Pending"
eventfld.long 0x04 3. " [3] ,Transaction parity error event pending channel 3" "Not pending,Pending"
eventfld.long 0x04 2. " [2] ,Transaction parity error event pending channel 2" "Not pending,Pending"
textline " "
eventfld.long 0x04 1. " [1] ,Transaction parity error event pending channel 1" "Not pending,Pending"
eventfld.long 0x04 0. " [0] ,Transaction parity error event pending channel 0" "Not pending,Pending"
rgroup.long 0x348++0x03
line.long 0x00 "TERROFFSET,TER Event Channel Offset Register"
bitfld.long 0x00 0.--5. " TER_OFF ,Transaction parity error occurrence first channel" "No interrupt,Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,Channel 8,Channel 9,Channel 10,Channel 11,Channel 12,Channel 13,Channel 14,Channel 15,Channel 16,Channel 17,Channel 18,Channel 19,Channel 20,Channel 21,Channel 22,Channel 23,Channel 24,Channel 25,Channel 26,Channel 27,Channel 28,Channel 29,Channel 30,Channel 31,?..."
base ad:0xFFF80000
width 9.
tree "Control Packet Registers"
tree "Primary Control Packet Registers"
tree "Primary Control Packet 0"
group.long 0x0++0x0B
line.long 0x00 "ISADDR,Initial Source Address Register"
line.long 0x04 "IDADDR,Initial Destination Address Register"
line.long 0x08 "ITCOUNT,Initial Transfer Count Register"
hexmask.long.word 0x08 16.--28. 1. " IFTCOUNT ,Initial frame transfer count"
hexmask.long.word 0x08 0.--12. 1. " IETCOUNT ,Initial element transfer count"
group.long (0x0+0x10)++0x0B
line.long 0x00 "CHCTRL,Channel Control Register"
bitfld.long 0x00 16.--21. " CHAIN ,Next channel to be triggered" "No channel,Ch0,Ch1,Ch2,Ch3,Ch4,Ch5,Ch6,Ch7,Ch8,Ch9,Ch10,Ch11,Ch12,Ch13,Ch14,Ch15,Ch16,Ch17,Ch18,Ch19,Ch20,Ch21,Ch22,Ch23,Ch24,Ch25,Ch26,Ch27,Ch28,Ch29,Ch30,Ch31,?..."
bitfld.long 0x00 14.--15. " RES ,Read element size" "8 bits,16 bits,32 bits,64 bits"
textline " "
bitfld.long 0x00 12.--13. " WES ,Write element size" "8 bits,16 bits,32 bits,64 bits"
bitfld.long 0x00 8. " TTYPE ,Transfer type" "Frame,Block"
textline " "
bitfld.long 0x00 3.--4. " ADDMR ,Addressing mode read" "Constant,Post-increment,,Indexed"
bitfld.long 0x00 1.--2. " ADDMW ,Addressing mode write" "Constant,Post-increment,,Indexed"
textline " "
bitfld.long 0x00 0. " AIM ,Autoinitiation mode" "Single block,Autoinitiation"
line.long 0x04 "EIOFF,Element Index Offset Register"
hexmask.long.word 0x04 16.--28. 1. " EIDXD ,Destination address element index"
hexmask.long.word 0x04 0.--12. 1. " EIDXS ,Source address element index"
line.long 0x08 "FIOFF,Frame Index Offset Register"
hexmask.long.word 0x08 16.--28. 1. " FIDXD ,Destination address frame index"
hexmask.long.word 0x08 0.--12. 1. " FIDXS ,Source address frame index"
tree.end
tree "Primary Control Packet 1"
group.long 0x20++0x0B
line.long 0x00 "ISADDR,Initial Source Address Register"
line.long 0x04 "IDADDR,Initial Destination Address Register"
line.long 0x08 "ITCOUNT,Initial Transfer Count Register"
hexmask.long.word 0x08 16.--28. 1. " IFTCOUNT ,Initial frame transfer count"
hexmask.long.word 0x08 0.--12. 1. " IETCOUNT ,Initial element transfer count"
group.long (0x20+0x10)++0x0B
line.long 0x00 "CHCTRL,Channel Control Register"
bitfld.long 0x00 16.--21. " CHAIN ,Next channel to be triggered" "No channel,Ch0,Ch1,Ch2,Ch3,Ch4,Ch5,Ch6,Ch7,Ch8,Ch9,Ch10,Ch11,Ch12,Ch13,Ch14,Ch15,Ch16,Ch17,Ch18,Ch19,Ch20,Ch21,Ch22,Ch23,Ch24,Ch25,Ch26,Ch27,Ch28,Ch29,Ch30,Ch31,?..."
bitfld.long 0x00 14.--15. " RES ,Read element size" "8 bits,16 bits,32 bits,64 bits"
textline " "
bitfld.long 0x00 12.--13. " WES ,Write element size" "8 bits,16 bits,32 bits,64 bits"
bitfld.long 0x00 8. " TTYPE ,Transfer type" "Frame,Block"
textline " "
bitfld.long 0x00 3.--4. " ADDMR ,Addressing mode read" "Constant,Post-increment,,Indexed"
bitfld.long 0x00 1.--2. " ADDMW ,Addressing mode write" "Constant,Post-increment,,Indexed"
textline " "
bitfld.long 0x00 0. " AIM ,Autoinitiation mode" "Single block,Autoinitiation"
line.long 0x04 "EIOFF,Element Index Offset Register"
hexmask.long.word 0x04 16.--28. 1. " EIDXD ,Destination address element index"
hexmask.long.word 0x04 0.--12. 1. " EIDXS ,Source address element index"
line.long 0x08 "FIOFF,Frame Index Offset Register"
hexmask.long.word 0x08 16.--28. 1. " FIDXD ,Destination address frame index"
hexmask.long.word 0x08 0.--12. 1. " FIDXS ,Source address frame index"
tree.end
tree "Primary Control Packet 2"
group.long 0x40++0x0B
line.long 0x00 "ISADDR,Initial Source Address Register"
line.long 0x04 "IDADDR,Initial Destination Address Register"
line.long 0x08 "ITCOUNT,Initial Transfer Count Register"
hexmask.long.word 0x08 16.--28. 1. " IFTCOUNT ,Initial frame transfer count"
hexmask.long.word 0x08 0.--12. 1. " IETCOUNT ,Initial element transfer count"
group.long (0x40+0x10)++0x0B
line.long 0x00 "CHCTRL,Channel Control Register"
bitfld.long 0x00 16.--21. " CHAIN ,Next channel to be triggered" "No channel,Ch0,Ch1,Ch2,Ch3,Ch4,Ch5,Ch6,Ch7,Ch8,Ch9,Ch10,Ch11,Ch12,Ch13,Ch14,Ch15,Ch16,Ch17,Ch18,Ch19,Ch20,Ch21,Ch22,Ch23,Ch24,Ch25,Ch26,Ch27,Ch28,Ch29,Ch30,Ch31,?..."
bitfld.long 0x00 14.--15. " RES ,Read element size" "8 bits,16 bits,32 bits,64 bits"
textline " "
bitfld.long 0x00 12.--13. " WES ,Write element size" "8 bits,16 bits,32 bits,64 bits"
bitfld.long 0x00 8. " TTYPE ,Transfer type" "Frame,Block"
textline " "
bitfld.long 0x00 3.--4. " ADDMR ,Addressing mode read" "Constant,Post-increment,,Indexed"
bitfld.long 0x00 1.--2. " ADDMW ,Addressing mode write" "Constant,Post-increment,,Indexed"
textline " "
bitfld.long 0x00 0. " AIM ,Autoinitiation mode" "Single block,Autoinitiation"
line.long 0x04 "EIOFF,Element Index Offset Register"
hexmask.long.word 0x04 16.--28. 1. " EIDXD ,Destination address element index"
hexmask.long.word 0x04 0.--12. 1. " EIDXS ,Source address element index"
line.long 0x08 "FIOFF,Frame Index Offset Register"
hexmask.long.word 0x08 16.--28. 1. " FIDXD ,Destination address frame index"
hexmask.long.word 0x08 0.--12. 1. " FIDXS ,Source address frame index"
tree.end
tree "Primary Control Packet 3"
group.long 0x60++0x0B
line.long 0x00 "ISADDR,Initial Source Address Register"
line.long 0x04 "IDADDR,Initial Destination Address Register"
line.long 0x08 "ITCOUNT,Initial Transfer Count Register"
hexmask.long.word 0x08 16.--28. 1. " IFTCOUNT ,Initial frame transfer count"
hexmask.long.word 0x08 0.--12. 1. " IETCOUNT ,Initial element transfer count"
group.long (0x60+0x10)++0x0B
line.long 0x00 "CHCTRL,Channel Control Register"
bitfld.long 0x00 16.--21. " CHAIN ,Next channel to be triggered" "No channel,Ch0,Ch1,Ch2,Ch3,Ch4,Ch5,Ch6,Ch7,Ch8,Ch9,Ch10,Ch11,Ch12,Ch13,Ch14,Ch15,Ch16,Ch17,Ch18,Ch19,Ch20,Ch21,Ch22,Ch23,Ch24,Ch25,Ch26,Ch27,Ch28,Ch29,Ch30,Ch31,?..."
bitfld.long 0x00 14.--15. " RES ,Read element size" "8 bits,16 bits,32 bits,64 bits"
textline " "
bitfld.long 0x00 12.--13. " WES ,Write element size" "8 bits,16 bits,32 bits,64 bits"
bitfld.long 0x00 8. " TTYPE ,Transfer type" "Frame,Block"
textline " "
bitfld.long 0x00 3.--4. " ADDMR ,Addressing mode read" "Constant,Post-increment,,Indexed"
bitfld.long 0x00 1.--2. " ADDMW ,Addressing mode write" "Constant,Post-increment,,Indexed"
textline " "
bitfld.long 0x00 0. " AIM ,Autoinitiation mode" "Single block,Autoinitiation"
line.long 0x04 "EIOFF,Element Index Offset Register"
hexmask.long.word 0x04 16.--28. 1. " EIDXD ,Destination address element index"
hexmask.long.word 0x04 0.--12. 1. " EIDXS ,Source address element index"
line.long 0x08 "FIOFF,Frame Index Offset Register"
hexmask.long.word 0x08 16.--28. 1. " FIDXD ,Destination address frame index"
hexmask.long.word 0x08 0.--12. 1. " FIDXS ,Source address frame index"
tree.end
tree "Primary Control Packet 4"
group.long 0x80++0x0B
line.long 0x00 "ISADDR,Initial Source Address Register"
line.long 0x04 "IDADDR,Initial Destination Address Register"
line.long 0x08 "ITCOUNT,Initial Transfer Count Register"
hexmask.long.word 0x08 16.--28. 1. " IFTCOUNT ,Initial frame transfer count"
hexmask.long.word 0x08 0.--12. 1. " IETCOUNT ,Initial element transfer count"
group.long (0x80+0x10)++0x0B
line.long 0x00 "CHCTRL,Channel Control Register"
bitfld.long 0x00 16.--21. " CHAIN ,Next channel to be triggered" "No channel,Ch0,Ch1,Ch2,Ch3,Ch4,Ch5,Ch6,Ch7,Ch8,Ch9,Ch10,Ch11,Ch12,Ch13,Ch14,Ch15,Ch16,Ch17,Ch18,Ch19,Ch20,Ch21,Ch22,Ch23,Ch24,Ch25,Ch26,Ch27,Ch28,Ch29,Ch30,Ch31,?..."
bitfld.long 0x00 14.--15. " RES ,Read element size" "8 bits,16 bits,32 bits,64 bits"
textline " "
bitfld.long 0x00 12.--13. " WES ,Write element size" "8 bits,16 bits,32 bits,64 bits"
bitfld.long 0x00 8. " TTYPE ,Transfer type" "Frame,Block"
textline " "
bitfld.long 0x00 3.--4. " ADDMR ,Addressing mode read" "Constant,Post-increment,,Indexed"
bitfld.long 0x00 1.--2. " ADDMW ,Addressing mode write" "Constant,Post-increment,,Indexed"
textline " "
bitfld.long 0x00 0. " AIM ,Autoinitiation mode" "Single block,Autoinitiation"
line.long 0x04 "EIOFF,Element Index Offset Register"
hexmask.long.word 0x04 16.--28. 1. " EIDXD ,Destination address element index"
hexmask.long.word 0x04 0.--12. 1. " EIDXS ,Source address element index"
line.long 0x08 "FIOFF,Frame Index Offset Register"
hexmask.long.word 0x08 16.--28. 1. " FIDXD ,Destination address frame index"
hexmask.long.word 0x08 0.--12. 1. " FIDXS ,Source address frame index"
tree.end
tree "Primary Control Packet 5"
group.long 0xA0++0x0B
line.long 0x00 "ISADDR,Initial Source Address Register"
line.long 0x04 "IDADDR,Initial Destination Address Register"
line.long 0x08 "ITCOUNT,Initial Transfer Count Register"
hexmask.long.word 0x08 16.--28. 1. " IFTCOUNT ,Initial frame transfer count"
hexmask.long.word 0x08 0.--12. 1. " IETCOUNT ,Initial element transfer count"
group.long (0xA0+0x10)++0x0B
line.long 0x00 "CHCTRL,Channel Control Register"
bitfld.long 0x00 16.--21. " CHAIN ,Next channel to be triggered" "No channel,Ch0,Ch1,Ch2,Ch3,Ch4,Ch5,Ch6,Ch7,Ch8,Ch9,Ch10,Ch11,Ch12,Ch13,Ch14,Ch15,Ch16,Ch17,Ch18,Ch19,Ch20,Ch21,Ch22,Ch23,Ch24,Ch25,Ch26,Ch27,Ch28,Ch29,Ch30,Ch31,?..."
bitfld.long 0x00 14.--15. " RES ,Read element size" "8 bits,16 bits,32 bits,64 bits"
textline " "
bitfld.long 0x00 12.--13. " WES ,Write element size" "8 bits,16 bits,32 bits,64 bits"
bitfld.long 0x00 8. " TTYPE ,Transfer type" "Frame,Block"
textline " "
bitfld.long 0x00 3.--4. " ADDMR ,Addressing mode read" "Constant,Post-increment,,Indexed"
bitfld.long 0x00 1.--2. " ADDMW ,Addressing mode write" "Constant,Post-increment,,Indexed"
textline " "
bitfld.long 0x00 0. " AIM ,Autoinitiation mode" "Single block,Autoinitiation"
line.long 0x04 "EIOFF,Element Index Offset Register"
hexmask.long.word 0x04 16.--28. 1. " EIDXD ,Destination address element index"
hexmask.long.word 0x04 0.--12. 1. " EIDXS ,Source address element index"
line.long 0x08 "FIOFF,Frame Index Offset Register"
hexmask.long.word 0x08 16.--28. 1. " FIDXD ,Destination address frame index"
hexmask.long.word 0x08 0.--12. 1. " FIDXS ,Source address frame index"
tree.end
tree "Primary Control Packet 6"
group.long 0xC0++0x0B
line.long 0x00 "ISADDR,Initial Source Address Register"
line.long 0x04 "IDADDR,Initial Destination Address Register"
line.long 0x08 "ITCOUNT,Initial Transfer Count Register"
hexmask.long.word 0x08 16.--28. 1. " IFTCOUNT ,Initial frame transfer count"
hexmask.long.word 0x08 0.--12. 1. " IETCOUNT ,Initial element transfer count"
group.long (0xC0+0x10)++0x0B
line.long 0x00 "CHCTRL,Channel Control Register"
bitfld.long 0x00 16.--21. " CHAIN ,Next channel to be triggered" "No channel,Ch0,Ch1,Ch2,Ch3,Ch4,Ch5,Ch6,Ch7,Ch8,Ch9,Ch10,Ch11,Ch12,Ch13,Ch14,Ch15,Ch16,Ch17,Ch18,Ch19,Ch20,Ch21,Ch22,Ch23,Ch24,Ch25,Ch26,Ch27,Ch28,Ch29,Ch30,Ch31,?..."
bitfld.long 0x00 14.--15. " RES ,Read element size" "8 bits,16 bits,32 bits,64 bits"
textline " "
bitfld.long 0x00 12.--13. " WES ,Write element size" "8 bits,16 bits,32 bits,64 bits"
bitfld.long 0x00 8. " TTYPE ,Transfer type" "Frame,Block"
textline " "
bitfld.long 0x00 3.--4. " ADDMR ,Addressing mode read" "Constant,Post-increment,,Indexed"
bitfld.long 0x00 1.--2. " ADDMW ,Addressing mode write" "Constant,Post-increment,,Indexed"
textline " "
bitfld.long 0x00 0. " AIM ,Autoinitiation mode" "Single block,Autoinitiation"
line.long 0x04 "EIOFF,Element Index Offset Register"
hexmask.long.word 0x04 16.--28. 1. " EIDXD ,Destination address element index"
hexmask.long.word 0x04 0.--12. 1. " EIDXS ,Source address element index"
line.long 0x08 "FIOFF,Frame Index Offset Register"
hexmask.long.word 0x08 16.--28. 1. " FIDXD ,Destination address frame index"
hexmask.long.word 0x08 0.--12. 1. " FIDXS ,Source address frame index"
tree.end
tree "Primary Control Packet 7"
group.long 0xE0++0x0B
line.long 0x00 "ISADDR,Initial Source Address Register"
line.long 0x04 "IDADDR,Initial Destination Address Register"
line.long 0x08 "ITCOUNT,Initial Transfer Count Register"
hexmask.long.word 0x08 16.--28. 1. " IFTCOUNT ,Initial frame transfer count"
hexmask.long.word 0x08 0.--12. 1. " IETCOUNT ,Initial element transfer count"
group.long (0xE0+0x10)++0x0B
line.long 0x00 "CHCTRL,Channel Control Register"
bitfld.long 0x00 16.--21. " CHAIN ,Next channel to be triggered" "No channel,Ch0,Ch1,Ch2,Ch3,Ch4,Ch5,Ch6,Ch7,Ch8,Ch9,Ch10,Ch11,Ch12,Ch13,Ch14,Ch15,Ch16,Ch17,Ch18,Ch19,Ch20,Ch21,Ch22,Ch23,Ch24,Ch25,Ch26,Ch27,Ch28,Ch29,Ch30,Ch31,?..."
bitfld.long 0x00 14.--15. " RES ,Read element size" "8 bits,16 bits,32 bits,64 bits"
textline " "
bitfld.long 0x00 12.--13. " WES ,Write element size" "8 bits,16 bits,32 bits,64 bits"
bitfld.long 0x00 8. " TTYPE ,Transfer type" "Frame,Block"
textline " "
bitfld.long 0x00 3.--4. " ADDMR ,Addressing mode read" "Constant,Post-increment,,Indexed"
bitfld.long 0x00 1.--2. " ADDMW ,Addressing mode write" "Constant,Post-increment,,Indexed"
textline " "
bitfld.long 0x00 0. " AIM ,Autoinitiation mode" "Single block,Autoinitiation"
line.long 0x04 "EIOFF,Element Index Offset Register"
hexmask.long.word 0x04 16.--28. 1. " EIDXD ,Destination address element index"
hexmask.long.word 0x04 0.--12. 1. " EIDXS ,Source address element index"
line.long 0x08 "FIOFF,Frame Index Offset Register"
hexmask.long.word 0x08 16.--28. 1. " FIDXD ,Destination address frame index"
hexmask.long.word 0x08 0.--12. 1. " FIDXS ,Source address frame index"
tree.end
tree "Primary Control Packet 8"
group.long 0x100++0x0B
line.long 0x00 "ISADDR,Initial Source Address Register"
line.long 0x04 "IDADDR,Initial Destination Address Register"
line.long 0x08 "ITCOUNT,Initial Transfer Count Register"
hexmask.long.word 0x08 16.--28. 1. " IFTCOUNT ,Initial frame transfer count"
hexmask.long.word 0x08 0.--12. 1. " IETCOUNT ,Initial element transfer count"
group.long (0x100+0x10)++0x0B
line.long 0x00 "CHCTRL,Channel Control Register"
bitfld.long 0x00 16.--21. " CHAIN ,Next channel to be triggered" "No channel,Ch0,Ch1,Ch2,Ch3,Ch4,Ch5,Ch6,Ch7,Ch8,Ch9,Ch10,Ch11,Ch12,Ch13,Ch14,Ch15,Ch16,Ch17,Ch18,Ch19,Ch20,Ch21,Ch22,Ch23,Ch24,Ch25,Ch26,Ch27,Ch28,Ch29,Ch30,Ch31,?..."
bitfld.long 0x00 14.--15. " RES ,Read element size" "8 bits,16 bits,32 bits,64 bits"
textline " "
bitfld.long 0x00 12.--13. " WES ,Write element size" "8 bits,16 bits,32 bits,64 bits"
bitfld.long 0x00 8. " TTYPE ,Transfer type" "Frame,Block"
textline " "
bitfld.long 0x00 3.--4. " ADDMR ,Addressing mode read" "Constant,Post-increment,,Indexed"
bitfld.long 0x00 1.--2. " ADDMW ,Addressing mode write" "Constant,Post-increment,,Indexed"
textline " "
bitfld.long 0x00 0. " AIM ,Autoinitiation mode" "Single block,Autoinitiation"
line.long 0x04 "EIOFF,Element Index Offset Register"
hexmask.long.word 0x04 16.--28. 1. " EIDXD ,Destination address element index"
hexmask.long.word 0x04 0.--12. 1. " EIDXS ,Source address element index"
line.long 0x08 "FIOFF,Frame Index Offset Register"
hexmask.long.word 0x08 16.--28. 1. " FIDXD ,Destination address frame index"
hexmask.long.word 0x08 0.--12. 1. " FIDXS ,Source address frame index"
tree.end
tree "Primary Control Packet 9"
group.long 0x120++0x0B
line.long 0x00 "ISADDR,Initial Source Address Register"
line.long 0x04 "IDADDR,Initial Destination Address Register"
line.long 0x08 "ITCOUNT,Initial Transfer Count Register"
hexmask.long.word 0x08 16.--28. 1. " IFTCOUNT ,Initial frame transfer count"
hexmask.long.word 0x08 0.--12. 1. " IETCOUNT ,Initial element transfer count"
group.long (0x120+0x10)++0x0B
line.long 0x00 "CHCTRL,Channel Control Register"
bitfld.long 0x00 16.--21. " CHAIN ,Next channel to be triggered" "No channel,Ch0,Ch1,Ch2,Ch3,Ch4,Ch5,Ch6,Ch7,Ch8,Ch9,Ch10,Ch11,Ch12,Ch13,Ch14,Ch15,Ch16,Ch17,Ch18,Ch19,Ch20,Ch21,Ch22,Ch23,Ch24,Ch25,Ch26,Ch27,Ch28,Ch29,Ch30,Ch31,?..."
bitfld.long 0x00 14.--15. " RES ,Read element size" "8 bits,16 bits,32 bits,64 bits"
textline " "
bitfld.long 0x00 12.--13. " WES ,Write element size" "8 bits,16 bits,32 bits,64 bits"
bitfld.long 0x00 8. " TTYPE ,Transfer type" "Frame,Block"
textline " "
bitfld.long 0x00 3.--4. " ADDMR ,Addressing mode read" "Constant,Post-increment,,Indexed"
bitfld.long 0x00 1.--2. " ADDMW ,Addressing mode write" "Constant,Post-increment,,Indexed"
textline " "
bitfld.long 0x00 0. " AIM ,Autoinitiation mode" "Single block,Autoinitiation"
line.long 0x04 "EIOFF,Element Index Offset Register"
hexmask.long.word 0x04 16.--28. 1. " EIDXD ,Destination address element index"
hexmask.long.word 0x04 0.--12. 1. " EIDXS ,Source address element index"
line.long 0x08 "FIOFF,Frame Index Offset Register"
hexmask.long.word 0x08 16.--28. 1. " FIDXD ,Destination address frame index"
hexmask.long.word 0x08 0.--12. 1. " FIDXS ,Source address frame index"
tree.end
tree "Primary Control Packet 10"
group.long 0x140++0x0B
line.long 0x00 "ISADDR,Initial Source Address Register"
line.long 0x04 "IDADDR,Initial Destination Address Register"
line.long 0x08 "ITCOUNT,Initial Transfer Count Register"
hexmask.long.word 0x08 16.--28. 1. " IFTCOUNT ,Initial frame transfer count"
hexmask.long.word 0x08 0.--12. 1. " IETCOUNT ,Initial element transfer count"
group.long (0x140+0x10)++0x0B
line.long 0x00 "CHCTRL,Channel Control Register"
bitfld.long 0x00 16.--21. " CHAIN ,Next channel to be triggered" "No channel,Ch0,Ch1,Ch2,Ch3,Ch4,Ch5,Ch6,Ch7,Ch8,Ch9,Ch10,Ch11,Ch12,Ch13,Ch14,Ch15,Ch16,Ch17,Ch18,Ch19,Ch20,Ch21,Ch22,Ch23,Ch24,Ch25,Ch26,Ch27,Ch28,Ch29,Ch30,Ch31,?..."
bitfld.long 0x00 14.--15. " RES ,Read element size" "8 bits,16 bits,32 bits,64 bits"
textline " "
bitfld.long 0x00 12.--13. " WES ,Write element size" "8 bits,16 bits,32 bits,64 bits"
bitfld.long 0x00 8. " TTYPE ,Transfer type" "Frame,Block"
textline " "
bitfld.long 0x00 3.--4. " ADDMR ,Addressing mode read" "Constant,Post-increment,,Indexed"
bitfld.long 0x00 1.--2. " ADDMW ,Addressing mode write" "Constant,Post-increment,,Indexed"
textline " "
bitfld.long 0x00 0. " AIM ,Autoinitiation mode" "Single block,Autoinitiation"
line.long 0x04 "EIOFF,Element Index Offset Register"
hexmask.long.word 0x04 16.--28. 1. " EIDXD ,Destination address element index"
hexmask.long.word 0x04 0.--12. 1. " EIDXS ,Source address element index"
line.long 0x08 "FIOFF,Frame Index Offset Register"
hexmask.long.word 0x08 16.--28. 1. " FIDXD ,Destination address frame index"
hexmask.long.word 0x08 0.--12. 1. " FIDXS ,Source address frame index"
tree.end
tree "Primary Control Packet 11"
group.long 0x160++0x0B
line.long 0x00 "ISADDR,Initial Source Address Register"
line.long 0x04 "IDADDR,Initial Destination Address Register"
line.long 0x08 "ITCOUNT,Initial Transfer Count Register"
hexmask.long.word 0x08 16.--28. 1. " IFTCOUNT ,Initial frame transfer count"
hexmask.long.word 0x08 0.--12. 1. " IETCOUNT ,Initial element transfer count"
group.long (0x160+0x10)++0x0B
line.long 0x00 "CHCTRL,Channel Control Register"
bitfld.long 0x00 16.--21. " CHAIN ,Next channel to be triggered" "No channel,Ch0,Ch1,Ch2,Ch3,Ch4,Ch5,Ch6,Ch7,Ch8,Ch9,Ch10,Ch11,Ch12,Ch13,Ch14,Ch15,Ch16,Ch17,Ch18,Ch19,Ch20,Ch21,Ch22,Ch23,Ch24,Ch25,Ch26,Ch27,Ch28,Ch29,Ch30,Ch31,?..."
bitfld.long 0x00 14.--15. " RES ,Read element size" "8 bits,16 bits,32 bits,64 bits"
textline " "
bitfld.long 0x00 12.--13. " WES ,Write element size" "8 bits,16 bits,32 bits,64 bits"
bitfld.long 0x00 8. " TTYPE ,Transfer type" "Frame,Block"
textline " "
bitfld.long 0x00 3.--4. " ADDMR ,Addressing mode read" "Constant,Post-increment,,Indexed"
bitfld.long 0x00 1.--2. " ADDMW ,Addressing mode write" "Constant,Post-increment,,Indexed"
textline " "
bitfld.long 0x00 0. " AIM ,Autoinitiation mode" "Single block,Autoinitiation"
line.long 0x04 "EIOFF,Element Index Offset Register"
hexmask.long.word 0x04 16.--28. 1. " EIDXD ,Destination address element index"
hexmask.long.word 0x04 0.--12. 1. " EIDXS ,Source address element index"
line.long 0x08 "FIOFF,Frame Index Offset Register"
hexmask.long.word 0x08 16.--28. 1. " FIDXD ,Destination address frame index"
hexmask.long.word 0x08 0.--12. 1. " FIDXS ,Source address frame index"
tree.end
tree "Primary Control Packet 12"
group.long 0x180++0x0B
line.long 0x00 "ISADDR,Initial Source Address Register"
line.long 0x04 "IDADDR,Initial Destination Address Register"
line.long 0x08 "ITCOUNT,Initial Transfer Count Register"
hexmask.long.word 0x08 16.--28. 1. " IFTCOUNT ,Initial frame transfer count"
hexmask.long.word 0x08 0.--12. 1. " IETCOUNT ,Initial element transfer count"
group.long (0x180+0x10)++0x0B
line.long 0x00 "CHCTRL,Channel Control Register"
bitfld.long 0x00 16.--21. " CHAIN ,Next channel to be triggered" "No channel,Ch0,Ch1,Ch2,Ch3,Ch4,Ch5,Ch6,Ch7,Ch8,Ch9,Ch10,Ch11,Ch12,Ch13,Ch14,Ch15,Ch16,Ch17,Ch18,Ch19,Ch20,Ch21,Ch22,Ch23,Ch24,Ch25,Ch26,Ch27,Ch28,Ch29,Ch30,Ch31,?..."
bitfld.long 0x00 14.--15. " RES ,Read element size" "8 bits,16 bits,32 bits,64 bits"
textline " "
bitfld.long 0x00 12.--13. " WES ,Write element size" "8 bits,16 bits,32 bits,64 bits"
bitfld.long 0x00 8. " TTYPE ,Transfer type" "Frame,Block"
textline " "
bitfld.long 0x00 3.--4. " ADDMR ,Addressing mode read" "Constant,Post-increment,,Indexed"
bitfld.long 0x00 1.--2. " ADDMW ,Addressing mode write" "Constant,Post-increment,,Indexed"
textline " "
bitfld.long 0x00 0. " AIM ,Autoinitiation mode" "Single block,Autoinitiation"
line.long 0x04 "EIOFF,Element Index Offset Register"
hexmask.long.word 0x04 16.--28. 1. " EIDXD ,Destination address element index"
hexmask.long.word 0x04 0.--12. 1. " EIDXS ,Source address element index"
line.long 0x08 "FIOFF,Frame Index Offset Register"
hexmask.long.word 0x08 16.--28. 1. " FIDXD ,Destination address frame index"
hexmask.long.word 0x08 0.--12. 1. " FIDXS ,Source address frame index"
tree.end
tree "Primary Control Packet 13"
group.long 0x1A0++0x0B
line.long 0x00 "ISADDR,Initial Source Address Register"
line.long 0x04 "IDADDR,Initial Destination Address Register"
line.long 0x08 "ITCOUNT,Initial Transfer Count Register"
hexmask.long.word 0x08 16.--28. 1. " IFTCOUNT ,Initial frame transfer count"
hexmask.long.word 0x08 0.--12. 1. " IETCOUNT ,Initial element transfer count"
group.long (0x1A0+0x10)++0x0B
line.long 0x00 "CHCTRL,Channel Control Register"
bitfld.long 0x00 16.--21. " CHAIN ,Next channel to be triggered" "No channel,Ch0,Ch1,Ch2,Ch3,Ch4,Ch5,Ch6,Ch7,Ch8,Ch9,Ch10,Ch11,Ch12,Ch13,Ch14,Ch15,Ch16,Ch17,Ch18,Ch19,Ch20,Ch21,Ch22,Ch23,Ch24,Ch25,Ch26,Ch27,Ch28,Ch29,Ch30,Ch31,?..."
bitfld.long 0x00 14.--15. " RES ,Read element size" "8 bits,16 bits,32 bits,64 bits"
textline " "
bitfld.long 0x00 12.--13. " WES ,Write element size" "8 bits,16 bits,32 bits,64 bits"
bitfld.long 0x00 8. " TTYPE ,Transfer type" "Frame,Block"
textline " "
bitfld.long 0x00 3.--4. " ADDMR ,Addressing mode read" "Constant,Post-increment,,Indexed"
bitfld.long 0x00 1.--2. " ADDMW ,Addressing mode write" "Constant,Post-increment,,Indexed"
textline " "
bitfld.long 0x00 0. " AIM ,Autoinitiation mode" "Single block,Autoinitiation"
line.long 0x04 "EIOFF,Element Index Offset Register"
hexmask.long.word 0x04 16.--28. 1. " EIDXD ,Destination address element index"
hexmask.long.word 0x04 0.--12. 1. " EIDXS ,Source address element index"
line.long 0x08 "FIOFF,Frame Index Offset Register"
hexmask.long.word 0x08 16.--28. 1. " FIDXD ,Destination address frame index"
hexmask.long.word 0x08 0.--12. 1. " FIDXS ,Source address frame index"
tree.end
tree "Primary Control Packet 14"
group.long 0x1C0++0x0B
line.long 0x00 "ISADDR,Initial Source Address Register"
line.long 0x04 "IDADDR,Initial Destination Address Register"
line.long 0x08 "ITCOUNT,Initial Transfer Count Register"
hexmask.long.word 0x08 16.--28. 1. " IFTCOUNT ,Initial frame transfer count"
hexmask.long.word 0x08 0.--12. 1. " IETCOUNT ,Initial element transfer count"
group.long (0x1C0+0x10)++0x0B
line.long 0x00 "CHCTRL,Channel Control Register"
bitfld.long 0x00 16.--21. " CHAIN ,Next channel to be triggered" "No channel,Ch0,Ch1,Ch2,Ch3,Ch4,Ch5,Ch6,Ch7,Ch8,Ch9,Ch10,Ch11,Ch12,Ch13,Ch14,Ch15,Ch16,Ch17,Ch18,Ch19,Ch20,Ch21,Ch22,Ch23,Ch24,Ch25,Ch26,Ch27,Ch28,Ch29,Ch30,Ch31,?..."
bitfld.long 0x00 14.--15. " RES ,Read element size" "8 bits,16 bits,32 bits,64 bits"
textline " "
bitfld.long 0x00 12.--13. " WES ,Write element size" "8 bits,16 bits,32 bits,64 bits"
bitfld.long 0x00 8. " TTYPE ,Transfer type" "Frame,Block"
textline " "
bitfld.long 0x00 3.--4. " ADDMR ,Addressing mode read" "Constant,Post-increment,,Indexed"
bitfld.long 0x00 1.--2. " ADDMW ,Addressing mode write" "Constant,Post-increment,,Indexed"
textline " "
bitfld.long 0x00 0. " AIM ,Autoinitiation mode" "Single block,Autoinitiation"
line.long 0x04 "EIOFF,Element Index Offset Register"
hexmask.long.word 0x04 16.--28. 1. " EIDXD ,Destination address element index"
hexmask.long.word 0x04 0.--12. 1. " EIDXS ,Source address element index"
line.long 0x08 "FIOFF,Frame Index Offset Register"
hexmask.long.word 0x08 16.--28. 1. " FIDXD ,Destination address frame index"
hexmask.long.word 0x08 0.--12. 1. " FIDXS ,Source address frame index"
tree.end
tree "Primary Control Packet 15"
group.long 0x1E0++0x0B
line.long 0x00 "ISADDR,Initial Source Address Register"
line.long 0x04 "IDADDR,Initial Destination Address Register"
line.long 0x08 "ITCOUNT,Initial Transfer Count Register"
hexmask.long.word 0x08 16.--28. 1. " IFTCOUNT ,Initial frame transfer count"
hexmask.long.word 0x08 0.--12. 1. " IETCOUNT ,Initial element transfer count"
group.long (0x1E0+0x10)++0x0B
line.long 0x00 "CHCTRL,Channel Control Register"
bitfld.long 0x00 16.--21. " CHAIN ,Next channel to be triggered" "No channel,Ch0,Ch1,Ch2,Ch3,Ch4,Ch5,Ch6,Ch7,Ch8,Ch9,Ch10,Ch11,Ch12,Ch13,Ch14,Ch15,Ch16,Ch17,Ch18,Ch19,Ch20,Ch21,Ch22,Ch23,Ch24,Ch25,Ch26,Ch27,Ch28,Ch29,Ch30,Ch31,?..."
bitfld.long 0x00 14.--15. " RES ,Read element size" "8 bits,16 bits,32 bits,64 bits"
textline " "
bitfld.long 0x00 12.--13. " WES ,Write element size" "8 bits,16 bits,32 bits,64 bits"
bitfld.long 0x00 8. " TTYPE ,Transfer type" "Frame,Block"
textline " "
bitfld.long 0x00 3.--4. " ADDMR ,Addressing mode read" "Constant,Post-increment,,Indexed"
bitfld.long 0x00 1.--2. " ADDMW ,Addressing mode write" "Constant,Post-increment,,Indexed"
textline " "
bitfld.long 0x00 0. " AIM ,Autoinitiation mode" "Single block,Autoinitiation"
line.long 0x04 "EIOFF,Element Index Offset Register"
hexmask.long.word 0x04 16.--28. 1. " EIDXD ,Destination address element index"
hexmask.long.word 0x04 0.--12. 1. " EIDXS ,Source address element index"
line.long 0x08 "FIOFF,Frame Index Offset Register"
hexmask.long.word 0x08 16.--28. 1. " FIDXD ,Destination address frame index"
hexmask.long.word 0x08 0.--12. 1. " FIDXS ,Source address frame index"
tree.end
tree "Primary Control Packet 16"
group.long 0x200++0x0B
line.long 0x00 "ISADDR,Initial Source Address Register"
line.long 0x04 "IDADDR,Initial Destination Address Register"
line.long 0x08 "ITCOUNT,Initial Transfer Count Register"
hexmask.long.word 0x08 16.--28. 1. " IFTCOUNT ,Initial frame transfer count"
hexmask.long.word 0x08 0.--12. 1. " IETCOUNT ,Initial element transfer count"
group.long (0x200+0x10)++0x0B
line.long 0x00 "CHCTRL,Channel Control Register"
bitfld.long 0x00 16.--21. " CHAIN ,Next channel to be triggered" "No channel,Ch0,Ch1,Ch2,Ch3,Ch4,Ch5,Ch6,Ch7,Ch8,Ch9,Ch10,Ch11,Ch12,Ch13,Ch14,Ch15,Ch16,Ch17,Ch18,Ch19,Ch20,Ch21,Ch22,Ch23,Ch24,Ch25,Ch26,Ch27,Ch28,Ch29,Ch30,Ch31,?..."
bitfld.long 0x00 14.--15. " RES ,Read element size" "8 bits,16 bits,32 bits,64 bits"
textline " "
bitfld.long 0x00 12.--13. " WES ,Write element size" "8 bits,16 bits,32 bits,64 bits"
bitfld.long 0x00 8. " TTYPE ,Transfer type" "Frame,Block"
textline " "
bitfld.long 0x00 3.--4. " ADDMR ,Addressing mode read" "Constant,Post-increment,,Indexed"
bitfld.long 0x00 1.--2. " ADDMW ,Addressing mode write" "Constant,Post-increment,,Indexed"
textline " "
bitfld.long 0x00 0. " AIM ,Autoinitiation mode" "Single block,Autoinitiation"
line.long 0x04 "EIOFF,Element Index Offset Register"
hexmask.long.word 0x04 16.--28. 1. " EIDXD ,Destination address element index"
hexmask.long.word 0x04 0.--12. 1. " EIDXS ,Source address element index"
line.long 0x08 "FIOFF,Frame Index Offset Register"
hexmask.long.word 0x08 16.--28. 1. " FIDXD ,Destination address frame index"
hexmask.long.word 0x08 0.--12. 1. " FIDXS ,Source address frame index"
tree.end
tree "Primary Control Packet 17"
group.long 0x220++0x0B
line.long 0x00 "ISADDR,Initial Source Address Register"
line.long 0x04 "IDADDR,Initial Destination Address Register"
line.long 0x08 "ITCOUNT,Initial Transfer Count Register"
hexmask.long.word 0x08 16.--28. 1. " IFTCOUNT ,Initial frame transfer count"
hexmask.long.word 0x08 0.--12. 1. " IETCOUNT ,Initial element transfer count"
group.long (0x220+0x10)++0x0B
line.long 0x00 "CHCTRL,Channel Control Register"
bitfld.long 0x00 16.--21. " CHAIN ,Next channel to be triggered" "No channel,Ch0,Ch1,Ch2,Ch3,Ch4,Ch5,Ch6,Ch7,Ch8,Ch9,Ch10,Ch11,Ch12,Ch13,Ch14,Ch15,Ch16,Ch17,Ch18,Ch19,Ch20,Ch21,Ch22,Ch23,Ch24,Ch25,Ch26,Ch27,Ch28,Ch29,Ch30,Ch31,?..."
bitfld.long 0x00 14.--15. " RES ,Read element size" "8 bits,16 bits,32 bits,64 bits"
textline " "
bitfld.long 0x00 12.--13. " WES ,Write element size" "8 bits,16 bits,32 bits,64 bits"
bitfld.long 0x00 8. " TTYPE ,Transfer type" "Frame,Block"
textline " "
bitfld.long 0x00 3.--4. " ADDMR ,Addressing mode read" "Constant,Post-increment,,Indexed"
bitfld.long 0x00 1.--2. " ADDMW ,Addressing mode write" "Constant,Post-increment,,Indexed"
textline " "
bitfld.long 0x00 0. " AIM ,Autoinitiation mode" "Single block,Autoinitiation"
line.long 0x04 "EIOFF,Element Index Offset Register"
hexmask.long.word 0x04 16.--28. 1. " EIDXD ,Destination address element index"
hexmask.long.word 0x04 0.--12. 1. " EIDXS ,Source address element index"
line.long 0x08 "FIOFF,Frame Index Offset Register"
hexmask.long.word 0x08 16.--28. 1. " FIDXD ,Destination address frame index"
hexmask.long.word 0x08 0.--12. 1. " FIDXS ,Source address frame index"
tree.end
tree "Primary Control Packet 18"
group.long 0x240++0x0B
line.long 0x00 "ISADDR,Initial Source Address Register"
line.long 0x04 "IDADDR,Initial Destination Address Register"
line.long 0x08 "ITCOUNT,Initial Transfer Count Register"
hexmask.long.word 0x08 16.--28. 1. " IFTCOUNT ,Initial frame transfer count"
hexmask.long.word 0x08 0.--12. 1. " IETCOUNT ,Initial element transfer count"
group.long (0x240+0x10)++0x0B
line.long 0x00 "CHCTRL,Channel Control Register"
bitfld.long 0x00 16.--21. " CHAIN ,Next channel to be triggered" "No channel,Ch0,Ch1,Ch2,Ch3,Ch4,Ch5,Ch6,Ch7,Ch8,Ch9,Ch10,Ch11,Ch12,Ch13,Ch14,Ch15,Ch16,Ch17,Ch18,Ch19,Ch20,Ch21,Ch22,Ch23,Ch24,Ch25,Ch26,Ch27,Ch28,Ch29,Ch30,Ch31,?..."
bitfld.long 0x00 14.--15. " RES ,Read element size" "8 bits,16 bits,32 bits,64 bits"
textline " "
bitfld.long 0x00 12.--13. " WES ,Write element size" "8 bits,16 bits,32 bits,64 bits"
bitfld.long 0x00 8. " TTYPE ,Transfer type" "Frame,Block"
textline " "
bitfld.long 0x00 3.--4. " ADDMR ,Addressing mode read" "Constant,Post-increment,,Indexed"
bitfld.long 0x00 1.--2. " ADDMW ,Addressing mode write" "Constant,Post-increment,,Indexed"
textline " "
bitfld.long 0x00 0. " AIM ,Autoinitiation mode" "Single block,Autoinitiation"
line.long 0x04 "EIOFF,Element Index Offset Register"
hexmask.long.word 0x04 16.--28. 1. " EIDXD ,Destination address element index"
hexmask.long.word 0x04 0.--12. 1. " EIDXS ,Source address element index"
line.long 0x08 "FIOFF,Frame Index Offset Register"
hexmask.long.word 0x08 16.--28. 1. " FIDXD ,Destination address frame index"
hexmask.long.word 0x08 0.--12. 1. " FIDXS ,Source address frame index"
tree.end
tree "Primary Control Packet 19"
group.long 0x260++0x0B
line.long 0x00 "ISADDR,Initial Source Address Register"
line.long 0x04 "IDADDR,Initial Destination Address Register"
line.long 0x08 "ITCOUNT,Initial Transfer Count Register"
hexmask.long.word 0x08 16.--28. 1. " IFTCOUNT ,Initial frame transfer count"
hexmask.long.word 0x08 0.--12. 1. " IETCOUNT ,Initial element transfer count"
group.long (0x260+0x10)++0x0B
line.long 0x00 "CHCTRL,Channel Control Register"
bitfld.long 0x00 16.--21. " CHAIN ,Next channel to be triggered" "No channel,Ch0,Ch1,Ch2,Ch3,Ch4,Ch5,Ch6,Ch7,Ch8,Ch9,Ch10,Ch11,Ch12,Ch13,Ch14,Ch15,Ch16,Ch17,Ch18,Ch19,Ch20,Ch21,Ch22,Ch23,Ch24,Ch25,Ch26,Ch27,Ch28,Ch29,Ch30,Ch31,?..."
bitfld.long 0x00 14.--15. " RES ,Read element size" "8 bits,16 bits,32 bits,64 bits"
textline " "
bitfld.long 0x00 12.--13. " WES ,Write element size" "8 bits,16 bits,32 bits,64 bits"
bitfld.long 0x00 8. " TTYPE ,Transfer type" "Frame,Block"
textline " "
bitfld.long 0x00 3.--4. " ADDMR ,Addressing mode read" "Constant,Post-increment,,Indexed"
bitfld.long 0x00 1.--2. " ADDMW ,Addressing mode write" "Constant,Post-increment,,Indexed"
textline " "
bitfld.long 0x00 0. " AIM ,Autoinitiation mode" "Single block,Autoinitiation"
line.long 0x04 "EIOFF,Element Index Offset Register"
hexmask.long.word 0x04 16.--28. 1. " EIDXD ,Destination address element index"
hexmask.long.word 0x04 0.--12. 1. " EIDXS ,Source address element index"
line.long 0x08 "FIOFF,Frame Index Offset Register"
hexmask.long.word 0x08 16.--28. 1. " FIDXD ,Destination address frame index"
hexmask.long.word 0x08 0.--12. 1. " FIDXS ,Source address frame index"
tree.end
tree "Primary Control Packet 20"
group.long 0x280++0x0B
line.long 0x00 "ISADDR,Initial Source Address Register"
line.long 0x04 "IDADDR,Initial Destination Address Register"
line.long 0x08 "ITCOUNT,Initial Transfer Count Register"
hexmask.long.word 0x08 16.--28. 1. " IFTCOUNT ,Initial frame transfer count"
hexmask.long.word 0x08 0.--12. 1. " IETCOUNT ,Initial element transfer count"
group.long (0x280+0x10)++0x0B
line.long 0x00 "CHCTRL,Channel Control Register"
bitfld.long 0x00 16.--21. " CHAIN ,Next channel to be triggered" "No channel,Ch0,Ch1,Ch2,Ch3,Ch4,Ch5,Ch6,Ch7,Ch8,Ch9,Ch10,Ch11,Ch12,Ch13,Ch14,Ch15,Ch16,Ch17,Ch18,Ch19,Ch20,Ch21,Ch22,Ch23,Ch24,Ch25,Ch26,Ch27,Ch28,Ch29,Ch30,Ch31,?..."
bitfld.long 0x00 14.--15. " RES ,Read element size" "8 bits,16 bits,32 bits,64 bits"
textline " "
bitfld.long 0x00 12.--13. " WES ,Write element size" "8 bits,16 bits,32 bits,64 bits"
bitfld.long 0x00 8. " TTYPE ,Transfer type" "Frame,Block"
textline " "
bitfld.long 0x00 3.--4. " ADDMR ,Addressing mode read" "Constant,Post-increment,,Indexed"
bitfld.long 0x00 1.--2. " ADDMW ,Addressing mode write" "Constant,Post-increment,,Indexed"
textline " "
bitfld.long 0x00 0. " AIM ,Autoinitiation mode" "Single block,Autoinitiation"
line.long 0x04 "EIOFF,Element Index Offset Register"
hexmask.long.word 0x04 16.--28. 1. " EIDXD ,Destination address element index"
hexmask.long.word 0x04 0.--12. 1. " EIDXS ,Source address element index"
line.long 0x08 "FIOFF,Frame Index Offset Register"
hexmask.long.word 0x08 16.--28. 1. " FIDXD ,Destination address frame index"
hexmask.long.word 0x08 0.--12. 1. " FIDXS ,Source address frame index"
tree.end
tree "Primary Control Packet 21"
group.long 0x2A0++0x0B
line.long 0x00 "ISADDR,Initial Source Address Register"
line.long 0x04 "IDADDR,Initial Destination Address Register"
line.long 0x08 "ITCOUNT,Initial Transfer Count Register"
hexmask.long.word 0x08 16.--28. 1. " IFTCOUNT ,Initial frame transfer count"
hexmask.long.word 0x08 0.--12. 1. " IETCOUNT ,Initial element transfer count"
group.long (0x2A0+0x10)++0x0B
line.long 0x00 "CHCTRL,Channel Control Register"
bitfld.long 0x00 16.--21. " CHAIN ,Next channel to be triggered" "No channel,Ch0,Ch1,Ch2,Ch3,Ch4,Ch5,Ch6,Ch7,Ch8,Ch9,Ch10,Ch11,Ch12,Ch13,Ch14,Ch15,Ch16,Ch17,Ch18,Ch19,Ch20,Ch21,Ch22,Ch23,Ch24,Ch25,Ch26,Ch27,Ch28,Ch29,Ch30,Ch31,?..."
bitfld.long 0x00 14.--15. " RES ,Read element size" "8 bits,16 bits,32 bits,64 bits"
textline " "
bitfld.long 0x00 12.--13. " WES ,Write element size" "8 bits,16 bits,32 bits,64 bits"
bitfld.long 0x00 8. " TTYPE ,Transfer type" "Frame,Block"
textline " "
bitfld.long 0x00 3.--4. " ADDMR ,Addressing mode read" "Constant,Post-increment,,Indexed"
bitfld.long 0x00 1.--2. " ADDMW ,Addressing mode write" "Constant,Post-increment,,Indexed"
textline " "
bitfld.long 0x00 0. " AIM ,Autoinitiation mode" "Single block,Autoinitiation"
line.long 0x04 "EIOFF,Element Index Offset Register"
hexmask.long.word 0x04 16.--28. 1. " EIDXD ,Destination address element index"
hexmask.long.word 0x04 0.--12. 1. " EIDXS ,Source address element index"
line.long 0x08 "FIOFF,Frame Index Offset Register"
hexmask.long.word 0x08 16.--28. 1. " FIDXD ,Destination address frame index"
hexmask.long.word 0x08 0.--12. 1. " FIDXS ,Source address frame index"
tree.end
tree "Primary Control Packet 22"
group.long 0x2C0++0x0B
line.long 0x00 "ISADDR,Initial Source Address Register"
line.long 0x04 "IDADDR,Initial Destination Address Register"
line.long 0x08 "ITCOUNT,Initial Transfer Count Register"
hexmask.long.word 0x08 16.--28. 1. " IFTCOUNT ,Initial frame transfer count"
hexmask.long.word 0x08 0.--12. 1. " IETCOUNT ,Initial element transfer count"
group.long (0x2C0+0x10)++0x0B
line.long 0x00 "CHCTRL,Channel Control Register"
bitfld.long 0x00 16.--21. " CHAIN ,Next channel to be triggered" "No channel,Ch0,Ch1,Ch2,Ch3,Ch4,Ch5,Ch6,Ch7,Ch8,Ch9,Ch10,Ch11,Ch12,Ch13,Ch14,Ch15,Ch16,Ch17,Ch18,Ch19,Ch20,Ch21,Ch22,Ch23,Ch24,Ch25,Ch26,Ch27,Ch28,Ch29,Ch30,Ch31,?..."
bitfld.long 0x00 14.--15. " RES ,Read element size" "8 bits,16 bits,32 bits,64 bits"
textline " "
bitfld.long 0x00 12.--13. " WES ,Write element size" "8 bits,16 bits,32 bits,64 bits"
bitfld.long 0x00 8. " TTYPE ,Transfer type" "Frame,Block"
textline " "
bitfld.long 0x00 3.--4. " ADDMR ,Addressing mode read" "Constant,Post-increment,,Indexed"
bitfld.long 0x00 1.--2. " ADDMW ,Addressing mode write" "Constant,Post-increment,,Indexed"
textline " "
bitfld.long 0x00 0. " AIM ,Autoinitiation mode" "Single block,Autoinitiation"
line.long 0x04 "EIOFF,Element Index Offset Register"
hexmask.long.word 0x04 16.--28. 1. " EIDXD ,Destination address element index"
hexmask.long.word 0x04 0.--12. 1. " EIDXS ,Source address element index"
line.long 0x08 "FIOFF,Frame Index Offset Register"
hexmask.long.word 0x08 16.--28. 1. " FIDXD ,Destination address frame index"
hexmask.long.word 0x08 0.--12. 1. " FIDXS ,Source address frame index"
tree.end
tree "Primary Control Packet 23"
group.long 0x2E0++0x0B
line.long 0x00 "ISADDR,Initial Source Address Register"
line.long 0x04 "IDADDR,Initial Destination Address Register"
line.long 0x08 "ITCOUNT,Initial Transfer Count Register"
hexmask.long.word 0x08 16.--28. 1. " IFTCOUNT ,Initial frame transfer count"
hexmask.long.word 0x08 0.--12. 1. " IETCOUNT ,Initial element transfer count"
group.long (0x2E0+0x10)++0x0B
line.long 0x00 "CHCTRL,Channel Control Register"
bitfld.long 0x00 16.--21. " CHAIN ,Next channel to be triggered" "No channel,Ch0,Ch1,Ch2,Ch3,Ch4,Ch5,Ch6,Ch7,Ch8,Ch9,Ch10,Ch11,Ch12,Ch13,Ch14,Ch15,Ch16,Ch17,Ch18,Ch19,Ch20,Ch21,Ch22,Ch23,Ch24,Ch25,Ch26,Ch27,Ch28,Ch29,Ch30,Ch31,?..."
bitfld.long 0x00 14.--15. " RES ,Read element size" "8 bits,16 bits,32 bits,64 bits"
textline " "
bitfld.long 0x00 12.--13. " WES ,Write element size" "8 bits,16 bits,32 bits,64 bits"
bitfld.long 0x00 8. " TTYPE ,Transfer type" "Frame,Block"
textline " "
bitfld.long 0x00 3.--4. " ADDMR ,Addressing mode read" "Constant,Post-increment,,Indexed"
bitfld.long 0x00 1.--2. " ADDMW ,Addressing mode write" "Constant,Post-increment,,Indexed"
textline " "
bitfld.long 0x00 0. " AIM ,Autoinitiation mode" "Single block,Autoinitiation"
line.long 0x04 "EIOFF,Element Index Offset Register"
hexmask.long.word 0x04 16.--28. 1. " EIDXD ,Destination address element index"
hexmask.long.word 0x04 0.--12. 1. " EIDXS ,Source address element index"
line.long 0x08 "FIOFF,Frame Index Offset Register"
hexmask.long.word 0x08 16.--28. 1. " FIDXD ,Destination address frame index"
hexmask.long.word 0x08 0.--12. 1. " FIDXS ,Source address frame index"
tree.end
tree "Primary Control Packet 24"
group.long 0x300++0x0B
line.long 0x00 "ISADDR,Initial Source Address Register"
line.long 0x04 "IDADDR,Initial Destination Address Register"
line.long 0x08 "ITCOUNT,Initial Transfer Count Register"
hexmask.long.word 0x08 16.--28. 1. " IFTCOUNT ,Initial frame transfer count"
hexmask.long.word 0x08 0.--12. 1. " IETCOUNT ,Initial element transfer count"
group.long (0x300+0x10)++0x0B
line.long 0x00 "CHCTRL,Channel Control Register"
bitfld.long 0x00 16.--21. " CHAIN ,Next channel to be triggered" "No channel,Ch0,Ch1,Ch2,Ch3,Ch4,Ch5,Ch6,Ch7,Ch8,Ch9,Ch10,Ch11,Ch12,Ch13,Ch14,Ch15,Ch16,Ch17,Ch18,Ch19,Ch20,Ch21,Ch22,Ch23,Ch24,Ch25,Ch26,Ch27,Ch28,Ch29,Ch30,Ch31,?..."
bitfld.long 0x00 14.--15. " RES ,Read element size" "8 bits,16 bits,32 bits,64 bits"
textline " "
bitfld.long 0x00 12.--13. " WES ,Write element size" "8 bits,16 bits,32 bits,64 bits"
bitfld.long 0x00 8. " TTYPE ,Transfer type" "Frame,Block"
textline " "
bitfld.long 0x00 3.--4. " ADDMR ,Addressing mode read" "Constant,Post-increment,,Indexed"
bitfld.long 0x00 1.--2. " ADDMW ,Addressing mode write" "Constant,Post-increment,,Indexed"
textline " "
bitfld.long 0x00 0. " AIM ,Autoinitiation mode" "Single block,Autoinitiation"
line.long 0x04 "EIOFF,Element Index Offset Register"
hexmask.long.word 0x04 16.--28. 1. " EIDXD ,Destination address element index"
hexmask.long.word 0x04 0.--12. 1. " EIDXS ,Source address element index"
line.long 0x08 "FIOFF,Frame Index Offset Register"
hexmask.long.word 0x08 16.--28. 1. " FIDXD ,Destination address frame index"
hexmask.long.word 0x08 0.--12. 1. " FIDXS ,Source address frame index"
tree.end
tree "Primary Control Packet 25"
group.long 0x320++0x0B
line.long 0x00 "ISADDR,Initial Source Address Register"
line.long 0x04 "IDADDR,Initial Destination Address Register"
line.long 0x08 "ITCOUNT,Initial Transfer Count Register"
hexmask.long.word 0x08 16.--28. 1. " IFTCOUNT ,Initial frame transfer count"
hexmask.long.word 0x08 0.--12. 1. " IETCOUNT ,Initial element transfer count"
group.long (0x320+0x10)++0x0B
line.long 0x00 "CHCTRL,Channel Control Register"
bitfld.long 0x00 16.--21. " CHAIN ,Next channel to be triggered" "No channel,Ch0,Ch1,Ch2,Ch3,Ch4,Ch5,Ch6,Ch7,Ch8,Ch9,Ch10,Ch11,Ch12,Ch13,Ch14,Ch15,Ch16,Ch17,Ch18,Ch19,Ch20,Ch21,Ch22,Ch23,Ch24,Ch25,Ch26,Ch27,Ch28,Ch29,Ch30,Ch31,?..."
bitfld.long 0x00 14.--15. " RES ,Read element size" "8 bits,16 bits,32 bits,64 bits"
textline " "
bitfld.long 0x00 12.--13. " WES ,Write element size" "8 bits,16 bits,32 bits,64 bits"
bitfld.long 0x00 8. " TTYPE ,Transfer type" "Frame,Block"
textline " "
bitfld.long 0x00 3.--4. " ADDMR ,Addressing mode read" "Constant,Post-increment,,Indexed"
bitfld.long 0x00 1.--2. " ADDMW ,Addressing mode write" "Constant,Post-increment,,Indexed"
textline " "
bitfld.long 0x00 0. " AIM ,Autoinitiation mode" "Single block,Autoinitiation"
line.long 0x04 "EIOFF,Element Index Offset Register"
hexmask.long.word 0x04 16.--28. 1. " EIDXD ,Destination address element index"
hexmask.long.word 0x04 0.--12. 1. " EIDXS ,Source address element index"
line.long 0x08 "FIOFF,Frame Index Offset Register"
hexmask.long.word 0x08 16.--28. 1. " FIDXD ,Destination address frame index"
hexmask.long.word 0x08 0.--12. 1. " FIDXS ,Source address frame index"
tree.end
tree "Primary Control Packet 26"
group.long 0x340++0x0B
line.long 0x00 "ISADDR,Initial Source Address Register"
line.long 0x04 "IDADDR,Initial Destination Address Register"
line.long 0x08 "ITCOUNT,Initial Transfer Count Register"
hexmask.long.word 0x08 16.--28. 1. " IFTCOUNT ,Initial frame transfer count"
hexmask.long.word 0x08 0.--12. 1. " IETCOUNT ,Initial element transfer count"
group.long (0x340+0x10)++0x0B
line.long 0x00 "CHCTRL,Channel Control Register"
bitfld.long 0x00 16.--21. " CHAIN ,Next channel to be triggered" "No channel,Ch0,Ch1,Ch2,Ch3,Ch4,Ch5,Ch6,Ch7,Ch8,Ch9,Ch10,Ch11,Ch12,Ch13,Ch14,Ch15,Ch16,Ch17,Ch18,Ch19,Ch20,Ch21,Ch22,Ch23,Ch24,Ch25,Ch26,Ch27,Ch28,Ch29,Ch30,Ch31,?..."
bitfld.long 0x00 14.--15. " RES ,Read element size" "8 bits,16 bits,32 bits,64 bits"
textline " "
bitfld.long 0x00 12.--13. " WES ,Write element size" "8 bits,16 bits,32 bits,64 bits"
bitfld.long 0x00 8. " TTYPE ,Transfer type" "Frame,Block"
textline " "
bitfld.long 0x00 3.--4. " ADDMR ,Addressing mode read" "Constant,Post-increment,,Indexed"
bitfld.long 0x00 1.--2. " ADDMW ,Addressing mode write" "Constant,Post-increment,,Indexed"
textline " "
bitfld.long 0x00 0. " AIM ,Autoinitiation mode" "Single block,Autoinitiation"
line.long 0x04 "EIOFF,Element Index Offset Register"
hexmask.long.word 0x04 16.--28. 1. " EIDXD ,Destination address element index"
hexmask.long.word 0x04 0.--12. 1. " EIDXS ,Source address element index"
line.long 0x08 "FIOFF,Frame Index Offset Register"
hexmask.long.word 0x08 16.--28. 1. " FIDXD ,Destination address frame index"
hexmask.long.word 0x08 0.--12. 1. " FIDXS ,Source address frame index"
tree.end
tree "Primary Control Packet 27"
group.long 0x360++0x0B
line.long 0x00 "ISADDR,Initial Source Address Register"
line.long 0x04 "IDADDR,Initial Destination Address Register"
line.long 0x08 "ITCOUNT,Initial Transfer Count Register"
hexmask.long.word 0x08 16.--28. 1. " IFTCOUNT ,Initial frame transfer count"
hexmask.long.word 0x08 0.--12. 1. " IETCOUNT ,Initial element transfer count"
group.long (0x360+0x10)++0x0B
line.long 0x00 "CHCTRL,Channel Control Register"
bitfld.long 0x00 16.--21. " CHAIN ,Next channel to be triggered" "No channel,Ch0,Ch1,Ch2,Ch3,Ch4,Ch5,Ch6,Ch7,Ch8,Ch9,Ch10,Ch11,Ch12,Ch13,Ch14,Ch15,Ch16,Ch17,Ch18,Ch19,Ch20,Ch21,Ch22,Ch23,Ch24,Ch25,Ch26,Ch27,Ch28,Ch29,Ch30,Ch31,?..."
bitfld.long 0x00 14.--15. " RES ,Read element size" "8 bits,16 bits,32 bits,64 bits"
textline " "
bitfld.long 0x00 12.--13. " WES ,Write element size" "8 bits,16 bits,32 bits,64 bits"
bitfld.long 0x00 8. " TTYPE ,Transfer type" "Frame,Block"
textline " "
bitfld.long 0x00 3.--4. " ADDMR ,Addressing mode read" "Constant,Post-increment,,Indexed"
bitfld.long 0x00 1.--2. " ADDMW ,Addressing mode write" "Constant,Post-increment,,Indexed"
textline " "
bitfld.long 0x00 0. " AIM ,Autoinitiation mode" "Single block,Autoinitiation"
line.long 0x04 "EIOFF,Element Index Offset Register"
hexmask.long.word 0x04 16.--28. 1. " EIDXD ,Destination address element index"
hexmask.long.word 0x04 0.--12. 1. " EIDXS ,Source address element index"
line.long 0x08 "FIOFF,Frame Index Offset Register"
hexmask.long.word 0x08 16.--28. 1. " FIDXD ,Destination address frame index"
hexmask.long.word 0x08 0.--12. 1. " FIDXS ,Source address frame index"
tree.end
tree "Primary Control Packet 28"
group.long 0x380++0x0B
line.long 0x00 "ISADDR,Initial Source Address Register"
line.long 0x04 "IDADDR,Initial Destination Address Register"
line.long 0x08 "ITCOUNT,Initial Transfer Count Register"
hexmask.long.word 0x08 16.--28. 1. " IFTCOUNT ,Initial frame transfer count"
hexmask.long.word 0x08 0.--12. 1. " IETCOUNT ,Initial element transfer count"
group.long (0x380+0x10)++0x0B
line.long 0x00 "CHCTRL,Channel Control Register"
bitfld.long 0x00 16.--21. " CHAIN ,Next channel to be triggered" "No channel,Ch0,Ch1,Ch2,Ch3,Ch4,Ch5,Ch6,Ch7,Ch8,Ch9,Ch10,Ch11,Ch12,Ch13,Ch14,Ch15,Ch16,Ch17,Ch18,Ch19,Ch20,Ch21,Ch22,Ch23,Ch24,Ch25,Ch26,Ch27,Ch28,Ch29,Ch30,Ch31,?..."
bitfld.long 0x00 14.--15. " RES ,Read element size" "8 bits,16 bits,32 bits,64 bits"
textline " "
bitfld.long 0x00 12.--13. " WES ,Write element size" "8 bits,16 bits,32 bits,64 bits"
bitfld.long 0x00 8. " TTYPE ,Transfer type" "Frame,Block"
textline " "
bitfld.long 0x00 3.--4. " ADDMR ,Addressing mode read" "Constant,Post-increment,,Indexed"
bitfld.long 0x00 1.--2. " ADDMW ,Addressing mode write" "Constant,Post-increment,,Indexed"
textline " "
bitfld.long 0x00 0. " AIM ,Autoinitiation mode" "Single block,Autoinitiation"
line.long 0x04 "EIOFF,Element Index Offset Register"
hexmask.long.word 0x04 16.--28. 1. " EIDXD ,Destination address element index"
hexmask.long.word 0x04 0.--12. 1. " EIDXS ,Source address element index"
line.long 0x08 "FIOFF,Frame Index Offset Register"
hexmask.long.word 0x08 16.--28. 1. " FIDXD ,Destination address frame index"
hexmask.long.word 0x08 0.--12. 1. " FIDXS ,Source address frame index"
tree.end
tree "Primary Control Packet 29"
group.long 0x3A0++0x0B
line.long 0x00 "ISADDR,Initial Source Address Register"
line.long 0x04 "IDADDR,Initial Destination Address Register"
line.long 0x08 "ITCOUNT,Initial Transfer Count Register"
hexmask.long.word 0x08 16.--28. 1. " IFTCOUNT ,Initial frame transfer count"
hexmask.long.word 0x08 0.--12. 1. " IETCOUNT ,Initial element transfer count"
group.long (0x3A0+0x10)++0x0B
line.long 0x00 "CHCTRL,Channel Control Register"
bitfld.long 0x00 16.--21. " CHAIN ,Next channel to be triggered" "No channel,Ch0,Ch1,Ch2,Ch3,Ch4,Ch5,Ch6,Ch7,Ch8,Ch9,Ch10,Ch11,Ch12,Ch13,Ch14,Ch15,Ch16,Ch17,Ch18,Ch19,Ch20,Ch21,Ch22,Ch23,Ch24,Ch25,Ch26,Ch27,Ch28,Ch29,Ch30,Ch31,?..."
bitfld.long 0x00 14.--15. " RES ,Read element size" "8 bits,16 bits,32 bits,64 bits"
textline " "
bitfld.long 0x00 12.--13. " WES ,Write element size" "8 bits,16 bits,32 bits,64 bits"
bitfld.long 0x00 8. " TTYPE ,Transfer type" "Frame,Block"
textline " "
bitfld.long 0x00 3.--4. " ADDMR ,Addressing mode read" "Constant,Post-increment,,Indexed"
bitfld.long 0x00 1.--2. " ADDMW ,Addressing mode write" "Constant,Post-increment,,Indexed"
textline " "
bitfld.long 0x00 0. " AIM ,Autoinitiation mode" "Single block,Autoinitiation"
line.long 0x04 "EIOFF,Element Index Offset Register"
hexmask.long.word 0x04 16.--28. 1. " EIDXD ,Destination address element index"
hexmask.long.word 0x04 0.--12. 1. " EIDXS ,Source address element index"
line.long 0x08 "FIOFF,Frame Index Offset Register"
hexmask.long.word 0x08 16.--28. 1. " FIDXD ,Destination address frame index"
hexmask.long.word 0x08 0.--12. 1. " FIDXS ,Source address frame index"
tree.end
tree "Primary Control Packet 30"
group.long 0x3C0++0x0B
line.long 0x00 "ISADDR,Initial Source Address Register"
line.long 0x04 "IDADDR,Initial Destination Address Register"
line.long 0x08 "ITCOUNT,Initial Transfer Count Register"
hexmask.long.word 0x08 16.--28. 1. " IFTCOUNT ,Initial frame transfer count"
hexmask.long.word 0x08 0.--12. 1. " IETCOUNT ,Initial element transfer count"
group.long (0x3C0+0x10)++0x0B
line.long 0x00 "CHCTRL,Channel Control Register"
bitfld.long 0x00 16.--21. " CHAIN ,Next channel to be triggered" "No channel,Ch0,Ch1,Ch2,Ch3,Ch4,Ch5,Ch6,Ch7,Ch8,Ch9,Ch10,Ch11,Ch12,Ch13,Ch14,Ch15,Ch16,Ch17,Ch18,Ch19,Ch20,Ch21,Ch22,Ch23,Ch24,Ch25,Ch26,Ch27,Ch28,Ch29,Ch30,Ch31,?..."
bitfld.long 0x00 14.--15. " RES ,Read element size" "8 bits,16 bits,32 bits,64 bits"
textline " "
bitfld.long 0x00 12.--13. " WES ,Write element size" "8 bits,16 bits,32 bits,64 bits"
bitfld.long 0x00 8. " TTYPE ,Transfer type" "Frame,Block"
textline " "
bitfld.long 0x00 3.--4. " ADDMR ,Addressing mode read" "Constant,Post-increment,,Indexed"
bitfld.long 0x00 1.--2. " ADDMW ,Addressing mode write" "Constant,Post-increment,,Indexed"
textline " "
bitfld.long 0x00 0. " AIM ,Autoinitiation mode" "Single block,Autoinitiation"
line.long 0x04 "EIOFF,Element Index Offset Register"
hexmask.long.word 0x04 16.--28. 1. " EIDXD ,Destination address element index"
hexmask.long.word 0x04 0.--12. 1. " EIDXS ,Source address element index"
line.long 0x08 "FIOFF,Frame Index Offset Register"
hexmask.long.word 0x08 16.--28. 1. " FIDXD ,Destination address frame index"
hexmask.long.word 0x08 0.--12. 1. " FIDXS ,Source address frame index"
tree.end
tree "Primary Control Packet 31"
group.long 0x3E0++0x0B
line.long 0x00 "ISADDR,Initial Source Address Register"
line.long 0x04 "IDADDR,Initial Destination Address Register"
line.long 0x08 "ITCOUNT,Initial Transfer Count Register"
hexmask.long.word 0x08 16.--28. 1. " IFTCOUNT ,Initial frame transfer count"
hexmask.long.word 0x08 0.--12. 1. " IETCOUNT ,Initial element transfer count"
group.long (0x3E0+0x10)++0x0B
line.long 0x00 "CHCTRL,Channel Control Register"
bitfld.long 0x00 16.--21. " CHAIN ,Next channel to be triggered" "No channel,Ch0,Ch1,Ch2,Ch3,Ch4,Ch5,Ch6,Ch7,Ch8,Ch9,Ch10,Ch11,Ch12,Ch13,Ch14,Ch15,Ch16,Ch17,Ch18,Ch19,Ch20,Ch21,Ch22,Ch23,Ch24,Ch25,Ch26,Ch27,Ch28,Ch29,Ch30,Ch31,?..."
bitfld.long 0x00 14.--15. " RES ,Read element size" "8 bits,16 bits,32 bits,64 bits"
textline " "
bitfld.long 0x00 12.--13. " WES ,Write element size" "8 bits,16 bits,32 bits,64 bits"
bitfld.long 0x00 8. " TTYPE ,Transfer type" "Frame,Block"
textline " "
bitfld.long 0x00 3.--4. " ADDMR ,Addressing mode read" "Constant,Post-increment,,Indexed"
bitfld.long 0x00 1.--2. " ADDMW ,Addressing mode write" "Constant,Post-increment,,Indexed"
textline " "
bitfld.long 0x00 0. " AIM ,Autoinitiation mode" "Single block,Autoinitiation"
line.long 0x04 "EIOFF,Element Index Offset Register"
hexmask.long.word 0x04 16.--28. 1. " EIDXD ,Destination address element index"
hexmask.long.word 0x04 0.--12. 1. " EIDXS ,Source address element index"
line.long 0x08 "FIOFF,Frame Index Offset Register"
hexmask.long.word 0x08 16.--28. 1. " FIDXD ,Destination address frame index"
hexmask.long.word 0x08 0.--12. 1. " FIDXS ,Source address frame index"
tree.end
tree.end
width 9.
tree "Working Control Packet Registers"
tree "Working Control Packet 0x800"
group.long 0x800++0x07
line.long 0x00 "CSADDR,Current Source Address Register"
line.long 0x04 "CDADDR,Current Destination Address Register"
rgroup.long (0x800+0x08)++0x03
line.long 0x00 "CTCOUNT,Current Transfer Count Register"
hexmask.long.word 0x00 16.--28. 1. " CFTCOUNT ,Current frame transfer count"
hexmask.long.word 0x00 0.--12. 1. " CETCOUNT ,Current element transfer count"
tree.end
tree "Working Control Packet 0x810"
group.long 0x810++0x07
line.long 0x00 "CSADDR,Current Source Address Register"
line.long 0x04 "CDADDR,Current Destination Address Register"
rgroup.long (0x810+0x08)++0x03
line.long 0x00 "CTCOUNT,Current Transfer Count Register"
hexmask.long.word 0x00 16.--28. 1. " CFTCOUNT ,Current frame transfer count"
hexmask.long.word 0x00 0.--12. 1. " CETCOUNT ,Current element transfer count"
tree.end
tree "Working Control Packet 0x820"
group.long 0x820++0x07
line.long 0x00 "CSADDR,Current Source Address Register"
line.long 0x04 "CDADDR,Current Destination Address Register"
rgroup.long (0x820+0x08)++0x03
line.long 0x00 "CTCOUNT,Current Transfer Count Register"
hexmask.long.word 0x00 16.--28. 1. " CFTCOUNT ,Current frame transfer count"
hexmask.long.word 0x00 0.--12. 1. " CETCOUNT ,Current element transfer count"
tree.end
tree "Working Control Packet 0x830"
group.long 0x830++0x07
line.long 0x00 "CSADDR,Current Source Address Register"
line.long 0x04 "CDADDR,Current Destination Address Register"
rgroup.long (0x830+0x08)++0x03
line.long 0x00 "CTCOUNT,Current Transfer Count Register"
hexmask.long.word 0x00 16.--28. 1. " CFTCOUNT ,Current frame transfer count"
hexmask.long.word 0x00 0.--12. 1. " CETCOUNT ,Current element transfer count"
tree.end
tree "Working Control Packet 0x840"
group.long 0x840++0x07
line.long 0x00 "CSADDR,Current Source Address Register"
line.long 0x04 "CDADDR,Current Destination Address Register"
rgroup.long (0x840+0x08)++0x03
line.long 0x00 "CTCOUNT,Current Transfer Count Register"
hexmask.long.word 0x00 16.--28. 1. " CFTCOUNT ,Current frame transfer count"
hexmask.long.word 0x00 0.--12. 1. " CETCOUNT ,Current element transfer count"
tree.end
tree "Working Control Packet 0x850"
group.long 0x850++0x07
line.long 0x00 "CSADDR,Current Source Address Register"
line.long 0x04 "CDADDR,Current Destination Address Register"
rgroup.long (0x850+0x08)++0x03
line.long 0x00 "CTCOUNT,Current Transfer Count Register"
hexmask.long.word 0x00 16.--28. 1. " CFTCOUNT ,Current frame transfer count"
hexmask.long.word 0x00 0.--12. 1. " CETCOUNT ,Current element transfer count"
tree.end
tree "Working Control Packet 0x860"
group.long 0x860++0x07
line.long 0x00 "CSADDR,Current Source Address Register"
line.long 0x04 "CDADDR,Current Destination Address Register"
rgroup.long (0x860+0x08)++0x03
line.long 0x00 "CTCOUNT,Current Transfer Count Register"
hexmask.long.word 0x00 16.--28. 1. " CFTCOUNT ,Current frame transfer count"
hexmask.long.word 0x00 0.--12. 1. " CETCOUNT ,Current element transfer count"
tree.end
tree "Working Control Packet 0x870"
group.long 0x870++0x07
line.long 0x00 "CSADDR,Current Source Address Register"
line.long 0x04 "CDADDR,Current Destination Address Register"
rgroup.long (0x870+0x08)++0x03
line.long 0x00 "CTCOUNT,Current Transfer Count Register"
hexmask.long.word 0x00 16.--28. 1. " CFTCOUNT ,Current frame transfer count"
hexmask.long.word 0x00 0.--12. 1. " CETCOUNT ,Current element transfer count"
tree.end
tree "Working Control Packet 0x880"
group.long 0x880++0x07
line.long 0x00 "CSADDR,Current Source Address Register"
line.long 0x04 "CDADDR,Current Destination Address Register"
rgroup.long (0x880+0x08)++0x03
line.long 0x00 "CTCOUNT,Current Transfer Count Register"
hexmask.long.word 0x00 16.--28. 1. " CFTCOUNT ,Current frame transfer count"
hexmask.long.word 0x00 0.--12. 1. " CETCOUNT ,Current element transfer count"
tree.end
tree "Working Control Packet 0x890"
group.long 0x890++0x07
line.long 0x00 "CSADDR,Current Source Address Register"
line.long 0x04 "CDADDR,Current Destination Address Register"
rgroup.long (0x890+0x08)++0x03
line.long 0x00 "CTCOUNT,Current Transfer Count Register"
hexmask.long.word 0x00 16.--28. 1. " CFTCOUNT ,Current frame transfer count"
hexmask.long.word 0x00 0.--12. 1. " CETCOUNT ,Current element transfer count"
tree.end
tree "Working Control Packet 0x8A0"
group.long 0x8A0++0x07
line.long 0x00 "CSADDR,Current Source Address Register"
line.long 0x04 "CDADDR,Current Destination Address Register"
rgroup.long (0x8A0+0x08)++0x03
line.long 0x00 "CTCOUNT,Current Transfer Count Register"
hexmask.long.word 0x00 16.--28. 1. " CFTCOUNT ,Current frame transfer count"
hexmask.long.word 0x00 0.--12. 1. " CETCOUNT ,Current element transfer count"
tree.end
tree "Working Control Packet 0x8B0"
group.long 0x8B0++0x07
line.long 0x00 "CSADDR,Current Source Address Register"
line.long 0x04 "CDADDR,Current Destination Address Register"
rgroup.long (0x8B0+0x08)++0x03
line.long 0x00 "CTCOUNT,Current Transfer Count Register"
hexmask.long.word 0x00 16.--28. 1. " CFTCOUNT ,Current frame transfer count"
hexmask.long.word 0x00 0.--12. 1. " CETCOUNT ,Current element transfer count"
tree.end
tree "Working Control Packet 0x8C0"
group.long 0x8C0++0x07
line.long 0x00 "CSADDR,Current Source Address Register"
line.long 0x04 "CDADDR,Current Destination Address Register"
rgroup.long (0x8C0+0x08)++0x03
line.long 0x00 "CTCOUNT,Current Transfer Count Register"
hexmask.long.word 0x00 16.--28. 1. " CFTCOUNT ,Current frame transfer count"
hexmask.long.word 0x00 0.--12. 1. " CETCOUNT ,Current element transfer count"
tree.end
tree "Working Control Packet 0x8D0"
group.long 0x8D0++0x07
line.long 0x00 "CSADDR,Current Source Address Register"
line.long 0x04 "CDADDR,Current Destination Address Register"
rgroup.long (0x8D0+0x08)++0x03
line.long 0x00 "CTCOUNT,Current Transfer Count Register"
hexmask.long.word 0x00 16.--28. 1. " CFTCOUNT ,Current frame transfer count"
hexmask.long.word 0x00 0.--12. 1. " CETCOUNT ,Current element transfer count"
tree.end
tree "Working Control Packet 0x8E0"
group.long 0x8E0++0x07
line.long 0x00 "CSADDR,Current Source Address Register"
line.long 0x04 "CDADDR,Current Destination Address Register"
rgroup.long (0x8E0+0x08)++0x03
line.long 0x00 "CTCOUNT,Current Transfer Count Register"
hexmask.long.word 0x00 16.--28. 1. " CFTCOUNT ,Current frame transfer count"
hexmask.long.word 0x00 0.--12. 1. " CETCOUNT ,Current element transfer count"
tree.end
tree "Working Control Packet 0x8F0"
group.long 0x8F0++0x07
line.long 0x00 "CSADDR,Current Source Address Register"
line.long 0x04 "CDADDR,Current Destination Address Register"
rgroup.long (0x8F0+0x08)++0x03
line.long 0x00 "CTCOUNT,Current Transfer Count Register"
hexmask.long.word 0x00 16.--28. 1. " CFTCOUNT ,Current frame transfer count"
hexmask.long.word 0x00 0.--12. 1. " CETCOUNT ,Current element transfer count"
tree.end
tree "Working Control Packet 0x900"
group.long 0x900++0x07
line.long 0x00 "CSADDR,Current Source Address Register"
line.long 0x04 "CDADDR,Current Destination Address Register"
rgroup.long (0x900+0x08)++0x03
line.long 0x00 "CTCOUNT,Current Transfer Count Register"
hexmask.long.word 0x00 16.--28. 1. " CFTCOUNT ,Current frame transfer count"
hexmask.long.word 0x00 0.--12. 1. " CETCOUNT ,Current element transfer count"
tree.end
tree "Working Control Packet 0x910"
group.long 0x910++0x07
line.long 0x00 "CSADDR,Current Source Address Register"
line.long 0x04 "CDADDR,Current Destination Address Register"
rgroup.long (0x910+0x08)++0x03
line.long 0x00 "CTCOUNT,Current Transfer Count Register"
hexmask.long.word 0x00 16.--28. 1. " CFTCOUNT ,Current frame transfer count"
hexmask.long.word 0x00 0.--12. 1. " CETCOUNT ,Current element transfer count"
tree.end
tree "Working Control Packet 0x920"
group.long 0x920++0x07
line.long 0x00 "CSADDR,Current Source Address Register"
line.long 0x04 "CDADDR,Current Destination Address Register"
rgroup.long (0x920+0x08)++0x03
line.long 0x00 "CTCOUNT,Current Transfer Count Register"
hexmask.long.word 0x00 16.--28. 1. " CFTCOUNT ,Current frame transfer count"
hexmask.long.word 0x00 0.--12. 1. " CETCOUNT ,Current element transfer count"
tree.end
tree "Working Control Packet 0x930"
group.long 0x930++0x07
line.long 0x00 "CSADDR,Current Source Address Register"
line.long 0x04 "CDADDR,Current Destination Address Register"
rgroup.long (0x930+0x08)++0x03
line.long 0x00 "CTCOUNT,Current Transfer Count Register"
hexmask.long.word 0x00 16.--28. 1. " CFTCOUNT ,Current frame transfer count"
hexmask.long.word 0x00 0.--12. 1. " CETCOUNT ,Current element transfer count"
tree.end
tree "Working Control Packet 0x940"
group.long 0x940++0x07
line.long 0x00 "CSADDR,Current Source Address Register"
line.long 0x04 "CDADDR,Current Destination Address Register"
rgroup.long (0x940+0x08)++0x03
line.long 0x00 "CTCOUNT,Current Transfer Count Register"
hexmask.long.word 0x00 16.--28. 1. " CFTCOUNT ,Current frame transfer count"
hexmask.long.word 0x00 0.--12. 1. " CETCOUNT ,Current element transfer count"
tree.end
tree "Working Control Packet 0x950"
group.long 0x950++0x07
line.long 0x00 "CSADDR,Current Source Address Register"
line.long 0x04 "CDADDR,Current Destination Address Register"
rgroup.long (0x950+0x08)++0x03
line.long 0x00 "CTCOUNT,Current Transfer Count Register"
hexmask.long.word 0x00 16.--28. 1. " CFTCOUNT ,Current frame transfer count"
hexmask.long.word 0x00 0.--12. 1. " CETCOUNT ,Current element transfer count"
tree.end
tree "Working Control Packet 0x960"
group.long 0x960++0x07
line.long 0x00 "CSADDR,Current Source Address Register"
line.long 0x04 "CDADDR,Current Destination Address Register"
rgroup.long (0x960+0x08)++0x03
line.long 0x00 "CTCOUNT,Current Transfer Count Register"
hexmask.long.word 0x00 16.--28. 1. " CFTCOUNT ,Current frame transfer count"
hexmask.long.word 0x00 0.--12. 1. " CETCOUNT ,Current element transfer count"
tree.end
tree "Working Control Packet 0x970"
group.long 0x970++0x07
line.long 0x00 "CSADDR,Current Source Address Register"
line.long 0x04 "CDADDR,Current Destination Address Register"
rgroup.long (0x970+0x08)++0x03
line.long 0x00 "CTCOUNT,Current Transfer Count Register"
hexmask.long.word 0x00 16.--28. 1. " CFTCOUNT ,Current frame transfer count"
hexmask.long.word 0x00 0.--12. 1. " CETCOUNT ,Current element transfer count"
tree.end
tree "Working Control Packet 0x980"
group.long 0x980++0x07
line.long 0x00 "CSADDR,Current Source Address Register"
line.long 0x04 "CDADDR,Current Destination Address Register"
rgroup.long (0x980+0x08)++0x03
line.long 0x00 "CTCOUNT,Current Transfer Count Register"
hexmask.long.word 0x00 16.--28. 1. " CFTCOUNT ,Current frame transfer count"
hexmask.long.word 0x00 0.--12. 1. " CETCOUNT ,Current element transfer count"
tree.end
tree "Working Control Packet 0x990"
group.long 0x990++0x07
line.long 0x00 "CSADDR,Current Source Address Register"
line.long 0x04 "CDADDR,Current Destination Address Register"
rgroup.long (0x990+0x08)++0x03
line.long 0x00 "CTCOUNT,Current Transfer Count Register"
hexmask.long.word 0x00 16.--28. 1. " CFTCOUNT ,Current frame transfer count"
hexmask.long.word 0x00 0.--12. 1. " CETCOUNT ,Current element transfer count"
tree.end
tree "Working Control Packet 0x9A0"
group.long 0x9A0++0x07
line.long 0x00 "CSADDR,Current Source Address Register"
line.long 0x04 "CDADDR,Current Destination Address Register"
rgroup.long (0x9A0+0x08)++0x03
line.long 0x00 "CTCOUNT,Current Transfer Count Register"
hexmask.long.word 0x00 16.--28. 1. " CFTCOUNT ,Current frame transfer count"
hexmask.long.word 0x00 0.--12. 1. " CETCOUNT ,Current element transfer count"
tree.end
tree "Working Control Packet 0x9B0"
group.long 0x9B0++0x07
line.long 0x00 "CSADDR,Current Source Address Register"
line.long 0x04 "CDADDR,Current Destination Address Register"
rgroup.long (0x9B0+0x08)++0x03
line.long 0x00 "CTCOUNT,Current Transfer Count Register"
hexmask.long.word 0x00 16.--28. 1. " CFTCOUNT ,Current frame transfer count"
hexmask.long.word 0x00 0.--12. 1. " CETCOUNT ,Current element transfer count"
tree.end
tree "Working Control Packet 0x9C0"
group.long 0x9C0++0x07
line.long 0x00 "CSADDR,Current Source Address Register"
line.long 0x04 "CDADDR,Current Destination Address Register"
rgroup.long (0x9C0+0x08)++0x03
line.long 0x00 "CTCOUNT,Current Transfer Count Register"
hexmask.long.word 0x00 16.--28. 1. " CFTCOUNT ,Current frame transfer count"
hexmask.long.word 0x00 0.--12. 1. " CETCOUNT ,Current element transfer count"
tree.end
tree "Working Control Packet 0x9D0"
group.long 0x9D0++0x07
line.long 0x00 "CSADDR,Current Source Address Register"
line.long 0x04 "CDADDR,Current Destination Address Register"
rgroup.long (0x9D0+0x08)++0x03
line.long 0x00 "CTCOUNT,Current Transfer Count Register"
hexmask.long.word 0x00 16.--28. 1. " CFTCOUNT ,Current frame transfer count"
hexmask.long.word 0x00 0.--12. 1. " CETCOUNT ,Current element transfer count"
tree.end
tree "Working Control Packet 0x9E0"
group.long 0x9E0++0x07
line.long 0x00 "CSADDR,Current Source Address Register"
line.long 0x04 "CDADDR,Current Destination Address Register"
rgroup.long (0x9E0+0x08)++0x03
line.long 0x00 "CTCOUNT,Current Transfer Count Register"
hexmask.long.word 0x00 16.--28. 1. " CFTCOUNT ,Current frame transfer count"
hexmask.long.word 0x00 0.--12. 1. " CETCOUNT ,Current element transfer count"
tree.end
tree "Working Control Packet 0x9F0"
group.long 0x9F0++0x07
line.long 0x00 "CSADDR,Current Source Address Register"
line.long 0x04 "CDADDR,Current Destination Address Register"
rgroup.long (0x9F0+0x08)++0x03
line.long 0x00 "CTCOUNT,Current Transfer Count Register"
hexmask.long.word 0x00 16.--28. 1. " CFTCOUNT ,Current frame transfer count"
hexmask.long.word 0x00 0.--12. 1. " CETCOUNT ,Current element transfer count"
tree.end
tree.end
tree.end
width 0x0B
tree.end
tree "EMIF (External Memory Interface)"
base ad:0xFCFFE800
width 14.
rgroup.long 0x00++0x03
line.long 0x00 "MIDR,Module ID Register"
group.long 0x04++0x0B
line.long 0x00 "AWCC,Asynchronous Wait Cycle Configuration Register"
bitfld.long 0x00 29. " WP1 ,EMIF_nWAIT[1] polarity bit" "Low,High"
bitfld.long 0x00 28. " WP0 ,EMIF_nWAIT[0] polarity bit" "Low,High"
newline
bitfld.long 0x00 20.--21. " CS4_WAIT ,Chip select 4 WAIT signal selection" "nWAIT[0] pin,nWAIT[1] pin,?..."
bitfld.long 0x00 18.--19. " CS3_WAIT ,Chip select 3 WAIT signal selection" "nWAIT[0] pin,nWAIT[1] pin,?..."
newline
bitfld.long 0x00 16.--17. " CS2_WAIT ,Chip select 2 WAIT signal selection" "nWAIT[0] pin,nWAIT[1] pin,?..."
hexmask.long.byte 0x00 0.--7. 1. " MAX_EXT_WAIT ,Maximum extended wait cycles"
line.long 0x04 "SDCR,SDRAM Configuration Register"
bitfld.long 0x04 31. " SR ,Self-refresh mode bit" "Disabled,Enabled"
bitfld.long 0x04 30. " PD ,Power down bit mode" "Disabled,Enabled"
newline
bitfld.long 0x04 29. " PDWR ,Perform refreshes during power down" "Not performed,Performed"
bitfld.long 0x04 14. " NM ,Narrow mode bit" "32-bit,16-bit"
newline
bitfld.long 0x04 9.--11. " CL ,CAS latency" ",,2 EMIF_CLK,3 EMIF_CLK,?..."
bitfld.long 0x04 8. " BIT11_9LOCK ,Bits 11 to 9 lock" "Locked,Not locked"
newline
bitfld.long 0x04 4.--6. " IBANK ,Internal SDRAM bank size" "1 bank,2 bank,4 bank,?..."
bitfld.long 0x04 0.--2. " PAGESIZE ,Internal page size of connected SDRAM devices" "8 column,9 column,10 column,11 column,?..."
line.long 0x08 "SDRCR,SDRAM Refresh Control Register"
hexmask.long.word 0x08 0.--12. 1. " RR ,Refresh rate"
group.long 0x10++0x03
line.long 0x00 "CE2CFG,Asynchronous 1 Configuration Register"
bitfld.long 0x00 31. " SS ,Select strobe bit" "Normal,Strobe"
bitfld.long 0x00 30. " EW ,Extend wait bit" "Disabled,Enabled"
newline
bitfld.long 0x00 26.--29. " W_SETUP ,Write setup width in EMIF_CLK cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 20.--25. " W_STROBE ,Write strobe width in EMIF_CLK cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.long 0x00 17.--19. " W_HOLD ,Write hold width in EMIF_CLK cycles" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 13.--16. " R_SETUP ,Read setup width in EMIF_CLK cycles (minus 1)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 7.--12. " R_STROBE ,Read strobe width in EMIF_CLK cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 4.--6. " R_HOLD ,Read hold width in EMIF_CLK cycles" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 2.--3. " TA ,Minimum turn-around time -" "0,1,2,3"
bitfld.long 0x00 0.--1. " ASIZE ,Asynchronous data bus width" "8-bit,16-bit,?..."
group.long 0x14++0x03
line.long 0x00 "CE3CFG,Asynchronous 2 Configuration Register"
bitfld.long 0x00 31. " SS ,Select strobe bit" "Normal,Strobe"
bitfld.long 0x00 30. " EW ,Extend wait bit" "Disabled,Enabled"
newline
bitfld.long 0x00 26.--29. " W_SETUP ,Write setup width in EMIF_CLK cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 20.--25. " W_STROBE ,Write strobe width in EMIF_CLK cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.long 0x00 17.--19. " W_HOLD ,Write hold width in EMIF_CLK cycles" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 13.--16. " R_SETUP ,Read setup width in EMIF_CLK cycles (minus 1)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 7.--12. " R_STROBE ,Read strobe width in EMIF_CLK cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 4.--6. " R_HOLD ,Read hold width in EMIF_CLK cycles" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 2.--3. " TA ,Minimum turn-around time -" "0,1,2,3"
bitfld.long 0x00 0.--1. " ASIZE ,Asynchronous data bus width" "8-bit,16-bit,?..."
group.long 0x18++0x03
line.long 0x00 "CE4CFG,Asynchronous 3 Configuration Register"
bitfld.long 0x00 31. " SS ,Select strobe bit" "Normal,Strobe"
bitfld.long 0x00 30. " EW ,Extend wait bit" "Disabled,Enabled"
newline
bitfld.long 0x00 26.--29. " W_SETUP ,Write setup width in EMIF_CLK cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 20.--25. " W_STROBE ,Write strobe width in EMIF_CLK cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.long 0x00 17.--19. " W_HOLD ,Write hold width in EMIF_CLK cycles" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 13.--16. " R_SETUP ,Read setup width in EMIF_CLK cycles (minus 1)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 7.--12. " R_STROBE ,Read strobe width in EMIF_CLK cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 4.--6. " R_HOLD ,Read hold width in EMIF_CLK cycles" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 2.--3. " TA ,Minimum turn-around time -" "0,1,2,3"
bitfld.long 0x00 0.--1. " ASIZE ,Asynchronous data bus width" "8-bit,16-bit,?..."
group.long 0x20++0x03
line.long 0x00 "SDTIMR,SDRAM Timing Register"
bitfld.long 0x00 27.--31. " T_RFC ,Specifies the Trfc value of the SDRAM" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 24.--26. " T_RP ,Specifies the Trp value of the SDRAM" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 20.--22. " T_RCD ,Specifies the Trcd value of the SDRAM" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 16.--18. " T_WR ,Specifies the Twr value of the SDRAM" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 12.--15. " T_RAS ,Specifies the Tras value of the SDRAM" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. " T_RC ,Specifies the Trc value of the SDRAM" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 4.--6. " T_RRD ,Specifies the Trrd value of the SDRAM" "0,1,2,3,4,5,6,7"
group.long 0x3C++0x07
line.long 0x00 "SDSRETR,SDRAM Self Refresh Exit Timing Register"
bitfld.long 0x00 0.--4. " T_XS ,Specifies the minimum number of ECLKOUT cycles (minus 1)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x04 "INTRAW,EMIF Interrupt Raw Register"
eventfld.long 0x04 2. " WR ,Wait rise" "Not occurred,Occurred"
eventfld.long 0x04 1. " LT ,Line trap" "No effect,Occurred"
newline
eventfld.long 0x04 0. " AT ,Asynchronous timeout" "Not occurred,Occurred"
sif !cpuis("TMS570LS3137-EP")
group.long 0x44++0x03
line.long 0x00 "INTMSK,EMIF Interrupt Masked Register"
setclrfld.long 0x00 2. 0x04 2. 0x08 2. " WR_MASKED_SET/CLR ,Wait rise masked" "Not masked,Masked"
setclrfld.long 0x00 1. 0x04 1. 0x08 1. " LT_MASKED_SET/CLR ,Masked line trap" "Not masked,Masked"
newline
setclrfld.long 0x00 0. 0x04 0. 0x08 0. " AT_MASKED_SET/CLR ,Asynchronous timeout masked" "Not masked,Masked"
else
group.long 0x44++0x03
line.long 0x00 "INTMSK,EMIF Interrupt Masked Register"
eventfld.long 0x00 2. " WR_MASKED ,Wait rise masked" "Not masked,Masked"
eventfld.long 0x00 1. " LT_MASKED ,Masked line trap" "Not masked,Masked"
newline
eventfld.long 0x00 0. " AT_MASKED ,Asynchronous timeout masked" "Not masked,Masked"
group.long 0x48++0x03
line.long 0x00 "INTMSK_SET/CLR,EMIF Interrupt Masked Register"
setclrfld.long 0x00 2. 0x00 2. 0x04 2. " WR_MASKED_SET/CLR ,Wait rise masked" "Not masked,Masked"
setclrfld.long 0x00 1. 0x00 1. 0x04 1. " LT_MASKED_SET/CLR ,Masked line trap" "Not masked,Masked"
newline
setclrfld.long 0x00 0. 0x00 0. 0x04 0. " AT_MASKED_SET/CLR ,Asynchronous timeout masked" "Not masked,Masked"
endif
group.long 0x68++0x03
line.long 0x00 "PMCR,Page Mode Control Register"
bitfld.long 0x00 18.--23. " CS4_PG_DEL ,Page access delay for NOR flash connected on CS4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 17. " CS4_PG_SIZE ,Page size for NOR flash connected on CS4" "4 words,8 words"
newline
bitfld.long 0x00 16. " CS4_PG_MD_EN ,Page mode enable for NOR flash connected on CS4" "Disabled,Enabled"
bitfld.long 0x00 10.--15. " CS3_PG_DEL ,Page access delay for NOR flash connected on CS3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.long 0x00 9. " CS3_PG_SIZE ,Page size for NOR flash connected on CS3" "4 words,8 words"
bitfld.long 0x00 8. " CS3_PG_MD_EN ,Page mode enable for NOR flash connected on CS3" "Disabled,Enabled"
newline
bitfld.long 0x00 2.--7. " CS2_PG_DEL ,Page access delay for NOR flash connected on CS2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 1. " CS2_PG_SIZE ,Page size for NOR flash connected on C2" "4 words,8 words"
newline
bitfld.long 0x00 0. " CS2_PG_MD_EN ,Page mode enable for NOR flash connected on CS2" "Disabled,Enabled"
width 0x0B
tree.end
tree.open "ADC (Analog To Digital Converter Module)"
tree "MibADC1"
base ad:0xFFF7C000
width 10.
group.long 0x00++0x3
line.long 0x0 "RSTCR,Reset Control Register"
bitfld.long 0x00 0. " RESET ,ADC Reset" "No reset,Reset"
group.long 0x04++0x3
line.long 0x0 "OPMODECR,Operating Mode Control Register"
bitfld.long 0x00 31. " 10/12_BIT ,Resolution of the ADC core" "10-bit,12-bit"
bitfld.long 0x00 24. " COS ,Continue on Suspend Enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 17.--20. " CHN_TEST_EN ,ADC Channel Test Enable" "Disabled,Disabled,Disabled,Disabled,Disabled,Enabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled"
bitfld.long 0x00 16. " RAM_TEST_EN ,ADC RAM Test Enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 8. " POWERDOWN ,ADC Internal Clocks Powerdown Mode" "Normal,Power-down"
bitfld.long 0x00 4. " NORMAL ,ADC Power Down When Idle" "Normal,Power-down"
textline " "
bitfld.long 0x00 0. " ADC_EN ,ADC Enable" "Disabled,Enabled"
group.long 0x08++0x3
line.long 0x0 "CLOCKCR,Clock Prescaler"
bitfld.long 0x00 0.--4. " PS[4:0] ,ADC Clock Prescaler" "1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles,16 cycles,17 cycles,18 cycles,19 cycles,20 cycles,21 cycles,22 cycles,23 cycles,24 cycles,25 cycles,26 cycles,27 cycles,28 cycles,29 cycles,30 cycles,31 cycles,32 cycles"
if (((d.l((ad:0xFFF7C000+0x0c)))&0x01000201)==0x00000001)
group.long (0x0c)++0x03
line.long 0x00 "CALCR,Calibration Conversion Register"
bitfld.long 0x00 24. " SELF_TEST ,Self-Test Enable" "Disabled,Enabled"
bitfld.long 0x00 16. " CAL_ST ,Calibration Conversion Start" "No effect/completed,Started"
textline " "
bitfld.long 0x00 9. " BRIDGE_EN ,Bridge Enable" "Midpoint,Full"
bitfld.long 0x00 8. " HILO ,Test and Reference Source Selection" "(AD_REFHI*R1+AD_REFLO*R2)/(R1+R2),(AD_REFLO*R1+AD_REFHI*R2)/(R1+R2)"
textline " "
bitfld.long 0x00 0. " CAL_EN ,Calibration Enable" "Disabled,Enabled"
elif (((d.l((ad:0xFFF7C000+0x0c)))&0x01000201)==0x01000000)
group.long (0x0c)++0x03
line.long 0x00 "CALCR,Calibration Conversion Register"
bitfld.long 0x00 24. " SELF_TEST ,Self-Test Enable" "Disabled,Enabled"
bitfld.long 0x00 16. " CAL_ST ,Calibration Conversion Start" "No effect/completed,Started"
textline " "
bitfld.long 0x00 9. " BRIDGE_EN ,Bridge Enable" "Midpoint,Full"
bitfld.long 0x00 8. " HILO ,Test and Reference Source Selection" "(AD_REFLO via R1)||(R2 to Vin),(AD_REFHI via R1)||(R2 to Vin)"
textline " "
bitfld.long 0x00 0. " CAL_EN ,Calibration Enable" "Disabled,Enabled"
elif (((d.l((ad:0xFFF7C000+0x0c)))&0x01000201)==0x00000201)
group.long (0x0c)++0x03
line.long 0x00 "CALCR,Calibration Conversion Register"
bitfld.long 0x00 24. " SELF_TEST ,Self-Test Enable" "Disabled,Enabled"
bitfld.long 0x00 16. " CAL_ST ,Calibration Conversion Start" "No effect/completed,Started"
textline " "
bitfld.long 0x00 9. " BRIDGE_EN ,Bridge Enable" "Midpoint,Full"
bitfld.long 0x00 8. " HILO ,Test and Reference Source Selection" "AD_REFLO,AD_REFHI"
textline " "
bitfld.long 0x00 0. " CAL_EN ,Calibration Enable" "Disabled,Enabled"
elif (((d.l((ad:0xFFF7C000+0x0c)))&0x01000201)==0x01000200)
group.long (0x0c)++0x03
line.long 0x00 "CALCR,Calibration Conversion Register"
bitfld.long 0x00 24. " SELF_TEST ,Self-Test Enable" "Disabled,Enabled"
bitfld.long 0x00 16. " CAL_ST ,Calibration Conversion Start" "No effect/completed,Started"
textline " "
bitfld.long 0x00 9. " BRIDGE_EN ,Bridge Enable" "Midpoint,Full"
bitfld.long 0x00 8. " HILO ,Test and Reference Source Selection" "(AD_REFLO via R1)||(R2 to Vin),(AD_REFHI via R1)||(R2 to Vin)"
textline " "
bitfld.long 0x00 0. " CAL_EN ,Calibration Enable" "Disabled,Enabled"
else
group.long (0x0c)++0x03
line.long 0x00 "CALCR,Calibration Conversion Register"
bitfld.long 0x00 24. " SELF_TEST ,Self-Test Enable" "Disabled,Enabled"
bitfld.long 0x00 16. " CAL_ST ,Calibration Conversion Start" "No effect/completed,Started"
textline " "
bitfld.long 0x00 9. " BRIDGE_EN ,Bridge Enable" "Midpoint,Full"
textline " "
bitfld.long 0x00 0. " CAL_EN ,Calibration Enable" "Disabled,Enabled"
endif
width 13.
tree "Event Group Registers"
group.long (0x0+0x10)++0x3
line.long 0x0 "EVMODECR,Event Group MODE Control Register"
bitfld.long 0x00 16. " NO_RESET_ON_CHNSEL ,No Event Group Results Memory Reset on New Channel Select" "Reset,No reset"
bitfld.long 0x00 8.--9. " EV_DATA_FMT ,Event Group (Read) Data Format" "12 bit,10 bit,8 bit,?..."
textline " "
bitfld.long 0x00 5. " EV_CHID ,Channel ID Mode for the Event Group" "Forced to 0,ID of A/D channel"
bitfld.long 0x00 4. " OVR_EV_RAM_IGN ,Overrun Event Group RAM Ignore" "Not ignored,Ignored"
textline " "
bitfld.long 0x00 2. " EV_8BIT ,Event Group 8-bit result mode" "10-bit,8-bit"
bitfld.long 0x00 1. " EV_MODE ,Event mode" "Single,Continuous"
textline " "
bitfld.long 0x00 0. " FRZ_EV ,Freeze conversion Event Group" "Completed,Frozen"
group.long (0x0+0x1C)++0x3
line.long 0x0 "EVSRC,Event Group Trigger Source Select"
bitfld.long 0x00 4. " EV_EDG_BOTH ,Event Group Trigger Edge Polarity Select" "Defined edge,Any edge"
bitfld.long 0x00 3. " EV_EDG_SEL ,ADC Event Group Trigger Edge Select" "High/low,Low/high"
textline " "
bitfld.long 0x00 0.--2. " EVSRC[2:0] ,Event Group Trigger Source Select" "ADEVT,Internal,Internal,Internal,Internal,Internal,Internal,Internal"
group.long (0x0+0x28)++0x3
line.long 0x0 "EVINTENA,Event Group Interrupt Enable"
bitfld.long 0x00 3. " EV_END_INT_EN ,Event Group Conversion End Interrupt Enable" "Disabled,Enabled"
bitfld.long 0x00 1. " EV_OVR_INT_EN ,Event Group Memory Overrun Interrupt Enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 0. " EV_THR_INT_EN ,Event Group Memory Threshold Interrupt Enable" "Disabled,Enabled"
group.long (0x0+0x34)++0x3
line.long 0x0 "EVINTFLG,Event Group Interrupt Flag"
eventfld.long 0x00 3. " EV_END ,Event Group Conversion End" "Not converted,Converted"
rbitfld.long 0x00 2. " EV_MEM_EMPTY ,Event Group FIFO Empty Status" "Not empty,Empty"
textline " "
rbitfld.long 0x00 1. " EV_MEM_OVERFLOW ,Event Group Memory Overrun Flag" "No overrun,Overrun"
eventfld.long 0x00 0. " EV_THR_INT_FLAG ,Event Group Threshold Interrupt Flag" "No interrupt,Interrupt"
group.long (0x0+0x40)++0x3
line.long 0x0 "EVINTCR,Event Group Interrupt Threshold Counter"
hexmask.long.byte 0x00 9.--15. 1. " SIGN_EXTENSION ,Sign Extension"
hexmask.long.word 0x00 0.--8. 1. " EV_THR[8:0] ,Event Group Interrupt Threshold Counter"
group.long (0x0+0x4C)++0x3
line.long 0x0 "EVDMACR,Event Group DMA Control Register"
hexmask.long.word 0x00 16.--24. 1. " EVBLOCKS[8:0] ,Number of Event Group Memory Buffers to be Transferred"
bitfld.long 0x00 3. " DMA_EV_END ,Event Group Conversion End DMA Transfer Enable" "0,1"
textline " "
bitfld.long 0x00 2. " EV_BLK_XFER ,Event Group Block DMA Transfer Enable" "Disabled,Enabled"
bitfld.long 0x00 0. " EV_DMA_EN ,Event Group DMA Transfer Enable" "Disabled,Enabled"
group.long (0x0+0x60)++0x3
line.long 0x0 "EVSAMP,Event Group Sample Window"
hexmask.long.word 0x00 0.--11. 1. " EV_ACQ ,Event Group Acquisition Prescale Bits"
group.long (0x0+0x6C)++0x3
line.long 0x0 "EVSR,Event Group Status Register"
rbitfld.long 0x00 3. " EV_MEM_EMPTY ,Event Group Memory Empty" "Not empty,Empty"
rbitfld.long 0x00 2. " EV_BUSY ,Event Group Conversion-Busy Flag" "Not active,Busy"
textline " "
rbitfld.long 0x00 1. " EV_STOP ,Event Group Conversion Stopped Flag" "Not frozen,Frozen"
eventfld.long 0x00 0. " EV_END ,Event Group Conversion-Ended Flag R/W" "Not completed,Completed"
group.long (0x0+0x78)++0x3
line.long 0x0 "EVSEL,Event Group select register"
bitfld.long 0x00 23. " EVCHNSEL [23] ,A/D Event Group Channel 23 Selection Bit" "Not converted,Converted"
bitfld.long 0x00 22. " [22] ,A/D Event Group Channel 22 Selection Bit" "Not converted,Converted"
bitfld.long 0x00 21. " [21] ,A/D Event Group Channel 21 Selection Bit" "Not converted,Converted"
bitfld.long 0x00 20. " [20] ,A/D Event Group Channel 20 Selection Bit" "Not converted,Converted"
textline " "
bitfld.long 0x00 19. " [19] ,A/D Event Group Channel 19 Selection Bit" "Not converted,Converted"
bitfld.long 0x00 18. " [18] ,A/D Event Group Channel 18 Selection Bit" "Not converted,Converted"
bitfld.long 0x00 17. " [17] ,A/D Event Group Channel 17 Selection Bit" "Not converted,Converted"
bitfld.long 0x00 16. " [16] ,A/D Event Group Channel 16 Selection Bit" "Not converted,Converted"
textline " "
bitfld.long 0x00 15. " [15] ,A/D Event Group Channel 15 Selection Bit" "Not converted,Converted"
bitfld.long 0x00 14. " [14] ,A/D Event Group Channel 14 Selection Bit" "Not converted,Converted"
bitfld.long 0x00 13. " [13] ,A/D Event Group Channel 13 Selection Bit" "Not converted,Converted"
bitfld.long 0x00 12. " [12] ,A/D Event Group Channel 12 Selection Bit" "Not converted,Converted"
textline " "
bitfld.long 0x00 11. " [11] ,A/D Event Group Channel 11 Selection Bit" "Not converted,Converted"
bitfld.long 0x00 10. " [10] ,A/D Event Group Channel 10 Selection Bit" "Not converted,Converted"
bitfld.long 0x00 9. " [9] ,A/D Event Group Channel 9 Selection Bit" "Not converted,Converted"
bitfld.long 0x00 8. " [8] ,A/D Event Group Channel 8 Selection Bit" "Not converted,Converted"
textline " "
bitfld.long 0x00 7. " [7] ,A/D Event Group Channel 7 Selection Bit" "Not converted,Converted"
bitfld.long 0x00 6. " [6] ,A/D Event Group Channel 6 Selection Bit" "Not converted,Converted"
bitfld.long 0x00 5. " [5] ,A/D Event Group Channel 5 Selection Bit" "Not converted,Converted"
bitfld.long 0x00 4. " [4] ,A/D Event Group Channel 4 Selection Bit" "Not converted,Converted"
textline " "
bitfld.long 0x00 3. " [3] ,A/D Event Group Channel 3 Selection Bit" "Not converted,Converted"
bitfld.long 0x00 2. " [2] ,A/D Event Group Channel 2 Selection Bit" "Not converted,Converted"
bitfld.long 0x00 1. " [1] ,A/D Event Group Channel 1 Selection Bit" "Not converted,Converted"
bitfld.long 0x00 0. " [0] ,A/D Event Group Channel 0 Selection Bit" "Not converted,Converted"
hgroup.long (0x0+0x90)++0x3
hide.long 0x0 "EVBUFFER0,Event Group Buffer 0"
in
hgroup.long (0x0+0x94)++0x3
hide.long 0x0 "EVBUFFER1,Event Group Buffer 1"
in
hgroup.long (0x0+0x98)++0x3
hide.long 0x0 "EVBUFFER2,Event Group Buffer 2"
in
hgroup.long (0x0+0x9C)++0x3
hide.long 0x0 "EVBUFFER3,Event Group Buffer 3"
in
hgroup.long (0x0+0xA0)++0x3
hide.long 0x0 "EVBUFFER4,Event Group Buffer 4"
in
hgroup.long (0x0+0xA4)++0x3
hide.long 0x0 "EVBUFFER5,Event Group Buffer 5"
in
hgroup.long (0x0+0xA8)++0x3
hide.long 0x0 "EVBUFFER6,Event Group Buffer 6"
in
hgroup.long (0x0+0xAC)++0x3
hide.long 0x0 "EVBUFFER7,Event Group Buffer 7"
in
if ((d.l(ad:0xFFF7C000+0x04)&0x80000000)==0x80000000)
group.long (0x0+0xF0)++0x3
line.long 0x0 "EVEMUBUFFER,Event Group EMU Buffer"
bitfld.long 0x00 31. " EV_EMPTY ,Event Group FIFO Empty" "Not empty,Empty"
bitfld.long 0x00 16.--20. " EVCHID[4:0] ,Event Group Channel ID" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,Channel 8,Channel 9,Channel 10,Channel 11,Channel 12,Channel 13,Channel 14,Channel 15,Channel 16,Channel 17,Channel 18,Channel 19,Channel 20,Channel 21,Channel 22,Channel 23,Channel 24,Channel 25,Channel 26,Channel 27,Channel 28,Channel 29,Channel 30,Channel 31"
textline " "
hexmask.long.word 0x00 0.--11. 1. " EVDR[11:0] ,Event Group Digital Result"
else
group.long (0x0+0xF0)++0x3
line.long 0x0 "EVEMUBUFFER,Event Group EMU Buffer"
bitfld.long 0x00 15. " EV_EMPTY ,Event Group FIFO Empty" "Not empty,Empty"
bitfld.long 0x00 10.--14. " EVCHID[4:0] ,Event Group Channel ID" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,Channel 8,Channel 9,Channel 10,Channel 11,Channel 12,Channel 13,Channel 14,Channel 15,Channel 16,Channel 17,Channel 18,Channel 19,Channel 20,Channel 21,Channel 22,Channel 23,Channel 24,Channel 25,Channel 26,Channel 27,Channel 28,Channel 29,Channel 30,Channel 31"
textline " "
hexmask.long.word 0x00 0.--9. 1. " EVDR[9:0] ,Event Group Digital Result"
endif
width 9.
tree "ADC ADEVT Pin Control Registers"
group.long 0xFC++0x3
line.long 0x0 "EVTDIR,Event Group pin direction selection"
bitfld.long 0x00 0. " EVT_DIR ,ADEVT Pin Direction Selection" "Input,Output"
if (((d.l((ad:0xFFF7C000+0xfc)))&0x01)==0x01)
group.long 0x100++0x3
line.long 0x0 "EVTOUT,Event Group pin data output"
bitfld.long 0x00 0. " EVT_OUT ,ADEVT Pin Data Output" "Low,High"
else
hgroup.long 0x100++0x3
hide.long 0x0 "EVTOUT,Event Group pin data output"
endif
rgroup.long 0x104++0x3
line.long 0x0 "EVTIN,Event Group pin input value"
bitfld.long 0x00 0. " EVT_IN ,ADEVT Pin Input Value" "Low,High"
group.long 0x108++0x3
line.long 0x0 "EVTSET,Event Group pin set"
setclrfld.long 0x00 0. 0x00 0. 0x04 0. " ADEVT_set/clr ,ADEVT Pin Set" "Low,High"
if ((((d.l((ad:0xFFF7C000+0xfc)))&0x01)==0x01)&&(((d.l((ad:0xFFF7C000+0x0100)))&0x01)==0x01))
group.long 0x110++0x3
line.long 0x0 "EVTPDR,Event Group pin open-drain enable"
bitfld.long 0x00 0. " ADEVT_PDR ,ADEVT Pin Open-Drain Enable" "Disabled,Enabled"
else
hgroup.long 0x110++0x3
hide.long 0x0 "EVTPDR,Event Group pin open-drain enable"
endif
if (((d.l((ad:0xFFF7C000+0xfc)))&0x01)==0x00)
group.long 0x114++0x3
line.long 0x0 "EVTPDIS,Event Group pin pull control enable"
bitfld.long 0x00 0. " ADEVT_PDIS ,ADEVT Pin Pull Control Enable" "Enabled,Disabled"
group.long 0x118++0x3
line.long 0x0 "EVTPSEL,Event Group pull select"
bitfld.long 0x00 0. " ADEVT_PSEL ,ADEVT Pull Select" "Pull-down,Pull-up"
else
hgroup.long 0x114++0x3
hide.long 0x0 "EVTPDIS,Event Group pin pull control enable"
hgroup.long 0x118++0x3
hide.long 0x0 "EVTPSEL,Event Group pull select"
endif
tree.end
width 18.
group.long (0x0+0x11C)++0x3
line.long 0x0 "EVSAMPDISEN,Event Group Sampling Capacitor Discharge Mode"
hexmask.long.byte 0x00 8.--15. 1. " EV_SAMP_DIS_CYC[7:0] ,ADC Sampling Capacitor is Dicharged Cycles"
bitfld.long 0x00 0. " EV_SAMP_DIS_EN ,Sampling Capacitor Discharge Mode" "Disabled,Enabled"
group.long (0x0+0x168)++0x3
line.long 0x0 "EVFIFORESETCR,Event Group FIFO Reset"
bitfld.long 0x00 0. " EV_FIFO_RESET ,Reset the ADC Event Group FIFO" "No reset,Reset"
group.long (0x0+0x174)++0x3
line.long 0x0 "EVRAMADDR,Event Group ADC RAM Pointer"
hexmask.long.word 0x00 0.--8. 1. " EV_RAM_ADDR ,Event Group ADC RAM Pointer"
group.long (0x0+0x190)++0x03
line.long 0x00 "EVCHNSELMODECTRL, ADC Event Group Channel Selection Mode Control Register"
bitfld.long 0x00 0.--3. " EV_ENH_CHNSEL_MODE_ENABLE , Enable Enhanced Channel Selection Mode" ",,,,,Disabled,,,,,Enabled,?..."
group.long (0x0+0x19C)++0x07
line.long 0x00 "EVCURRCOUNT, ADC Event Group Current Count Register"
bitfld.long 0x00 0.--4. " EV_CURRENT_COUNT , Value For The Event Group Conversions" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x04 "EVMAXCOUNT, ADC Event Group Maximum Count Register"
bitfld.long 0x04 0.--4. " EV_MAX_COUNT , Value For The Event Group Conversions" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
tree.end
width 13.
tree "Group 1 Registers"
group.long (0x4+0x10)++0x3
line.long 0x0 "G1MODECR,Group 1 MODE Control Register"
bitfld.long 0x00 16. " NO_RESET_ON_CHNSEL ,No Group 1 Results Memory Reset on New Channel Select" "Reset,No reset"
bitfld.long 0x00 8.--9. " G1_DATA_FMT ,Group 1 (Read) Data Format" "12 bit,10 bit,8 bit,?..."
textline " "
bitfld.long 0x00 5. " G1_CHID ,Channel ID Mode for the Group 1" "Forced to 0,ID of A/D channel"
bitfld.long 0x00 4. " OVR_G1_RAM_IGN ,Overrun Event Group RAM Ignore" "Not ignored,Ignored"
textline " "
bitfld.long 0x00 3. " G1_HW_TRIG ,Group 1 Hardware Triggered" "Software,Event"
bitfld.long 0x00 2. " G1_SBIT ,Group1 8-bit result mode" "10-bit,8-bit"
textline " "
bitfld.long 0x00 1. " G1_MODE ,Group 1 mode" "Single,Continuous"
bitfld.long 0x00 0. " FRZ_G1 ,Freeze Conversion Group 1" "Completed,Frozen"
group.long (0x4+0x1C)++0x3
line.long 0x0 "G1SRC,Group 1 Trigger Source Select"
bitfld.long 0x00 4. " G1_EDG_BOTH ,Group 1 Trigger Edge Polarity Select" "Defined edge,Any edge"
bitfld.long 0x00 3. " G1_EDG_SEL ,ADC Group 1 Trigger Edge Select" "High/low,Low/high"
textline " "
bitfld.long 0x00 0.--2. " G1SRC[2:0] ,Group 1 Trigger Source Select" "ADEVT,Internal,Internal,Internal,Internal,Internal,Internal,Internal"
group.long (0x4+0x28)++0x3
line.long 0x0 "G1INTENA,Group 1 Interrupt Enable"
bitfld.long 0x00 3. " G1_END_INT_EN ,Group 1 Conversion End Interrupt Enable" "Disabled,Enabled"
bitfld.long 0x00 1. " G1_OVR_INT_EN ,Group 1 Memory Overrun Interrupt Enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 0. " G1_THR_INT_EN ,Group 1 Memory Threshold Interrupt Enable" "Disabled,Enabled"
group.long (0x4+0x34)++0x3
line.long 0x0 "G1INTFLG,Group 1 Interrupt Flag"
eventfld.long 0x00 3. " G1_END ,Group 1 Conversion End" "Not converted,Converted"
rbitfld.long 0x00 2. " G1_MEM_EMPTY ,Group 1 FIFO Empty Status" "Not empty,Empty"
textline " "
rbitfld.long 0x00 1. " G1_MEM_OVERFLOW ,Group 1 Memory Overrun Flag" "No overrun,Overrun"
eventfld.long 0x00 0. " G1_THR_INT_FLAG ,Group 1 Threshold Interrupt Flag" "No interrupt,Interrupt"
group.long (0x4+0x40)++0x3
line.long 0x0 "G1INTCR,Group 1 Interrupt Threshold Counter"
hexmask.long.byte 0x00 9.--15. 1. " SIGN_EXTENSION ,Sign Extension"
hexmask.long.word 0x00 0.--8. 1. " G1_THR[8:0] ,Group 1 Interrupt Threshold Counter"
group.long (0x4+0x4C)++0x3
line.long 0x0 "G1DMACR,Group 1 DMA Control Register"
hexmask.long.word 0x00 16.--24. 1. " G1BLOCKS[8:0] ,Number of Group 1 Memory Buffers to be Transferred"
bitfld.long 0x00 3. " DMA_G1_END ,Group 1 Conversion End DMA Transfer Enable" "0,1"
textline " "
bitfld.long 0x00 2. " G1_BLK_XFER ,Group 1 Block DMA Transfer Enable" "Disabled,Enabled"
bitfld.long 0x00 0. " G1_DMA_EN ,Group 1 DMA Transfer Enable" "Disabled,Enabled"
group.long (0x4+0x60)++0x3
line.long 0x0 "G1SAMP,Group 1 Sample Window"
hexmask.long.word 0x00 0.--11. 1. " G1_ACQ ,Group 1 Acquisition Prescale Bits"
group.long (0x4+0x6C)++0x3
line.long 0x0 "G1SR,Group 1 Status Register"
rbitfld.long 0x00 3. " G1_MEM_EMPTY ,Group 1 Memory Empty" "Not empty,Empty"
rbitfld.long 0x00 2. " G1_BUSY ,Group 1 Conversion-Busy Flag" "Not active,Busy"
textline " "
rbitfld.long 0x00 1. " G1_STOP ,Group 1 Conversion Stopped Flag" "Not frozen,Frozen"
eventfld.long 0x00 0. " G1_END ,Group 1 Conversion-Ended Flag R/W" "Not completed,Completed"
group.long (0x4+0x78)++0x3
line.long 0x0 "G1SEL,Group 1 select register"
bitfld.long 0x00 23. " G1CHNSEL [23] ,A/D Group 1 Channel 23 Selection Bit" "Not converted,Converted"
bitfld.long 0x00 22. " [22] ,A/D Group 1 Channel 22 Selection Bit" "Not converted,Converted"
bitfld.long 0x00 21. " [21] ,A/D Group 1 Channel 21 Selection Bit" "Not converted,Converted"
bitfld.long 0x00 20. " [20] ,A/D Group 1 Channel 20 Selection Bit" "Not converted,Converted"
textline " "
bitfld.long 0x00 19. " [19] ,A/D Group 1 Channel 19 Selection Bit" "Not converted,Converted"
bitfld.long 0x00 18. " [18] ,A/D Group 1 Channel 18 Selection Bit" "Not converted,Converted"
bitfld.long 0x00 17. " [17] ,A/D Group 1 Channel 17 Selection Bit" "Not converted,Converted"
bitfld.long 0x00 16. " [16] ,A/D Group 1 Channel 16 Selection Bit" "Not converted,Converted"
textline " "
bitfld.long 0x00 15. " [15] ,A/D Group 1 Channel 15 Selection Bit" "Not converted,Converted"
bitfld.long 0x00 14. " [14] ,A/D Group 1 Channel 14 Selection Bit" "Not converted,Converted"
bitfld.long 0x00 13. " [13] ,A/D Group 1 Channel 13 Selection Bit" "Not converted,Converted"
bitfld.long 0x00 12. " [12] ,A/D Group 1 Channel 12 Selection Bit" "Not converted,Converted"
textline " "
bitfld.long 0x00 11. " [11] ,A/D Group 1 Channel 11 Selection Bit" "Not converted,Converted"
bitfld.long 0x00 10. " [10] ,A/D Group 1 Channel 10 Selection Bit" "Not converted,Converted"
bitfld.long 0x00 9. " [9] ,A/D Group 1 Channel 9 Selection Bit" "Not converted,Converted"
bitfld.long 0x00 8. " [8] ,A/D Group 1 Channel 8 Selection Bit" "Not converted,Converted"
textline " "
bitfld.long 0x00 7. " [7] ,A/D Group 1 Channel 7 Selection Bit" "Not converted,Converted"
bitfld.long 0x00 6. " [6] ,A/D Group 1 Channel 6 Selection Bit" "Not converted,Converted"
bitfld.long 0x00 5. " [5] ,A/D Group 1 Channel 5 Selection Bit" "Not converted,Converted"
bitfld.long 0x00 4. " [4] ,A/D Group 1 Channel 4 Selection Bit" "Not converted,Converted"
textline " "
bitfld.long 0x00 3. " [3] ,A/D Group 1 Channel 3 Selection Bit" "Not converted,Converted"
bitfld.long 0x00 2. " [2] ,A/D Group 1 Channel 2 Selection Bit" "Not converted,Converted"
bitfld.long 0x00 1. " [1] ,A/D Group 1 Channel 1 Selection Bit" "Not converted,Converted"
bitfld.long 0x00 0. " [0] ,A/D Group 1 Channel 0 Selection Bit" "Not converted,Converted"
hgroup.long (0x20+0x90)++0x3
hide.long 0x0 "G1BUFFER0,Group 1 Buffer 0"
in
hgroup.long (0x20+0x94)++0x3
hide.long 0x0 "G1BUFFER1,Group 1 Buffer 1"
in
hgroup.long (0x20+0x98)++0x3
hide.long 0x0 "G1BUFFER2,Group 1 Buffer 2"
in
hgroup.long (0x20+0x9C)++0x3
hide.long 0x0 "G1BUFFER3,Group 1 Buffer 3"
in
hgroup.long (0x20+0xA0)++0x3
hide.long 0x0 "G1BUFFER4,Group 1 Buffer 4"
in
hgroup.long (0x20+0xA4)++0x3
hide.long 0x0 "G1BUFFER5,Group 1 Buffer 5"
in
hgroup.long (0x20+0xA8)++0x3
hide.long 0x0 "G1BUFFER6,Group 1 Buffer 6"
in
hgroup.long (0x20+0xAC)++0x3
hide.long 0x0 "G1BUFFER7,Group 1 Buffer 7"
in
if ((d.l(ad:0xFFF7C000+0x04)&0x80000000)==0x80000000)
group.long (0x4+0xF0)++0x3
line.long 0x0 "G1EMUBUFFER,Group 1 EMU Buffer"
bitfld.long 0x00 31. " G1_EMPTY ,Group 1 FIFO Empty" "Not empty,Empty"
bitfld.long 0x00 16.--20. " G1CHID[4:0] ,Group 1 Channel ID" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,Channel 8,Channel 9,Channel 10,Channel 11,Channel 12,Channel 13,Channel 14,Channel 15,Channel 16,Channel 17,Channel 18,Channel 19,Channel 20,Channel 21,Channel 22,Channel 23,Channel 24,Channel 25,Channel 26,Channel 27,Channel 28,Channel 29,Channel 30,Channel 31"
textline " "
hexmask.long.word 0x00 0.--11. 1. " G1DR[11:0] ,Group 1 Digital Result"
else
group.long (0x4+0xF0)++0x3
line.long 0x0 "G1EMUBUFFER,Group 1 EMU Buffer"
bitfld.long 0x00 15. " G1_EMPTY ,Group 1 FIFO Empty" "Not empty,Empty"
bitfld.long 0x00 10.--14. " G1CHID[4:0] ,Group 1 Channel ID" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,Channel 8,Channel 9,Channel 10,Channel 11,Channel 12,Channel 13,Channel 14,Channel 15,Channel 16,Channel 17,Channel 18,Channel 19,Channel 20,Channel 21,Channel 22,Channel 23,Channel 24,Channel 25,Channel 26,Channel 27,Channel 28,Channel 29,Channel 30,Channel 31"
textline " "
hexmask.long.word 0x00 0.--9. 1. " G1DR[9:0] ,Group 1 Digital Result"
endif
width 18.
group.long (0x4+0x11C)++0x3
line.long 0x0 "G1SAMPDISEN,Group 1 Sampling Capacitor Discharge Mode"
hexmask.long.byte 0x00 8.--15. 1. " G1_SAMP_DIS_CYC[7:0] ,ADC Sampling Capacitor is Dicharged Cycles"
bitfld.long 0x00 0. " G1_SAMP_DIS_EN ,Sampling Capacitor Discharge Mode" "Disabled,Enabled"
group.long (0x4+0x168)++0x3
line.long 0x0 "G1FIFORESETCR,Group 1 FIFO Reset"
bitfld.long 0x00 0. " G1_FIFO_RESET ,Reset the ADC Group 1 FIFO" "No reset,Reset"
group.long (0x4+0x174)++0x3
line.long 0x0 "G1RAMADDR,Group 1 ADC RAM Pointer"
hexmask.long.word 0x00 0.--8. 1. " G1_RAM_ADDR ,Group 1 ADC RAM Pointer"
group.long (0x4+0x190)++0x03
line.long 0x00 "G1CHNSELMODECTRL, ADC Group 1 Channel Selection Mode Control Register"
bitfld.long 0x00 0.--3. " G1_ENH_CHNSEL_MODE_ENABLE , Enable Enhanced Channel Selection Mode" ",,,,,Disabled,,,,,Enabled,?..."
group.long (0x8+0x19C)++0x07
line.long 0x00 "G1CURRCOUNT, ADC Group 1 Current Count Register"
bitfld.long 0x00 0.--4. " G1_CURRENT_COUNT , Value For The Group 1 Conversions" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x04 "G1MAXCOUNT, ADC Group 1 Maximum Count Register"
bitfld.long 0x04 0.--4. " G1_MAX_COUNT , Value For The Group 1 Conversions" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
tree.end
width 13.
tree "Group 2 Registers"
group.long (0x8+0x10)++0x3
line.long 0x0 "G2MODECR,Group 2 MODE Control Register"
bitfld.long 0x00 16. " NO_RESET_ON_CHNSEL ,No Group 2 Results Memory Reset on New Channel Select" "Reset,No reset"
bitfld.long 0x00 8.--9. " G2_DATA_FMT ,Group 2 (Read) Data Format" "12 bit,10 bit,8 bit,?..."
textline " "
bitfld.long 0x00 5. " G2_CHID ,Channel ID Mode for the Group 2" "Forced to 0,ID of A/D channel"
bitfld.long 0x00 4. " OVR_G2_RAM_IGN ,Overrun Event Group RAM Ignore" "Not ignored,Ignored"
textline " "
bitfld.long 0x00 3. " G2_HW_TRIG ,Group 2 Hardware Triggered" "Software,Event"
bitfld.long 0x00 2. " G2_SBIT ,Group1 8-bit result mode" "10-bit,8-bit"
textline " "
bitfld.long 0x00 1. " G2_MODE ,Group 2 mode" "Single,Continuous"
bitfld.long 0x00 0. " FRZ_G1 ,Freeze Conversion Group 2" "Completed,Frozen"
group.long (0x8+0x1C)++0x3
line.long 0x0 "G2SRC,Group 2 Trigger Source Select"
bitfld.long 0x00 4. " G2_EDG_BOTH ,Group 2 Trigger Edge Polarity Select" "Defined edge,Any edge"
bitfld.long 0x00 3. " G2_EDG_SEL ,ADC Group 2 Trigger Edge Select" "High/low,Low/high"
textline " "
bitfld.long 0x00 0.--2. " G2SRC[2:0] ,Group 2 Trigger Source Select" "ADEVT,Internal,Internal,Internal,Internal,Internal,Internal,Internal"
group.long (0x8+0x28)++0x3
line.long 0x0 "G2INTENA,Group 2 Interrupt Enable"
bitfld.long 0x00 3. " G2_END_INT_EN ,Group 2 Conversion End Interrupt Enable" "Disabled,Enabled"
bitfld.long 0x00 1. " G2_OVR_INT_EN ,Group 2 Memory Overrun Interrupt Enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 0. " G2_THR_INT_EN ,Group 2 Memory Threshold Interrupt Enable" "Disabled,Enabled"
group.long (0x8+0x34)++0x3
line.long 0x0 "G2INTFLG,Group 2 Interrupt Flag"
eventfld.long 0x00 3. " G2_END ,Group 2 Conversion End" "Not converted,Converted"
rbitfld.long 0x00 2. " G2_MEM_EMPTY ,Group 2 FIFO Empty Status" "Not empty,Empty"
textline " "
rbitfld.long 0x00 1. " G2_MEM_OVERFLOW ,Group 2 Memory Overrun Flag" "No overrun,Overrun"
eventfld.long 0x00 0. " G2_THR_INT_FLAG ,Group 2 Threshold Interrupt Flag" "No interrupt,Interrupt"
group.long (0x8+0x40)++0x3
line.long 0x0 "G2INTCR,Group 2 Interrupt Threshold Counter"
hexmask.long.byte 0x00 9.--15. 1. " SIGN_EXTENSION ,Sign Extension"
hexmask.long.word 0x00 0.--8. 1. " G2_THR[8:0] ,Group 2 Interrupt Threshold Counter"
group.long (0x8+0x4C)++0x3
line.long 0x0 "G2DMACR,Group 2 DMA Control Register"
hexmask.long.word 0x00 16.--24. 1. " G2BLOCKS[8:0] ,Number of Group 2 Memory Buffers to be Transferred"
bitfld.long 0x00 3. " DMA_G2_END ,Group 2 Conversion End DMA Transfer Enable" "0,1"
textline " "
bitfld.long 0x00 2. " G2_BLK_XFER ,Group 2 Block DMA Transfer Enable" "Disabled,Enabled"
bitfld.long 0x00 0. " G2_DMA_EN ,Group 2 DMA Transfer Enable" "Disabled,Enabled"
group.long (0x8+0x60)++0x3
line.long 0x0 "G2SAMP,Group 2 Sample Window"
hexmask.long.word 0x00 0.--11. 1. " G2_ACQ ,Group 2 Acquisition Prescale Bits"
group.long (0x8+0x6C)++0x3
line.long 0x0 "G2SR,Group 2 Status Register"
rbitfld.long 0x00 3. " G2_MEM_EMPTY ,Group 2 Memory Empty" "Not empty,Empty"
rbitfld.long 0x00 2. " G2_BUSY ,Group 2 Conversion-Busy Flag" "Not active,Busy"
textline " "
rbitfld.long 0x00 1. " G2_STOP ,Group 2 Conversion Stopped Flag" "Not frozen,Frozen"
eventfld.long 0x00 0. " G2_END ,Group 2 Conversion-Ended Flag R/W" "Not completed,Completed"
group.long (0x8+0x78)++0x3
line.long 0x0 "G2SEL,Group 2 select register"
bitfld.long 0x00 23. " G2CHNSEL [23] ,A/D Group 2 Channel 23 Selection Bit" "Not converted,Converted"
bitfld.long 0x00 22. " [22] ,A/D Group 2 Channel 22 Selection Bit" "Not converted,Converted"
bitfld.long 0x00 21. " [21] ,A/D Group 2 Channel 21 Selection Bit" "Not converted,Converted"
bitfld.long 0x00 20. " [20] ,A/D Group 2 Channel 20 Selection Bit" "Not converted,Converted"
textline " "
bitfld.long 0x00 19. " [19] ,A/D Group 2 Channel 19 Selection Bit" "Not converted,Converted"
bitfld.long 0x00 18. " [18] ,A/D Group 2 Channel 18 Selection Bit" "Not converted,Converted"
bitfld.long 0x00 17. " [17] ,A/D Group 2 Channel 17 Selection Bit" "Not converted,Converted"
bitfld.long 0x00 16. " [16] ,A/D Group 2 Channel 16 Selection Bit" "Not converted,Converted"
textline " "
bitfld.long 0x00 15. " [15] ,A/D Group 2 Channel 15 Selection Bit" "Not converted,Converted"
bitfld.long 0x00 14. " [14] ,A/D Group 2 Channel 14 Selection Bit" "Not converted,Converted"
bitfld.long 0x00 13. " [13] ,A/D Group 2 Channel 13 Selection Bit" "Not converted,Converted"
bitfld.long 0x00 12. " [12] ,A/D Group 2 Channel 12 Selection Bit" "Not converted,Converted"
textline " "
bitfld.long 0x00 11. " [11] ,A/D Group 2 Channel 11 Selection Bit" "Not converted,Converted"
bitfld.long 0x00 10. " [10] ,A/D Group 2 Channel 10 Selection Bit" "Not converted,Converted"
bitfld.long 0x00 9. " [9] ,A/D Group 2 Channel 9 Selection Bit" "Not converted,Converted"
bitfld.long 0x00 8. " [8] ,A/D Group 2 Channel 8 Selection Bit" "Not converted,Converted"
textline " "
bitfld.long 0x00 7. " [7] ,A/D Group 2 Channel 7 Selection Bit" "Not converted,Converted"
bitfld.long 0x00 6. " [6] ,A/D Group 2 Channel 6 Selection Bit" "Not converted,Converted"
bitfld.long 0x00 5. " [5] ,A/D Group 2 Channel 5 Selection Bit" "Not converted,Converted"
bitfld.long 0x00 4. " [4] ,A/D Group 2 Channel 4 Selection Bit" "Not converted,Converted"
textline " "
bitfld.long 0x00 3. " [3] ,A/D Group 2 Channel 3 Selection Bit" "Not converted,Converted"
bitfld.long 0x00 2. " [2] ,A/D Group 2 Channel 2 Selection Bit" "Not converted,Converted"
bitfld.long 0x00 1. " [1] ,A/D Group 2 Channel 1 Selection Bit" "Not converted,Converted"
bitfld.long 0x00 0. " [0] ,A/D Group 2 Channel 0 Selection Bit" "Not converted,Converted"
hgroup.long (0x40+0x90)++0x3
hide.long 0x0 "G2BUFFER0,Group 2 Buffer 0"
in
hgroup.long (0x40+0x94)++0x3
hide.long 0x0 "G2BUFFER1,Group 2 Buffer 1"
in
hgroup.long (0x40+0x98)++0x3
hide.long 0x0 "G2BUFFER2,Group 2 Buffer 2"
in
hgroup.long (0x40+0x9C)++0x3
hide.long 0x0 "G2BUFFER3,Group 2 Buffer 3"
in
hgroup.long (0x40+0xA0)++0x3
hide.long 0x0 "G2BUFFER4,Group 2 Buffer 4"
in
hgroup.long (0x40+0xA4)++0x3
hide.long 0x0 "G2BUFFER5,Group 2 Buffer 5"
in
hgroup.long (0x40+0xA8)++0x3
hide.long 0x0 "G2BUFFER6,Group 2 Buffer 6"
in
hgroup.long (0x40+0xAC)++0x3
hide.long 0x0 "G2BUFFER7,Group 2 Buffer 7"
in
if ((d.l(ad:0xFFF7C000+0x04)&0x80000000)==0x80000000)
group.long (0x8+0xF0)++0x3
line.long 0x0 "G2EMUBUFFER,Group 2 EMU Buffer"
bitfld.long 0x00 31. " G2_EMPTY ,Group 2 FIFO Empty" "Not empty,Empty"
bitfld.long 0x00 16.--20. " G2CHID[4:0] ,Group 2 Channel ID" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,Channel 8,Channel 9,Channel 10,Channel 11,Channel 12,Channel 13,Channel 14,Channel 15,Channel 16,Channel 17,Channel 18,Channel 19,Channel 20,Channel 21,Channel 22,Channel 23,Channel 24,Channel 25,Channel 26,Channel 27,Channel 28,Channel 29,Channel 30,Channel 31"
textline " "
hexmask.long.word 0x00 0.--11. 1. " G2DR[11:0] ,Group 2 Digital Result"
else
group.long (0x8+0xF0)++0x3
line.long 0x0 "G2EMUBUFFER,Group 2 EMU Buffer"
bitfld.long 0x00 15. " G2_EMPTY ,Group 2 FIFO Empty" "Not empty,Empty"
bitfld.long 0x00 10.--14. " G2CHID[4:0] ,Group 2 Channel ID" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,Channel 8,Channel 9,Channel 10,Channel 11,Channel 12,Channel 13,Channel 14,Channel 15,Channel 16,Channel 17,Channel 18,Channel 19,Channel 20,Channel 21,Channel 22,Channel 23,Channel 24,Channel 25,Channel 26,Channel 27,Channel 28,Channel 29,Channel 30,Channel 31"
textline " "
hexmask.long.word 0x00 0.--9. 1. " G2DR[9:0] ,Group 2 Digital Result"
endif
width 18.
group.long (0x8+0x11C)++0x3
line.long 0x0 "G2SAMPDISEN,Group 2 Sampling Capacitor Discharge Mode"
hexmask.long.byte 0x00 8.--15. 1. " G2_SAMP_DIS_CYC[7:0] ,ADC Sampling Capacitor is Dicharged Cycles"
bitfld.long 0x00 0. " G2_SAMP_DIS_EN ,Sampling Capacitor Discharge Mode" "Disabled,Enabled"
group.long (0x8+0x168)++0x3
line.long 0x0 "G2FIFORESETCR,Group 2 FIFO Reset"
bitfld.long 0x00 0. " G2_FIFO_RESET ,Reset the ADC Group 2 FIFO" "No reset,Reset"
group.long (0x8+0x174)++0x3
line.long 0x0 "G2RAMADDR,Group 2 ADC RAM Pointer"
hexmask.long.word 0x00 0.--8. 1. " G2_RAM_ADDR ,Group 2 ADC RAM Pointer"
group.long (0x8+0x190)++0x03
line.long 0x00 "G2CHNSELMODECTRL, ADC Group 2 Channel Selection Mode Control Register"
bitfld.long 0x00 0.--3. " G2_ENH_CHNSEL_MODE_ENABLE , Enable Enhanced Channel Selection Mode" ",,,,,Disabled,,,,,Enabled,?..."
group.long (0x10+0x19C)++0x07
line.long 0x00 "G2CURRCOUNT, ADC Group 2 Current Count Register"
bitfld.long 0x00 0.--4. " G2_CURRENT_COUNT , Value For The Group 2 Conversions" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x04 "G2MAXCOUNT, ADC Group 2 Maximum Count Register"
bitfld.long 0x04 0.--4. " G2_MAX_COUNT , Value For The Group 2 Conversions" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
tree.end
width 10.
group.long 0x58++0x3
line.long 0x0 "BNDCR,Buffer Boundary Control Register"
hexmask.long.word 0x00 16.--24. 1. " BNDA[8:0] ,Buffer Boundary A"
hexmask.long.word 0x00 0.--8. 1. " BNDB[8:0] ,Buffer Boundary B"
group.long 0x5C++0x3
line.long 0x0 "BNDEND,Buffer End Boundary"
rbitfld.long 0x00 16. " BUF_INIT_ACTIVE ,Indicates the Status of the ADC RAM Intialization Process" "Not initialized,Initialized"
bitfld.long 0x00 0.--2. " BNDEND[2:0] ,Buffer End Boundary" "16 words,32 words,64 words,128 words,192 words,256 words,512 words,1024 words"
if ((d.l(ad:0xFFF7C000+0x04)&0x80000000)==0x80000000)
group.long 0x84++0x3
line.long 0x0 "CALR,Calibration Register"
hexmask.long.word 0x00 0.--11. 1. " CALR[11:0] ,Calibration Bits"
else
group.long 0x84++0x3
line.long 0x0 "CALR,Calibration Register"
hexmask.long.word 0x00 0.--9. 1. " CALR[9:0] ,Calibration Bits"
endif
rgroup.long 0x88++0x3
line.long 0x0 "SMSTATE,State Macine Current State"
bitfld.long 0x00 0.--3. " SMSTATE[3:0] ,ADC State Macine Current State" "Idle,Conv_EV,Conv_SW1,Conv_SW2,Conv_Cal,Start_EV,Start_SW1,Start_SW2,Start_Cal,Wait_EV,Wait_SW1,Wait_SW2,Wait_CAL,?..."
width 10.
rgroup.long 0x8C++0x3
line.long 0x0 "LASTCONV,Last Conversion"
bitfld.long 0x00 23. " IN [23] ,Digital input pin 23" "Low,High"
bitfld.long 0x00 22. " [22] ,Digital input pin 22" "Low,High"
bitfld.long 0x00 21. " [21] ,Digital input pin 21" "Low,High"
bitfld.long 0x00 20. " [20] ,Digital input pin 20" "Low,High"
bitfld.long 0x00 19. " [19] ,Digital input pin 19" "Low,High"
bitfld.long 0x00 18. " [18] ,Digital input pin 18" "Low,High"
bitfld.long 0x00 17. " [17] ,Digital input pin 17" "Low,High"
bitfld.long 0x00 16. " [16] ,Digital input pin 16" "Low,High"
textline " "
bitfld.long 0x00 15. " [15] ,Digital input pin 15" "Low,High"
bitfld.long 0x00 14. " [14] ,Digital input pin 14" "Low,High"
bitfld.long 0x00 13. " [13] ,Digital input pin 13" "Low,High"
bitfld.long 0x00 12. " [12] ,Digital input pin 12" "Low,High"
bitfld.long 0x00 11. " [11] ,Digital input pin 11" "Low,High"
bitfld.long 0x00 10. " [10] ,Digital input pin 10" "Low,High"
bitfld.long 0x00 9. " [9] ,Digital input pin 9" "Low,High"
bitfld.long 0x00 8. " [8] ,Digital input pin 8" "Low,High"
textline " "
bitfld.long 0x00 7. " [7] ,Digital input pin 7" "Low,High"
bitfld.long 0x00 6. " [6] ,Digital input pin 6" "Low,High"
bitfld.long 0x00 5. " [5] ,Digital input pin 5" "Low,High"
bitfld.long 0x00 4. " [4] ,Digital input pin 4" "Low,High"
bitfld.long 0x00 3. " [3] ,Digital input pin 3" "Low,High"
bitfld.long 0x00 2. " [2] ,Digital input pin 2" "Low,High"
bitfld.long 0x00 1. " [1] ,Digital input pin 1" "Low,High"
bitfld.long 0x00 0. " [0] ,Digital input pin 0" "Low,High"
tree "ADC Interrupt Control Registers"
width 17.
group.long 0x128++0x3
line.long 0x0 "MAGINTCR1,Magnitude Interrupt Control Register 1"
bitfld.long 0x00 26.--30. " MAG_CHID1[4:0] ,MAG CHID1 [4:0]" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,Channel 8,Channel 9,Channel 10,Channel 11,Channel 12,Channel 13,Channel 14,Channel 15,Channel 16,Channel 17,Channel 18,Channel 19,Channel 20,Channel 21,Channel 22,Channel 23,Channel 24,Channel 25,Channel 26,Channel 27,Channel 28,Channel 29,Channel 30,Channel 31"
hexmask.long.word 0x00 16.--25. 1. " MAG_THR1 ,Compare Value"
textline " "
bitfld.long 0x00 8.--12. " COMP_CHID1[4:0] ,COMP CHID1 [4:0]" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,Channel 8,Channel 9,Channel 10,Channel 11,Channel 12,Channel 13,Channel 14,Channel 15,Channel 16,Channel 17,Channel 18,Channel 19,Channel 20,Channel 21,Channel 22,Channel 23,Channel 24,Channel 25,Channel 26,Channel 27,Channel 28,Channel 29,Channel 30,Channel 31"
bitfld.long 0x00 1. " CHN/THR_COMP1 , Channel OR Threshold Comparison" "Treshold,Channel"
textline " "
bitfld.long 0x00 0. " CMP_GE/LT1 , Greater than or equal to OR Less than comparison operator" "Lower,Greater"
width 17.
group.long 0x12C++0x3
line.long 0x0 "MAGINT1MASK,Magnitude Interrupt Mask 1"
bitfld.long 0x00 9. " MAG_INT1_MASK [9] ,Comparison for the Magnitude Threshold Interrupt 1 Mask 9" "Not masked,Masked"
bitfld.long 0x00 8. " [8] ,Comparison for the Magnitude Threshold Interrupt 1 Mask 8" "Not masked,Masked"
bitfld.long 0x00 7. " [7] ,Comparison for the Magnitude Threshold Interrupt 1 Mask 7" "Not masked,Masked"
bitfld.long 0x00 6. " [6] ,Comparison for the Magnitude Threshold Interrupt 1 Mask 6" "Not masked,Masked"
bitfld.long 0x00 5. " [5] ,Comparison for the Magnitude Threshold Interrupt 1 Mask 5" "Not masked,Masked"
textline " "
bitfld.long 0x00 4. " [4] ,Comparison for the Magnitude Threshold Interrupt 1 Mask 4" "Not masked,Masked"
bitfld.long 0x00 3. " [3] ,Comparison for the Magnitude Threshold Interrupt 1 Mask 3" "Not masked,Masked"
bitfld.long 0x00 2. " [2] ,Comparison for the Magnitude Threshold Interrupt 1 Mask 2" "Not masked,Masked"
bitfld.long 0x00 1. " [1] ,Comparison for the Magnitude Threshold Interrupt 1 Mask 1" "Not masked,Masked"
bitfld.long 0x00 0. " [0] ,Comparison for the Magnitude Threshold Interrupt 1 Mask 0" "Not masked,Masked"
width 17.
group.long 0x130++0x3
line.long 0x0 "MAGINTCR2,Magnitude Interrupt Control Register 2"
bitfld.long 0x00 26.--30. " MAG_CHID2[4:0] ,MAG CHID2 [4:0]" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,Channel 8,Channel 9,Channel 10,Channel 11,Channel 12,Channel 13,Channel 14,Channel 15,Channel 16,Channel 17,Channel 18,Channel 19,Channel 20,Channel 21,Channel 22,Channel 23,Channel 24,Channel 25,Channel 26,Channel 27,Channel 28,Channel 29,Channel 30,Channel 31"
hexmask.long.word 0x00 16.--25. 1. " MAG_THR2 ,Compare Value"
textline " "
bitfld.long 0x00 8.--12. " COMP_CHID2[4:0] ,COMP CHID2 [4:0]" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,Channel 8,Channel 9,Channel 10,Channel 11,Channel 12,Channel 13,Channel 14,Channel 15,Channel 16,Channel 17,Channel 18,Channel 19,Channel 20,Channel 21,Channel 22,Channel 23,Channel 24,Channel 25,Channel 26,Channel 27,Channel 28,Channel 29,Channel 30,Channel 31"
bitfld.long 0x00 1. " CHN/THR_COMP2 , Channel OR Threshold Comparison" "Treshold,Channel"
textline " "
bitfld.long 0x00 0. " CMP_GE/LT2 , Greater than or equal to OR Less than comparison operator" "Lower,Greater"
width 17.
group.long 0x134++0x3
line.long 0x0 "MAGINT2MASK,Magnitude Interrupt Mask 2"
bitfld.long 0x00 9. " MAG_INT2_MASK [9] ,Comparison for the Magnitude Threshold Interrupt 2 Mask 9" "Not masked,Masked"
bitfld.long 0x00 8. " [8] ,Comparison for the Magnitude Threshold Interrupt 2 Mask 8" "Not masked,Masked"
bitfld.long 0x00 7. " [7] ,Comparison for the Magnitude Threshold Interrupt 2 Mask 7" "Not masked,Masked"
bitfld.long 0x00 6. " [6] ,Comparison for the Magnitude Threshold Interrupt 2 Mask 6" "Not masked,Masked"
bitfld.long 0x00 5. " [5] ,Comparison for the Magnitude Threshold Interrupt 2 Mask 5" "Not masked,Masked"
textline " "
bitfld.long 0x00 4. " [4] ,Comparison for the Magnitude Threshold Interrupt 2 Mask 4" "Not masked,Masked"
bitfld.long 0x00 3. " [3] ,Comparison for the Magnitude Threshold Interrupt 2 Mask 3" "Not masked,Masked"
bitfld.long 0x00 2. " [2] ,Comparison for the Magnitude Threshold Interrupt 2 Mask 2" "Not masked,Masked"
bitfld.long 0x00 1. " [1] ,Comparison for the Magnitude Threshold Interrupt 2 Mask 1" "Not masked,Masked"
bitfld.long 0x00 0. " [0] ,Comparison for the Magnitude Threshold Interrupt 2 Mask 0" "Not masked,Masked"
width 17.
group.long 0x138++0x3
line.long 0x0 "MAGINTCR3,Magnitude Interrupt Control Register 3"
bitfld.long 0x00 26.--30. " MAG_CHID3[4:0] ,MAG CHID3 [4:0]" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,Channel 8,Channel 9,Channel 10,Channel 11,Channel 12,Channel 13,Channel 14,Channel 15,Channel 16,Channel 17,Channel 18,Channel 19,Channel 20,Channel 21,Channel 22,Channel 23,Channel 24,Channel 25,Channel 26,Channel 27,Channel 28,Channel 29,Channel 30,Channel 31"
hexmask.long.word 0x00 16.--25. 1. " MAG_THR3 ,Compare Value"
textline " "
bitfld.long 0x00 8.--12. " COMP_CHID3[4:0] ,COMP CHID3 [4:0]" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,Channel 8,Channel 9,Channel 10,Channel 11,Channel 12,Channel 13,Channel 14,Channel 15,Channel 16,Channel 17,Channel 18,Channel 19,Channel 20,Channel 21,Channel 22,Channel 23,Channel 24,Channel 25,Channel 26,Channel 27,Channel 28,Channel 29,Channel 30,Channel 31"
bitfld.long 0x00 1. " CHN/THR_COMP3 , Channel OR Threshold Comparison" "Treshold,Channel"
textline " "
bitfld.long 0x00 0. " CMP_GE/LT3 , Greater than or equal to OR Less than comparison operator" "Lower,Greater"
width 17.
group.long 0x13C++0x3
line.long 0x0 "MAGINT3MASK,Magnitude Interrupt Mask 3"
bitfld.long 0x00 9. " MAG_INT3_MASK [9] ,Comparison for the Magnitude Threshold Interrupt 3 Mask 9" "Not masked,Masked"
bitfld.long 0x00 8. " [8] ,Comparison for the Magnitude Threshold Interrupt 3 Mask 8" "Not masked,Masked"
bitfld.long 0x00 7. " [7] ,Comparison for the Magnitude Threshold Interrupt 3 Mask 7" "Not masked,Masked"
bitfld.long 0x00 6. " [6] ,Comparison for the Magnitude Threshold Interrupt 3 Mask 6" "Not masked,Masked"
bitfld.long 0x00 5. " [5] ,Comparison for the Magnitude Threshold Interrupt 3 Mask 5" "Not masked,Masked"
textline " "
bitfld.long 0x00 4. " [4] ,Comparison for the Magnitude Threshold Interrupt 3 Mask 4" "Not masked,Masked"
bitfld.long 0x00 3. " [3] ,Comparison for the Magnitude Threshold Interrupt 3 Mask 3" "Not masked,Masked"
bitfld.long 0x00 2. " [2] ,Comparison for the Magnitude Threshold Interrupt 3 Mask 2" "Not masked,Masked"
bitfld.long 0x00 1. " [1] ,Comparison for the Magnitude Threshold Interrupt 3 Mask 1" "Not masked,Masked"
bitfld.long 0x00 0. " [0] ,Comparison for the Magnitude Threshold Interrupt 3 Mask 0" "Not masked,Masked"
width 17.
group.long 0x160++0x3
line.long 0x0 "MAGTHRINTFLG,Magnitude Threshold Interrupt Flag"
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " MAG_THR_INT2_set/clr ,Magnitude Threshold Interrupt Flag Bit[2]" "No interrupt,Interrupt"
textline " "
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " MAG_THR_INT1_set/clr ,Magnitude Threshold Interrupt Flag Bit[1]" "No interrupt,Interrupt"
textline " "
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " MAG_THR_INT0_set/clr ,Magnitude Threshold Interrupt Flag Bit[0]" "No interrupt,Interrupt"
group.long 0x164++0x3
line.long 0x0 "MAGTHRINTOFFSET,Magnitude Threshold Interrupt Offset Register"
bitfld.long 0x00 0.--3. " INT_OFF[3:0] ,Magnitude Threshold Interrupt Offset" "No interrupt,Interrupt 1,Interrupt 2,Interrupt 3,?..."
tree.end
width 13.
group.long 0x180++0x3
line.long 0x0 "PARCR,Parity Control Register"
bitfld.long 0x00 8. " TEST ,Parity Bits Map" "Not mapped,Mapped"
bitfld.long 0x00 0.--3. " PARITY_ENA[3:0] ,Enable/Disable Parity Checking" "Enabled,Enabled,Enabled,Enabled,Enabled,Disabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled"
rgroup.long 0x184++0x3
line.long 0x0 "PARADDR,Parity Address"
hexmask.long.word 0x00 2.--11. 0x4 " ERROR_ADDRESS ,ERROR ADDRESS"
group.long 0x188++0x03
line.long 0x00 "PWRUPDLYCTRL, ADC Power-Up Delay Control Register"
hexmask.long.word 0x00 0.--9. 1. " PWRUP_DLY , Number Of VCLK Cycles"
width 0xB
tree.end
tree "MibADC2"
base ad:0xFFF7C200
width 10.
group.long 0x00++0x3
line.long 0x0 "RSTCR,Reset Control Register"
bitfld.long 0x00 0. " RESET ,ADC Reset" "No reset,Reset"
group.long 0x04++0x3
line.long 0x0 "OPMODECR,Operating Mode Control Register"
bitfld.long 0x00 31. " 10/12_BIT ,Resolution of the ADC core" "10-bit,12-bit"
bitfld.long 0x00 24. " COS ,Continue on Suspend Enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 17.--20. " CHN_TEST_EN ,ADC Channel Test Enable" "Disabled,Disabled,Disabled,Disabled,Disabled,Enabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled"
bitfld.long 0x00 16. " RAM_TEST_EN ,ADC RAM Test Enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 8. " POWERDOWN ,ADC Internal Clocks Powerdown Mode" "Normal,Power-down"
bitfld.long 0x00 4. " NORMAL ,ADC Power Down When Idle" "Normal,Power-down"
textline " "
bitfld.long 0x00 0. " ADC_EN ,ADC Enable" "Disabled,Enabled"
group.long 0x08++0x3
line.long 0x0 "CLOCKCR,Clock Prescaler"
bitfld.long 0x00 0.--4. " PS[4:0] ,ADC Clock Prescaler" "1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles,16 cycles,17 cycles,18 cycles,19 cycles,20 cycles,21 cycles,22 cycles,23 cycles,24 cycles,25 cycles,26 cycles,27 cycles,28 cycles,29 cycles,30 cycles,31 cycles,32 cycles"
if (((d.l((ad:0xFFF7C200+0x0c)))&0x01000201)==0x00000001)
group.long (0x0c)++0x03
line.long 0x00 "CALCR,Calibration Conversion Register"
bitfld.long 0x00 24. " SELF_TEST ,Self-Test Enable" "Disabled,Enabled"
bitfld.long 0x00 16. " CAL_ST ,Calibration Conversion Start" "No effect/completed,Started"
textline " "
bitfld.long 0x00 9. " BRIDGE_EN ,Bridge Enable" "Midpoint,Full"
bitfld.long 0x00 8. " HILO ,Test and Reference Source Selection" "(AD_REFHI*R1+AD_REFLO*R2)/(R1+R2),(AD_REFLO*R1+AD_REFHI*R2)/(R1+R2)"
textline " "
bitfld.long 0x00 0. " CAL_EN ,Calibration Enable" "Disabled,Enabled"
elif (((d.l((ad:0xFFF7C200+0x0c)))&0x01000201)==0x01000000)
group.long (0x0c)++0x03
line.long 0x00 "CALCR,Calibration Conversion Register"
bitfld.long 0x00 24. " SELF_TEST ,Self-Test Enable" "Disabled,Enabled"
bitfld.long 0x00 16. " CAL_ST ,Calibration Conversion Start" "No effect/completed,Started"
textline " "
bitfld.long 0x00 9. " BRIDGE_EN ,Bridge Enable" "Midpoint,Full"
bitfld.long 0x00 8. " HILO ,Test and Reference Source Selection" "(AD_REFLO via R1)||(R2 to Vin),(AD_REFHI via R1)||(R2 to Vin)"
textline " "
bitfld.long 0x00 0. " CAL_EN ,Calibration Enable" "Disabled,Enabled"
elif (((d.l((ad:0xFFF7C200+0x0c)))&0x01000201)==0x00000201)
group.long (0x0c)++0x03
line.long 0x00 "CALCR,Calibration Conversion Register"
bitfld.long 0x00 24. " SELF_TEST ,Self-Test Enable" "Disabled,Enabled"
bitfld.long 0x00 16. " CAL_ST ,Calibration Conversion Start" "No effect/completed,Started"
textline " "
bitfld.long 0x00 9. " BRIDGE_EN ,Bridge Enable" "Midpoint,Full"
bitfld.long 0x00 8. " HILO ,Test and Reference Source Selection" "AD_REFLO,AD_REFHI"
textline " "
bitfld.long 0x00 0. " CAL_EN ,Calibration Enable" "Disabled,Enabled"
elif (((d.l((ad:0xFFF7C200+0x0c)))&0x01000201)==0x01000200)
group.long (0x0c)++0x03
line.long 0x00 "CALCR,Calibration Conversion Register"
bitfld.long 0x00 24. " SELF_TEST ,Self-Test Enable" "Disabled,Enabled"
bitfld.long 0x00 16. " CAL_ST ,Calibration Conversion Start" "No effect/completed,Started"
textline " "
bitfld.long 0x00 9. " BRIDGE_EN ,Bridge Enable" "Midpoint,Full"
bitfld.long 0x00 8. " HILO ,Test and Reference Source Selection" "(AD_REFLO via R1)||(R2 to Vin),(AD_REFHI via R1)||(R2 to Vin)"
textline " "
bitfld.long 0x00 0. " CAL_EN ,Calibration Enable" "Disabled,Enabled"
else
group.long (0x0c)++0x03
line.long 0x00 "CALCR,Calibration Conversion Register"
bitfld.long 0x00 24. " SELF_TEST ,Self-Test Enable" "Disabled,Enabled"
bitfld.long 0x00 16. " CAL_ST ,Calibration Conversion Start" "No effect/completed,Started"
textline " "
bitfld.long 0x00 9. " BRIDGE_EN ,Bridge Enable" "Midpoint,Full"
textline " "
bitfld.long 0x00 0. " CAL_EN ,Calibration Enable" "Disabled,Enabled"
endif
width 13.
tree "Event Group Registers"
group.long (0x0+0x10)++0x3
line.long 0x0 "EVMODECR,Event Group MODE Control Register"
bitfld.long 0x00 16. " NO_RESET_ON_CHNSEL ,No Event Group Results Memory Reset on New Channel Select" "Reset,No reset"
bitfld.long 0x00 8.--9. " EV_DATA_FMT ,Event Group (Read) Data Format" "12 bit,10 bit,8 bit,?..."
textline " "
bitfld.long 0x00 5. " EV_CHID ,Channel ID Mode for the Event Group" "Forced to 0,ID of A/D channel"
bitfld.long 0x00 4. " OVR_EV_RAM_IGN ,Overrun Event Group RAM Ignore" "Not ignored,Ignored"
textline " "
bitfld.long 0x00 2. " EV_8BIT ,Event Group 8-bit result mode" "10-bit,8-bit"
bitfld.long 0x00 1. " EV_MODE ,Event mode" "Single,Continuous"
textline " "
bitfld.long 0x00 0. " FRZ_EV ,Freeze conversion Event Group" "Completed,Frozen"
group.long (0x0+0x1C)++0x3
line.long 0x0 "EVSRC,Event Group Trigger Source Select"
bitfld.long 0x00 4. " EV_EDG_BOTH ,Event Group Trigger Edge Polarity Select" "Defined edge,Any edge"
bitfld.long 0x00 3. " EV_EDG_SEL ,ADC Event Group Trigger Edge Select" "High/low,Low/high"
textline " "
bitfld.long 0x00 0.--2. " EVSRC[2:0] ,Event Group Trigger Source Select" "ADEVT,Internal,Internal,Internal,Internal,Internal,Internal,Internal"
group.long (0x0+0x28)++0x3
line.long 0x0 "EVINTENA,Event Group Interrupt Enable"
bitfld.long 0x00 3. " EV_END_INT_EN ,Event Group Conversion End Interrupt Enable" "Disabled,Enabled"
bitfld.long 0x00 1. " EV_OVR_INT_EN ,Event Group Memory Overrun Interrupt Enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 0. " EV_THR_INT_EN ,Event Group Memory Threshold Interrupt Enable" "Disabled,Enabled"
group.long (0x0+0x34)++0x3
line.long 0x0 "EVINTFLG,Event Group Interrupt Flag"
eventfld.long 0x00 3. " EV_END ,Event Group Conversion End" "Not converted,Converted"
rbitfld.long 0x00 2. " EV_MEM_EMPTY ,Event Group FIFO Empty Status" "Not empty,Empty"
textline " "
rbitfld.long 0x00 1. " EV_MEM_OVERFLOW ,Event Group Memory Overrun Flag" "No overrun,Overrun"
eventfld.long 0x00 0. " EV_THR_INT_FLAG ,Event Group Threshold Interrupt Flag" "No interrupt,Interrupt"
group.long (0x0+0x40)++0x3
line.long 0x0 "EVINTCR,Event Group Interrupt Threshold Counter"
hexmask.long.byte 0x00 9.--15. 1. " SIGN_EXTENSION ,Sign Extension"
hexmask.long.word 0x00 0.--8. 1. " EV_THR[8:0] ,Event Group Interrupt Threshold Counter"
group.long (0x0+0x4C)++0x3
line.long 0x0 "EVDMACR,Event Group DMA Control Register"
hexmask.long.word 0x00 16.--24. 1. " EVBLOCKS[8:0] ,Number of Event Group Memory Buffers to be Transferred"
bitfld.long 0x00 3. " DMA_EV_END ,Event Group Conversion End DMA Transfer Enable" "0,1"
textline " "
bitfld.long 0x00 2. " EV_BLK_XFER ,Event Group Block DMA Transfer Enable" "Disabled,Enabled"
bitfld.long 0x00 0. " EV_DMA_EN ,Event Group DMA Transfer Enable" "Disabled,Enabled"
group.long (0x0+0x60)++0x3
line.long 0x0 "EVSAMP,Event Group Sample Window"
hexmask.long.word 0x00 0.--11. 1. " EV_ACQ ,Event Group Acquisition Prescale Bits"
group.long (0x0+0x6C)++0x3
line.long 0x0 "EVSR,Event Group Status Register"
rbitfld.long 0x00 3. " EV_MEM_EMPTY ,Event Group Memory Empty" "Not empty,Empty"
rbitfld.long 0x00 2. " EV_BUSY ,Event Group Conversion-Busy Flag" "Not active,Busy"
textline " "
rbitfld.long 0x00 1. " EV_STOP ,Event Group Conversion Stopped Flag" "Not frozen,Frozen"
eventfld.long 0x00 0. " EV_END ,Event Group Conversion-Ended Flag R/W" "Not completed,Completed"
group.long (0x0+0x78)++0x3
line.long 0x0 "EVSEL,Event Group select register"
bitfld.long 0x00 23. " EVCHNSEL [23] ,A/D Event Group Channel 23 Selection Bit" "Not converted,Converted"
bitfld.long 0x00 22. " [22] ,A/D Event Group Channel 22 Selection Bit" "Not converted,Converted"
bitfld.long 0x00 21. " [21] ,A/D Event Group Channel 21 Selection Bit" "Not converted,Converted"
bitfld.long 0x00 20. " [20] ,A/D Event Group Channel 20 Selection Bit" "Not converted,Converted"
textline " "
bitfld.long 0x00 19. " [19] ,A/D Event Group Channel 19 Selection Bit" "Not converted,Converted"
bitfld.long 0x00 18. " [18] ,A/D Event Group Channel 18 Selection Bit" "Not converted,Converted"
bitfld.long 0x00 17. " [17] ,A/D Event Group Channel 17 Selection Bit" "Not converted,Converted"
bitfld.long 0x00 16. " [16] ,A/D Event Group Channel 16 Selection Bit" "Not converted,Converted"
textline " "
bitfld.long 0x00 15. " [15] ,A/D Event Group Channel 15 Selection Bit" "Not converted,Converted"
bitfld.long 0x00 14. " [14] ,A/D Event Group Channel 14 Selection Bit" "Not converted,Converted"
bitfld.long 0x00 13. " [13] ,A/D Event Group Channel 13 Selection Bit" "Not converted,Converted"
bitfld.long 0x00 12. " [12] ,A/D Event Group Channel 12 Selection Bit" "Not converted,Converted"
textline " "
bitfld.long 0x00 11. " [11] ,A/D Event Group Channel 11 Selection Bit" "Not converted,Converted"
bitfld.long 0x00 10. " [10] ,A/D Event Group Channel 10 Selection Bit" "Not converted,Converted"
bitfld.long 0x00 9. " [9] ,A/D Event Group Channel 9 Selection Bit" "Not converted,Converted"
bitfld.long 0x00 8. " [8] ,A/D Event Group Channel 8 Selection Bit" "Not converted,Converted"
textline " "
bitfld.long 0x00 7. " [7] ,A/D Event Group Channel 7 Selection Bit" "Not converted,Converted"
bitfld.long 0x00 6. " [6] ,A/D Event Group Channel 6 Selection Bit" "Not converted,Converted"
bitfld.long 0x00 5. " [5] ,A/D Event Group Channel 5 Selection Bit" "Not converted,Converted"
bitfld.long 0x00 4. " [4] ,A/D Event Group Channel 4 Selection Bit" "Not converted,Converted"
textline " "
bitfld.long 0x00 3. " [3] ,A/D Event Group Channel 3 Selection Bit" "Not converted,Converted"
bitfld.long 0x00 2. " [2] ,A/D Event Group Channel 2 Selection Bit" "Not converted,Converted"
bitfld.long 0x00 1. " [1] ,A/D Event Group Channel 1 Selection Bit" "Not converted,Converted"
bitfld.long 0x00 0. " [0] ,A/D Event Group Channel 0 Selection Bit" "Not converted,Converted"
hgroup.long (0x0+0x90)++0x3
hide.long 0x0 "EVBUFFER0,Event Group Buffer 0"
in
hgroup.long (0x0+0x94)++0x3
hide.long 0x0 "EVBUFFER1,Event Group Buffer 1"
in
hgroup.long (0x0+0x98)++0x3
hide.long 0x0 "EVBUFFER2,Event Group Buffer 2"
in
hgroup.long (0x0+0x9C)++0x3
hide.long 0x0 "EVBUFFER3,Event Group Buffer 3"
in
hgroup.long (0x0+0xA0)++0x3
hide.long 0x0 "EVBUFFER4,Event Group Buffer 4"
in
hgroup.long (0x0+0xA4)++0x3
hide.long 0x0 "EVBUFFER5,Event Group Buffer 5"
in
hgroup.long (0x0+0xA8)++0x3
hide.long 0x0 "EVBUFFER6,Event Group Buffer 6"
in
hgroup.long (0x0+0xAC)++0x3
hide.long 0x0 "EVBUFFER7,Event Group Buffer 7"
in
if ((d.l(ad:0xFFF7C200+0x04)&0x80000000)==0x80000000)
group.long (0x0+0xF0)++0x3
line.long 0x0 "EVEMUBUFFER,Event Group EMU Buffer"
bitfld.long 0x00 31. " EV_EMPTY ,Event Group FIFO Empty" "Not empty,Empty"
bitfld.long 0x00 16.--20. " EVCHID[4:0] ,Event Group Channel ID" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,Channel 8,Channel 9,Channel 10,Channel 11,Channel 12,Channel 13,Channel 14,Channel 15,Channel 16,Channel 17,Channel 18,Channel 19,Channel 20,Channel 21,Channel 22,Channel 23,Channel 24,Channel 25,Channel 26,Channel 27,Channel 28,Channel 29,Channel 30,Channel 31"
textline " "
hexmask.long.word 0x00 0.--11. 1. " EVDR[11:0] ,Event Group Digital Result"
else
group.long (0x0+0xF0)++0x3
line.long 0x0 "EVEMUBUFFER,Event Group EMU Buffer"
bitfld.long 0x00 15. " EV_EMPTY ,Event Group FIFO Empty" "Not empty,Empty"
bitfld.long 0x00 10.--14. " EVCHID[4:0] ,Event Group Channel ID" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,Channel 8,Channel 9,Channel 10,Channel 11,Channel 12,Channel 13,Channel 14,Channel 15,Channel 16,Channel 17,Channel 18,Channel 19,Channel 20,Channel 21,Channel 22,Channel 23,Channel 24,Channel 25,Channel 26,Channel 27,Channel 28,Channel 29,Channel 30,Channel 31"
textline " "
hexmask.long.word 0x00 0.--9. 1. " EVDR[9:0] ,Event Group Digital Result"
endif
width 9.
tree "ADC ADEVT Pin Control Registers"
group.long 0xFC++0x3
line.long 0x0 "EVTDIR,Event Group pin direction selection"
bitfld.long 0x00 0. " EVT_DIR ,ADEVT Pin Direction Selection" "Input,Output"
if (((d.l((ad:0xFFF7C200+0xfc)))&0x01)==0x01)
group.long 0x100++0x3
line.long 0x0 "EVTOUT,Event Group pin data output"
bitfld.long 0x00 0. " EVT_OUT ,ADEVT Pin Data Output" "Low,High"
else
hgroup.long 0x100++0x3
hide.long 0x0 "EVTOUT,Event Group pin data output"
endif
rgroup.long 0x104++0x3
line.long 0x0 "EVTIN,Event Group pin input value"
bitfld.long 0x00 0. " EVT_IN ,ADEVT Pin Input Value" "Low,High"
group.long 0x108++0x3
line.long 0x0 "EVTSET,Event Group pin set"
setclrfld.long 0x00 0. 0x00 0. 0x04 0. " ADEVT_set/clr ,ADEVT Pin Set" "Low,High"
if ((((d.l((ad:0xFFF7C200+0xfc)))&0x01)==0x01)&&(((d.l((ad:0xFFF7C200+0x0100)))&0x01)==0x01))
group.long 0x110++0x3
line.long 0x0 "EVTPDR,Event Group pin open-drain enable"
bitfld.long 0x00 0. " ADEVT_PDR ,ADEVT Pin Open-Drain Enable" "Disabled,Enabled"
else
hgroup.long 0x110++0x3
hide.long 0x0 "EVTPDR,Event Group pin open-drain enable"
endif
if (((d.l((ad:0xFFF7C200+0xfc)))&0x01)==0x00)
group.long 0x114++0x3
line.long 0x0 "EVTPDIS,Event Group pin pull control enable"
bitfld.long 0x00 0. " ADEVT_PDIS ,ADEVT Pin Pull Control Enable" "Enabled,Disabled"
group.long 0x118++0x3
line.long 0x0 "EVTPSEL,Event Group pull select"
bitfld.long 0x00 0. " ADEVT_PSEL ,ADEVT Pull Select" "Pull-down,Pull-up"
else
hgroup.long 0x114++0x3
hide.long 0x0 "EVTPDIS,Event Group pin pull control enable"
hgroup.long 0x118++0x3
hide.long 0x0 "EVTPSEL,Event Group pull select"
endif
tree.end
width 18.
group.long (0x0+0x11C)++0x3
line.long 0x0 "EVSAMPDISEN,Event Group Sampling Capacitor Discharge Mode"
hexmask.long.byte 0x00 8.--15. 1. " EV_SAMP_DIS_CYC[7:0] ,ADC Sampling Capacitor is Dicharged Cycles"
bitfld.long 0x00 0. " EV_SAMP_DIS_EN ,Sampling Capacitor Discharge Mode" "Disabled,Enabled"
group.long (0x0+0x168)++0x3
line.long 0x0 "EVFIFORESETCR,Event Group FIFO Reset"
bitfld.long 0x00 0. " EV_FIFO_RESET ,Reset the ADC Event Group FIFO" "No reset,Reset"
group.long (0x0+0x174)++0x3
line.long 0x0 "EVRAMADDR,Event Group ADC RAM Pointer"
hexmask.long.word 0x00 0.--8. 1. " EV_RAM_ADDR ,Event Group ADC RAM Pointer"
group.long (0x0+0x190)++0x03
line.long 0x00 "EVCHNSELMODECTRL, ADC Event Group Channel Selection Mode Control Register"
bitfld.long 0x00 0.--3. " EV_ENH_CHNSEL_MODE_ENABLE , Enable Enhanced Channel Selection Mode" ",,,,,Disabled,,,,,Enabled,?..."
group.long (0x0+0x19C)++0x07
line.long 0x00 "EVCURRCOUNT, ADC Event Group Current Count Register"
bitfld.long 0x00 0.--4. " EV_CURRENT_COUNT , Value For The Event Group Conversions" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x04 "EVMAXCOUNT, ADC Event Group Maximum Count Register"
bitfld.long 0x04 0.--4. " EV_MAX_COUNT , Value For The Event Group Conversions" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
tree.end
width 13.
tree "Group 1 Registers"
group.long (0x4+0x10)++0x3
line.long 0x0 "G1MODECR,Group 1 MODE Control Register"
bitfld.long 0x00 16. " NO_RESET_ON_CHNSEL ,No Group 1 Results Memory Reset on New Channel Select" "Reset,No reset"
bitfld.long 0x00 8.--9. " G1_DATA_FMT ,Group 1 (Read) Data Format" "12 bit,10 bit,8 bit,?..."
textline " "
bitfld.long 0x00 5. " G1_CHID ,Channel ID Mode for the Group 1" "Forced to 0,ID of A/D channel"
bitfld.long 0x00 4. " OVR_G1_RAM_IGN ,Overrun Event Group RAM Ignore" "Not ignored,Ignored"
textline " "
bitfld.long 0x00 3. " G1_HW_TRIG ,Group 1 Hardware Triggered" "Software,Event"
bitfld.long 0x00 2. " G1_SBIT ,Group1 8-bit result mode" "10-bit,8-bit"
textline " "
bitfld.long 0x00 1. " G1_MODE ,Group 1 mode" "Single,Continuous"
bitfld.long 0x00 0. " FRZ_G1 ,Freeze Conversion Group 1" "Completed,Frozen"
group.long (0x4+0x1C)++0x3
line.long 0x0 "G1SRC,Group 1 Trigger Source Select"
bitfld.long 0x00 4. " G1_EDG_BOTH ,Group 1 Trigger Edge Polarity Select" "Defined edge,Any edge"
bitfld.long 0x00 3. " G1_EDG_SEL ,ADC Group 1 Trigger Edge Select" "High/low,Low/high"
textline " "
bitfld.long 0x00 0.--2. " G1SRC[2:0] ,Group 1 Trigger Source Select" "ADEVT,Internal,Internal,Internal,Internal,Internal,Internal,Internal"
group.long (0x4+0x28)++0x3
line.long 0x0 "G1INTENA,Group 1 Interrupt Enable"
bitfld.long 0x00 3. " G1_END_INT_EN ,Group 1 Conversion End Interrupt Enable" "Disabled,Enabled"
bitfld.long 0x00 1. " G1_OVR_INT_EN ,Group 1 Memory Overrun Interrupt Enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 0. " G1_THR_INT_EN ,Group 1 Memory Threshold Interrupt Enable" "Disabled,Enabled"
group.long (0x4+0x34)++0x3
line.long 0x0 "G1INTFLG,Group 1 Interrupt Flag"
eventfld.long 0x00 3. " G1_END ,Group 1 Conversion End" "Not converted,Converted"
rbitfld.long 0x00 2. " G1_MEM_EMPTY ,Group 1 FIFO Empty Status" "Not empty,Empty"
textline " "
rbitfld.long 0x00 1. " G1_MEM_OVERFLOW ,Group 1 Memory Overrun Flag" "No overrun,Overrun"
eventfld.long 0x00 0. " G1_THR_INT_FLAG ,Group 1 Threshold Interrupt Flag" "No interrupt,Interrupt"
group.long (0x4+0x40)++0x3
line.long 0x0 "G1INTCR,Group 1 Interrupt Threshold Counter"
hexmask.long.byte 0x00 9.--15. 1. " SIGN_EXTENSION ,Sign Extension"
hexmask.long.word 0x00 0.--8. 1. " G1_THR[8:0] ,Group 1 Interrupt Threshold Counter"
group.long (0x4+0x4C)++0x3
line.long 0x0 "G1DMACR,Group 1 DMA Control Register"
hexmask.long.word 0x00 16.--24. 1. " G1BLOCKS[8:0] ,Number of Group 1 Memory Buffers to be Transferred"
bitfld.long 0x00 3. " DMA_G1_END ,Group 1 Conversion End DMA Transfer Enable" "0,1"
textline " "
bitfld.long 0x00 2. " G1_BLK_XFER ,Group 1 Block DMA Transfer Enable" "Disabled,Enabled"
bitfld.long 0x00 0. " G1_DMA_EN ,Group 1 DMA Transfer Enable" "Disabled,Enabled"
group.long (0x4+0x60)++0x3
line.long 0x0 "G1SAMP,Group 1 Sample Window"
hexmask.long.word 0x00 0.--11. 1. " G1_ACQ ,Group 1 Acquisition Prescale Bits"
group.long (0x4+0x6C)++0x3
line.long 0x0 "G1SR,Group 1 Status Register"
rbitfld.long 0x00 3. " G1_MEM_EMPTY ,Group 1 Memory Empty" "Not empty,Empty"
rbitfld.long 0x00 2. " G1_BUSY ,Group 1 Conversion-Busy Flag" "Not active,Busy"
textline " "
rbitfld.long 0x00 1. " G1_STOP ,Group 1 Conversion Stopped Flag" "Not frozen,Frozen"
eventfld.long 0x00 0. " G1_END ,Group 1 Conversion-Ended Flag R/W" "Not completed,Completed"
group.long (0x4+0x78)++0x3
line.long 0x0 "G1SEL,Group 1 select register"
bitfld.long 0x00 23. " G1CHNSEL [23] ,A/D Group 1 Channel 23 Selection Bit" "Not converted,Converted"
bitfld.long 0x00 22. " [22] ,A/D Group 1 Channel 22 Selection Bit" "Not converted,Converted"
bitfld.long 0x00 21. " [21] ,A/D Group 1 Channel 21 Selection Bit" "Not converted,Converted"
bitfld.long 0x00 20. " [20] ,A/D Group 1 Channel 20 Selection Bit" "Not converted,Converted"
textline " "
bitfld.long 0x00 19. " [19] ,A/D Group 1 Channel 19 Selection Bit" "Not converted,Converted"
bitfld.long 0x00 18. " [18] ,A/D Group 1 Channel 18 Selection Bit" "Not converted,Converted"
bitfld.long 0x00 17. " [17] ,A/D Group 1 Channel 17 Selection Bit" "Not converted,Converted"
bitfld.long 0x00 16. " [16] ,A/D Group 1 Channel 16 Selection Bit" "Not converted,Converted"
textline " "
bitfld.long 0x00 15. " [15] ,A/D Group 1 Channel 15 Selection Bit" "Not converted,Converted"
bitfld.long 0x00 14. " [14] ,A/D Group 1 Channel 14 Selection Bit" "Not converted,Converted"
bitfld.long 0x00 13. " [13] ,A/D Group 1 Channel 13 Selection Bit" "Not converted,Converted"
bitfld.long 0x00 12. " [12] ,A/D Group 1 Channel 12 Selection Bit" "Not converted,Converted"
textline " "
bitfld.long 0x00 11. " [11] ,A/D Group 1 Channel 11 Selection Bit" "Not converted,Converted"
bitfld.long 0x00 10. " [10] ,A/D Group 1 Channel 10 Selection Bit" "Not converted,Converted"
bitfld.long 0x00 9. " [9] ,A/D Group 1 Channel 9 Selection Bit" "Not converted,Converted"
bitfld.long 0x00 8. " [8] ,A/D Group 1 Channel 8 Selection Bit" "Not converted,Converted"
textline " "
bitfld.long 0x00 7. " [7] ,A/D Group 1 Channel 7 Selection Bit" "Not converted,Converted"
bitfld.long 0x00 6. " [6] ,A/D Group 1 Channel 6 Selection Bit" "Not converted,Converted"
bitfld.long 0x00 5. " [5] ,A/D Group 1 Channel 5 Selection Bit" "Not converted,Converted"
bitfld.long 0x00 4. " [4] ,A/D Group 1 Channel 4 Selection Bit" "Not converted,Converted"
textline " "
bitfld.long 0x00 3. " [3] ,A/D Group 1 Channel 3 Selection Bit" "Not converted,Converted"
bitfld.long 0x00 2. " [2] ,A/D Group 1 Channel 2 Selection Bit" "Not converted,Converted"
bitfld.long 0x00 1. " [1] ,A/D Group 1 Channel 1 Selection Bit" "Not converted,Converted"
bitfld.long 0x00 0. " [0] ,A/D Group 1 Channel 0 Selection Bit" "Not converted,Converted"
hgroup.long (0x20+0x90)++0x3
hide.long 0x0 "G1BUFFER0,Group 1 Buffer 0"
in
hgroup.long (0x20+0x94)++0x3
hide.long 0x0 "G1BUFFER1,Group 1 Buffer 1"
in
hgroup.long (0x20+0x98)++0x3
hide.long 0x0 "G1BUFFER2,Group 1 Buffer 2"
in
hgroup.long (0x20+0x9C)++0x3
hide.long 0x0 "G1BUFFER3,Group 1 Buffer 3"
in
hgroup.long (0x20+0xA0)++0x3
hide.long 0x0 "G1BUFFER4,Group 1 Buffer 4"
in
hgroup.long (0x20+0xA4)++0x3
hide.long 0x0 "G1BUFFER5,Group 1 Buffer 5"
in
hgroup.long (0x20+0xA8)++0x3
hide.long 0x0 "G1BUFFER6,Group 1 Buffer 6"
in
hgroup.long (0x20+0xAC)++0x3
hide.long 0x0 "G1BUFFER7,Group 1 Buffer 7"
in
if ((d.l(ad:0xFFF7C200+0x04)&0x80000000)==0x80000000)
group.long (0x4+0xF0)++0x3
line.long 0x0 "G1EMUBUFFER,Group 1 EMU Buffer"
bitfld.long 0x00 31. " G1_EMPTY ,Group 1 FIFO Empty" "Not empty,Empty"
bitfld.long 0x00 16.--20. " G1CHID[4:0] ,Group 1 Channel ID" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,Channel 8,Channel 9,Channel 10,Channel 11,Channel 12,Channel 13,Channel 14,Channel 15,Channel 16,Channel 17,Channel 18,Channel 19,Channel 20,Channel 21,Channel 22,Channel 23,Channel 24,Channel 25,Channel 26,Channel 27,Channel 28,Channel 29,Channel 30,Channel 31"
textline " "
hexmask.long.word 0x00 0.--11. 1. " G1DR[11:0] ,Group 1 Digital Result"
else
group.long (0x4+0xF0)++0x3
line.long 0x0 "G1EMUBUFFER,Group 1 EMU Buffer"
bitfld.long 0x00 15. " G1_EMPTY ,Group 1 FIFO Empty" "Not empty,Empty"
bitfld.long 0x00 10.--14. " G1CHID[4:0] ,Group 1 Channel ID" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,Channel 8,Channel 9,Channel 10,Channel 11,Channel 12,Channel 13,Channel 14,Channel 15,Channel 16,Channel 17,Channel 18,Channel 19,Channel 20,Channel 21,Channel 22,Channel 23,Channel 24,Channel 25,Channel 26,Channel 27,Channel 28,Channel 29,Channel 30,Channel 31"
textline " "
hexmask.long.word 0x00 0.--9. 1. " G1DR[9:0] ,Group 1 Digital Result"
endif
width 18.
group.long (0x4+0x11C)++0x3
line.long 0x0 "G1SAMPDISEN,Group 1 Sampling Capacitor Discharge Mode"
hexmask.long.byte 0x00 8.--15. 1. " G1_SAMP_DIS_CYC[7:0] ,ADC Sampling Capacitor is Dicharged Cycles"
bitfld.long 0x00 0. " G1_SAMP_DIS_EN ,Sampling Capacitor Discharge Mode" "Disabled,Enabled"
group.long (0x4+0x168)++0x3
line.long 0x0 "G1FIFORESETCR,Group 1 FIFO Reset"
bitfld.long 0x00 0. " G1_FIFO_RESET ,Reset the ADC Group 1 FIFO" "No reset,Reset"
group.long (0x4+0x174)++0x3
line.long 0x0 "G1RAMADDR,Group 1 ADC RAM Pointer"
hexmask.long.word 0x00 0.--8. 1. " G1_RAM_ADDR ,Group 1 ADC RAM Pointer"
group.long (0x4+0x190)++0x03
line.long 0x00 "G1CHNSELMODECTRL, ADC Group 1 Channel Selection Mode Control Register"
bitfld.long 0x00 0.--3. " G1_ENH_CHNSEL_MODE_ENABLE , Enable Enhanced Channel Selection Mode" ",,,,,Disabled,,,,,Enabled,?..."
group.long (0x8+0x19C)++0x07
line.long 0x00 "G1CURRCOUNT, ADC Group 1 Current Count Register"
bitfld.long 0x00 0.--4. " G1_CURRENT_COUNT , Value For The Group 1 Conversions" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x04 "G1MAXCOUNT, ADC Group 1 Maximum Count Register"
bitfld.long 0x04 0.--4. " G1_MAX_COUNT , Value For The Group 1 Conversions" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
tree.end
width 13.
tree "Group 2 Registers"
group.long (0x8+0x10)++0x3
line.long 0x0 "G2MODECR,Group 2 MODE Control Register"
bitfld.long 0x00 16. " NO_RESET_ON_CHNSEL ,No Group 2 Results Memory Reset on New Channel Select" "Reset,No reset"
bitfld.long 0x00 8.--9. " G2_DATA_FMT ,Group 2 (Read) Data Format" "12 bit,10 bit,8 bit,?..."
textline " "
bitfld.long 0x00 5. " G2_CHID ,Channel ID Mode for the Group 2" "Forced to 0,ID of A/D channel"
bitfld.long 0x00 4. " OVR_G2_RAM_IGN ,Overrun Event Group RAM Ignore" "Not ignored,Ignored"
textline " "
bitfld.long 0x00 3. " G2_HW_TRIG ,Group 2 Hardware Triggered" "Software,Event"
bitfld.long 0x00 2. " G2_SBIT ,Group1 8-bit result mode" "10-bit,8-bit"
textline " "
bitfld.long 0x00 1. " G2_MODE ,Group 2 mode" "Single,Continuous"
bitfld.long 0x00 0. " FRZ_G1 ,Freeze Conversion Group 2" "Completed,Frozen"
group.long (0x8+0x1C)++0x3
line.long 0x0 "G2SRC,Group 2 Trigger Source Select"
bitfld.long 0x00 4. " G2_EDG_BOTH ,Group 2 Trigger Edge Polarity Select" "Defined edge,Any edge"
bitfld.long 0x00 3. " G2_EDG_SEL ,ADC Group 2 Trigger Edge Select" "High/low,Low/high"
textline " "
bitfld.long 0x00 0.--2. " G2SRC[2:0] ,Group 2 Trigger Source Select" "ADEVT,Internal,Internal,Internal,Internal,Internal,Internal,Internal"
group.long (0x8+0x28)++0x3
line.long 0x0 "G2INTENA,Group 2 Interrupt Enable"
bitfld.long 0x00 3. " G2_END_INT_EN ,Group 2 Conversion End Interrupt Enable" "Disabled,Enabled"
bitfld.long 0x00 1. " G2_OVR_INT_EN ,Group 2 Memory Overrun Interrupt Enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 0. " G2_THR_INT_EN ,Group 2 Memory Threshold Interrupt Enable" "Disabled,Enabled"
group.long (0x8+0x34)++0x3
line.long 0x0 "G2INTFLG,Group 2 Interrupt Flag"
eventfld.long 0x00 3. " G2_END ,Group 2 Conversion End" "Not converted,Converted"
rbitfld.long 0x00 2. " G2_MEM_EMPTY ,Group 2 FIFO Empty Status" "Not empty,Empty"
textline " "
rbitfld.long 0x00 1. " G2_MEM_OVERFLOW ,Group 2 Memory Overrun Flag" "No overrun,Overrun"
eventfld.long 0x00 0. " G2_THR_INT_FLAG ,Group 2 Threshold Interrupt Flag" "No interrupt,Interrupt"
group.long (0x8+0x40)++0x3
line.long 0x0 "G2INTCR,Group 2 Interrupt Threshold Counter"
hexmask.long.byte 0x00 9.--15. 1. " SIGN_EXTENSION ,Sign Extension"
hexmask.long.word 0x00 0.--8. 1. " G2_THR[8:0] ,Group 2 Interrupt Threshold Counter"
group.long (0x8+0x4C)++0x3
line.long 0x0 "G2DMACR,Group 2 DMA Control Register"
hexmask.long.word 0x00 16.--24. 1. " G2BLOCKS[8:0] ,Number of Group 2 Memory Buffers to be Transferred"
bitfld.long 0x00 3. " DMA_G2_END ,Group 2 Conversion End DMA Transfer Enable" "0,1"
textline " "
bitfld.long 0x00 2. " G2_BLK_XFER ,Group 2 Block DMA Transfer Enable" "Disabled,Enabled"
bitfld.long 0x00 0. " G2_DMA_EN ,Group 2 DMA Transfer Enable" "Disabled,Enabled"
group.long (0x8+0x60)++0x3
line.long 0x0 "G2SAMP,Group 2 Sample Window"
hexmask.long.word 0x00 0.--11. 1. " G2_ACQ ,Group 2 Acquisition Prescale Bits"
group.long (0x8+0x6C)++0x3
line.long 0x0 "G2SR,Group 2 Status Register"
rbitfld.long 0x00 3. " G2_MEM_EMPTY ,Group 2 Memory Empty" "Not empty,Empty"
rbitfld.long 0x00 2. " G2_BUSY ,Group 2 Conversion-Busy Flag" "Not active,Busy"
textline " "
rbitfld.long 0x00 1. " G2_STOP ,Group 2 Conversion Stopped Flag" "Not frozen,Frozen"
eventfld.long 0x00 0. " G2_END ,Group 2 Conversion-Ended Flag R/W" "Not completed,Completed"
group.long (0x8+0x78)++0x3
line.long 0x0 "G2SEL,Group 2 select register"
bitfld.long 0x00 23. " G2CHNSEL [23] ,A/D Group 2 Channel 23 Selection Bit" "Not converted,Converted"
bitfld.long 0x00 22. " [22] ,A/D Group 2 Channel 22 Selection Bit" "Not converted,Converted"
bitfld.long 0x00 21. " [21] ,A/D Group 2 Channel 21 Selection Bit" "Not converted,Converted"
bitfld.long 0x00 20. " [20] ,A/D Group 2 Channel 20 Selection Bit" "Not converted,Converted"
textline " "
bitfld.long 0x00 19. " [19] ,A/D Group 2 Channel 19 Selection Bit" "Not converted,Converted"
bitfld.long 0x00 18. " [18] ,A/D Group 2 Channel 18 Selection Bit" "Not converted,Converted"
bitfld.long 0x00 17. " [17] ,A/D Group 2 Channel 17 Selection Bit" "Not converted,Converted"
bitfld.long 0x00 16. " [16] ,A/D Group 2 Channel 16 Selection Bit" "Not converted,Converted"
textline " "
bitfld.long 0x00 15. " [15] ,A/D Group 2 Channel 15 Selection Bit" "Not converted,Converted"
bitfld.long 0x00 14. " [14] ,A/D Group 2 Channel 14 Selection Bit" "Not converted,Converted"
bitfld.long 0x00 13. " [13] ,A/D Group 2 Channel 13 Selection Bit" "Not converted,Converted"
bitfld.long 0x00 12. " [12] ,A/D Group 2 Channel 12 Selection Bit" "Not converted,Converted"
textline " "
bitfld.long 0x00 11. " [11] ,A/D Group 2 Channel 11 Selection Bit" "Not converted,Converted"
bitfld.long 0x00 10. " [10] ,A/D Group 2 Channel 10 Selection Bit" "Not converted,Converted"
bitfld.long 0x00 9. " [9] ,A/D Group 2 Channel 9 Selection Bit" "Not converted,Converted"
bitfld.long 0x00 8. " [8] ,A/D Group 2 Channel 8 Selection Bit" "Not converted,Converted"
textline " "
bitfld.long 0x00 7. " [7] ,A/D Group 2 Channel 7 Selection Bit" "Not converted,Converted"
bitfld.long 0x00 6. " [6] ,A/D Group 2 Channel 6 Selection Bit" "Not converted,Converted"
bitfld.long 0x00 5. " [5] ,A/D Group 2 Channel 5 Selection Bit" "Not converted,Converted"
bitfld.long 0x00 4. " [4] ,A/D Group 2 Channel 4 Selection Bit" "Not converted,Converted"
textline " "
bitfld.long 0x00 3. " [3] ,A/D Group 2 Channel 3 Selection Bit" "Not converted,Converted"
bitfld.long 0x00 2. " [2] ,A/D Group 2 Channel 2 Selection Bit" "Not converted,Converted"
bitfld.long 0x00 1. " [1] ,A/D Group 2 Channel 1 Selection Bit" "Not converted,Converted"
bitfld.long 0x00 0. " [0] ,A/D Group 2 Channel 0 Selection Bit" "Not converted,Converted"
hgroup.long (0x40+0x90)++0x3
hide.long 0x0 "G2BUFFER0,Group 2 Buffer 0"
in
hgroup.long (0x40+0x94)++0x3
hide.long 0x0 "G2BUFFER1,Group 2 Buffer 1"
in
hgroup.long (0x40+0x98)++0x3
hide.long 0x0 "G2BUFFER2,Group 2 Buffer 2"
in
hgroup.long (0x40+0x9C)++0x3
hide.long 0x0 "G2BUFFER3,Group 2 Buffer 3"
in
hgroup.long (0x40+0xA0)++0x3
hide.long 0x0 "G2BUFFER4,Group 2 Buffer 4"
in
hgroup.long (0x40+0xA4)++0x3
hide.long 0x0 "G2BUFFER5,Group 2 Buffer 5"
in
hgroup.long (0x40+0xA8)++0x3
hide.long 0x0 "G2BUFFER6,Group 2 Buffer 6"
in
hgroup.long (0x40+0xAC)++0x3
hide.long 0x0 "G2BUFFER7,Group 2 Buffer 7"
in
if ((d.l(ad:0xFFF7C200+0x04)&0x80000000)==0x80000000)
group.long (0x8+0xF0)++0x3
line.long 0x0 "G2EMUBUFFER,Group 2 EMU Buffer"
bitfld.long 0x00 31. " G2_EMPTY ,Group 2 FIFO Empty" "Not empty,Empty"
bitfld.long 0x00 16.--20. " G2CHID[4:0] ,Group 2 Channel ID" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,Channel 8,Channel 9,Channel 10,Channel 11,Channel 12,Channel 13,Channel 14,Channel 15,Channel 16,Channel 17,Channel 18,Channel 19,Channel 20,Channel 21,Channel 22,Channel 23,Channel 24,Channel 25,Channel 26,Channel 27,Channel 28,Channel 29,Channel 30,Channel 31"
textline " "
hexmask.long.word 0x00 0.--11. 1. " G2DR[11:0] ,Group 2 Digital Result"
else
group.long (0x8+0xF0)++0x3
line.long 0x0 "G2EMUBUFFER,Group 2 EMU Buffer"
bitfld.long 0x00 15. " G2_EMPTY ,Group 2 FIFO Empty" "Not empty,Empty"
bitfld.long 0x00 10.--14. " G2CHID[4:0] ,Group 2 Channel ID" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,Channel 8,Channel 9,Channel 10,Channel 11,Channel 12,Channel 13,Channel 14,Channel 15,Channel 16,Channel 17,Channel 18,Channel 19,Channel 20,Channel 21,Channel 22,Channel 23,Channel 24,Channel 25,Channel 26,Channel 27,Channel 28,Channel 29,Channel 30,Channel 31"
textline " "
hexmask.long.word 0x00 0.--9. 1. " G2DR[9:0] ,Group 2 Digital Result"
endif
width 18.
group.long (0x8+0x11C)++0x3
line.long 0x0 "G2SAMPDISEN,Group 2 Sampling Capacitor Discharge Mode"
hexmask.long.byte 0x00 8.--15. 1. " G2_SAMP_DIS_CYC[7:0] ,ADC Sampling Capacitor is Dicharged Cycles"
bitfld.long 0x00 0. " G2_SAMP_DIS_EN ,Sampling Capacitor Discharge Mode" "Disabled,Enabled"
group.long (0x8+0x168)++0x3
line.long 0x0 "G2FIFORESETCR,Group 2 FIFO Reset"
bitfld.long 0x00 0. " G2_FIFO_RESET ,Reset the ADC Group 2 FIFO" "No reset,Reset"
group.long (0x8+0x174)++0x3
line.long 0x0 "G2RAMADDR,Group 2 ADC RAM Pointer"
hexmask.long.word 0x00 0.--8. 1. " G2_RAM_ADDR ,Group 2 ADC RAM Pointer"
group.long (0x8+0x190)++0x03
line.long 0x00 "G2CHNSELMODECTRL, ADC Group 2 Channel Selection Mode Control Register"
bitfld.long 0x00 0.--3. " G2_ENH_CHNSEL_MODE_ENABLE , Enable Enhanced Channel Selection Mode" ",,,,,Disabled,,,,,Enabled,?..."
group.long (0x10+0x19C)++0x07
line.long 0x00 "G2CURRCOUNT, ADC Group 2 Current Count Register"
bitfld.long 0x00 0.--4. " G2_CURRENT_COUNT , Value For The Group 2 Conversions" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x04 "G2MAXCOUNT, ADC Group 2 Maximum Count Register"
bitfld.long 0x04 0.--4. " G2_MAX_COUNT , Value For The Group 2 Conversions" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
tree.end
width 10.
group.long 0x58++0x3
line.long 0x0 "BNDCR,Buffer Boundary Control Register"
hexmask.long.word 0x00 16.--24. 1. " BNDA[8:0] ,Buffer Boundary A"
hexmask.long.word 0x00 0.--8. 1. " BNDB[8:0] ,Buffer Boundary B"
group.long 0x5C++0x3
line.long 0x0 "BNDEND,Buffer End Boundary"
rbitfld.long 0x00 16. " BUF_INIT_ACTIVE ,Indicates the Status of the ADC RAM Intialization Process" "Not initialized,Initialized"
bitfld.long 0x00 0.--2. " BNDEND[2:0] ,Buffer End Boundary" "16 words,32 words,64 words,128 words,192 words,256 words,512 words,1024 words"
if ((d.l(ad:0xFFF7C200+0x04)&0x80000000)==0x80000000)
group.long 0x84++0x3
line.long 0x0 "CALR,Calibration Register"
hexmask.long.word 0x00 0.--11. 1. " CALR[11:0] ,Calibration Bits"
else
group.long 0x84++0x3
line.long 0x0 "CALR,Calibration Register"
hexmask.long.word 0x00 0.--9. 1. " CALR[9:0] ,Calibration Bits"
endif
rgroup.long 0x88++0x3
line.long 0x0 "SMSTATE,State Macine Current State"
bitfld.long 0x00 0.--3. " SMSTATE[3:0] ,ADC State Macine Current State" "Idle,Conv_EV,Conv_SW1,Conv_SW2,Conv_Cal,Start_EV,Start_SW1,Start_SW2,Start_Cal,Wait_EV,Wait_SW1,Wait_SW2,Wait_CAL,?..."
width 10.
rgroup.long 0x8C++0x3
line.long 0x0 "LASTCONV,Last Conversion"
bitfld.long 0x00 23. " IN [23] ,Digital input pin 23" "Low,High"
bitfld.long 0x00 22. " [22] ,Digital input pin 22" "Low,High"
bitfld.long 0x00 21. " [21] ,Digital input pin 21" "Low,High"
bitfld.long 0x00 20. " [20] ,Digital input pin 20" "Low,High"
bitfld.long 0x00 19. " [19] ,Digital input pin 19" "Low,High"
bitfld.long 0x00 18. " [18] ,Digital input pin 18" "Low,High"
bitfld.long 0x00 17. " [17] ,Digital input pin 17" "Low,High"
bitfld.long 0x00 16. " [16] ,Digital input pin 16" "Low,High"
textline " "
bitfld.long 0x00 15. " [15] ,Digital input pin 15" "Low,High"
bitfld.long 0x00 14. " [14] ,Digital input pin 14" "Low,High"
bitfld.long 0x00 13. " [13] ,Digital input pin 13" "Low,High"
bitfld.long 0x00 12. " [12] ,Digital input pin 12" "Low,High"
bitfld.long 0x00 11. " [11] ,Digital input pin 11" "Low,High"
bitfld.long 0x00 10. " [10] ,Digital input pin 10" "Low,High"
bitfld.long 0x00 9. " [9] ,Digital input pin 9" "Low,High"
bitfld.long 0x00 8. " [8] ,Digital input pin 8" "Low,High"
textline " "
bitfld.long 0x00 7. " [7] ,Digital input pin 7" "Low,High"
bitfld.long 0x00 6. " [6] ,Digital input pin 6" "Low,High"
bitfld.long 0x00 5. " [5] ,Digital input pin 5" "Low,High"
bitfld.long 0x00 4. " [4] ,Digital input pin 4" "Low,High"
bitfld.long 0x00 3. " [3] ,Digital input pin 3" "Low,High"
bitfld.long 0x00 2. " [2] ,Digital input pin 2" "Low,High"
bitfld.long 0x00 1. " [1] ,Digital input pin 1" "Low,High"
bitfld.long 0x00 0. " [0] ,Digital input pin 0" "Low,High"
tree "ADC Interrupt Control Registers"
width 17.
group.long 0x128++0x3
line.long 0x0 "MAGINTCR1,Magnitude Interrupt Control Register 1"
bitfld.long 0x00 26.--30. " MAG_CHID1[4:0] ,MAG CHID1 [4:0]" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,Channel 8,Channel 9,Channel 10,Channel 11,Channel 12,Channel 13,Channel 14,Channel 15,Channel 16,Channel 17,Channel 18,Channel 19,Channel 20,Channel 21,Channel 22,Channel 23,Channel 24,Channel 25,Channel 26,Channel 27,Channel 28,Channel 29,Channel 30,Channel 31"
hexmask.long.word 0x00 16.--25. 1. " MAG_THR1 ,Compare Value"
textline " "
bitfld.long 0x00 8.--12. " COMP_CHID1[4:0] ,COMP CHID1 [4:0]" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,Channel 8,Channel 9,Channel 10,Channel 11,Channel 12,Channel 13,Channel 14,Channel 15,Channel 16,Channel 17,Channel 18,Channel 19,Channel 20,Channel 21,Channel 22,Channel 23,Channel 24,Channel 25,Channel 26,Channel 27,Channel 28,Channel 29,Channel 30,Channel 31"
bitfld.long 0x00 1. " CHN/THR_COMP1 , Channel OR Threshold Comparison" "Treshold,Channel"
textline " "
bitfld.long 0x00 0. " CMP_GE/LT1 , Greater than or equal to OR Less than comparison operator" "Lower,Greater"
width 17.
group.long 0x12C++0x3
line.long 0x0 "MAGINT1MASK,Magnitude Interrupt Mask 1"
bitfld.long 0x00 9. " MAG_INT1_MASK [9] ,Comparison for the Magnitude Threshold Interrupt 1 Mask 9" "Not masked,Masked"
bitfld.long 0x00 8. " [8] ,Comparison for the Magnitude Threshold Interrupt 1 Mask 8" "Not masked,Masked"
bitfld.long 0x00 7. " [7] ,Comparison for the Magnitude Threshold Interrupt 1 Mask 7" "Not masked,Masked"
bitfld.long 0x00 6. " [6] ,Comparison for the Magnitude Threshold Interrupt 1 Mask 6" "Not masked,Masked"
bitfld.long 0x00 5. " [5] ,Comparison for the Magnitude Threshold Interrupt 1 Mask 5" "Not masked,Masked"
textline " "
bitfld.long 0x00 4. " [4] ,Comparison for the Magnitude Threshold Interrupt 1 Mask 4" "Not masked,Masked"
bitfld.long 0x00 3. " [3] ,Comparison for the Magnitude Threshold Interrupt 1 Mask 3" "Not masked,Masked"
bitfld.long 0x00 2. " [2] ,Comparison for the Magnitude Threshold Interrupt 1 Mask 2" "Not masked,Masked"
bitfld.long 0x00 1. " [1] ,Comparison for the Magnitude Threshold Interrupt 1 Mask 1" "Not masked,Masked"
bitfld.long 0x00 0. " [0] ,Comparison for the Magnitude Threshold Interrupt 1 Mask 0" "Not masked,Masked"
width 17.
group.long 0x130++0x3
line.long 0x0 "MAGINTCR2,Magnitude Interrupt Control Register 2"
bitfld.long 0x00 26.--30. " MAG_CHID2[4:0] ,MAG CHID2 [4:0]" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,Channel 8,Channel 9,Channel 10,Channel 11,Channel 12,Channel 13,Channel 14,Channel 15,Channel 16,Channel 17,Channel 18,Channel 19,Channel 20,Channel 21,Channel 22,Channel 23,Channel 24,Channel 25,Channel 26,Channel 27,Channel 28,Channel 29,Channel 30,Channel 31"
hexmask.long.word 0x00 16.--25. 1. " MAG_THR2 ,Compare Value"
textline " "
bitfld.long 0x00 8.--12. " COMP_CHID2[4:0] ,COMP CHID2 [4:0]" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,Channel 8,Channel 9,Channel 10,Channel 11,Channel 12,Channel 13,Channel 14,Channel 15,Channel 16,Channel 17,Channel 18,Channel 19,Channel 20,Channel 21,Channel 22,Channel 23,Channel 24,Channel 25,Channel 26,Channel 27,Channel 28,Channel 29,Channel 30,Channel 31"
bitfld.long 0x00 1. " CHN/THR_COMP2 , Channel OR Threshold Comparison" "Treshold,Channel"
textline " "
bitfld.long 0x00 0. " CMP_GE/LT2 , Greater than or equal to OR Less than comparison operator" "Lower,Greater"
width 17.
group.long 0x134++0x3
line.long 0x0 "MAGINT2MASK,Magnitude Interrupt Mask 2"
bitfld.long 0x00 9. " MAG_INT2_MASK [9] ,Comparison for the Magnitude Threshold Interrupt 2 Mask 9" "Not masked,Masked"
bitfld.long 0x00 8. " [8] ,Comparison for the Magnitude Threshold Interrupt 2 Mask 8" "Not masked,Masked"
bitfld.long 0x00 7. " [7] ,Comparison for the Magnitude Threshold Interrupt 2 Mask 7" "Not masked,Masked"
bitfld.long 0x00 6. " [6] ,Comparison for the Magnitude Threshold Interrupt 2 Mask 6" "Not masked,Masked"
bitfld.long 0x00 5. " [5] ,Comparison for the Magnitude Threshold Interrupt 2 Mask 5" "Not masked,Masked"
textline " "
bitfld.long 0x00 4. " [4] ,Comparison for the Magnitude Threshold Interrupt 2 Mask 4" "Not masked,Masked"
bitfld.long 0x00 3. " [3] ,Comparison for the Magnitude Threshold Interrupt 2 Mask 3" "Not masked,Masked"
bitfld.long 0x00 2. " [2] ,Comparison for the Magnitude Threshold Interrupt 2 Mask 2" "Not masked,Masked"
bitfld.long 0x00 1. " [1] ,Comparison for the Magnitude Threshold Interrupt 2 Mask 1" "Not masked,Masked"
bitfld.long 0x00 0. " [0] ,Comparison for the Magnitude Threshold Interrupt 2 Mask 0" "Not masked,Masked"
width 17.
group.long 0x138++0x3
line.long 0x0 "MAGINTCR3,Magnitude Interrupt Control Register 3"
bitfld.long 0x00 26.--30. " MAG_CHID3[4:0] ,MAG CHID3 [4:0]" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,Channel 8,Channel 9,Channel 10,Channel 11,Channel 12,Channel 13,Channel 14,Channel 15,Channel 16,Channel 17,Channel 18,Channel 19,Channel 20,Channel 21,Channel 22,Channel 23,Channel 24,Channel 25,Channel 26,Channel 27,Channel 28,Channel 29,Channel 30,Channel 31"
hexmask.long.word 0x00 16.--25. 1. " MAG_THR3 ,Compare Value"
textline " "
bitfld.long 0x00 8.--12. " COMP_CHID3[4:0] ,COMP CHID3 [4:0]" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,Channel 8,Channel 9,Channel 10,Channel 11,Channel 12,Channel 13,Channel 14,Channel 15,Channel 16,Channel 17,Channel 18,Channel 19,Channel 20,Channel 21,Channel 22,Channel 23,Channel 24,Channel 25,Channel 26,Channel 27,Channel 28,Channel 29,Channel 30,Channel 31"
bitfld.long 0x00 1. " CHN/THR_COMP3 , Channel OR Threshold Comparison" "Treshold,Channel"
textline " "
bitfld.long 0x00 0. " CMP_GE/LT3 , Greater than or equal to OR Less than comparison operator" "Lower,Greater"
width 17.
group.long 0x13C++0x3
line.long 0x0 "MAGINT3MASK,Magnitude Interrupt Mask 3"
bitfld.long 0x00 9. " MAG_INT3_MASK [9] ,Comparison for the Magnitude Threshold Interrupt 3 Mask 9" "Not masked,Masked"
bitfld.long 0x00 8. " [8] ,Comparison for the Magnitude Threshold Interrupt 3 Mask 8" "Not masked,Masked"
bitfld.long 0x00 7. " [7] ,Comparison for the Magnitude Threshold Interrupt 3 Mask 7" "Not masked,Masked"
bitfld.long 0x00 6. " [6] ,Comparison for the Magnitude Threshold Interrupt 3 Mask 6" "Not masked,Masked"
bitfld.long 0x00 5. " [5] ,Comparison for the Magnitude Threshold Interrupt 3 Mask 5" "Not masked,Masked"
textline " "
bitfld.long 0x00 4. " [4] ,Comparison for the Magnitude Threshold Interrupt 3 Mask 4" "Not masked,Masked"
bitfld.long 0x00 3. " [3] ,Comparison for the Magnitude Threshold Interrupt 3 Mask 3" "Not masked,Masked"
bitfld.long 0x00 2. " [2] ,Comparison for the Magnitude Threshold Interrupt 3 Mask 2" "Not masked,Masked"
bitfld.long 0x00 1. " [1] ,Comparison for the Magnitude Threshold Interrupt 3 Mask 1" "Not masked,Masked"
bitfld.long 0x00 0. " [0] ,Comparison for the Magnitude Threshold Interrupt 3 Mask 0" "Not masked,Masked"
width 17.
group.long 0x160++0x3
line.long 0x0 "MAGTHRINTFLG,Magnitude Threshold Interrupt Flag"
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " MAG_THR_INT2_set/clr ,Magnitude Threshold Interrupt Flag Bit[2]" "No interrupt,Interrupt"
textline " "
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " MAG_THR_INT1_set/clr ,Magnitude Threshold Interrupt Flag Bit[1]" "No interrupt,Interrupt"
textline " "
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " MAG_THR_INT0_set/clr ,Magnitude Threshold Interrupt Flag Bit[0]" "No interrupt,Interrupt"
group.long 0x164++0x3
line.long 0x0 "MAGTHRINTOFFSET,Magnitude Threshold Interrupt Offset Register"
bitfld.long 0x00 0.--3. " INT_OFF[3:0] ,Magnitude Threshold Interrupt Offset" "No interrupt,Interrupt 1,Interrupt 2,Interrupt 3,?..."
tree.end
width 13.
group.long 0x180++0x3
line.long 0x0 "PARCR,Parity Control Register"
bitfld.long 0x00 8. " TEST ,Parity Bits Map" "Not mapped,Mapped"
bitfld.long 0x00 0.--3. " PARITY_ENA[3:0] ,Enable/Disable Parity Checking" "Enabled,Enabled,Enabled,Enabled,Enabled,Disabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled"
rgroup.long 0x184++0x3
line.long 0x0 "PARADDR,Parity Address"
hexmask.long.word 0x00 2.--11. 0x4 " ERROR_ADDRESS ,ERROR ADDRESS"
group.long 0x188++0x03
line.long 0x00 "PWRUPDLYCTRL, ADC Power-Up Delay Control Register"
hexmask.long.word 0x00 0.--9. 1. " PWRUP_DLY , Number Of VCLK Cycles"
width 0xB
tree.end
tree.end
tree.open "N2HET (High-End Timer Module)"
tree "N2HET1"
base ad:0xFFF7B800
width 11.
if ((d.l(ad:0xFFF7B800+0x00)&0x01)==0x01)
group.long 0x00++0x03
line.long 0x00 "GCR,Global Control Register"
bitfld.long 0x00 24. " HET_PIN_ENA ,NHET pin enable" "Disabled,Enabled"
bitfld.long 0x00 21.--22. " MP ,Master priority" "Lower,Higher,Round robin,?..."
bitfld.long 0x00 18. " PPF ,Protect program fields" "Unprotected,Protected"
textline " "
bitfld.long 0x00 17. " IS ,Ignore suspend" "Not ignored,Ignored"
bitfld.long 0x00 16. " CMS ,Clk_master/slave" "Slave,Master"
bitfld.long 0x00 0. " TO ,Turn on/off" "Off,On"
else
group.long 0x00++0x03
line.long 0x00 "GCR,Global Control Register"
bitfld.long 0x00 24. " HET_PIN_ENA ,NHET pin enable" "Disabled,Enabled"
bitfld.long 0x00 21.--22. " MP ,Master priority" "Lower,Higher,Round robin,?..."
bitfld.long 0x00 18. " PPF ,Protect program fields" "Unprotected,Unprotected"
textline " "
bitfld.long 0x00 17. " IS ,Ignore suspend" "Not ignored,Ignored"
bitfld.long 0x00 16. " CMS ,Clk_master/slave" "Slave,Master"
bitfld.long 0x00 0. " TO ,Turn on/off" "Off,On"
endif
group.long 0x04++0x03
line.long 0x00 "PFR,Prescaler Factor Register"
bitfld.long 0x00 8.--10. " LRPFC ,Loop resolution Pre-scale factor code" "1,2,4,8,16,32,64,128"
bitfld.long 0x00 0.--5. " HRPFC ,HR prescale factor code" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64"
rgroup.long 0x08++0x03
line.long 0x00 "ADDR,Current Address Register"
hexmask.long.word 0x00 0.--8. 1. " HETADDR[8:0] ,NHET current address"
hgroup.long 0x0C++0x03
hide.long 0x00 "OFF1,Offset Level 1 Register"
in
hgroup.long 0x10++0x03
hide.long 0x00 "OFF2,Offset Level 2 Register"
in
textline " "
group.long 0x14++0x03
line.long 0x00 "INTENA,Interrupt Enable Register"
setclrfld.long 0x00 31. 0x00 31. 0x04 31. " HETINTENA_SET/CLR_[31] ,Interrupt enable set pin 31" "Disabled,Enabled"
setclrfld.long 0x00 30. 0x00 30. 0x04 30. " [30] ,Interrupt enable set pin 30" "Disabled,Enabled"
setclrfld.long 0x00 29. 0x00 29. 0x04 29. " [29] ,Interrupt enable set pin 29" "Disabled,Enabled"
setclrfld.long 0x00 28. 0x00 28. 0x04 28. " [28] ,Interrupt enable set pin 28" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 27. 0x00 27. 0x04 27. " [27] ,Interrupt enable set pin 27" "Disabled,Enabled"
setclrfld.long 0x00 26. 0x00 26. 0x04 26. " [26] ,Interrupt enable set pin 26" "Disabled,Enabled"
setclrfld.long 0x00 25. 0x00 25. 0x04 25. " [25] ,Interrupt enable set pin 25" "Disabled,Enabled"
setclrfld.long 0x00 24. 0x00 24. 0x04 24. " [24] ,Interrupt enable set pin 24" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 23. 0x00 23. 0x04 23. " [23] ,Interrupt enable set pin 23" "Disabled,Enabled"
setclrfld.long 0x00 22. 0x00 22. 0x04 22. " [22] ,Interrupt enable set pin 22" "Disabled,Enabled"
setclrfld.long 0x00 21. 0x00 21. 0x04 21. " [21] ,Interrupt enable set pin 21" "Disabled,Enabled"
setclrfld.long 0x00 20. 0x00 20. 0x04 20. " [20] ,Interrupt enable set pin 20" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 19. 0x00 19. 0x04 19. " [19] ,Interrupt enable set pin 19" "Disabled,Enabled"
setclrfld.long 0x00 18. 0x00 18. 0x04 18. " [18] ,Interrupt enable set pin 18" "Disabled,Enabled"
setclrfld.long 0x00 17. 0x00 17. 0x04 17. " [17] ,Interrupt enable set pin 17" "Disabled,Enabled"
setclrfld.long 0x00 16. 0x00 16. 0x04 16. " [16] ,Interrupt enable set pin 16" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 15. 0x00 15. 0x04 15. " [15] ,Interrupt enable set pin 15" "Disabled,Enabled"
setclrfld.long 0x00 14. 0x00 14. 0x04 14. " [14] ,Interrupt enable set pin 14" "Disabled,Enabled"
setclrfld.long 0x00 13. 0x00 13. 0x04 13. " [13] ,Interrupt enable set pin 13" "Disabled,Enabled"
setclrfld.long 0x00 12. 0x00 12. 0x04 12. " [12] ,Interrupt enable set pin 12" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 11. 0x00 11. 0x04 11. " [11] ,Interrupt enable set pin 11" "Disabled,Enabled"
setclrfld.long 0x00 10. 0x00 10. 0x04 10. " [10] ,Interrupt enable set pin 10" "Disabled,Enabled"
setclrfld.long 0x00 9. 0x00 9. 0x04 9. " [9] ,Interrupt enable set pin 9" "Disabled,Enabled"
setclrfld.long 0x00 8. 0x00 8. 0x04 8. " [8] ,Interrupt enable set pin 8" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 7. 0x00 7. 0x04 7. " [7] ,Interrupt enable set pin 7" "Disabled,Enabled"
setclrfld.long 0x00 6. 0x00 6. 0x04 6. " [6] ,Interrupt enable set pin 6" "Disabled,Enabled"
setclrfld.long 0x00 5. 0x00 5. 0x04 5. " [5] ,Interrupt enable set pin 5" "Disabled,Enabled"
setclrfld.long 0x00 4. 0x00 4. 0x04 4. " [4] ,Interrupt enable set pin 4" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 3. 0x00 3. 0x04 3. " [3] ,Interrupt enable set pin 3" "Disabled,Enabled"
setclrfld.long 0x00 2. 0x00 2. 0x04 2. " [2] ,Interrupt enable set pin 2" "Disabled,Enabled"
setclrfld.long 0x00 1. 0x00 1. 0x04 1. " [1] ,Interrupt enable set pin 1" "Disabled,Enabled"
setclrfld.long 0x00 0. 0x00 0. 0x04 0. " [0] ,Interrupt enable set pin 0" "Disabled,Enabled"
textline " "
group.long 0x1C++0x03
line.long 0x00 "EXC1,Exception Control Register 1"
bitfld.long 0x00 24. " APCNT_OVRFL_ENA ,APCNT overflow enable" "Disabled,Enabled"
bitfld.long 0x00 16. " APCNT_UNDRFL_ENA ,APCNT underflow enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 8. " PRGM_OVRFL_ENA ,Program overflow enable" "Disabled,Enabled"
bitfld.long 0x00 2. " APCNT_OVRFL_ENA_PRY ,Apcnt_ovrfl_ena priority" "Level 2,Level 1"
textline " "
bitfld.long 0x00 1. " APCNT_UNDRFL_ENA_PRY ,Apcnt_undrfl_ena priority" "Level 2,Level 1"
bitfld.long 0x00 0. " PRGM_OVRFL_ENA_PRY ,Prgm_ovrfl_ena priority" "Level 2,Level 1"
group.long 0x20++0x03
line.long 0x00 "EXC2,Exception Control Register 2"
eventfld.long 0x00 8. " DEBUG_STATUS_FLG ,Debug_status flag" "No NHET,NHET"
eventfld.long 0x00 2. " APCNT_OVRFL_FLG ,APCNT overflow flag" "Not occurred,Occurred"
textline " "
eventfld.long 0x00 1. " APCNT_UNDRFL_FLG ,APCNT underflow flag" "Not occurred,Occurred"
eventfld.long 0x00 0. " PRGM_OVERFL_FLG ,Program overflow flag" "Not occurred,Occurred"
textline " "
group.long 0x24++0x03
line.long 0x00 "PRY,Interrupt Priority Register"
bitfld.long 0x00 31. " HETPRY[31] ,HET priority level bit[31]" "Level 2,Level 1"
bitfld.long 0x00 30. " [30] ,HET priority level bit[30]" "Level 2,Level 1"
bitfld.long 0x00 29. " [29] ,HET priority level bit[29]" "Level 2,Level 1"
bitfld.long 0x00 28. " [28] ,HET priority level bit[28]" "Level 2,Level 1"
textline " "
bitfld.long 0x00 27. " [27] ,HET priority level bit[27]" "Level 2,Level 1"
bitfld.long 0x00 26. " [26] ,HET priority level bit[26]" "Level 2,Level 1"
bitfld.long 0x00 25. " [25] ,HET priority level bit[25]" "Level 2,Level 1"
bitfld.long 0x00 24. " [24] ,HET priority level bit[24]" "Level 2,Level 1"
textline " "
bitfld.long 0x00 23. " [23] ,HET priority level bit[23]" "Level 2,Level 1"
bitfld.long 0x00 22. " [22] ,HET priority level bit[22]" "Level 2,Level 1"
bitfld.long 0x00 21. " [21] ,HET priority level bit[21]" "Level 2,Level 1"
bitfld.long 0x00 20. " [20] ,HET priority level bit[20]" "Level 2,Level 1"
textline " "
bitfld.long 0x00 19. " [19] ,HET priority level bit[19]" "Level 2,Level 1"
bitfld.long 0x00 18. " [18] ,HET priority level bit[18]" "Level 2,Level 1"
bitfld.long 0x00 17. " [17] ,HET priority level bit[17]" "Level 2,Level 1"
bitfld.long 0x00 16. " [16] ,HET priority level bit[16]" "Level 2,Level 1"
textline " "
bitfld.long 0x00 15. " [15] ,HET priority level bit[15]" "Level 2,Level 1"
bitfld.long 0x00 14. " [14] ,HET priority level bit[14]" "Level 2,Level 1"
bitfld.long 0x00 13. " [13] ,HET priority level bit[13]" "Level 2,Level 1"
bitfld.long 0x00 12. " [12] ,HET priority level bit[12]" "Level 2,Level 1"
textline " "
bitfld.long 0x00 11. " [11] ,HET priority level bit[11]" "Level 2,Level 1"
bitfld.long 0x00 10. " [10] ,HET priority level bit[10]" "Level 2,Level 1"
bitfld.long 0x00 9. " [9] ,HET priority level bit[9]" "Level 2,Level 1"
bitfld.long 0x00 8. " [8] ,HET priority level bit[8]" "Level 2,Level 1"
textline " "
bitfld.long 0x00 7. " [7] ,HET priority level bit[7]" "Level 2,Level 1"
bitfld.long 0x00 6. " [6] ,HET priority level bit[6]" "Level 2,Level 1"
bitfld.long 0x00 5. " [5] ,HET priority level bit[5]" "Level 2,Level 1"
bitfld.long 0x00 4. " [4] ,HET priority level bit[4]" "Level 2,Level 1"
textline " "
bitfld.long 0x00 3. " [3] ,HET priority level bit[3]" "Level 2,Level 1"
bitfld.long 0x00 2. " [2] ,HET priority level bit[2]" "Level 2,Level 1"
bitfld.long 0x00 1. " [1] ,HET priority level bit[1]" "Level 2,Level 1"
bitfld.long 0x00 0. " [0] ,HET priority level bit[0]" "Level 2,Level 1"
textline " "
group.long 0x28++0x03
line.long 0x00 "FLG,Interrupt Flag Register"
eventfld.long 0x00 31. " HETFLAG_[31] ,Interrupt flag register bit[31]" "No interrupt,Interrupt"
eventfld.long 0x00 30. " [30] ,Interrupt flag register bit[30]" "No interrupt,Interrupt"
eventfld.long 0x00 29. " [29] ,Interrupt flag register bit[29]" "No interrupt,Interrupt"
eventfld.long 0x00 28. " [28] ,Interrupt flag register bit[28]" "No interrupt,Interrupt"
textline " "
eventfld.long 0x00 27. " [27] ,Interrupt flag register bit[27]" "No interrupt,Interrupt"
eventfld.long 0x00 26. " [26] ,Interrupt flag register bit[26]" "No interrupt,Interrupt"
eventfld.long 0x00 25. " [25] ,Interrupt flag register bit[25]" "No interrupt,Interrupt"
eventfld.long 0x00 24. " [24] ,Interrupt flag register bit[24]" "No interrupt,Interrupt"
textline " "
eventfld.long 0x00 23. " [23] ,Interrupt flag register bit[23]" "No interrupt,Interrupt"
eventfld.long 0x00 22. " [22] ,Interrupt flag register bit[22]" "No interrupt,Interrupt"
eventfld.long 0x00 21. " [21] ,Interrupt flag register bit[21]" "No interrupt,Interrupt"
eventfld.long 0x00 20. " [20] ,Interrupt flag register bit[20]" "No interrupt,Interrupt"
textline " "
eventfld.long 0x00 19. " [19] ,Interrupt flag register bit[19]" "No interrupt,Interrupt"
eventfld.long 0x00 18. " [18] ,Interrupt flag register bit[18]" "No interrupt,Interrupt"
eventfld.long 0x00 17. " [17] ,Interrupt flag register bit[17]" "No interrupt,Interrupt"
eventfld.long 0x00 16. " [16] ,Interrupt flag register bit[16]" "No interrupt,Interrupt"
textline " "
eventfld.long 0x00 15. " [15] ,Interrupt flag register bit[15]" "No interrupt,Interrupt"
eventfld.long 0x00 14. " [14] ,Interrupt flag register bit[14]" "No interrupt,Interrupt"
eventfld.long 0x00 13. " [13] ,Interrupt flag register bit[13]" "No interrupt,Interrupt"
eventfld.long 0x00 12. " [12] ,Interrupt flag register bit[12]" "No interrupt,Interrupt"
textline " "
eventfld.long 0x00 11. " [11] ,Interrupt flag register bit[11]" "No interrupt,Interrupt"
eventfld.long 0x00 10. " [10] ,Interrupt flag register bit[10]" "No interrupt,Interrupt"
eventfld.long 0x00 9. " [9] ,Interrupt flag register bit[9]" "No interrupt,Interrupt"
eventfld.long 0x00 8. " [8] ,Interrupt flag register bit[8]" "No interrupt,Interrupt"
textline " "
eventfld.long 0x00 7. " [7] ,Interrupt flag register bit[7]" "No interrupt,Interrupt"
eventfld.long 0x00 6. " [6] ,Interrupt flag register bit[6]" "No interrupt,Interrupt"
eventfld.long 0x00 5. " [5] ,Interrupt flag register bit[5]" "No interrupt,Interrupt"
eventfld.long 0x00 4. " [4] ,Interrupt flag register bit[4]" "No interrupt,Interrupt"
textline " "
eventfld.long 0x00 3. " [3] ,Interrupt flag register bit[3]" "No interrupt,Interrupt"
eventfld.long 0x00 2. " [2] ,Interrupt flag register bit[2]" "No interrupt,Interrupt"
eventfld.long 0x00 1. " [1] ,Interrupt flag register bit[1]" "No interrupt,Interrupt"
eventfld.long 0x00 0. " [0] ,Interrupt flag register bit[0]" "No interrupt,Interrupt"
textline " "
sif (CPU()==("TMS570LS2124-PGE")||CPU()==("TMS570LS2124-ZWT")||CPU()==("TMS570LS2134-PGE")||CPU()==("TMS570LS2134-ZWT")||CPU()==("TMS570LS3134-PGE")||CPU()==("TMS570LS3134-ZWT")||CPU()==("TMS570LS3135-PGE")||CPU()==("TMS570LS3135-ZWT")||CPU()==("TMS570LS3136")||CPU()==("TMS570LS3137-PGE")||CPU()==("TMS570LS3137-ZWT")||CPU()==("TMS570LS30336")||CPU()==("TMS570LS2126")||CPU()==("TMS570LS2127")||CPU()==("TMS570LS2136")||CPU()==("TMS570LS2137")||CPU()==("TMS570LS2125-PGE")||CPU()==("TMS570LS2125-ZWT")||CPU()==("TMS570LS2135-PGE")||CPU()==("TMS570LS2135-ZWT")||CPU()==("RM48L950")||CPU()=="RM48L952-PGE"||CPU()=="RM48L950-PGE"||CPU()=="RM48L950-ZWT"||CPU()=="RM48L940-ZWT"||CPU()=="RM48L940-PGE"||CPU()=="RM48L930-ZWT"||CPU()=="RM48L930-PGE"||CPU()=="RM48L750-ZWT"||CPU()=="RM48L750-PGE"||CPU()=="RM48L740-ZWT"||CPU()=="RM48L740-PGE"||CPU()=="RM48L730-ZWT"||CPU()=="RM48L730-PGE"||CPU()=="RM48L550-PGE"||CPU()=="RM48L540-ZWT"||CPU()=="RM48L540-PGE"||CPU()=="RM48L530-ZWT"||CPU()=="RM48L530-PGE"||CPU()=="RM46L852-PGE"||CPU()=="RM46L852-ZWT"||CPU()=="RM46L850-PGE"||CPU()=="RM46L850-ZWT"||CPU()=="RM46L840-ZWT"||CPU()=="RM46L840-PGE"||CPU()=="RM46L830-ZWT"||CPU()=="RM46L830-PGE"||CPU()=="RM46L450-ZWT"||CPU()=="RM46L450-PGE"||CPU()=="RM46L440-ZWT"||CPU()=="RM46L440-PGE"||CPU()=="RM46L430-ZWT"||CPU()=="RM46L430-PGE"||CPU()=="RM42L432"||CPU()=="TMS570LC4357"||CPU()==("TMS570LS0332")||CPU()==("TMS570LS0432")||CPUIS("TMS570LS1114*")||CPUIS("TMS570LS1115*")||CPUIS("TMS570LS1224*")||CPUIS("TMS570LS1225*")||CPUIS("TMS570LS1227*")||cpu()=="RM57L843-ZWT")
group.long 0x2C++0x03
line.long 0x00 "HETAND,And Share Control Register"
bitfld.long 0x00 15. " AND_SHARE[31/30] ,AND share enable 31/30" "Not AND-shared,And-shared"
bitfld.long 0x00 14. " [29/28] ,AND share enable 29/28" "Not AND-shared,And-shared"
bitfld.long 0x00 13. " [27/26] ,AND share enable 27/26" "Not AND-shared,And-shared"
bitfld.long 0x00 12. " [25/24] ,AND share enable 25/24" "Not AND-shared,And-shared"
textline " "
bitfld.long 0x00 11. " [23/22] ,AND share enable 23/22" "Not AND-shared,And-shared"
bitfld.long 0x00 10. " [21/20] ,AND share enable 21/20" "Not AND-shared,And-shared"
bitfld.long 0x00 9. " [19/18] ,AND share enable 19/18" "Not AND-shared,And-shared"
bitfld.long 0x00 8. " [17/16] ,AND share enable 17/16" "Not AND-shared,And-shared"
textline " "
bitfld.long 0x00 7. " [15/14] ,AND share enable 15/14" "Not AND-shared,And-shared"
bitfld.long 0x00 6. " [13/12] ,AND share enable 13/12" "Not AND-shared,And-shared"
bitfld.long 0x00 5. " [11/10] ,AND share enable 11/10" "Not AND-shared,And-shared"
bitfld.long 0x00 4. " [9/8] ,AND share enable 9/8" "Not AND-shared,And-shared"
textline " "
bitfld.long 0x00 3. " [7/6] ,AND share enable 7/6" "Not AND-shared,And-shared"
bitfld.long 0x00 2. " [5/4] ,AND share enable 5/4" "Not AND-shared,And-shared"
bitfld.long 0x00 1. " [3/2] ,AND share enable 3/2" "Not AND-shared,And-shared"
bitfld.long 0x00 0. " [1/0] ,AND share enable 1/0" "Not AND-shared,And-shared"
textline " "
endif
group.long 0x34++0x03
line.long 0x00 "HRSH,HR Share Control Register"
bitfld.long 0x00 15. " HR_SHARE[31/30] ,HR share 31/30" "Not shared,Shared"
bitfld.long 0x00 14. " [29/28] ,HR share 29/28" "Not shared,Shared"
bitfld.long 0x00 13. " [27/26] ,HR share 27/26" "Not shared,Shared"
bitfld.long 0x00 12. " [25/24] ,HR share 25/24" "Not shared,Shared"
textline " "
bitfld.long 0x00 11. " [23/22] ,HR share 23/22" "Not shared,Shared"
bitfld.long 0x00 10. " [21/20] ,HR share 21/20" "Not shared,Shared"
bitfld.long 0x00 9. " [19/18] ,HR share 19/18" "Not shared,Shared"
bitfld.long 0x00 8. " [17/16] ,HR share 17/16" "Not shared,Shared"
textline " "
bitfld.long 0x00 7. " [15/14] ,HR share 15/14" "Not shared,Shared"
bitfld.long 0x00 6. " [13/12] ,HR share 13/12" "Not shared,Shared"
bitfld.long 0x00 5. " [11/10] ,HR share 11/10" "Not shared,Shared"
bitfld.long 0x00 4. " [9/8] ,HR share 9/8" "Not shared,Shared"
textline " "
bitfld.long 0x00 3. " [7/6] ,HR share 7/6" "Not shared,Shared"
bitfld.long 0x00 2. " [5/4] ,HR share 5/4" "Not shared,Shared"
bitfld.long 0x00 1. " [3/2] ,HR share 3/2" "Not shared,Shared"
bitfld.long 0x00 0. " [1/0] ,HR share 1/0" "Not shared,Shared"
textline " "
group.long 0x38++0x03
line.long 0x00 "XOR,HR XOR Control Register"
bitfld.long 0x00 15. " HR_XOR_SHARE_[31/30] ,HR XOR-Share 31/30" "Not XOR-shared,Xor-shared"
bitfld.long 0x00 14. " [29/28] ,HR XOR-Share 29/28" "Not XOR-shared,Xor-shared"
bitfld.long 0x00 13. " [27/26] ,HR XOR-Share 27/26" "Not XOR-shared,Xor-shared"
bitfld.long 0x00 12. " [25/24] ,HR XOR-Share 25/24" "Not XOR-shared,Xor-shared"
textline " "
bitfld.long 0x00 11. " [23/22] ,HR XOR-Share 23/22" "Not XOR-shared,Xor-shared"
bitfld.long 0x00 10. " [21/20] ,HR XOR-Share 21/20" "Not XOR-shared,Xor-shared"
bitfld.long 0x00 9. " [19/18] ,HR XOR-Share 19/18" "Not XOR-shared,Xor-shared"
bitfld.long 0x00 8. " [17/16] ,HR XOR-Share 17/16" "Not XOR-shared,Xor-shared"
textline " "
bitfld.long 0x00 7. " [15/14] ,HR XOR-Share 15/14" "Not XOR-shared,Xor-shared"
bitfld.long 0x00 6. " [13/12] ,HR XOR-Share 13/12" "Not XOR-shared,Xor-shared"
bitfld.long 0x00 5. " [11/10] ,HR XOR-Share 11/10" "Not XOR-shared,Xor-shared"
bitfld.long 0x00 4. " [9/8] ,HR XOR-Share 9/8" "Not XOR-shared,Xor-shared"
textline " "
bitfld.long 0x00 3. " [7/6] ,HR XOR-Share 7/6" "Not XOR-shared,Xor-shared"
bitfld.long 0x00 2. " [5/4] ,HR XOR-Share 5/4" "Not XOR-shared,Xor-shared"
bitfld.long 0x00 1. " [3/2] ,HR XOR-Share 3/2" "Not XOR-shared,Xor-shared"
bitfld.long 0x00 0. " [1/0] ,HR XOR-Share 1/0" "Not XOR-shared,Xor-shared"
textline " "
group.long 0x3C++0x03
line.long 0x00 "REQEN,Request Enable Register"
setclrfld.long 0x00 7. 0x00 7. 0x04 7. " REQENA_SET/CLR[7] ,Request enable bit[7]" "Disabled,Enabled"
setclrfld.long 0x00 6. 0x00 6. 0x04 6. " [6] ,Request enable bit[6]" "Disabled,Enabled"
setclrfld.long 0x00 5. 0x00 5. 0x04 5. " [5] ,Request enable bit[5]" "Disabled,Enabled"
setclrfld.long 0x00 4. 0x00 4. 0x04 4. " [4] ,Request enable bit[4]" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 3. 0x00 3. 0x04 3. " [3] ,Request enable bit[3]" "Disabled,Enabled"
setclrfld.long 0x00 2. 0x00 2. 0x04 2. " [2] ,Request enable bit[2]" "Disabled,Enabled"
setclrfld.long 0x00 1. 0x00 1. 0x04 1. " [1] ,Request enable bit[1]" "Disabled,Enabled"
setclrfld.long 0x00 0. 0x00 0. 0x04 0. " [0] ,Request enable bit[0]" "Disabled,Enabled"
textline " "
sif (cpu()!=("TMS570LS0332")&&cpu()!=("TMS570LS0432"))
group.long 0x44++0x03
line.long 0x00 "REQDS,Request Destination Select Register"
bitfld.long 0x00 7. 23. " TDS[7] ,HTU or DMA select bit[7]" "HTU,DMA,HTU & DMA,HTU & DMA"
bitfld.long 0x00 6. 22. " [6] ,HTU or DMA select bit[6]" "HTU,DMA,HTU & DMA,HTU & DMA"
bitfld.long 0x00 5. 21. " [5] ,HTU or DMA select bit[5]" "HTU,DMA,HTU & DMA,HTU & DMA"
bitfld.long 0x00 4. 20. " [4] ,HTU or DMA select bit[4]" "HTU,DMA,HTU & DMA,HTU & DMA"
textline " "
bitfld.long 0x00 3. 19. " [3] ,HTU or DMA select bit[3]" "HTU,DMA,HTU & DMA,HTU & DMA"
bitfld.long 0x00 2. 18. " [2] ,HTU or DMA select bit[2]" "HTU,DMA,HTU & DMA,HTU & DMA"
bitfld.long 0x00 1. 17. " [1] ,HTU or DMA select bit[1]" "HTU,DMA,HTU & DMA,HTU & DMA"
bitfld.long 0x00 0. 16. " [0] ,HTU or DMA select bit[0]" "HTU,DMA,HTU & DMA,HTU & DMA"
textline " "
endif
group.long 0x4C++0x03
line.long 0x00 "DIR,Direction Register"
bitfld.long 0x00 31. " HET_DIR[31] ,Input/output direction pin 31" "Input,Output"
bitfld.long 0x00 30. " [30] ,Input/output direction pin 30" "Input,Output"
bitfld.long 0x00 29. " [29] ,Input/output direction pin 29" "Input,Output"
bitfld.long 0x00 28. " [28] ,Input/output direction pin 28" "Input,Output"
textline " "
bitfld.long 0x00 27. " [27] ,Input/output direction pin 27" "Input,Output"
bitfld.long 0x00 26. " [26] ,Input/output direction pin 26" "Input,Output"
bitfld.long 0x00 25. " [25] ,Input/output direction pin 25" "Input,Output"
bitfld.long 0x00 24. " [24] ,Input/output direction pin 24" "Input,Output"
textline " "
bitfld.long 0x00 23. " [23] ,Input/output direction pin 23" "Input,Output"
bitfld.long 0x00 22. " [22] ,Input/output direction pin 22" "Input,Output"
bitfld.long 0x00 21. " [21] ,Input/output direction pin 21" "Input,Output"
bitfld.long 0x00 20. " [20] ,Input/output direction pin 20" "Input,Output"
textline " "
bitfld.long 0x00 19. " [19] ,Input/output direction pin 19" "Input,Output"
bitfld.long 0x00 18. " [18] ,Input/output direction pin 18" "Input,Output"
bitfld.long 0x00 17. " [17] ,Input/output direction pin 17" "Input,Output"
bitfld.long 0x00 16. " [16] ,Input/output direction pin 16" "Input,Output"
textline " "
bitfld.long 0x00 15. " [15] ,Input/output direction pin 15" "Input,Output"
bitfld.long 0x00 14. " [14] ,Input/output direction pin 14" "Input,Output"
bitfld.long 0x00 13. " [13] ,Input/output direction pin 13" "Input,Output"
bitfld.long 0x00 12. " [12] ,Input/output direction pin 12" "Input,Output"
textline " "
bitfld.long 0x00 11. " [11] ,Input/output direction pin 11" "Input,Output"
bitfld.long 0x00 10. " [10] ,Input/output direction pin 10" "Input,Output"
bitfld.long 0x00 9. " [9] ,Input/output direction pin 9" "Input,Output"
bitfld.long 0x00 8. " [8] ,Input/output direction pin 8" "Input,Output"
textline " "
bitfld.long 0x00 7. " [7] ,Input/output direction pin 7" "Input,Output"
bitfld.long 0x00 6. " [6] ,Input/output direction pin 6" "Input,Output"
bitfld.long 0x00 5. " [5] ,Input/output direction pin 5" "Input,Output"
bitfld.long 0x00 4. " [4] ,Input/output direction pin 4" "Input,Output"
textline " "
bitfld.long 0x00 3. " [3] ,Input/output direction pin 3" "Input,Output"
bitfld.long 0x00 2. " [2] ,Input/output direction pin 2" "Input,Output"
bitfld.long 0x00 1. " [1] ,Input/output direction pin 1" "Input,Output"
bitfld.long 0x00 0. " [0] ,Input/output direction pin 0" "Input,Output"
textline " "
rgroup.long 0x50++0x03
line.long 0x00 "DIN,Input Data Register"
bitfld.long 0x00 31. " HETDIN[31] ,NHET data input register pin 31" "Low,High"
bitfld.long 0x00 30. " [30] ,NHET data input register pin 30" "Low,High"
bitfld.long 0x00 29. " [29] ,NHET data input register pin 29" "Low,High"
bitfld.long 0x00 28. " [28] ,NHET data input register pin 28" "Low,High"
textline " "
bitfld.long 0x00 27. " [27] ,NHET data input register pin 27" "Low,High"
bitfld.long 0x00 26. " [26] ,NHET data input register pin 26" "Low,High"
bitfld.long 0x00 25. " [25] ,NHET data input register pin 25" "Low,High"
bitfld.long 0x00 24. " [24] ,NHET data input register pin 24" "Low,High"
textline " "
bitfld.long 0x00 23. " [23] ,NHET data input register pin 23" "Low,High"
bitfld.long 0x00 22. " [22] ,NHET data input register pin 22" "Low,High"
bitfld.long 0x00 21. " [21] ,NHET data input register pin 21" "Low,High"
bitfld.long 0x00 20. " [20] ,NHET data input register pin 20" "Low,High"
textline " "
bitfld.long 0x00 19. " [19] ,NHET data input register pin 19" "Low,High"
bitfld.long 0x00 18. " [18] ,NHET data input register pin 18" "Low,High"
bitfld.long 0x00 17. " [17] ,NHET data input register pin 17" "Low,High"
bitfld.long 0x00 16. " [16] ,NHET data input register pin 16" "Low,High"
textline " "
bitfld.long 0x00 15. " [15] ,NHET data input register pin 15" "Low,High"
bitfld.long 0x00 14. " [14] ,NHET data input register pin 14" "Low,High"
bitfld.long 0x00 13. " [13] ,NHET data input register pin 13" "Low,High"
bitfld.long 0x00 12. " [12] ,NHET data input register pin 12" "Low,High"
textline " "
bitfld.long 0x00 11. " [11] ,NHET data input register pin 11" "Low,High"
bitfld.long 0x00 10. " [10] ,NHET data input register pin 10" "Low,High"
bitfld.long 0x00 9. " [9] ,NHET data input register pin 9" "Low,High"
bitfld.long 0x00 8. " [8] ,NHET data input register pin 8" "Low,High"
textline " "
bitfld.long 0x00 7. " [7] ,NHET data input register pin 7" "Low,High"
bitfld.long 0x00 6. " [6] ,NHET data input register pin 6" "Low,High"
bitfld.long 0x00 5. " [5] ,NHET data input register pin 5" "Low,High"
bitfld.long 0x00 4. " [4] ,NHET data input register pin 4" "Low,High"
textline " "
bitfld.long 0x00 3. " [3] ,NHET data input register pin 3" "Low,High"
bitfld.long 0x00 2. " [2] ,NHET data input register pin 2" "Low,High"
bitfld.long 0x00 1. " [1] ,NHET data input register pin 1" "Low,High"
bitfld.long 0x00 0. " [0] ,NHET data input register pin 0" "Low,High"
textline " "
group.long 0x54++0x03
line.long 0x00 "DOUT,Output Data Register"
setclrfld.long 0x00 31. 0x04 31. 0x08 31. " HETDOUT_SET/CLR_[31] ,NHET data output register bit[31]" "Low,High"
setclrfld.long 0x00 30. 0x04 30. 0x08 30. " [30] ,NHET data output register bit[30]" "Low,High"
setclrfld.long 0x00 29. 0x04 29. 0x08 29. " [29] ,NHET data output register bit[29]" "Low,High"
setclrfld.long 0x00 28. 0x04 28. 0x08 28. " [28] ,NHET data output register bit[28]" "Low,High"
textline " "
setclrfld.long 0x00 27. 0x04 27. 0x08 27. " [27] ,NHET data output register bit[27]" "Low,High"
setclrfld.long 0x00 26. 0x04 26. 0x08 26. " [26] ,NHET data output register bit[26]" "Low,High"
setclrfld.long 0x00 25. 0x04 25. 0x08 25. " [25] ,NHET data output register bit[25]" "Low,High"
setclrfld.long 0x00 24. 0x04 24. 0x08 24. " [24] ,NHET data output register bit[24]" "Low,High"
textline " "
setclrfld.long 0x00 23. 0x04 23. 0x08 23. " [23] ,NHET data output register bit[23]" "Low,High"
setclrfld.long 0x00 22. 0x04 22. 0x08 22. " [22] ,NHET data output register bit[22]" "Low,High"
setclrfld.long 0x00 21. 0x04 21. 0x08 21. " [21] ,NHET data output register bit[21]" "Low,High"
setclrfld.long 0x00 20. 0x04 20. 0x08 20. " [20] ,NHET data output register bit[20]" "Low,High"
textline " "
setclrfld.long 0x00 19. 0x04 19. 0x08 19. " [19] ,NHET data output register bit[19]" "Low,High"
setclrfld.long 0x00 18. 0x04 18. 0x08 18. " [18] ,NHET data output register bit[18]" "Low,High"
setclrfld.long 0x00 17. 0x04 17. 0x08 17. " [17] ,NHET data output register bit[17]" "Low,High"
setclrfld.long 0x00 16. 0x04 16. 0x08 16. " [16] ,NHET data output register bit[16]" "Low,High"
textline " "
setclrfld.long 0x00 15. 0x04 15. 0x08 15. " [15] ,NHET data output register bit[15]" "Low,High"
setclrfld.long 0x00 14. 0x04 14. 0x08 14. " [14] ,NHET data output register bit[14]" "Low,High"
setclrfld.long 0x00 13. 0x04 13. 0x08 13. " [13] ,NHET data output register bit[13]" "Low,High"
setclrfld.long 0x00 12. 0x04 12. 0x08 12. " [12] ,NHET data output register bit[12]" "Low,High"
textline " "
setclrfld.long 0x00 11. 0x04 11. 0x08 11. " [11] ,NHET data output register bit[11]" "Low,High"
setclrfld.long 0x00 10. 0x04 10. 0x08 10. " [10] ,NHET data output register bit[10]" "Low,High"
setclrfld.long 0x00 9. 0x04 9. 0x08 9. " [9] ,NHET data output register bit[9]" "Low,High"
setclrfld.long 0x00 8. 0x04 8. 0x08 8. " [8] ,NHET data output register bit[8]" "Low,High"
textline " "
setclrfld.long 0x00 7. 0x04 7. 0x08 7. " [7] ,NHET data output register bit[7]" "Low,High"
setclrfld.long 0x00 6. 0x04 6. 0x08 6. " [6] ,NHET data output register bit[6]" "Low,High"
setclrfld.long 0x00 5. 0x04 5. 0x08 5. " [5] ,NHET data output register bit[5]" "Low,High"
setclrfld.long 0x00 4. 0x04 4. 0x08 4. " [4] ,NHET data output register bit[4]" "Low,High"
textline " "
setclrfld.long 0x00 3. 0x04 3. 0x08 3. " [3] ,NHET data output register bit[3]" "Low,High"
setclrfld.long 0x00 2. 0x04 2. 0x08 2. " [2] ,NHET data output register bit[2]" "Low,High"
setclrfld.long 0x00 1. 0x04 1. 0x08 1. " [1] ,NHET data output register bit[1]" "Low,High"
setclrfld.long 0x00 0. 0x04 0. 0x08 0. " [0] ,NHET data output register bit[0]" "Low,High"
textline " "
group.long 0x60++0x03
line.long 0x00 "PDR,Open Drain Register"
bitfld.long 0x00 31. " HETPDR[31] ,NHET open drain bit[31]" "Disabled,Enabled"
bitfld.long 0x00 30. " [30] ,NHET open drain bit[30]" "Disabled,Enabled"
bitfld.long 0x00 29. " [29] ,NHET open drain bit[29]" "Disabled,Enabled"
bitfld.long 0x00 28. " [28] ,NHET open drain bit[28]" "Disabled,Enabled"
textline " "
bitfld.long 0x00 27. " [27] ,NHET open drain bit[27]" "Disabled,Enabled"
bitfld.long 0x00 26. " [26] ,NHET open drain bit[26]" "Disabled,Enabled"
bitfld.long 0x00 25. " [25] ,NHET open drain bit[25]" "Disabled,Enabled"
bitfld.long 0x00 24. " [24] ,NHET open drain bit[24]" "Disabled,Enabled"
textline " "
bitfld.long 0x00 23. " [23] ,NHET open drain bit[23]" "Disabled,Enabled"
bitfld.long 0x00 22. " [22] ,NHET open drain bit[22]" "Disabled,Enabled"
bitfld.long 0x00 21. " [21] ,NHET open drain bit[21]" "Disabled,Enabled"
bitfld.long 0x00 20. " [20] ,NHET open drain bit[20]" "Disabled,Enabled"
textline " "
bitfld.long 0x00 19. " [19] ,NHET open drain bit[19]" "Disabled,Enabled"
bitfld.long 0x00 18. " [18] ,NHET open drain bit[18]" "Disabled,Enabled"
bitfld.long 0x00 17. " [17] ,NHET open drain bit[17]" "Disabled,Enabled"
bitfld.long 0x00 16. " [16] ,NHET open drain bit[16]" "Disabled,Enabled"
textline " "
bitfld.long 0x00 15. " [15] ,NHET open drain bit[15]" "Disabled,Enabled"
bitfld.long 0x00 14. " [14] ,NHET open drain bit[14]" "Disabled,Enabled"
bitfld.long 0x00 13. " [13] ,NHET open drain bit[13]" "Disabled,Enabled"
bitfld.long 0x00 12. " [12] ,NHET open drain bit[12]" "Disabled,Enabled"
textline " "
bitfld.long 0x00 11. " [11] ,NHET open drain bit[11]" "Disabled,Enabled"
bitfld.long 0x00 10. " [10] ,NHET open drain bit[10]" "Disabled,Enabled"
bitfld.long 0x00 9. " [9] ,NHET open drain bit[9]" "Disabled,Enabled"
bitfld.long 0x00 8. " [8] ,NHET open drain bit[8]" "Disabled,Enabled"
textline " "
bitfld.long 0x00 7. " [7] ,NHET open drain bit[7]" "Disabled,Enabled"
bitfld.long 0x00 6. " [6] ,NHET open drain bit[6]" "Disabled,Enabled"
bitfld.long 0x00 5. " [5] ,NHET open drain bit[5]" "Disabled,Enabled"
bitfld.long 0x00 4. " [4] ,NHET open drain bit[4]" "Disabled,Enabled"
textline " "
bitfld.long 0x00 3. " [3] ,NHET open drain bit[3]" "Disabled,Enabled"
bitfld.long 0x00 2. " [2] ,NHET open drain bit[2]" "Disabled,Enabled"
bitfld.long 0x00 1. " [1] ,NHET open drain bit[1]" "Disabled,Enabled"
bitfld.long 0x00 0. " [0] ,NHET open drain bit[0]" "Disabled,Enabled"
textline " "
group.long 0x64++0x03
line.long 0x00 "PULDIS,Pull Disable Register"
bitfld.long 0x00 31. " HETPULDIS[31] ,NHET pull disable bit[31]" "No,Yes"
bitfld.long 0x00 30. " [30] ,NHET pull disable bit[30]" "No,Yes"
bitfld.long 0x00 29. " [29] ,NHET pull disable bit[29]" "No,Yes"
bitfld.long 0x00 28. " [28] ,NHET pull disable bit[28]" "No,Yes"
textline " "
bitfld.long 0x00 27. " [27] ,NHET pull disable bit[27]" "No,Yes"
bitfld.long 0x00 26. " [26] ,NHET pull disable bit[26]" "No,Yes"
bitfld.long 0x00 25. " [25] ,NHET pull disable bit[25]" "No,Yes"
bitfld.long 0x00 24. " [24] ,NHET pull disable bit[24]" "No,Yes"
textline " "
bitfld.long 0x00 23. " [23] ,NHET pull disable bit[23]" "No,Yes"
bitfld.long 0x00 22. " [22] ,NHET pull disable bit[22]" "No,Yes"
bitfld.long 0x00 21. " [21] ,NHET pull disable bit[21]" "No,Yes"
bitfld.long 0x00 20. " [20] ,NHET pull disable bit[20]" "No,Yes"
textline " "
bitfld.long 0x00 19. " [19] ,NHET pull disable bit[19]" "No,Yes"
bitfld.long 0x00 18. " [18] ,NHET pull disable bit[18]" "No,Yes"
bitfld.long 0x00 17. " [17] ,NHET pull disable bit[17]" "No,Yes"
bitfld.long 0x00 16. " [16] ,NHET pull disable bit[16]" "No,Yes"
textline " "
bitfld.long 0x00 15. " [15] ,NHET pull disable bit[15]" "No,Yes"
bitfld.long 0x00 14. " [14] ,NHET pull disable bit[14]" "No,Yes"
bitfld.long 0x00 13. " [13] ,NHET pull disable bit[13]" "No,Yes"
bitfld.long 0x00 12. " [12] ,NHET pull disable bit[12]" "No,Yes"
textline " "
bitfld.long 0x00 11. " [11] ,NHET pull disable bit[11]" "No,Yes"
bitfld.long 0x00 10. " [10] ,NHET pull disable bit[10]" "No,Yes"
bitfld.long 0x00 9. " [9] ,NHET pull disable bit[9]" "No,Yes"
bitfld.long 0x00 8. " [8] ,NHET pull disable bit[8]" "No,Yes"
textline " "
bitfld.long 0x00 7. " [7] ,NHET pull disable bit[7]" "No,Yes"
bitfld.long 0x00 6. " [6] ,NHET pull disable bit[6]" "No,Yes"
bitfld.long 0x00 5. " [5] ,NHET pull disable bit[5]" "No,Yes"
bitfld.long 0x00 4. " [4] ,NHET pull disable bit[4]" "No,Yes"
textline " "
bitfld.long 0x00 3. " [3] ,NHET pull disable bit[3]" "No,Yes"
bitfld.long 0x00 2. " [2] ,NHET pull disable bit[2]" "No,Yes"
bitfld.long 0x00 1. " [1] ,NHET pull disable bit[1]" "No,Yes"
bitfld.long 0x00 0. " [0] ,NHET pull disable bit[0]" "No,Yes"
textline " "
group.long 0x68++0x03
line.long 0x00 "PSL,Pull Select Register"
bitfld.long 0x00 31. " HETPSL[31] ,NHET pull select bit[31]" "Pull down,Pull up"
bitfld.long 0x00 30. " [30] ,NHET pull select bit[30]" "Pull down,Pull up"
bitfld.long 0x00 29. " [29] ,NHET pull select bit[29]" "Pull down,Pull up"
bitfld.long 0x00 28. " [28] ,NHET pull select bit[28]" "Pull down,Pull up"
textline " "
bitfld.long 0x00 27. " [27] ,NHET pull select bit[27]" "Pull down,Pull up"
bitfld.long 0x00 26. " [26] ,NHET pull select bit[26]" "Pull down,Pull up"
bitfld.long 0x00 25. " [25] ,NHET pull select bit[25]" "Pull down,Pull up"
bitfld.long 0x00 24. " [24] ,NHET pull select bit[24]" "Pull down,Pull up"
textline " "
bitfld.long 0x00 23. " [23] ,NHET pull select bit[23]" "Pull down,Pull up"
bitfld.long 0x00 22. " [22] ,NHET pull select bit[22]" "Pull down,Pull up"
bitfld.long 0x00 21. " [21] ,NHET pull select bit[21]" "Pull down,Pull up"
bitfld.long 0x00 20. " [20] ,NHET pull select bit[20]" "Pull down,Pull up"
textline " "
bitfld.long 0x00 19. " [19] ,NHET pull select bit[19]" "Pull down,Pull up"
bitfld.long 0x00 18. " [18] ,NHET pull select bit[18]" "Pull down,Pull up"
bitfld.long 0x00 17. " [17] ,NHET pull select bit[17]" "Pull down,Pull up"
bitfld.long 0x00 16. " [16] ,NHET pull select bit[16]" "Pull down,Pull up"
textline " "
bitfld.long 0x00 15. " [15] ,NHET pull select bit[15]" "Pull down,Pull up"
bitfld.long 0x00 14. " [14] ,NHET pull select bit[14]" "Pull down,Pull up"
bitfld.long 0x00 13. " [13] ,NHET pull select bit[13]" "Pull down,Pull up"
bitfld.long 0x00 12. " [12] ,NHET pull select bit[12]" "Pull down,Pull up"
textline " "
bitfld.long 0x00 11. " [11] ,NHET pull select bit[11]" "Pull down,Pull up"
bitfld.long 0x00 10. " [10] ,NHET pull select bit[10]" "Pull down,Pull up"
bitfld.long 0x00 9. " [9] ,NHET pull select bit[9]" "Pull down,Pull up"
bitfld.long 0x00 8. " [8] ,NHET pull select bit[8]" "Pull down,Pull up"
textline " "
bitfld.long 0x00 7. " [7] ,NHET pull select bit[7]" "Pull down,Pull up"
bitfld.long 0x00 6. " [6] ,NHET pull select bit[6]" "Pull down,Pull up"
bitfld.long 0x00 5. " [5] ,NHET pull select bit[5]" "Pull down,Pull up"
bitfld.long 0x00 4. " [4] ,NHET pull select bit[4]" "Pull down,Pull up"
textline " "
bitfld.long 0x00 3. " [3] ,NHET pull select bit[3]" "Pull down,Pull up"
bitfld.long 0x00 2. " [2] ,NHET pull select bit[2]" "Pull down,Pull up"
bitfld.long 0x00 1. " [1] ,NHET pull select bit[1]" "Pull down,Pull up"
bitfld.long 0x00 0. " [0] ,NHET pull select bit[0]" "Pull down,Pull up"
textline " "
group.long 0x74++0x03
line.long 0x00 "PCR,Parity Control Register"
bitfld.long 0x00 8. " TEST ,Test bit - parity bits memory mapping" "Not mapped,Mapped"
bitfld.long 0x00 0.--3. " PARITY_ENA ,Enable / disable parity checking" "Enabled,Enabled,Enabled,Enabled,Enabled,Disabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled"
rgroup.long 0x78++0x03
line.long 0x00 "PAR,Parity Address Register"
hexmask.long.word 0x00 2.--12. 0x04 " PAOFF ,Parity error address offset"
textline " "
group.long 0x7C++0x03
line.long 0x00 "PPR,Parity Pin Register"
bitfld.long 0x00 31. " HETPPR_[31] ,NHET parity pin select bit[31]" "Not affected,Known state"
bitfld.long 0x00 30. " [30] ,NHET parity pin select bit[30]" "Not affected,Known state"
bitfld.long 0x00 29. " [29] ,NHET parity pin select bit[29]" "Not affected,Known state"
bitfld.long 0x00 28. " [28] ,NHET parity pin select bit[28]" "Not affected,Known state"
textline " "
bitfld.long 0x00 27. " [27] ,NHET parity pin select bit[27]" "Not affected,Known state"
bitfld.long 0x00 26. " [26] ,NHET parity pin select bit[26]" "Not affected,Known state"
bitfld.long 0x00 25. " [25] ,NHET parity pin select bit[25]" "Not affected,Known state"
bitfld.long 0x00 24. " [24] ,NHET parity pin select bit[24]" "Not affected,Known state"
textline " "
bitfld.long 0x00 23. " [23] ,NHET parity pin select bit[23]" "Not affected,Known state"
bitfld.long 0x00 22. " [22] ,NHET parity pin select bit[22]" "Not affected,Known state"
bitfld.long 0x00 21. " [21] ,NHET parity pin select bit[21]" "Not affected,Known state"
bitfld.long 0x00 20. " [20] ,NHET parity pin select bit[20]" "Not affected,Known state"
textline " "
bitfld.long 0x00 19. " [19] ,NHET parity pin select bit[19]" "Not affected,Known state"
bitfld.long 0x00 18. " [18] ,NHET parity pin select bit[18]" "Not affected,Known state"
bitfld.long 0x00 17. " [17] ,NHET parity pin select bit[17]" "Not affected,Known state"
bitfld.long 0x00 16. " [16] ,NHET parity pin select bit[16]" "Not affected,Known state"
textline " "
bitfld.long 0x00 15. " [15] ,NHET parity pin select bit[15]" "Not affected,Known state"
bitfld.long 0x00 14. " [14] ,NHET parity pin select bit[14]" "Not affected,Known state"
bitfld.long 0x00 13. " [13] ,NHET parity pin select bit[13]" "Not affected,Known state"
bitfld.long 0x00 12. " [12] ,NHET parity pin select bit[12]" "Not affected,Known state"
textline " "
bitfld.long 0x00 11. " [11] ,NHET parity pin select bit[11]" "Not affected,Known state"
bitfld.long 0x00 10. " [10] ,NHET parity pin select bit[10]" "Not affected,Known state"
bitfld.long 0x00 9. " [9] ,NHET parity pin select bit[9]" "Not affected,Known state"
bitfld.long 0x00 8. " [8] ,NHET parity pin select bit[8]" "Not affected,Known state"
textline " "
bitfld.long 0x00 7. " [7] ,NHET parity pin select bit[7]" "Not affected,Known state"
bitfld.long 0x00 6. " [6] ,NHET parity pin select bit[6]" "Not affected,Known state"
bitfld.long 0x00 5. " [5] ,NHET parity pin select bit[5]" "Not affected,Known state"
bitfld.long 0x00 4. " [4] ,NHET parity pin select bit[4]" "Not affected,Known state"
textline " "
bitfld.long 0x00 3. " [3] ,NHET parity pin select bit[3]" "Not affected,Known state"
bitfld.long 0x00 2. " [2] ,NHET parity pin select bit[2]" "Not affected,Known state"
bitfld.long 0x00 1. " [1] ,NHET parity pin select bit[1]" "Not affected,Known state"
bitfld.long 0x00 0. " [0] ,NHET parity pin select bit[0]" "Not affected,Known state"
textline " "
group.long 0x80++0x03
line.long 0x00 "SFPRLD,Suppresion Filter Preload Register"
bitfld.long 0x00 16.--17. " CCDIV ,Counter clock divider" "VCLK2,VCLK2/2,VCLK2/3,VCLK2/4"
hexmask.long.word 0x00 0.--9. 1. " CPRLD ,Counter preload value"
textline " "
group.long 0x84++0x03
line.long 0x00 "SFENA,Suppresion Filter Enable Register"
bitfld.long 0x00 31. " HETSFENA[31] ,Suppression filter enable bit[31]" "Disabled,Enabled"
bitfld.long 0x00 30. " [30] ,Suppression filter enable bit[30]" "Disabled,Enabled"
bitfld.long 0x00 29. " [29] ,Suppression filter enable bit[29]" "Disabled,Enabled"
bitfld.long 0x00 28. " [28] ,Suppression filter enable bit[28]" "Disabled,Enabled"
textline " "
bitfld.long 0x00 27. " [27] ,Suppression filter enable bit[27]" "Disabled,Enabled"
bitfld.long 0x00 26. " [26] ,Suppression filter enable bit[26]" "Disabled,Enabled"
bitfld.long 0x00 25. " [25] ,Suppression filter enable bit[25]" "Disabled,Enabled"
bitfld.long 0x00 24. " [24] ,Suppression filter enable bit[24]" "Disabled,Enabled"
textline " "
bitfld.long 0x00 23. " [23] ,Suppression filter enable bit[23]" "Disabled,Enabled"
bitfld.long 0x00 22. " [22] ,Suppression filter enable bit[22]" "Disabled,Enabled"
bitfld.long 0x00 21. " [21] ,Suppression filter enable bit[21]" "Disabled,Enabled"
bitfld.long 0x00 20. " [20] ,Suppression filter enable bit[20]" "Disabled,Enabled"
textline " "
bitfld.long 0x00 19. " [19] ,Suppression filter enable bit[19]" "Disabled,Enabled"
bitfld.long 0x00 18. " [18] ,Suppression filter enable bit[18]" "Disabled,Enabled"
bitfld.long 0x00 17. " [17] ,Suppression filter enable bit[17]" "Disabled,Enabled"
bitfld.long 0x00 16. " [16] ,Suppression filter enable bit[16]" "Disabled,Enabled"
textline " "
bitfld.long 0x00 15. " [15] ,Suppression filter enable bit[15]" "Disabled,Enabled"
bitfld.long 0x00 14. " [14] ,Suppression filter enable bit[14]" "Disabled,Enabled"
bitfld.long 0x00 13. " [13] ,Suppression filter enable bit[13]" "Disabled,Enabled"
bitfld.long 0x00 12. " [12] ,Suppression filter enable bit[12]" "Disabled,Enabled"
textline " "
bitfld.long 0x00 11. " [11] ,Suppression filter enable bit[11]" "Disabled,Enabled"
bitfld.long 0x00 10. " [10] ,Suppression filter enable bit[10]" "Disabled,Enabled"
bitfld.long 0x00 9. " [9] ,Suppression filter enable bit[9]" "Disabled,Enabled"
bitfld.long 0x00 8. " [8] ,Suppression filter enable bit[8]" "Disabled,Enabled"
textline " "
bitfld.long 0x00 7. " [7] ,Suppression filter enable bit[7]" "Disabled,Enabled"
bitfld.long 0x00 6. " [6] ,Suppression filter enable bit[6]" "Disabled,Enabled"
bitfld.long 0x00 5. " [5] ,Suppression filter enable bit[5]" "Disabled,Enabled"
bitfld.long 0x00 4. " [4] ,Suppression filter enable bit[4]" "Disabled,Enabled"
textline " "
bitfld.long 0x00 3. " [3] ,Suppression filter enable bit[3]" "Disabled,Enabled"
bitfld.long 0x00 2. " [2] ,Suppression filter enable bit[2]" "Disabled,Enabled"
bitfld.long 0x00 1. " [1] ,Suppression filter enable bit[1]" "Disabled,Enabled"
bitfld.long 0x00 0. " [0] ,Suppression filter enable bit[0]" "Disabled,Enabled"
textline " "
sif (cpu()!="RM48L952-PGE"&&cpu()!="RM48L950-PGE"&&cpu()!="RM48L950-ZWT"&&cpu()!="RM48L940-ZWT"&&cpu()!="RM48L940-PGE"&&cpu()!="RM48L930-ZWT"&&cpu()!="RM48L930-PGE"&&cpu()!="RM48L750-ZWT"&&cpu()!="RM48L750-PGE"&&cpu()!="RM48L740-ZWT"&&cpu()!="RM48L740-PGE"&&cpu()!="RM48L730-ZWT"&&cpu()!="RM48L730-PGE"&&cpu()!="RM48L550-PGE"&&cpu()!="RM48L540-ZWT"&&cpu()!="RM48L540-PGE"&&cpu()!="RM48L530-ZWT"&&cpu()!="RM48L530-PGE"&&cpu()!="RM46L852-PGE"&&cpu()!="RM46L852-ZWT"&&cpu()!="RM46L850-PGE"&&cpu()!="RM46L850-ZWT"&&cpu()!="RM46L840-ZWT"&&cpu()!="RM46L840-PGE"&&cpu()!="RM46L830-ZWT"&&cpu()!="RM46L830-PGE"&&cpu()!="RM46L450-ZWT"&&cpu()!="RM46L450-PGE"&&cpu()!="RM46L440-ZWT"&&cpu()!="RM46L440-PGE"&&cpu()!="RM46L430-ZWT"&&cpu()!="RM46L430-PGE"&&cpu()!="TMS570LC4357"&&cpu()!="RM48L550-ZWT"&&cpu()!="RM42L432"&&cpu()!="RM57L843-ZWT")
if ((d.l(ad:0xFFF7B800+0x90)&0xF00)==0xA00)
group.long 0x8C++0x03
line.long 0x00 "LBPSEL,Loop Back Pair Select Register"
bitfld.long 0x00 31. " LBPTYPE[15] ,Loop back pair type select bit[15]" "Digital,Analog"
bitfld.long 0x00 30. " [14] ,Loop back pair type select bit[14]" "Digital,Analog"
bitfld.long 0x00 29. " [13] ,Loop back pair type select bit[13]" "Digital,Analog"
bitfld.long 0x00 28. " [12] ,Loop back pair type select bit[12]" "Digital,Analog"
textline " "
bitfld.long 0x00 27. " [11] ,Loop back pair type select bit[11]" "Digital,Analog"
bitfld.long 0x00 26. " [10] ,Loop back pair type select bit[10]" "Digital,Analog"
bitfld.long 0x00 25. " [9] ,Loop back pair type select bit[9]" "Digital,Analog"
bitfld.long 0x00 24. " [8] ,Loop back pair type select bit[8]" "Digital,Analog"
textline " "
bitfld.long 0x00 23. " [7] ,Loop back pair type select bit[7]" "Digital,Analog"
bitfld.long 0x00 22. " [6] ,Loop back pair type select bit[6]" "Digital,Analog"
bitfld.long 0x00 21. " [5] ,Loop back pair type select bit[5]" "Digital,Analog"
bitfld.long 0x00 20. " [4] ,Loop back pair type select bit[4]" "Digital,Analog"
textline " "
bitfld.long 0x00 19. " [3] ,Loop back pair type select bit[3]" "Digital,Analog"
bitfld.long 0x00 18. " [2] ,Loop back pair type select bit[2]" "Digital,Analog"
bitfld.long 0x00 17. " [1] ,Loop back pair type select bit[1]" "Digital,Analog"
bitfld.long 0x00 16. " [0] ,Loop back pair type select bit[0]" "Digital,Analog"
textline " "
bitfld.long 0x00 15. " LBPSEL[15] ,Loop back pair select bit[15]" "Not selected,Selected"
bitfld.long 0x00 14. " [14] ,Loop back pair select bit[14]" "Not selected,Selected"
bitfld.long 0x00 13. " [13] ,Loop back pair select bit[13]" "Not selected,Selected"
bitfld.long 0x00 12. " [12] ,Loop back pair select bit[12]" "Not selected,Selected"
textline " "
bitfld.long 0x00 11. " [11] ,Loop back pair select bit[11]" "Not selected,Selected"
bitfld.long 0x00 10. " [10] ,Loop back pair select bit[10]" "Not selected,Selected"
bitfld.long 0x00 9. " [9] ,Loop back pair select bit[9]" "Not selected,Selected"
bitfld.long 0x00 8. " [8] ,Loop back pair select bit[8]" "Not selected,Selected"
textline " "
bitfld.long 0x00 7. " [7] ,Loop back pair select bit[7]" "Not selected,Selected"
bitfld.long 0x00 6. " [6] ,Loop back pair select bit[6]" "Not selected,Selected"
bitfld.long 0x00 5. " [5] ,Loop back pair select bit[5]" "Not selected,Selected"
bitfld.long 0x00 4. " [4] ,Loop back pair select bit[4]" "Not selected,Selected"
textline " "
bitfld.long 0x00 3. " [3] ,Loop back pair select bit[3]" "Not selected,Selected"
bitfld.long 0x00 2. " [2] ,Loop back pair select bit[2]" "Not selected,Selected"
bitfld.long 0x00 1. " [1] ,Loop back pair select bit[1]" "Not selected,Selected"
bitfld.long 0x00 0. " [0] ,Loop back pair select bit[0]" "Not selected,Selected"
else
hgroup.long 0x8C++0x03
hide.long 0x00 "LBPSEL,Loop Back Pair Select Register"
endif
else
if ((d.l(ad:0xFFF7B800+0x90)&0xF0000)==0xA0000)
group.long 0x8C++0x03
line.long 0x00 "LBPSEL,Loop Back Pair Select Register"
bitfld.long 0x00 31. " LBPTYPE[15] ,Loop back pair type select bit[15]" "Digital,Analog"
bitfld.long 0x00 30. " [14] ,Loop back pair type select bit[14]" "Digital,Analog"
bitfld.long 0x00 29. " [13] ,Loop back pair type select bit[13]" "Digital,Analog"
bitfld.long 0x00 28. " [12] ,Loop back pair type select bit[12]" "Digital,Analog"
textline " "
bitfld.long 0x00 27. " [11] ,Loop back pair type select bit[11]" "Digital,Analog"
bitfld.long 0x00 26. " [10] ,Loop back pair type select bit[10]" "Digital,Analog"
bitfld.long 0x00 25. " [9] ,Loop back pair type select bit[9]" "Digital,Analog"
bitfld.long 0x00 24. " [8] ,Loop back pair type select bit[8]" "Digital,Analog"
textline " "
bitfld.long 0x00 23. " [7] ,Loop back pair type select bit[7]" "Digital,Analog"
bitfld.long 0x00 22. " [6] ,Loop back pair type select bit[6]" "Digital,Analog"
bitfld.long 0x00 21. " [5] ,Loop back pair type select bit[5]" "Digital,Analog"
bitfld.long 0x00 20. " [4] ,Loop back pair type select bit[4]" "Digital,Analog"
textline " "
bitfld.long 0x00 19. " [3] ,Loop back pair type select bit[3]" "Digital,Analog"
bitfld.long 0x00 18. " [2] ,Loop back pair type select bit[2]" "Digital,Analog"
bitfld.long 0x00 17. " [1] ,Loop back pair type select bit[1]" "Digital,Analog"
bitfld.long 0x00 16. " [0] ,Loop back pair type select bit[0]" "Digital,Analog"
textline " "
bitfld.long 0x00 15. " LBPSEL[15] ,Loop back pair select bit[15]" "Not selected,Selected"
bitfld.long 0x00 14. " [14] ,Loop back pair select bit[14]" "Not selected,Selected"
bitfld.long 0x00 13. " [13] ,Loop back pair select bit[13]" "Not selected,Selected"
bitfld.long 0x00 12. " [12] ,Loop back pair select bit[12]" "Not selected,Selected"
textline " "
bitfld.long 0x00 11. " [11] ,Loop back pair select bit[11]" "Not selected,Selected"
bitfld.long 0x00 10. " [10] ,Loop back pair select bit[10]" "Not selected,Selected"
bitfld.long 0x00 9. " [9] ,Loop back pair select bit[9]" "Not selected,Selected"
bitfld.long 0x00 8. " [8] ,Loop back pair select bit[8]" "Not selected,Selected"
textline " "
bitfld.long 0x00 7. " [7] ,Loop back pair select bit[7]" "Not selected,Selected"
bitfld.long 0x00 6. " [6] ,Loop back pair select bit[6]" "Not selected,Selected"
bitfld.long 0x00 5. " [5] ,Loop back pair select bit[5]" "Not selected,Selected"
bitfld.long 0x00 4. " [4] ,Loop back pair select bit[4]" "Not selected,Selected"
textline " "
bitfld.long 0x00 3. " [3] ,Loop back pair select bit[3]" "Not selected,Selected"
bitfld.long 0x00 2. " [2] ,Loop back pair select bit[2]" "Not selected,Selected"
bitfld.long 0x00 1. " [1] ,Loop back pair select bit[1]" "Not selected,Selected"
bitfld.long 0x00 0. " [0] ,Loop back pair select bit[0]" "Not selected,Selected"
textline " "
else
hgroup.long 0x8C++0x03
hide.long 0x00 "LBPSEL,Loop Back Pair Select Register"
endif
endif
group.long 0x90++0x03
line.long 0x00 "LBPDIR,Loop Back Pair Direction Register"
sif cpu()=="RM57L843-ZWT"
bitfld.long 0x00 16.--19. " LBPTSTENA ,Loopback test enable key" "Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Enabled,Disabled,Disabled,Disabled,Disabled,Disabled"
else
bitfld.long 0x00 16.--19. " IODFTENA ,Module IODFT enable key" "Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Enabled,Disabled,Disabled,Disabled,Disabled,Disabled"
endif
textline " "
bitfld.long 0x00 15. " LBPDIR[15] ,Loop back pair direction bit[15]" "31 in/30 out,31 out/30 in"
bitfld.long 0x00 14. " [14] ,Loop back pair direction bit[14]" "29 in/28 out,29 out/28 in"
bitfld.long 0x00 13. " [13] ,Loop back pair direction bit[13]" "27 in/26 out,27 out/26 in"
bitfld.long 0x00 12. " [12] ,Loop back pair direction bit[12]" "25 in/24 out,25 out/24 in"
textline " "
bitfld.long 0x00 11. " [11] ,Loop back pair direction bit[11]" "23 in/22 out,23 out/22 in"
bitfld.long 0x00 10. " [10] ,Loop back pair direction bit[10]" "21 in/20 out,21 out/20 in"
bitfld.long 0x00 9. " [9] ,Loop back pair direction bit[9]" "19 in/18 out,19 out/18 in"
bitfld.long 0x00 8. " [8] ,Loop back pair direction bit[8]" "17 in/16 out,17 out/16 in"
textline " "
bitfld.long 0x00 7. " [7] ,Loop back pair direction bit[7]" "15 in/14 out,15 out/14 in"
bitfld.long 0x00 6. " [6] ,Loop back pair direction bit[6]" "13 in/12 out,13 out/12 in"
bitfld.long 0x00 5. " [5] ,Loop back pair direction bit[5]" "11 in/10 out,11 out/10 in"
bitfld.long 0x00 4. " [4] ,Loop back pair direction bit[4]" "9 in/8 out,9 out/8 in"
textline " "
bitfld.long 0x00 3. " [3] ,Loop back pair direction bit[3]" "7 in/6 out,7 out/6 in"
bitfld.long 0x00 2. " [2] ,Loop back pair direction bit[2]" "5 in/4 out,5 out/4 in"
bitfld.long 0x00 1. " [1] ,Loop back pair direction bit[1]" "3 in/2 out,3 out/2 in"
bitfld.long 0x00 0. " [0] ,Loop back pair direction bit[0]" "1 in/0 out,1 out/0 in"
textline " "
group.long 0x94++0x03
line.long 0x00 "PINDIS,Pin Disable Register"
bitfld.long 0x00 31. " HETPINDIS_[31] ,NHET pin disable bit[31]" "No,Yes"
bitfld.long 0x00 30. " [30] ,NHET pin disable bit[30]" "No,Yes"
bitfld.long 0x00 29. " [29] ,NHET pin disable bit[29]" "No,Yes"
bitfld.long 0x00 28. " [28] ,NHET pin disable bit[28]" "No,Yes"
textline " "
bitfld.long 0x00 27. " [27] ,NHET pin disable bit[27]" "No,Yes"
bitfld.long 0x00 26. " [26] ,NHET pin disable bit[26]" "No,Yes"
bitfld.long 0x00 25. " [25] ,NHET pin disable bit[25]" "No,Yes"
bitfld.long 0x00 24. " [24] ,NHET pin disable bit[24]" "No,Yes"
textline " "
bitfld.long 0x00 23. " [23] ,NHET pin disable bit[23]" "No,Yes"
bitfld.long 0x00 22. " [22] ,NHET pin disable bit[22]" "No,Yes"
bitfld.long 0x00 21. " [21] ,NHET pin disable bit[21]" "No,Yes"
bitfld.long 0x00 20. " [20] ,NHET pin disable bit[20]" "No,Yes"
textline " "
bitfld.long 0x00 19. " [19] ,NHET pin disable bit[19]" "No,Yes"
bitfld.long 0x00 18. " [18] ,NHET pin disable bit[18]" "No,Yes"
bitfld.long 0x00 17. " [17] ,NHET pin disable bit[17]" "No,Yes"
bitfld.long 0x00 16. " [16] ,NHET pin disable bit[16]" "No,Yes"
textline " "
bitfld.long 0x00 15. " [15] ,NHET pin disable bit[15]" "No,Yes"
bitfld.long 0x00 14. " [14] ,NHET pin disable bit[14]" "No,Yes"
bitfld.long 0x00 13. " [13] ,NHET pin disable bit[13]" "No,Yes"
bitfld.long 0x00 12. " [12] ,NHET pin disable bit[12]" "No,Yes"
textline " "
bitfld.long 0x00 11. " [11] ,NHET pin disable bit[11]" "No,Yes"
bitfld.long 0x00 10. " [10] ,NHET pin disable bit[10]" "No,Yes"
bitfld.long 0x00 9. " [9] ,NHET pin disable bit[9]" "No,Yes"
bitfld.long 0x00 8. " [8] ,NHET pin disable bit[8]" "No,Yes"
textline " "
bitfld.long 0x00 7. " [7] ,NHET pin disable bit[7]" "No,Yes"
bitfld.long 0x00 6. " [6] ,NHET pin disable bit[6]" "No,Yes"
bitfld.long 0x00 5. " [5] ,NHET pin disable bit[5]" "No,Yes"
bitfld.long 0x00 4. " [4] ,NHET pin disable bit[4]" "No,Yes"
textline " "
bitfld.long 0x00 3. " [3] ,NHET pin disable bit[3]" "No,Yes"
bitfld.long 0x00 2. " [2] ,NHET pin disable bit[2]" "No,Yes"
bitfld.long 0x00 1. " [1] ,NHET pin disable bit[1]" "No,Yes"
bitfld.long 0x00 0. " [0] ,NHET pin disable bit[0]" "No,Yes"
sif (cpu()==("TMS570LS2126")||cpu()==("TMS570LS2127")||cpu()==("TMS570LS2136")||cpu()==("TMS570LS2137")||cpu()==("TMS570LS2125-PGE")||cpu()==("TMS570LS2125-ZWT")||cpu()==("TMS570LS2135-PGE")||cpu()==("TMS570LS2135-ZWT")||cpu()==("TMS570LS2124-PGE")||cpu()==("TMS570LS2124-ZWT")||cpu()==("TMS570LS2134-PGE")||cpu()==("TMS570LS2134-ZWT")||cpu()==("TMS570LS3134-PGE")||cpu()==("TMS570LS3134-ZWT")||cpu()==("TMS570LS3135-PGE")||cpu()==("TMS570LS3135-ZWT")||cpu()==("TMS570LS3136")||cpu()==("TMS570LS3137-PGE")||cpu()==("TMS570LS3137-ZWT")||cpu()==("TMS570LS30336")||cpuis("RM48L950*"))
group.long 0xA0++0x03
line.long 0x00 "HWAGCR0,HWAG Control Register 0"
group.long 0xA4++0x03
line.long 0x00 "HWAGCR1,HWAG Control Register 1"
group.long 0xA8++0x03
line.long 0x00 "HWAGCR2,HWAG Control Register 2"
group.long 0xAC++0x03
line.long 0x00 "HWAENASET,HWAG Interrupt Enable Set Register"
group.long 0xB0++0x03
line.long 0x00 "HWAENACLR,HWAG Interrupt Enable Clear Register"
group.long 0xB4++0x03
line.long 0x00 "HWALVLSET,HWAG Interrupt Priority Set Register"
group.long 0xB8++0x03
line.long 0x00 "HWALVLCLR,HWAG Interrupt Priority Clear Register"
group.long 0xBC++0x03
line.long 0x00 "HWAFLG,HWAG Interrupt Flags Register"
group.long 0xC0++0x03
line.long 0x00 "HWAOFF0,HWAG Interrupt Offset Register 1, HWAG Low Priority Interrupt Offset"
group.long 0xC4++0x03
line.long 0x00 "HWAOFF1,HWAG Interrupt Offset Register 2, HWAG High Priority Interrupt Offset"
group.long 0xC8++0x03
line.long 0x00 "HWAACNT,HWAG ACNT Register, HWAG Angle Value"
group.long 0xCC++0x03
line.long 0x00 "HWAPCNT1,HWAG PCNT (N-1) Register, HWAG Previous Tooth Period"
group.long 0xD0++0x03
line.long 0x00 "HWAPCNT,HWAG PCNT (N) Register, HWAG Current Tooth Period"
group.long 0xD4++0x03
line.long 0x00 "HWASTWD,HWAG Step Register"
group.long 0xD8++0x03
line.long 0x00 "HWATHNB,HWAG Teeth Number Register"
group.long 0xDC++0x03
line.long 0x00 "HWATHVL,HHWAG Current Teeth Number Register"
group.long 0xE0++0x03
line.long 0x00 "HWAFIL,HWAG Filter Register, HWAG Tick Counter Compare Value"
group.long 0xE8++0x03
line.long 0x00 "HWAFIL2,HWAG Filter Register 2, HWAG Tick Counter Compare Value During Singularity Tooth"
group.long 0xF0++0x03
line.long 0x00 "HWAANGI,HWAG Angle Increment Register"
endif
width 0x0B
tree.end
tree "N2HET2"
base ad:0xFFF7B900
width 11.
if ((d.l(ad:0xFFF7B900+0x00)&0x01)==0x01)
group.long 0x00++0x03
line.long 0x00 "GCR,Global Control Register"
bitfld.long 0x00 24. " HET_PIN_ENA ,NHET pin enable" "Disabled,Enabled"
bitfld.long 0x00 21.--22. " MP ,Master priority" "Lower,Higher,Round robin,?..."
bitfld.long 0x00 18. " PPF ,Protect program fields" "Unprotected,Protected"
textline " "
bitfld.long 0x00 17. " IS ,Ignore suspend" "Not ignored,Ignored"
bitfld.long 0x00 16. " CMS ,Clk_master/slave" "Slave,Master"
bitfld.long 0x00 0. " TO ,Turn on/off" "Off,On"
else
group.long 0x00++0x03
line.long 0x00 "GCR,Global Control Register"
bitfld.long 0x00 24. " HET_PIN_ENA ,NHET pin enable" "Disabled,Enabled"
bitfld.long 0x00 21.--22. " MP ,Master priority" "Lower,Higher,Round robin,?..."
bitfld.long 0x00 18. " PPF ,Protect program fields" "Unprotected,Unprotected"
textline " "
bitfld.long 0x00 17. " IS ,Ignore suspend" "Not ignored,Ignored"
bitfld.long 0x00 16. " CMS ,Clk_master/slave" "Slave,Master"
bitfld.long 0x00 0. " TO ,Turn on/off" "Off,On"
endif
group.long 0x04++0x03
line.long 0x00 "PFR,Prescaler Factor Register"
bitfld.long 0x00 8.--10. " LRPFC ,Loop resolution Pre-scale factor code" "1,2,4,8,16,32,64,128"
bitfld.long 0x00 0.--5. " HRPFC ,HR prescale factor code" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64"
rgroup.long 0x08++0x03
line.long 0x00 "ADDR,Current Address Register"
hexmask.long.word 0x00 0.--8. 1. " HETADDR[8:0] ,NHET current address"
hgroup.long 0x0C++0x03
hide.long 0x00 "OFF1,Offset Level 1 Register"
in
hgroup.long 0x10++0x03
hide.long 0x00 "OFF2,Offset Level 2 Register"
in
textline " "
group.long 0x14++0x03
line.long 0x00 "INTENA,Interrupt Enable Register"
setclrfld.long 0x00 31. 0x00 31. 0x04 31. " HETINTENA_SET/CLR_[31] ,Interrupt enable set pin 31" "Disabled,Enabled"
setclrfld.long 0x00 30. 0x00 30. 0x04 30. " [30] ,Interrupt enable set pin 30" "Disabled,Enabled"
setclrfld.long 0x00 29. 0x00 29. 0x04 29. " [29] ,Interrupt enable set pin 29" "Disabled,Enabled"
setclrfld.long 0x00 28. 0x00 28. 0x04 28. " [28] ,Interrupt enable set pin 28" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 27. 0x00 27. 0x04 27. " [27] ,Interrupt enable set pin 27" "Disabled,Enabled"
setclrfld.long 0x00 26. 0x00 26. 0x04 26. " [26] ,Interrupt enable set pin 26" "Disabled,Enabled"
setclrfld.long 0x00 25. 0x00 25. 0x04 25. " [25] ,Interrupt enable set pin 25" "Disabled,Enabled"
setclrfld.long 0x00 24. 0x00 24. 0x04 24. " [24] ,Interrupt enable set pin 24" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 23. 0x00 23. 0x04 23. " [23] ,Interrupt enable set pin 23" "Disabled,Enabled"
setclrfld.long 0x00 22. 0x00 22. 0x04 22. " [22] ,Interrupt enable set pin 22" "Disabled,Enabled"
setclrfld.long 0x00 21. 0x00 21. 0x04 21. " [21] ,Interrupt enable set pin 21" "Disabled,Enabled"
setclrfld.long 0x00 20. 0x00 20. 0x04 20. " [20] ,Interrupt enable set pin 20" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 19. 0x00 19. 0x04 19. " [19] ,Interrupt enable set pin 19" "Disabled,Enabled"
setclrfld.long 0x00 18. 0x00 18. 0x04 18. " [18] ,Interrupt enable set pin 18" "Disabled,Enabled"
setclrfld.long 0x00 17. 0x00 17. 0x04 17. " [17] ,Interrupt enable set pin 17" "Disabled,Enabled"
setclrfld.long 0x00 16. 0x00 16. 0x04 16. " [16] ,Interrupt enable set pin 16" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 15. 0x00 15. 0x04 15. " [15] ,Interrupt enable set pin 15" "Disabled,Enabled"
setclrfld.long 0x00 14. 0x00 14. 0x04 14. " [14] ,Interrupt enable set pin 14" "Disabled,Enabled"
setclrfld.long 0x00 13. 0x00 13. 0x04 13. " [13] ,Interrupt enable set pin 13" "Disabled,Enabled"
setclrfld.long 0x00 12. 0x00 12. 0x04 12. " [12] ,Interrupt enable set pin 12" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 11. 0x00 11. 0x04 11. " [11] ,Interrupt enable set pin 11" "Disabled,Enabled"
setclrfld.long 0x00 10. 0x00 10. 0x04 10. " [10] ,Interrupt enable set pin 10" "Disabled,Enabled"
setclrfld.long 0x00 9. 0x00 9. 0x04 9. " [9] ,Interrupt enable set pin 9" "Disabled,Enabled"
setclrfld.long 0x00 8. 0x00 8. 0x04 8. " [8] ,Interrupt enable set pin 8" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 7. 0x00 7. 0x04 7. " [7] ,Interrupt enable set pin 7" "Disabled,Enabled"
setclrfld.long 0x00 6. 0x00 6. 0x04 6. " [6] ,Interrupt enable set pin 6" "Disabled,Enabled"
setclrfld.long 0x00 5. 0x00 5. 0x04 5. " [5] ,Interrupt enable set pin 5" "Disabled,Enabled"
setclrfld.long 0x00 4. 0x00 4. 0x04 4. " [4] ,Interrupt enable set pin 4" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 3. 0x00 3. 0x04 3. " [3] ,Interrupt enable set pin 3" "Disabled,Enabled"
setclrfld.long 0x00 2. 0x00 2. 0x04 2. " [2] ,Interrupt enable set pin 2" "Disabled,Enabled"
setclrfld.long 0x00 1. 0x00 1. 0x04 1. " [1] ,Interrupt enable set pin 1" "Disabled,Enabled"
setclrfld.long 0x00 0. 0x00 0. 0x04 0. " [0] ,Interrupt enable set pin 0" "Disabled,Enabled"
textline " "
group.long 0x1C++0x03
line.long 0x00 "EXC1,Exception Control Register 1"
bitfld.long 0x00 24. " APCNT_OVRFL_ENA ,APCNT overflow enable" "Disabled,Enabled"
bitfld.long 0x00 16. " APCNT_UNDRFL_ENA ,APCNT underflow enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 8. " PRGM_OVRFL_ENA ,Program overflow enable" "Disabled,Enabled"
bitfld.long 0x00 2. " APCNT_OVRFL_ENA_PRY ,Apcnt_ovrfl_ena priority" "Level 2,Level 1"
textline " "
bitfld.long 0x00 1. " APCNT_UNDRFL_ENA_PRY ,Apcnt_undrfl_ena priority" "Level 2,Level 1"
bitfld.long 0x00 0. " PRGM_OVRFL_ENA_PRY ,Prgm_ovrfl_ena priority" "Level 2,Level 1"
group.long 0x20++0x03
line.long 0x00 "EXC2,Exception Control Register 2"
eventfld.long 0x00 8. " DEBUG_STATUS_FLG ,Debug_status flag" "No NHET,NHET"
eventfld.long 0x00 2. " APCNT_OVRFL_FLG ,APCNT overflow flag" "Not occurred,Occurred"
textline " "
eventfld.long 0x00 1. " APCNT_UNDRFL_FLG ,APCNT underflow flag" "Not occurred,Occurred"
eventfld.long 0x00 0. " PRGM_OVERFL_FLG ,Program overflow flag" "Not occurred,Occurred"
textline " "
group.long 0x24++0x03
line.long 0x00 "PRY,Interrupt Priority Register"
bitfld.long 0x00 31. " HETPRY[31] ,HET priority level bit[31]" "Level 2,Level 1"
bitfld.long 0x00 30. " [30] ,HET priority level bit[30]" "Level 2,Level 1"
bitfld.long 0x00 29. " [29] ,HET priority level bit[29]" "Level 2,Level 1"
bitfld.long 0x00 28. " [28] ,HET priority level bit[28]" "Level 2,Level 1"
textline " "
bitfld.long 0x00 27. " [27] ,HET priority level bit[27]" "Level 2,Level 1"
bitfld.long 0x00 26. " [26] ,HET priority level bit[26]" "Level 2,Level 1"
bitfld.long 0x00 25. " [25] ,HET priority level bit[25]" "Level 2,Level 1"
bitfld.long 0x00 24. " [24] ,HET priority level bit[24]" "Level 2,Level 1"
textline " "
bitfld.long 0x00 23. " [23] ,HET priority level bit[23]" "Level 2,Level 1"
bitfld.long 0x00 22. " [22] ,HET priority level bit[22]" "Level 2,Level 1"
bitfld.long 0x00 21. " [21] ,HET priority level bit[21]" "Level 2,Level 1"
bitfld.long 0x00 20. " [20] ,HET priority level bit[20]" "Level 2,Level 1"
textline " "
bitfld.long 0x00 19. " [19] ,HET priority level bit[19]" "Level 2,Level 1"
bitfld.long 0x00 18. " [18] ,HET priority level bit[18]" "Level 2,Level 1"
bitfld.long 0x00 17. " [17] ,HET priority level bit[17]" "Level 2,Level 1"
bitfld.long 0x00 16. " [16] ,HET priority level bit[16]" "Level 2,Level 1"
textline " "
bitfld.long 0x00 15. " [15] ,HET priority level bit[15]" "Level 2,Level 1"
bitfld.long 0x00 14. " [14] ,HET priority level bit[14]" "Level 2,Level 1"
bitfld.long 0x00 13. " [13] ,HET priority level bit[13]" "Level 2,Level 1"
bitfld.long 0x00 12. " [12] ,HET priority level bit[12]" "Level 2,Level 1"
textline " "
bitfld.long 0x00 11. " [11] ,HET priority level bit[11]" "Level 2,Level 1"
bitfld.long 0x00 10. " [10] ,HET priority level bit[10]" "Level 2,Level 1"
bitfld.long 0x00 9. " [9] ,HET priority level bit[9]" "Level 2,Level 1"
bitfld.long 0x00 8. " [8] ,HET priority level bit[8]" "Level 2,Level 1"
textline " "
bitfld.long 0x00 7. " [7] ,HET priority level bit[7]" "Level 2,Level 1"
bitfld.long 0x00 6. " [6] ,HET priority level bit[6]" "Level 2,Level 1"
bitfld.long 0x00 5. " [5] ,HET priority level bit[5]" "Level 2,Level 1"
bitfld.long 0x00 4. " [4] ,HET priority level bit[4]" "Level 2,Level 1"
textline " "
bitfld.long 0x00 3. " [3] ,HET priority level bit[3]" "Level 2,Level 1"
bitfld.long 0x00 2. " [2] ,HET priority level bit[2]" "Level 2,Level 1"
bitfld.long 0x00 1. " [1] ,HET priority level bit[1]" "Level 2,Level 1"
bitfld.long 0x00 0. " [0] ,HET priority level bit[0]" "Level 2,Level 1"
textline " "
group.long 0x28++0x03
line.long 0x00 "FLG,Interrupt Flag Register"
eventfld.long 0x00 31. " HETFLAG_[31] ,Interrupt flag register bit[31]" "No interrupt,Interrupt"
eventfld.long 0x00 30. " [30] ,Interrupt flag register bit[30]" "No interrupt,Interrupt"
eventfld.long 0x00 29. " [29] ,Interrupt flag register bit[29]" "No interrupt,Interrupt"
eventfld.long 0x00 28. " [28] ,Interrupt flag register bit[28]" "No interrupt,Interrupt"
textline " "
eventfld.long 0x00 27. " [27] ,Interrupt flag register bit[27]" "No interrupt,Interrupt"
eventfld.long 0x00 26. " [26] ,Interrupt flag register bit[26]" "No interrupt,Interrupt"
eventfld.long 0x00 25. " [25] ,Interrupt flag register bit[25]" "No interrupt,Interrupt"
eventfld.long 0x00 24. " [24] ,Interrupt flag register bit[24]" "No interrupt,Interrupt"
textline " "
eventfld.long 0x00 23. " [23] ,Interrupt flag register bit[23]" "No interrupt,Interrupt"
eventfld.long 0x00 22. " [22] ,Interrupt flag register bit[22]" "No interrupt,Interrupt"
eventfld.long 0x00 21. " [21] ,Interrupt flag register bit[21]" "No interrupt,Interrupt"
eventfld.long 0x00 20. " [20] ,Interrupt flag register bit[20]" "No interrupt,Interrupt"
textline " "
eventfld.long 0x00 19. " [19] ,Interrupt flag register bit[19]" "No interrupt,Interrupt"
eventfld.long 0x00 18. " [18] ,Interrupt flag register bit[18]" "No interrupt,Interrupt"
eventfld.long 0x00 17. " [17] ,Interrupt flag register bit[17]" "No interrupt,Interrupt"
eventfld.long 0x00 16. " [16] ,Interrupt flag register bit[16]" "No interrupt,Interrupt"
textline " "
eventfld.long 0x00 15. " [15] ,Interrupt flag register bit[15]" "No interrupt,Interrupt"
eventfld.long 0x00 14. " [14] ,Interrupt flag register bit[14]" "No interrupt,Interrupt"
eventfld.long 0x00 13. " [13] ,Interrupt flag register bit[13]" "No interrupt,Interrupt"
eventfld.long 0x00 12. " [12] ,Interrupt flag register bit[12]" "No interrupt,Interrupt"
textline " "
eventfld.long 0x00 11. " [11] ,Interrupt flag register bit[11]" "No interrupt,Interrupt"
eventfld.long 0x00 10. " [10] ,Interrupt flag register bit[10]" "No interrupt,Interrupt"
eventfld.long 0x00 9. " [9] ,Interrupt flag register bit[9]" "No interrupt,Interrupt"
eventfld.long 0x00 8. " [8] ,Interrupt flag register bit[8]" "No interrupt,Interrupt"
textline " "
eventfld.long 0x00 7. " [7] ,Interrupt flag register bit[7]" "No interrupt,Interrupt"
eventfld.long 0x00 6. " [6] ,Interrupt flag register bit[6]" "No interrupt,Interrupt"
eventfld.long 0x00 5. " [5] ,Interrupt flag register bit[5]" "No interrupt,Interrupt"
eventfld.long 0x00 4. " [4] ,Interrupt flag register bit[4]" "No interrupt,Interrupt"
textline " "
eventfld.long 0x00 3. " [3] ,Interrupt flag register bit[3]" "No interrupt,Interrupt"
eventfld.long 0x00 2. " [2] ,Interrupt flag register bit[2]" "No interrupt,Interrupt"
eventfld.long 0x00 1. " [1] ,Interrupt flag register bit[1]" "No interrupt,Interrupt"
eventfld.long 0x00 0. " [0] ,Interrupt flag register bit[0]" "No interrupt,Interrupt"
textline " "
sif (CPU()==("TMS570LS2124-PGE")||CPU()==("TMS570LS2124-ZWT")||CPU()==("TMS570LS2134-PGE")||CPU()==("TMS570LS2134-ZWT")||CPU()==("TMS570LS3134-PGE")||CPU()==("TMS570LS3134-ZWT")||CPU()==("TMS570LS3135-PGE")||CPU()==("TMS570LS3135-ZWT")||CPU()==("TMS570LS3136")||CPU()==("TMS570LS3137-PGE")||CPU()==("TMS570LS3137-ZWT")||CPU()==("TMS570LS30336")||CPU()==("TMS570LS2126")||CPU()==("TMS570LS2127")||CPU()==("TMS570LS2136")||CPU()==("TMS570LS2137")||CPU()==("TMS570LS2125-PGE")||CPU()==("TMS570LS2125-ZWT")||CPU()==("TMS570LS2135-PGE")||CPU()==("TMS570LS2135-ZWT")||CPU()==("RM48L950")||CPU()=="RM48L952-PGE"||CPU()=="RM48L950-PGE"||CPU()=="RM48L950-ZWT"||CPU()=="RM48L940-ZWT"||CPU()=="RM48L940-PGE"||CPU()=="RM48L930-ZWT"||CPU()=="RM48L930-PGE"||CPU()=="RM48L750-ZWT"||CPU()=="RM48L750-PGE"||CPU()=="RM48L740-ZWT"||CPU()=="RM48L740-PGE"||CPU()=="RM48L730-ZWT"||CPU()=="RM48L730-PGE"||CPU()=="RM48L550-PGE"||CPU()=="RM48L540-ZWT"||CPU()=="RM48L540-PGE"||CPU()=="RM48L530-ZWT"||CPU()=="RM48L530-PGE"||CPU()=="RM46L852-PGE"||CPU()=="RM46L852-ZWT"||CPU()=="RM46L850-PGE"||CPU()=="RM46L850-ZWT"||CPU()=="RM46L840-ZWT"||CPU()=="RM46L840-PGE"||CPU()=="RM46L830-ZWT"||CPU()=="RM46L830-PGE"||CPU()=="RM46L450-ZWT"||CPU()=="RM46L450-PGE"||CPU()=="RM46L440-ZWT"||CPU()=="RM46L440-PGE"||CPU()=="RM46L430-ZWT"||CPU()=="RM46L430-PGE"||CPU()=="RM42L432"||CPU()=="TMS570LC4357"||CPU()==("TMS570LS0332")||CPU()==("TMS570LS0432")||CPUIS("TMS570LS1114*")||CPUIS("TMS570LS1115*")||CPUIS("TMS570LS1224*")||CPUIS("TMS570LS1225*")||CPUIS("TMS570LS1227*")||cpu()=="RM57L843-ZWT")
group.long 0x2C++0x03
line.long 0x00 "HETAND,And Share Control Register"
bitfld.long 0x00 15. " AND_SHARE[31/30] ,AND share enable 31/30" "Not AND-shared,And-shared"
bitfld.long 0x00 14. " [29/28] ,AND share enable 29/28" "Not AND-shared,And-shared"
bitfld.long 0x00 13. " [27/26] ,AND share enable 27/26" "Not AND-shared,And-shared"
bitfld.long 0x00 12. " [25/24] ,AND share enable 25/24" "Not AND-shared,And-shared"
textline " "
bitfld.long 0x00 11. " [23/22] ,AND share enable 23/22" "Not AND-shared,And-shared"
bitfld.long 0x00 10. " [21/20] ,AND share enable 21/20" "Not AND-shared,And-shared"
bitfld.long 0x00 9. " [19/18] ,AND share enable 19/18" "Not AND-shared,And-shared"
bitfld.long 0x00 8. " [17/16] ,AND share enable 17/16" "Not AND-shared,And-shared"
textline " "
bitfld.long 0x00 7. " [15/14] ,AND share enable 15/14" "Not AND-shared,And-shared"
bitfld.long 0x00 6. " [13/12] ,AND share enable 13/12" "Not AND-shared,And-shared"
bitfld.long 0x00 5. " [11/10] ,AND share enable 11/10" "Not AND-shared,And-shared"
bitfld.long 0x00 4. " [9/8] ,AND share enable 9/8" "Not AND-shared,And-shared"
textline " "
bitfld.long 0x00 3. " [7/6] ,AND share enable 7/6" "Not AND-shared,And-shared"
bitfld.long 0x00 2. " [5/4] ,AND share enable 5/4" "Not AND-shared,And-shared"
bitfld.long 0x00 1. " [3/2] ,AND share enable 3/2" "Not AND-shared,And-shared"
bitfld.long 0x00 0. " [1/0] ,AND share enable 1/0" "Not AND-shared,And-shared"
textline " "
endif
group.long 0x34++0x03
line.long 0x00 "HRSH,HR Share Control Register"
bitfld.long 0x00 15. " HR_SHARE[31/30] ,HR share 31/30" "Not shared,Shared"
bitfld.long 0x00 14. " [29/28] ,HR share 29/28" "Not shared,Shared"
bitfld.long 0x00 13. " [27/26] ,HR share 27/26" "Not shared,Shared"
bitfld.long 0x00 12. " [25/24] ,HR share 25/24" "Not shared,Shared"
textline " "
bitfld.long 0x00 11. " [23/22] ,HR share 23/22" "Not shared,Shared"
bitfld.long 0x00 10. " [21/20] ,HR share 21/20" "Not shared,Shared"
bitfld.long 0x00 9. " [19/18] ,HR share 19/18" "Not shared,Shared"
bitfld.long 0x00 8. " [17/16] ,HR share 17/16" "Not shared,Shared"
textline " "
bitfld.long 0x00 7. " [15/14] ,HR share 15/14" "Not shared,Shared"
bitfld.long 0x00 6. " [13/12] ,HR share 13/12" "Not shared,Shared"
bitfld.long 0x00 5. " [11/10] ,HR share 11/10" "Not shared,Shared"
bitfld.long 0x00 4. " [9/8] ,HR share 9/8" "Not shared,Shared"
textline " "
bitfld.long 0x00 3. " [7/6] ,HR share 7/6" "Not shared,Shared"
bitfld.long 0x00 2. " [5/4] ,HR share 5/4" "Not shared,Shared"
bitfld.long 0x00 1. " [3/2] ,HR share 3/2" "Not shared,Shared"
bitfld.long 0x00 0. " [1/0] ,HR share 1/0" "Not shared,Shared"
textline " "
group.long 0x38++0x03
line.long 0x00 "XOR,HR XOR Control Register"
bitfld.long 0x00 15. " HR_XOR_SHARE_[31/30] ,HR XOR-Share 31/30" "Not XOR-shared,Xor-shared"
bitfld.long 0x00 14. " [29/28] ,HR XOR-Share 29/28" "Not XOR-shared,Xor-shared"
bitfld.long 0x00 13. " [27/26] ,HR XOR-Share 27/26" "Not XOR-shared,Xor-shared"
bitfld.long 0x00 12. " [25/24] ,HR XOR-Share 25/24" "Not XOR-shared,Xor-shared"
textline " "
bitfld.long 0x00 11. " [23/22] ,HR XOR-Share 23/22" "Not XOR-shared,Xor-shared"
bitfld.long 0x00 10. " [21/20] ,HR XOR-Share 21/20" "Not XOR-shared,Xor-shared"
bitfld.long 0x00 9. " [19/18] ,HR XOR-Share 19/18" "Not XOR-shared,Xor-shared"
bitfld.long 0x00 8. " [17/16] ,HR XOR-Share 17/16" "Not XOR-shared,Xor-shared"
textline " "
bitfld.long 0x00 7. " [15/14] ,HR XOR-Share 15/14" "Not XOR-shared,Xor-shared"
bitfld.long 0x00 6. " [13/12] ,HR XOR-Share 13/12" "Not XOR-shared,Xor-shared"
bitfld.long 0x00 5. " [11/10] ,HR XOR-Share 11/10" "Not XOR-shared,Xor-shared"
bitfld.long 0x00 4. " [9/8] ,HR XOR-Share 9/8" "Not XOR-shared,Xor-shared"
textline " "
bitfld.long 0x00 3. " [7/6] ,HR XOR-Share 7/6" "Not XOR-shared,Xor-shared"
bitfld.long 0x00 2. " [5/4] ,HR XOR-Share 5/4" "Not XOR-shared,Xor-shared"
bitfld.long 0x00 1. " [3/2] ,HR XOR-Share 3/2" "Not XOR-shared,Xor-shared"
bitfld.long 0x00 0. " [1/0] ,HR XOR-Share 1/0" "Not XOR-shared,Xor-shared"
textline " "
group.long 0x3C++0x03
line.long 0x00 "REQEN,Request Enable Register"
setclrfld.long 0x00 7. 0x00 7. 0x04 7. " REQENA_SET/CLR[7] ,Request enable bit[7]" "Disabled,Enabled"
setclrfld.long 0x00 6. 0x00 6. 0x04 6. " [6] ,Request enable bit[6]" "Disabled,Enabled"
setclrfld.long 0x00 5. 0x00 5. 0x04 5. " [5] ,Request enable bit[5]" "Disabled,Enabled"
setclrfld.long 0x00 4. 0x00 4. 0x04 4. " [4] ,Request enable bit[4]" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 3. 0x00 3. 0x04 3. " [3] ,Request enable bit[3]" "Disabled,Enabled"
setclrfld.long 0x00 2. 0x00 2. 0x04 2. " [2] ,Request enable bit[2]" "Disabled,Enabled"
setclrfld.long 0x00 1. 0x00 1. 0x04 1. " [1] ,Request enable bit[1]" "Disabled,Enabled"
setclrfld.long 0x00 0. 0x00 0. 0x04 0. " [0] ,Request enable bit[0]" "Disabled,Enabled"
textline " "
sif (cpu()!=("TMS570LS0332")&&cpu()!=("TMS570LS0432"))
group.long 0x44++0x03
line.long 0x00 "REQDS,Request Destination Select Register"
bitfld.long 0x00 7. 23. " TDS[7] ,HTU or DMA select bit[7]" "HTU,DMA,HTU & DMA,HTU & DMA"
bitfld.long 0x00 6. 22. " [6] ,HTU or DMA select bit[6]" "HTU,DMA,HTU & DMA,HTU & DMA"
bitfld.long 0x00 5. 21. " [5] ,HTU or DMA select bit[5]" "HTU,DMA,HTU & DMA,HTU & DMA"
bitfld.long 0x00 4. 20. " [4] ,HTU or DMA select bit[4]" "HTU,DMA,HTU & DMA,HTU & DMA"
textline " "
bitfld.long 0x00 3. 19. " [3] ,HTU or DMA select bit[3]" "HTU,DMA,HTU & DMA,HTU & DMA"
bitfld.long 0x00 2. 18. " [2] ,HTU or DMA select bit[2]" "HTU,DMA,HTU & DMA,HTU & DMA"
bitfld.long 0x00 1. 17. " [1] ,HTU or DMA select bit[1]" "HTU,DMA,HTU & DMA,HTU & DMA"
bitfld.long 0x00 0. 16. " [0] ,HTU or DMA select bit[0]" "HTU,DMA,HTU & DMA,HTU & DMA"
textline " "
endif
group.long 0x4C++0x03
line.long 0x00 "DIR,Direction Register"
bitfld.long 0x00 31. " HET_DIR[31] ,Input/output direction pin 31" "Input,Output"
bitfld.long 0x00 30. " [30] ,Input/output direction pin 30" "Input,Output"
bitfld.long 0x00 29. " [29] ,Input/output direction pin 29" "Input,Output"
bitfld.long 0x00 28. " [28] ,Input/output direction pin 28" "Input,Output"
textline " "
bitfld.long 0x00 27. " [27] ,Input/output direction pin 27" "Input,Output"
bitfld.long 0x00 26. " [26] ,Input/output direction pin 26" "Input,Output"
bitfld.long 0x00 25. " [25] ,Input/output direction pin 25" "Input,Output"
bitfld.long 0x00 24. " [24] ,Input/output direction pin 24" "Input,Output"
textline " "
bitfld.long 0x00 23. " [23] ,Input/output direction pin 23" "Input,Output"
bitfld.long 0x00 22. " [22] ,Input/output direction pin 22" "Input,Output"
bitfld.long 0x00 21. " [21] ,Input/output direction pin 21" "Input,Output"
bitfld.long 0x00 20. " [20] ,Input/output direction pin 20" "Input,Output"
textline " "
bitfld.long 0x00 19. " [19] ,Input/output direction pin 19" "Input,Output"
bitfld.long 0x00 18. " [18] ,Input/output direction pin 18" "Input,Output"
bitfld.long 0x00 17. " [17] ,Input/output direction pin 17" "Input,Output"
bitfld.long 0x00 16. " [16] ,Input/output direction pin 16" "Input,Output"
textline " "
bitfld.long 0x00 15. " [15] ,Input/output direction pin 15" "Input,Output"
bitfld.long 0x00 14. " [14] ,Input/output direction pin 14" "Input,Output"
bitfld.long 0x00 13. " [13] ,Input/output direction pin 13" "Input,Output"
bitfld.long 0x00 12. " [12] ,Input/output direction pin 12" "Input,Output"
textline " "
bitfld.long 0x00 11. " [11] ,Input/output direction pin 11" "Input,Output"
bitfld.long 0x00 10. " [10] ,Input/output direction pin 10" "Input,Output"
bitfld.long 0x00 9. " [9] ,Input/output direction pin 9" "Input,Output"
bitfld.long 0x00 8. " [8] ,Input/output direction pin 8" "Input,Output"
textline " "
bitfld.long 0x00 7. " [7] ,Input/output direction pin 7" "Input,Output"
bitfld.long 0x00 6. " [6] ,Input/output direction pin 6" "Input,Output"
bitfld.long 0x00 5. " [5] ,Input/output direction pin 5" "Input,Output"
bitfld.long 0x00 4. " [4] ,Input/output direction pin 4" "Input,Output"
textline " "
bitfld.long 0x00 3. " [3] ,Input/output direction pin 3" "Input,Output"
bitfld.long 0x00 2. " [2] ,Input/output direction pin 2" "Input,Output"
bitfld.long 0x00 1. " [1] ,Input/output direction pin 1" "Input,Output"
bitfld.long 0x00 0. " [0] ,Input/output direction pin 0" "Input,Output"
textline " "
rgroup.long 0x50++0x03
line.long 0x00 "DIN,Input Data Register"
bitfld.long 0x00 31. " HETDIN[31] ,NHET data input register pin 31" "Low,High"
bitfld.long 0x00 30. " [30] ,NHET data input register pin 30" "Low,High"
bitfld.long 0x00 29. " [29] ,NHET data input register pin 29" "Low,High"
bitfld.long 0x00 28. " [28] ,NHET data input register pin 28" "Low,High"
textline " "
bitfld.long 0x00 27. " [27] ,NHET data input register pin 27" "Low,High"
bitfld.long 0x00 26. " [26] ,NHET data input register pin 26" "Low,High"
bitfld.long 0x00 25. " [25] ,NHET data input register pin 25" "Low,High"
bitfld.long 0x00 24. " [24] ,NHET data input register pin 24" "Low,High"
textline " "
bitfld.long 0x00 23. " [23] ,NHET data input register pin 23" "Low,High"
bitfld.long 0x00 22. " [22] ,NHET data input register pin 22" "Low,High"
bitfld.long 0x00 21. " [21] ,NHET data input register pin 21" "Low,High"
bitfld.long 0x00 20. " [20] ,NHET data input register pin 20" "Low,High"
textline " "
bitfld.long 0x00 19. " [19] ,NHET data input register pin 19" "Low,High"
bitfld.long 0x00 18. " [18] ,NHET data input register pin 18" "Low,High"
bitfld.long 0x00 17. " [17] ,NHET data input register pin 17" "Low,High"
bitfld.long 0x00 16. " [16] ,NHET data input register pin 16" "Low,High"
textline " "
bitfld.long 0x00 15. " [15] ,NHET data input register pin 15" "Low,High"
bitfld.long 0x00 14. " [14] ,NHET data input register pin 14" "Low,High"
bitfld.long 0x00 13. " [13] ,NHET data input register pin 13" "Low,High"
bitfld.long 0x00 12. " [12] ,NHET data input register pin 12" "Low,High"
textline " "
bitfld.long 0x00 11. " [11] ,NHET data input register pin 11" "Low,High"
bitfld.long 0x00 10. " [10] ,NHET data input register pin 10" "Low,High"
bitfld.long 0x00 9. " [9] ,NHET data input register pin 9" "Low,High"
bitfld.long 0x00 8. " [8] ,NHET data input register pin 8" "Low,High"
textline " "
bitfld.long 0x00 7. " [7] ,NHET data input register pin 7" "Low,High"
bitfld.long 0x00 6. " [6] ,NHET data input register pin 6" "Low,High"
bitfld.long 0x00 5. " [5] ,NHET data input register pin 5" "Low,High"
bitfld.long 0x00 4. " [4] ,NHET data input register pin 4" "Low,High"
textline " "
bitfld.long 0x00 3. " [3] ,NHET data input register pin 3" "Low,High"
bitfld.long 0x00 2. " [2] ,NHET data input register pin 2" "Low,High"
bitfld.long 0x00 1. " [1] ,NHET data input register pin 1" "Low,High"
bitfld.long 0x00 0. " [0] ,NHET data input register pin 0" "Low,High"
textline " "
group.long 0x54++0x03
line.long 0x00 "DOUT,Output Data Register"
setclrfld.long 0x00 31. 0x04 31. 0x08 31. " HETDOUT_SET/CLR_[31] ,NHET data output register bit[31]" "Low,High"
setclrfld.long 0x00 30. 0x04 30. 0x08 30. " [30] ,NHET data output register bit[30]" "Low,High"
setclrfld.long 0x00 29. 0x04 29. 0x08 29. " [29] ,NHET data output register bit[29]" "Low,High"
setclrfld.long 0x00 28. 0x04 28. 0x08 28. " [28] ,NHET data output register bit[28]" "Low,High"
textline " "
setclrfld.long 0x00 27. 0x04 27. 0x08 27. " [27] ,NHET data output register bit[27]" "Low,High"
setclrfld.long 0x00 26. 0x04 26. 0x08 26. " [26] ,NHET data output register bit[26]" "Low,High"
setclrfld.long 0x00 25. 0x04 25. 0x08 25. " [25] ,NHET data output register bit[25]" "Low,High"
setclrfld.long 0x00 24. 0x04 24. 0x08 24. " [24] ,NHET data output register bit[24]" "Low,High"
textline " "
setclrfld.long 0x00 23. 0x04 23. 0x08 23. " [23] ,NHET data output register bit[23]" "Low,High"
setclrfld.long 0x00 22. 0x04 22. 0x08 22. " [22] ,NHET data output register bit[22]" "Low,High"
setclrfld.long 0x00 21. 0x04 21. 0x08 21. " [21] ,NHET data output register bit[21]" "Low,High"
setclrfld.long 0x00 20. 0x04 20. 0x08 20. " [20] ,NHET data output register bit[20]" "Low,High"
textline " "
setclrfld.long 0x00 19. 0x04 19. 0x08 19. " [19] ,NHET data output register bit[19]" "Low,High"
setclrfld.long 0x00 18. 0x04 18. 0x08 18. " [18] ,NHET data output register bit[18]" "Low,High"
setclrfld.long 0x00 17. 0x04 17. 0x08 17. " [17] ,NHET data output register bit[17]" "Low,High"
setclrfld.long 0x00 16. 0x04 16. 0x08 16. " [16] ,NHET data output register bit[16]" "Low,High"
textline " "
setclrfld.long 0x00 15. 0x04 15. 0x08 15. " [15] ,NHET data output register bit[15]" "Low,High"
setclrfld.long 0x00 14. 0x04 14. 0x08 14. " [14] ,NHET data output register bit[14]" "Low,High"
setclrfld.long 0x00 13. 0x04 13. 0x08 13. " [13] ,NHET data output register bit[13]" "Low,High"
setclrfld.long 0x00 12. 0x04 12. 0x08 12. " [12] ,NHET data output register bit[12]" "Low,High"
textline " "
setclrfld.long 0x00 11. 0x04 11. 0x08 11. " [11] ,NHET data output register bit[11]" "Low,High"
setclrfld.long 0x00 10. 0x04 10. 0x08 10. " [10] ,NHET data output register bit[10]" "Low,High"
setclrfld.long 0x00 9. 0x04 9. 0x08 9. " [9] ,NHET data output register bit[9]" "Low,High"
setclrfld.long 0x00 8. 0x04 8. 0x08 8. " [8] ,NHET data output register bit[8]" "Low,High"
textline " "
setclrfld.long 0x00 7. 0x04 7. 0x08 7. " [7] ,NHET data output register bit[7]" "Low,High"
setclrfld.long 0x00 6. 0x04 6. 0x08 6. " [6] ,NHET data output register bit[6]" "Low,High"
setclrfld.long 0x00 5. 0x04 5. 0x08 5. " [5] ,NHET data output register bit[5]" "Low,High"
setclrfld.long 0x00 4. 0x04 4. 0x08 4. " [4] ,NHET data output register bit[4]" "Low,High"
textline " "
setclrfld.long 0x00 3. 0x04 3. 0x08 3. " [3] ,NHET data output register bit[3]" "Low,High"
setclrfld.long 0x00 2. 0x04 2. 0x08 2. " [2] ,NHET data output register bit[2]" "Low,High"
setclrfld.long 0x00 1. 0x04 1. 0x08 1. " [1] ,NHET data output register bit[1]" "Low,High"
setclrfld.long 0x00 0. 0x04 0. 0x08 0. " [0] ,NHET data output register bit[0]" "Low,High"
textline " "
group.long 0x60++0x03
line.long 0x00 "PDR,Open Drain Register"
bitfld.long 0x00 31. " HETPDR[31] ,NHET open drain bit[31]" "Disabled,Enabled"
bitfld.long 0x00 30. " [30] ,NHET open drain bit[30]" "Disabled,Enabled"
bitfld.long 0x00 29. " [29] ,NHET open drain bit[29]" "Disabled,Enabled"
bitfld.long 0x00 28. " [28] ,NHET open drain bit[28]" "Disabled,Enabled"
textline " "
bitfld.long 0x00 27. " [27] ,NHET open drain bit[27]" "Disabled,Enabled"
bitfld.long 0x00 26. " [26] ,NHET open drain bit[26]" "Disabled,Enabled"
bitfld.long 0x00 25. " [25] ,NHET open drain bit[25]" "Disabled,Enabled"
bitfld.long 0x00 24. " [24] ,NHET open drain bit[24]" "Disabled,Enabled"
textline " "
bitfld.long 0x00 23. " [23] ,NHET open drain bit[23]" "Disabled,Enabled"
bitfld.long 0x00 22. " [22] ,NHET open drain bit[22]" "Disabled,Enabled"
bitfld.long 0x00 21. " [21] ,NHET open drain bit[21]" "Disabled,Enabled"
bitfld.long 0x00 20. " [20] ,NHET open drain bit[20]" "Disabled,Enabled"
textline " "
bitfld.long 0x00 19. " [19] ,NHET open drain bit[19]" "Disabled,Enabled"
bitfld.long 0x00 18. " [18] ,NHET open drain bit[18]" "Disabled,Enabled"
bitfld.long 0x00 17. " [17] ,NHET open drain bit[17]" "Disabled,Enabled"
bitfld.long 0x00 16. " [16] ,NHET open drain bit[16]" "Disabled,Enabled"
textline " "
bitfld.long 0x00 15. " [15] ,NHET open drain bit[15]" "Disabled,Enabled"
bitfld.long 0x00 14. " [14] ,NHET open drain bit[14]" "Disabled,Enabled"
bitfld.long 0x00 13. " [13] ,NHET open drain bit[13]" "Disabled,Enabled"
bitfld.long 0x00 12. " [12] ,NHET open drain bit[12]" "Disabled,Enabled"
textline " "
bitfld.long 0x00 11. " [11] ,NHET open drain bit[11]" "Disabled,Enabled"
bitfld.long 0x00 10. " [10] ,NHET open drain bit[10]" "Disabled,Enabled"
bitfld.long 0x00 9. " [9] ,NHET open drain bit[9]" "Disabled,Enabled"
bitfld.long 0x00 8. " [8] ,NHET open drain bit[8]" "Disabled,Enabled"
textline " "
bitfld.long 0x00 7. " [7] ,NHET open drain bit[7]" "Disabled,Enabled"
bitfld.long 0x00 6. " [6] ,NHET open drain bit[6]" "Disabled,Enabled"
bitfld.long 0x00 5. " [5] ,NHET open drain bit[5]" "Disabled,Enabled"
bitfld.long 0x00 4. " [4] ,NHET open drain bit[4]" "Disabled,Enabled"
textline " "
bitfld.long 0x00 3. " [3] ,NHET open drain bit[3]" "Disabled,Enabled"
bitfld.long 0x00 2. " [2] ,NHET open drain bit[2]" "Disabled,Enabled"
bitfld.long 0x00 1. " [1] ,NHET open drain bit[1]" "Disabled,Enabled"
bitfld.long 0x00 0. " [0] ,NHET open drain bit[0]" "Disabled,Enabled"
textline " "
group.long 0x64++0x03
line.long 0x00 "PULDIS,Pull Disable Register"
bitfld.long 0x00 31. " HETPULDIS[31] ,NHET pull disable bit[31]" "No,Yes"
bitfld.long 0x00 30. " [30] ,NHET pull disable bit[30]" "No,Yes"
bitfld.long 0x00 29. " [29] ,NHET pull disable bit[29]" "No,Yes"
bitfld.long 0x00 28. " [28] ,NHET pull disable bit[28]" "No,Yes"
textline " "
bitfld.long 0x00 27. " [27] ,NHET pull disable bit[27]" "No,Yes"
bitfld.long 0x00 26. " [26] ,NHET pull disable bit[26]" "No,Yes"
bitfld.long 0x00 25. " [25] ,NHET pull disable bit[25]" "No,Yes"
bitfld.long 0x00 24. " [24] ,NHET pull disable bit[24]" "No,Yes"
textline " "
bitfld.long 0x00 23. " [23] ,NHET pull disable bit[23]" "No,Yes"
bitfld.long 0x00 22. " [22] ,NHET pull disable bit[22]" "No,Yes"
bitfld.long 0x00 21. " [21] ,NHET pull disable bit[21]" "No,Yes"
bitfld.long 0x00 20. " [20] ,NHET pull disable bit[20]" "No,Yes"
textline " "
bitfld.long 0x00 19. " [19] ,NHET pull disable bit[19]" "No,Yes"
bitfld.long 0x00 18. " [18] ,NHET pull disable bit[18]" "No,Yes"
bitfld.long 0x00 17. " [17] ,NHET pull disable bit[17]" "No,Yes"
bitfld.long 0x00 16. " [16] ,NHET pull disable bit[16]" "No,Yes"
textline " "
bitfld.long 0x00 15. " [15] ,NHET pull disable bit[15]" "No,Yes"
bitfld.long 0x00 14. " [14] ,NHET pull disable bit[14]" "No,Yes"
bitfld.long 0x00 13. " [13] ,NHET pull disable bit[13]" "No,Yes"
bitfld.long 0x00 12. " [12] ,NHET pull disable bit[12]" "No,Yes"
textline " "
bitfld.long 0x00 11. " [11] ,NHET pull disable bit[11]" "No,Yes"
bitfld.long 0x00 10. " [10] ,NHET pull disable bit[10]" "No,Yes"
bitfld.long 0x00 9. " [9] ,NHET pull disable bit[9]" "No,Yes"
bitfld.long 0x00 8. " [8] ,NHET pull disable bit[8]" "No,Yes"
textline " "
bitfld.long 0x00 7. " [7] ,NHET pull disable bit[7]" "No,Yes"
bitfld.long 0x00 6. " [6] ,NHET pull disable bit[6]" "No,Yes"
bitfld.long 0x00 5. " [5] ,NHET pull disable bit[5]" "No,Yes"
bitfld.long 0x00 4. " [4] ,NHET pull disable bit[4]" "No,Yes"
textline " "
bitfld.long 0x00 3. " [3] ,NHET pull disable bit[3]" "No,Yes"
bitfld.long 0x00 2. " [2] ,NHET pull disable bit[2]" "No,Yes"
bitfld.long 0x00 1. " [1] ,NHET pull disable bit[1]" "No,Yes"
bitfld.long 0x00 0. " [0] ,NHET pull disable bit[0]" "No,Yes"
textline " "
group.long 0x68++0x03
line.long 0x00 "PSL,Pull Select Register"
bitfld.long 0x00 31. " HETPSL[31] ,NHET pull select bit[31]" "Pull down,Pull up"
bitfld.long 0x00 30. " [30] ,NHET pull select bit[30]" "Pull down,Pull up"
bitfld.long 0x00 29. " [29] ,NHET pull select bit[29]" "Pull down,Pull up"
bitfld.long 0x00 28. " [28] ,NHET pull select bit[28]" "Pull down,Pull up"
textline " "
bitfld.long 0x00 27. " [27] ,NHET pull select bit[27]" "Pull down,Pull up"
bitfld.long 0x00 26. " [26] ,NHET pull select bit[26]" "Pull down,Pull up"
bitfld.long 0x00 25. " [25] ,NHET pull select bit[25]" "Pull down,Pull up"
bitfld.long 0x00 24. " [24] ,NHET pull select bit[24]" "Pull down,Pull up"
textline " "
bitfld.long 0x00 23. " [23] ,NHET pull select bit[23]" "Pull down,Pull up"
bitfld.long 0x00 22. " [22] ,NHET pull select bit[22]" "Pull down,Pull up"
bitfld.long 0x00 21. " [21] ,NHET pull select bit[21]" "Pull down,Pull up"
bitfld.long 0x00 20. " [20] ,NHET pull select bit[20]" "Pull down,Pull up"
textline " "
bitfld.long 0x00 19. " [19] ,NHET pull select bit[19]" "Pull down,Pull up"
bitfld.long 0x00 18. " [18] ,NHET pull select bit[18]" "Pull down,Pull up"
bitfld.long 0x00 17. " [17] ,NHET pull select bit[17]" "Pull down,Pull up"
bitfld.long 0x00 16. " [16] ,NHET pull select bit[16]" "Pull down,Pull up"
textline " "
bitfld.long 0x00 15. " [15] ,NHET pull select bit[15]" "Pull down,Pull up"
bitfld.long 0x00 14. " [14] ,NHET pull select bit[14]" "Pull down,Pull up"
bitfld.long 0x00 13. " [13] ,NHET pull select bit[13]" "Pull down,Pull up"
bitfld.long 0x00 12. " [12] ,NHET pull select bit[12]" "Pull down,Pull up"
textline " "
bitfld.long 0x00 11. " [11] ,NHET pull select bit[11]" "Pull down,Pull up"
bitfld.long 0x00 10. " [10] ,NHET pull select bit[10]" "Pull down,Pull up"
bitfld.long 0x00 9. " [9] ,NHET pull select bit[9]" "Pull down,Pull up"
bitfld.long 0x00 8. " [8] ,NHET pull select bit[8]" "Pull down,Pull up"
textline " "
bitfld.long 0x00 7. " [7] ,NHET pull select bit[7]" "Pull down,Pull up"
bitfld.long 0x00 6. " [6] ,NHET pull select bit[6]" "Pull down,Pull up"
bitfld.long 0x00 5. " [5] ,NHET pull select bit[5]" "Pull down,Pull up"
bitfld.long 0x00 4. " [4] ,NHET pull select bit[4]" "Pull down,Pull up"
textline " "
bitfld.long 0x00 3. " [3] ,NHET pull select bit[3]" "Pull down,Pull up"
bitfld.long 0x00 2. " [2] ,NHET pull select bit[2]" "Pull down,Pull up"
bitfld.long 0x00 1. " [1] ,NHET pull select bit[1]" "Pull down,Pull up"
bitfld.long 0x00 0. " [0] ,NHET pull select bit[0]" "Pull down,Pull up"
textline " "
group.long 0x74++0x03
line.long 0x00 "PCR,Parity Control Register"
bitfld.long 0x00 8. " TEST ,Test bit - parity bits memory mapping" "Not mapped,Mapped"
bitfld.long 0x00 0.--3. " PARITY_ENA ,Enable / disable parity checking" "Enabled,Enabled,Enabled,Enabled,Enabled,Disabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled"
rgroup.long 0x78++0x03
line.long 0x00 "PAR,Parity Address Register"
hexmask.long.word 0x00 2.--12. 0x04 " PAOFF ,Parity error address offset"
textline " "
group.long 0x7C++0x03
line.long 0x00 "PPR,Parity Pin Register"
bitfld.long 0x00 31. " HETPPR_[31] ,NHET parity pin select bit[31]" "Not affected,Known state"
bitfld.long 0x00 30. " [30] ,NHET parity pin select bit[30]" "Not affected,Known state"
bitfld.long 0x00 29. " [29] ,NHET parity pin select bit[29]" "Not affected,Known state"
bitfld.long 0x00 28. " [28] ,NHET parity pin select bit[28]" "Not affected,Known state"
textline " "
bitfld.long 0x00 27. " [27] ,NHET parity pin select bit[27]" "Not affected,Known state"
bitfld.long 0x00 26. " [26] ,NHET parity pin select bit[26]" "Not affected,Known state"
bitfld.long 0x00 25. " [25] ,NHET parity pin select bit[25]" "Not affected,Known state"
bitfld.long 0x00 24. " [24] ,NHET parity pin select bit[24]" "Not affected,Known state"
textline " "
bitfld.long 0x00 23. " [23] ,NHET parity pin select bit[23]" "Not affected,Known state"
bitfld.long 0x00 22. " [22] ,NHET parity pin select bit[22]" "Not affected,Known state"
bitfld.long 0x00 21. " [21] ,NHET parity pin select bit[21]" "Not affected,Known state"
bitfld.long 0x00 20. " [20] ,NHET parity pin select bit[20]" "Not affected,Known state"
textline " "
bitfld.long 0x00 19. " [19] ,NHET parity pin select bit[19]" "Not affected,Known state"
bitfld.long 0x00 18. " [18] ,NHET parity pin select bit[18]" "Not affected,Known state"
bitfld.long 0x00 17. " [17] ,NHET parity pin select bit[17]" "Not affected,Known state"
bitfld.long 0x00 16. " [16] ,NHET parity pin select bit[16]" "Not affected,Known state"
textline " "
bitfld.long 0x00 15. " [15] ,NHET parity pin select bit[15]" "Not affected,Known state"
bitfld.long 0x00 14. " [14] ,NHET parity pin select bit[14]" "Not affected,Known state"
bitfld.long 0x00 13. " [13] ,NHET parity pin select bit[13]" "Not affected,Known state"
bitfld.long 0x00 12. " [12] ,NHET parity pin select bit[12]" "Not affected,Known state"
textline " "
bitfld.long 0x00 11. " [11] ,NHET parity pin select bit[11]" "Not affected,Known state"
bitfld.long 0x00 10. " [10] ,NHET parity pin select bit[10]" "Not affected,Known state"
bitfld.long 0x00 9. " [9] ,NHET parity pin select bit[9]" "Not affected,Known state"
bitfld.long 0x00 8. " [8] ,NHET parity pin select bit[8]" "Not affected,Known state"
textline " "
bitfld.long 0x00 7. " [7] ,NHET parity pin select bit[7]" "Not affected,Known state"
bitfld.long 0x00 6. " [6] ,NHET parity pin select bit[6]" "Not affected,Known state"
bitfld.long 0x00 5. " [5] ,NHET parity pin select bit[5]" "Not affected,Known state"
bitfld.long 0x00 4. " [4] ,NHET parity pin select bit[4]" "Not affected,Known state"
textline " "
bitfld.long 0x00 3. " [3] ,NHET parity pin select bit[3]" "Not affected,Known state"
bitfld.long 0x00 2. " [2] ,NHET parity pin select bit[2]" "Not affected,Known state"
bitfld.long 0x00 1. " [1] ,NHET parity pin select bit[1]" "Not affected,Known state"
bitfld.long 0x00 0. " [0] ,NHET parity pin select bit[0]" "Not affected,Known state"
textline " "
group.long 0x80++0x03
line.long 0x00 "SFPRLD,Suppresion Filter Preload Register"
bitfld.long 0x00 16.--17. " CCDIV ,Counter clock divider" "VCLK2,VCLK2/2,VCLK2/3,VCLK2/4"
hexmask.long.word 0x00 0.--9. 1. " CPRLD ,Counter preload value"
textline " "
group.long 0x84++0x03
line.long 0x00 "SFENA,Suppresion Filter Enable Register"
bitfld.long 0x00 31. " HETSFENA[31] ,Suppression filter enable bit[31]" "Disabled,Enabled"
bitfld.long 0x00 30. " [30] ,Suppression filter enable bit[30]" "Disabled,Enabled"
bitfld.long 0x00 29. " [29] ,Suppression filter enable bit[29]" "Disabled,Enabled"
bitfld.long 0x00 28. " [28] ,Suppression filter enable bit[28]" "Disabled,Enabled"
textline " "
bitfld.long 0x00 27. " [27] ,Suppression filter enable bit[27]" "Disabled,Enabled"
bitfld.long 0x00 26. " [26] ,Suppression filter enable bit[26]" "Disabled,Enabled"
bitfld.long 0x00 25. " [25] ,Suppression filter enable bit[25]" "Disabled,Enabled"
bitfld.long 0x00 24. " [24] ,Suppression filter enable bit[24]" "Disabled,Enabled"
textline " "
bitfld.long 0x00 23. " [23] ,Suppression filter enable bit[23]" "Disabled,Enabled"
bitfld.long 0x00 22. " [22] ,Suppression filter enable bit[22]" "Disabled,Enabled"
bitfld.long 0x00 21. " [21] ,Suppression filter enable bit[21]" "Disabled,Enabled"
bitfld.long 0x00 20. " [20] ,Suppression filter enable bit[20]" "Disabled,Enabled"
textline " "
bitfld.long 0x00 19. " [19] ,Suppression filter enable bit[19]" "Disabled,Enabled"
bitfld.long 0x00 18. " [18] ,Suppression filter enable bit[18]" "Disabled,Enabled"
bitfld.long 0x00 17. " [17] ,Suppression filter enable bit[17]" "Disabled,Enabled"
bitfld.long 0x00 16. " [16] ,Suppression filter enable bit[16]" "Disabled,Enabled"
textline " "
bitfld.long 0x00 15. " [15] ,Suppression filter enable bit[15]" "Disabled,Enabled"
bitfld.long 0x00 14. " [14] ,Suppression filter enable bit[14]" "Disabled,Enabled"
bitfld.long 0x00 13. " [13] ,Suppression filter enable bit[13]" "Disabled,Enabled"
bitfld.long 0x00 12. " [12] ,Suppression filter enable bit[12]" "Disabled,Enabled"
textline " "
bitfld.long 0x00 11. " [11] ,Suppression filter enable bit[11]" "Disabled,Enabled"
bitfld.long 0x00 10. " [10] ,Suppression filter enable bit[10]" "Disabled,Enabled"
bitfld.long 0x00 9. " [9] ,Suppression filter enable bit[9]" "Disabled,Enabled"
bitfld.long 0x00 8. " [8] ,Suppression filter enable bit[8]" "Disabled,Enabled"
textline " "
bitfld.long 0x00 7. " [7] ,Suppression filter enable bit[7]" "Disabled,Enabled"
bitfld.long 0x00 6. " [6] ,Suppression filter enable bit[6]" "Disabled,Enabled"
bitfld.long 0x00 5. " [5] ,Suppression filter enable bit[5]" "Disabled,Enabled"
bitfld.long 0x00 4. " [4] ,Suppression filter enable bit[4]" "Disabled,Enabled"
textline " "
bitfld.long 0x00 3. " [3] ,Suppression filter enable bit[3]" "Disabled,Enabled"
bitfld.long 0x00 2. " [2] ,Suppression filter enable bit[2]" "Disabled,Enabled"
bitfld.long 0x00 1. " [1] ,Suppression filter enable bit[1]" "Disabled,Enabled"
bitfld.long 0x00 0. " [0] ,Suppression filter enable bit[0]" "Disabled,Enabled"
textline " "
sif (cpu()!="RM48L952-PGE"&&cpu()!="RM48L950-PGE"&&cpu()!="RM48L950-ZWT"&&cpu()!="RM48L940-ZWT"&&cpu()!="RM48L940-PGE"&&cpu()!="RM48L930-ZWT"&&cpu()!="RM48L930-PGE"&&cpu()!="RM48L750-ZWT"&&cpu()!="RM48L750-PGE"&&cpu()!="RM48L740-ZWT"&&cpu()!="RM48L740-PGE"&&cpu()!="RM48L730-ZWT"&&cpu()!="RM48L730-PGE"&&cpu()!="RM48L550-PGE"&&cpu()!="RM48L540-ZWT"&&cpu()!="RM48L540-PGE"&&cpu()!="RM48L530-ZWT"&&cpu()!="RM48L530-PGE"&&cpu()!="RM46L852-PGE"&&cpu()!="RM46L852-ZWT"&&cpu()!="RM46L850-PGE"&&cpu()!="RM46L850-ZWT"&&cpu()!="RM46L840-ZWT"&&cpu()!="RM46L840-PGE"&&cpu()!="RM46L830-ZWT"&&cpu()!="RM46L830-PGE"&&cpu()!="RM46L450-ZWT"&&cpu()!="RM46L450-PGE"&&cpu()!="RM46L440-ZWT"&&cpu()!="RM46L440-PGE"&&cpu()!="RM46L430-ZWT"&&cpu()!="RM46L430-PGE"&&cpu()!="TMS570LC4357"&&cpu()!="RM48L550-ZWT"&&cpu()!="RM42L432"&&cpu()!="RM57L843-ZWT")
if ((d.l(ad:0xFFF7B900+0x90)&0xF00)==0xA00)
group.long 0x8C++0x03
line.long 0x00 "LBPSEL,Loop Back Pair Select Register"
bitfld.long 0x00 31. " LBPTYPE[15] ,Loop back pair type select bit[15]" "Digital,Analog"
bitfld.long 0x00 30. " [14] ,Loop back pair type select bit[14]" "Digital,Analog"
bitfld.long 0x00 29. " [13] ,Loop back pair type select bit[13]" "Digital,Analog"
bitfld.long 0x00 28. " [12] ,Loop back pair type select bit[12]" "Digital,Analog"
textline " "
bitfld.long 0x00 27. " [11] ,Loop back pair type select bit[11]" "Digital,Analog"
bitfld.long 0x00 26. " [10] ,Loop back pair type select bit[10]" "Digital,Analog"
bitfld.long 0x00 25. " [9] ,Loop back pair type select bit[9]" "Digital,Analog"
bitfld.long 0x00 24. " [8] ,Loop back pair type select bit[8]" "Digital,Analog"
textline " "
bitfld.long 0x00 23. " [7] ,Loop back pair type select bit[7]" "Digital,Analog"
bitfld.long 0x00 22. " [6] ,Loop back pair type select bit[6]" "Digital,Analog"
bitfld.long 0x00 21. " [5] ,Loop back pair type select bit[5]" "Digital,Analog"
bitfld.long 0x00 20. " [4] ,Loop back pair type select bit[4]" "Digital,Analog"
textline " "
bitfld.long 0x00 19. " [3] ,Loop back pair type select bit[3]" "Digital,Analog"
bitfld.long 0x00 18. " [2] ,Loop back pair type select bit[2]" "Digital,Analog"
bitfld.long 0x00 17. " [1] ,Loop back pair type select bit[1]" "Digital,Analog"
bitfld.long 0x00 16. " [0] ,Loop back pair type select bit[0]" "Digital,Analog"
textline " "
bitfld.long 0x00 15. " LBPSEL[15] ,Loop back pair select bit[15]" "Not selected,Selected"
bitfld.long 0x00 14. " [14] ,Loop back pair select bit[14]" "Not selected,Selected"
bitfld.long 0x00 13. " [13] ,Loop back pair select bit[13]" "Not selected,Selected"
bitfld.long 0x00 12. " [12] ,Loop back pair select bit[12]" "Not selected,Selected"
textline " "
bitfld.long 0x00 11. " [11] ,Loop back pair select bit[11]" "Not selected,Selected"
bitfld.long 0x00 10. " [10] ,Loop back pair select bit[10]" "Not selected,Selected"
bitfld.long 0x00 9. " [9] ,Loop back pair select bit[9]" "Not selected,Selected"
bitfld.long 0x00 8. " [8] ,Loop back pair select bit[8]" "Not selected,Selected"
textline " "
bitfld.long 0x00 7. " [7] ,Loop back pair select bit[7]" "Not selected,Selected"
bitfld.long 0x00 6. " [6] ,Loop back pair select bit[6]" "Not selected,Selected"
bitfld.long 0x00 5. " [5] ,Loop back pair select bit[5]" "Not selected,Selected"
bitfld.long 0x00 4. " [4] ,Loop back pair select bit[4]" "Not selected,Selected"
textline " "
bitfld.long 0x00 3. " [3] ,Loop back pair select bit[3]" "Not selected,Selected"
bitfld.long 0x00 2. " [2] ,Loop back pair select bit[2]" "Not selected,Selected"
bitfld.long 0x00 1. " [1] ,Loop back pair select bit[1]" "Not selected,Selected"
bitfld.long 0x00 0. " [0] ,Loop back pair select bit[0]" "Not selected,Selected"
else
hgroup.long 0x8C++0x03
hide.long 0x00 "LBPSEL,Loop Back Pair Select Register"
endif
else
if ((d.l(ad:0xFFF7B900+0x90)&0xF0000)==0xA0000)
group.long 0x8C++0x03
line.long 0x00 "LBPSEL,Loop Back Pair Select Register"
bitfld.long 0x00 31. " LBPTYPE[15] ,Loop back pair type select bit[15]" "Digital,Analog"
bitfld.long 0x00 30. " [14] ,Loop back pair type select bit[14]" "Digital,Analog"
bitfld.long 0x00 29. " [13] ,Loop back pair type select bit[13]" "Digital,Analog"
bitfld.long 0x00 28. " [12] ,Loop back pair type select bit[12]" "Digital,Analog"
textline " "
bitfld.long 0x00 27. " [11] ,Loop back pair type select bit[11]" "Digital,Analog"
bitfld.long 0x00 26. " [10] ,Loop back pair type select bit[10]" "Digital,Analog"
bitfld.long 0x00 25. " [9] ,Loop back pair type select bit[9]" "Digital,Analog"
bitfld.long 0x00 24. " [8] ,Loop back pair type select bit[8]" "Digital,Analog"
textline " "
bitfld.long 0x00 23. " [7] ,Loop back pair type select bit[7]" "Digital,Analog"
bitfld.long 0x00 22. " [6] ,Loop back pair type select bit[6]" "Digital,Analog"
bitfld.long 0x00 21. " [5] ,Loop back pair type select bit[5]" "Digital,Analog"
bitfld.long 0x00 20. " [4] ,Loop back pair type select bit[4]" "Digital,Analog"
textline " "
bitfld.long 0x00 19. " [3] ,Loop back pair type select bit[3]" "Digital,Analog"
bitfld.long 0x00 18. " [2] ,Loop back pair type select bit[2]" "Digital,Analog"
bitfld.long 0x00 17. " [1] ,Loop back pair type select bit[1]" "Digital,Analog"
bitfld.long 0x00 16. " [0] ,Loop back pair type select bit[0]" "Digital,Analog"
textline " "
bitfld.long 0x00 15. " LBPSEL[15] ,Loop back pair select bit[15]" "Not selected,Selected"
bitfld.long 0x00 14. " [14] ,Loop back pair select bit[14]" "Not selected,Selected"
bitfld.long 0x00 13. " [13] ,Loop back pair select bit[13]" "Not selected,Selected"
bitfld.long 0x00 12. " [12] ,Loop back pair select bit[12]" "Not selected,Selected"
textline " "
bitfld.long 0x00 11. " [11] ,Loop back pair select bit[11]" "Not selected,Selected"
bitfld.long 0x00 10. " [10] ,Loop back pair select bit[10]" "Not selected,Selected"
bitfld.long 0x00 9. " [9] ,Loop back pair select bit[9]" "Not selected,Selected"
bitfld.long 0x00 8. " [8] ,Loop back pair select bit[8]" "Not selected,Selected"
textline " "
bitfld.long 0x00 7. " [7] ,Loop back pair select bit[7]" "Not selected,Selected"
bitfld.long 0x00 6. " [6] ,Loop back pair select bit[6]" "Not selected,Selected"
bitfld.long 0x00 5. " [5] ,Loop back pair select bit[5]" "Not selected,Selected"
bitfld.long 0x00 4. " [4] ,Loop back pair select bit[4]" "Not selected,Selected"
textline " "
bitfld.long 0x00 3. " [3] ,Loop back pair select bit[3]" "Not selected,Selected"
bitfld.long 0x00 2. " [2] ,Loop back pair select bit[2]" "Not selected,Selected"
bitfld.long 0x00 1. " [1] ,Loop back pair select bit[1]" "Not selected,Selected"
bitfld.long 0x00 0. " [0] ,Loop back pair select bit[0]" "Not selected,Selected"
textline " "
else
hgroup.long 0x8C++0x03
hide.long 0x00 "LBPSEL,Loop Back Pair Select Register"
endif
endif
group.long 0x90++0x03
line.long 0x00 "LBPDIR,Loop Back Pair Direction Register"
sif cpu()=="RM57L843-ZWT"
bitfld.long 0x00 16.--19. " LBPTSTENA ,Loopback test enable key" "Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Enabled,Disabled,Disabled,Disabled,Disabled,Disabled"
else
bitfld.long 0x00 16.--19. " IODFTENA ,Module IODFT enable key" "Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Enabled,Disabled,Disabled,Disabled,Disabled,Disabled"
endif
textline " "
bitfld.long 0x00 15. " LBPDIR[15] ,Loop back pair direction bit[15]" "31 in/30 out,31 out/30 in"
bitfld.long 0x00 14. " [14] ,Loop back pair direction bit[14]" "29 in/28 out,29 out/28 in"
bitfld.long 0x00 13. " [13] ,Loop back pair direction bit[13]" "27 in/26 out,27 out/26 in"
bitfld.long 0x00 12. " [12] ,Loop back pair direction bit[12]" "25 in/24 out,25 out/24 in"
textline " "
bitfld.long 0x00 11. " [11] ,Loop back pair direction bit[11]" "23 in/22 out,23 out/22 in"
bitfld.long 0x00 10. " [10] ,Loop back pair direction bit[10]" "21 in/20 out,21 out/20 in"
bitfld.long 0x00 9. " [9] ,Loop back pair direction bit[9]" "19 in/18 out,19 out/18 in"
bitfld.long 0x00 8. " [8] ,Loop back pair direction bit[8]" "17 in/16 out,17 out/16 in"
textline " "
bitfld.long 0x00 7. " [7] ,Loop back pair direction bit[7]" "15 in/14 out,15 out/14 in"
bitfld.long 0x00 6. " [6] ,Loop back pair direction bit[6]" "13 in/12 out,13 out/12 in"
bitfld.long 0x00 5. " [5] ,Loop back pair direction bit[5]" "11 in/10 out,11 out/10 in"
bitfld.long 0x00 4. " [4] ,Loop back pair direction bit[4]" "9 in/8 out,9 out/8 in"
textline " "
bitfld.long 0x00 3. " [3] ,Loop back pair direction bit[3]" "7 in/6 out,7 out/6 in"
bitfld.long 0x00 2. " [2] ,Loop back pair direction bit[2]" "5 in/4 out,5 out/4 in"
bitfld.long 0x00 1. " [1] ,Loop back pair direction bit[1]" "3 in/2 out,3 out/2 in"
bitfld.long 0x00 0. " [0] ,Loop back pair direction bit[0]" "1 in/0 out,1 out/0 in"
textline " "
group.long 0x94++0x03
line.long 0x00 "PINDIS,Pin Disable Register"
bitfld.long 0x00 31. " HETPINDIS_[31] ,NHET pin disable bit[31]" "No,Yes"
bitfld.long 0x00 30. " [30] ,NHET pin disable bit[30]" "No,Yes"
bitfld.long 0x00 29. " [29] ,NHET pin disable bit[29]" "No,Yes"
bitfld.long 0x00 28. " [28] ,NHET pin disable bit[28]" "No,Yes"
textline " "
bitfld.long 0x00 27. " [27] ,NHET pin disable bit[27]" "No,Yes"
bitfld.long 0x00 26. " [26] ,NHET pin disable bit[26]" "No,Yes"
bitfld.long 0x00 25. " [25] ,NHET pin disable bit[25]" "No,Yes"
bitfld.long 0x00 24. " [24] ,NHET pin disable bit[24]" "No,Yes"
textline " "
bitfld.long 0x00 23. " [23] ,NHET pin disable bit[23]" "No,Yes"
bitfld.long 0x00 22. " [22] ,NHET pin disable bit[22]" "No,Yes"
bitfld.long 0x00 21. " [21] ,NHET pin disable bit[21]" "No,Yes"
bitfld.long 0x00 20. " [20] ,NHET pin disable bit[20]" "No,Yes"
textline " "
bitfld.long 0x00 19. " [19] ,NHET pin disable bit[19]" "No,Yes"
bitfld.long 0x00 18. " [18] ,NHET pin disable bit[18]" "No,Yes"
bitfld.long 0x00 17. " [17] ,NHET pin disable bit[17]" "No,Yes"
bitfld.long 0x00 16. " [16] ,NHET pin disable bit[16]" "No,Yes"
textline " "
bitfld.long 0x00 15. " [15] ,NHET pin disable bit[15]" "No,Yes"
bitfld.long 0x00 14. " [14] ,NHET pin disable bit[14]" "No,Yes"
bitfld.long 0x00 13. " [13] ,NHET pin disable bit[13]" "No,Yes"
bitfld.long 0x00 12. " [12] ,NHET pin disable bit[12]" "No,Yes"
textline " "
bitfld.long 0x00 11. " [11] ,NHET pin disable bit[11]" "No,Yes"
bitfld.long 0x00 10. " [10] ,NHET pin disable bit[10]" "No,Yes"
bitfld.long 0x00 9. " [9] ,NHET pin disable bit[9]" "No,Yes"
bitfld.long 0x00 8. " [8] ,NHET pin disable bit[8]" "No,Yes"
textline " "
bitfld.long 0x00 7. " [7] ,NHET pin disable bit[7]" "No,Yes"
bitfld.long 0x00 6. " [6] ,NHET pin disable bit[6]" "No,Yes"
bitfld.long 0x00 5. " [5] ,NHET pin disable bit[5]" "No,Yes"
bitfld.long 0x00 4. " [4] ,NHET pin disable bit[4]" "No,Yes"
textline " "
bitfld.long 0x00 3. " [3] ,NHET pin disable bit[3]" "No,Yes"
bitfld.long 0x00 2. " [2] ,NHET pin disable bit[2]" "No,Yes"
bitfld.long 0x00 1. " [1] ,NHET pin disable bit[1]" "No,Yes"
bitfld.long 0x00 0. " [0] ,NHET pin disable bit[0]" "No,Yes"
sif (cpu()==("TMS570LS2126")||cpu()==("TMS570LS2127")||cpu()==("TMS570LS2136")||cpu()==("TMS570LS2137")||cpu()==("TMS570LS2125-PGE")||cpu()==("TMS570LS2125-ZWT")||cpu()==("TMS570LS2135-PGE")||cpu()==("TMS570LS2135-ZWT")||cpu()==("TMS570LS2124-PGE")||cpu()==("TMS570LS2124-ZWT")||cpu()==("TMS570LS2134-PGE")||cpu()==("TMS570LS2134-ZWT")||cpu()==("TMS570LS3134-PGE")||cpu()==("TMS570LS3134-ZWT")||cpu()==("TMS570LS3135-PGE")||cpu()==("TMS570LS3135-ZWT")||cpu()==("TMS570LS3136")||cpu()==("TMS570LS3137-PGE")||cpu()==("TMS570LS3137-ZWT")||cpu()==("TMS570LS30336")||cpuis("RM48L950*"))
group.long 0xA0++0x03
line.long 0x00 "HWAGCR0,HWAG Control Register 0"
group.long 0xA4++0x03
line.long 0x00 "HWAGCR1,HWAG Control Register 1"
group.long 0xA8++0x03
line.long 0x00 "HWAGCR2,HWAG Control Register 2"
group.long 0xAC++0x03
line.long 0x00 "HWAENASET,HWAG Interrupt Enable Set Register"
group.long 0xB0++0x03
line.long 0x00 "HWAENACLR,HWAG Interrupt Enable Clear Register"
group.long 0xB4++0x03
line.long 0x00 "HWALVLSET,HWAG Interrupt Priority Set Register"
group.long 0xB8++0x03
line.long 0x00 "HWALVLCLR,HWAG Interrupt Priority Clear Register"
group.long 0xBC++0x03
line.long 0x00 "HWAFLG,HWAG Interrupt Flags Register"
group.long 0xC0++0x03
line.long 0x00 "HWAOFF0,HWAG Interrupt Offset Register 1, HWAG Low Priority Interrupt Offset"
group.long 0xC4++0x03
line.long 0x00 "HWAOFF1,HWAG Interrupt Offset Register 2, HWAG High Priority Interrupt Offset"
group.long 0xC8++0x03
line.long 0x00 "HWAACNT,HWAG ACNT Register, HWAG Angle Value"
group.long 0xCC++0x03
line.long 0x00 "HWAPCNT1,HWAG PCNT (N-1) Register, HWAG Previous Tooth Period"
group.long 0xD0++0x03
line.long 0x00 "HWAPCNT,HWAG PCNT (N) Register, HWAG Current Tooth Period"
group.long 0xD4++0x03
line.long 0x00 "HWASTWD,HWAG Step Register"
group.long 0xD8++0x03
line.long 0x00 "HWATHNB,HWAG Teeth Number Register"
group.long 0xDC++0x03
line.long 0x00 "HWATHVL,HHWAG Current Teeth Number Register"
group.long 0xE0++0x03
line.long 0x00 "HWAFIL,HWAG Filter Register, HWAG Tick Counter Compare Value"
group.long 0xE8++0x03
line.long 0x00 "HWAFIL2,HWAG Filter Register 2, HWAG Tick Counter Compare Value During Singularity Tooth"
group.long 0xF0++0x03
line.long 0x00 "HWAANGI,HWAG Angle Increment Register"
endif
width 0x0B
tree.end
tree.end
tree.open "HTU (High-End Timer Transfer Unit Module)"
tree "HTU1"
base ad:0xFFF7A400
width 10.
group.long 0x00++0x03
line.long 0x00 "GC,Global Control Register"
bitfld.long 0x00 24. " VBUS_HOLD ,Hold the VBUS bus" "Not held,Held"
bitfld.long 0x00 16. " HTUEN ,Transfer unit enable bit" "Disabled,Enabled"
bitfld.long 0x00 8. " DEBM ,Debug mode" "Suspended,Continue"
textline " "
bitfld.long 0x00 0. " HTU_RES ,HTU software reset" "No reset,Reset"
textline " "
group.long 0x04++0x03
line.long 0x00 "CPENA,Control Packet Enable Register"
bitfld.long 0x00 14.--15. " CPENA_[7] ,CP enable bits 7 (Cp A/CP B)" "(R) DCP disabled,(Rw) A enabled/b disabled,(Rw) A disabled/b enabled,(W) disable DCP"
bitfld.long 0x00 12.--13. " [6] ,CP enable bits 6 (Cp A/CP B)" "(R) DCP disabled,(Rw) A enabled/b disabled,(Rw) A disabled/b enabled,(W) disable DCP"
bitfld.long 0x00 10.--11. " [5] ,CP enable bits 5 (Cp A/CP B)" "(R) DCP disabled,(Rw) A enabled/b disabled,(Rw) A disabled/b enabled,(W) disable DCP"
bitfld.long 0x00 8.--9. " [4] ,CP enable bits 4 (Cp A/CP B)" "(R) DCP disabled,(Rw) A enabled/b disabled,(Rw) A disabled/b enabled,(W) disable DCP"
textline " "
bitfld.long 0x00 6.--7. " [3] ,CP enable bits 3 (Cp A/CP B)" "(R) DCP disabled,(Rw) A enabled/b disabled,(Rw) A disabled/b enabled,(W) disable DCP"
bitfld.long 0x00 4.--5. " [2] ,CP enable bits 2 (Cp A/CP B)" "(R) DCP disabled,(Rw) A enabled/b disabled,(Rw) A disabled/b enabled,(W) disable DCP"
bitfld.long 0x00 2.--3. " [1] ,CP enable bits 1 (Cp A/CP B)" "(R) DCP disabled,(Rw) A enabled/b disabled,(Rw) A disabled/b enabled,(W) disable DCP"
bitfld.long 0x00 0.--1. " [0] ,CP enable bits 0 (Cp A/CP B)" "(R) DCP disabled,(Rw) A enabled/b disabled,(Rw) A disabled/b enabled,(W) disable DCP"
textline " "
group.long 0x08++0x03
line.long 0x00 "BUSY0,Control Packet (Cp) Busy Register 0"
eventfld.long 0x00 24. " BUSY_[0A] ,Busy flag for CP A of double CP 0" "Not busy,Busy"
eventfld.long 0x00 16. " [0B] ,Busy flag for CP B of double CP 0" "Not busy,Busy"
eventfld.long 0x00 8. " [1A] ,Busy flag for CP A of double CP 1" "Not busy,Busy"
eventfld.long 0x00 0. " [1B] ,Busy flag for CP B of double CP 1" "Not busy,Busy"
group.long 0x0C++0x03
line.long 0x00 "BUSY1,Control Packet (Cp) Busy Register 1"
eventfld.long 0x00 24. " BUSY_[2A] ,Busy flag for CP A of double CP 2" "Not busy,Busy"
eventfld.long 0x00 16. " [2B] ,Busy flag for CP B of double CP 2" "Not busy,Busy"
eventfld.long 0x00 8. " [3A] ,Busy flag for CP A of double CP 3" "Not busy,Busy"
eventfld.long 0x00 0. " [3B] ,Busy flag for CP B of double CP 3" "Not busy,Busy"
group.long 0x10++0x03
line.long 0x00 "BUSY2,Control Packet (Cp) Busy Register 2"
eventfld.long 0x00 24. " BUSY_[4A] ,Busy flag for CP A of double CP 4" "Not busy,Busy"
eventfld.long 0x00 16. " [4B] ,Busy flag for CP B of double CP 4" "Not busy,Busy"
eventfld.long 0x00 8. " [5A] ,Busy flag for CP A of double CP 5" "Not busy,Busy"
eventfld.long 0x00 0. " [5B] ,Busy flag for CP B of double CP 5" "Not busy,Busy"
group.long 0x14++0x03
line.long 0x00 "BUSY3,Control Packet (Cp) Busy Register 3"
eventfld.long 0x00 24. " BUSY_[6A] ,Busy flag for CP A of double CP 6" "Not busy,Busy"
eventfld.long 0x00 16. " [6B] ,Busy flag for CP B of double CP 6" "Not busy,Busy"
eventfld.long 0x00 8. " [7A] ,Busy flag for CP A of double CP 7" "Not busy,Busy"
eventfld.long 0x00 0. " [7B] ,Busy flag for CP B of double CP 7" "Not busy,Busy"
textline " "
group.long 0x18++0x03
line.long 0x00 "ACPE,Active Control Packet Register"
eventfld.long 0x00 31. " ERRF ,Error flag" "No error,Error"
rbitfld.long 0x00 24.--28. " ERRETC ,Error element transfer counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
rbitfld.long 0x00 16.--19. " ERRCPN ,Error control packet number" "CP A of DCP0,CP B of DCP0,CP A of DCP1,CP B of DCP1,CP A of DCP2,CP B of DCP2,CP A of DCP3,CP B of DCP3,CP A of DCP4,CP B of DCP4,CP A of DCP5,CP B of DCP5,CP A of DCP6,CP B of DCP6,CP A of DCP7,CP B of DCP7"
textline " "
rbitfld.long 0x00 15. " TIPF ,Transfer in progress flag" "Not active,Active"
rbitfld.long 0x00 14. " BUS_BUSY ,VBUSP bus is busy" "Not busy,Busy"
rbitfld.long 0x00 8.--12. " CETCOUNT ,Current element transfer counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline " "
rbitfld.long 0x00 0.--3. " NACP ,Number of active control packet" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x20++0x03
line.long 0x00 "RLBECTRL,Request Lost And Bus Error Control Register"
bitfld.long 0x00 16. " BERINTENA ,Bus error interrupt enable bit" "Disabled,Enabled"
bitfld.long 0x00 8. " CORL ,Continue on request lost error" "Lost,Continue"
bitfld.long 0x00 0. " RLINTENA ,Request lost interrupt enable bit" "Disabled,Enabled"
textline " "
group.long 0x24++0x03
line.long 0x00 "BFINT,Buffer Full Interrupt Enable Set Register"
setclrfld.long 0x00 15. 0x00 15. 0x04 15. " BFINTENA_SET/CLR_[15] ,CP B buffer full interrupt enable bit 15" "Disabled,Enabled"
setclrfld.long 0x00 14. 0x00 14. 0x04 14. " [14] ,CP A buffer full interrupt enable bit 14" "Disabled,Enabled"
setclrfld.long 0x00 13. 0x00 13. 0x04 13. " [13] ,CP B buffer full interrupt enable bit 13" "Disabled,Enabled"
setclrfld.long 0x00 12. 0x00 12. 0x04 12. " [12] ,CP A buffer full interrupt enable bit 12" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 11. 0x00 11. 0x04 11. " [11] ,CP B buffer full interrupt enable bit 11" "Disabled,Enabled"
setclrfld.long 0x00 10. 0x00 10. 0x04 10. " [10] ,CP A buffer full interrupt enable bit 10" "Disabled,Enabled"
setclrfld.long 0x00 9. 0x00 9. 0x04 9. " [9] ,CP B buffer full interrupt enable bit 9" "Disabled,Enabled"
setclrfld.long 0x00 8. 0x00 8. 0x04 8. " [8] ,CP A buffer full interrupt enable bit 8" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 7. 0x00 7. 0x04 7. " [7] ,CP B buffer full interrupt enable bit 7" "Disabled,Enabled"
setclrfld.long 0x00 6. 0x00 6. 0x04 6. " [6] ,CP A buffer full interrupt enable bit 6" "Disabled,Enabled"
setclrfld.long 0x00 5. 0x00 5. 0x04 5. " [5] ,CP B buffer full interrupt enable bit 5" "Disabled,Enabled"
setclrfld.long 0x00 4. 0x00 4. 0x04 4. " [4] ,CP A buffer full interrupt enable bit 4" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 3. 0x00 3. 0x04 3. " [3] ,CP B buffer full interrupt enable bit 3" "Disabled,Enabled"
setclrfld.long 0x00 2. 0x00 2. 0x04 2. " [2] ,CP A buffer full interrupt enable bit 2" "Disabled,Enabled"
setclrfld.long 0x00 1. 0x00 1. 0x04 1. " [1] ,CP B buffer full interrupt enable bit 1" "Disabled,Enabled"
setclrfld.long 0x00 0. 0x00 0. 0x04 0. " [0] ,CP A buffer full interrupt enable bit 0" "Disabled,Enabled"
textline " "
group.long 0x2C++0x03
line.long 0x00 "INTMAP,Interrupt Mapping Register"
bitfld.long 0x00 16. " MAPSEL ,Interrupt mapping select bit" "Low,High"
textline " "
bitfld.long 0x00 15. " CPINTMAP_[15] ,CP B interrupt mapping bit 15" "Line 0,Line 1"
bitfld.long 0x00 14. " [14] ,CP A interrupt mapping bit 14" "Line 0,Line 1"
bitfld.long 0x00 13. " [13] ,CP B interrupt mapping bit 13" "Line 0,Line 1"
bitfld.long 0x00 12. " [12] ,CP A interrupt mapping bit 12" "Line 0,Line 1"
textline " "
bitfld.long 0x00 11. " [11] ,CP B interrupt mapping bit 11" "Line 0,Line 1"
bitfld.long 0x00 10. " [10] ,CP A interrupt mapping bit 10" "Line 0,Line 1"
bitfld.long 0x00 9. " [9] ,CP B interrupt mapping bit 9" "Line 0,Line 1"
bitfld.long 0x00 8. " [8] ,CP A interrupt mapping bit 8" "Line 0,Line 1"
textline " "
bitfld.long 0x00 7. " [7] ,CP B interrupt mapping bit 7" "Line 0,Line 1"
bitfld.long 0x00 6. " [6] ,CP A interrupt mapping bit 6" "Line 0,Line 1"
bitfld.long 0x00 5. " [5] ,CP B interrupt mapping bit 5" "Line 0,Line 1"
bitfld.long 0x00 4. " [4] ,CP A interrupt mapping bit 4" "Line 0,Line 1"
textline " "
bitfld.long 0x00 3. " [3] ,CP B interrupt mapping bit 3" "Line 0,Line 1"
bitfld.long 0x00 2. " [2] ,CP A interrupt mapping bit 2" "Line 0,Line 1"
bitfld.long 0x00 1. " [1] ,CP B interrupt mapping bit 1" "Line 0,Line 1"
bitfld.long 0x00 0. " [0] ,CP A interrupt mapping bit 0" "Line 0,Line 1"
hgroup.long 0x34++0x03
hide.long 0x00 "INTOFF0,Interrupt Offset Register 0"
in
hgroup.long 0x38++0x03
hide.long 0x00 "INTOFF1,Interrupt Offset Register 1"
in
textline " "
group.long 0x3C++0x03
line.long 0x00 "BIM,Buffer Initialization Mode Register"
bitfld.long 0x00 7. " BIM[7] ,Buffer initialization mode bit 7" "Normal,Special"
bitfld.long 0x00 6. " [6] ,Buffer initialization mode bit 6" "Normal,Special"
bitfld.long 0x00 5. " [5] ,Buffer initialization mode bit 5" "Normal,Special"
bitfld.long 0x00 4. " [4] ,Buffer initialization mode bit 4" "Normal,Special"
textline " "
bitfld.long 0x00 3. " [3] ,Buffer initialization mode bit 3" "Normal,Special"
bitfld.long 0x00 2. " [2] ,Buffer initialization mode bit 2" "Normal,Special"
bitfld.long 0x00 1. " [1] ,Buffer initialization mode bit 1" "Normal,Special"
bitfld.long 0x00 0. " [0] ,Buffer initialization mode bit 0" "Normal,Special"
textline " "
group.long 0x40++0x03
line.long 0x00 "RLOSTFL,Request Lost Flag Register"
eventfld.long 0x00 15. " CPRLFL[15] ,CP B request lost flag 15" "Not requested,Requested"
eventfld.long 0x00 14. " [14] ,CP A request lost flag 14" "Not requested,Requested"
eventfld.long 0x00 13. " [13] ,CP B request lost flag 13" "Not requested,Requested"
eventfld.long 0x00 12. " [12] ,CP A request lost flag 12" "Not requested,Requested"
textline " "
eventfld.long 0x00 11. " [11] ,CP B request lost flag 11" "Not requested,Requested"
eventfld.long 0x00 10. " [10] ,CP A request lost flag 10" "Not requested,Requested"
eventfld.long 0x00 9. " [9] ,CP B request lost flag 9" "Not requested,Requested"
eventfld.long 0x00 8. " [8] ,CP A request lost flag 8" "Not requested,Requested"
textline " "
eventfld.long 0x00 7. " [7] ,CP B request lost flag 7" "Not requested,Requested"
eventfld.long 0x00 6. " [6] ,CP A request lost flag 6" "Not requested,Requested"
eventfld.long 0x00 5. " [5] ,CP B request lost flag 5" "Not requested,Requested"
eventfld.long 0x00 4. " [4] ,CP A request lost flag 4" "Not requested,Requested"
textline " "
eventfld.long 0x00 3. " [3] ,CP B request lost flag 3" "Not requested,Requested"
eventfld.long 0x00 2. " [2] ,CP A request lost flag 2" "Not requested,Requested"
eventfld.long 0x00 1. " [1] ,CP B request lost flag 1" "Not requested,Requested"
eventfld.long 0x00 0. " [0] ,CP A request lost flag 0" "Not requested,Requested"
textline " "
group.long 0x44++0x03
line.long 0x00 "BFINTFL,Buffer Full Interrupt Flag Register"
eventfld.long 0x00 15. " BFINTFL[15] ,CP B buffer full interrupt flag 15" "No interrupt,Interrupt"
eventfld.long 0x00 14. " [14] ,CP A buffer full interrupt flag 14" "No interrupt,Interrupt"
eventfld.long 0x00 13. " [13] ,CP B buffer full interrupt flag 13" "No interrupt,Interrupt"
eventfld.long 0x00 12. " [12] ,CP A buffer full interrupt flag 12" "No interrupt,Interrupt"
textline " "
eventfld.long 0x00 11. " [11] ,CP B buffer full interrupt flag 11" "No interrupt,Interrupt"
eventfld.long 0x00 10. " [10] ,CP A buffer full interrupt flag 10" "No interrupt,Interrupt"
eventfld.long 0x00 9. " [9] ,CP B buffer full interrupt flag 9" "No interrupt,Interrupt"
eventfld.long 0x00 8. " [8] ,CP A buffer full interrupt flag 8" "No interrupt,Interrupt"
textline " "
eventfld.long 0x00 7. " [7] ,CP B buffer full interrupt flag 7" "No interrupt,Interrupt"
eventfld.long 0x00 6. " [6] ,CP A buffer full interrupt flag 6" "No interrupt,Interrupt"
eventfld.long 0x00 5. " [5] ,CP B buffer full interrupt flag 5" "No interrupt,Interrupt"
eventfld.long 0x00 4. " [4] ,CP A buffer full interrupt flag 4" "No interrupt,Interrupt"
textline " "
eventfld.long 0x00 3. " [3] ,CP B buffer full interrupt flag 3" "No interrupt,Interrupt"
eventfld.long 0x00 2. " [2] ,CP A buffer full interrupt flag 2" "No interrupt,Interrupt"
eventfld.long 0x00 1. " [1] ,CP B buffer full interrupt flag 1" "No interrupt,Interrupt"
eventfld.long 0x00 0. " [0] ,CP A buffer full interrupt flag 0" "No interrupt,Interrupt"
textline " "
group.long 0x48++0x03
line.long 0x00 "BERINTFL,BER Interrupt Flag Register"
eventfld.long 0x00 15. " BERINTFL_[15] ,CP B bus error interrupt flag 15" "No interrupt,Interrupt"
eventfld.long 0x00 14. " [14] ,CP A bus error interrupt flag 14" "No interrupt,Interrupt"
eventfld.long 0x00 13. " [13] ,CP B bus error interrupt flag 13" "No interrupt,Interrupt"
eventfld.long 0x00 12. " [12] ,CP A bus error interrupt flag 12" "No interrupt,Interrupt"
textline " "
eventfld.long 0x00 11. " [11] ,CP B bus error interrupt flag 11" "No interrupt,Interrupt"
eventfld.long 0x00 10. " [10] ,CP A bus error interrupt flag 10" "No interrupt,Interrupt"
eventfld.long 0x00 9. " [9] ,CP B bus error interrupt flag 9" "No interrupt,Interrupt"
eventfld.long 0x00 8. " [8] ,CP A bus error interrupt flag 8" "No interrupt,Interrupt"
textline " "
eventfld.long 0x00 7. " [7] ,CP B bus error interrupt flag 7" "No interrupt,Interrupt"
eventfld.long 0x00 6. " [6] ,CP A bus error interrupt flag 6" "No interrupt,Interrupt"
eventfld.long 0x00 5. " [5] ,CP B bus error interrupt flag 5" "No interrupt,Interrupt"
eventfld.long 0x00 4. " [4] ,CP A bus error interrupt flag 4" "No interrupt,Interrupt"
textline " "
eventfld.long 0x00 3. " [3] ,CP B bus error interrupt flag 3" "No interrupt,Interrupt"
eventfld.long 0x00 2. " [2] ,CP A bus error interrupt flag 2" "No interrupt,Interrupt"
eventfld.long 0x00 1. " [1] ,CP B bus error interrupt flag 1" "No interrupt,Interrupt"
eventfld.long 0x00 0. " [0] ,CP A bus error interrupt flag 0" "No interrupt,Interrupt"
group.long 0x4C++0x03
line.long 0x00 "MP1S,Memory Protection 1 Start Address"
group.long 0x50++0x03
line.long 0x00 "MP1E,Memory Protection 1 End Address"
group.long 0x54++0x03
line.long 0x00 "DCTRL,Debug Control Register"
rbitfld.long 0x00 24.--27. " CPNUM ,CP number" "CP A of DCP0,CP B of DCP0,CP A of DCP1,CP B of DCP1,CP A of DCP2,CP B of DCP2,CP A of DCP3,CP B of DCP3,CP A of DCP4,CP B of DCP4,CP A of DCP5,CP B of DCP5,CP A of DCP6,CP B of DCP6,CP A of DCP7,CP B of DCP7"
eventfld.long 0x00 16. " HTUDBGS ,HTU debug status" "Not detected,Detected"
bitfld.long 0x00 0. " DBREN ,Debug request enable" "Disabled,Enabled"
group.long 0x58++0x03
line.long 0x00 "WPR,Watch Point Register"
group.long 0x5C++0x03
line.long 0x00 "WMR,Watch Mask Register"
rgroup.long 0x60++0x03
line.long 0x00 "ID,Module Identification Register"
hexmask.long.byte 0x00 16.--23. 1. " CLASS ,Module class"
hexmask.long.byte 0x00 8.--15. 1. " TYPE ,Subtype within a class"
hexmask.long.byte 0x00 0.--7. 1. " REV ,Module revision number"
group.long 0x64++0x03
line.long 0x00 "PCR,Parity Control Register"
bitfld.long 0x00 16. " COPE ,Continue on parity error" "Stop,Continue"
bitfld.long 0x00 8. " TEST ,Test" "Not mapped,Mapped"
bitfld.long 0x00 0.--3. " PARITY_ENA ,Enable/disable parity checking" "Enabled,Enabled,Enabled,Enabled,Enabled,Disabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled"
group.long 0x68++0x03
line.long 0x00 "PAR,Parity Address Register"
eventfld.long 0x00 16. " PEFT ,Parity error fault flag" "Not detected,Detected"
hexmask.long.word 0x00 0.--8. 1. " PAOFF ,Parity error address offset"
group.long 0x70++0x03
line.long 0x00 "MPCS,Memory Protection Control And Status Register"
bitfld.long 0x00 24.--27. " CPNUM0 ,CP number" "CP A of DCP0,CP B of DCP0,CP A of DCP1,CP B of DCP1,CP A of DCP2,CP B of DCP2,CP A of DCP3,CP B of DCP3,CP A of DCP4,CP B of DCP4,CP A of DCP5,CP B of DCP5,CP A of DCP6,CP B of DCP6,CP A of DCP7,CP B of DCP7"
eventfld.long 0x00 17. " MPEFT1 ,Memory protection error fault flag" "Not detected,Detected"
eventfld.long 0x00 16. " MPEFT0 ,Memory protection error fault flag" "Not detected,Detected"
textline " "
rbitfld.long 0x00 8.--11. " CPNUM1 ,CP number" "CP A of DCP0,CP B of DCP0,CP A of DCP1,CP B of DCP1,CP A of DCP2,CP B of DCP2,CP A of DCP3,CP B of DCP3,CP A of DCP4,CP B of DCP4,CP A of DCP5,CP B of DCP5,CP A of DCP6,CP B of DCP6,CP A of DCP7,CP B of DCP7"
bitfld.long 0x00 5. " INTENA01 ,Interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 4. " ACCR01 ,Access rights HTU" "Allowed,Forbidden"
textline " "
bitfld.long 0x00 3. " REG01ENA ,Region enable" "Disabled,Enabled"
bitfld.long 0x00 2. " INTENA0 ,Interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 1. " ACCR ,Access rights HTU" "Allowed,Forbidden"
textline " "
bitfld.long 0x00 0. " REG0ENA ,Region enable" "Disabled,Enabled"
group.long 0x74++0x03
line.long 0x00 "MP0S,Memory Protection Start Address Register"
group.long 0x78++0x03
line.long 0x00 "MP0E,Memory Protection End Address Register"
base ad:0xFF4E0000
width 10.
tree "Double Control Packet Configuration Memory"
tree "Set 0"
group.long (0x0+0x00)++0x0F
line.long 0x00 "IFADDRA,Initial Main Memory Address Control Packet A"
line.long 0x04 "IFADDRB,Initial Main Memory Address Control Packet B"
line.long 0x08 "IHADDRCT,Initial NHET Address And Control"
bitfld.long 0x08 23. " DIR ,Direction of transfer (Read->write)" "Nhet->main,Main->nhet"
bitfld.long 0x08 22. " SIZE ,Size of transferred data" "32-bit,64-bit"
textline " "
bitfld.long 0x08 21. " ADDMH ,Addressing mode NHET address (Increment value)" "16 bytes,8 bytes"
bitfld.long 0x08 20. " ADDMF ,Addressing mode main memory address" "Post-increment,Constant"
textline " "
bitfld.long 0x08 18.--19. " TMBA ,Transfer mode for buffer A" "One shot,Circular,Auto switch,Auto switch"
bitfld.long 0x08 16.--17. " TMBB ,Transfer mode for buffer B" "One shot,Circular,Auto switch,Auto switch"
textline " "
hexmask.long.word 0x08 2.--12. 0x04 " IHADDR ,Initial NHET address"
line.long 0x0C "ITCOUNT,Initial Transfer Count"
bitfld.long 0x0C 16.--20. " IETCOUNT ,Initial element transfer count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
hexmask.long.byte 0x0C 0.--7. 1. " IFTCOUNT ,Initial frame transfer count"
group.long (0x0+0x100)++0x0B
line.long 0x00 "CFADDRA,Current Main Memory Address Control Packet A"
line.long 0x04 "CFADDRB,Current Main Memory Address Control Packet B"
line.long 0x08 "CFCOUNT,Current Frame Count"
hexmask.long.byte 0x08 16.--23. 1. " CFTCTA ,Current frame transfer count for CP A"
hexmask.long.byte 0x08 0.--7. 1. " CFTCTB ,Current frame transfer count for CP B"
tree.end
tree "Set 1"
group.long (0x10+0x00)++0x0F
line.long 0x00 "IFADDRA,Initial Main Memory Address Control Packet A"
line.long 0x04 "IFADDRB,Initial Main Memory Address Control Packet B"
line.long 0x08 "IHADDRCT,Initial NHET Address And Control"
bitfld.long 0x08 23. " DIR ,Direction of transfer (Read->write)" "Nhet->main,Main->nhet"
bitfld.long 0x08 22. " SIZE ,Size of transferred data" "32-bit,64-bit"
textline " "
bitfld.long 0x08 21. " ADDMH ,Addressing mode NHET address (Increment value)" "16 bytes,8 bytes"
bitfld.long 0x08 20. " ADDMF ,Addressing mode main memory address" "Post-increment,Constant"
textline " "
bitfld.long 0x08 18.--19. " TMBA ,Transfer mode for buffer A" "One shot,Circular,Auto switch,Auto switch"
bitfld.long 0x08 16.--17. " TMBB ,Transfer mode for buffer B" "One shot,Circular,Auto switch,Auto switch"
textline " "
hexmask.long.word 0x08 2.--12. 0x04 " IHADDR ,Initial NHET address"
line.long 0x0C "ITCOUNT,Initial Transfer Count"
bitfld.long 0x0C 16.--20. " IETCOUNT ,Initial element transfer count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
hexmask.long.byte 0x0C 0.--7. 1. " IFTCOUNT ,Initial frame transfer count"
group.long (0x10+0x100)++0x0B
line.long 0x00 "CFADDRA,Current Main Memory Address Control Packet A"
line.long 0x04 "CFADDRB,Current Main Memory Address Control Packet B"
line.long 0x08 "CFCOUNT,Current Frame Count"
hexmask.long.byte 0x08 16.--23. 1. " CFTCTA ,Current frame transfer count for CP A"
hexmask.long.byte 0x08 0.--7. 1. " CFTCTB ,Current frame transfer count for CP B"
tree.end
tree "Set 2"
group.long (0x20+0x00)++0x0F
line.long 0x00 "IFADDRA,Initial Main Memory Address Control Packet A"
line.long 0x04 "IFADDRB,Initial Main Memory Address Control Packet B"
line.long 0x08 "IHADDRCT,Initial NHET Address And Control"
bitfld.long 0x08 23. " DIR ,Direction of transfer (Read->write)" "Nhet->main,Main->nhet"
bitfld.long 0x08 22. " SIZE ,Size of transferred data" "32-bit,64-bit"
textline " "
bitfld.long 0x08 21. " ADDMH ,Addressing mode NHET address (Increment value)" "16 bytes,8 bytes"
bitfld.long 0x08 20. " ADDMF ,Addressing mode main memory address" "Post-increment,Constant"
textline " "
bitfld.long 0x08 18.--19. " TMBA ,Transfer mode for buffer A" "One shot,Circular,Auto switch,Auto switch"
bitfld.long 0x08 16.--17. " TMBB ,Transfer mode for buffer B" "One shot,Circular,Auto switch,Auto switch"
textline " "
hexmask.long.word 0x08 2.--12. 0x04 " IHADDR ,Initial NHET address"
line.long 0x0C "ITCOUNT,Initial Transfer Count"
bitfld.long 0x0C 16.--20. " IETCOUNT ,Initial element transfer count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
hexmask.long.byte 0x0C 0.--7. 1. " IFTCOUNT ,Initial frame transfer count"
group.long (0x20+0x100)++0x0B
line.long 0x00 "CFADDRA,Current Main Memory Address Control Packet A"
line.long 0x04 "CFADDRB,Current Main Memory Address Control Packet B"
line.long 0x08 "CFCOUNT,Current Frame Count"
hexmask.long.byte 0x08 16.--23. 1. " CFTCTA ,Current frame transfer count for CP A"
hexmask.long.byte 0x08 0.--7. 1. " CFTCTB ,Current frame transfer count for CP B"
tree.end
tree "Set 3"
group.long (0x30+0x00)++0x0F
line.long 0x00 "IFADDRA,Initial Main Memory Address Control Packet A"
line.long 0x04 "IFADDRB,Initial Main Memory Address Control Packet B"
line.long 0x08 "IHADDRCT,Initial NHET Address And Control"
bitfld.long 0x08 23. " DIR ,Direction of transfer (Read->write)" "Nhet->main,Main->nhet"
bitfld.long 0x08 22. " SIZE ,Size of transferred data" "32-bit,64-bit"
textline " "
bitfld.long 0x08 21. " ADDMH ,Addressing mode NHET address (Increment value)" "16 bytes,8 bytes"
bitfld.long 0x08 20. " ADDMF ,Addressing mode main memory address" "Post-increment,Constant"
textline " "
bitfld.long 0x08 18.--19. " TMBA ,Transfer mode for buffer A" "One shot,Circular,Auto switch,Auto switch"
bitfld.long 0x08 16.--17. " TMBB ,Transfer mode for buffer B" "One shot,Circular,Auto switch,Auto switch"
textline " "
hexmask.long.word 0x08 2.--12. 0x04 " IHADDR ,Initial NHET address"
line.long 0x0C "ITCOUNT,Initial Transfer Count"
bitfld.long 0x0C 16.--20. " IETCOUNT ,Initial element transfer count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
hexmask.long.byte 0x0C 0.--7. 1. " IFTCOUNT ,Initial frame transfer count"
group.long (0x30+0x100)++0x0B
line.long 0x00 "CFADDRA,Current Main Memory Address Control Packet A"
line.long 0x04 "CFADDRB,Current Main Memory Address Control Packet B"
line.long 0x08 "CFCOUNT,Current Frame Count"
hexmask.long.byte 0x08 16.--23. 1. " CFTCTA ,Current frame transfer count for CP A"
hexmask.long.byte 0x08 0.--7. 1. " CFTCTB ,Current frame transfer count for CP B"
tree.end
tree "Set 4"
group.long (0x40+0x00)++0x0F
line.long 0x00 "IFADDRA,Initial Main Memory Address Control Packet A"
line.long 0x04 "IFADDRB,Initial Main Memory Address Control Packet B"
line.long 0x08 "IHADDRCT,Initial NHET Address And Control"
bitfld.long 0x08 23. " DIR ,Direction of transfer (Read->write)" "Nhet->main,Main->nhet"
bitfld.long 0x08 22. " SIZE ,Size of transferred data" "32-bit,64-bit"
textline " "
bitfld.long 0x08 21. " ADDMH ,Addressing mode NHET address (Increment value)" "16 bytes,8 bytes"
bitfld.long 0x08 20. " ADDMF ,Addressing mode main memory address" "Post-increment,Constant"
textline " "
bitfld.long 0x08 18.--19. " TMBA ,Transfer mode for buffer A" "One shot,Circular,Auto switch,Auto switch"
bitfld.long 0x08 16.--17. " TMBB ,Transfer mode for buffer B" "One shot,Circular,Auto switch,Auto switch"
textline " "
hexmask.long.word 0x08 2.--12. 0x04 " IHADDR ,Initial NHET address"
line.long 0x0C "ITCOUNT,Initial Transfer Count"
bitfld.long 0x0C 16.--20. " IETCOUNT ,Initial element transfer count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
hexmask.long.byte 0x0C 0.--7. 1. " IFTCOUNT ,Initial frame transfer count"
group.long (0x40+0x100)++0x0B
line.long 0x00 "CFADDRA,Current Main Memory Address Control Packet A"
line.long 0x04 "CFADDRB,Current Main Memory Address Control Packet B"
line.long 0x08 "CFCOUNT,Current Frame Count"
hexmask.long.byte 0x08 16.--23. 1. " CFTCTA ,Current frame transfer count for CP A"
hexmask.long.byte 0x08 0.--7. 1. " CFTCTB ,Current frame transfer count for CP B"
tree.end
tree "Set 5"
group.long (0x50+0x00)++0x0F
line.long 0x00 "IFADDRA,Initial Main Memory Address Control Packet A"
line.long 0x04 "IFADDRB,Initial Main Memory Address Control Packet B"
line.long 0x08 "IHADDRCT,Initial NHET Address And Control"
bitfld.long 0x08 23. " DIR ,Direction of transfer (Read->write)" "Nhet->main,Main->nhet"
bitfld.long 0x08 22. " SIZE ,Size of transferred data" "32-bit,64-bit"
textline " "
bitfld.long 0x08 21. " ADDMH ,Addressing mode NHET address (Increment value)" "16 bytes,8 bytes"
bitfld.long 0x08 20. " ADDMF ,Addressing mode main memory address" "Post-increment,Constant"
textline " "
bitfld.long 0x08 18.--19. " TMBA ,Transfer mode for buffer A" "One shot,Circular,Auto switch,Auto switch"
bitfld.long 0x08 16.--17. " TMBB ,Transfer mode for buffer B" "One shot,Circular,Auto switch,Auto switch"
textline " "
hexmask.long.word 0x08 2.--12. 0x04 " IHADDR ,Initial NHET address"
line.long 0x0C "ITCOUNT,Initial Transfer Count"
bitfld.long 0x0C 16.--20. " IETCOUNT ,Initial element transfer count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
hexmask.long.byte 0x0C 0.--7. 1. " IFTCOUNT ,Initial frame transfer count"
group.long (0x50+0x100)++0x0B
line.long 0x00 "CFADDRA,Current Main Memory Address Control Packet A"
line.long 0x04 "CFADDRB,Current Main Memory Address Control Packet B"
line.long 0x08 "CFCOUNT,Current Frame Count"
hexmask.long.byte 0x08 16.--23. 1. " CFTCTA ,Current frame transfer count for CP A"
hexmask.long.byte 0x08 0.--7. 1. " CFTCTB ,Current frame transfer count for CP B"
tree.end
tree "Set 6"
group.long (0x60+0x00)++0x0F
line.long 0x00 "IFADDRA,Initial Main Memory Address Control Packet A"
line.long 0x04 "IFADDRB,Initial Main Memory Address Control Packet B"
line.long 0x08 "IHADDRCT,Initial NHET Address And Control"
bitfld.long 0x08 23. " DIR ,Direction of transfer (Read->write)" "Nhet->main,Main->nhet"
bitfld.long 0x08 22. " SIZE ,Size of transferred data" "32-bit,64-bit"
textline " "
bitfld.long 0x08 21. " ADDMH ,Addressing mode NHET address (Increment value)" "16 bytes,8 bytes"
bitfld.long 0x08 20. " ADDMF ,Addressing mode main memory address" "Post-increment,Constant"
textline " "
bitfld.long 0x08 18.--19. " TMBA ,Transfer mode for buffer A" "One shot,Circular,Auto switch,Auto switch"
bitfld.long 0x08 16.--17. " TMBB ,Transfer mode for buffer B" "One shot,Circular,Auto switch,Auto switch"
textline " "
hexmask.long.word 0x08 2.--12. 0x04 " IHADDR ,Initial NHET address"
line.long 0x0C "ITCOUNT,Initial Transfer Count"
bitfld.long 0x0C 16.--20. " IETCOUNT ,Initial element transfer count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
hexmask.long.byte 0x0C 0.--7. 1. " IFTCOUNT ,Initial frame transfer count"
group.long (0x60+0x100)++0x0B
line.long 0x00 "CFADDRA,Current Main Memory Address Control Packet A"
line.long 0x04 "CFADDRB,Current Main Memory Address Control Packet B"
line.long 0x08 "CFCOUNT,Current Frame Count"
hexmask.long.byte 0x08 16.--23. 1. " CFTCTA ,Current frame transfer count for CP A"
hexmask.long.byte 0x08 0.--7. 1. " CFTCTB ,Current frame transfer count for CP B"
tree.end
tree "Set 7"
group.long (0x70+0x00)++0x0F
line.long 0x00 "IFADDRA,Initial Main Memory Address Control Packet A"
line.long 0x04 "IFADDRB,Initial Main Memory Address Control Packet B"
line.long 0x08 "IHADDRCT,Initial NHET Address And Control"
bitfld.long 0x08 23. " DIR ,Direction of transfer (Read->write)" "Nhet->main,Main->nhet"
bitfld.long 0x08 22. " SIZE ,Size of transferred data" "32-bit,64-bit"
textline " "
bitfld.long 0x08 21. " ADDMH ,Addressing mode NHET address (Increment value)" "16 bytes,8 bytes"
bitfld.long 0x08 20. " ADDMF ,Addressing mode main memory address" "Post-increment,Constant"
textline " "
bitfld.long 0x08 18.--19. " TMBA ,Transfer mode for buffer A" "One shot,Circular,Auto switch,Auto switch"
bitfld.long 0x08 16.--17. " TMBB ,Transfer mode for buffer B" "One shot,Circular,Auto switch,Auto switch"
textline " "
hexmask.long.word 0x08 2.--12. 0x04 " IHADDR ,Initial NHET address"
line.long 0x0C "ITCOUNT,Initial Transfer Count"
bitfld.long 0x0C 16.--20. " IETCOUNT ,Initial element transfer count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
hexmask.long.byte 0x0C 0.--7. 1. " IFTCOUNT ,Initial frame transfer count"
group.long (0x70+0x100)++0x0B
line.long 0x00 "CFADDRA,Current Main Memory Address Control Packet A"
line.long 0x04 "CFADDRB,Current Main Memory Address Control Packet B"
line.long 0x08 "CFCOUNT,Current Frame Count"
hexmask.long.byte 0x08 16.--23. 1. " CFTCTA ,Current frame transfer count for CP A"
hexmask.long.byte 0x08 0.--7. 1. " CFTCTB ,Current frame transfer count for CP B"
tree.end
tree.end
width 0x0B
tree.end
tree "HTU2"
base ad:0xFFF7A500
width 10.
group.long 0x00++0x03
line.long 0x00 "GC,Global Control Register"
bitfld.long 0x00 24. " VBUS_HOLD ,Hold the VBUS bus" "Not held,Held"
bitfld.long 0x00 16. " HTUEN ,Transfer unit enable bit" "Disabled,Enabled"
bitfld.long 0x00 8. " DEBM ,Debug mode" "Suspended,Continue"
textline " "
bitfld.long 0x00 0. " HTU_RES ,HTU software reset" "No reset,Reset"
textline " "
group.long 0x04++0x03
line.long 0x00 "CPENA,Control Packet Enable Register"
bitfld.long 0x00 14.--15. " CPENA_[7] ,CP enable bits 7 (Cp A/CP B)" "(R) DCP disabled,(Rw) A enabled/b disabled,(Rw) A disabled/b enabled,(W) disable DCP"
bitfld.long 0x00 12.--13. " [6] ,CP enable bits 6 (Cp A/CP B)" "(R) DCP disabled,(Rw) A enabled/b disabled,(Rw) A disabled/b enabled,(W) disable DCP"
bitfld.long 0x00 10.--11. " [5] ,CP enable bits 5 (Cp A/CP B)" "(R) DCP disabled,(Rw) A enabled/b disabled,(Rw) A disabled/b enabled,(W) disable DCP"
bitfld.long 0x00 8.--9. " [4] ,CP enable bits 4 (Cp A/CP B)" "(R) DCP disabled,(Rw) A enabled/b disabled,(Rw) A disabled/b enabled,(W) disable DCP"
textline " "
bitfld.long 0x00 6.--7. " [3] ,CP enable bits 3 (Cp A/CP B)" "(R) DCP disabled,(Rw) A enabled/b disabled,(Rw) A disabled/b enabled,(W) disable DCP"
bitfld.long 0x00 4.--5. " [2] ,CP enable bits 2 (Cp A/CP B)" "(R) DCP disabled,(Rw) A enabled/b disabled,(Rw) A disabled/b enabled,(W) disable DCP"
bitfld.long 0x00 2.--3. " [1] ,CP enable bits 1 (Cp A/CP B)" "(R) DCP disabled,(Rw) A enabled/b disabled,(Rw) A disabled/b enabled,(W) disable DCP"
bitfld.long 0x00 0.--1. " [0] ,CP enable bits 0 (Cp A/CP B)" "(R) DCP disabled,(Rw) A enabled/b disabled,(Rw) A disabled/b enabled,(W) disable DCP"
textline " "
group.long 0x08++0x03
line.long 0x00 "BUSY0,Control Packet (Cp) Busy Register 0"
eventfld.long 0x00 24. " BUSY_[0A] ,Busy flag for CP A of double CP 0" "Not busy,Busy"
eventfld.long 0x00 16. " [0B] ,Busy flag for CP B of double CP 0" "Not busy,Busy"
eventfld.long 0x00 8. " [1A] ,Busy flag for CP A of double CP 1" "Not busy,Busy"
eventfld.long 0x00 0. " [1B] ,Busy flag for CP B of double CP 1" "Not busy,Busy"
group.long 0x0C++0x03
line.long 0x00 "BUSY1,Control Packet (Cp) Busy Register 1"
eventfld.long 0x00 24. " BUSY_[2A] ,Busy flag for CP A of double CP 2" "Not busy,Busy"
eventfld.long 0x00 16. " [2B] ,Busy flag for CP B of double CP 2" "Not busy,Busy"
eventfld.long 0x00 8. " [3A] ,Busy flag for CP A of double CP 3" "Not busy,Busy"
eventfld.long 0x00 0. " [3B] ,Busy flag for CP B of double CP 3" "Not busy,Busy"
group.long 0x10++0x03
line.long 0x00 "BUSY2,Control Packet (Cp) Busy Register 2"
eventfld.long 0x00 24. " BUSY_[4A] ,Busy flag for CP A of double CP 4" "Not busy,Busy"
eventfld.long 0x00 16. " [4B] ,Busy flag for CP B of double CP 4" "Not busy,Busy"
eventfld.long 0x00 8. " [5A] ,Busy flag for CP A of double CP 5" "Not busy,Busy"
eventfld.long 0x00 0. " [5B] ,Busy flag for CP B of double CP 5" "Not busy,Busy"
group.long 0x14++0x03
line.long 0x00 "BUSY3,Control Packet (Cp) Busy Register 3"
eventfld.long 0x00 24. " BUSY_[6A] ,Busy flag for CP A of double CP 6" "Not busy,Busy"
eventfld.long 0x00 16. " [6B] ,Busy flag for CP B of double CP 6" "Not busy,Busy"
eventfld.long 0x00 8. " [7A] ,Busy flag for CP A of double CP 7" "Not busy,Busy"
eventfld.long 0x00 0. " [7B] ,Busy flag for CP B of double CP 7" "Not busy,Busy"
textline " "
group.long 0x18++0x03
line.long 0x00 "ACPE,Active Control Packet Register"
eventfld.long 0x00 31. " ERRF ,Error flag" "No error,Error"
rbitfld.long 0x00 24.--28. " ERRETC ,Error element transfer counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
rbitfld.long 0x00 16.--19. " ERRCPN ,Error control packet number" "CP A of DCP0,CP B of DCP0,CP A of DCP1,CP B of DCP1,CP A of DCP2,CP B of DCP2,CP A of DCP3,CP B of DCP3,CP A of DCP4,CP B of DCP4,CP A of DCP5,CP B of DCP5,CP A of DCP6,CP B of DCP6,CP A of DCP7,CP B of DCP7"
textline " "
rbitfld.long 0x00 15. " TIPF ,Transfer in progress flag" "Not active,Active"
rbitfld.long 0x00 14. " BUS_BUSY ,VBUSP bus is busy" "Not busy,Busy"
rbitfld.long 0x00 8.--12. " CETCOUNT ,Current element transfer counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline " "
rbitfld.long 0x00 0.--3. " NACP ,Number of active control packet" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x20++0x03
line.long 0x00 "RLBECTRL,Request Lost And Bus Error Control Register"
bitfld.long 0x00 16. " BERINTENA ,Bus error interrupt enable bit" "Disabled,Enabled"
bitfld.long 0x00 8. " CORL ,Continue on request lost error" "Lost,Continue"
bitfld.long 0x00 0. " RLINTENA ,Request lost interrupt enable bit" "Disabled,Enabled"
textline " "
group.long 0x24++0x03
line.long 0x00 "BFINT,Buffer Full Interrupt Enable Set Register"
setclrfld.long 0x00 15. 0x00 15. 0x04 15. " BFINTENA_SET/CLR_[15] ,CP B buffer full interrupt enable bit 15" "Disabled,Enabled"
setclrfld.long 0x00 14. 0x00 14. 0x04 14. " [14] ,CP A buffer full interrupt enable bit 14" "Disabled,Enabled"
setclrfld.long 0x00 13. 0x00 13. 0x04 13. " [13] ,CP B buffer full interrupt enable bit 13" "Disabled,Enabled"
setclrfld.long 0x00 12. 0x00 12. 0x04 12. " [12] ,CP A buffer full interrupt enable bit 12" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 11. 0x00 11. 0x04 11. " [11] ,CP B buffer full interrupt enable bit 11" "Disabled,Enabled"
setclrfld.long 0x00 10. 0x00 10. 0x04 10. " [10] ,CP A buffer full interrupt enable bit 10" "Disabled,Enabled"
setclrfld.long 0x00 9. 0x00 9. 0x04 9. " [9] ,CP B buffer full interrupt enable bit 9" "Disabled,Enabled"
setclrfld.long 0x00 8. 0x00 8. 0x04 8. " [8] ,CP A buffer full interrupt enable bit 8" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 7. 0x00 7. 0x04 7. " [7] ,CP B buffer full interrupt enable bit 7" "Disabled,Enabled"
setclrfld.long 0x00 6. 0x00 6. 0x04 6. " [6] ,CP A buffer full interrupt enable bit 6" "Disabled,Enabled"
setclrfld.long 0x00 5. 0x00 5. 0x04 5. " [5] ,CP B buffer full interrupt enable bit 5" "Disabled,Enabled"
setclrfld.long 0x00 4. 0x00 4. 0x04 4. " [4] ,CP A buffer full interrupt enable bit 4" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 3. 0x00 3. 0x04 3. " [3] ,CP B buffer full interrupt enable bit 3" "Disabled,Enabled"
setclrfld.long 0x00 2. 0x00 2. 0x04 2. " [2] ,CP A buffer full interrupt enable bit 2" "Disabled,Enabled"
setclrfld.long 0x00 1. 0x00 1. 0x04 1. " [1] ,CP B buffer full interrupt enable bit 1" "Disabled,Enabled"
setclrfld.long 0x00 0. 0x00 0. 0x04 0. " [0] ,CP A buffer full interrupt enable bit 0" "Disabled,Enabled"
textline " "
group.long 0x2C++0x03
line.long 0x00 "INTMAP,Interrupt Mapping Register"
bitfld.long 0x00 16. " MAPSEL ,Interrupt mapping select bit" "Low,High"
textline " "
bitfld.long 0x00 15. " CPINTMAP_[15] ,CP B interrupt mapping bit 15" "Line 0,Line 1"
bitfld.long 0x00 14. " [14] ,CP A interrupt mapping bit 14" "Line 0,Line 1"
bitfld.long 0x00 13. " [13] ,CP B interrupt mapping bit 13" "Line 0,Line 1"
bitfld.long 0x00 12. " [12] ,CP A interrupt mapping bit 12" "Line 0,Line 1"
textline " "
bitfld.long 0x00 11. " [11] ,CP B interrupt mapping bit 11" "Line 0,Line 1"
bitfld.long 0x00 10. " [10] ,CP A interrupt mapping bit 10" "Line 0,Line 1"
bitfld.long 0x00 9. " [9] ,CP B interrupt mapping bit 9" "Line 0,Line 1"
bitfld.long 0x00 8. " [8] ,CP A interrupt mapping bit 8" "Line 0,Line 1"
textline " "
bitfld.long 0x00 7. " [7] ,CP B interrupt mapping bit 7" "Line 0,Line 1"
bitfld.long 0x00 6. " [6] ,CP A interrupt mapping bit 6" "Line 0,Line 1"
bitfld.long 0x00 5. " [5] ,CP B interrupt mapping bit 5" "Line 0,Line 1"
bitfld.long 0x00 4. " [4] ,CP A interrupt mapping bit 4" "Line 0,Line 1"
textline " "
bitfld.long 0x00 3. " [3] ,CP B interrupt mapping bit 3" "Line 0,Line 1"
bitfld.long 0x00 2. " [2] ,CP A interrupt mapping bit 2" "Line 0,Line 1"
bitfld.long 0x00 1. " [1] ,CP B interrupt mapping bit 1" "Line 0,Line 1"
bitfld.long 0x00 0. " [0] ,CP A interrupt mapping bit 0" "Line 0,Line 1"
hgroup.long 0x34++0x03
hide.long 0x00 "INTOFF0,Interrupt Offset Register 0"
in
hgroup.long 0x38++0x03
hide.long 0x00 "INTOFF1,Interrupt Offset Register 1"
in
textline " "
group.long 0x3C++0x03
line.long 0x00 "BIM,Buffer Initialization Mode Register"
bitfld.long 0x00 7. " BIM[7] ,Buffer initialization mode bit 7" "Normal,Special"
bitfld.long 0x00 6. " [6] ,Buffer initialization mode bit 6" "Normal,Special"
bitfld.long 0x00 5. " [5] ,Buffer initialization mode bit 5" "Normal,Special"
bitfld.long 0x00 4. " [4] ,Buffer initialization mode bit 4" "Normal,Special"
textline " "
bitfld.long 0x00 3. " [3] ,Buffer initialization mode bit 3" "Normal,Special"
bitfld.long 0x00 2. " [2] ,Buffer initialization mode bit 2" "Normal,Special"
bitfld.long 0x00 1. " [1] ,Buffer initialization mode bit 1" "Normal,Special"
bitfld.long 0x00 0. " [0] ,Buffer initialization mode bit 0" "Normal,Special"
textline " "
group.long 0x40++0x03
line.long 0x00 "RLOSTFL,Request Lost Flag Register"
eventfld.long 0x00 15. " CPRLFL[15] ,CP B request lost flag 15" "Not requested,Requested"
eventfld.long 0x00 14. " [14] ,CP A request lost flag 14" "Not requested,Requested"
eventfld.long 0x00 13. " [13] ,CP B request lost flag 13" "Not requested,Requested"
eventfld.long 0x00 12. " [12] ,CP A request lost flag 12" "Not requested,Requested"
textline " "
eventfld.long 0x00 11. " [11] ,CP B request lost flag 11" "Not requested,Requested"
eventfld.long 0x00 10. " [10] ,CP A request lost flag 10" "Not requested,Requested"
eventfld.long 0x00 9. " [9] ,CP B request lost flag 9" "Not requested,Requested"
eventfld.long 0x00 8. " [8] ,CP A request lost flag 8" "Not requested,Requested"
textline " "
eventfld.long 0x00 7. " [7] ,CP B request lost flag 7" "Not requested,Requested"
eventfld.long 0x00 6. " [6] ,CP A request lost flag 6" "Not requested,Requested"
eventfld.long 0x00 5. " [5] ,CP B request lost flag 5" "Not requested,Requested"
eventfld.long 0x00 4. " [4] ,CP A request lost flag 4" "Not requested,Requested"
textline " "
eventfld.long 0x00 3. " [3] ,CP B request lost flag 3" "Not requested,Requested"
eventfld.long 0x00 2. " [2] ,CP A request lost flag 2" "Not requested,Requested"
eventfld.long 0x00 1. " [1] ,CP B request lost flag 1" "Not requested,Requested"
eventfld.long 0x00 0. " [0] ,CP A request lost flag 0" "Not requested,Requested"
textline " "
group.long 0x44++0x03
line.long 0x00 "BFINTFL,Buffer Full Interrupt Flag Register"
eventfld.long 0x00 15. " BFINTFL[15] ,CP B buffer full interrupt flag 15" "No interrupt,Interrupt"
eventfld.long 0x00 14. " [14] ,CP A buffer full interrupt flag 14" "No interrupt,Interrupt"
eventfld.long 0x00 13. " [13] ,CP B buffer full interrupt flag 13" "No interrupt,Interrupt"
eventfld.long 0x00 12. " [12] ,CP A buffer full interrupt flag 12" "No interrupt,Interrupt"
textline " "
eventfld.long 0x00 11. " [11] ,CP B buffer full interrupt flag 11" "No interrupt,Interrupt"
eventfld.long 0x00 10. " [10] ,CP A buffer full interrupt flag 10" "No interrupt,Interrupt"
eventfld.long 0x00 9. " [9] ,CP B buffer full interrupt flag 9" "No interrupt,Interrupt"
eventfld.long 0x00 8. " [8] ,CP A buffer full interrupt flag 8" "No interrupt,Interrupt"
textline " "
eventfld.long 0x00 7. " [7] ,CP B buffer full interrupt flag 7" "No interrupt,Interrupt"
eventfld.long 0x00 6. " [6] ,CP A buffer full interrupt flag 6" "No interrupt,Interrupt"
eventfld.long 0x00 5. " [5] ,CP B buffer full interrupt flag 5" "No interrupt,Interrupt"
eventfld.long 0x00 4. " [4] ,CP A buffer full interrupt flag 4" "No interrupt,Interrupt"
textline " "
eventfld.long 0x00 3. " [3] ,CP B buffer full interrupt flag 3" "No interrupt,Interrupt"
eventfld.long 0x00 2. " [2] ,CP A buffer full interrupt flag 2" "No interrupt,Interrupt"
eventfld.long 0x00 1. " [1] ,CP B buffer full interrupt flag 1" "No interrupt,Interrupt"
eventfld.long 0x00 0. " [0] ,CP A buffer full interrupt flag 0" "No interrupt,Interrupt"
textline " "
group.long 0x48++0x03
line.long 0x00 "BERINTFL,BER Interrupt Flag Register"
eventfld.long 0x00 15. " BERINTFL_[15] ,CP B bus error interrupt flag 15" "No interrupt,Interrupt"
eventfld.long 0x00 14. " [14] ,CP A bus error interrupt flag 14" "No interrupt,Interrupt"
eventfld.long 0x00 13. " [13] ,CP B bus error interrupt flag 13" "No interrupt,Interrupt"
eventfld.long 0x00 12. " [12] ,CP A bus error interrupt flag 12" "No interrupt,Interrupt"
textline " "
eventfld.long 0x00 11. " [11] ,CP B bus error interrupt flag 11" "No interrupt,Interrupt"
eventfld.long 0x00 10. " [10] ,CP A bus error interrupt flag 10" "No interrupt,Interrupt"
eventfld.long 0x00 9. " [9] ,CP B bus error interrupt flag 9" "No interrupt,Interrupt"
eventfld.long 0x00 8. " [8] ,CP A bus error interrupt flag 8" "No interrupt,Interrupt"
textline " "
eventfld.long 0x00 7. " [7] ,CP B bus error interrupt flag 7" "No interrupt,Interrupt"
eventfld.long 0x00 6. " [6] ,CP A bus error interrupt flag 6" "No interrupt,Interrupt"
eventfld.long 0x00 5. " [5] ,CP B bus error interrupt flag 5" "No interrupt,Interrupt"
eventfld.long 0x00 4. " [4] ,CP A bus error interrupt flag 4" "No interrupt,Interrupt"
textline " "
eventfld.long 0x00 3. " [3] ,CP B bus error interrupt flag 3" "No interrupt,Interrupt"
eventfld.long 0x00 2. " [2] ,CP A bus error interrupt flag 2" "No interrupt,Interrupt"
eventfld.long 0x00 1. " [1] ,CP B bus error interrupt flag 1" "No interrupt,Interrupt"
eventfld.long 0x00 0. " [0] ,CP A bus error interrupt flag 0" "No interrupt,Interrupt"
group.long 0x4C++0x03
line.long 0x00 "MP1S,Memory Protection 1 Start Address"
group.long 0x50++0x03
line.long 0x00 "MP1E,Memory Protection 1 End Address"
group.long 0x54++0x03
line.long 0x00 "DCTRL,Debug Control Register"
rbitfld.long 0x00 24.--27. " CPNUM ,CP number" "CP A of DCP0,CP B of DCP0,CP A of DCP1,CP B of DCP1,CP A of DCP2,CP B of DCP2,CP A of DCP3,CP B of DCP3,CP A of DCP4,CP B of DCP4,CP A of DCP5,CP B of DCP5,CP A of DCP6,CP B of DCP6,CP A of DCP7,CP B of DCP7"
eventfld.long 0x00 16. " HTUDBGS ,HTU debug status" "Not detected,Detected"
bitfld.long 0x00 0. " DBREN ,Debug request enable" "Disabled,Enabled"
group.long 0x58++0x03
line.long 0x00 "WPR,Watch Point Register"
group.long 0x5C++0x03
line.long 0x00 "WMR,Watch Mask Register"
rgroup.long 0x60++0x03
line.long 0x00 "ID,Module Identification Register"
hexmask.long.byte 0x00 16.--23. 1. " CLASS ,Module class"
hexmask.long.byte 0x00 8.--15. 1. " TYPE ,Subtype within a class"
hexmask.long.byte 0x00 0.--7. 1. " REV ,Module revision number"
group.long 0x64++0x03
line.long 0x00 "PCR,Parity Control Register"
bitfld.long 0x00 16. " COPE ,Continue on parity error" "Stop,Continue"
bitfld.long 0x00 8. " TEST ,Test" "Not mapped,Mapped"
bitfld.long 0x00 0.--3. " PARITY_ENA ,Enable/disable parity checking" "Enabled,Enabled,Enabled,Enabled,Enabled,Disabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled"
group.long 0x68++0x03
line.long 0x00 "PAR,Parity Address Register"
eventfld.long 0x00 16. " PEFT ,Parity error fault flag" "Not detected,Detected"
hexmask.long.word 0x00 0.--8. 1. " PAOFF ,Parity error address offset"
group.long 0x70++0x03
line.long 0x00 "MPCS,Memory Protection Control And Status Register"
bitfld.long 0x00 24.--27. " CPNUM0 ,CP number" "CP A of DCP0,CP B of DCP0,CP A of DCP1,CP B of DCP1,CP A of DCP2,CP B of DCP2,CP A of DCP3,CP B of DCP3,CP A of DCP4,CP B of DCP4,CP A of DCP5,CP B of DCP5,CP A of DCP6,CP B of DCP6,CP A of DCP7,CP B of DCP7"
eventfld.long 0x00 17. " MPEFT1 ,Memory protection error fault flag" "Not detected,Detected"
eventfld.long 0x00 16. " MPEFT0 ,Memory protection error fault flag" "Not detected,Detected"
textline " "
rbitfld.long 0x00 8.--11. " CPNUM1 ,CP number" "CP A of DCP0,CP B of DCP0,CP A of DCP1,CP B of DCP1,CP A of DCP2,CP B of DCP2,CP A of DCP3,CP B of DCP3,CP A of DCP4,CP B of DCP4,CP A of DCP5,CP B of DCP5,CP A of DCP6,CP B of DCP6,CP A of DCP7,CP B of DCP7"
bitfld.long 0x00 5. " INTENA01 ,Interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 4. " ACCR01 ,Access rights HTU" "Allowed,Forbidden"
textline " "
bitfld.long 0x00 3. " REG01ENA ,Region enable" "Disabled,Enabled"
bitfld.long 0x00 2. " INTENA0 ,Interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 1. " ACCR ,Access rights HTU" "Allowed,Forbidden"
textline " "
bitfld.long 0x00 0. " REG0ENA ,Region enable" "Disabled,Enabled"
group.long 0x74++0x03
line.long 0x00 "MP0S,Memory Protection Start Address Register"
group.long 0x78++0x03
line.long 0x00 "MP0E,Memory Protection End Address Register"
base ad:0xFF4C0000
width 10.
tree "Double Control Packet Configuration Memory"
tree "Set 0"
group.long (0x0+0x00)++0x0F
line.long 0x00 "IFADDRA,Initial Main Memory Address Control Packet A"
line.long 0x04 "IFADDRB,Initial Main Memory Address Control Packet B"
line.long 0x08 "IHADDRCT,Initial NHET Address And Control"
bitfld.long 0x08 23. " DIR ,Direction of transfer (Read->write)" "Nhet->main,Main->nhet"
bitfld.long 0x08 22. " SIZE ,Size of transferred data" "32-bit,64-bit"
textline " "
bitfld.long 0x08 21. " ADDMH ,Addressing mode NHET address (Increment value)" "16 bytes,8 bytes"
bitfld.long 0x08 20. " ADDMF ,Addressing mode main memory address" "Post-increment,Constant"
textline " "
bitfld.long 0x08 18.--19. " TMBA ,Transfer mode for buffer A" "One shot,Circular,Auto switch,Auto switch"
bitfld.long 0x08 16.--17. " TMBB ,Transfer mode for buffer B" "One shot,Circular,Auto switch,Auto switch"
textline " "
hexmask.long.word 0x08 2.--12. 0x04 " IHADDR ,Initial NHET address"
line.long 0x0C "ITCOUNT,Initial Transfer Count"
bitfld.long 0x0C 16.--20. " IETCOUNT ,Initial element transfer count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
hexmask.long.byte 0x0C 0.--7. 1. " IFTCOUNT ,Initial frame transfer count"
group.long (0x0+0x100)++0x0B
line.long 0x00 "CFADDRA,Current Main Memory Address Control Packet A"
line.long 0x04 "CFADDRB,Current Main Memory Address Control Packet B"
line.long 0x08 "CFCOUNT,Current Frame Count"
hexmask.long.byte 0x08 16.--23. 1. " CFTCTA ,Current frame transfer count for CP A"
hexmask.long.byte 0x08 0.--7. 1. " CFTCTB ,Current frame transfer count for CP B"
tree.end
tree "Set 1"
group.long (0x10+0x00)++0x0F
line.long 0x00 "IFADDRA,Initial Main Memory Address Control Packet A"
line.long 0x04 "IFADDRB,Initial Main Memory Address Control Packet B"
line.long 0x08 "IHADDRCT,Initial NHET Address And Control"
bitfld.long 0x08 23. " DIR ,Direction of transfer (Read->write)" "Nhet->main,Main->nhet"
bitfld.long 0x08 22. " SIZE ,Size of transferred data" "32-bit,64-bit"
textline " "
bitfld.long 0x08 21. " ADDMH ,Addressing mode NHET address (Increment value)" "16 bytes,8 bytes"
bitfld.long 0x08 20. " ADDMF ,Addressing mode main memory address" "Post-increment,Constant"
textline " "
bitfld.long 0x08 18.--19. " TMBA ,Transfer mode for buffer A" "One shot,Circular,Auto switch,Auto switch"
bitfld.long 0x08 16.--17. " TMBB ,Transfer mode for buffer B" "One shot,Circular,Auto switch,Auto switch"
textline " "
hexmask.long.word 0x08 2.--12. 0x04 " IHADDR ,Initial NHET address"
line.long 0x0C "ITCOUNT,Initial Transfer Count"
bitfld.long 0x0C 16.--20. " IETCOUNT ,Initial element transfer count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
hexmask.long.byte 0x0C 0.--7. 1. " IFTCOUNT ,Initial frame transfer count"
group.long (0x10+0x100)++0x0B
line.long 0x00 "CFADDRA,Current Main Memory Address Control Packet A"
line.long 0x04 "CFADDRB,Current Main Memory Address Control Packet B"
line.long 0x08 "CFCOUNT,Current Frame Count"
hexmask.long.byte 0x08 16.--23. 1. " CFTCTA ,Current frame transfer count for CP A"
hexmask.long.byte 0x08 0.--7. 1. " CFTCTB ,Current frame transfer count for CP B"
tree.end
tree "Set 2"
group.long (0x20+0x00)++0x0F
line.long 0x00 "IFADDRA,Initial Main Memory Address Control Packet A"
line.long 0x04 "IFADDRB,Initial Main Memory Address Control Packet B"
line.long 0x08 "IHADDRCT,Initial NHET Address And Control"
bitfld.long 0x08 23. " DIR ,Direction of transfer (Read->write)" "Nhet->main,Main->nhet"
bitfld.long 0x08 22. " SIZE ,Size of transferred data" "32-bit,64-bit"
textline " "
bitfld.long 0x08 21. " ADDMH ,Addressing mode NHET address (Increment value)" "16 bytes,8 bytes"
bitfld.long 0x08 20. " ADDMF ,Addressing mode main memory address" "Post-increment,Constant"
textline " "
bitfld.long 0x08 18.--19. " TMBA ,Transfer mode for buffer A" "One shot,Circular,Auto switch,Auto switch"
bitfld.long 0x08 16.--17. " TMBB ,Transfer mode for buffer B" "One shot,Circular,Auto switch,Auto switch"
textline " "
hexmask.long.word 0x08 2.--12. 0x04 " IHADDR ,Initial NHET address"
line.long 0x0C "ITCOUNT,Initial Transfer Count"
bitfld.long 0x0C 16.--20. " IETCOUNT ,Initial element transfer count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
hexmask.long.byte 0x0C 0.--7. 1. " IFTCOUNT ,Initial frame transfer count"
group.long (0x20+0x100)++0x0B
line.long 0x00 "CFADDRA,Current Main Memory Address Control Packet A"
line.long 0x04 "CFADDRB,Current Main Memory Address Control Packet B"
line.long 0x08 "CFCOUNT,Current Frame Count"
hexmask.long.byte 0x08 16.--23. 1. " CFTCTA ,Current frame transfer count for CP A"
hexmask.long.byte 0x08 0.--7. 1. " CFTCTB ,Current frame transfer count for CP B"
tree.end
tree "Set 3"
group.long (0x30+0x00)++0x0F
line.long 0x00 "IFADDRA,Initial Main Memory Address Control Packet A"
line.long 0x04 "IFADDRB,Initial Main Memory Address Control Packet B"
line.long 0x08 "IHADDRCT,Initial NHET Address And Control"
bitfld.long 0x08 23. " DIR ,Direction of transfer (Read->write)" "Nhet->main,Main->nhet"
bitfld.long 0x08 22. " SIZE ,Size of transferred data" "32-bit,64-bit"
textline " "
bitfld.long 0x08 21. " ADDMH ,Addressing mode NHET address (Increment value)" "16 bytes,8 bytes"
bitfld.long 0x08 20. " ADDMF ,Addressing mode main memory address" "Post-increment,Constant"
textline " "
bitfld.long 0x08 18.--19. " TMBA ,Transfer mode for buffer A" "One shot,Circular,Auto switch,Auto switch"
bitfld.long 0x08 16.--17. " TMBB ,Transfer mode for buffer B" "One shot,Circular,Auto switch,Auto switch"
textline " "
hexmask.long.word 0x08 2.--12. 0x04 " IHADDR ,Initial NHET address"
line.long 0x0C "ITCOUNT,Initial Transfer Count"
bitfld.long 0x0C 16.--20. " IETCOUNT ,Initial element transfer count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
hexmask.long.byte 0x0C 0.--7. 1. " IFTCOUNT ,Initial frame transfer count"
group.long (0x30+0x100)++0x0B
line.long 0x00 "CFADDRA,Current Main Memory Address Control Packet A"
line.long 0x04 "CFADDRB,Current Main Memory Address Control Packet B"
line.long 0x08 "CFCOUNT,Current Frame Count"
hexmask.long.byte 0x08 16.--23. 1. " CFTCTA ,Current frame transfer count for CP A"
hexmask.long.byte 0x08 0.--7. 1. " CFTCTB ,Current frame transfer count for CP B"
tree.end
tree "Set 4"
group.long (0x40+0x00)++0x0F
line.long 0x00 "IFADDRA,Initial Main Memory Address Control Packet A"
line.long 0x04 "IFADDRB,Initial Main Memory Address Control Packet B"
line.long 0x08 "IHADDRCT,Initial NHET Address And Control"
bitfld.long 0x08 23. " DIR ,Direction of transfer (Read->write)" "Nhet->main,Main->nhet"
bitfld.long 0x08 22. " SIZE ,Size of transferred data" "32-bit,64-bit"
textline " "
bitfld.long 0x08 21. " ADDMH ,Addressing mode NHET address (Increment value)" "16 bytes,8 bytes"
bitfld.long 0x08 20. " ADDMF ,Addressing mode main memory address" "Post-increment,Constant"
textline " "
bitfld.long 0x08 18.--19. " TMBA ,Transfer mode for buffer A" "One shot,Circular,Auto switch,Auto switch"
bitfld.long 0x08 16.--17. " TMBB ,Transfer mode for buffer B" "One shot,Circular,Auto switch,Auto switch"
textline " "
hexmask.long.word 0x08 2.--12. 0x04 " IHADDR ,Initial NHET address"
line.long 0x0C "ITCOUNT,Initial Transfer Count"
bitfld.long 0x0C 16.--20. " IETCOUNT ,Initial element transfer count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
hexmask.long.byte 0x0C 0.--7. 1. " IFTCOUNT ,Initial frame transfer count"
group.long (0x40+0x100)++0x0B
line.long 0x00 "CFADDRA,Current Main Memory Address Control Packet A"
line.long 0x04 "CFADDRB,Current Main Memory Address Control Packet B"
line.long 0x08 "CFCOUNT,Current Frame Count"
hexmask.long.byte 0x08 16.--23. 1. " CFTCTA ,Current frame transfer count for CP A"
hexmask.long.byte 0x08 0.--7. 1. " CFTCTB ,Current frame transfer count for CP B"
tree.end
tree "Set 5"
group.long (0x50+0x00)++0x0F
line.long 0x00 "IFADDRA,Initial Main Memory Address Control Packet A"
line.long 0x04 "IFADDRB,Initial Main Memory Address Control Packet B"
line.long 0x08 "IHADDRCT,Initial NHET Address And Control"
bitfld.long 0x08 23. " DIR ,Direction of transfer (Read->write)" "Nhet->main,Main->nhet"
bitfld.long 0x08 22. " SIZE ,Size of transferred data" "32-bit,64-bit"
textline " "
bitfld.long 0x08 21. " ADDMH ,Addressing mode NHET address (Increment value)" "16 bytes,8 bytes"
bitfld.long 0x08 20. " ADDMF ,Addressing mode main memory address" "Post-increment,Constant"
textline " "
bitfld.long 0x08 18.--19. " TMBA ,Transfer mode for buffer A" "One shot,Circular,Auto switch,Auto switch"
bitfld.long 0x08 16.--17. " TMBB ,Transfer mode for buffer B" "One shot,Circular,Auto switch,Auto switch"
textline " "
hexmask.long.word 0x08 2.--12. 0x04 " IHADDR ,Initial NHET address"
line.long 0x0C "ITCOUNT,Initial Transfer Count"
bitfld.long 0x0C 16.--20. " IETCOUNT ,Initial element transfer count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
hexmask.long.byte 0x0C 0.--7. 1. " IFTCOUNT ,Initial frame transfer count"
group.long (0x50+0x100)++0x0B
line.long 0x00 "CFADDRA,Current Main Memory Address Control Packet A"
line.long 0x04 "CFADDRB,Current Main Memory Address Control Packet B"
line.long 0x08 "CFCOUNT,Current Frame Count"
hexmask.long.byte 0x08 16.--23. 1. " CFTCTA ,Current frame transfer count for CP A"
hexmask.long.byte 0x08 0.--7. 1. " CFTCTB ,Current frame transfer count for CP B"
tree.end
tree "Set 6"
group.long (0x60+0x00)++0x0F
line.long 0x00 "IFADDRA,Initial Main Memory Address Control Packet A"
line.long 0x04 "IFADDRB,Initial Main Memory Address Control Packet B"
line.long 0x08 "IHADDRCT,Initial NHET Address And Control"
bitfld.long 0x08 23. " DIR ,Direction of transfer (Read->write)" "Nhet->main,Main->nhet"
bitfld.long 0x08 22. " SIZE ,Size of transferred data" "32-bit,64-bit"
textline " "
bitfld.long 0x08 21. " ADDMH ,Addressing mode NHET address (Increment value)" "16 bytes,8 bytes"
bitfld.long 0x08 20. " ADDMF ,Addressing mode main memory address" "Post-increment,Constant"
textline " "
bitfld.long 0x08 18.--19. " TMBA ,Transfer mode for buffer A" "One shot,Circular,Auto switch,Auto switch"
bitfld.long 0x08 16.--17. " TMBB ,Transfer mode for buffer B" "One shot,Circular,Auto switch,Auto switch"
textline " "
hexmask.long.word 0x08 2.--12. 0x04 " IHADDR ,Initial NHET address"
line.long 0x0C "ITCOUNT,Initial Transfer Count"
bitfld.long 0x0C 16.--20. " IETCOUNT ,Initial element transfer count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
hexmask.long.byte 0x0C 0.--7. 1. " IFTCOUNT ,Initial frame transfer count"
group.long (0x60+0x100)++0x0B
line.long 0x00 "CFADDRA,Current Main Memory Address Control Packet A"
line.long 0x04 "CFADDRB,Current Main Memory Address Control Packet B"
line.long 0x08 "CFCOUNT,Current Frame Count"
hexmask.long.byte 0x08 16.--23. 1. " CFTCTA ,Current frame transfer count for CP A"
hexmask.long.byte 0x08 0.--7. 1. " CFTCTB ,Current frame transfer count for CP B"
tree.end
tree "Set 7"
group.long (0x70+0x00)++0x0F
line.long 0x00 "IFADDRA,Initial Main Memory Address Control Packet A"
line.long 0x04 "IFADDRB,Initial Main Memory Address Control Packet B"
line.long 0x08 "IHADDRCT,Initial NHET Address And Control"
bitfld.long 0x08 23. " DIR ,Direction of transfer (Read->write)" "Nhet->main,Main->nhet"
bitfld.long 0x08 22. " SIZE ,Size of transferred data" "32-bit,64-bit"
textline " "
bitfld.long 0x08 21. " ADDMH ,Addressing mode NHET address (Increment value)" "16 bytes,8 bytes"
bitfld.long 0x08 20. " ADDMF ,Addressing mode main memory address" "Post-increment,Constant"
textline " "
bitfld.long 0x08 18.--19. " TMBA ,Transfer mode for buffer A" "One shot,Circular,Auto switch,Auto switch"
bitfld.long 0x08 16.--17. " TMBB ,Transfer mode for buffer B" "One shot,Circular,Auto switch,Auto switch"
textline " "
hexmask.long.word 0x08 2.--12. 0x04 " IHADDR ,Initial NHET address"
line.long 0x0C "ITCOUNT,Initial Transfer Count"
bitfld.long 0x0C 16.--20. " IETCOUNT ,Initial element transfer count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
hexmask.long.byte 0x0C 0.--7. 1. " IFTCOUNT ,Initial frame transfer count"
group.long (0x70+0x100)++0x0B
line.long 0x00 "CFADDRA,Current Main Memory Address Control Packet A"
line.long 0x04 "CFADDRB,Current Main Memory Address Control Packet B"
line.long 0x08 "CFCOUNT,Current Frame Count"
hexmask.long.byte 0x08 16.--23. 1. " CFTCTA ,Current frame transfer count for CP A"
hexmask.long.byte 0x08 0.--7. 1. " CFTCTB ,Current frame transfer count for CP B"
tree.end
tree.end
width 0x0B
tree.end
tree.end
tree.open "GIO (General Purpose Input/Output Module)"
tree "GPIO"
base ad:0xFFF7BC00
width 8.
group.long 0x00++0x03
line.long 0x00 "GCR0,Global Control Register"
bitfld.long 0x00 0. " RESET ,GIO reset" "Reset,Normal"
textline " "
group.long 0x08++0x03
line.long 0x00 "INTDET,Interrupt Detect"
bitfld.long 0x00 15. " INTDET1_[7] ,GIOB7 interrupt detection select" "Falling/rising,Both"
bitfld.long 0x00 14. " [6] ,GIOB6 interrupt detection select" "Falling/rising,Both"
bitfld.long 0x00 13. " [5] ,GIOB5 interrupt detection select" "Falling/rising,Both"
bitfld.long 0x00 12. " [4] ,GIOB4 interrupt detection select" "Falling/rising,Both"
textline " "
bitfld.long 0x00 11. " [3] ,GIOB3 interrupt detection select" "Falling/rising,Both"
bitfld.long 0x00 10. " [2] ,GIOB2 interrupt detection select" "Falling/rising,Both"
bitfld.long 0x00 9. " [1] ,GIOB1 interrupt detection select" "Falling/rising,Both"
bitfld.long 0x00 8. " [0] ,GIOB0 interrupt detection select" "Falling/rising,Both"
textline " "
bitfld.long 0x00 7. " INTDET0_[7] ,GIOA7 interrupt detection select" "Falling/rising,Both"
bitfld.long 0x00 6. " [6] ,GIOA6 interrupt detection select" "Falling/rising,Both"
bitfld.long 0x00 5. " [5] ,GIOA5 interrupt detection select" "Falling/rising,Both"
bitfld.long 0x00 4. " [4] ,GIOA4 interrupt detection select" "Falling/rising,Both"
textline " "
bitfld.long 0x00 3. " [3] ,GIOA3 interrupt detection select" "Falling/rising,Both"
bitfld.long 0x00 2. " [2] ,GIOA2 interrupt detection select" "Falling/rising,Both"
bitfld.long 0x00 1. " [1] ,GIOA1 interrupt detection select" "Falling/rising,Both"
bitfld.long 0x00 0. " [0] ,GIOA0 interrupt detection select" "Falling/rising,Both"
group.long 0x0C++0x03
line.long 0x00 "POL,Interrupt Polarity"
bitfld.long 0x00 15. " GIOPOL1_[7] ,GIOB7 interrupt polarity select (User-priviledge/low power mode)" "Falling/low,Rising/high"
bitfld.long 0x00 14. " [6] ,GIOB6 interrupt polarity select (User-priviledge/low power mode)" "Falling/low,Rising/high"
bitfld.long 0x00 13. " [5] ,GIOB5 interrupt polarity select (User-priviledge/low power mode)" "Falling/low,Rising/high"
bitfld.long 0x00 12. " [4] ,GIOB4 interrupt polarity select (User-priviledge/low power mode)" "Falling/low,Rising/high"
textline " "
bitfld.long 0x00 11. " [3] ,GIOB3 interrupt polarity select (User-priviledge/low power mode)" "Falling/low,Rising/high"
bitfld.long 0x00 10. " [2] ,GIOB2 interrupt polarity select (User-priviledge/low power mode)" "Falling/low,Rising/high"
bitfld.long 0x00 9. " [1] ,GIOB1 interrupt polarity select (User-priviledge/low power mode)" "Falling/low,Rising/high"
bitfld.long 0x00 8. " [0] ,GIOB0 interrupt polarity select (User-priviledge/low power mode)" "Falling/low,Rising/high"
textline " "
bitfld.long 0x00 7. " GIOPOL0_[7] ,GIOA7 interrupt polarity select (User-priviledge/low power mode)" "Falling/low,Rising/high"
bitfld.long 0x00 6. " [6] ,GIOA6 interrupt polarity select (User-priviledge/low power mode)" "Falling/low,Rising/high"
bitfld.long 0x00 5. " [5] ,GIOA5 interrupt polarity select (User-priviledge/low power mode)" "Falling/low,Rising/high"
bitfld.long 0x00 4. " [4] ,GIOA4 interrupt polarity select (User-priviledge/low power mode)" "Falling/low,Rising/high"
textline " "
bitfld.long 0x00 3. " [3] ,GIOA3 interrupt polarity select (User-priviledge/low power mode)" "Falling/low,Rising/high"
bitfld.long 0x00 2. " [2] ,GIOA2 interrupt polarity select (User-priviledge/low power mode)" "Falling/low,Rising/high"
bitfld.long 0x00 1. " [1] ,GIOA1 interrupt polarity select (User-priviledge/low power mode)" "Falling/low,Rising/high"
bitfld.long 0x00 0. " [0] ,GIOA0 interrupt polarity select (User-priviledge/low power mode)" "Falling/low,Rising/high"
textline " "
group.long 0x10++0x03
line.long 0x00 "ENA,Interrupt Enable"
setclrfld.long 0x00 15. 0x00 15. 0x04 15. " GIOENA1_SET/CLR_[7] ,GIOB7 interrupt enable" "Disabled,Enabled"
setclrfld.long 0x00 14. 0x00 14. 0x04 14. " [6] ,GIOB6 interrupt enable" "Disabled,Enabled"
setclrfld.long 0x00 13. 0x00 13. 0x04 13. " [5] ,GIOB5 interrupt enable" "Disabled,Enabled"
setclrfld.long 0x00 12. 0x00 12. 0x04 12. " [4] ,GIOB4 interrupt enable" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 11. 0x00 11. 0x04 11. " [3] ,GIOB3 interrupt enable" "Disabled,Enabled"
setclrfld.long 0x00 10. 0x00 10. 0x04 10. " [2] ,GIOB2 interrupt enable" "Disabled,Enabled"
setclrfld.long 0x00 9. 0x00 9. 0x04 9. " [1] ,GIOB1 interrupt enable" "Disabled,Enabled"
setclrfld.long 0x00 8. 0x00 8. 0x04 8. " [0] ,GIOB0 interrupt enable" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 7. 0x00 7. 0x04 7. " GIOENA0_SET/CLR_[7] ,GIOA7 interrupt enable" "Disabled,Enabled"
setclrfld.long 0x00 6. 0x00 6. 0x04 6. " [6] ,GIOA6 interrupt enable" "Disabled,Enabled"
setclrfld.long 0x00 5. 0x00 5. 0x04 5. " [5] ,GIOA5 interrupt enable" "Disabled,Enabled"
setclrfld.long 0x00 4. 0x00 4. 0x04 4. " [4] ,GIOA4 interrupt enable" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 3. 0x00 3. 0x04 3. " [3] ,GIOA3 interrupt enable" "Disabled,Enabled"
setclrfld.long 0x00 2. 0x00 2. 0x04 2. " [2] ,GIOA2 interrupt enable" "Disabled,Enabled"
setclrfld.long 0x00 1. 0x00 1. 0x04 1. " [1] ,GIOA1 interrupt enable" "Disabled,Enabled"
setclrfld.long 0x00 0. 0x00 0. 0x04 0. " [0] ,GIOA0 interrupt enable" "Disabled,Enabled"
group.long 0x18++0x03
line.long 0x00 "LVL,Interrupt Priority"
setclrfld.long 0x00 15. 0x00 15. 0x04 15. " GIOLVL1_SET/CLR_[7] ,GIOB7 interrupt priority" "Low,High"
setclrfld.long 0x00 14. 0x00 14. 0x04 14. " [6] ,GIOB6 interrupt priority" "Low,High"
setclrfld.long 0x00 13. 0x00 13. 0x04 13. " [5] ,GIOB5 interrupt priority" "Low,High"
setclrfld.long 0x00 12. 0x00 12. 0x04 12. " [4] ,GIOB4 interrupt priority" "Low,High"
textline " "
setclrfld.long 0x00 11. 0x00 11. 0x04 11. " [3] ,GIOB3 interrupt priority" "Low,High"
setclrfld.long 0x00 10. 0x00 10. 0x04 10. " [2] ,GIOB2 interrupt priority" "Low,High"
setclrfld.long 0x00 9. 0x00 9. 0x04 9. " [1] ,GIOB1 interrupt priority" "Low,High"
setclrfld.long 0x00 8. 0x00 8. 0x04 8. " [0] ,GIOB0 interrupt priority" "Low,High"
textline " "
setclrfld.long 0x00 7. 0x00 7. 0x04 7. " GIOLVL0_SET/CLR_[7] ,GIOA7 interrupt priority" "Low,High"
setclrfld.long 0x00 6. 0x00 6. 0x04 6. " [6] ,GIOA6 interrupt priority" "Low,High"
setclrfld.long 0x00 5. 0x00 5. 0x04 5. " [5] ,GIOA5 interrupt priority" "Low,High"
setclrfld.long 0x00 4. 0x00 4. 0x04 4. " [4] ,GIOA4 interrupt priority" "Low,High"
textline " "
setclrfld.long 0x00 3. 0x00 3. 0x04 3. " [3] ,GIOA3 interrupt priority" "Low,High"
setclrfld.long 0x00 2. 0x00 2. 0x04 2. " [2] ,GIOA2 interrupt priority" "Low,High"
setclrfld.long 0x00 1. 0x00 1. 0x04 1. " [1] ,GIOA1 interrupt priority" "Low,High"
setclrfld.long 0x00 0. 0x00 0. 0x04 0. " [0] ,GIOA0 interrupt priority" "Low,High"
textline " "
group.long 0x20++0x03
line.long 0x00 "FLG,Interrupt Flag"
eventfld.long 0x00 15. " GIOFLG1_[7] ,GIOB7 flag" "No interrupt,Interrupt"
eventfld.long 0x00 14. " [6] ,GIOB6 flag" "No interrupt,Interrupt"
eventfld.long 0x00 13. " [5] ,GIOB5 flag" "No interrupt,Interrupt"
eventfld.long 0x00 12. " [4] ,GIOB4 flag" "No interrupt,Interrupt"
textline " "
eventfld.long 0x00 11. " [3] ,GIOB3 flag" "No interrupt,Interrupt"
eventfld.long 0x00 10. " [2] ,GIOB2 flag" "No interrupt,Interrupt"
eventfld.long 0x00 9. " [1] ,GIOB1 flag" "No interrupt,Interrupt"
eventfld.long 0x00 8. " [0] ,GIOB0 flag" "No interrupt,Interrupt"
textline " "
eventfld.long 0x00 7. " GIOFLG0_[7] ,GIOA7 flag" "No interrupt,Interrupt"
eventfld.long 0x00 6. " [6] ,GIOA6 flag" "No interrupt,Interrupt"
eventfld.long 0x00 5. " [5] ,GIOA5 flag" "No interrupt,Interrupt"
eventfld.long 0x00 4. " [4] ,GIOA4 flag" "No interrupt,Interrupt"
textline " "
eventfld.long 0x00 3. " [3] ,GIOA3 flag" "No interrupt,Interrupt"
eventfld.long 0x00 2. " [2] ,GIOA2 flag" "No interrupt,Interrupt"
eventfld.long 0x00 1. " [1] ,GIOA1 flag" "No interrupt,Interrupt"
eventfld.long 0x00 0. " [0] ,GIOA0 flag" "No interrupt,Interrupt"
textline " "
hgroup.long 0x24++0x03
hide.long 0x00 "OFF1,Offset 1"
in
rgroup.long 0x2C++0x03
line.long 0x00 "EMU1,Emulation 1"
bitfld.long 0x00 0.--5. " GIOEMU1 ,GIO offset 1" "No interrupt,GIOA0 interrupt,GIOA1 interrupt,GIOA2 interrupt,GIOA3 interrupt,GIOA4 interrupt,GIOA5 interrupt,GIOA6 interrupt,GIOA7 interrupt,GIOB0 interrupt,GIOB1 interrupt,GIOB2 interrupt,GIOB3 interrupt,GIOB4 interrupt,GIOB5 interrupt,GIOB6 interrupt,GIOB7 interrupt,?..."
hgroup.long 0x28++0x03
hide.long 0x00 "OFF2,Offset 2"
in
rgroup.long 0x30++0x03
line.long 0x00 "EMU2,Emulation 2"
bitfld.long 0x00 0.--5. " GIOEMU2 ,GIO offset 2" "No interrupt,GIOA0 interrupt,GIOA1 interrupt,GIOA2 interrupt,GIOA3 interrupt,GIOA4 interrupt,GIOA5 interrupt,GIOA6 interrupt,GIOA7 interrupt,GIOB0 interrupt,GIOB1 interrupt,GIOB2 interrupt,GIOB3 interrupt,GIOB4 interrupt,GIOB5 interrupt,GIOB6 interrupt,GIOB7 interrupt,?..."
width 0x0B
tree.end
tree "GPIO_A"
base ad:0xFFF7BC00
width 9.
rgroup.long 0x34++0x03
line.long 0x00 "DIR,Data Direction GIOA"
bitfld.long 0x00 7. " GIODIR_[7] ,GIO data direction 7" "Output disabled,Output enabled"
bitfld.long 0x00 6. " [6] ,GIO data direction 6" "Output disabled,Output enabled"
bitfld.long 0x00 5. " [5] ,GIO data direction 5" "Output disabled,Output enabled"
bitfld.long 0x00 4. " [4] ,GIO data direction 4" "Output disabled,Output enabled"
textline " "
bitfld.long 0x00 3. " [3] ,GIO data direction 3" "Output disabled,Output enabled"
bitfld.long 0x00 2. " [2] ,GIO data direction 2" "Output disabled,Output enabled"
bitfld.long 0x00 1. " [1] ,GIO data direction 1" "Output disabled,Output enabled"
bitfld.long 0x00 0. " [0] ,GIO data direction 0" "Output disabled,Output enabled"
rgroup.long 0x38++0x03
line.long 0x00 "DIN,Data Input GIOA"
bitfld.long 0x00 7. " GIODIN_[7] ,GIO data input 7" "Low,High"
bitfld.long 0x00 6. " [6] ,GIO data input 6" "Low,High"
bitfld.long 0x00 5. " [5] ,GIO data input 5" "Low,High"
bitfld.long 0x00 4. " [4] ,GIO data input 4" "Low,High"
textline " "
bitfld.long 0x00 3. " [3] ,GIO data input 3" "Low,High"
bitfld.long 0x00 2. " [2] ,GIO data input 2" "Low,High"
bitfld.long 0x00 1. " [1] ,GIO data input 1" "Low,High"
bitfld.long 0x00 0. " [0] ,GIO data input 0" "Low,High"
textline " "
group.long 0x3C++0x03
line.long 0x00 "DOUT,Data Output GIOA"
setclrfld.long 0x00 7. 0x04 7. 0x08 7. " GIODOUT_SET/CLR_[7] ,GIO data output 7" "Low,High"
setclrfld.long 0x00 6. 0x04 6. 0x08 6. " [6] ,GIO data output 6" "Low,High"
setclrfld.long 0x00 5. 0x04 5. 0x08 5. " [5] ,GIO data output 5" "Low,High"
setclrfld.long 0x00 4. 0x04 4. 0x08 4. " [4] ,GIO data output 4" "Low,High"
textline " "
setclrfld.long 0x00 3. 0x04 3. 0x08 3. " [3] ,GIO data output 3" "Low,High"
setclrfld.long 0x00 2. 0x04 2. 0x08 2. " [2] ,GIO data output 2" "Low,High"
setclrfld.long 0x00 1. 0x04 1. 0x08 1. " [1] ,GIO data output 1" "Low,High"
setclrfld.long 0x00 0. 0x04 0. 0x08 0. " [0] ,GIO data output 0" "Low,High"
textline " "
group.long 0x48++0x03
line.long 0x00 "PDR,Open Drain GIOA"
bitfld.long 0x00 7. " GIOPDR[7] ,GIO open drain 7" "Disabled,Enabled"
bitfld.long 0x00 6. " [6] ,GIO open drain 6" "Disabled,Enabled"
bitfld.long 0x00 5. " [5] ,GIO open drain 5" "Disabled,Enabled"
bitfld.long 0x00 4. " [4] ,GIO open drain 4" "Disabled,Enabled"
textline " "
bitfld.long 0x00 3. " [3] ,GIO open drain 3" "Disabled,Enabled"
bitfld.long 0x00 2. " [2] ,GIO open drain 2" "Disabled,Enabled"
bitfld.long 0x00 1. " [1] ,GIO open drain 1" "Disabled,Enabled"
bitfld.long 0x00 0. " [0] ,GIO open drain 0" "Disabled,Enabled"
textline " "
group.long 0x4C++0x03
line.long 0x00 "PULLDIS,Pull Disable GIOA"
bitfld.long 0x00 7. " GIOPULDIS_[7] ,GIO pull disable 7" "No,Yes"
bitfld.long 0x00 6. " [6] ,GIO pull disable 6" "No,Yes"
bitfld.long 0x00 5. " [5] ,GIO pull disable 5" "No,Yes"
bitfld.long 0x00 4. " [4] ,GIO pull disable 4" "No,Yes"
textline " "
bitfld.long 0x00 3. " [3] ,GIO pull disable 3" "No,Yes"
bitfld.long 0x00 2. " [2] ,GIO pull disable 2" "No,Yes"
bitfld.long 0x00 1. " [1] ,GIO pull disable 1" "No,Yes"
bitfld.long 0x00 0. " [0] ,GIO pull disable 0" "No,Yes"
textline " "
group.long 0x50++0x03
line.long 0x00 "PSL,Pull Select GIOA"
bitfld.long 0x00 7. " GIOPSL[7] ,GIO pull select 7" "Pull down,Pull up"
bitfld.long 0x00 6. " [6] ,GIO pull select 6" "Pull down,Pull up"
bitfld.long 0x00 5. " [5] ,GIO pull select 5" "Pull down,Pull up"
bitfld.long 0x00 4. " [4] ,GIO pull select 4" "Pull down,Pull up"
textline " "
bitfld.long 0x00 3. " [3] ,GIO pull select 3" "Pull down,Pull up"
bitfld.long 0x00 2. " [2] ,GIO pull select 2" "Pull down,Pull up"
bitfld.long 0x00 1. " [1] ,GIO pull select 1" "Pull down,Pull up"
bitfld.long 0x00 0. " [0] ,GIO pull select 0" "Pull down,Pull up"
width 0x0B
tree.end
tree "GPIO_B"
base ad:0xFFF7BC20
width 9.
rgroup.long 0x34++0x03
line.long 0x00 "DIR,Data Direction GIOB"
bitfld.long 0x00 7. " GIODIR_[7] ,GIO data direction 7" "Output disabled,Output enabled"
bitfld.long 0x00 6. " [6] ,GIO data direction 6" "Output disabled,Output enabled"
bitfld.long 0x00 5. " [5] ,GIO data direction 5" "Output disabled,Output enabled"
bitfld.long 0x00 4. " [4] ,GIO data direction 4" "Output disabled,Output enabled"
textline " "
bitfld.long 0x00 3. " [3] ,GIO data direction 3" "Output disabled,Output enabled"
bitfld.long 0x00 2. " [2] ,GIO data direction 2" "Output disabled,Output enabled"
bitfld.long 0x00 1. " [1] ,GIO data direction 1" "Output disabled,Output enabled"
bitfld.long 0x00 0. " [0] ,GIO data direction 0" "Output disabled,Output enabled"
rgroup.long 0x38++0x03
line.long 0x00 "DIN,Data Input GIOB"
bitfld.long 0x00 7. " GIODIN_[7] ,GIO data input 7" "Low,High"
bitfld.long 0x00 6. " [6] ,GIO data input 6" "Low,High"
bitfld.long 0x00 5. " [5] ,GIO data input 5" "Low,High"
bitfld.long 0x00 4. " [4] ,GIO data input 4" "Low,High"
textline " "
bitfld.long 0x00 3. " [3] ,GIO data input 3" "Low,High"
bitfld.long 0x00 2. " [2] ,GIO data input 2" "Low,High"
bitfld.long 0x00 1. " [1] ,GIO data input 1" "Low,High"
bitfld.long 0x00 0. " [0] ,GIO data input 0" "Low,High"
textline " "
group.long 0x3C++0x03
line.long 0x00 "DOUT,Data Output GIOB"
setclrfld.long 0x00 7. 0x04 7. 0x08 7. " GIODOUT_SET/CLR_[7] ,GIO data output 7" "Low,High"
setclrfld.long 0x00 6. 0x04 6. 0x08 6. " [6] ,GIO data output 6" "Low,High"
setclrfld.long 0x00 5. 0x04 5. 0x08 5. " [5] ,GIO data output 5" "Low,High"
setclrfld.long 0x00 4. 0x04 4. 0x08 4. " [4] ,GIO data output 4" "Low,High"
textline " "
setclrfld.long 0x00 3. 0x04 3. 0x08 3. " [3] ,GIO data output 3" "Low,High"
setclrfld.long 0x00 2. 0x04 2. 0x08 2. " [2] ,GIO data output 2" "Low,High"
setclrfld.long 0x00 1. 0x04 1. 0x08 1. " [1] ,GIO data output 1" "Low,High"
setclrfld.long 0x00 0. 0x04 0. 0x08 0. " [0] ,GIO data output 0" "Low,High"
textline " "
group.long 0x48++0x03
line.long 0x00 "PDR,Open Drain GIOB"
bitfld.long 0x00 7. " GIOPDR[7] ,GIO open drain 7" "Disabled,Enabled"
bitfld.long 0x00 6. " [6] ,GIO open drain 6" "Disabled,Enabled"
bitfld.long 0x00 5. " [5] ,GIO open drain 5" "Disabled,Enabled"
bitfld.long 0x00 4. " [4] ,GIO open drain 4" "Disabled,Enabled"
textline " "
bitfld.long 0x00 3. " [3] ,GIO open drain 3" "Disabled,Enabled"
bitfld.long 0x00 2. " [2] ,GIO open drain 2" "Disabled,Enabled"
bitfld.long 0x00 1. " [1] ,GIO open drain 1" "Disabled,Enabled"
bitfld.long 0x00 0. " [0] ,GIO open drain 0" "Disabled,Enabled"
textline " "
group.long 0x4C++0x03
line.long 0x00 "PULLDIS,Pull Disable GIOB"
bitfld.long 0x00 7. " GIOPULDIS_[7] ,GIO pull disable 7" "No,Yes"
bitfld.long 0x00 6. " [6] ,GIO pull disable 6" "No,Yes"
bitfld.long 0x00 5. " [5] ,GIO pull disable 5" "No,Yes"
bitfld.long 0x00 4. " [4] ,GIO pull disable 4" "No,Yes"
textline " "
bitfld.long 0x00 3. " [3] ,GIO pull disable 3" "No,Yes"
bitfld.long 0x00 2. " [2] ,GIO pull disable 2" "No,Yes"
bitfld.long 0x00 1. " [1] ,GIO pull disable 1" "No,Yes"
bitfld.long 0x00 0. " [0] ,GIO pull disable 0" "No,Yes"
textline " "
group.long 0x50++0x03
line.long 0x00 "PSL,Pull Select GIOB"
bitfld.long 0x00 7. " GIOPSL[7] ,GIO pull select 7" "Pull down,Pull up"
bitfld.long 0x00 6. " [6] ,GIO pull select 6" "Pull down,Pull up"
bitfld.long 0x00 5. " [5] ,GIO pull select 5" "Pull down,Pull up"
bitfld.long 0x00 4. " [4] ,GIO pull select 4" "Pull down,Pull up"
textline " "
bitfld.long 0x00 3. " [3] ,GIO pull select 3" "Pull down,Pull up"
bitfld.long 0x00 2. " [2] ,GIO pull select 2" "Pull down,Pull up"
bitfld.long 0x00 1. " [1] ,GIO pull select 1" "Pull down,Pull up"
bitfld.long 0x00 0. " [0] ,GIO pull select 0" "Pull down,Pull up"
width 0x0B
tree.end
tree.end
tree.open "FlexRay Module"
tree "Transfer Unit"
base ad:0xFFF7A000
width 11.
rgroup.long 0x00++0x7
line.long 0x0 "GSN0,Global Static Number 0"
hexmask.long.word 0x00 16.--31. 1. " DATA_A ,Data A"
hexmask.long.word 0x00 0.--15. 1. " DATA_B ,Data A Complement"
line.long 0x04 "GSN1,Global Static Number 1"
hexmask.long.word 0x04 16.--31. 1. " DATA_C ,Data C"
hexmask.long.word 0x04 0.--15. 1. " DATA_D ,Data C Complement"
group.long 0x10++0x7
line.long 0x0 "GCS/R,Global Control Set/Reset"
setclrfld.long 0x00 31. 0x00 31. 0x04 31. " ENDVBM_set/clr ,Endianess Correction on VBusp Master" "Off,On"
setclrfld.long 0x00 30. 0x00 30. 0x04 30. " ENDVBS_set/clr ,ENDianess correction on VBusp Slave" "Off,On"
bitfld.long 0x00 28.--29. " ENDR ,ENDianess Correction for No (header or payload) Data Sink Access" "0xABCD,0xBADC,0xCDAB,0xDCBA"
textline " "
bitfld.long 0x00 26.--27. " ENDH ,ENDianess Correction for Header" "0xABCD,0xBADC,0xCDAB,0xDCBA"
bitfld.long 0x00 24.--25. " ENDP ,ENDianess Correction for Payload" "0xABCD,0xBADC,0xCDAB,0xDCBA"
setclrfld.long 0x00 21. 0x00 21. 0x04 21. " PRIO_set/clr ,Transfer Priority" "TTSM>TTCC,TTCC>TTSM"
textline " "
bitfld.long 0x00 16.--19. " PEL ,Parity/ECC Lock" "On,On,On,On,On,Off,On,On,On,On,On,On,On,On,On,On"
setclrfld.long 0x00 14. 0x00 14. 0x04 14. " CETESM_set/clr ,Clear ETESM Register" "Not cleared,Cleared"
setclrfld.long 0x00 13. 0x00 13. 0x04 13. " CTTCC_set/clr ,Clear TTCC Register" "Not cleared,Cleared"
textline " "
setclrfld.long 0x00 12. 0x00 12. 0x04 12. " CTTSM_set/clr ,Clear TTSM Register" "Not cleared,Cleared"
setclrfld.long 0x00 8. 0x00 8. 0x04 8. " ETSM_set/clr ,Enable Transfer Status Mirrored (TSCB/LTBCC/LTBSM/TSMO1-4/TCCO1-4/TOOFF)" "Disabled,Enabled"
setclrfld.long 0x00 5. 0x00 5. 0x04 5. " SILE_set/clr ,Status Interrupt Line Enable (TU_int0)" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 4. 0x00 4. 0x04 4. " EILE_set/clr ,Error Interrupt Line Enable (TU_int1)" "Disabled,Enabled"
setclrfld.long 0x00 1. 0x00 1. 0x04 1. " TUH_set/clr ,Transfer Unit Halted" "Not halted,Halted"
setclrfld.long 0x00 0. 0x00 0. 0x04 0. " TUE_set/clr ,Transfer Unit Enabled" "Disabled,Enabled"
line.long 0x04 "GCR,Global Control Clear"
bitfld.long 0x04 28.--29. " ENDR ,ENDianess Correction for No (header or payload) Data Sink Access" "0xABCD,0xBADC,0xCDAB,0xDCBA"
bitfld.long 0x04 26.--27. " ENDH ,ENDianess Correction for Header" "0xABCD,0xBADC,0xCDAB,0xDCBA"
bitfld.long 0x04 24.--25. " ENDP ,ENDianess Correction for Payload" "0xABCD,0xBADC,0xCDAB,0xDCBA"
textline " "
bitfld.long 0x04 16.--19. " PEL ,Parity/ECC Lock" "On,On,On,On,On,Off,On,On,On,On,On,On,On,On,On,On"
group.long 0x18++0x3
line.long 0x0 "TSCB,Transfer Status Current Buffer"
rbitfld.long 0x00 16.--20. " TSMS ,Transfer State Machine Status" "Normal,IDLE,TTSM_START,TTSM_OBCM,TTSM_REQ,TTSM_VIEW,TTSM_CHECK,TTSM_RDHS,TTSM_RDDS,TTCC_START,TTCC_IBUSY,TTCC_CHECK,TTCC_WRHS,TTCC_PLC_READ,TTCC_PLC_CALC,TTCC_WRDS,TTCC_IBCM,TTCC_IBCR,TTCC_MIRROR,TTSM_END,,,,,,,,,,,,Undefined state"
rbitfld.long 0x00 12. " STUH ,Status of Transfer Unit State Machine for Halt Detection" "Not halted,Halted"
eventfld.long 0x00 8. " IDLE ,Detects Transfer State Machine State IDLE" "Not reached,Reached"
textline " "
hexmask.long.byte 0x00 0.--6. 1. " BN ,Buffer Number"
rgroup.long 0x1c++0x7
line.long 0x00 "LTBCC,Last Transferred Buffer to Communication Controller"
hexmask.long.byte 0x00 0.--6. 1. " BN ,Buffer Number"
line.long 0x4 "LTBSM,Last Transferred Buffer to System Memory"
hexmask.long.byte 0x04 0.--6. 1. " BN ,Buffer Number"
group.long 0x24++0x13
line.long 0x0 "TBA,Transfer Base Address"
line.long 0x4 "NTBA,Next Transfer Base Address"
line.long 0x8 "BAMS,Base Address of Mirrored Status"
line.long 0xc "SAMP,Start Address of Memory Protection"
line.long 0x10 "EAMP,End Address of Memory Protection"
width 11.
group.long 0x40++0xf
line.long 0x0 "TSMO1,Transfer to System Memory Occurred 1"
eventfld.long 0x00 31. " TSMO1 [31] ,Transfer to System Memory Occurred Register 1 Buffer 31" "Not occurred,Occurred"
eventfld.long 0x00 30. " [30] ,Transfer to System Memory Occurred Register 1 Buffer 30" "Not occurred,Occurred"
eventfld.long 0x00 29. " [29] ,Transfer to System Memory Occurred Register 1 Buffer 29" "Not occurred,Occurred"
eventfld.long 0x00 28. " [28] ,Transfer to System Memory Occurred Register 1 Buffer 28" "Not occurred,Occurred"
eventfld.long 0x00 27. " [27] ,Transfer to System Memory Occurred Register 1 Buffer 27" "Not occurred,Occurred"
eventfld.long 0x00 26. " [26] ,Transfer to System Memory Occurred Register 1 Buffer 26" "Not occurred,Occurred"
textline " "
eventfld.long 0x00 25. " [25] ,Transfer to System Memory Occurred Register 1 Buffer 25" "Not occurred,Occurred"
eventfld.long 0x00 24. " [24] ,Transfer to System Memory Occurred Register 1 Buffer 24" "Not occurred,Occurred"
eventfld.long 0x00 23. " [23] ,Transfer to System Memory Occurred Register 1 Buffer 23" "Not occurred,Occurred"
eventfld.long 0x00 22. " [22] ,Transfer to System Memory Occurred Register 1 Buffer 22" "Not occurred,Occurred"
eventfld.long 0x00 21. " [21] ,Transfer to System Memory Occurred Register 1 Buffer 21" "Not occurred,Occurred"
eventfld.long 0x00 20. " [20] ,Transfer to System Memory Occurred Register 1 Buffer 20" "Not occurred,Occurred"
textline " "
eventfld.long 0x00 19. " [19] ,Transfer to System Memory Occurred Register 1 Buffer 19" "Not occurred,Occurred"
eventfld.long 0x00 18. " [18] ,Transfer to System Memory Occurred Register 1 Buffer 18" "Not occurred,Occurred"
eventfld.long 0x00 17. " [17] ,Transfer to System Memory Occurred Register 1 Buffer 17" "Not occurred,Occurred"
eventfld.long 0x00 16. " [16] ,Transfer to System Memory Occurred Register 1 Buffer 16" "Not occurred,Occurred"
eventfld.long 0x00 15. " [15] ,Transfer to System Memory Occurred Register 1 Buffer 15" "Not occurred,Occurred"
eventfld.long 0x00 14. " [14] ,Transfer to System Memory Occurred Register 1 Buffer 14" "Not occurred,Occurred"
textline " "
eventfld.long 0x00 13. " [13] ,Transfer to System Memory Occurred Register 1 Buffer 13" "Not occurred,Occurred"
eventfld.long 0x00 12. " [12] ,Transfer to System Memory Occurred Register 1 Buffer 12" "Not occurred,Occurred"
eventfld.long 0x00 11. " [11] ,Transfer to System Memory Occurred Register 1 Buffer 11" "Not occurred,Occurred"
eventfld.long 0x00 10. " [10] ,Transfer to System Memory Occurred Register 1 Buffer 10" "Not occurred,Occurred"
eventfld.long 0x00 9. " [9] ,Transfer to System Memory Occurred Register 1 Buffer 9" "Not occurred,Occurred"
eventfld.long 0x00 8. " [8] ,Transfer to System Memory Occurred Register 1 Buffer 8" "Not occurred,Occurred"
textline " "
eventfld.long 0x00 7. " [7] ,Transfer to System Memory Occurred Register 1 Buffer 7" "Not occurred,Occurred"
eventfld.long 0x00 6. " [6] ,Transfer to System Memory Occurred Register 1 Buffer 6" "Not occurred,Occurred"
eventfld.long 0x00 5. " [5] ,Transfer to System Memory Occurred Register 1 Buffer 5" "Not occurred,Occurred"
eventfld.long 0x00 4. " [4] ,Transfer to System Memory Occurred Register 1 Buffer 4" "Not occurred,Occurred"
eventfld.long 0x00 3. " [3] ,Transfer to System Memory Occurred Register 1 Buffer 3" "Not occurred,Occurred"
eventfld.long 0x00 2. " [2] ,Transfer to System Memory Occurred Register 1 Buffer 2" "Not occurred,Occurred"
textline " "
eventfld.long 0x00 1. " [1] ,Transfer to System Memory Occurred Register 1 Buffer 1" "Not occurred,Occurred"
eventfld.long 0x00 0. " [0] ,Transfer to System Memory Occurred Register 1 Buffer 0" "Not occurred,Occurred"
line.long 0x4 "TSMO2,Transfer to System Memory Occurred 2"
eventfld.long 0x04 31. " TSMO2 [31] ,Transfer to System Memory Occurred Register 2 Buffer 63" "Not occurred,Occurred"
eventfld.long 0x04 30. " [30] ,Transfer to System Memory Occurred Register 2 Buffer 62" "Not occurred,Occurred"
eventfld.long 0x04 29. " [29] ,Transfer to System Memory Occurred Register 2 Buffer 61" "Not occurred,Occurred"
eventfld.long 0x04 28. " [28] ,Transfer to System Memory Occurred Register 2 Buffer 60" "Not occurred,Occurred"
eventfld.long 0x04 27. " [27] ,Transfer to System Memory Occurred Register 2 Buffer 59" "Not occurred,Occurred"
eventfld.long 0x04 26. " [26] ,Transfer to System Memory Occurred Register 2 Buffer 58" "Not occurred,Occurred"
textline " "
eventfld.long 0x04 25. " [25] ,Transfer to System Memory Occurred Register 2 Buffer 57" "Not occurred,Occurred"
eventfld.long 0x04 24. " [24] ,Transfer to System Memory Occurred Register 2 Buffer 56" "Not occurred,Occurred"
eventfld.long 0x04 23. " [23] ,Transfer to System Memory Occurred Register 2 Buffer 55" "Not occurred,Occurred"
eventfld.long 0x04 22. " [22] ,Transfer to System Memory Occurred Register 2 Buffer 54" "Not occurred,Occurred"
eventfld.long 0x04 21. " [21] ,Transfer to System Memory Occurred Register 2 Buffer 53" "Not occurred,Occurred"
eventfld.long 0x04 20. " [20] ,Transfer to System Memory Occurred Register 2 Buffer 52" "Not occurred,Occurred"
textline " "
eventfld.long 0x04 19. " [19] ,Transfer to System Memory Occurred Register 2 Buffer 51" "Not occurred,Occurred"
eventfld.long 0x04 18. " [18] ,Transfer to System Memory Occurred Register 2 Buffer 50" "Not occurred,Occurred"
eventfld.long 0x04 17. " [17] ,Transfer to System Memory Occurred Register 2 Buffer 49" "Not occurred,Occurred"
eventfld.long 0x04 16. " [16] ,Transfer to System Memory Occurred Register 2 Buffer 48" "Not occurred,Occurred"
eventfld.long 0x04 15. " [15] ,Transfer to System Memory Occurred Register 2 Buffer 47" "Not occurred,Occurred"
eventfld.long 0x04 14. " [14] ,Transfer to System Memory Occurred Register 2 Buffer 46" "Not occurred,Occurred"
textline " "
eventfld.long 0x04 13. " [13] ,Transfer to System Memory Occurred Register 2 Buffer 45" "Not occurred,Occurred"
eventfld.long 0x04 12. " [12] ,Transfer to System Memory Occurred Register 2 Buffer 44" "Not occurred,Occurred"
eventfld.long 0x04 11. " [11] ,Transfer to System Memory Occurred Register 2 Buffer 43" "Not occurred,Occurred"
eventfld.long 0x04 10. " [10] ,Transfer to System Memory Occurred Register 2 Buffer 42" "Not occurred,Occurred"
eventfld.long 0x04 9. " [9] ,Transfer to System Memory Occurred Register 2 Buffer 41" "Not occurred,Occurred"
eventfld.long 0x04 8. " [8] ,Transfer to System Memory Occurred Register 2 Buffer 40" "Not occurred,Occurred"
textline " "
eventfld.long 0x04 7. " [7] ,Transfer to System Memory Occurred Register 2 Buffer 39" "Not occurred,Occurred"
eventfld.long 0x04 6. " [6] ,Transfer to System Memory Occurred Register 2 Buffer 38" "Not occurred,Occurred"
eventfld.long 0x04 5. " [5] ,Transfer to System Memory Occurred Register 2 Buffer 37" "Not occurred,Occurred"
eventfld.long 0x04 4. " [4] ,Transfer to System Memory Occurred Register 2 Buffer 36" "Not occurred,Occurred"
eventfld.long 0x04 3. " [3] ,Transfer to System Memory Occurred Register 2 Buffer 35" "Not occurred,Occurred"
eventfld.long 0x04 2. " [2] ,Transfer to System Memory Occurred Register 2 Buffer 34" "Not occurred,Occurred"
textline " "
eventfld.long 0x04 1. " [1] ,Transfer to System Memory Occurred Register 2 Buffer 33" "Not occurred,Occurred"
eventfld.long 0x04 0. " [0] ,Transfer to System Memory Occurred Register 2 Buffer 32" "Not occurred,Occurred"
line.long 0x8 "TSMO3,Transfer to System Memory Occurred 3"
eventfld.long 0x08 31. " TSMO3 [31] ,Transfer to System Memory Occurred Register 3 Buffer 95" "Not occurred,Occurred"
eventfld.long 0x08 30. " [30] ,Transfer to System Memory Occurred Register 3 Buffer 94" "Not occurred,Occurred"
eventfld.long 0x08 29. " [29] ,Transfer to System Memory Occurred Register 3 Buffer 93" "Not occurred,Occurred"
eventfld.long 0x08 28. " [28] ,Transfer to System Memory Occurred Register 3 Buffer 92" "Not occurred,Occurred"
eventfld.long 0x08 27. " [27] ,Transfer to System Memory Occurred Register 3 Buffer 91" "Not occurred,Occurred"
eventfld.long 0x08 26. " [26] ,Transfer to System Memory Occurred Register 3 Buffer 90" "Not occurred,Occurred"
textline " "
eventfld.long 0x08 25. " [25] ,Transfer to System Memory Occurred Register 3 Buffer 89" "Not occurred,Occurred"
eventfld.long 0x08 24. " [24] ,Transfer to System Memory Occurred Register 3 Buffer 88" "Not occurred,Occurred"
eventfld.long 0x08 23. " [23] ,Transfer to System Memory Occurred Register 3 Buffer 87" "Not occurred,Occurred"
eventfld.long 0x08 22. " [22] ,Transfer to System Memory Occurred Register 3 Buffer 86" "Not occurred,Occurred"
eventfld.long 0x08 21. " [21] ,Transfer to System Memory Occurred Register 3 Buffer 85" "Not occurred,Occurred"
eventfld.long 0x08 20. " [20] ,Transfer to System Memory Occurred Register 3 Buffer 84" "Not occurred,Occurred"
textline " "
eventfld.long 0x08 19. " [19] ,Transfer to System Memory Occurred Register 3 Buffer 83" "Not occurred,Occurred"
eventfld.long 0x08 18. " [18] ,Transfer to System Memory Occurred Register 3 Buffer 82" "Not occurred,Occurred"
eventfld.long 0x08 17. " [17] ,Transfer to System Memory Occurred Register 3 Buffer 81" "Not occurred,Occurred"
eventfld.long 0x08 16. " [16] ,Transfer to System Memory Occurred Register 3 Buffer 80" "Not occurred,Occurred"
eventfld.long 0x08 15. " [15] ,Transfer to System Memory Occurred Register 3 Buffer 79" "Not occurred,Occurred"
eventfld.long 0x08 14. " [14] ,Transfer to System Memory Occurred Register 3 Buffer 78" "Not occurred,Occurred"
textline " "
eventfld.long 0x08 13. " [13] ,Transfer to System Memory Occurred Register 3 Buffer 77" "Not occurred,Occurred"
eventfld.long 0x08 12. " [12] ,Transfer to System Memory Occurred Register 3 Buffer 76" "Not occurred,Occurred"
eventfld.long 0x08 11. " [11] ,Transfer to System Memory Occurred Register 3 Buffer 75" "Not occurred,Occurred"
eventfld.long 0x08 10. " [10] ,Transfer to System Memory Occurred Register 3 Buffer 74" "Not occurred,Occurred"
eventfld.long 0x08 9. " [9] ,Transfer to System Memory Occurred Register 3 Buffer 73" "Not occurred,Occurred"
eventfld.long 0x08 8. " [8] ,Transfer to System Memory Occurred Register 3 Buffer 72" "Not occurred,Occurred"
textline " "
eventfld.long 0x08 7. " [7] ,Transfer to System Memory Occurred Register 3 Buffer 71" "Not occurred,Occurred"
eventfld.long 0x08 6. " [6] ,Transfer to System Memory Occurred Register 3 Buffer 70" "Not occurred,Occurred"
eventfld.long 0x08 5. " [5] ,Transfer to System Memory Occurred Register 3 Buffer 69" "Not occurred,Occurred"
eventfld.long 0x08 4. " [4] ,Transfer to System Memory Occurred Register 3 Buffer 68" "Not occurred,Occurred"
eventfld.long 0x08 3. " [3] ,Transfer to System Memory Occurred Register 3 Buffer 67" "Not occurred,Occurred"
eventfld.long 0x08 2. " [2] ,Transfer to System Memory Occurred Register 3 Buffer 66" "Not occurred,Occurred"
textline " "
eventfld.long 0x08 1. " [1] ,Transfer to System Memory Occurred Register 3 Buffer 65" "Not occurred,Occurred"
eventfld.long 0x08 0. " [0] ,Transfer to System Memory Occurred Register 3 Buffer 64" "Not occurred,Occurred"
line.long 0xc "TSMO4,Transfer to System Memory Occurred 4"
eventfld.long 0x0c 31. " TSMO4 [31] ,Transfer to System Memory Occurred Register 4 Buffer 127" "Not occurred,Occurred"
eventfld.long 0x0c 30. " [30] ,Transfer to System Memory Occurred Register 4 Buffer 126" "Not occurred,Occurred"
eventfld.long 0x0c 29. " [29] ,Transfer to System Memory Occurred Register 4 Buffer 125" "Not occurred,Occurred"
eventfld.long 0x0c 28. " [28] ,Transfer to System Memory Occurred Register 4 Buffer 124" "Not occurred,Occurred"
eventfld.long 0x0c 27. " [27] ,Transfer to System Memory Occurred Register 4 Buffer 123" "Not occurred,Occurred"
eventfld.long 0x0c 26. " [26] ,Transfer to System Memory Occurred Register 4 Buffer 122" "Not occurred,Occurred"
textline " "
eventfld.long 0x0c 25. " [25] ,Transfer to System Memory Occurred Register 4 Buffer 121" "Not occurred,Occurred"
eventfld.long 0x0c 24. " [24] ,Transfer to System Memory Occurred Register 4 Buffer 120" "Not occurred,Occurred"
eventfld.long 0x0c 23. " [23] ,Transfer to System Memory Occurred Register 4 Buffer 119" "Not occurred,Occurred"
eventfld.long 0x0c 22. " [22] ,Transfer to System Memory Occurred Register 4 Buffer 118" "Not occurred,Occurred"
eventfld.long 0x0c 21. " [21] ,Transfer to System Memory Occurred Register 4 Buffer 117" "Not occurred,Occurred"
eventfld.long 0x0c 20. " [20] ,Transfer to System Memory Occurred Register 4 Buffer 116" "Not occurred,Occurred"
textline " "
eventfld.long 0x0c 19. " [19] ,Transfer to System Memory Occurred Register 4 Buffer 115" "Not occurred,Occurred"
eventfld.long 0x0c 18. " [18] ,Transfer to System Memory Occurred Register 4 Buffer 114" "Not occurred,Occurred"
eventfld.long 0x0c 17. " [17] ,Transfer to System Memory Occurred Register 4 Buffer 113" "Not occurred,Occurred"
eventfld.long 0x0c 16. " [16] ,Transfer to System Memory Occurred Register 4 Buffer 112" "Not occurred,Occurred"
eventfld.long 0x0c 15. " [15] ,Transfer to System Memory Occurred Register 4 Buffer 111" "Not occurred,Occurred"
eventfld.long 0x0c 14. " [14] ,Transfer to System Memory Occurred Register 4 Buffer 110" "Not occurred,Occurred"
textline " "
eventfld.long 0x0c 13. " [13] ,Transfer to System Memory Occurred Register 4 Buffer 109" "Not occurred,Occurred"
eventfld.long 0x0c 12. " [12] ,Transfer to System Memory Occurred Register 4 Buffer 108" "Not occurred,Occurred"
eventfld.long 0x0c 11. " [11] ,Transfer to System Memory Occurred Register 4 Buffer 107" "Not occurred,Occurred"
eventfld.long 0x0c 10. " [10] ,Transfer to System Memory Occurred Register 4 Buffer 106" "Not occurred,Occurred"
eventfld.long 0x0c 9. " [9] ,Transfer to System Memory Occurred Register 4 Buffer 105" "Not occurred,Occurred"
eventfld.long 0x0c 8. " [8] ,Transfer to System Memory Occurred Register 4 Buffer 104" "Not occurred,Occurred"
textline " "
eventfld.long 0x0c 7. " [7] ,Transfer to System Memory Occurred Register 4 Buffer 103" "Not occurred,Occurred"
eventfld.long 0x0c 6. " [6] ,Transfer to System Memory Occurred Register 4 Buffer 102" "Not occurred,Occurred"
eventfld.long 0x0c 5. " [5] ,Transfer to System Memory Occurred Register 4 Buffer 101" "Not occurred,Occurred"
eventfld.long 0x0c 4. " [4] ,Transfer to System Memory Occurred Register 4 Buffer 100" "Not occurred,Occurred"
eventfld.long 0x0c 3. " [3] ,Transfer to System Memory Occurred Register 4 Buffer 99" "Not occurred,Occurred"
eventfld.long 0x0c 2. " [2] ,Transfer to System Memory Occurred Register 4 Buffer 98" "Not occurred,Occurred"
textline " "
eventfld.long 0x0c 1. " [1] ,Transfer to System Memory Occurred Register 4 Buffer 97" "Not occurred,Occurred"
eventfld.long 0x0c 0. " [0] ,Transfer to System Memory Occurred Register 4 Buffer 96" "Not occurred,Occurred"
group.long 0x50++0xf
line.long 0x0 "TCCO1,Transfer to Communication Controller Occurred 1"
eventfld.long 0x00 31. " TCCO1 [31] ,Transfer to Communication Controller Occurred Register 1 Buffer 31" "Not occurred,Occurred"
eventfld.long 0x00 30. " [30] ,Transfer to Communication Controller Occurred Register 1 Buffer 30" "Not occurred,Occurred"
eventfld.long 0x00 29. " [29] ,Transfer to Communication Controller Occurred Register 1 Buffer 29" "Not occurred,Occurred"
eventfld.long 0x00 28. " [28] ,Transfer to Communication Controller Occurred Register 1 Buffer 28" "Not occurred,Occurred"
eventfld.long 0x00 27. " [27] ,Transfer to Communication Controller Occurred Register 1 Buffer 27" "Not occurred,Occurred"
eventfld.long 0x00 26. " [26] ,Transfer to Communication Controller Occurred Register 1 Buffer 26" "Not occurred,Occurred"
textline " "
eventfld.long 0x00 25. " [25] ,Transfer to Communication Controller Occurred Register 1 Buffer 25" "Not occurred,Occurred"
eventfld.long 0x00 24. " [24] ,Transfer to Communication Controller Occurred Register 1 Buffer 24" "Not occurred,Occurred"
eventfld.long 0x00 23. " [23] ,Transfer to Communication Controller Occurred Register 1 Buffer 23" "Not occurred,Occurred"
eventfld.long 0x00 22. " [22] ,Transfer to Communication Controller Occurred Register 1 Buffer 22" "Not occurred,Occurred"
eventfld.long 0x00 21. " [21] ,Transfer to Communication Controller Occurred Register 1 Buffer 21" "Not occurred,Occurred"
eventfld.long 0x00 20. " [20] ,Transfer to Communication Controller Occurred Register 1 Buffer 20" "Not occurred,Occurred"
textline " "
eventfld.long 0x00 19. " [19] ,Transfer to Communication Controller Occurred Register 1 Buffer 19" "Not occurred,Occurred"
eventfld.long 0x00 18. " [18] ,Transfer to Communication Controller Occurred Register 1 Buffer 18" "Not occurred,Occurred"
eventfld.long 0x00 17. " [17] ,Transfer to Communication Controller Occurred Register 1 Buffer 17" "Not occurred,Occurred"
eventfld.long 0x00 16. " [16] ,Transfer to Communication Controller Occurred Register 1 Buffer 16" "Not occurred,Occurred"
eventfld.long 0x00 15. " [15] ,Transfer to Communication Controller Occurred Register 1 Buffer 15" "Not occurred,Occurred"
eventfld.long 0x00 14. " [14] ,Transfer to Communication Controller Occurred Register 1 Buffer 14" "Not occurred,Occurred"
textline " "
eventfld.long 0x00 13. " [13] ,Transfer to Communication Controller Occurred Register 1 Buffer 13" "Not occurred,Occurred"
eventfld.long 0x00 12. " [12] ,Transfer to Communication Controller Occurred Register 1 Buffer 12" "Not occurred,Occurred"
eventfld.long 0x00 11. " [11] ,Transfer to Communication Controller Occurred Register 1 Buffer 11" "Not occurred,Occurred"
eventfld.long 0x00 10. " [10] ,Transfer to Communication Controller Occurred Register 1 Buffer 10" "Not occurred,Occurred"
eventfld.long 0x00 9. " [9] ,Transfer to Communication Controller Occurred Register 1 Buffer 9" "Not occurred,Occurred"
eventfld.long 0x00 8. " [8] ,Transfer to Communication Controller Occurred Register 1 Buffer 8" "Not occurred,Occurred"
textline " "
eventfld.long 0x00 7. " [7] ,Transfer to Communication Controller Occurred Register 1 Buffer 7" "Not occurred,Occurred"
eventfld.long 0x00 6. " [6] ,Transfer to Communication Controller Occurred Register 1 Buffer 6" "Not occurred,Occurred"
eventfld.long 0x00 5. " [5] ,Transfer to Communication Controller Occurred Register 1 Buffer 5" "Not occurred,Occurred"
eventfld.long 0x00 4. " [4] ,Transfer to Communication Controller Occurred Register 1 Buffer 4" "Not occurred,Occurred"
eventfld.long 0x00 3. " [3] ,Transfer to Communication Controller Occurred Register 1 Buffer 3" "Not occurred,Occurred"
eventfld.long 0x00 2. " [2] ,Transfer to Communication Controller Occurred Register 1 Buffer 2" "Not occurred,Occurred"
textline " "
eventfld.long 0x00 1. " [1] ,Transfer to Communication Controller Occurred Register 1 Buffer 1" "Not occurred,Occurred"
eventfld.long 0x00 0. " [0] ,Transfer to Communication Controller Occurred Register 1 Buffer 0" "Not occurred,Occurred"
line.long 0x4 "TCCO2,Transfer to Communication Controller Occurred 2"
eventfld.long 0x04 31. " TCCO2 [31] ,Transfer to Communication Controller Occurred Register 2 Buffer 63" "Not occurred,Occurred"
eventfld.long 0x04 30. " [30] ,Transfer to Communication Controller Occurred Register 2 Buffer 62" "Not occurred,Occurred"
eventfld.long 0x04 29. " [29] ,Transfer to Communication Controller Occurred Register 2 Buffer 61" "Not occurred,Occurred"
eventfld.long 0x04 28. " [28] ,Transfer to Communication Controller Occurred Register 2 Buffer 60" "Not occurred,Occurred"
eventfld.long 0x04 27. " [27] ,Transfer to Communication Controller Occurred Register 2 Buffer 59" "Not occurred,Occurred"
eventfld.long 0x04 26. " [26] ,Transfer to Communication Controller Occurred Register 2 Buffer 58" "Not occurred,Occurred"
textline " "
eventfld.long 0x04 25. " [25] ,Transfer to Communication Controller Occurred Register 2 Buffer 57" "Not occurred,Occurred"
eventfld.long 0x04 24. " [24] ,Transfer to Communication Controller Occurred Register 2 Buffer 56" "Not occurred,Occurred"
eventfld.long 0x04 23. " [23] ,Transfer to Communication Controller Occurred Register 2 Buffer 55" "Not occurred,Occurred"
eventfld.long 0x04 22. " [22] ,Transfer to Communication Controller Occurred Register 2 Buffer 54" "Not occurred,Occurred"
eventfld.long 0x04 21. " [21] ,Transfer to Communication Controller Occurred Register 2 Buffer 53" "Not occurred,Occurred"
eventfld.long 0x04 20. " [20] ,Transfer to Communication Controller Occurred Register 2 Buffer 52" "Not occurred,Occurred"
textline " "
eventfld.long 0x04 19. " [19] ,Transfer to Communication Controller Occurred Register 2 Buffer 51" "Not occurred,Occurred"
eventfld.long 0x04 18. " [18] ,Transfer to Communication Controller Occurred Register 2 Buffer 50" "Not occurred,Occurred"
eventfld.long 0x04 17. " [17] ,Transfer to Communication Controller Occurred Register 2 Buffer 49" "Not occurred,Occurred"
eventfld.long 0x04 16. " [16] ,Transfer to Communication Controller Occurred Register 2 Buffer 48" "Not occurred,Occurred"
eventfld.long 0x04 15. " [15] ,Transfer to Communication Controller Occurred Register 2 Buffer 47" "Not occurred,Occurred"
eventfld.long 0x04 14. " [14] ,Transfer to Communication Controller Occurred Register 2 Buffer 46" "Not occurred,Occurred"
textline " "
eventfld.long 0x04 13. " [13] ,Transfer to Communication Controller Occurred Register 2 Buffer 45" "Not occurred,Occurred"
eventfld.long 0x04 12. " [12] ,Transfer to Communication Controller Occurred Register 2 Buffer 44" "Not occurred,Occurred"
eventfld.long 0x04 11. " [11] ,Transfer to Communication Controller Occurred Register 2 Buffer 43" "Not occurred,Occurred"
eventfld.long 0x04 10. " [10] ,Transfer to Communication Controller Occurred Register 2 Buffer 42" "Not occurred,Occurred"
eventfld.long 0x04 9. " [9] ,Transfer to Communication Controller Occurred Register 2 Buffer 41" "Not occurred,Occurred"
eventfld.long 0x04 8. " [8] ,Transfer to Communication Controller Occurred Register 2 Buffer 40" "Not occurred,Occurred"
textline " "
eventfld.long 0x04 7. " [7] ,Transfer to Communication Controller Occurred Register 2 Buffer 39" "Not occurred,Occurred"
eventfld.long 0x04 6. " [6] ,Transfer to Communication Controller Occurred Register 2 Buffer 38" "Not occurred,Occurred"
eventfld.long 0x04 5. " [5] ,Transfer to Communication Controller Occurred Register 2 Buffer 37" "Not occurred,Occurred"
eventfld.long 0x04 4. " [4] ,Transfer to Communication Controller Occurred Register 2 Buffer 36" "Not occurred,Occurred"
eventfld.long 0x04 3. " [3] ,Transfer to Communication Controller Occurred Register 2 Buffer 35" "Not occurred,Occurred"
eventfld.long 0x04 2. " [2] ,Transfer to Communication Controller Occurred Register 2 Buffer 34" "Not occurred,Occurred"
textline " "
eventfld.long 0x04 1. " [1] ,Transfer to Communication Controller Occurred Register 2 Buffer 33" "Not occurred,Occurred"
eventfld.long 0x04 0. " [0] ,Transfer to Communication Controller Occurred Register 2 Buffer 32" "Not occurred,Occurred"
line.long 0x8 "TCCO3,Transfer to Communication Controller Occurred 3"
eventfld.long 0x08 31. " TCCO3 [31] ,Transfer to Communication Controller Occurred Register 3 Buffer 95" "Not occurred,Occurred"
eventfld.long 0x08 30. " [30] ,Transfer to Communication Controller Occurred Register 3 Buffer 94" "Not occurred,Occurred"
eventfld.long 0x08 29. " [29] ,Transfer to Communication Controller Occurred Register 3 Buffer 93" "Not occurred,Occurred"
eventfld.long 0x08 28. " [28] ,Transfer to Communication Controller Occurred Register 3 Buffer 92" "Not occurred,Occurred"
eventfld.long 0x08 27. " [27] ,Transfer to Communication Controller Occurred Register 3 Buffer 91" "Not occurred,Occurred"
eventfld.long 0x08 26. " [26] ,Transfer to Communication Controller Occurred Register 3 Buffer 90" "Not occurred,Occurred"
textline " "
eventfld.long 0x08 25. " [25] ,Transfer to Communication Controller Occurred Register 3 Buffer 89" "Not occurred,Occurred"
eventfld.long 0x08 24. " [24] ,Transfer to Communication Controller Occurred Register 3 Buffer 88" "Not occurred,Occurred"
eventfld.long 0x08 23. " [23] ,Transfer to Communication Controller Occurred Register 3 Buffer 87" "Not occurred,Occurred"
eventfld.long 0x08 22. " [22] ,Transfer to Communication Controller Occurred Register 3 Buffer 86" "Not occurred,Occurred"
eventfld.long 0x08 21. " [21] ,Transfer to Communication Controller Occurred Register 3 Buffer 85" "Not occurred,Occurred"
eventfld.long 0x08 20. " [20] ,Transfer to Communication Controller Occurred Register 3 Buffer 84" "Not occurred,Occurred"
textline " "
eventfld.long 0x08 19. " [19] ,Transfer to Communication Controller Occurred Register 3 Buffer 83" "Not occurred,Occurred"
eventfld.long 0x08 18. " [18] ,Transfer to Communication Controller Occurred Register 3 Buffer 82" "Not occurred,Occurred"
eventfld.long 0x08 17. " [17] ,Transfer to Communication Controller Occurred Register 3 Buffer 81" "Not occurred,Occurred"
eventfld.long 0x08 16. " [16] ,Transfer to Communication Controller Occurred Register 3 Buffer 80" "Not occurred,Occurred"
eventfld.long 0x08 15. " [15] ,Transfer to Communication Controller Occurred Register 3 Buffer 79" "Not occurred,Occurred"
eventfld.long 0x08 14. " [14] ,Transfer to Communication Controller Occurred Register 3 Buffer 78" "Not occurred,Occurred"
textline " "
eventfld.long 0x08 13. " [13] ,Transfer to Communication Controller Occurred Register 3 Buffer 77" "Not occurred,Occurred"
eventfld.long 0x08 12. " [12] ,Transfer to Communication Controller Occurred Register 3 Buffer 76" "Not occurred,Occurred"
eventfld.long 0x08 11. " [11] ,Transfer to Communication Controller Occurred Register 3 Buffer 75" "Not occurred,Occurred"
eventfld.long 0x08 10. " [10] ,Transfer to Communication Controller Occurred Register 3 Buffer 74" "Not occurred,Occurred"
eventfld.long 0x08 9. " [9] ,Transfer to Communication Controller Occurred Register 3 Buffer 73" "Not occurred,Occurred"
eventfld.long 0x08 8. " [8] ,Transfer to Communication Controller Occurred Register 3 Buffer 72" "Not occurred,Occurred"
textline " "
eventfld.long 0x08 7. " [7] ,Transfer to Communication Controller Occurred Register 3 Buffer 71" "Not occurred,Occurred"
eventfld.long 0x08 6. " [6] ,Transfer to Communication Controller Occurred Register 3 Buffer 70" "Not occurred,Occurred"
eventfld.long 0x08 5. " [5] ,Transfer to Communication Controller Occurred Register 3 Buffer 69" "Not occurred,Occurred"
eventfld.long 0x08 4. " [4] ,Transfer to Communication Controller Occurred Register 3 Buffer 68" "Not occurred,Occurred"
eventfld.long 0x08 3. " [3] ,Transfer to Communication Controller Occurred Register 3 Buffer 67" "Not occurred,Occurred"
eventfld.long 0x08 2. " [2] ,Transfer to Communication Controller Occurred Register 3 Buffer 66" "Not occurred,Occurred"
textline " "
eventfld.long 0x08 1. " [1] ,Transfer to Communication Controller Occurred Register 3 Buffer 65" "Not occurred,Occurred"
eventfld.long 0x08 0. " [0] ,Transfer to Communication Controller Occurred Register 3 Buffer 64" "Not occurred,Occurred"
line.long 0xc "TCCO4,Transfer to Communication Controller Occurred 4"
eventfld.long 0x0c 31. " TCCO4 [31] ,Transfer to Communication Controller Occurred Register 4 Buffer 127" "Not occurred,Occurred"
eventfld.long 0x0c 30. " [30] ,Transfer to Communication Controller Occurred Register 4 Buffer 126" "Not occurred,Occurred"
eventfld.long 0x0c 29. " [29] ,Transfer to Communication Controller Occurred Register 4 Buffer 125" "Not occurred,Occurred"
eventfld.long 0x0c 28. " [28] ,Transfer to Communication Controller Occurred Register 4 Buffer 124" "Not occurred,Occurred"
eventfld.long 0x0c 27. " [27] ,Transfer to Communication Controller Occurred Register 4 Buffer 123" "Not occurred,Occurred"
eventfld.long 0x0c 26. " [26] ,Transfer to Communication Controller Occurred Register 4 Buffer 122" "Not occurred,Occurred"
textline " "
eventfld.long 0x0c 25. " [25] ,Transfer to Communication Controller Occurred Register 4 Buffer 121" "Not occurred,Occurred"
eventfld.long 0x0c 24. " [24] ,Transfer to Communication Controller Occurred Register 4 Buffer 120" "Not occurred,Occurred"
eventfld.long 0x0c 23. " [23] ,Transfer to Communication Controller Occurred Register 4 Buffer 119" "Not occurred,Occurred"
eventfld.long 0x0c 22. " [22] ,Transfer to Communication Controller Occurred Register 4 Buffer 118" "Not occurred,Occurred"
eventfld.long 0x0c 21. " [21] ,Transfer to Communication Controller Occurred Register 4 Buffer 117" "Not occurred,Occurred"
eventfld.long 0x0c 20. " [20] ,Transfer to Communication Controller Occurred Register 4 Buffer 116" "Not occurred,Occurred"
textline " "
eventfld.long 0x0c 19. " [19] ,Transfer to Communication Controller Occurred Register 4 Buffer 115" "Not occurred,Occurred"
eventfld.long 0x0c 18. " [18] ,Transfer to Communication Controller Occurred Register 4 Buffer 114" "Not occurred,Occurred"
eventfld.long 0x0c 17. " [17] ,Transfer to Communication Controller Occurred Register 4 Buffer 113" "Not occurred,Occurred"
eventfld.long 0x0c 16. " [16] ,Transfer to Communication Controller Occurred Register 4 Buffer 112" "Not occurred,Occurred"
eventfld.long 0x0c 15. " [15] ,Transfer to Communication Controller Occurred Register 4 Buffer 111" "Not occurred,Occurred"
eventfld.long 0x0c 14. " [14] ,Transfer to Communication Controller Occurred Register 4 Buffer 110" "Not occurred,Occurred"
textline " "
eventfld.long 0x0c 13. " [13] ,Transfer to Communication Controller Occurred Register 4 Buffer 109" "Not occurred,Occurred"
eventfld.long 0x0c 12. " [12] ,Transfer to Communication Controller Occurred Register 4 Buffer 108" "Not occurred,Occurred"
eventfld.long 0x0c 11. " [11] ,Transfer to Communication Controller Occurred Register 4 Buffer 107" "Not occurred,Occurred"
eventfld.long 0x0c 10. " [10] ,Transfer to Communication Controller Occurred Register 4 Buffer 106" "Not occurred,Occurred"
eventfld.long 0x0c 9. " [9] ,Transfer to Communication Controller Occurred Register 4 Buffer 105" "Not occurred,Occurred"
eventfld.long 0x0c 8. " [8] ,Transfer to Communication Controller Occurred Register 4 Buffer 104" "Not occurred,Occurred"
textline " "
eventfld.long 0x0c 7. " [7] ,Transfer to Communication Controller Occurred Register 4 Buffer 103" "Not occurred,Occurred"
eventfld.long 0x0c 6. " [6] ,Transfer to Communication Controller Occurred Register 4 Buffer 102" "Not occurred,Occurred"
eventfld.long 0x0c 5. " [5] ,Transfer to Communication Controller Occurred Register 4 Buffer 101" "Not occurred,Occurred"
eventfld.long 0x0c 4. " [4] ,Transfer to Communication Controller Occurred Register 4 Buffer 100" "Not occurred,Occurred"
eventfld.long 0x0c 3. " [3] ,Transfer to Communication Controller Occurred Register 4 Buffer 99" "Not occurred,Occurred"
eventfld.long 0x0c 2. " [2] ,Transfer to Communication Controller Occurred Register 4 Buffer 98" "Not occurred,Occurred"
textline " "
eventfld.long 0x0c 1. " [1] ,Transfer to Communication Controller Occurred Register 4 Buffer 97" "Not occurred,Occurred"
eventfld.long 0x0c 0. " [0] ,Transfer to Communication Controller Occurred Register 4 Buffer 96" "Not occurred,Occurred"
width 11.
rgroup.long 0x60++0x3
line.long 0x0 "TOOFF,Transfer Occurred Offset"
bitfld.long 0x00 8. " TDIR ,Transfer Direction" "System Memory,Communication Controller"
hexmask.long.byte 0x00 0.--7. 1. " OFF ,Offset Vector"
hgroup.long 0x6C++0x3
hide.long 0x0 "TSBESTAT,TCR Single Bit Error Status"
in
hgroup.long 0x70++0x3
hide.long 0x0 "PEADR,Parity Error Address"
in
group.long 0x74++0x3
line.long 0x0 "TEIR,Transfer Error Interrupt"
eventfld.long 0x00 17. " MPV ,Memory Protection Violation" "Not occurred,Occurred"
eventfld.long 0x00 16. " PE ,Parity/ECC Error" "Not occurred,Occurred"
textline " "
bitfld.long 0x00 8.--10. " RSTAT ,Read Status of Transfer Unit State Machine" "Success,Addressing error,Protection error,Timeout error,Data error,Unsupported addressing mode error,,Exclusive read failure"
textline " "
bitfld.long 0x00 4.--6. " WSTAT ,Write Status of Transfer Unit State Machine" "Success,Addressing error,Protection error,Timeout error,,Unsupported addressing mode error,,Exclusive read failure"
textline " "
eventfld.long 0x00 1. " TNR ,Transfer Not Ready" "Ready,Not ready"
eventfld.long 0x00 0. " FAC ,Forbidden Access" "No forbidden,Forbidden"
group.long 0x78++0x7
line.long 0x0 "TEIRES,Transfer Error InterRupt Enable Set"
bitfld.long 0x00 8.--10. " RSTATE ,Read Error Interrupt Generation" "Disabled,,,,,,,Enabled"
textline " "
bitfld.long 0x00 4.--6. " WSTATE ,Write Error Interrupt Generation" "Disabled,,,,,,,Enabled"
textline " "
setclrfld.long 0x00 1. 0x00 1. 0x04 1. " TNRE_set/clr ,Transfer Not Ready Enable" "Disabled,Enabled"
setclrfld.long 0x00 0. 0x00 0. 0x04 0. " FACE_set/clr ,Forbidden Access Enable" "Disabled,Enabled"
line.long 0x4 "TEIRER,Transfer Error InterRupt Enable Reset"
bitfld.long 0x04 8.--10. " RSTATE ,Read Error Interrupt Generation" "Disabled,Not guaranted,Not guaranted,Not guaranted,Not guaranted,Not guaranted,Not guaranted,Enabled"
textline " "
bitfld.long 0x04 4.--6. " WSTATE ,Write Error Interrupt Generation" "Disabled,Not guaranted,Not guaranted,Not guaranted,Not guaranted,Not guaranted,Not guaranted,Enabled"
width 11.
group.long 0x80++0x3
line.long 0x0 "TTSMS/R1,Trigger Transfer to System Memory Set/Reset 1"
setclrfld.long 0x00 31. 0x00 31. 0x04 31. " TTSMS/R1_set/clr [31] ,Trigger Transfer to System Memory Set/Reset 1 Buffer 31" "Not requested,Requested"
setclrfld.long 0x00 30. 0x00 30. 0x04 30. " [30] ,Trigger Transfer to System Memory Set/Reset 1 Buffer 30" "Not requested,Requested"
setclrfld.long 0x00 29. 0x00 29. 0x04 29. " [29] ,Trigger Transfer to System Memory Set/Reset 1 Buffer 29" "Not requested,Requested"
setclrfld.long 0x00 28. 0x00 28. 0x04 28. " [28] ,Trigger Transfer to System Memory Set/Reset 1 Buffer 28" "Not requested,Requested"
textline " "
setclrfld.long 0x00 27. 0x00 27. 0x04 27. " [27] ,Trigger Transfer to System Memory Set/Reset 1 Buffer 27" "Not requested,Requested"
setclrfld.long 0x00 26. 0x00 26. 0x04 26. " [26] ,Trigger Transfer to System Memory Set/Reset 1 Buffer 26" "Not requested,Requested"
setclrfld.long 0x00 25. 0x00 25. 0x04 25. " [25] ,Trigger Transfer to System Memory Set/Reset 1 Buffer 25" "Not requested,Requested"
setclrfld.long 0x00 24. 0x00 24. 0x04 24. " [24] ,Trigger Transfer to System Memory Set/Reset 1 Buffer 24" "Not requested,Requested"
textline " "
setclrfld.long 0x00 23. 0x00 23. 0x04 23. " [23] ,Trigger Transfer to System Memory Set/Reset 1 Buffer 23" "Not requested,Requested"
setclrfld.long 0x00 22. 0x00 22. 0x04 22. " [22] ,Trigger Transfer to System Memory Set/Reset 1 Buffer 22" "Not requested,Requested"
setclrfld.long 0x00 21. 0x00 21. 0x04 21. " [21] ,Trigger Transfer to System Memory Set/Reset 1 Buffer 21" "Not requested,Requested"
setclrfld.long 0x00 20. 0x00 20. 0x04 20. " [20] ,Trigger Transfer to System Memory Set/Reset 1 Buffer 20" "Not requested,Requested"
textline " "
setclrfld.long 0x00 19. 0x00 19. 0x04 19. " [19] ,Trigger Transfer to System Memory Set/Reset 1 Buffer 19" "Not requested,Requested"
setclrfld.long 0x00 18. 0x00 18. 0x04 18. " [18] ,Trigger Transfer to System Memory Set/Reset 1 Buffer 18" "Not requested,Requested"
setclrfld.long 0x00 17. 0x00 17. 0x04 17. " [17] ,Trigger Transfer to System Memory Set/Reset 1 Buffer 17" "Not requested,Requested"
setclrfld.long 0x00 16. 0x00 16. 0x04 16. " [16] ,Trigger Transfer to System Memory Set/Reset 1 Buffer 16" "Not requested,Requested"
textline " "
setclrfld.long 0x00 15. 0x00 15. 0x04 15. " [15] ,Trigger Transfer to System Memory Set/Reset 1 Buffer 15" "Not requested,Requested"
setclrfld.long 0x00 14. 0x00 14. 0x04 14. " [14] ,Trigger Transfer to System Memory Set/Reset 1 Buffer 14" "Not requested,Requested"
setclrfld.long 0x00 13. 0x00 13. 0x04 13. " [13] ,Trigger Transfer to System Memory Set/Reset 1 Buffer 13" "Not requested,Requested"
setclrfld.long 0x00 12. 0x00 12. 0x04 12. " [12] ,Trigger Transfer to System Memory Set/Reset 1 Buffer 12" "Not requested,Requested"
textline " "
setclrfld.long 0x00 11. 0x00 11. 0x04 11. " [11] ,Trigger Transfer to System Memory Set/Reset 1 Buffer 11" "Not requested,Requested"
setclrfld.long 0x00 10. 0x00 10. 0x04 10. " [10] ,Trigger Transfer to System Memory Set/Reset 1 Buffer 10" "Not requested,Requested"
setclrfld.long 0x00 9. 0x00 9. 0x04 9. " [9] ,Trigger Transfer to System Memory Set/Reset 1 Buffer 9" "Not requested,Requested"
setclrfld.long 0x00 8. 0x00 8. 0x04 8. " [8] ,Trigger Transfer to System Memory Set/Reset 1 Buffer 8" "Not requested,Requested"
textline " "
setclrfld.long 0x00 7. 0x00 7. 0x04 7. " [7] ,Trigger Transfer to System Memory Set/Reset 1 Buffer 7" "Not requested,Requested"
setclrfld.long 0x00 6. 0x00 6. 0x04 6. " [6] ,Trigger Transfer to System Memory Set/Reset 1 Buffer 6" "Not requested,Requested"
setclrfld.long 0x00 5. 0x00 5. 0x04 5. " [5] ,Trigger Transfer to System Memory Set/Reset 1 Buffer 5" "Not requested,Requested"
setclrfld.long 0x00 4. 0x00 4. 0x04 4. " [4] ,Trigger Transfer to System Memory Set/Reset 1 Buffer 4" "Not requested,Requested"
textline " "
setclrfld.long 0x00 3. 0x00 3. 0x04 3. " [3] ,Trigger Transfer to System Memory Set/Reset 1 Buffer 3" "Not requested,Requested"
setclrfld.long 0x00 2. 0x00 2. 0x04 2. " [2] ,Trigger Transfer to System Memory Set/Reset 1 Buffer 2" "Not requested,Requested"
setclrfld.long 0x00 1. 0x00 1. 0x04 1. " [1] ,Trigger Transfer to System Memory Set/Reset 1 Buffer 1" "Not requested,Requested"
setclrfld.long 0x00 0. 0x00 0. 0x04 0. " [0] ,Trigger Transfer to System Memory Set/Reset 1 Buffer 0" "Not requested,Requested"
group.long 0x88++0x3
line.long 0x0 "TTSMS/R2,Trigger Transfer to System Memory Set/Reset 2"
setclrfld.long 0x00 31. 0x00 31. 0x04 31. " TTSMS/R2_set/clr [31] ,Trigger Transfer to System Memory Set/Reset 2 Buffer 63" "Not requested,Requested"
setclrfld.long 0x00 30. 0x00 30. 0x04 30. " [30] ,Trigger Transfer to System Memory Set/Reset 2 Buffer 62" "Not requested,Requested"
setclrfld.long 0x00 29. 0x00 29. 0x04 29. " [29] ,Trigger Transfer to System Memory Set/Reset 2 Buffer 61" "Not requested,Requested"
setclrfld.long 0x00 28. 0x00 28. 0x04 28. " [28] ,Trigger Transfer to System Memory Set/Reset 2 Buffer 60" "Not requested,Requested"
textline " "
setclrfld.long 0x00 27. 0x00 27. 0x04 27. " [27] ,Trigger Transfer to System Memory Set/Reset 2 Buffer 59" "Not requested,Requested"
setclrfld.long 0x00 26. 0x00 26. 0x04 26. " [26] ,Trigger Transfer to System Memory Set/Reset 2 Buffer 58" "Not requested,Requested"
setclrfld.long 0x00 25. 0x00 25. 0x04 25. " [25] ,Trigger Transfer to System Memory Set/Reset 2 Buffer 57" "Not requested,Requested"
setclrfld.long 0x00 24. 0x00 24. 0x04 24. " [24] ,Trigger Transfer to System Memory Set/Reset 2 Buffer 56" "Not requested,Requested"
textline " "
setclrfld.long 0x00 23. 0x00 23. 0x04 23. " [23] ,Trigger Transfer to System Memory Set/Reset 2 Buffer 55" "Not requested,Requested"
setclrfld.long 0x00 22. 0x00 22. 0x04 22. " [22] ,Trigger Transfer to System Memory Set/Reset 2 Buffer 54" "Not requested,Requested"
setclrfld.long 0x00 21. 0x00 21. 0x04 21. " [21] ,Trigger Transfer to System Memory Set/Reset 2 Buffer 53" "Not requested,Requested"
setclrfld.long 0x00 20. 0x00 20. 0x04 20. " [20] ,Trigger Transfer to System Memory Set/Reset 2 Buffer 52" "Not requested,Requested"
textline " "
setclrfld.long 0x00 19. 0x00 19. 0x04 19. " [19] ,Trigger Transfer to System Memory Set/Reset 2 Buffer 51" "Not requested,Requested"
setclrfld.long 0x00 18. 0x00 18. 0x04 18. " [18] ,Trigger Transfer to System Memory Set/Reset 2 Buffer 50" "Not requested,Requested"
setclrfld.long 0x00 17. 0x00 17. 0x04 17. " [17] ,Trigger Transfer to System Memory Set/Reset 2 Buffer 49" "Not requested,Requested"
setclrfld.long 0x00 16. 0x00 16. 0x04 16. " [16] ,Trigger Transfer to System Memory Set/Reset 2 Buffer 48" "Not requested,Requested"
textline " "
setclrfld.long 0x00 15. 0x00 15. 0x04 15. " [15] ,Trigger Transfer to System Memory Set/Reset 2 Buffer 47" "Not requested,Requested"
setclrfld.long 0x00 14. 0x00 14. 0x04 14. " [14] ,Trigger Transfer to System Memory Set/Reset 2 Buffer 46" "Not requested,Requested"
setclrfld.long 0x00 13. 0x00 13. 0x04 13. " [13] ,Trigger Transfer to System Memory Set/Reset 2 Buffer 45" "Not requested,Requested"
setclrfld.long 0x00 12. 0x00 12. 0x04 12. " [12] ,Trigger Transfer to System Memory Set/Reset 2 Buffer 44" "Not requested,Requested"
textline " "
setclrfld.long 0x00 11. 0x00 11. 0x04 11. " [11] ,Trigger Transfer to System Memory Set/Reset 2 Buffer 43" "Not requested,Requested"
setclrfld.long 0x00 10. 0x00 10. 0x04 10. " [10] ,Trigger Transfer to System Memory Set/Reset 2 Buffer 42" "Not requested,Requested"
setclrfld.long 0x00 9. 0x00 9. 0x04 9. " [9] ,Trigger Transfer to System Memory Set/Reset 2 Buffer 41" "Not requested,Requested"
setclrfld.long 0x00 8. 0x00 8. 0x04 8. " [8] ,Trigger Transfer to System Memory Set/Reset 2 Buffer 40" "Not requested,Requested"
textline " "
setclrfld.long 0x00 7. 0x00 7. 0x04 7. " [7] ,Trigger Transfer to System Memory Set/Reset 2 Buffer 39" "Not requested,Requested"
setclrfld.long 0x00 6. 0x00 6. 0x04 6. " [6] ,Trigger Transfer to System Memory Set/Reset 2 Buffer 38" "Not requested,Requested"
setclrfld.long 0x00 5. 0x00 5. 0x04 5. " [5] ,Trigger Transfer to System Memory Set/Reset 2 Buffer 37" "Not requested,Requested"
setclrfld.long 0x00 4. 0x00 4. 0x04 4. " [4] ,Trigger Transfer to System Memory Set/Reset 2 Buffer 36" "Not requested,Requested"
textline " "
setclrfld.long 0x00 3. 0x00 3. 0x04 3. " [3] ,Trigger Transfer to System Memory Set/Reset 2 Buffer 35" "Not requested,Requested"
setclrfld.long 0x00 2. 0x00 2. 0x04 2. " [2] ,Trigger Transfer to System Memory Set/Reset 2 Buffer 34" "Not requested,Requested"
setclrfld.long 0x00 1. 0x00 1. 0x04 1. " [1] ,Trigger Transfer to System Memory Set/Reset 2 Buffer 33" "Not requested,Requested"
setclrfld.long 0x00 0. 0x00 0. 0x04 0. " [0] ,Trigger Transfer to System Memory Set/Reset 2 Buffer 32" "Not requested,Requested"
group.long 0x90++0x3
line.long 0x0 "TTSMS/R3,Trigger Transfer to System Memory Set/Reset 3"
setclrfld.long 0x00 31. 0x00 31. 0x04 31. " TTSMS/R3_set/clr [31] ,Trigger Transfer to System Memory Set/Reset 3 Buffer 95" "Not requested,Requested"
setclrfld.long 0x00 30. 0x00 30. 0x04 30. " [30] ,Trigger Transfer to System Memory Set/Reset 3 Buffer 94" "Not requested,Requested"
setclrfld.long 0x00 29. 0x00 29. 0x04 29. " [29] ,Trigger Transfer to System Memory Set/Reset 3 Buffer 93" "Not requested,Requested"
setclrfld.long 0x00 28. 0x00 28. 0x04 28. " [28] ,Trigger Transfer to System Memory Set/Reset 3 Buffer 92" "Not requested,Requested"
textline " "
setclrfld.long 0x00 27. 0x00 27. 0x04 27. " [27] ,Trigger Transfer to System Memory Set/Reset 3 Buffer 91" "Not requested,Requested"
setclrfld.long 0x00 26. 0x00 26. 0x04 26. " [26] ,Trigger Transfer to System Memory Set/Reset 3 Buffer 90" "Not requested,Requested"
setclrfld.long 0x00 25. 0x00 25. 0x04 25. " [25] ,Trigger Transfer to System Memory Set/Reset 3 Buffer 89" "Not requested,Requested"
setclrfld.long 0x00 24. 0x00 24. 0x04 24. " [24] ,Trigger Transfer to System Memory Set/Reset 3 Buffer 88" "Not requested,Requested"
textline " "
setclrfld.long 0x00 23. 0x00 23. 0x04 23. " [23] ,Trigger Transfer to System Memory Set/Reset 3 Buffer 87" "Not requested,Requested"
setclrfld.long 0x00 22. 0x00 22. 0x04 22. " [22] ,Trigger Transfer to System Memory Set/Reset 3 Buffer 86" "Not requested,Requested"
setclrfld.long 0x00 21. 0x00 21. 0x04 21. " [21] ,Trigger Transfer to System Memory Set/Reset 3 Buffer 85" "Not requested,Requested"
setclrfld.long 0x00 20. 0x00 20. 0x04 20. " [20] ,Trigger Transfer to System Memory Set/Reset 3 Buffer 84" "Not requested,Requested"
textline " "
setclrfld.long 0x00 19. 0x00 19. 0x04 19. " [19] ,Trigger Transfer to System Memory Set/Reset 3 Buffer 83" "Not requested,Requested"
setclrfld.long 0x00 18. 0x00 18. 0x04 18. " [18] ,Trigger Transfer to System Memory Set/Reset 3 Buffer 82" "Not requested,Requested"
setclrfld.long 0x00 17. 0x00 17. 0x04 17. " [17] ,Trigger Transfer to System Memory Set/Reset 3 Buffer 81" "Not requested,Requested"
setclrfld.long 0x00 16. 0x00 16. 0x04 16. " [16] ,Trigger Transfer to System Memory Set/Reset 3 Buffer 80" "Not requested,Requested"
textline " "
setclrfld.long 0x00 15. 0x00 15. 0x04 15. " [15] ,Trigger Transfer to System Memory Set/Reset 3 Buffer 79" "Not requested,Requested"
setclrfld.long 0x00 14. 0x00 14. 0x04 14. " [14] ,Trigger Transfer to System Memory Set/Reset 3 Buffer 78" "Not requested,Requested"
setclrfld.long 0x00 13. 0x00 13. 0x04 13. " [13] ,Trigger Transfer to System Memory Set/Reset 3 Buffer 77" "Not requested,Requested"
setclrfld.long 0x00 12. 0x00 12. 0x04 12. " [12] ,Trigger Transfer to System Memory Set/Reset 3 Buffer 76" "Not requested,Requested"
textline " "
setclrfld.long 0x00 11. 0x00 11. 0x04 11. " [11] ,Trigger Transfer to System Memory Set/Reset 3 Buffer 75" "Not requested,Requested"
setclrfld.long 0x00 10. 0x00 10. 0x04 10. " [10] ,Trigger Transfer to System Memory Set/Reset 3 Buffer 74" "Not requested,Requested"
setclrfld.long 0x00 9. 0x00 9. 0x04 9. " [9] ,Trigger Transfer to System Memory Set/Reset 3 Buffer 73" "Not requested,Requested"
setclrfld.long 0x00 8. 0x00 8. 0x04 8. " [8] ,Trigger Transfer to System Memory Set/Reset 3 Buffer 72" "Not requested,Requested"
textline " "
setclrfld.long 0x00 7. 0x00 7. 0x04 7. " [7] ,Trigger Transfer to System Memory Set/Reset 3 Buffer 71" "Not requested,Requested"
setclrfld.long 0x00 6. 0x00 6. 0x04 6. " [6] ,Trigger Transfer to System Memory Set/Reset 3 Buffer 70" "Not requested,Requested"
setclrfld.long 0x00 5. 0x00 5. 0x04 5. " [5] ,Trigger Transfer to System Memory Set/Reset 3 Buffer 69" "Not requested,Requested"
setclrfld.long 0x00 4. 0x00 4. 0x04 4. " [4] ,Trigger Transfer to System Memory Set/Reset 3 Buffer 68" "Not requested,Requested"
textline " "
setclrfld.long 0x00 3. 0x00 3. 0x04 3. " [3] ,Trigger Transfer to System Memory Set/Reset 3 Buffer 67" "Not requested,Requested"
setclrfld.long 0x00 2. 0x00 2. 0x04 2. " [2] ,Trigger Transfer to System Memory Set/Reset 3 Buffer 66" "Not requested,Requested"
setclrfld.long 0x00 1. 0x00 1. 0x04 1. " [1] ,Trigger Transfer to System Memory Set/Reset 3 Buffer 65" "Not requested,Requested"
setclrfld.long 0x00 0. 0x00 0. 0x04 0. " [0] ,Trigger Transfer to System Memory Set/Reset 3 Buffer 64" "Not requested,Requested"
group.long 0x98++0x3
line.long 0x0 "TTSMS/R4,Trigger Transfer to System Memory Set/Reset 4"
setclrfld.long 0x00 31. 0x00 31. 0x04 31. " TTSMS/R4_set/clr [31] ,Trigger Transfer to System Memory Set/Reset 4 Buffer 127" "Not requested,Requested"
setclrfld.long 0x00 30. 0x00 30. 0x04 30. " [30] ,Trigger Transfer to System Memory Set/Reset 4 Buffer 126" "Not requested,Requested"
setclrfld.long 0x00 29. 0x00 29. 0x04 29. " [29] ,Trigger Transfer to System Memory Set/Reset 4 Buffer 125" "Not requested,Requested"
setclrfld.long 0x00 28. 0x00 28. 0x04 28. " [28] ,Trigger Transfer to System Memory Set/Reset 4 Buffer 124" "Not requested,Requested"
textline " "
setclrfld.long 0x00 27. 0x00 27. 0x04 27. " [27] ,Trigger Transfer to System Memory Set/Reset 4 Buffer 123" "Not requested,Requested"
setclrfld.long 0x00 26. 0x00 26. 0x04 26. " [26] ,Trigger Transfer to System Memory Set/Reset 4 Buffer 122" "Not requested,Requested"
setclrfld.long 0x00 25. 0x00 25. 0x04 25. " [25] ,Trigger Transfer to System Memory Set/Reset 4 Buffer 121" "Not requested,Requested"
setclrfld.long 0x00 24. 0x00 24. 0x04 24. " [24] ,Trigger Transfer to System Memory Set/Reset 4 Buffer 120" "Not requested,Requested"
textline " "
setclrfld.long 0x00 23. 0x00 23. 0x04 23. " [23] ,Trigger Transfer to System Memory Set/Reset 4 Buffer 119" "Not requested,Requested"
setclrfld.long 0x00 22. 0x00 22. 0x04 22. " [22] ,Trigger Transfer to System Memory Set/Reset 4 Buffer 118" "Not requested,Requested"
setclrfld.long 0x00 21. 0x00 21. 0x04 21. " [21] ,Trigger Transfer to System Memory Set/Reset 4 Buffer 117" "Not requested,Requested"
setclrfld.long 0x00 20. 0x00 20. 0x04 20. " [20] ,Trigger Transfer to System Memory Set/Reset 4 Buffer 116" "Not requested,Requested"
textline " "
setclrfld.long 0x00 19. 0x00 19. 0x04 19. " [19] ,Trigger Transfer to System Memory Set/Reset 4 Buffer 115" "Not requested,Requested"
setclrfld.long 0x00 18. 0x00 18. 0x04 18. " [18] ,Trigger Transfer to System Memory Set/Reset 4 Buffer 114" "Not requested,Requested"
setclrfld.long 0x00 17. 0x00 17. 0x04 17. " [17] ,Trigger Transfer to System Memory Set/Reset 4 Buffer 113" "Not requested,Requested"
setclrfld.long 0x00 16. 0x00 16. 0x04 16. " [16] ,Trigger Transfer to System Memory Set/Reset 4 Buffer 112" "Not requested,Requested"
textline " "
setclrfld.long 0x00 15. 0x00 15. 0x04 15. " [15] ,Trigger Transfer to System Memory Set/Reset 4 Buffer 111" "Not requested,Requested"
setclrfld.long 0x00 14. 0x00 14. 0x04 14. " [14] ,Trigger Transfer to System Memory Set/Reset 4 Buffer 110" "Not requested,Requested"
setclrfld.long 0x00 13. 0x00 13. 0x04 13. " [13] ,Trigger Transfer to System Memory Set/Reset 4 Buffer 109" "Not requested,Requested"
setclrfld.long 0x00 12. 0x00 12. 0x04 12. " [12] ,Trigger Transfer to System Memory Set/Reset 4 Buffer 108" "Not requested,Requested"
textline " "
setclrfld.long 0x00 11. 0x00 11. 0x04 11. " [11] ,Trigger Transfer to System Memory Set/Reset 4 Buffer 107" "Not requested,Requested"
setclrfld.long 0x00 10. 0x00 10. 0x04 10. " [10] ,Trigger Transfer to System Memory Set/Reset 4 Buffer 106" "Not requested,Requested"
setclrfld.long 0x00 9. 0x00 9. 0x04 9. " [9] ,Trigger Transfer to System Memory Set/Reset 4 Buffer 105" "Not requested,Requested"
setclrfld.long 0x00 8. 0x00 8. 0x04 8. " [8] ,Trigger Transfer to System Memory Set/Reset 4 Buffer 104" "Not requested,Requested"
textline " "
setclrfld.long 0x00 7. 0x00 7. 0x04 7. " [7] ,Trigger Transfer to System Memory Set/Reset 4 Buffer 103" "Not requested,Requested"
setclrfld.long 0x00 6. 0x00 6. 0x04 6. " [6] ,Trigger Transfer to System Memory Set/Reset 4 Buffer 102" "Not requested,Requested"
setclrfld.long 0x00 5. 0x00 5. 0x04 5. " [5] ,Trigger Transfer to System Memory Set/Reset 4 Buffer 101" "Not requested,Requested"
setclrfld.long 0x00 4. 0x00 4. 0x04 4. " [4] ,Trigger Transfer to System Memory Set/Reset 4 Buffer 100" "Not requested,Requested"
textline " "
setclrfld.long 0x00 3. 0x00 3. 0x04 3. " [3] ,Trigger Transfer to System Memory Set/Reset 4 Buffer 99" "Not requested,Requested"
setclrfld.long 0x00 2. 0x00 2. 0x04 2. " [2] ,Trigger Transfer to System Memory Set/Reset 4 Buffer 98" "Not requested,Requested"
setclrfld.long 0x00 1. 0x00 1. 0x04 1. " [1] ,Trigger Transfer to System Memory Set/Reset 4 Buffer 97" "Not requested,Requested"
setclrfld.long 0x00 0. 0x00 0. 0x04 0. " [0] ,Trigger Transfer to System Memory Set/Reset 4 Buffer 96" "Not requested,Requested"
group.long 0xA0++0x3
line.long 0x0 "TTCCS/R1,Trigger Transfer to Communication Controller Set/Reset 1"
setclrfld.long 0x00 31. 0x00 31. 0x04 31. " TTCCS/R1_set/clr [31] ,Trigger Transfer to Communication Controller Set/Reset 1 Buffer 31" "Not requested,Requested"
setclrfld.long 0x00 30. 0x00 30. 0x04 30. " [30] ,Trigger Transfer to Communication Controller Set/Reset 1 Buffer 30" "Not requested,Requested"
setclrfld.long 0x00 29. 0x00 29. 0x04 29. " [29] ,Trigger Transfer to Communication Controller Set/Reset 1 Buffer 29" "Not requested,Requested"
setclrfld.long 0x00 28. 0x00 28. 0x04 28. " [28] ,Trigger Transfer to Communication Controller Set/Reset 1 Buffer 28" "Not requested,Requested"
textline " "
setclrfld.long 0x00 27. 0x00 27. 0x04 27. " [27] ,Trigger Transfer to Communication Controller Set/Reset 1 Buffer 27" "Not requested,Requested"
setclrfld.long 0x00 26. 0x00 26. 0x04 26. " [26] ,Trigger Transfer to Communication Controller Set/Reset 1 Buffer 26" "Not requested,Requested"
setclrfld.long 0x00 25. 0x00 25. 0x04 25. " [25] ,Trigger Transfer to Communication Controller Set/Reset 1 Buffer 25" "Not requested,Requested"
setclrfld.long 0x00 24. 0x00 24. 0x04 24. " [24] ,Trigger Transfer to Communication Controller Set/Reset 1 Buffer 24" "Not requested,Requested"
textline " "
setclrfld.long 0x00 23. 0x00 23. 0x04 23. " [23] ,Trigger Transfer to Communication Controller Set/Reset 1 Buffer 23" "Not requested,Requested"
setclrfld.long 0x00 22. 0x00 22. 0x04 22. " [22] ,Trigger Transfer to Communication Controller Set/Reset 1 Buffer 22" "Not requested,Requested"
setclrfld.long 0x00 21. 0x00 21. 0x04 21. " [21] ,Trigger Transfer to Communication Controller Set/Reset 1 Buffer 21" "Not requested,Requested"
setclrfld.long 0x00 20. 0x00 20. 0x04 20. " [20] ,Trigger Transfer to Communication Controller Set/Reset 1 Buffer 20" "Not requested,Requested"
textline " "
setclrfld.long 0x00 19. 0x00 19. 0x04 19. " [19] ,Trigger Transfer to Communication Controller Set/Reset 1 Buffer 19" "Not requested,Requested"
setclrfld.long 0x00 18. 0x00 18. 0x04 18. " [18] ,Trigger Transfer to Communication Controller Set/Reset 1 Buffer 18" "Not requested,Requested"
setclrfld.long 0x00 17. 0x00 17. 0x04 17. " [17] ,Trigger Transfer to Communication Controller Set/Reset 1 Buffer 17" "Not requested,Requested"
setclrfld.long 0x00 16. 0x00 16. 0x04 16. " [16] ,Trigger Transfer to Communication Controller Set/Reset 1 Buffer 16" "Not requested,Requested"
textline " "
setclrfld.long 0x00 15. 0x00 15. 0x04 15. " [15] ,Trigger Transfer to Communication Controller Set/Reset 1 Buffer 15" "Not requested,Requested"
setclrfld.long 0x00 14. 0x00 14. 0x04 14. " [14] ,Trigger Transfer to Communication Controller Set/Reset 1 Buffer 14" "Not requested,Requested"
setclrfld.long 0x00 13. 0x00 13. 0x04 13. " [13] ,Trigger Transfer to Communication Controller Set/Reset 1 Buffer 13" "Not requested,Requested"
setclrfld.long 0x00 12. 0x00 12. 0x04 12. " [12] ,Trigger Transfer to Communication Controller Set/Reset 1 Buffer 12" "Not requested,Requested"
textline " "
setclrfld.long 0x00 11. 0x00 11. 0x04 11. " [11] ,Trigger Transfer to Communication Controller Set/Reset 1 Buffer 11" "Not requested,Requested"
setclrfld.long 0x00 10. 0x00 10. 0x04 10. " [10] ,Trigger Transfer to Communication Controller Set/Reset 1 Buffer 10" "Not requested,Requested"
setclrfld.long 0x00 9. 0x00 9. 0x04 9. " [9] ,Trigger Transfer to Communication Controller Set/Reset 1 Buffer 9" "Not requested,Requested"
setclrfld.long 0x00 8. 0x00 8. 0x04 8. " [8] ,Trigger Transfer to Communication Controller Set/Reset 1 Buffer 8" "Not requested,Requested"
textline " "
setclrfld.long 0x00 7. 0x00 7. 0x04 7. " [7] ,Trigger Transfer to Communication Controller Set/Reset 1 Buffer 7" "Not requested,Requested"
setclrfld.long 0x00 6. 0x00 6. 0x04 6. " [6] ,Trigger Transfer to Communication Controller Set/Reset 1 Buffer 6" "Not requested,Requested"
setclrfld.long 0x00 5. 0x00 5. 0x04 5. " [5] ,Trigger Transfer to Communication Controller Set/Reset 1 Buffer 5" "Not requested,Requested"
setclrfld.long 0x00 4. 0x00 4. 0x04 4. " [4] ,Trigger Transfer to Communication Controller Set/Reset 1 Buffer 4" "Not requested,Requested"
textline " "
setclrfld.long 0x00 3. 0x00 3. 0x04 3. " [3] ,Trigger Transfer to Communication Controller Set/Reset 1 Buffer 3" "Not requested,Requested"
setclrfld.long 0x00 2. 0x00 2. 0x04 2. " [2] ,Trigger Transfer to Communication Controller Set/Reset 1 Buffer 2" "Not requested,Requested"
setclrfld.long 0x00 1. 0x00 1. 0x04 1. " [1] ,Trigger Transfer to Communication Controller Set/Reset 1 Buffer 1" "Not requested,Requested"
setclrfld.long 0x00 0. 0x00 0. 0x04 0. " [0] ,Trigger Transfer to Communication Controller Set/Reset 1 Buffer 0" "Not requested,Requested"
group.long 0xA8++0x3
line.long 0x0 "TTCCS/R2,Trigger Transfer to Communication Controller Set/Reset 2"
setclrfld.long 0x00 31. 0x00 31. 0x04 31. " TTCCS/R2_set/clr [31] ,Trigger Transfer to Communication Controller Set/Reset 2 Buffer 63" "Not requested,Requested"
setclrfld.long 0x00 30. 0x00 30. 0x04 30. " [30] ,Trigger Transfer to Communication Controller Set/Reset 2 Buffer 62" "Not requested,Requested"
setclrfld.long 0x00 29. 0x00 29. 0x04 29. " [29] ,Trigger Transfer to Communication Controller Set/Reset 2 Buffer 61" "Not requested,Requested"
setclrfld.long 0x00 28. 0x00 28. 0x04 28. " [28] ,Trigger Transfer to Communication Controller Set/Reset 2 Buffer 60" "Not requested,Requested"
textline " "
setclrfld.long 0x00 27. 0x00 27. 0x04 27. " [27] ,Trigger Transfer to Communication Controller Set/Reset 2 Buffer 59" "Not requested,Requested"
setclrfld.long 0x00 26. 0x00 26. 0x04 26. " [26] ,Trigger Transfer to Communication Controller Set/Reset 2 Buffer 58" "Not requested,Requested"
setclrfld.long 0x00 25. 0x00 25. 0x04 25. " [25] ,Trigger Transfer to Communication Controller Set/Reset 2 Buffer 57" "Not requested,Requested"
setclrfld.long 0x00 24. 0x00 24. 0x04 24. " [24] ,Trigger Transfer to Communication Controller Set/Reset 2 Buffer 56" "Not requested,Requested"
textline " "
setclrfld.long 0x00 23. 0x00 23. 0x04 23. " [23] ,Trigger Transfer to Communication Controller Set/Reset 2 Buffer 55" "Not requested,Requested"
setclrfld.long 0x00 22. 0x00 22. 0x04 22. " [22] ,Trigger Transfer to Communication Controller Set/Reset 2 Buffer 54" "Not requested,Requested"
setclrfld.long 0x00 21. 0x00 21. 0x04 21. " [21] ,Trigger Transfer to Communication Controller Set/Reset 2 Buffer 53" "Not requested,Requested"
setclrfld.long 0x00 20. 0x00 20. 0x04 20. " [20] ,Trigger Transfer to Communication Controller Set/Reset 2 Buffer 52" "Not requested,Requested"
textline " "
setclrfld.long 0x00 19. 0x00 19. 0x04 19. " [19] ,Trigger Transfer to Communication Controller Set/Reset 2 Buffer 51" "Not requested,Requested"
setclrfld.long 0x00 18. 0x00 18. 0x04 18. " [18] ,Trigger Transfer to Communication Controller Set/Reset 2 Buffer 50" "Not requested,Requested"
setclrfld.long 0x00 17. 0x00 17. 0x04 17. " [17] ,Trigger Transfer to Communication Controller Set/Reset 2 Buffer 49" "Not requested,Requested"
setclrfld.long 0x00 16. 0x00 16. 0x04 16. " [16] ,Trigger Transfer to Communication Controller Set/Reset 2 Buffer 48" "Not requested,Requested"
textline " "
setclrfld.long 0x00 15. 0x00 15. 0x04 15. " [15] ,Trigger Transfer to Communication Controller Set/Reset 2 Buffer 47" "Not requested,Requested"
setclrfld.long 0x00 14. 0x00 14. 0x04 14. " [14] ,Trigger Transfer to Communication Controller Set/Reset 2 Buffer 46" "Not requested,Requested"
setclrfld.long 0x00 13. 0x00 13. 0x04 13. " [13] ,Trigger Transfer to Communication Controller Set/Reset 2 Buffer 45" "Not requested,Requested"
setclrfld.long 0x00 12. 0x00 12. 0x04 12. " [12] ,Trigger Transfer to Communication Controller Set/Reset 2 Buffer 44" "Not requested,Requested"
textline " "
setclrfld.long 0x00 11. 0x00 11. 0x04 11. " [11] ,Trigger Transfer to Communication Controller Set/Reset 2 Buffer 43" "Not requested,Requested"
setclrfld.long 0x00 10. 0x00 10. 0x04 10. " [10] ,Trigger Transfer to Communication Controller Set/Reset 2 Buffer 42" "Not requested,Requested"
setclrfld.long 0x00 9. 0x00 9. 0x04 9. " [9] ,Trigger Transfer to Communication Controller Set/Reset 2 Buffer 41" "Not requested,Requested"
setclrfld.long 0x00 8. 0x00 8. 0x04 8. " [8] ,Trigger Transfer to Communication Controller Set/Reset 2 Buffer 40" "Not requested,Requested"
textline " "
setclrfld.long 0x00 7. 0x00 7. 0x04 7. " [7] ,Trigger Transfer to Communication Controller Set/Reset 2 Buffer 39" "Not requested,Requested"
setclrfld.long 0x00 6. 0x00 6. 0x04 6. " [6] ,Trigger Transfer to Communication Controller Set/Reset 2 Buffer 38" "Not requested,Requested"
setclrfld.long 0x00 5. 0x00 5. 0x04 5. " [5] ,Trigger Transfer to Communication Controller Set/Reset 2 Buffer 37" "Not requested,Requested"
setclrfld.long 0x00 4. 0x00 4. 0x04 4. " [4] ,Trigger Transfer to Communication Controller Set/Reset 2 Buffer 36" "Not requested,Requested"
textline " "
setclrfld.long 0x00 3. 0x00 3. 0x04 3. " [3] ,Trigger Transfer to Communication Controller Set/Reset 2 Buffer 35" "Not requested,Requested"
setclrfld.long 0x00 2. 0x00 2. 0x04 2. " [2] ,Trigger Transfer to Communication Controller Set/Reset 2 Buffer 34" "Not requested,Requested"
setclrfld.long 0x00 1. 0x00 1. 0x04 1. " [1] ,Trigger Transfer to Communication Controller Set/Reset 2 Buffer 33" "Not requested,Requested"
setclrfld.long 0x00 0. 0x00 0. 0x04 0. " [0] ,Trigger Transfer to Communication Controller Set/Reset 2 Buffer 32" "Not requested,Requested"
group.long 0xB0++0x3
line.long 0x0 "TTCCS/R3,Trigger Transfer to Communication Controller Set/Reset 3"
setclrfld.long 0x00 31. 0x00 31. 0x04 31. " TTCCS/R3_set/clr [31] ,Trigger Transfer to Communication Controller Set/Reset 3 Buffer 95" "Not requested,Requested"
setclrfld.long 0x00 30. 0x00 30. 0x04 30. " [30] ,Trigger Transfer to Communication Controller Set/Reset 3 Buffer 94" "Not requested,Requested"
setclrfld.long 0x00 29. 0x00 29. 0x04 29. " [29] ,Trigger Transfer to Communication Controller Set/Reset 3 Buffer 93" "Not requested,Requested"
setclrfld.long 0x00 28. 0x00 28. 0x04 28. " [28] ,Trigger Transfer to Communication Controller Set/Reset 3 Buffer 92" "Not requested,Requested"
textline " "
setclrfld.long 0x00 27. 0x00 27. 0x04 27. " [27] ,Trigger Transfer to Communication Controller Set/Reset 3 Buffer 91" "Not requested,Requested"
setclrfld.long 0x00 26. 0x00 26. 0x04 26. " [26] ,Trigger Transfer to Communication Controller Set/Reset 3 Buffer 90" "Not requested,Requested"
setclrfld.long 0x00 25. 0x00 25. 0x04 25. " [25] ,Trigger Transfer to Communication Controller Set/Reset 3 Buffer 89" "Not requested,Requested"
setclrfld.long 0x00 24. 0x00 24. 0x04 24. " [24] ,Trigger Transfer to Communication Controller Set/Reset 3 Buffer 88" "Not requested,Requested"
textline " "
setclrfld.long 0x00 23. 0x00 23. 0x04 23. " [23] ,Trigger Transfer to Communication Controller Set/Reset 3 Buffer 87" "Not requested,Requested"
setclrfld.long 0x00 22. 0x00 22. 0x04 22. " [22] ,Trigger Transfer to Communication Controller Set/Reset 3 Buffer 86" "Not requested,Requested"
setclrfld.long 0x00 21. 0x00 21. 0x04 21. " [21] ,Trigger Transfer to Communication Controller Set/Reset 3 Buffer 85" "Not requested,Requested"
setclrfld.long 0x00 20. 0x00 20. 0x04 20. " [20] ,Trigger Transfer to Communication Controller Set/Reset 3 Buffer 84" "Not requested,Requested"
textline " "
setclrfld.long 0x00 19. 0x00 19. 0x04 19. " [19] ,Trigger Transfer to Communication Controller Set/Reset 3 Buffer 83" "Not requested,Requested"
setclrfld.long 0x00 18. 0x00 18. 0x04 18. " [18] ,Trigger Transfer to Communication Controller Set/Reset 3 Buffer 82" "Not requested,Requested"
setclrfld.long 0x00 17. 0x00 17. 0x04 17. " [17] ,Trigger Transfer to Communication Controller Set/Reset 3 Buffer 81" "Not requested,Requested"
setclrfld.long 0x00 16. 0x00 16. 0x04 16. " [16] ,Trigger Transfer to Communication Controller Set/Reset 3 Buffer 80" "Not requested,Requested"
textline " "
setclrfld.long 0x00 15. 0x00 15. 0x04 15. " [15] ,Trigger Transfer to Communication Controller Set/Reset 3 Buffer 79" "Not requested,Requested"
setclrfld.long 0x00 14. 0x00 14. 0x04 14. " [14] ,Trigger Transfer to Communication Controller Set/Reset 3 Buffer 78" "Not requested,Requested"
setclrfld.long 0x00 13. 0x00 13. 0x04 13. " [13] ,Trigger Transfer to Communication Controller Set/Reset 3 Buffer 77" "Not requested,Requested"
setclrfld.long 0x00 12. 0x00 12. 0x04 12. " [12] ,Trigger Transfer to Communication Controller Set/Reset 3 Buffer 76" "Not requested,Requested"
textline " "
setclrfld.long 0x00 11. 0x00 11. 0x04 11. " [11] ,Trigger Transfer to Communication Controller Set/Reset 3 Buffer 75" "Not requested,Requested"
setclrfld.long 0x00 10. 0x00 10. 0x04 10. " [10] ,Trigger Transfer to Communication Controller Set/Reset 3 Buffer 74" "Not requested,Requested"
setclrfld.long 0x00 9. 0x00 9. 0x04 9. " [9] ,Trigger Transfer to Communication Controller Set/Reset 3 Buffer 73" "Not requested,Requested"
setclrfld.long 0x00 8. 0x00 8. 0x04 8. " [8] ,Trigger Transfer to Communication Controller Set/Reset 3 Buffer 72" "Not requested,Requested"
textline " "
setclrfld.long 0x00 7. 0x00 7. 0x04 7. " [7] ,Trigger Transfer to Communication Controller Set/Reset 3 Buffer 71" "Not requested,Requested"
setclrfld.long 0x00 6. 0x00 6. 0x04 6. " [6] ,Trigger Transfer to Communication Controller Set/Reset 3 Buffer 70" "Not requested,Requested"
setclrfld.long 0x00 5. 0x00 5. 0x04 5. " [5] ,Trigger Transfer to Communication Controller Set/Reset 3 Buffer 69" "Not requested,Requested"
setclrfld.long 0x00 4. 0x00 4. 0x04 4. " [4] ,Trigger Transfer to Communication Controller Set/Reset 3 Buffer 68" "Not requested,Requested"
textline " "
setclrfld.long 0x00 3. 0x00 3. 0x04 3. " [3] ,Trigger Transfer to Communication Controller Set/Reset 3 Buffer 67" "Not requested,Requested"
setclrfld.long 0x00 2. 0x00 2. 0x04 2. " [2] ,Trigger Transfer to Communication Controller Set/Reset 3 Buffer 66" "Not requested,Requested"
setclrfld.long 0x00 1. 0x00 1. 0x04 1. " [1] ,Trigger Transfer to Communication Controller Set/Reset 3 Buffer 65" "Not requested,Requested"
setclrfld.long 0x00 0. 0x00 0. 0x04 0. " [0] ,Trigger Transfer to Communication Controller Set/Reset 3 Buffer 64" "Not requested,Requested"
group.long 0xB8++0x3
line.long 0x0 "TTCCS/R4,Trigger Transfer to Communication Controller Set/Reset 4"
setclrfld.long 0x00 31. 0x00 31. 0x04 31. " TTCCS/R4_set/clr [31] ,Trigger Transfer to Communication Controller Set/Reset 4 Buffer 127" "Not requested,Requested"
setclrfld.long 0x00 30. 0x00 30. 0x04 30. " [30] ,Trigger Transfer to Communication Controller Set/Reset 4 Buffer 126" "Not requested,Requested"
setclrfld.long 0x00 29. 0x00 29. 0x04 29. " [29] ,Trigger Transfer to Communication Controller Set/Reset 4 Buffer 125" "Not requested,Requested"
setclrfld.long 0x00 28. 0x00 28. 0x04 28. " [28] ,Trigger Transfer to Communication Controller Set/Reset 4 Buffer 124" "Not requested,Requested"
textline " "
setclrfld.long 0x00 27. 0x00 27. 0x04 27. " [27] ,Trigger Transfer to Communication Controller Set/Reset 4 Buffer 123" "Not requested,Requested"
setclrfld.long 0x00 26. 0x00 26. 0x04 26. " [26] ,Trigger Transfer to Communication Controller Set/Reset 4 Buffer 122" "Not requested,Requested"
setclrfld.long 0x00 25. 0x00 25. 0x04 25. " [25] ,Trigger Transfer to Communication Controller Set/Reset 4 Buffer 121" "Not requested,Requested"
setclrfld.long 0x00 24. 0x00 24. 0x04 24. " [24] ,Trigger Transfer to Communication Controller Set/Reset 4 Buffer 120" "Not requested,Requested"
textline " "
setclrfld.long 0x00 23. 0x00 23. 0x04 23. " [23] ,Trigger Transfer to Communication Controller Set/Reset 4 Buffer 119" "Not requested,Requested"
setclrfld.long 0x00 22. 0x00 22. 0x04 22. " [22] ,Trigger Transfer to Communication Controller Set/Reset 4 Buffer 118" "Not requested,Requested"
setclrfld.long 0x00 21. 0x00 21. 0x04 21. " [21] ,Trigger Transfer to Communication Controller Set/Reset 4 Buffer 117" "Not requested,Requested"
setclrfld.long 0x00 20. 0x00 20. 0x04 20. " [20] ,Trigger Transfer to Communication Controller Set/Reset 4 Buffer 116" "Not requested,Requested"
textline " "
setclrfld.long 0x00 19. 0x00 19. 0x04 19. " [19] ,Trigger Transfer to Communication Controller Set/Reset 4 Buffer 115" "Not requested,Requested"
setclrfld.long 0x00 18. 0x00 18. 0x04 18. " [18] ,Trigger Transfer to Communication Controller Set/Reset 4 Buffer 114" "Not requested,Requested"
setclrfld.long 0x00 17. 0x00 17. 0x04 17. " [17] ,Trigger Transfer to Communication Controller Set/Reset 4 Buffer 113" "Not requested,Requested"
setclrfld.long 0x00 16. 0x00 16. 0x04 16. " [16] ,Trigger Transfer to Communication Controller Set/Reset 4 Buffer 112" "Not requested,Requested"
textline " "
setclrfld.long 0x00 15. 0x00 15. 0x04 15. " [15] ,Trigger Transfer to Communication Controller Set/Reset 4 Buffer 111" "Not requested,Requested"
setclrfld.long 0x00 14. 0x00 14. 0x04 14. " [14] ,Trigger Transfer to Communication Controller Set/Reset 4 Buffer 110" "Not requested,Requested"
setclrfld.long 0x00 13. 0x00 13. 0x04 13. " [13] ,Trigger Transfer to Communication Controller Set/Reset 4 Buffer 109" "Not requested,Requested"
setclrfld.long 0x00 12. 0x00 12. 0x04 12. " [12] ,Trigger Transfer to Communication Controller Set/Reset 4 Buffer 108" "Not requested,Requested"
textline " "
setclrfld.long 0x00 11. 0x00 11. 0x04 11. " [11] ,Trigger Transfer to Communication Controller Set/Reset 4 Buffer 107" "Not requested,Requested"
setclrfld.long 0x00 10. 0x00 10. 0x04 10. " [10] ,Trigger Transfer to Communication Controller Set/Reset 4 Buffer 106" "Not requested,Requested"
setclrfld.long 0x00 9. 0x00 9. 0x04 9. " [9] ,Trigger Transfer to Communication Controller Set/Reset 4 Buffer 105" "Not requested,Requested"
setclrfld.long 0x00 8. 0x00 8. 0x04 8. " [8] ,Trigger Transfer to Communication Controller Set/Reset 4 Buffer 104" "Not requested,Requested"
textline " "
setclrfld.long 0x00 7. 0x00 7. 0x04 7. " [7] ,Trigger Transfer to Communication Controller Set/Reset 4 Buffer 103" "Not requested,Requested"
setclrfld.long 0x00 6. 0x00 6. 0x04 6. " [6] ,Trigger Transfer to Communication Controller Set/Reset 4 Buffer 102" "Not requested,Requested"
setclrfld.long 0x00 5. 0x00 5. 0x04 5. " [5] ,Trigger Transfer to Communication Controller Set/Reset 4 Buffer 101" "Not requested,Requested"
setclrfld.long 0x00 4. 0x00 4. 0x04 4. " [4] ,Trigger Transfer to Communication Controller Set/Reset 4 Buffer 100" "Not requested,Requested"
textline " "
setclrfld.long 0x00 3. 0x00 3. 0x04 3. " [3] ,Trigger Transfer to Communication Controller Set/Reset 4 Buffer 99" "Not requested,Requested"
setclrfld.long 0x00 2. 0x00 2. 0x04 2. " [2] ,Trigger Transfer to Communication Controller Set/Reset 4 Buffer 98" "Not requested,Requested"
setclrfld.long 0x00 1. 0x00 1. 0x04 1. " [1] ,Trigger Transfer to Communication Controller Set/Reset 4 Buffer 97" "Not requested,Requested"
setclrfld.long 0x00 0. 0x00 0. 0x04 0. " [0] ,Trigger Transfer to Communication Controller Set/Reset 4 Buffer 96" "Not requested,Requested"
group.long 0xC0++0x3
line.long 0x0 "ETESMS/R1,Enable Transfer on Event to System Memory Set/Reset 1"
setclrfld.long 0x00 31. 0x00 31. 0x04 31. " ETESMS/R1_set/clr [31] ,Enable Transfer on Event to System Memory Set/Reset 1 Buffer 31" "Disabled,Enabled"
setclrfld.long 0x00 30. 0x00 30. 0x04 30. " [30] ,Enable Transfer on Event to System Memory Set/Reset 1 Buffer 30" "Disabled,Enabled"
setclrfld.long 0x00 29. 0x00 29. 0x04 29. " [29] ,Enable Transfer on Event to System Memory Set/Reset 1 Buffer 29" "Disabled,Enabled"
setclrfld.long 0x00 28. 0x00 28. 0x04 28. " [28] ,Enable Transfer on Event to System Memory Set/Reset 1 Buffer 28" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 27. 0x00 27. 0x04 27. " [27] ,Enable Transfer on Event to System Memory Set/Reset 1 Buffer 27" "Disabled,Enabled"
setclrfld.long 0x00 26. 0x00 26. 0x04 26. " [26] ,Enable Transfer on Event to System Memory Set/Reset 1 Buffer 26" "Disabled,Enabled"
setclrfld.long 0x00 25. 0x00 25. 0x04 25. " [25] ,Enable Transfer on Event to System Memory Set/Reset 1 Buffer 25" "Disabled,Enabled"
setclrfld.long 0x00 24. 0x00 24. 0x04 24. " [24] ,Enable Transfer on Event to System Memory Set/Reset 1 Buffer 24" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 23. 0x00 23. 0x04 23. " [23] ,Enable Transfer on Event to System Memory Set/Reset 1 Buffer 23" "Disabled,Enabled"
setclrfld.long 0x00 22. 0x00 22. 0x04 22. " [22] ,Enable Transfer on Event to System Memory Set/Reset 1 Buffer 22" "Disabled,Enabled"
setclrfld.long 0x00 21. 0x00 21. 0x04 21. " [21] ,Enable Transfer on Event to System Memory Set/Reset 1 Buffer 21" "Disabled,Enabled"
setclrfld.long 0x00 20. 0x00 20. 0x04 20. " [20] ,Enable Transfer on Event to System Memory Set/Reset 1 Buffer 20" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 19. 0x00 19. 0x04 19. " [19] ,Enable Transfer on Event to System Memory Set/Reset 1 Buffer 19" "Disabled,Enabled"
setclrfld.long 0x00 18. 0x00 18. 0x04 18. " [18] ,Enable Transfer on Event to System Memory Set/Reset 1 Buffer 18" "Disabled,Enabled"
setclrfld.long 0x00 17. 0x00 17. 0x04 17. " [17] ,Enable Transfer on Event to System Memory Set/Reset 1 Buffer 17" "Disabled,Enabled"
setclrfld.long 0x00 16. 0x00 16. 0x04 16. " [16] ,Enable Transfer on Event to System Memory Set/Reset 1 Buffer 16" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 15. 0x00 15. 0x04 15. " [15] ,Enable Transfer on Event to System Memory Set/Reset 1 Buffer 15" "Disabled,Enabled"
setclrfld.long 0x00 14. 0x00 14. 0x04 14. " [14] ,Enable Transfer on Event to System Memory Set/Reset 1 Buffer 14" "Disabled,Enabled"
setclrfld.long 0x00 13. 0x00 13. 0x04 13. " [13] ,Enable Transfer on Event to System Memory Set/Reset 1 Buffer 13" "Disabled,Enabled"
setclrfld.long 0x00 12. 0x00 12. 0x04 12. " [12] ,Enable Transfer on Event to System Memory Set/Reset 1 Buffer 12" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 11. 0x00 11. 0x04 11. " [11] ,Enable Transfer on Event to System Memory Set/Reset 1 Buffer 11" "Disabled,Enabled"
setclrfld.long 0x00 10. 0x00 10. 0x04 10. " [10] ,Enable Transfer on Event to System Memory Set/Reset 1 Buffer 10" "Disabled,Enabled"
setclrfld.long 0x00 9. 0x00 9. 0x04 9. " [9] ,Enable Transfer on Event to System Memory Set/Reset 1 Buffer 9" "Disabled,Enabled"
setclrfld.long 0x00 8. 0x00 8. 0x04 8. " [8] ,Enable Transfer on Event to System Memory Set/Reset 1 Buffer 8" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 7. 0x00 7. 0x04 7. " [7] ,Enable Transfer on Event to System Memory Set/Reset 1 Buffer 7" "Disabled,Enabled"
setclrfld.long 0x00 6. 0x00 6. 0x04 6. " [6] ,Enable Transfer on Event to System Memory Set/Reset 1 Buffer 6" "Disabled,Enabled"
setclrfld.long 0x00 5. 0x00 5. 0x04 5. " [5] ,Enable Transfer on Event to System Memory Set/Reset 1 Buffer 5" "Disabled,Enabled"
setclrfld.long 0x00 4. 0x00 4. 0x04 4. " [4] ,Enable Transfer on Event to System Memory Set/Reset 1 Buffer 4" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 3. 0x00 3. 0x04 3. " [3] ,Enable Transfer on Event to System Memory Set/Reset 1 Buffer 3" "Disabled,Enabled"
setclrfld.long 0x00 2. 0x00 2. 0x04 2. " [2] ,Enable Transfer on Event to System Memory Set/Reset 1 Buffer 2" "Disabled,Enabled"
setclrfld.long 0x00 1. 0x00 1. 0x04 1. " [1] ,Enable Transfer on Event to System Memory Set/Reset 1 Buffer 1" "Disabled,Enabled"
setclrfld.long 0x00 0. 0x00 0. 0x04 0. " [0] ,Enable Transfer on Event to System Memory Set/Reset 1 Buffer 0" "Disabled,Enabled"
group.long 0xC8++0x3
line.long 0x0 "ETESMS/R2,Enable Transfer on Event to System Memory Set/Reset 2"
setclrfld.long 0x00 31. 0x00 31. 0x04 31. " ETESMS/R2_set/clr [31] ,Enable Transfer on Event to System Memory Set/Reset 2 Buffer 63" "Disabled,Enabled"
setclrfld.long 0x00 30. 0x00 30. 0x04 30. " [30] ,Enable Transfer on Event to System Memory Set/Reset 2 Buffer 62" "Disabled,Enabled"
setclrfld.long 0x00 29. 0x00 29. 0x04 29. " [29] ,Enable Transfer on Event to System Memory Set/Reset 2 Buffer 61" "Disabled,Enabled"
setclrfld.long 0x00 28. 0x00 28. 0x04 28. " [28] ,Enable Transfer on Event to System Memory Set/Reset 2 Buffer 60" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 27. 0x00 27. 0x04 27. " [27] ,Enable Transfer on Event to System Memory Set/Reset 2 Buffer 59" "Disabled,Enabled"
setclrfld.long 0x00 26. 0x00 26. 0x04 26. " [26] ,Enable Transfer on Event to System Memory Set/Reset 2 Buffer 58" "Disabled,Enabled"
setclrfld.long 0x00 25. 0x00 25. 0x04 25. " [25] ,Enable Transfer on Event to System Memory Set/Reset 2 Buffer 57" "Disabled,Enabled"
setclrfld.long 0x00 24. 0x00 24. 0x04 24. " [24] ,Enable Transfer on Event to System Memory Set/Reset 2 Buffer 56" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 23. 0x00 23. 0x04 23. " [23] ,Enable Transfer on Event to System Memory Set/Reset 2 Buffer 55" "Disabled,Enabled"
setclrfld.long 0x00 22. 0x00 22. 0x04 22. " [22] ,Enable Transfer on Event to System Memory Set/Reset 2 Buffer 54" "Disabled,Enabled"
setclrfld.long 0x00 21. 0x00 21. 0x04 21. " [21] ,Enable Transfer on Event to System Memory Set/Reset 2 Buffer 53" "Disabled,Enabled"
setclrfld.long 0x00 20. 0x00 20. 0x04 20. " [20] ,Enable Transfer on Event to System Memory Set/Reset 2 Buffer 52" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 19. 0x00 19. 0x04 19. " [19] ,Enable Transfer on Event to System Memory Set/Reset 2 Buffer 51" "Disabled,Enabled"
setclrfld.long 0x00 18. 0x00 18. 0x04 18. " [18] ,Enable Transfer on Event to System Memory Set/Reset 2 Buffer 50" "Disabled,Enabled"
setclrfld.long 0x00 17. 0x00 17. 0x04 17. " [17] ,Enable Transfer on Event to System Memory Set/Reset 2 Buffer 49" "Disabled,Enabled"
setclrfld.long 0x00 16. 0x00 16. 0x04 16. " [16] ,Enable Transfer on Event to System Memory Set/Reset 2 Buffer 48" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 15. 0x00 15. 0x04 15. " [15] ,Enable Transfer on Event to System Memory Set/Reset 2 Buffer 47" "Disabled,Enabled"
setclrfld.long 0x00 14. 0x00 14. 0x04 14. " [14] ,Enable Transfer on Event to System Memory Set/Reset 2 Buffer 46" "Disabled,Enabled"
setclrfld.long 0x00 13. 0x00 13. 0x04 13. " [13] ,Enable Transfer on Event to System Memory Set/Reset 2 Buffer 45" "Disabled,Enabled"
setclrfld.long 0x00 12. 0x00 12. 0x04 12. " [12] ,Enable Transfer on Event to System Memory Set/Reset 2 Buffer 44" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 11. 0x00 11. 0x04 11. " [11] ,Enable Transfer on Event to System Memory Set/Reset 2 Buffer 43" "Disabled,Enabled"
setclrfld.long 0x00 10. 0x00 10. 0x04 10. " [10] ,Enable Transfer on Event to System Memory Set/Reset 2 Buffer 42" "Disabled,Enabled"
setclrfld.long 0x00 9. 0x00 9. 0x04 9. " [9] ,Enable Transfer on Event to System Memory Set/Reset 2 Buffer 41" "Disabled,Enabled"
setclrfld.long 0x00 8. 0x00 8. 0x04 8. " [8] ,Enable Transfer on Event to System Memory Set/Reset 2 Buffer 40" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 7. 0x00 7. 0x04 7. " [7] ,Enable Transfer on Event to System Memory Set/Reset 2 Buffer 39" "Disabled,Enabled"
setclrfld.long 0x00 6. 0x00 6. 0x04 6. " [6] ,Enable Transfer on Event to System Memory Set/Reset 2 Buffer 38" "Disabled,Enabled"
setclrfld.long 0x00 5. 0x00 5. 0x04 5. " [5] ,Enable Transfer on Event to System Memory Set/Reset 2 Buffer 37" "Disabled,Enabled"
setclrfld.long 0x00 4. 0x00 4. 0x04 4. " [4] ,Enable Transfer on Event to System Memory Set/Reset 2 Buffer 36" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 3. 0x00 3. 0x04 3. " [3] ,Enable Transfer on Event to System Memory Set/Reset 2 Buffer 35" "Disabled,Enabled"
setclrfld.long 0x00 2. 0x00 2. 0x04 2. " [2] ,Enable Transfer on Event to System Memory Set/Reset 2 Buffer 34" "Disabled,Enabled"
setclrfld.long 0x00 1. 0x00 1. 0x04 1. " [1] ,Enable Transfer on Event to System Memory Set/Reset 2 Buffer 33" "Disabled,Enabled"
setclrfld.long 0x00 0. 0x00 0. 0x04 0. " [0] ,Enable Transfer on Event to System Memory Set/Reset 2 Buffer 32" "Disabled,Enabled"
group.long 0xD0++0x3
line.long 0x0 "ETESMS/R3,Enable Transfer on Event to System Memory Set/Reset 3"
setclrfld.long 0x00 31. 0x00 31. 0x04 31. " ETESMS/R3_set/clr [31] ,Enable Transfer on Event to System Memory Set/Reset 3 Buffer 95" "Disabled,Enabled"
setclrfld.long 0x00 30. 0x00 30. 0x04 30. " [30] ,Enable Transfer on Event to System Memory Set/Reset 3 Buffer 94" "Disabled,Enabled"
setclrfld.long 0x00 29. 0x00 29. 0x04 29. " [29] ,Enable Transfer on Event to System Memory Set/Reset 3 Buffer 93" "Disabled,Enabled"
setclrfld.long 0x00 28. 0x00 28. 0x04 28. " [28] ,Enable Transfer on Event to System Memory Set/Reset 3 Buffer 92" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 27. 0x00 27. 0x04 27. " [27] ,Enable Transfer on Event to System Memory Set/Reset 3 Buffer 91" "Disabled,Enabled"
setclrfld.long 0x00 26. 0x00 26. 0x04 26. " [26] ,Enable Transfer on Event to System Memory Set/Reset 3 Buffer 90" "Disabled,Enabled"
setclrfld.long 0x00 25. 0x00 25. 0x04 25. " [25] ,Enable Transfer on Event to System Memory Set/Reset 3 Buffer 89" "Disabled,Enabled"
setclrfld.long 0x00 24. 0x00 24. 0x04 24. " [24] ,Enable Transfer on Event to System Memory Set/Reset 3 Buffer 88" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 23. 0x00 23. 0x04 23. " [23] ,Enable Transfer on Event to System Memory Set/Reset 3 Buffer 87" "Disabled,Enabled"
setclrfld.long 0x00 22. 0x00 22. 0x04 22. " [22] ,Enable Transfer on Event to System Memory Set/Reset 3 Buffer 86" "Disabled,Enabled"
setclrfld.long 0x00 21. 0x00 21. 0x04 21. " [21] ,Enable Transfer on Event to System Memory Set/Reset 3 Buffer 85" "Disabled,Enabled"
setclrfld.long 0x00 20. 0x00 20. 0x04 20. " [20] ,Enable Transfer on Event to System Memory Set/Reset 3 Buffer 84" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 19. 0x00 19. 0x04 19. " [19] ,Enable Transfer on Event to System Memory Set/Reset 3 Buffer 83" "Disabled,Enabled"
setclrfld.long 0x00 18. 0x00 18. 0x04 18. " [18] ,Enable Transfer on Event to System Memory Set/Reset 3 Buffer 82" "Disabled,Enabled"
setclrfld.long 0x00 17. 0x00 17. 0x04 17. " [17] ,Enable Transfer on Event to System Memory Set/Reset 3 Buffer 81" "Disabled,Enabled"
setclrfld.long 0x00 16. 0x00 16. 0x04 16. " [16] ,Enable Transfer on Event to System Memory Set/Reset 3 Buffer 80" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 15. 0x00 15. 0x04 15. " [15] ,Enable Transfer on Event to System Memory Set/Reset 3 Buffer 79" "Disabled,Enabled"
setclrfld.long 0x00 14. 0x00 14. 0x04 14. " [14] ,Enable Transfer on Event to System Memory Set/Reset 3 Buffer 78" "Disabled,Enabled"
setclrfld.long 0x00 13. 0x00 13. 0x04 13. " [13] ,Enable Transfer on Event to System Memory Set/Reset 3 Buffer 77" "Disabled,Enabled"
setclrfld.long 0x00 12. 0x00 12. 0x04 12. " [12] ,Enable Transfer on Event to System Memory Set/Reset 3 Buffer 76" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 11. 0x00 11. 0x04 11. " [11] ,Enable Transfer on Event to System Memory Set/Reset 3 Buffer 75" "Disabled,Enabled"
setclrfld.long 0x00 10. 0x00 10. 0x04 10. " [10] ,Enable Transfer on Event to System Memory Set/Reset 3 Buffer 74" "Disabled,Enabled"
setclrfld.long 0x00 9. 0x00 9. 0x04 9. " [9] ,Enable Transfer on Event to System Memory Set/Reset 3 Buffer 73" "Disabled,Enabled"
setclrfld.long 0x00 8. 0x00 8. 0x04 8. " [8] ,Enable Transfer on Event to System Memory Set/Reset 3 Buffer 72" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 7. 0x00 7. 0x04 7. " [7] ,Enable Transfer on Event to System Memory Set/Reset 3 Buffer 71" "Disabled,Enabled"
setclrfld.long 0x00 6. 0x00 6. 0x04 6. " [6] ,Enable Transfer on Event to System Memory Set/Reset 3 Buffer 70" "Disabled,Enabled"
setclrfld.long 0x00 5. 0x00 5. 0x04 5. " [5] ,Enable Transfer on Event to System Memory Set/Reset 3 Buffer 69" "Disabled,Enabled"
setclrfld.long 0x00 4. 0x00 4. 0x04 4. " [4] ,Enable Transfer on Event to System Memory Set/Reset 3 Buffer 68" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 3. 0x00 3. 0x04 3. " [3] ,Enable Transfer on Event to System Memory Set/Reset 3 Buffer 67" "Disabled,Enabled"
setclrfld.long 0x00 2. 0x00 2. 0x04 2. " [2] ,Enable Transfer on Event to System Memory Set/Reset 3 Buffer 66" "Disabled,Enabled"
setclrfld.long 0x00 1. 0x00 1. 0x04 1. " [1] ,Enable Transfer on Event to System Memory Set/Reset 3 Buffer 65" "Disabled,Enabled"
setclrfld.long 0x00 0. 0x00 0. 0x04 0. " [0] ,Enable Transfer on Event to System Memory Set/Reset 3 Buffer 64" "Disabled,Enabled"
group.long 0xD8++0x3
line.long 0x0 "ETESMS/R4,Enable Transfer on Event to System Memory Set/Reset 4"
setclrfld.long 0x00 31. 0x00 31. 0x04 31. " ETESMS/R4_set/clr [31] ,Enable Transfer on Event to System Memory Set/Reset 4 Buffer 127" "Disabled,Enabled"
setclrfld.long 0x00 30. 0x00 30. 0x04 30. " [30] ,Enable Transfer on Event to System Memory Set/Reset 4 Buffer 126" "Disabled,Enabled"
setclrfld.long 0x00 29. 0x00 29. 0x04 29. " [29] ,Enable Transfer on Event to System Memory Set/Reset 4 Buffer 125" "Disabled,Enabled"
setclrfld.long 0x00 28. 0x00 28. 0x04 28. " [28] ,Enable Transfer on Event to System Memory Set/Reset 4 Buffer 124" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 27. 0x00 27. 0x04 27. " [27] ,Enable Transfer on Event to System Memory Set/Reset 4 Buffer 123" "Disabled,Enabled"
setclrfld.long 0x00 26. 0x00 26. 0x04 26. " [26] ,Enable Transfer on Event to System Memory Set/Reset 4 Buffer 122" "Disabled,Enabled"
setclrfld.long 0x00 25. 0x00 25. 0x04 25. " [25] ,Enable Transfer on Event to System Memory Set/Reset 4 Buffer 121" "Disabled,Enabled"
setclrfld.long 0x00 24. 0x00 24. 0x04 24. " [24] ,Enable Transfer on Event to System Memory Set/Reset 4 Buffer 120" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 23. 0x00 23. 0x04 23. " [23] ,Enable Transfer on Event to System Memory Set/Reset 4 Buffer 119" "Disabled,Enabled"
setclrfld.long 0x00 22. 0x00 22. 0x04 22. " [22] ,Enable Transfer on Event to System Memory Set/Reset 4 Buffer 118" "Disabled,Enabled"
setclrfld.long 0x00 21. 0x00 21. 0x04 21. " [21] ,Enable Transfer on Event to System Memory Set/Reset 4 Buffer 117" "Disabled,Enabled"
setclrfld.long 0x00 20. 0x00 20. 0x04 20. " [20] ,Enable Transfer on Event to System Memory Set/Reset 4 Buffer 116" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 19. 0x00 19. 0x04 19. " [19] ,Enable Transfer on Event to System Memory Set/Reset 4 Buffer 115" "Disabled,Enabled"
setclrfld.long 0x00 18. 0x00 18. 0x04 18. " [18] ,Enable Transfer on Event to System Memory Set/Reset 4 Buffer 114" "Disabled,Enabled"
setclrfld.long 0x00 17. 0x00 17. 0x04 17. " [17] ,Enable Transfer on Event to System Memory Set/Reset 4 Buffer 113" "Disabled,Enabled"
setclrfld.long 0x00 16. 0x00 16. 0x04 16. " [16] ,Enable Transfer on Event to System Memory Set/Reset 4 Buffer 112" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 15. 0x00 15. 0x04 15. " [15] ,Enable Transfer on Event to System Memory Set/Reset 4 Buffer 111" "Disabled,Enabled"
setclrfld.long 0x00 14. 0x00 14. 0x04 14. " [14] ,Enable Transfer on Event to System Memory Set/Reset 4 Buffer 110" "Disabled,Enabled"
setclrfld.long 0x00 13. 0x00 13. 0x04 13. " [13] ,Enable Transfer on Event to System Memory Set/Reset 4 Buffer 109" "Disabled,Enabled"
setclrfld.long 0x00 12. 0x00 12. 0x04 12. " [12] ,Enable Transfer on Event to System Memory Set/Reset 4 Buffer 108" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 11. 0x00 11. 0x04 11. " [11] ,Enable Transfer on Event to System Memory Set/Reset 4 Buffer 107" "Disabled,Enabled"
setclrfld.long 0x00 10. 0x00 10. 0x04 10. " [10] ,Enable Transfer on Event to System Memory Set/Reset 4 Buffer 106" "Disabled,Enabled"
setclrfld.long 0x00 9. 0x00 9. 0x04 9. " [9] ,Enable Transfer on Event to System Memory Set/Reset 4 Buffer 105" "Disabled,Enabled"
setclrfld.long 0x00 8. 0x00 8. 0x04 8. " [8] ,Enable Transfer on Event to System Memory Set/Reset 4 Buffer 104" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 7. 0x00 7. 0x04 7. " [7] ,Enable Transfer on Event to System Memory Set/Reset 4 Buffer 103" "Disabled,Enabled"
setclrfld.long 0x00 6. 0x00 6. 0x04 6. " [6] ,Enable Transfer on Event to System Memory Set/Reset 4 Buffer 102" "Disabled,Enabled"
setclrfld.long 0x00 5. 0x00 5. 0x04 5. " [5] ,Enable Transfer on Event to System Memory Set/Reset 4 Buffer 101" "Disabled,Enabled"
setclrfld.long 0x00 4. 0x00 4. 0x04 4. " [4] ,Enable Transfer on Event to System Memory Set/Reset 4 Buffer 100" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 3. 0x00 3. 0x04 3. " [3] ,Enable Transfer on Event to System Memory Set/Reset 4 Buffer 99" "Disabled,Enabled"
setclrfld.long 0x00 2. 0x00 2. 0x04 2. " [2] ,Enable Transfer on Event to System Memory Set/Reset 4 Buffer 98" "Disabled,Enabled"
setclrfld.long 0x00 1. 0x00 1. 0x04 1. " [1] ,Enable Transfer on Event to System Memory Set/Reset 4 Buffer 97" "Disabled,Enabled"
setclrfld.long 0x00 0. 0x00 0. 0x04 0. " [0] ,Enable Transfer on Event to System Memory Set/Reset 4 Buffer 96" "Disabled,Enabled"
group.long 0xE0++0x3
line.long 0x0 "CESMS/R1,Clear on Event to System Memory Set/Reset 1"
setclrfld.long 0x00 31. 0x00 31. 0x04 31. " CESMS/R1_set/clr [31] ,Clear on Event to System Memory Set/Reset 1 Buffer 31" "Not cleared,Cleared"
setclrfld.long 0x00 30. 0x00 30. 0x04 30. " [30] ,Clear on Event to System Memory Set/Reset 1 Buffer 30" "Not cleared,Cleared"
setclrfld.long 0x00 29. 0x00 29. 0x04 29. " [29] ,Clear on Event to System Memory Set/Reset 1 Buffer 29" "Not cleared,Cleared"
setclrfld.long 0x00 28. 0x00 28. 0x04 28. " [28] ,Clear on Event to System Memory Set/Reset 1 Buffer 28" "Not cleared,Cleared"
textline " "
setclrfld.long 0x00 27. 0x00 27. 0x04 27. " [27] ,Clear on Event to System Memory Set/Reset 1 Buffer 27" "Not cleared,Cleared"
setclrfld.long 0x00 26. 0x00 26. 0x04 26. " [26] ,Clear on Event to System Memory Set/Reset 1 Buffer 26" "Not cleared,Cleared"
setclrfld.long 0x00 25. 0x00 25. 0x04 25. " [25] ,Clear on Event to System Memory Set/Reset 1 Buffer 25" "Not cleared,Cleared"
setclrfld.long 0x00 24. 0x00 24. 0x04 24. " [24] ,Clear on Event to System Memory Set/Reset 1 Buffer 24" "Not cleared,Cleared"
textline " "
setclrfld.long 0x00 23. 0x00 23. 0x04 23. " [23] ,Clear on Event to System Memory Set/Reset 1 Buffer 23" "Not cleared,Cleared"
setclrfld.long 0x00 22. 0x00 22. 0x04 22. " [22] ,Clear on Event to System Memory Set/Reset 1 Buffer 22" "Not cleared,Cleared"
setclrfld.long 0x00 21. 0x00 21. 0x04 21. " [21] ,Clear on Event to System Memory Set/Reset 1 Buffer 21" "Not cleared,Cleared"
setclrfld.long 0x00 20. 0x00 20. 0x04 20. " [20] ,Clear on Event to System Memory Set/Reset 1 Buffer 20" "Not cleared,Cleared"
textline " "
setclrfld.long 0x00 19. 0x00 19. 0x04 19. " [19] ,Clear on Event to System Memory Set/Reset 1 Buffer 19" "Not cleared,Cleared"
setclrfld.long 0x00 18. 0x00 18. 0x04 18. " [18] ,Clear on Event to System Memory Set/Reset 1 Buffer 18" "Not cleared,Cleared"
setclrfld.long 0x00 17. 0x00 17. 0x04 17. " [17] ,Clear on Event to System Memory Set/Reset 1 Buffer 17" "Not cleared,Cleared"
setclrfld.long 0x00 16. 0x00 16. 0x04 16. " [16] ,Clear on Event to System Memory Set/Reset 1 Buffer 16" "Not cleared,Cleared"
textline " "
setclrfld.long 0x00 15. 0x00 15. 0x04 15. " [15] ,Clear on Event to System Memory Set/Reset 1 Buffer 15" "Not cleared,Cleared"
setclrfld.long 0x00 14. 0x00 14. 0x04 14. " [14] ,Clear on Event to System Memory Set/Reset 1 Buffer 14" "Not cleared,Cleared"
setclrfld.long 0x00 13. 0x00 13. 0x04 13. " [13] ,Clear on Event to System Memory Set/Reset 1 Buffer 13" "Not cleared,Cleared"
setclrfld.long 0x00 12. 0x00 12. 0x04 12. " [12] ,Clear on Event to System Memory Set/Reset 1 Buffer 12" "Not cleared,Cleared"
textline " "
setclrfld.long 0x00 11. 0x00 11. 0x04 11. " [11] ,Clear on Event to System Memory Set/Reset 1 Buffer 11" "Not cleared,Cleared"
setclrfld.long 0x00 10. 0x00 10. 0x04 10. " [10] ,Clear on Event to System Memory Set/Reset 1 Buffer 10" "Not cleared,Cleared"
setclrfld.long 0x00 9. 0x00 9. 0x04 9. " [9] ,Clear on Event to System Memory Set/Reset 1 Buffer 9" "Not cleared,Cleared"
setclrfld.long 0x00 8. 0x00 8. 0x04 8. " [8] ,Clear on Event to System Memory Set/Reset 1 Buffer 8" "Not cleared,Cleared"
textline " "
setclrfld.long 0x00 7. 0x00 7. 0x04 7. " [7] ,Clear on Event to System Memory Set/Reset 1 Buffer 7" "Not cleared,Cleared"
setclrfld.long 0x00 6. 0x00 6. 0x04 6. " [6] ,Clear on Event to System Memory Set/Reset 1 Buffer 6" "Not cleared,Cleared"
setclrfld.long 0x00 5. 0x00 5. 0x04 5. " [5] ,Clear on Event to System Memory Set/Reset 1 Buffer 5" "Not cleared,Cleared"
setclrfld.long 0x00 4. 0x00 4. 0x04 4. " [4] ,Clear on Event to System Memory Set/Reset 1 Buffer 4" "Not cleared,Cleared"
textline " "
setclrfld.long 0x00 3. 0x00 3. 0x04 3. " [3] ,Clear on Event to System Memory Set/Reset 1 Buffer 3" "Not cleared,Cleared"
setclrfld.long 0x00 2. 0x00 2. 0x04 2. " [2] ,Clear on Event to System Memory Set/Reset 1 Buffer 2" "Not cleared,Cleared"
setclrfld.long 0x00 1. 0x00 1. 0x04 1. " [1] ,Clear on Event to System Memory Set/Reset 1 Buffer 1" "Not cleared,Cleared"
setclrfld.long 0x00 0. 0x00 0. 0x04 0. " [0] ,Clear on Event to System Memory Set/Reset 1 Buffer 0" "Not cleared,Cleared"
group.long 0xE8++0x3
line.long 0x0 "CESMS/R2,Clear on Event to System Memory Set/Reset 2"
setclrfld.long 0x00 31. 0x00 31. 0x04 31. " CESMS/R2_set/clr [31] ,Clear on Event to System Memory Set/Reset 2 Buffer 63" "Not cleared,Cleared"
setclrfld.long 0x00 30. 0x00 30. 0x04 30. " [30] ,Clear on Event to System Memory Set/Reset 2 Buffer 62" "Not cleared,Cleared"
setclrfld.long 0x00 29. 0x00 29. 0x04 29. " [29] ,Clear on Event to System Memory Set/Reset 2 Buffer 61" "Not cleared,Cleared"
setclrfld.long 0x00 28. 0x00 28. 0x04 28. " [28] ,Clear on Event to System Memory Set/Reset 2 Buffer 60" "Not cleared,Cleared"
textline " "
setclrfld.long 0x00 27. 0x00 27. 0x04 27. " [27] ,Clear on Event to System Memory Set/Reset 2 Buffer 59" "Not cleared,Cleared"
setclrfld.long 0x00 26. 0x00 26. 0x04 26. " [26] ,Clear on Event to System Memory Set/Reset 2 Buffer 58" "Not cleared,Cleared"
setclrfld.long 0x00 25. 0x00 25. 0x04 25. " [25] ,Clear on Event to System Memory Set/Reset 2 Buffer 57" "Not cleared,Cleared"
setclrfld.long 0x00 24. 0x00 24. 0x04 24. " [24] ,Clear on Event to System Memory Set/Reset 2 Buffer 56" "Not cleared,Cleared"
textline " "
setclrfld.long 0x00 23. 0x00 23. 0x04 23. " [23] ,Clear on Event to System Memory Set/Reset 2 Buffer 55" "Not cleared,Cleared"
setclrfld.long 0x00 22. 0x00 22. 0x04 22. " [22] ,Clear on Event to System Memory Set/Reset 2 Buffer 54" "Not cleared,Cleared"
setclrfld.long 0x00 21. 0x00 21. 0x04 21. " [21] ,Clear on Event to System Memory Set/Reset 2 Buffer 53" "Not cleared,Cleared"
setclrfld.long 0x00 20. 0x00 20. 0x04 20. " [20] ,Clear on Event to System Memory Set/Reset 2 Buffer 52" "Not cleared,Cleared"
textline " "
setclrfld.long 0x00 19. 0x00 19. 0x04 19. " [19] ,Clear on Event to System Memory Set/Reset 2 Buffer 51" "Not cleared,Cleared"
setclrfld.long 0x00 18. 0x00 18. 0x04 18. " [18] ,Clear on Event to System Memory Set/Reset 2 Buffer 50" "Not cleared,Cleared"
setclrfld.long 0x00 17. 0x00 17. 0x04 17. " [17] ,Clear on Event to System Memory Set/Reset 2 Buffer 49" "Not cleared,Cleared"
setclrfld.long 0x00 16. 0x00 16. 0x04 16. " [16] ,Clear on Event to System Memory Set/Reset 2 Buffer 48" "Not cleared,Cleared"
textline " "
setclrfld.long 0x00 15. 0x00 15. 0x04 15. " [15] ,Clear on Event to System Memory Set/Reset 2 Buffer 47" "Not cleared,Cleared"
setclrfld.long 0x00 14. 0x00 14. 0x04 14. " [14] ,Clear on Event to System Memory Set/Reset 2 Buffer 46" "Not cleared,Cleared"
setclrfld.long 0x00 13. 0x00 13. 0x04 13. " [13] ,Clear on Event to System Memory Set/Reset 2 Buffer 45" "Not cleared,Cleared"
setclrfld.long 0x00 12. 0x00 12. 0x04 12. " [12] ,Clear on Event to System Memory Set/Reset 2 Buffer 44" "Not cleared,Cleared"
textline " "
setclrfld.long 0x00 11. 0x00 11. 0x04 11. " [11] ,Clear on Event to System Memory Set/Reset 2 Buffer 43" "Not cleared,Cleared"
setclrfld.long 0x00 10. 0x00 10. 0x04 10. " [10] ,Clear on Event to System Memory Set/Reset 2 Buffer 42" "Not cleared,Cleared"
setclrfld.long 0x00 9. 0x00 9. 0x04 9. " [9] ,Clear on Event to System Memory Set/Reset 2 Buffer 41" "Not cleared,Cleared"
setclrfld.long 0x00 8. 0x00 8. 0x04 8. " [8] ,Clear on Event to System Memory Set/Reset 2 Buffer 40" "Not cleared,Cleared"
textline " "
setclrfld.long 0x00 7. 0x00 7. 0x04 7. " [7] ,Clear on Event to System Memory Set/Reset 2 Buffer 39" "Not cleared,Cleared"
setclrfld.long 0x00 6. 0x00 6. 0x04 6. " [6] ,Clear on Event to System Memory Set/Reset 2 Buffer 38" "Not cleared,Cleared"
setclrfld.long 0x00 5. 0x00 5. 0x04 5. " [5] ,Clear on Event to System Memory Set/Reset 2 Buffer 37" "Not cleared,Cleared"
setclrfld.long 0x00 4. 0x00 4. 0x04 4. " [4] ,Clear on Event to System Memory Set/Reset 2 Buffer 36" "Not cleared,Cleared"
textline " "
setclrfld.long 0x00 3. 0x00 3. 0x04 3. " [3] ,Clear on Event to System Memory Set/Reset 2 Buffer 35" "Not cleared,Cleared"
setclrfld.long 0x00 2. 0x00 2. 0x04 2. " [2] ,Clear on Event to System Memory Set/Reset 2 Buffer 34" "Not cleared,Cleared"
setclrfld.long 0x00 1. 0x00 1. 0x04 1. " [1] ,Clear on Event to System Memory Set/Reset 2 Buffer 33" "Not cleared,Cleared"
setclrfld.long 0x00 0. 0x00 0. 0x04 0. " [0] ,Clear on Event to System Memory Set/Reset 2 Buffer 32" "Not cleared,Cleared"
group.long 0xF0++0x3
line.long 0x0 "CESMS/R3,Clear on Event to System Memory Set/Reset 3"
setclrfld.long 0x00 31. 0x00 31. 0x04 31. " CESMS/R3_set/clr [31] ,Clear on Event to System Memory Set/Reset 3 Buffer 95" "Not cleared,Cleared"
setclrfld.long 0x00 30. 0x00 30. 0x04 30. " [30] ,Clear on Event to System Memory Set/Reset 3 Buffer 94" "Not cleared,Cleared"
setclrfld.long 0x00 29. 0x00 29. 0x04 29. " [29] ,Clear on Event to System Memory Set/Reset 3 Buffer 93" "Not cleared,Cleared"
setclrfld.long 0x00 28. 0x00 28. 0x04 28. " [28] ,Clear on Event to System Memory Set/Reset 3 Buffer 92" "Not cleared,Cleared"
textline " "
setclrfld.long 0x00 27. 0x00 27. 0x04 27. " [27] ,Clear on Event to System Memory Set/Reset 3 Buffer 91" "Not cleared,Cleared"
setclrfld.long 0x00 26. 0x00 26. 0x04 26. " [26] ,Clear on Event to System Memory Set/Reset 3 Buffer 90" "Not cleared,Cleared"
setclrfld.long 0x00 25. 0x00 25. 0x04 25. " [25] ,Clear on Event to System Memory Set/Reset 3 Buffer 89" "Not cleared,Cleared"
setclrfld.long 0x00 24. 0x00 24. 0x04 24. " [24] ,Clear on Event to System Memory Set/Reset 3 Buffer 88" "Not cleared,Cleared"
textline " "
setclrfld.long 0x00 23. 0x00 23. 0x04 23. " [23] ,Clear on Event to System Memory Set/Reset 3 Buffer 87" "Not cleared,Cleared"
setclrfld.long 0x00 22. 0x00 22. 0x04 22. " [22] ,Clear on Event to System Memory Set/Reset 3 Buffer 86" "Not cleared,Cleared"
setclrfld.long 0x00 21. 0x00 21. 0x04 21. " [21] ,Clear on Event to System Memory Set/Reset 3 Buffer 85" "Not cleared,Cleared"
setclrfld.long 0x00 20. 0x00 20. 0x04 20. " [20] ,Clear on Event to System Memory Set/Reset 3 Buffer 84" "Not cleared,Cleared"
textline " "
setclrfld.long 0x00 19. 0x00 19. 0x04 19. " [19] ,Clear on Event to System Memory Set/Reset 3 Buffer 83" "Not cleared,Cleared"
setclrfld.long 0x00 18. 0x00 18. 0x04 18. " [18] ,Clear on Event to System Memory Set/Reset 3 Buffer 82" "Not cleared,Cleared"
setclrfld.long 0x00 17. 0x00 17. 0x04 17. " [17] ,Clear on Event to System Memory Set/Reset 3 Buffer 81" "Not cleared,Cleared"
setclrfld.long 0x00 16. 0x00 16. 0x04 16. " [16] ,Clear on Event to System Memory Set/Reset 3 Buffer 80" "Not cleared,Cleared"
textline " "
setclrfld.long 0x00 15. 0x00 15. 0x04 15. " [15] ,Clear on Event to System Memory Set/Reset 3 Buffer 79" "Not cleared,Cleared"
setclrfld.long 0x00 14. 0x00 14. 0x04 14. " [14] ,Clear on Event to System Memory Set/Reset 3 Buffer 78" "Not cleared,Cleared"
setclrfld.long 0x00 13. 0x00 13. 0x04 13. " [13] ,Clear on Event to System Memory Set/Reset 3 Buffer 77" "Not cleared,Cleared"
setclrfld.long 0x00 12. 0x00 12. 0x04 12. " [12] ,Clear on Event to System Memory Set/Reset 3 Buffer 76" "Not cleared,Cleared"
textline " "
setclrfld.long 0x00 11. 0x00 11. 0x04 11. " [11] ,Clear on Event to System Memory Set/Reset 3 Buffer 75" "Not cleared,Cleared"
setclrfld.long 0x00 10. 0x00 10. 0x04 10. " [10] ,Clear on Event to System Memory Set/Reset 3 Buffer 74" "Not cleared,Cleared"
setclrfld.long 0x00 9. 0x00 9. 0x04 9. " [9] ,Clear on Event to System Memory Set/Reset 3 Buffer 73" "Not cleared,Cleared"
setclrfld.long 0x00 8. 0x00 8. 0x04 8. " [8] ,Clear on Event to System Memory Set/Reset 3 Buffer 72" "Not cleared,Cleared"
textline " "
setclrfld.long 0x00 7. 0x00 7. 0x04 7. " [7] ,Clear on Event to System Memory Set/Reset 3 Buffer 71" "Not cleared,Cleared"
setclrfld.long 0x00 6. 0x00 6. 0x04 6. " [6] ,Clear on Event to System Memory Set/Reset 3 Buffer 70" "Not cleared,Cleared"
setclrfld.long 0x00 5. 0x00 5. 0x04 5. " [5] ,Clear on Event to System Memory Set/Reset 3 Buffer 69" "Not cleared,Cleared"
setclrfld.long 0x00 4. 0x00 4. 0x04 4. " [4] ,Clear on Event to System Memory Set/Reset 3 Buffer 68" "Not cleared,Cleared"
textline " "
setclrfld.long 0x00 3. 0x00 3. 0x04 3. " [3] ,Clear on Event to System Memory Set/Reset 3 Buffer 67" "Not cleared,Cleared"
setclrfld.long 0x00 2. 0x00 2. 0x04 2. " [2] ,Clear on Event to System Memory Set/Reset 3 Buffer 66" "Not cleared,Cleared"
setclrfld.long 0x00 1. 0x00 1. 0x04 1. " [1] ,Clear on Event to System Memory Set/Reset 3 Buffer 65" "Not cleared,Cleared"
setclrfld.long 0x00 0. 0x00 0. 0x04 0. " [0] ,Clear on Event to System Memory Set/Reset 3 Buffer 64" "Not cleared,Cleared"
group.long 0xF8++0x3
line.long 0x0 "CESMS/R4,Clear on Event to System Memory Set/Reset 4"
setclrfld.long 0x00 31. 0x00 31. 0x04 31. " CESMS/R4_set/clr [31] ,Clear on Event to System Memory Set/Reset 4 Buffer 127" "Not cleared,Cleared"
setclrfld.long 0x00 30. 0x00 30. 0x04 30. " [30] ,Clear on Event to System Memory Set/Reset 4 Buffer 126" "Not cleared,Cleared"
setclrfld.long 0x00 29. 0x00 29. 0x04 29. " [29] ,Clear on Event to System Memory Set/Reset 4 Buffer 125" "Not cleared,Cleared"
setclrfld.long 0x00 28. 0x00 28. 0x04 28. " [28] ,Clear on Event to System Memory Set/Reset 4 Buffer 124" "Not cleared,Cleared"
textline " "
setclrfld.long 0x00 27. 0x00 27. 0x04 27. " [27] ,Clear on Event to System Memory Set/Reset 4 Buffer 123" "Not cleared,Cleared"
setclrfld.long 0x00 26. 0x00 26. 0x04 26. " [26] ,Clear on Event to System Memory Set/Reset 4 Buffer 122" "Not cleared,Cleared"
setclrfld.long 0x00 25. 0x00 25. 0x04 25. " [25] ,Clear on Event to System Memory Set/Reset 4 Buffer 121" "Not cleared,Cleared"
setclrfld.long 0x00 24. 0x00 24. 0x04 24. " [24] ,Clear on Event to System Memory Set/Reset 4 Buffer 120" "Not cleared,Cleared"
textline " "
setclrfld.long 0x00 23. 0x00 23. 0x04 23. " [23] ,Clear on Event to System Memory Set/Reset 4 Buffer 119" "Not cleared,Cleared"
setclrfld.long 0x00 22. 0x00 22. 0x04 22. " [22] ,Clear on Event to System Memory Set/Reset 4 Buffer 118" "Not cleared,Cleared"
setclrfld.long 0x00 21. 0x00 21. 0x04 21. " [21] ,Clear on Event to System Memory Set/Reset 4 Buffer 117" "Not cleared,Cleared"
setclrfld.long 0x00 20. 0x00 20. 0x04 20. " [20] ,Clear on Event to System Memory Set/Reset 4 Buffer 116" "Not cleared,Cleared"
textline " "
setclrfld.long 0x00 19. 0x00 19. 0x04 19. " [19] ,Clear on Event to System Memory Set/Reset 4 Buffer 115" "Not cleared,Cleared"
setclrfld.long 0x00 18. 0x00 18. 0x04 18. " [18] ,Clear on Event to System Memory Set/Reset 4 Buffer 114" "Not cleared,Cleared"
setclrfld.long 0x00 17. 0x00 17. 0x04 17. " [17] ,Clear on Event to System Memory Set/Reset 4 Buffer 113" "Not cleared,Cleared"
setclrfld.long 0x00 16. 0x00 16. 0x04 16. " [16] ,Clear on Event to System Memory Set/Reset 4 Buffer 112" "Not cleared,Cleared"
textline " "
setclrfld.long 0x00 15. 0x00 15. 0x04 15. " [15] ,Clear on Event to System Memory Set/Reset 4 Buffer 111" "Not cleared,Cleared"
setclrfld.long 0x00 14. 0x00 14. 0x04 14. " [14] ,Clear on Event to System Memory Set/Reset 4 Buffer 110" "Not cleared,Cleared"
setclrfld.long 0x00 13. 0x00 13. 0x04 13. " [13] ,Clear on Event to System Memory Set/Reset 4 Buffer 109" "Not cleared,Cleared"
setclrfld.long 0x00 12. 0x00 12. 0x04 12. " [12] ,Clear on Event to System Memory Set/Reset 4 Buffer 108" "Not cleared,Cleared"
textline " "
setclrfld.long 0x00 11. 0x00 11. 0x04 11. " [11] ,Clear on Event to System Memory Set/Reset 4 Buffer 107" "Not cleared,Cleared"
setclrfld.long 0x00 10. 0x00 10. 0x04 10. " [10] ,Clear on Event to System Memory Set/Reset 4 Buffer 106" "Not cleared,Cleared"
setclrfld.long 0x00 9. 0x00 9. 0x04 9. " [9] ,Clear on Event to System Memory Set/Reset 4 Buffer 105" "Not cleared,Cleared"
setclrfld.long 0x00 8. 0x00 8. 0x04 8. " [8] ,Clear on Event to System Memory Set/Reset 4 Buffer 104" "Not cleared,Cleared"
textline " "
setclrfld.long 0x00 7. 0x00 7. 0x04 7. " [7] ,Clear on Event to System Memory Set/Reset 4 Buffer 103" "Not cleared,Cleared"
setclrfld.long 0x00 6. 0x00 6. 0x04 6. " [6] ,Clear on Event to System Memory Set/Reset 4 Buffer 102" "Not cleared,Cleared"
setclrfld.long 0x00 5. 0x00 5. 0x04 5. " [5] ,Clear on Event to System Memory Set/Reset 4 Buffer 101" "Not cleared,Cleared"
setclrfld.long 0x00 4. 0x00 4. 0x04 4. " [4] ,Clear on Event to System Memory Set/Reset 4 Buffer 100" "Not cleared,Cleared"
textline " "
setclrfld.long 0x00 3. 0x00 3. 0x04 3. " [3] ,Clear on Event to System Memory Set/Reset 4 Buffer 99" "Not cleared,Cleared"
setclrfld.long 0x00 2. 0x00 2. 0x04 2. " [2] ,Clear on Event to System Memory Set/Reset 4 Buffer 98" "Not cleared,Cleared"
setclrfld.long 0x00 1. 0x00 1. 0x04 1. " [1] ,Clear on Event to System Memory Set/Reset 4 Buffer 97" "Not cleared,Cleared"
setclrfld.long 0x00 0. 0x00 0. 0x04 0. " [0] ,Clear on Event to System Memory Set/Reset 4 Buffer 96" "Not cleared,Cleared"
group.long 0x100++0x3
line.long 0x0 "TSMIES/R1,Transfer to System Memory Interrupt Enable Set/Reset 1"
setclrfld.long 0x00 31. 0x00 31. 0x04 31. " TSMIES/R1_set/clr [31] ,Transfer to System Memory Interrupt Enable Set/Reset 1 Buffer 31" "No interrupt,Interrupt"
setclrfld.long 0x00 30. 0x00 30. 0x04 30. " [30] ,Transfer to System Memory Interrupt Enable Set/Reset 1 Buffer 30" "No interrupt,Interrupt"
setclrfld.long 0x00 29. 0x00 29. 0x04 29. " [29] ,Transfer to System Memory Interrupt Enable Set/Reset 1 Buffer 29" "No interrupt,Interrupt"
setclrfld.long 0x00 28. 0x00 28. 0x04 28. " [28] ,Transfer to System Memory Interrupt Enable Set/Reset 1 Buffer 28" "No interrupt,Interrupt"
textline " "
setclrfld.long 0x00 27. 0x00 27. 0x04 27. " [27] ,Transfer to System Memory Interrupt Enable Set/Reset 1 Buffer 27" "No interrupt,Interrupt"
setclrfld.long 0x00 26. 0x00 26. 0x04 26. " [26] ,Transfer to System Memory Interrupt Enable Set/Reset 1 Buffer 26" "No interrupt,Interrupt"
setclrfld.long 0x00 25. 0x00 25. 0x04 25. " [25] ,Transfer to System Memory Interrupt Enable Set/Reset 1 Buffer 25" "No interrupt,Interrupt"
setclrfld.long 0x00 24. 0x00 24. 0x04 24. " [24] ,Transfer to System Memory Interrupt Enable Set/Reset 1 Buffer 24" "No interrupt,Interrupt"
textline " "
setclrfld.long 0x00 23. 0x00 23. 0x04 23. " [23] ,Transfer to System Memory Interrupt Enable Set/Reset 1 Buffer 23" "No interrupt,Interrupt"
setclrfld.long 0x00 22. 0x00 22. 0x04 22. " [22] ,Transfer to System Memory Interrupt Enable Set/Reset 1 Buffer 22" "No interrupt,Interrupt"
setclrfld.long 0x00 21. 0x00 21. 0x04 21. " [21] ,Transfer to System Memory Interrupt Enable Set/Reset 1 Buffer 21" "No interrupt,Interrupt"
setclrfld.long 0x00 20. 0x00 20. 0x04 20. " [20] ,Transfer to System Memory Interrupt Enable Set/Reset 1 Buffer 20" "No interrupt,Interrupt"
textline " "
setclrfld.long 0x00 19. 0x00 19. 0x04 19. " [19] ,Transfer to System Memory Interrupt Enable Set/Reset 1 Buffer 19" "No interrupt,Interrupt"
setclrfld.long 0x00 18. 0x00 18. 0x04 18. " [18] ,Transfer to System Memory Interrupt Enable Set/Reset 1 Buffer 18" "No interrupt,Interrupt"
setclrfld.long 0x00 17. 0x00 17. 0x04 17. " [17] ,Transfer to System Memory Interrupt Enable Set/Reset 1 Buffer 17" "No interrupt,Interrupt"
setclrfld.long 0x00 16. 0x00 16. 0x04 16. " [16] ,Transfer to System Memory Interrupt Enable Set/Reset 1 Buffer 16" "No interrupt,Interrupt"
textline " "
setclrfld.long 0x00 15. 0x00 15. 0x04 15. " [15] ,Transfer to System Memory Interrupt Enable Set/Reset 1 Buffer 15" "No interrupt,Interrupt"
setclrfld.long 0x00 14. 0x00 14. 0x04 14. " [14] ,Transfer to System Memory Interrupt Enable Set/Reset 1 Buffer 14" "No interrupt,Interrupt"
setclrfld.long 0x00 13. 0x00 13. 0x04 13. " [13] ,Transfer to System Memory Interrupt Enable Set/Reset 1 Buffer 13" "No interrupt,Interrupt"
setclrfld.long 0x00 12. 0x00 12. 0x04 12. " [12] ,Transfer to System Memory Interrupt Enable Set/Reset 1 Buffer 12" "No interrupt,Interrupt"
textline " "
setclrfld.long 0x00 11. 0x00 11. 0x04 11. " [11] ,Transfer to System Memory Interrupt Enable Set/Reset 1 Buffer 11" "No interrupt,Interrupt"
setclrfld.long 0x00 10. 0x00 10. 0x04 10. " [10] ,Transfer to System Memory Interrupt Enable Set/Reset 1 Buffer 10" "No interrupt,Interrupt"
setclrfld.long 0x00 9. 0x00 9. 0x04 9. " [9] ,Transfer to System Memory Interrupt Enable Set/Reset 1 Buffer 9" "No interrupt,Interrupt"
setclrfld.long 0x00 8. 0x00 8. 0x04 8. " [8] ,Transfer to System Memory Interrupt Enable Set/Reset 1 Buffer 8" "No interrupt,Interrupt"
textline " "
setclrfld.long 0x00 7. 0x00 7. 0x04 7. " [7] ,Transfer to System Memory Interrupt Enable Set/Reset 1 Buffer 7" "No interrupt,Interrupt"
setclrfld.long 0x00 6. 0x00 6. 0x04 6. " [6] ,Transfer to System Memory Interrupt Enable Set/Reset 1 Buffer 6" "No interrupt,Interrupt"
setclrfld.long 0x00 5. 0x00 5. 0x04 5. " [5] ,Transfer to System Memory Interrupt Enable Set/Reset 1 Buffer 5" "No interrupt,Interrupt"
setclrfld.long 0x00 4. 0x00 4. 0x04 4. " [4] ,Transfer to System Memory Interrupt Enable Set/Reset 1 Buffer 4" "No interrupt,Interrupt"
textline " "
setclrfld.long 0x00 3. 0x00 3. 0x04 3. " [3] ,Transfer to System Memory Interrupt Enable Set/Reset 1 Buffer 3" "No interrupt,Interrupt"
setclrfld.long 0x00 2. 0x00 2. 0x04 2. " [2] ,Transfer to System Memory Interrupt Enable Set/Reset 1 Buffer 2" "No interrupt,Interrupt"
setclrfld.long 0x00 1. 0x00 1. 0x04 1. " [1] ,Transfer to System Memory Interrupt Enable Set/Reset 1 Buffer 1" "No interrupt,Interrupt"
setclrfld.long 0x00 0. 0x00 0. 0x04 0. " [0] ,Transfer to System Memory Interrupt Enable Set/Reset 1 Buffer 0" "No interrupt,Interrupt"
group.long 0x108++0x3
line.long 0x0 "TSMIES/R2,Transfer to System Memory Interrupt Enable Set/Reset 2"
setclrfld.long 0x00 31. 0x00 31. 0x04 31. " TSMIES/R2_set/clr [31] ,Transfer to System Memory Interrupt Enable Set/Reset 2 Buffer 63" "No interrupt,Interrupt"
setclrfld.long 0x00 30. 0x00 30. 0x04 30. " [30] ,Transfer to System Memory Interrupt Enable Set/Reset 2 Buffer 62" "No interrupt,Interrupt"
setclrfld.long 0x00 29. 0x00 29. 0x04 29. " [29] ,Transfer to System Memory Interrupt Enable Set/Reset 2 Buffer 61" "No interrupt,Interrupt"
setclrfld.long 0x00 28. 0x00 28. 0x04 28. " [28] ,Transfer to System Memory Interrupt Enable Set/Reset 2 Buffer 60" "No interrupt,Interrupt"
textline " "
setclrfld.long 0x00 27. 0x00 27. 0x04 27. " [27] ,Transfer to System Memory Interrupt Enable Set/Reset 2 Buffer 59" "No interrupt,Interrupt"
setclrfld.long 0x00 26. 0x00 26. 0x04 26. " [26] ,Transfer to System Memory Interrupt Enable Set/Reset 2 Buffer 58" "No interrupt,Interrupt"
setclrfld.long 0x00 25. 0x00 25. 0x04 25. " [25] ,Transfer to System Memory Interrupt Enable Set/Reset 2 Buffer 57" "No interrupt,Interrupt"
setclrfld.long 0x00 24. 0x00 24. 0x04 24. " [24] ,Transfer to System Memory Interrupt Enable Set/Reset 2 Buffer 56" "No interrupt,Interrupt"
textline " "
setclrfld.long 0x00 23. 0x00 23. 0x04 23. " [23] ,Transfer to System Memory Interrupt Enable Set/Reset 2 Buffer 55" "No interrupt,Interrupt"
setclrfld.long 0x00 22. 0x00 22. 0x04 22. " [22] ,Transfer to System Memory Interrupt Enable Set/Reset 2 Buffer 54" "No interrupt,Interrupt"
setclrfld.long 0x00 21. 0x00 21. 0x04 21. " [21] ,Transfer to System Memory Interrupt Enable Set/Reset 2 Buffer 53" "No interrupt,Interrupt"
setclrfld.long 0x00 20. 0x00 20. 0x04 20. " [20] ,Transfer to System Memory Interrupt Enable Set/Reset 2 Buffer 52" "No interrupt,Interrupt"
textline " "
setclrfld.long 0x00 19. 0x00 19. 0x04 19. " [19] ,Transfer to System Memory Interrupt Enable Set/Reset 2 Buffer 51" "No interrupt,Interrupt"
setclrfld.long 0x00 18. 0x00 18. 0x04 18. " [18] ,Transfer to System Memory Interrupt Enable Set/Reset 2 Buffer 50" "No interrupt,Interrupt"
setclrfld.long 0x00 17. 0x00 17. 0x04 17. " [17] ,Transfer to System Memory Interrupt Enable Set/Reset 2 Buffer 49" "No interrupt,Interrupt"
setclrfld.long 0x00 16. 0x00 16. 0x04 16. " [16] ,Transfer to System Memory Interrupt Enable Set/Reset 2 Buffer 48" "No interrupt,Interrupt"
textline " "
setclrfld.long 0x00 15. 0x00 15. 0x04 15. " [15] ,Transfer to System Memory Interrupt Enable Set/Reset 2 Buffer 47" "No interrupt,Interrupt"
setclrfld.long 0x00 14. 0x00 14. 0x04 14. " [14] ,Transfer to System Memory Interrupt Enable Set/Reset 2 Buffer 46" "No interrupt,Interrupt"
setclrfld.long 0x00 13. 0x00 13. 0x04 13. " [13] ,Transfer to System Memory Interrupt Enable Set/Reset 2 Buffer 45" "No interrupt,Interrupt"
setclrfld.long 0x00 12. 0x00 12. 0x04 12. " [12] ,Transfer to System Memory Interrupt Enable Set/Reset 2 Buffer 44" "No interrupt,Interrupt"
textline " "
setclrfld.long 0x00 11. 0x00 11. 0x04 11. " [11] ,Transfer to System Memory Interrupt Enable Set/Reset 2 Buffer 43" "No interrupt,Interrupt"
setclrfld.long 0x00 10. 0x00 10. 0x04 10. " [10] ,Transfer to System Memory Interrupt Enable Set/Reset 2 Buffer 42" "No interrupt,Interrupt"
setclrfld.long 0x00 9. 0x00 9. 0x04 9. " [9] ,Transfer to System Memory Interrupt Enable Set/Reset 2 Buffer 41" "No interrupt,Interrupt"
setclrfld.long 0x00 8. 0x00 8. 0x04 8. " [8] ,Transfer to System Memory Interrupt Enable Set/Reset 2 Buffer 40" "No interrupt,Interrupt"
textline " "
setclrfld.long 0x00 7. 0x00 7. 0x04 7. " [7] ,Transfer to System Memory Interrupt Enable Set/Reset 2 Buffer 39" "No interrupt,Interrupt"
setclrfld.long 0x00 6. 0x00 6. 0x04 6. " [6] ,Transfer to System Memory Interrupt Enable Set/Reset 2 Buffer 38" "No interrupt,Interrupt"
setclrfld.long 0x00 5. 0x00 5. 0x04 5. " [5] ,Transfer to System Memory Interrupt Enable Set/Reset 2 Buffer 37" "No interrupt,Interrupt"
setclrfld.long 0x00 4. 0x00 4. 0x04 4. " [4] ,Transfer to System Memory Interrupt Enable Set/Reset 2 Buffer 36" "No interrupt,Interrupt"
textline " "
setclrfld.long 0x00 3. 0x00 3. 0x04 3. " [3] ,Transfer to System Memory Interrupt Enable Set/Reset 2 Buffer 35" "No interrupt,Interrupt"
setclrfld.long 0x00 2. 0x00 2. 0x04 2. " [2] ,Transfer to System Memory Interrupt Enable Set/Reset 2 Buffer 34" "No interrupt,Interrupt"
setclrfld.long 0x00 1. 0x00 1. 0x04 1. " [1] ,Transfer to System Memory Interrupt Enable Set/Reset 2 Buffer 33" "No interrupt,Interrupt"
setclrfld.long 0x00 0. 0x00 0. 0x04 0. " [0] ,Transfer to System Memory Interrupt Enable Set/Reset 2 Buffer 32" "No interrupt,Interrupt"
group.long 0x110++0x3
line.long 0x0 "TSMIES/R3,Transfer to System Memory Interrupt Enable Set/Reset 3"
setclrfld.long 0x00 31. 0x00 31. 0x04 31. " TSMIES/R3_set/clr [31] ,Transfer to System Memory Interrupt Enable Set/Reset 3 Buffer 95" "No interrupt,Interrupt"
setclrfld.long 0x00 30. 0x00 30. 0x04 30. " [30] ,Transfer to System Memory Interrupt Enable Set/Reset 3 Buffer 94" "No interrupt,Interrupt"
setclrfld.long 0x00 29. 0x00 29. 0x04 29. " [29] ,Transfer to System Memory Interrupt Enable Set/Reset 3 Buffer 93" "No interrupt,Interrupt"
setclrfld.long 0x00 28. 0x00 28. 0x04 28. " [28] ,Transfer to System Memory Interrupt Enable Set/Reset 3 Buffer 92" "No interrupt,Interrupt"
textline " "
setclrfld.long 0x00 27. 0x00 27. 0x04 27. " [27] ,Transfer to System Memory Interrupt Enable Set/Reset 3 Buffer 91" "No interrupt,Interrupt"
setclrfld.long 0x00 26. 0x00 26. 0x04 26. " [26] ,Transfer to System Memory Interrupt Enable Set/Reset 3 Buffer 90" "No interrupt,Interrupt"
setclrfld.long 0x00 25. 0x00 25. 0x04 25. " [25] ,Transfer to System Memory Interrupt Enable Set/Reset 3 Buffer 89" "No interrupt,Interrupt"
setclrfld.long 0x00 24. 0x00 24. 0x04 24. " [24] ,Transfer to System Memory Interrupt Enable Set/Reset 3 Buffer 88" "No interrupt,Interrupt"
textline " "
setclrfld.long 0x00 23. 0x00 23. 0x04 23. " [23] ,Transfer to System Memory Interrupt Enable Set/Reset 3 Buffer 87" "No interrupt,Interrupt"
setclrfld.long 0x00 22. 0x00 22. 0x04 22. " [22] ,Transfer to System Memory Interrupt Enable Set/Reset 3 Buffer 86" "No interrupt,Interrupt"
setclrfld.long 0x00 21. 0x00 21. 0x04 21. " [21] ,Transfer to System Memory Interrupt Enable Set/Reset 3 Buffer 85" "No interrupt,Interrupt"
setclrfld.long 0x00 20. 0x00 20. 0x04 20. " [20] ,Transfer to System Memory Interrupt Enable Set/Reset 3 Buffer 84" "No interrupt,Interrupt"
textline " "
setclrfld.long 0x00 19. 0x00 19. 0x04 19. " [19] ,Transfer to System Memory Interrupt Enable Set/Reset 3 Buffer 83" "No interrupt,Interrupt"
setclrfld.long 0x00 18. 0x00 18. 0x04 18. " [18] ,Transfer to System Memory Interrupt Enable Set/Reset 3 Buffer 82" "No interrupt,Interrupt"
setclrfld.long 0x00 17. 0x00 17. 0x04 17. " [17] ,Transfer to System Memory Interrupt Enable Set/Reset 3 Buffer 81" "No interrupt,Interrupt"
setclrfld.long 0x00 16. 0x00 16. 0x04 16. " [16] ,Transfer to System Memory Interrupt Enable Set/Reset 3 Buffer 80" "No interrupt,Interrupt"
textline " "
setclrfld.long 0x00 15. 0x00 15. 0x04 15. " [15] ,Transfer to System Memory Interrupt Enable Set/Reset 3 Buffer 79" "No interrupt,Interrupt"
setclrfld.long 0x00 14. 0x00 14. 0x04 14. " [14] ,Transfer to System Memory Interrupt Enable Set/Reset 3 Buffer 78" "No interrupt,Interrupt"
setclrfld.long 0x00 13. 0x00 13. 0x04 13. " [13] ,Transfer to System Memory Interrupt Enable Set/Reset 3 Buffer 77" "No interrupt,Interrupt"
setclrfld.long 0x00 12. 0x00 12. 0x04 12. " [12] ,Transfer to System Memory Interrupt Enable Set/Reset 3 Buffer 76" "No interrupt,Interrupt"
textline " "
setclrfld.long 0x00 11. 0x00 11. 0x04 11. " [11] ,Transfer to System Memory Interrupt Enable Set/Reset 3 Buffer 75" "No interrupt,Interrupt"
setclrfld.long 0x00 10. 0x00 10. 0x04 10. " [10] ,Transfer to System Memory Interrupt Enable Set/Reset 3 Buffer 74" "No interrupt,Interrupt"
setclrfld.long 0x00 9. 0x00 9. 0x04 9. " [9] ,Transfer to System Memory Interrupt Enable Set/Reset 3 Buffer 73" "No interrupt,Interrupt"
setclrfld.long 0x00 8. 0x00 8. 0x04 8. " [8] ,Transfer to System Memory Interrupt Enable Set/Reset 3 Buffer 72" "No interrupt,Interrupt"
textline " "
setclrfld.long 0x00 7. 0x00 7. 0x04 7. " [7] ,Transfer to System Memory Interrupt Enable Set/Reset 3 Buffer 71" "No interrupt,Interrupt"
setclrfld.long 0x00 6. 0x00 6. 0x04 6. " [6] ,Transfer to System Memory Interrupt Enable Set/Reset 3 Buffer 70" "No interrupt,Interrupt"
setclrfld.long 0x00 5. 0x00 5. 0x04 5. " [5] ,Transfer to System Memory Interrupt Enable Set/Reset 3 Buffer 69" "No interrupt,Interrupt"
setclrfld.long 0x00 4. 0x00 4. 0x04 4. " [4] ,Transfer to System Memory Interrupt Enable Set/Reset 3 Buffer 68" "No interrupt,Interrupt"
textline " "
setclrfld.long 0x00 3. 0x00 3. 0x04 3. " [3] ,Transfer to System Memory Interrupt Enable Set/Reset 3 Buffer 67" "No interrupt,Interrupt"
setclrfld.long 0x00 2. 0x00 2. 0x04 2. " [2] ,Transfer to System Memory Interrupt Enable Set/Reset 3 Buffer 66" "No interrupt,Interrupt"
setclrfld.long 0x00 1. 0x00 1. 0x04 1. " [1] ,Transfer to System Memory Interrupt Enable Set/Reset 3 Buffer 65" "No interrupt,Interrupt"
setclrfld.long 0x00 0. 0x00 0. 0x04 0. " [0] ,Transfer to System Memory Interrupt Enable Set/Reset 3 Buffer 64" "No interrupt,Interrupt"
group.long 0x118++0x3
line.long 0x0 "TSMIES/R4,Transfer to System Memory Interrupt Enable Set/Reset 4"
setclrfld.long 0x00 31. 0x00 31. 0x04 31. " TSMIES/R4_set/clr [31] ,Transfer to System Memory Interrupt Enable Set/Reset 4 Buffer 127" "No interrupt,Interrupt"
setclrfld.long 0x00 30. 0x00 30. 0x04 30. " [30] ,Transfer to System Memory Interrupt Enable Set/Reset 4 Buffer 126" "No interrupt,Interrupt"
setclrfld.long 0x00 29. 0x00 29. 0x04 29. " [29] ,Transfer to System Memory Interrupt Enable Set/Reset 4 Buffer 125" "No interrupt,Interrupt"
setclrfld.long 0x00 28. 0x00 28. 0x04 28. " [28] ,Transfer to System Memory Interrupt Enable Set/Reset 4 Buffer 124" "No interrupt,Interrupt"
textline " "
setclrfld.long 0x00 27. 0x00 27. 0x04 27. " [27] ,Transfer to System Memory Interrupt Enable Set/Reset 4 Buffer 123" "No interrupt,Interrupt"
setclrfld.long 0x00 26. 0x00 26. 0x04 26. " [26] ,Transfer to System Memory Interrupt Enable Set/Reset 4 Buffer 122" "No interrupt,Interrupt"
setclrfld.long 0x00 25. 0x00 25. 0x04 25. " [25] ,Transfer to System Memory Interrupt Enable Set/Reset 4 Buffer 121" "No interrupt,Interrupt"
setclrfld.long 0x00 24. 0x00 24. 0x04 24. " [24] ,Transfer to System Memory Interrupt Enable Set/Reset 4 Buffer 120" "No interrupt,Interrupt"
textline " "
setclrfld.long 0x00 23. 0x00 23. 0x04 23. " [23] ,Transfer to System Memory Interrupt Enable Set/Reset 4 Buffer 119" "No interrupt,Interrupt"
setclrfld.long 0x00 22. 0x00 22. 0x04 22. " [22] ,Transfer to System Memory Interrupt Enable Set/Reset 4 Buffer 118" "No interrupt,Interrupt"
setclrfld.long 0x00 21. 0x00 21. 0x04 21. " [21] ,Transfer to System Memory Interrupt Enable Set/Reset 4 Buffer 117" "No interrupt,Interrupt"
setclrfld.long 0x00 20. 0x00 20. 0x04 20. " [20] ,Transfer to System Memory Interrupt Enable Set/Reset 4 Buffer 116" "No interrupt,Interrupt"
textline " "
setclrfld.long 0x00 19. 0x00 19. 0x04 19. " [19] ,Transfer to System Memory Interrupt Enable Set/Reset 4 Buffer 115" "No interrupt,Interrupt"
setclrfld.long 0x00 18. 0x00 18. 0x04 18. " [18] ,Transfer to System Memory Interrupt Enable Set/Reset 4 Buffer 114" "No interrupt,Interrupt"
setclrfld.long 0x00 17. 0x00 17. 0x04 17. " [17] ,Transfer to System Memory Interrupt Enable Set/Reset 4 Buffer 113" "No interrupt,Interrupt"
setclrfld.long 0x00 16. 0x00 16. 0x04 16. " [16] ,Transfer to System Memory Interrupt Enable Set/Reset 4 Buffer 112" "No interrupt,Interrupt"
textline " "
setclrfld.long 0x00 15. 0x00 15. 0x04 15. " [15] ,Transfer to System Memory Interrupt Enable Set/Reset 4 Buffer 111" "No interrupt,Interrupt"
setclrfld.long 0x00 14. 0x00 14. 0x04 14. " [14] ,Transfer to System Memory Interrupt Enable Set/Reset 4 Buffer 110" "No interrupt,Interrupt"
setclrfld.long 0x00 13. 0x00 13. 0x04 13. " [13] ,Transfer to System Memory Interrupt Enable Set/Reset 4 Buffer 109" "No interrupt,Interrupt"
setclrfld.long 0x00 12. 0x00 12. 0x04 12. " [12] ,Transfer to System Memory Interrupt Enable Set/Reset 4 Buffer 108" "No interrupt,Interrupt"
textline " "
setclrfld.long 0x00 11. 0x00 11. 0x04 11. " [11] ,Transfer to System Memory Interrupt Enable Set/Reset 4 Buffer 107" "No interrupt,Interrupt"
setclrfld.long 0x00 10. 0x00 10. 0x04 10. " [10] ,Transfer to System Memory Interrupt Enable Set/Reset 4 Buffer 106" "No interrupt,Interrupt"
setclrfld.long 0x00 9. 0x00 9. 0x04 9. " [9] ,Transfer to System Memory Interrupt Enable Set/Reset 4 Buffer 105" "No interrupt,Interrupt"
setclrfld.long 0x00 8. 0x00 8. 0x04 8. " [8] ,Transfer to System Memory Interrupt Enable Set/Reset 4 Buffer 104" "No interrupt,Interrupt"
textline " "
setclrfld.long 0x00 7. 0x00 7. 0x04 7. " [7] ,Transfer to System Memory Interrupt Enable Set/Reset 4 Buffer 103" "No interrupt,Interrupt"
setclrfld.long 0x00 6. 0x00 6. 0x04 6. " [6] ,Transfer to System Memory Interrupt Enable Set/Reset 4 Buffer 102" "No interrupt,Interrupt"
setclrfld.long 0x00 5. 0x00 5. 0x04 5. " [5] ,Transfer to System Memory Interrupt Enable Set/Reset 4 Buffer 101" "No interrupt,Interrupt"
setclrfld.long 0x00 4. 0x00 4. 0x04 4. " [4] ,Transfer to System Memory Interrupt Enable Set/Reset 4 Buffer 100" "No interrupt,Interrupt"
textline " "
setclrfld.long 0x00 3. 0x00 3. 0x04 3. " [3] ,Transfer to System Memory Interrupt Enable Set/Reset 4 Buffer 99" "No interrupt,Interrupt"
setclrfld.long 0x00 2. 0x00 2. 0x04 2. " [2] ,Transfer to System Memory Interrupt Enable Set/Reset 4 Buffer 98" "No interrupt,Interrupt"
setclrfld.long 0x00 1. 0x00 1. 0x04 1. " [1] ,Transfer to System Memory Interrupt Enable Set/Reset 4 Buffer 97" "No interrupt,Interrupt"
setclrfld.long 0x00 0. 0x00 0. 0x04 0. " [0] ,Transfer to System Memory Interrupt Enable Set/Reset 4 Buffer 96" "No interrupt,Interrupt"
group.long 0x120++0x3
line.long 0x0 "TCCIES/R1,Transfer to Communication Controller Interrupt Enable Set/Reset 1"
setclrfld.long 0x00 31. 0x00 31. 0x04 31. " TCCIES/R1_set/clr [31] ,Transfer to Communication Controller Interrupt Enable Set/Reset 1 Buffer 31" "No interrupt,Interrupt"
setclrfld.long 0x00 30. 0x00 30. 0x04 30. " [30] ,Transfer to Communication Controller Interrupt Enable Set/Reset 1 Buffer 30" "No interrupt,Interrupt"
setclrfld.long 0x00 29. 0x00 29. 0x04 29. " [29] ,Transfer to Communication Controller Interrupt Enable Set/Reset 1 Buffer 29" "No interrupt,Interrupt"
setclrfld.long 0x00 28. 0x00 28. 0x04 28. " [28] ,Transfer to Communication Controller Interrupt Enable Set/Reset 1 Buffer 28" "No interrupt,Interrupt"
textline " "
setclrfld.long 0x00 27. 0x00 27. 0x04 27. " [27] ,Transfer to Communication Controller Interrupt Enable Set/Reset 1 Buffer 27" "No interrupt,Interrupt"
setclrfld.long 0x00 26. 0x00 26. 0x04 26. " [26] ,Transfer to Communication Controller Interrupt Enable Set/Reset 1 Buffer 26" "No interrupt,Interrupt"
setclrfld.long 0x00 25. 0x00 25. 0x04 25. " [25] ,Transfer to Communication Controller Interrupt Enable Set/Reset 1 Buffer 25" "No interrupt,Interrupt"
setclrfld.long 0x00 24. 0x00 24. 0x04 24. " [24] ,Transfer to Communication Controller Interrupt Enable Set/Reset 1 Buffer 24" "No interrupt,Interrupt"
textline " "
setclrfld.long 0x00 23. 0x00 23. 0x04 23. " [23] ,Transfer to Communication Controller Interrupt Enable Set/Reset 1 Buffer 23" "No interrupt,Interrupt"
setclrfld.long 0x00 22. 0x00 22. 0x04 22. " [22] ,Transfer to Communication Controller Interrupt Enable Set/Reset 1 Buffer 22" "No interrupt,Interrupt"
setclrfld.long 0x00 21. 0x00 21. 0x04 21. " [21] ,Transfer to Communication Controller Interrupt Enable Set/Reset 1 Buffer 21" "No interrupt,Interrupt"
setclrfld.long 0x00 20. 0x00 20. 0x04 20. " [20] ,Transfer to Communication Controller Interrupt Enable Set/Reset 1 Buffer 20" "No interrupt,Interrupt"
textline " "
setclrfld.long 0x00 19. 0x00 19. 0x04 19. " [19] ,Transfer to Communication Controller Interrupt Enable Set/Reset 1 Buffer 19" "No interrupt,Interrupt"
setclrfld.long 0x00 18. 0x00 18. 0x04 18. " [18] ,Transfer to Communication Controller Interrupt Enable Set/Reset 1 Buffer 18" "No interrupt,Interrupt"
setclrfld.long 0x00 17. 0x00 17. 0x04 17. " [17] ,Transfer to Communication Controller Interrupt Enable Set/Reset 1 Buffer 17" "No interrupt,Interrupt"
setclrfld.long 0x00 16. 0x00 16. 0x04 16. " [16] ,Transfer to Communication Controller Interrupt Enable Set/Reset 1 Buffer 16" "No interrupt,Interrupt"
textline " "
setclrfld.long 0x00 15. 0x00 15. 0x04 15. " [15] ,Transfer to Communication Controller Interrupt Enable Set/Reset 1 Buffer 15" "No interrupt,Interrupt"
setclrfld.long 0x00 14. 0x00 14. 0x04 14. " [14] ,Transfer to Communication Controller Interrupt Enable Set/Reset 1 Buffer 14" "No interrupt,Interrupt"
setclrfld.long 0x00 13. 0x00 13. 0x04 13. " [13] ,Transfer to Communication Controller Interrupt Enable Set/Reset 1 Buffer 13" "No interrupt,Interrupt"
setclrfld.long 0x00 12. 0x00 12. 0x04 12. " [12] ,Transfer to Communication Controller Interrupt Enable Set/Reset 1 Buffer 12" "No interrupt,Interrupt"
textline " "
setclrfld.long 0x00 11. 0x00 11. 0x04 11. " [11] ,Transfer to Communication Controller Interrupt Enable Set/Reset 1 Buffer 11" "No interrupt,Interrupt"
setclrfld.long 0x00 10. 0x00 10. 0x04 10. " [10] ,Transfer to Communication Controller Interrupt Enable Set/Reset 1 Buffer 10" "No interrupt,Interrupt"
setclrfld.long 0x00 9. 0x00 9. 0x04 9. " [9] ,Transfer to Communication Controller Interrupt Enable Set/Reset 1 Buffer 9" "No interrupt,Interrupt"
setclrfld.long 0x00 8. 0x00 8. 0x04 8. " [8] ,Transfer to Communication Controller Interrupt Enable Set/Reset 1 Buffer 8" "No interrupt,Interrupt"
textline " "
setclrfld.long 0x00 7. 0x00 7. 0x04 7. " [7] ,Transfer to Communication Controller Interrupt Enable Set/Reset 1 Buffer 7" "No interrupt,Interrupt"
setclrfld.long 0x00 6. 0x00 6. 0x04 6. " [6] ,Transfer to Communication Controller Interrupt Enable Set/Reset 1 Buffer 6" "No interrupt,Interrupt"
setclrfld.long 0x00 5. 0x00 5. 0x04 5. " [5] ,Transfer to Communication Controller Interrupt Enable Set/Reset 1 Buffer 5" "No interrupt,Interrupt"
setclrfld.long 0x00 4. 0x00 4. 0x04 4. " [4] ,Transfer to Communication Controller Interrupt Enable Set/Reset 1 Buffer 4" "No interrupt,Interrupt"
textline " "
setclrfld.long 0x00 3. 0x00 3. 0x04 3. " [3] ,Transfer to Communication Controller Interrupt Enable Set/Reset 1 Buffer 3" "No interrupt,Interrupt"
setclrfld.long 0x00 2. 0x00 2. 0x04 2. " [2] ,Transfer to Communication Controller Interrupt Enable Set/Reset 1 Buffer 2" "No interrupt,Interrupt"
setclrfld.long 0x00 1. 0x00 1. 0x04 1. " [1] ,Transfer to Communication Controller Interrupt Enable Set/Reset 1 Buffer 1" "No interrupt,Interrupt"
setclrfld.long 0x00 0. 0x00 0. 0x04 0. " [0] ,Transfer to Communication Controller Interrupt Enable Set/Reset 1 Buffer 0" "No interrupt,Interrupt"
group.long 0x128++0x3
line.long 0x0 "TCCIES/R2,Transfer to Communication Controller Interrupt Enable Set/Reset 2"
setclrfld.long 0x00 31. 0x00 31. 0x04 31. " TCCIES/R2_set/clr [31] ,Transfer to Communication Controller Interrupt Enable Set/Reset 2 Buffer 63" "No interrupt,Interrupt"
setclrfld.long 0x00 30. 0x00 30. 0x04 30. " [30] ,Transfer to Communication Controller Interrupt Enable Set/Reset 2 Buffer 62" "No interrupt,Interrupt"
setclrfld.long 0x00 29. 0x00 29. 0x04 29. " [29] ,Transfer to Communication Controller Interrupt Enable Set/Reset 2 Buffer 61" "No interrupt,Interrupt"
setclrfld.long 0x00 28. 0x00 28. 0x04 28. " [28] ,Transfer to Communication Controller Interrupt Enable Set/Reset 2 Buffer 60" "No interrupt,Interrupt"
textline " "
setclrfld.long 0x00 27. 0x00 27. 0x04 27. " [27] ,Transfer to Communication Controller Interrupt Enable Set/Reset 2 Buffer 59" "No interrupt,Interrupt"
setclrfld.long 0x00 26. 0x00 26. 0x04 26. " [26] ,Transfer to Communication Controller Interrupt Enable Set/Reset 2 Buffer 58" "No interrupt,Interrupt"
setclrfld.long 0x00 25. 0x00 25. 0x04 25. " [25] ,Transfer to Communication Controller Interrupt Enable Set/Reset 2 Buffer 57" "No interrupt,Interrupt"
setclrfld.long 0x00 24. 0x00 24. 0x04 24. " [24] ,Transfer to Communication Controller Interrupt Enable Set/Reset 2 Buffer 56" "No interrupt,Interrupt"
textline " "
setclrfld.long 0x00 23. 0x00 23. 0x04 23. " [23] ,Transfer to Communication Controller Interrupt Enable Set/Reset 2 Buffer 55" "No interrupt,Interrupt"
setclrfld.long 0x00 22. 0x00 22. 0x04 22. " [22] ,Transfer to Communication Controller Interrupt Enable Set/Reset 2 Buffer 54" "No interrupt,Interrupt"
setclrfld.long 0x00 21. 0x00 21. 0x04 21. " [21] ,Transfer to Communication Controller Interrupt Enable Set/Reset 2 Buffer 53" "No interrupt,Interrupt"
setclrfld.long 0x00 20. 0x00 20. 0x04 20. " [20] ,Transfer to Communication Controller Interrupt Enable Set/Reset 2 Buffer 52" "No interrupt,Interrupt"
textline " "
setclrfld.long 0x00 19. 0x00 19. 0x04 19. " [19] ,Transfer to Communication Controller Interrupt Enable Set/Reset 2 Buffer 51" "No interrupt,Interrupt"
setclrfld.long 0x00 18. 0x00 18. 0x04 18. " [18] ,Transfer to Communication Controller Interrupt Enable Set/Reset 2 Buffer 50" "No interrupt,Interrupt"
setclrfld.long 0x00 17. 0x00 17. 0x04 17. " [17] ,Transfer to Communication Controller Interrupt Enable Set/Reset 2 Buffer 49" "No interrupt,Interrupt"
setclrfld.long 0x00 16. 0x00 16. 0x04 16. " [16] ,Transfer to Communication Controller Interrupt Enable Set/Reset 2 Buffer 48" "No interrupt,Interrupt"
textline " "
setclrfld.long 0x00 15. 0x00 15. 0x04 15. " [15] ,Transfer to Communication Controller Interrupt Enable Set/Reset 2 Buffer 47" "No interrupt,Interrupt"
setclrfld.long 0x00 14. 0x00 14. 0x04 14. " [14] ,Transfer to Communication Controller Interrupt Enable Set/Reset 2 Buffer 46" "No interrupt,Interrupt"
setclrfld.long 0x00 13. 0x00 13. 0x04 13. " [13] ,Transfer to Communication Controller Interrupt Enable Set/Reset 2 Buffer 45" "No interrupt,Interrupt"
setclrfld.long 0x00 12. 0x00 12. 0x04 12. " [12] ,Transfer to Communication Controller Interrupt Enable Set/Reset 2 Buffer 44" "No interrupt,Interrupt"
textline " "
setclrfld.long 0x00 11. 0x00 11. 0x04 11. " [11] ,Transfer to Communication Controller Interrupt Enable Set/Reset 2 Buffer 43" "No interrupt,Interrupt"
setclrfld.long 0x00 10. 0x00 10. 0x04 10. " [10] ,Transfer to Communication Controller Interrupt Enable Set/Reset 2 Buffer 42" "No interrupt,Interrupt"
setclrfld.long 0x00 9. 0x00 9. 0x04 9. " [9] ,Transfer to Communication Controller Interrupt Enable Set/Reset 2 Buffer 41" "No interrupt,Interrupt"
setclrfld.long 0x00 8. 0x00 8. 0x04 8. " [8] ,Transfer to Communication Controller Interrupt Enable Set/Reset 2 Buffer 40" "No interrupt,Interrupt"
textline " "
setclrfld.long 0x00 7. 0x00 7. 0x04 7. " [7] ,Transfer to Communication Controller Interrupt Enable Set/Reset 2 Buffer 39" "No interrupt,Interrupt"
setclrfld.long 0x00 6. 0x00 6. 0x04 6. " [6] ,Transfer to Communication Controller Interrupt Enable Set/Reset 2 Buffer 38" "No interrupt,Interrupt"
setclrfld.long 0x00 5. 0x00 5. 0x04 5. " [5] ,Transfer to Communication Controller Interrupt Enable Set/Reset 2 Buffer 37" "No interrupt,Interrupt"
setclrfld.long 0x00 4. 0x00 4. 0x04 4. " [4] ,Transfer to Communication Controller Interrupt Enable Set/Reset 2 Buffer 36" "No interrupt,Interrupt"
textline " "
setclrfld.long 0x00 3. 0x00 3. 0x04 3. " [3] ,Transfer to Communication Controller Interrupt Enable Set/Reset 2 Buffer 35" "No interrupt,Interrupt"
setclrfld.long 0x00 2. 0x00 2. 0x04 2. " [2] ,Transfer to Communication Controller Interrupt Enable Set/Reset 2 Buffer 34" "No interrupt,Interrupt"
setclrfld.long 0x00 1. 0x00 1. 0x04 1. " [1] ,Transfer to Communication Controller Interrupt Enable Set/Reset 2 Buffer 33" "No interrupt,Interrupt"
setclrfld.long 0x00 0. 0x00 0. 0x04 0. " [0] ,Transfer to Communication Controller Interrupt Enable Set/Reset 2 Buffer 32" "No interrupt,Interrupt"
group.long 0x130++0x3
line.long 0x0 "TCCIES/R3,Transfer to Communication Controller Interrupt Enable Set/Reset 3"
setclrfld.long 0x00 31. 0x00 31. 0x04 31. " TCCIES/R3_set/clr [31] ,Transfer to Communication Controller Interrupt Enable Set/Reset 3 Buffer 95" "No interrupt,Interrupt"
setclrfld.long 0x00 30. 0x00 30. 0x04 30. " [30] ,Transfer to Communication Controller Interrupt Enable Set/Reset 3 Buffer 94" "No interrupt,Interrupt"
setclrfld.long 0x00 29. 0x00 29. 0x04 29. " [29] ,Transfer to Communication Controller Interrupt Enable Set/Reset 3 Buffer 93" "No interrupt,Interrupt"
setclrfld.long 0x00 28. 0x00 28. 0x04 28. " [28] ,Transfer to Communication Controller Interrupt Enable Set/Reset 3 Buffer 92" "No interrupt,Interrupt"
textline " "
setclrfld.long 0x00 27. 0x00 27. 0x04 27. " [27] ,Transfer to Communication Controller Interrupt Enable Set/Reset 3 Buffer 91" "No interrupt,Interrupt"
setclrfld.long 0x00 26. 0x00 26. 0x04 26. " [26] ,Transfer to Communication Controller Interrupt Enable Set/Reset 3 Buffer 90" "No interrupt,Interrupt"
setclrfld.long 0x00 25. 0x00 25. 0x04 25. " [25] ,Transfer to Communication Controller Interrupt Enable Set/Reset 3 Buffer 89" "No interrupt,Interrupt"
setclrfld.long 0x00 24. 0x00 24. 0x04 24. " [24] ,Transfer to Communication Controller Interrupt Enable Set/Reset 3 Buffer 88" "No interrupt,Interrupt"
textline " "
setclrfld.long 0x00 23. 0x00 23. 0x04 23. " [23] ,Transfer to Communication Controller Interrupt Enable Set/Reset 3 Buffer 87" "No interrupt,Interrupt"
setclrfld.long 0x00 22. 0x00 22. 0x04 22. " [22] ,Transfer to Communication Controller Interrupt Enable Set/Reset 3 Buffer 86" "No interrupt,Interrupt"
setclrfld.long 0x00 21. 0x00 21. 0x04 21. " [21] ,Transfer to Communication Controller Interrupt Enable Set/Reset 3 Buffer 85" "No interrupt,Interrupt"
setclrfld.long 0x00 20. 0x00 20. 0x04 20. " [20] ,Transfer to Communication Controller Interrupt Enable Set/Reset 3 Buffer 84" "No interrupt,Interrupt"
textline " "
setclrfld.long 0x00 19. 0x00 19. 0x04 19. " [19] ,Transfer to Communication Controller Interrupt Enable Set/Reset 3 Buffer 83" "No interrupt,Interrupt"
setclrfld.long 0x00 18. 0x00 18. 0x04 18. " [18] ,Transfer to Communication Controller Interrupt Enable Set/Reset 3 Buffer 82" "No interrupt,Interrupt"
setclrfld.long 0x00 17. 0x00 17. 0x04 17. " [17] ,Transfer to Communication Controller Interrupt Enable Set/Reset 3 Buffer 81" "No interrupt,Interrupt"
setclrfld.long 0x00 16. 0x00 16. 0x04 16. " [16] ,Transfer to Communication Controller Interrupt Enable Set/Reset 3 Buffer 80" "No interrupt,Interrupt"
textline " "
setclrfld.long 0x00 15. 0x00 15. 0x04 15. " [15] ,Transfer to Communication Controller Interrupt Enable Set/Reset 3 Buffer 79" "No interrupt,Interrupt"
setclrfld.long 0x00 14. 0x00 14. 0x04 14. " [14] ,Transfer to Communication Controller Interrupt Enable Set/Reset 3 Buffer 78" "No interrupt,Interrupt"
setclrfld.long 0x00 13. 0x00 13. 0x04 13. " [13] ,Transfer to Communication Controller Interrupt Enable Set/Reset 3 Buffer 77" "No interrupt,Interrupt"
setclrfld.long 0x00 12. 0x00 12. 0x04 12. " [12] ,Transfer to Communication Controller Interrupt Enable Set/Reset 3 Buffer 76" "No interrupt,Interrupt"
textline " "
setclrfld.long 0x00 11. 0x00 11. 0x04 11. " [11] ,Transfer to Communication Controller Interrupt Enable Set/Reset 3 Buffer 75" "No interrupt,Interrupt"
setclrfld.long 0x00 10. 0x00 10. 0x04 10. " [10] ,Transfer to Communication Controller Interrupt Enable Set/Reset 3 Buffer 74" "No interrupt,Interrupt"
setclrfld.long 0x00 9. 0x00 9. 0x04 9. " [9] ,Transfer to Communication Controller Interrupt Enable Set/Reset 3 Buffer 73" "No interrupt,Interrupt"
setclrfld.long 0x00 8. 0x00 8. 0x04 8. " [8] ,Transfer to Communication Controller Interrupt Enable Set/Reset 3 Buffer 72" "No interrupt,Interrupt"
textline " "
setclrfld.long 0x00 7. 0x00 7. 0x04 7. " [7] ,Transfer to Communication Controller Interrupt Enable Set/Reset 3 Buffer 71" "No interrupt,Interrupt"
setclrfld.long 0x00 6. 0x00 6. 0x04 6. " [6] ,Transfer to Communication Controller Interrupt Enable Set/Reset 3 Buffer 70" "No interrupt,Interrupt"
setclrfld.long 0x00 5. 0x00 5. 0x04 5. " [5] ,Transfer to Communication Controller Interrupt Enable Set/Reset 3 Buffer 69" "No interrupt,Interrupt"
setclrfld.long 0x00 4. 0x00 4. 0x04 4. " [4] ,Transfer to Communication Controller Interrupt Enable Set/Reset 3 Buffer 68" "No interrupt,Interrupt"
textline " "
setclrfld.long 0x00 3. 0x00 3. 0x04 3. " [3] ,Transfer to Communication Controller Interrupt Enable Set/Reset 3 Buffer 67" "No interrupt,Interrupt"
setclrfld.long 0x00 2. 0x00 2. 0x04 2. " [2] ,Transfer to Communication Controller Interrupt Enable Set/Reset 3 Buffer 66" "No interrupt,Interrupt"
setclrfld.long 0x00 1. 0x00 1. 0x04 1. " [1] ,Transfer to Communication Controller Interrupt Enable Set/Reset 3 Buffer 65" "No interrupt,Interrupt"
setclrfld.long 0x00 0. 0x00 0. 0x04 0. " [0] ,Transfer to Communication Controller Interrupt Enable Set/Reset 3 Buffer 64" "No interrupt,Interrupt"
group.long 0x138++0x3
line.long 0x0 "TCCIES/R4,Transfer to Communication Controller Interrupt Enable Set/Reset 4"
setclrfld.long 0x00 31. 0x00 31. 0x04 31. " TCCIES/R4_set/clr [31] ,Transfer to Communication Controller Interrupt Enable Set/Reset 4 Buffer 127" "No interrupt,Interrupt"
setclrfld.long 0x00 30. 0x00 30. 0x04 30. " [30] ,Transfer to Communication Controller Interrupt Enable Set/Reset 4 Buffer 126" "No interrupt,Interrupt"
setclrfld.long 0x00 29. 0x00 29. 0x04 29. " [29] ,Transfer to Communication Controller Interrupt Enable Set/Reset 4 Buffer 125" "No interrupt,Interrupt"
setclrfld.long 0x00 28. 0x00 28. 0x04 28. " [28] ,Transfer to Communication Controller Interrupt Enable Set/Reset 4 Buffer 124" "No interrupt,Interrupt"
textline " "
setclrfld.long 0x00 27. 0x00 27. 0x04 27. " [27] ,Transfer to Communication Controller Interrupt Enable Set/Reset 4 Buffer 123" "No interrupt,Interrupt"
setclrfld.long 0x00 26. 0x00 26. 0x04 26. " [26] ,Transfer to Communication Controller Interrupt Enable Set/Reset 4 Buffer 122" "No interrupt,Interrupt"
setclrfld.long 0x00 25. 0x00 25. 0x04 25. " [25] ,Transfer to Communication Controller Interrupt Enable Set/Reset 4 Buffer 121" "No interrupt,Interrupt"
setclrfld.long 0x00 24. 0x00 24. 0x04 24. " [24] ,Transfer to Communication Controller Interrupt Enable Set/Reset 4 Buffer 120" "No interrupt,Interrupt"
textline " "
setclrfld.long 0x00 23. 0x00 23. 0x04 23. " [23] ,Transfer to Communication Controller Interrupt Enable Set/Reset 4 Buffer 119" "No interrupt,Interrupt"
setclrfld.long 0x00 22. 0x00 22. 0x04 22. " [22] ,Transfer to Communication Controller Interrupt Enable Set/Reset 4 Buffer 118" "No interrupt,Interrupt"
setclrfld.long 0x00 21. 0x00 21. 0x04 21. " [21] ,Transfer to Communication Controller Interrupt Enable Set/Reset 4 Buffer 117" "No interrupt,Interrupt"
setclrfld.long 0x00 20. 0x00 20. 0x04 20. " [20] ,Transfer to Communication Controller Interrupt Enable Set/Reset 4 Buffer 116" "No interrupt,Interrupt"
textline " "
setclrfld.long 0x00 19. 0x00 19. 0x04 19. " [19] ,Transfer to Communication Controller Interrupt Enable Set/Reset 4 Buffer 115" "No interrupt,Interrupt"
setclrfld.long 0x00 18. 0x00 18. 0x04 18. " [18] ,Transfer to Communication Controller Interrupt Enable Set/Reset 4 Buffer 114" "No interrupt,Interrupt"
setclrfld.long 0x00 17. 0x00 17. 0x04 17. " [17] ,Transfer to Communication Controller Interrupt Enable Set/Reset 4 Buffer 113" "No interrupt,Interrupt"
setclrfld.long 0x00 16. 0x00 16. 0x04 16. " [16] ,Transfer to Communication Controller Interrupt Enable Set/Reset 4 Buffer 112" "No interrupt,Interrupt"
textline " "
setclrfld.long 0x00 15. 0x00 15. 0x04 15. " [15] ,Transfer to Communication Controller Interrupt Enable Set/Reset 4 Buffer 111" "No interrupt,Interrupt"
setclrfld.long 0x00 14. 0x00 14. 0x04 14. " [14] ,Transfer to Communication Controller Interrupt Enable Set/Reset 4 Buffer 110" "No interrupt,Interrupt"
setclrfld.long 0x00 13. 0x00 13. 0x04 13. " [13] ,Transfer to Communication Controller Interrupt Enable Set/Reset 4 Buffer 109" "No interrupt,Interrupt"
setclrfld.long 0x00 12. 0x00 12. 0x04 12. " [12] ,Transfer to Communication Controller Interrupt Enable Set/Reset 4 Buffer 108" "No interrupt,Interrupt"
textline " "
setclrfld.long 0x00 11. 0x00 11. 0x04 11. " [11] ,Transfer to Communication Controller Interrupt Enable Set/Reset 4 Buffer 107" "No interrupt,Interrupt"
setclrfld.long 0x00 10. 0x00 10. 0x04 10. " [10] ,Transfer to Communication Controller Interrupt Enable Set/Reset 4 Buffer 106" "No interrupt,Interrupt"
setclrfld.long 0x00 9. 0x00 9. 0x04 9. " [9] ,Transfer to Communication Controller Interrupt Enable Set/Reset 4 Buffer 105" "No interrupt,Interrupt"
setclrfld.long 0x00 8. 0x00 8. 0x04 8. " [8] ,Transfer to Communication Controller Interrupt Enable Set/Reset 4 Buffer 104" "No interrupt,Interrupt"
textline " "
setclrfld.long 0x00 7. 0x00 7. 0x04 7. " [7] ,Transfer to Communication Controller Interrupt Enable Set/Reset 4 Buffer 103" "No interrupt,Interrupt"
setclrfld.long 0x00 6. 0x00 6. 0x04 6. " [6] ,Transfer to Communication Controller Interrupt Enable Set/Reset 4 Buffer 102" "No interrupt,Interrupt"
setclrfld.long 0x00 5. 0x00 5. 0x04 5. " [5] ,Transfer to Communication Controller Interrupt Enable Set/Reset 4 Buffer 101" "No interrupt,Interrupt"
setclrfld.long 0x00 4. 0x00 4. 0x04 4. " [4] ,Transfer to Communication Controller Interrupt Enable Set/Reset 4 Buffer 100" "No interrupt,Interrupt"
textline " "
setclrfld.long 0x00 3. 0x00 3. 0x04 3. " [3] ,Transfer to Communication Controller Interrupt Enable Set/Reset 4 Buffer 99" "No interrupt,Interrupt"
setclrfld.long 0x00 2. 0x00 2. 0x04 2. " [2] ,Transfer to Communication Controller Interrupt Enable Set/Reset 4 Buffer 98" "No interrupt,Interrupt"
setclrfld.long 0x00 1. 0x00 1. 0x04 1. " [1] ,Transfer to Communication Controller Interrupt Enable Set/Reset 4 Buffer 97" "No interrupt,Interrupt"
setclrfld.long 0x00 0. 0x00 0. 0x04 0. " [0] ,Transfer to Communication Controller Interrupt Enable Set/Reset 4 Buffer 96" "No interrupt,Interrupt"
base ad:0xFF500000
width 9.
tree "TU RAM (Transfer Configuration RAM)"
tree "Normal Mode"
group.long 0x00++0x1ff
line.long 0x0 "TCR0,Transfer Configuration RAM 0"
bitfld.long 0x0 18. " STXR ,Set Transmit Request" "Not set,Set"
bitfld.long 0x0 17. " THTSM ,Transfer Header to System Memory" "No transfer,Transfer"
bitfld.long 0x0 16. " TPTSM ,Transfer Payload to System Memory" "No transfer,Transfer"
textline " "
bitfld.long 0x0 15. " THTCC ,Transfer Header to Communication Controller" "No transfer,Transfer"
bitfld.long 0x0 14. " TPTCC ,Transfer Payload to Communication Controller" "No transfer,Transfer"
hexmask.long.word 0x0 0.--13. 1. " TSO ,Transfer Start Offset"
line.long 0x4 "TCR1,Transfer Configuration RAM 1"
bitfld.long 0x4 18. " STXR ,Set Transmit Request" "Not set,Set"
bitfld.long 0x4 17. " THTSM ,Transfer Header to System Memory" "No transfer,Transfer"
bitfld.long 0x4 16. " TPTSM ,Transfer Payload to System Memory" "No transfer,Transfer"
textline " "
bitfld.long 0x4 15. " THTCC ,Transfer Header to Communication Controller" "No transfer,Transfer"
bitfld.long 0x4 14. " TPTCC ,Transfer Payload to Communication Controller" "No transfer,Transfer"
hexmask.long.word 0x4 0.--13. 1. " TSO ,Transfer Start Offset"
line.long 0x8 "TCR2,Transfer Configuration RAM 2"
bitfld.long 0x8 18. " STXR ,Set Transmit Request" "Not set,Set"
bitfld.long 0x8 17. " THTSM ,Transfer Header to System Memory" "No transfer,Transfer"
bitfld.long 0x8 16. " TPTSM ,Transfer Payload to System Memory" "No transfer,Transfer"
textline " "
bitfld.long 0x8 15. " THTCC ,Transfer Header to Communication Controller" "No transfer,Transfer"
bitfld.long 0x8 14. " TPTCC ,Transfer Payload to Communication Controller" "No transfer,Transfer"
hexmask.long.word 0x8 0.--13. 1. " TSO ,Transfer Start Offset"
line.long 0xC "TCR3,Transfer Configuration RAM 3"
bitfld.long 0xC 18. " STXR ,Set Transmit Request" "Not set,Set"
bitfld.long 0xC 17. " THTSM ,Transfer Header to System Memory" "No transfer,Transfer"
bitfld.long 0xC 16. " TPTSM ,Transfer Payload to System Memory" "No transfer,Transfer"
textline " "
bitfld.long 0xC 15. " THTCC ,Transfer Header to Communication Controller" "No transfer,Transfer"
bitfld.long 0xC 14. " TPTCC ,Transfer Payload to Communication Controller" "No transfer,Transfer"
hexmask.long.word 0xC 0.--13. 1. " TSO ,Transfer Start Offset"
line.long 0x10 "TCR4,Transfer Configuration RAM 4"
bitfld.long 0x10 18. " STXR ,Set Transmit Request" "Not set,Set"
bitfld.long 0x10 17. " THTSM ,Transfer Header to System Memory" "No transfer,Transfer"
bitfld.long 0x10 16. " TPTSM ,Transfer Payload to System Memory" "No transfer,Transfer"
textline " "
bitfld.long 0x10 15. " THTCC ,Transfer Header to Communication Controller" "No transfer,Transfer"
bitfld.long 0x10 14. " TPTCC ,Transfer Payload to Communication Controller" "No transfer,Transfer"
hexmask.long.word 0x10 0.--13. 1. " TSO ,Transfer Start Offset"
line.long 0x14 "TCR5,Transfer Configuration RAM 5"
bitfld.long 0x14 18. " STXR ,Set Transmit Request" "Not set,Set"
bitfld.long 0x14 17. " THTSM ,Transfer Header to System Memory" "No transfer,Transfer"
bitfld.long 0x14 16. " TPTSM ,Transfer Payload to System Memory" "No transfer,Transfer"
textline " "
bitfld.long 0x14 15. " THTCC ,Transfer Header to Communication Controller" "No transfer,Transfer"
bitfld.long 0x14 14. " TPTCC ,Transfer Payload to Communication Controller" "No transfer,Transfer"
hexmask.long.word 0x14 0.--13. 1. " TSO ,Transfer Start Offset"
line.long 0x18 "TCR6,Transfer Configuration RAM 6"
bitfld.long 0x18 18. " STXR ,Set Transmit Request" "Not set,Set"
bitfld.long 0x18 17. " THTSM ,Transfer Header to System Memory" "No transfer,Transfer"
bitfld.long 0x18 16. " TPTSM ,Transfer Payload to System Memory" "No transfer,Transfer"
textline " "
bitfld.long 0x18 15. " THTCC ,Transfer Header to Communication Controller" "No transfer,Transfer"
bitfld.long 0x18 14. " TPTCC ,Transfer Payload to Communication Controller" "No transfer,Transfer"
hexmask.long.word 0x18 0.--13. 1. " TSO ,Transfer Start Offset"
line.long 0x1C "TCR7,Transfer Configuration RAM 7"
bitfld.long 0x1C 18. " STXR ,Set Transmit Request" "Not set,Set"
bitfld.long 0x1C 17. " THTSM ,Transfer Header to System Memory" "No transfer,Transfer"
bitfld.long 0x1C 16. " TPTSM ,Transfer Payload to System Memory" "No transfer,Transfer"
textline " "
bitfld.long 0x1C 15. " THTCC ,Transfer Header to Communication Controller" "No transfer,Transfer"
bitfld.long 0x1C 14. " TPTCC ,Transfer Payload to Communication Controller" "No transfer,Transfer"
hexmask.long.word 0x1C 0.--13. 1. " TSO ,Transfer Start Offset"
line.long 0x20 "TCR8,Transfer Configuration RAM 8"
bitfld.long 0x20 18. " STXR ,Set Transmit Request" "Not set,Set"
bitfld.long 0x20 17. " THTSM ,Transfer Header to System Memory" "No transfer,Transfer"
bitfld.long 0x20 16. " TPTSM ,Transfer Payload to System Memory" "No transfer,Transfer"
textline " "
bitfld.long 0x20 15. " THTCC ,Transfer Header to Communication Controller" "No transfer,Transfer"
bitfld.long 0x20 14. " TPTCC ,Transfer Payload to Communication Controller" "No transfer,Transfer"
hexmask.long.word 0x20 0.--13. 1. " TSO ,Transfer Start Offset"
line.long 0x24 "TCR9,Transfer Configuration RAM 9"
bitfld.long 0x24 18. " STXR ,Set Transmit Request" "Not set,Set"
bitfld.long 0x24 17. " THTSM ,Transfer Header to System Memory" "No transfer,Transfer"
bitfld.long 0x24 16. " TPTSM ,Transfer Payload to System Memory" "No transfer,Transfer"
textline " "
bitfld.long 0x24 15. " THTCC ,Transfer Header to Communication Controller" "No transfer,Transfer"
bitfld.long 0x24 14. " TPTCC ,Transfer Payload to Communication Controller" "No transfer,Transfer"
hexmask.long.word 0x24 0.--13. 1. " TSO ,Transfer Start Offset"
line.long 0x28 "TCR10,Transfer Configuration RAM 10"
bitfld.long 0x28 18. " STXR ,Set Transmit Request" "Not set,Set"
bitfld.long 0x28 17. " THTSM ,Transfer Header to System Memory" "No transfer,Transfer"
bitfld.long 0x28 16. " TPTSM ,Transfer Payload to System Memory" "No transfer,Transfer"
textline " "
bitfld.long 0x28 15. " THTCC ,Transfer Header to Communication Controller" "No transfer,Transfer"
bitfld.long 0x28 14. " TPTCC ,Transfer Payload to Communication Controller" "No transfer,Transfer"
hexmask.long.word 0x28 0.--13. 1. " TSO ,Transfer Start Offset"
line.long 0x2C "TCR11,Transfer Configuration RAM 11"
bitfld.long 0x2C 18. " STXR ,Set Transmit Request" "Not set,Set"
bitfld.long 0x2C 17. " THTSM ,Transfer Header to System Memory" "No transfer,Transfer"
bitfld.long 0x2C 16. " TPTSM ,Transfer Payload to System Memory" "No transfer,Transfer"
textline " "
bitfld.long 0x2C 15. " THTCC ,Transfer Header to Communication Controller" "No transfer,Transfer"
bitfld.long 0x2C 14. " TPTCC ,Transfer Payload to Communication Controller" "No transfer,Transfer"
hexmask.long.word 0x2C 0.--13. 1. " TSO ,Transfer Start Offset"
line.long 0x30 "TCR12,Transfer Configuration RAM 12"
bitfld.long 0x30 18. " STXR ,Set Transmit Request" "Not set,Set"
bitfld.long 0x30 17. " THTSM ,Transfer Header to System Memory" "No transfer,Transfer"
bitfld.long 0x30 16. " TPTSM ,Transfer Payload to System Memory" "No transfer,Transfer"
textline " "
bitfld.long 0x30 15. " THTCC ,Transfer Header to Communication Controller" "No transfer,Transfer"
bitfld.long 0x30 14. " TPTCC ,Transfer Payload to Communication Controller" "No transfer,Transfer"
hexmask.long.word 0x30 0.--13. 1. " TSO ,Transfer Start Offset"
line.long 0x34 "TCR13,Transfer Configuration RAM 13"
bitfld.long 0x34 18. " STXR ,Set Transmit Request" "Not set,Set"
bitfld.long 0x34 17. " THTSM ,Transfer Header to System Memory" "No transfer,Transfer"
bitfld.long 0x34 16. " TPTSM ,Transfer Payload to System Memory" "No transfer,Transfer"
textline " "
bitfld.long 0x34 15. " THTCC ,Transfer Header to Communication Controller" "No transfer,Transfer"
bitfld.long 0x34 14. " TPTCC ,Transfer Payload to Communication Controller" "No transfer,Transfer"
hexmask.long.word 0x34 0.--13. 1. " TSO ,Transfer Start Offset"
line.long 0x38 "TCR14,Transfer Configuration RAM 14"
bitfld.long 0x38 18. " STXR ,Set Transmit Request" "Not set,Set"
bitfld.long 0x38 17. " THTSM ,Transfer Header to System Memory" "No transfer,Transfer"
bitfld.long 0x38 16. " TPTSM ,Transfer Payload to System Memory" "No transfer,Transfer"
textline " "
bitfld.long 0x38 15. " THTCC ,Transfer Header to Communication Controller" "No transfer,Transfer"
bitfld.long 0x38 14. " TPTCC ,Transfer Payload to Communication Controller" "No transfer,Transfer"
hexmask.long.word 0x38 0.--13. 1. " TSO ,Transfer Start Offset"
line.long 0x3C "TCR15,Transfer Configuration RAM 15"
bitfld.long 0x3C 18. " STXR ,Set Transmit Request" "Not set,Set"
bitfld.long 0x3C 17. " THTSM ,Transfer Header to System Memory" "No transfer,Transfer"
bitfld.long 0x3C 16. " TPTSM ,Transfer Payload to System Memory" "No transfer,Transfer"
textline " "
bitfld.long 0x3C 15. " THTCC ,Transfer Header to Communication Controller" "No transfer,Transfer"
bitfld.long 0x3C 14. " TPTCC ,Transfer Payload to Communication Controller" "No transfer,Transfer"
hexmask.long.word 0x3C 0.--13. 1. " TSO ,Transfer Start Offset"
line.long 0x40 "TCR16,Transfer Configuration RAM 16"
bitfld.long 0x40 18. " STXR ,Set Transmit Request" "Not set,Set"
bitfld.long 0x40 17. " THTSM ,Transfer Header to System Memory" "No transfer,Transfer"
bitfld.long 0x40 16. " TPTSM ,Transfer Payload to System Memory" "No transfer,Transfer"
textline " "
bitfld.long 0x40 15. " THTCC ,Transfer Header to Communication Controller" "No transfer,Transfer"
bitfld.long 0x40 14. " TPTCC ,Transfer Payload to Communication Controller" "No transfer,Transfer"
hexmask.long.word 0x40 0.--13. 1. " TSO ,Transfer Start Offset"
line.long 0x44 "TCR17,Transfer Configuration RAM 17"
bitfld.long 0x44 18. " STXR ,Set Transmit Request" "Not set,Set"
bitfld.long 0x44 17. " THTSM ,Transfer Header to System Memory" "No transfer,Transfer"
bitfld.long 0x44 16. " TPTSM ,Transfer Payload to System Memory" "No transfer,Transfer"
textline " "
bitfld.long 0x44 15. " THTCC ,Transfer Header to Communication Controller" "No transfer,Transfer"
bitfld.long 0x44 14. " TPTCC ,Transfer Payload to Communication Controller" "No transfer,Transfer"
hexmask.long.word 0x44 0.--13. 1. " TSO ,Transfer Start Offset"
line.long 0x48 "TCR18,Transfer Configuration RAM 18"
bitfld.long 0x48 18. " STXR ,Set Transmit Request" "Not set,Set"
bitfld.long 0x48 17. " THTSM ,Transfer Header to System Memory" "No transfer,Transfer"
bitfld.long 0x48 16. " TPTSM ,Transfer Payload to System Memory" "No transfer,Transfer"
textline " "
bitfld.long 0x48 15. " THTCC ,Transfer Header to Communication Controller" "No transfer,Transfer"
bitfld.long 0x48 14. " TPTCC ,Transfer Payload to Communication Controller" "No transfer,Transfer"
hexmask.long.word 0x48 0.--13. 1. " TSO ,Transfer Start Offset"
line.long 0x4C "TCR19,Transfer Configuration RAM 19"
bitfld.long 0x4C 18. " STXR ,Set Transmit Request" "Not set,Set"
bitfld.long 0x4C 17. " THTSM ,Transfer Header to System Memory" "No transfer,Transfer"
bitfld.long 0x4C 16. " TPTSM ,Transfer Payload to System Memory" "No transfer,Transfer"
textline " "
bitfld.long 0x4C 15. " THTCC ,Transfer Header to Communication Controller" "No transfer,Transfer"
bitfld.long 0x4C 14. " TPTCC ,Transfer Payload to Communication Controller" "No transfer,Transfer"
hexmask.long.word 0x4C 0.--13. 1. " TSO ,Transfer Start Offset"
line.long 0x50 "TCR20,Transfer Configuration RAM 20"
bitfld.long 0x50 18. " STXR ,Set Transmit Request" "Not set,Set"
bitfld.long 0x50 17. " THTSM ,Transfer Header to System Memory" "No transfer,Transfer"
bitfld.long 0x50 16. " TPTSM ,Transfer Payload to System Memory" "No transfer,Transfer"
textline " "
bitfld.long 0x50 15. " THTCC ,Transfer Header to Communication Controller" "No transfer,Transfer"
bitfld.long 0x50 14. " TPTCC ,Transfer Payload to Communication Controller" "No transfer,Transfer"
hexmask.long.word 0x50 0.--13. 1. " TSO ,Transfer Start Offset"
line.long 0x54 "TCR21,Transfer Configuration RAM 21"
bitfld.long 0x54 18. " STXR ,Set Transmit Request" "Not set,Set"
bitfld.long 0x54 17. " THTSM ,Transfer Header to System Memory" "No transfer,Transfer"
bitfld.long 0x54 16. " TPTSM ,Transfer Payload to System Memory" "No transfer,Transfer"
textline " "
bitfld.long 0x54 15. " THTCC ,Transfer Header to Communication Controller" "No transfer,Transfer"
bitfld.long 0x54 14. " TPTCC ,Transfer Payload to Communication Controller" "No transfer,Transfer"
hexmask.long.word 0x54 0.--13. 1. " TSO ,Transfer Start Offset"
line.long 0x58 "TCR22,Transfer Configuration RAM 22"
bitfld.long 0x58 18. " STXR ,Set Transmit Request" "Not set,Set"
bitfld.long 0x58 17. " THTSM ,Transfer Header to System Memory" "No transfer,Transfer"
bitfld.long 0x58 16. " TPTSM ,Transfer Payload to System Memory" "No transfer,Transfer"
textline " "
bitfld.long 0x58 15. " THTCC ,Transfer Header to Communication Controller" "No transfer,Transfer"
bitfld.long 0x58 14. " TPTCC ,Transfer Payload to Communication Controller" "No transfer,Transfer"
hexmask.long.word 0x58 0.--13. 1. " TSO ,Transfer Start Offset"
line.long 0x5C "TCR23,Transfer Configuration RAM 23"
bitfld.long 0x5C 18. " STXR ,Set Transmit Request" "Not set,Set"
bitfld.long 0x5C 17. " THTSM ,Transfer Header to System Memory" "No transfer,Transfer"
bitfld.long 0x5C 16. " TPTSM ,Transfer Payload to System Memory" "No transfer,Transfer"
textline " "
bitfld.long 0x5C 15. " THTCC ,Transfer Header to Communication Controller" "No transfer,Transfer"
bitfld.long 0x5C 14. " TPTCC ,Transfer Payload to Communication Controller" "No transfer,Transfer"
hexmask.long.word 0x5C 0.--13. 1. " TSO ,Transfer Start Offset"
line.long 0x60 "TCR24,Transfer Configuration RAM 24"
bitfld.long 0x60 18. " STXR ,Set Transmit Request" "Not set,Set"
bitfld.long 0x60 17. " THTSM ,Transfer Header to System Memory" "No transfer,Transfer"
bitfld.long 0x60 16. " TPTSM ,Transfer Payload to System Memory" "No transfer,Transfer"
textline " "
bitfld.long 0x60 15. " THTCC ,Transfer Header to Communication Controller" "No transfer,Transfer"
bitfld.long 0x60 14. " TPTCC ,Transfer Payload to Communication Controller" "No transfer,Transfer"
hexmask.long.word 0x60 0.--13. 1. " TSO ,Transfer Start Offset"
line.long 0x64 "TCR25,Transfer Configuration RAM 25"
bitfld.long 0x64 18. " STXR ,Set Transmit Request" "Not set,Set"
bitfld.long 0x64 17. " THTSM ,Transfer Header to System Memory" "No transfer,Transfer"
bitfld.long 0x64 16. " TPTSM ,Transfer Payload to System Memory" "No transfer,Transfer"
textline " "
bitfld.long 0x64 15. " THTCC ,Transfer Header to Communication Controller" "No transfer,Transfer"
bitfld.long 0x64 14. " TPTCC ,Transfer Payload to Communication Controller" "No transfer,Transfer"
hexmask.long.word 0x64 0.--13. 1. " TSO ,Transfer Start Offset"
line.long 0x68 "TCR26,Transfer Configuration RAM 26"
bitfld.long 0x68 18. " STXR ,Set Transmit Request" "Not set,Set"
bitfld.long 0x68 17. " THTSM ,Transfer Header to System Memory" "No transfer,Transfer"
bitfld.long 0x68 16. " TPTSM ,Transfer Payload to System Memory" "No transfer,Transfer"
textline " "
bitfld.long 0x68 15. " THTCC ,Transfer Header to Communication Controller" "No transfer,Transfer"
bitfld.long 0x68 14. " TPTCC ,Transfer Payload to Communication Controller" "No transfer,Transfer"
hexmask.long.word 0x68 0.--13. 1. " TSO ,Transfer Start Offset"
line.long 0x6C "TCR27,Transfer Configuration RAM 27"
bitfld.long 0x6C 18. " STXR ,Set Transmit Request" "Not set,Set"
bitfld.long 0x6C 17. " THTSM ,Transfer Header to System Memory" "No transfer,Transfer"
bitfld.long 0x6C 16. " TPTSM ,Transfer Payload to System Memory" "No transfer,Transfer"
textline " "
bitfld.long 0x6C 15. " THTCC ,Transfer Header to Communication Controller" "No transfer,Transfer"
bitfld.long 0x6C 14. " TPTCC ,Transfer Payload to Communication Controller" "No transfer,Transfer"
hexmask.long.word 0x6C 0.--13. 1. " TSO ,Transfer Start Offset"
line.long 0x70 "TCR28,Transfer Configuration RAM 28"
bitfld.long 0x70 18. " STXR ,Set Transmit Request" "Not set,Set"
bitfld.long 0x70 17. " THTSM ,Transfer Header to System Memory" "No transfer,Transfer"
bitfld.long 0x70 16. " TPTSM ,Transfer Payload to System Memory" "No transfer,Transfer"
textline " "
bitfld.long 0x70 15. " THTCC ,Transfer Header to Communication Controller" "No transfer,Transfer"
bitfld.long 0x70 14. " TPTCC ,Transfer Payload to Communication Controller" "No transfer,Transfer"
hexmask.long.word 0x70 0.--13. 1. " TSO ,Transfer Start Offset"
line.long 0x74 "TCR29,Transfer Configuration RAM 29"
bitfld.long 0x74 18. " STXR ,Set Transmit Request" "Not set,Set"
bitfld.long 0x74 17. " THTSM ,Transfer Header to System Memory" "No transfer,Transfer"
bitfld.long 0x74 16. " TPTSM ,Transfer Payload to System Memory" "No transfer,Transfer"
textline " "
bitfld.long 0x74 15. " THTCC ,Transfer Header to Communication Controller" "No transfer,Transfer"
bitfld.long 0x74 14. " TPTCC ,Transfer Payload to Communication Controller" "No transfer,Transfer"
hexmask.long.word 0x74 0.--13. 1. " TSO ,Transfer Start Offset"
line.long 0x78 "TCR30,Transfer Configuration RAM 30"
bitfld.long 0x78 18. " STXR ,Set Transmit Request" "Not set,Set"
bitfld.long 0x78 17. " THTSM ,Transfer Header to System Memory" "No transfer,Transfer"
bitfld.long 0x78 16. " TPTSM ,Transfer Payload to System Memory" "No transfer,Transfer"
textline " "
bitfld.long 0x78 15. " THTCC ,Transfer Header to Communication Controller" "No transfer,Transfer"
bitfld.long 0x78 14. " TPTCC ,Transfer Payload to Communication Controller" "No transfer,Transfer"
hexmask.long.word 0x78 0.--13. 1. " TSO ,Transfer Start Offset"
line.long 0x7C "TCR31,Transfer Configuration RAM 31"
bitfld.long 0x7C 18. " STXR ,Set Transmit Request" "Not set,Set"
bitfld.long 0x7C 17. " THTSM ,Transfer Header to System Memory" "No transfer,Transfer"
bitfld.long 0x7C 16. " TPTSM ,Transfer Payload to System Memory" "No transfer,Transfer"
textline " "
bitfld.long 0x7C 15. " THTCC ,Transfer Header to Communication Controller" "No transfer,Transfer"
bitfld.long 0x7C 14. " TPTCC ,Transfer Payload to Communication Controller" "No transfer,Transfer"
hexmask.long.word 0x7C 0.--13. 1. " TSO ,Transfer Start Offset"
line.long 0x80 "TCR32,Transfer Configuration RAM 32"
bitfld.long 0x80 18. " STXR ,Set Transmit Request" "Not set,Set"
bitfld.long 0x80 17. " THTSM ,Transfer Header to System Memory" "No transfer,Transfer"
bitfld.long 0x80 16. " TPTSM ,Transfer Payload to System Memory" "No transfer,Transfer"
textline " "
bitfld.long 0x80 15. " THTCC ,Transfer Header to Communication Controller" "No transfer,Transfer"
bitfld.long 0x80 14. " TPTCC ,Transfer Payload to Communication Controller" "No transfer,Transfer"
hexmask.long.word 0x80 0.--13. 1. " TSO ,Transfer Start Offset"
line.long 0x84 "TCR33,Transfer Configuration RAM 33"
bitfld.long 0x84 18. " STXR ,Set Transmit Request" "Not set,Set"
bitfld.long 0x84 17. " THTSM ,Transfer Header to System Memory" "No transfer,Transfer"
bitfld.long 0x84 16. " TPTSM ,Transfer Payload to System Memory" "No transfer,Transfer"
textline " "
bitfld.long 0x84 15. " THTCC ,Transfer Header to Communication Controller" "No transfer,Transfer"
bitfld.long 0x84 14. " TPTCC ,Transfer Payload to Communication Controller" "No transfer,Transfer"
hexmask.long.word 0x84 0.--13. 1. " TSO ,Transfer Start Offset"
line.long 0x88 "TCR34,Transfer Configuration RAM 34"
bitfld.long 0x88 18. " STXR ,Set Transmit Request" "Not set,Set"
bitfld.long 0x88 17. " THTSM ,Transfer Header to System Memory" "No transfer,Transfer"
bitfld.long 0x88 16. " TPTSM ,Transfer Payload to System Memory" "No transfer,Transfer"
textline " "
bitfld.long 0x88 15. " THTCC ,Transfer Header to Communication Controller" "No transfer,Transfer"
bitfld.long 0x88 14. " TPTCC ,Transfer Payload to Communication Controller" "No transfer,Transfer"
hexmask.long.word 0x88 0.--13. 1. " TSO ,Transfer Start Offset"
line.long 0x8C "TCR35,Transfer Configuration RAM 35"
bitfld.long 0x8C 18. " STXR ,Set Transmit Request" "Not set,Set"
bitfld.long 0x8C 17. " THTSM ,Transfer Header to System Memory" "No transfer,Transfer"
bitfld.long 0x8C 16. " TPTSM ,Transfer Payload to System Memory" "No transfer,Transfer"
textline " "
bitfld.long 0x8C 15. " THTCC ,Transfer Header to Communication Controller" "No transfer,Transfer"
bitfld.long 0x8C 14. " TPTCC ,Transfer Payload to Communication Controller" "No transfer,Transfer"
hexmask.long.word 0x8C 0.--13. 1. " TSO ,Transfer Start Offset"
line.long 0x90 "TCR36,Transfer Configuration RAM 36"
bitfld.long 0x90 18. " STXR ,Set Transmit Request" "Not set,Set"
bitfld.long 0x90 17. " THTSM ,Transfer Header to System Memory" "No transfer,Transfer"
bitfld.long 0x90 16. " TPTSM ,Transfer Payload to System Memory" "No transfer,Transfer"
textline " "
bitfld.long 0x90 15. " THTCC ,Transfer Header to Communication Controller" "No transfer,Transfer"
bitfld.long 0x90 14. " TPTCC ,Transfer Payload to Communication Controller" "No transfer,Transfer"
hexmask.long.word 0x90 0.--13. 1. " TSO ,Transfer Start Offset"
line.long 0x94 "TCR37,Transfer Configuration RAM 37"
bitfld.long 0x94 18. " STXR ,Set Transmit Request" "Not set,Set"
bitfld.long 0x94 17. " THTSM ,Transfer Header to System Memory" "No transfer,Transfer"
bitfld.long 0x94 16. " TPTSM ,Transfer Payload to System Memory" "No transfer,Transfer"
textline " "
bitfld.long 0x94 15. " THTCC ,Transfer Header to Communication Controller" "No transfer,Transfer"
bitfld.long 0x94 14. " TPTCC ,Transfer Payload to Communication Controller" "No transfer,Transfer"
hexmask.long.word 0x94 0.--13. 1. " TSO ,Transfer Start Offset"
line.long 0x98 "TCR38,Transfer Configuration RAM 38"
bitfld.long 0x98 18. " STXR ,Set Transmit Request" "Not set,Set"
bitfld.long 0x98 17. " THTSM ,Transfer Header to System Memory" "No transfer,Transfer"
bitfld.long 0x98 16. " TPTSM ,Transfer Payload to System Memory" "No transfer,Transfer"
textline " "
bitfld.long 0x98 15. " THTCC ,Transfer Header to Communication Controller" "No transfer,Transfer"
bitfld.long 0x98 14. " TPTCC ,Transfer Payload to Communication Controller" "No transfer,Transfer"
hexmask.long.word 0x98 0.--13. 1. " TSO ,Transfer Start Offset"
line.long 0x9C "TCR39,Transfer Configuration RAM 39"
bitfld.long 0x9C 18. " STXR ,Set Transmit Request" "Not set,Set"
bitfld.long 0x9C 17. " THTSM ,Transfer Header to System Memory" "No transfer,Transfer"
bitfld.long 0x9C 16. " TPTSM ,Transfer Payload to System Memory" "No transfer,Transfer"
textline " "
bitfld.long 0x9C 15. " THTCC ,Transfer Header to Communication Controller" "No transfer,Transfer"
bitfld.long 0x9C 14. " TPTCC ,Transfer Payload to Communication Controller" "No transfer,Transfer"
hexmask.long.word 0x9C 0.--13. 1. " TSO ,Transfer Start Offset"
line.long 0xA0 "TCR40,Transfer Configuration RAM 40"
bitfld.long 0xA0 18. " STXR ,Set Transmit Request" "Not set,Set"
bitfld.long 0xA0 17. " THTSM ,Transfer Header to System Memory" "No transfer,Transfer"
bitfld.long 0xA0 16. " TPTSM ,Transfer Payload to System Memory" "No transfer,Transfer"
textline " "
bitfld.long 0xA0 15. " THTCC ,Transfer Header to Communication Controller" "No transfer,Transfer"
bitfld.long 0xA0 14. " TPTCC ,Transfer Payload to Communication Controller" "No transfer,Transfer"
hexmask.long.word 0xA0 0.--13. 1. " TSO ,Transfer Start Offset"
line.long 0xA4 "TCR41,Transfer Configuration RAM 41"
bitfld.long 0xA4 18. " STXR ,Set Transmit Request" "Not set,Set"
bitfld.long 0xA4 17. " THTSM ,Transfer Header to System Memory" "No transfer,Transfer"
bitfld.long 0xA4 16. " TPTSM ,Transfer Payload to System Memory" "No transfer,Transfer"
textline " "
bitfld.long 0xA4 15. " THTCC ,Transfer Header to Communication Controller" "No transfer,Transfer"
bitfld.long 0xA4 14. " TPTCC ,Transfer Payload to Communication Controller" "No transfer,Transfer"
hexmask.long.word 0xA4 0.--13. 1. " TSO ,Transfer Start Offset"
line.long 0xA8 "TCR42,Transfer Configuration RAM 42"
bitfld.long 0xA8 18. " STXR ,Set Transmit Request" "Not set,Set"
bitfld.long 0xA8 17. " THTSM ,Transfer Header to System Memory" "No transfer,Transfer"
bitfld.long 0xA8 16. " TPTSM ,Transfer Payload to System Memory" "No transfer,Transfer"
textline " "
bitfld.long 0xA8 15. " THTCC ,Transfer Header to Communication Controller" "No transfer,Transfer"
bitfld.long 0xA8 14. " TPTCC ,Transfer Payload to Communication Controller" "No transfer,Transfer"
hexmask.long.word 0xA8 0.--13. 1. " TSO ,Transfer Start Offset"
line.long 0xAC "TCR43,Transfer Configuration RAM 43"
bitfld.long 0xAC 18. " STXR ,Set Transmit Request" "Not set,Set"
bitfld.long 0xAC 17. " THTSM ,Transfer Header to System Memory" "No transfer,Transfer"
bitfld.long 0xAC 16. " TPTSM ,Transfer Payload to System Memory" "No transfer,Transfer"
textline " "
bitfld.long 0xAC 15. " THTCC ,Transfer Header to Communication Controller" "No transfer,Transfer"
bitfld.long 0xAC 14. " TPTCC ,Transfer Payload to Communication Controller" "No transfer,Transfer"
hexmask.long.word 0xAC 0.--13. 1. " TSO ,Transfer Start Offset"
line.long 0xB0 "TCR44,Transfer Configuration RAM 44"
bitfld.long 0xB0 18. " STXR ,Set Transmit Request" "Not set,Set"
bitfld.long 0xB0 17. " THTSM ,Transfer Header to System Memory" "No transfer,Transfer"
bitfld.long 0xB0 16. " TPTSM ,Transfer Payload to System Memory" "No transfer,Transfer"
textline " "
bitfld.long 0xB0 15. " THTCC ,Transfer Header to Communication Controller" "No transfer,Transfer"
bitfld.long 0xB0 14. " TPTCC ,Transfer Payload to Communication Controller" "No transfer,Transfer"
hexmask.long.word 0xB0 0.--13. 1. " TSO ,Transfer Start Offset"
line.long 0xB4 "TCR45,Transfer Configuration RAM 45"
bitfld.long 0xB4 18. " STXR ,Set Transmit Request" "Not set,Set"
bitfld.long 0xB4 17. " THTSM ,Transfer Header to System Memory" "No transfer,Transfer"
bitfld.long 0xB4 16. " TPTSM ,Transfer Payload to System Memory" "No transfer,Transfer"
textline " "
bitfld.long 0xB4 15. " THTCC ,Transfer Header to Communication Controller" "No transfer,Transfer"
bitfld.long 0xB4 14. " TPTCC ,Transfer Payload to Communication Controller" "No transfer,Transfer"
hexmask.long.word 0xB4 0.--13. 1. " TSO ,Transfer Start Offset"
line.long 0xB8 "TCR46,Transfer Configuration RAM 46"
bitfld.long 0xB8 18. " STXR ,Set Transmit Request" "Not set,Set"
bitfld.long 0xB8 17. " THTSM ,Transfer Header to System Memory" "No transfer,Transfer"
bitfld.long 0xB8 16. " TPTSM ,Transfer Payload to System Memory" "No transfer,Transfer"
textline " "
bitfld.long 0xB8 15. " THTCC ,Transfer Header to Communication Controller" "No transfer,Transfer"
bitfld.long 0xB8 14. " TPTCC ,Transfer Payload to Communication Controller" "No transfer,Transfer"
hexmask.long.word 0xB8 0.--13. 1. " TSO ,Transfer Start Offset"
line.long 0xBC "TCR47,Transfer Configuration RAM 47"
bitfld.long 0xBC 18. " STXR ,Set Transmit Request" "Not set,Set"
bitfld.long 0xBC 17. " THTSM ,Transfer Header to System Memory" "No transfer,Transfer"
bitfld.long 0xBC 16. " TPTSM ,Transfer Payload to System Memory" "No transfer,Transfer"
textline " "
bitfld.long 0xBC 15. " THTCC ,Transfer Header to Communication Controller" "No transfer,Transfer"
bitfld.long 0xBC 14. " TPTCC ,Transfer Payload to Communication Controller" "No transfer,Transfer"
hexmask.long.word 0xBC 0.--13. 1. " TSO ,Transfer Start Offset"
line.long 0xC0 "TCR48,Transfer Configuration RAM 48"
bitfld.long 0xC0 18. " STXR ,Set Transmit Request" "Not set,Set"
bitfld.long 0xC0 17. " THTSM ,Transfer Header to System Memory" "No transfer,Transfer"
bitfld.long 0xC0 16. " TPTSM ,Transfer Payload to System Memory" "No transfer,Transfer"
textline " "
bitfld.long 0xC0 15. " THTCC ,Transfer Header to Communication Controller" "No transfer,Transfer"
bitfld.long 0xC0 14. " TPTCC ,Transfer Payload to Communication Controller" "No transfer,Transfer"
hexmask.long.word 0xC0 0.--13. 1. " TSO ,Transfer Start Offset"
line.long 0xC4 "TCR49,Transfer Configuration RAM 49"
bitfld.long 0xC4 18. " STXR ,Set Transmit Request" "Not set,Set"
bitfld.long 0xC4 17. " THTSM ,Transfer Header to System Memory" "No transfer,Transfer"
bitfld.long 0xC4 16. " TPTSM ,Transfer Payload to System Memory" "No transfer,Transfer"
textline " "
bitfld.long 0xC4 15. " THTCC ,Transfer Header to Communication Controller" "No transfer,Transfer"
bitfld.long 0xC4 14. " TPTCC ,Transfer Payload to Communication Controller" "No transfer,Transfer"
hexmask.long.word 0xC4 0.--13. 1. " TSO ,Transfer Start Offset"
line.long 0xC8 "TCR50,Transfer Configuration RAM 50"
bitfld.long 0xC8 18. " STXR ,Set Transmit Request" "Not set,Set"
bitfld.long 0xC8 17. " THTSM ,Transfer Header to System Memory" "No transfer,Transfer"
bitfld.long 0xC8 16. " TPTSM ,Transfer Payload to System Memory" "No transfer,Transfer"
textline " "
bitfld.long 0xC8 15. " THTCC ,Transfer Header to Communication Controller" "No transfer,Transfer"
bitfld.long 0xC8 14. " TPTCC ,Transfer Payload to Communication Controller" "No transfer,Transfer"
hexmask.long.word 0xC8 0.--13. 1. " TSO ,Transfer Start Offset"
line.long 0xCC "TCR51,Transfer Configuration RAM 51"
bitfld.long 0xCC 18. " STXR ,Set Transmit Request" "Not set,Set"
bitfld.long 0xCC 17. " THTSM ,Transfer Header to System Memory" "No transfer,Transfer"
bitfld.long 0xCC 16. " TPTSM ,Transfer Payload to System Memory" "No transfer,Transfer"
textline " "
bitfld.long 0xCC 15. " THTCC ,Transfer Header to Communication Controller" "No transfer,Transfer"
bitfld.long 0xCC 14. " TPTCC ,Transfer Payload to Communication Controller" "No transfer,Transfer"
hexmask.long.word 0xCC 0.--13. 1. " TSO ,Transfer Start Offset"
line.long 0xD0 "TCR52,Transfer Configuration RAM 52"
bitfld.long 0xD0 18. " STXR ,Set Transmit Request" "Not set,Set"
bitfld.long 0xD0 17. " THTSM ,Transfer Header to System Memory" "No transfer,Transfer"
bitfld.long 0xD0 16. " TPTSM ,Transfer Payload to System Memory" "No transfer,Transfer"
textline " "
bitfld.long 0xD0 15. " THTCC ,Transfer Header to Communication Controller" "No transfer,Transfer"
bitfld.long 0xD0 14. " TPTCC ,Transfer Payload to Communication Controller" "No transfer,Transfer"
hexmask.long.word 0xD0 0.--13. 1. " TSO ,Transfer Start Offset"
line.long 0xD4 "TCR53,Transfer Configuration RAM 53"
bitfld.long 0xD4 18. " STXR ,Set Transmit Request" "Not set,Set"
bitfld.long 0xD4 17. " THTSM ,Transfer Header to System Memory" "No transfer,Transfer"
bitfld.long 0xD4 16. " TPTSM ,Transfer Payload to System Memory" "No transfer,Transfer"
textline " "
bitfld.long 0xD4 15. " THTCC ,Transfer Header to Communication Controller" "No transfer,Transfer"
bitfld.long 0xD4 14. " TPTCC ,Transfer Payload to Communication Controller" "No transfer,Transfer"
hexmask.long.word 0xD4 0.--13. 1. " TSO ,Transfer Start Offset"
line.long 0xD8 "TCR54,Transfer Configuration RAM 54"
bitfld.long 0xD8 18. " STXR ,Set Transmit Request" "Not set,Set"
bitfld.long 0xD8 17. " THTSM ,Transfer Header to System Memory" "No transfer,Transfer"
bitfld.long 0xD8 16. " TPTSM ,Transfer Payload to System Memory" "No transfer,Transfer"
textline " "
bitfld.long 0xD8 15. " THTCC ,Transfer Header to Communication Controller" "No transfer,Transfer"
bitfld.long 0xD8 14. " TPTCC ,Transfer Payload to Communication Controller" "No transfer,Transfer"
hexmask.long.word 0xD8 0.--13. 1. " TSO ,Transfer Start Offset"
line.long 0xDC "TCR55,Transfer Configuration RAM 55"
bitfld.long 0xDC 18. " STXR ,Set Transmit Request" "Not set,Set"
bitfld.long 0xDC 17. " THTSM ,Transfer Header to System Memory" "No transfer,Transfer"
bitfld.long 0xDC 16. " TPTSM ,Transfer Payload to System Memory" "No transfer,Transfer"
textline " "
bitfld.long 0xDC 15. " THTCC ,Transfer Header to Communication Controller" "No transfer,Transfer"
bitfld.long 0xDC 14. " TPTCC ,Transfer Payload to Communication Controller" "No transfer,Transfer"
hexmask.long.word 0xDC 0.--13. 1. " TSO ,Transfer Start Offset"
line.long 0xE0 "TCR56,Transfer Configuration RAM 56"
bitfld.long 0xE0 18. " STXR ,Set Transmit Request" "Not set,Set"
bitfld.long 0xE0 17. " THTSM ,Transfer Header to System Memory" "No transfer,Transfer"
bitfld.long 0xE0 16. " TPTSM ,Transfer Payload to System Memory" "No transfer,Transfer"
textline " "
bitfld.long 0xE0 15. " THTCC ,Transfer Header to Communication Controller" "No transfer,Transfer"
bitfld.long 0xE0 14. " TPTCC ,Transfer Payload to Communication Controller" "No transfer,Transfer"
hexmask.long.word 0xE0 0.--13. 1. " TSO ,Transfer Start Offset"
line.long 0xE4 "TCR57,Transfer Configuration RAM 57"
bitfld.long 0xE4 18. " STXR ,Set Transmit Request" "Not set,Set"
bitfld.long 0xE4 17. " THTSM ,Transfer Header to System Memory" "No transfer,Transfer"
bitfld.long 0xE4 16. " TPTSM ,Transfer Payload to System Memory" "No transfer,Transfer"
textline " "
bitfld.long 0xE4 15. " THTCC ,Transfer Header to Communication Controller" "No transfer,Transfer"
bitfld.long 0xE4 14. " TPTCC ,Transfer Payload to Communication Controller" "No transfer,Transfer"
hexmask.long.word 0xE4 0.--13. 1. " TSO ,Transfer Start Offset"
line.long 0xE8 "TCR58,Transfer Configuration RAM 58"
bitfld.long 0xE8 18. " STXR ,Set Transmit Request" "Not set,Set"
bitfld.long 0xE8 17. " THTSM ,Transfer Header to System Memory" "No transfer,Transfer"
bitfld.long 0xE8 16. " TPTSM ,Transfer Payload to System Memory" "No transfer,Transfer"
textline " "
bitfld.long 0xE8 15. " THTCC ,Transfer Header to Communication Controller" "No transfer,Transfer"
bitfld.long 0xE8 14. " TPTCC ,Transfer Payload to Communication Controller" "No transfer,Transfer"
hexmask.long.word 0xE8 0.--13. 1. " TSO ,Transfer Start Offset"
line.long 0xEC "TCR59,Transfer Configuration RAM 59"
bitfld.long 0xEC 18. " STXR ,Set Transmit Request" "Not set,Set"
bitfld.long 0xEC 17. " THTSM ,Transfer Header to System Memory" "No transfer,Transfer"
bitfld.long 0xEC 16. " TPTSM ,Transfer Payload to System Memory" "No transfer,Transfer"
textline " "
bitfld.long 0xEC 15. " THTCC ,Transfer Header to Communication Controller" "No transfer,Transfer"
bitfld.long 0xEC 14. " TPTCC ,Transfer Payload to Communication Controller" "No transfer,Transfer"
hexmask.long.word 0xEC 0.--13. 1. " TSO ,Transfer Start Offset"
line.long 0xF0 "TCR60,Transfer Configuration RAM 60"
bitfld.long 0xF0 18. " STXR ,Set Transmit Request" "Not set,Set"
bitfld.long 0xF0 17. " THTSM ,Transfer Header to System Memory" "No transfer,Transfer"
bitfld.long 0xF0 16. " TPTSM ,Transfer Payload to System Memory" "No transfer,Transfer"
textline " "
bitfld.long 0xF0 15. " THTCC ,Transfer Header to Communication Controller" "No transfer,Transfer"
bitfld.long 0xF0 14. " TPTCC ,Transfer Payload to Communication Controller" "No transfer,Transfer"
hexmask.long.word 0xF0 0.--13. 1. " TSO ,Transfer Start Offset"
line.long 0xF4 "TCR61,Transfer Configuration RAM 61"
bitfld.long 0xF4 18. " STXR ,Set Transmit Request" "Not set,Set"
bitfld.long 0xF4 17. " THTSM ,Transfer Header to System Memory" "No transfer,Transfer"
bitfld.long 0xF4 16. " TPTSM ,Transfer Payload to System Memory" "No transfer,Transfer"
textline " "
bitfld.long 0xF4 15. " THTCC ,Transfer Header to Communication Controller" "No transfer,Transfer"
bitfld.long 0xF4 14. " TPTCC ,Transfer Payload to Communication Controller" "No transfer,Transfer"
hexmask.long.word 0xF4 0.--13. 1. " TSO ,Transfer Start Offset"
line.long 0xF8 "TCR62,Transfer Configuration RAM 62"
bitfld.long 0xF8 18. " STXR ,Set Transmit Request" "Not set,Set"
bitfld.long 0xF8 17. " THTSM ,Transfer Header to System Memory" "No transfer,Transfer"
bitfld.long 0xF8 16. " TPTSM ,Transfer Payload to System Memory" "No transfer,Transfer"
textline " "
bitfld.long 0xF8 15. " THTCC ,Transfer Header to Communication Controller" "No transfer,Transfer"
bitfld.long 0xF8 14. " TPTCC ,Transfer Payload to Communication Controller" "No transfer,Transfer"
hexmask.long.word 0xF8 0.--13. 1. " TSO ,Transfer Start Offset"
line.long 0xFC "TCR63,Transfer Configuration RAM 63"
bitfld.long 0xFC 18. " STXR ,Set Transmit Request" "Not set,Set"
bitfld.long 0xFC 17. " THTSM ,Transfer Header to System Memory" "No transfer,Transfer"
bitfld.long 0xFC 16. " TPTSM ,Transfer Payload to System Memory" "No transfer,Transfer"
textline " "
bitfld.long 0xFC 15. " THTCC ,Transfer Header to Communication Controller" "No transfer,Transfer"
bitfld.long 0xFC 14. " TPTCC ,Transfer Payload to Communication Controller" "No transfer,Transfer"
hexmask.long.word 0xFC 0.--13. 1. " TSO ,Transfer Start Offset"
line.long 0x100 "TCR64,Transfer Configuration RAM 64"
bitfld.long 0x100 18. " STXR ,Set Transmit Request" "Not set,Set"
bitfld.long 0x100 17. " THTSM ,Transfer Header to System Memory" "No transfer,Transfer"
bitfld.long 0x100 16. " TPTSM ,Transfer Payload to System Memory" "No transfer,Transfer"
textline " "
bitfld.long 0x100 15. " THTCC ,Transfer Header to Communication Controller" "No transfer,Transfer"
bitfld.long 0x100 14. " TPTCC ,Transfer Payload to Communication Controller" "No transfer,Transfer"
hexmask.long.word 0x100 0.--13. 1. " TSO ,Transfer Start Offset"
line.long 0x104 "TCR65,Transfer Configuration RAM 65"
bitfld.long 0x104 18. " STXR ,Set Transmit Request" "Not set,Set"
bitfld.long 0x104 17. " THTSM ,Transfer Header to System Memory" "No transfer,Transfer"
bitfld.long 0x104 16. " TPTSM ,Transfer Payload to System Memory" "No transfer,Transfer"
textline " "
bitfld.long 0x104 15. " THTCC ,Transfer Header to Communication Controller" "No transfer,Transfer"
bitfld.long 0x104 14. " TPTCC ,Transfer Payload to Communication Controller" "No transfer,Transfer"
hexmask.long.word 0x104 0.--13. 1. " TSO ,Transfer Start Offset"
line.long 0x108 "TCR66,Transfer Configuration RAM 66"
bitfld.long 0x108 18. " STXR ,Set Transmit Request" "Not set,Set"
bitfld.long 0x108 17. " THTSM ,Transfer Header to System Memory" "No transfer,Transfer"
bitfld.long 0x108 16. " TPTSM ,Transfer Payload to System Memory" "No transfer,Transfer"
textline " "
bitfld.long 0x108 15. " THTCC ,Transfer Header to Communication Controller" "No transfer,Transfer"
bitfld.long 0x108 14. " TPTCC ,Transfer Payload to Communication Controller" "No transfer,Transfer"
hexmask.long.word 0x108 0.--13. 1. " TSO ,Transfer Start Offset"
line.long 0x10C "TCR67,Transfer Configuration RAM 67"
bitfld.long 0x10C 18. " STXR ,Set Transmit Request" "Not set,Set"
bitfld.long 0x10C 17. " THTSM ,Transfer Header to System Memory" "No transfer,Transfer"
bitfld.long 0x10C 16. " TPTSM ,Transfer Payload to System Memory" "No transfer,Transfer"
textline " "
bitfld.long 0x10C 15. " THTCC ,Transfer Header to Communication Controller" "No transfer,Transfer"
bitfld.long 0x10C 14. " TPTCC ,Transfer Payload to Communication Controller" "No transfer,Transfer"
hexmask.long.word 0x10C 0.--13. 1. " TSO ,Transfer Start Offset"
line.long 0x110 "TCR68,Transfer Configuration RAM 68"
bitfld.long 0x110 18. " STXR ,Set Transmit Request" "Not set,Set"
bitfld.long 0x110 17. " THTSM ,Transfer Header to System Memory" "No transfer,Transfer"
bitfld.long 0x110 16. " TPTSM ,Transfer Payload to System Memory" "No transfer,Transfer"
textline " "
bitfld.long 0x110 15. " THTCC ,Transfer Header to Communication Controller" "No transfer,Transfer"
bitfld.long 0x110 14. " TPTCC ,Transfer Payload to Communication Controller" "No transfer,Transfer"
hexmask.long.word 0x110 0.--13. 1. " TSO ,Transfer Start Offset"
line.long 0x114 "TCR69,Transfer Configuration RAM 69"
bitfld.long 0x114 18. " STXR ,Set Transmit Request" "Not set,Set"
bitfld.long 0x114 17. " THTSM ,Transfer Header to System Memory" "No transfer,Transfer"
bitfld.long 0x114 16. " TPTSM ,Transfer Payload to System Memory" "No transfer,Transfer"
textline " "
bitfld.long 0x114 15. " THTCC ,Transfer Header to Communication Controller" "No transfer,Transfer"
bitfld.long 0x114 14. " TPTCC ,Transfer Payload to Communication Controller" "No transfer,Transfer"
hexmask.long.word 0x114 0.--13. 1. " TSO ,Transfer Start Offset"
line.long 0x118 "TCR70,Transfer Configuration RAM 70"
bitfld.long 0x118 18. " STXR ,Set Transmit Request" "Not set,Set"
bitfld.long 0x118 17. " THTSM ,Transfer Header to System Memory" "No transfer,Transfer"
bitfld.long 0x118 16. " TPTSM ,Transfer Payload to System Memory" "No transfer,Transfer"
textline " "
bitfld.long 0x118 15. " THTCC ,Transfer Header to Communication Controller" "No transfer,Transfer"
bitfld.long 0x118 14. " TPTCC ,Transfer Payload to Communication Controller" "No transfer,Transfer"
hexmask.long.word 0x118 0.--13. 1. " TSO ,Transfer Start Offset"
line.long 0x11C "TCR71,Transfer Configuration RAM 71"
bitfld.long 0x11C 18. " STXR ,Set Transmit Request" "Not set,Set"
bitfld.long 0x11C 17. " THTSM ,Transfer Header to System Memory" "No transfer,Transfer"
bitfld.long 0x11C 16. " TPTSM ,Transfer Payload to System Memory" "No transfer,Transfer"
textline " "
bitfld.long 0x11C 15. " THTCC ,Transfer Header to Communication Controller" "No transfer,Transfer"
bitfld.long 0x11C 14. " TPTCC ,Transfer Payload to Communication Controller" "No transfer,Transfer"
hexmask.long.word 0x11C 0.--13. 1. " TSO ,Transfer Start Offset"
line.long 0x120 "TCR72,Transfer Configuration RAM 72"
bitfld.long 0x120 18. " STXR ,Set Transmit Request" "Not set,Set"
bitfld.long 0x120 17. " THTSM ,Transfer Header to System Memory" "No transfer,Transfer"
bitfld.long 0x120 16. " TPTSM ,Transfer Payload to System Memory" "No transfer,Transfer"
textline " "
bitfld.long 0x120 15. " THTCC ,Transfer Header to Communication Controller" "No transfer,Transfer"
bitfld.long 0x120 14. " TPTCC ,Transfer Payload to Communication Controller" "No transfer,Transfer"
hexmask.long.word 0x120 0.--13. 1. " TSO ,Transfer Start Offset"
line.long 0x124 "TCR73,Transfer Configuration RAM 73"
bitfld.long 0x124 18. " STXR ,Set Transmit Request" "Not set,Set"
bitfld.long 0x124 17. " THTSM ,Transfer Header to System Memory" "No transfer,Transfer"
bitfld.long 0x124 16. " TPTSM ,Transfer Payload to System Memory" "No transfer,Transfer"
textline " "
bitfld.long 0x124 15. " THTCC ,Transfer Header to Communication Controller" "No transfer,Transfer"
bitfld.long 0x124 14. " TPTCC ,Transfer Payload to Communication Controller" "No transfer,Transfer"
hexmask.long.word 0x124 0.--13. 1. " TSO ,Transfer Start Offset"
line.long 0x128 "TCR74,Transfer Configuration RAM 74"
bitfld.long 0x128 18. " STXR ,Set Transmit Request" "Not set,Set"
bitfld.long 0x128 17. " THTSM ,Transfer Header to System Memory" "No transfer,Transfer"
bitfld.long 0x128 16. " TPTSM ,Transfer Payload to System Memory" "No transfer,Transfer"
textline " "
bitfld.long 0x128 15. " THTCC ,Transfer Header to Communication Controller" "No transfer,Transfer"
bitfld.long 0x128 14. " TPTCC ,Transfer Payload to Communication Controller" "No transfer,Transfer"
hexmask.long.word 0x128 0.--13. 1. " TSO ,Transfer Start Offset"
line.long 0x12C "TCR75,Transfer Configuration RAM 75"
bitfld.long 0x12C 18. " STXR ,Set Transmit Request" "Not set,Set"
bitfld.long 0x12C 17. " THTSM ,Transfer Header to System Memory" "No transfer,Transfer"
bitfld.long 0x12C 16. " TPTSM ,Transfer Payload to System Memory" "No transfer,Transfer"
textline " "
bitfld.long 0x12C 15. " THTCC ,Transfer Header to Communication Controller" "No transfer,Transfer"
bitfld.long 0x12C 14. " TPTCC ,Transfer Payload to Communication Controller" "No transfer,Transfer"
hexmask.long.word 0x12C 0.--13. 1. " TSO ,Transfer Start Offset"
line.long 0x130 "TCR76,Transfer Configuration RAM 76"
bitfld.long 0x130 18. " STXR ,Set Transmit Request" "Not set,Set"
bitfld.long 0x130 17. " THTSM ,Transfer Header to System Memory" "No transfer,Transfer"
bitfld.long 0x130 16. " TPTSM ,Transfer Payload to System Memory" "No transfer,Transfer"
textline " "
bitfld.long 0x130 15. " THTCC ,Transfer Header to Communication Controller" "No transfer,Transfer"
bitfld.long 0x130 14. " TPTCC ,Transfer Payload to Communication Controller" "No transfer,Transfer"
hexmask.long.word 0x130 0.--13. 1. " TSO ,Transfer Start Offset"
line.long 0x134 "TCR77,Transfer Configuration RAM 77"
bitfld.long 0x134 18. " STXR ,Set Transmit Request" "Not set,Set"
bitfld.long 0x134 17. " THTSM ,Transfer Header to System Memory" "No transfer,Transfer"
bitfld.long 0x134 16. " TPTSM ,Transfer Payload to System Memory" "No transfer,Transfer"
textline " "
bitfld.long 0x134 15. " THTCC ,Transfer Header to Communication Controller" "No transfer,Transfer"
bitfld.long 0x134 14. " TPTCC ,Transfer Payload to Communication Controller" "No transfer,Transfer"
hexmask.long.word 0x134 0.--13. 1. " TSO ,Transfer Start Offset"
line.long 0x138 "TCR78,Transfer Configuration RAM 78"
bitfld.long 0x138 18. " STXR ,Set Transmit Request" "Not set,Set"
bitfld.long 0x138 17. " THTSM ,Transfer Header to System Memory" "No transfer,Transfer"
bitfld.long 0x138 16. " TPTSM ,Transfer Payload to System Memory" "No transfer,Transfer"
textline " "
bitfld.long 0x138 15. " THTCC ,Transfer Header to Communication Controller" "No transfer,Transfer"
bitfld.long 0x138 14. " TPTCC ,Transfer Payload to Communication Controller" "No transfer,Transfer"
hexmask.long.word 0x138 0.--13. 1. " TSO ,Transfer Start Offset"
line.long 0x13C "TCR79,Transfer Configuration RAM 79"
bitfld.long 0x13C 18. " STXR ,Set Transmit Request" "Not set,Set"
bitfld.long 0x13C 17. " THTSM ,Transfer Header to System Memory" "No transfer,Transfer"
bitfld.long 0x13C 16. " TPTSM ,Transfer Payload to System Memory" "No transfer,Transfer"
textline " "
bitfld.long 0x13C 15. " THTCC ,Transfer Header to Communication Controller" "No transfer,Transfer"
bitfld.long 0x13C 14. " TPTCC ,Transfer Payload to Communication Controller" "No transfer,Transfer"
hexmask.long.word 0x13C 0.--13. 1. " TSO ,Transfer Start Offset"
line.long 0x140 "TCR80,Transfer Configuration RAM 80"
bitfld.long 0x140 18. " STXR ,Set Transmit Request" "Not set,Set"
bitfld.long 0x140 17. " THTSM ,Transfer Header to System Memory" "No transfer,Transfer"
bitfld.long 0x140 16. " TPTSM ,Transfer Payload to System Memory" "No transfer,Transfer"
textline " "
bitfld.long 0x140 15. " THTCC ,Transfer Header to Communication Controller" "No transfer,Transfer"
bitfld.long 0x140 14. " TPTCC ,Transfer Payload to Communication Controller" "No transfer,Transfer"
hexmask.long.word 0x140 0.--13. 1. " TSO ,Transfer Start Offset"
line.long 0x144 "TCR81,Transfer Configuration RAM 81"
bitfld.long 0x144 18. " STXR ,Set Transmit Request" "Not set,Set"
bitfld.long 0x144 17. " THTSM ,Transfer Header to System Memory" "No transfer,Transfer"
bitfld.long 0x144 16. " TPTSM ,Transfer Payload to System Memory" "No transfer,Transfer"
textline " "
bitfld.long 0x144 15. " THTCC ,Transfer Header to Communication Controller" "No transfer,Transfer"
bitfld.long 0x144 14. " TPTCC ,Transfer Payload to Communication Controller" "No transfer,Transfer"
hexmask.long.word 0x144 0.--13. 1. " TSO ,Transfer Start Offset"
line.long 0x148 "TCR82,Transfer Configuration RAM 82"
bitfld.long 0x148 18. " STXR ,Set Transmit Request" "Not set,Set"
bitfld.long 0x148 17. " THTSM ,Transfer Header to System Memory" "No transfer,Transfer"
bitfld.long 0x148 16. " TPTSM ,Transfer Payload to System Memory" "No transfer,Transfer"
textline " "
bitfld.long 0x148 15. " THTCC ,Transfer Header to Communication Controller" "No transfer,Transfer"
bitfld.long 0x148 14. " TPTCC ,Transfer Payload to Communication Controller" "No transfer,Transfer"
hexmask.long.word 0x148 0.--13. 1. " TSO ,Transfer Start Offset"
line.long 0x14C "TCR83,Transfer Configuration RAM 83"
bitfld.long 0x14C 18. " STXR ,Set Transmit Request" "Not set,Set"
bitfld.long 0x14C 17. " THTSM ,Transfer Header to System Memory" "No transfer,Transfer"
bitfld.long 0x14C 16. " TPTSM ,Transfer Payload to System Memory" "No transfer,Transfer"
textline " "
bitfld.long 0x14C 15. " THTCC ,Transfer Header to Communication Controller" "No transfer,Transfer"
bitfld.long 0x14C 14. " TPTCC ,Transfer Payload to Communication Controller" "No transfer,Transfer"
hexmask.long.word 0x14C 0.--13. 1. " TSO ,Transfer Start Offset"
line.long 0x150 "TCR84,Transfer Configuration RAM 84"
bitfld.long 0x150 18. " STXR ,Set Transmit Request" "Not set,Set"
bitfld.long 0x150 17. " THTSM ,Transfer Header to System Memory" "No transfer,Transfer"
bitfld.long 0x150 16. " TPTSM ,Transfer Payload to System Memory" "No transfer,Transfer"
textline " "
bitfld.long 0x150 15. " THTCC ,Transfer Header to Communication Controller" "No transfer,Transfer"
bitfld.long 0x150 14. " TPTCC ,Transfer Payload to Communication Controller" "No transfer,Transfer"
hexmask.long.word 0x150 0.--13. 1. " TSO ,Transfer Start Offset"
line.long 0x154 "TCR85,Transfer Configuration RAM 85"
bitfld.long 0x154 18. " STXR ,Set Transmit Request" "Not set,Set"
bitfld.long 0x154 17. " THTSM ,Transfer Header to System Memory" "No transfer,Transfer"
bitfld.long 0x154 16. " TPTSM ,Transfer Payload to System Memory" "No transfer,Transfer"
textline " "
bitfld.long 0x154 15. " THTCC ,Transfer Header to Communication Controller" "No transfer,Transfer"
bitfld.long 0x154 14. " TPTCC ,Transfer Payload to Communication Controller" "No transfer,Transfer"
hexmask.long.word 0x154 0.--13. 1. " TSO ,Transfer Start Offset"
line.long 0x158 "TCR86,Transfer Configuration RAM 86"
bitfld.long 0x158 18. " STXR ,Set Transmit Request" "Not set,Set"
bitfld.long 0x158 17. " THTSM ,Transfer Header to System Memory" "No transfer,Transfer"
bitfld.long 0x158 16. " TPTSM ,Transfer Payload to System Memory" "No transfer,Transfer"
textline " "
bitfld.long 0x158 15. " THTCC ,Transfer Header to Communication Controller" "No transfer,Transfer"
bitfld.long 0x158 14. " TPTCC ,Transfer Payload to Communication Controller" "No transfer,Transfer"
hexmask.long.word 0x158 0.--13. 1. " TSO ,Transfer Start Offset"
line.long 0x15C "TCR87,Transfer Configuration RAM 87"
bitfld.long 0x15C 18. " STXR ,Set Transmit Request" "Not set,Set"
bitfld.long 0x15C 17. " THTSM ,Transfer Header to System Memory" "No transfer,Transfer"
bitfld.long 0x15C 16. " TPTSM ,Transfer Payload to System Memory" "No transfer,Transfer"
textline " "
bitfld.long 0x15C 15. " THTCC ,Transfer Header to Communication Controller" "No transfer,Transfer"
bitfld.long 0x15C 14. " TPTCC ,Transfer Payload to Communication Controller" "No transfer,Transfer"
hexmask.long.word 0x15C 0.--13. 1. " TSO ,Transfer Start Offset"
line.long 0x160 "TCR88,Transfer Configuration RAM 88"
bitfld.long 0x160 18. " STXR ,Set Transmit Request" "Not set,Set"
bitfld.long 0x160 17. " THTSM ,Transfer Header to System Memory" "No transfer,Transfer"
bitfld.long 0x160 16. " TPTSM ,Transfer Payload to System Memory" "No transfer,Transfer"
textline " "
bitfld.long 0x160 15. " THTCC ,Transfer Header to Communication Controller" "No transfer,Transfer"
bitfld.long 0x160 14. " TPTCC ,Transfer Payload to Communication Controller" "No transfer,Transfer"
hexmask.long.word 0x160 0.--13. 1. " TSO ,Transfer Start Offset"
line.long 0x164 "TCR89,Transfer Configuration RAM 89"
bitfld.long 0x164 18. " STXR ,Set Transmit Request" "Not set,Set"
bitfld.long 0x164 17. " THTSM ,Transfer Header to System Memory" "No transfer,Transfer"
bitfld.long 0x164 16. " TPTSM ,Transfer Payload to System Memory" "No transfer,Transfer"
textline " "
bitfld.long 0x164 15. " THTCC ,Transfer Header to Communication Controller" "No transfer,Transfer"
bitfld.long 0x164 14. " TPTCC ,Transfer Payload to Communication Controller" "No transfer,Transfer"
hexmask.long.word 0x164 0.--13. 1. " TSO ,Transfer Start Offset"
line.long 0x168 "TCR90,Transfer Configuration RAM 90"
bitfld.long 0x168 18. " STXR ,Set Transmit Request" "Not set,Set"
bitfld.long 0x168 17. " THTSM ,Transfer Header to System Memory" "No transfer,Transfer"
bitfld.long 0x168 16. " TPTSM ,Transfer Payload to System Memory" "No transfer,Transfer"
textline " "
bitfld.long 0x168 15. " THTCC ,Transfer Header to Communication Controller" "No transfer,Transfer"
bitfld.long 0x168 14. " TPTCC ,Transfer Payload to Communication Controller" "No transfer,Transfer"
hexmask.long.word 0x168 0.--13. 1. " TSO ,Transfer Start Offset"
line.long 0x16C "TCR91,Transfer Configuration RAM 91"
bitfld.long 0x16C 18. " STXR ,Set Transmit Request" "Not set,Set"
bitfld.long 0x16C 17. " THTSM ,Transfer Header to System Memory" "No transfer,Transfer"
bitfld.long 0x16C 16. " TPTSM ,Transfer Payload to System Memory" "No transfer,Transfer"
textline " "
bitfld.long 0x16C 15. " THTCC ,Transfer Header to Communication Controller" "No transfer,Transfer"
bitfld.long 0x16C 14. " TPTCC ,Transfer Payload to Communication Controller" "No transfer,Transfer"
hexmask.long.word 0x16C 0.--13. 1. " TSO ,Transfer Start Offset"
line.long 0x170 "TCR92,Transfer Configuration RAM 92"
bitfld.long 0x170 18. " STXR ,Set Transmit Request" "Not set,Set"
bitfld.long 0x170 17. " THTSM ,Transfer Header to System Memory" "No transfer,Transfer"
bitfld.long 0x170 16. " TPTSM ,Transfer Payload to System Memory" "No transfer,Transfer"
textline " "
bitfld.long 0x170 15. " THTCC ,Transfer Header to Communication Controller" "No transfer,Transfer"
bitfld.long 0x170 14. " TPTCC ,Transfer Payload to Communication Controller" "No transfer,Transfer"
hexmask.long.word 0x170 0.--13. 1. " TSO ,Transfer Start Offset"
line.long 0x174 "TCR93,Transfer Configuration RAM 93"
bitfld.long 0x174 18. " STXR ,Set Transmit Request" "Not set,Set"
bitfld.long 0x174 17. " THTSM ,Transfer Header to System Memory" "No transfer,Transfer"
bitfld.long 0x174 16. " TPTSM ,Transfer Payload to System Memory" "No transfer,Transfer"
textline " "
bitfld.long 0x174 15. " THTCC ,Transfer Header to Communication Controller" "No transfer,Transfer"
bitfld.long 0x174 14. " TPTCC ,Transfer Payload to Communication Controller" "No transfer,Transfer"
hexmask.long.word 0x174 0.--13. 1. " TSO ,Transfer Start Offset"
line.long 0x178 "TCR94,Transfer Configuration RAM 94"
bitfld.long 0x178 18. " STXR ,Set Transmit Request" "Not set,Set"
bitfld.long 0x178 17. " THTSM ,Transfer Header to System Memory" "No transfer,Transfer"
bitfld.long 0x178 16. " TPTSM ,Transfer Payload to System Memory" "No transfer,Transfer"
textline " "
bitfld.long 0x178 15. " THTCC ,Transfer Header to Communication Controller" "No transfer,Transfer"
bitfld.long 0x178 14. " TPTCC ,Transfer Payload to Communication Controller" "No transfer,Transfer"
hexmask.long.word 0x178 0.--13. 1. " TSO ,Transfer Start Offset"
line.long 0x17C "TCR95,Transfer Configuration RAM 95"
bitfld.long 0x17C 18. " STXR ,Set Transmit Request" "Not set,Set"
bitfld.long 0x17C 17. " THTSM ,Transfer Header to System Memory" "No transfer,Transfer"
bitfld.long 0x17C 16. " TPTSM ,Transfer Payload to System Memory" "No transfer,Transfer"
textline " "
bitfld.long 0x17C 15. " THTCC ,Transfer Header to Communication Controller" "No transfer,Transfer"
bitfld.long 0x17C 14. " TPTCC ,Transfer Payload to Communication Controller" "No transfer,Transfer"
hexmask.long.word 0x17C 0.--13. 1. " TSO ,Transfer Start Offset"
line.long 0x180 "TCR96,Transfer Configuration RAM 96"
bitfld.long 0x180 18. " STXR ,Set Transmit Request" "Not set,Set"
bitfld.long 0x180 17. " THTSM ,Transfer Header to System Memory" "No transfer,Transfer"
bitfld.long 0x180 16. " TPTSM ,Transfer Payload to System Memory" "No transfer,Transfer"
textline " "
bitfld.long 0x180 15. " THTCC ,Transfer Header to Communication Controller" "No transfer,Transfer"
bitfld.long 0x180 14. " TPTCC ,Transfer Payload to Communication Controller" "No transfer,Transfer"
hexmask.long.word 0x180 0.--13. 1. " TSO ,Transfer Start Offset"
line.long 0x184 "TCR97,Transfer Configuration RAM 97"
bitfld.long 0x184 18. " STXR ,Set Transmit Request" "Not set,Set"
bitfld.long 0x184 17. " THTSM ,Transfer Header to System Memory" "No transfer,Transfer"
bitfld.long 0x184 16. " TPTSM ,Transfer Payload to System Memory" "No transfer,Transfer"
textline " "
bitfld.long 0x184 15. " THTCC ,Transfer Header to Communication Controller" "No transfer,Transfer"
bitfld.long 0x184 14. " TPTCC ,Transfer Payload to Communication Controller" "No transfer,Transfer"
hexmask.long.word 0x184 0.--13. 1. " TSO ,Transfer Start Offset"
line.long 0x188 "TCR98,Transfer Configuration RAM 98"
bitfld.long 0x188 18. " STXR ,Set Transmit Request" "Not set,Set"
bitfld.long 0x188 17. " THTSM ,Transfer Header to System Memory" "No transfer,Transfer"
bitfld.long 0x188 16. " TPTSM ,Transfer Payload to System Memory" "No transfer,Transfer"
textline " "
bitfld.long 0x188 15. " THTCC ,Transfer Header to Communication Controller" "No transfer,Transfer"
bitfld.long 0x188 14. " TPTCC ,Transfer Payload to Communication Controller" "No transfer,Transfer"
hexmask.long.word 0x188 0.--13. 1. " TSO ,Transfer Start Offset"
line.long 0x18C "TCR99,Transfer Configuration RAM 99"
bitfld.long 0x18C 18. " STXR ,Set Transmit Request" "Not set,Set"
bitfld.long 0x18C 17. " THTSM ,Transfer Header to System Memory" "No transfer,Transfer"
bitfld.long 0x18C 16. " TPTSM ,Transfer Payload to System Memory" "No transfer,Transfer"
textline " "
bitfld.long 0x18C 15. " THTCC ,Transfer Header to Communication Controller" "No transfer,Transfer"
bitfld.long 0x18C 14. " TPTCC ,Transfer Payload to Communication Controller" "No transfer,Transfer"
hexmask.long.word 0x18C 0.--13. 1. " TSO ,Transfer Start Offset"
line.long 0x190 "TCR100,Transfer Configuration RAM 100"
bitfld.long 0x190 18. " STXR ,Set Transmit Request" "Not set,Set"
bitfld.long 0x190 17. " THTSM ,Transfer Header to System Memory" "No transfer,Transfer"
bitfld.long 0x190 16. " TPTSM ,Transfer Payload to System Memory" "No transfer,Transfer"
textline " "
bitfld.long 0x190 15. " THTCC ,Transfer Header to Communication Controller" "No transfer,Transfer"
bitfld.long 0x190 14. " TPTCC ,Transfer Payload to Communication Controller" "No transfer,Transfer"
hexmask.long.word 0x190 0.--13. 1. " TSO ,Transfer Start Offset"
line.long 0x194 "TCR101,Transfer Configuration RAM 101"
bitfld.long 0x194 18. " STXR ,Set Transmit Request" "Not set,Set"
bitfld.long 0x194 17. " THTSM ,Transfer Header to System Memory" "No transfer,Transfer"
bitfld.long 0x194 16. " TPTSM ,Transfer Payload to System Memory" "No transfer,Transfer"
textline " "
bitfld.long 0x194 15. " THTCC ,Transfer Header to Communication Controller" "No transfer,Transfer"
bitfld.long 0x194 14. " TPTCC ,Transfer Payload to Communication Controller" "No transfer,Transfer"
hexmask.long.word 0x194 0.--13. 1. " TSO ,Transfer Start Offset"
line.long 0x198 "TCR102,Transfer Configuration RAM 102"
bitfld.long 0x198 18. " STXR ,Set Transmit Request" "Not set,Set"
bitfld.long 0x198 17. " THTSM ,Transfer Header to System Memory" "No transfer,Transfer"
bitfld.long 0x198 16. " TPTSM ,Transfer Payload to System Memory" "No transfer,Transfer"
textline " "
bitfld.long 0x198 15. " THTCC ,Transfer Header to Communication Controller" "No transfer,Transfer"
bitfld.long 0x198 14. " TPTCC ,Transfer Payload to Communication Controller" "No transfer,Transfer"
hexmask.long.word 0x198 0.--13. 1. " TSO ,Transfer Start Offset"
line.long 0x19C "TCR103,Transfer Configuration RAM 103"
bitfld.long 0x19C 18. " STXR ,Set Transmit Request" "Not set,Set"
bitfld.long 0x19C 17. " THTSM ,Transfer Header to System Memory" "No transfer,Transfer"
bitfld.long 0x19C 16. " TPTSM ,Transfer Payload to System Memory" "No transfer,Transfer"
textline " "
bitfld.long 0x19C 15. " THTCC ,Transfer Header to Communication Controller" "No transfer,Transfer"
bitfld.long 0x19C 14. " TPTCC ,Transfer Payload to Communication Controller" "No transfer,Transfer"
hexmask.long.word 0x19C 0.--13. 1. " TSO ,Transfer Start Offset"
line.long 0x1A0 "TCR104,Transfer Configuration RAM 104"
bitfld.long 0x1A0 18. " STXR ,Set Transmit Request" "Not set,Set"
bitfld.long 0x1A0 17. " THTSM ,Transfer Header to System Memory" "No transfer,Transfer"
bitfld.long 0x1A0 16. " TPTSM ,Transfer Payload to System Memory" "No transfer,Transfer"
textline " "
bitfld.long 0x1A0 15. " THTCC ,Transfer Header to Communication Controller" "No transfer,Transfer"
bitfld.long 0x1A0 14. " TPTCC ,Transfer Payload to Communication Controller" "No transfer,Transfer"
hexmask.long.word 0x1A0 0.--13. 1. " TSO ,Transfer Start Offset"
line.long 0x1A4 "TCR105,Transfer Configuration RAM 105"
bitfld.long 0x1A4 18. " STXR ,Set Transmit Request" "Not set,Set"
bitfld.long 0x1A4 17. " THTSM ,Transfer Header to System Memory" "No transfer,Transfer"
bitfld.long 0x1A4 16. " TPTSM ,Transfer Payload to System Memory" "No transfer,Transfer"
textline " "
bitfld.long 0x1A4 15. " THTCC ,Transfer Header to Communication Controller" "No transfer,Transfer"
bitfld.long 0x1A4 14. " TPTCC ,Transfer Payload to Communication Controller" "No transfer,Transfer"
hexmask.long.word 0x1A4 0.--13. 1. " TSO ,Transfer Start Offset"
line.long 0x1A8 "TCR106,Transfer Configuration RAM 106"
bitfld.long 0x1A8 18. " STXR ,Set Transmit Request" "Not set,Set"
bitfld.long 0x1A8 17. " THTSM ,Transfer Header to System Memory" "No transfer,Transfer"
bitfld.long 0x1A8 16. " TPTSM ,Transfer Payload to System Memory" "No transfer,Transfer"
textline " "
bitfld.long 0x1A8 15. " THTCC ,Transfer Header to Communication Controller" "No transfer,Transfer"
bitfld.long 0x1A8 14. " TPTCC ,Transfer Payload to Communication Controller" "No transfer,Transfer"
hexmask.long.word 0x1A8 0.--13. 1. " TSO ,Transfer Start Offset"
line.long 0x1AC "TCR107,Transfer Configuration RAM 107"
bitfld.long 0x1AC 18. " STXR ,Set Transmit Request" "Not set,Set"
bitfld.long 0x1AC 17. " THTSM ,Transfer Header to System Memory" "No transfer,Transfer"
bitfld.long 0x1AC 16. " TPTSM ,Transfer Payload to System Memory" "No transfer,Transfer"
textline " "
bitfld.long 0x1AC 15. " THTCC ,Transfer Header to Communication Controller" "No transfer,Transfer"
bitfld.long 0x1AC 14. " TPTCC ,Transfer Payload to Communication Controller" "No transfer,Transfer"
hexmask.long.word 0x1AC 0.--13. 1. " TSO ,Transfer Start Offset"
line.long 0x1B0 "TCR108,Transfer Configuration RAM 108"
bitfld.long 0x1B0 18. " STXR ,Set Transmit Request" "Not set,Set"
bitfld.long 0x1B0 17. " THTSM ,Transfer Header to System Memory" "No transfer,Transfer"
bitfld.long 0x1B0 16. " TPTSM ,Transfer Payload to System Memory" "No transfer,Transfer"
textline " "
bitfld.long 0x1B0 15. " THTCC ,Transfer Header to Communication Controller" "No transfer,Transfer"
bitfld.long 0x1B0 14. " TPTCC ,Transfer Payload to Communication Controller" "No transfer,Transfer"
hexmask.long.word 0x1B0 0.--13. 1. " TSO ,Transfer Start Offset"
line.long 0x1B4 "TCR109,Transfer Configuration RAM 109"
bitfld.long 0x1B4 18. " STXR ,Set Transmit Request" "Not set,Set"
bitfld.long 0x1B4 17. " THTSM ,Transfer Header to System Memory" "No transfer,Transfer"
bitfld.long 0x1B4 16. " TPTSM ,Transfer Payload to System Memory" "No transfer,Transfer"
textline " "
bitfld.long 0x1B4 15. " THTCC ,Transfer Header to Communication Controller" "No transfer,Transfer"
bitfld.long 0x1B4 14. " TPTCC ,Transfer Payload to Communication Controller" "No transfer,Transfer"
hexmask.long.word 0x1B4 0.--13. 1. " TSO ,Transfer Start Offset"
line.long 0x1B8 "TCR110,Transfer Configuration RAM 110"
bitfld.long 0x1B8 18. " STXR ,Set Transmit Request" "Not set,Set"
bitfld.long 0x1B8 17. " THTSM ,Transfer Header to System Memory" "No transfer,Transfer"
bitfld.long 0x1B8 16. " TPTSM ,Transfer Payload to System Memory" "No transfer,Transfer"
textline " "
bitfld.long 0x1B8 15. " THTCC ,Transfer Header to Communication Controller" "No transfer,Transfer"
bitfld.long 0x1B8 14. " TPTCC ,Transfer Payload to Communication Controller" "No transfer,Transfer"
hexmask.long.word 0x1B8 0.--13. 1. " TSO ,Transfer Start Offset"
line.long 0x1BC "TCR111,Transfer Configuration RAM 111"
bitfld.long 0x1BC 18. " STXR ,Set Transmit Request" "Not set,Set"
bitfld.long 0x1BC 17. " THTSM ,Transfer Header to System Memory" "No transfer,Transfer"
bitfld.long 0x1BC 16. " TPTSM ,Transfer Payload to System Memory" "No transfer,Transfer"
textline " "
bitfld.long 0x1BC 15. " THTCC ,Transfer Header to Communication Controller" "No transfer,Transfer"
bitfld.long 0x1BC 14. " TPTCC ,Transfer Payload to Communication Controller" "No transfer,Transfer"
hexmask.long.word 0x1BC 0.--13. 1. " TSO ,Transfer Start Offset"
line.long 0x1C0 "TCR112,Transfer Configuration RAM 112"
bitfld.long 0x1C0 18. " STXR ,Set Transmit Request" "Not set,Set"
bitfld.long 0x1C0 17. " THTSM ,Transfer Header to System Memory" "No transfer,Transfer"
bitfld.long 0x1C0 16. " TPTSM ,Transfer Payload to System Memory" "No transfer,Transfer"
textline " "
bitfld.long 0x1C0 15. " THTCC ,Transfer Header to Communication Controller" "No transfer,Transfer"
bitfld.long 0x1C0 14. " TPTCC ,Transfer Payload to Communication Controller" "No transfer,Transfer"
hexmask.long.word 0x1C0 0.--13. 1. " TSO ,Transfer Start Offset"
line.long 0x1C4 "TCR113,Transfer Configuration RAM 113"
bitfld.long 0x1C4 18. " STXR ,Set Transmit Request" "Not set,Set"
bitfld.long 0x1C4 17. " THTSM ,Transfer Header to System Memory" "No transfer,Transfer"
bitfld.long 0x1C4 16. " TPTSM ,Transfer Payload to System Memory" "No transfer,Transfer"
textline " "
bitfld.long 0x1C4 15. " THTCC ,Transfer Header to Communication Controller" "No transfer,Transfer"
bitfld.long 0x1C4 14. " TPTCC ,Transfer Payload to Communication Controller" "No transfer,Transfer"
hexmask.long.word 0x1C4 0.--13. 1. " TSO ,Transfer Start Offset"
line.long 0x1C8 "TCR114,Transfer Configuration RAM 114"
bitfld.long 0x1C8 18. " STXR ,Set Transmit Request" "Not set,Set"
bitfld.long 0x1C8 17. " THTSM ,Transfer Header to System Memory" "No transfer,Transfer"
bitfld.long 0x1C8 16. " TPTSM ,Transfer Payload to System Memory" "No transfer,Transfer"
textline " "
bitfld.long 0x1C8 15. " THTCC ,Transfer Header to Communication Controller" "No transfer,Transfer"
bitfld.long 0x1C8 14. " TPTCC ,Transfer Payload to Communication Controller" "No transfer,Transfer"
hexmask.long.word 0x1C8 0.--13. 1. " TSO ,Transfer Start Offset"
line.long 0x1CC "TCR115,Transfer Configuration RAM 115"
bitfld.long 0x1CC 18. " STXR ,Set Transmit Request" "Not set,Set"
bitfld.long 0x1CC 17. " THTSM ,Transfer Header to System Memory" "No transfer,Transfer"
bitfld.long 0x1CC 16. " TPTSM ,Transfer Payload to System Memory" "No transfer,Transfer"
textline " "
bitfld.long 0x1CC 15. " THTCC ,Transfer Header to Communication Controller" "No transfer,Transfer"
bitfld.long 0x1CC 14. " TPTCC ,Transfer Payload to Communication Controller" "No transfer,Transfer"
hexmask.long.word 0x1CC 0.--13. 1. " TSO ,Transfer Start Offset"
line.long 0x1D0 "TCR116,Transfer Configuration RAM 116"
bitfld.long 0x1D0 18. " STXR ,Set Transmit Request" "Not set,Set"
bitfld.long 0x1D0 17. " THTSM ,Transfer Header to System Memory" "No transfer,Transfer"
bitfld.long 0x1D0 16. " TPTSM ,Transfer Payload to System Memory" "No transfer,Transfer"
textline " "
bitfld.long 0x1D0 15. " THTCC ,Transfer Header to Communication Controller" "No transfer,Transfer"
bitfld.long 0x1D0 14. " TPTCC ,Transfer Payload to Communication Controller" "No transfer,Transfer"
hexmask.long.word 0x1D0 0.--13. 1. " TSO ,Transfer Start Offset"
line.long 0x1D4 "TCR117,Transfer Configuration RAM 117"
bitfld.long 0x1D4 18. " STXR ,Set Transmit Request" "Not set,Set"
bitfld.long 0x1D4 17. " THTSM ,Transfer Header to System Memory" "No transfer,Transfer"
bitfld.long 0x1D4 16. " TPTSM ,Transfer Payload to System Memory" "No transfer,Transfer"
textline " "
bitfld.long 0x1D4 15. " THTCC ,Transfer Header to Communication Controller" "No transfer,Transfer"
bitfld.long 0x1D4 14. " TPTCC ,Transfer Payload to Communication Controller" "No transfer,Transfer"
hexmask.long.word 0x1D4 0.--13. 1. " TSO ,Transfer Start Offset"
line.long 0x1D8 "TCR118,Transfer Configuration RAM 118"
bitfld.long 0x1D8 18. " STXR ,Set Transmit Request" "Not set,Set"
bitfld.long 0x1D8 17. " THTSM ,Transfer Header to System Memory" "No transfer,Transfer"
bitfld.long 0x1D8 16. " TPTSM ,Transfer Payload to System Memory" "No transfer,Transfer"
textline " "
bitfld.long 0x1D8 15. " THTCC ,Transfer Header to Communication Controller" "No transfer,Transfer"
bitfld.long 0x1D8 14. " TPTCC ,Transfer Payload to Communication Controller" "No transfer,Transfer"
hexmask.long.word 0x1D8 0.--13. 1. " TSO ,Transfer Start Offset"
line.long 0x1DC "TCR119,Transfer Configuration RAM 119"
bitfld.long 0x1DC 18. " STXR ,Set Transmit Request" "Not set,Set"
bitfld.long 0x1DC 17. " THTSM ,Transfer Header to System Memory" "No transfer,Transfer"
bitfld.long 0x1DC 16. " TPTSM ,Transfer Payload to System Memory" "No transfer,Transfer"
textline " "
bitfld.long 0x1DC 15. " THTCC ,Transfer Header to Communication Controller" "No transfer,Transfer"
bitfld.long 0x1DC 14. " TPTCC ,Transfer Payload to Communication Controller" "No transfer,Transfer"
hexmask.long.word 0x1DC 0.--13. 1. " TSO ,Transfer Start Offset"
line.long 0x1E0 "TCR120,Transfer Configuration RAM 120"
bitfld.long 0x1E0 18. " STXR ,Set Transmit Request" "Not set,Set"
bitfld.long 0x1E0 17. " THTSM ,Transfer Header to System Memory" "No transfer,Transfer"
bitfld.long 0x1E0 16. " TPTSM ,Transfer Payload to System Memory" "No transfer,Transfer"
textline " "
bitfld.long 0x1E0 15. " THTCC ,Transfer Header to Communication Controller" "No transfer,Transfer"
bitfld.long 0x1E0 14. " TPTCC ,Transfer Payload to Communication Controller" "No transfer,Transfer"
hexmask.long.word 0x1E0 0.--13. 1. " TSO ,Transfer Start Offset"
line.long 0x1E4 "TCR121,Transfer Configuration RAM 121"
bitfld.long 0x1E4 18. " STXR ,Set Transmit Request" "Not set,Set"
bitfld.long 0x1E4 17. " THTSM ,Transfer Header to System Memory" "No transfer,Transfer"
bitfld.long 0x1E4 16. " TPTSM ,Transfer Payload to System Memory" "No transfer,Transfer"
textline " "
bitfld.long 0x1E4 15. " THTCC ,Transfer Header to Communication Controller" "No transfer,Transfer"
bitfld.long 0x1E4 14. " TPTCC ,Transfer Payload to Communication Controller" "No transfer,Transfer"
hexmask.long.word 0x1E4 0.--13. 1. " TSO ,Transfer Start Offset"
line.long 0x1E8 "TCR122,Transfer Configuration RAM 122"
bitfld.long 0x1E8 18. " STXR ,Set Transmit Request" "Not set,Set"
bitfld.long 0x1E8 17. " THTSM ,Transfer Header to System Memory" "No transfer,Transfer"
bitfld.long 0x1E8 16. " TPTSM ,Transfer Payload to System Memory" "No transfer,Transfer"
textline " "
bitfld.long 0x1E8 15. " THTCC ,Transfer Header to Communication Controller" "No transfer,Transfer"
bitfld.long 0x1E8 14. " TPTCC ,Transfer Payload to Communication Controller" "No transfer,Transfer"
hexmask.long.word 0x1E8 0.--13. 1. " TSO ,Transfer Start Offset"
line.long 0x1EC "TCR123,Transfer Configuration RAM 123"
bitfld.long 0x1EC 18. " STXR ,Set Transmit Request" "Not set,Set"
bitfld.long 0x1EC 17. " THTSM ,Transfer Header to System Memory" "No transfer,Transfer"
bitfld.long 0x1EC 16. " TPTSM ,Transfer Payload to System Memory" "No transfer,Transfer"
textline " "
bitfld.long 0x1EC 15. " THTCC ,Transfer Header to Communication Controller" "No transfer,Transfer"
bitfld.long 0x1EC 14. " TPTCC ,Transfer Payload to Communication Controller" "No transfer,Transfer"
hexmask.long.word 0x1EC 0.--13. 1. " TSO ,Transfer Start Offset"
line.long 0x1F0 "TCR124,Transfer Configuration RAM 124"
bitfld.long 0x1F0 18. " STXR ,Set Transmit Request" "Not set,Set"
bitfld.long 0x1F0 17. " THTSM ,Transfer Header to System Memory" "No transfer,Transfer"
bitfld.long 0x1F0 16. " TPTSM ,Transfer Payload to System Memory" "No transfer,Transfer"
textline " "
bitfld.long 0x1F0 15. " THTCC ,Transfer Header to Communication Controller" "No transfer,Transfer"
bitfld.long 0x1F0 14. " TPTCC ,Transfer Payload to Communication Controller" "No transfer,Transfer"
hexmask.long.word 0x1F0 0.--13. 1. " TSO ,Transfer Start Offset"
line.long 0x1F4 "TCR125,Transfer Configuration RAM 125"
bitfld.long 0x1F4 18. " STXR ,Set Transmit Request" "Not set,Set"
bitfld.long 0x1F4 17. " THTSM ,Transfer Header to System Memory" "No transfer,Transfer"
bitfld.long 0x1F4 16. " TPTSM ,Transfer Payload to System Memory" "No transfer,Transfer"
textline " "
bitfld.long 0x1F4 15. " THTCC ,Transfer Header to Communication Controller" "No transfer,Transfer"
bitfld.long 0x1F4 14. " TPTCC ,Transfer Payload to Communication Controller" "No transfer,Transfer"
hexmask.long.word 0x1F4 0.--13. 1. " TSO ,Transfer Start Offset"
line.long 0x1F8 "TCR126,Transfer Configuration RAM 126"
bitfld.long 0x1F8 18. " STXR ,Set Transmit Request" "Not set,Set"
bitfld.long 0x1F8 17. " THTSM ,Transfer Header to System Memory" "No transfer,Transfer"
bitfld.long 0x1F8 16. " TPTSM ,Transfer Payload to System Memory" "No transfer,Transfer"
textline " "
bitfld.long 0x1F8 15. " THTCC ,Transfer Header to Communication Controller" "No transfer,Transfer"
bitfld.long 0x1F8 14. " TPTCC ,Transfer Payload to Communication Controller" "No transfer,Transfer"
hexmask.long.word 0x1F8 0.--13. 1. " TSO ,Transfer Start Offset"
line.long 0x1FC "TCR127,Transfer Configuration RAM 127"
bitfld.long 0x1FC 18. " STXR ,Set Transmit Request" "Not set,Set"
bitfld.long 0x1FC 17. " THTSM ,Transfer Header to System Memory" "No transfer,Transfer"
bitfld.long 0x1FC 16. " TPTSM ,Transfer Payload to System Memory" "No transfer,Transfer"
textline " "
bitfld.long 0x1FC 15. " THTCC ,Transfer Header to Communication Controller" "No transfer,Transfer"
bitfld.long 0x1FC 14. " TPTCC ,Transfer Payload to Communication Controller" "No transfer,Transfer"
hexmask.long.word 0x1FC 0.--13. 1. " TSO ,Transfer Start Offset"
tree.end
tree "TCR ECC Test Mode"
group.long 0x200++0x1ff
line.long 0x0 "TCRE0,TCR Parity Test Mode 0"
hexmask.long.byte 0x0 0.--5. 1. " ECCINF ,ECC Data of TCR RAM location 0"
line.long 0x4 "TCRE1,TCR Parity Test Mode 1"
hexmask.long.byte 0x4 0.--5. 1. " ECCINF ,ECC Data of TCR RAM location 1"
line.long 0x8 "TCRE2,TCR Parity Test Mode 2"
hexmask.long.byte 0x8 0.--5. 1. " ECCINF ,ECC Data of TCR RAM location 2"
line.long 0xC "TCRE3,TCR Parity Test Mode 3"
hexmask.long.byte 0xC 0.--5. 1. " ECCINF ,ECC Data of TCR RAM location 3"
line.long 0x10 "TCRE4,TCR Parity Test Mode 4"
hexmask.long.byte 0x10 0.--5. 1. " ECCINF ,ECC Data of TCR RAM location 4"
line.long 0x14 "TCRE5,TCR Parity Test Mode 5"
hexmask.long.byte 0x14 0.--5. 1. " ECCINF ,ECC Data of TCR RAM location 5"
line.long 0x18 "TCRE6,TCR Parity Test Mode 6"
hexmask.long.byte 0x18 0.--5. 1. " ECCINF ,ECC Data of TCR RAM location 6"
line.long 0x1C "TCRE7,TCR Parity Test Mode 7"
hexmask.long.byte 0x1C 0.--5. 1. " ECCINF ,ECC Data of TCR RAM location 7"
line.long 0x20 "TCRE8,TCR Parity Test Mode 8"
hexmask.long.byte 0x20 0.--5. 1. " ECCINF ,ECC Data of TCR RAM location 8"
line.long 0x24 "TCRE9,TCR Parity Test Mode 9"
hexmask.long.byte 0x24 0.--5. 1. " ECCINF ,ECC Data of TCR RAM location 9"
line.long 0x28 "TCRE10,TCR Parity Test Mode 10"
hexmask.long.byte 0x28 0.--5. 1. " ECCINF ,ECC Data of TCR RAM location 10"
line.long 0x2C "TCRE11,TCR Parity Test Mode 11"
hexmask.long.byte 0x2C 0.--5. 1. " ECCINF ,ECC Data of TCR RAM location 11"
line.long 0x30 "TCRE12,TCR Parity Test Mode 12"
hexmask.long.byte 0x30 0.--5. 1. " ECCINF ,ECC Data of TCR RAM location 12"
line.long 0x34 "TCRE13,TCR Parity Test Mode 13"
hexmask.long.byte 0x34 0.--5. 1. " ECCINF ,ECC Data of TCR RAM location 13"
line.long 0x38 "TCRE14,TCR Parity Test Mode 14"
hexmask.long.byte 0x38 0.--5. 1. " ECCINF ,ECC Data of TCR RAM location 14"
line.long 0x3C "TCRE15,TCR Parity Test Mode 15"
hexmask.long.byte 0x3C 0.--5. 1. " ECCINF ,ECC Data of TCR RAM location 15"
line.long 0x40 "TCRE16,TCR Parity Test Mode 16"
hexmask.long.byte 0x40 0.--5. 1. " ECCINF ,ECC Data of TCR RAM location 16"
line.long 0x44 "TCRE17,TCR Parity Test Mode 17"
hexmask.long.byte 0x44 0.--5. 1. " ECCINF ,ECC Data of TCR RAM location 17"
line.long 0x48 "TCRE18,TCR Parity Test Mode 18"
hexmask.long.byte 0x48 0.--5. 1. " ECCINF ,ECC Data of TCR RAM location 18"
line.long 0x4C "TCRE19,TCR Parity Test Mode 19"
hexmask.long.byte 0x4C 0.--5. 1. " ECCINF ,ECC Data of TCR RAM location 19"
line.long 0x50 "TCRE20,TCR Parity Test Mode 20"
hexmask.long.byte 0x50 0.--5. 1. " ECCINF ,ECC Data of TCR RAM location 20"
line.long 0x54 "TCRE21,TCR Parity Test Mode 21"
hexmask.long.byte 0x54 0.--5. 1. " ECCINF ,ECC Data of TCR RAM location 21"
line.long 0x58 "TCRE22,TCR Parity Test Mode 22"
hexmask.long.byte 0x58 0.--5. 1. " ECCINF ,ECC Data of TCR RAM location 22"
line.long 0x5C "TCRE23,TCR Parity Test Mode 23"
hexmask.long.byte 0x5C 0.--5. 1. " ECCINF ,ECC Data of TCR RAM location 23"
line.long 0x60 "TCRE24,TCR Parity Test Mode 24"
hexmask.long.byte 0x60 0.--5. 1. " ECCINF ,ECC Data of TCR RAM location 24"
line.long 0x64 "TCRE25,TCR Parity Test Mode 25"
hexmask.long.byte 0x64 0.--5. 1. " ECCINF ,ECC Data of TCR RAM location 25"
line.long 0x68 "TCRE26,TCR Parity Test Mode 26"
hexmask.long.byte 0x68 0.--5. 1. " ECCINF ,ECC Data of TCR RAM location 26"
line.long 0x6C "TCRE27,TCR Parity Test Mode 27"
hexmask.long.byte 0x6C 0.--5. 1. " ECCINF ,ECC Data of TCR RAM location 27"
line.long 0x70 "TCRE28,TCR Parity Test Mode 28"
hexmask.long.byte 0x70 0.--5. 1. " ECCINF ,ECC Data of TCR RAM location 28"
line.long 0x74 "TCRE29,TCR Parity Test Mode 29"
hexmask.long.byte 0x74 0.--5. 1. " ECCINF ,ECC Data of TCR RAM location 29"
line.long 0x78 "TCRE30,TCR Parity Test Mode 30"
hexmask.long.byte 0x78 0.--5. 1. " ECCINF ,ECC Data of TCR RAM location 30"
line.long 0x7C "TCRE31,TCR Parity Test Mode 31"
hexmask.long.byte 0x7C 0.--5. 1. " ECCINF ,ECC Data of TCR RAM location 31"
line.long 0x80 "TCRE32,TCR Parity Test Mode 32"
hexmask.long.byte 0x80 0.--5. 1. " ECCINF ,ECC Data of TCR RAM location 32"
line.long 0x84 "TCRE33,TCR Parity Test Mode 33"
hexmask.long.byte 0x84 0.--5. 1. " ECCINF ,ECC Data of TCR RAM location 33"
line.long 0x88 "TCRE34,TCR Parity Test Mode 34"
hexmask.long.byte 0x88 0.--5. 1. " ECCINF ,ECC Data of TCR RAM location 34"
line.long 0x8C "TCRE35,TCR Parity Test Mode 35"
hexmask.long.byte 0x8C 0.--5. 1. " ECCINF ,ECC Data of TCR RAM location 35"
line.long 0x90 "TCRE36,TCR Parity Test Mode 36"
hexmask.long.byte 0x90 0.--5. 1. " ECCINF ,ECC Data of TCR RAM location 36"
line.long 0x94 "TCRE37,TCR Parity Test Mode 37"
hexmask.long.byte 0x94 0.--5. 1. " ECCINF ,ECC Data of TCR RAM location 37"
line.long 0x98 "TCRE38,TCR Parity Test Mode 38"
hexmask.long.byte 0x98 0.--5. 1. " ECCINF ,ECC Data of TCR RAM location 38"
line.long 0x9C "TCRE39,TCR Parity Test Mode 39"
hexmask.long.byte 0x9C 0.--5. 1. " ECCINF ,ECC Data of TCR RAM location 39"
line.long 0xA0 "TCRE40,TCR Parity Test Mode 40"
hexmask.long.byte 0xA0 0.--5. 1. " ECCINF ,ECC Data of TCR RAM location 40"
line.long 0xA4 "TCRE41,TCR Parity Test Mode 41"
hexmask.long.byte 0xA4 0.--5. 1. " ECCINF ,ECC Data of TCR RAM location 41"
line.long 0xA8 "TCRE42,TCR Parity Test Mode 42"
hexmask.long.byte 0xA8 0.--5. 1. " ECCINF ,ECC Data of TCR RAM location 42"
line.long 0xAC "TCRE43,TCR Parity Test Mode 43"
hexmask.long.byte 0xAC 0.--5. 1. " ECCINF ,ECC Data of TCR RAM location 43"
line.long 0xB0 "TCRE44,TCR Parity Test Mode 44"
hexmask.long.byte 0xB0 0.--5. 1. " ECCINF ,ECC Data of TCR RAM location 44"
line.long 0xB4 "TCRE45,TCR Parity Test Mode 45"
hexmask.long.byte 0xB4 0.--5. 1. " ECCINF ,ECC Data of TCR RAM location 45"
line.long 0xB8 "TCRE46,TCR Parity Test Mode 46"
hexmask.long.byte 0xB8 0.--5. 1. " ECCINF ,ECC Data of TCR RAM location 46"
line.long 0xBC "TCRE47,TCR Parity Test Mode 47"
hexmask.long.byte 0xBC 0.--5. 1. " ECCINF ,ECC Data of TCR RAM location 47"
line.long 0xC0 "TCRE48,TCR Parity Test Mode 48"
hexmask.long.byte 0xC0 0.--5. 1. " ECCINF ,ECC Data of TCR RAM location 48"
line.long 0xC4 "TCRE49,TCR Parity Test Mode 49"
hexmask.long.byte 0xC4 0.--5. 1. " ECCINF ,ECC Data of TCR RAM location 49"
line.long 0xC8 "TCRE50,TCR Parity Test Mode 50"
hexmask.long.byte 0xC8 0.--5. 1. " ECCINF ,ECC Data of TCR RAM location 50"
line.long 0xCC "TCRE51,TCR Parity Test Mode 51"
hexmask.long.byte 0xCC 0.--5. 1. " ECCINF ,ECC Data of TCR RAM location 51"
line.long 0xD0 "TCRE52,TCR Parity Test Mode 52"
hexmask.long.byte 0xD0 0.--5. 1. " ECCINF ,ECC Data of TCR RAM location 52"
line.long 0xD4 "TCRE53,TCR Parity Test Mode 53"
hexmask.long.byte 0xD4 0.--5. 1. " ECCINF ,ECC Data of TCR RAM location 53"
line.long 0xD8 "TCRE54,TCR Parity Test Mode 54"
hexmask.long.byte 0xD8 0.--5. 1. " ECCINF ,ECC Data of TCR RAM location 54"
line.long 0xDC "TCRE55,TCR Parity Test Mode 55"
hexmask.long.byte 0xDC 0.--5. 1. " ECCINF ,ECC Data of TCR RAM location 55"
line.long 0xE0 "TCRE56,TCR Parity Test Mode 56"
hexmask.long.byte 0xE0 0.--5. 1. " ECCINF ,ECC Data of TCR RAM location 56"
line.long 0xE4 "TCRE57,TCR Parity Test Mode 57"
hexmask.long.byte 0xE4 0.--5. 1. " ECCINF ,ECC Data of TCR RAM location 57"
line.long 0xE8 "TCRE58,TCR Parity Test Mode 58"
hexmask.long.byte 0xE8 0.--5. 1. " ECCINF ,ECC Data of TCR RAM location 58"
line.long 0xEC "TCRE59,TCR Parity Test Mode 59"
hexmask.long.byte 0xEC 0.--5. 1. " ECCINF ,ECC Data of TCR RAM location 59"
line.long 0xF0 "TCRE60,TCR Parity Test Mode 60"
hexmask.long.byte 0xF0 0.--5. 1. " ECCINF ,ECC Data of TCR RAM location 60"
line.long 0xF4 "TCRE61,TCR Parity Test Mode 61"
hexmask.long.byte 0xF4 0.--5. 1. " ECCINF ,ECC Data of TCR RAM location 61"
line.long 0xF8 "TCRE62,TCR Parity Test Mode 62"
hexmask.long.byte 0xF8 0.--5. 1. " ECCINF ,ECC Data of TCR RAM location 62"
line.long 0xFC "TCRE63,TCR Parity Test Mode 63"
hexmask.long.byte 0xFC 0.--5. 1. " ECCINF ,ECC Data of TCR RAM location 63"
line.long 0x100 "TCRE64,TCR Parity Test Mode 64"
hexmask.long.byte 0x100 0.--5. 1. " ECCINF ,ECC Data of TCR RAM location 64"
line.long 0x104 "TCRE65,TCR Parity Test Mode 65"
hexmask.long.byte 0x104 0.--5. 1. " ECCINF ,ECC Data of TCR RAM location 65"
line.long 0x108 "TCRE66,TCR Parity Test Mode 66"
hexmask.long.byte 0x108 0.--5. 1. " ECCINF ,ECC Data of TCR RAM location 66"
line.long 0x10C "TCRE67,TCR Parity Test Mode 67"
hexmask.long.byte 0x10C 0.--5. 1. " ECCINF ,ECC Data of TCR RAM location 67"
line.long 0x110 "TCRE68,TCR Parity Test Mode 68"
hexmask.long.byte 0x110 0.--5. 1. " ECCINF ,ECC Data of TCR RAM location 68"
line.long 0x114 "TCRE69,TCR Parity Test Mode 69"
hexmask.long.byte 0x114 0.--5. 1. " ECCINF ,ECC Data of TCR RAM location 69"
line.long 0x118 "TCRE70,TCR Parity Test Mode 70"
hexmask.long.byte 0x118 0.--5. 1. " ECCINF ,ECC Data of TCR RAM location 70"
line.long 0x11C "TCRE71,TCR Parity Test Mode 71"
hexmask.long.byte 0x11C 0.--5. 1. " ECCINF ,ECC Data of TCR RAM location 71"
line.long 0x120 "TCRE72,TCR Parity Test Mode 72"
hexmask.long.byte 0x120 0.--5. 1. " ECCINF ,ECC Data of TCR RAM location 72"
line.long 0x124 "TCRE73,TCR Parity Test Mode 73"
hexmask.long.byte 0x124 0.--5. 1. " ECCINF ,ECC Data of TCR RAM location 73"
line.long 0x128 "TCRE74,TCR Parity Test Mode 74"
hexmask.long.byte 0x128 0.--5. 1. " ECCINF ,ECC Data of TCR RAM location 74"
line.long 0x12C "TCRE75,TCR Parity Test Mode 75"
hexmask.long.byte 0x12C 0.--5. 1. " ECCINF ,ECC Data of TCR RAM location 75"
line.long 0x130 "TCRE76,TCR Parity Test Mode 76"
hexmask.long.byte 0x130 0.--5. 1. " ECCINF ,ECC Data of TCR RAM location 76"
line.long 0x134 "TCRE77,TCR Parity Test Mode 77"
hexmask.long.byte 0x134 0.--5. 1. " ECCINF ,ECC Data of TCR RAM location 77"
line.long 0x138 "TCRE78,TCR Parity Test Mode 78"
hexmask.long.byte 0x138 0.--5. 1. " ECCINF ,ECC Data of TCR RAM location 78"
line.long 0x13C "TCRE79,TCR Parity Test Mode 79"
hexmask.long.byte 0x13C 0.--5. 1. " ECCINF ,ECC Data of TCR RAM location 79"
line.long 0x140 "TCRE80,TCR Parity Test Mode 80"
hexmask.long.byte 0x140 0.--5. 1. " ECCINF ,ECC Data of TCR RAM location 80"
line.long 0x144 "TCRE81,TCR Parity Test Mode 81"
hexmask.long.byte 0x144 0.--5. 1. " ECCINF ,ECC Data of TCR RAM location 81"
line.long 0x148 "TCRE82,TCR Parity Test Mode 82"
hexmask.long.byte 0x148 0.--5. 1. " ECCINF ,ECC Data of TCR RAM location 82"
line.long 0x14C "TCRE83,TCR Parity Test Mode 83"
hexmask.long.byte 0x14C 0.--5. 1. " ECCINF ,ECC Data of TCR RAM location 83"
line.long 0x150 "TCRE84,TCR Parity Test Mode 84"
hexmask.long.byte 0x150 0.--5. 1. " ECCINF ,ECC Data of TCR RAM location 84"
line.long 0x154 "TCRE85,TCR Parity Test Mode 85"
hexmask.long.byte 0x154 0.--5. 1. " ECCINF ,ECC Data of TCR RAM location 85"
line.long 0x158 "TCRE86,TCR Parity Test Mode 86"
hexmask.long.byte 0x158 0.--5. 1. " ECCINF ,ECC Data of TCR RAM location 86"
line.long 0x15C "TCRE87,TCR Parity Test Mode 87"
hexmask.long.byte 0x15C 0.--5. 1. " ECCINF ,ECC Data of TCR RAM location 87"
line.long 0x160 "TCRE88,TCR Parity Test Mode 88"
hexmask.long.byte 0x160 0.--5. 1. " ECCINF ,ECC Data of TCR RAM location 88"
line.long 0x164 "TCRE89,TCR Parity Test Mode 89"
hexmask.long.byte 0x164 0.--5. 1. " ECCINF ,ECC Data of TCR RAM location 89"
line.long 0x168 "TCRE90,TCR Parity Test Mode 90"
hexmask.long.byte 0x168 0.--5. 1. " ECCINF ,ECC Data of TCR RAM location 90"
line.long 0x16C "TCRE91,TCR Parity Test Mode 91"
hexmask.long.byte 0x16C 0.--5. 1. " ECCINF ,ECC Data of TCR RAM location 91"
line.long 0x170 "TCRE92,TCR Parity Test Mode 92"
hexmask.long.byte 0x170 0.--5. 1. " ECCINF ,ECC Data of TCR RAM location 92"
line.long 0x174 "TCRE93,TCR Parity Test Mode 93"
hexmask.long.byte 0x174 0.--5. 1. " ECCINF ,ECC Data of TCR RAM location 93"
line.long 0x178 "TCRE94,TCR Parity Test Mode 94"
hexmask.long.byte 0x178 0.--5. 1. " ECCINF ,ECC Data of TCR RAM location 94"
line.long 0x17C "TCRE95,TCR Parity Test Mode 95"
hexmask.long.byte 0x17C 0.--5. 1. " ECCINF ,ECC Data of TCR RAM location 95"
line.long 0x180 "TCRE96,TCR Parity Test Mode 96"
hexmask.long.byte 0x180 0.--5. 1. " ECCINF ,ECC Data of TCR RAM location 96"
line.long 0x184 "TCRE97,TCR Parity Test Mode 97"
hexmask.long.byte 0x184 0.--5. 1. " ECCINF ,ECC Data of TCR RAM location 97"
line.long 0x188 "TCRE98,TCR Parity Test Mode 98"
hexmask.long.byte 0x188 0.--5. 1. " ECCINF ,ECC Data of TCR RAM location 98"
line.long 0x18C "TCRE99,TCR Parity Test Mode 99"
hexmask.long.byte 0x18C 0.--5. 1. " ECCINF ,ECC Data of TCR RAM location 99"
line.long 0x190 "TCRE100,TCR Parity Test Mode 100"
hexmask.long.byte 0x190 0.--5. 1. " ECCINF ,ECC Data of TCR RAM location 100"
line.long 0x194 "TCRE101,TCR Parity Test Mode 101"
hexmask.long.byte 0x194 0.--5. 1. " ECCINF ,ECC Data of TCR RAM location 101"
line.long 0x198 "TCRE102,TCR Parity Test Mode 102"
hexmask.long.byte 0x198 0.--5. 1. " ECCINF ,ECC Data of TCR RAM location 102"
line.long 0x19C "TCRE103,TCR Parity Test Mode 103"
hexmask.long.byte 0x19C 0.--5. 1. " ECCINF ,ECC Data of TCR RAM location 103"
line.long 0x1A0 "TCRE104,TCR Parity Test Mode 104"
hexmask.long.byte 0x1A0 0.--5. 1. " ECCINF ,ECC Data of TCR RAM location 104"
line.long 0x1A4 "TCRE105,TCR Parity Test Mode 105"
hexmask.long.byte 0x1A4 0.--5. 1. " ECCINF ,ECC Data of TCR RAM location 105"
line.long 0x1A8 "TCRE106,TCR Parity Test Mode 106"
hexmask.long.byte 0x1A8 0.--5. 1. " ECCINF ,ECC Data of TCR RAM location 106"
line.long 0x1AC "TCRE107,TCR Parity Test Mode 107"
hexmask.long.byte 0x1AC 0.--5. 1. " ECCINF ,ECC Data of TCR RAM location 107"
line.long 0x1B0 "TCRE108,TCR Parity Test Mode 108"
hexmask.long.byte 0x1B0 0.--5. 1. " ECCINF ,ECC Data of TCR RAM location 108"
line.long 0x1B4 "TCRE109,TCR Parity Test Mode 109"
hexmask.long.byte 0x1B4 0.--5. 1. " ECCINF ,ECC Data of TCR RAM location 109"
line.long 0x1B8 "TCRE110,TCR Parity Test Mode 110"
hexmask.long.byte 0x1B8 0.--5. 1. " ECCINF ,ECC Data of TCR RAM location 110"
line.long 0x1BC "TCRE111,TCR Parity Test Mode 111"
hexmask.long.byte 0x1BC 0.--5. 1. " ECCINF ,ECC Data of TCR RAM location 111"
line.long 0x1C0 "TCRE112,TCR Parity Test Mode 112"
hexmask.long.byte 0x1C0 0.--5. 1. " ECCINF ,ECC Data of TCR RAM location 112"
line.long 0x1C4 "TCRE113,TCR Parity Test Mode 113"
hexmask.long.byte 0x1C4 0.--5. 1. " ECCINF ,ECC Data of TCR RAM location 113"
line.long 0x1C8 "TCRE114,TCR Parity Test Mode 114"
hexmask.long.byte 0x1C8 0.--5. 1. " ECCINF ,ECC Data of TCR RAM location 114"
line.long 0x1CC "TCRE115,TCR Parity Test Mode 115"
hexmask.long.byte 0x1CC 0.--5. 1. " ECCINF ,ECC Data of TCR RAM location 115"
line.long 0x1D0 "TCRE116,TCR Parity Test Mode 116"
hexmask.long.byte 0x1D0 0.--5. 1. " ECCINF ,ECC Data of TCR RAM location 116"
line.long 0x1D4 "TCRE117,TCR Parity Test Mode 117"
hexmask.long.byte 0x1D4 0.--5. 1. " ECCINF ,ECC Data of TCR RAM location 117"
line.long 0x1D8 "TCRE118,TCR Parity Test Mode 118"
hexmask.long.byte 0x1D8 0.--5. 1. " ECCINF ,ECC Data of TCR RAM location 118"
line.long 0x1DC "TCRE119,TCR Parity Test Mode 119"
hexmask.long.byte 0x1DC 0.--5. 1. " ECCINF ,ECC Data of TCR RAM location 119"
line.long 0x1E0 "TCRE120,TCR Parity Test Mode 120"
hexmask.long.byte 0x1E0 0.--5. 1. " ECCINF ,ECC Data of TCR RAM location 120"
line.long 0x1E4 "TCRE121,TCR Parity Test Mode 121"
hexmask.long.byte 0x1E4 0.--5. 1. " ECCINF ,ECC Data of TCR RAM location 121"
line.long 0x1E8 "TCRE122,TCR Parity Test Mode 122"
hexmask.long.byte 0x1E8 0.--5. 1. " ECCINF ,ECC Data of TCR RAM location 122"
line.long 0x1EC "TCRE123,TCR Parity Test Mode 123"
hexmask.long.byte 0x1EC 0.--5. 1. " ECCINF ,ECC Data of TCR RAM location 123"
line.long 0x1F0 "TCRE124,TCR Parity Test Mode 124"
hexmask.long.byte 0x1F0 0.--5. 1. " ECCINF ,ECC Data of TCR RAM location 124"
line.long 0x1F4 "TCRE125,TCR Parity Test Mode 125"
hexmask.long.byte 0x1F4 0.--5. 1. " ECCINF ,ECC Data of TCR RAM location 125"
line.long 0x1F8 "TCRE126,TCR Parity Test Mode 126"
hexmask.long.byte 0x1F8 0.--5. 1. " ECCINF ,ECC Data of TCR RAM location 126"
line.long 0x1FC "TCRE127,TCR Parity Test Mode 127"
hexmask.long.byte 0x1FC 0.--5. 1. " ECCINF ,ECC Data of TCR RAM location 127"
tree.end
tree.end
width 0xb
tree.end
tree "Communication Controller"
base ad:0xFFF7C800
width 10.
tree "Special registers"
group.long 0x00++0x0B
line.long 0x00 "ECC_CTRL, ECC Control Register"
bitfld.long 0x00 24.--27. " SBE_EVT_EN , ECC Single Bit Error Indication" "Enabled,Enabled,Enabled,Enabled,Enabled,Disabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled"
bitfld.long 0x00 16.--19. " SBEL , ECC Single Bit Error Lock" "Enabled,Enabled,Enabled,Enabled,Enabled,Disabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled"
textline " "
bitfld.long 0x00 0.--3. " DIAGSEL , Diagnostic Mode select Key" "Disabled,Disabled,Disabled,Disabled,Disabled,Enabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled"
line.long 0x04 "ECCDSTAT, ECC Diagnostic Status Register"
eventfld.long 0x04 23. " DEFH , ECC Double Bit Error Flag for FTU RAM" "No error,Error"
eventfld.long 0x04 22. " DEFG , ECC Double Bit Error Flag for FlexRay Message RAM" "No error,Error"
eventfld.long 0x04 21. " DEFF , ECC Double Bit Error Flag for Transient Buffer B RAM" "No error,Error"
eventfld.long 0x04 20. " DEFE , ECC Double Bit Error Flag for Transient Buffer A RAM" "No error,Error"
textline " "
eventfld.long 0x04 19. " DEFD , ECC Double Bit Error Flag for Output Buffer 2 RAM" "No error,Error"
eventfld.long 0x04 18. " DEFC , ECC Double Bit Error Flag for Output Buffer 1 RAM" "No error,Error"
eventfld.long 0x04 17. " DEFB , ECC Double Bit Error Flag for Input Buffer 2 RAM" "No error,Error"
eventfld.long 0x04 16. " DEFA , ECC Double Bit Error Flag for Input Buffer 1 RAM" "No error,Error"
textline " "
eventfld.long 0x04 7. " SEFH , ECC Single Bit Error Flag for FTU RAM" "No error,Error"
eventfld.long 0x04 6. " SEFG , ECC Single Bit Error Flag for FlexRay Message RAM" "No error,Error"
eventfld.long 0x04 5. " SEFF , ECC Single Bit Error Flag for Transient Buffer B RAM" "No error,Error"
eventfld.long 0x04 4. " SEFE , ECC Single Bit Error Flag for Transient Buffer A RAM" "No error,Error"
textline " "
eventfld.long 0x04 3. " SEFD , ECC Single Bit Error Flag for Output Buffer 2 RAM" "No error,Error"
eventfld.long 0x04 2. " SEFC , ECC Single Bit Error Flag for Output Buffer 1 RAM" "No error,Error"
eventfld.long 0x04 1. " SEFB , ECC Single Bit Error Flag for Input Buffer 2 RAM" "No error,Error"
eventfld.long 0x04 0. " SEFB , ECC Single Bit Error Flag for Input Buffer 1 RAM" "No error,Error"
line.long 0x08 "ECCTEST, ECC Test Register"
hexmask.long.byte 0x08 16.--22. 1. " RDECC , Holds ECC bits when reading a RAM location"
hexmask.long.byte 0x08 0.--6. 1. " WRECC , ECC bits to be written in ECC location when writing to a RAM location"
if (d.l(ad:0xFFF7C800+0x0C)&0x3D)==(0x21||0x24||0x28||0x30)
group.long 0x0C++0x03
line.long 0x00 "SBESTAT, Single Bit Error Status Register"
eventfld.long 0x00 31. " SBE , ECC Single Bit Error" "No error,Error"
hexmask.long.byte 0x00 8.--14. 1. " FMB , Faulty message buffer"
textline " "
eventfld.long 0x00 6. " MFMB , Multiple message buffers with ECC single bit error fault detected" "Not detected,Detected"
eventfld.long 0x00 5. " FMBD , Message buffer with ECC single bit error fault detected" "Not detected,Detected"
textline " "
eventfld.long 0x00 4. " STBF2 , ECC single bit error in transient buffer RAM B" "No error,Error"
eventfld.long 0x00 3. " STBF1 , ECC single bit error in transient buffer RAM A" "No error,Error"
textline " "
eventfld.long 0x00 2. " SMR , ECC single bit error in message RAM" "No error,Error"
eventfld.long 0x00 1. " SOBF , ECC single bit error in output buffer RAM 1, 2" "No error,Error"
eventfld.long 0x00 0. " SIBF , ECC single bit error in input buffer RAM 1, 2" "No error,Error"
else
group.long 0x0C++0x03
line.long 0x00 "SBESTAT, Single Bit Error Status Register"
eventfld.long 0x00 31. " SBE , ECC Single Bit Error" "No error,Error"
textline " "
eventfld.long 0x00 6. " MFMB , Multiple message buffers with ECC single bit error fault detected" "Not detected,Detected"
eventfld.long 0x00 5. " FMBD , Message buffer with ECC single bit error fault detected" "Not detected,Detected"
textline " "
eventfld.long 0x00 4. " STBF2 , ECC single bit error in transient buffer RAM B" "No error,Error"
eventfld.long 0x00 3. " STBF1 , ECC single bit error in transient buffer RAM A" "No error,Error"
textline " "
eventfld.long 0x00 2. " SMR , ECC single bit error in message RAM" "No error,Error"
eventfld.long 0x00 1. " SOBF , ECC single bit error in output buffer RAM 1, 2" "No error,Error"
eventfld.long 0x00 0. " SIBF , ECC single bit error in input buffer RAM 1, 2" "No error,Error"
endif
width 7.
group.long 0x10++0x3
line.long 0x0 "TEST1,Test register 1"
rbitfld.long 0x00 28.--31. " CERB ,Coding Error Report Channel B" "No error,Header CRC,Frame CRC,FSS too long,1st BSS seen LOW,2nd BSS seen HIGH,1st FES seen HIGH,2nd FES seen LOW,CAS/MTS too short,CAS/MTS too long,?..."
rbitfld.long 0x00 24.--27. " CERA ,Coding Error Report Channel A" "No error,Header CRC,Frame CRC,FSS too long,1st BSS seen LOW,2nd BSS seen HIGH,1st FES seen HIGH,2nd FES seen LOW,CAS/MTS too short,CAS/MTS too long,?..."
bitfld.long 0x00 21. " TXENB ,Control of channel B transmit enable pin (txen2)" "Disabled,Enabled"
textline " "
bitfld.long 0x00 20. " TXENA ,Control of channel A transmit enable pin (txen1)" "Disabled,Enabled"
bitfld.long 0x00 19. " TXB ,Control of channel B transmit pin (txd2)" "Low,High"
bitfld.long 0x00 18. " TXA ,Control of channel A transmit pin (txd1)" "Low,High"
textline " "
rbitfld.long 0x00 17. " RXB ,Monitor channel B receive pin (rxd2)" "Low,High"
rbitfld.long 0x00 16. " RXA ,Monitor channel A receive pin (rxd1)" "Low,High"
bitfld.long 0x00 9. " AOB ,Activity on B" "No activity,Activity"
textline " "
bitfld.long 0x00 8. " AOA ,Activity on A" "No activity,Activity"
bitfld.long 0x00 4.--5. " TMC ,Test mode control" "Normal,RAM,I/O,?..."
bitfld.long 0x00 1. " ELBE ,External Loop Back Enable" "Internal,External"
textline " "
bitfld.long 0x00 0. " WRTEN ,Write test register enable" "Disabled,Enabled"
if (((d.l(ad:0xFFF7C800+0x10))&0x01)==0x00)
rgroup.long 0x14++0x3
line.long 0x0 "TEST2,Test register 2"
bitfld.long 0x00 15. " RDPB ,Read parity bit" "No parity,Parity"
bitfld.long 0x00 14. " WRPB ,Write parity bit" "No parity,Parity"
bitfld.long 0x00 4.--6. " SSEL ,Segment select" "0x0000 to 0x03FF,0x0400 to 0x07FF,0x0800 to 0x0BFF,0x0C00 to 0x0FFF,0x1000 to 0x13FF,0x1400 to 0x17FF,0x1800 to 0x1BFF,0x1C00 to 0x1FFF"
textline " "
bitfld.long 0x00 0.--2. " RS ,RAM select" "IBF1,IBF2,OBF1,OBF2,TBF1,TBF2,MBF,?..."
else
group.long 0x14++0x3
line.long 0x0 "TEST2,Test register 2"
bitfld.long 0x00 15. " RDPB ,Read parity bit" "No parity,Parity"
bitfld.long 0x00 14. " WRPB ,Write parity bit" "No parity,Parity"
bitfld.long 0x00 4.--6. " SSEL ,Segment select" "0x0000 to 0x03FF,0x0400 to 0x07FF,0x0800 to 0x0BFF,0x0C00 to 0x0FFF,0x1000 to 0x13FF,0x1400 to 0x17FF,0x1800 to 0x1BFF,0x1C00 to 0x1FFF"
textline " "
bitfld.long 0x00 0.--2. " RS ,RAM select" "IBF1,IBF2,OBF1,OBF2,TBF1,TBF2,MBF,?..."
endif
group.long 0x1C++0x3
line.long 0x0 "LCK,Lock register"
hexmask.long.byte 0x00 8.--15. 1. " TMK ,Test mode key"
hexmask.long.byte 0x00 0.--7. 1. " CLK ,Configuration lock key"
tree.end
width 7.
tree "Interrupt registers"
group.long 0x20++0x13
line.long 0x0 "EIR,Error interrupt register"
eventfld.long 0x00 26. " TABB ,Transmission Across Boundary Channel B" "Not occurred,Occurred"
eventfld.long 0x00 25. " LTVB ,Latest Transmit Violation Channel B" "No violation,Violation"
eventfld.long 0x00 24. " EDB ,Error Detected on Channel B" "No error,Error"
textline " "
eventfld.long 0x00 18. " TABA ,Transmission Across Boundary Channel A" "Not occurred,Occurred"
eventfld.long 0x00 17. " LTVA ,Latest Transmit Violation Channel A" "No violation,Violation"
eventfld.long 0x00 16. " EDA ,Error Detected on Channel A" "No error,Error"
textline " "
eventfld.long 0x00 11. " MHF ,Message Handler Constraints Flag" "Not occurred,Occurred"
eventfld.long 0x00 10. " IOBA ,Illegal Output Buffer Access" "Not occurred,Occurred"
eventfld.long 0x00 9. " IIBA ,Illegal Input Buffer Access" "Not occurred,Occurred"
textline " "
eventfld.long 0x00 8. " EFA ,Empty FIFO Access" "Not occurred,Occurred"
eventfld.long 0x00 7. " RFO ,Receive FIFO Overrun" "No overrun,Overrun"
eventfld.long 0x00 6. " PERR ,Parity Error" "No error,Error"
textline " "
eventfld.long 0x00 5. " CCL ,CHI Command Locked" "Not locked,Locked"
eventfld.long 0x00 4. " CCF ,Clock Correction Failure" "Successful,Failed"
eventfld.long 0x00 3. " SFO ,SYNC Frame Overflow" "No overflow,Overflow"
textline " "
eventfld.long 0x00 2. " SFBM ,SYNC Frames Below Minimum" "2 or more,Less than required"
eventfld.long 0x00 1. " CNA ,Command Not Accepted" "Accepted,Not accepted"
eventfld.long 0x00 0. " PEMC ,POC Error Mode Changed" "Not changed,Changed"
line.long 0x4 "SIR,Status interrupt register"
eventfld.long 0x04 25. " MTSB ,MTS Received on Channel B" "No MTS,MTS"
eventfld.long 0x04 24. " WUPB ,Wakeup Pattern Channel B" "No pattern,Pattern"
eventfld.long 0x04 17. " MTSA ,MTS Received on Channel A" "No MTS,MTS"
textline " "
eventfld.long 0x04 16. " WUPA ,Wakeup Pattern Channel A" "No pattern,Pattern"
eventfld.long 0x04 15. " SDS ,Start of Dynamic Segment" "Not started,Started"
eventfld.long 0x04 14. " MBSI ,Message Buffer Status Interrupt Request" "Not requested,Requested"
textline " "
eventfld.long 0x04 13. " SUCS ,Startup Completed Successfully" "No startup,Startup"
eventfld.long 0x04 12. " SWE ,Stop Watch Event" "No event,Event"
eventfld.long 0x04 11. " TOBC ,Transfer Output Buffer Completed" "Not completed,Completed"
textline " "
eventfld.long 0x04 10. " TIBC ,Transfer Input Buffer Completed" "Not completed,Completed"
eventfld.long 0x04 9. " TI1 ,Timer Interrupt 1" "No interrupt,Interrupt"
eventfld.long 0x04 8. " TI0 ,Timer Interrupt 0" "No interrupt,Interrupt"
textline " "
eventfld.long 0x04 7. " NMVC ,Network Management Vector Changed" "Not changed,Changed"
eventfld.long 0x04 6. " RFCL ,Receive FIFO Critical Level" "Below,Reached"
eventfld.long 0x04 5. " RFNE ,Receive FIFO Not Empty" "Empty,Not empty"
textline " "
eventfld.long 0x04 4. " RXI ,Receive Service Request" "No ND flag,At least 1 ND flag"
eventfld.long 0x04 3. " TXI ,Transmit Service Request" "No frame,At least 1 frame"
eventfld.long 0x04 2. " CYCS ,Cycle Start Service Request" "Not started,Started"
textline " "
eventfld.long 0x04 1. " CAS ,Collision Avoidance Symbol" "No pattern,Pattern"
eventfld.long 0x04 0. " WST ,Wakeup Status" "Not changed,Changed"
line.long 0x8 "EILS,Error interrupt line select"
bitfld.long 0x08 26. " TABBL ,Transmission Across Boundary Channel B Interrupt Line" "CC_int0,CC_int1"
bitfld.long 0x08 25. " LTVBL ,Latest Transmit Violation Channel B Interrupt Line" "CC_int0,CC_int1"
bitfld.long 0x08 24. " EDBL ,Error Detected on Channel B Interrupt Line" "CC_int0,CC_int1"
bitfld.long 0x08 18. " TABAL ,Transmission Across Boundary Channel A Interrupt Line" "CC_int0,CC_int1"
textline " "
bitfld.long 0x08 17. " LTVAL ,Latest Transmit Violation Channel A Interrupt Line" "CC_int0,CC_int1"
bitfld.long 0x08 16. " EDAL ,Error Detected on Channel A Interrupt Line" "CC_int0,CC_int1"
bitfld.long 0x08 11. " MHFL ,Message Handler Constrains Flag Interrupt Line" "CC_int0,CC_int1"
bitfld.long 0x08 10. " IOBAL ,Illegal Output Buffer Access Interrupt Line" "CC_int0,CC_int1"
textline " "
bitfld.long 0x08 9. " IIBAL ,Illegal Input Buffer Access Interrupt Line" "CC_int0,CC_int1"
bitfld.long 0x08 8. " EVAL ,Empty FIFO Access Interrupt Line" "CC_int0,CC_int1"
bitfld.long 0x08 7. " RFOL ,Receive FIFO Overrun Interrupt Line" "CC_int0,CC_int1"
bitfld.long 0x08 6. " PERRL ,Parity Error Interrupt Line" "CC_int0,CC_int1"
textline " "
bitfld.long 0x08 5. " CCLL ,CHI Command Locked Interrupt Line" "CC_int0,CC_int1"
bitfld.long 0x08 4. " CCFL ,Clock Correction Failure Interrupt Line" "CC_int0,CC_int1"
bitfld.long 0x08 3. " SFOL ,SYNC Frame Overflow Interrupt Line" "CC_int0,CC_int1"
bitfld.long 0x08 2. " SFBML ,SYNC Frames Below Minimum Interrupt Line" "CC_int0,CC_int1"
textline " "
bitfld.long 0x08 1. " CNAL ,Command Not Accepted Interrupt Line" "CC_int0,CC_int1"
bitfld.long 0x08 0. " PEMCL ,POC Error Mode Changed Interrupt Line" "CC_int0,CC_int1"
line.long 0xC "SILS,Status interrupt line select"
bitfld.long 0x0C 25. " MTSBL ,Media Access Test Symbol Channel B Interrupt Line" "CC_int0,CC_int1"
bitfld.long 0x0C 24. " WUPBL ,Wakeup Pattern Channel B Interrupt Line" "CC_int0,CC_int1"
bitfld.long 0x0C 17. " MTSAL ,Media Access Test Symbol Channel A Interrupt Line" "CC_int0,CC_int1"
bitfld.long 0x0C 16. " WUPAL ,Wakeup Pattern Channel A Interrupt Line" "CC_int0,CC_int1"
textline " "
bitfld.long 0x0C 15. " SDSL ,Start of Dynamic Segment Interrupt Line" "CC_int0,CC_int1"
bitfld.long 0x0C 14. " MBSIL ,Message Buffer Status Interrupt Line" "CC_int0,CC_int1"
bitfld.long 0x0C 13. " SUCSL ,Startup Completed Successfully Interrupt Line" "CC_int0,CC_int1"
bitfld.long 0x0C 12. " SWEL ,Stop Watch Event Interrupt Line" "CC_int0,CC_int1"
textline " "
bitfld.long 0x0C 11. " TOBCL ,Transfer Output Buffer Completed Interrupt Line" "CC_int0,CC_int1"
bitfld.long 0x0C 10. " TIBCL ,Transfer Input Buffer Completed Interrupt Line" "CC_int0,CC_int1"
bitfld.long 0x0C 9. " TI1L ,Timer Interrupt 1 Line" "CC_int0,CC_int1"
bitfld.long 0x0C 8. " TI0L ,Timer Interrupt 0 Line" "CC_int0,CC_int1"
textline " "
bitfld.long 0x0C 7. " NMVCL ,Network Management Vector Changed Interrupt Line" "CC_int0,CC_int1"
bitfld.long 0x0C 6. " RFFL ,Receive FIFO Full Interrupt Line" "CC_int0,CC_int1"
bitfld.long 0x0C 5. " RFNEL ,Receive FIFO Not Empty Interrupt Line" "CC_int0,CC_int1"
bitfld.long 0x0C 4. " RXIL ,Receive Interrupt Line" "CC_int0,CC_int1"
textline " "
bitfld.long 0x0C 3. " TXIL ,Transmit Interrupt Line" "CC_int0,CC_int1"
bitfld.long 0x0C 2. " CYCSL ,Cycle Start Interrupt Line" "CC_int0,CC_int1"
bitfld.long 0x0C 1. " CASL ,Collision Avoidance Symbol Interrupt Line" "CC_int0,CC_int1"
bitfld.long 0x0C 0. " WSTL ,Wakeup Status Interrupt Line" "CC_int0,CC_int1"
line.long 0x10 "EIE,Error interrupt enable"
setclrfld.long 0x10 26. 0x10 26. 0x14 26. " TABBE_set/clr ,Transmission Across Boundary Channel B Interrupt Enable" "Disabled,Enabled"
setclrfld.long 0x10 25. 0x10 25. 0x14 25. " LTVBE_set/clr ,Latest Transmit Violation Channel B Interrupt Enable" "Disabled,Enabled"
setclrfld.long 0x10 24. 0x10 24. 0x14 24. " EDBE_set/clr ,Error Detected on Channel B Interrupt Enable" "Disabled,Enabled"
textline " "
setclrfld.long 0x10 18. 0x10 18. 0x14 18. " TABAE_set/clr ,Transmission Across Boundary Channel A Interrupt Enable" "Disabled,Enabled"
setclrfld.long 0x10 17. 0x10 17. 0x14 17. " LTVAE_set/clr ,Last Transmit Violation Channel A Interrupt Enable" "Disabled,Enabled"
setclrfld.long 0x10 16. 0x10 16. 0x14 16. " EDAE_set/clr ,Error Detected on Channel A Interrupt Enable" "Disabled,Enabled"
textline " "
setclrfld.long 0x10 11. 0x10 11. 0x14 11. " MHFE_set/clr ,Message Handler Constraints Flag Interrupt Enable" "Disabled,Enabled"
setclrfld.long 0x10 10. 0x10 10. 0x14 10. " IOBAE_set/clr ,Illegal Output Buffer Access Interrupt Enable" "Disabled,Enabled"
setclrfld.long 0x10 9. 0x10 9. 0x14 9. " IIBAE_set/clr ,Illegal Input Buffer Access Interrupt Enable" "Disabled,Enabled"
textline " "
setclrfld.long 0x10 8. 0x10 8. 0x14 8. " EFAE_set/clr ,Empty FIFO Access Interrupt Enable" "Disabled,Enabled"
setclrfld.long 0x10 7. 0x10 7. 0x14 7. " RFOE_set/clr ,Receive FIFO Overrun Interrupt Enable" "Disabled,Enabled"
setclrfld.long 0x10 6. 0x10 6. 0x14 6. " PERRE_set/clr ,Parity Error Interrupt Enable" "Disabled,Enabled"
textline " "
setclrfld.long 0x10 5. 0x10 5. 0x14 5. " CCLE_set/clr ,CHI Command Locked Interrupt Enable" "Disabled,Enabled"
setclrfld.long 0x10 4. 0x10 4. 0x14 4. " CCFE_set/clr ,Clock Correction Failure Interrupt Enable" "Disabled,Enabled"
setclrfld.long 0x10 3. 0x10 3. 0x14 3. " SFOE_set/clr ,Sync Frame Overflow Interrupt Enable" "Disabled,Enabled"
textline " "
setclrfld.long 0x10 2. 0x10 2. 0x14 2. " SFBME_set/clr ,Sync Frames Below Minimum Interrupt Enable" "Disabled,Enabled"
setclrfld.long 0x10 1. 0x10 1. 0x14 1. " CNAE_set/clr ,Command Not Accepted Interrupt Enable" "Disabled,Enabled"
setclrfld.long 0x10 0. 0x10 0. 0x14 0. " PEMCE_set/clr ,POC Error Mode Changed PEMCE Interrupt Enable" "Disabled,Enabled"
group.long 0x38++0x03
line.long 0x00 "SIE,Status interrupt enable"
setclrfld.long 0x00 25. 0x00 25. 0x04 25. " MTSBE_set/clr ,MTS Received on Channel B Interrupt Enable" "Disabled,Enabled"
setclrfld.long 0x00 24. 0x00 24. 0x04 24. " WUPBE_set/clr ,Wakeup Pattern Channel B Interrupt Enable" "Disabled,Enabled"
setclrfld.long 0x00 17. 0x00 17. 0x04 17. " MTSAE_set/clr ,MTS Received on Channel A Interrupt Enable" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 16. 0x00 16. 0x04 16. " WUPAE_set/clr ,Wakeup Pattern Channel A Interrupt Enable" "Disabled,Enabled"
setclrfld.long 0x00 15. 0x00 15. 0x04 15. " SDSE_set/clr ,Start of Dynamic Segment Interrupt Enable" "Disabled,Enabled"
setclrfld.long 0x00 14. 0x00 14. 0x04 14. " MBSIE_set/clr ,Message Buffer Status Interrupt Enable" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 13. 0x00 13. 0x04 13. " SUCSE_set/clr ,Startup Completed Successfully Interrupt Enable" "Disabled,Enabled"
setclrfld.long 0x00 12. 0x00 12. 0x04 12. " SWEE_set/clr ,Stop Watch Event Interrupt Enable" "Disabled,Enabled"
setclrfld.long 0x00 11. 0x00 11. 0x04 11. " TOBCE_set/clr ,Transfer Output Buffer Completed Interrupt Enable" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 10. 0x00 10. 0x04 10. " TIBCE_set/clr ,Transfer Input Buffer Completed Interrupt Enable" "Disabled,Enabled"
setclrfld.long 0x00 9. 0x00 9. 0x04 9. " TI1E_set/clr ,Timer Interrupt 1 Enable" "Disabled,Enabled"
setclrfld.long 0x00 8. 0x00 8. 0x04 8. " TI0E_set/clr ,Timer Interrupt 0 Enable" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 7. 0x00 7. 0x04 7. " NMVCE_set/clr ,Network Management Vector Changed Interrupt Enable" "Disabled,Enabled"
setclrfld.long 0x00 6. 0x00 6. 0x04 6. " RFFE_set/clr ,Receive FIFO Full Interrupt Enable" "Disabled,Enabled"
setclrfld.long 0x00 5. 0x00 5. 0x04 5. " RFNEE_set/clr ,Receive FIFO Not Empty Interrupt Enable" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 4. 0x00 4. 0x04 4. " RXIE_set/clr ,Receive Interrupt Enable" "Disabled,Enabled"
setclrfld.long 0x00 3. 0x00 3. 0x04 3. " TXIE_set/clr ,Transmit Interrupt Enable" "Disabled,Enabled"
setclrfld.long 0x00 2. 0x00 2. 0x04 2. " CYCSE_set/clr ,Cycle Start Interrupt Enable" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 1. 0x00 1. 0x04 1. " CASE_set/clr ,Collision Avoidance Symbol Interrupt Enable" "Disabled,Enabled"
setclrfld.long 0x00 0. 0x00 0. 0x04 0. " WSTE_set/clr ,Wakeup Status Interrupt Enable" "Disabled,Enabled"
width 7.
group.long 0x40++0x0F
line.long 0x00 "ILE,Interrupt line enable"
bitfld.long 0x00 1. " EINT1 ,Enable Interrupt Line 1 (CC_int1)" "Disabled,Enabled"
bitfld.long 0x00 0. " EINT0 ,Enable Interrupt Line 0 (CC_int0)" "Disabled,Enabled"
line.long 0x04 "T0C,Timer 0 configuration"
hexmask.long.word 0x04 16.--29. 1. " T0MO ,Timer 0 Macrotick Offset"
hexmask.long.byte 0x04 8.--14. 1. " T0CC ,Timer 0 Cycle Code"
textline " "
bitfld.long 0x04 1. " T0MS ,Timer 0 Mode Select" "Single-shot,Continuous"
bitfld.long 0x04 0. " T0RC ,Timer 0 Run Control" "Halted,Running"
line.long 0x08 "T1C,Timer 1 configuration"
hexmask.long.word 0x08 16.--29. 1. " T1MC ,Timer 1 Macrotick Count"
bitfld.long 0x08 1. " T1MS ,Timer 1 Mode Select" "Single-shot,Continuous"
bitfld.long 0x08 0. " T1RC ,Timer 1 Run Control" "Halted,Running"
line.long 0x0C "STPW1,Stop watch register1"
hexmask.long.word 0x0C 16.--29. 1. " SMTV ,Stop Watch Captured Macrotick Value"
hexmask.long.byte 0x0C 8.--13. 1. " SCCV ,Stop Watch Captured Cycle Counter Value"
textline " "
bitfld.long 0x0C 6. " EINT1 ,Enable Interrupt 1 Trigger" "Disabled,Enabled"
bitfld.long 0x0C 5. " EINT0 ,Enable Interrupt 0 Trigger" "Disabled,Enabled"
bitfld.long 0x0C 4. " EETP ,Enable external trigger pin" "Disabled,Enabled"
textline " "
bitfld.long 0x0C 3. " SSWT ,Software Stop Watch Trigger" "Disabled,Enabled"
bitfld.long 0x0C 2. " EDGE ,Stop watch trigger edge select" "Falling,Rising"
bitfld.long 0x0C 1. " SWMS ,Stop Watch Mode Select" "Single-shot,Continuous"
textline " "
bitfld.long 0x0C 0. " ESWT ,Enable Stop Watch Trigger" "Disabled,Enabled"
rgroup.long 0x50++0x3
line.long 0x0 "STPW2,Stop watch register2"
hexmask.long.word 0x00 16.--26. 1. " SSCVB ,Stop Watch Captured Slot Counter Value Channel B"
hexmask.long.word 0x00 0.--10. 1. " SSCVA ,Stop Watch Captured Slot Counter Value Channel A"
tree.end
width 7.
tree "Communication Controller Control Registers"
group.long 0x80++0x1B
line.long 0x0 "SUCC1,SUC configuration register 1"
bitfld.long 0x00 27. " CCHB ,Connected to Channel B" "Not connected,Connected"
bitfld.long 0x00 26. " CCHA ,Connected to Channel A" "Not connected,Connected"
textline " "
bitfld.long 0x00 25. " MTSB ,Select Channel B for MTS Transmission" "Not Selected,Selected"
bitfld.long 0x00 24. " MTSA ,Select Channel A for MTS Transmission" "Not Selected,Selected"
textline " "
bitfld.long 0x00 23. " HCSE ,Halt due to Clock Sync Error" "Not halted,Halted"
bitfld.long 0x00 22. " TSM ,Transmission Slot Mode" "ALL,SINGLE"
textline " "
bitfld.long 0x00 21. " WUCS ,Wakeup Channel Select" "Channel A,Channel B"
bitfld.long 0x00 16.--20. " PTA ,Passive to Actives" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline " "
bitfld.long 0x00 11.--15. " CSA ,Cold Start Attemptss" ",,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 9. " TXSY ,Transmit Sync Frame in Key Slots" "Not used,Used"
textline " "
bitfld.long 0x00 8. " TXST ,Transmit Startup Frame in Key Slots" "Not used,Used"
bitfld.long 0x00 7. " PBSY ,POC Busy Flag" "Not busy,Busy"
textline " "
bitfld.long 0x00 0.--3. " CMD ,CHI Command Vector" "Disabled,CONFIG,READY,WAKEUP,RUN,ALL_SLOTS,HALT,FREEZE,SEND_MTS,ALLOW_COLDSTART,RESET_STATUS_INDICATORS,MONITOR_MODE,CLEAR_RAMS,,,LOOPBACK MODE"
line.long 0x4 "SUCC2,SUC configuration register 2"
bitfld.long 0x04 24.--27. " LTN ,Listen Timeout Noisess" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16"
hexmask.long.tbyte 0x04 0.--20. 1. " LT ,Listen Timeoutss"
line.long 0x8 "SUCC3,SUC configuration register 3"
bitfld.long 0x08 4.--7. " WCF ,Maximum Without Clock Correction Fatals" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x08 0.--3. " WCP ,Maximum Without Clock Correction Passives" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0xC "NEMC,NEM configuration register"
bitfld.long 0x0C 0.--3. " NML ,Network Management Vector Length" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x10 "PRTC1,PRT configuration register 1"
bitfld.long 0x10 26.--31. " RWP ,Repetitions of Tx Wakeup Patterns" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.word 0x10 16.--24. 1. " RXW ,Wakeup Symbol Receive Window Lengths"
bitfld.long 0x10 14.--15. " BRP ,Baud Rate Prescaler" "10 Mbps,5 Mbps,2.5 Mbps,2.5 Mbps"
textline " "
bitfld.long 0x10 12.--13. " SPP ,Strobe Point Positions" "5,4,6,5"
hexmask.long.byte 0x10 4.--10. 1. " CASM ,Collision Avoidance Symbol Maxs"
bitfld.long 0x10 0.--3. " TSST ,Transmission Start Sequence Transmitters" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x14 "PRTC2,PRT configuration register 2"
bitfld.long 0x14 24.--29. " TXL ,Wakeup Symbol Transmit Low" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.byte 0x14 16.--23. 1. " TXI ,Wakeup Symbol Transmit Idle"
textline " "
bitfld.long 0x14 8.--13. " RXL ,Wakeup Symbol Receive Low" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x14 0.--5. " RXI ,Wakeup Symbol Receive Idle" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x18 "MHDC,MHD configuration register"
hexmask.long.word 0x18 16.--28. 1. " SLT ,Start of Latest Transmit"
hexmask.long.byte 0x18 0.--6. 1. " SFDL ,Static Frame Data Length"
group.long 0xA0++0x2B
line.long 0x0 "GTUC1,GTU configuration register 1"
hexmask.long.tbyte 0x00 0.--19. 1. " UT ,Microtick per Cycles"
line.long 0x4 "GTUC2,GTU configuration register 2"
bitfld.long 0x04 16.--19. " SNM ,Sync Node Max" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.word 0x04 0.--13. 1. " MPC ,Macrotick Per Cycles"
line.long 0x8 "GTUC3,GTU configuration register 3"
hexmask.long.byte 0x08 24.--30. 1. " MIOB ,Macrotick Initial Offset Channel B"
hexmask.long.byte 0x08 16.--22. 1. " MIOA ,Macrotick Initial Offset Channel A"
textline " "
hexmask.long.byte 0x08 8.--15. 1. " UIOB ,Microtick Initial Offset Channel B"
hexmask.long.byte 0x08 0.--7. 1. " UIOA ,Microtick Initial Offset Channel A"
line.long 0xC "GTUC4,GTU configuration register 4"
hexmask.long.word 0x0C 16.--29. 1. " OCS ,Offset Correction Starts"
hexmask.long.word 0x0C 0.--13. 1. " NIT ,Network Idle Time Starts"
line.long 0x10 "GTUC5,GTU configuration register 5"
hexmask.long.byte 0x10 24.--31. 1. " DEC ,Decoding Corrections"
bitfld.long 0x10 16.--20. " CDD ,Cluster Drift Damping" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline " "
hexmask.long.byte 0x10 8.--15. 1. " DCB ,Delay Compensation Channel B"
hexmask.long.byte 0x10 0.--7. 1. " DCA ,Delay Compensation Channel A"
line.long 0x14 "GTUC6,GTU configuration register 6"
hexmask.long.word 0x14 16.--26. 1. " MOD ,Maximum Oscillator Drift"
hexmask.long.word 0x14 0.--10. 1. " ASR ,Accepted Startup Range"
line.long 0x18 "GTUC7,GTU configuration register 7"
hexmask.long.word 0x18 16.--25. 1. " NSS ,Number of Static Slots"
hexmask.long.word 0x18 0.--9. 1. " SSL ,Static Slot Length"
line.long 0x1C "GTUC8,GTU configuration register 8"
hexmask.long.word 0x1C 16.--28. 1. " NMS ,Number of Minislots"
bitfld.long 0x1C 0.--5. " MSL ,Minislot Length" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x20 "GTUC9,GTU configuration register 9"
bitfld.long 0x20 16.--17. " DSI ,Dynamic Slot Idle Phase" "0,1,2,3"
bitfld.long 0x20 8.--12. " MAPO ,Minislot Action Point Offset" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x20 0.--5. " APO ,Action Point Offset" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x24 "GTUC10,GTU configuration register 10"
hexmask.long.word 0x24 16.--26. 1. " MRC ,Maximum Rate Correction"
hexmask.long.word 0x24 0.--13. 1. " MOC ,Maximum Offset Correction"
line.long 0x28 "GTUC11,GTU configuration register 11"
bitfld.long 0x28 24.--26. " ERC ,External Rate Correction" "0,1,2,3,4,5,6,7"
bitfld.long 0x28 16.--18. " EOC ,External Offset Correction" "0,1,2,3,4,5,6,7"
textline " "
width 7.
bitfld.long 0x28 8.--9. " ERCC ,External Offset Correction" "No correction,No correction,Subtracted from calc. rate correction,Added to calc. rate correction"
textline " "
bitfld.long 0x28 0.--1. " EOCC ,External Offset Correction Control" "No correction,No correction,Subtracted from calc. rate correction,Added to calc. rate correction"
tree.end
width 8.
tree "Communication Controller Status Registers"
group.long 0x100++0x3
line.long 0x0 "CCSV,communication controller status vector"
bitfld.long 0x00 24.--29. " PSL ,POC Status Log" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 19.--23. " RCA ,Remaining Coldstart Attempts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline " "
bitfld.long 0x00 16.--18. " WSV ,Wakeup Status" "UNDEFINED,RECEIVED_HEADER,RECEIVED_WUP,COLLISION_HEADER,COLLISION_WUP,COLLISION_UNKNOWN,TRANSMITTED,?..."
bitfld.long 0x00 14. " CSI ,Cold Start Inhibit Flag" "Enabled,Disabled"
textline " "
bitfld.long 0x00 13. " CSAI ,Coldstart Abort Indicator Flag" "Not aborted,Aborted"
bitfld.long 0x00 12. " CSNI ,Coldstart Noise Indicator Flag" "Not occurred,Occurred"
textline " "
bitfld.long 0x00 8.--9. " SLM ,Slot Mode Flag" "SINGLE,,ALL_PENDING,ALL"
bitfld.long 0x00 7. " HRQ ,Halt Request Flag" "Not requested,Requested"
textline " "
bitfld.long 0x00 6. " FSI ,Freeze Status Indicator Flag" "Not Frozen,Frozen"
textline " "
bitfld.long 0x00 0.--5. " POCS ,Protocol Operation Control Status Flag" "DEFAULT_CONFIG,READY,NORMAL_ACTIVE,NORMAL_PASSIVE,HALT,MONITOR_MODE,,,,,,,,LOOPBACK MODE,,CONFIG,WAKEUP_STANDBY,WAKEUP_LISTEN,WAKEUP_SEND,WAKEUP_DETECT,,,,,,,,,,,,,STARTUP_PREPARE,COLDSTART_LISTEN,COLDSTART_COLLISION_RESOLUTION,COLDSTART_CONSISTENCY_CHECK,COLDSTART_GAP,COLDSTART_JOIN,INTEGRATION_COLDSTART_CHECK,INTEGRATION_LISTEN,INTEGRATION_CONSISTENCY_CHECK,INITIALIZE_SCHEDULE,ABORT_STARTUP,?..."
width 8.
rgroup.long 0x104++0x3
line.long 0x0 "CCEV,communication controller error vector"
bitfld.long 0x00 8.--12. " PTAC ,Passive to Active Count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 6.--7. " ERRM ,Error Mode Flag" "ACTIVE,PASSIVE,COMM_HALT,?..."
bitfld.long 0x00 0.--3. " CCFC ,Clock Correction Failed Counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
rgroup.long 0x110++0x17
line.long 0x0 "SCV,Slot counter value"
hexmask.long.word 0x00 16.--26. 1. " SCCB ,Slot Counter Channel B"
hexmask.long.word 0x00 0.--10. 1. " SCCA ,Slot Counter Channel A"
line.long 0x4 "MTCCV,Macrotick and cycle counter"
bitfld.long 0x04 16.--21. " CCV ,Cycle Counter Value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.word 0x04 0.--13. 1. " MTV ,Macrotick Value"
line.long 0x8 "RCV,Rate correction value"
hexmask.long.word 0x08 0.--11. 1. " RCV ,Rate Correction Value"
line.long 0xC "OCV,Offset correction value"
hexmask.long.tbyte 0x0C 0.--19. 1. " OCV ,Offset Correction Value"
line.long 0x10 "SFS,Sync frame status"
bitfld.long 0x10 19. " RCLR ,Rate Correction Limit Reached Flag" "Not reached,Reached"
bitfld.long 0x10 18. " MRCS ,Missing Rate Correction Signal Flag" "Not missing,Missing"
bitfld.long 0x10 17. " OCLR ,Offset Correction Limit Reached Flag" "Not reached,Reached"
textline " "
bitfld.long 0x10 16. " MOCS ,Missing Offset Correction Signal Flag" "Not missing,Missing"
bitfld.long 0x10 12.--15. " VSBO ,Valid Sync Frames Channel B odd communication cycle" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x10 8.--11. " VSBE ,Valid Sync Frames Channel B even communication cycle" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x10 4.--7. " VSAO ,Valid Sync Frames Channel A odd communication cycle" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x10 0.--3. " VSAE ,Valid Sync Frames Channel A even communication cycle" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x14 "SWNIT,Symbol window and NIT status"
bitfld.long 0x14 11. " SBNB ,Slot Boundary Violation during NIT Channel B Flag" "Not detected,Detected"
bitfld.long 0x14 10. " SENB ,Syntax Error during NIT Channel B Flag" "Not detected,Detected"
bitfld.long 0x14 9. " SBNA ,Slot Boundary Violation during NIT Channel A Flag" "Not detected,Detected"
textline " "
bitfld.long 0x14 8. " SENA ,Syntax Error during NIT Channel A Flag" "Not detected,Detected"
bitfld.long 0x14 7. " MTSB ,MTS Received on Channel B Flag" "Not received,Received"
bitfld.long 0x14 6. " MTSA ,MTS Received on Channel A Flag" "Not received,Received"
textline " "
bitfld.long 0x14 5. " TCSB ,Transmission Conflict in Symbol Window Channel B Flag" "Not detected,Detected"
bitfld.long 0x14 4. " SBSB ,Slot Boundary Violation in Symbol Window Channel B Flag" "Not detected,Detected"
bitfld.long 0x14 3. " SESB ,Syntax Error in Symbol Window Channel B Flag" "Not detected,Detected"
textline " "
bitfld.long 0x14 2. " TCSA ,Transmission Conflict in Symbol Window Channel A Flag" "Not detected,Detected"
bitfld.long 0x14 1. " SBSA ,Slot Boundary Violation in Symbol Window Channel A Flag" "Not detected,Detected"
bitfld.long 0x14 0. " SESA ,Syntax Error in Symbol Window Channel A Flag" "Not detected,Detected"
group.long 0x128++0x3
line.long 0x0 "ACS,Aggregated channel status"
eventfld.long 0x00 12. " SBVB ,Slot Boundary Violation on Channel B Flag" "Not observed,Observed"
eventfld.long 0x00 11. " CIB ,Communication Indicator Channel B Flag" "Not valid,Valid"
eventfld.long 0x00 10. " CEDB ,Content Error Detected on Channel B Flag" "Not detected,Detected"
textline " "
eventfld.long 0x00 9. " SEDB ,Syntax Error Detected on Channel B Flag" "Not observed,Observed"
eventfld.long 0x00 8. " VFRB ,Valid Frame Received on Channel B Flag" "Not valid,Valid"
eventfld.long 0x00 4. " SBVA ,Slot Boundary Violation on Channel A Flag" "Not observed,Observed"
textline " "
eventfld.long 0x00 3. " CIA ,Communication Indicator Channel A Flag" "Not valid,Valid"
eventfld.long 0x00 2. " CEDA ,Content Error Detected on Channel A Flag" "Not detected,Detected"
eventfld.long 0x00 1. " SEDA ,Syntax Error Detected on Channel A Flag" "Not observed,Observed"
textline " "
eventfld.long 0x00 0. " VFRA ,Valid Frame Received on Channel A Flag" "Not valid,Valid"
rgroup.long 0x130++0x3B
line.long 0x0 "ESID1,Even sync ID [1]"
bitfld.long 0x0 15. " RXEB ,Received Even Sync ID on Channel B Flag" "Not received,Received"
bitfld.long 0x0 14. " RXEA ,Received / Configured Even Sync ID on Channel A Flag" "Not received,Received"
hexmask.long.word 0x0 0.--9. 1. " EID[9:0] ,Even Sync ID"
line.long 0x4 "ESID2,Even sync ID [2]"
bitfld.long 0x4 15. " RXEB ,Received Even Sync ID on Channel B Flag" "Not received,Received"
bitfld.long 0x4 14. " RXEA ,Received / Configured Even Sync ID on Channel A Flag" "Not received,Received"
hexmask.long.word 0x4 0.--9. 1. " EID[9:0] ,Even Sync ID"
line.long 0x8 "ESID3,Even sync ID [3]"
bitfld.long 0x8 15. " RXEB ,Received Even Sync ID on Channel B Flag" "Not received,Received"
bitfld.long 0x8 14. " RXEA ,Received / Configured Even Sync ID on Channel A Flag" "Not received,Received"
hexmask.long.word 0x8 0.--9. 1. " EID[9:0] ,Even Sync ID"
line.long 0xC "ESID4,Even sync ID [4]"
bitfld.long 0xC 15. " RXEB ,Received Even Sync ID on Channel B Flag" "Not received,Received"
bitfld.long 0xC 14. " RXEA ,Received / Configured Even Sync ID on Channel A Flag" "Not received,Received"
hexmask.long.word 0xC 0.--9. 1. " EID[9:0] ,Even Sync ID"
line.long 0x10 "ESID5,Even sync ID [5]"
bitfld.long 0x10 15. " RXEB ,Received Even Sync ID on Channel B Flag" "Not received,Received"
bitfld.long 0x10 14. " RXEA ,Received / Configured Even Sync ID on Channel A Flag" "Not received,Received"
hexmask.long.word 0x10 0.--9. 1. " EID[9:0] ,Even Sync ID"
line.long 0x14 "ESID6,Even sync ID [6]"
bitfld.long 0x14 15. " RXEB ,Received Even Sync ID on Channel B Flag" "Not received,Received"
bitfld.long 0x14 14. " RXEA ,Received / Configured Even Sync ID on Channel A Flag" "Not received,Received"
hexmask.long.word 0x14 0.--9. 1. " EID[9:0] ,Even Sync ID"
line.long 0x18 "ESID7,Even sync ID [7]"
bitfld.long 0x18 15. " RXEB ,Received Even Sync ID on Channel B Flag" "Not received,Received"
bitfld.long 0x18 14. " RXEA ,Received / Configured Even Sync ID on Channel A Flag" "Not received,Received"
hexmask.long.word 0x18 0.--9. 1. " EID[9:0] ,Even Sync ID"
line.long 0x1C "ESID8,Even sync ID [8]"
bitfld.long 0x1C 15. " RXEB ,Received Even Sync ID on Channel B Flag" "Not received,Received"
bitfld.long 0x1C 14. " RXEA ,Received / Configured Even Sync ID on Channel A Flag" "Not received,Received"
hexmask.long.word 0x1C 0.--9. 1. " EID[9:0] ,Even Sync ID"
line.long 0x20 "ESID9,Even sync ID [9]"
bitfld.long 0x20 15. " RXEB ,Received Even Sync ID on Channel B Flag" "Not received,Received"
bitfld.long 0x20 14. " RXEA ,Received / Configured Even Sync ID on Channel A Flag" "Not received,Received"
hexmask.long.word 0x20 0.--9. 1. " EID[9:0] ,Even Sync ID"
line.long 0x24 "ESID10,Even sync ID [10]"
bitfld.long 0x24 15. " RXEB ,Received Even Sync ID on Channel B Flag" "Not received,Received"
bitfld.long 0x24 14. " RXEA ,Received / Configured Even Sync ID on Channel A Flag" "Not received,Received"
hexmask.long.word 0x24 0.--9. 1. " EID[9:0] ,Even Sync ID"
line.long 0x28 "ESID11,Even sync ID [11]"
bitfld.long 0x28 15. " RXEB ,Received Even Sync ID on Channel B Flag" "Not received,Received"
bitfld.long 0x28 14. " RXEA ,Received / Configured Even Sync ID on Channel A Flag" "Not received,Received"
hexmask.long.word 0x28 0.--9. 1. " EID[9:0] ,Even Sync ID"
line.long 0x2C "ESID12,Even sync ID [12]"
bitfld.long 0x2C 15. " RXEB ,Received Even Sync ID on Channel B Flag" "Not received,Received"
bitfld.long 0x2C 14. " RXEA ,Received / Configured Even Sync ID on Channel A Flag" "Not received,Received"
hexmask.long.word 0x2C 0.--9. 1. " EID[9:0] ,Even Sync ID"
line.long 0x30 "ESID13,Even sync ID [13]"
bitfld.long 0x30 15. " RXEB ,Received Even Sync ID on Channel B Flag" "Not received,Received"
bitfld.long 0x30 14. " RXEA ,Received / Configured Even Sync ID on Channel A Flag" "Not received,Received"
hexmask.long.word 0x30 0.--9. 1. " EID[9:0] ,Even Sync ID"
line.long 0x34 "ESID14,Even sync ID [14]"
bitfld.long 0x34 15. " RXEB ,Received Even Sync ID on Channel B Flag" "Not received,Received"
bitfld.long 0x34 14. " RXEA ,Received / Configured Even Sync ID on Channel A Flag" "Not received,Received"
hexmask.long.word 0x34 0.--9. 1. " EID[9:0] ,Even Sync ID"
line.long 0x38 "ESID15,Even sync ID [15]"
bitfld.long 0x38 15. " RXEB ,Received Even Sync ID on Channel B Flag" "Not received,Received"
bitfld.long 0x38 14. " RXEA ,Received / Configured Even Sync ID on Channel A Flag" "Not received,Received"
hexmask.long.word 0x38 0.--9. 1. " EID[9:0] ,Even Sync ID"
width 8.
rgroup.long 0x170++0x3B
line.long 0x0 "OSID1,Odd sync ID [1]"
bitfld.long 0x0 15. " RXOB ,Received / Configured Odd Sync ID on Channel B Flag" "No sync,Sync"
bitfld.long 0x0 14. " RXOA ,Received / Configured Odd Sync ID on Channel A Flag" "No sync,Sync"
hexmask.long.word 0x0 0.--9. 1. " OID[9:0] ,Odd Sync ID"
line.long 0x4 "OSID2,Odd sync ID [2]"
bitfld.long 0x4 15. " RXOB ,Received / Configured Odd Sync ID on Channel B Flag" "No sync,Sync"
bitfld.long 0x4 14. " RXOA ,Received / Configured Odd Sync ID on Channel A Flag" "No sync,Sync"
hexmask.long.word 0x4 0.--9. 1. " OID[9:0] ,Odd Sync ID"
line.long 0x8 "OSID3,Odd sync ID [3]"
bitfld.long 0x8 15. " RXOB ,Received / Configured Odd Sync ID on Channel B Flag" "No sync,Sync"
bitfld.long 0x8 14. " RXOA ,Received / Configured Odd Sync ID on Channel A Flag" "No sync,Sync"
hexmask.long.word 0x8 0.--9. 1. " OID[9:0] ,Odd Sync ID"
line.long 0xC "OSID4,Odd sync ID [4]"
bitfld.long 0xC 15. " RXOB ,Received / Configured Odd Sync ID on Channel B Flag" "No sync,Sync"
bitfld.long 0xC 14. " RXOA ,Received / Configured Odd Sync ID on Channel A Flag" "No sync,Sync"
hexmask.long.word 0xC 0.--9. 1. " OID[9:0] ,Odd Sync ID"
line.long 0x10 "OSID5,Odd sync ID [5]"
bitfld.long 0x10 15. " RXOB ,Received / Configured Odd Sync ID on Channel B Flag" "No sync,Sync"
bitfld.long 0x10 14. " RXOA ,Received / Configured Odd Sync ID on Channel A Flag" "No sync,Sync"
hexmask.long.word 0x10 0.--9. 1. " OID[9:0] ,Odd Sync ID"
line.long 0x14 "OSID6,Odd sync ID [6]"
bitfld.long 0x14 15. " RXOB ,Received / Configured Odd Sync ID on Channel B Flag" "No sync,Sync"
bitfld.long 0x14 14. " RXOA ,Received / Configured Odd Sync ID on Channel A Flag" "No sync,Sync"
hexmask.long.word 0x14 0.--9. 1. " OID[9:0] ,Odd Sync ID"
line.long 0x18 "OSID7,Odd sync ID [7]"
bitfld.long 0x18 15. " RXOB ,Received / Configured Odd Sync ID on Channel B Flag" "No sync,Sync"
bitfld.long 0x18 14. " RXOA ,Received / Configured Odd Sync ID on Channel A Flag" "No sync,Sync"
hexmask.long.word 0x18 0.--9. 1. " OID[9:0] ,Odd Sync ID"
line.long 0x1C "OSID8,Odd sync ID [8]"
bitfld.long 0x1C 15. " RXOB ,Received / Configured Odd Sync ID on Channel B Flag" "No sync,Sync"
bitfld.long 0x1C 14. " RXOA ,Received / Configured Odd Sync ID on Channel A Flag" "No sync,Sync"
hexmask.long.word 0x1C 0.--9. 1. " OID[9:0] ,Odd Sync ID"
line.long 0x20 "OSID9,Odd sync ID [9]"
bitfld.long 0x20 15. " RXOB ,Received / Configured Odd Sync ID on Channel B Flag" "No sync,Sync"
bitfld.long 0x20 14. " RXOA ,Received / Configured Odd Sync ID on Channel A Flag" "No sync,Sync"
hexmask.long.word 0x20 0.--9. 1. " OID[9:0] ,Odd Sync ID"
line.long 0x24 "OSID10,Odd sync ID [10]"
bitfld.long 0x24 15. " RXOB ,Received / Configured Odd Sync ID on Channel B Flag" "No sync,Sync"
bitfld.long 0x24 14. " RXOA ,Received / Configured Odd Sync ID on Channel A Flag" "No sync,Sync"
hexmask.long.word 0x24 0.--9. 1. " OID[9:0] ,Odd Sync ID"
line.long 0x28 "OSID11,Odd sync ID [11]"
bitfld.long 0x28 15. " RXOB ,Received / Configured Odd Sync ID on Channel B Flag" "No sync,Sync"
bitfld.long 0x28 14. " RXOA ,Received / Configured Odd Sync ID on Channel A Flag" "No sync,Sync"
hexmask.long.word 0x28 0.--9. 1. " OID[9:0] ,Odd Sync ID"
line.long 0x2C "OSID12,Odd sync ID [12]"
bitfld.long 0x2C 15. " RXOB ,Received / Configured Odd Sync ID on Channel B Flag" "No sync,Sync"
bitfld.long 0x2C 14. " RXOA ,Received / Configured Odd Sync ID on Channel A Flag" "No sync,Sync"
hexmask.long.word 0x2C 0.--9. 1. " OID[9:0] ,Odd Sync ID"
line.long 0x30 "OSID13,Odd sync ID [13]"
bitfld.long 0x30 15. " RXOB ,Received / Configured Odd Sync ID on Channel B Flag" "No sync,Sync"
bitfld.long 0x30 14. " RXOA ,Received / Configured Odd Sync ID on Channel A Flag" "No sync,Sync"
hexmask.long.word 0x30 0.--9. 1. " OID[9:0] ,Odd Sync ID"
line.long 0x34 "OSID14,Odd sync ID [14]"
bitfld.long 0x34 15. " RXOB ,Received / Configured Odd Sync ID on Channel B Flag" "No sync,Sync"
bitfld.long 0x34 14. " RXOA ,Received / Configured Odd Sync ID on Channel A Flag" "No sync,Sync"
hexmask.long.word 0x34 0.--9. 1. " OID[9:0] ,Odd Sync ID"
line.long 0x38 "OSID15,Odd sync ID [15]"
bitfld.long 0x38 15. " RXOB ,Received / Configured Odd Sync ID on Channel B Flag" "No sync,Sync"
bitfld.long 0x38 14. " RXOA ,Received / Configured Odd Sync ID on Channel A Flag" "No sync,Sync"
hexmask.long.word 0x38 0.--9. 1. " OID[9:0] ,Odd Sync ID"
width 8.
rgroup.long 0x1B0++0xB
line.long 0x00 "NMV1,Network management vector [1]"
hexmask.long.byte 0x00 24.--31. 1. " NMIDATA_[3] ,Network Management Vector Data 3"
hexmask.long.byte 0x00 16.--23. 1. " [2] ,Network Management Vector Data 2"
hexmask.long.byte 0x00 8.--15. 1. " [1] ,Network Management Vector Data 1"
hexmask.long.byte 0x00 0.--7. 1. " [0] ,Network Management Vector Data 0"
line.long 0x04 "NMV2,Network management vector [2]"
hexmask.long.byte 0x04 24.--31. 1. " NMIDATA_[7] ,Network Management Vector Data 7"
hexmask.long.byte 0x04 16.--23. 1. " [6] ,Network Management Vector Data 6"
hexmask.long.byte 0x04 8.--15. 1. " [5] ,Network Management Vector Data 5"
hexmask.long.byte 0x04 0.--7. 1. " [4] ,Network Management Vector Data 4"
line.long 0x08 "NMV3,Network management vector [3]"
hexmask.long.byte 0x08 24.--31. 1. " NMIDATA_[11] ,Network Management Vector Data 11"
hexmask.long.byte 0x08 16.--23. 1. " [10] ,Network Management Vector Data 10"
hexmask.long.byte 0x08 8.--15. 1. " [9] ,Network Management Vector Data 9"
hexmask.long.byte 0x08 0.--7. 1. " [8] ,Network Management Vector Data 8"
tree.end
width 6.
tree "Message Buffer Control Registers"
group.long 0x300++0xF
line.long 0x00 "MRC,Message RAM configuration"
bitfld.long 0x00 26. " SPLM ,Sync Frame Payload Multiplex" "Buffer 0,Buffers 0 & 1"
bitfld.long 0x00 24.--25. " SEC ,Secure Buffers" "Reconfig all enabled,Reconfig < FDB & FFB locked/FDB TX disabled,All buffers locked,Reconfig FDB locked/FDB TX disabled"
textline " "
hexmask.long.byte 0x00 16.--23. 1. " LCB ,Last Configured Buffer"
hexmask.long.byte 0x00 8.--15. 1. " FFB ,First Buffer of FIFO"
textline " "
hexmask.long.byte 0x00 0.--7. 1. " FDB ,First Dynamic Buffer"
line.long 0x04 "FRF,FIFO rejection filter"
bitfld.long 0x04 24. " RNF ,Reject Null Frames" "Not rejected,Rejected"
bitfld.long 0x04 23. " RSS ,Reject in Static Segment" "Not rejected,Rejected"
textline " "
hexmask.long.byte 0x04 16.--22. 1. " CYF ,Cycle Counter Filter"
hexmask.long.word 0x04 2.--12. 1. " FID ,Frame ID Filter"
textline " "
bitfld.long 0x04 0.--1. " CH ,Channel Filter" "Both,Channel B,Channel A,No reception"
line.long 0x08 "FRFM,FIFO rejection filter mask"
bitfld.long 0x08 12. " MFID ,Mask Frame ID Filter 10" "0,1"
bitfld.long 0x08 11. ",Mask Frame ID Filter 9" "0,1"
bitfld.long 0x08 10. ",Mask Frame ID Filter 8" "0,1"
bitfld.long 0x08 9. ",Mask Frame ID Filter 7" "0,1"
bitfld.long 0x08 8. ",Mask Frame ID Filter 6" "0,1"
bitfld.long 0x08 7. ",Mask Frame ID Filter 5" "0,1"
bitfld.long 0x08 6. ",Mask Frame ID Filter 4" "0,1"
bitfld.long 0x08 5. ",Mask Frame ID Filter 3" "0,1"
bitfld.long 0x08 4. ",Mask Frame ID Filter 2" "0,1"
bitfld.long 0x08 3. ",Mask Frame ID Filter 1" "0,1"
bitfld.long 0x08 2. ",Mask Frame ID Filter 0" "0,1"
line.long 0xC "FCL,FIFO Critical Level"
hexmask.long.byte 0x0C 0.--7. 1. " CL ,Critical Level"
tree.end
width 8.
tree "Message Buffer Status Registers"
group.long 0x310++0x3
line.long 0x0 "MHDS,Message handler status"
hexmask.long.byte 0x00 24.--30. 1. " MBU ,Message Buffer Updated"
hexmask.long.byte 0x00 16.--22. 1. " MBT ,Message Buffer Transmitted"
hexmask.long.byte 0x00 8.--14. 1. " FMB ,Faulty Message Buffer"
textline " "
rbitfld.long 0x00 7. " CRAM ,Clear all internal RAM's Flag" "No execution,Execution"
eventfld.long 0x00 6. " MFMB ,Multiple Faulty Message Buffers detected Flag" "Not detected,Detected"
eventfld.long 0x00 5. " FMBD ,Faulty Message Buffer Detected Flag" "Not detected,Detected"
textline " "
eventfld.long 0x00 4. " PTBF2 ,Parity Error Transient Buffer RAM B Flag" "No error,Error"
eventfld.long 0x00 3. " PTBF1 ,Parity Error Transient Buffer RAM A Flag" "No error,Error"
eventfld.long 0x00 2. " PMR ,Parity Error Message RAM Flag" "No error,Error"
textline " "
eventfld.long 0x00 1. " POBF ,Parity Error Output Buffer RAM 1 & 2 Flag" "No error,Error"
eventfld.long 0x00 0. " PIBF ,Parity Error Input Buffer RAM 1 & 2 Flag" "No error,Error"
rgroup.long 0x314++0x7
line.long 0x0 "LDTS,Last dynamic transmit slot"
hexmask.long.word 0x00 16.--26. 1. " LDTB ,Last Dynamic Transmission Channel B"
hexmask.long.word 0x00 0.--10. 1. " LDTA ,Last Dynamic Transmission Channel A"
line.long 0x4 "FSR,FIFO status register"
hexmask.long.byte 0x04 8.--15. 1. " RFFL ,Receive FIFO Fill Level"
bitfld.long 0x04 2. " RFO ,Receive FIFO Overrun Flag" "Not detected,Detected"
bitfld.long 0x04 1. " RFCL ,Receive FIFO Critical Level Flag" "Not reached,Reached"
textline " "
bitfld.long 0x04 0. " RFNE ,Receive FIFO Not Empty Flag" "Empty,Not empty"
group.long 0x31C++0x3
line.long 0x0 "MHDF,Message handler constraint flags"
eventfld.long 0x00 8. " WAHP ,Write Attempt to Header Partition Flag" "Not attempted,Attempted"
eventfld.long 0x00 7. " TNSA ,Transmission Not Started Channel A" "Not occurred,Occurred"
eventfld.long 0x00 6. " TNSB ,Transmission Not Started Channel B" "Not occurred,Occurred"
textline " "
eventfld.long 0x00 5. " TBFB ,Transient Buffer Access Failure B Flag" "Not Failed,Failed"
eventfld.long 0x00 4. " TBFA ,Transient Buffer Access Failure A Flag" "Not Failed,Failed"
eventfld.long 0x00 3. " FNFB ,Find Sequence Not Finished for Channel B Flag" "Not Found,Found"
textline " "
eventfld.long 0x00 2. " FNFA ,Find Sequence Not Finished for Channel B Flag" "Not Found,Found"
eventfld.long 0x00 1. " SNUB ,Status Not Updated Channel B Flag" "Updated,Not updated"
eventfld.long 0x00 0. " SNUA ,Status Not Updated Channel A Flag" "Updated,Not updated"
rgroup.long 0x320++0xF
line.long 0x0 "TXRQ1,Transmission request 1"
bitfld.long 0x00 31. " TXR [31] ,Transmission Request Flag 31" "Not requested,Requested"
bitfld.long 0x00 30. " [30] ,Transmission Request Flag 30" "Not requested,Requested"
bitfld.long 0x00 29. " [29] ,Transmission Request Flag 29" "Not requested,Requested"
bitfld.long 0x00 28. " [28] ,Transmission Request Flag 28" "Not requested,Requested"
textline " "
bitfld.long 0x00 27. " [27] ,Transmission Request Flag 27" "Not requested,Requested"
bitfld.long 0x00 26. " [26] ,Transmission Request Flag 26" "Not requested,Requested"
bitfld.long 0x00 25. " [25] ,Transmission Request Flag 25" "Not requested,Requested"
bitfld.long 0x00 24. " [24] ,Transmission Request Flag 24" "Not requested,Requested"
textline " "
bitfld.long 0x00 23. " [23] ,Transmission Request Flag 23" "Not requested,Requested"
bitfld.long 0x00 22. " [22] ,Transmission Request Flag 22" "Not requested,Requested"
bitfld.long 0x00 21. " [21] ,Transmission Request Flag 21" "Not requested,Requested"
bitfld.long 0x00 20. " [20] ,Transmission Request Flag 20" "Not requested,Requested"
textline " "
bitfld.long 0x00 19. " [19] ,Transmission Request Flag 19" "Not requested,Requested"
bitfld.long 0x00 18. " [18] ,Transmission Request Flag 18" "Not requested,Requested"
bitfld.long 0x00 17. " [17] ,Transmission Request Flag 17" "Not requested,Requested"
bitfld.long 0x00 16. " [16] ,Transmission Request Flag 16" "Not requested,Requested"
textline " "
bitfld.long 0x00 15. " [15] ,Transmission Request Flag 15" "Not requested,Requested"
bitfld.long 0x00 14. " [14] ,Transmission Request Flag 14" "Not requested,Requested"
bitfld.long 0x00 13. " [13] ,Transmission Request Flag 13" "Not requested,Requested"
bitfld.long 0x00 12. " [12] ,Transmission Request Flag 12" "Not requested,Requested"
textline " "
bitfld.long 0x00 11. " [11] ,Transmission Request Flag 11" "Not requested,Requested"
bitfld.long 0x00 10. " [10] ,Transmission Request Flag 10" "Not requested,Requested"
bitfld.long 0x00 9. " [9] ,Transmission Request Flag 9" "Not requested,Requested"
bitfld.long 0x00 8. " [8] ,Transmission Request Flag 8" "Not requested,Requested"
textline " "
bitfld.long 0x00 7. " [7] ,Transmission Request Flag 7" "Not requested,Requested"
bitfld.long 0x00 6. " [6] ,Transmission Request Flag 6" "Not requested,Requested"
bitfld.long 0x00 5. " [5] ,Transmission Request Flag 5" "Not requested,Requested"
bitfld.long 0x00 4. " [4] ,Transmission Request Flag 4" "Not requested,Requested"
textline " "
bitfld.long 0x00 3. " [3] ,Transmission Request Flag 3" "Not requested,Requested"
bitfld.long 0x00 2. " [2] ,Transmission Request Flag 2" "Not requested,Requested"
bitfld.long 0x00 1. " [1] ,Transmission Request Flag 1" "Not requested,Requested"
bitfld.long 0x00 0. " [0] ,Transmission Request Flag 0" "Not requested,Requested"
line.long 0x04 "TXRQ2,FlexRay Transmission Request Register 2"
bitfld.long 0x04 31. " TXR [63] ,Transmission Request Flag 63" "Not requested,Requested"
bitfld.long 0x04 30. " [62] ,Transmission Request Flag 62" "Not requested,Requested"
bitfld.long 0x04 29. " [61] ,Transmission Request Flag 61" "Not requested,Requested"
bitfld.long 0x04 28. " [60] ,Transmission Request Flag 60" "Not requested,Requested"
textline " "
bitfld.long 0x04 27. " [59] ,Transmission Request Flag 59" "Not requested,Requested"
bitfld.long 0x04 26. " [58] ,Transmission Request Flag 58" "Not requested,Requested"
bitfld.long 0x04 25. " [57] ,Transmission Request Flag 57" "Not requested,Requested"
bitfld.long 0x04 24. " [56] ,Transmission Request Flag 56" "Not requested,Requested"
textline " "
bitfld.long 0x04 23. " [55] ,Transmission Request Flag 55" "Not requested,Requested"
bitfld.long 0x04 22. " [54] ,Transmission Request Flag 54" "Not requested,Requested"
bitfld.long 0x04 21. " [53] ,Transmission Request Flag 53" "Not requested,Requested"
bitfld.long 0x04 20. " [52] ,Transmission Request Flag 52" "Not requested,Requested"
textline " "
bitfld.long 0x04 19. " [51] ,Transmission Request Flag 51" "Not requested,Requested"
bitfld.long 0x04 18. " [50] ,Transmission Request Flag 50" "Not requested,Requested"
bitfld.long 0x04 17. " [49] ,Transmission Request Flag 49" "Not requested,Requested"
bitfld.long 0x04 16. " [48] ,Transmission Request Flag 48" "Not requested,Requested"
textline " "
bitfld.long 0x04 15. " [47] ,Transmission Request Flag 47" "Not requested,Requested"
bitfld.long 0x04 14. " [46] ,Transmission Request Flag 46" "Not requested,Requested"
bitfld.long 0x04 13. " [45] ,Transmission Request Flag 45" "Not requested,Requested"
bitfld.long 0x04 12. " [44] ,Transmission Request Flag 44" "Not requested,Requested"
textline " "
bitfld.long 0x04 11. " [43] ,Transmission Request Flag 43" "Not requested,Requested"
bitfld.long 0x04 10. " [42] ,Transmission Request Flag 42" "Not requested,Requested"
bitfld.long 0x04 9. " [41] ,Transmission Request Flag 41" "Not requested,Requested"
bitfld.long 0x04 8. " [40] ,Transmission Request Flag 40" "Not requested,Requested"
textline " "
bitfld.long 0x04 7. " [39] ,Transmission Request Flag 39" "Not requested,Requested"
bitfld.long 0x04 6. " [38] ,Transmission Request Flag 38" "Not requested,Requested"
bitfld.long 0x04 5. " [37] ,Transmission Request Flag 37" "Not requested,Requested"
bitfld.long 0x04 4. " [36] ,Transmission Request Flag 36" "Not requested,Requested"
textline " "
bitfld.long 0x04 3. " [35] ,Transmission Request Flag 35" "Not requested,Requested"
bitfld.long 0x04 2. " [34] ,Transmission Request Flag 34" "Not requested,Requested"
bitfld.long 0x04 1. " [33] ,Transmission Request Flag 33" "Not requested,Requested"
bitfld.long 0x04 0. " [32] ,Transmission Request Flag 32" "Not requested,Requested"
line.long 0x08 "TXRQ3,FlexRay Transmission Request Register 3"
bitfld.long 0x08 31. " TXR [95] ,Transmission Request Flag 95" "Not requested,Requested"
bitfld.long 0x08 30. " [94] ,Transmission Request Flag 94" "Not requested,Requested"
bitfld.long 0x08 29. " [93] ,Transmission Request Flag 93" "Not requested,Requested"
bitfld.long 0x08 28. " [92] ,Transmission Request Flag 92" "Not requested,Requested"
textline " "
bitfld.long 0x08 27. " [91] ,Transmission Request Flag 91" "Not requested,Requested"
bitfld.long 0x08 26. " [90] ,Transmission Request Flag 90" "Not requested,Requested"
bitfld.long 0x08 25. " [89] ,Transmission Request Flag 89" "Not requested,Requested"
bitfld.long 0x08 24. " [88] ,Transmission Request Flag 88" "Not requested,Requested"
textline " "
bitfld.long 0x08 23. " [87] ,Transmission Request Flag 87" "Not requested,Requested"
bitfld.long 0x08 22. " [86] ,Transmission Request Flag 86" "Not requested,Requested"
bitfld.long 0x08 21. " [85] ,Transmission Request Flag 85" "Not requested,Requested"
bitfld.long 0x08 20. " [84] ,Transmission Request Flag 84" "Not requested,Requested"
textline " "
bitfld.long 0x08 19. " [83] ,Transmission Request Flag 83" "Not requested,Requested"
bitfld.long 0x08 18. " [82] ,Transmission Request Flag 82" "Not requested,Requested"
bitfld.long 0x08 17. " [81] ,Transmission Request Flag 81" "Not requested,Requested"
bitfld.long 0x08 16. " [80] ,Transmission Request Flag 80" "Not requested,Requested"
textline " "
bitfld.long 0x08 15. " [79] ,Transmission Request Flag 79" "Not requested,Requested"
bitfld.long 0x08 14. " [78] ,Transmission Request Flag 78" "Not requested,Requested"
bitfld.long 0x08 13. " [77] ,Transmission Request Flag 77" "Not requested,Requested"
bitfld.long 0x08 12. " [76] ,Transmission Request Flag 76" "Not requested,Requested"
textline " "
bitfld.long 0x08 11. " [75] ,Transmission Request Flag 75" "Not requested,Requested"
bitfld.long 0x08 10. " [74] ,Transmission Request Flag 74" "Not requested,Requested"
bitfld.long 0x08 9. " [73] ,Transmission Request Flag 73" "Not requested,Requested"
bitfld.long 0x08 8. " [72] ,Transmission Request Flag 72" "Not requested,Requested"
textline " "
bitfld.long 0x08 7. " [71] ,Transmission Request Flag 71" "Not requested,Requested"
bitfld.long 0x08 6. " [70] ,Transmission Request Flag 70" "Not requested,Requested"
bitfld.long 0x08 5. " [69] ,Transmission Request Flag 69" "Not requested,Requested"
bitfld.long 0x08 4. " [68] ,Transmission Request Flag 68" "Not requested,Requested"
textline " "
bitfld.long 0x08 3. " [67] ,Transmission Request Flag 67" "Not requested,Requested"
bitfld.long 0x08 2. " [66] ,Transmission Request Flag 66" "Not requested,Requested"
bitfld.long 0x08 1. " [65] ,Transmission Request Flag 65" "Not requested,Requested"
bitfld.long 0x08 0. " [64] ,Transmission Request Flag 64" "Not requested,Requested"
line.long 0x0C "TXRQ4,FlexRay Transmission Request Register 4"
bitfld.long 0x0C 31. " TXR [127] ,Transmission Request Flag 127" "Not requested,Requested"
bitfld.long 0x0C 30. " [126] ,Transmission Request Flag 126" "Not requested,Requested"
bitfld.long 0x0C 29. " [125] ,Transmission Request Flag 125" "Not requested,Requested"
bitfld.long 0x0C 28. " [124] ,Transmission Request Flag 124" "Not requested,Requested"
textline " "
bitfld.long 0x0C 27. " [123] ,Transmission Request Flag 123" "Not requested,Requested"
bitfld.long 0x0C 26. " [122] ,Transmission Request Flag 122" "Not requested,Requested"
bitfld.long 0x0C 25. " [121] ,Transmission Request Flag 121" "Not requested,Requested"
bitfld.long 0x0C 24. " [120] ,Transmission Request Flag 120" "Not requested,Requested"
textline " "
bitfld.long 0x0C 23. " [119] ,Transmission Request Flag 119" "Not requested,Requested"
bitfld.long 0x0C 22. " [118] ,Transmission Request Flag 118" "Not requested,Requested"
bitfld.long 0x0C 21. " [117] ,Transmission Request Flag 117" "Not requested,Requested"
bitfld.long 0x0C 20. " [116] ,Transmission Request Flag 116" "Not requested,Requested"
textline " "
bitfld.long 0x0C 19. " [115] ,Transmission Request Flag 115" "Not requested,Requested"
bitfld.long 0x0C 18. " [114] ,Transmission Request Flag 114" "Not requested,Requested"
bitfld.long 0x0C 17. " [113] ,Transmission Request Flag 113" "Not requested,Requested"
bitfld.long 0x0C 16. " [112] ,Transmission Request Flag 112" "Not requested,Requested"
textline " "
bitfld.long 0x0C 15. " [111] ,Transmission Request Flag 111" "Not requested,Requested"
bitfld.long 0x0C 14. " [110] ,Transmission Request Flag 110" "Not requested,Requested"
bitfld.long 0x0C 13. " [109] ,Transmission Request Flag 109" "Not requested,Requested"
bitfld.long 0x0C 12. " [108] ,Transmission Request Flag 108" "Not requested,Requested"
textline " "
bitfld.long 0x0C 11. " [107] ,Transmission Request Flag 107" "Not requested,Requested"
bitfld.long 0x0C 10. " [106] ,Transmission Request Flag 106" "Not requested,Requested"
bitfld.long 0x0C 9. " [105] ,Transmission Request Flag 105" "Not requested,Requested"
bitfld.long 0x0C 8. " [104] ,Transmission Request Flag 104" "Not requested,Requested"
textline " "
bitfld.long 0x0C 7. " [103] ,Transmission Request Flag 103" "Not requested,Requested"
bitfld.long 0x0C 6. " [102] ,Transmission Request Flag 102" "Not requested,Requested"
bitfld.long 0x0C 5. " [101] ,Transmission Request Flag 101" "Not requested,Requested"
bitfld.long 0x0C 4. " [100] ,Transmission Request Flag 100" "Not requested,Requested"
textline " "
bitfld.long 0x0C 3. " [99] ,Transmission Request Flag 99" "Not requested,Requested"
bitfld.long 0x0C 2. " [98] ,Transmission Request Flag 98" "Not requested,Requested"
bitfld.long 0x0C 1. " [97] ,Transmission Request Flag 97" "Not requested,Requested"
bitfld.long 0x0C 0. " [96] ,Transmission Request Flag 96" "Not requested,Requested"
rgroup.long 0x330++0xF
line.long 0x0 "NDAT1,New data 1"
bitfld.long 0x00 31. " ND [31] ,New Data Flag 31" "Not detected,Detected"
bitfld.long 0x00 30. " [30] ,New Data Flag 30" "Not detected,Detected"
bitfld.long 0x00 29. " [29] ,New Data Flag 29" "Not detected,Detected"
bitfld.long 0x00 28. " [28] ,New Data Flag 28" "Not detected,Detected"
textline " "
bitfld.long 0x00 27. " [27] ,New Data Flag 27" "Not detected,Detected"
bitfld.long 0x00 26. " [26] ,New Data Flag 26" "Not detected,Detected"
bitfld.long 0x00 25. " [25] ,New Data Flag 25" "Not detected,Detected"
bitfld.long 0x00 24. " [24] ,New Data Flag 24" "Not detected,Detected"
textline " "
bitfld.long 0x00 23. " [23] ,New Data Flag 23" "Not detected,Detected"
bitfld.long 0x00 22. " [22] ,New Data Flag 22" "Not detected,Detected"
bitfld.long 0x00 21. " [21] ,New Data Flag 21" "Not detected,Detected"
bitfld.long 0x00 20. " [20] ,New Data Flag 20" "Not detected,Detected"
textline " "
bitfld.long 0x00 19. " [19] ,New Data Flag 19" "Not detected,Detected"
bitfld.long 0x00 18. " [18] ,New Data Flag 18" "Not detected,Detected"
bitfld.long 0x00 17. " [17] ,New Data Flag 17" "Not detected,Detected"
bitfld.long 0x00 16. " [16] ,New Data Flag 16" "Not detected,Detected"
textline " "
bitfld.long 0x00 15. " [15] ,New Data Flag 15" "Not detected,Detected"
bitfld.long 0x00 14. " [14] ,New Data Flag 14" "Not detected,Detected"
bitfld.long 0x00 13. " [13] ,New Data Flag 13" "Not detected,Detected"
bitfld.long 0x00 12. " [12] ,New Data Flag 12" "Not detected,Detected"
textline " "
bitfld.long 0x00 11. " [11] ,New Data Flag 11" "Not detected,Detected"
bitfld.long 0x00 10. " [10] ,New Data Flag 10" "Not detected,Detected"
bitfld.long 0x00 9. " [9] ,New Data Flag 9" "Not detected,Detected"
bitfld.long 0x00 8. " [8] ,New Data Flag 8" "Not detected,Detected"
textline " "
bitfld.long 0x00 7. " [7] ,New Data Flag 7" "Not detected,Detected"
bitfld.long 0x00 6. " [6] ,New Data Flag 6" "Not detected,Detected"
bitfld.long 0x00 5. " [5] ,New Data Flag 5" "Not detected,Detected"
bitfld.long 0x00 4. " [4] ,New Data Flag 4" "Not detected,Detected"
textline " "
bitfld.long 0x00 3. " [3] ,New Data Flag 3" "Not detected,Detected"
bitfld.long 0x00 2. " [2] ,New Data Flag 2" "Not detected,Detected"
bitfld.long 0x00 1. " [1] ,New Data Flag 1" "Not detected,Detected"
bitfld.long 0x00 0. " [0] ,New Data Flag 0" "Not detected,Detected"
line.long 0x04 "NDAT2,FlexRay New Data Register 2"
bitfld.long 0x04 31. " ND [63] ,New Data Flag 63" "Not detected,Detected"
bitfld.long 0x04 30. " [62] ,New Data Flag 62" "Not detected,Detected"
bitfld.long 0x04 29. " [61] ,New Data Flag 61" "Not detected,Detected"
bitfld.long 0x04 28. " [60] ,New Data Flag 60" "Not detected,Detected"
textline " "
bitfld.long 0x04 27. " [59] ,New Data Flag 59" "Not detected,Detected"
bitfld.long 0x04 26. " [58] ,New Data Flag 58" "Not detected,Detected"
bitfld.long 0x04 25. " [57] ,New Data Flag 57" "Not detected,Detected"
bitfld.long 0x04 24. " [56] ,New Data Flag 56" "Not detected,Detected"
textline " "
bitfld.long 0x04 23. " [55] ,New Data Flag 55" "Not detected,Detected"
bitfld.long 0x04 22. " [54] ,New Data Flag 54" "Not detected,Detected"
bitfld.long 0x04 21. " [53] ,New Data Flag 53" "Not detected,Detected"
bitfld.long 0x04 20. " [52] ,New Data Flag 52" "Not detected,Detected"
textline " "
bitfld.long 0x04 19. " [51] ,New Data Flag 51" "Not detected,Detected"
bitfld.long 0x04 18. " [50] ,New Data Flag 50" "Not detected,Detected"
bitfld.long 0x04 17. " [49] ,New Data Flag 49" "Not detected,Detected"
bitfld.long 0x04 16. " [48] ,New Data Flag 48" "Not detected,Detected"
textline " "
bitfld.long 0x04 15. " [47] ,New Data Flag 47" "Not detected,Detected"
bitfld.long 0x04 14. " [46] ,New Data Flag 46" "Not detected,Detected"
bitfld.long 0x04 13. " [45] ,New Data Flag 45" "Not detected,Detected"
bitfld.long 0x04 12. " [44] ,New Data Flag 44" "Not detected,Detected"
textline " "
bitfld.long 0x04 11. " [43] ,New Data Flag 43" "Not detected,Detected"
bitfld.long 0x04 10. " [42] ,New Data Flag 42" "Not detected,Detected"
bitfld.long 0x04 9. " [41] ,New Data Flag 41" "Not detected,Detected"
bitfld.long 0x04 8. " [40] ,New Data Flag 40" "Not detected,Detected"
textline " "
bitfld.long 0x04 7. " [39] ,New Data Flag 39" "Not detected,Detected"
bitfld.long 0x04 6. " [38] ,New Data Flag 38" "Not detected,Detected"
bitfld.long 0x04 5. " [37] ,New Data Flag 37" "Not detected,Detected"
bitfld.long 0x04 4. " [36] ,New Data Flag 36" "Not detected,Detected"
textline " "
bitfld.long 0x04 3. " [35] ,New Data Flag 35" "Not detected,Detected"
bitfld.long 0x04 2. " [34] ,New Data Flag 34" "Not detected,Detected"
bitfld.long 0x04 1. " [33] ,New Data Flag 33" "Not detected,Detected"
bitfld.long 0x04 0. " [32] ,New Data Flag 32" "Not detected,Detected"
line.long 0x08 "NDAT3,FlexRay New Data Register 3"
bitfld.long 0x08 31. " ND [95] ,New Data Flag 95" "Not detected,Detected"
bitfld.long 0x08 30. " [94] ,New Data Flag 94" "Not detected,Detected"
bitfld.long 0x08 29. " [93] ,New Data Flag 93" "Not detected,Detected"
bitfld.long 0x08 28. " [92] ,New Data Flag 92" "Not detected,Detected"
textline " "
bitfld.long 0x08 27. " [91] ,New Data Flag 91" "Not detected,Detected"
bitfld.long 0x08 26. " [90] ,New Data Flag 90" "Not detected,Detected"
bitfld.long 0x08 25. " [89] ,New Data Flag 89" "Not detected,Detected"
bitfld.long 0x08 24. " [88] ,New Data Flag 88" "Not detected,Detected"
textline " "
bitfld.long 0x08 23. " [87] ,New Data Flag 87" "Not detected,Detected"
bitfld.long 0x08 22. " [86] ,New Data Flag 86" "Not detected,Detected"
bitfld.long 0x08 21. " [85] ,New Data Flag 85" "Not detected,Detected"
bitfld.long 0x08 20. " [84] ,New Data Flag 84" "Not detected,Detected"
textline " "
bitfld.long 0x08 19. " [83] ,New Data Flag 83" "Not detected,Detected"
bitfld.long 0x08 18. " [82] ,New Data Flag 82" "Not detected,Detected"
bitfld.long 0x08 17. " [81] ,New Data Flag 81" "Not detected,Detected"
bitfld.long 0x08 16. " [80] ,New Data Flag 80" "Not detected,Detected"
textline " "
bitfld.long 0x08 15. " [79] ,New Data Flag 79" "Not detected,Detected"
bitfld.long 0x08 14. " [78] ,New Data Flag 78" "Not detected,Detected"
bitfld.long 0x08 13. " [77] ,New Data Flag 77" "Not detected,Detected"
bitfld.long 0x08 12. " [76] ,New Data Flag 76" "Not detected,Detected"
textline " "
bitfld.long 0x08 11. " [75] ,New Data Flag 75" "Not detected,Detected"
bitfld.long 0x08 10. " [74] ,New Data Flag 74" "Not detected,Detected"
bitfld.long 0x08 9. " [73] ,New Data Flag 73" "Not detected,Detected"
bitfld.long 0x08 8. " [72] ,New Data Flag 72" "Not detected,Detected"
textline " "
bitfld.long 0x08 7. " [71] ,New Data Flag 71" "Not detected,Detected"
bitfld.long 0x08 6. " [70] ,New Data Flag 70" "Not detected,Detected"
bitfld.long 0x08 5. " [69] ,New Data Flag 69" "Not detected,Detected"
bitfld.long 0x08 4. " [68] ,New Data Flag 68" "Not detected,Detected"
textline " "
bitfld.long 0x08 3. " [67] ,New Data Flag 67" "Not detected,Detected"
bitfld.long 0x08 2. " [66] ,New Data Flag 66" "Not detected,Detected"
bitfld.long 0x08 1. " [65] ,New Data Flag 65" "Not detected,Detected"
bitfld.long 0x08 0. " [64] ,New Data Flag 64" "Not detected,Detected"
line.long 0x0C "NDAT4,FlexRay New Data Register 4"
bitfld.long 0x0C 31. " ND [127] ,New Data Flag 127" "Not detected,Detected"
bitfld.long 0x0C 30. " [126] ,New Data Flag 126" "Not detected,Detected"
bitfld.long 0x0C 29. " [125] ,New Data Flag 125" "Not detected,Detected"
bitfld.long 0x0C 28. " [124] ,New Data Flag 124" "Not detected,Detected"
textline " "
bitfld.long 0x0C 27. " [123] ,New Data Flag 123" "Not detected,Detected"
bitfld.long 0x0C 26. " [122] ,New Data Flag 122" "Not detected,Detected"
bitfld.long 0x0C 25. " [121] ,New Data Flag 121" "Not detected,Detected"
bitfld.long 0x0C 24. " [120] ,New Data Flag 120" "Not detected,Detected"
textline " "
bitfld.long 0x0C 23. " [119] ,New Data Flag 119" "Not detected,Detected"
bitfld.long 0x0C 22. " [118] ,New Data Flag 118" "Not detected,Detected"
bitfld.long 0x0C 21. " [117] ,New Data Flag 117" "Not detected,Detected"
bitfld.long 0x0C 20. " [116] ,New Data Flag 116" "Not detected,Detected"
textline " "
bitfld.long 0x0C 19. " [115] ,New Data Flag 115" "Not detected,Detected"
bitfld.long 0x0C 18. " [114] ,New Data Flag 114" "Not detected,Detected"
bitfld.long 0x0C 17. " [113] ,New Data Flag 113" "Not detected,Detected"
bitfld.long 0x0C 16. " [112] ,New Data Flag 112" "Not detected,Detected"
textline " "
bitfld.long 0x0C 15. " [111] ,New Data Flag 111" "Not detected,Detected"
bitfld.long 0x0C 14. " [110] ,New Data Flag 110" "Not detected,Detected"
bitfld.long 0x0C 13. " [109] ,New Data Flag 109" "Not detected,Detected"
bitfld.long 0x0C 12. " [108] ,New Data Flag 108" "Not detected,Detected"
textline " "
bitfld.long 0x0C 11. " [107] ,New Data Flag 107" "Not detected,Detected"
bitfld.long 0x0C 10. " [106] ,New Data Flag 106" "Not detected,Detected"
bitfld.long 0x0C 9. " [105] ,New Data Flag 105" "Not detected,Detected"
bitfld.long 0x0C 8. " [104] ,New Data Flag 104" "Not detected,Detected"
textline " "
bitfld.long 0x0C 7. " [103] ,New Data Flag 103" "Not detected,Detected"
bitfld.long 0x0C 6. " [102] ,New Data Flag 102" "Not detected,Detected"
bitfld.long 0x0C 5. " [101] ,New Data Flag 101" "Not detected,Detected"
bitfld.long 0x0C 4. " [100] ,New Data Flag 100" "Not detected,Detected"
textline " "
bitfld.long 0x0C 3. " [99] ,New Data Flag 99" "Not detected,Detected"
bitfld.long 0x0C 2. " [98] ,New Data Flag 98" "Not detected,Detected"
bitfld.long 0x0C 1. " [97] ,New Data Flag 97" "Not detected,Detected"
bitfld.long 0x0C 0. " [96] ,New Data Flag 96" "Not detected,Detected"
rgroup.long 0x340++0xF
line.long 0x0 "MBSC1,Message buffer status changed 1"
bitfld.long 0x00 31. " MBS [31] ,Message Buffer Status Changed Flag 31" "Not changed,Changed"
bitfld.long 0x00 30. " [30] ,Message Buffer Status Changed Flag 30" "Not changed,Changed"
bitfld.long 0x00 29. " [29] ,Message Buffer Status Changed Flag 29" "Not changed,Changed"
bitfld.long 0x00 28. " [28] ,Message Buffer Status Changed Flag 28" "Not changed,Changed"
textline " "
bitfld.long 0x00 27. " [27] ,Message Buffer Status Changed Flag 27" "Not changed,Changed"
bitfld.long 0x00 26. " [26] ,Message Buffer Status Changed Flag 26" "Not changed,Changed"
bitfld.long 0x00 25. " [25] ,Message Buffer Status Changed Flag 25" "Not changed,Changed"
bitfld.long 0x00 24. " [24] ,Message Buffer Status Changed Flag 24" "Not changed,Changed"
textline " "
bitfld.long 0x00 23. " [23] ,Message Buffer Status Changed Flag 23" "Not changed,Changed"
bitfld.long 0x00 22. " [22] ,Message Buffer Status Changed Flag 22" "Not changed,Changed"
bitfld.long 0x00 21. " [21] ,Message Buffer Status Changed Flag 21" "Not changed,Changed"
bitfld.long 0x00 20. " [20] ,Message Buffer Status Changed Flag 20" "Not changed,Changed"
textline " "
bitfld.long 0x00 19. " [19] ,Message Buffer Status Changed Flag 19" "Not changed,Changed"
bitfld.long 0x00 18. " [18] ,Message Buffer Status Changed Flag 18" "Not changed,Changed"
bitfld.long 0x00 17. " [17] ,Message Buffer Status Changed Flag 17" "Not changed,Changed"
bitfld.long 0x00 16. " [16] ,Message Buffer Status Changed Flag 16" "Not changed,Changed"
textline " "
bitfld.long 0x00 15. " [15] ,Message Buffer Status Changed Flag 15" "Not changed,Changed"
bitfld.long 0x00 14. " [14] ,Message Buffer Status Changed Flag 14" "Not changed,Changed"
bitfld.long 0x00 13. " [13] ,Message Buffer Status Changed Flag 13" "Not changed,Changed"
bitfld.long 0x00 12. " [12] ,Message Buffer Status Changed Flag 12" "Not changed,Changed"
textline " "
bitfld.long 0x00 11. " [11] ,Message Buffer Status Changed Flag 11" "Not changed,Changed"
bitfld.long 0x00 10. " [10] ,Message Buffer Status Changed Flag 10" "Not changed,Changed"
bitfld.long 0x00 9. " [9] ,Message Buffer Status Changed Flag 9" "Not changed,Changed"
bitfld.long 0x00 8. " [8] ,Message Buffer Status Changed Flag 8" "Not changed,Changed"
textline " "
bitfld.long 0x00 7. " [7] ,Message Buffer Status Changed Flag 7" "Not changed,Changed"
bitfld.long 0x00 6. " [6] ,Message Buffer Status Changed Flag 6" "Not changed,Changed"
bitfld.long 0x00 5. " [5] ,Message Buffer Status Changed Flag 5" "Not changed,Changed"
bitfld.long 0x00 4. " [4] ,Message Buffer Status Changed Flag 4" "Not changed,Changed"
textline " "
bitfld.long 0x00 3. " [3] ,Message Buffer Status Changed Flag 3" "Not changed,Changed"
bitfld.long 0x00 2. " [2] ,Message Buffer Status Changed Flag 2" "Not changed,Changed"
bitfld.long 0x00 1. " [1] ,Message Buffer Status Changed Flag 1" "Not changed,Changed"
bitfld.long 0x00 0. " [0] ,Message Buffer Status Changed Flag 0" "Not changed,Changed"
line.long 0x04 "FRMBSC2,FlexRay Message Buffer Status Changed Register 2"
bitfld.long 0x04 31. " MBS [63] ,Message Buffer Status Changed Flag 63" "Not changed,Changed"
bitfld.long 0x04 30. " [62] ,Message Buffer Status Changed Flag 62" "Not changed,Changed"
bitfld.long 0x04 29. " [61] ,Message Buffer Status Changed Flag 61" "Not changed,Changed"
bitfld.long 0x04 28. " [60] ,Message Buffer Status Changed Flag 60" "Not changed,Changed"
textline " "
bitfld.long 0x04 27. " [59] ,Message Buffer Status Changed Flag 59" "Not changed,Changed"
bitfld.long 0x04 26. " [58] ,Message Buffer Status Changed Flag 58" "Not changed,Changed"
bitfld.long 0x04 25. " [57] ,Message Buffer Status Changed Flag 57" "Not changed,Changed"
bitfld.long 0x04 24. " [56] ,Message Buffer Status Changed Flag 56" "Not changed,Changed"
textline " "
bitfld.long 0x04 23. " [55] ,Message Buffer Status Changed Flag 55" "Not changed,Changed"
bitfld.long 0x04 22. " [54] ,Message Buffer Status Changed Flag 54" "Not changed,Changed"
bitfld.long 0x04 21. " [53] ,Message Buffer Status Changed Flag 53" "Not changed,Changed"
bitfld.long 0x04 20. " [52] ,Message Buffer Status Changed Flag 52" "Not changed,Changed"
textline " "
bitfld.long 0x04 19. " [51] ,Message Buffer Status Changed Flag 51" "Not changed,Changed"
bitfld.long 0x04 18. " [50] ,Message Buffer Status Changed Flag 50" "Not changed,Changed"
bitfld.long 0x04 17. " [49] ,Message Buffer Status Changed Flag 49" "Not changed,Changed"
bitfld.long 0x04 16. " [48] ,Message Buffer Status Changed Flag 48" "Not changed,Changed"
textline " "
bitfld.long 0x04 15. " [47] ,Message Buffer Status Changed Flag 47" "Not changed,Changed"
bitfld.long 0x04 14. " [46] ,Message Buffer Status Changed Flag 46" "Not changed,Changed"
bitfld.long 0x04 13. " [45] ,Message Buffer Status Changed Flag 45" "Not changed,Changed"
bitfld.long 0x04 12. " [44] ,Message Buffer Status Changed Flag 44" "Not changed,Changed"
textline " "
bitfld.long 0x04 11. " [43] ,Message Buffer Status Changed Flag 43" "Not changed,Changed"
bitfld.long 0x04 10. " [42] ,Message Buffer Status Changed Flag 42" "Not changed,Changed"
bitfld.long 0x04 9. " [41] ,Message Buffer Status Changed Flag 41" "Not changed,Changed"
bitfld.long 0x04 8. " [40] ,Message Buffer Status Changed Flag 40" "Not changed,Changed"
textline " "
bitfld.long 0x04 7. " [39] ,Message Buffer Status Changed Flag 39" "Not changed,Changed"
bitfld.long 0x04 6. " [38] ,Message Buffer Status Changed Flag 38" "Not changed,Changed"
bitfld.long 0x04 5. " [37] ,Message Buffer Status Changed Flag 37" "Not changed,Changed"
bitfld.long 0x04 4. " [36] ,Message Buffer Status Changed Flag 36" "Not changed,Changed"
textline " "
bitfld.long 0x04 3. " [35] ,Message Buffer Status Changed Flag 35" "Not changed,Changed"
bitfld.long 0x04 2. " [34] ,Message Buffer Status Changed Flag 34" "Not changed,Changed"
bitfld.long 0x04 1. " [33] ,Message Buffer Status Changed Flag 33" "Not changed,Changed"
bitfld.long 0x04 0. " [32] ,Message Buffer Status Changed Flag 32" "Not changed,Changed"
line.long 0x08 "FRMBSC3,FlexRay Message Buffer Status Changed Register 3"
bitfld.long 0x08 31. " MBS [95] ,Message Buffer Status Changed Flag 95" "Not changed,Changed"
bitfld.long 0x08 30. " [94] ,Message Buffer Status Changed Flag 94" "Not changed,Changed"
bitfld.long 0x08 29. " [93] ,Message Buffer Status Changed Flag 93" "Not changed,Changed"
bitfld.long 0x08 28. " [92] ,Message Buffer Status Changed Flag 92" "Not changed,Changed"
textline " "
bitfld.long 0x08 27. " [91] ,Message Buffer Status Changed Flag 91" "Not changed,Changed"
bitfld.long 0x08 26. " [90] ,Message Buffer Status Changed Flag 90" "Not changed,Changed"
bitfld.long 0x08 25. " [89] ,Message Buffer Status Changed Flag 89" "Not changed,Changed"
bitfld.long 0x08 24. " [88] ,Message Buffer Status Changed Flag 88" "Not changed,Changed"
textline " "
bitfld.long 0x08 23. " [87] ,Message Buffer Status Changed Flag 87" "Not changed,Changed"
bitfld.long 0x08 22. " [86] ,Message Buffer Status Changed Flag 86" "Not changed,Changed"
bitfld.long 0x08 21. " [85] ,Message Buffer Status Changed Flag 85" "Not changed,Changed"
bitfld.long 0x08 20. " [84] ,Message Buffer Status Changed Flag 84" "Not changed,Changed"
textline " "
bitfld.long 0x08 19. " [83] ,Message Buffer Status Changed Flag 83" "Not changed,Changed"
bitfld.long 0x08 18. " [82] ,Message Buffer Status Changed Flag 82" "Not changed,Changed"
bitfld.long 0x08 17. " [81] ,Message Buffer Status Changed Flag 81" "Not changed,Changed"
bitfld.long 0x08 16. " [80] ,Message Buffer Status Changed Flag 80" "Not changed,Changed"
textline " "
bitfld.long 0x08 15. " [79] ,Message Buffer Status Changed Flag 79" "Not changed,Changed"
bitfld.long 0x08 14. " [78] ,Message Buffer Status Changed Flag 78" "Not changed,Changed"
bitfld.long 0x08 13. " [77] ,Message Buffer Status Changed Flag 77" "Not changed,Changed"
bitfld.long 0x08 12. " [76] ,Message Buffer Status Changed Flag 76" "Not changed,Changed"
textline " "
bitfld.long 0x08 11. " [75] ,Message Buffer Status Changed Flag 75" "Not changed,Changed"
bitfld.long 0x08 10. " [74] ,Message Buffer Status Changed Flag 74" "Not changed,Changed"
bitfld.long 0x08 9. " [73] ,Message Buffer Status Changed Flag 73" "Not changed,Changed"
bitfld.long 0x08 8. " [72] ,Message Buffer Status Changed Flag 72" "Not changed,Changed"
textline " "
bitfld.long 0x08 7. " [71] ,Message Buffer Status Changed Flag 71" "Not changed,Changed"
bitfld.long 0x08 6. " [70] ,Message Buffer Status Changed Flag 70" "Not changed,Changed"
bitfld.long 0x08 5. " [69] ,Message Buffer Status Changed Flag 69" "Not changed,Changed"
bitfld.long 0x08 4. " [68] ,Message Buffer Status Changed Flag 68" "Not changed,Changed"
textline " "
bitfld.long 0x08 3. " [67] ,Message Buffer Status Changed Flag 67" "Not changed,Changed"
bitfld.long 0x08 2. " [66] ,Message Buffer Status Changed Flag 66" "Not changed,Changed"
bitfld.long 0x08 1. " [65] ,Message Buffer Status Changed Flag 65" "Not changed,Changed"
bitfld.long 0x08 0. " [64] ,Message Buffer Status Changed Flag 64" "Not changed,Changed"
line.long 0x0C "FRMBSC4,FlexRay Message Buffer Status Changed Register 4"
bitfld.long 0x0C 31. " MBS [127] ,Message Buffer Status Changed Flag 127" "Not changed,Changed"
bitfld.long 0x0C 30. " [126] ,Message Buffer Status Changed Flag 126" "Not changed,Changed"
bitfld.long 0x0C 29. " [125] ,Message Buffer Status Changed Flag 125" "Not changed,Changed"
bitfld.long 0x0C 28. " [124] ,Message Buffer Status Changed Flag 124" "Not changed,Changed"
textline " "
bitfld.long 0x0C 27. " [123] ,Message Buffer Status Changed Flag 123" "Not changed,Changed"
bitfld.long 0x0C 26. " [122] ,Message Buffer Status Changed Flag 122" "Not changed,Changed"
bitfld.long 0x0C 25. " [121] ,Message Buffer Status Changed Flag 121" "Not changed,Changed"
bitfld.long 0x0C 24. " [120] ,Message Buffer Status Changed Flag 120" "Not changed,Changed"
textline " "
bitfld.long 0x0C 23. " [119] ,Message Buffer Status Changed Flag 119" "Not changed,Changed"
bitfld.long 0x0C 22. " [118] ,Message Buffer Status Changed Flag 118" "Not changed,Changed"
bitfld.long 0x0C 21. " [117] ,Message Buffer Status Changed Flag 117" "Not changed,Changed"
bitfld.long 0x0C 20. " [116] ,Message Buffer Status Changed Flag 116" "Not changed,Changed"
textline " "
bitfld.long 0x0C 19. " [115] ,Message Buffer Status Changed Flag 115" "Not changed,Changed"
bitfld.long 0x0C 18. " [114] ,Message Buffer Status Changed Flag 114" "Not changed,Changed"
bitfld.long 0x0C 17. " [113] ,Message Buffer Status Changed Flag 113" "Not changed,Changed"
bitfld.long 0x0C 16. " [112] ,Message Buffer Status Changed Flag 112" "Not changed,Changed"
textline " "
bitfld.long 0x0C 15. " [111] ,Message Buffer Status Changed Flag 111" "Not changed,Changed"
bitfld.long 0x0C 14. " [110] ,Message Buffer Status Changed Flag 110" "Not changed,Changed"
bitfld.long 0x0C 13. " [109] ,Message Buffer Status Changed Flag 109" "Not changed,Changed"
bitfld.long 0x0C 12. " [108] ,Message Buffer Status Changed Flag 108" "Not changed,Changed"
textline " "
bitfld.long 0x0C 11. " [107] ,Message Buffer Status Changed Flag 107" "Not changed,Changed"
bitfld.long 0x0C 10. " [106] ,Message Buffer Status Changed Flag 106" "Not changed,Changed"
bitfld.long 0x0C 9. " [105] ,Message Buffer Status Changed Flag 105" "Not changed,Changed"
bitfld.long 0x0C 8. " [104] ,Message Buffer Status Changed Flag 104" "Not changed,Changed"
textline " "
bitfld.long 0x0C 7. " [103] ,Message Buffer Status Changed Flag 103" "Not changed,Changed"
bitfld.long 0x0C 6. " [102] ,Message Buffer Status Changed Flag 102" "Not changed,Changed"
bitfld.long 0x0C 5. " [101] ,Message Buffer Status Changed Flag 101" "Not changed,Changed"
bitfld.long 0x0C 4. " [100] ,Message Buffer Status Changed Flag 100" "Not changed,Changed"
textline " "
bitfld.long 0x0C 3. " [99] ,Message Buffer Status Changed Flag 99" "Not changed,Changed"
bitfld.long 0x0C 2. " [98] ,Message Buffer Status Changed Flag 98" "Not changed,Changed"
bitfld.long 0x0C 1. " [97] ,Message Buffer Status Changed Flag 97" "Not changed,Changed"
bitfld.long 0x0C 0. " [96] ,Message Buffer Status Changed Flag 96" "Not changed,Changed"
tree.end
width 6.
tree "Identification Registers"
group.long 0x3F0++0x3
line.long 0x00 "CREL,Core Release Register"
bitfld.long 0x00 28.--31. " REL ,Core Release" ",1,?..."
hexmask.long.byte 0x00 20.--27. 1. " STEP ,Step of Core Release"
textline " "
bitfld.long 0x00 16.--19. " YEAR ,Design Time Stamp- Year" "0,1,2,3,4,5,6,7,8,9,-,-,-,?..."
hexmask.long.byte 0x00 8.--15. 1. " MON ,Design Time Stamp- Month"
textline " "
hexmask.long.byte 0x00 0.--7. 1. " DAY ,Design Time Stamp- Day"
rgroup.long 0x3F4++0x3
line.long 0x0 "ENDN,Endian register"
tree.end
width 8.
tree "Input Buffer"
group.long 0x400++0x23
line.long 0x0 "WRDS1,Write data section [1]"
hexmask.long.byte 0x0 24.--31. 1. " MD [3] ,Message Data Byte 3"
hexmask.long.byte 0x0 16.--23. 1. " [2] ,Message Data Byte 2"
hexmask.long.byte 0x0 8.--15. 1. " [1] ,Message Data Byte 1"
hexmask.long.byte 0x0 0.--7. 1. " [0] ,Message Data Byte 0"
line.long 0x4 "WRDS2,Write data section [2]"
hexmask.long.byte 0x4 24.--31. 1. " MD [3] ,Message Data Byte 3"
hexmask.long.byte 0x4 16.--23. 1. " [2] ,Message Data Byte 2"
hexmask.long.byte 0x4 8.--15. 1. " [1] ,Message Data Byte 1"
hexmask.long.byte 0x4 0.--7. 1. " [0] ,Message Data Byte 0"
line.long 0x8 "WRDS3,Write data section [3]"
hexmask.long.byte 0x8 24.--31. 1. " MD [3] ,Message Data Byte 3"
hexmask.long.byte 0x8 16.--23. 1. " [2] ,Message Data Byte 2"
hexmask.long.byte 0x8 8.--15. 1. " [1] ,Message Data Byte 1"
hexmask.long.byte 0x8 0.--7. 1. " [0] ,Message Data Byte 0"
line.long 0xC "WRDS4,Write data section [4]"
hexmask.long.byte 0xC 24.--31. 1. " MD [3] ,Message Data Byte 3"
hexmask.long.byte 0xC 16.--23. 1. " [2] ,Message Data Byte 2"
hexmask.long.byte 0xC 8.--15. 1. " [1] ,Message Data Byte 1"
hexmask.long.byte 0xC 0.--7. 1. " [0] ,Message Data Byte 0"
line.long 0x10 "WRDS5,Write data section [5]"
hexmask.long.byte 0x10 24.--31. 1. " MD [3] ,Message Data Byte 3"
hexmask.long.byte 0x10 16.--23. 1. " [2] ,Message Data Byte 2"
hexmask.long.byte 0x10 8.--15. 1. " [1] ,Message Data Byte 1"
hexmask.long.byte 0x10 0.--7. 1. " [0] ,Message Data Byte 0"
line.long 0x14 "WRDS6,Write data section [6]"
hexmask.long.byte 0x14 24.--31. 1. " MD [3] ,Message Data Byte 3"
hexmask.long.byte 0x14 16.--23. 1. " [2] ,Message Data Byte 2"
hexmask.long.byte 0x14 8.--15. 1. " [1] ,Message Data Byte 1"
hexmask.long.byte 0x14 0.--7. 1. " [0] ,Message Data Byte 0"
line.long 0x18 "WRDS7,Write data section [7]"
hexmask.long.byte 0x18 24.--31. 1. " MD [3] ,Message Data Byte 3"
hexmask.long.byte 0x18 16.--23. 1. " [2] ,Message Data Byte 2"
hexmask.long.byte 0x18 8.--15. 1. " [1] ,Message Data Byte 1"
hexmask.long.byte 0x18 0.--7. 1. " [0] ,Message Data Byte 0"
line.long 0x1C "WRDS8,Write data section [8]"
hexmask.long.byte 0x1C 24.--31. 1. " MD [3] ,Message Data Byte 3"
hexmask.long.byte 0x1C 16.--23. 1. " [2] ,Message Data Byte 2"
hexmask.long.byte 0x1C 8.--15. 1. " [1] ,Message Data Byte 1"
hexmask.long.byte 0x1C 0.--7. 1. " [0] ,Message Data Byte 0"
line.long 0x20 "WRDS9,Write data section [9]"
hexmask.long.byte 0x20 24.--31. 1. " MD [3] ,Message Data Byte 3"
hexmask.long.byte 0x20 16.--23. 1. " [2] ,Message Data Byte 2"
hexmask.long.byte 0x20 8.--15. 1. " [1] ,Message Data Byte 1"
hexmask.long.byte 0x20 0.--7. 1. " [0] ,Message Data Byte 0"
group.long 0x424++0xDB
line.long 0x0 "WRDS10,Write data section [10]"
hexmask.long.byte 0x0 24.--31. 1. " MD [3] ,Message Data Byte 3"
hexmask.long.byte 0x0 16.--23. 1. " [2] ,Message Data Byte 2"
hexmask.long.byte 0x0 8.--15. 1. " [1] ,Message Data Byte 1"
hexmask.long.byte 0x0 0.--7. 1. " [0] ,Message Data Byte 0"
line.long 0x4 "WRDS11,Write data section [11]"
hexmask.long.byte 0x4 24.--31. 1. " MD [3] ,Message Data Byte 3"
hexmask.long.byte 0x4 16.--23. 1. " [2] ,Message Data Byte 2"
hexmask.long.byte 0x4 8.--15. 1. " [1] ,Message Data Byte 1"
hexmask.long.byte 0x4 0.--7. 1. " [0] ,Message Data Byte 0"
line.long 0x8 "WRDS12,Write data section [12]"
hexmask.long.byte 0x8 24.--31. 1. " MD [3] ,Message Data Byte 3"
hexmask.long.byte 0x8 16.--23. 1. " [2] ,Message Data Byte 2"
hexmask.long.byte 0x8 8.--15. 1. " [1] ,Message Data Byte 1"
hexmask.long.byte 0x8 0.--7. 1. " [0] ,Message Data Byte 0"
line.long 0xC "WRDS13,Write data section [13]"
hexmask.long.byte 0xC 24.--31. 1. " MD [3] ,Message Data Byte 3"
hexmask.long.byte 0xC 16.--23. 1. " [2] ,Message Data Byte 2"
hexmask.long.byte 0xC 8.--15. 1. " [1] ,Message Data Byte 1"
hexmask.long.byte 0xC 0.--7. 1. " [0] ,Message Data Byte 0"
line.long 0x10 "WRDS14,Write data section [14]"
hexmask.long.byte 0x10 24.--31. 1. " MD [3] ,Message Data Byte 3"
hexmask.long.byte 0x10 16.--23. 1. " [2] ,Message Data Byte 2"
hexmask.long.byte 0x10 8.--15. 1. " [1] ,Message Data Byte 1"
hexmask.long.byte 0x10 0.--7. 1. " [0] ,Message Data Byte 0"
line.long 0x14 "WRDS15,Write data section [15]"
hexmask.long.byte 0x14 24.--31. 1. " MD [3] ,Message Data Byte 3"
hexmask.long.byte 0x14 16.--23. 1. " [2] ,Message Data Byte 2"
hexmask.long.byte 0x14 8.--15. 1. " [1] ,Message Data Byte 1"
hexmask.long.byte 0x14 0.--7. 1. " [0] ,Message Data Byte 0"
line.long 0x18 "WRDS16,Write data section [16]"
hexmask.long.byte 0x18 24.--31. 1. " MD [3] ,Message Data Byte 3"
hexmask.long.byte 0x18 16.--23. 1. " [2] ,Message Data Byte 2"
hexmask.long.byte 0x18 8.--15. 1. " [1] ,Message Data Byte 1"
hexmask.long.byte 0x18 0.--7. 1. " [0] ,Message Data Byte 0"
line.long 0x1C "WRDS17,Write data section [17]"
hexmask.long.byte 0x1C 24.--31. 1. " MD [3] ,Message Data Byte 3"
hexmask.long.byte 0x1C 16.--23. 1. " [2] ,Message Data Byte 2"
hexmask.long.byte 0x1C 8.--15. 1. " [1] ,Message Data Byte 1"
hexmask.long.byte 0x1C 0.--7. 1. " [0] ,Message Data Byte 0"
line.long 0x20 "WRDS18,Write data section [18]"
hexmask.long.byte 0x20 24.--31. 1. " MD [3] ,Message Data Byte 3"
hexmask.long.byte 0x20 16.--23. 1. " [2] ,Message Data Byte 2"
hexmask.long.byte 0x20 8.--15. 1. " [1] ,Message Data Byte 1"
hexmask.long.byte 0x20 0.--7. 1. " [0] ,Message Data Byte 0"
line.long 0x24 "WRDS19,Write data section [19]"
hexmask.long.byte 0x24 24.--31. 1. " MD [3] ,Message Data Byte 3"
hexmask.long.byte 0x24 16.--23. 1. " [2] ,Message Data Byte 2"
hexmask.long.byte 0x24 8.--15. 1. " [1] ,Message Data Byte 1"
hexmask.long.byte 0x24 0.--7. 1. " [0] ,Message Data Byte 0"
line.long 0x28 "WRDS20,Write data section [20]"
hexmask.long.byte 0x28 24.--31. 1. " MD [3] ,Message Data Byte 3"
hexmask.long.byte 0x28 16.--23. 1. " [2] ,Message Data Byte 2"
hexmask.long.byte 0x28 8.--15. 1. " [1] ,Message Data Byte 1"
hexmask.long.byte 0x28 0.--7. 1. " [0] ,Message Data Byte 0"
line.long 0x2C "WRDS21,Write data section [21]"
hexmask.long.byte 0x2C 24.--31. 1. " MD [3] ,Message Data Byte 3"
hexmask.long.byte 0x2C 16.--23. 1. " [2] ,Message Data Byte 2"
hexmask.long.byte 0x2C 8.--15. 1. " [1] ,Message Data Byte 1"
hexmask.long.byte 0x2C 0.--7. 1. " [0] ,Message Data Byte 0"
line.long 0x30 "WRDS22,Write data section [22]"
hexmask.long.byte 0x30 24.--31. 1. " MD [3] ,Message Data Byte 3"
hexmask.long.byte 0x30 16.--23. 1. " [2] ,Message Data Byte 2"
hexmask.long.byte 0x30 8.--15. 1. " [1] ,Message Data Byte 1"
hexmask.long.byte 0x30 0.--7. 1. " [0] ,Message Data Byte 0"
line.long 0x34 "WRDS23,Write data section [23]"
hexmask.long.byte 0x34 24.--31. 1. " MD [3] ,Message Data Byte 3"
hexmask.long.byte 0x34 16.--23. 1. " [2] ,Message Data Byte 2"
hexmask.long.byte 0x34 8.--15. 1. " [1] ,Message Data Byte 1"
hexmask.long.byte 0x34 0.--7. 1. " [0] ,Message Data Byte 0"
line.long 0x38 "WRDS24,Write data section [24]"
hexmask.long.byte 0x38 24.--31. 1. " MD [3] ,Message Data Byte 3"
hexmask.long.byte 0x38 16.--23. 1. " [2] ,Message Data Byte 2"
hexmask.long.byte 0x38 8.--15. 1. " [1] ,Message Data Byte 1"
hexmask.long.byte 0x38 0.--7. 1. " [0] ,Message Data Byte 0"
line.long 0x3C "WRDS25,Write data section [25]"
hexmask.long.byte 0x3C 24.--31. 1. " MD [3] ,Message Data Byte 3"
hexmask.long.byte 0x3C 16.--23. 1. " [2] ,Message Data Byte 2"
hexmask.long.byte 0x3C 8.--15. 1. " [1] ,Message Data Byte 1"
hexmask.long.byte 0x3C 0.--7. 1. " [0] ,Message Data Byte 0"
line.long 0x40 "WRDS26,Write data section [26]"
hexmask.long.byte 0x40 24.--31. 1. " MD [3] ,Message Data Byte 3"
hexmask.long.byte 0x40 16.--23. 1. " [2] ,Message Data Byte 2"
hexmask.long.byte 0x40 8.--15. 1. " [1] ,Message Data Byte 1"
hexmask.long.byte 0x40 0.--7. 1. " [0] ,Message Data Byte 0"
line.long 0x44 "WRDS27,Write data section [27]"
hexmask.long.byte 0x44 24.--31. 1. " MD [3] ,Message Data Byte 3"
hexmask.long.byte 0x44 16.--23. 1. " [2] ,Message Data Byte 2"
hexmask.long.byte 0x44 8.--15. 1. " [1] ,Message Data Byte 1"
hexmask.long.byte 0x44 0.--7. 1. " [0] ,Message Data Byte 0"
line.long 0x48 "WRDS28,Write data section [28]"
hexmask.long.byte 0x48 24.--31. 1. " MD [3] ,Message Data Byte 3"
hexmask.long.byte 0x48 16.--23. 1. " [2] ,Message Data Byte 2"
hexmask.long.byte 0x48 8.--15. 1. " [1] ,Message Data Byte 1"
hexmask.long.byte 0x48 0.--7. 1. " [0] ,Message Data Byte 0"
line.long 0x4C "WRDS29,Write data section [29]"
hexmask.long.byte 0x4C 24.--31. 1. " MD [3] ,Message Data Byte 3"
hexmask.long.byte 0x4C 16.--23. 1. " [2] ,Message Data Byte 2"
hexmask.long.byte 0x4C 8.--15. 1. " [1] ,Message Data Byte 1"
hexmask.long.byte 0x4C 0.--7. 1. " [0] ,Message Data Byte 0"
line.long 0x50 "WRDS30,Write data section [30]"
hexmask.long.byte 0x50 24.--31. 1. " MD [3] ,Message Data Byte 3"
hexmask.long.byte 0x50 16.--23. 1. " [2] ,Message Data Byte 2"
hexmask.long.byte 0x50 8.--15. 1. " [1] ,Message Data Byte 1"
hexmask.long.byte 0x50 0.--7. 1. " [0] ,Message Data Byte 0"
line.long 0x54 "WRDS31,Write data section [31]"
hexmask.long.byte 0x54 24.--31. 1. " MD [3] ,Message Data Byte 3"
hexmask.long.byte 0x54 16.--23. 1. " [2] ,Message Data Byte 2"
hexmask.long.byte 0x54 8.--15. 1. " [1] ,Message Data Byte 1"
hexmask.long.byte 0x54 0.--7. 1. " [0] ,Message Data Byte 0"
line.long 0x58 "WRDS32,Write data section [32]"
hexmask.long.byte 0x58 24.--31. 1. " MD [3] ,Message Data Byte 3"
hexmask.long.byte 0x58 16.--23. 1. " [2] ,Message Data Byte 2"
hexmask.long.byte 0x58 8.--15. 1. " [1] ,Message Data Byte 1"
hexmask.long.byte 0x58 0.--7. 1. " [0] ,Message Data Byte 0"
line.long 0x5C "WRDS33,Write data section [33]"
hexmask.long.byte 0x5C 24.--31. 1. " MD [3] ,Message Data Byte 3"
hexmask.long.byte 0x5C 16.--23. 1. " [2] ,Message Data Byte 2"
hexmask.long.byte 0x5C 8.--15. 1. " [1] ,Message Data Byte 1"
hexmask.long.byte 0x5C 0.--7. 1. " [0] ,Message Data Byte 0"
line.long 0x60 "WRDS34,Write data section [34]"
hexmask.long.byte 0x60 24.--31. 1. " MD [3] ,Message Data Byte 3"
hexmask.long.byte 0x60 16.--23. 1. " [2] ,Message Data Byte 2"
hexmask.long.byte 0x60 8.--15. 1. " [1] ,Message Data Byte 1"
hexmask.long.byte 0x60 0.--7. 1. " [0] ,Message Data Byte 0"
line.long 0x64 "WRDS35,Write data section [35]"
hexmask.long.byte 0x64 24.--31. 1. " MD [3] ,Message Data Byte 3"
hexmask.long.byte 0x64 16.--23. 1. " [2] ,Message Data Byte 2"
hexmask.long.byte 0x64 8.--15. 1. " [1] ,Message Data Byte 1"
hexmask.long.byte 0x64 0.--7. 1. " [0] ,Message Data Byte 0"
line.long 0x68 "WRDS36,Write data section [36]"
hexmask.long.byte 0x68 24.--31. 1. " MD [3] ,Message Data Byte 3"
hexmask.long.byte 0x68 16.--23. 1. " [2] ,Message Data Byte 2"
hexmask.long.byte 0x68 8.--15. 1. " [1] ,Message Data Byte 1"
hexmask.long.byte 0x68 0.--7. 1. " [0] ,Message Data Byte 0"
line.long 0x6C "WRDS37,Write data section [37]"
hexmask.long.byte 0x6C 24.--31. 1. " MD [3] ,Message Data Byte 3"
hexmask.long.byte 0x6C 16.--23. 1. " [2] ,Message Data Byte 2"
hexmask.long.byte 0x6C 8.--15. 1. " [1] ,Message Data Byte 1"
hexmask.long.byte 0x6C 0.--7. 1. " [0] ,Message Data Byte 0"
line.long 0x70 "WRDS38,Write data section [38]"
hexmask.long.byte 0x70 24.--31. 1. " MD [3] ,Message Data Byte 3"
hexmask.long.byte 0x70 16.--23. 1. " [2] ,Message Data Byte 2"
hexmask.long.byte 0x70 8.--15. 1. " [1] ,Message Data Byte 1"
hexmask.long.byte 0x70 0.--7. 1. " [0] ,Message Data Byte 0"
line.long 0x74 "WRDS39,Write data section [39]"
hexmask.long.byte 0x74 24.--31. 1. " MD [3] ,Message Data Byte 3"
hexmask.long.byte 0x74 16.--23. 1. " [2] ,Message Data Byte 2"
hexmask.long.byte 0x74 8.--15. 1. " [1] ,Message Data Byte 1"
hexmask.long.byte 0x74 0.--7. 1. " [0] ,Message Data Byte 0"
line.long 0x78 "WRDS40,Write data section [40]"
hexmask.long.byte 0x78 24.--31. 1. " MD [3] ,Message Data Byte 3"
hexmask.long.byte 0x78 16.--23. 1. " [2] ,Message Data Byte 2"
hexmask.long.byte 0x78 8.--15. 1. " [1] ,Message Data Byte 1"
hexmask.long.byte 0x78 0.--7. 1. " [0] ,Message Data Byte 0"
line.long 0x7C "WRDS41,Write data section [41]"
hexmask.long.byte 0x7C 24.--31. 1. " MD [3] ,Message Data Byte 3"
hexmask.long.byte 0x7C 16.--23. 1. " [2] ,Message Data Byte 2"
hexmask.long.byte 0x7C 8.--15. 1. " [1] ,Message Data Byte 1"
hexmask.long.byte 0x7C 0.--7. 1. " [0] ,Message Data Byte 0"
line.long 0x80 "WRDS42,Write data section [42]"
hexmask.long.byte 0x80 24.--31. 1. " MD [3] ,Message Data Byte 3"
hexmask.long.byte 0x80 16.--23. 1. " [2] ,Message Data Byte 2"
hexmask.long.byte 0x80 8.--15. 1. " [1] ,Message Data Byte 1"
hexmask.long.byte 0x80 0.--7. 1. " [0] ,Message Data Byte 0"
line.long 0x84 "WRDS43,Write data section [43]"
hexmask.long.byte 0x84 24.--31. 1. " MD [3] ,Message Data Byte 3"
hexmask.long.byte 0x84 16.--23. 1. " [2] ,Message Data Byte 2"
hexmask.long.byte 0x84 8.--15. 1. " [1] ,Message Data Byte 1"
hexmask.long.byte 0x84 0.--7. 1. " [0] ,Message Data Byte 0"
line.long 0x88 "WRDS44,Write data section [44]"
hexmask.long.byte 0x88 24.--31. 1. " MD [3] ,Message Data Byte 3"
hexmask.long.byte 0x88 16.--23. 1. " [2] ,Message Data Byte 2"
hexmask.long.byte 0x88 8.--15. 1. " [1] ,Message Data Byte 1"
hexmask.long.byte 0x88 0.--7. 1. " [0] ,Message Data Byte 0"
line.long 0x8C "WRDS45,Write data section [45]"
hexmask.long.byte 0x8C 24.--31. 1. " MD [3] ,Message Data Byte 3"
hexmask.long.byte 0x8C 16.--23. 1. " [2] ,Message Data Byte 2"
hexmask.long.byte 0x8C 8.--15. 1. " [1] ,Message Data Byte 1"
hexmask.long.byte 0x8C 0.--7. 1. " [0] ,Message Data Byte 0"
line.long 0x90 "WRDS46,Write data section [46]"
hexmask.long.byte 0x90 24.--31. 1. " MD [3] ,Message Data Byte 3"
hexmask.long.byte 0x90 16.--23. 1. " [2] ,Message Data Byte 2"
hexmask.long.byte 0x90 8.--15. 1. " [1] ,Message Data Byte 1"
hexmask.long.byte 0x90 0.--7. 1. " [0] ,Message Data Byte 0"
line.long 0x94 "WRDS47,Write data section [47]"
hexmask.long.byte 0x94 24.--31. 1. " MD [3] ,Message Data Byte 3"
hexmask.long.byte 0x94 16.--23. 1. " [2] ,Message Data Byte 2"
hexmask.long.byte 0x94 8.--15. 1. " [1] ,Message Data Byte 1"
hexmask.long.byte 0x94 0.--7. 1. " [0] ,Message Data Byte 0"
line.long 0x98 "WRDS48,Write data section [48]"
hexmask.long.byte 0x98 24.--31. 1. " MD [3] ,Message Data Byte 3"
hexmask.long.byte 0x98 16.--23. 1. " [2] ,Message Data Byte 2"
hexmask.long.byte 0x98 8.--15. 1. " [1] ,Message Data Byte 1"
hexmask.long.byte 0x98 0.--7. 1. " [0] ,Message Data Byte 0"
line.long 0x9C "WRDS49,Write data section [49]"
hexmask.long.byte 0x9C 24.--31. 1. " MD [3] ,Message Data Byte 3"
hexmask.long.byte 0x9C 16.--23. 1. " [2] ,Message Data Byte 2"
hexmask.long.byte 0x9C 8.--15. 1. " [1] ,Message Data Byte 1"
hexmask.long.byte 0x9C 0.--7. 1. " [0] ,Message Data Byte 0"
line.long 0xA0 "WRDS50,Write data section [50]"
hexmask.long.byte 0xA0 24.--31. 1. " MD [3] ,Message Data Byte 3"
hexmask.long.byte 0xA0 16.--23. 1. " [2] ,Message Data Byte 2"
hexmask.long.byte 0xA0 8.--15. 1. " [1] ,Message Data Byte 1"
hexmask.long.byte 0xA0 0.--7. 1. " [0] ,Message Data Byte 0"
line.long 0xA4 "WRDS51,Write data section [51]"
hexmask.long.byte 0xA4 24.--31. 1. " MD [3] ,Message Data Byte 3"
hexmask.long.byte 0xA4 16.--23. 1. " [2] ,Message Data Byte 2"
hexmask.long.byte 0xA4 8.--15. 1. " [1] ,Message Data Byte 1"
hexmask.long.byte 0xA4 0.--7. 1. " [0] ,Message Data Byte 0"
line.long 0xA8 "WRDS52,Write data section [52]"
hexmask.long.byte 0xA8 24.--31. 1. " MD [3] ,Message Data Byte 3"
hexmask.long.byte 0xA8 16.--23. 1. " [2] ,Message Data Byte 2"
hexmask.long.byte 0xA8 8.--15. 1. " [1] ,Message Data Byte 1"
hexmask.long.byte 0xA8 0.--7. 1. " [0] ,Message Data Byte 0"
line.long 0xAC "WRDS53,Write data section [53]"
hexmask.long.byte 0xAC 24.--31. 1. " MD [3] ,Message Data Byte 3"
hexmask.long.byte 0xAC 16.--23. 1. " [2] ,Message Data Byte 2"
hexmask.long.byte 0xAC 8.--15. 1. " [1] ,Message Data Byte 1"
hexmask.long.byte 0xAC 0.--7. 1. " [0] ,Message Data Byte 0"
line.long 0xB0 "WRDS54,Write data section [54]"
hexmask.long.byte 0xB0 24.--31. 1. " MD [3] ,Message Data Byte 3"
hexmask.long.byte 0xB0 16.--23. 1. " [2] ,Message Data Byte 2"
hexmask.long.byte 0xB0 8.--15. 1. " [1] ,Message Data Byte 1"
hexmask.long.byte 0xB0 0.--7. 1. " [0] ,Message Data Byte 0"
line.long 0xB4 "WRDS55,Write data section [55]"
hexmask.long.byte 0xB4 24.--31. 1. " MD [3] ,Message Data Byte 3"
hexmask.long.byte 0xB4 16.--23. 1. " [2] ,Message Data Byte 2"
hexmask.long.byte 0xB4 8.--15. 1. " [1] ,Message Data Byte 1"
hexmask.long.byte 0xB4 0.--7. 1. " [0] ,Message Data Byte 0"
line.long 0xB8 "WRDS56,Write data section [56]"
hexmask.long.byte 0xB8 24.--31. 1. " MD [3] ,Message Data Byte 3"
hexmask.long.byte 0xB8 16.--23. 1. " [2] ,Message Data Byte 2"
hexmask.long.byte 0xB8 8.--15. 1. " [1] ,Message Data Byte 1"
hexmask.long.byte 0xB8 0.--7. 1. " [0] ,Message Data Byte 0"
line.long 0xBC "WRDS57,Write data section [57]"
hexmask.long.byte 0xBC 24.--31. 1. " MD [3] ,Message Data Byte 3"
hexmask.long.byte 0xBC 16.--23. 1. " [2] ,Message Data Byte 2"
hexmask.long.byte 0xBC 8.--15. 1. " [1] ,Message Data Byte 1"
hexmask.long.byte 0xBC 0.--7. 1. " [0] ,Message Data Byte 0"
line.long 0xC0 "WRDS58,Write data section [58]"
hexmask.long.byte 0xC0 24.--31. 1. " MD [3] ,Message Data Byte 3"
hexmask.long.byte 0xC0 16.--23. 1. " [2] ,Message Data Byte 2"
hexmask.long.byte 0xC0 8.--15. 1. " [1] ,Message Data Byte 1"
hexmask.long.byte 0xC0 0.--7. 1. " [0] ,Message Data Byte 0"
line.long 0xC4 "WRDS59,Write data section [59]"
hexmask.long.byte 0xC4 24.--31. 1. " MD [3] ,Message Data Byte 3"
hexmask.long.byte 0xC4 16.--23. 1. " [2] ,Message Data Byte 2"
hexmask.long.byte 0xC4 8.--15. 1. " [1] ,Message Data Byte 1"
hexmask.long.byte 0xC4 0.--7. 1. " [0] ,Message Data Byte 0"
line.long 0xC8 "WRDS60,Write data section [60]"
hexmask.long.byte 0xC8 24.--31. 1. " MD [3] ,Message Data Byte 3"
hexmask.long.byte 0xC8 16.--23. 1. " [2] ,Message Data Byte 2"
hexmask.long.byte 0xC8 8.--15. 1. " [1] ,Message Data Byte 1"
hexmask.long.byte 0xC8 0.--7. 1. " [0] ,Message Data Byte 0"
line.long 0xCC "WRDS61,Write data section [61]"
hexmask.long.byte 0xCC 24.--31. 1. " MD [3] ,Message Data Byte 3"
hexmask.long.byte 0xCC 16.--23. 1. " [2] ,Message Data Byte 2"
hexmask.long.byte 0xCC 8.--15. 1. " [1] ,Message Data Byte 1"
hexmask.long.byte 0xCC 0.--7. 1. " [0] ,Message Data Byte 0"
line.long 0xD0 "WRDS62,Write data section [62]"
hexmask.long.byte 0xD0 24.--31. 1. " MD [3] ,Message Data Byte 3"
hexmask.long.byte 0xD0 16.--23. 1. " [2] ,Message Data Byte 2"
hexmask.long.byte 0xD0 8.--15. 1. " [1] ,Message Data Byte 1"
hexmask.long.byte 0xD0 0.--7. 1. " [0] ,Message Data Byte 0"
line.long 0xD4 "WRDS63,Write data section [63]"
hexmask.long.byte 0xD4 24.--31. 1. " MD [3] ,Message Data Byte 3"
hexmask.long.byte 0xD4 16.--23. 1. " [2] ,Message Data Byte 2"
hexmask.long.byte 0xD4 8.--15. 1. " [1] ,Message Data Byte 1"
hexmask.long.byte 0xD4 0.--7. 1. " [0] ,Message Data Byte 0"
line.long 0xD8 "WRDS64,Write data section [64]"
hexmask.long.byte 0xD8 24.--31. 1. " MD [3] ,Message Data Byte 3"
hexmask.long.byte 0xD8 16.--23. 1. " [2] ,Message Data Byte 2"
hexmask.long.byte 0xD8 8.--15. 1. " [1] ,Message Data Byte 1"
hexmask.long.byte 0xD8 0.--7. 1. " [0] ,Message Data Byte 0"
width 8.
group.long 0x500++0xB
line.long 0x0 "WRHS1,Write header section 1"
bitfld.long 0x00 29. " MBI ,Message Buffer Interrupt" "Enabled,Disabled"
bitfld.long 0x00 28. " TXM ,Transmission Mode" "Continuous,Single-shot"
textline " "
bitfld.long 0x00 27. " PPIT ,Payload Preamble Indicator Transmit" "Not set,Set"
bitfld.long 0x00 26. " CFG ,Message Buffer Configuration Bit" "Receive,Transmit"
textline " "
bitfld.long 0x00 25. " CHB ,Channel Filter Control B" "No effect,Channel B"
bitfld.long 0x00 24. " CHA ,Channel Filter Control A" "No effect,Channel A"
textline " "
hexmask.long.byte 0x00 16.--22. 1. " CYC ,Cycle Code"
hexmask.long.word 0x00 0.--10. 1. " FID ,Frame ID"
line.long 0x4 "WRHS2,Write header section 2"
hexmask.long.byte 0x04 16.--22. 1. " PLC ,Payload Length Configured"
hexmask.long.word 0x04 0.--10. 1. " CRC ,Header CRC"
line.long 0x8 "WRHS3,Write header section 3"
hexmask.long.word 0x08 0.--10. 1. " DP ,Data Pointer"
group.long 0x510++0x7
line.long 0x0 "IBCM,Input buffer command mask"
bitfld.long 0x00 18. " STXRS ,Transmission Request Shadow" "Reset,Set"
bitfld.long 0x00 17. " LDSS ,Load Data Section Shadow" "Not updated,Updated"
textline " "
bitfld.long 0x00 16. " LHSS ,Load Header Section Shadow" "Not updated,Updated"
bitfld.long 0x00 2. " STXRH ,Set Transmission Request Host" "Reset,Set"
textline " "
bitfld.long 0x00 1. " LDSH ,Load Data Section Host" "Not updated,Updated"
bitfld.long 0x00 0. " LHSH ,Load Header Section Host" "Not updated,Updated"
line.long 0x4 "IBCR,Input buffer command request"
bitfld.long 0x04 31. " IBSYS ,Input Buffer Busy Shadow" "Completed,In progress"
hexmask.long.byte 0x04 16.--22. 1. " IBRS ,Input Buffer Request Shadow"
textline " "
bitfld.long 0x04 15. " IBSYH ,Input Buffer Busy Host" "Not requested,Requested"
hexmask.long.byte 0x04 0.--6. 1. " IBRH ,Input Buffer Request Host"
tree.end
width 8.
tree "Output Buffer"
rgroup.long 0x600++0x23
line.long 0x0 "RDDS1,Read data section [1]"
hexmask.long.byte 0x0 24.--31. 1. " MD [3] ,Message Data Byte 3"
hexmask.long.byte 0x0 16.--23. 1. " [2] ,Message Data Byte 2"
hexmask.long.byte 0x0 8.--15. 1. " [1] ,Message Data Byte 1"
hexmask.long.byte 0x0 0.--7. 1. " [0] ,Message Data Byte 0"
line.long 0x4 "RDDS2,Read data section [2]"
hexmask.long.byte 0x4 24.--31. 1. " MD [3] ,Message Data Byte 3"
hexmask.long.byte 0x4 16.--23. 1. " [2] ,Message Data Byte 2"
hexmask.long.byte 0x4 8.--15. 1. " [1] ,Message Data Byte 1"
hexmask.long.byte 0x4 0.--7. 1. " [0] ,Message Data Byte 0"
line.long 0x8 "RDDS3,Read data section [3]"
hexmask.long.byte 0x8 24.--31. 1. " MD [3] ,Message Data Byte 3"
hexmask.long.byte 0x8 16.--23. 1. " [2] ,Message Data Byte 2"
hexmask.long.byte 0x8 8.--15. 1. " [1] ,Message Data Byte 1"
hexmask.long.byte 0x8 0.--7. 1. " [0] ,Message Data Byte 0"
line.long 0xC "RDDS4,Read data section [4]"
hexmask.long.byte 0xC 24.--31. 1. " MD [3] ,Message Data Byte 3"
hexmask.long.byte 0xC 16.--23. 1. " [2] ,Message Data Byte 2"
hexmask.long.byte 0xC 8.--15. 1. " [1] ,Message Data Byte 1"
hexmask.long.byte 0xC 0.--7. 1. " [0] ,Message Data Byte 0"
line.long 0x10 "RDDS5,Read data section [5]"
hexmask.long.byte 0x10 24.--31. 1. " MD [3] ,Message Data Byte 3"
hexmask.long.byte 0x10 16.--23. 1. " [2] ,Message Data Byte 2"
hexmask.long.byte 0x10 8.--15. 1. " [1] ,Message Data Byte 1"
hexmask.long.byte 0x10 0.--7. 1. " [0] ,Message Data Byte 0"
line.long 0x14 "RDDS6,Read data section [6]"
hexmask.long.byte 0x14 24.--31. 1. " MD [3] ,Message Data Byte 3"
hexmask.long.byte 0x14 16.--23. 1. " [2] ,Message Data Byte 2"
hexmask.long.byte 0x14 8.--15. 1. " [1] ,Message Data Byte 1"
hexmask.long.byte 0x14 0.--7. 1. " [0] ,Message Data Byte 0"
line.long 0x18 "RDDS7,Read data section [7]"
hexmask.long.byte 0x18 24.--31. 1. " MD [3] ,Message Data Byte 3"
hexmask.long.byte 0x18 16.--23. 1. " [2] ,Message Data Byte 2"
hexmask.long.byte 0x18 8.--15. 1. " [1] ,Message Data Byte 1"
hexmask.long.byte 0x18 0.--7. 1. " [0] ,Message Data Byte 0"
line.long 0x1C "RDDS8,Read data section [8]"
hexmask.long.byte 0x1C 24.--31. 1. " MD [3] ,Message Data Byte 3"
hexmask.long.byte 0x1C 16.--23. 1. " [2] ,Message Data Byte 2"
hexmask.long.byte 0x1C 8.--15. 1. " [1] ,Message Data Byte 1"
hexmask.long.byte 0x1C 0.--7. 1. " [0] ,Message Data Byte 0"
line.long 0x20 "RDDS9,Read data section [9]"
hexmask.long.byte 0x20 24.--31. 1. " MD [3] ,Message Data Byte 3"
hexmask.long.byte 0x20 16.--23. 1. " [2] ,Message Data Byte 2"
hexmask.long.byte 0x20 8.--15. 1. " [1] ,Message Data Byte 1"
hexmask.long.byte 0x20 0.--7. 1. " [0] ,Message Data Byte 0"
rgroup.long 0x624++0xDB
line.long 0x0 "RDDS10,Read data section [10]"
hexmask.long.byte 0x0 24.--31. 1. " MD [3] ,Message Data Byte 3"
hexmask.long.byte 0x0 16.--23. 1. " [2] ,Message Data Byte 2"
hexmask.long.byte 0x0 8.--15. 1. " [1] ,Message Data Byte 1"
hexmask.long.byte 0x0 0.--7. 1. " [0] ,Message Data Byte 0"
line.long 0x4 "RDDS11,Read data section [11]"
hexmask.long.byte 0x4 24.--31. 1. " MD [3] ,Message Data Byte 3"
hexmask.long.byte 0x4 16.--23. 1. " [2] ,Message Data Byte 2"
hexmask.long.byte 0x4 8.--15. 1. " [1] ,Message Data Byte 1"
hexmask.long.byte 0x4 0.--7. 1. " [0] ,Message Data Byte 0"
line.long 0x8 "RDDS12,Read data section [12]"
hexmask.long.byte 0x8 24.--31. 1. " MD [3] ,Message Data Byte 3"
hexmask.long.byte 0x8 16.--23. 1. " [2] ,Message Data Byte 2"
hexmask.long.byte 0x8 8.--15. 1. " [1] ,Message Data Byte 1"
hexmask.long.byte 0x8 0.--7. 1. " [0] ,Message Data Byte 0"
line.long 0xC "RDDS13,Read data section [13]"
hexmask.long.byte 0xC 24.--31. 1. " MD [3] ,Message Data Byte 3"
hexmask.long.byte 0xC 16.--23. 1. " [2] ,Message Data Byte 2"
hexmask.long.byte 0xC 8.--15. 1. " [1] ,Message Data Byte 1"
hexmask.long.byte 0xC 0.--7. 1. " [0] ,Message Data Byte 0"
line.long 0x10 "RDDS14,Read data section [14]"
hexmask.long.byte 0x10 24.--31. 1. " MD [3] ,Message Data Byte 3"
hexmask.long.byte 0x10 16.--23. 1. " [2] ,Message Data Byte 2"
hexmask.long.byte 0x10 8.--15. 1. " [1] ,Message Data Byte 1"
hexmask.long.byte 0x10 0.--7. 1. " [0] ,Message Data Byte 0"
line.long 0x14 "RDDS15,Read data section [15]"
hexmask.long.byte 0x14 24.--31. 1. " MD [3] ,Message Data Byte 3"
hexmask.long.byte 0x14 16.--23. 1. " [2] ,Message Data Byte 2"
hexmask.long.byte 0x14 8.--15. 1. " [1] ,Message Data Byte 1"
hexmask.long.byte 0x14 0.--7. 1. " [0] ,Message Data Byte 0"
line.long 0x18 "RDDS16,Read data section [16]"
hexmask.long.byte 0x18 24.--31. 1. " MD [3] ,Message Data Byte 3"
hexmask.long.byte 0x18 16.--23. 1. " [2] ,Message Data Byte 2"
hexmask.long.byte 0x18 8.--15. 1. " [1] ,Message Data Byte 1"
hexmask.long.byte 0x18 0.--7. 1. " [0] ,Message Data Byte 0"
line.long 0x1C "RDDS17,Read data section [17]"
hexmask.long.byte 0x1C 24.--31. 1. " MD [3] ,Message Data Byte 3"
hexmask.long.byte 0x1C 16.--23. 1. " [2] ,Message Data Byte 2"
hexmask.long.byte 0x1C 8.--15. 1. " [1] ,Message Data Byte 1"
hexmask.long.byte 0x1C 0.--7. 1. " [0] ,Message Data Byte 0"
line.long 0x20 "RDDS18,Read data section [18]"
hexmask.long.byte 0x20 24.--31. 1. " MD [3] ,Message Data Byte 3"
hexmask.long.byte 0x20 16.--23. 1. " [2] ,Message Data Byte 2"
hexmask.long.byte 0x20 8.--15. 1. " [1] ,Message Data Byte 1"
hexmask.long.byte 0x20 0.--7. 1. " [0] ,Message Data Byte 0"
line.long 0x24 "RDDS19,Read data section [19]"
hexmask.long.byte 0x24 24.--31. 1. " MD [3] ,Message Data Byte 3"
hexmask.long.byte 0x24 16.--23. 1. " [2] ,Message Data Byte 2"
hexmask.long.byte 0x24 8.--15. 1. " [1] ,Message Data Byte 1"
hexmask.long.byte 0x24 0.--7. 1. " [0] ,Message Data Byte 0"
line.long 0x28 "RDDS20,Read data section [20]"
hexmask.long.byte 0x28 24.--31. 1. " MD [3] ,Message Data Byte 3"
hexmask.long.byte 0x28 16.--23. 1. " [2] ,Message Data Byte 2"
hexmask.long.byte 0x28 8.--15. 1. " [1] ,Message Data Byte 1"
hexmask.long.byte 0x28 0.--7. 1. " [0] ,Message Data Byte 0"
line.long 0x2C "RDDS21,Read data section [21]"
hexmask.long.byte 0x2C 24.--31. 1. " MD [3] ,Message Data Byte 3"
hexmask.long.byte 0x2C 16.--23. 1. " [2] ,Message Data Byte 2"
hexmask.long.byte 0x2C 8.--15. 1. " [1] ,Message Data Byte 1"
hexmask.long.byte 0x2C 0.--7. 1. " [0] ,Message Data Byte 0"
line.long 0x30 "RDDS22,Read data section [22]"
hexmask.long.byte 0x30 24.--31. 1. " MD [3] ,Message Data Byte 3"
hexmask.long.byte 0x30 16.--23. 1. " [2] ,Message Data Byte 2"
hexmask.long.byte 0x30 8.--15. 1. " [1] ,Message Data Byte 1"
hexmask.long.byte 0x30 0.--7. 1. " [0] ,Message Data Byte 0"
line.long 0x34 "RDDS23,Read data section [23]"
hexmask.long.byte 0x34 24.--31. 1. " MD [3] ,Message Data Byte 3"
hexmask.long.byte 0x34 16.--23. 1. " [2] ,Message Data Byte 2"
hexmask.long.byte 0x34 8.--15. 1. " [1] ,Message Data Byte 1"
hexmask.long.byte 0x34 0.--7. 1. " [0] ,Message Data Byte 0"
line.long 0x38 "RDDS24,Read data section [24]"
hexmask.long.byte 0x38 24.--31. 1. " MD [3] ,Message Data Byte 3"
hexmask.long.byte 0x38 16.--23. 1. " [2] ,Message Data Byte 2"
hexmask.long.byte 0x38 8.--15. 1. " [1] ,Message Data Byte 1"
hexmask.long.byte 0x38 0.--7. 1. " [0] ,Message Data Byte 0"
line.long 0x3C "RDDS25,Read data section [25]"
hexmask.long.byte 0x3C 24.--31. 1. " MD [3] ,Message Data Byte 3"
hexmask.long.byte 0x3C 16.--23. 1. " [2] ,Message Data Byte 2"
hexmask.long.byte 0x3C 8.--15. 1. " [1] ,Message Data Byte 1"
hexmask.long.byte 0x3C 0.--7. 1. " [0] ,Message Data Byte 0"
line.long 0x40 "RDDS26,Read data section [26]"
hexmask.long.byte 0x40 24.--31. 1. " MD [3] ,Message Data Byte 3"
hexmask.long.byte 0x40 16.--23. 1. " [2] ,Message Data Byte 2"
hexmask.long.byte 0x40 8.--15. 1. " [1] ,Message Data Byte 1"
hexmask.long.byte 0x40 0.--7. 1. " [0] ,Message Data Byte 0"
line.long 0x44 "RDDS27,Read data section [27]"
hexmask.long.byte 0x44 24.--31. 1. " MD [3] ,Message Data Byte 3"
hexmask.long.byte 0x44 16.--23. 1. " [2] ,Message Data Byte 2"
hexmask.long.byte 0x44 8.--15. 1. " [1] ,Message Data Byte 1"
hexmask.long.byte 0x44 0.--7. 1. " [0] ,Message Data Byte 0"
line.long 0x48 "RDDS28,Read data section [28]"
hexmask.long.byte 0x48 24.--31. 1. " MD [3] ,Message Data Byte 3"
hexmask.long.byte 0x48 16.--23. 1. " [2] ,Message Data Byte 2"
hexmask.long.byte 0x48 8.--15. 1. " [1] ,Message Data Byte 1"
hexmask.long.byte 0x48 0.--7. 1. " [0] ,Message Data Byte 0"
line.long 0x4C "RDDS29,Read data section [29]"
hexmask.long.byte 0x4C 24.--31. 1. " MD [3] ,Message Data Byte 3"
hexmask.long.byte 0x4C 16.--23. 1. " [2] ,Message Data Byte 2"
hexmask.long.byte 0x4C 8.--15. 1. " [1] ,Message Data Byte 1"
hexmask.long.byte 0x4C 0.--7. 1. " [0] ,Message Data Byte 0"
line.long 0x50 "RDDS30,Read data section [30]"
hexmask.long.byte 0x50 24.--31. 1. " MD [3] ,Message Data Byte 3"
hexmask.long.byte 0x50 16.--23. 1. " [2] ,Message Data Byte 2"
hexmask.long.byte 0x50 8.--15. 1. " [1] ,Message Data Byte 1"
hexmask.long.byte 0x50 0.--7. 1. " [0] ,Message Data Byte 0"
line.long 0x54 "RDDS31,Read data section [31]"
hexmask.long.byte 0x54 24.--31. 1. " MD [3] ,Message Data Byte 3"
hexmask.long.byte 0x54 16.--23. 1. " [2] ,Message Data Byte 2"
hexmask.long.byte 0x54 8.--15. 1. " [1] ,Message Data Byte 1"
hexmask.long.byte 0x54 0.--7. 1. " [0] ,Message Data Byte 0"
line.long 0x58 "RDDS32,Read data section [32]"
hexmask.long.byte 0x58 24.--31. 1. " MD [3] ,Message Data Byte 3"
hexmask.long.byte 0x58 16.--23. 1. " [2] ,Message Data Byte 2"
hexmask.long.byte 0x58 8.--15. 1. " [1] ,Message Data Byte 1"
hexmask.long.byte 0x58 0.--7. 1. " [0] ,Message Data Byte 0"
line.long 0x5C "RDDS33,Read data section [33]"
hexmask.long.byte 0x5C 24.--31. 1. " MD [3] ,Message Data Byte 3"
hexmask.long.byte 0x5C 16.--23. 1. " [2] ,Message Data Byte 2"
hexmask.long.byte 0x5C 8.--15. 1. " [1] ,Message Data Byte 1"
hexmask.long.byte 0x5C 0.--7. 1. " [0] ,Message Data Byte 0"
line.long 0x60 "RDDS34,Read data section [34]"
hexmask.long.byte 0x60 24.--31. 1. " MD [3] ,Message Data Byte 3"
hexmask.long.byte 0x60 16.--23. 1. " [2] ,Message Data Byte 2"
hexmask.long.byte 0x60 8.--15. 1. " [1] ,Message Data Byte 1"
hexmask.long.byte 0x60 0.--7. 1. " [0] ,Message Data Byte 0"
line.long 0x64 "RDDS35,Read data section [35]"
hexmask.long.byte 0x64 24.--31. 1. " MD [3] ,Message Data Byte 3"
hexmask.long.byte 0x64 16.--23. 1. " [2] ,Message Data Byte 2"
hexmask.long.byte 0x64 8.--15. 1. " [1] ,Message Data Byte 1"
hexmask.long.byte 0x64 0.--7. 1. " [0] ,Message Data Byte 0"
line.long 0x68 "RDDS36,Read data section [36]"
hexmask.long.byte 0x68 24.--31. 1. " MD [3] ,Message Data Byte 3"
hexmask.long.byte 0x68 16.--23. 1. " [2] ,Message Data Byte 2"
hexmask.long.byte 0x68 8.--15. 1. " [1] ,Message Data Byte 1"
hexmask.long.byte 0x68 0.--7. 1. " [0] ,Message Data Byte 0"
line.long 0x6C "RDDS37,Read data section [37]"
hexmask.long.byte 0x6C 24.--31. 1. " MD [3] ,Message Data Byte 3"
hexmask.long.byte 0x6C 16.--23. 1. " [2] ,Message Data Byte 2"
hexmask.long.byte 0x6C 8.--15. 1. " [1] ,Message Data Byte 1"
hexmask.long.byte 0x6C 0.--7. 1. " [0] ,Message Data Byte 0"
line.long 0x70 "RDDS38,Read data section [38]"
hexmask.long.byte 0x70 24.--31. 1. " MD [3] ,Message Data Byte 3"
hexmask.long.byte 0x70 16.--23. 1. " [2] ,Message Data Byte 2"
hexmask.long.byte 0x70 8.--15. 1. " [1] ,Message Data Byte 1"
hexmask.long.byte 0x70 0.--7. 1. " [0] ,Message Data Byte 0"
line.long 0x74 "RDDS39,Read data section [39]"
hexmask.long.byte 0x74 24.--31. 1. " MD [3] ,Message Data Byte 3"
hexmask.long.byte 0x74 16.--23. 1. " [2] ,Message Data Byte 2"
hexmask.long.byte 0x74 8.--15. 1. " [1] ,Message Data Byte 1"
hexmask.long.byte 0x74 0.--7. 1. " [0] ,Message Data Byte 0"
line.long 0x78 "RDDS40,Read data section [40]"
hexmask.long.byte 0x78 24.--31. 1. " MD [3] ,Message Data Byte 3"
hexmask.long.byte 0x78 16.--23. 1. " [2] ,Message Data Byte 2"
hexmask.long.byte 0x78 8.--15. 1. " [1] ,Message Data Byte 1"
hexmask.long.byte 0x78 0.--7. 1. " [0] ,Message Data Byte 0"
line.long 0x7C "RDDS41,Read data section [41]"
hexmask.long.byte 0x7C 24.--31. 1. " MD [3] ,Message Data Byte 3"
hexmask.long.byte 0x7C 16.--23. 1. " [2] ,Message Data Byte 2"
hexmask.long.byte 0x7C 8.--15. 1. " [1] ,Message Data Byte 1"
hexmask.long.byte 0x7C 0.--7. 1. " [0] ,Message Data Byte 0"
line.long 0x80 "RDDS42,Read data section [42]"
hexmask.long.byte 0x80 24.--31. 1. " MD [3] ,Message Data Byte 3"
hexmask.long.byte 0x80 16.--23. 1. " [2] ,Message Data Byte 2"
hexmask.long.byte 0x80 8.--15. 1. " [1] ,Message Data Byte 1"
hexmask.long.byte 0x80 0.--7. 1. " [0] ,Message Data Byte 0"
line.long 0x84 "RDDS43,Read data section [43]"
hexmask.long.byte 0x84 24.--31. 1. " MD [3] ,Message Data Byte 3"
hexmask.long.byte 0x84 16.--23. 1. " [2] ,Message Data Byte 2"
hexmask.long.byte 0x84 8.--15. 1. " [1] ,Message Data Byte 1"
hexmask.long.byte 0x84 0.--7. 1. " [0] ,Message Data Byte 0"
line.long 0x88 "RDDS44,Read data section [44]"
hexmask.long.byte 0x88 24.--31. 1. " MD [3] ,Message Data Byte 3"
hexmask.long.byte 0x88 16.--23. 1. " [2] ,Message Data Byte 2"
hexmask.long.byte 0x88 8.--15. 1. " [1] ,Message Data Byte 1"
hexmask.long.byte 0x88 0.--7. 1. " [0] ,Message Data Byte 0"
line.long 0x8C "RDDS45,Read data section [45]"
hexmask.long.byte 0x8C 24.--31. 1. " MD [3] ,Message Data Byte 3"
hexmask.long.byte 0x8C 16.--23. 1. " [2] ,Message Data Byte 2"
hexmask.long.byte 0x8C 8.--15. 1. " [1] ,Message Data Byte 1"
hexmask.long.byte 0x8C 0.--7. 1. " [0] ,Message Data Byte 0"
line.long 0x90 "RDDS46,Read data section [46]"
hexmask.long.byte 0x90 24.--31. 1. " MD [3] ,Message Data Byte 3"
hexmask.long.byte 0x90 16.--23. 1. " [2] ,Message Data Byte 2"
hexmask.long.byte 0x90 8.--15. 1. " [1] ,Message Data Byte 1"
hexmask.long.byte 0x90 0.--7. 1. " [0] ,Message Data Byte 0"
line.long 0x94 "RDDS47,Read data section [47]"
hexmask.long.byte 0x94 24.--31. 1. " MD [3] ,Message Data Byte 3"
hexmask.long.byte 0x94 16.--23. 1. " [2] ,Message Data Byte 2"
hexmask.long.byte 0x94 8.--15. 1. " [1] ,Message Data Byte 1"
hexmask.long.byte 0x94 0.--7. 1. " [0] ,Message Data Byte 0"
line.long 0x98 "RDDS48,Read data section [48]"
hexmask.long.byte 0x98 24.--31. 1. " MD [3] ,Message Data Byte 3"
hexmask.long.byte 0x98 16.--23. 1. " [2] ,Message Data Byte 2"
hexmask.long.byte 0x98 8.--15. 1. " [1] ,Message Data Byte 1"
hexmask.long.byte 0x98 0.--7. 1. " [0] ,Message Data Byte 0"
line.long 0x9C "RDDS49,Read data section [49]"
hexmask.long.byte 0x9C 24.--31. 1. " MD [3] ,Message Data Byte 3"
hexmask.long.byte 0x9C 16.--23. 1. " [2] ,Message Data Byte 2"
hexmask.long.byte 0x9C 8.--15. 1. " [1] ,Message Data Byte 1"
hexmask.long.byte 0x9C 0.--7. 1. " [0] ,Message Data Byte 0"
line.long 0xA0 "RDDS50,Read data section [50]"
hexmask.long.byte 0xA0 24.--31. 1. " MD [3] ,Message Data Byte 3"
hexmask.long.byte 0xA0 16.--23. 1. " [2] ,Message Data Byte 2"
hexmask.long.byte 0xA0 8.--15. 1. " [1] ,Message Data Byte 1"
hexmask.long.byte 0xA0 0.--7. 1. " [0] ,Message Data Byte 0"
line.long 0xA4 "RDDS51,Read data section [51]"
hexmask.long.byte 0xA4 24.--31. 1. " MD [3] ,Message Data Byte 3"
hexmask.long.byte 0xA4 16.--23. 1. " [2] ,Message Data Byte 2"
hexmask.long.byte 0xA4 8.--15. 1. " [1] ,Message Data Byte 1"
hexmask.long.byte 0xA4 0.--7. 1. " [0] ,Message Data Byte 0"
line.long 0xA8 "RDDS52,Read data section [52]"
hexmask.long.byte 0xA8 24.--31. 1. " MD [3] ,Message Data Byte 3"
hexmask.long.byte 0xA8 16.--23. 1. " [2] ,Message Data Byte 2"
hexmask.long.byte 0xA8 8.--15. 1. " [1] ,Message Data Byte 1"
hexmask.long.byte 0xA8 0.--7. 1. " [0] ,Message Data Byte 0"
line.long 0xAC "RDDS53,Read data section [53]"
hexmask.long.byte 0xAC 24.--31. 1. " MD [3] ,Message Data Byte 3"
hexmask.long.byte 0xAC 16.--23. 1. " [2] ,Message Data Byte 2"
hexmask.long.byte 0xAC 8.--15. 1. " [1] ,Message Data Byte 1"
hexmask.long.byte 0xAC 0.--7. 1. " [0] ,Message Data Byte 0"
line.long 0xB0 "RDDS54,Read data section [54]"
hexmask.long.byte 0xB0 24.--31. 1. " MD [3] ,Message Data Byte 3"
hexmask.long.byte 0xB0 16.--23. 1. " [2] ,Message Data Byte 2"
hexmask.long.byte 0xB0 8.--15. 1. " [1] ,Message Data Byte 1"
hexmask.long.byte 0xB0 0.--7. 1. " [0] ,Message Data Byte 0"
line.long 0xB4 "RDDS55,Read data section [55]"
hexmask.long.byte 0xB4 24.--31. 1. " MD [3] ,Message Data Byte 3"
hexmask.long.byte 0xB4 16.--23. 1. " [2] ,Message Data Byte 2"
hexmask.long.byte 0xB4 8.--15. 1. " [1] ,Message Data Byte 1"
hexmask.long.byte 0xB4 0.--7. 1. " [0] ,Message Data Byte 0"
line.long 0xB8 "RDDS56,Read data section [56]"
hexmask.long.byte 0xB8 24.--31. 1. " MD [3] ,Message Data Byte 3"
hexmask.long.byte 0xB8 16.--23. 1. " [2] ,Message Data Byte 2"
hexmask.long.byte 0xB8 8.--15. 1. " [1] ,Message Data Byte 1"
hexmask.long.byte 0xB8 0.--7. 1. " [0] ,Message Data Byte 0"
line.long 0xBC "RDDS57,Read data section [57]"
hexmask.long.byte 0xBC 24.--31. 1. " MD [3] ,Message Data Byte 3"
hexmask.long.byte 0xBC 16.--23. 1. " [2] ,Message Data Byte 2"
hexmask.long.byte 0xBC 8.--15. 1. " [1] ,Message Data Byte 1"
hexmask.long.byte 0xBC 0.--7. 1. " [0] ,Message Data Byte 0"
line.long 0xC0 "RDDS58,Read data section [58]"
hexmask.long.byte 0xC0 24.--31. 1. " MD [3] ,Message Data Byte 3"
hexmask.long.byte 0xC0 16.--23. 1. " [2] ,Message Data Byte 2"
hexmask.long.byte 0xC0 8.--15. 1. " [1] ,Message Data Byte 1"
hexmask.long.byte 0xC0 0.--7. 1. " [0] ,Message Data Byte 0"
line.long 0xC4 "RDDS59,Read data section [59]"
hexmask.long.byte 0xC4 24.--31. 1. " MD [3] ,Message Data Byte 3"
hexmask.long.byte 0xC4 16.--23. 1. " [2] ,Message Data Byte 2"
hexmask.long.byte 0xC4 8.--15. 1. " [1] ,Message Data Byte 1"
hexmask.long.byte 0xC4 0.--7. 1. " [0] ,Message Data Byte 0"
line.long 0xC8 "RDDS60,Read data section [60]"
hexmask.long.byte 0xC8 24.--31. 1. " MD [3] ,Message Data Byte 3"
hexmask.long.byte 0xC8 16.--23. 1. " [2] ,Message Data Byte 2"
hexmask.long.byte 0xC8 8.--15. 1. " [1] ,Message Data Byte 1"
hexmask.long.byte 0xC8 0.--7. 1. " [0] ,Message Data Byte 0"
line.long 0xCC "RDDS61,Read data section [61]"
hexmask.long.byte 0xCC 24.--31. 1. " MD [3] ,Message Data Byte 3"
hexmask.long.byte 0xCC 16.--23. 1. " [2] ,Message Data Byte 2"
hexmask.long.byte 0xCC 8.--15. 1. " [1] ,Message Data Byte 1"
hexmask.long.byte 0xCC 0.--7. 1. " [0] ,Message Data Byte 0"
line.long 0xD0 "RDDS62,Read data section [62]"
hexmask.long.byte 0xD0 24.--31. 1. " MD [3] ,Message Data Byte 3"
hexmask.long.byte 0xD0 16.--23. 1. " [2] ,Message Data Byte 2"
hexmask.long.byte 0xD0 8.--15. 1. " [1] ,Message Data Byte 1"
hexmask.long.byte 0xD0 0.--7. 1. " [0] ,Message Data Byte 0"
line.long 0xD4 "RDDS63,Read data section [63]"
hexmask.long.byte 0xD4 24.--31. 1. " MD [3] ,Message Data Byte 3"
hexmask.long.byte 0xD4 16.--23. 1. " [2] ,Message Data Byte 2"
hexmask.long.byte 0xD4 8.--15. 1. " [1] ,Message Data Byte 1"
hexmask.long.byte 0xD4 0.--7. 1. " [0] ,Message Data Byte 0"
line.long 0xD8 "RDDS64,Read data section [64]"
hexmask.long.byte 0xD8 24.--31. 1. " MD [3] ,Message Data Byte 3"
hexmask.long.byte 0xD8 16.--23. 1. " [2] ,Message Data Byte 2"
hexmask.long.byte 0xD8 8.--15. 1. " [1] ,Message Data Byte 1"
hexmask.long.byte 0xD8 0.--7. 1. " [0] ,Message Data Byte 0"
width 8.
rgroup.long 0x700++0xF
line.long 0x0 "RDHS1,Read header section 1"
bitfld.long 0x00 29. " MBI ,Message Buffer Interrupt" "Enabled,Disabled"
bitfld.long 0x00 28. " TXM ,Transmission Mode" "Continuous,Single-shot"
textline " "
bitfld.long 0x00 27. " PPIT ,Payload Preamble Indicator Transmit" "Not set,Set"
bitfld.long 0x00 26. " CFG ,Message Buffer Configuration Bit" "Receive,Transmit"
textline " "
bitfld.long 0x00 25. " CHB ,Channel Filter Control B" "No effect,Channel B"
bitfld.long 0x00 24. " CHA ,Channel Filter Control A" "No effect,Channel A"
textline " "
hexmask.long.byte 0x00 16.--22. 1. " CYC ,Cycle Code"
hexmask.long.word 0x00 0.--10. 1. " FID ,Frame ID"
line.long 0x4 "RDHS2,Read header section 2"
hexmask.long.byte 0x04 24.--30. 1. " PLR ,Payload Length Received"
hexmask.long.byte 0x04 16.--22. 1. " PLC ,Payload Length Configured"
textline " "
hexmask.long.word 0x04 0.--10. 1. " CRC ,Header CRC"
line.long 0x8 "RDHS3,Read header section 3"
bitfld.long 0x08 28. " PPI ,Payload Preamble Indicator" "Not contained,Contained"
bitfld.long 0x08 27. " NFI ,NULL Frame Indicator" "No frame,Frame"
textline " "
bitfld.long 0x08 26. " SYN ,SYNC Frame Indicator" "Not received,Received"
bitfld.long 0x08 25. " SFI ,Startup Frame Indicator" "Not received,Received"
textline " "
bitfld.long 0x08 24. " RCI ,Received on Channel Indicator" "Channel B,Channel A"
hexmask.long.byte 0x08 16.--21. 1. " RCC ,Receive Cycle Count"
textline " "
hexmask.long.word 0x08 0.--10. 1. " DP ,Data Pointer"
line.long 0xC "MBS,Message buffer status"
bitfld.long 0x0C 28. " PPIS ,Payload Preamble Indictor Status" "Not contained,Contained"
bitfld.long 0x0C 27. " NFIS ,NULL Frame Indicator Status" "Received,Not received"
textline " "
bitfld.long 0x0C 26. " SYNS ,SYNC Frame Indicator Status" "Not received,Received"
bitfld.long 0x0C 25. " SFIS ,Startup Frame Indicator Status" "Not received,Received"
textline " "
bitfld.long 0x0C 24. " RCIS ,Received on Channel Indicator Status" "B,A"
hexmask.long.byte 0x0c 16.--21. 1. " CCS ,Cycle Count Status"
textline " "
bitfld.long 0x0C 15. " MTB ,Frame Transmitted on Channel B" "Not transmitted,Transmitted"
bitfld.long 0x0C 14. " MTA ,Frame Transmitted on Channel A" "Not transmitted,Transmitted"
textline " "
bitfld.long 0x0C 12. " MLST ,Message Lost" "Not lost,Overwritten"
bitfld.long 0x0C 11. " ESB ,Empty Slot Channel B" "Not empty,Empty"
textline " "
bitfld.long 0x0C 10. " ESA ,Empty Slot Channel A" "Not empty,Empty"
bitfld.long 0x0C 9. " TCIB ,Transmission Conflict Indication Channel B" "No conflict,Conflict"
textline " "
bitfld.long 0x0C 8. " TCIA ,Transmission Conflict Indication Channel A" "No conflict,Conflict"
bitfld.long 0x0C 7. " SVOB ,Slot Boundary Violation Observed on Channel B" "No violation,Violation"
textline " "
bitfld.long 0x0C 6. " SVOA ,Slot Boundary Violation Observed on Channel A" "No violation,Violation"
bitfld.long 0x0C 5. " CEOB ,Content Error Observed on Channel B" "No error,Error"
textline " "
bitfld.long 0x0C 4. " CEOA ,Content Error Observed on Channel A" "No error,Error"
bitfld.long 0x0C 3. " SEOB ,Syntax Error Observed on Channel B" "No error,Error"
textline " "
bitfld.long 0x0C 2. " SEOA ,Syntax Error Observed on Channel A" "No error,Error"
bitfld.long 0x0C 1. " VFRB ,Valid Frame Received on Channel B" "Not received,Received"
textline " "
bitfld.long 0x0C 0. " VFRA ,Valid Frame Received on Channel A" "Not received,Received"
group.long 0x710++0x7
line.long 0x0 "OBCM,Output buffer command mask"
sif (cpuis("TMS570LS1115*")||cpuis("TMS570LS1225*")||cpuis("TMS570LS1227*"))
rbitfld.long 0x00 17. " RDSH ,Read Data Section Host" "Not read,Selected"
rbitfld.long 0x00 16. " RHSH ,Read Header Section Host" "Not read,Selected"
textline " "
else
bitfld.long 0x00 17. " RDSH ,Read Data Section Host" "Not read,Selected"
bitfld.long 0x00 16. " RHSH ,Read Header Section Host" "Not read,Selected"
textline " "
endif
bitfld.long 0x00 1. " RDSS ,Read Data Section Shadow" "Not read,Selected"
bitfld.long 0x00 0. " RHSS ,Read Header Section Shadow" "Not read,Selected"
line.long 0x4 "OBCR,Output buffer command request"
hexmask.long.byte 0x04 16.--22. 1. " OBRH ,Output Buffer Request Host"
bitfld.long 0x04 15. " OBSYS ,Output Buffer Busy Shadow" "Not requested,Requested"
textline " "
bitfld.long 0x04 9. " REQ ,Request Message RAM Transfer" "Not requested,Requested"
bitfld.long 0x04 8. " VIEW ,View Shadow Buffer" "No action,Swapped"
textline " "
hexmask.long.byte 0x04 0.--6. 1. " OBRS ,Output Buffer Request Shadow"
tree.end
width 0x0B
tree.end
tree.end
tree.open "DCAN (Controller Area Network Module)"
tree "DCAN1"
base ad:0xFFF7DC00
width 12.
group.long 0x00++0x3
line.long 0x0 "CTRL,Config Register"
bitfld.long 0x00 25. " WUBA ,Automatic Wake Up on Bus Activity When in Local Power Down Mode" "Not detected,Detected"
bitfld.long 0x00 24. " PDR ,Request for Local Low Power Down Mode" "Not requested,Power down"
bitfld.long 0x00 20. " DE3 ,DMA Enable for IF3" "Disabled,Enabled"
textline " "
bitfld.long 0x00 19. " DE2 ,DMA Enable for IF2" "Disabled,Enabled"
bitfld.long 0x00 18. " DE1 ,DMA Enable for IF1" "Disabled,Enabled"
bitfld.long 0x00 17. " IE1 ,DCAN1INT Interrupt Enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 16. " INITDBG ,Internal Init State While Debug Access Mode" "No debug,Debug"
bitfld.long 0x00 15. " SWR ,SW Reset Enable" "No reset,Reset"
bitfld.long 0x00 10.--13. " PMD ,Parity on/off" "Enabled,Enabled,Enabled,Enabled,Enabled,Disabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled"
textline " "
bitfld.long 0x00 9. " ABO ,Auto Bus On Enable" "Disabled,Enabled"
bitfld.long 0x00 8. " IDS ,Interruption Debug Support Enable" "Disabled,Enabled"
bitfld.long 0x00 7. " TEST ,Test Mode Enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 6. " CCE ,Configuration Change Enable" "No write,Write"
bitfld.long 0x00 5. " DAR ,Disable Automatic Retransmission" "No,Yes"
bitfld.long 0x00 3. " EIE ,Error Interrupt Enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 2. " SIE ,Status Interrupt Enable" "Disabled,Enabled"
bitfld.long 0x00 1. " IE ,DCAN0INT Interrupt Enable" "Disabled,Enabled"
bitfld.long 0x00 0. " INIT ,Initialization" "Disabled,Enabled"
hgroup.long 0x04++0x3
hide.long 0x0 "ES,Error and Status Register"
in
width 12.
rgroup.long 0x08++0x3
line.long 0x0 "ERRC,Error Counter Register"
bitfld.long 0x00 15. " RP ,Receive Error Passive" "Below,Reached"
hexmask.long.byte 0x00 8.--14. 1. " REC[6-0] ,Receive Error Counter"
hexmask.long.byte 0x00 0.--7. 1. " TEC[7-0] ,Transmit Error Counter"
group.long 0x0C++0x3
line.long 0x0 "BTBRP,Bit Timing_BRP Extension Register"
bitfld.long 0x00 16.--19. " BRPE ,Baud Rate Prescaler Extension" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 12.--14. " TSEG2 ,The Time Segment After the Sample Point" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 8.--11. " TSEG1 ,The Time Segment Before the Sample Point" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x00 6.--7. " SJW ,Synchronization Jump Width" "0,1,2,3"
bitfld.long 0x00 0.--5. " BRP ,Baud Rate Prescaler" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
rgroup.long 0x10++0x3
line.long 0x0 "INTR,Interrupt Register"
hexmask.long.byte 0x00 16.--23. 1. " INT1ID[7-0] ,Interrupt 1 Identifier"
hexmask.long.word 0x00 0.--15. 1. " INTID[15-0] ,Interrupt Identifier"
width 12.
group.long 0x14++0x3
line.long 0x0 "TEST,Test Register"
bitfld.long 0x00 9. " RDA ,RAM Direct Access Enable" "Disabled,Enabled"
bitfld.long 0x00 8. " EXL ,External Loop Back Mode" "Disabled,Enabled"
bitfld.long 0x00 7. " RX ,Receive Pin" "Dominant,Recessive"
textline " "
bitfld.long 0x00 5.--6. " TX1-0 ,Control of CAN_TX pin" "Normal,Sample point,Dominant,Recessive"
bitfld.long 0x00 4. " LBACK ,Loop Back Mode" "Disabled,Enabled"
bitfld.long 0x00 3. " SILENT ,Silent Mode" "Disabled,Enabled"
rgroup.long 0x1C++0x3
line.long 0x0 "PERR,Parity Error Code Register"
bitfld.long 0x00 8.--10. " WORD_NUMBER ,Word Number" ",1,2,3,4,5,?..."
hexmask.long.byte 0x00 0.--7. 1. " MESSAGE_NUMBER ,Message Number"
width 19.
group.long 0x24++0x03
line.long 0x00 "DCAN_ECCDIAG, ECC Diagnostic Register"
bitfld.long 0x00 0.--3. " ECCDIAG , SECDED diagnostic mode enable/disable" ",,,,,Enabled,,,,,Disabled,?..."
group.long 0x28++0x03
line.long 0x00 "DCAN_ECCDIAG_STAT, ECC Diagnostic Status Register"
eventfld.long 0x00 8. " DEFLG_DIAG , Double bit error diagnostic" "No error,Error"
eventfld.long 0x00 0. " SEFLG_DIAG , Single bit error diagnostic" "No error,Error"
group.long 0x2C++0x03
line.long 0x00 "DCAN_ECC_CS, ECC Control and Status Register"
bitfld.long 0x00 24.--27. " SBE_EVT_EN , Single bit error event" "Enabled,Enabled,Enabled,Enabled,Enabled,Disabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled"
bitfld.long 0x00 16.--19. " ECCMODE , Single bit error correction" "Enabled,Enabled,Enabled,Enabled,Enabled,Disabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled"
eventfld.long 0x00 8. " DEFLG , Double bit error flag" "No error,Error"
eventfld.long 0x00 0. " SEFLG , Single bit error flag" "No error,Error"
rgroup.long 0x30++0x03
line.long 0x00 "DCAN_ECC_SERR, ECC Single Bit Error Code Register"
hexmask.long.byte 0x00 0.--7. 1. " Message_Number , Message object number where ECC single bit error has been detected"
group.long 0x80++0x3
line.long 0x0 "ABOT,Auto Bus On Time"
width 12.
rgroup.long 0x84++0x3
line.long 0x0 "TRREQ,Transmission Request X"
bitfld.long 0x00 14.--15. " TXRQSTREG [8] ,Transmission Request 8" "0,1,2,3"
bitfld.long 0x00 12.--13. " [7] ,Transmission Request 7" "0,1,2,3"
bitfld.long 0x00 10.--11. " [6] ,Transmission Request 6" "0,1,2,3"
bitfld.long 0x00 8.--9. " [5] ,Transmission Request 5" "0,1,2,3"
textline " "
bitfld.long 0x00 6.--7. " [4] ,Transmission Request 4" "0,1,2,3"
bitfld.long 0x00 4.--5. " [3] ,Transmission Request 3" "0,1,2,3"
bitfld.long 0x00 2.--3. " [2] ,Transmission Request 2" "0,1,2,3"
bitfld.long 0x00 0.--1. " [1] ,Transmission Request 1" "0,1,2,3"
width 12.
rgroup.long 0x88++0x3
line.long 0x0 "TRREQ21,Transmission Request 2_1"
bitfld.long 0x00 31. " TXRQST [32] ,Transmission Request Bits[32]" "Not requested,Requested"
bitfld.long 0x00 30. " [31] ,Transmission Request Bits[31]" "Not requested,Requested"
bitfld.long 0x00 29. " [30] ,Transmission Request Bits[30]" "Not requested,Requested"
bitfld.long 0x00 28. " [29] ,Transmission Request Bits[29]" "Not requested,Requested"
textline " "
bitfld.long 0x00 27. " [28] ,Transmission Request Bits[28]" "Not requested,Requested"
bitfld.long 0x00 26. " [27] ,Transmission Request Bits[27]" "Not requested,Requested"
bitfld.long 0x00 25. " [26] ,Transmission Request Bits[26]" "Not requested,Requested"
bitfld.long 0x00 24. " [25] ,Transmission Request Bits[25]" "Not requested,Requested"
textline " "
bitfld.long 0x00 23. " [24] ,Transmission Request Bits[24]" "Not requested,Requested"
bitfld.long 0x00 22. " [23] ,Transmission Request Bits[23]" "Not requested,Requested"
bitfld.long 0x00 21. " [22] ,Transmission Request Bits[22]" "Not requested,Requested"
bitfld.long 0x00 20. " [21] ,Transmission Request Bits[21]" "Not requested,Requested"
textline " "
bitfld.long 0x00 19. " [20] ,Transmission Request Bits[20]" "Not requested,Requested"
bitfld.long 0x00 18. " [19] ,Transmission Request Bits[19]" "Not requested,Requested"
bitfld.long 0x00 17. " [18] ,Transmission Request Bits[18]" "Not requested,Requested"
bitfld.long 0x00 16. " [17] ,Transmission Request Bits[17]" "Not requested,Requested"
textline " "
bitfld.long 0x00 15. " [16] ,Transmission Request Bits[16]" "Not requested,Requested"
bitfld.long 0x00 14. " [15] ,Transmission Request Bits[15]" "Not requested,Requested"
bitfld.long 0x00 13. " [14] ,Transmission Request Bits[14]" "Not requested,Requested"
bitfld.long 0x00 12. " [13] ,Transmission Request Bits[13]" "Not requested,Requested"
textline " "
bitfld.long 0x00 11. " [12] ,Transmission Request Bits[12]" "Not requested,Requested"
bitfld.long 0x00 10. " [11] ,Transmission Request Bits[11]" "Not requested,Requested"
bitfld.long 0x00 9. " [10] ,Transmission Request Bits[10]" "Not requested,Requested"
bitfld.long 0x00 8. " [9] ,Transmission Request Bits[9]" "Not requested,Requested"
textline " "
bitfld.long 0x00 7. " [8] ,Transmission Request Bits[8]" "Not requested,Requested"
bitfld.long 0x00 6. " [7] ,Transmission Request Bits[7]" "Not requested,Requested"
bitfld.long 0x00 5. " [6] ,Transmission Request Bits[6]" "Not requested,Requested"
bitfld.long 0x00 4. " [5] ,Transmission Request Bits[5]" "Not requested,Requested"
textline " "
bitfld.long 0x00 3. " [4] ,Transmission Request Bits[4]" "Not requested,Requested"
bitfld.long 0x00 2. " [3] ,Transmission Request Bits[3]" "Not requested,Requested"
bitfld.long 0x00 1. " [2] ,Transmission Request Bits[2]" "Not requested,Requested"
bitfld.long 0x00 0. " [1] ,Transmission Request Bits[1]" "Not requested,Requested"
rgroup.long 0x8C++0x3
line.long 0x0 "TRREQ43,Transmission Request 4_3"
bitfld.long 0x00 31. " TXRQST [64] ,Transmission Request Bits[64]" "Not requested,Requested"
bitfld.long 0x00 30. " [63] ,Transmission Request Bits[63]" "Not requested,Requested"
bitfld.long 0x00 29. " [62] ,Transmission Request Bits[62]" "Not requested,Requested"
bitfld.long 0x00 28. " [61] ,Transmission Request Bits[61]" "Not requested,Requested"
textline " "
bitfld.long 0x00 27. " [60] ,Transmission Request Bits[60]" "Not requested,Requested"
bitfld.long 0x00 26. " [59] ,Transmission Request Bits[59]" "Not requested,Requested"
bitfld.long 0x00 25. " [58] ,Transmission Request Bits[58]" "Not requested,Requested"
bitfld.long 0x00 24. " [57] ,Transmission Request Bits[57]" "Not requested,Requested"
textline " "
bitfld.long 0x00 23. " [56] ,Transmission Request Bits[56]" "Not requested,Requested"
bitfld.long 0x00 22. " [55] ,Transmission Request Bits[55]" "Not requested,Requested"
bitfld.long 0x00 21. " [54] ,Transmission Request Bits[54]" "Not requested,Requested"
bitfld.long 0x00 20. " [53] ,Transmission Request Bits[53]" "Not requested,Requested"
textline " "
bitfld.long 0x00 19. " [52] ,Transmission Request Bits[52]" "Not requested,Requested"
bitfld.long 0x00 18. " [51] ,Transmission Request Bits[51]" "Not requested,Requested"
bitfld.long 0x00 17. " [50] ,Transmission Request Bits[50]" "Not requested,Requested"
bitfld.long 0x00 16. " [49] ,Transmission Request Bits[49]" "Not requested,Requested"
textline " "
bitfld.long 0x00 15. " [48] ,Transmission Request Bits[48]" "Not requested,Requested"
bitfld.long 0x00 14. " [47] ,Transmission Request Bits[47]" "Not requested,Requested"
bitfld.long 0x00 13. " [46] ,Transmission Request Bits[46]" "Not requested,Requested"
bitfld.long 0x00 12. " [45] ,Transmission Request Bits[45]" "Not requested,Requested"
textline " "
bitfld.long 0x00 11. " [44] ,Transmission Request Bits[44]" "Not requested,Requested"
bitfld.long 0x00 10. " [43] ,Transmission Request Bits[43]" "Not requested,Requested"
bitfld.long 0x00 9. " [42] ,Transmission Request Bits[42]" "Not requested,Requested"
bitfld.long 0x00 8. " [41] ,Transmission Request Bits[41]" "Not requested,Requested"
textline " "
bitfld.long 0x00 7. " [40] ,Transmission Request Bits[40]" "Not requested,Requested"
bitfld.long 0x00 6. " [39] ,Transmission Request Bits[39]" "Not requested,Requested"
bitfld.long 0x00 5. " [38] ,Transmission Request Bits[38]" "Not requested,Requested"
bitfld.long 0x00 4. " [37] ,Transmission Request Bits[37]" "Not requested,Requested"
textline " "
bitfld.long 0x00 3. " [36] ,Transmission Request Bits[36]" "Not requested,Requested"
bitfld.long 0x00 2. " [35] ,Transmission Request Bits[35]" "Not requested,Requested"
bitfld.long 0x00 1. " [34] ,Transmission Request Bits[34]" "Not requested,Requested"
bitfld.long 0x00 0. " [33] ,Transmission Request Bits[33]" "Not requested,Requested"
rgroup.long 0x90++0x3
line.long 0x0 "TRREQ65,Transmission Request 6_5"
bitfld.long 0x00 31. " TXRQST [96] ,Transmission Request Bits[96]" "Not requested,Requested"
bitfld.long 0x00 30. " [95] ,Transmission Request Bits[95]" "Not requested,Requested"
bitfld.long 0x00 29. " [94] ,Transmission Request Bits[94]" "Not requested,Requested"
bitfld.long 0x00 28. " [93] ,Transmission Request Bits[93]" "Not requested,Requested"
textline " "
bitfld.long 0x00 27. " [92] ,Transmission Request Bits[92]" "Not requested,Requested"
bitfld.long 0x00 26. " [91] ,Transmission Request Bits[91]" "Not requested,Requested"
bitfld.long 0x00 25. " [90] ,Transmission Request Bits[90]" "Not requested,Requested"
bitfld.long 0x00 24. " [89] ,Transmission Request Bits[89]" "Not requested,Requested"
textline " "
bitfld.long 0x00 23. " [88] ,Transmission Request Bits[88]" "Not requested,Requested"
bitfld.long 0x00 22. " [87] ,Transmission Request Bits[87]" "Not requested,Requested"
bitfld.long 0x00 21. " [86] ,Transmission Request Bits[86]" "Not requested,Requested"
bitfld.long 0x00 20. " [85] ,Transmission Request Bits[85]" "Not requested,Requested"
textline " "
bitfld.long 0x00 19. " [84] ,Transmission Request Bits[84]" "Not requested,Requested"
bitfld.long 0x00 18. " [83] ,Transmission Request Bits[83]" "Not requested,Requested"
bitfld.long 0x00 17. " [82] ,Transmission Request Bits[82]" "Not requested,Requested"
bitfld.long 0x00 16. " [81] ,Transmission Request Bits[81]" "Not requested,Requested"
textline " "
bitfld.long 0x00 15. " [80] ,Transmission Request Bits[80]" "Not requested,Requested"
bitfld.long 0x00 14. " [79] ,Transmission Request Bits[79]" "Not requested,Requested"
bitfld.long 0x00 13. " [78] ,Transmission Request Bits[78]" "Not requested,Requested"
bitfld.long 0x00 12. " [77] ,Transmission Request Bits[77]" "Not requested,Requested"
textline " "
bitfld.long 0x00 11. " [76] ,Transmission Request Bits[76]" "Not requested,Requested"
bitfld.long 0x00 10. " [75] ,Transmission Request Bits[75]" "Not requested,Requested"
bitfld.long 0x00 9. " [74] ,Transmission Request Bits[74]" "Not requested,Requested"
bitfld.long 0x00 8. " [73] ,Transmission Request Bits[73]" "Not requested,Requested"
textline " "
bitfld.long 0x00 7. " [72] ,Transmission Request Bits[72]" "Not requested,Requested"
bitfld.long 0x00 6. " [71] ,Transmission Request Bits[71]" "Not requested,Requested"
bitfld.long 0x00 5. " [70] ,Transmission Request Bits[70]" "Not requested,Requested"
bitfld.long 0x00 4. " [69] ,Transmission Request Bits[69]" "Not requested,Requested"
textline " "
bitfld.long 0x00 3. " [68] ,Transmission Request Bits[68]" "Not requested,Requested"
bitfld.long 0x00 2. " [67] ,Transmission Request Bits[67]" "Not requested,Requested"
bitfld.long 0x00 1. " [66] ,Transmission Request Bits[66]" "Not requested,Requested"
bitfld.long 0x00 0. " [65] ,Transmission Request Bits[65]" "Not requested,Requested"
rgroup.long 0x94++0x3
line.long 0x0 "TRREQ87,Transmission Request 8_7"
bitfld.long 0x00 31. " TXRQST [128] ,Transmission Request Bits[128]" "Not requested,Requested"
bitfld.long 0x00 30. " [127] ,Transmission Request Bits[127]" "Not requested,Requested"
bitfld.long 0x00 29. " [126] ,Transmission Request Bits[126]" "Not requested,Requested"
bitfld.long 0x00 28. " [125] ,Transmission Request Bits[125]" "Not requested,Requested"
textline " "
bitfld.long 0x00 27. " [124] ,Transmission Request Bits[124]" "Not requested,Requested"
bitfld.long 0x00 26. " [123] ,Transmission Request Bits[123]" "Not requested,Requested"
bitfld.long 0x00 25. " [122] ,Transmission Request Bits[122]" "Not requested,Requested"
bitfld.long 0x00 24. " [121] ,Transmission Request Bits[121]" "Not requested,Requested"
textline " "
bitfld.long 0x00 23. " [120] ,Transmission Request Bits[120]" "Not requested,Requested"
bitfld.long 0x00 22. " [119] ,Transmission Request Bits[119]" "Not requested,Requested"
bitfld.long 0x00 21. " [118] ,Transmission Request Bits[118]" "Not requested,Requested"
bitfld.long 0x00 20. " [117] ,Transmission Request Bits[117]" "Not requested,Requested"
textline " "
bitfld.long 0x00 19. " [116] ,Transmission Request Bits[116]" "Not requested,Requested"
bitfld.long 0x00 18. " [115] ,Transmission Request Bits[115]" "Not requested,Requested"
bitfld.long 0x00 17. " [114] ,Transmission Request Bits[114]" "Not requested,Requested"
bitfld.long 0x00 16. " [113] ,Transmission Request Bits[113]" "Not requested,Requested"
textline " "
bitfld.long 0x00 15. " [112] ,Transmission Request Bits[112]" "Not requested,Requested"
bitfld.long 0x00 14. " [111] ,Transmission Request Bits[111]" "Not requested,Requested"
bitfld.long 0x00 13. " [110] ,Transmission Request Bits[110]" "Not requested,Requested"
bitfld.long 0x00 12. " [109] ,Transmission Request Bits[109]" "Not requested,Requested"
textline " "
bitfld.long 0x00 11. " [108] ,Transmission Request Bits[108]" "Not requested,Requested"
bitfld.long 0x00 10. " [107] ,Transmission Request Bits[107]" "Not requested,Requested"
bitfld.long 0x00 9. " [106] ,Transmission Request Bits[106]" "Not requested,Requested"
bitfld.long 0x00 8. " [105] ,Transmission Request Bits[105]" "Not requested,Requested"
textline " "
bitfld.long 0x00 7. " [104] ,Transmission Request Bits[104]" "Not requested,Requested"
bitfld.long 0x00 6. " [103] ,Transmission Request Bits[103]" "Not requested,Requested"
bitfld.long 0x00 5. " [102] ,Transmission Request Bits[102]" "Not requested,Requested"
bitfld.long 0x00 4. " [101] ,Transmission Request Bits[101]" "Not requested,Requested"
textline " "
bitfld.long 0x00 3. " [100] ,Transmission Request Bits[100]" "Not requested,Requested"
bitfld.long 0x00 2. " [99] ,Transmission Request Bits[99]" "Not requested,Requested"
bitfld.long 0x00 1. " [98] ,Transmission Request Bits[98]" "Not requested,Requested"
bitfld.long 0x00 0. " [97] ,Transmission Request Bits[97]" "Not requested,Requested"
width 12.
rgroup.long 0x98++0x3
line.long 0x0 "NEWDAT,New Data X"
bitfld.long 0x00 14.--15. " NEWDATREG [8] ,New Data 8" "0,1,2,3"
bitfld.long 0x00 12.--13. " [7] ,New Data 7" "0,1,2,3"
bitfld.long 0x00 10.--11. " [6] ,New Data 6" "0,1,2,3"
bitfld.long 0x00 8.--9. " [5] ,New Data 5" "0,1,2,3"
textline " "
bitfld.long 0x00 6.--7. " [4] ,New Data 4" "0,1,2,3"
bitfld.long 0x00 4.--5. " [3] ,New Data 3" "0,1,2,3"
bitfld.long 0x00 2.--3. " [2] ,New Data 2" "0,1,2,3"
bitfld.long 0x00 0.--1. " [1] ,New Data 1" "0,1,2,3"
width 12.
rgroup.long 0x9C++0x3
line.long 0x0 "NEWDAT21,New Data 2_1"
bitfld.long 0x00 31. " NEWDAT [32] ,New Data Bit[32]" "Not requested,Requested"
bitfld.long 0x00 30. " [31] ,New Data Bit[31]" "Not requested,Requested"
bitfld.long 0x00 29. " [30] ,New Data Bit[30]" "Not requested,Requested"
bitfld.long 0x00 28. " [29] ,New Data Bit[29]" "Not requested,Requested"
textline " "
bitfld.long 0x00 27. " [28] ,New Data Bit[28]" "Not requested,Requested"
bitfld.long 0x00 26. " [27] ,New Data Bit[27]" "Not requested,Requested"
bitfld.long 0x00 25. " [26] ,New Data Bit[26]" "Not requested,Requested"
bitfld.long 0x00 24. " [25] ,New Data Bit[25]" "Not requested,Requested"
textline " "
bitfld.long 0x00 23. " [24] ,New Data Bit[24]" "Not requested,Requested"
bitfld.long 0x00 22. " [23] ,New Data Bit[23]" "Not requested,Requested"
bitfld.long 0x00 21. " [22] ,New Data Bit[22]" "Not requested,Requested"
bitfld.long 0x00 20. " [21] ,New Data Bit[21]" "Not requested,Requested"
textline " "
bitfld.long 0x00 19. " [20] ,New Data Bit[20]" "Not requested,Requested"
bitfld.long 0x00 18. " [19] ,New Data Bit[19]" "Not requested,Requested"
bitfld.long 0x00 17. " [18] ,New Data Bit[18]" "Not requested,Requested"
bitfld.long 0x00 16. " [17] ,New Data Bit[17]" "Not requested,Requested"
textline " "
bitfld.long 0x00 15. " [16] ,New Data Bit[16]" "Not requested,Requested"
bitfld.long 0x00 14. " [15] ,New Data Bit[15]" "Not requested,Requested"
bitfld.long 0x00 13. " [14] ,New Data Bit[14]" "Not requested,Requested"
bitfld.long 0x00 12. " [13] ,New Data Bit[13]" "Not requested,Requested"
textline " "
bitfld.long 0x00 11. " [12] ,New Data Bit[12]" "Not requested,Requested"
bitfld.long 0x00 10. " [11] ,New Data Bit[11]" "Not requested,Requested"
bitfld.long 0x00 9. " [10] ,New Data Bit[10]" "Not requested,Requested"
bitfld.long 0x00 8. " [9] ,New Data Bit[9]" "Not requested,Requested"
textline " "
bitfld.long 0x00 7. " [8] ,New Data Bit[8]" "Not requested,Requested"
bitfld.long 0x00 6. " [7] ,New Data Bit[7]" "Not requested,Requested"
bitfld.long 0x00 5. " [6] ,New Data Bit[6]" "Not requested,Requested"
bitfld.long 0x00 4. " [5] ,New Data Bit[5]" "Not requested,Requested"
textline " "
bitfld.long 0x00 3. " [4] ,New Data Bit[4]" "Not requested,Requested"
bitfld.long 0x00 2. " [3] ,New Data Bit[3]" "Not requested,Requested"
bitfld.long 0x00 1. " [2] ,New Data Bit[2]" "Not requested,Requested"
bitfld.long 0x00 0. " [1] ,New Data Bit[1]" "Not requested,Requested"
rgroup.long 0xA0++0x3
line.long 0x0 "NEWDAT43,New Data 4_3"
bitfld.long 0x00 31. " NEWDAT [64] ,New Data Bit[64]" "Not requested,Requested"
bitfld.long 0x00 30. " [63] ,New Data Bit[63]" "Not requested,Requested"
bitfld.long 0x00 29. " [62] ,New Data Bit[62]" "Not requested,Requested"
bitfld.long 0x00 28. " [61] ,New Data Bit[61]" "Not requested,Requested"
textline " "
bitfld.long 0x00 27. " [60] ,New Data Bit[60]" "Not requested,Requested"
bitfld.long 0x00 26. " [59] ,New Data Bit[59]" "Not requested,Requested"
bitfld.long 0x00 25. " [58] ,New Data Bit[58]" "Not requested,Requested"
bitfld.long 0x00 24. " [57] ,New Data Bit[57]" "Not requested,Requested"
textline " "
bitfld.long 0x00 23. " [56] ,New Data Bit[56]" "Not requested,Requested"
bitfld.long 0x00 22. " [55] ,New Data Bit[55]" "Not requested,Requested"
bitfld.long 0x00 21. " [54] ,New Data Bit[54]" "Not requested,Requested"
bitfld.long 0x00 20. " [53] ,New Data Bit[53]" "Not requested,Requested"
textline " "
bitfld.long 0x00 19. " [52] ,New Data Bit[52]" "Not requested,Requested"
bitfld.long 0x00 18. " [51] ,New Data Bit[51]" "Not requested,Requested"
bitfld.long 0x00 17. " [50] ,New Data Bit[50]" "Not requested,Requested"
bitfld.long 0x00 16. " [49] ,New Data Bit[49]" "Not requested,Requested"
textline " "
bitfld.long 0x00 15. " [48] ,New Data Bit[48]" "Not requested,Requested"
bitfld.long 0x00 14. " [47] ,New Data Bit[47]" "Not requested,Requested"
bitfld.long 0x00 13. " [46] ,New Data Bit[46]" "Not requested,Requested"
bitfld.long 0x00 12. " [45] ,New Data Bit[45]" "Not requested,Requested"
textline " "
bitfld.long 0x00 11. " [44] ,New Data Bit[44]" "Not requested,Requested"
bitfld.long 0x00 10. " [43] ,New Data Bit[43]" "Not requested,Requested"
bitfld.long 0x00 9. " [42] ,New Data Bit[42]" "Not requested,Requested"
bitfld.long 0x00 8. " [41] ,New Data Bit[41]" "Not requested,Requested"
textline " "
bitfld.long 0x00 7. " [40] ,New Data Bit[40]" "Not requested,Requested"
bitfld.long 0x00 6. " [39] ,New Data Bit[39]" "Not requested,Requested"
bitfld.long 0x00 5. " [38] ,New Data Bit[38]" "Not requested,Requested"
bitfld.long 0x00 4. " [37] ,New Data Bit[37]" "Not requested,Requested"
textline " "
bitfld.long 0x00 3. " [36] ,New Data Bit[36]" "Not requested,Requested"
bitfld.long 0x00 2. " [35] ,New Data Bit[35]" "Not requested,Requested"
bitfld.long 0x00 1. " [34] ,New Data Bit[34]" "Not requested,Requested"
bitfld.long 0x00 0. " [33] ,New Data Bit[33]" "Not requested,Requested"
rgroup.long 0xA4++0x3
line.long 0x0 "NEWDAT65,New Data 6_5"
bitfld.long 0x00 31. " NEWDAT [96] ,New Data Bit[96]" "Not requested,Requested"
bitfld.long 0x00 30. " [95] ,New Data Bit[95]" "Not requested,Requested"
bitfld.long 0x00 29. " [94] ,New Data Bit[94]" "Not requested,Requested"
bitfld.long 0x00 28. " [93] ,New Data Bit[93]" "Not requested,Requested"
textline " "
bitfld.long 0x00 27. " [92] ,New Data Bit[92]" "Not requested,Requested"
bitfld.long 0x00 26. " [91] ,New Data Bit[91]" "Not requested,Requested"
bitfld.long 0x00 25. " [90] ,New Data Bit[90]" "Not requested,Requested"
bitfld.long 0x00 24. " [89] ,New Data Bit[89]" "Not requested,Requested"
textline " "
bitfld.long 0x00 23. " [88] ,New Data Bit[88]" "Not requested,Requested"
bitfld.long 0x00 22. " [87] ,New Data Bit[87]" "Not requested,Requested"
bitfld.long 0x00 21. " [86] ,New Data Bit[86]" "Not requested,Requested"
bitfld.long 0x00 20. " [85] ,New Data Bit[85]" "Not requested,Requested"
textline " "
bitfld.long 0x00 19. " [84] ,New Data Bit[84]" "Not requested,Requested"
bitfld.long 0x00 18. " [83] ,New Data Bit[83]" "Not requested,Requested"
bitfld.long 0x00 17. " [82] ,New Data Bit[82]" "Not requested,Requested"
bitfld.long 0x00 16. " [81] ,New Data Bit[81]" "Not requested,Requested"
textline " "
bitfld.long 0x00 15. " [80] ,New Data Bit[80]" "Not requested,Requested"
bitfld.long 0x00 14. " [79] ,New Data Bit[79]" "Not requested,Requested"
bitfld.long 0x00 13. " [78] ,New Data Bit[78]" "Not requested,Requested"
bitfld.long 0x00 12. " [77] ,New Data Bit[77]" "Not requested,Requested"
textline " "
bitfld.long 0x00 11. " [76] ,New Data Bit[76]" "Not requested,Requested"
bitfld.long 0x00 10. " [75] ,New Data Bit[75]" "Not requested,Requested"
bitfld.long 0x00 9. " [74] ,New Data Bit[74]" "Not requested,Requested"
bitfld.long 0x00 8. " [73] ,New Data Bit[73]" "Not requested,Requested"
textline " "
bitfld.long 0x00 7. " [72] ,New Data Bit[72]" "Not requested,Requested"
bitfld.long 0x00 6. " [71] ,New Data Bit[71]" "Not requested,Requested"
bitfld.long 0x00 5. " [70] ,New Data Bit[70]" "Not requested,Requested"
bitfld.long 0x00 4. " [69] ,New Data Bit[69]" "Not requested,Requested"
textline " "
bitfld.long 0x00 3. " [68] ,New Data Bit[68]" "Not requested,Requested"
bitfld.long 0x00 2. " [67] ,New Data Bit[67]" "Not requested,Requested"
bitfld.long 0x00 1. " [66] ,New Data Bit[66]" "Not requested,Requested"
bitfld.long 0x00 0. " [65] ,New Data Bit[65]" "Not requested,Requested"
rgroup.long 0xA8++0x3
line.long 0x0 "NEWDAT87,New Data 8_7"
bitfld.long 0x00 31. " NEWDAT [128] ,New Data Bit[128]" "Not requested,Requested"
bitfld.long 0x00 30. " [127] ,New Data Bit[127]" "Not requested,Requested"
bitfld.long 0x00 29. " [126] ,New Data Bit[126]" "Not requested,Requested"
bitfld.long 0x00 28. " [125] ,New Data Bit[125]" "Not requested,Requested"
textline " "
bitfld.long 0x00 27. " [124] ,New Data Bit[124]" "Not requested,Requested"
bitfld.long 0x00 26. " [123] ,New Data Bit[123]" "Not requested,Requested"
bitfld.long 0x00 25. " [122] ,New Data Bit[122]" "Not requested,Requested"
bitfld.long 0x00 24. " [121] ,New Data Bit[121]" "Not requested,Requested"
textline " "
bitfld.long 0x00 23. " [120] ,New Data Bit[120]" "Not requested,Requested"
bitfld.long 0x00 22. " [119] ,New Data Bit[119]" "Not requested,Requested"
bitfld.long 0x00 21. " [118] ,New Data Bit[118]" "Not requested,Requested"
bitfld.long 0x00 20. " [117] ,New Data Bit[117]" "Not requested,Requested"
textline " "
bitfld.long 0x00 19. " [116] ,New Data Bit[116]" "Not requested,Requested"
bitfld.long 0x00 18. " [115] ,New Data Bit[115]" "Not requested,Requested"
bitfld.long 0x00 17. " [114] ,New Data Bit[114]" "Not requested,Requested"
bitfld.long 0x00 16. " [113] ,New Data Bit[113]" "Not requested,Requested"
textline " "
bitfld.long 0x00 15. " [112] ,New Data Bit[112]" "Not requested,Requested"
bitfld.long 0x00 14. " [111] ,New Data Bit[111]" "Not requested,Requested"
bitfld.long 0x00 13. " [110] ,New Data Bit[110]" "Not requested,Requested"
bitfld.long 0x00 12. " [109] ,New Data Bit[109]" "Not requested,Requested"
textline " "
bitfld.long 0x00 11. " [108] ,New Data Bit[108]" "Not requested,Requested"
bitfld.long 0x00 10. " [107] ,New Data Bit[107]" "Not requested,Requested"
bitfld.long 0x00 9. " [106] ,New Data Bit[106]" "Not requested,Requested"
bitfld.long 0x00 8. " [105] ,New Data Bit[105]" "Not requested,Requested"
textline " "
bitfld.long 0x00 7. " [104] ,New Data Bit[104]" "Not requested,Requested"
bitfld.long 0x00 6. " [103] ,New Data Bit[103]" "Not requested,Requested"
bitfld.long 0x00 5. " [102] ,New Data Bit[102]" "Not requested,Requested"
bitfld.long 0x00 4. " [101] ,New Data Bit[101]" "Not requested,Requested"
textline " "
bitfld.long 0x00 3. " [100] ,New Data Bit[100]" "Not requested,Requested"
bitfld.long 0x00 2. " [99] ,New Data Bit[99]" "Not requested,Requested"
bitfld.long 0x00 1. " [98] ,New Data Bit[98]" "Not requested,Requested"
bitfld.long 0x00 0. " [97] ,New Data Bit[97]" "Not requested,Requested"
width 12.
rgroup.long 0xAC++0x3
line.long 0x0 "INTPEN,Interrupt Pending X"
bitfld.long 0x00 14.--15. " INTPENDREG [8] ,Interrupt Pending 8" "0,1,2,3"
bitfld.long 0x00 12.--13. " [7] ,Interrupt Pending 7" "0,1,2,3"
bitfld.long 0x00 10.--11. " [6] ,Interrupt Pending 6" "0,1,2,3"
bitfld.long 0x00 8.--9. " [5] ,Interrupt Pending 5" "0,1,2,3"
textline " "
bitfld.long 0x00 6.--7. " [4] ,Interrupt Pending 4" "0,1,2,3"
bitfld.long 0x00 4.--5. " [3] ,Interrupt Pending 3" "0,1,2,3"
bitfld.long 0x00 2.--3. " [2] ,Interrupt Pending 2" "0,1,2,3"
bitfld.long 0x00 0.--1. " [1] ,Interrupt Pending 1" "0,1,2,3"
width 12.
rgroup.long 0xB0++0x3
line.long 0x0 "INTPEN21,Interrupt Pending 2_1"
bitfld.long 0x00 31. " INTPND [32] ,Interrupt Pending Bit[32]" "No interrupt,Interrupt"
bitfld.long 0x00 30. " [31] ,Interrupt Pending Bit[31]" "No interrupt,Interrupt"
bitfld.long 0x00 29. " [30] ,Interrupt Pending Bit[30]" "No interrupt,Interrupt"
bitfld.long 0x00 28. " [29] ,Interrupt Pending Bit[29]" "No interrupt,Interrupt"
textline " "
bitfld.long 0x00 27. " [28] ,Interrupt Pending Bit[28]" "No interrupt,Interrupt"
bitfld.long 0x00 26. " [27] ,Interrupt Pending Bit[27]" "No interrupt,Interrupt"
bitfld.long 0x00 25. " [26] ,Interrupt Pending Bit[26]" "No interrupt,Interrupt"
bitfld.long 0x00 24. " [25] ,Interrupt Pending Bit[25]" "No interrupt,Interrupt"
textline " "
bitfld.long 0x00 23. " [24] ,Interrupt Pending Bit[24]" "No interrupt,Interrupt"
bitfld.long 0x00 22. " [23] ,Interrupt Pending Bit[23]" "No interrupt,Interrupt"
bitfld.long 0x00 21. " [22] ,Interrupt Pending Bit[22]" "No interrupt,Interrupt"
bitfld.long 0x00 20. " [21] ,Interrupt Pending Bit[21]" "No interrupt,Interrupt"
textline " "
bitfld.long 0x00 19. " [20] ,Interrupt Pending Bit[20]" "No interrupt,Interrupt"
bitfld.long 0x00 18. " [19] ,Interrupt Pending Bit[19]" "No interrupt,Interrupt"
bitfld.long 0x00 17. " [18] ,Interrupt Pending Bit[18]" "No interrupt,Interrupt"
bitfld.long 0x00 16. " [17] ,Interrupt Pending Bit[17]" "No interrupt,Interrupt"
textline " "
bitfld.long 0x00 15. " [16] ,Interrupt Pending Bit[16]" "No interrupt,Interrupt"
bitfld.long 0x00 14. " [15] ,Interrupt Pending Bit[15]" "No interrupt,Interrupt"
bitfld.long 0x00 13. " [14] ,Interrupt Pending Bit[14]" "No interrupt,Interrupt"
bitfld.long 0x00 12. " [13] ,Interrupt Pending Bit[13]" "No interrupt,Interrupt"
textline " "
bitfld.long 0x00 11. " [12] ,Interrupt Pending Bit[12]" "No interrupt,Interrupt"
bitfld.long 0x00 10. " [11] ,Interrupt Pending Bit[11]" "No interrupt,Interrupt"
bitfld.long 0x00 9. " [10] ,Interrupt Pending Bit[10]" "No interrupt,Interrupt"
bitfld.long 0x00 8. " [9] ,Interrupt Pending Bit[9]" "No interrupt,Interrupt"
textline " "
bitfld.long 0x00 7. " [8] ,Interrupt Pending Bit[8]" "No interrupt,Interrupt"
bitfld.long 0x00 6. " [7] ,Interrupt Pending Bit[7]" "No interrupt,Interrupt"
bitfld.long 0x00 5. " [6] ,Interrupt Pending Bit[6]" "No interrupt,Interrupt"
bitfld.long 0x00 4. " [5] ,Interrupt Pending Bit[5]" "No interrupt,Interrupt"
textline " "
bitfld.long 0x00 3. " [4] ,Interrupt Pending Bit[4]" "No interrupt,Interrupt"
bitfld.long 0x00 2. " [3] ,Interrupt Pending Bit[3]" "No interrupt,Interrupt"
bitfld.long 0x00 1. " [2] ,Interrupt Pending Bit[2]" "No interrupt,Interrupt"
bitfld.long 0x00 0. " [1] ,Interrupt Pending Bit[1]" "No interrupt,Interrupt"
rgroup.long 0xB4++0x3
line.long 0x0 "INTPEN43,Interrupt Pending 4_3"
bitfld.long 0x00 31. " INTPND [64] ,Interrupt Pending Bit[64]" "No interrupt,Interrupt"
bitfld.long 0x00 30. " [63] ,Interrupt Pending Bit[63]" "No interrupt,Interrupt"
bitfld.long 0x00 29. " [62] ,Interrupt Pending Bit[62]" "No interrupt,Interrupt"
bitfld.long 0x00 28. " [61] ,Interrupt Pending Bit[61]" "No interrupt,Interrupt"
textline " "
bitfld.long 0x00 27. " [60] ,Interrupt Pending Bit[60]" "No interrupt,Interrupt"
bitfld.long 0x00 26. " [59] ,Interrupt Pending Bit[59]" "No interrupt,Interrupt"
bitfld.long 0x00 25. " [58] ,Interrupt Pending Bit[58]" "No interrupt,Interrupt"
bitfld.long 0x00 24. " [57] ,Interrupt Pending Bit[57]" "No interrupt,Interrupt"
textline " "
bitfld.long 0x00 23. " [56] ,Interrupt Pending Bit[56]" "No interrupt,Interrupt"
bitfld.long 0x00 22. " [55] ,Interrupt Pending Bit[55]" "No interrupt,Interrupt"
bitfld.long 0x00 21. " [54] ,Interrupt Pending Bit[54]" "No interrupt,Interrupt"
bitfld.long 0x00 20. " [53] ,Interrupt Pending Bit[53]" "No interrupt,Interrupt"
textline " "
bitfld.long 0x00 19. " [52] ,Interrupt Pending Bit[52]" "No interrupt,Interrupt"
bitfld.long 0x00 18. " [51] ,Interrupt Pending Bit[51]" "No interrupt,Interrupt"
bitfld.long 0x00 17. " [50] ,Interrupt Pending Bit[50]" "No interrupt,Interrupt"
bitfld.long 0x00 16. " [49] ,Interrupt Pending Bit[49]" "No interrupt,Interrupt"
textline " "
bitfld.long 0x00 15. " [48] ,Interrupt Pending Bit[48]" "No interrupt,Interrupt"
bitfld.long 0x00 14. " [47] ,Interrupt Pending Bit[47]" "No interrupt,Interrupt"
bitfld.long 0x00 13. " [46] ,Interrupt Pending Bit[46]" "No interrupt,Interrupt"
bitfld.long 0x00 12. " [45] ,Interrupt Pending Bit[45]" "No interrupt,Interrupt"
textline " "
bitfld.long 0x00 11. " [44] ,Interrupt Pending Bit[44]" "No interrupt,Interrupt"
bitfld.long 0x00 10. " [43] ,Interrupt Pending Bit[43]" "No interrupt,Interrupt"
bitfld.long 0x00 9. " [42] ,Interrupt Pending Bit[42]" "No interrupt,Interrupt"
bitfld.long 0x00 8. " [41] ,Interrupt Pending Bit[41]" "No interrupt,Interrupt"
textline " "
bitfld.long 0x00 7. " [40] ,Interrupt Pending Bit[40]" "No interrupt,Interrupt"
bitfld.long 0x00 6. " [39] ,Interrupt Pending Bit[39]" "No interrupt,Interrupt"
bitfld.long 0x00 5. " [38] ,Interrupt Pending Bit[38]" "No interrupt,Interrupt"
bitfld.long 0x00 4. " [37] ,Interrupt Pending Bit[37]" "No interrupt,Interrupt"
textline " "
bitfld.long 0x00 3. " [36] ,Interrupt Pending Bit[36]" "No interrupt,Interrupt"
bitfld.long 0x00 2. " [35] ,Interrupt Pending Bit[35]" "No interrupt,Interrupt"
bitfld.long 0x00 1. " [34] ,Interrupt Pending Bit[34]" "No interrupt,Interrupt"
bitfld.long 0x00 0. " [33] ,Interrupt Pending Bit[33]" "No interrupt,Interrupt"
rgroup.long 0xB8++0x3
line.long 0x0 "INTPEN65,Interrupt Pending 6_5"
bitfld.long 0x00 31. " INTPND [96] ,Interrupt Pending Bit[96]" "No interrupt,Interrupt"
bitfld.long 0x00 30. " [95] ,Interrupt Pending Bit[95]" "No interrupt,Interrupt"
bitfld.long 0x00 29. " [94] ,Interrupt Pending Bit[94]" "No interrupt,Interrupt"
bitfld.long 0x00 28. " [93] ,Interrupt Pending Bit[93]" "No interrupt,Interrupt"
textline " "
bitfld.long 0x00 27. " [92] ,Interrupt Pending Bit[92]" "No interrupt,Interrupt"
bitfld.long 0x00 26. " [91] ,Interrupt Pending Bit[91]" "No interrupt,Interrupt"
bitfld.long 0x00 25. " [90] ,Interrupt Pending Bit[90]" "No interrupt,Interrupt"
bitfld.long 0x00 24. " [89] ,Interrupt Pending Bit[89]" "No interrupt,Interrupt"
textline " "
bitfld.long 0x00 23. " [88] ,Interrupt Pending Bit[88]" "No interrupt,Interrupt"
bitfld.long 0x00 22. " [87] ,Interrupt Pending Bit[87]" "No interrupt,Interrupt"
bitfld.long 0x00 21. " [86] ,Interrupt Pending Bit[86]" "No interrupt,Interrupt"
bitfld.long 0x00 20. " [85] ,Interrupt Pending Bit[85]" "No interrupt,Interrupt"
textline " "
bitfld.long 0x00 19. " [84] ,Interrupt Pending Bit[84]" "No interrupt,Interrupt"
bitfld.long 0x00 18. " [83] ,Interrupt Pending Bit[83]" "No interrupt,Interrupt"
bitfld.long 0x00 17. " [82] ,Interrupt Pending Bit[82]" "No interrupt,Interrupt"
bitfld.long 0x00 16. " [81] ,Interrupt Pending Bit[81]" "No interrupt,Interrupt"
textline " "
bitfld.long 0x00 15. " [80] ,Interrupt Pending Bit[80]" "No interrupt,Interrupt"
bitfld.long 0x00 14. " [79] ,Interrupt Pending Bit[79]" "No interrupt,Interrupt"
bitfld.long 0x00 13. " [78] ,Interrupt Pending Bit[78]" "No interrupt,Interrupt"
bitfld.long 0x00 12. " [77] ,Interrupt Pending Bit[77]" "No interrupt,Interrupt"
textline " "
bitfld.long 0x00 11. " [76] ,Interrupt Pending Bit[76]" "No interrupt,Interrupt"
bitfld.long 0x00 10. " [75] ,Interrupt Pending Bit[75]" "No interrupt,Interrupt"
bitfld.long 0x00 9. " [74] ,Interrupt Pending Bit[74]" "No interrupt,Interrupt"
bitfld.long 0x00 8. " [73] ,Interrupt Pending Bit[73]" "No interrupt,Interrupt"
textline " "
bitfld.long 0x00 7. " [72] ,Interrupt Pending Bit[72]" "No interrupt,Interrupt"
bitfld.long 0x00 6. " [71] ,Interrupt Pending Bit[71]" "No interrupt,Interrupt"
bitfld.long 0x00 5. " [70] ,Interrupt Pending Bit[70]" "No interrupt,Interrupt"
bitfld.long 0x00 4. " [69] ,Interrupt Pending Bit[69]" "No interrupt,Interrupt"
textline " "
bitfld.long 0x00 3. " [68] ,Interrupt Pending Bit[68]" "No interrupt,Interrupt"
bitfld.long 0x00 2. " [67] ,Interrupt Pending Bit[67]" "No interrupt,Interrupt"
bitfld.long 0x00 1. " [66] ,Interrupt Pending Bit[66]" "No interrupt,Interrupt"
bitfld.long 0x00 0. " [65] ,Interrupt Pending Bit[65]" "No interrupt,Interrupt"
rgroup.long 0xBC++0x3
line.long 0x0 "INTPEN87,Interrupt Pending 8_7"
bitfld.long 0x00 31. " INTPND [128] ,Interrupt Pending Bit[128]" "No interrupt,Interrupt"
bitfld.long 0x00 30. " [127] ,Interrupt Pending Bit[127]" "No interrupt,Interrupt"
bitfld.long 0x00 29. " [126] ,Interrupt Pending Bit[126]" "No interrupt,Interrupt"
bitfld.long 0x00 28. " [125] ,Interrupt Pending Bit[125]" "No interrupt,Interrupt"
textline " "
bitfld.long 0x00 27. " [124] ,Interrupt Pending Bit[124]" "No interrupt,Interrupt"
bitfld.long 0x00 26. " [123] ,Interrupt Pending Bit[123]" "No interrupt,Interrupt"
bitfld.long 0x00 25. " [122] ,Interrupt Pending Bit[122]" "No interrupt,Interrupt"
bitfld.long 0x00 24. " [121] ,Interrupt Pending Bit[121]" "No interrupt,Interrupt"
textline " "
bitfld.long 0x00 23. " [120] ,Interrupt Pending Bit[120]" "No interrupt,Interrupt"
bitfld.long 0x00 22. " [119] ,Interrupt Pending Bit[119]" "No interrupt,Interrupt"
bitfld.long 0x00 21. " [118] ,Interrupt Pending Bit[118]" "No interrupt,Interrupt"
bitfld.long 0x00 20. " [117] ,Interrupt Pending Bit[117]" "No interrupt,Interrupt"
textline " "
bitfld.long 0x00 19. " [116] ,Interrupt Pending Bit[116]" "No interrupt,Interrupt"
bitfld.long 0x00 18. " [115] ,Interrupt Pending Bit[115]" "No interrupt,Interrupt"
bitfld.long 0x00 17. " [114] ,Interrupt Pending Bit[114]" "No interrupt,Interrupt"
bitfld.long 0x00 16. " [113] ,Interrupt Pending Bit[113]" "No interrupt,Interrupt"
textline " "
bitfld.long 0x00 15. " [112] ,Interrupt Pending Bit[112]" "No interrupt,Interrupt"
bitfld.long 0x00 14. " [111] ,Interrupt Pending Bit[111]" "No interrupt,Interrupt"
bitfld.long 0x00 13. " [110] ,Interrupt Pending Bit[110]" "No interrupt,Interrupt"
bitfld.long 0x00 12. " [109] ,Interrupt Pending Bit[109]" "No interrupt,Interrupt"
textline " "
bitfld.long 0x00 11. " [108] ,Interrupt Pending Bit[108]" "No interrupt,Interrupt"
bitfld.long 0x00 10. " [107] ,Interrupt Pending Bit[107]" "No interrupt,Interrupt"
bitfld.long 0x00 9. " [106] ,Interrupt Pending Bit[106]" "No interrupt,Interrupt"
bitfld.long 0x00 8. " [105] ,Interrupt Pending Bit[105]" "No interrupt,Interrupt"
textline " "
bitfld.long 0x00 7. " [104] ,Interrupt Pending Bit[104]" "No interrupt,Interrupt"
bitfld.long 0x00 6. " [103] ,Interrupt Pending Bit[103]" "No interrupt,Interrupt"
bitfld.long 0x00 5. " [102] ,Interrupt Pending Bit[102]" "No interrupt,Interrupt"
bitfld.long 0x00 4. " [101] ,Interrupt Pending Bit[101]" "No interrupt,Interrupt"
textline " "
bitfld.long 0x00 3. " [100] ,Interrupt Pending Bit[100]" "No interrupt,Interrupt"
bitfld.long 0x00 2. " [99] ,Interrupt Pending Bit[99]" "No interrupt,Interrupt"
bitfld.long 0x00 1. " [98] ,Interrupt Pending Bit[98]" "No interrupt,Interrupt"
bitfld.long 0x00 0. " [97] ,Interrupt Pending Bit[97]" "No interrupt,Interrupt"
width 12.
rgroup.long 0xC0++0x3
line.long 0x0 "MVAL,Message Valid X"
bitfld.long 0x00 14.--15. " MSGVALREG [8] ,Message Valid Register 8" "0,1,2,3"
bitfld.long 0x00 12.--13. " [7] ,Message Valid Register 7" "0,1,2,3"
bitfld.long 0x00 10.--11. " [6] ,Message Valid Register 6" "0,1,2,3"
bitfld.long 0x00 8.--9. " [5] ,Message Valid Register 5" "0,1,2,3"
textline " "
bitfld.long 0x00 6.--7. " [4] ,Message Valid Register 4" "0,1,2,3"
bitfld.long 0x00 4.--5. " [3] ,Message Valid Register 3" "0,1,2,3"
bitfld.long 0x00 2.--3. " [2] ,Message Valid Register 2" "0,1,2,3"
bitfld.long 0x00 0.--1. " [1] ,Message Valid Register 1" "0,1,2,3"
width 12.
rgroup.long 0xC4++0x3
line.long 0x0 "MVAL21,Message Valid 2_1"
bitfld.long 0x00 31. " MSGVAL [32] ,Message Valid Bit[32]" "Ignored,Configured"
bitfld.long 0x00 30. " [31] ,Message Valid Bit[31]" "Ignored,Configured"
bitfld.long 0x00 29. " [30] ,Message Valid Bit[30]" "Ignored,Configured"
bitfld.long 0x00 28. " [29] ,Message Valid Bit[29]" "Ignored,Configured"
textline " "
bitfld.long 0x00 27. " [28] ,Message Valid Bit[28]" "Ignored,Configured"
bitfld.long 0x00 26. " [27] ,Message Valid Bit[27]" "Ignored,Configured"
bitfld.long 0x00 25. " [26] ,Message Valid Bit[26]" "Ignored,Configured"
bitfld.long 0x00 24. " [25] ,Message Valid Bit[25]" "Ignored,Configured"
textline " "
bitfld.long 0x00 23. " [24] ,Message Valid Bit[24]" "Ignored,Configured"
bitfld.long 0x00 22. " [23] ,Message Valid Bit[23]" "Ignored,Configured"
bitfld.long 0x00 21. " [22] ,Message Valid Bit[22]" "Ignored,Configured"
bitfld.long 0x00 20. " [21] ,Message Valid Bit[21]" "Ignored,Configured"
textline " "
bitfld.long 0x00 19. " [20] ,Message Valid Bit[20]" "Ignored,Configured"
bitfld.long 0x00 18. " [19] ,Message Valid Bit[19]" "Ignored,Configured"
bitfld.long 0x00 17. " [18] ,Message Valid Bit[18]" "Ignored,Configured"
bitfld.long 0x00 16. " [17] ,Message Valid Bit[17]" "Ignored,Configured"
textline " "
bitfld.long 0x00 15. " [16] ,Message Valid Bit[16]" "Ignored,Configured"
bitfld.long 0x00 14. " [15] ,Message Valid Bit[15]" "Ignored,Configured"
bitfld.long 0x00 13. " [14] ,Message Valid Bit[14]" "Ignored,Configured"
bitfld.long 0x00 12. " [13] ,Message Valid Bit[13]" "Ignored,Configured"
textline " "
bitfld.long 0x00 11. " [12] ,Message Valid Bit[12]" "Ignored,Configured"
bitfld.long 0x00 10. " [11] ,Message Valid Bit[11]" "Ignored,Configured"
bitfld.long 0x00 9. " [10] ,Message Valid Bit[10]" "Ignored,Configured"
bitfld.long 0x00 8. " [9] ,Message Valid Bit[9]" "Ignored,Configured"
textline " "
bitfld.long 0x00 7. " [8] ,Message Valid Bit[8]" "Ignored,Configured"
bitfld.long 0x00 6. " [7] ,Message Valid Bit[7]" "Ignored,Configured"
bitfld.long 0x00 5. " [6] ,Message Valid Bit[6]" "Ignored,Configured"
bitfld.long 0x00 4. " [5] ,Message Valid Bit[5]" "Ignored,Configured"
textline " "
bitfld.long 0x00 3. " [4] ,Message Valid Bit[4]" "Ignored,Configured"
bitfld.long 0x00 2. " [3] ,Message Valid Bit[3]" "Ignored,Configured"
bitfld.long 0x00 1. " [2] ,Message Valid Bit[2]" "Ignored,Configured"
bitfld.long 0x00 0. " [1] ,Message Valid Bit[1]" "Ignored,Configured"
rgroup.long 0xC8++0x3
line.long 0x0 "MVAL43,Message Valid 4_3"
bitfld.long 0x00 31. " MSGVAL [64] ,Message Valid Bit[64]" "Ignored,Configured"
bitfld.long 0x00 30. " [63] ,Message Valid Bit[63]" "Ignored,Configured"
bitfld.long 0x00 29. " [62] ,Message Valid Bit[62]" "Ignored,Configured"
bitfld.long 0x00 28. " [61] ,Message Valid Bit[61]" "Ignored,Configured"
textline " "
bitfld.long 0x00 27. " [60] ,Message Valid Bit[60]" "Ignored,Configured"
bitfld.long 0x00 26. " [59] ,Message Valid Bit[59]" "Ignored,Configured"
bitfld.long 0x00 25. " [58] ,Message Valid Bit[58]" "Ignored,Configured"
bitfld.long 0x00 24. " [57] ,Message Valid Bit[57]" "Ignored,Configured"
textline " "
bitfld.long 0x00 23. " [56] ,Message Valid Bit[56]" "Ignored,Configured"
bitfld.long 0x00 22. " [55] ,Message Valid Bit[55]" "Ignored,Configured"
bitfld.long 0x00 21. " [54] ,Message Valid Bit[54]" "Ignored,Configured"
bitfld.long 0x00 20. " [53] ,Message Valid Bit[53]" "Ignored,Configured"
textline " "
bitfld.long 0x00 19. " [52] ,Message Valid Bit[52]" "Ignored,Configured"
bitfld.long 0x00 18. " [51] ,Message Valid Bit[51]" "Ignored,Configured"
bitfld.long 0x00 17. " [50] ,Message Valid Bit[50]" "Ignored,Configured"
bitfld.long 0x00 16. " [49] ,Message Valid Bit[49]" "Ignored,Configured"
textline " "
bitfld.long 0x00 15. " [48] ,Message Valid Bit[48]" "Ignored,Configured"
bitfld.long 0x00 14. " [47] ,Message Valid Bit[47]" "Ignored,Configured"
bitfld.long 0x00 13. " [46] ,Message Valid Bit[46]" "Ignored,Configured"
bitfld.long 0x00 12. " [45] ,Message Valid Bit[45]" "Ignored,Configured"
textline " "
bitfld.long 0x00 11. " [44] ,Message Valid Bit[44]" "Ignored,Configured"
bitfld.long 0x00 10. " [43] ,Message Valid Bit[43]" "Ignored,Configured"
bitfld.long 0x00 9. " [42] ,Message Valid Bit[42]" "Ignored,Configured"
bitfld.long 0x00 8. " [41] ,Message Valid Bit[41]" "Ignored,Configured"
textline " "
bitfld.long 0x00 7. " [40] ,Message Valid Bit[40]" "Ignored,Configured"
bitfld.long 0x00 6. " [39] ,Message Valid Bit[39]" "Ignored,Configured"
bitfld.long 0x00 5. " [38] ,Message Valid Bit[38]" "Ignored,Configured"
bitfld.long 0x00 4. " [37] ,Message Valid Bit[37]" "Ignored,Configured"
textline " "
bitfld.long 0x00 3. " [36] ,Message Valid Bit[36]" "Ignored,Configured"
bitfld.long 0x00 2. " [35] ,Message Valid Bit[35]" "Ignored,Configured"
bitfld.long 0x00 1. " [34] ,Message Valid Bit[34]" "Ignored,Configured"
bitfld.long 0x00 0. " [33] ,Message Valid Bit[33]" "Ignored,Configured"
rgroup.long 0xCC++0x3
line.long 0x0 "MVAL65,Message Valid 6_5"
bitfld.long 0x00 31. " MSGVAL [96] ,Message Valid Bit[96]" "Ignored,Configured"
bitfld.long 0x00 30. " [95] ,Message Valid Bit[95]" "Ignored,Configured"
bitfld.long 0x00 29. " [94] ,Message Valid Bit[94]" "Ignored,Configured"
bitfld.long 0x00 28. " [93] ,Message Valid Bit[93]" "Ignored,Configured"
textline " "
bitfld.long 0x00 27. " [92] ,Message Valid Bit[92]" "Ignored,Configured"
bitfld.long 0x00 26. " [91] ,Message Valid Bit[91]" "Ignored,Configured"
bitfld.long 0x00 25. " [90] ,Message Valid Bit[90]" "Ignored,Configured"
bitfld.long 0x00 24. " [89] ,Message Valid Bit[89]" "Ignored,Configured"
textline " "
bitfld.long 0x00 23. " [88] ,Message Valid Bit[88]" "Ignored,Configured"
bitfld.long 0x00 22. " [87] ,Message Valid Bit[87]" "Ignored,Configured"
bitfld.long 0x00 21. " [86] ,Message Valid Bit[86]" "Ignored,Configured"
bitfld.long 0x00 20. " [85] ,Message Valid Bit[85]" "Ignored,Configured"
textline " "
bitfld.long 0x00 19. " [84] ,Message Valid Bit[84]" "Ignored,Configured"
bitfld.long 0x00 18. " [83] ,Message Valid Bit[83]" "Ignored,Configured"
bitfld.long 0x00 17. " [82] ,Message Valid Bit[82]" "Ignored,Configured"
bitfld.long 0x00 16. " [81] ,Message Valid Bit[81]" "Ignored,Configured"
textline " "
bitfld.long 0x00 15. " [80] ,Message Valid Bit[80]" "Ignored,Configured"
bitfld.long 0x00 14. " [79] ,Message Valid Bit[79]" "Ignored,Configured"
bitfld.long 0x00 13. " [78] ,Message Valid Bit[78]" "Ignored,Configured"
bitfld.long 0x00 12. " [77] ,Message Valid Bit[77]" "Ignored,Configured"
textline " "
bitfld.long 0x00 11. " [76] ,Message Valid Bit[76]" "Ignored,Configured"
bitfld.long 0x00 10. " [75] ,Message Valid Bit[75]" "Ignored,Configured"
bitfld.long 0x00 9. " [74] ,Message Valid Bit[74]" "Ignored,Configured"
bitfld.long 0x00 8. " [73] ,Message Valid Bit[73]" "Ignored,Configured"
textline " "
bitfld.long 0x00 7. " [72] ,Message Valid Bit[72]" "Ignored,Configured"
bitfld.long 0x00 6. " [71] ,Message Valid Bit[71]" "Ignored,Configured"
bitfld.long 0x00 5. " [70] ,Message Valid Bit[70]" "Ignored,Configured"
bitfld.long 0x00 4. " [69] ,Message Valid Bit[69]" "Ignored,Configured"
textline " "
bitfld.long 0x00 3. " [68] ,Message Valid Bit[68]" "Ignored,Configured"
bitfld.long 0x00 2. " [67] ,Message Valid Bit[67]" "Ignored,Configured"
bitfld.long 0x00 1. " [66] ,Message Valid Bit[66]" "Ignored,Configured"
bitfld.long 0x00 0. " [65] ,Message Valid Bit[65]" "Ignored,Configured"
rgroup.long 0xD0++0x3
line.long 0x0 "MVAL87,Message Valid 8_7"
bitfld.long 0x00 31. " MSGVAL [128] ,Message Valid Bit[128]" "Ignored,Configured"
bitfld.long 0x00 30. " [127] ,Message Valid Bit[127]" "Ignored,Configured"
bitfld.long 0x00 29. " [126] ,Message Valid Bit[126]" "Ignored,Configured"
bitfld.long 0x00 28. " [125] ,Message Valid Bit[125]" "Ignored,Configured"
textline " "
bitfld.long 0x00 27. " [124] ,Message Valid Bit[124]" "Ignored,Configured"
bitfld.long 0x00 26. " [123] ,Message Valid Bit[123]" "Ignored,Configured"
bitfld.long 0x00 25. " [122] ,Message Valid Bit[122]" "Ignored,Configured"
bitfld.long 0x00 24. " [121] ,Message Valid Bit[121]" "Ignored,Configured"
textline " "
bitfld.long 0x00 23. " [120] ,Message Valid Bit[120]" "Ignored,Configured"
bitfld.long 0x00 22. " [119] ,Message Valid Bit[119]" "Ignored,Configured"
bitfld.long 0x00 21. " [118] ,Message Valid Bit[118]" "Ignored,Configured"
bitfld.long 0x00 20. " [117] ,Message Valid Bit[117]" "Ignored,Configured"
textline " "
bitfld.long 0x00 19. " [116] ,Message Valid Bit[116]" "Ignored,Configured"
bitfld.long 0x00 18. " [115] ,Message Valid Bit[115]" "Ignored,Configured"
bitfld.long 0x00 17. " [114] ,Message Valid Bit[114]" "Ignored,Configured"
bitfld.long 0x00 16. " [113] ,Message Valid Bit[113]" "Ignored,Configured"
textline " "
bitfld.long 0x00 15. " [112] ,Message Valid Bit[112]" "Ignored,Configured"
bitfld.long 0x00 14. " [111] ,Message Valid Bit[111]" "Ignored,Configured"
bitfld.long 0x00 13. " [110] ,Message Valid Bit[110]" "Ignored,Configured"
bitfld.long 0x00 12. " [109] ,Message Valid Bit[109]" "Ignored,Configured"
textline " "
bitfld.long 0x00 11. " [108] ,Message Valid Bit[108]" "Ignored,Configured"
bitfld.long 0x00 10. " [107] ,Message Valid Bit[107]" "Ignored,Configured"
bitfld.long 0x00 9. " [106] ,Message Valid Bit[106]" "Ignored,Configured"
bitfld.long 0x00 8. " [105] ,Message Valid Bit[105]" "Ignored,Configured"
textline " "
bitfld.long 0x00 7. " [104] ,Message Valid Bit[104]" "Ignored,Configured"
bitfld.long 0x00 6. " [103] ,Message Valid Bit[103]" "Ignored,Configured"
bitfld.long 0x00 5. " [102] ,Message Valid Bit[102]" "Ignored,Configured"
bitfld.long 0x00 4. " [101] ,Message Valid Bit[101]" "Ignored,Configured"
textline " "
bitfld.long 0x00 3. " [100] ,Message Valid Bit[100]" "Ignored,Configured"
bitfld.long 0x00 2. " [99] ,Message Valid Bit[99]" "Ignored,Configured"
bitfld.long 0x00 1. " [98] ,Message Valid Bit[98]" "Ignored,Configured"
bitfld.long 0x00 0. " [97] ,Message Valid Bit[97]" "Ignored,Configured"
width 12.
group.long 0xD8++0x3
line.long 0x0 "INTPMX21,IntPndMux 2_1"
bitfld.long 0x00 31. " INTPNDMUX [32] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[32]" "DCAN0INT,DCAN1INT"
bitfld.long 0x00 30. " [31] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[31]" "DCAN0INT,DCAN1INT"
bitfld.long 0x00 29. " [30] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[30]" "DCAN0INT,DCAN1INT"
bitfld.long 0x00 28. " [29] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[29]" "DCAN0INT,DCAN1INT"
textline " "
bitfld.long 0x00 27. " [28] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[28]" "DCAN0INT,DCAN1INT"
bitfld.long 0x00 26. " [27] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[27]" "DCAN0INT,DCAN1INT"
bitfld.long 0x00 25. " [26] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[26]" "DCAN0INT,DCAN1INT"
bitfld.long 0x00 24. " [25] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[25]" "DCAN0INT,DCAN1INT"
textline " "
bitfld.long 0x00 23. " [24] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[24]" "DCAN0INT,DCAN1INT"
bitfld.long 0x00 22. " [23] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[23]" "DCAN0INT,DCAN1INT"
bitfld.long 0x00 21. " [22] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[22]" "DCAN0INT,DCAN1INT"
bitfld.long 0x00 20. " [21] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[21]" "DCAN0INT,DCAN1INT"
textline " "
bitfld.long 0x00 19. " [20] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[20]" "DCAN0INT,DCAN1INT"
bitfld.long 0x00 18. " [19] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[19]" "DCAN0INT,DCAN1INT"
bitfld.long 0x00 17. " [18] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[18]" "DCAN0INT,DCAN1INT"
bitfld.long 0x00 16. " [17] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[17]" "DCAN0INT,DCAN1INT"
textline " "
bitfld.long 0x00 15. " [16] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[16]" "DCAN0INT,DCAN1INT"
bitfld.long 0x00 14. " [15] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[15]" "DCAN0INT,DCAN1INT"
bitfld.long 0x00 13. " [14] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[14]" "DCAN0INT,DCAN1INT"
bitfld.long 0x00 12. " [13] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[13]" "DCAN0INT,DCAN1INT"
textline " "
bitfld.long 0x00 11. " [12] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[12]" "DCAN0INT,DCAN1INT"
bitfld.long 0x00 10. " [11] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[11]" "DCAN0INT,DCAN1INT"
bitfld.long 0x00 9. " [10] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[10]" "DCAN0INT,DCAN1INT"
bitfld.long 0x00 8. " [9] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[9]" "DCAN0INT,DCAN1INT"
textline " "
bitfld.long 0x00 7. " [8] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[8]" "DCAN0INT,DCAN1INT"
bitfld.long 0x00 6. " [7] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[7]" "DCAN0INT,DCAN1INT"
bitfld.long 0x00 5. " [6] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[6]" "DCAN0INT,DCAN1INT"
bitfld.long 0x00 4. " [5] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[5]" "DCAN0INT,DCAN1INT"
textline " "
bitfld.long 0x00 3. " [4] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[4]" "DCAN0INT,DCAN1INT"
bitfld.long 0x00 2. " [3] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[3]" "DCAN0INT,DCAN1INT"
bitfld.long 0x00 1. " [2] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[2]" "DCAN0INT,DCAN1INT"
bitfld.long 0x00 0. " [1] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[1]" "DCAN0INT,DCAN1INT"
group.long 0xDC++0x3
line.long 0x0 "INTPMX43,IntPndMux 4_3"
bitfld.long 0x00 31. " INTPNDMUX [64] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[64]" "DCAN0INT,DCAN1INT"
bitfld.long 0x00 30. " [63] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[63]" "DCAN0INT,DCAN1INT"
bitfld.long 0x00 29. " [62] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[62]" "DCAN0INT,DCAN1INT"
bitfld.long 0x00 28. " [61] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[61]" "DCAN0INT,DCAN1INT"
textline " "
bitfld.long 0x00 27. " [60] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[60]" "DCAN0INT,DCAN1INT"
bitfld.long 0x00 26. " [59] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[59]" "DCAN0INT,DCAN1INT"
bitfld.long 0x00 25. " [58] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[58]" "DCAN0INT,DCAN1INT"
bitfld.long 0x00 24. " [57] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[57]" "DCAN0INT,DCAN1INT"
textline " "
bitfld.long 0x00 23. " [56] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[56]" "DCAN0INT,DCAN1INT"
bitfld.long 0x00 22. " [55] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[55]" "DCAN0INT,DCAN1INT"
bitfld.long 0x00 21. " [54] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[54]" "DCAN0INT,DCAN1INT"
bitfld.long 0x00 20. " [53] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[53]" "DCAN0INT,DCAN1INT"
textline " "
bitfld.long 0x00 19. " [52] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[52]" "DCAN0INT,DCAN1INT"
bitfld.long 0x00 18. " [51] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[51]" "DCAN0INT,DCAN1INT"
bitfld.long 0x00 17. " [50] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[50]" "DCAN0INT,DCAN1INT"
bitfld.long 0x00 16. " [49] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[49]" "DCAN0INT,DCAN1INT"
textline " "
bitfld.long 0x00 15. " [48] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[48]" "DCAN0INT,DCAN1INT"
bitfld.long 0x00 14. " [47] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[47]" "DCAN0INT,DCAN1INT"
bitfld.long 0x00 13. " [46] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[46]" "DCAN0INT,DCAN1INT"
bitfld.long 0x00 12. " [45] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[45]" "DCAN0INT,DCAN1INT"
textline " "
bitfld.long 0x00 11. " [44] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[44]" "DCAN0INT,DCAN1INT"
bitfld.long 0x00 10. " [43] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[43]" "DCAN0INT,DCAN1INT"
bitfld.long 0x00 9. " [42] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[42]" "DCAN0INT,DCAN1INT"
bitfld.long 0x00 8. " [41] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[41]" "DCAN0INT,DCAN1INT"
textline " "
bitfld.long 0x00 7. " [40] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[40]" "DCAN0INT,DCAN1INT"
bitfld.long 0x00 6. " [39] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[39]" "DCAN0INT,DCAN1INT"
bitfld.long 0x00 5. " [38] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[38]" "DCAN0INT,DCAN1INT"
bitfld.long 0x00 4. " [37] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[37]" "DCAN0INT,DCAN1INT"
textline " "
bitfld.long 0x00 3. " [36] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[36]" "DCAN0INT,DCAN1INT"
bitfld.long 0x00 2. " [35] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[35]" "DCAN0INT,DCAN1INT"
bitfld.long 0x00 1. " [34] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[34]" "DCAN0INT,DCAN1INT"
bitfld.long 0x00 0. " [33] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[33]" "DCAN0INT,DCAN1INT"
group.long 0xE0++0x3
line.long 0x0 "INTPMX65,IntPndMux 6_5"
bitfld.long 0x00 31. " INTPNDMUX [96] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[96]" "DCAN0INT,DCAN1INT"
bitfld.long 0x00 30. " [95] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[95]" "DCAN0INT,DCAN1INT"
bitfld.long 0x00 29. " [94] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[94]" "DCAN0INT,DCAN1INT"
bitfld.long 0x00 28. " [93] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[93]" "DCAN0INT,DCAN1INT"
textline " "
bitfld.long 0x00 27. " [92] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[92]" "DCAN0INT,DCAN1INT"
bitfld.long 0x00 26. " [91] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[91]" "DCAN0INT,DCAN1INT"
bitfld.long 0x00 25. " [90] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[90]" "DCAN0INT,DCAN1INT"
bitfld.long 0x00 24. " [89] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[89]" "DCAN0INT,DCAN1INT"
textline " "
bitfld.long 0x00 23. " [88] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[88]" "DCAN0INT,DCAN1INT"
bitfld.long 0x00 22. " [87] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[87]" "DCAN0INT,DCAN1INT"
bitfld.long 0x00 21. " [86] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[86]" "DCAN0INT,DCAN1INT"
bitfld.long 0x00 20. " [85] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[85]" "DCAN0INT,DCAN1INT"
textline " "
bitfld.long 0x00 19. " [84] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[84]" "DCAN0INT,DCAN1INT"
bitfld.long 0x00 18. " [83] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[83]" "DCAN0INT,DCAN1INT"
bitfld.long 0x00 17. " [82] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[82]" "DCAN0INT,DCAN1INT"
bitfld.long 0x00 16. " [81] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[81]" "DCAN0INT,DCAN1INT"
textline " "
bitfld.long 0x00 15. " [80] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[80]" "DCAN0INT,DCAN1INT"
bitfld.long 0x00 14. " [79] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[79]" "DCAN0INT,DCAN1INT"
bitfld.long 0x00 13. " [78] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[78]" "DCAN0INT,DCAN1INT"
bitfld.long 0x00 12. " [77] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[77]" "DCAN0INT,DCAN1INT"
textline " "
bitfld.long 0x00 11. " [76] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[76]" "DCAN0INT,DCAN1INT"
bitfld.long 0x00 10. " [75] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[75]" "DCAN0INT,DCAN1INT"
bitfld.long 0x00 9. " [74] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[74]" "DCAN0INT,DCAN1INT"
bitfld.long 0x00 8. " [73] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[73]" "DCAN0INT,DCAN1INT"
textline " "
bitfld.long 0x00 7. " [72] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[72]" "DCAN0INT,DCAN1INT"
bitfld.long 0x00 6. " [71] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[71]" "DCAN0INT,DCAN1INT"
bitfld.long 0x00 5. " [70] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[70]" "DCAN0INT,DCAN1INT"
bitfld.long 0x00 4. " [69] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[69]" "DCAN0INT,DCAN1INT"
textline " "
bitfld.long 0x00 3. " [68] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[68]" "DCAN0INT,DCAN1INT"
bitfld.long 0x00 2. " [67] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[67]" "DCAN0INT,DCAN1INT"
bitfld.long 0x00 1. " [66] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[66]" "DCAN0INT,DCAN1INT"
bitfld.long 0x00 0. " [65] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[65]" "DCAN0INT,DCAN1INT"
group.long 0xE4++0x3
line.long 0x0 "INTPMX87,IntPndMux 8_7"
bitfld.long 0x00 31. " INTPNDMUX [128] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[128]" "DCAN0INT,DCAN1INT"
bitfld.long 0x00 30. " [127] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[127]" "DCAN0INT,DCAN1INT"
bitfld.long 0x00 29. " [126] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[126]" "DCAN0INT,DCAN1INT"
bitfld.long 0x00 28. " [125] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[125]" "DCAN0INT,DCAN1INT"
textline " "
bitfld.long 0x00 27. " [124] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[124]" "DCAN0INT,DCAN1INT"
bitfld.long 0x00 26. " [123] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[123]" "DCAN0INT,DCAN1INT"
bitfld.long 0x00 25. " [122] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[122]" "DCAN0INT,DCAN1INT"
bitfld.long 0x00 24. " [121] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[121]" "DCAN0INT,DCAN1INT"
textline " "
bitfld.long 0x00 23. " [120] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[120]" "DCAN0INT,DCAN1INT"
bitfld.long 0x00 22. " [119] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[119]" "DCAN0INT,DCAN1INT"
bitfld.long 0x00 21. " [118] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[118]" "DCAN0INT,DCAN1INT"
bitfld.long 0x00 20. " [117] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[117]" "DCAN0INT,DCAN1INT"
textline " "
bitfld.long 0x00 19. " [116] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[116]" "DCAN0INT,DCAN1INT"
bitfld.long 0x00 18. " [115] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[115]" "DCAN0INT,DCAN1INT"
bitfld.long 0x00 17. " [114] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[114]" "DCAN0INT,DCAN1INT"
bitfld.long 0x00 16. " [113] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[113]" "DCAN0INT,DCAN1INT"
textline " "
bitfld.long 0x00 15. " [112] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[112]" "DCAN0INT,DCAN1INT"
bitfld.long 0x00 14. " [111] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[111]" "DCAN0INT,DCAN1INT"
bitfld.long 0x00 13. " [110] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[110]" "DCAN0INT,DCAN1INT"
bitfld.long 0x00 12. " [109] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[109]" "DCAN0INT,DCAN1INT"
textline " "
bitfld.long 0x00 11. " [108] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[108]" "DCAN0INT,DCAN1INT"
bitfld.long 0x00 10. " [107] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[107]" "DCAN0INT,DCAN1INT"
bitfld.long 0x00 9. " [106] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[106]" "DCAN0INT,DCAN1INT"
bitfld.long 0x00 8. " [105] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[105]" "DCAN0INT,DCAN1INT"
textline " "
bitfld.long 0x00 7. " [104] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[104]" "DCAN0INT,DCAN1INT"
bitfld.long 0x00 6. " [103] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[103]" "DCAN0INT,DCAN1INT"
bitfld.long 0x00 5. " [102] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[102]" "DCAN0INT,DCAN1INT"
bitfld.long 0x00 4. " [101] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[101]" "DCAN0INT,DCAN1INT"
textline " "
bitfld.long 0x00 3. " [100] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[100]" "DCAN0INT,DCAN1INT"
bitfld.long 0x00 2. " [99] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[99]" "DCAN0INT,DCAN1INT"
bitfld.long 0x00 1. " [98] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[98]" "DCAN0INT,DCAN1INT"
bitfld.long 0x00 0. " [97] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[97]" "DCAN0INT,DCAN1INT"
width 12.
group.long 0x100++0x3
line.long 0x0 "IF1COM,IF1 Command Mask / Command Request Register"
bitfld.long 0x00 23. " WR/RD ,Write / Read" "Read,Write"
textline " "
width 12.
bitfld.long 0x00 22. " MASK ,Access Mask Bits" "Unchanged,Identifier Mask+MDir+MXtd"
textline " "
bitfld.long 0x00 21. " ARB ,Access Arbitration Bits" "Unchanged,Identifier+Dir+Xtd+MSGVAl"
textline " "
width 12.
bitfld.long 0x00 20. " CONTROL ,Access Control Bits" "Unchanged,Control bits"
bitfld.long 0x00 19. " CLRINTPND ,Clear Interrupt Pending Bit" "Low,High"
textline " "
bitfld.long 0x00 18. " TXRQST/NEWDAT ,Access Transmission Request Bit" "Not requested,Requested"
bitfld.long 0x00 17. " DATA_A ,Access Data Bytes 0-3" "Unchanged,Data bytes 0-3"
textline " "
bitfld.long 0x00 16. " DATA_B ,Access Data Bytes 4-7" "Unchanged,Data bytes 4-7"
bitfld.long 0x00 15. " BUSY ,Busy Flag" "Reset,Set"
textline " "
bitfld.long 0x00 14. " DMAACTIVE ,Activation of DMA Feature for Subsequent Internal IF1 Update" "No active,Active"
hexmask.long.byte 0x00 0.--7. 1. " MESSAGE_NUMBER ,Message Number"
width 12.
if (((d.l((ad:0xFFF7DC00+0x108)))&0x40000000)==0x00000000)
group.long 0x104++0x3
line.long 0x0 "IF1MASK,IF1 Mask Register"
bitfld.long 0x00 31. " MXTD ,Mask Extended Identifier" "No effect,Filtering"
bitfld.long 0x00 30. " MDIR ,Mask Message Direction" "No effect,Filtering"
textline " "
bitfld.long 0x00 28. " ID ,Message Identifier bit[28]" "0,1"
bitfld.long 0x00 27. ",Message Identifier bit[27]" "0,1"
bitfld.long 0x00 26. ",Message Identifier bit[26]" "0,1"
bitfld.long 0x00 25. ",Message Identifier bit[25]" "0,1"
bitfld.long 0x00 24. ",Message Identifier bit[24]" "0,1"
bitfld.long 0x00 23. ",Message Identifier bit[23]" "0,1"
bitfld.long 0x00 22. ",Message Identifier bit[22]" "0,1"
bitfld.long 0x00 21. ",Message Identifier bit[21]" "0,1"
bitfld.long 0x00 20. ",Message Identifier bit[20]" "0,1"
bitfld.long 0x00 19. ",Message Identifier bit[19]" "0,1"
bitfld.long 0x00 18. ",Message Identifier bit[18]" "0,1"
else
group.long 0x104++0x3
line.long 0x0 "IF1MASK,IF1 Mask Register"
bitfld.long 0x00 31. " MXTD ,Mask Extended Identifier" "No effect,Filtering"
bitfld.long 0x00 30. " MDIR ,Mask Message Direction" "No effect,Filtering"
textline " "
bitfld.long 0x00 28. " ID ,Message Identifier bit[28]" "0,1"
bitfld.long 0x00 27. ",Message Identifier bit[27]" "0,1"
bitfld.long 0x00 26. ",Message Identifier bit[26]" "0,1"
bitfld.long 0x00 25. ",Message Identifier bit[25]" "0,1"
bitfld.long 0x00 24. ",Message Identifier bit[24]" "0,1"
bitfld.long 0x00 23. ",Message Identifier bit[23]" "0,1"
bitfld.long 0x00 22. ",Message Identifier bit[22]" "0,1"
bitfld.long 0x00 21. ",Message Identifier bit[21]" "0,1"
bitfld.long 0x00 20. ",Message Identifier bit[20]" "0,1"
bitfld.long 0x00 19. ",Message Identifier bit[19]" "0,1"
bitfld.long 0x00 18. ",Message Identifier bit[18]" "0,1"
bitfld.long 0x00 17. ",Message Identifier bit[17]" "0,1"
bitfld.long 0x00 16. ",Message Identifier bit[16]" "0,1"
bitfld.long 0x00 15. ",Message Identifier bit[15]" "0,1"
bitfld.long 0x00 14. ",Message Identifier bit[14]" "0,1"
bitfld.long 0x00 13. ",Message Identifier bit[13]" "0,1"
bitfld.long 0x00 12. ",Message Identifier bit[12]" "0,1"
bitfld.long 0x00 11. ",Message Identifier bit[11]" "0,1"
bitfld.long 0x00 10. ",Message Identifier bit[10]" "0,1"
bitfld.long 0x00 9. ",Message Identifier bit[9]" "0,1"
bitfld.long 0x00 8. ",Message Identifier bit[8]" "0,1"
bitfld.long 0x00 7. ",Message Identifier bit[7]" "0,1"
bitfld.long 0x00 6. ",Message Identifier bit[6]" "0,1"
bitfld.long 0x00 5. ",Message Identifier bit[5]" "0,1"
bitfld.long 0x00 4. ",Message Identifier bit[4]" "0,1"
bitfld.long 0x00 3. ",Message Identifier bit[3]" "0,1"
bitfld.long 0x00 2. ",Message Identifier bit[2]" "0,1"
bitfld.long 0x00 1. ",Message Identifier bit[1]" "0,1"
bitfld.long 0x00 0. ",Message Identifier bit[0]" "0,1"
endif
width 12.
group.long 0x108++0x3
line.long 0x0 "IF1ARB,IF1 Arbitation Register"
bitfld.long 0x00 31. " MSGVAL ,Message Valid" "Ignore,Configure"
bitfld.long 0x00 30. " XTD ,Extended Identifier" "11-bit,29-bit"
bitfld.long 0x00 29. " DIR ,Message Direction" "Receive,Transmit"
hexmask.long 0x00 0.--28. 1. " ID28-0 ,Message Identifier"
width 12.
group.long 0x10C++0x3
line.long 0x0 "IF1MCTRL,IF1 Message Control Register"
bitfld.long 0x00 15. " NEWDAT ,New Data" "No new data,New data"
bitfld.long 0x00 14. " MSGLST ,Message Lost" "Not lost,Lost"
bitfld.long 0x00 13. " INTPND ,Interrupt Pending" "No interrupt,Interrupt"
textline " "
bitfld.long 0x00 12. " UMASK ,Use Acceptance Mask" "Ignored,Masked"
bitfld.long 0x00 11. " TXIE ,Transmit Interrupt Enable" "Unchanged,Set"
bitfld.long 0x00 10. " RXIE ,Receive Interrupt Enable" "Unchanged,Set"
textline " "
bitfld.long 0x00 9. " RMTEN ,Remote Enable" "Disabled,Enabled"
bitfld.long 0x00 8. " TXRQST ,Transmit Request" "Not requested,Requested"
bitfld.long 0x00 7. " EOB ,End of Block" "Single/Last,Not last"
textline " "
bitfld.long 0x00 0.--3. " DLC[3-0] ,Data Length Code" "0 byte,1 bytes,2 bytes,3 bytes,4 bytes,5 bytes,6 bytes,7 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes"
width 12.
group.long 0x110++0x3
line.long 0x0 "IF1DATA,IF1 Data A Register"
hexmask.long.byte 0x00 24.--31. 1. " DATA [3] ,4th data byte of a CAN Data Frame"
hexmask.long.byte 0x00 16.--23. 1. " [2] ,3rd data byte of a CAN Data Frame"
hexmask.long.byte 0x00 8.--15. 1. " [1] ,2nd data byte of a CAN Data Frame"
hexmask.long.byte 0x00 0.--7. 1. " [0] ,1st data byte of a CAN Data Frame"
group.long 0x114++0x3
line.long 0x0 "IF1DATB,IF1 Data B Register"
hexmask.long.byte 0x00 24.--31. 1. " DATA [7] ,8th data byte of a CAN Data Frame"
hexmask.long.byte 0x00 16.--23. 1. " [6] ,7th data byte of a CAN Data Frame"
hexmask.long.byte 0x00 8.--15. 1. " [5] ,6th data byte of a CAN Data Frame"
hexmask.long.byte 0x00 0.--7. 1. " [4] ,5th data byte of a CAN Data Frame"
width 12.
group.long 0x120++0x3
line.long 0x0 "IF2COM,IF2 Command Mask / Command Request Register"
bitfld.long 0x00 23. " WR/RD ,Write / Read" "Read,Write"
textline " "
width 12.
bitfld.long 0x00 22. " MASK ,Access Mask Bits" "Unchanged,Identifier Mask+MDir+MXtd"
textline " "
bitfld.long 0x00 21. " ARB ,Access Arbitration Bits" "Unchanged,Identifier+Dir+Xtd+MSGVAl"
textline " "
width 12.
bitfld.long 0x00 20. " CONTROL ,Access Control Bits" "Unchanged,Control bits"
bitfld.long 0x00 19. " CLRINTPND ,Clear Interrupt Pending Bit" "Low,High"
textline " "
bitfld.long 0x00 18. " TXRQST/NEWDAT ,Access Transmission Request Bit" "Not requested,Requested"
bitfld.long 0x00 17. " DATA_A ,Access Data Bytes 0-3" "Unchanged,Data bytes 0-3"
textline " "
bitfld.long 0x00 16. " DATA_B ,Access Data Bytes 4-7" "Unchanged,Data bytes 4-7"
bitfld.long 0x00 15. " BUSY ,Busy Flag" "Reset,Set"
textline " "
bitfld.long 0x00 14. " DMAACTIVE ,Activation of DMA Feature for Subsequent Internal IF1 Update" "No active,Active"
hexmask.long.byte 0x00 0.--7. 1. " MESSAGE_NUMBER ,Message Number"
width 12.
if (((d.l((ad:0xFFF7DC00+0x128)))&0x40000000)==0x00000000)
group.long 0x124++0x3
line.long 0x0 "IF2MASK,IF2 Mask Register"
bitfld.long 0x00 31. " MXTD ,Mask Extended Identifier" "No effect,Filtering"
bitfld.long 0x00 30. " MDIR ,Mask Message Direction" "No effect,Filtering"
textline " "
bitfld.long 0x00 28. " ID ,Message Identifier bit[28]" "0,1"
bitfld.long 0x00 27. ",Message Identifier bit[27]" "0,1"
bitfld.long 0x00 26. ",Message Identifier bit[26]" "0,1"
bitfld.long 0x00 25. ",Message Identifier bit[25]" "0,1"
bitfld.long 0x00 24. ",Message Identifier bit[24]" "0,1"
bitfld.long 0x00 23. ",Message Identifier bit[23]" "0,1"
bitfld.long 0x00 22. ",Message Identifier bit[22]" "0,1"
bitfld.long 0x00 21. ",Message Identifier bit[21]" "0,1"
bitfld.long 0x00 20. ",Message Identifier bit[20]" "0,1"
bitfld.long 0x00 19. ",Message Identifier bit[19]" "0,1"
bitfld.long 0x00 18. ",Message Identifier bit[18]" "0,1"
else
group.long 0x124++0x3
line.long 0x0 "IF2MASK,IF2 Mask Register"
bitfld.long 0x00 31. " MXTD ,Mask Extended Identifier" "No effect,Filtering"
bitfld.long 0x00 30. " MDIR ,Mask Message Direction" "No effect,Filtering"
textline " "
bitfld.long 0x00 28. " ID ,Message Identifier bit[28]" "0,1"
bitfld.long 0x00 27. ",Message Identifier bit[27]" "0,1"
bitfld.long 0x00 26. ",Message Identifier bit[26]" "0,1"
bitfld.long 0x00 25. ",Message Identifier bit[25]" "0,1"
bitfld.long 0x00 24. ",Message Identifier bit[24]" "0,1"
bitfld.long 0x00 23. ",Message Identifier bit[23]" "0,1"
bitfld.long 0x00 22. ",Message Identifier bit[22]" "0,1"
bitfld.long 0x00 21. ",Message Identifier bit[21]" "0,1"
bitfld.long 0x00 20. ",Message Identifier bit[20]" "0,1"
bitfld.long 0x00 19. ",Message Identifier bit[19]" "0,1"
bitfld.long 0x00 18. ",Message Identifier bit[18]" "0,1"
bitfld.long 0x00 17. ",Message Identifier bit[17]" "0,1"
bitfld.long 0x00 16. ",Message Identifier bit[16]" "0,1"
bitfld.long 0x00 15. ",Message Identifier bit[15]" "0,1"
bitfld.long 0x00 14. ",Message Identifier bit[14]" "0,1"
bitfld.long 0x00 13. ",Message Identifier bit[13]" "0,1"
bitfld.long 0x00 12. ",Message Identifier bit[12]" "0,1"
bitfld.long 0x00 11. ",Message Identifier bit[11]" "0,1"
bitfld.long 0x00 10. ",Message Identifier bit[10]" "0,1"
bitfld.long 0x00 9. ",Message Identifier bit[9]" "0,1"
bitfld.long 0x00 8. ",Message Identifier bit[8]" "0,1"
bitfld.long 0x00 7. ",Message Identifier bit[7]" "0,1"
bitfld.long 0x00 6. ",Message Identifier bit[6]" "0,1"
bitfld.long 0x00 5. ",Message Identifier bit[5]" "0,1"
bitfld.long 0x00 4. ",Message Identifier bit[4]" "0,1"
bitfld.long 0x00 3. ",Message Identifier bit[3]" "0,1"
bitfld.long 0x00 2. ",Message Identifier bit[2]" "0,1"
bitfld.long 0x00 1. ",Message Identifier bit[1]" "0,1"
bitfld.long 0x00 0. ",Message Identifier bit[0]" "0,1"
endif
width 12.
group.long 0x128++0x3
line.long 0x0 "IF2ARB,IF2 Arbitation Register"
bitfld.long 0x00 31. " MSGVAL ,Message Valid" "Ignore,Configure"
bitfld.long 0x00 30. " XTD ,Extended Identifier" "11-bit,29-bit"
bitfld.long 0x00 29. " DIR ,Message Direction" "Receive,Transmit"
hexmask.long 0x00 0.--28. 1. " ID28-0 ,Message Identifier"
width 12.
group.long 0x12C++0x3
line.long 0x0 "IF2MCTRL,IF2 Message Control Register"
bitfld.long 0x00 15. " NEWDAT ,New Data" "No new data,New data"
bitfld.long 0x00 14. " MSGLST ,Message Lost" "Not lost,Lost"
bitfld.long 0x00 13. " INTPND ,Interrupt Pending" "No interrupt,Interrupt"
textline " "
bitfld.long 0x00 12. " UMASK ,Use Acceptance Mask" "Ignored,Masked"
bitfld.long 0x00 11. " TXIE ,Transmit Interrupt Enable" "Unchanged,Set"
bitfld.long 0x00 10. " RXIE ,Receive Interrupt Enable" "Unchanged,Set"
textline " "
bitfld.long 0x00 9. " RMTEN ,Remote Enable" "Disabled,Enabled"
bitfld.long 0x00 8. " TXRQST ,Transmit Request" "Not requested,Requested"
bitfld.long 0x00 7. " EOB ,End of Block" "Single/Last,Not last"
textline " "
bitfld.long 0x00 0.--3. " DLC[3-0] ,Data Length Code" "0 byte,1 bytes,2 bytes,3 bytes,4 bytes,5 bytes,6 bytes,7 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes"
width 12.
group.long 0x130++0x3
line.long 0x0 "IF2DATA,IF2 Data A Register"
hexmask.long.byte 0x00 24.--31. 1. " DATA [3] ,4th data byte of a CAN Data Frame"
hexmask.long.byte 0x00 16.--23. 1. " [2] ,3rd data byte of a CAN Data Frame"
hexmask.long.byte 0x00 8.--15. 1. " [1] ,2nd data byte of a CAN Data Frame"
hexmask.long.byte 0x00 0.--7. 1. " [0] ,1st data byte of a CAN Data Frame"
group.long 0x134++0x3
line.long 0x0 "IF2DATB,IF2 Data B Register"
hexmask.long.byte 0x00 24.--31. 1. " DATA [7] ,8th data byte of a CAN Data Frame"
hexmask.long.byte 0x00 16.--23. 1. " [6] ,7th data byte of a CAN Data Frame"
hexmask.long.byte 0x00 8.--15. 1. " [5] ,6th data byte of a CAN Data Frame"
hexmask.long.byte 0x00 0.--7. 1. " [4] ,5th data byte of a CAN Data Frame"
width 12.
group.long 0x140++0x3
line.long 0x0 "IF3OB,IF3 Observation Register"
bitfld.long 0x00 15. " IF3UPD ,IF3 Updata Data" "Not loaded,Loaded"
bitfld.long 0x00 12. " IF3SDB ,IF3 Status of Data B Read Access" "Low,High"
bitfld.long 0x00 11. " IF3SDA ,IF3 Status of Data A Read Access" "Low,High"
textline " "
bitfld.long 0x00 10. " IF3SC ,IF3 Status of Control Bits Read Access" "Low,High"
bitfld.long 0x00 9. " IF3SA ,IF3 Status of Arbitration Data Read Access" "Low,High"
bitfld.long 0x00 8. " IF3SM ,IF3 Status of Mask Data Read Access" "Low,High"
textline " "
bitfld.long 0x00 4. " DATA_B ,Data B Read Observation" "Not read,Read"
bitfld.long 0x00 3. " DATA_A ,Data A Read Observation" "Not read,Read"
bitfld.long 0x00 2. " CTRL ,Ctrl Read Observation" "Not read,Read"
textline " "
bitfld.long 0x00 1. " ARB ,Arbitration Data Read Observation" "Not read,Read"
bitfld.long 0x00 0. " MASK ,Mask Data Read Observation" "Not read,Read"
if (((d.l((ad:0xFFF7DC00+0x148)))&0x40000000)==0x00000000)
rgroup.long 0x144++0x3
line.long 0x0 "IF3MASK,IF3 Mask Register"
bitfld.long 0x00 31. " MXTD ,Mask Extended Identifier" "No effect,Filtering"
bitfld.long 0x00 30. " MDIR ,Mask Message Direction" "No effect,Filtering"
textline " "
bitfld.long 0x00 28. " ID ,Message Identifier bit[28]" "0,1"
bitfld.long 0x00 27. ",Message Identifier bit[27]" "0,1"
bitfld.long 0x00 26. ",Message Identifier bit[26]" "0,1"
bitfld.long 0x00 25. ",Message Identifier bit[25]" "0,1"
bitfld.long 0x00 24. ",Message Identifier bit[24]" "0,1"
bitfld.long 0x00 23. ",Message Identifier bit[23]" "0,1"
bitfld.long 0x00 22. ",Message Identifier bit[22]" "0,1"
bitfld.long 0x00 21. ",Message Identifier bit[21]" "0,1"
bitfld.long 0x00 20. ",Message Identifier bit[20]" "0,1"
bitfld.long 0x00 19. ",Message Identifier bit[19]" "0,1"
bitfld.long 0x00 18. ",Message Identifier bit[18]" "0,1"
else
group.long 0x144++0x3
line.long 0x0 "IF3MASK,IF3 Mask Register"
bitfld.long 0x00 31. " MXTD ,Mask Extended Identifier" "No effect,Filtering"
bitfld.long 0x00 30. " MDIR ,Mask Message Direction" "No effect,Filtering"
textline " "
bitfld.long 0x00 28. " ID ,Message Identifier bit[28]" "0,1"
bitfld.long 0x00 27. ",Message Identifier bit[27]" "0,1"
bitfld.long 0x00 26. ",Message Identifier bit[26]" "0,1"
bitfld.long 0x00 25. ",Message Identifier bit[25]" "0,1"
bitfld.long 0x00 24. ",Message Identifier bit[24]" "0,1"
bitfld.long 0x00 23. ",Message Identifier bit[23]" "0,1"
bitfld.long 0x00 22. ",Message Identifier bit[22]" "0,1"
bitfld.long 0x00 21. ",Message Identifier bit[21]" "0,1"
bitfld.long 0x00 20. ",Message Identifier bit[20]" "0,1"
bitfld.long 0x00 19. ",Message Identifier bit[19]" "0,1"
bitfld.long 0x00 18. ",Message Identifier bit[18]" "0,1"
bitfld.long 0x00 17. ",Message Identifier bit[17]" "0,1"
bitfld.long 0x00 16. ",Message Identifier bit[16]" "0,1"
bitfld.long 0x00 15. ",Message Identifier bit[15]" "0,1"
bitfld.long 0x00 14. ",Message Identifier bit[14]" "0,1"
bitfld.long 0x00 13. ",Message Identifier bit[13]" "0,1"
bitfld.long 0x00 12. ",Message Identifier bit[12]" "0,1"
bitfld.long 0x00 11. ",Message Identifier bit[11]" "0,1"
bitfld.long 0x00 10. ",Message Identifier bit[10]" "0,1"
bitfld.long 0x00 9. ",Message Identifier bit[9]" "0,1"
bitfld.long 0x00 8. ",Message Identifier bit[8]" "0,1"
bitfld.long 0x00 7. ",Message Identifier bit[7]" "0,1"
bitfld.long 0x00 6. ",Message Identifier bit[6]" "0,1"
bitfld.long 0x00 5. ",Message Identifier bit[5]" "0,1"
bitfld.long 0x00 4. ",Message Identifier bit[4]" "0,1"
bitfld.long 0x00 3. ",Message Identifier bit[3]" "0,1"
bitfld.long 0x00 2. ",Message Identifier bit[2]" "0,1"
bitfld.long 0x00 1. ",Message Identifier bit[1]" "0,1"
bitfld.long 0x00 0. ",Message Identifier bit[0]" "0,1"
endif
group.long 0x148++0x3
line.long 0x0 "IF3ARB,IF3 Arbitation Register"
bitfld.long 0x00 31. " MSGVAL ,Message Valid" "Ignored,Configured"
bitfld.long 0x00 30. " XTD ,Extended Identifier" "11-bit,29-bit"
bitfld.long 0x00 29. " DIR ,Message Direction" "Receive,Transmit"
textline " "
hexmask.long 0x00 0.--28. 1. " ID[28-0] ,Message Identifier"
group.long 0x14C++0x3
line.long 0x0 "IF3MCTRL,IF3 Message Control Register"
bitfld.long 0x00 15. " NEWDAT ,New Data" "No new data,New data"
bitfld.long 0x00 14. " MSGLST ,Message Lost" "Not lost,Lost"
bitfld.long 0x00 13. " INTPND ,Interrupt Pending" "No interrupt,Interrupt"
textline " "
bitfld.long 0x00 12. " UMASK ,Use Acceptance Mask" "Ignored,Masked"
bitfld.long 0x00 11. " TXIE ,Transmit Interrupt Enable" "Unchanged,Enabled"
bitfld.long 0x00 10. " RXIE ,Receive Interrupt Enable" "Unchanged,Enabled"
textline " "
bitfld.long 0x00 9. " RMTEN ,Remote Enable" "Unchanged,Enabled"
bitfld.long 0x00 8. " TXRQST ,Transmit Request" "Not requested,Requested"
bitfld.long 0x00 7. " EOB ,End of Block" "Not last,Single/Last"
textline " "
bitfld.long 0x00 0.--3. " DLC[3-0] ,Data Length Code" "0 byte,1 byte,2 bytes,3 bytes,4 bytes,5 bytes,6 bytes,7 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes"
width 12.
group.long 0x150++0x3
line.long 0x0 "IF3DATA,IF3 Data A Register"
hexmask.long.byte 0x00 24.--31. 1. " DATA [3] ,4th data byte of a CAN Data Frame"
hexmask.long.byte 0x00 16.--23. 1. " [2] ,3rd data byte of a CAN Data Frame"
hexmask.long.byte 0x00 8.--15. 1. " [1] ,2nd data byte of a CAN Data Frame"
hexmask.long.byte 0x00 0.--7. 1. " [0] ,1st data byte of a CAN Data Frame"
group.long 0x154++0x3
line.long 0x0 "IF3DATB,IF3 Data B Register"
hexmask.long.byte 0x00 24.--31. 1. " DATA [7] ,8th data byte of a CAN Data Frame"
hexmask.long.byte 0x00 16.--23. 1. " [6] ,7th data byte of a CAN Data Frame"
hexmask.long.byte 0x00 8.--15. 1. " [5] ,6th data byte of a CAN Data Frame"
hexmask.long.byte 0x00 0.--7. 1. " ATA [4] ,5th data byte of a CAN Data Frame"
width 12.
group.long 0x160++0x3
line.long 0x0 "IF3UENA2_1,Update Enable 2_1 Register"
bitfld.long 0x00 31. " IF3UPDATEEN [32] ,IF3 Update Enabled Bit[32]" "Disabled,Enabled"
bitfld.long 0x00 30. " [31] ,IF3 Update Enabled Bit[31]" "Disabled,Enabled"
bitfld.long 0x00 29. " [30] ,IF3 Update Enabled Bit[30]" "Disabled,Enabled"
bitfld.long 0x00 28. " [29] ,IF3 Update Enabled Bit[29]" "Disabled,Enabled"
textline " "
bitfld.long 0x00 27. " [28] ,IF3 Update Enabled Bit[28]" "Disabled,Enabled"
bitfld.long 0x00 26. " [27] ,IF3 Update Enabled Bit[27]" "Disabled,Enabled"
bitfld.long 0x00 25. " [26] ,IF3 Update Enabled Bit[26]" "Disabled,Enabled"
bitfld.long 0x00 24. " [25] ,IF3 Update Enabled Bit[25]" "Disabled,Enabled"
textline " "
bitfld.long 0x00 23. " [24] ,IF3 Update Enabled Bit[24]" "Disabled,Enabled"
bitfld.long 0x00 22. " [23] ,IF3 Update Enabled Bit[23]" "Disabled,Enabled"
bitfld.long 0x00 21. " [22] ,IF3 Update Enabled Bit[22]" "Disabled,Enabled"
bitfld.long 0x00 20. " [21] ,IF3 Update Enabled Bit[21]" "Disabled,Enabled"
textline " "
bitfld.long 0x00 19. " [20] ,IF3 Update Enabled Bit[20]" "Disabled,Enabled"
bitfld.long 0x00 18. " [19] ,IF3 Update Enabled Bit[19]" "Disabled,Enabled"
bitfld.long 0x00 17. " [18] ,IF3 Update Enabled Bit[18]" "Disabled,Enabled"
bitfld.long 0x00 16. " [17] ,IF3 Update Enabled Bit[17]" "Disabled,Enabled"
textline " "
bitfld.long 0x00 15. " [16] ,IF3 Update Enabled Bit[16]" "Disabled,Enabled"
bitfld.long 0x00 14. " [15] ,IF3 Update Enabled Bit[15]" "Disabled,Enabled"
bitfld.long 0x00 13. " [14] ,IF3 Update Enabled Bit[14]" "Disabled,Enabled"
bitfld.long 0x00 12. " [13] ,IF3 Update Enabled Bit[13]" "Disabled,Enabled"
textline " "
bitfld.long 0x00 11. " [12] ,IF3 Update Enabled Bit[12]" "Disabled,Enabled"
bitfld.long 0x00 10. " [11] ,IF3 Update Enabled Bit[11]" "Disabled,Enabled"
bitfld.long 0x00 9. " [10] ,IF3 Update Enabled Bit[10]" "Disabled,Enabled"
bitfld.long 0x00 8. " [9] ,IF3 Update Enabled Bit[9]" "Disabled,Enabled"
textline " "
bitfld.long 0x00 7. " [8] ,IF3 Update Enabled Bit[8]" "Disabled,Enabled"
bitfld.long 0x00 6. " [7] ,IF3 Update Enabled Bit[7]" "Disabled,Enabled"
bitfld.long 0x00 5. " [6] ,IF3 Update Enabled Bit[6]" "Disabled,Enabled"
bitfld.long 0x00 4. " [5] ,IF3 Update Enabled Bit[5]" "Disabled,Enabled"
textline " "
bitfld.long 0x00 3. " [4] ,IF3 Update Enabled Bit[4]" "Disabled,Enabled"
bitfld.long 0x00 2. " [3] ,IF3 Update Enabled Bit[3]" "Disabled,Enabled"
bitfld.long 0x00 1. " [2] ,IF3 Update Enabled Bit[2]" "Disabled,Enabled"
bitfld.long 0x00 0. " [1] ,IF3 Update Enabled Bit[1]" "Disabled,Enabled"
group.long 0x164++0x3
line.long 0x0 "IF3UENA4_3,Update Enable 4_3 Register"
bitfld.long 0x00 31. " IF3UPDATEEN [64] ,IF3 Update Enabled Bit[64]" "Disabled,Enabled"
bitfld.long 0x00 30. " [63] ,IF3 Update Enabled Bit[63]" "Disabled,Enabled"
bitfld.long 0x00 29. " [62] ,IF3 Update Enabled Bit[62]" "Disabled,Enabled"
bitfld.long 0x00 28. " [61] ,IF3 Update Enabled Bit[61]" "Disabled,Enabled"
textline " "
bitfld.long 0x00 27. " [60] ,IF3 Update Enabled Bit[60]" "Disabled,Enabled"
bitfld.long 0x00 26. " [59] ,IF3 Update Enabled Bit[59]" "Disabled,Enabled"
bitfld.long 0x00 25. " [58] ,IF3 Update Enabled Bit[58]" "Disabled,Enabled"
bitfld.long 0x00 24. " [57] ,IF3 Update Enabled Bit[57]" "Disabled,Enabled"
textline " "
bitfld.long 0x00 23. " [56] ,IF3 Update Enabled Bit[56]" "Disabled,Enabled"
bitfld.long 0x00 22. " [55] ,IF3 Update Enabled Bit[55]" "Disabled,Enabled"
bitfld.long 0x00 21. " [54] ,IF3 Update Enabled Bit[54]" "Disabled,Enabled"
bitfld.long 0x00 20. " [53] ,IF3 Update Enabled Bit[53]" "Disabled,Enabled"
textline " "
bitfld.long 0x00 19. " [52] ,IF3 Update Enabled Bit[52]" "Disabled,Enabled"
bitfld.long 0x00 18. " [51] ,IF3 Update Enabled Bit[51]" "Disabled,Enabled"
bitfld.long 0x00 17. " [50] ,IF3 Update Enabled Bit[50]" "Disabled,Enabled"
bitfld.long 0x00 16. " [49] ,IF3 Update Enabled Bit[49]" "Disabled,Enabled"
textline " "
bitfld.long 0x00 15. " [48] ,IF3 Update Enabled Bit[48]" "Disabled,Enabled"
bitfld.long 0x00 14. " [47] ,IF3 Update Enabled Bit[47]" "Disabled,Enabled"
bitfld.long 0x00 13. " [46] ,IF3 Update Enabled Bit[46]" "Disabled,Enabled"
bitfld.long 0x00 12. " [45] ,IF3 Update Enabled Bit[45]" "Disabled,Enabled"
textline " "
bitfld.long 0x00 11. " [44] ,IF3 Update Enabled Bit[44]" "Disabled,Enabled"
bitfld.long 0x00 10. " [43] ,IF3 Update Enabled Bit[43]" "Disabled,Enabled"
bitfld.long 0x00 9. " [42] ,IF3 Update Enabled Bit[42]" "Disabled,Enabled"
bitfld.long 0x00 8. " [41] ,IF3 Update Enabled Bit[41]" "Disabled,Enabled"
textline " "
bitfld.long 0x00 7. " [40] ,IF3 Update Enabled Bit[40]" "Disabled,Enabled"
bitfld.long 0x00 6. " [39] ,IF3 Update Enabled Bit[39]" "Disabled,Enabled"
bitfld.long 0x00 5. " [38] ,IF3 Update Enabled Bit[38]" "Disabled,Enabled"
bitfld.long 0x00 4. " [37] ,IF3 Update Enabled Bit[37]" "Disabled,Enabled"
textline " "
bitfld.long 0x00 3. " [36] ,IF3 Update Enabled Bit[36]" "Disabled,Enabled"
bitfld.long 0x00 2. " [35] ,IF3 Update Enabled Bit[35]" "Disabled,Enabled"
bitfld.long 0x00 1. " [34] ,IF3 Update Enabled Bit[34]" "Disabled,Enabled"
bitfld.long 0x00 0. " [33] ,IF3 Update Enabled Bit[33]" "Disabled,Enabled"
group.long 0x168++0x3
line.long 0x0 "IF3UENA6_5,Update Enable 6_5 Register"
bitfld.long 0x00 31. " IF3UPDATEEN [96] ,IF3 Update Enabled Bit[96]" "Disabled,Enabled"
bitfld.long 0x00 30. " [95] ,IF3 Update Enabled Bit[95]" "Disabled,Enabled"
bitfld.long 0x00 29. " [94] ,IF3 Update Enabled Bit[94]" "Disabled,Enabled"
bitfld.long 0x00 28. " [93] ,IF3 Update Enabled Bit[93]" "Disabled,Enabled"
textline " "
bitfld.long 0x00 27. " [92] ,IF3 Update Enabled Bit[92]" "Disabled,Enabled"
bitfld.long 0x00 26. " [91] ,IF3 Update Enabled Bit[91]" "Disabled,Enabled"
bitfld.long 0x00 25. " [90] ,IF3 Update Enabled Bit[90]" "Disabled,Enabled"
bitfld.long 0x00 24. " [89] ,IF3 Update Enabled Bit[89]" "Disabled,Enabled"
textline " "
bitfld.long 0x00 23. " [88] ,IF3 Update Enabled Bit[88]" "Disabled,Enabled"
bitfld.long 0x00 22. " [87] ,IF3 Update Enabled Bit[87]" "Disabled,Enabled"
bitfld.long 0x00 21. " [86] ,IF3 Update Enabled Bit[86]" "Disabled,Enabled"
bitfld.long 0x00 20. " [85] ,IF3 Update Enabled Bit[85]" "Disabled,Enabled"
textline " "
bitfld.long 0x00 19. " [84] ,IF3 Update Enabled Bit[84]" "Disabled,Enabled"
bitfld.long 0x00 18. " [83] ,IF3 Update Enabled Bit[83]" "Disabled,Enabled"
bitfld.long 0x00 17. " [82] ,IF3 Update Enabled Bit[82]" "Disabled,Enabled"
bitfld.long 0x00 16. " [81] ,IF3 Update Enabled Bit[81]" "Disabled,Enabled"
textline " "
bitfld.long 0x00 15. " [80] ,IF3 Update Enabled Bit[80]" "Disabled,Enabled"
bitfld.long 0x00 14. " [79] ,IF3 Update Enabled Bit[79]" "Disabled,Enabled"
bitfld.long 0x00 13. " [78] ,IF3 Update Enabled Bit[78]" "Disabled,Enabled"
bitfld.long 0x00 12. " [77] ,IF3 Update Enabled Bit[77]" "Disabled,Enabled"
textline " "
bitfld.long 0x00 11. " [76] ,IF3 Update Enabled Bit[76]" "Disabled,Enabled"
bitfld.long 0x00 10. " [75] ,IF3 Update Enabled Bit[75]" "Disabled,Enabled"
bitfld.long 0x00 9. " [74] ,IF3 Update Enabled Bit[74]" "Disabled,Enabled"
bitfld.long 0x00 8. " [73] ,IF3 Update Enabled Bit[73]" "Disabled,Enabled"
textline " "
bitfld.long 0x00 7. " [72] ,IF3 Update Enabled Bit[72]" "Disabled,Enabled"
bitfld.long 0x00 6. " [71] ,IF3 Update Enabled Bit[71]" "Disabled,Enabled"
bitfld.long 0x00 5. " [70] ,IF3 Update Enabled Bit[70]" "Disabled,Enabled"
bitfld.long 0x00 4. " [69] ,IF3 Update Enabled Bit[69]" "Disabled,Enabled"
textline " "
bitfld.long 0x00 3. " [68] ,IF3 Update Enabled Bit[68]" "Disabled,Enabled"
bitfld.long 0x00 2. " [67] ,IF3 Update Enabled Bit[67]" "Disabled,Enabled"
bitfld.long 0x00 1. " [66] ,IF3 Update Enabled Bit[66]" "Disabled,Enabled"
bitfld.long 0x00 0. " [65] ,IF3 Update Enabled Bit[65]" "Disabled,Enabled"
group.long 0x16C++0x3
line.long 0x0 "IF3UENA8_7,Update Enable 8_7 Register"
bitfld.long 0x00 31. " IF3UPDATEEN [128] ,IF3 Update Enabled Bit[128]" "Disabled,Enabled"
bitfld.long 0x00 30. " [127] ,IF3 Update Enabled Bit[127]" "Disabled,Enabled"
bitfld.long 0x00 29. " [126] ,IF3 Update Enabled Bit[126]" "Disabled,Enabled"
bitfld.long 0x00 28. " [125] ,IF3 Update Enabled Bit[125]" "Disabled,Enabled"
textline " "
bitfld.long 0x00 27. " [124] ,IF3 Update Enabled Bit[124]" "Disabled,Enabled"
bitfld.long 0x00 26. " [123] ,IF3 Update Enabled Bit[123]" "Disabled,Enabled"
bitfld.long 0x00 25. " [122] ,IF3 Update Enabled Bit[122]" "Disabled,Enabled"
bitfld.long 0x00 24. " [121] ,IF3 Update Enabled Bit[121]" "Disabled,Enabled"
textline " "
bitfld.long 0x00 23. " [120] ,IF3 Update Enabled Bit[120]" "Disabled,Enabled"
bitfld.long 0x00 22. " [119] ,IF3 Update Enabled Bit[119]" "Disabled,Enabled"
bitfld.long 0x00 21. " [118] ,IF3 Update Enabled Bit[118]" "Disabled,Enabled"
bitfld.long 0x00 20. " [117] ,IF3 Update Enabled Bit[117]" "Disabled,Enabled"
textline " "
bitfld.long 0x00 19. " [116] ,IF3 Update Enabled Bit[116]" "Disabled,Enabled"
bitfld.long 0x00 18. " [115] ,IF3 Update Enabled Bit[115]" "Disabled,Enabled"
bitfld.long 0x00 17. " [114] ,IF3 Update Enabled Bit[114]" "Disabled,Enabled"
bitfld.long 0x00 16. " [113] ,IF3 Update Enabled Bit[113]" "Disabled,Enabled"
textline " "
bitfld.long 0x00 15. " [112] ,IF3 Update Enabled Bit[112]" "Disabled,Enabled"
bitfld.long 0x00 14. " [111] ,IF3 Update Enabled Bit[111]" "Disabled,Enabled"
bitfld.long 0x00 13. " [110] ,IF3 Update Enabled Bit[110]" "Disabled,Enabled"
bitfld.long 0x00 12. " [109] ,IF3 Update Enabled Bit[109]" "Disabled,Enabled"
textline " "
bitfld.long 0x00 11. " [108] ,IF3 Update Enabled Bit[108]" "Disabled,Enabled"
bitfld.long 0x00 10. " [107] ,IF3 Update Enabled Bit[107]" "Disabled,Enabled"
bitfld.long 0x00 9. " [106] ,IF3 Update Enabled Bit[106]" "Disabled,Enabled"
bitfld.long 0x00 8. " [105] ,IF3 Update Enabled Bit[105]" "Disabled,Enabled"
textline " "
bitfld.long 0x00 7. " [104] ,IF3 Update Enabled Bit[104]" "Disabled,Enabled"
bitfld.long 0x00 6. " [103] ,IF3 Update Enabled Bit[103]" "Disabled,Enabled"
bitfld.long 0x00 5. " [102] ,IF3 Update Enabled Bit[102]" "Disabled,Enabled"
bitfld.long 0x00 4. " [101] ,IF3 Update Enabled Bit[101]" "Disabled,Enabled"
textline " "
bitfld.long 0x00 3. " [100] ,IF3 Update Enabled Bit[100]" "Disabled,Enabled"
bitfld.long 0x00 2. " [99] ,IF3 Update Enabled Bit[99]" "Disabled,Enabled"
bitfld.long 0x00 1. " [98] ,IF3 Update Enabled Bit[98]" "Disabled,Enabled"
bitfld.long 0x00 0. " [97] ,IF3 Update Enabled Bit[97]" "Disabled,Enabled"
width 12.
group.long 0x1E0++0x3
line.long 0x0 "IOCTRLTX,TX IO Control Register"
bitfld.long 0x00 18. " PU ,Selection of Pull Direction" "Pull down,Pull up"
bitfld.long 0x00 17. " PD ,Pull Functionality Disable" "No,Yes"
bitfld.long 0x00 16. " OD ,Open Drain Mode" "Push pull,Open Drain"
textline " "
bitfld.long 0x00 3. " FUNC ,Functionality of Pin" "General,CAN"
bitfld.long 0x00 2. " DIR ,Direction of Pin" "Input,Output"
bitfld.long 0x00 1. " OUT ,Value to Drive to Pin if Configured for I/O" "Low,High"
textline " "
bitfld.long 0x00 0. " IN ,Value of Pin" "Low,High"
group.long 0x1E4++0x3
line.long 0x0 "IOCTRLRX,RX IO Control Register"
bitfld.long 0x00 18. " PU ,Selection of Pull Direction" "Pull down,Pull up"
bitfld.long 0x00 17. " PD ,Pull Functionality Disable" "No,Yes"
bitfld.long 0x00 16. " OD ,Open Drain Mode" "Push pull,Open Drain"
textline " "
bitfld.long 0x00 3. " FUNC ,Functionality of Pin" "General,CAN"
bitfld.long 0x00 2. " DIR ,Direction of Pin" "Input,Output"
bitfld.long 0x00 1. " OUT ,Value to Drive to Pin if Configured for I/O" "Low,High"
textline " "
bitfld.long 0x00 0. " IN ,Value of Pin" "Low,High"
width 0xb
tree.end
tree "DCAN2"
base ad:0xFFF7DE00
width 12.
group.long 0x00++0x3
line.long 0x0 "CTRL,Config Register"
bitfld.long 0x00 25. " WUBA ,Automatic Wake Up on Bus Activity When in Local Power Down Mode" "Not detected,Detected"
bitfld.long 0x00 24. " PDR ,Request for Local Low Power Down Mode" "Not requested,Power down"
bitfld.long 0x00 20. " DE3 ,DMA Enable for IF3" "Disabled,Enabled"
textline " "
bitfld.long 0x00 19. " DE2 ,DMA Enable for IF2" "Disabled,Enabled"
bitfld.long 0x00 18. " DE1 ,DMA Enable for IF1" "Disabled,Enabled"
bitfld.long 0x00 17. " IE1 ,DCAN1INT Interrupt Enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 16. " INITDBG ,Internal Init State While Debug Access Mode" "No debug,Debug"
bitfld.long 0x00 15. " SWR ,SW Reset Enable" "No reset,Reset"
bitfld.long 0x00 10.--13. " PMD ,Parity on/off" "Enabled,Enabled,Enabled,Enabled,Enabled,Disabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled"
textline " "
bitfld.long 0x00 9. " ABO ,Auto Bus On Enable" "Disabled,Enabled"
bitfld.long 0x00 8. " IDS ,Interruption Debug Support Enable" "Disabled,Enabled"
bitfld.long 0x00 7. " TEST ,Test Mode Enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 6. " CCE ,Configuration Change Enable" "No write,Write"
bitfld.long 0x00 5. " DAR ,Disable Automatic Retransmission" "No,Yes"
bitfld.long 0x00 3. " EIE ,Error Interrupt Enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 2. " SIE ,Status Interrupt Enable" "Disabled,Enabled"
bitfld.long 0x00 1. " IE ,DCAN0INT Interrupt Enable" "Disabled,Enabled"
bitfld.long 0x00 0. " INIT ,Initialization" "Disabled,Enabled"
hgroup.long 0x04++0x3
hide.long 0x0 "ES,Error and Status Register"
in
width 12.
rgroup.long 0x08++0x3
line.long 0x0 "ERRC,Error Counter Register"
bitfld.long 0x00 15. " RP ,Receive Error Passive" "Below,Reached"
hexmask.long.byte 0x00 8.--14. 1. " REC[6-0] ,Receive Error Counter"
hexmask.long.byte 0x00 0.--7. 1. " TEC[7-0] ,Transmit Error Counter"
group.long 0x0C++0x3
line.long 0x0 "BTBRP,Bit Timing_BRP Extension Register"
bitfld.long 0x00 16.--19. " BRPE ,Baud Rate Prescaler Extension" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 12.--14. " TSEG2 ,The Time Segment After the Sample Point" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 8.--11. " TSEG1 ,The Time Segment Before the Sample Point" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x00 6.--7. " SJW ,Synchronization Jump Width" "0,1,2,3"
bitfld.long 0x00 0.--5. " BRP ,Baud Rate Prescaler" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
rgroup.long 0x10++0x3
line.long 0x0 "INTR,Interrupt Register"
hexmask.long.byte 0x00 16.--23. 1. " INT1ID[7-0] ,Interrupt 1 Identifier"
hexmask.long.word 0x00 0.--15. 1. " INTID[15-0] ,Interrupt Identifier"
width 12.
group.long 0x14++0x3
line.long 0x0 "TEST,Test Register"
bitfld.long 0x00 9. " RDA ,RAM Direct Access Enable" "Disabled,Enabled"
bitfld.long 0x00 8. " EXL ,External Loop Back Mode" "Disabled,Enabled"
bitfld.long 0x00 7. " RX ,Receive Pin" "Dominant,Recessive"
textline " "
bitfld.long 0x00 5.--6. " TX1-0 ,Control of CAN_TX pin" "Normal,Sample point,Dominant,Recessive"
bitfld.long 0x00 4. " LBACK ,Loop Back Mode" "Disabled,Enabled"
bitfld.long 0x00 3. " SILENT ,Silent Mode" "Disabled,Enabled"
rgroup.long 0x1C++0x3
line.long 0x0 "PERR,Parity Error Code Register"
bitfld.long 0x00 8.--10. " WORD_NUMBER ,Word Number" ",1,2,3,4,5,?..."
hexmask.long.byte 0x00 0.--7. 1. " MESSAGE_NUMBER ,Message Number"
width 19.
group.long 0x24++0x03
line.long 0x00 "DCAN_ECCDIAG, ECC Diagnostic Register"
bitfld.long 0x00 0.--3. " ECCDIAG , SECDED diagnostic mode enable/disable" ",,,,,Enabled,,,,,Disabled,?..."
group.long 0x28++0x03
line.long 0x00 "DCAN_ECCDIAG_STAT, ECC Diagnostic Status Register"
eventfld.long 0x00 8. " DEFLG_DIAG , Double bit error diagnostic" "No error,Error"
eventfld.long 0x00 0. " SEFLG_DIAG , Single bit error diagnostic" "No error,Error"
group.long 0x2C++0x03
line.long 0x00 "DCAN_ECC_CS, ECC Control and Status Register"
bitfld.long 0x00 24.--27. " SBE_EVT_EN , Single bit error event" "Enabled,Enabled,Enabled,Enabled,Enabled,Disabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled"
bitfld.long 0x00 16.--19. " ECCMODE , Single bit error correction" "Enabled,Enabled,Enabled,Enabled,Enabled,Disabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled"
eventfld.long 0x00 8. " DEFLG , Double bit error flag" "No error,Error"
eventfld.long 0x00 0. " SEFLG , Single bit error flag" "No error,Error"
rgroup.long 0x30++0x03
line.long 0x00 "DCAN_ECC_SERR, ECC Single Bit Error Code Register"
hexmask.long.byte 0x00 0.--7. 1. " Message_Number , Message object number where ECC single bit error has been detected"
group.long 0x80++0x3
line.long 0x0 "ABOT,Auto Bus On Time"
width 12.
rgroup.long 0x84++0x3
line.long 0x0 "TRREQ,Transmission Request X"
bitfld.long 0x00 14.--15. " TXRQSTREG [8] ,Transmission Request 8" "0,1,2,3"
bitfld.long 0x00 12.--13. " [7] ,Transmission Request 7" "0,1,2,3"
bitfld.long 0x00 10.--11. " [6] ,Transmission Request 6" "0,1,2,3"
bitfld.long 0x00 8.--9. " [5] ,Transmission Request 5" "0,1,2,3"
textline " "
bitfld.long 0x00 6.--7. " [4] ,Transmission Request 4" "0,1,2,3"
bitfld.long 0x00 4.--5. " [3] ,Transmission Request 3" "0,1,2,3"
bitfld.long 0x00 2.--3. " [2] ,Transmission Request 2" "0,1,2,3"
bitfld.long 0x00 0.--1. " [1] ,Transmission Request 1" "0,1,2,3"
width 12.
rgroup.long 0x88++0x3
line.long 0x0 "TRREQ21,Transmission Request 2_1"
bitfld.long 0x00 31. " TXRQST [32] ,Transmission Request Bits[32]" "Not requested,Requested"
bitfld.long 0x00 30. " [31] ,Transmission Request Bits[31]" "Not requested,Requested"
bitfld.long 0x00 29. " [30] ,Transmission Request Bits[30]" "Not requested,Requested"
bitfld.long 0x00 28. " [29] ,Transmission Request Bits[29]" "Not requested,Requested"
textline " "
bitfld.long 0x00 27. " [28] ,Transmission Request Bits[28]" "Not requested,Requested"
bitfld.long 0x00 26. " [27] ,Transmission Request Bits[27]" "Not requested,Requested"
bitfld.long 0x00 25. " [26] ,Transmission Request Bits[26]" "Not requested,Requested"
bitfld.long 0x00 24. " [25] ,Transmission Request Bits[25]" "Not requested,Requested"
textline " "
bitfld.long 0x00 23. " [24] ,Transmission Request Bits[24]" "Not requested,Requested"
bitfld.long 0x00 22. " [23] ,Transmission Request Bits[23]" "Not requested,Requested"
bitfld.long 0x00 21. " [22] ,Transmission Request Bits[22]" "Not requested,Requested"
bitfld.long 0x00 20. " [21] ,Transmission Request Bits[21]" "Not requested,Requested"
textline " "
bitfld.long 0x00 19. " [20] ,Transmission Request Bits[20]" "Not requested,Requested"
bitfld.long 0x00 18. " [19] ,Transmission Request Bits[19]" "Not requested,Requested"
bitfld.long 0x00 17. " [18] ,Transmission Request Bits[18]" "Not requested,Requested"
bitfld.long 0x00 16. " [17] ,Transmission Request Bits[17]" "Not requested,Requested"
textline " "
bitfld.long 0x00 15. " [16] ,Transmission Request Bits[16]" "Not requested,Requested"
bitfld.long 0x00 14. " [15] ,Transmission Request Bits[15]" "Not requested,Requested"
bitfld.long 0x00 13. " [14] ,Transmission Request Bits[14]" "Not requested,Requested"
bitfld.long 0x00 12. " [13] ,Transmission Request Bits[13]" "Not requested,Requested"
textline " "
bitfld.long 0x00 11. " [12] ,Transmission Request Bits[12]" "Not requested,Requested"
bitfld.long 0x00 10. " [11] ,Transmission Request Bits[11]" "Not requested,Requested"
bitfld.long 0x00 9. " [10] ,Transmission Request Bits[10]" "Not requested,Requested"
bitfld.long 0x00 8. " [9] ,Transmission Request Bits[9]" "Not requested,Requested"
textline " "
bitfld.long 0x00 7. " [8] ,Transmission Request Bits[8]" "Not requested,Requested"
bitfld.long 0x00 6. " [7] ,Transmission Request Bits[7]" "Not requested,Requested"
bitfld.long 0x00 5. " [6] ,Transmission Request Bits[6]" "Not requested,Requested"
bitfld.long 0x00 4. " [5] ,Transmission Request Bits[5]" "Not requested,Requested"
textline " "
bitfld.long 0x00 3. " [4] ,Transmission Request Bits[4]" "Not requested,Requested"
bitfld.long 0x00 2. " [3] ,Transmission Request Bits[3]" "Not requested,Requested"
bitfld.long 0x00 1. " [2] ,Transmission Request Bits[2]" "Not requested,Requested"
bitfld.long 0x00 0. " [1] ,Transmission Request Bits[1]" "Not requested,Requested"
rgroup.long 0x8C++0x3
line.long 0x0 "TRREQ43,Transmission Request 4_3"
bitfld.long 0x00 31. " TXRQST [64] ,Transmission Request Bits[64]" "Not requested,Requested"
bitfld.long 0x00 30. " [63] ,Transmission Request Bits[63]" "Not requested,Requested"
bitfld.long 0x00 29. " [62] ,Transmission Request Bits[62]" "Not requested,Requested"
bitfld.long 0x00 28. " [61] ,Transmission Request Bits[61]" "Not requested,Requested"
textline " "
bitfld.long 0x00 27. " [60] ,Transmission Request Bits[60]" "Not requested,Requested"
bitfld.long 0x00 26. " [59] ,Transmission Request Bits[59]" "Not requested,Requested"
bitfld.long 0x00 25. " [58] ,Transmission Request Bits[58]" "Not requested,Requested"
bitfld.long 0x00 24. " [57] ,Transmission Request Bits[57]" "Not requested,Requested"
textline " "
bitfld.long 0x00 23. " [56] ,Transmission Request Bits[56]" "Not requested,Requested"
bitfld.long 0x00 22. " [55] ,Transmission Request Bits[55]" "Not requested,Requested"
bitfld.long 0x00 21. " [54] ,Transmission Request Bits[54]" "Not requested,Requested"
bitfld.long 0x00 20. " [53] ,Transmission Request Bits[53]" "Not requested,Requested"
textline " "
bitfld.long 0x00 19. " [52] ,Transmission Request Bits[52]" "Not requested,Requested"
bitfld.long 0x00 18. " [51] ,Transmission Request Bits[51]" "Not requested,Requested"
bitfld.long 0x00 17. " [50] ,Transmission Request Bits[50]" "Not requested,Requested"
bitfld.long 0x00 16. " [49] ,Transmission Request Bits[49]" "Not requested,Requested"
textline " "
bitfld.long 0x00 15. " [48] ,Transmission Request Bits[48]" "Not requested,Requested"
bitfld.long 0x00 14. " [47] ,Transmission Request Bits[47]" "Not requested,Requested"
bitfld.long 0x00 13. " [46] ,Transmission Request Bits[46]" "Not requested,Requested"
bitfld.long 0x00 12. " [45] ,Transmission Request Bits[45]" "Not requested,Requested"
textline " "
bitfld.long 0x00 11. " [44] ,Transmission Request Bits[44]" "Not requested,Requested"
bitfld.long 0x00 10. " [43] ,Transmission Request Bits[43]" "Not requested,Requested"
bitfld.long 0x00 9. " [42] ,Transmission Request Bits[42]" "Not requested,Requested"
bitfld.long 0x00 8. " [41] ,Transmission Request Bits[41]" "Not requested,Requested"
textline " "
bitfld.long 0x00 7. " [40] ,Transmission Request Bits[40]" "Not requested,Requested"
bitfld.long 0x00 6. " [39] ,Transmission Request Bits[39]" "Not requested,Requested"
bitfld.long 0x00 5. " [38] ,Transmission Request Bits[38]" "Not requested,Requested"
bitfld.long 0x00 4. " [37] ,Transmission Request Bits[37]" "Not requested,Requested"
textline " "
bitfld.long 0x00 3. " [36] ,Transmission Request Bits[36]" "Not requested,Requested"
bitfld.long 0x00 2. " [35] ,Transmission Request Bits[35]" "Not requested,Requested"
bitfld.long 0x00 1. " [34] ,Transmission Request Bits[34]" "Not requested,Requested"
bitfld.long 0x00 0. " [33] ,Transmission Request Bits[33]" "Not requested,Requested"
rgroup.long 0x90++0x3
line.long 0x0 "TRREQ65,Transmission Request 6_5"
bitfld.long 0x00 31. " TXRQST [96] ,Transmission Request Bits[96]" "Not requested,Requested"
bitfld.long 0x00 30. " [95] ,Transmission Request Bits[95]" "Not requested,Requested"
bitfld.long 0x00 29. " [94] ,Transmission Request Bits[94]" "Not requested,Requested"
bitfld.long 0x00 28. " [93] ,Transmission Request Bits[93]" "Not requested,Requested"
textline " "
bitfld.long 0x00 27. " [92] ,Transmission Request Bits[92]" "Not requested,Requested"
bitfld.long 0x00 26. " [91] ,Transmission Request Bits[91]" "Not requested,Requested"
bitfld.long 0x00 25. " [90] ,Transmission Request Bits[90]" "Not requested,Requested"
bitfld.long 0x00 24. " [89] ,Transmission Request Bits[89]" "Not requested,Requested"
textline " "
bitfld.long 0x00 23. " [88] ,Transmission Request Bits[88]" "Not requested,Requested"
bitfld.long 0x00 22. " [87] ,Transmission Request Bits[87]" "Not requested,Requested"
bitfld.long 0x00 21. " [86] ,Transmission Request Bits[86]" "Not requested,Requested"
bitfld.long 0x00 20. " [85] ,Transmission Request Bits[85]" "Not requested,Requested"
textline " "
bitfld.long 0x00 19. " [84] ,Transmission Request Bits[84]" "Not requested,Requested"
bitfld.long 0x00 18. " [83] ,Transmission Request Bits[83]" "Not requested,Requested"
bitfld.long 0x00 17. " [82] ,Transmission Request Bits[82]" "Not requested,Requested"
bitfld.long 0x00 16. " [81] ,Transmission Request Bits[81]" "Not requested,Requested"
textline " "
bitfld.long 0x00 15. " [80] ,Transmission Request Bits[80]" "Not requested,Requested"
bitfld.long 0x00 14. " [79] ,Transmission Request Bits[79]" "Not requested,Requested"
bitfld.long 0x00 13. " [78] ,Transmission Request Bits[78]" "Not requested,Requested"
bitfld.long 0x00 12. " [77] ,Transmission Request Bits[77]" "Not requested,Requested"
textline " "
bitfld.long 0x00 11. " [76] ,Transmission Request Bits[76]" "Not requested,Requested"
bitfld.long 0x00 10. " [75] ,Transmission Request Bits[75]" "Not requested,Requested"
bitfld.long 0x00 9. " [74] ,Transmission Request Bits[74]" "Not requested,Requested"
bitfld.long 0x00 8. " [73] ,Transmission Request Bits[73]" "Not requested,Requested"
textline " "
bitfld.long 0x00 7. " [72] ,Transmission Request Bits[72]" "Not requested,Requested"
bitfld.long 0x00 6. " [71] ,Transmission Request Bits[71]" "Not requested,Requested"
bitfld.long 0x00 5. " [70] ,Transmission Request Bits[70]" "Not requested,Requested"
bitfld.long 0x00 4. " [69] ,Transmission Request Bits[69]" "Not requested,Requested"
textline " "
bitfld.long 0x00 3. " [68] ,Transmission Request Bits[68]" "Not requested,Requested"
bitfld.long 0x00 2. " [67] ,Transmission Request Bits[67]" "Not requested,Requested"
bitfld.long 0x00 1. " [66] ,Transmission Request Bits[66]" "Not requested,Requested"
bitfld.long 0x00 0. " [65] ,Transmission Request Bits[65]" "Not requested,Requested"
rgroup.long 0x94++0x3
line.long 0x0 "TRREQ87,Transmission Request 8_7"
bitfld.long 0x00 31. " TXRQST [128] ,Transmission Request Bits[128]" "Not requested,Requested"
bitfld.long 0x00 30. " [127] ,Transmission Request Bits[127]" "Not requested,Requested"
bitfld.long 0x00 29. " [126] ,Transmission Request Bits[126]" "Not requested,Requested"
bitfld.long 0x00 28. " [125] ,Transmission Request Bits[125]" "Not requested,Requested"
textline " "
bitfld.long 0x00 27. " [124] ,Transmission Request Bits[124]" "Not requested,Requested"
bitfld.long 0x00 26. " [123] ,Transmission Request Bits[123]" "Not requested,Requested"
bitfld.long 0x00 25. " [122] ,Transmission Request Bits[122]" "Not requested,Requested"
bitfld.long 0x00 24. " [121] ,Transmission Request Bits[121]" "Not requested,Requested"
textline " "
bitfld.long 0x00 23. " [120] ,Transmission Request Bits[120]" "Not requested,Requested"
bitfld.long 0x00 22. " [119] ,Transmission Request Bits[119]" "Not requested,Requested"
bitfld.long 0x00 21. " [118] ,Transmission Request Bits[118]" "Not requested,Requested"
bitfld.long 0x00 20. " [117] ,Transmission Request Bits[117]" "Not requested,Requested"
textline " "
bitfld.long 0x00 19. " [116] ,Transmission Request Bits[116]" "Not requested,Requested"
bitfld.long 0x00 18. " [115] ,Transmission Request Bits[115]" "Not requested,Requested"
bitfld.long 0x00 17. " [114] ,Transmission Request Bits[114]" "Not requested,Requested"
bitfld.long 0x00 16. " [113] ,Transmission Request Bits[113]" "Not requested,Requested"
textline " "
bitfld.long 0x00 15. " [112] ,Transmission Request Bits[112]" "Not requested,Requested"
bitfld.long 0x00 14. " [111] ,Transmission Request Bits[111]" "Not requested,Requested"
bitfld.long 0x00 13. " [110] ,Transmission Request Bits[110]" "Not requested,Requested"
bitfld.long 0x00 12. " [109] ,Transmission Request Bits[109]" "Not requested,Requested"
textline " "
bitfld.long 0x00 11. " [108] ,Transmission Request Bits[108]" "Not requested,Requested"
bitfld.long 0x00 10. " [107] ,Transmission Request Bits[107]" "Not requested,Requested"
bitfld.long 0x00 9. " [106] ,Transmission Request Bits[106]" "Not requested,Requested"
bitfld.long 0x00 8. " [105] ,Transmission Request Bits[105]" "Not requested,Requested"
textline " "
bitfld.long 0x00 7. " [104] ,Transmission Request Bits[104]" "Not requested,Requested"
bitfld.long 0x00 6. " [103] ,Transmission Request Bits[103]" "Not requested,Requested"
bitfld.long 0x00 5. " [102] ,Transmission Request Bits[102]" "Not requested,Requested"
bitfld.long 0x00 4. " [101] ,Transmission Request Bits[101]" "Not requested,Requested"
textline " "
bitfld.long 0x00 3. " [100] ,Transmission Request Bits[100]" "Not requested,Requested"
bitfld.long 0x00 2. " [99] ,Transmission Request Bits[99]" "Not requested,Requested"
bitfld.long 0x00 1. " [98] ,Transmission Request Bits[98]" "Not requested,Requested"
bitfld.long 0x00 0. " [97] ,Transmission Request Bits[97]" "Not requested,Requested"
width 12.
rgroup.long 0x98++0x3
line.long 0x0 "NEWDAT,New Data X"
bitfld.long 0x00 14.--15. " NEWDATREG [8] ,New Data 8" "0,1,2,3"
bitfld.long 0x00 12.--13. " [7] ,New Data 7" "0,1,2,3"
bitfld.long 0x00 10.--11. " [6] ,New Data 6" "0,1,2,3"
bitfld.long 0x00 8.--9. " [5] ,New Data 5" "0,1,2,3"
textline " "
bitfld.long 0x00 6.--7. " [4] ,New Data 4" "0,1,2,3"
bitfld.long 0x00 4.--5. " [3] ,New Data 3" "0,1,2,3"
bitfld.long 0x00 2.--3. " [2] ,New Data 2" "0,1,2,3"
bitfld.long 0x00 0.--1. " [1] ,New Data 1" "0,1,2,3"
width 12.
rgroup.long 0x9C++0x3
line.long 0x0 "NEWDAT21,New Data 2_1"
bitfld.long 0x00 31. " NEWDAT [32] ,New Data Bit[32]" "Not requested,Requested"
bitfld.long 0x00 30. " [31] ,New Data Bit[31]" "Not requested,Requested"
bitfld.long 0x00 29. " [30] ,New Data Bit[30]" "Not requested,Requested"
bitfld.long 0x00 28. " [29] ,New Data Bit[29]" "Not requested,Requested"
textline " "
bitfld.long 0x00 27. " [28] ,New Data Bit[28]" "Not requested,Requested"
bitfld.long 0x00 26. " [27] ,New Data Bit[27]" "Not requested,Requested"
bitfld.long 0x00 25. " [26] ,New Data Bit[26]" "Not requested,Requested"
bitfld.long 0x00 24. " [25] ,New Data Bit[25]" "Not requested,Requested"
textline " "
bitfld.long 0x00 23. " [24] ,New Data Bit[24]" "Not requested,Requested"
bitfld.long 0x00 22. " [23] ,New Data Bit[23]" "Not requested,Requested"
bitfld.long 0x00 21. " [22] ,New Data Bit[22]" "Not requested,Requested"
bitfld.long 0x00 20. " [21] ,New Data Bit[21]" "Not requested,Requested"
textline " "
bitfld.long 0x00 19. " [20] ,New Data Bit[20]" "Not requested,Requested"
bitfld.long 0x00 18. " [19] ,New Data Bit[19]" "Not requested,Requested"
bitfld.long 0x00 17. " [18] ,New Data Bit[18]" "Not requested,Requested"
bitfld.long 0x00 16. " [17] ,New Data Bit[17]" "Not requested,Requested"
textline " "
bitfld.long 0x00 15. " [16] ,New Data Bit[16]" "Not requested,Requested"
bitfld.long 0x00 14. " [15] ,New Data Bit[15]" "Not requested,Requested"
bitfld.long 0x00 13. " [14] ,New Data Bit[14]" "Not requested,Requested"
bitfld.long 0x00 12. " [13] ,New Data Bit[13]" "Not requested,Requested"
textline " "
bitfld.long 0x00 11. " [12] ,New Data Bit[12]" "Not requested,Requested"
bitfld.long 0x00 10. " [11] ,New Data Bit[11]" "Not requested,Requested"
bitfld.long 0x00 9. " [10] ,New Data Bit[10]" "Not requested,Requested"
bitfld.long 0x00 8. " [9] ,New Data Bit[9]" "Not requested,Requested"
textline " "
bitfld.long 0x00 7. " [8] ,New Data Bit[8]" "Not requested,Requested"
bitfld.long 0x00 6. " [7] ,New Data Bit[7]" "Not requested,Requested"
bitfld.long 0x00 5. " [6] ,New Data Bit[6]" "Not requested,Requested"
bitfld.long 0x00 4. " [5] ,New Data Bit[5]" "Not requested,Requested"
textline " "
bitfld.long 0x00 3. " [4] ,New Data Bit[4]" "Not requested,Requested"
bitfld.long 0x00 2. " [3] ,New Data Bit[3]" "Not requested,Requested"
bitfld.long 0x00 1. " [2] ,New Data Bit[2]" "Not requested,Requested"
bitfld.long 0x00 0. " [1] ,New Data Bit[1]" "Not requested,Requested"
rgroup.long 0xA0++0x3
line.long 0x0 "NEWDAT43,New Data 4_3"
bitfld.long 0x00 31. " NEWDAT [64] ,New Data Bit[64]" "Not requested,Requested"
bitfld.long 0x00 30. " [63] ,New Data Bit[63]" "Not requested,Requested"
bitfld.long 0x00 29. " [62] ,New Data Bit[62]" "Not requested,Requested"
bitfld.long 0x00 28. " [61] ,New Data Bit[61]" "Not requested,Requested"
textline " "
bitfld.long 0x00 27. " [60] ,New Data Bit[60]" "Not requested,Requested"
bitfld.long 0x00 26. " [59] ,New Data Bit[59]" "Not requested,Requested"
bitfld.long 0x00 25. " [58] ,New Data Bit[58]" "Not requested,Requested"
bitfld.long 0x00 24. " [57] ,New Data Bit[57]" "Not requested,Requested"
textline " "
bitfld.long 0x00 23. " [56] ,New Data Bit[56]" "Not requested,Requested"
bitfld.long 0x00 22. " [55] ,New Data Bit[55]" "Not requested,Requested"
bitfld.long 0x00 21. " [54] ,New Data Bit[54]" "Not requested,Requested"
bitfld.long 0x00 20. " [53] ,New Data Bit[53]" "Not requested,Requested"
textline " "
bitfld.long 0x00 19. " [52] ,New Data Bit[52]" "Not requested,Requested"
bitfld.long 0x00 18. " [51] ,New Data Bit[51]" "Not requested,Requested"
bitfld.long 0x00 17. " [50] ,New Data Bit[50]" "Not requested,Requested"
bitfld.long 0x00 16. " [49] ,New Data Bit[49]" "Not requested,Requested"
textline " "
bitfld.long 0x00 15. " [48] ,New Data Bit[48]" "Not requested,Requested"
bitfld.long 0x00 14. " [47] ,New Data Bit[47]" "Not requested,Requested"
bitfld.long 0x00 13. " [46] ,New Data Bit[46]" "Not requested,Requested"
bitfld.long 0x00 12. " [45] ,New Data Bit[45]" "Not requested,Requested"
textline " "
bitfld.long 0x00 11. " [44] ,New Data Bit[44]" "Not requested,Requested"
bitfld.long 0x00 10. " [43] ,New Data Bit[43]" "Not requested,Requested"
bitfld.long 0x00 9. " [42] ,New Data Bit[42]" "Not requested,Requested"
bitfld.long 0x00 8. " [41] ,New Data Bit[41]" "Not requested,Requested"
textline " "
bitfld.long 0x00 7. " [40] ,New Data Bit[40]" "Not requested,Requested"
bitfld.long 0x00 6. " [39] ,New Data Bit[39]" "Not requested,Requested"
bitfld.long 0x00 5. " [38] ,New Data Bit[38]" "Not requested,Requested"
bitfld.long 0x00 4. " [37] ,New Data Bit[37]" "Not requested,Requested"
textline " "
bitfld.long 0x00 3. " [36] ,New Data Bit[36]" "Not requested,Requested"
bitfld.long 0x00 2. " [35] ,New Data Bit[35]" "Not requested,Requested"
bitfld.long 0x00 1. " [34] ,New Data Bit[34]" "Not requested,Requested"
bitfld.long 0x00 0. " [33] ,New Data Bit[33]" "Not requested,Requested"
rgroup.long 0xA4++0x3
line.long 0x0 "NEWDAT65,New Data 6_5"
bitfld.long 0x00 31. " NEWDAT [96] ,New Data Bit[96]" "Not requested,Requested"
bitfld.long 0x00 30. " [95] ,New Data Bit[95]" "Not requested,Requested"
bitfld.long 0x00 29. " [94] ,New Data Bit[94]" "Not requested,Requested"
bitfld.long 0x00 28. " [93] ,New Data Bit[93]" "Not requested,Requested"
textline " "
bitfld.long 0x00 27. " [92] ,New Data Bit[92]" "Not requested,Requested"
bitfld.long 0x00 26. " [91] ,New Data Bit[91]" "Not requested,Requested"
bitfld.long 0x00 25. " [90] ,New Data Bit[90]" "Not requested,Requested"
bitfld.long 0x00 24. " [89] ,New Data Bit[89]" "Not requested,Requested"
textline " "
bitfld.long 0x00 23. " [88] ,New Data Bit[88]" "Not requested,Requested"
bitfld.long 0x00 22. " [87] ,New Data Bit[87]" "Not requested,Requested"
bitfld.long 0x00 21. " [86] ,New Data Bit[86]" "Not requested,Requested"
bitfld.long 0x00 20. " [85] ,New Data Bit[85]" "Not requested,Requested"
textline " "
bitfld.long 0x00 19. " [84] ,New Data Bit[84]" "Not requested,Requested"
bitfld.long 0x00 18. " [83] ,New Data Bit[83]" "Not requested,Requested"
bitfld.long 0x00 17. " [82] ,New Data Bit[82]" "Not requested,Requested"
bitfld.long 0x00 16. " [81] ,New Data Bit[81]" "Not requested,Requested"
textline " "
bitfld.long 0x00 15. " [80] ,New Data Bit[80]" "Not requested,Requested"
bitfld.long 0x00 14. " [79] ,New Data Bit[79]" "Not requested,Requested"
bitfld.long 0x00 13. " [78] ,New Data Bit[78]" "Not requested,Requested"
bitfld.long 0x00 12. " [77] ,New Data Bit[77]" "Not requested,Requested"
textline " "
bitfld.long 0x00 11. " [76] ,New Data Bit[76]" "Not requested,Requested"
bitfld.long 0x00 10. " [75] ,New Data Bit[75]" "Not requested,Requested"
bitfld.long 0x00 9. " [74] ,New Data Bit[74]" "Not requested,Requested"
bitfld.long 0x00 8. " [73] ,New Data Bit[73]" "Not requested,Requested"
textline " "
bitfld.long 0x00 7. " [72] ,New Data Bit[72]" "Not requested,Requested"
bitfld.long 0x00 6. " [71] ,New Data Bit[71]" "Not requested,Requested"
bitfld.long 0x00 5. " [70] ,New Data Bit[70]" "Not requested,Requested"
bitfld.long 0x00 4. " [69] ,New Data Bit[69]" "Not requested,Requested"
textline " "
bitfld.long 0x00 3. " [68] ,New Data Bit[68]" "Not requested,Requested"
bitfld.long 0x00 2. " [67] ,New Data Bit[67]" "Not requested,Requested"
bitfld.long 0x00 1. " [66] ,New Data Bit[66]" "Not requested,Requested"
bitfld.long 0x00 0. " [65] ,New Data Bit[65]" "Not requested,Requested"
rgroup.long 0xA8++0x3
line.long 0x0 "NEWDAT87,New Data 8_7"
bitfld.long 0x00 31. " NEWDAT [128] ,New Data Bit[128]" "Not requested,Requested"
bitfld.long 0x00 30. " [127] ,New Data Bit[127]" "Not requested,Requested"
bitfld.long 0x00 29. " [126] ,New Data Bit[126]" "Not requested,Requested"
bitfld.long 0x00 28. " [125] ,New Data Bit[125]" "Not requested,Requested"
textline " "
bitfld.long 0x00 27. " [124] ,New Data Bit[124]" "Not requested,Requested"
bitfld.long 0x00 26. " [123] ,New Data Bit[123]" "Not requested,Requested"
bitfld.long 0x00 25. " [122] ,New Data Bit[122]" "Not requested,Requested"
bitfld.long 0x00 24. " [121] ,New Data Bit[121]" "Not requested,Requested"
textline " "
bitfld.long 0x00 23. " [120] ,New Data Bit[120]" "Not requested,Requested"
bitfld.long 0x00 22. " [119] ,New Data Bit[119]" "Not requested,Requested"
bitfld.long 0x00 21. " [118] ,New Data Bit[118]" "Not requested,Requested"
bitfld.long 0x00 20. " [117] ,New Data Bit[117]" "Not requested,Requested"
textline " "
bitfld.long 0x00 19. " [116] ,New Data Bit[116]" "Not requested,Requested"
bitfld.long 0x00 18. " [115] ,New Data Bit[115]" "Not requested,Requested"
bitfld.long 0x00 17. " [114] ,New Data Bit[114]" "Not requested,Requested"
bitfld.long 0x00 16. " [113] ,New Data Bit[113]" "Not requested,Requested"
textline " "
bitfld.long 0x00 15. " [112] ,New Data Bit[112]" "Not requested,Requested"
bitfld.long 0x00 14. " [111] ,New Data Bit[111]" "Not requested,Requested"
bitfld.long 0x00 13. " [110] ,New Data Bit[110]" "Not requested,Requested"
bitfld.long 0x00 12. " [109] ,New Data Bit[109]" "Not requested,Requested"
textline " "
bitfld.long 0x00 11. " [108] ,New Data Bit[108]" "Not requested,Requested"
bitfld.long 0x00 10. " [107] ,New Data Bit[107]" "Not requested,Requested"
bitfld.long 0x00 9. " [106] ,New Data Bit[106]" "Not requested,Requested"
bitfld.long 0x00 8. " [105] ,New Data Bit[105]" "Not requested,Requested"
textline " "
bitfld.long 0x00 7. " [104] ,New Data Bit[104]" "Not requested,Requested"
bitfld.long 0x00 6. " [103] ,New Data Bit[103]" "Not requested,Requested"
bitfld.long 0x00 5. " [102] ,New Data Bit[102]" "Not requested,Requested"
bitfld.long 0x00 4. " [101] ,New Data Bit[101]" "Not requested,Requested"
textline " "
bitfld.long 0x00 3. " [100] ,New Data Bit[100]" "Not requested,Requested"
bitfld.long 0x00 2. " [99] ,New Data Bit[99]" "Not requested,Requested"
bitfld.long 0x00 1. " [98] ,New Data Bit[98]" "Not requested,Requested"
bitfld.long 0x00 0. " [97] ,New Data Bit[97]" "Not requested,Requested"
width 12.
rgroup.long 0xAC++0x3
line.long 0x0 "INTPEN,Interrupt Pending X"
bitfld.long 0x00 14.--15. " INTPENDREG [8] ,Interrupt Pending 8" "0,1,2,3"
bitfld.long 0x00 12.--13. " [7] ,Interrupt Pending 7" "0,1,2,3"
bitfld.long 0x00 10.--11. " [6] ,Interrupt Pending 6" "0,1,2,3"
bitfld.long 0x00 8.--9. " [5] ,Interrupt Pending 5" "0,1,2,3"
textline " "
bitfld.long 0x00 6.--7. " [4] ,Interrupt Pending 4" "0,1,2,3"
bitfld.long 0x00 4.--5. " [3] ,Interrupt Pending 3" "0,1,2,3"
bitfld.long 0x00 2.--3. " [2] ,Interrupt Pending 2" "0,1,2,3"
bitfld.long 0x00 0.--1. " [1] ,Interrupt Pending 1" "0,1,2,3"
width 12.
rgroup.long 0xB0++0x3
line.long 0x0 "INTPEN21,Interrupt Pending 2_1"
bitfld.long 0x00 31. " INTPND [32] ,Interrupt Pending Bit[32]" "No interrupt,Interrupt"
bitfld.long 0x00 30. " [31] ,Interrupt Pending Bit[31]" "No interrupt,Interrupt"
bitfld.long 0x00 29. " [30] ,Interrupt Pending Bit[30]" "No interrupt,Interrupt"
bitfld.long 0x00 28. " [29] ,Interrupt Pending Bit[29]" "No interrupt,Interrupt"
textline " "
bitfld.long 0x00 27. " [28] ,Interrupt Pending Bit[28]" "No interrupt,Interrupt"
bitfld.long 0x00 26. " [27] ,Interrupt Pending Bit[27]" "No interrupt,Interrupt"
bitfld.long 0x00 25. " [26] ,Interrupt Pending Bit[26]" "No interrupt,Interrupt"
bitfld.long 0x00 24. " [25] ,Interrupt Pending Bit[25]" "No interrupt,Interrupt"
textline " "
bitfld.long 0x00 23. " [24] ,Interrupt Pending Bit[24]" "No interrupt,Interrupt"
bitfld.long 0x00 22. " [23] ,Interrupt Pending Bit[23]" "No interrupt,Interrupt"
bitfld.long 0x00 21. " [22] ,Interrupt Pending Bit[22]" "No interrupt,Interrupt"
bitfld.long 0x00 20. " [21] ,Interrupt Pending Bit[21]" "No interrupt,Interrupt"
textline " "
bitfld.long 0x00 19. " [20] ,Interrupt Pending Bit[20]" "No interrupt,Interrupt"
bitfld.long 0x00 18. " [19] ,Interrupt Pending Bit[19]" "No interrupt,Interrupt"
bitfld.long 0x00 17. " [18] ,Interrupt Pending Bit[18]" "No interrupt,Interrupt"
bitfld.long 0x00 16. " [17] ,Interrupt Pending Bit[17]" "No interrupt,Interrupt"
textline " "
bitfld.long 0x00 15. " [16] ,Interrupt Pending Bit[16]" "No interrupt,Interrupt"
bitfld.long 0x00 14. " [15] ,Interrupt Pending Bit[15]" "No interrupt,Interrupt"
bitfld.long 0x00 13. " [14] ,Interrupt Pending Bit[14]" "No interrupt,Interrupt"
bitfld.long 0x00 12. " [13] ,Interrupt Pending Bit[13]" "No interrupt,Interrupt"
textline " "
bitfld.long 0x00 11. " [12] ,Interrupt Pending Bit[12]" "No interrupt,Interrupt"
bitfld.long 0x00 10. " [11] ,Interrupt Pending Bit[11]" "No interrupt,Interrupt"
bitfld.long 0x00 9. " [10] ,Interrupt Pending Bit[10]" "No interrupt,Interrupt"
bitfld.long 0x00 8. " [9] ,Interrupt Pending Bit[9]" "No interrupt,Interrupt"
textline " "
bitfld.long 0x00 7. " [8] ,Interrupt Pending Bit[8]" "No interrupt,Interrupt"
bitfld.long 0x00 6. " [7] ,Interrupt Pending Bit[7]" "No interrupt,Interrupt"
bitfld.long 0x00 5. " [6] ,Interrupt Pending Bit[6]" "No interrupt,Interrupt"
bitfld.long 0x00 4. " [5] ,Interrupt Pending Bit[5]" "No interrupt,Interrupt"
textline " "
bitfld.long 0x00 3. " [4] ,Interrupt Pending Bit[4]" "No interrupt,Interrupt"
bitfld.long 0x00 2. " [3] ,Interrupt Pending Bit[3]" "No interrupt,Interrupt"
bitfld.long 0x00 1. " [2] ,Interrupt Pending Bit[2]" "No interrupt,Interrupt"
bitfld.long 0x00 0. " [1] ,Interrupt Pending Bit[1]" "No interrupt,Interrupt"
rgroup.long 0xB4++0x3
line.long 0x0 "INTPEN43,Interrupt Pending 4_3"
bitfld.long 0x00 31. " INTPND [64] ,Interrupt Pending Bit[64]" "No interrupt,Interrupt"
bitfld.long 0x00 30. " [63] ,Interrupt Pending Bit[63]" "No interrupt,Interrupt"
bitfld.long 0x00 29. " [62] ,Interrupt Pending Bit[62]" "No interrupt,Interrupt"
bitfld.long 0x00 28. " [61] ,Interrupt Pending Bit[61]" "No interrupt,Interrupt"
textline " "
bitfld.long 0x00 27. " [60] ,Interrupt Pending Bit[60]" "No interrupt,Interrupt"
bitfld.long 0x00 26. " [59] ,Interrupt Pending Bit[59]" "No interrupt,Interrupt"
bitfld.long 0x00 25. " [58] ,Interrupt Pending Bit[58]" "No interrupt,Interrupt"
bitfld.long 0x00 24. " [57] ,Interrupt Pending Bit[57]" "No interrupt,Interrupt"
textline " "
bitfld.long 0x00 23. " [56] ,Interrupt Pending Bit[56]" "No interrupt,Interrupt"
bitfld.long 0x00 22. " [55] ,Interrupt Pending Bit[55]" "No interrupt,Interrupt"
bitfld.long 0x00 21. " [54] ,Interrupt Pending Bit[54]" "No interrupt,Interrupt"
bitfld.long 0x00 20. " [53] ,Interrupt Pending Bit[53]" "No interrupt,Interrupt"
textline " "
bitfld.long 0x00 19. " [52] ,Interrupt Pending Bit[52]" "No interrupt,Interrupt"
bitfld.long 0x00 18. " [51] ,Interrupt Pending Bit[51]" "No interrupt,Interrupt"
bitfld.long 0x00 17. " [50] ,Interrupt Pending Bit[50]" "No interrupt,Interrupt"
bitfld.long 0x00 16. " [49] ,Interrupt Pending Bit[49]" "No interrupt,Interrupt"
textline " "
bitfld.long 0x00 15. " [48] ,Interrupt Pending Bit[48]" "No interrupt,Interrupt"
bitfld.long 0x00 14. " [47] ,Interrupt Pending Bit[47]" "No interrupt,Interrupt"
bitfld.long 0x00 13. " [46] ,Interrupt Pending Bit[46]" "No interrupt,Interrupt"
bitfld.long 0x00 12. " [45] ,Interrupt Pending Bit[45]" "No interrupt,Interrupt"
textline " "
bitfld.long 0x00 11. " [44] ,Interrupt Pending Bit[44]" "No interrupt,Interrupt"
bitfld.long 0x00 10. " [43] ,Interrupt Pending Bit[43]" "No interrupt,Interrupt"
bitfld.long 0x00 9. " [42] ,Interrupt Pending Bit[42]" "No interrupt,Interrupt"
bitfld.long 0x00 8. " [41] ,Interrupt Pending Bit[41]" "No interrupt,Interrupt"
textline " "
bitfld.long 0x00 7. " [40] ,Interrupt Pending Bit[40]" "No interrupt,Interrupt"
bitfld.long 0x00 6. " [39] ,Interrupt Pending Bit[39]" "No interrupt,Interrupt"
bitfld.long 0x00 5. " [38] ,Interrupt Pending Bit[38]" "No interrupt,Interrupt"
bitfld.long 0x00 4. " [37] ,Interrupt Pending Bit[37]" "No interrupt,Interrupt"
textline " "
bitfld.long 0x00 3. " [36] ,Interrupt Pending Bit[36]" "No interrupt,Interrupt"
bitfld.long 0x00 2. " [35] ,Interrupt Pending Bit[35]" "No interrupt,Interrupt"
bitfld.long 0x00 1. " [34] ,Interrupt Pending Bit[34]" "No interrupt,Interrupt"
bitfld.long 0x00 0. " [33] ,Interrupt Pending Bit[33]" "No interrupt,Interrupt"
rgroup.long 0xB8++0x3
line.long 0x0 "INTPEN65,Interrupt Pending 6_5"
bitfld.long 0x00 31. " INTPND [96] ,Interrupt Pending Bit[96]" "No interrupt,Interrupt"
bitfld.long 0x00 30. " [95] ,Interrupt Pending Bit[95]" "No interrupt,Interrupt"
bitfld.long 0x00 29. " [94] ,Interrupt Pending Bit[94]" "No interrupt,Interrupt"
bitfld.long 0x00 28. " [93] ,Interrupt Pending Bit[93]" "No interrupt,Interrupt"
textline " "
bitfld.long 0x00 27. " [92] ,Interrupt Pending Bit[92]" "No interrupt,Interrupt"
bitfld.long 0x00 26. " [91] ,Interrupt Pending Bit[91]" "No interrupt,Interrupt"
bitfld.long 0x00 25. " [90] ,Interrupt Pending Bit[90]" "No interrupt,Interrupt"
bitfld.long 0x00 24. " [89] ,Interrupt Pending Bit[89]" "No interrupt,Interrupt"
textline " "
bitfld.long 0x00 23. " [88] ,Interrupt Pending Bit[88]" "No interrupt,Interrupt"
bitfld.long 0x00 22. " [87] ,Interrupt Pending Bit[87]" "No interrupt,Interrupt"
bitfld.long 0x00 21. " [86] ,Interrupt Pending Bit[86]" "No interrupt,Interrupt"
bitfld.long 0x00 20. " [85] ,Interrupt Pending Bit[85]" "No interrupt,Interrupt"
textline " "
bitfld.long 0x00 19. " [84] ,Interrupt Pending Bit[84]" "No interrupt,Interrupt"
bitfld.long 0x00 18. " [83] ,Interrupt Pending Bit[83]" "No interrupt,Interrupt"
bitfld.long 0x00 17. " [82] ,Interrupt Pending Bit[82]" "No interrupt,Interrupt"
bitfld.long 0x00 16. " [81] ,Interrupt Pending Bit[81]" "No interrupt,Interrupt"
textline " "
bitfld.long 0x00 15. " [80] ,Interrupt Pending Bit[80]" "No interrupt,Interrupt"
bitfld.long 0x00 14. " [79] ,Interrupt Pending Bit[79]" "No interrupt,Interrupt"
bitfld.long 0x00 13. " [78] ,Interrupt Pending Bit[78]" "No interrupt,Interrupt"
bitfld.long 0x00 12. " [77] ,Interrupt Pending Bit[77]" "No interrupt,Interrupt"
textline " "
bitfld.long 0x00 11. " [76] ,Interrupt Pending Bit[76]" "No interrupt,Interrupt"
bitfld.long 0x00 10. " [75] ,Interrupt Pending Bit[75]" "No interrupt,Interrupt"
bitfld.long 0x00 9. " [74] ,Interrupt Pending Bit[74]" "No interrupt,Interrupt"
bitfld.long 0x00 8. " [73] ,Interrupt Pending Bit[73]" "No interrupt,Interrupt"
textline " "
bitfld.long 0x00 7. " [72] ,Interrupt Pending Bit[72]" "No interrupt,Interrupt"
bitfld.long 0x00 6. " [71] ,Interrupt Pending Bit[71]" "No interrupt,Interrupt"
bitfld.long 0x00 5. " [70] ,Interrupt Pending Bit[70]" "No interrupt,Interrupt"
bitfld.long 0x00 4. " [69] ,Interrupt Pending Bit[69]" "No interrupt,Interrupt"
textline " "
bitfld.long 0x00 3. " [68] ,Interrupt Pending Bit[68]" "No interrupt,Interrupt"
bitfld.long 0x00 2. " [67] ,Interrupt Pending Bit[67]" "No interrupt,Interrupt"
bitfld.long 0x00 1. " [66] ,Interrupt Pending Bit[66]" "No interrupt,Interrupt"
bitfld.long 0x00 0. " [65] ,Interrupt Pending Bit[65]" "No interrupt,Interrupt"
rgroup.long 0xBC++0x3
line.long 0x0 "INTPEN87,Interrupt Pending 8_7"
bitfld.long 0x00 31. " INTPND [128] ,Interrupt Pending Bit[128]" "No interrupt,Interrupt"
bitfld.long 0x00 30. " [127] ,Interrupt Pending Bit[127]" "No interrupt,Interrupt"
bitfld.long 0x00 29. " [126] ,Interrupt Pending Bit[126]" "No interrupt,Interrupt"
bitfld.long 0x00 28. " [125] ,Interrupt Pending Bit[125]" "No interrupt,Interrupt"
textline " "
bitfld.long 0x00 27. " [124] ,Interrupt Pending Bit[124]" "No interrupt,Interrupt"
bitfld.long 0x00 26. " [123] ,Interrupt Pending Bit[123]" "No interrupt,Interrupt"
bitfld.long 0x00 25. " [122] ,Interrupt Pending Bit[122]" "No interrupt,Interrupt"
bitfld.long 0x00 24. " [121] ,Interrupt Pending Bit[121]" "No interrupt,Interrupt"
textline " "
bitfld.long 0x00 23. " [120] ,Interrupt Pending Bit[120]" "No interrupt,Interrupt"
bitfld.long 0x00 22. " [119] ,Interrupt Pending Bit[119]" "No interrupt,Interrupt"
bitfld.long 0x00 21. " [118] ,Interrupt Pending Bit[118]" "No interrupt,Interrupt"
bitfld.long 0x00 20. " [117] ,Interrupt Pending Bit[117]" "No interrupt,Interrupt"
textline " "
bitfld.long 0x00 19. " [116] ,Interrupt Pending Bit[116]" "No interrupt,Interrupt"
bitfld.long 0x00 18. " [115] ,Interrupt Pending Bit[115]" "No interrupt,Interrupt"
bitfld.long 0x00 17. " [114] ,Interrupt Pending Bit[114]" "No interrupt,Interrupt"
bitfld.long 0x00 16. " [113] ,Interrupt Pending Bit[113]" "No interrupt,Interrupt"
textline " "
bitfld.long 0x00 15. " [112] ,Interrupt Pending Bit[112]" "No interrupt,Interrupt"
bitfld.long 0x00 14. " [111] ,Interrupt Pending Bit[111]" "No interrupt,Interrupt"
bitfld.long 0x00 13. " [110] ,Interrupt Pending Bit[110]" "No interrupt,Interrupt"
bitfld.long 0x00 12. " [109] ,Interrupt Pending Bit[109]" "No interrupt,Interrupt"
textline " "
bitfld.long 0x00 11. " [108] ,Interrupt Pending Bit[108]" "No interrupt,Interrupt"
bitfld.long 0x00 10. " [107] ,Interrupt Pending Bit[107]" "No interrupt,Interrupt"
bitfld.long 0x00 9. " [106] ,Interrupt Pending Bit[106]" "No interrupt,Interrupt"
bitfld.long 0x00 8. " [105] ,Interrupt Pending Bit[105]" "No interrupt,Interrupt"
textline " "
bitfld.long 0x00 7. " [104] ,Interrupt Pending Bit[104]" "No interrupt,Interrupt"
bitfld.long 0x00 6. " [103] ,Interrupt Pending Bit[103]" "No interrupt,Interrupt"
bitfld.long 0x00 5. " [102] ,Interrupt Pending Bit[102]" "No interrupt,Interrupt"
bitfld.long 0x00 4. " [101] ,Interrupt Pending Bit[101]" "No interrupt,Interrupt"
textline " "
bitfld.long 0x00 3. " [100] ,Interrupt Pending Bit[100]" "No interrupt,Interrupt"
bitfld.long 0x00 2. " [99] ,Interrupt Pending Bit[99]" "No interrupt,Interrupt"
bitfld.long 0x00 1. " [98] ,Interrupt Pending Bit[98]" "No interrupt,Interrupt"
bitfld.long 0x00 0. " [97] ,Interrupt Pending Bit[97]" "No interrupt,Interrupt"
width 12.
rgroup.long 0xC0++0x3
line.long 0x0 "MVAL,Message Valid X"
bitfld.long 0x00 14.--15. " MSGVALREG [8] ,Message Valid Register 8" "0,1,2,3"
bitfld.long 0x00 12.--13. " [7] ,Message Valid Register 7" "0,1,2,3"
bitfld.long 0x00 10.--11. " [6] ,Message Valid Register 6" "0,1,2,3"
bitfld.long 0x00 8.--9. " [5] ,Message Valid Register 5" "0,1,2,3"
textline " "
bitfld.long 0x00 6.--7. " [4] ,Message Valid Register 4" "0,1,2,3"
bitfld.long 0x00 4.--5. " [3] ,Message Valid Register 3" "0,1,2,3"
bitfld.long 0x00 2.--3. " [2] ,Message Valid Register 2" "0,1,2,3"
bitfld.long 0x00 0.--1. " [1] ,Message Valid Register 1" "0,1,2,3"
width 12.
rgroup.long 0xC4++0x3
line.long 0x0 "MVAL21,Message Valid 2_1"
bitfld.long 0x00 31. " MSGVAL [32] ,Message Valid Bit[32]" "Ignored,Configured"
bitfld.long 0x00 30. " [31] ,Message Valid Bit[31]" "Ignored,Configured"
bitfld.long 0x00 29. " [30] ,Message Valid Bit[30]" "Ignored,Configured"
bitfld.long 0x00 28. " [29] ,Message Valid Bit[29]" "Ignored,Configured"
textline " "
bitfld.long 0x00 27. " [28] ,Message Valid Bit[28]" "Ignored,Configured"
bitfld.long 0x00 26. " [27] ,Message Valid Bit[27]" "Ignored,Configured"
bitfld.long 0x00 25. " [26] ,Message Valid Bit[26]" "Ignored,Configured"
bitfld.long 0x00 24. " [25] ,Message Valid Bit[25]" "Ignored,Configured"
textline " "
bitfld.long 0x00 23. " [24] ,Message Valid Bit[24]" "Ignored,Configured"
bitfld.long 0x00 22. " [23] ,Message Valid Bit[23]" "Ignored,Configured"
bitfld.long 0x00 21. " [22] ,Message Valid Bit[22]" "Ignored,Configured"
bitfld.long 0x00 20. " [21] ,Message Valid Bit[21]" "Ignored,Configured"
textline " "
bitfld.long 0x00 19. " [20] ,Message Valid Bit[20]" "Ignored,Configured"
bitfld.long 0x00 18. " [19] ,Message Valid Bit[19]" "Ignored,Configured"
bitfld.long 0x00 17. " [18] ,Message Valid Bit[18]" "Ignored,Configured"
bitfld.long 0x00 16. " [17] ,Message Valid Bit[17]" "Ignored,Configured"
textline " "
bitfld.long 0x00 15. " [16] ,Message Valid Bit[16]" "Ignored,Configured"
bitfld.long 0x00 14. " [15] ,Message Valid Bit[15]" "Ignored,Configured"
bitfld.long 0x00 13. " [14] ,Message Valid Bit[14]" "Ignored,Configured"
bitfld.long 0x00 12. " [13] ,Message Valid Bit[13]" "Ignored,Configured"
textline " "
bitfld.long 0x00 11. " [12] ,Message Valid Bit[12]" "Ignored,Configured"
bitfld.long 0x00 10. " [11] ,Message Valid Bit[11]" "Ignored,Configured"
bitfld.long 0x00 9. " [10] ,Message Valid Bit[10]" "Ignored,Configured"
bitfld.long 0x00 8. " [9] ,Message Valid Bit[9]" "Ignored,Configured"
textline " "
bitfld.long 0x00 7. " [8] ,Message Valid Bit[8]" "Ignored,Configured"
bitfld.long 0x00 6. " [7] ,Message Valid Bit[7]" "Ignored,Configured"
bitfld.long 0x00 5. " [6] ,Message Valid Bit[6]" "Ignored,Configured"
bitfld.long 0x00 4. " [5] ,Message Valid Bit[5]" "Ignored,Configured"
textline " "
bitfld.long 0x00 3. " [4] ,Message Valid Bit[4]" "Ignored,Configured"
bitfld.long 0x00 2. " [3] ,Message Valid Bit[3]" "Ignored,Configured"
bitfld.long 0x00 1. " [2] ,Message Valid Bit[2]" "Ignored,Configured"
bitfld.long 0x00 0. " [1] ,Message Valid Bit[1]" "Ignored,Configured"
rgroup.long 0xC8++0x3
line.long 0x0 "MVAL43,Message Valid 4_3"
bitfld.long 0x00 31. " MSGVAL [64] ,Message Valid Bit[64]" "Ignored,Configured"
bitfld.long 0x00 30. " [63] ,Message Valid Bit[63]" "Ignored,Configured"
bitfld.long 0x00 29. " [62] ,Message Valid Bit[62]" "Ignored,Configured"
bitfld.long 0x00 28. " [61] ,Message Valid Bit[61]" "Ignored,Configured"
textline " "
bitfld.long 0x00 27. " [60] ,Message Valid Bit[60]" "Ignored,Configured"
bitfld.long 0x00 26. " [59] ,Message Valid Bit[59]" "Ignored,Configured"
bitfld.long 0x00 25. " [58] ,Message Valid Bit[58]" "Ignored,Configured"
bitfld.long 0x00 24. " [57] ,Message Valid Bit[57]" "Ignored,Configured"
textline " "
bitfld.long 0x00 23. " [56] ,Message Valid Bit[56]" "Ignored,Configured"
bitfld.long 0x00 22. " [55] ,Message Valid Bit[55]" "Ignored,Configured"
bitfld.long 0x00 21. " [54] ,Message Valid Bit[54]" "Ignored,Configured"
bitfld.long 0x00 20. " [53] ,Message Valid Bit[53]" "Ignored,Configured"
textline " "
bitfld.long 0x00 19. " [52] ,Message Valid Bit[52]" "Ignored,Configured"
bitfld.long 0x00 18. " [51] ,Message Valid Bit[51]" "Ignored,Configured"
bitfld.long 0x00 17. " [50] ,Message Valid Bit[50]" "Ignored,Configured"
bitfld.long 0x00 16. " [49] ,Message Valid Bit[49]" "Ignored,Configured"
textline " "
bitfld.long 0x00 15. " [48] ,Message Valid Bit[48]" "Ignored,Configured"
bitfld.long 0x00 14. " [47] ,Message Valid Bit[47]" "Ignored,Configured"
bitfld.long 0x00 13. " [46] ,Message Valid Bit[46]" "Ignored,Configured"
bitfld.long 0x00 12. " [45] ,Message Valid Bit[45]" "Ignored,Configured"
textline " "
bitfld.long 0x00 11. " [44] ,Message Valid Bit[44]" "Ignored,Configured"
bitfld.long 0x00 10. " [43] ,Message Valid Bit[43]" "Ignored,Configured"
bitfld.long 0x00 9. " [42] ,Message Valid Bit[42]" "Ignored,Configured"
bitfld.long 0x00 8. " [41] ,Message Valid Bit[41]" "Ignored,Configured"
textline " "
bitfld.long 0x00 7. " [40] ,Message Valid Bit[40]" "Ignored,Configured"
bitfld.long 0x00 6. " [39] ,Message Valid Bit[39]" "Ignored,Configured"
bitfld.long 0x00 5. " [38] ,Message Valid Bit[38]" "Ignored,Configured"
bitfld.long 0x00 4. " [37] ,Message Valid Bit[37]" "Ignored,Configured"
textline " "
bitfld.long 0x00 3. " [36] ,Message Valid Bit[36]" "Ignored,Configured"
bitfld.long 0x00 2. " [35] ,Message Valid Bit[35]" "Ignored,Configured"
bitfld.long 0x00 1. " [34] ,Message Valid Bit[34]" "Ignored,Configured"
bitfld.long 0x00 0. " [33] ,Message Valid Bit[33]" "Ignored,Configured"
rgroup.long 0xCC++0x3
line.long 0x0 "MVAL65,Message Valid 6_5"
bitfld.long 0x00 31. " MSGVAL [96] ,Message Valid Bit[96]" "Ignored,Configured"
bitfld.long 0x00 30. " [95] ,Message Valid Bit[95]" "Ignored,Configured"
bitfld.long 0x00 29. " [94] ,Message Valid Bit[94]" "Ignored,Configured"
bitfld.long 0x00 28. " [93] ,Message Valid Bit[93]" "Ignored,Configured"
textline " "
bitfld.long 0x00 27. " [92] ,Message Valid Bit[92]" "Ignored,Configured"
bitfld.long 0x00 26. " [91] ,Message Valid Bit[91]" "Ignored,Configured"
bitfld.long 0x00 25. " [90] ,Message Valid Bit[90]" "Ignored,Configured"
bitfld.long 0x00 24. " [89] ,Message Valid Bit[89]" "Ignored,Configured"
textline " "
bitfld.long 0x00 23. " [88] ,Message Valid Bit[88]" "Ignored,Configured"
bitfld.long 0x00 22. " [87] ,Message Valid Bit[87]" "Ignored,Configured"
bitfld.long 0x00 21. " [86] ,Message Valid Bit[86]" "Ignored,Configured"
bitfld.long 0x00 20. " [85] ,Message Valid Bit[85]" "Ignored,Configured"
textline " "
bitfld.long 0x00 19. " [84] ,Message Valid Bit[84]" "Ignored,Configured"
bitfld.long 0x00 18. " [83] ,Message Valid Bit[83]" "Ignored,Configured"
bitfld.long 0x00 17. " [82] ,Message Valid Bit[82]" "Ignored,Configured"
bitfld.long 0x00 16. " [81] ,Message Valid Bit[81]" "Ignored,Configured"
textline " "
bitfld.long 0x00 15. " [80] ,Message Valid Bit[80]" "Ignored,Configured"
bitfld.long 0x00 14. " [79] ,Message Valid Bit[79]" "Ignored,Configured"
bitfld.long 0x00 13. " [78] ,Message Valid Bit[78]" "Ignored,Configured"
bitfld.long 0x00 12. " [77] ,Message Valid Bit[77]" "Ignored,Configured"
textline " "
bitfld.long 0x00 11. " [76] ,Message Valid Bit[76]" "Ignored,Configured"
bitfld.long 0x00 10. " [75] ,Message Valid Bit[75]" "Ignored,Configured"
bitfld.long 0x00 9. " [74] ,Message Valid Bit[74]" "Ignored,Configured"
bitfld.long 0x00 8. " [73] ,Message Valid Bit[73]" "Ignored,Configured"
textline " "
bitfld.long 0x00 7. " [72] ,Message Valid Bit[72]" "Ignored,Configured"
bitfld.long 0x00 6. " [71] ,Message Valid Bit[71]" "Ignored,Configured"
bitfld.long 0x00 5. " [70] ,Message Valid Bit[70]" "Ignored,Configured"
bitfld.long 0x00 4. " [69] ,Message Valid Bit[69]" "Ignored,Configured"
textline " "
bitfld.long 0x00 3. " [68] ,Message Valid Bit[68]" "Ignored,Configured"
bitfld.long 0x00 2. " [67] ,Message Valid Bit[67]" "Ignored,Configured"
bitfld.long 0x00 1. " [66] ,Message Valid Bit[66]" "Ignored,Configured"
bitfld.long 0x00 0. " [65] ,Message Valid Bit[65]" "Ignored,Configured"
rgroup.long 0xD0++0x3
line.long 0x0 "MVAL87,Message Valid 8_7"
bitfld.long 0x00 31. " MSGVAL [128] ,Message Valid Bit[128]" "Ignored,Configured"
bitfld.long 0x00 30. " [127] ,Message Valid Bit[127]" "Ignored,Configured"
bitfld.long 0x00 29. " [126] ,Message Valid Bit[126]" "Ignored,Configured"
bitfld.long 0x00 28. " [125] ,Message Valid Bit[125]" "Ignored,Configured"
textline " "
bitfld.long 0x00 27. " [124] ,Message Valid Bit[124]" "Ignored,Configured"
bitfld.long 0x00 26. " [123] ,Message Valid Bit[123]" "Ignored,Configured"
bitfld.long 0x00 25. " [122] ,Message Valid Bit[122]" "Ignored,Configured"
bitfld.long 0x00 24. " [121] ,Message Valid Bit[121]" "Ignored,Configured"
textline " "
bitfld.long 0x00 23. " [120] ,Message Valid Bit[120]" "Ignored,Configured"
bitfld.long 0x00 22. " [119] ,Message Valid Bit[119]" "Ignored,Configured"
bitfld.long 0x00 21. " [118] ,Message Valid Bit[118]" "Ignored,Configured"
bitfld.long 0x00 20. " [117] ,Message Valid Bit[117]" "Ignored,Configured"
textline " "
bitfld.long 0x00 19. " [116] ,Message Valid Bit[116]" "Ignored,Configured"
bitfld.long 0x00 18. " [115] ,Message Valid Bit[115]" "Ignored,Configured"
bitfld.long 0x00 17. " [114] ,Message Valid Bit[114]" "Ignored,Configured"
bitfld.long 0x00 16. " [113] ,Message Valid Bit[113]" "Ignored,Configured"
textline " "
bitfld.long 0x00 15. " [112] ,Message Valid Bit[112]" "Ignored,Configured"
bitfld.long 0x00 14. " [111] ,Message Valid Bit[111]" "Ignored,Configured"
bitfld.long 0x00 13. " [110] ,Message Valid Bit[110]" "Ignored,Configured"
bitfld.long 0x00 12. " [109] ,Message Valid Bit[109]" "Ignored,Configured"
textline " "
bitfld.long 0x00 11. " [108] ,Message Valid Bit[108]" "Ignored,Configured"
bitfld.long 0x00 10. " [107] ,Message Valid Bit[107]" "Ignored,Configured"
bitfld.long 0x00 9. " [106] ,Message Valid Bit[106]" "Ignored,Configured"
bitfld.long 0x00 8. " [105] ,Message Valid Bit[105]" "Ignored,Configured"
textline " "
bitfld.long 0x00 7. " [104] ,Message Valid Bit[104]" "Ignored,Configured"
bitfld.long 0x00 6. " [103] ,Message Valid Bit[103]" "Ignored,Configured"
bitfld.long 0x00 5. " [102] ,Message Valid Bit[102]" "Ignored,Configured"
bitfld.long 0x00 4. " [101] ,Message Valid Bit[101]" "Ignored,Configured"
textline " "
bitfld.long 0x00 3. " [100] ,Message Valid Bit[100]" "Ignored,Configured"
bitfld.long 0x00 2. " [99] ,Message Valid Bit[99]" "Ignored,Configured"
bitfld.long 0x00 1. " [98] ,Message Valid Bit[98]" "Ignored,Configured"
bitfld.long 0x00 0. " [97] ,Message Valid Bit[97]" "Ignored,Configured"
width 12.
group.long 0xD8++0x3
line.long 0x0 "INTPMX21,IntPndMux 2_1"
bitfld.long 0x00 31. " INTPNDMUX [32] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[32]" "DCAN0INT,DCAN1INT"
bitfld.long 0x00 30. " [31] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[31]" "DCAN0INT,DCAN1INT"
bitfld.long 0x00 29. " [30] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[30]" "DCAN0INT,DCAN1INT"
bitfld.long 0x00 28. " [29] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[29]" "DCAN0INT,DCAN1INT"
textline " "
bitfld.long 0x00 27. " [28] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[28]" "DCAN0INT,DCAN1INT"
bitfld.long 0x00 26. " [27] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[27]" "DCAN0INT,DCAN1INT"
bitfld.long 0x00 25. " [26] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[26]" "DCAN0INT,DCAN1INT"
bitfld.long 0x00 24. " [25] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[25]" "DCAN0INT,DCAN1INT"
textline " "
bitfld.long 0x00 23. " [24] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[24]" "DCAN0INT,DCAN1INT"
bitfld.long 0x00 22. " [23] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[23]" "DCAN0INT,DCAN1INT"
bitfld.long 0x00 21. " [22] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[22]" "DCAN0INT,DCAN1INT"
bitfld.long 0x00 20. " [21] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[21]" "DCAN0INT,DCAN1INT"
textline " "
bitfld.long 0x00 19. " [20] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[20]" "DCAN0INT,DCAN1INT"
bitfld.long 0x00 18. " [19] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[19]" "DCAN0INT,DCAN1INT"
bitfld.long 0x00 17. " [18] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[18]" "DCAN0INT,DCAN1INT"
bitfld.long 0x00 16. " [17] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[17]" "DCAN0INT,DCAN1INT"
textline " "
bitfld.long 0x00 15. " [16] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[16]" "DCAN0INT,DCAN1INT"
bitfld.long 0x00 14. " [15] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[15]" "DCAN0INT,DCAN1INT"
bitfld.long 0x00 13. " [14] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[14]" "DCAN0INT,DCAN1INT"
bitfld.long 0x00 12. " [13] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[13]" "DCAN0INT,DCAN1INT"
textline " "
bitfld.long 0x00 11. " [12] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[12]" "DCAN0INT,DCAN1INT"
bitfld.long 0x00 10. " [11] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[11]" "DCAN0INT,DCAN1INT"
bitfld.long 0x00 9. " [10] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[10]" "DCAN0INT,DCAN1INT"
bitfld.long 0x00 8. " [9] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[9]" "DCAN0INT,DCAN1INT"
textline " "
bitfld.long 0x00 7. " [8] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[8]" "DCAN0INT,DCAN1INT"
bitfld.long 0x00 6. " [7] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[7]" "DCAN0INT,DCAN1INT"
bitfld.long 0x00 5. " [6] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[6]" "DCAN0INT,DCAN1INT"
bitfld.long 0x00 4. " [5] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[5]" "DCAN0INT,DCAN1INT"
textline " "
bitfld.long 0x00 3. " [4] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[4]" "DCAN0INT,DCAN1INT"
bitfld.long 0x00 2. " [3] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[3]" "DCAN0INT,DCAN1INT"
bitfld.long 0x00 1. " [2] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[2]" "DCAN0INT,DCAN1INT"
bitfld.long 0x00 0. " [1] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[1]" "DCAN0INT,DCAN1INT"
group.long 0xDC++0x3
line.long 0x0 "INTPMX43,IntPndMux 4_3"
bitfld.long 0x00 31. " INTPNDMUX [64] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[64]" "DCAN0INT,DCAN1INT"
bitfld.long 0x00 30. " [63] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[63]" "DCAN0INT,DCAN1INT"
bitfld.long 0x00 29. " [62] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[62]" "DCAN0INT,DCAN1INT"
bitfld.long 0x00 28. " [61] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[61]" "DCAN0INT,DCAN1INT"
textline " "
bitfld.long 0x00 27. " [60] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[60]" "DCAN0INT,DCAN1INT"
bitfld.long 0x00 26. " [59] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[59]" "DCAN0INT,DCAN1INT"
bitfld.long 0x00 25. " [58] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[58]" "DCAN0INT,DCAN1INT"
bitfld.long 0x00 24. " [57] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[57]" "DCAN0INT,DCAN1INT"
textline " "
bitfld.long 0x00 23. " [56] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[56]" "DCAN0INT,DCAN1INT"
bitfld.long 0x00 22. " [55] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[55]" "DCAN0INT,DCAN1INT"
bitfld.long 0x00 21. " [54] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[54]" "DCAN0INT,DCAN1INT"
bitfld.long 0x00 20. " [53] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[53]" "DCAN0INT,DCAN1INT"
textline " "
bitfld.long 0x00 19. " [52] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[52]" "DCAN0INT,DCAN1INT"
bitfld.long 0x00 18. " [51] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[51]" "DCAN0INT,DCAN1INT"
bitfld.long 0x00 17. " [50] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[50]" "DCAN0INT,DCAN1INT"
bitfld.long 0x00 16. " [49] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[49]" "DCAN0INT,DCAN1INT"
textline " "
bitfld.long 0x00 15. " [48] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[48]" "DCAN0INT,DCAN1INT"
bitfld.long 0x00 14. " [47] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[47]" "DCAN0INT,DCAN1INT"
bitfld.long 0x00 13. " [46] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[46]" "DCAN0INT,DCAN1INT"
bitfld.long 0x00 12. " [45] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[45]" "DCAN0INT,DCAN1INT"
textline " "
bitfld.long 0x00 11. " [44] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[44]" "DCAN0INT,DCAN1INT"
bitfld.long 0x00 10. " [43] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[43]" "DCAN0INT,DCAN1INT"
bitfld.long 0x00 9. " [42] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[42]" "DCAN0INT,DCAN1INT"
bitfld.long 0x00 8. " [41] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[41]" "DCAN0INT,DCAN1INT"
textline " "
bitfld.long 0x00 7. " [40] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[40]" "DCAN0INT,DCAN1INT"
bitfld.long 0x00 6. " [39] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[39]" "DCAN0INT,DCAN1INT"
bitfld.long 0x00 5. " [38] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[38]" "DCAN0INT,DCAN1INT"
bitfld.long 0x00 4. " [37] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[37]" "DCAN0INT,DCAN1INT"
textline " "
bitfld.long 0x00 3. " [36] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[36]" "DCAN0INT,DCAN1INT"
bitfld.long 0x00 2. " [35] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[35]" "DCAN0INT,DCAN1INT"
bitfld.long 0x00 1. " [34] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[34]" "DCAN0INT,DCAN1INT"
bitfld.long 0x00 0. " [33] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[33]" "DCAN0INT,DCAN1INT"
group.long 0xE0++0x3
line.long 0x0 "INTPMX65,IntPndMux 6_5"
bitfld.long 0x00 31. " INTPNDMUX [96] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[96]" "DCAN0INT,DCAN1INT"
bitfld.long 0x00 30. " [95] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[95]" "DCAN0INT,DCAN1INT"
bitfld.long 0x00 29. " [94] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[94]" "DCAN0INT,DCAN1INT"
bitfld.long 0x00 28. " [93] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[93]" "DCAN0INT,DCAN1INT"
textline " "
bitfld.long 0x00 27. " [92] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[92]" "DCAN0INT,DCAN1INT"
bitfld.long 0x00 26. " [91] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[91]" "DCAN0INT,DCAN1INT"
bitfld.long 0x00 25. " [90] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[90]" "DCAN0INT,DCAN1INT"
bitfld.long 0x00 24. " [89] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[89]" "DCAN0INT,DCAN1INT"
textline " "
bitfld.long 0x00 23. " [88] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[88]" "DCAN0INT,DCAN1INT"
bitfld.long 0x00 22. " [87] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[87]" "DCAN0INT,DCAN1INT"
bitfld.long 0x00 21. " [86] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[86]" "DCAN0INT,DCAN1INT"
bitfld.long 0x00 20. " [85] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[85]" "DCAN0INT,DCAN1INT"
textline " "
bitfld.long 0x00 19. " [84] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[84]" "DCAN0INT,DCAN1INT"
bitfld.long 0x00 18. " [83] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[83]" "DCAN0INT,DCAN1INT"
bitfld.long 0x00 17. " [82] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[82]" "DCAN0INT,DCAN1INT"
bitfld.long 0x00 16. " [81] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[81]" "DCAN0INT,DCAN1INT"
textline " "
bitfld.long 0x00 15. " [80] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[80]" "DCAN0INT,DCAN1INT"
bitfld.long 0x00 14. " [79] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[79]" "DCAN0INT,DCAN1INT"
bitfld.long 0x00 13. " [78] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[78]" "DCAN0INT,DCAN1INT"
bitfld.long 0x00 12. " [77] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[77]" "DCAN0INT,DCAN1INT"
textline " "
bitfld.long 0x00 11. " [76] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[76]" "DCAN0INT,DCAN1INT"
bitfld.long 0x00 10. " [75] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[75]" "DCAN0INT,DCAN1INT"
bitfld.long 0x00 9. " [74] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[74]" "DCAN0INT,DCAN1INT"
bitfld.long 0x00 8. " [73] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[73]" "DCAN0INT,DCAN1INT"
textline " "
bitfld.long 0x00 7. " [72] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[72]" "DCAN0INT,DCAN1INT"
bitfld.long 0x00 6. " [71] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[71]" "DCAN0INT,DCAN1INT"
bitfld.long 0x00 5. " [70] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[70]" "DCAN0INT,DCAN1INT"
bitfld.long 0x00 4. " [69] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[69]" "DCAN0INT,DCAN1INT"
textline " "
bitfld.long 0x00 3. " [68] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[68]" "DCAN0INT,DCAN1INT"
bitfld.long 0x00 2. " [67] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[67]" "DCAN0INT,DCAN1INT"
bitfld.long 0x00 1. " [66] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[66]" "DCAN0INT,DCAN1INT"
bitfld.long 0x00 0. " [65] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[65]" "DCAN0INT,DCAN1INT"
group.long 0xE4++0x3
line.long 0x0 "INTPMX87,IntPndMux 8_7"
bitfld.long 0x00 31. " INTPNDMUX [128] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[128]" "DCAN0INT,DCAN1INT"
bitfld.long 0x00 30. " [127] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[127]" "DCAN0INT,DCAN1INT"
bitfld.long 0x00 29. " [126] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[126]" "DCAN0INT,DCAN1INT"
bitfld.long 0x00 28. " [125] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[125]" "DCAN0INT,DCAN1INT"
textline " "
bitfld.long 0x00 27. " [124] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[124]" "DCAN0INT,DCAN1INT"
bitfld.long 0x00 26. " [123] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[123]" "DCAN0INT,DCAN1INT"
bitfld.long 0x00 25. " [122] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[122]" "DCAN0INT,DCAN1INT"
bitfld.long 0x00 24. " [121] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[121]" "DCAN0INT,DCAN1INT"
textline " "
bitfld.long 0x00 23. " [120] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[120]" "DCAN0INT,DCAN1INT"
bitfld.long 0x00 22. " [119] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[119]" "DCAN0INT,DCAN1INT"
bitfld.long 0x00 21. " [118] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[118]" "DCAN0INT,DCAN1INT"
bitfld.long 0x00 20. " [117] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[117]" "DCAN0INT,DCAN1INT"
textline " "
bitfld.long 0x00 19. " [116] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[116]" "DCAN0INT,DCAN1INT"
bitfld.long 0x00 18. " [115] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[115]" "DCAN0INT,DCAN1INT"
bitfld.long 0x00 17. " [114] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[114]" "DCAN0INT,DCAN1INT"
bitfld.long 0x00 16. " [113] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[113]" "DCAN0INT,DCAN1INT"
textline " "
bitfld.long 0x00 15. " [112] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[112]" "DCAN0INT,DCAN1INT"
bitfld.long 0x00 14. " [111] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[111]" "DCAN0INT,DCAN1INT"
bitfld.long 0x00 13. " [110] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[110]" "DCAN0INT,DCAN1INT"
bitfld.long 0x00 12. " [109] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[109]" "DCAN0INT,DCAN1INT"
textline " "
bitfld.long 0x00 11. " [108] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[108]" "DCAN0INT,DCAN1INT"
bitfld.long 0x00 10. " [107] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[107]" "DCAN0INT,DCAN1INT"
bitfld.long 0x00 9. " [106] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[106]" "DCAN0INT,DCAN1INT"
bitfld.long 0x00 8. " [105] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[105]" "DCAN0INT,DCAN1INT"
textline " "
bitfld.long 0x00 7. " [104] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[104]" "DCAN0INT,DCAN1INT"
bitfld.long 0x00 6. " [103] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[103]" "DCAN0INT,DCAN1INT"
bitfld.long 0x00 5. " [102] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[102]" "DCAN0INT,DCAN1INT"
bitfld.long 0x00 4. " [101] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[101]" "DCAN0INT,DCAN1INT"
textline " "
bitfld.long 0x00 3. " [100] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[100]" "DCAN0INT,DCAN1INT"
bitfld.long 0x00 2. " [99] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[99]" "DCAN0INT,DCAN1INT"
bitfld.long 0x00 1. " [98] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[98]" "DCAN0INT,DCAN1INT"
bitfld.long 0x00 0. " [97] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[97]" "DCAN0INT,DCAN1INT"
width 12.
group.long 0x100++0x3
line.long 0x0 "IF1COM,IF1 Command Mask / Command Request Register"
bitfld.long 0x00 23. " WR/RD ,Write / Read" "Read,Write"
textline " "
width 12.
bitfld.long 0x00 22. " MASK ,Access Mask Bits" "Unchanged,Identifier Mask+MDir+MXtd"
textline " "
bitfld.long 0x00 21. " ARB ,Access Arbitration Bits" "Unchanged,Identifier+Dir+Xtd+MSGVAl"
textline " "
width 12.
bitfld.long 0x00 20. " CONTROL ,Access Control Bits" "Unchanged,Control bits"
bitfld.long 0x00 19. " CLRINTPND ,Clear Interrupt Pending Bit" "Low,High"
textline " "
bitfld.long 0x00 18. " TXRQST/NEWDAT ,Access Transmission Request Bit" "Not requested,Requested"
bitfld.long 0x00 17. " DATA_A ,Access Data Bytes 0-3" "Unchanged,Data bytes 0-3"
textline " "
bitfld.long 0x00 16. " DATA_B ,Access Data Bytes 4-7" "Unchanged,Data bytes 4-7"
bitfld.long 0x00 15. " BUSY ,Busy Flag" "Reset,Set"
textline " "
bitfld.long 0x00 14. " DMAACTIVE ,Activation of DMA Feature for Subsequent Internal IF1 Update" "No active,Active"
hexmask.long.byte 0x00 0.--7. 1. " MESSAGE_NUMBER ,Message Number"
width 12.
if (((d.l((ad:0xFFF7DE00+0x108)))&0x40000000)==0x00000000)
group.long 0x104++0x3
line.long 0x0 "IF1MASK,IF1 Mask Register"
bitfld.long 0x00 31. " MXTD ,Mask Extended Identifier" "No effect,Filtering"
bitfld.long 0x00 30. " MDIR ,Mask Message Direction" "No effect,Filtering"
textline " "
bitfld.long 0x00 28. " ID ,Message Identifier bit[28]" "0,1"
bitfld.long 0x00 27. ",Message Identifier bit[27]" "0,1"
bitfld.long 0x00 26. ",Message Identifier bit[26]" "0,1"
bitfld.long 0x00 25. ",Message Identifier bit[25]" "0,1"
bitfld.long 0x00 24. ",Message Identifier bit[24]" "0,1"
bitfld.long 0x00 23. ",Message Identifier bit[23]" "0,1"
bitfld.long 0x00 22. ",Message Identifier bit[22]" "0,1"
bitfld.long 0x00 21. ",Message Identifier bit[21]" "0,1"
bitfld.long 0x00 20. ",Message Identifier bit[20]" "0,1"
bitfld.long 0x00 19. ",Message Identifier bit[19]" "0,1"
bitfld.long 0x00 18. ",Message Identifier bit[18]" "0,1"
else
group.long 0x104++0x3
line.long 0x0 "IF1MASK,IF1 Mask Register"
bitfld.long 0x00 31. " MXTD ,Mask Extended Identifier" "No effect,Filtering"
bitfld.long 0x00 30. " MDIR ,Mask Message Direction" "No effect,Filtering"
textline " "
bitfld.long 0x00 28. " ID ,Message Identifier bit[28]" "0,1"
bitfld.long 0x00 27. ",Message Identifier bit[27]" "0,1"
bitfld.long 0x00 26. ",Message Identifier bit[26]" "0,1"
bitfld.long 0x00 25. ",Message Identifier bit[25]" "0,1"
bitfld.long 0x00 24. ",Message Identifier bit[24]" "0,1"
bitfld.long 0x00 23. ",Message Identifier bit[23]" "0,1"
bitfld.long 0x00 22. ",Message Identifier bit[22]" "0,1"
bitfld.long 0x00 21. ",Message Identifier bit[21]" "0,1"
bitfld.long 0x00 20. ",Message Identifier bit[20]" "0,1"
bitfld.long 0x00 19. ",Message Identifier bit[19]" "0,1"
bitfld.long 0x00 18. ",Message Identifier bit[18]" "0,1"
bitfld.long 0x00 17. ",Message Identifier bit[17]" "0,1"
bitfld.long 0x00 16. ",Message Identifier bit[16]" "0,1"
bitfld.long 0x00 15. ",Message Identifier bit[15]" "0,1"
bitfld.long 0x00 14. ",Message Identifier bit[14]" "0,1"
bitfld.long 0x00 13. ",Message Identifier bit[13]" "0,1"
bitfld.long 0x00 12. ",Message Identifier bit[12]" "0,1"
bitfld.long 0x00 11. ",Message Identifier bit[11]" "0,1"
bitfld.long 0x00 10. ",Message Identifier bit[10]" "0,1"
bitfld.long 0x00 9. ",Message Identifier bit[9]" "0,1"
bitfld.long 0x00 8. ",Message Identifier bit[8]" "0,1"
bitfld.long 0x00 7. ",Message Identifier bit[7]" "0,1"
bitfld.long 0x00 6. ",Message Identifier bit[6]" "0,1"
bitfld.long 0x00 5. ",Message Identifier bit[5]" "0,1"
bitfld.long 0x00 4. ",Message Identifier bit[4]" "0,1"
bitfld.long 0x00 3. ",Message Identifier bit[3]" "0,1"
bitfld.long 0x00 2. ",Message Identifier bit[2]" "0,1"
bitfld.long 0x00 1. ",Message Identifier bit[1]" "0,1"
bitfld.long 0x00 0. ",Message Identifier bit[0]" "0,1"
endif
width 12.
group.long 0x108++0x3
line.long 0x0 "IF1ARB,IF1 Arbitation Register"
bitfld.long 0x00 31. " MSGVAL ,Message Valid" "Ignore,Configure"
bitfld.long 0x00 30. " XTD ,Extended Identifier" "11-bit,29-bit"
bitfld.long 0x00 29. " DIR ,Message Direction" "Receive,Transmit"
hexmask.long 0x00 0.--28. 1. " ID28-0 ,Message Identifier"
width 12.
group.long 0x10C++0x3
line.long 0x0 "IF1MCTRL,IF1 Message Control Register"
bitfld.long 0x00 15. " NEWDAT ,New Data" "No new data,New data"
bitfld.long 0x00 14. " MSGLST ,Message Lost" "Not lost,Lost"
bitfld.long 0x00 13. " INTPND ,Interrupt Pending" "No interrupt,Interrupt"
textline " "
bitfld.long 0x00 12. " UMASK ,Use Acceptance Mask" "Ignored,Masked"
bitfld.long 0x00 11. " TXIE ,Transmit Interrupt Enable" "Unchanged,Set"
bitfld.long 0x00 10. " RXIE ,Receive Interrupt Enable" "Unchanged,Set"
textline " "
bitfld.long 0x00 9. " RMTEN ,Remote Enable" "Disabled,Enabled"
bitfld.long 0x00 8. " TXRQST ,Transmit Request" "Not requested,Requested"
bitfld.long 0x00 7. " EOB ,End of Block" "Single/Last,Not last"
textline " "
bitfld.long 0x00 0.--3. " DLC[3-0] ,Data Length Code" "0 byte,1 bytes,2 bytes,3 bytes,4 bytes,5 bytes,6 bytes,7 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes"
width 12.
group.long 0x110++0x3
line.long 0x0 "IF1DATA,IF1 Data A Register"
hexmask.long.byte 0x00 24.--31. 1. " DATA [3] ,4th data byte of a CAN Data Frame"
hexmask.long.byte 0x00 16.--23. 1. " [2] ,3rd data byte of a CAN Data Frame"
hexmask.long.byte 0x00 8.--15. 1. " [1] ,2nd data byte of a CAN Data Frame"
hexmask.long.byte 0x00 0.--7. 1. " [0] ,1st data byte of a CAN Data Frame"
group.long 0x114++0x3
line.long 0x0 "IF1DATB,IF1 Data B Register"
hexmask.long.byte 0x00 24.--31. 1. " DATA [7] ,8th data byte of a CAN Data Frame"
hexmask.long.byte 0x00 16.--23. 1. " [6] ,7th data byte of a CAN Data Frame"
hexmask.long.byte 0x00 8.--15. 1. " [5] ,6th data byte of a CAN Data Frame"
hexmask.long.byte 0x00 0.--7. 1. " [4] ,5th data byte of a CAN Data Frame"
width 12.
group.long 0x120++0x3
line.long 0x0 "IF2COM,IF2 Command Mask / Command Request Register"
bitfld.long 0x00 23. " WR/RD ,Write / Read" "Read,Write"
textline " "
width 12.
bitfld.long 0x00 22. " MASK ,Access Mask Bits" "Unchanged,Identifier Mask+MDir+MXtd"
textline " "
bitfld.long 0x00 21. " ARB ,Access Arbitration Bits" "Unchanged,Identifier+Dir+Xtd+MSGVAl"
textline " "
width 12.
bitfld.long 0x00 20. " CONTROL ,Access Control Bits" "Unchanged,Control bits"
bitfld.long 0x00 19. " CLRINTPND ,Clear Interrupt Pending Bit" "Low,High"
textline " "
bitfld.long 0x00 18. " TXRQST/NEWDAT ,Access Transmission Request Bit" "Not requested,Requested"
bitfld.long 0x00 17. " DATA_A ,Access Data Bytes 0-3" "Unchanged,Data bytes 0-3"
textline " "
bitfld.long 0x00 16. " DATA_B ,Access Data Bytes 4-7" "Unchanged,Data bytes 4-7"
bitfld.long 0x00 15. " BUSY ,Busy Flag" "Reset,Set"
textline " "
bitfld.long 0x00 14. " DMAACTIVE ,Activation of DMA Feature for Subsequent Internal IF1 Update" "No active,Active"
hexmask.long.byte 0x00 0.--7. 1. " MESSAGE_NUMBER ,Message Number"
width 12.
if (((d.l((ad:0xFFF7DE00+0x128)))&0x40000000)==0x00000000)
group.long 0x124++0x3
line.long 0x0 "IF2MASK,IF2 Mask Register"
bitfld.long 0x00 31. " MXTD ,Mask Extended Identifier" "No effect,Filtering"
bitfld.long 0x00 30. " MDIR ,Mask Message Direction" "No effect,Filtering"
textline " "
bitfld.long 0x00 28. " ID ,Message Identifier bit[28]" "0,1"
bitfld.long 0x00 27. ",Message Identifier bit[27]" "0,1"
bitfld.long 0x00 26. ",Message Identifier bit[26]" "0,1"
bitfld.long 0x00 25. ",Message Identifier bit[25]" "0,1"
bitfld.long 0x00 24. ",Message Identifier bit[24]" "0,1"
bitfld.long 0x00 23. ",Message Identifier bit[23]" "0,1"
bitfld.long 0x00 22. ",Message Identifier bit[22]" "0,1"
bitfld.long 0x00 21. ",Message Identifier bit[21]" "0,1"
bitfld.long 0x00 20. ",Message Identifier bit[20]" "0,1"
bitfld.long 0x00 19. ",Message Identifier bit[19]" "0,1"
bitfld.long 0x00 18. ",Message Identifier bit[18]" "0,1"
else
group.long 0x124++0x3
line.long 0x0 "IF2MASK,IF2 Mask Register"
bitfld.long 0x00 31. " MXTD ,Mask Extended Identifier" "No effect,Filtering"
bitfld.long 0x00 30. " MDIR ,Mask Message Direction" "No effect,Filtering"
textline " "
bitfld.long 0x00 28. " ID ,Message Identifier bit[28]" "0,1"
bitfld.long 0x00 27. ",Message Identifier bit[27]" "0,1"
bitfld.long 0x00 26. ",Message Identifier bit[26]" "0,1"
bitfld.long 0x00 25. ",Message Identifier bit[25]" "0,1"
bitfld.long 0x00 24. ",Message Identifier bit[24]" "0,1"
bitfld.long 0x00 23. ",Message Identifier bit[23]" "0,1"
bitfld.long 0x00 22. ",Message Identifier bit[22]" "0,1"
bitfld.long 0x00 21. ",Message Identifier bit[21]" "0,1"
bitfld.long 0x00 20. ",Message Identifier bit[20]" "0,1"
bitfld.long 0x00 19. ",Message Identifier bit[19]" "0,1"
bitfld.long 0x00 18. ",Message Identifier bit[18]" "0,1"
bitfld.long 0x00 17. ",Message Identifier bit[17]" "0,1"
bitfld.long 0x00 16. ",Message Identifier bit[16]" "0,1"
bitfld.long 0x00 15. ",Message Identifier bit[15]" "0,1"
bitfld.long 0x00 14. ",Message Identifier bit[14]" "0,1"
bitfld.long 0x00 13. ",Message Identifier bit[13]" "0,1"
bitfld.long 0x00 12. ",Message Identifier bit[12]" "0,1"
bitfld.long 0x00 11. ",Message Identifier bit[11]" "0,1"
bitfld.long 0x00 10. ",Message Identifier bit[10]" "0,1"
bitfld.long 0x00 9. ",Message Identifier bit[9]" "0,1"
bitfld.long 0x00 8. ",Message Identifier bit[8]" "0,1"
bitfld.long 0x00 7. ",Message Identifier bit[7]" "0,1"
bitfld.long 0x00 6. ",Message Identifier bit[6]" "0,1"
bitfld.long 0x00 5. ",Message Identifier bit[5]" "0,1"
bitfld.long 0x00 4. ",Message Identifier bit[4]" "0,1"
bitfld.long 0x00 3. ",Message Identifier bit[3]" "0,1"
bitfld.long 0x00 2. ",Message Identifier bit[2]" "0,1"
bitfld.long 0x00 1. ",Message Identifier bit[1]" "0,1"
bitfld.long 0x00 0. ",Message Identifier bit[0]" "0,1"
endif
width 12.
group.long 0x128++0x3
line.long 0x0 "IF2ARB,IF2 Arbitation Register"
bitfld.long 0x00 31. " MSGVAL ,Message Valid" "Ignore,Configure"
bitfld.long 0x00 30. " XTD ,Extended Identifier" "11-bit,29-bit"
bitfld.long 0x00 29. " DIR ,Message Direction" "Receive,Transmit"
hexmask.long 0x00 0.--28. 1. " ID28-0 ,Message Identifier"
width 12.
group.long 0x12C++0x3
line.long 0x0 "IF2MCTRL,IF2 Message Control Register"
bitfld.long 0x00 15. " NEWDAT ,New Data" "No new data,New data"
bitfld.long 0x00 14. " MSGLST ,Message Lost" "Not lost,Lost"
bitfld.long 0x00 13. " INTPND ,Interrupt Pending" "No interrupt,Interrupt"
textline " "
bitfld.long 0x00 12. " UMASK ,Use Acceptance Mask" "Ignored,Masked"
bitfld.long 0x00 11. " TXIE ,Transmit Interrupt Enable" "Unchanged,Set"
bitfld.long 0x00 10. " RXIE ,Receive Interrupt Enable" "Unchanged,Set"
textline " "
bitfld.long 0x00 9. " RMTEN ,Remote Enable" "Disabled,Enabled"
bitfld.long 0x00 8. " TXRQST ,Transmit Request" "Not requested,Requested"
bitfld.long 0x00 7. " EOB ,End of Block" "Single/Last,Not last"
textline " "
bitfld.long 0x00 0.--3. " DLC[3-0] ,Data Length Code" "0 byte,1 bytes,2 bytes,3 bytes,4 bytes,5 bytes,6 bytes,7 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes"
width 12.
group.long 0x130++0x3
line.long 0x0 "IF2DATA,IF2 Data A Register"
hexmask.long.byte 0x00 24.--31. 1. " DATA [3] ,4th data byte of a CAN Data Frame"
hexmask.long.byte 0x00 16.--23. 1. " [2] ,3rd data byte of a CAN Data Frame"
hexmask.long.byte 0x00 8.--15. 1. " [1] ,2nd data byte of a CAN Data Frame"
hexmask.long.byte 0x00 0.--7. 1. " [0] ,1st data byte of a CAN Data Frame"
group.long 0x134++0x3
line.long 0x0 "IF2DATB,IF2 Data B Register"
hexmask.long.byte 0x00 24.--31. 1. " DATA [7] ,8th data byte of a CAN Data Frame"
hexmask.long.byte 0x00 16.--23. 1. " [6] ,7th data byte of a CAN Data Frame"
hexmask.long.byte 0x00 8.--15. 1. " [5] ,6th data byte of a CAN Data Frame"
hexmask.long.byte 0x00 0.--7. 1. " [4] ,5th data byte of a CAN Data Frame"
width 12.
group.long 0x140++0x3
line.long 0x0 "IF3OB,IF3 Observation Register"
bitfld.long 0x00 15. " IF3UPD ,IF3 Updata Data" "Not loaded,Loaded"
bitfld.long 0x00 12. " IF3SDB ,IF3 Status of Data B Read Access" "Low,High"
bitfld.long 0x00 11. " IF3SDA ,IF3 Status of Data A Read Access" "Low,High"
textline " "
bitfld.long 0x00 10. " IF3SC ,IF3 Status of Control Bits Read Access" "Low,High"
bitfld.long 0x00 9. " IF3SA ,IF3 Status of Arbitration Data Read Access" "Low,High"
bitfld.long 0x00 8. " IF3SM ,IF3 Status of Mask Data Read Access" "Low,High"
textline " "
bitfld.long 0x00 4. " DATA_B ,Data B Read Observation" "Not read,Read"
bitfld.long 0x00 3. " DATA_A ,Data A Read Observation" "Not read,Read"
bitfld.long 0x00 2. " CTRL ,Ctrl Read Observation" "Not read,Read"
textline " "
bitfld.long 0x00 1. " ARB ,Arbitration Data Read Observation" "Not read,Read"
bitfld.long 0x00 0. " MASK ,Mask Data Read Observation" "Not read,Read"
if (((d.l((ad:0xFFF7DE00+0x148)))&0x40000000)==0x00000000)
rgroup.long 0x144++0x3
line.long 0x0 "IF3MASK,IF3 Mask Register"
bitfld.long 0x00 31. " MXTD ,Mask Extended Identifier" "No effect,Filtering"
bitfld.long 0x00 30. " MDIR ,Mask Message Direction" "No effect,Filtering"
textline " "
bitfld.long 0x00 28. " ID ,Message Identifier bit[28]" "0,1"
bitfld.long 0x00 27. ",Message Identifier bit[27]" "0,1"
bitfld.long 0x00 26. ",Message Identifier bit[26]" "0,1"
bitfld.long 0x00 25. ",Message Identifier bit[25]" "0,1"
bitfld.long 0x00 24. ",Message Identifier bit[24]" "0,1"
bitfld.long 0x00 23. ",Message Identifier bit[23]" "0,1"
bitfld.long 0x00 22. ",Message Identifier bit[22]" "0,1"
bitfld.long 0x00 21. ",Message Identifier bit[21]" "0,1"
bitfld.long 0x00 20. ",Message Identifier bit[20]" "0,1"
bitfld.long 0x00 19. ",Message Identifier bit[19]" "0,1"
bitfld.long 0x00 18. ",Message Identifier bit[18]" "0,1"
else
group.long 0x144++0x3
line.long 0x0 "IF3MASK,IF3 Mask Register"
bitfld.long 0x00 31. " MXTD ,Mask Extended Identifier" "No effect,Filtering"
bitfld.long 0x00 30. " MDIR ,Mask Message Direction" "No effect,Filtering"
textline " "
bitfld.long 0x00 28. " ID ,Message Identifier bit[28]" "0,1"
bitfld.long 0x00 27. ",Message Identifier bit[27]" "0,1"
bitfld.long 0x00 26. ",Message Identifier bit[26]" "0,1"
bitfld.long 0x00 25. ",Message Identifier bit[25]" "0,1"
bitfld.long 0x00 24. ",Message Identifier bit[24]" "0,1"
bitfld.long 0x00 23. ",Message Identifier bit[23]" "0,1"
bitfld.long 0x00 22. ",Message Identifier bit[22]" "0,1"
bitfld.long 0x00 21. ",Message Identifier bit[21]" "0,1"
bitfld.long 0x00 20. ",Message Identifier bit[20]" "0,1"
bitfld.long 0x00 19. ",Message Identifier bit[19]" "0,1"
bitfld.long 0x00 18. ",Message Identifier bit[18]" "0,1"
bitfld.long 0x00 17. ",Message Identifier bit[17]" "0,1"
bitfld.long 0x00 16. ",Message Identifier bit[16]" "0,1"
bitfld.long 0x00 15. ",Message Identifier bit[15]" "0,1"
bitfld.long 0x00 14. ",Message Identifier bit[14]" "0,1"
bitfld.long 0x00 13. ",Message Identifier bit[13]" "0,1"
bitfld.long 0x00 12. ",Message Identifier bit[12]" "0,1"
bitfld.long 0x00 11. ",Message Identifier bit[11]" "0,1"
bitfld.long 0x00 10. ",Message Identifier bit[10]" "0,1"
bitfld.long 0x00 9. ",Message Identifier bit[9]" "0,1"
bitfld.long 0x00 8. ",Message Identifier bit[8]" "0,1"
bitfld.long 0x00 7. ",Message Identifier bit[7]" "0,1"
bitfld.long 0x00 6. ",Message Identifier bit[6]" "0,1"
bitfld.long 0x00 5. ",Message Identifier bit[5]" "0,1"
bitfld.long 0x00 4. ",Message Identifier bit[4]" "0,1"
bitfld.long 0x00 3. ",Message Identifier bit[3]" "0,1"
bitfld.long 0x00 2. ",Message Identifier bit[2]" "0,1"
bitfld.long 0x00 1. ",Message Identifier bit[1]" "0,1"
bitfld.long 0x00 0. ",Message Identifier bit[0]" "0,1"
endif
group.long 0x148++0x3
line.long 0x0 "IF3ARB,IF3 Arbitation Register"
bitfld.long 0x00 31. " MSGVAL ,Message Valid" "Ignored,Configured"
bitfld.long 0x00 30. " XTD ,Extended Identifier" "11-bit,29-bit"
bitfld.long 0x00 29. " DIR ,Message Direction" "Receive,Transmit"
textline " "
hexmask.long 0x00 0.--28. 1. " ID[28-0] ,Message Identifier"
group.long 0x14C++0x3
line.long 0x0 "IF3MCTRL,IF3 Message Control Register"
bitfld.long 0x00 15. " NEWDAT ,New Data" "No new data,New data"
bitfld.long 0x00 14. " MSGLST ,Message Lost" "Not lost,Lost"
bitfld.long 0x00 13. " INTPND ,Interrupt Pending" "No interrupt,Interrupt"
textline " "
bitfld.long 0x00 12. " UMASK ,Use Acceptance Mask" "Ignored,Masked"
bitfld.long 0x00 11. " TXIE ,Transmit Interrupt Enable" "Unchanged,Enabled"
bitfld.long 0x00 10. " RXIE ,Receive Interrupt Enable" "Unchanged,Enabled"
textline " "
bitfld.long 0x00 9. " RMTEN ,Remote Enable" "Unchanged,Enabled"
bitfld.long 0x00 8. " TXRQST ,Transmit Request" "Not requested,Requested"
bitfld.long 0x00 7. " EOB ,End of Block" "Not last,Single/Last"
textline " "
bitfld.long 0x00 0.--3. " DLC[3-0] ,Data Length Code" "0 byte,1 byte,2 bytes,3 bytes,4 bytes,5 bytes,6 bytes,7 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes"
width 12.
group.long 0x150++0x3
line.long 0x0 "IF3DATA,IF3 Data A Register"
hexmask.long.byte 0x00 24.--31. 1. " DATA [3] ,4th data byte of a CAN Data Frame"
hexmask.long.byte 0x00 16.--23. 1. " [2] ,3rd data byte of a CAN Data Frame"
hexmask.long.byte 0x00 8.--15. 1. " [1] ,2nd data byte of a CAN Data Frame"
hexmask.long.byte 0x00 0.--7. 1. " [0] ,1st data byte of a CAN Data Frame"
group.long 0x154++0x3
line.long 0x0 "IF3DATB,IF3 Data B Register"
hexmask.long.byte 0x00 24.--31. 1. " DATA [7] ,8th data byte of a CAN Data Frame"
hexmask.long.byte 0x00 16.--23. 1. " [6] ,7th data byte of a CAN Data Frame"
hexmask.long.byte 0x00 8.--15. 1. " [5] ,6th data byte of a CAN Data Frame"
hexmask.long.byte 0x00 0.--7. 1. " ATA [4] ,5th data byte of a CAN Data Frame"
width 12.
group.long 0x160++0x3
line.long 0x0 "IF3UENA2_1,Update Enable 2_1 Register"
bitfld.long 0x00 31. " IF3UPDATEEN [32] ,IF3 Update Enabled Bit[32]" "Disabled,Enabled"
bitfld.long 0x00 30. " [31] ,IF3 Update Enabled Bit[31]" "Disabled,Enabled"
bitfld.long 0x00 29. " [30] ,IF3 Update Enabled Bit[30]" "Disabled,Enabled"
bitfld.long 0x00 28. " [29] ,IF3 Update Enabled Bit[29]" "Disabled,Enabled"
textline " "
bitfld.long 0x00 27. " [28] ,IF3 Update Enabled Bit[28]" "Disabled,Enabled"
bitfld.long 0x00 26. " [27] ,IF3 Update Enabled Bit[27]" "Disabled,Enabled"
bitfld.long 0x00 25. " [26] ,IF3 Update Enabled Bit[26]" "Disabled,Enabled"
bitfld.long 0x00 24. " [25] ,IF3 Update Enabled Bit[25]" "Disabled,Enabled"
textline " "
bitfld.long 0x00 23. " [24] ,IF3 Update Enabled Bit[24]" "Disabled,Enabled"
bitfld.long 0x00 22. " [23] ,IF3 Update Enabled Bit[23]" "Disabled,Enabled"
bitfld.long 0x00 21. " [22] ,IF3 Update Enabled Bit[22]" "Disabled,Enabled"
bitfld.long 0x00 20. " [21] ,IF3 Update Enabled Bit[21]" "Disabled,Enabled"
textline " "
bitfld.long 0x00 19. " [20] ,IF3 Update Enabled Bit[20]" "Disabled,Enabled"
bitfld.long 0x00 18. " [19] ,IF3 Update Enabled Bit[19]" "Disabled,Enabled"
bitfld.long 0x00 17. " [18] ,IF3 Update Enabled Bit[18]" "Disabled,Enabled"
bitfld.long 0x00 16. " [17] ,IF3 Update Enabled Bit[17]" "Disabled,Enabled"
textline " "
bitfld.long 0x00 15. " [16] ,IF3 Update Enabled Bit[16]" "Disabled,Enabled"
bitfld.long 0x00 14. " [15] ,IF3 Update Enabled Bit[15]" "Disabled,Enabled"
bitfld.long 0x00 13. " [14] ,IF3 Update Enabled Bit[14]" "Disabled,Enabled"
bitfld.long 0x00 12. " [13] ,IF3 Update Enabled Bit[13]" "Disabled,Enabled"
textline " "
bitfld.long 0x00 11. " [12] ,IF3 Update Enabled Bit[12]" "Disabled,Enabled"
bitfld.long 0x00 10. " [11] ,IF3 Update Enabled Bit[11]" "Disabled,Enabled"
bitfld.long 0x00 9. " [10] ,IF3 Update Enabled Bit[10]" "Disabled,Enabled"
bitfld.long 0x00 8. " [9] ,IF3 Update Enabled Bit[9]" "Disabled,Enabled"
textline " "
bitfld.long 0x00 7. " [8] ,IF3 Update Enabled Bit[8]" "Disabled,Enabled"
bitfld.long 0x00 6. " [7] ,IF3 Update Enabled Bit[7]" "Disabled,Enabled"
bitfld.long 0x00 5. " [6] ,IF3 Update Enabled Bit[6]" "Disabled,Enabled"
bitfld.long 0x00 4. " [5] ,IF3 Update Enabled Bit[5]" "Disabled,Enabled"
textline " "
bitfld.long 0x00 3. " [4] ,IF3 Update Enabled Bit[4]" "Disabled,Enabled"
bitfld.long 0x00 2. " [3] ,IF3 Update Enabled Bit[3]" "Disabled,Enabled"
bitfld.long 0x00 1. " [2] ,IF3 Update Enabled Bit[2]" "Disabled,Enabled"
bitfld.long 0x00 0. " [1] ,IF3 Update Enabled Bit[1]" "Disabled,Enabled"
group.long 0x164++0x3
line.long 0x0 "IF3UENA4_3,Update Enable 4_3 Register"
bitfld.long 0x00 31. " IF3UPDATEEN [64] ,IF3 Update Enabled Bit[64]" "Disabled,Enabled"
bitfld.long 0x00 30. " [63] ,IF3 Update Enabled Bit[63]" "Disabled,Enabled"
bitfld.long 0x00 29. " [62] ,IF3 Update Enabled Bit[62]" "Disabled,Enabled"
bitfld.long 0x00 28. " [61] ,IF3 Update Enabled Bit[61]" "Disabled,Enabled"
textline " "
bitfld.long 0x00 27. " [60] ,IF3 Update Enabled Bit[60]" "Disabled,Enabled"
bitfld.long 0x00 26. " [59] ,IF3 Update Enabled Bit[59]" "Disabled,Enabled"
bitfld.long 0x00 25. " [58] ,IF3 Update Enabled Bit[58]" "Disabled,Enabled"
bitfld.long 0x00 24. " [57] ,IF3 Update Enabled Bit[57]" "Disabled,Enabled"
textline " "
bitfld.long 0x00 23. " [56] ,IF3 Update Enabled Bit[56]" "Disabled,Enabled"
bitfld.long 0x00 22. " [55] ,IF3 Update Enabled Bit[55]" "Disabled,Enabled"
bitfld.long 0x00 21. " [54] ,IF3 Update Enabled Bit[54]" "Disabled,Enabled"
bitfld.long 0x00 20. " [53] ,IF3 Update Enabled Bit[53]" "Disabled,Enabled"
textline " "
bitfld.long 0x00 19. " [52] ,IF3 Update Enabled Bit[52]" "Disabled,Enabled"
bitfld.long 0x00 18. " [51] ,IF3 Update Enabled Bit[51]" "Disabled,Enabled"
bitfld.long 0x00 17. " [50] ,IF3 Update Enabled Bit[50]" "Disabled,Enabled"
bitfld.long 0x00 16. " [49] ,IF3 Update Enabled Bit[49]" "Disabled,Enabled"
textline " "
bitfld.long 0x00 15. " [48] ,IF3 Update Enabled Bit[48]" "Disabled,Enabled"
bitfld.long 0x00 14. " [47] ,IF3 Update Enabled Bit[47]" "Disabled,Enabled"
bitfld.long 0x00 13. " [46] ,IF3 Update Enabled Bit[46]" "Disabled,Enabled"
bitfld.long 0x00 12. " [45] ,IF3 Update Enabled Bit[45]" "Disabled,Enabled"
textline " "
bitfld.long 0x00 11. " [44] ,IF3 Update Enabled Bit[44]" "Disabled,Enabled"
bitfld.long 0x00 10. " [43] ,IF3 Update Enabled Bit[43]" "Disabled,Enabled"
bitfld.long 0x00 9. " [42] ,IF3 Update Enabled Bit[42]" "Disabled,Enabled"
bitfld.long 0x00 8. " [41] ,IF3 Update Enabled Bit[41]" "Disabled,Enabled"
textline " "
bitfld.long 0x00 7. " [40] ,IF3 Update Enabled Bit[40]" "Disabled,Enabled"
bitfld.long 0x00 6. " [39] ,IF3 Update Enabled Bit[39]" "Disabled,Enabled"
bitfld.long 0x00 5. " [38] ,IF3 Update Enabled Bit[38]" "Disabled,Enabled"
bitfld.long 0x00 4. " [37] ,IF3 Update Enabled Bit[37]" "Disabled,Enabled"
textline " "
bitfld.long 0x00 3. " [36] ,IF3 Update Enabled Bit[36]" "Disabled,Enabled"
bitfld.long 0x00 2. " [35] ,IF3 Update Enabled Bit[35]" "Disabled,Enabled"
bitfld.long 0x00 1. " [34] ,IF3 Update Enabled Bit[34]" "Disabled,Enabled"
bitfld.long 0x00 0. " [33] ,IF3 Update Enabled Bit[33]" "Disabled,Enabled"
group.long 0x168++0x3
line.long 0x0 "IF3UENA6_5,Update Enable 6_5 Register"
bitfld.long 0x00 31. " IF3UPDATEEN [96] ,IF3 Update Enabled Bit[96]" "Disabled,Enabled"
bitfld.long 0x00 30. " [95] ,IF3 Update Enabled Bit[95]" "Disabled,Enabled"
bitfld.long 0x00 29. " [94] ,IF3 Update Enabled Bit[94]" "Disabled,Enabled"
bitfld.long 0x00 28. " [93] ,IF3 Update Enabled Bit[93]" "Disabled,Enabled"
textline " "
bitfld.long 0x00 27. " [92] ,IF3 Update Enabled Bit[92]" "Disabled,Enabled"
bitfld.long 0x00 26. " [91] ,IF3 Update Enabled Bit[91]" "Disabled,Enabled"
bitfld.long 0x00 25. " [90] ,IF3 Update Enabled Bit[90]" "Disabled,Enabled"
bitfld.long 0x00 24. " [89] ,IF3 Update Enabled Bit[89]" "Disabled,Enabled"
textline " "
bitfld.long 0x00 23. " [88] ,IF3 Update Enabled Bit[88]" "Disabled,Enabled"
bitfld.long 0x00 22. " [87] ,IF3 Update Enabled Bit[87]" "Disabled,Enabled"
bitfld.long 0x00 21. " [86] ,IF3 Update Enabled Bit[86]" "Disabled,Enabled"
bitfld.long 0x00 20. " [85] ,IF3 Update Enabled Bit[85]" "Disabled,Enabled"
textline " "
bitfld.long 0x00 19. " [84] ,IF3 Update Enabled Bit[84]" "Disabled,Enabled"
bitfld.long 0x00 18. " [83] ,IF3 Update Enabled Bit[83]" "Disabled,Enabled"
bitfld.long 0x00 17. " [82] ,IF3 Update Enabled Bit[82]" "Disabled,Enabled"
bitfld.long 0x00 16. " [81] ,IF3 Update Enabled Bit[81]" "Disabled,Enabled"
textline " "
bitfld.long 0x00 15. " [80] ,IF3 Update Enabled Bit[80]" "Disabled,Enabled"
bitfld.long 0x00 14. " [79] ,IF3 Update Enabled Bit[79]" "Disabled,Enabled"
bitfld.long 0x00 13. " [78] ,IF3 Update Enabled Bit[78]" "Disabled,Enabled"
bitfld.long 0x00 12. " [77] ,IF3 Update Enabled Bit[77]" "Disabled,Enabled"
textline " "
bitfld.long 0x00 11. " [76] ,IF3 Update Enabled Bit[76]" "Disabled,Enabled"
bitfld.long 0x00 10. " [75] ,IF3 Update Enabled Bit[75]" "Disabled,Enabled"
bitfld.long 0x00 9. " [74] ,IF3 Update Enabled Bit[74]" "Disabled,Enabled"
bitfld.long 0x00 8. " [73] ,IF3 Update Enabled Bit[73]" "Disabled,Enabled"
textline " "
bitfld.long 0x00 7. " [72] ,IF3 Update Enabled Bit[72]" "Disabled,Enabled"
bitfld.long 0x00 6. " [71] ,IF3 Update Enabled Bit[71]" "Disabled,Enabled"
bitfld.long 0x00 5. " [70] ,IF3 Update Enabled Bit[70]" "Disabled,Enabled"
bitfld.long 0x00 4. " [69] ,IF3 Update Enabled Bit[69]" "Disabled,Enabled"
textline " "
bitfld.long 0x00 3. " [68] ,IF3 Update Enabled Bit[68]" "Disabled,Enabled"
bitfld.long 0x00 2. " [67] ,IF3 Update Enabled Bit[67]" "Disabled,Enabled"
bitfld.long 0x00 1. " [66] ,IF3 Update Enabled Bit[66]" "Disabled,Enabled"
bitfld.long 0x00 0. " [65] ,IF3 Update Enabled Bit[65]" "Disabled,Enabled"
group.long 0x16C++0x3
line.long 0x0 "IF3UENA8_7,Update Enable 8_7 Register"
bitfld.long 0x00 31. " IF3UPDATEEN [128] ,IF3 Update Enabled Bit[128]" "Disabled,Enabled"
bitfld.long 0x00 30. " [127] ,IF3 Update Enabled Bit[127]" "Disabled,Enabled"
bitfld.long 0x00 29. " [126] ,IF3 Update Enabled Bit[126]" "Disabled,Enabled"
bitfld.long 0x00 28. " [125] ,IF3 Update Enabled Bit[125]" "Disabled,Enabled"
textline " "
bitfld.long 0x00 27. " [124] ,IF3 Update Enabled Bit[124]" "Disabled,Enabled"
bitfld.long 0x00 26. " [123] ,IF3 Update Enabled Bit[123]" "Disabled,Enabled"
bitfld.long 0x00 25. " [122] ,IF3 Update Enabled Bit[122]" "Disabled,Enabled"
bitfld.long 0x00 24. " [121] ,IF3 Update Enabled Bit[121]" "Disabled,Enabled"
textline " "
bitfld.long 0x00 23. " [120] ,IF3 Update Enabled Bit[120]" "Disabled,Enabled"
bitfld.long 0x00 22. " [119] ,IF3 Update Enabled Bit[119]" "Disabled,Enabled"
bitfld.long 0x00 21. " [118] ,IF3 Update Enabled Bit[118]" "Disabled,Enabled"
bitfld.long 0x00 20. " [117] ,IF3 Update Enabled Bit[117]" "Disabled,Enabled"
textline " "
bitfld.long 0x00 19. " [116] ,IF3 Update Enabled Bit[116]" "Disabled,Enabled"
bitfld.long 0x00 18. " [115] ,IF3 Update Enabled Bit[115]" "Disabled,Enabled"
bitfld.long 0x00 17. " [114] ,IF3 Update Enabled Bit[114]" "Disabled,Enabled"
bitfld.long 0x00 16. " [113] ,IF3 Update Enabled Bit[113]" "Disabled,Enabled"
textline " "
bitfld.long 0x00 15. " [112] ,IF3 Update Enabled Bit[112]" "Disabled,Enabled"
bitfld.long 0x00 14. " [111] ,IF3 Update Enabled Bit[111]" "Disabled,Enabled"
bitfld.long 0x00 13. " [110] ,IF3 Update Enabled Bit[110]" "Disabled,Enabled"
bitfld.long 0x00 12. " [109] ,IF3 Update Enabled Bit[109]" "Disabled,Enabled"
textline " "
bitfld.long 0x00 11. " [108] ,IF3 Update Enabled Bit[108]" "Disabled,Enabled"
bitfld.long 0x00 10. " [107] ,IF3 Update Enabled Bit[107]" "Disabled,Enabled"
bitfld.long 0x00 9. " [106] ,IF3 Update Enabled Bit[106]" "Disabled,Enabled"
bitfld.long 0x00 8. " [105] ,IF3 Update Enabled Bit[105]" "Disabled,Enabled"
textline " "
bitfld.long 0x00 7. " [104] ,IF3 Update Enabled Bit[104]" "Disabled,Enabled"
bitfld.long 0x00 6. " [103] ,IF3 Update Enabled Bit[103]" "Disabled,Enabled"
bitfld.long 0x00 5. " [102] ,IF3 Update Enabled Bit[102]" "Disabled,Enabled"
bitfld.long 0x00 4. " [101] ,IF3 Update Enabled Bit[101]" "Disabled,Enabled"
textline " "
bitfld.long 0x00 3. " [100] ,IF3 Update Enabled Bit[100]" "Disabled,Enabled"
bitfld.long 0x00 2. " [99] ,IF3 Update Enabled Bit[99]" "Disabled,Enabled"
bitfld.long 0x00 1. " [98] ,IF3 Update Enabled Bit[98]" "Disabled,Enabled"
bitfld.long 0x00 0. " [97] ,IF3 Update Enabled Bit[97]" "Disabled,Enabled"
width 12.
group.long 0x1E0++0x3
line.long 0x0 "IOCTRLTX,TX IO Control Register"
bitfld.long 0x00 18. " PU ,Selection of Pull Direction" "Pull down,Pull up"
bitfld.long 0x00 17. " PD ,Pull Functionality Disable" "No,Yes"
bitfld.long 0x00 16. " OD ,Open Drain Mode" "Push pull,Open Drain"
textline " "
bitfld.long 0x00 3. " FUNC ,Functionality of Pin" "General,CAN"
bitfld.long 0x00 2. " DIR ,Direction of Pin" "Input,Output"
bitfld.long 0x00 1. " OUT ,Value to Drive to Pin if Configured for I/O" "Low,High"
textline " "
bitfld.long 0x00 0. " IN ,Value of Pin" "Low,High"
group.long 0x1E4++0x3
line.long 0x0 "IOCTRLRX,RX IO Control Register"
bitfld.long 0x00 18. " PU ,Selection of Pull Direction" "Pull down,Pull up"
bitfld.long 0x00 17. " PD ,Pull Functionality Disable" "No,Yes"
bitfld.long 0x00 16. " OD ,Open Drain Mode" "Push pull,Open Drain"
textline " "
bitfld.long 0x00 3. " FUNC ,Functionality of Pin" "General,CAN"
bitfld.long 0x00 2. " DIR ,Direction of Pin" "Input,Output"
bitfld.long 0x00 1. " OUT ,Value to Drive to Pin if Configured for I/O" "Low,High"
textline " "
bitfld.long 0x00 0. " IN ,Value of Pin" "Low,High"
width 0xb
tree.end
tree "DCAN3"
base ad:0xFFF7E000
width 12.
group.long 0x00++0x3
line.long 0x0 "CTRL,Config Register"
bitfld.long 0x00 25. " WUBA ,Automatic Wake Up on Bus Activity When in Local Power Down Mode" "Not detected,Detected"
bitfld.long 0x00 24. " PDR ,Request for Local Low Power Down Mode" "Not requested,Power down"
bitfld.long 0x00 20. " DE3 ,DMA Enable for IF3" "Disabled,Enabled"
textline " "
bitfld.long 0x00 19. " DE2 ,DMA Enable for IF2" "Disabled,Enabled"
bitfld.long 0x00 18. " DE1 ,DMA Enable for IF1" "Disabled,Enabled"
bitfld.long 0x00 17. " IE1 ,DCAN1INT Interrupt Enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 16. " INITDBG ,Internal Init State While Debug Access Mode" "No debug,Debug"
bitfld.long 0x00 15. " SWR ,SW Reset Enable" "No reset,Reset"
bitfld.long 0x00 10.--13. " PMD ,Parity on/off" "Enabled,Enabled,Enabled,Enabled,Enabled,Disabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled"
textline " "
bitfld.long 0x00 9. " ABO ,Auto Bus On Enable" "Disabled,Enabled"
bitfld.long 0x00 8. " IDS ,Interruption Debug Support Enable" "Disabled,Enabled"
bitfld.long 0x00 7. " TEST ,Test Mode Enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 6. " CCE ,Configuration Change Enable" "No write,Write"
bitfld.long 0x00 5. " DAR ,Disable Automatic Retransmission" "No,Yes"
bitfld.long 0x00 3. " EIE ,Error Interrupt Enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 2. " SIE ,Status Interrupt Enable" "Disabled,Enabled"
bitfld.long 0x00 1. " IE ,DCAN0INT Interrupt Enable" "Disabled,Enabled"
bitfld.long 0x00 0. " INIT ,Initialization" "Disabled,Enabled"
hgroup.long 0x04++0x3
hide.long 0x0 "ES,Error and Status Register"
in
width 12.
rgroup.long 0x08++0x3
line.long 0x0 "ERRC,Error Counter Register"
bitfld.long 0x00 15. " RP ,Receive Error Passive" "Below,Reached"
hexmask.long.byte 0x00 8.--14. 1. " REC[6-0] ,Receive Error Counter"
hexmask.long.byte 0x00 0.--7. 1. " TEC[7-0] ,Transmit Error Counter"
group.long 0x0C++0x3
line.long 0x0 "BTBRP,Bit Timing_BRP Extension Register"
bitfld.long 0x00 16.--19. " BRPE ,Baud Rate Prescaler Extension" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 12.--14. " TSEG2 ,The Time Segment After the Sample Point" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 8.--11. " TSEG1 ,The Time Segment Before the Sample Point" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x00 6.--7. " SJW ,Synchronization Jump Width" "0,1,2,3"
bitfld.long 0x00 0.--5. " BRP ,Baud Rate Prescaler" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
rgroup.long 0x10++0x3
line.long 0x0 "INTR,Interrupt Register"
hexmask.long.byte 0x00 16.--23. 1. " INT1ID[7-0] ,Interrupt 1 Identifier"
hexmask.long.word 0x00 0.--15. 1. " INTID[15-0] ,Interrupt Identifier"
width 12.
group.long 0x14++0x3
line.long 0x0 "TEST,Test Register"
bitfld.long 0x00 9. " RDA ,RAM Direct Access Enable" "Disabled,Enabled"
bitfld.long 0x00 8. " EXL ,External Loop Back Mode" "Disabled,Enabled"
bitfld.long 0x00 7. " RX ,Receive Pin" "Dominant,Recessive"
textline " "
bitfld.long 0x00 5.--6. " TX1-0 ,Control of CAN_TX pin" "Normal,Sample point,Dominant,Recessive"
bitfld.long 0x00 4. " LBACK ,Loop Back Mode" "Disabled,Enabled"
bitfld.long 0x00 3. " SILENT ,Silent Mode" "Disabled,Enabled"
rgroup.long 0x1C++0x3
line.long 0x0 "PERR,Parity Error Code Register"
bitfld.long 0x00 8.--10. " WORD_NUMBER ,Word Number" ",1,2,3,4,5,?..."
hexmask.long.byte 0x00 0.--7. 1. " MESSAGE_NUMBER ,Message Number"
width 19.
group.long 0x24++0x03
line.long 0x00 "DCAN_ECCDIAG, ECC Diagnostic Register"
bitfld.long 0x00 0.--3. " ECCDIAG , SECDED diagnostic mode enable/disable" ",,,,,Enabled,,,,,Disabled,?..."
group.long 0x28++0x03
line.long 0x00 "DCAN_ECCDIAG_STAT, ECC Diagnostic Status Register"
eventfld.long 0x00 8. " DEFLG_DIAG , Double bit error diagnostic" "No error,Error"
eventfld.long 0x00 0. " SEFLG_DIAG , Single bit error diagnostic" "No error,Error"
group.long 0x2C++0x03
line.long 0x00 "DCAN_ECC_CS, ECC Control and Status Register"
bitfld.long 0x00 24.--27. " SBE_EVT_EN , Single bit error event" "Enabled,Enabled,Enabled,Enabled,Enabled,Disabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled"
bitfld.long 0x00 16.--19. " ECCMODE , Single bit error correction" "Enabled,Enabled,Enabled,Enabled,Enabled,Disabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled"
eventfld.long 0x00 8. " DEFLG , Double bit error flag" "No error,Error"
eventfld.long 0x00 0. " SEFLG , Single bit error flag" "No error,Error"
rgroup.long 0x30++0x03
line.long 0x00 "DCAN_ECC_SERR, ECC Single Bit Error Code Register"
hexmask.long.byte 0x00 0.--7. 1. " Message_Number , Message object number where ECC single bit error has been detected"
group.long 0x80++0x3
line.long 0x0 "ABOT,Auto Bus On Time"
width 12.
rgroup.long 0x84++0x3
line.long 0x0 "TRREQ,Transmission Request X"
bitfld.long 0x00 14.--15. " TXRQSTREG [8] ,Transmission Request 8" "0,1,2,3"
bitfld.long 0x00 12.--13. " [7] ,Transmission Request 7" "0,1,2,3"
bitfld.long 0x00 10.--11. " [6] ,Transmission Request 6" "0,1,2,3"
bitfld.long 0x00 8.--9. " [5] ,Transmission Request 5" "0,1,2,3"
textline " "
bitfld.long 0x00 6.--7. " [4] ,Transmission Request 4" "0,1,2,3"
bitfld.long 0x00 4.--5. " [3] ,Transmission Request 3" "0,1,2,3"
bitfld.long 0x00 2.--3. " [2] ,Transmission Request 2" "0,1,2,3"
bitfld.long 0x00 0.--1. " [1] ,Transmission Request 1" "0,1,2,3"
width 12.
rgroup.long 0x88++0x3
line.long 0x0 "TRREQ21,Transmission Request 2_1"
bitfld.long 0x00 31. " TXRQST [32] ,Transmission Request Bits[32]" "Not requested,Requested"
bitfld.long 0x00 30. " [31] ,Transmission Request Bits[31]" "Not requested,Requested"
bitfld.long 0x00 29. " [30] ,Transmission Request Bits[30]" "Not requested,Requested"
bitfld.long 0x00 28. " [29] ,Transmission Request Bits[29]" "Not requested,Requested"
textline " "
bitfld.long 0x00 27. " [28] ,Transmission Request Bits[28]" "Not requested,Requested"
bitfld.long 0x00 26. " [27] ,Transmission Request Bits[27]" "Not requested,Requested"
bitfld.long 0x00 25. " [26] ,Transmission Request Bits[26]" "Not requested,Requested"
bitfld.long 0x00 24. " [25] ,Transmission Request Bits[25]" "Not requested,Requested"
textline " "
bitfld.long 0x00 23. " [24] ,Transmission Request Bits[24]" "Not requested,Requested"
bitfld.long 0x00 22. " [23] ,Transmission Request Bits[23]" "Not requested,Requested"
bitfld.long 0x00 21. " [22] ,Transmission Request Bits[22]" "Not requested,Requested"
bitfld.long 0x00 20. " [21] ,Transmission Request Bits[21]" "Not requested,Requested"
textline " "
bitfld.long 0x00 19. " [20] ,Transmission Request Bits[20]" "Not requested,Requested"
bitfld.long 0x00 18. " [19] ,Transmission Request Bits[19]" "Not requested,Requested"
bitfld.long 0x00 17. " [18] ,Transmission Request Bits[18]" "Not requested,Requested"
bitfld.long 0x00 16. " [17] ,Transmission Request Bits[17]" "Not requested,Requested"
textline " "
bitfld.long 0x00 15. " [16] ,Transmission Request Bits[16]" "Not requested,Requested"
bitfld.long 0x00 14. " [15] ,Transmission Request Bits[15]" "Not requested,Requested"
bitfld.long 0x00 13. " [14] ,Transmission Request Bits[14]" "Not requested,Requested"
bitfld.long 0x00 12. " [13] ,Transmission Request Bits[13]" "Not requested,Requested"
textline " "
bitfld.long 0x00 11. " [12] ,Transmission Request Bits[12]" "Not requested,Requested"
bitfld.long 0x00 10. " [11] ,Transmission Request Bits[11]" "Not requested,Requested"
bitfld.long 0x00 9. " [10] ,Transmission Request Bits[10]" "Not requested,Requested"
bitfld.long 0x00 8. " [9] ,Transmission Request Bits[9]" "Not requested,Requested"
textline " "
bitfld.long 0x00 7. " [8] ,Transmission Request Bits[8]" "Not requested,Requested"
bitfld.long 0x00 6. " [7] ,Transmission Request Bits[7]" "Not requested,Requested"
bitfld.long 0x00 5. " [6] ,Transmission Request Bits[6]" "Not requested,Requested"
bitfld.long 0x00 4. " [5] ,Transmission Request Bits[5]" "Not requested,Requested"
textline " "
bitfld.long 0x00 3. " [4] ,Transmission Request Bits[4]" "Not requested,Requested"
bitfld.long 0x00 2. " [3] ,Transmission Request Bits[3]" "Not requested,Requested"
bitfld.long 0x00 1. " [2] ,Transmission Request Bits[2]" "Not requested,Requested"
bitfld.long 0x00 0. " [1] ,Transmission Request Bits[1]" "Not requested,Requested"
rgroup.long 0x8C++0x3
line.long 0x0 "TRREQ43,Transmission Request 4_3"
bitfld.long 0x00 31. " TXRQST [64] ,Transmission Request Bits[64]" "Not requested,Requested"
bitfld.long 0x00 30. " [63] ,Transmission Request Bits[63]" "Not requested,Requested"
bitfld.long 0x00 29. " [62] ,Transmission Request Bits[62]" "Not requested,Requested"
bitfld.long 0x00 28. " [61] ,Transmission Request Bits[61]" "Not requested,Requested"
textline " "
bitfld.long 0x00 27. " [60] ,Transmission Request Bits[60]" "Not requested,Requested"
bitfld.long 0x00 26. " [59] ,Transmission Request Bits[59]" "Not requested,Requested"
bitfld.long 0x00 25. " [58] ,Transmission Request Bits[58]" "Not requested,Requested"
bitfld.long 0x00 24. " [57] ,Transmission Request Bits[57]" "Not requested,Requested"
textline " "
bitfld.long 0x00 23. " [56] ,Transmission Request Bits[56]" "Not requested,Requested"
bitfld.long 0x00 22. " [55] ,Transmission Request Bits[55]" "Not requested,Requested"
bitfld.long 0x00 21. " [54] ,Transmission Request Bits[54]" "Not requested,Requested"
bitfld.long 0x00 20. " [53] ,Transmission Request Bits[53]" "Not requested,Requested"
textline " "
bitfld.long 0x00 19. " [52] ,Transmission Request Bits[52]" "Not requested,Requested"
bitfld.long 0x00 18. " [51] ,Transmission Request Bits[51]" "Not requested,Requested"
bitfld.long 0x00 17. " [50] ,Transmission Request Bits[50]" "Not requested,Requested"
bitfld.long 0x00 16. " [49] ,Transmission Request Bits[49]" "Not requested,Requested"
textline " "
bitfld.long 0x00 15. " [48] ,Transmission Request Bits[48]" "Not requested,Requested"
bitfld.long 0x00 14. " [47] ,Transmission Request Bits[47]" "Not requested,Requested"
bitfld.long 0x00 13. " [46] ,Transmission Request Bits[46]" "Not requested,Requested"
bitfld.long 0x00 12. " [45] ,Transmission Request Bits[45]" "Not requested,Requested"
textline " "
bitfld.long 0x00 11. " [44] ,Transmission Request Bits[44]" "Not requested,Requested"
bitfld.long 0x00 10. " [43] ,Transmission Request Bits[43]" "Not requested,Requested"
bitfld.long 0x00 9. " [42] ,Transmission Request Bits[42]" "Not requested,Requested"
bitfld.long 0x00 8. " [41] ,Transmission Request Bits[41]" "Not requested,Requested"
textline " "
bitfld.long 0x00 7. " [40] ,Transmission Request Bits[40]" "Not requested,Requested"
bitfld.long 0x00 6. " [39] ,Transmission Request Bits[39]" "Not requested,Requested"
bitfld.long 0x00 5. " [38] ,Transmission Request Bits[38]" "Not requested,Requested"
bitfld.long 0x00 4. " [37] ,Transmission Request Bits[37]" "Not requested,Requested"
textline " "
bitfld.long 0x00 3. " [36] ,Transmission Request Bits[36]" "Not requested,Requested"
bitfld.long 0x00 2. " [35] ,Transmission Request Bits[35]" "Not requested,Requested"
bitfld.long 0x00 1. " [34] ,Transmission Request Bits[34]" "Not requested,Requested"
bitfld.long 0x00 0. " [33] ,Transmission Request Bits[33]" "Not requested,Requested"
rgroup.long 0x90++0x3
line.long 0x0 "TRREQ65,Transmission Request 6_5"
bitfld.long 0x00 31. " TXRQST [96] ,Transmission Request Bits[96]" "Not requested,Requested"
bitfld.long 0x00 30. " [95] ,Transmission Request Bits[95]" "Not requested,Requested"
bitfld.long 0x00 29. " [94] ,Transmission Request Bits[94]" "Not requested,Requested"
bitfld.long 0x00 28. " [93] ,Transmission Request Bits[93]" "Not requested,Requested"
textline " "
bitfld.long 0x00 27. " [92] ,Transmission Request Bits[92]" "Not requested,Requested"
bitfld.long 0x00 26. " [91] ,Transmission Request Bits[91]" "Not requested,Requested"
bitfld.long 0x00 25. " [90] ,Transmission Request Bits[90]" "Not requested,Requested"
bitfld.long 0x00 24. " [89] ,Transmission Request Bits[89]" "Not requested,Requested"
textline " "
bitfld.long 0x00 23. " [88] ,Transmission Request Bits[88]" "Not requested,Requested"
bitfld.long 0x00 22. " [87] ,Transmission Request Bits[87]" "Not requested,Requested"
bitfld.long 0x00 21. " [86] ,Transmission Request Bits[86]" "Not requested,Requested"
bitfld.long 0x00 20. " [85] ,Transmission Request Bits[85]" "Not requested,Requested"
textline " "
bitfld.long 0x00 19. " [84] ,Transmission Request Bits[84]" "Not requested,Requested"
bitfld.long 0x00 18. " [83] ,Transmission Request Bits[83]" "Not requested,Requested"
bitfld.long 0x00 17. " [82] ,Transmission Request Bits[82]" "Not requested,Requested"
bitfld.long 0x00 16. " [81] ,Transmission Request Bits[81]" "Not requested,Requested"
textline " "
bitfld.long 0x00 15. " [80] ,Transmission Request Bits[80]" "Not requested,Requested"
bitfld.long 0x00 14. " [79] ,Transmission Request Bits[79]" "Not requested,Requested"
bitfld.long 0x00 13. " [78] ,Transmission Request Bits[78]" "Not requested,Requested"
bitfld.long 0x00 12. " [77] ,Transmission Request Bits[77]" "Not requested,Requested"
textline " "
bitfld.long 0x00 11. " [76] ,Transmission Request Bits[76]" "Not requested,Requested"
bitfld.long 0x00 10. " [75] ,Transmission Request Bits[75]" "Not requested,Requested"
bitfld.long 0x00 9. " [74] ,Transmission Request Bits[74]" "Not requested,Requested"
bitfld.long 0x00 8. " [73] ,Transmission Request Bits[73]" "Not requested,Requested"
textline " "
bitfld.long 0x00 7. " [72] ,Transmission Request Bits[72]" "Not requested,Requested"
bitfld.long 0x00 6. " [71] ,Transmission Request Bits[71]" "Not requested,Requested"
bitfld.long 0x00 5. " [70] ,Transmission Request Bits[70]" "Not requested,Requested"
bitfld.long 0x00 4. " [69] ,Transmission Request Bits[69]" "Not requested,Requested"
textline " "
bitfld.long 0x00 3. " [68] ,Transmission Request Bits[68]" "Not requested,Requested"
bitfld.long 0x00 2. " [67] ,Transmission Request Bits[67]" "Not requested,Requested"
bitfld.long 0x00 1. " [66] ,Transmission Request Bits[66]" "Not requested,Requested"
bitfld.long 0x00 0. " [65] ,Transmission Request Bits[65]" "Not requested,Requested"
rgroup.long 0x94++0x3
line.long 0x0 "TRREQ87,Transmission Request 8_7"
bitfld.long 0x00 31. " TXRQST [128] ,Transmission Request Bits[128]" "Not requested,Requested"
bitfld.long 0x00 30. " [127] ,Transmission Request Bits[127]" "Not requested,Requested"
bitfld.long 0x00 29. " [126] ,Transmission Request Bits[126]" "Not requested,Requested"
bitfld.long 0x00 28. " [125] ,Transmission Request Bits[125]" "Not requested,Requested"
textline " "
bitfld.long 0x00 27. " [124] ,Transmission Request Bits[124]" "Not requested,Requested"
bitfld.long 0x00 26. " [123] ,Transmission Request Bits[123]" "Not requested,Requested"
bitfld.long 0x00 25. " [122] ,Transmission Request Bits[122]" "Not requested,Requested"
bitfld.long 0x00 24. " [121] ,Transmission Request Bits[121]" "Not requested,Requested"
textline " "
bitfld.long 0x00 23. " [120] ,Transmission Request Bits[120]" "Not requested,Requested"
bitfld.long 0x00 22. " [119] ,Transmission Request Bits[119]" "Not requested,Requested"
bitfld.long 0x00 21. " [118] ,Transmission Request Bits[118]" "Not requested,Requested"
bitfld.long 0x00 20. " [117] ,Transmission Request Bits[117]" "Not requested,Requested"
textline " "
bitfld.long 0x00 19. " [116] ,Transmission Request Bits[116]" "Not requested,Requested"
bitfld.long 0x00 18. " [115] ,Transmission Request Bits[115]" "Not requested,Requested"
bitfld.long 0x00 17. " [114] ,Transmission Request Bits[114]" "Not requested,Requested"
bitfld.long 0x00 16. " [113] ,Transmission Request Bits[113]" "Not requested,Requested"
textline " "
bitfld.long 0x00 15. " [112] ,Transmission Request Bits[112]" "Not requested,Requested"
bitfld.long 0x00 14. " [111] ,Transmission Request Bits[111]" "Not requested,Requested"
bitfld.long 0x00 13. " [110] ,Transmission Request Bits[110]" "Not requested,Requested"
bitfld.long 0x00 12. " [109] ,Transmission Request Bits[109]" "Not requested,Requested"
textline " "
bitfld.long 0x00 11. " [108] ,Transmission Request Bits[108]" "Not requested,Requested"
bitfld.long 0x00 10. " [107] ,Transmission Request Bits[107]" "Not requested,Requested"
bitfld.long 0x00 9. " [106] ,Transmission Request Bits[106]" "Not requested,Requested"
bitfld.long 0x00 8. " [105] ,Transmission Request Bits[105]" "Not requested,Requested"
textline " "
bitfld.long 0x00 7. " [104] ,Transmission Request Bits[104]" "Not requested,Requested"
bitfld.long 0x00 6. " [103] ,Transmission Request Bits[103]" "Not requested,Requested"
bitfld.long 0x00 5. " [102] ,Transmission Request Bits[102]" "Not requested,Requested"
bitfld.long 0x00 4. " [101] ,Transmission Request Bits[101]" "Not requested,Requested"
textline " "
bitfld.long 0x00 3. " [100] ,Transmission Request Bits[100]" "Not requested,Requested"
bitfld.long 0x00 2. " [99] ,Transmission Request Bits[99]" "Not requested,Requested"
bitfld.long 0x00 1. " [98] ,Transmission Request Bits[98]" "Not requested,Requested"
bitfld.long 0x00 0. " [97] ,Transmission Request Bits[97]" "Not requested,Requested"
width 12.
rgroup.long 0x98++0x3
line.long 0x0 "NEWDAT,New Data X"
bitfld.long 0x00 14.--15. " NEWDATREG [8] ,New Data 8" "0,1,2,3"
bitfld.long 0x00 12.--13. " [7] ,New Data 7" "0,1,2,3"
bitfld.long 0x00 10.--11. " [6] ,New Data 6" "0,1,2,3"
bitfld.long 0x00 8.--9. " [5] ,New Data 5" "0,1,2,3"
textline " "
bitfld.long 0x00 6.--7. " [4] ,New Data 4" "0,1,2,3"
bitfld.long 0x00 4.--5. " [3] ,New Data 3" "0,1,2,3"
bitfld.long 0x00 2.--3. " [2] ,New Data 2" "0,1,2,3"
bitfld.long 0x00 0.--1. " [1] ,New Data 1" "0,1,2,3"
width 12.
rgroup.long 0x9C++0x3
line.long 0x0 "NEWDAT21,New Data 2_1"
bitfld.long 0x00 31. " NEWDAT [32] ,New Data Bit[32]" "Not requested,Requested"
bitfld.long 0x00 30. " [31] ,New Data Bit[31]" "Not requested,Requested"
bitfld.long 0x00 29. " [30] ,New Data Bit[30]" "Not requested,Requested"
bitfld.long 0x00 28. " [29] ,New Data Bit[29]" "Not requested,Requested"
textline " "
bitfld.long 0x00 27. " [28] ,New Data Bit[28]" "Not requested,Requested"
bitfld.long 0x00 26. " [27] ,New Data Bit[27]" "Not requested,Requested"
bitfld.long 0x00 25. " [26] ,New Data Bit[26]" "Not requested,Requested"
bitfld.long 0x00 24. " [25] ,New Data Bit[25]" "Not requested,Requested"
textline " "
bitfld.long 0x00 23. " [24] ,New Data Bit[24]" "Not requested,Requested"
bitfld.long 0x00 22. " [23] ,New Data Bit[23]" "Not requested,Requested"
bitfld.long 0x00 21. " [22] ,New Data Bit[22]" "Not requested,Requested"
bitfld.long 0x00 20. " [21] ,New Data Bit[21]" "Not requested,Requested"
textline " "
bitfld.long 0x00 19. " [20] ,New Data Bit[20]" "Not requested,Requested"
bitfld.long 0x00 18. " [19] ,New Data Bit[19]" "Not requested,Requested"
bitfld.long 0x00 17. " [18] ,New Data Bit[18]" "Not requested,Requested"
bitfld.long 0x00 16. " [17] ,New Data Bit[17]" "Not requested,Requested"
textline " "
bitfld.long 0x00 15. " [16] ,New Data Bit[16]" "Not requested,Requested"
bitfld.long 0x00 14. " [15] ,New Data Bit[15]" "Not requested,Requested"
bitfld.long 0x00 13. " [14] ,New Data Bit[14]" "Not requested,Requested"
bitfld.long 0x00 12. " [13] ,New Data Bit[13]" "Not requested,Requested"
textline " "
bitfld.long 0x00 11. " [12] ,New Data Bit[12]" "Not requested,Requested"
bitfld.long 0x00 10. " [11] ,New Data Bit[11]" "Not requested,Requested"
bitfld.long 0x00 9. " [10] ,New Data Bit[10]" "Not requested,Requested"
bitfld.long 0x00 8. " [9] ,New Data Bit[9]" "Not requested,Requested"
textline " "
bitfld.long 0x00 7. " [8] ,New Data Bit[8]" "Not requested,Requested"
bitfld.long 0x00 6. " [7] ,New Data Bit[7]" "Not requested,Requested"
bitfld.long 0x00 5. " [6] ,New Data Bit[6]" "Not requested,Requested"
bitfld.long 0x00 4. " [5] ,New Data Bit[5]" "Not requested,Requested"
textline " "
bitfld.long 0x00 3. " [4] ,New Data Bit[4]" "Not requested,Requested"
bitfld.long 0x00 2. " [3] ,New Data Bit[3]" "Not requested,Requested"
bitfld.long 0x00 1. " [2] ,New Data Bit[2]" "Not requested,Requested"
bitfld.long 0x00 0. " [1] ,New Data Bit[1]" "Not requested,Requested"
rgroup.long 0xA0++0x3
line.long 0x0 "NEWDAT43,New Data 4_3"
bitfld.long 0x00 31. " NEWDAT [64] ,New Data Bit[64]" "Not requested,Requested"
bitfld.long 0x00 30. " [63] ,New Data Bit[63]" "Not requested,Requested"
bitfld.long 0x00 29. " [62] ,New Data Bit[62]" "Not requested,Requested"
bitfld.long 0x00 28. " [61] ,New Data Bit[61]" "Not requested,Requested"
textline " "
bitfld.long 0x00 27. " [60] ,New Data Bit[60]" "Not requested,Requested"
bitfld.long 0x00 26. " [59] ,New Data Bit[59]" "Not requested,Requested"
bitfld.long 0x00 25. " [58] ,New Data Bit[58]" "Not requested,Requested"
bitfld.long 0x00 24. " [57] ,New Data Bit[57]" "Not requested,Requested"
textline " "
bitfld.long 0x00 23. " [56] ,New Data Bit[56]" "Not requested,Requested"
bitfld.long 0x00 22. " [55] ,New Data Bit[55]" "Not requested,Requested"
bitfld.long 0x00 21. " [54] ,New Data Bit[54]" "Not requested,Requested"
bitfld.long 0x00 20. " [53] ,New Data Bit[53]" "Not requested,Requested"
textline " "
bitfld.long 0x00 19. " [52] ,New Data Bit[52]" "Not requested,Requested"
bitfld.long 0x00 18. " [51] ,New Data Bit[51]" "Not requested,Requested"
bitfld.long 0x00 17. " [50] ,New Data Bit[50]" "Not requested,Requested"
bitfld.long 0x00 16. " [49] ,New Data Bit[49]" "Not requested,Requested"
textline " "
bitfld.long 0x00 15. " [48] ,New Data Bit[48]" "Not requested,Requested"
bitfld.long 0x00 14. " [47] ,New Data Bit[47]" "Not requested,Requested"
bitfld.long 0x00 13. " [46] ,New Data Bit[46]" "Not requested,Requested"
bitfld.long 0x00 12. " [45] ,New Data Bit[45]" "Not requested,Requested"
textline " "
bitfld.long 0x00 11. " [44] ,New Data Bit[44]" "Not requested,Requested"
bitfld.long 0x00 10. " [43] ,New Data Bit[43]" "Not requested,Requested"
bitfld.long 0x00 9. " [42] ,New Data Bit[42]" "Not requested,Requested"
bitfld.long 0x00 8. " [41] ,New Data Bit[41]" "Not requested,Requested"
textline " "
bitfld.long 0x00 7. " [40] ,New Data Bit[40]" "Not requested,Requested"
bitfld.long 0x00 6. " [39] ,New Data Bit[39]" "Not requested,Requested"
bitfld.long 0x00 5. " [38] ,New Data Bit[38]" "Not requested,Requested"
bitfld.long 0x00 4. " [37] ,New Data Bit[37]" "Not requested,Requested"
textline " "
bitfld.long 0x00 3. " [36] ,New Data Bit[36]" "Not requested,Requested"
bitfld.long 0x00 2. " [35] ,New Data Bit[35]" "Not requested,Requested"
bitfld.long 0x00 1. " [34] ,New Data Bit[34]" "Not requested,Requested"
bitfld.long 0x00 0. " [33] ,New Data Bit[33]" "Not requested,Requested"
rgroup.long 0xA4++0x3
line.long 0x0 "NEWDAT65,New Data 6_5"
bitfld.long 0x00 31. " NEWDAT [96] ,New Data Bit[96]" "Not requested,Requested"
bitfld.long 0x00 30. " [95] ,New Data Bit[95]" "Not requested,Requested"
bitfld.long 0x00 29. " [94] ,New Data Bit[94]" "Not requested,Requested"
bitfld.long 0x00 28. " [93] ,New Data Bit[93]" "Not requested,Requested"
textline " "
bitfld.long 0x00 27. " [92] ,New Data Bit[92]" "Not requested,Requested"
bitfld.long 0x00 26. " [91] ,New Data Bit[91]" "Not requested,Requested"
bitfld.long 0x00 25. " [90] ,New Data Bit[90]" "Not requested,Requested"
bitfld.long 0x00 24. " [89] ,New Data Bit[89]" "Not requested,Requested"
textline " "
bitfld.long 0x00 23. " [88] ,New Data Bit[88]" "Not requested,Requested"
bitfld.long 0x00 22. " [87] ,New Data Bit[87]" "Not requested,Requested"
bitfld.long 0x00 21. " [86] ,New Data Bit[86]" "Not requested,Requested"
bitfld.long 0x00 20. " [85] ,New Data Bit[85]" "Not requested,Requested"
textline " "
bitfld.long 0x00 19. " [84] ,New Data Bit[84]" "Not requested,Requested"
bitfld.long 0x00 18. " [83] ,New Data Bit[83]" "Not requested,Requested"
bitfld.long 0x00 17. " [82] ,New Data Bit[82]" "Not requested,Requested"
bitfld.long 0x00 16. " [81] ,New Data Bit[81]" "Not requested,Requested"
textline " "
bitfld.long 0x00 15. " [80] ,New Data Bit[80]" "Not requested,Requested"
bitfld.long 0x00 14. " [79] ,New Data Bit[79]" "Not requested,Requested"
bitfld.long 0x00 13. " [78] ,New Data Bit[78]" "Not requested,Requested"
bitfld.long 0x00 12. " [77] ,New Data Bit[77]" "Not requested,Requested"
textline " "
bitfld.long 0x00 11. " [76] ,New Data Bit[76]" "Not requested,Requested"
bitfld.long 0x00 10. " [75] ,New Data Bit[75]" "Not requested,Requested"
bitfld.long 0x00 9. " [74] ,New Data Bit[74]" "Not requested,Requested"
bitfld.long 0x00 8. " [73] ,New Data Bit[73]" "Not requested,Requested"
textline " "
bitfld.long 0x00 7. " [72] ,New Data Bit[72]" "Not requested,Requested"
bitfld.long 0x00 6. " [71] ,New Data Bit[71]" "Not requested,Requested"
bitfld.long 0x00 5. " [70] ,New Data Bit[70]" "Not requested,Requested"
bitfld.long 0x00 4. " [69] ,New Data Bit[69]" "Not requested,Requested"
textline " "
bitfld.long 0x00 3. " [68] ,New Data Bit[68]" "Not requested,Requested"
bitfld.long 0x00 2. " [67] ,New Data Bit[67]" "Not requested,Requested"
bitfld.long 0x00 1. " [66] ,New Data Bit[66]" "Not requested,Requested"
bitfld.long 0x00 0. " [65] ,New Data Bit[65]" "Not requested,Requested"
rgroup.long 0xA8++0x3
line.long 0x0 "NEWDAT87,New Data 8_7"
bitfld.long 0x00 31. " NEWDAT [128] ,New Data Bit[128]" "Not requested,Requested"
bitfld.long 0x00 30. " [127] ,New Data Bit[127]" "Not requested,Requested"
bitfld.long 0x00 29. " [126] ,New Data Bit[126]" "Not requested,Requested"
bitfld.long 0x00 28. " [125] ,New Data Bit[125]" "Not requested,Requested"
textline " "
bitfld.long 0x00 27. " [124] ,New Data Bit[124]" "Not requested,Requested"
bitfld.long 0x00 26. " [123] ,New Data Bit[123]" "Not requested,Requested"
bitfld.long 0x00 25. " [122] ,New Data Bit[122]" "Not requested,Requested"
bitfld.long 0x00 24. " [121] ,New Data Bit[121]" "Not requested,Requested"
textline " "
bitfld.long 0x00 23. " [120] ,New Data Bit[120]" "Not requested,Requested"
bitfld.long 0x00 22. " [119] ,New Data Bit[119]" "Not requested,Requested"
bitfld.long 0x00 21. " [118] ,New Data Bit[118]" "Not requested,Requested"
bitfld.long 0x00 20. " [117] ,New Data Bit[117]" "Not requested,Requested"
textline " "
bitfld.long 0x00 19. " [116] ,New Data Bit[116]" "Not requested,Requested"
bitfld.long 0x00 18. " [115] ,New Data Bit[115]" "Not requested,Requested"
bitfld.long 0x00 17. " [114] ,New Data Bit[114]" "Not requested,Requested"
bitfld.long 0x00 16. " [113] ,New Data Bit[113]" "Not requested,Requested"
textline " "
bitfld.long 0x00 15. " [112] ,New Data Bit[112]" "Not requested,Requested"
bitfld.long 0x00 14. " [111] ,New Data Bit[111]" "Not requested,Requested"
bitfld.long 0x00 13. " [110] ,New Data Bit[110]" "Not requested,Requested"
bitfld.long 0x00 12. " [109] ,New Data Bit[109]" "Not requested,Requested"
textline " "
bitfld.long 0x00 11. " [108] ,New Data Bit[108]" "Not requested,Requested"
bitfld.long 0x00 10. " [107] ,New Data Bit[107]" "Not requested,Requested"
bitfld.long 0x00 9. " [106] ,New Data Bit[106]" "Not requested,Requested"
bitfld.long 0x00 8. " [105] ,New Data Bit[105]" "Not requested,Requested"
textline " "
bitfld.long 0x00 7. " [104] ,New Data Bit[104]" "Not requested,Requested"
bitfld.long 0x00 6. " [103] ,New Data Bit[103]" "Not requested,Requested"
bitfld.long 0x00 5. " [102] ,New Data Bit[102]" "Not requested,Requested"
bitfld.long 0x00 4. " [101] ,New Data Bit[101]" "Not requested,Requested"
textline " "
bitfld.long 0x00 3. " [100] ,New Data Bit[100]" "Not requested,Requested"
bitfld.long 0x00 2. " [99] ,New Data Bit[99]" "Not requested,Requested"
bitfld.long 0x00 1. " [98] ,New Data Bit[98]" "Not requested,Requested"
bitfld.long 0x00 0. " [97] ,New Data Bit[97]" "Not requested,Requested"
width 12.
rgroup.long 0xAC++0x3
line.long 0x0 "INTPEN,Interrupt Pending X"
bitfld.long 0x00 14.--15. " INTPENDREG [8] ,Interrupt Pending 8" "0,1,2,3"
bitfld.long 0x00 12.--13. " [7] ,Interrupt Pending 7" "0,1,2,3"
bitfld.long 0x00 10.--11. " [6] ,Interrupt Pending 6" "0,1,2,3"
bitfld.long 0x00 8.--9. " [5] ,Interrupt Pending 5" "0,1,2,3"
textline " "
bitfld.long 0x00 6.--7. " [4] ,Interrupt Pending 4" "0,1,2,3"
bitfld.long 0x00 4.--5. " [3] ,Interrupt Pending 3" "0,1,2,3"
bitfld.long 0x00 2.--3. " [2] ,Interrupt Pending 2" "0,1,2,3"
bitfld.long 0x00 0.--1. " [1] ,Interrupt Pending 1" "0,1,2,3"
width 12.
rgroup.long 0xB0++0x3
line.long 0x0 "INTPEN21,Interrupt Pending 2_1"
bitfld.long 0x00 31. " INTPND [32] ,Interrupt Pending Bit[32]" "No interrupt,Interrupt"
bitfld.long 0x00 30. " [31] ,Interrupt Pending Bit[31]" "No interrupt,Interrupt"
bitfld.long 0x00 29. " [30] ,Interrupt Pending Bit[30]" "No interrupt,Interrupt"
bitfld.long 0x00 28. " [29] ,Interrupt Pending Bit[29]" "No interrupt,Interrupt"
textline " "
bitfld.long 0x00 27. " [28] ,Interrupt Pending Bit[28]" "No interrupt,Interrupt"
bitfld.long 0x00 26. " [27] ,Interrupt Pending Bit[27]" "No interrupt,Interrupt"
bitfld.long 0x00 25. " [26] ,Interrupt Pending Bit[26]" "No interrupt,Interrupt"
bitfld.long 0x00 24. " [25] ,Interrupt Pending Bit[25]" "No interrupt,Interrupt"
textline " "
bitfld.long 0x00 23. " [24] ,Interrupt Pending Bit[24]" "No interrupt,Interrupt"
bitfld.long 0x00 22. " [23] ,Interrupt Pending Bit[23]" "No interrupt,Interrupt"
bitfld.long 0x00 21. " [22] ,Interrupt Pending Bit[22]" "No interrupt,Interrupt"
bitfld.long 0x00 20. " [21] ,Interrupt Pending Bit[21]" "No interrupt,Interrupt"
textline " "
bitfld.long 0x00 19. " [20] ,Interrupt Pending Bit[20]" "No interrupt,Interrupt"
bitfld.long 0x00 18. " [19] ,Interrupt Pending Bit[19]" "No interrupt,Interrupt"
bitfld.long 0x00 17. " [18] ,Interrupt Pending Bit[18]" "No interrupt,Interrupt"
bitfld.long 0x00 16. " [17] ,Interrupt Pending Bit[17]" "No interrupt,Interrupt"
textline " "
bitfld.long 0x00 15. " [16] ,Interrupt Pending Bit[16]" "No interrupt,Interrupt"
bitfld.long 0x00 14. " [15] ,Interrupt Pending Bit[15]" "No interrupt,Interrupt"
bitfld.long 0x00 13. " [14] ,Interrupt Pending Bit[14]" "No interrupt,Interrupt"
bitfld.long 0x00 12. " [13] ,Interrupt Pending Bit[13]" "No interrupt,Interrupt"
textline " "
bitfld.long 0x00 11. " [12] ,Interrupt Pending Bit[12]" "No interrupt,Interrupt"
bitfld.long 0x00 10. " [11] ,Interrupt Pending Bit[11]" "No interrupt,Interrupt"
bitfld.long 0x00 9. " [10] ,Interrupt Pending Bit[10]" "No interrupt,Interrupt"
bitfld.long 0x00 8. " [9] ,Interrupt Pending Bit[9]" "No interrupt,Interrupt"
textline " "
bitfld.long 0x00 7. " [8] ,Interrupt Pending Bit[8]" "No interrupt,Interrupt"
bitfld.long 0x00 6. " [7] ,Interrupt Pending Bit[7]" "No interrupt,Interrupt"
bitfld.long 0x00 5. " [6] ,Interrupt Pending Bit[6]" "No interrupt,Interrupt"
bitfld.long 0x00 4. " [5] ,Interrupt Pending Bit[5]" "No interrupt,Interrupt"
textline " "
bitfld.long 0x00 3. " [4] ,Interrupt Pending Bit[4]" "No interrupt,Interrupt"
bitfld.long 0x00 2. " [3] ,Interrupt Pending Bit[3]" "No interrupt,Interrupt"
bitfld.long 0x00 1. " [2] ,Interrupt Pending Bit[2]" "No interrupt,Interrupt"
bitfld.long 0x00 0. " [1] ,Interrupt Pending Bit[1]" "No interrupt,Interrupt"
rgroup.long 0xB4++0x3
line.long 0x0 "INTPEN43,Interrupt Pending 4_3"
bitfld.long 0x00 31. " INTPND [64] ,Interrupt Pending Bit[64]" "No interrupt,Interrupt"
bitfld.long 0x00 30. " [63] ,Interrupt Pending Bit[63]" "No interrupt,Interrupt"
bitfld.long 0x00 29. " [62] ,Interrupt Pending Bit[62]" "No interrupt,Interrupt"
bitfld.long 0x00 28. " [61] ,Interrupt Pending Bit[61]" "No interrupt,Interrupt"
textline " "
bitfld.long 0x00 27. " [60] ,Interrupt Pending Bit[60]" "No interrupt,Interrupt"
bitfld.long 0x00 26. " [59] ,Interrupt Pending Bit[59]" "No interrupt,Interrupt"
bitfld.long 0x00 25. " [58] ,Interrupt Pending Bit[58]" "No interrupt,Interrupt"
bitfld.long 0x00 24. " [57] ,Interrupt Pending Bit[57]" "No interrupt,Interrupt"
textline " "
bitfld.long 0x00 23. " [56] ,Interrupt Pending Bit[56]" "No interrupt,Interrupt"
bitfld.long 0x00 22. " [55] ,Interrupt Pending Bit[55]" "No interrupt,Interrupt"
bitfld.long 0x00 21. " [54] ,Interrupt Pending Bit[54]" "No interrupt,Interrupt"
bitfld.long 0x00 20. " [53] ,Interrupt Pending Bit[53]" "No interrupt,Interrupt"
textline " "
bitfld.long 0x00 19. " [52] ,Interrupt Pending Bit[52]" "No interrupt,Interrupt"
bitfld.long 0x00 18. " [51] ,Interrupt Pending Bit[51]" "No interrupt,Interrupt"
bitfld.long 0x00 17. " [50] ,Interrupt Pending Bit[50]" "No interrupt,Interrupt"
bitfld.long 0x00 16. " [49] ,Interrupt Pending Bit[49]" "No interrupt,Interrupt"
textline " "
bitfld.long 0x00 15. " [48] ,Interrupt Pending Bit[48]" "No interrupt,Interrupt"
bitfld.long 0x00 14. " [47] ,Interrupt Pending Bit[47]" "No interrupt,Interrupt"
bitfld.long 0x00 13. " [46] ,Interrupt Pending Bit[46]" "No interrupt,Interrupt"
bitfld.long 0x00 12. " [45] ,Interrupt Pending Bit[45]" "No interrupt,Interrupt"
textline " "
bitfld.long 0x00 11. " [44] ,Interrupt Pending Bit[44]" "No interrupt,Interrupt"
bitfld.long 0x00 10. " [43] ,Interrupt Pending Bit[43]" "No interrupt,Interrupt"
bitfld.long 0x00 9. " [42] ,Interrupt Pending Bit[42]" "No interrupt,Interrupt"
bitfld.long 0x00 8. " [41] ,Interrupt Pending Bit[41]" "No interrupt,Interrupt"
textline " "
bitfld.long 0x00 7. " [40] ,Interrupt Pending Bit[40]" "No interrupt,Interrupt"
bitfld.long 0x00 6. " [39] ,Interrupt Pending Bit[39]" "No interrupt,Interrupt"
bitfld.long 0x00 5. " [38] ,Interrupt Pending Bit[38]" "No interrupt,Interrupt"
bitfld.long 0x00 4. " [37] ,Interrupt Pending Bit[37]" "No interrupt,Interrupt"
textline " "
bitfld.long 0x00 3. " [36] ,Interrupt Pending Bit[36]" "No interrupt,Interrupt"
bitfld.long 0x00 2. " [35] ,Interrupt Pending Bit[35]" "No interrupt,Interrupt"
bitfld.long 0x00 1. " [34] ,Interrupt Pending Bit[34]" "No interrupt,Interrupt"
bitfld.long 0x00 0. " [33] ,Interrupt Pending Bit[33]" "No interrupt,Interrupt"
rgroup.long 0xB8++0x3
line.long 0x0 "INTPEN65,Interrupt Pending 6_5"
bitfld.long 0x00 31. " INTPND [96] ,Interrupt Pending Bit[96]" "No interrupt,Interrupt"
bitfld.long 0x00 30. " [95] ,Interrupt Pending Bit[95]" "No interrupt,Interrupt"
bitfld.long 0x00 29. " [94] ,Interrupt Pending Bit[94]" "No interrupt,Interrupt"
bitfld.long 0x00 28. " [93] ,Interrupt Pending Bit[93]" "No interrupt,Interrupt"
textline " "
bitfld.long 0x00 27. " [92] ,Interrupt Pending Bit[92]" "No interrupt,Interrupt"
bitfld.long 0x00 26. " [91] ,Interrupt Pending Bit[91]" "No interrupt,Interrupt"
bitfld.long 0x00 25. " [90] ,Interrupt Pending Bit[90]" "No interrupt,Interrupt"
bitfld.long 0x00 24. " [89] ,Interrupt Pending Bit[89]" "No interrupt,Interrupt"
textline " "
bitfld.long 0x00 23. " [88] ,Interrupt Pending Bit[88]" "No interrupt,Interrupt"
bitfld.long 0x00 22. " [87] ,Interrupt Pending Bit[87]" "No interrupt,Interrupt"
bitfld.long 0x00 21. " [86] ,Interrupt Pending Bit[86]" "No interrupt,Interrupt"
bitfld.long 0x00 20. " [85] ,Interrupt Pending Bit[85]" "No interrupt,Interrupt"
textline " "
bitfld.long 0x00 19. " [84] ,Interrupt Pending Bit[84]" "No interrupt,Interrupt"
bitfld.long 0x00 18. " [83] ,Interrupt Pending Bit[83]" "No interrupt,Interrupt"
bitfld.long 0x00 17. " [82] ,Interrupt Pending Bit[82]" "No interrupt,Interrupt"
bitfld.long 0x00 16. " [81] ,Interrupt Pending Bit[81]" "No interrupt,Interrupt"
textline " "
bitfld.long 0x00 15. " [80] ,Interrupt Pending Bit[80]" "No interrupt,Interrupt"
bitfld.long 0x00 14. " [79] ,Interrupt Pending Bit[79]" "No interrupt,Interrupt"
bitfld.long 0x00 13. " [78] ,Interrupt Pending Bit[78]" "No interrupt,Interrupt"
bitfld.long 0x00 12. " [77] ,Interrupt Pending Bit[77]" "No interrupt,Interrupt"
textline " "
bitfld.long 0x00 11. " [76] ,Interrupt Pending Bit[76]" "No interrupt,Interrupt"
bitfld.long 0x00 10. " [75] ,Interrupt Pending Bit[75]" "No interrupt,Interrupt"
bitfld.long 0x00 9. " [74] ,Interrupt Pending Bit[74]" "No interrupt,Interrupt"
bitfld.long 0x00 8. " [73] ,Interrupt Pending Bit[73]" "No interrupt,Interrupt"
textline " "
bitfld.long 0x00 7. " [72] ,Interrupt Pending Bit[72]" "No interrupt,Interrupt"
bitfld.long 0x00 6. " [71] ,Interrupt Pending Bit[71]" "No interrupt,Interrupt"
bitfld.long 0x00 5. " [70] ,Interrupt Pending Bit[70]" "No interrupt,Interrupt"
bitfld.long 0x00 4. " [69] ,Interrupt Pending Bit[69]" "No interrupt,Interrupt"
textline " "
bitfld.long 0x00 3. " [68] ,Interrupt Pending Bit[68]" "No interrupt,Interrupt"
bitfld.long 0x00 2. " [67] ,Interrupt Pending Bit[67]" "No interrupt,Interrupt"
bitfld.long 0x00 1. " [66] ,Interrupt Pending Bit[66]" "No interrupt,Interrupt"
bitfld.long 0x00 0. " [65] ,Interrupt Pending Bit[65]" "No interrupt,Interrupt"
rgroup.long 0xBC++0x3
line.long 0x0 "INTPEN87,Interrupt Pending 8_7"
bitfld.long 0x00 31. " INTPND [128] ,Interrupt Pending Bit[128]" "No interrupt,Interrupt"
bitfld.long 0x00 30. " [127] ,Interrupt Pending Bit[127]" "No interrupt,Interrupt"
bitfld.long 0x00 29. " [126] ,Interrupt Pending Bit[126]" "No interrupt,Interrupt"
bitfld.long 0x00 28. " [125] ,Interrupt Pending Bit[125]" "No interrupt,Interrupt"
textline " "
bitfld.long 0x00 27. " [124] ,Interrupt Pending Bit[124]" "No interrupt,Interrupt"
bitfld.long 0x00 26. " [123] ,Interrupt Pending Bit[123]" "No interrupt,Interrupt"
bitfld.long 0x00 25. " [122] ,Interrupt Pending Bit[122]" "No interrupt,Interrupt"
bitfld.long 0x00 24. " [121] ,Interrupt Pending Bit[121]" "No interrupt,Interrupt"
textline " "
bitfld.long 0x00 23. " [120] ,Interrupt Pending Bit[120]" "No interrupt,Interrupt"
bitfld.long 0x00 22. " [119] ,Interrupt Pending Bit[119]" "No interrupt,Interrupt"
bitfld.long 0x00 21. " [118] ,Interrupt Pending Bit[118]" "No interrupt,Interrupt"
bitfld.long 0x00 20. " [117] ,Interrupt Pending Bit[117]" "No interrupt,Interrupt"
textline " "
bitfld.long 0x00 19. " [116] ,Interrupt Pending Bit[116]" "No interrupt,Interrupt"
bitfld.long 0x00 18. " [115] ,Interrupt Pending Bit[115]" "No interrupt,Interrupt"
bitfld.long 0x00 17. " [114] ,Interrupt Pending Bit[114]" "No interrupt,Interrupt"
bitfld.long 0x00 16. " [113] ,Interrupt Pending Bit[113]" "No interrupt,Interrupt"
textline " "
bitfld.long 0x00 15. " [112] ,Interrupt Pending Bit[112]" "No interrupt,Interrupt"
bitfld.long 0x00 14. " [111] ,Interrupt Pending Bit[111]" "No interrupt,Interrupt"
bitfld.long 0x00 13. " [110] ,Interrupt Pending Bit[110]" "No interrupt,Interrupt"
bitfld.long 0x00 12. " [109] ,Interrupt Pending Bit[109]" "No interrupt,Interrupt"
textline " "
bitfld.long 0x00 11. " [108] ,Interrupt Pending Bit[108]" "No interrupt,Interrupt"
bitfld.long 0x00 10. " [107] ,Interrupt Pending Bit[107]" "No interrupt,Interrupt"
bitfld.long 0x00 9. " [106] ,Interrupt Pending Bit[106]" "No interrupt,Interrupt"
bitfld.long 0x00 8. " [105] ,Interrupt Pending Bit[105]" "No interrupt,Interrupt"
textline " "
bitfld.long 0x00 7. " [104] ,Interrupt Pending Bit[104]" "No interrupt,Interrupt"
bitfld.long 0x00 6. " [103] ,Interrupt Pending Bit[103]" "No interrupt,Interrupt"
bitfld.long 0x00 5. " [102] ,Interrupt Pending Bit[102]" "No interrupt,Interrupt"
bitfld.long 0x00 4. " [101] ,Interrupt Pending Bit[101]" "No interrupt,Interrupt"
textline " "
bitfld.long 0x00 3. " [100] ,Interrupt Pending Bit[100]" "No interrupt,Interrupt"
bitfld.long 0x00 2. " [99] ,Interrupt Pending Bit[99]" "No interrupt,Interrupt"
bitfld.long 0x00 1. " [98] ,Interrupt Pending Bit[98]" "No interrupt,Interrupt"
bitfld.long 0x00 0. " [97] ,Interrupt Pending Bit[97]" "No interrupt,Interrupt"
width 12.
rgroup.long 0xC0++0x3
line.long 0x0 "MVAL,Message Valid X"
bitfld.long 0x00 14.--15. " MSGVALREG [8] ,Message Valid Register 8" "0,1,2,3"
bitfld.long 0x00 12.--13. " [7] ,Message Valid Register 7" "0,1,2,3"
bitfld.long 0x00 10.--11. " [6] ,Message Valid Register 6" "0,1,2,3"
bitfld.long 0x00 8.--9. " [5] ,Message Valid Register 5" "0,1,2,3"
textline " "
bitfld.long 0x00 6.--7. " [4] ,Message Valid Register 4" "0,1,2,3"
bitfld.long 0x00 4.--5. " [3] ,Message Valid Register 3" "0,1,2,3"
bitfld.long 0x00 2.--3. " [2] ,Message Valid Register 2" "0,1,2,3"
bitfld.long 0x00 0.--1. " [1] ,Message Valid Register 1" "0,1,2,3"
width 12.
rgroup.long 0xC4++0x3
line.long 0x0 "MVAL21,Message Valid 2_1"
bitfld.long 0x00 31. " MSGVAL [32] ,Message Valid Bit[32]" "Ignored,Configured"
bitfld.long 0x00 30. " [31] ,Message Valid Bit[31]" "Ignored,Configured"
bitfld.long 0x00 29. " [30] ,Message Valid Bit[30]" "Ignored,Configured"
bitfld.long 0x00 28. " [29] ,Message Valid Bit[29]" "Ignored,Configured"
textline " "
bitfld.long 0x00 27. " [28] ,Message Valid Bit[28]" "Ignored,Configured"
bitfld.long 0x00 26. " [27] ,Message Valid Bit[27]" "Ignored,Configured"
bitfld.long 0x00 25. " [26] ,Message Valid Bit[26]" "Ignored,Configured"
bitfld.long 0x00 24. " [25] ,Message Valid Bit[25]" "Ignored,Configured"
textline " "
bitfld.long 0x00 23. " [24] ,Message Valid Bit[24]" "Ignored,Configured"
bitfld.long 0x00 22. " [23] ,Message Valid Bit[23]" "Ignored,Configured"
bitfld.long 0x00 21. " [22] ,Message Valid Bit[22]" "Ignored,Configured"
bitfld.long 0x00 20. " [21] ,Message Valid Bit[21]" "Ignored,Configured"
textline " "
bitfld.long 0x00 19. " [20] ,Message Valid Bit[20]" "Ignored,Configured"
bitfld.long 0x00 18. " [19] ,Message Valid Bit[19]" "Ignored,Configured"
bitfld.long 0x00 17. " [18] ,Message Valid Bit[18]" "Ignored,Configured"
bitfld.long 0x00 16. " [17] ,Message Valid Bit[17]" "Ignored,Configured"
textline " "
bitfld.long 0x00 15. " [16] ,Message Valid Bit[16]" "Ignored,Configured"
bitfld.long 0x00 14. " [15] ,Message Valid Bit[15]" "Ignored,Configured"
bitfld.long 0x00 13. " [14] ,Message Valid Bit[14]" "Ignored,Configured"
bitfld.long 0x00 12. " [13] ,Message Valid Bit[13]" "Ignored,Configured"
textline " "
bitfld.long 0x00 11. " [12] ,Message Valid Bit[12]" "Ignored,Configured"
bitfld.long 0x00 10. " [11] ,Message Valid Bit[11]" "Ignored,Configured"
bitfld.long 0x00 9. " [10] ,Message Valid Bit[10]" "Ignored,Configured"
bitfld.long 0x00 8. " [9] ,Message Valid Bit[9]" "Ignored,Configured"
textline " "
bitfld.long 0x00 7. " [8] ,Message Valid Bit[8]" "Ignored,Configured"
bitfld.long 0x00 6. " [7] ,Message Valid Bit[7]" "Ignored,Configured"
bitfld.long 0x00 5. " [6] ,Message Valid Bit[6]" "Ignored,Configured"
bitfld.long 0x00 4. " [5] ,Message Valid Bit[5]" "Ignored,Configured"
textline " "
bitfld.long 0x00 3. " [4] ,Message Valid Bit[4]" "Ignored,Configured"
bitfld.long 0x00 2. " [3] ,Message Valid Bit[3]" "Ignored,Configured"
bitfld.long 0x00 1. " [2] ,Message Valid Bit[2]" "Ignored,Configured"
bitfld.long 0x00 0. " [1] ,Message Valid Bit[1]" "Ignored,Configured"
rgroup.long 0xC8++0x3
line.long 0x0 "MVAL43,Message Valid 4_3"
bitfld.long 0x00 31. " MSGVAL [64] ,Message Valid Bit[64]" "Ignored,Configured"
bitfld.long 0x00 30. " [63] ,Message Valid Bit[63]" "Ignored,Configured"
bitfld.long 0x00 29. " [62] ,Message Valid Bit[62]" "Ignored,Configured"
bitfld.long 0x00 28. " [61] ,Message Valid Bit[61]" "Ignored,Configured"
textline " "
bitfld.long 0x00 27. " [60] ,Message Valid Bit[60]" "Ignored,Configured"
bitfld.long 0x00 26. " [59] ,Message Valid Bit[59]" "Ignored,Configured"
bitfld.long 0x00 25. " [58] ,Message Valid Bit[58]" "Ignored,Configured"
bitfld.long 0x00 24. " [57] ,Message Valid Bit[57]" "Ignored,Configured"
textline " "
bitfld.long 0x00 23. " [56] ,Message Valid Bit[56]" "Ignored,Configured"
bitfld.long 0x00 22. " [55] ,Message Valid Bit[55]" "Ignored,Configured"
bitfld.long 0x00 21. " [54] ,Message Valid Bit[54]" "Ignored,Configured"
bitfld.long 0x00 20. " [53] ,Message Valid Bit[53]" "Ignored,Configured"
textline " "
bitfld.long 0x00 19. " [52] ,Message Valid Bit[52]" "Ignored,Configured"
bitfld.long 0x00 18. " [51] ,Message Valid Bit[51]" "Ignored,Configured"
bitfld.long 0x00 17. " [50] ,Message Valid Bit[50]" "Ignored,Configured"
bitfld.long 0x00 16. " [49] ,Message Valid Bit[49]" "Ignored,Configured"
textline " "
bitfld.long 0x00 15. " [48] ,Message Valid Bit[48]" "Ignored,Configured"
bitfld.long 0x00 14. " [47] ,Message Valid Bit[47]" "Ignored,Configured"
bitfld.long 0x00 13. " [46] ,Message Valid Bit[46]" "Ignored,Configured"
bitfld.long 0x00 12. " [45] ,Message Valid Bit[45]" "Ignored,Configured"
textline " "
bitfld.long 0x00 11. " [44] ,Message Valid Bit[44]" "Ignored,Configured"
bitfld.long 0x00 10. " [43] ,Message Valid Bit[43]" "Ignored,Configured"
bitfld.long 0x00 9. " [42] ,Message Valid Bit[42]" "Ignored,Configured"
bitfld.long 0x00 8. " [41] ,Message Valid Bit[41]" "Ignored,Configured"
textline " "
bitfld.long 0x00 7. " [40] ,Message Valid Bit[40]" "Ignored,Configured"
bitfld.long 0x00 6. " [39] ,Message Valid Bit[39]" "Ignored,Configured"
bitfld.long 0x00 5. " [38] ,Message Valid Bit[38]" "Ignored,Configured"
bitfld.long 0x00 4. " [37] ,Message Valid Bit[37]" "Ignored,Configured"
textline " "
bitfld.long 0x00 3. " [36] ,Message Valid Bit[36]" "Ignored,Configured"
bitfld.long 0x00 2. " [35] ,Message Valid Bit[35]" "Ignored,Configured"
bitfld.long 0x00 1. " [34] ,Message Valid Bit[34]" "Ignored,Configured"
bitfld.long 0x00 0. " [33] ,Message Valid Bit[33]" "Ignored,Configured"
rgroup.long 0xCC++0x3
line.long 0x0 "MVAL65,Message Valid 6_5"
bitfld.long 0x00 31. " MSGVAL [96] ,Message Valid Bit[96]" "Ignored,Configured"
bitfld.long 0x00 30. " [95] ,Message Valid Bit[95]" "Ignored,Configured"
bitfld.long 0x00 29. " [94] ,Message Valid Bit[94]" "Ignored,Configured"
bitfld.long 0x00 28. " [93] ,Message Valid Bit[93]" "Ignored,Configured"
textline " "
bitfld.long 0x00 27. " [92] ,Message Valid Bit[92]" "Ignored,Configured"
bitfld.long 0x00 26. " [91] ,Message Valid Bit[91]" "Ignored,Configured"
bitfld.long 0x00 25. " [90] ,Message Valid Bit[90]" "Ignored,Configured"
bitfld.long 0x00 24. " [89] ,Message Valid Bit[89]" "Ignored,Configured"
textline " "
bitfld.long 0x00 23. " [88] ,Message Valid Bit[88]" "Ignored,Configured"
bitfld.long 0x00 22. " [87] ,Message Valid Bit[87]" "Ignored,Configured"
bitfld.long 0x00 21. " [86] ,Message Valid Bit[86]" "Ignored,Configured"
bitfld.long 0x00 20. " [85] ,Message Valid Bit[85]" "Ignored,Configured"
textline " "
bitfld.long 0x00 19. " [84] ,Message Valid Bit[84]" "Ignored,Configured"
bitfld.long 0x00 18. " [83] ,Message Valid Bit[83]" "Ignored,Configured"
bitfld.long 0x00 17. " [82] ,Message Valid Bit[82]" "Ignored,Configured"
bitfld.long 0x00 16. " [81] ,Message Valid Bit[81]" "Ignored,Configured"
textline " "
bitfld.long 0x00 15. " [80] ,Message Valid Bit[80]" "Ignored,Configured"
bitfld.long 0x00 14. " [79] ,Message Valid Bit[79]" "Ignored,Configured"
bitfld.long 0x00 13. " [78] ,Message Valid Bit[78]" "Ignored,Configured"
bitfld.long 0x00 12. " [77] ,Message Valid Bit[77]" "Ignored,Configured"
textline " "
bitfld.long 0x00 11. " [76] ,Message Valid Bit[76]" "Ignored,Configured"
bitfld.long 0x00 10. " [75] ,Message Valid Bit[75]" "Ignored,Configured"
bitfld.long 0x00 9. " [74] ,Message Valid Bit[74]" "Ignored,Configured"
bitfld.long 0x00 8. " [73] ,Message Valid Bit[73]" "Ignored,Configured"
textline " "
bitfld.long 0x00 7. " [72] ,Message Valid Bit[72]" "Ignored,Configured"
bitfld.long 0x00 6. " [71] ,Message Valid Bit[71]" "Ignored,Configured"
bitfld.long 0x00 5. " [70] ,Message Valid Bit[70]" "Ignored,Configured"
bitfld.long 0x00 4. " [69] ,Message Valid Bit[69]" "Ignored,Configured"
textline " "
bitfld.long 0x00 3. " [68] ,Message Valid Bit[68]" "Ignored,Configured"
bitfld.long 0x00 2. " [67] ,Message Valid Bit[67]" "Ignored,Configured"
bitfld.long 0x00 1. " [66] ,Message Valid Bit[66]" "Ignored,Configured"
bitfld.long 0x00 0. " [65] ,Message Valid Bit[65]" "Ignored,Configured"
rgroup.long 0xD0++0x3
line.long 0x0 "MVAL87,Message Valid 8_7"
bitfld.long 0x00 31. " MSGVAL [128] ,Message Valid Bit[128]" "Ignored,Configured"
bitfld.long 0x00 30. " [127] ,Message Valid Bit[127]" "Ignored,Configured"
bitfld.long 0x00 29. " [126] ,Message Valid Bit[126]" "Ignored,Configured"
bitfld.long 0x00 28. " [125] ,Message Valid Bit[125]" "Ignored,Configured"
textline " "
bitfld.long 0x00 27. " [124] ,Message Valid Bit[124]" "Ignored,Configured"
bitfld.long 0x00 26. " [123] ,Message Valid Bit[123]" "Ignored,Configured"
bitfld.long 0x00 25. " [122] ,Message Valid Bit[122]" "Ignored,Configured"
bitfld.long 0x00 24. " [121] ,Message Valid Bit[121]" "Ignored,Configured"
textline " "
bitfld.long 0x00 23. " [120] ,Message Valid Bit[120]" "Ignored,Configured"
bitfld.long 0x00 22. " [119] ,Message Valid Bit[119]" "Ignored,Configured"
bitfld.long 0x00 21. " [118] ,Message Valid Bit[118]" "Ignored,Configured"
bitfld.long 0x00 20. " [117] ,Message Valid Bit[117]" "Ignored,Configured"
textline " "
bitfld.long 0x00 19. " [116] ,Message Valid Bit[116]" "Ignored,Configured"
bitfld.long 0x00 18. " [115] ,Message Valid Bit[115]" "Ignored,Configured"
bitfld.long 0x00 17. " [114] ,Message Valid Bit[114]" "Ignored,Configured"
bitfld.long 0x00 16. " [113] ,Message Valid Bit[113]" "Ignored,Configured"
textline " "
bitfld.long 0x00 15. " [112] ,Message Valid Bit[112]" "Ignored,Configured"
bitfld.long 0x00 14. " [111] ,Message Valid Bit[111]" "Ignored,Configured"
bitfld.long 0x00 13. " [110] ,Message Valid Bit[110]" "Ignored,Configured"
bitfld.long 0x00 12. " [109] ,Message Valid Bit[109]" "Ignored,Configured"
textline " "
bitfld.long 0x00 11. " [108] ,Message Valid Bit[108]" "Ignored,Configured"
bitfld.long 0x00 10. " [107] ,Message Valid Bit[107]" "Ignored,Configured"
bitfld.long 0x00 9. " [106] ,Message Valid Bit[106]" "Ignored,Configured"
bitfld.long 0x00 8. " [105] ,Message Valid Bit[105]" "Ignored,Configured"
textline " "
bitfld.long 0x00 7. " [104] ,Message Valid Bit[104]" "Ignored,Configured"
bitfld.long 0x00 6. " [103] ,Message Valid Bit[103]" "Ignored,Configured"
bitfld.long 0x00 5. " [102] ,Message Valid Bit[102]" "Ignored,Configured"
bitfld.long 0x00 4. " [101] ,Message Valid Bit[101]" "Ignored,Configured"
textline " "
bitfld.long 0x00 3. " [100] ,Message Valid Bit[100]" "Ignored,Configured"
bitfld.long 0x00 2. " [99] ,Message Valid Bit[99]" "Ignored,Configured"
bitfld.long 0x00 1. " [98] ,Message Valid Bit[98]" "Ignored,Configured"
bitfld.long 0x00 0. " [97] ,Message Valid Bit[97]" "Ignored,Configured"
width 12.
group.long 0xD8++0x3
line.long 0x0 "INTPMX21,IntPndMux 2_1"
bitfld.long 0x00 31. " INTPNDMUX [32] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[32]" "DCAN0INT,DCAN1INT"
bitfld.long 0x00 30. " [31] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[31]" "DCAN0INT,DCAN1INT"
bitfld.long 0x00 29. " [30] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[30]" "DCAN0INT,DCAN1INT"
bitfld.long 0x00 28. " [29] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[29]" "DCAN0INT,DCAN1INT"
textline " "
bitfld.long 0x00 27. " [28] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[28]" "DCAN0INT,DCAN1INT"
bitfld.long 0x00 26. " [27] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[27]" "DCAN0INT,DCAN1INT"
bitfld.long 0x00 25. " [26] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[26]" "DCAN0INT,DCAN1INT"
bitfld.long 0x00 24. " [25] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[25]" "DCAN0INT,DCAN1INT"
textline " "
bitfld.long 0x00 23. " [24] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[24]" "DCAN0INT,DCAN1INT"
bitfld.long 0x00 22. " [23] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[23]" "DCAN0INT,DCAN1INT"
bitfld.long 0x00 21. " [22] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[22]" "DCAN0INT,DCAN1INT"
bitfld.long 0x00 20. " [21] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[21]" "DCAN0INT,DCAN1INT"
textline " "
bitfld.long 0x00 19. " [20] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[20]" "DCAN0INT,DCAN1INT"
bitfld.long 0x00 18. " [19] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[19]" "DCAN0INT,DCAN1INT"
bitfld.long 0x00 17. " [18] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[18]" "DCAN0INT,DCAN1INT"
bitfld.long 0x00 16. " [17] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[17]" "DCAN0INT,DCAN1INT"
textline " "
bitfld.long 0x00 15. " [16] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[16]" "DCAN0INT,DCAN1INT"
bitfld.long 0x00 14. " [15] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[15]" "DCAN0INT,DCAN1INT"
bitfld.long 0x00 13. " [14] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[14]" "DCAN0INT,DCAN1INT"
bitfld.long 0x00 12. " [13] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[13]" "DCAN0INT,DCAN1INT"
textline " "
bitfld.long 0x00 11. " [12] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[12]" "DCAN0INT,DCAN1INT"
bitfld.long 0x00 10. " [11] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[11]" "DCAN0INT,DCAN1INT"
bitfld.long 0x00 9. " [10] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[10]" "DCAN0INT,DCAN1INT"
bitfld.long 0x00 8. " [9] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[9]" "DCAN0INT,DCAN1INT"
textline " "
bitfld.long 0x00 7. " [8] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[8]" "DCAN0INT,DCAN1INT"
bitfld.long 0x00 6. " [7] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[7]" "DCAN0INT,DCAN1INT"
bitfld.long 0x00 5. " [6] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[6]" "DCAN0INT,DCAN1INT"
bitfld.long 0x00 4. " [5] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[5]" "DCAN0INT,DCAN1INT"
textline " "
bitfld.long 0x00 3. " [4] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[4]" "DCAN0INT,DCAN1INT"
bitfld.long 0x00 2. " [3] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[3]" "DCAN0INT,DCAN1INT"
bitfld.long 0x00 1. " [2] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[2]" "DCAN0INT,DCAN1INT"
bitfld.long 0x00 0. " [1] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[1]" "DCAN0INT,DCAN1INT"
group.long 0xDC++0x3
line.long 0x0 "INTPMX43,IntPndMux 4_3"
bitfld.long 0x00 31. " INTPNDMUX [64] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[64]" "DCAN0INT,DCAN1INT"
bitfld.long 0x00 30. " [63] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[63]" "DCAN0INT,DCAN1INT"
bitfld.long 0x00 29. " [62] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[62]" "DCAN0INT,DCAN1INT"
bitfld.long 0x00 28. " [61] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[61]" "DCAN0INT,DCAN1INT"
textline " "
bitfld.long 0x00 27. " [60] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[60]" "DCAN0INT,DCAN1INT"
bitfld.long 0x00 26. " [59] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[59]" "DCAN0INT,DCAN1INT"
bitfld.long 0x00 25. " [58] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[58]" "DCAN0INT,DCAN1INT"
bitfld.long 0x00 24. " [57] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[57]" "DCAN0INT,DCAN1INT"
textline " "
bitfld.long 0x00 23. " [56] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[56]" "DCAN0INT,DCAN1INT"
bitfld.long 0x00 22. " [55] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[55]" "DCAN0INT,DCAN1INT"
bitfld.long 0x00 21. " [54] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[54]" "DCAN0INT,DCAN1INT"
bitfld.long 0x00 20. " [53] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[53]" "DCAN0INT,DCAN1INT"
textline " "
bitfld.long 0x00 19. " [52] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[52]" "DCAN0INT,DCAN1INT"
bitfld.long 0x00 18. " [51] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[51]" "DCAN0INT,DCAN1INT"
bitfld.long 0x00 17. " [50] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[50]" "DCAN0INT,DCAN1INT"
bitfld.long 0x00 16. " [49] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[49]" "DCAN0INT,DCAN1INT"
textline " "
bitfld.long 0x00 15. " [48] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[48]" "DCAN0INT,DCAN1INT"
bitfld.long 0x00 14. " [47] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[47]" "DCAN0INT,DCAN1INT"
bitfld.long 0x00 13. " [46] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[46]" "DCAN0INT,DCAN1INT"
bitfld.long 0x00 12. " [45] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[45]" "DCAN0INT,DCAN1INT"
textline " "
bitfld.long 0x00 11. " [44] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[44]" "DCAN0INT,DCAN1INT"
bitfld.long 0x00 10. " [43] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[43]" "DCAN0INT,DCAN1INT"
bitfld.long 0x00 9. " [42] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[42]" "DCAN0INT,DCAN1INT"
bitfld.long 0x00 8. " [41] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[41]" "DCAN0INT,DCAN1INT"
textline " "
bitfld.long 0x00 7. " [40] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[40]" "DCAN0INT,DCAN1INT"
bitfld.long 0x00 6. " [39] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[39]" "DCAN0INT,DCAN1INT"
bitfld.long 0x00 5. " [38] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[38]" "DCAN0INT,DCAN1INT"
bitfld.long 0x00 4. " [37] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[37]" "DCAN0INT,DCAN1INT"
textline " "
bitfld.long 0x00 3. " [36] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[36]" "DCAN0INT,DCAN1INT"
bitfld.long 0x00 2. " [35] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[35]" "DCAN0INT,DCAN1INT"
bitfld.long 0x00 1. " [34] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[34]" "DCAN0INT,DCAN1INT"
bitfld.long 0x00 0. " [33] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[33]" "DCAN0INT,DCAN1INT"
group.long 0xE0++0x3
line.long 0x0 "INTPMX65,IntPndMux 6_5"
bitfld.long 0x00 31. " INTPNDMUX [96] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[96]" "DCAN0INT,DCAN1INT"
bitfld.long 0x00 30. " [95] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[95]" "DCAN0INT,DCAN1INT"
bitfld.long 0x00 29. " [94] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[94]" "DCAN0INT,DCAN1INT"
bitfld.long 0x00 28. " [93] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[93]" "DCAN0INT,DCAN1INT"
textline " "
bitfld.long 0x00 27. " [92] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[92]" "DCAN0INT,DCAN1INT"
bitfld.long 0x00 26. " [91] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[91]" "DCAN0INT,DCAN1INT"
bitfld.long 0x00 25. " [90] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[90]" "DCAN0INT,DCAN1INT"
bitfld.long 0x00 24. " [89] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[89]" "DCAN0INT,DCAN1INT"
textline " "
bitfld.long 0x00 23. " [88] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[88]" "DCAN0INT,DCAN1INT"
bitfld.long 0x00 22. " [87] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[87]" "DCAN0INT,DCAN1INT"
bitfld.long 0x00 21. " [86] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[86]" "DCAN0INT,DCAN1INT"
bitfld.long 0x00 20. " [85] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[85]" "DCAN0INT,DCAN1INT"
textline " "
bitfld.long 0x00 19. " [84] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[84]" "DCAN0INT,DCAN1INT"
bitfld.long 0x00 18. " [83] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[83]" "DCAN0INT,DCAN1INT"
bitfld.long 0x00 17. " [82] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[82]" "DCAN0INT,DCAN1INT"
bitfld.long 0x00 16. " [81] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[81]" "DCAN0INT,DCAN1INT"
textline " "
bitfld.long 0x00 15. " [80] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[80]" "DCAN0INT,DCAN1INT"
bitfld.long 0x00 14. " [79] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[79]" "DCAN0INT,DCAN1INT"
bitfld.long 0x00 13. " [78] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[78]" "DCAN0INT,DCAN1INT"
bitfld.long 0x00 12. " [77] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[77]" "DCAN0INT,DCAN1INT"
textline " "
bitfld.long 0x00 11. " [76] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[76]" "DCAN0INT,DCAN1INT"
bitfld.long 0x00 10. " [75] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[75]" "DCAN0INT,DCAN1INT"
bitfld.long 0x00 9. " [74] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[74]" "DCAN0INT,DCAN1INT"
bitfld.long 0x00 8. " [73] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[73]" "DCAN0INT,DCAN1INT"
textline " "
bitfld.long 0x00 7. " [72] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[72]" "DCAN0INT,DCAN1INT"
bitfld.long 0x00 6. " [71] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[71]" "DCAN0INT,DCAN1INT"
bitfld.long 0x00 5. " [70] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[70]" "DCAN0INT,DCAN1INT"
bitfld.long 0x00 4. " [69] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[69]" "DCAN0INT,DCAN1INT"
textline " "
bitfld.long 0x00 3. " [68] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[68]" "DCAN0INT,DCAN1INT"
bitfld.long 0x00 2. " [67] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[67]" "DCAN0INT,DCAN1INT"
bitfld.long 0x00 1. " [66] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[66]" "DCAN0INT,DCAN1INT"
bitfld.long 0x00 0. " [65] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[65]" "DCAN0INT,DCAN1INT"
group.long 0xE4++0x3
line.long 0x0 "INTPMX87,IntPndMux 8_7"
bitfld.long 0x00 31. " INTPNDMUX [128] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[128]" "DCAN0INT,DCAN1INT"
bitfld.long 0x00 30. " [127] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[127]" "DCAN0INT,DCAN1INT"
bitfld.long 0x00 29. " [126] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[126]" "DCAN0INT,DCAN1INT"
bitfld.long 0x00 28. " [125] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[125]" "DCAN0INT,DCAN1INT"
textline " "
bitfld.long 0x00 27. " [124] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[124]" "DCAN0INT,DCAN1INT"
bitfld.long 0x00 26. " [123] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[123]" "DCAN0INT,DCAN1INT"
bitfld.long 0x00 25. " [122] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[122]" "DCAN0INT,DCAN1INT"
bitfld.long 0x00 24. " [121] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[121]" "DCAN0INT,DCAN1INT"
textline " "
bitfld.long 0x00 23. " [120] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[120]" "DCAN0INT,DCAN1INT"
bitfld.long 0x00 22. " [119] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[119]" "DCAN0INT,DCAN1INT"
bitfld.long 0x00 21. " [118] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[118]" "DCAN0INT,DCAN1INT"
bitfld.long 0x00 20. " [117] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[117]" "DCAN0INT,DCAN1INT"
textline " "
bitfld.long 0x00 19. " [116] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[116]" "DCAN0INT,DCAN1INT"
bitfld.long 0x00 18. " [115] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[115]" "DCAN0INT,DCAN1INT"
bitfld.long 0x00 17. " [114] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[114]" "DCAN0INT,DCAN1INT"
bitfld.long 0x00 16. " [113] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[113]" "DCAN0INT,DCAN1INT"
textline " "
bitfld.long 0x00 15. " [112] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[112]" "DCAN0INT,DCAN1INT"
bitfld.long 0x00 14. " [111] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[111]" "DCAN0INT,DCAN1INT"
bitfld.long 0x00 13. " [110] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[110]" "DCAN0INT,DCAN1INT"
bitfld.long 0x00 12. " [109] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[109]" "DCAN0INT,DCAN1INT"
textline " "
bitfld.long 0x00 11. " [108] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[108]" "DCAN0INT,DCAN1INT"
bitfld.long 0x00 10. " [107] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[107]" "DCAN0INT,DCAN1INT"
bitfld.long 0x00 9. " [106] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[106]" "DCAN0INT,DCAN1INT"
bitfld.long 0x00 8. " [105] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[105]" "DCAN0INT,DCAN1INT"
textline " "
bitfld.long 0x00 7. " [104] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[104]" "DCAN0INT,DCAN1INT"
bitfld.long 0x00 6. " [103] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[103]" "DCAN0INT,DCAN1INT"
bitfld.long 0x00 5. " [102] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[102]" "DCAN0INT,DCAN1INT"
bitfld.long 0x00 4. " [101] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[101]" "DCAN0INT,DCAN1INT"
textline " "
bitfld.long 0x00 3. " [100] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[100]" "DCAN0INT,DCAN1INT"
bitfld.long 0x00 2. " [99] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[99]" "DCAN0INT,DCAN1INT"
bitfld.long 0x00 1. " [98] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[98]" "DCAN0INT,DCAN1INT"
bitfld.long 0x00 0. " [97] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[97]" "DCAN0INT,DCAN1INT"
width 12.
group.long 0x100++0x3
line.long 0x0 "IF1COM,IF1 Command Mask / Command Request Register"
bitfld.long 0x00 23. " WR/RD ,Write / Read" "Read,Write"
textline " "
width 12.
bitfld.long 0x00 22. " MASK ,Access Mask Bits" "Unchanged,Identifier Mask+MDir+MXtd"
textline " "
bitfld.long 0x00 21. " ARB ,Access Arbitration Bits" "Unchanged,Identifier+Dir+Xtd+MSGVAl"
textline " "
width 12.
bitfld.long 0x00 20. " CONTROL ,Access Control Bits" "Unchanged,Control bits"
bitfld.long 0x00 19. " CLRINTPND ,Clear Interrupt Pending Bit" "Low,High"
textline " "
bitfld.long 0x00 18. " TXRQST/NEWDAT ,Access Transmission Request Bit" "Not requested,Requested"
bitfld.long 0x00 17. " DATA_A ,Access Data Bytes 0-3" "Unchanged,Data bytes 0-3"
textline " "
bitfld.long 0x00 16. " DATA_B ,Access Data Bytes 4-7" "Unchanged,Data bytes 4-7"
bitfld.long 0x00 15. " BUSY ,Busy Flag" "Reset,Set"
textline " "
bitfld.long 0x00 14. " DMAACTIVE ,Activation of DMA Feature for Subsequent Internal IF1 Update" "No active,Active"
hexmask.long.byte 0x00 0.--7. 1. " MESSAGE_NUMBER ,Message Number"
width 12.
if (((d.l((ad:0xFFF7E000+0x108)))&0x40000000)==0x00000000)
group.long 0x104++0x3
line.long 0x0 "IF1MASK,IF1 Mask Register"
bitfld.long 0x00 31. " MXTD ,Mask Extended Identifier" "No effect,Filtering"
bitfld.long 0x00 30. " MDIR ,Mask Message Direction" "No effect,Filtering"
textline " "
bitfld.long 0x00 28. " ID ,Message Identifier bit[28]" "0,1"
bitfld.long 0x00 27. ",Message Identifier bit[27]" "0,1"
bitfld.long 0x00 26. ",Message Identifier bit[26]" "0,1"
bitfld.long 0x00 25. ",Message Identifier bit[25]" "0,1"
bitfld.long 0x00 24. ",Message Identifier bit[24]" "0,1"
bitfld.long 0x00 23. ",Message Identifier bit[23]" "0,1"
bitfld.long 0x00 22. ",Message Identifier bit[22]" "0,1"
bitfld.long 0x00 21. ",Message Identifier bit[21]" "0,1"
bitfld.long 0x00 20. ",Message Identifier bit[20]" "0,1"
bitfld.long 0x00 19. ",Message Identifier bit[19]" "0,1"
bitfld.long 0x00 18. ",Message Identifier bit[18]" "0,1"
else
group.long 0x104++0x3
line.long 0x0 "IF1MASK,IF1 Mask Register"
bitfld.long 0x00 31. " MXTD ,Mask Extended Identifier" "No effect,Filtering"
bitfld.long 0x00 30. " MDIR ,Mask Message Direction" "No effect,Filtering"
textline " "
bitfld.long 0x00 28. " ID ,Message Identifier bit[28]" "0,1"
bitfld.long 0x00 27. ",Message Identifier bit[27]" "0,1"
bitfld.long 0x00 26. ",Message Identifier bit[26]" "0,1"
bitfld.long 0x00 25. ",Message Identifier bit[25]" "0,1"
bitfld.long 0x00 24. ",Message Identifier bit[24]" "0,1"
bitfld.long 0x00 23. ",Message Identifier bit[23]" "0,1"
bitfld.long 0x00 22. ",Message Identifier bit[22]" "0,1"
bitfld.long 0x00 21. ",Message Identifier bit[21]" "0,1"
bitfld.long 0x00 20. ",Message Identifier bit[20]" "0,1"
bitfld.long 0x00 19. ",Message Identifier bit[19]" "0,1"
bitfld.long 0x00 18. ",Message Identifier bit[18]" "0,1"
bitfld.long 0x00 17. ",Message Identifier bit[17]" "0,1"
bitfld.long 0x00 16. ",Message Identifier bit[16]" "0,1"
bitfld.long 0x00 15. ",Message Identifier bit[15]" "0,1"
bitfld.long 0x00 14. ",Message Identifier bit[14]" "0,1"
bitfld.long 0x00 13. ",Message Identifier bit[13]" "0,1"
bitfld.long 0x00 12. ",Message Identifier bit[12]" "0,1"
bitfld.long 0x00 11. ",Message Identifier bit[11]" "0,1"
bitfld.long 0x00 10. ",Message Identifier bit[10]" "0,1"
bitfld.long 0x00 9. ",Message Identifier bit[9]" "0,1"
bitfld.long 0x00 8. ",Message Identifier bit[8]" "0,1"
bitfld.long 0x00 7. ",Message Identifier bit[7]" "0,1"
bitfld.long 0x00 6. ",Message Identifier bit[6]" "0,1"
bitfld.long 0x00 5. ",Message Identifier bit[5]" "0,1"
bitfld.long 0x00 4. ",Message Identifier bit[4]" "0,1"
bitfld.long 0x00 3. ",Message Identifier bit[3]" "0,1"
bitfld.long 0x00 2. ",Message Identifier bit[2]" "0,1"
bitfld.long 0x00 1. ",Message Identifier bit[1]" "0,1"
bitfld.long 0x00 0. ",Message Identifier bit[0]" "0,1"
endif
width 12.
group.long 0x108++0x3
line.long 0x0 "IF1ARB,IF1 Arbitation Register"
bitfld.long 0x00 31. " MSGVAL ,Message Valid" "Ignore,Configure"
bitfld.long 0x00 30. " XTD ,Extended Identifier" "11-bit,29-bit"
bitfld.long 0x00 29. " DIR ,Message Direction" "Receive,Transmit"
hexmask.long 0x00 0.--28. 1. " ID28-0 ,Message Identifier"
width 12.
group.long 0x10C++0x3
line.long 0x0 "IF1MCTRL,IF1 Message Control Register"
bitfld.long 0x00 15. " NEWDAT ,New Data" "No new data,New data"
bitfld.long 0x00 14. " MSGLST ,Message Lost" "Not lost,Lost"
bitfld.long 0x00 13. " INTPND ,Interrupt Pending" "No interrupt,Interrupt"
textline " "
bitfld.long 0x00 12. " UMASK ,Use Acceptance Mask" "Ignored,Masked"
bitfld.long 0x00 11. " TXIE ,Transmit Interrupt Enable" "Unchanged,Set"
bitfld.long 0x00 10. " RXIE ,Receive Interrupt Enable" "Unchanged,Set"
textline " "
bitfld.long 0x00 9. " RMTEN ,Remote Enable" "Disabled,Enabled"
bitfld.long 0x00 8. " TXRQST ,Transmit Request" "Not requested,Requested"
bitfld.long 0x00 7. " EOB ,End of Block" "Single/Last,Not last"
textline " "
bitfld.long 0x00 0.--3. " DLC[3-0] ,Data Length Code" "0 byte,1 bytes,2 bytes,3 bytes,4 bytes,5 bytes,6 bytes,7 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes"
width 12.
group.long 0x110++0x3
line.long 0x0 "IF1DATA,IF1 Data A Register"
hexmask.long.byte 0x00 24.--31. 1. " DATA [3] ,4th data byte of a CAN Data Frame"
hexmask.long.byte 0x00 16.--23. 1. " [2] ,3rd data byte of a CAN Data Frame"
hexmask.long.byte 0x00 8.--15. 1. " [1] ,2nd data byte of a CAN Data Frame"
hexmask.long.byte 0x00 0.--7. 1. " [0] ,1st data byte of a CAN Data Frame"
group.long 0x114++0x3
line.long 0x0 "IF1DATB,IF1 Data B Register"
hexmask.long.byte 0x00 24.--31. 1. " DATA [7] ,8th data byte of a CAN Data Frame"
hexmask.long.byte 0x00 16.--23. 1. " [6] ,7th data byte of a CAN Data Frame"
hexmask.long.byte 0x00 8.--15. 1. " [5] ,6th data byte of a CAN Data Frame"
hexmask.long.byte 0x00 0.--7. 1. " [4] ,5th data byte of a CAN Data Frame"
width 12.
group.long 0x120++0x3
line.long 0x0 "IF2COM,IF2 Command Mask / Command Request Register"
bitfld.long 0x00 23. " WR/RD ,Write / Read" "Read,Write"
textline " "
width 12.
bitfld.long 0x00 22. " MASK ,Access Mask Bits" "Unchanged,Identifier Mask+MDir+MXtd"
textline " "
bitfld.long 0x00 21. " ARB ,Access Arbitration Bits" "Unchanged,Identifier+Dir+Xtd+MSGVAl"
textline " "
width 12.
bitfld.long 0x00 20. " CONTROL ,Access Control Bits" "Unchanged,Control bits"
bitfld.long 0x00 19. " CLRINTPND ,Clear Interrupt Pending Bit" "Low,High"
textline " "
bitfld.long 0x00 18. " TXRQST/NEWDAT ,Access Transmission Request Bit" "Not requested,Requested"
bitfld.long 0x00 17. " DATA_A ,Access Data Bytes 0-3" "Unchanged,Data bytes 0-3"
textline " "
bitfld.long 0x00 16. " DATA_B ,Access Data Bytes 4-7" "Unchanged,Data bytes 4-7"
bitfld.long 0x00 15. " BUSY ,Busy Flag" "Reset,Set"
textline " "
bitfld.long 0x00 14. " DMAACTIVE ,Activation of DMA Feature for Subsequent Internal IF1 Update" "No active,Active"
hexmask.long.byte 0x00 0.--7. 1. " MESSAGE_NUMBER ,Message Number"
width 12.
if (((d.l((ad:0xFFF7E000+0x128)))&0x40000000)==0x00000000)
group.long 0x124++0x3
line.long 0x0 "IF2MASK,IF2 Mask Register"
bitfld.long 0x00 31. " MXTD ,Mask Extended Identifier" "No effect,Filtering"
bitfld.long 0x00 30. " MDIR ,Mask Message Direction" "No effect,Filtering"
textline " "
bitfld.long 0x00 28. " ID ,Message Identifier bit[28]" "0,1"
bitfld.long 0x00 27. ",Message Identifier bit[27]" "0,1"
bitfld.long 0x00 26. ",Message Identifier bit[26]" "0,1"
bitfld.long 0x00 25. ",Message Identifier bit[25]" "0,1"
bitfld.long 0x00 24. ",Message Identifier bit[24]" "0,1"
bitfld.long 0x00 23. ",Message Identifier bit[23]" "0,1"
bitfld.long 0x00 22. ",Message Identifier bit[22]" "0,1"
bitfld.long 0x00 21. ",Message Identifier bit[21]" "0,1"
bitfld.long 0x00 20. ",Message Identifier bit[20]" "0,1"
bitfld.long 0x00 19. ",Message Identifier bit[19]" "0,1"
bitfld.long 0x00 18. ",Message Identifier bit[18]" "0,1"
else
group.long 0x124++0x3
line.long 0x0 "IF2MASK,IF2 Mask Register"
bitfld.long 0x00 31. " MXTD ,Mask Extended Identifier" "No effect,Filtering"
bitfld.long 0x00 30. " MDIR ,Mask Message Direction" "No effect,Filtering"
textline " "
bitfld.long 0x00 28. " ID ,Message Identifier bit[28]" "0,1"
bitfld.long 0x00 27. ",Message Identifier bit[27]" "0,1"
bitfld.long 0x00 26. ",Message Identifier bit[26]" "0,1"
bitfld.long 0x00 25. ",Message Identifier bit[25]" "0,1"
bitfld.long 0x00 24. ",Message Identifier bit[24]" "0,1"
bitfld.long 0x00 23. ",Message Identifier bit[23]" "0,1"
bitfld.long 0x00 22. ",Message Identifier bit[22]" "0,1"
bitfld.long 0x00 21. ",Message Identifier bit[21]" "0,1"
bitfld.long 0x00 20. ",Message Identifier bit[20]" "0,1"
bitfld.long 0x00 19. ",Message Identifier bit[19]" "0,1"
bitfld.long 0x00 18. ",Message Identifier bit[18]" "0,1"
bitfld.long 0x00 17. ",Message Identifier bit[17]" "0,1"
bitfld.long 0x00 16. ",Message Identifier bit[16]" "0,1"
bitfld.long 0x00 15. ",Message Identifier bit[15]" "0,1"
bitfld.long 0x00 14. ",Message Identifier bit[14]" "0,1"
bitfld.long 0x00 13. ",Message Identifier bit[13]" "0,1"
bitfld.long 0x00 12. ",Message Identifier bit[12]" "0,1"
bitfld.long 0x00 11. ",Message Identifier bit[11]" "0,1"
bitfld.long 0x00 10. ",Message Identifier bit[10]" "0,1"
bitfld.long 0x00 9. ",Message Identifier bit[9]" "0,1"
bitfld.long 0x00 8. ",Message Identifier bit[8]" "0,1"
bitfld.long 0x00 7. ",Message Identifier bit[7]" "0,1"
bitfld.long 0x00 6. ",Message Identifier bit[6]" "0,1"
bitfld.long 0x00 5. ",Message Identifier bit[5]" "0,1"
bitfld.long 0x00 4. ",Message Identifier bit[4]" "0,1"
bitfld.long 0x00 3. ",Message Identifier bit[3]" "0,1"
bitfld.long 0x00 2. ",Message Identifier bit[2]" "0,1"
bitfld.long 0x00 1. ",Message Identifier bit[1]" "0,1"
bitfld.long 0x00 0. ",Message Identifier bit[0]" "0,1"
endif
width 12.
group.long 0x128++0x3
line.long 0x0 "IF2ARB,IF2 Arbitation Register"
bitfld.long 0x00 31. " MSGVAL ,Message Valid" "Ignore,Configure"
bitfld.long 0x00 30. " XTD ,Extended Identifier" "11-bit,29-bit"
bitfld.long 0x00 29. " DIR ,Message Direction" "Receive,Transmit"
hexmask.long 0x00 0.--28. 1. " ID28-0 ,Message Identifier"
width 12.
group.long 0x12C++0x3
line.long 0x0 "IF2MCTRL,IF2 Message Control Register"
bitfld.long 0x00 15. " NEWDAT ,New Data" "No new data,New data"
bitfld.long 0x00 14. " MSGLST ,Message Lost" "Not lost,Lost"
bitfld.long 0x00 13. " INTPND ,Interrupt Pending" "No interrupt,Interrupt"
textline " "
bitfld.long 0x00 12. " UMASK ,Use Acceptance Mask" "Ignored,Masked"
bitfld.long 0x00 11. " TXIE ,Transmit Interrupt Enable" "Unchanged,Set"
bitfld.long 0x00 10. " RXIE ,Receive Interrupt Enable" "Unchanged,Set"
textline " "
bitfld.long 0x00 9. " RMTEN ,Remote Enable" "Disabled,Enabled"
bitfld.long 0x00 8. " TXRQST ,Transmit Request" "Not requested,Requested"
bitfld.long 0x00 7. " EOB ,End of Block" "Single/Last,Not last"
textline " "
bitfld.long 0x00 0.--3. " DLC[3-0] ,Data Length Code" "0 byte,1 bytes,2 bytes,3 bytes,4 bytes,5 bytes,6 bytes,7 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes"
width 12.
group.long 0x130++0x3
line.long 0x0 "IF2DATA,IF2 Data A Register"
hexmask.long.byte 0x00 24.--31. 1. " DATA [3] ,4th data byte of a CAN Data Frame"
hexmask.long.byte 0x00 16.--23. 1. " [2] ,3rd data byte of a CAN Data Frame"
hexmask.long.byte 0x00 8.--15. 1. " [1] ,2nd data byte of a CAN Data Frame"
hexmask.long.byte 0x00 0.--7. 1. " [0] ,1st data byte of a CAN Data Frame"
group.long 0x134++0x3
line.long 0x0 "IF2DATB,IF2 Data B Register"
hexmask.long.byte 0x00 24.--31. 1. " DATA [7] ,8th data byte of a CAN Data Frame"
hexmask.long.byte 0x00 16.--23. 1. " [6] ,7th data byte of a CAN Data Frame"
hexmask.long.byte 0x00 8.--15. 1. " [5] ,6th data byte of a CAN Data Frame"
hexmask.long.byte 0x00 0.--7. 1. " [4] ,5th data byte of a CAN Data Frame"
width 12.
group.long 0x140++0x3
line.long 0x0 "IF3OB,IF3 Observation Register"
bitfld.long 0x00 15. " IF3UPD ,IF3 Updata Data" "Not loaded,Loaded"
bitfld.long 0x00 12. " IF3SDB ,IF3 Status of Data B Read Access" "Low,High"
bitfld.long 0x00 11. " IF3SDA ,IF3 Status of Data A Read Access" "Low,High"
textline " "
bitfld.long 0x00 10. " IF3SC ,IF3 Status of Control Bits Read Access" "Low,High"
bitfld.long 0x00 9. " IF3SA ,IF3 Status of Arbitration Data Read Access" "Low,High"
bitfld.long 0x00 8. " IF3SM ,IF3 Status of Mask Data Read Access" "Low,High"
textline " "
bitfld.long 0x00 4. " DATA_B ,Data B Read Observation" "Not read,Read"
bitfld.long 0x00 3. " DATA_A ,Data A Read Observation" "Not read,Read"
bitfld.long 0x00 2. " CTRL ,Ctrl Read Observation" "Not read,Read"
textline " "
bitfld.long 0x00 1. " ARB ,Arbitration Data Read Observation" "Not read,Read"
bitfld.long 0x00 0. " MASK ,Mask Data Read Observation" "Not read,Read"
if (((d.l((ad:0xFFF7E000+0x148)))&0x40000000)==0x00000000)
rgroup.long 0x144++0x3
line.long 0x0 "IF3MASK,IF3 Mask Register"
bitfld.long 0x00 31. " MXTD ,Mask Extended Identifier" "No effect,Filtering"
bitfld.long 0x00 30. " MDIR ,Mask Message Direction" "No effect,Filtering"
textline " "
bitfld.long 0x00 28. " ID ,Message Identifier bit[28]" "0,1"
bitfld.long 0x00 27. ",Message Identifier bit[27]" "0,1"
bitfld.long 0x00 26. ",Message Identifier bit[26]" "0,1"
bitfld.long 0x00 25. ",Message Identifier bit[25]" "0,1"
bitfld.long 0x00 24. ",Message Identifier bit[24]" "0,1"
bitfld.long 0x00 23. ",Message Identifier bit[23]" "0,1"
bitfld.long 0x00 22. ",Message Identifier bit[22]" "0,1"
bitfld.long 0x00 21. ",Message Identifier bit[21]" "0,1"
bitfld.long 0x00 20. ",Message Identifier bit[20]" "0,1"
bitfld.long 0x00 19. ",Message Identifier bit[19]" "0,1"
bitfld.long 0x00 18. ",Message Identifier bit[18]" "0,1"
else
group.long 0x144++0x3
line.long 0x0 "IF3MASK,IF3 Mask Register"
bitfld.long 0x00 31. " MXTD ,Mask Extended Identifier" "No effect,Filtering"
bitfld.long 0x00 30. " MDIR ,Mask Message Direction" "No effect,Filtering"
textline " "
bitfld.long 0x00 28. " ID ,Message Identifier bit[28]" "0,1"
bitfld.long 0x00 27. ",Message Identifier bit[27]" "0,1"
bitfld.long 0x00 26. ",Message Identifier bit[26]" "0,1"
bitfld.long 0x00 25. ",Message Identifier bit[25]" "0,1"
bitfld.long 0x00 24. ",Message Identifier bit[24]" "0,1"
bitfld.long 0x00 23. ",Message Identifier bit[23]" "0,1"
bitfld.long 0x00 22. ",Message Identifier bit[22]" "0,1"
bitfld.long 0x00 21. ",Message Identifier bit[21]" "0,1"
bitfld.long 0x00 20. ",Message Identifier bit[20]" "0,1"
bitfld.long 0x00 19. ",Message Identifier bit[19]" "0,1"
bitfld.long 0x00 18. ",Message Identifier bit[18]" "0,1"
bitfld.long 0x00 17. ",Message Identifier bit[17]" "0,1"
bitfld.long 0x00 16. ",Message Identifier bit[16]" "0,1"
bitfld.long 0x00 15. ",Message Identifier bit[15]" "0,1"
bitfld.long 0x00 14. ",Message Identifier bit[14]" "0,1"
bitfld.long 0x00 13. ",Message Identifier bit[13]" "0,1"
bitfld.long 0x00 12. ",Message Identifier bit[12]" "0,1"
bitfld.long 0x00 11. ",Message Identifier bit[11]" "0,1"
bitfld.long 0x00 10. ",Message Identifier bit[10]" "0,1"
bitfld.long 0x00 9. ",Message Identifier bit[9]" "0,1"
bitfld.long 0x00 8. ",Message Identifier bit[8]" "0,1"
bitfld.long 0x00 7. ",Message Identifier bit[7]" "0,1"
bitfld.long 0x00 6. ",Message Identifier bit[6]" "0,1"
bitfld.long 0x00 5. ",Message Identifier bit[5]" "0,1"
bitfld.long 0x00 4. ",Message Identifier bit[4]" "0,1"
bitfld.long 0x00 3. ",Message Identifier bit[3]" "0,1"
bitfld.long 0x00 2. ",Message Identifier bit[2]" "0,1"
bitfld.long 0x00 1. ",Message Identifier bit[1]" "0,1"
bitfld.long 0x00 0. ",Message Identifier bit[0]" "0,1"
endif
group.long 0x148++0x3
line.long 0x0 "IF3ARB,IF3 Arbitation Register"
bitfld.long 0x00 31. " MSGVAL ,Message Valid" "Ignored,Configured"
bitfld.long 0x00 30. " XTD ,Extended Identifier" "11-bit,29-bit"
bitfld.long 0x00 29. " DIR ,Message Direction" "Receive,Transmit"
textline " "
hexmask.long 0x00 0.--28. 1. " ID[28-0] ,Message Identifier"
group.long 0x14C++0x3
line.long 0x0 "IF3MCTRL,IF3 Message Control Register"
bitfld.long 0x00 15. " NEWDAT ,New Data" "No new data,New data"
bitfld.long 0x00 14. " MSGLST ,Message Lost" "Not lost,Lost"
bitfld.long 0x00 13. " INTPND ,Interrupt Pending" "No interrupt,Interrupt"
textline " "
bitfld.long 0x00 12. " UMASK ,Use Acceptance Mask" "Ignored,Masked"
bitfld.long 0x00 11. " TXIE ,Transmit Interrupt Enable" "Unchanged,Enabled"
bitfld.long 0x00 10. " RXIE ,Receive Interrupt Enable" "Unchanged,Enabled"
textline " "
bitfld.long 0x00 9. " RMTEN ,Remote Enable" "Unchanged,Enabled"
bitfld.long 0x00 8. " TXRQST ,Transmit Request" "Not requested,Requested"
bitfld.long 0x00 7. " EOB ,End of Block" "Not last,Single/Last"
textline " "
bitfld.long 0x00 0.--3. " DLC[3-0] ,Data Length Code" "0 byte,1 byte,2 bytes,3 bytes,4 bytes,5 bytes,6 bytes,7 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes"
width 12.
group.long 0x150++0x3
line.long 0x0 "IF3DATA,IF3 Data A Register"
hexmask.long.byte 0x00 24.--31. 1. " DATA [3] ,4th data byte of a CAN Data Frame"
hexmask.long.byte 0x00 16.--23. 1. " [2] ,3rd data byte of a CAN Data Frame"
hexmask.long.byte 0x00 8.--15. 1. " [1] ,2nd data byte of a CAN Data Frame"
hexmask.long.byte 0x00 0.--7. 1. " [0] ,1st data byte of a CAN Data Frame"
group.long 0x154++0x3
line.long 0x0 "IF3DATB,IF3 Data B Register"
hexmask.long.byte 0x00 24.--31. 1. " DATA [7] ,8th data byte of a CAN Data Frame"
hexmask.long.byte 0x00 16.--23. 1. " [6] ,7th data byte of a CAN Data Frame"
hexmask.long.byte 0x00 8.--15. 1. " [5] ,6th data byte of a CAN Data Frame"
hexmask.long.byte 0x00 0.--7. 1. " ATA [4] ,5th data byte of a CAN Data Frame"
width 12.
group.long 0x160++0x3
line.long 0x0 "IF3UENA2_1,Update Enable 2_1 Register"
bitfld.long 0x00 31. " IF3UPDATEEN [32] ,IF3 Update Enabled Bit[32]" "Disabled,Enabled"
bitfld.long 0x00 30. " [31] ,IF3 Update Enabled Bit[31]" "Disabled,Enabled"
bitfld.long 0x00 29. " [30] ,IF3 Update Enabled Bit[30]" "Disabled,Enabled"
bitfld.long 0x00 28. " [29] ,IF3 Update Enabled Bit[29]" "Disabled,Enabled"
textline " "
bitfld.long 0x00 27. " [28] ,IF3 Update Enabled Bit[28]" "Disabled,Enabled"
bitfld.long 0x00 26. " [27] ,IF3 Update Enabled Bit[27]" "Disabled,Enabled"
bitfld.long 0x00 25. " [26] ,IF3 Update Enabled Bit[26]" "Disabled,Enabled"
bitfld.long 0x00 24. " [25] ,IF3 Update Enabled Bit[25]" "Disabled,Enabled"
textline " "
bitfld.long 0x00 23. " [24] ,IF3 Update Enabled Bit[24]" "Disabled,Enabled"
bitfld.long 0x00 22. " [23] ,IF3 Update Enabled Bit[23]" "Disabled,Enabled"
bitfld.long 0x00 21. " [22] ,IF3 Update Enabled Bit[22]" "Disabled,Enabled"
bitfld.long 0x00 20. " [21] ,IF3 Update Enabled Bit[21]" "Disabled,Enabled"
textline " "
bitfld.long 0x00 19. " [20] ,IF3 Update Enabled Bit[20]" "Disabled,Enabled"
bitfld.long 0x00 18. " [19] ,IF3 Update Enabled Bit[19]" "Disabled,Enabled"
bitfld.long 0x00 17. " [18] ,IF3 Update Enabled Bit[18]" "Disabled,Enabled"
bitfld.long 0x00 16. " [17] ,IF3 Update Enabled Bit[17]" "Disabled,Enabled"
textline " "
bitfld.long 0x00 15. " [16] ,IF3 Update Enabled Bit[16]" "Disabled,Enabled"
bitfld.long 0x00 14. " [15] ,IF3 Update Enabled Bit[15]" "Disabled,Enabled"
bitfld.long 0x00 13. " [14] ,IF3 Update Enabled Bit[14]" "Disabled,Enabled"
bitfld.long 0x00 12. " [13] ,IF3 Update Enabled Bit[13]" "Disabled,Enabled"
textline " "
bitfld.long 0x00 11. " [12] ,IF3 Update Enabled Bit[12]" "Disabled,Enabled"
bitfld.long 0x00 10. " [11] ,IF3 Update Enabled Bit[11]" "Disabled,Enabled"
bitfld.long 0x00 9. " [10] ,IF3 Update Enabled Bit[10]" "Disabled,Enabled"
bitfld.long 0x00 8. " [9] ,IF3 Update Enabled Bit[9]" "Disabled,Enabled"
textline " "
bitfld.long 0x00 7. " [8] ,IF3 Update Enabled Bit[8]" "Disabled,Enabled"
bitfld.long 0x00 6. " [7] ,IF3 Update Enabled Bit[7]" "Disabled,Enabled"
bitfld.long 0x00 5. " [6] ,IF3 Update Enabled Bit[6]" "Disabled,Enabled"
bitfld.long 0x00 4. " [5] ,IF3 Update Enabled Bit[5]" "Disabled,Enabled"
textline " "
bitfld.long 0x00 3. " [4] ,IF3 Update Enabled Bit[4]" "Disabled,Enabled"
bitfld.long 0x00 2. " [3] ,IF3 Update Enabled Bit[3]" "Disabled,Enabled"
bitfld.long 0x00 1. " [2] ,IF3 Update Enabled Bit[2]" "Disabled,Enabled"
bitfld.long 0x00 0. " [1] ,IF3 Update Enabled Bit[1]" "Disabled,Enabled"
group.long 0x164++0x3
line.long 0x0 "IF3UENA4_3,Update Enable 4_3 Register"
bitfld.long 0x00 31. " IF3UPDATEEN [64] ,IF3 Update Enabled Bit[64]" "Disabled,Enabled"
bitfld.long 0x00 30. " [63] ,IF3 Update Enabled Bit[63]" "Disabled,Enabled"
bitfld.long 0x00 29. " [62] ,IF3 Update Enabled Bit[62]" "Disabled,Enabled"
bitfld.long 0x00 28. " [61] ,IF3 Update Enabled Bit[61]" "Disabled,Enabled"
textline " "
bitfld.long 0x00 27. " [60] ,IF3 Update Enabled Bit[60]" "Disabled,Enabled"
bitfld.long 0x00 26. " [59] ,IF3 Update Enabled Bit[59]" "Disabled,Enabled"
bitfld.long 0x00 25. " [58] ,IF3 Update Enabled Bit[58]" "Disabled,Enabled"
bitfld.long 0x00 24. " [57] ,IF3 Update Enabled Bit[57]" "Disabled,Enabled"
textline " "
bitfld.long 0x00 23. " [56] ,IF3 Update Enabled Bit[56]" "Disabled,Enabled"
bitfld.long 0x00 22. " [55] ,IF3 Update Enabled Bit[55]" "Disabled,Enabled"
bitfld.long 0x00 21. " [54] ,IF3 Update Enabled Bit[54]" "Disabled,Enabled"
bitfld.long 0x00 20. " [53] ,IF3 Update Enabled Bit[53]" "Disabled,Enabled"
textline " "
bitfld.long 0x00 19. " [52] ,IF3 Update Enabled Bit[52]" "Disabled,Enabled"
bitfld.long 0x00 18. " [51] ,IF3 Update Enabled Bit[51]" "Disabled,Enabled"
bitfld.long 0x00 17. " [50] ,IF3 Update Enabled Bit[50]" "Disabled,Enabled"
bitfld.long 0x00 16. " [49] ,IF3 Update Enabled Bit[49]" "Disabled,Enabled"
textline " "
bitfld.long 0x00 15. " [48] ,IF3 Update Enabled Bit[48]" "Disabled,Enabled"
bitfld.long 0x00 14. " [47] ,IF3 Update Enabled Bit[47]" "Disabled,Enabled"
bitfld.long 0x00 13. " [46] ,IF3 Update Enabled Bit[46]" "Disabled,Enabled"
bitfld.long 0x00 12. " [45] ,IF3 Update Enabled Bit[45]" "Disabled,Enabled"
textline " "
bitfld.long 0x00 11. " [44] ,IF3 Update Enabled Bit[44]" "Disabled,Enabled"
bitfld.long 0x00 10. " [43] ,IF3 Update Enabled Bit[43]" "Disabled,Enabled"
bitfld.long 0x00 9. " [42] ,IF3 Update Enabled Bit[42]" "Disabled,Enabled"
bitfld.long 0x00 8. " [41] ,IF3 Update Enabled Bit[41]" "Disabled,Enabled"
textline " "
bitfld.long 0x00 7. " [40] ,IF3 Update Enabled Bit[40]" "Disabled,Enabled"
bitfld.long 0x00 6. " [39] ,IF3 Update Enabled Bit[39]" "Disabled,Enabled"
bitfld.long 0x00 5. " [38] ,IF3 Update Enabled Bit[38]" "Disabled,Enabled"
bitfld.long 0x00 4. " [37] ,IF3 Update Enabled Bit[37]" "Disabled,Enabled"
textline " "
bitfld.long 0x00 3. " [36] ,IF3 Update Enabled Bit[36]" "Disabled,Enabled"
bitfld.long 0x00 2. " [35] ,IF3 Update Enabled Bit[35]" "Disabled,Enabled"
bitfld.long 0x00 1. " [34] ,IF3 Update Enabled Bit[34]" "Disabled,Enabled"
bitfld.long 0x00 0. " [33] ,IF3 Update Enabled Bit[33]" "Disabled,Enabled"
group.long 0x168++0x3
line.long 0x0 "IF3UENA6_5,Update Enable 6_5 Register"
bitfld.long 0x00 31. " IF3UPDATEEN [96] ,IF3 Update Enabled Bit[96]" "Disabled,Enabled"
bitfld.long 0x00 30. " [95] ,IF3 Update Enabled Bit[95]" "Disabled,Enabled"
bitfld.long 0x00 29. " [94] ,IF3 Update Enabled Bit[94]" "Disabled,Enabled"
bitfld.long 0x00 28. " [93] ,IF3 Update Enabled Bit[93]" "Disabled,Enabled"
textline " "
bitfld.long 0x00 27. " [92] ,IF3 Update Enabled Bit[92]" "Disabled,Enabled"
bitfld.long 0x00 26. " [91] ,IF3 Update Enabled Bit[91]" "Disabled,Enabled"
bitfld.long 0x00 25. " [90] ,IF3 Update Enabled Bit[90]" "Disabled,Enabled"
bitfld.long 0x00 24. " [89] ,IF3 Update Enabled Bit[89]" "Disabled,Enabled"
textline " "
bitfld.long 0x00 23. " [88] ,IF3 Update Enabled Bit[88]" "Disabled,Enabled"
bitfld.long 0x00 22. " [87] ,IF3 Update Enabled Bit[87]" "Disabled,Enabled"
bitfld.long 0x00 21. " [86] ,IF3 Update Enabled Bit[86]" "Disabled,Enabled"
bitfld.long 0x00 20. " [85] ,IF3 Update Enabled Bit[85]" "Disabled,Enabled"
textline " "
bitfld.long 0x00 19. " [84] ,IF3 Update Enabled Bit[84]" "Disabled,Enabled"
bitfld.long 0x00 18. " [83] ,IF3 Update Enabled Bit[83]" "Disabled,Enabled"
bitfld.long 0x00 17. " [82] ,IF3 Update Enabled Bit[82]" "Disabled,Enabled"
bitfld.long 0x00 16. " [81] ,IF3 Update Enabled Bit[81]" "Disabled,Enabled"
textline " "
bitfld.long 0x00 15. " [80] ,IF3 Update Enabled Bit[80]" "Disabled,Enabled"
bitfld.long 0x00 14. " [79] ,IF3 Update Enabled Bit[79]" "Disabled,Enabled"
bitfld.long 0x00 13. " [78] ,IF3 Update Enabled Bit[78]" "Disabled,Enabled"
bitfld.long 0x00 12. " [77] ,IF3 Update Enabled Bit[77]" "Disabled,Enabled"
textline " "
bitfld.long 0x00 11. " [76] ,IF3 Update Enabled Bit[76]" "Disabled,Enabled"
bitfld.long 0x00 10. " [75] ,IF3 Update Enabled Bit[75]" "Disabled,Enabled"
bitfld.long 0x00 9. " [74] ,IF3 Update Enabled Bit[74]" "Disabled,Enabled"
bitfld.long 0x00 8. " [73] ,IF3 Update Enabled Bit[73]" "Disabled,Enabled"
textline " "
bitfld.long 0x00 7. " [72] ,IF3 Update Enabled Bit[72]" "Disabled,Enabled"
bitfld.long 0x00 6. " [71] ,IF3 Update Enabled Bit[71]" "Disabled,Enabled"
bitfld.long 0x00 5. " [70] ,IF3 Update Enabled Bit[70]" "Disabled,Enabled"
bitfld.long 0x00 4. " [69] ,IF3 Update Enabled Bit[69]" "Disabled,Enabled"
textline " "
bitfld.long 0x00 3. " [68] ,IF3 Update Enabled Bit[68]" "Disabled,Enabled"
bitfld.long 0x00 2. " [67] ,IF3 Update Enabled Bit[67]" "Disabled,Enabled"
bitfld.long 0x00 1. " [66] ,IF3 Update Enabled Bit[66]" "Disabled,Enabled"
bitfld.long 0x00 0. " [65] ,IF3 Update Enabled Bit[65]" "Disabled,Enabled"
group.long 0x16C++0x3
line.long 0x0 "IF3UENA8_7,Update Enable 8_7 Register"
bitfld.long 0x00 31. " IF3UPDATEEN [128] ,IF3 Update Enabled Bit[128]" "Disabled,Enabled"
bitfld.long 0x00 30. " [127] ,IF3 Update Enabled Bit[127]" "Disabled,Enabled"
bitfld.long 0x00 29. " [126] ,IF3 Update Enabled Bit[126]" "Disabled,Enabled"
bitfld.long 0x00 28. " [125] ,IF3 Update Enabled Bit[125]" "Disabled,Enabled"
textline " "
bitfld.long 0x00 27. " [124] ,IF3 Update Enabled Bit[124]" "Disabled,Enabled"
bitfld.long 0x00 26. " [123] ,IF3 Update Enabled Bit[123]" "Disabled,Enabled"
bitfld.long 0x00 25. " [122] ,IF3 Update Enabled Bit[122]" "Disabled,Enabled"
bitfld.long 0x00 24. " [121] ,IF3 Update Enabled Bit[121]" "Disabled,Enabled"
textline " "
bitfld.long 0x00 23. " [120] ,IF3 Update Enabled Bit[120]" "Disabled,Enabled"
bitfld.long 0x00 22. " [119] ,IF3 Update Enabled Bit[119]" "Disabled,Enabled"
bitfld.long 0x00 21. " [118] ,IF3 Update Enabled Bit[118]" "Disabled,Enabled"
bitfld.long 0x00 20. " [117] ,IF3 Update Enabled Bit[117]" "Disabled,Enabled"
textline " "
bitfld.long 0x00 19. " [116] ,IF3 Update Enabled Bit[116]" "Disabled,Enabled"
bitfld.long 0x00 18. " [115] ,IF3 Update Enabled Bit[115]" "Disabled,Enabled"
bitfld.long 0x00 17. " [114] ,IF3 Update Enabled Bit[114]" "Disabled,Enabled"
bitfld.long 0x00 16. " [113] ,IF3 Update Enabled Bit[113]" "Disabled,Enabled"
textline " "
bitfld.long 0x00 15. " [112] ,IF3 Update Enabled Bit[112]" "Disabled,Enabled"
bitfld.long 0x00 14. " [111] ,IF3 Update Enabled Bit[111]" "Disabled,Enabled"
bitfld.long 0x00 13. " [110] ,IF3 Update Enabled Bit[110]" "Disabled,Enabled"
bitfld.long 0x00 12. " [109] ,IF3 Update Enabled Bit[109]" "Disabled,Enabled"
textline " "
bitfld.long 0x00 11. " [108] ,IF3 Update Enabled Bit[108]" "Disabled,Enabled"
bitfld.long 0x00 10. " [107] ,IF3 Update Enabled Bit[107]" "Disabled,Enabled"
bitfld.long 0x00 9. " [106] ,IF3 Update Enabled Bit[106]" "Disabled,Enabled"
bitfld.long 0x00 8. " [105] ,IF3 Update Enabled Bit[105]" "Disabled,Enabled"
textline " "
bitfld.long 0x00 7. " [104] ,IF3 Update Enabled Bit[104]" "Disabled,Enabled"
bitfld.long 0x00 6. " [103] ,IF3 Update Enabled Bit[103]" "Disabled,Enabled"
bitfld.long 0x00 5. " [102] ,IF3 Update Enabled Bit[102]" "Disabled,Enabled"
bitfld.long 0x00 4. " [101] ,IF3 Update Enabled Bit[101]" "Disabled,Enabled"
textline " "
bitfld.long 0x00 3. " [100] ,IF3 Update Enabled Bit[100]" "Disabled,Enabled"
bitfld.long 0x00 2. " [99] ,IF3 Update Enabled Bit[99]" "Disabled,Enabled"
bitfld.long 0x00 1. " [98] ,IF3 Update Enabled Bit[98]" "Disabled,Enabled"
bitfld.long 0x00 0. " [97] ,IF3 Update Enabled Bit[97]" "Disabled,Enabled"
width 12.
group.long 0x1E0++0x3
line.long 0x0 "IOCTRLTX,TX IO Control Register"
bitfld.long 0x00 18. " PU ,Selection of Pull Direction" "Pull down,Pull up"
bitfld.long 0x00 17. " PD ,Pull Functionality Disable" "No,Yes"
bitfld.long 0x00 16. " OD ,Open Drain Mode" "Push pull,Open Drain"
textline " "
bitfld.long 0x00 3. " FUNC ,Functionality of Pin" "General,CAN"
bitfld.long 0x00 2. " DIR ,Direction of Pin" "Input,Output"
bitfld.long 0x00 1. " OUT ,Value to Drive to Pin if Configured for I/O" "Low,High"
textline " "
bitfld.long 0x00 0. " IN ,Value of Pin" "Low,High"
group.long 0x1E4++0x3
line.long 0x0 "IOCTRLRX,RX IO Control Register"
bitfld.long 0x00 18. " PU ,Selection of Pull Direction" "Pull down,Pull up"
bitfld.long 0x00 17. " PD ,Pull Functionality Disable" "No,Yes"
bitfld.long 0x00 16. " OD ,Open Drain Mode" "Push pull,Open Drain"
textline " "
bitfld.long 0x00 3. " FUNC ,Functionality of Pin" "General,CAN"
bitfld.long 0x00 2. " DIR ,Direction of Pin" "Input,Output"
bitfld.long 0x00 1. " OUT ,Value to Drive to Pin if Configured for I/O" "Low,High"
textline " "
bitfld.long 0x00 0. " IN ,Value of Pin" "Low,High"
width 0xb
tree.end
tree "DCAN4"
base ad:0xFFF7E200
width 12.
group.long 0x00++0x3
line.long 0x0 "CTRL,Config Register"
bitfld.long 0x00 25. " WUBA ,Automatic Wake Up on Bus Activity When in Local Power Down Mode" "Not detected,Detected"
bitfld.long 0x00 24. " PDR ,Request for Local Low Power Down Mode" "Not requested,Power down"
bitfld.long 0x00 20. " DE3 ,DMA Enable for IF3" "Disabled,Enabled"
textline " "
bitfld.long 0x00 19. " DE2 ,DMA Enable for IF2" "Disabled,Enabled"
bitfld.long 0x00 18. " DE1 ,DMA Enable for IF1" "Disabled,Enabled"
bitfld.long 0x00 17. " IE1 ,DCAN1INT Interrupt Enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 16. " INITDBG ,Internal Init State While Debug Access Mode" "No debug,Debug"
bitfld.long 0x00 15. " SWR ,SW Reset Enable" "No reset,Reset"
bitfld.long 0x00 10.--13. " PMD ,Parity on/off" "Enabled,Enabled,Enabled,Enabled,Enabled,Disabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled"
textline " "
bitfld.long 0x00 9. " ABO ,Auto Bus On Enable" "Disabled,Enabled"
bitfld.long 0x00 8. " IDS ,Interruption Debug Support Enable" "Disabled,Enabled"
bitfld.long 0x00 7. " TEST ,Test Mode Enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 6. " CCE ,Configuration Change Enable" "No write,Write"
bitfld.long 0x00 5. " DAR ,Disable Automatic Retransmission" "No,Yes"
bitfld.long 0x00 3. " EIE ,Error Interrupt Enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 2. " SIE ,Status Interrupt Enable" "Disabled,Enabled"
bitfld.long 0x00 1. " IE ,DCAN0INT Interrupt Enable" "Disabled,Enabled"
bitfld.long 0x00 0. " INIT ,Initialization" "Disabled,Enabled"
hgroup.long 0x04++0x3
hide.long 0x0 "ES,Error and Status Register"
in
width 12.
rgroup.long 0x08++0x3
line.long 0x0 "ERRC,Error Counter Register"
bitfld.long 0x00 15. " RP ,Receive Error Passive" "Below,Reached"
hexmask.long.byte 0x00 8.--14. 1. " REC[6-0] ,Receive Error Counter"
hexmask.long.byte 0x00 0.--7. 1. " TEC[7-0] ,Transmit Error Counter"
group.long 0x0C++0x3
line.long 0x0 "BTBRP,Bit Timing_BRP Extension Register"
bitfld.long 0x00 16.--19. " BRPE ,Baud Rate Prescaler Extension" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 12.--14. " TSEG2 ,The Time Segment After the Sample Point" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 8.--11. " TSEG1 ,The Time Segment Before the Sample Point" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x00 6.--7. " SJW ,Synchronization Jump Width" "0,1,2,3"
bitfld.long 0x00 0.--5. " BRP ,Baud Rate Prescaler" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
rgroup.long 0x10++0x3
line.long 0x0 "INTR,Interrupt Register"
hexmask.long.byte 0x00 16.--23. 1. " INT1ID[7-0] ,Interrupt 1 Identifier"
hexmask.long.word 0x00 0.--15. 1. " INTID[15-0] ,Interrupt Identifier"
width 12.
group.long 0x14++0x3
line.long 0x0 "TEST,Test Register"
bitfld.long 0x00 9. " RDA ,RAM Direct Access Enable" "Disabled,Enabled"
bitfld.long 0x00 8. " EXL ,External Loop Back Mode" "Disabled,Enabled"
bitfld.long 0x00 7. " RX ,Receive Pin" "Dominant,Recessive"
textline " "
bitfld.long 0x00 5.--6. " TX1-0 ,Control of CAN_TX pin" "Normal,Sample point,Dominant,Recessive"
bitfld.long 0x00 4. " LBACK ,Loop Back Mode" "Disabled,Enabled"
bitfld.long 0x00 3. " SILENT ,Silent Mode" "Disabled,Enabled"
rgroup.long 0x1C++0x3
line.long 0x0 "PERR,Parity Error Code Register"
bitfld.long 0x00 8.--10. " WORD_NUMBER ,Word Number" ",1,2,3,4,5,?..."
hexmask.long.byte 0x00 0.--7. 1. " MESSAGE_NUMBER ,Message Number"
width 19.
group.long 0x24++0x03
line.long 0x00 "DCAN_ECCDIAG, ECC Diagnostic Register"
bitfld.long 0x00 0.--3. " ECCDIAG , SECDED diagnostic mode enable/disable" ",,,,,Enabled,,,,,Disabled,?..."
group.long 0x28++0x03
line.long 0x00 "DCAN_ECCDIAG_STAT, ECC Diagnostic Status Register"
eventfld.long 0x00 8. " DEFLG_DIAG , Double bit error diagnostic" "No error,Error"
eventfld.long 0x00 0. " SEFLG_DIAG , Single bit error diagnostic" "No error,Error"
group.long 0x2C++0x03
line.long 0x00 "DCAN_ECC_CS, ECC Control and Status Register"
bitfld.long 0x00 24.--27. " SBE_EVT_EN , Single bit error event" "Enabled,Enabled,Enabled,Enabled,Enabled,Disabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled"
bitfld.long 0x00 16.--19. " ECCMODE , Single bit error correction" "Enabled,Enabled,Enabled,Enabled,Enabled,Disabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled"
eventfld.long 0x00 8. " DEFLG , Double bit error flag" "No error,Error"
eventfld.long 0x00 0. " SEFLG , Single bit error flag" "No error,Error"
rgroup.long 0x30++0x03
line.long 0x00 "DCAN_ECC_SERR, ECC Single Bit Error Code Register"
hexmask.long.byte 0x00 0.--7. 1. " Message_Number , Message object number where ECC single bit error has been detected"
group.long 0x80++0x3
line.long 0x0 "ABOT,Auto Bus On Time"
width 12.
rgroup.long 0x84++0x3
line.long 0x0 "TRREQ,Transmission Request X"
bitfld.long 0x00 14.--15. " TXRQSTREG [8] ,Transmission Request 8" "0,1,2,3"
bitfld.long 0x00 12.--13. " [7] ,Transmission Request 7" "0,1,2,3"
bitfld.long 0x00 10.--11. " [6] ,Transmission Request 6" "0,1,2,3"
bitfld.long 0x00 8.--9. " [5] ,Transmission Request 5" "0,1,2,3"
textline " "
bitfld.long 0x00 6.--7. " [4] ,Transmission Request 4" "0,1,2,3"
bitfld.long 0x00 4.--5. " [3] ,Transmission Request 3" "0,1,2,3"
bitfld.long 0x00 2.--3. " [2] ,Transmission Request 2" "0,1,2,3"
bitfld.long 0x00 0.--1. " [1] ,Transmission Request 1" "0,1,2,3"
width 12.
rgroup.long 0x88++0x3
line.long 0x0 "TRREQ21,Transmission Request 2_1"
bitfld.long 0x00 31. " TXRQST [32] ,Transmission Request Bits[32]" "Not requested,Requested"
bitfld.long 0x00 30. " [31] ,Transmission Request Bits[31]" "Not requested,Requested"
bitfld.long 0x00 29. " [30] ,Transmission Request Bits[30]" "Not requested,Requested"
bitfld.long 0x00 28. " [29] ,Transmission Request Bits[29]" "Not requested,Requested"
textline " "
bitfld.long 0x00 27. " [28] ,Transmission Request Bits[28]" "Not requested,Requested"
bitfld.long 0x00 26. " [27] ,Transmission Request Bits[27]" "Not requested,Requested"
bitfld.long 0x00 25. " [26] ,Transmission Request Bits[26]" "Not requested,Requested"
bitfld.long 0x00 24. " [25] ,Transmission Request Bits[25]" "Not requested,Requested"
textline " "
bitfld.long 0x00 23. " [24] ,Transmission Request Bits[24]" "Not requested,Requested"
bitfld.long 0x00 22. " [23] ,Transmission Request Bits[23]" "Not requested,Requested"
bitfld.long 0x00 21. " [22] ,Transmission Request Bits[22]" "Not requested,Requested"
bitfld.long 0x00 20. " [21] ,Transmission Request Bits[21]" "Not requested,Requested"
textline " "
bitfld.long 0x00 19. " [20] ,Transmission Request Bits[20]" "Not requested,Requested"
bitfld.long 0x00 18. " [19] ,Transmission Request Bits[19]" "Not requested,Requested"
bitfld.long 0x00 17. " [18] ,Transmission Request Bits[18]" "Not requested,Requested"
bitfld.long 0x00 16. " [17] ,Transmission Request Bits[17]" "Not requested,Requested"
textline " "
bitfld.long 0x00 15. " [16] ,Transmission Request Bits[16]" "Not requested,Requested"
bitfld.long 0x00 14. " [15] ,Transmission Request Bits[15]" "Not requested,Requested"
bitfld.long 0x00 13. " [14] ,Transmission Request Bits[14]" "Not requested,Requested"
bitfld.long 0x00 12. " [13] ,Transmission Request Bits[13]" "Not requested,Requested"
textline " "
bitfld.long 0x00 11. " [12] ,Transmission Request Bits[12]" "Not requested,Requested"
bitfld.long 0x00 10. " [11] ,Transmission Request Bits[11]" "Not requested,Requested"
bitfld.long 0x00 9. " [10] ,Transmission Request Bits[10]" "Not requested,Requested"
bitfld.long 0x00 8. " [9] ,Transmission Request Bits[9]" "Not requested,Requested"
textline " "
bitfld.long 0x00 7. " [8] ,Transmission Request Bits[8]" "Not requested,Requested"
bitfld.long 0x00 6. " [7] ,Transmission Request Bits[7]" "Not requested,Requested"
bitfld.long 0x00 5. " [6] ,Transmission Request Bits[6]" "Not requested,Requested"
bitfld.long 0x00 4. " [5] ,Transmission Request Bits[5]" "Not requested,Requested"
textline " "
bitfld.long 0x00 3. " [4] ,Transmission Request Bits[4]" "Not requested,Requested"
bitfld.long 0x00 2. " [3] ,Transmission Request Bits[3]" "Not requested,Requested"
bitfld.long 0x00 1. " [2] ,Transmission Request Bits[2]" "Not requested,Requested"
bitfld.long 0x00 0. " [1] ,Transmission Request Bits[1]" "Not requested,Requested"
rgroup.long 0x8C++0x3
line.long 0x0 "TRREQ43,Transmission Request 4_3"
bitfld.long 0x00 31. " TXRQST [64] ,Transmission Request Bits[64]" "Not requested,Requested"
bitfld.long 0x00 30. " [63] ,Transmission Request Bits[63]" "Not requested,Requested"
bitfld.long 0x00 29. " [62] ,Transmission Request Bits[62]" "Not requested,Requested"
bitfld.long 0x00 28. " [61] ,Transmission Request Bits[61]" "Not requested,Requested"
textline " "
bitfld.long 0x00 27. " [60] ,Transmission Request Bits[60]" "Not requested,Requested"
bitfld.long 0x00 26. " [59] ,Transmission Request Bits[59]" "Not requested,Requested"
bitfld.long 0x00 25. " [58] ,Transmission Request Bits[58]" "Not requested,Requested"
bitfld.long 0x00 24. " [57] ,Transmission Request Bits[57]" "Not requested,Requested"
textline " "
bitfld.long 0x00 23. " [56] ,Transmission Request Bits[56]" "Not requested,Requested"
bitfld.long 0x00 22. " [55] ,Transmission Request Bits[55]" "Not requested,Requested"
bitfld.long 0x00 21. " [54] ,Transmission Request Bits[54]" "Not requested,Requested"
bitfld.long 0x00 20. " [53] ,Transmission Request Bits[53]" "Not requested,Requested"
textline " "
bitfld.long 0x00 19. " [52] ,Transmission Request Bits[52]" "Not requested,Requested"
bitfld.long 0x00 18. " [51] ,Transmission Request Bits[51]" "Not requested,Requested"
bitfld.long 0x00 17. " [50] ,Transmission Request Bits[50]" "Not requested,Requested"
bitfld.long 0x00 16. " [49] ,Transmission Request Bits[49]" "Not requested,Requested"
textline " "
bitfld.long 0x00 15. " [48] ,Transmission Request Bits[48]" "Not requested,Requested"
bitfld.long 0x00 14. " [47] ,Transmission Request Bits[47]" "Not requested,Requested"
bitfld.long 0x00 13. " [46] ,Transmission Request Bits[46]" "Not requested,Requested"
bitfld.long 0x00 12. " [45] ,Transmission Request Bits[45]" "Not requested,Requested"
textline " "
bitfld.long 0x00 11. " [44] ,Transmission Request Bits[44]" "Not requested,Requested"
bitfld.long 0x00 10. " [43] ,Transmission Request Bits[43]" "Not requested,Requested"
bitfld.long 0x00 9. " [42] ,Transmission Request Bits[42]" "Not requested,Requested"
bitfld.long 0x00 8. " [41] ,Transmission Request Bits[41]" "Not requested,Requested"
textline " "
bitfld.long 0x00 7. " [40] ,Transmission Request Bits[40]" "Not requested,Requested"
bitfld.long 0x00 6. " [39] ,Transmission Request Bits[39]" "Not requested,Requested"
bitfld.long 0x00 5. " [38] ,Transmission Request Bits[38]" "Not requested,Requested"
bitfld.long 0x00 4. " [37] ,Transmission Request Bits[37]" "Not requested,Requested"
textline " "
bitfld.long 0x00 3. " [36] ,Transmission Request Bits[36]" "Not requested,Requested"
bitfld.long 0x00 2. " [35] ,Transmission Request Bits[35]" "Not requested,Requested"
bitfld.long 0x00 1. " [34] ,Transmission Request Bits[34]" "Not requested,Requested"
bitfld.long 0x00 0. " [33] ,Transmission Request Bits[33]" "Not requested,Requested"
rgroup.long 0x90++0x3
line.long 0x0 "TRREQ65,Transmission Request 6_5"
bitfld.long 0x00 31. " TXRQST [96] ,Transmission Request Bits[96]" "Not requested,Requested"
bitfld.long 0x00 30. " [95] ,Transmission Request Bits[95]" "Not requested,Requested"
bitfld.long 0x00 29. " [94] ,Transmission Request Bits[94]" "Not requested,Requested"
bitfld.long 0x00 28. " [93] ,Transmission Request Bits[93]" "Not requested,Requested"
textline " "
bitfld.long 0x00 27. " [92] ,Transmission Request Bits[92]" "Not requested,Requested"
bitfld.long 0x00 26. " [91] ,Transmission Request Bits[91]" "Not requested,Requested"
bitfld.long 0x00 25. " [90] ,Transmission Request Bits[90]" "Not requested,Requested"
bitfld.long 0x00 24. " [89] ,Transmission Request Bits[89]" "Not requested,Requested"
textline " "
bitfld.long 0x00 23. " [88] ,Transmission Request Bits[88]" "Not requested,Requested"
bitfld.long 0x00 22. " [87] ,Transmission Request Bits[87]" "Not requested,Requested"
bitfld.long 0x00 21. " [86] ,Transmission Request Bits[86]" "Not requested,Requested"
bitfld.long 0x00 20. " [85] ,Transmission Request Bits[85]" "Not requested,Requested"
textline " "
bitfld.long 0x00 19. " [84] ,Transmission Request Bits[84]" "Not requested,Requested"
bitfld.long 0x00 18. " [83] ,Transmission Request Bits[83]" "Not requested,Requested"
bitfld.long 0x00 17. " [82] ,Transmission Request Bits[82]" "Not requested,Requested"
bitfld.long 0x00 16. " [81] ,Transmission Request Bits[81]" "Not requested,Requested"
textline " "
bitfld.long 0x00 15. " [80] ,Transmission Request Bits[80]" "Not requested,Requested"
bitfld.long 0x00 14. " [79] ,Transmission Request Bits[79]" "Not requested,Requested"
bitfld.long 0x00 13. " [78] ,Transmission Request Bits[78]" "Not requested,Requested"
bitfld.long 0x00 12. " [77] ,Transmission Request Bits[77]" "Not requested,Requested"
textline " "
bitfld.long 0x00 11. " [76] ,Transmission Request Bits[76]" "Not requested,Requested"
bitfld.long 0x00 10. " [75] ,Transmission Request Bits[75]" "Not requested,Requested"
bitfld.long 0x00 9. " [74] ,Transmission Request Bits[74]" "Not requested,Requested"
bitfld.long 0x00 8. " [73] ,Transmission Request Bits[73]" "Not requested,Requested"
textline " "
bitfld.long 0x00 7. " [72] ,Transmission Request Bits[72]" "Not requested,Requested"
bitfld.long 0x00 6. " [71] ,Transmission Request Bits[71]" "Not requested,Requested"
bitfld.long 0x00 5. " [70] ,Transmission Request Bits[70]" "Not requested,Requested"
bitfld.long 0x00 4. " [69] ,Transmission Request Bits[69]" "Not requested,Requested"
textline " "
bitfld.long 0x00 3. " [68] ,Transmission Request Bits[68]" "Not requested,Requested"
bitfld.long 0x00 2. " [67] ,Transmission Request Bits[67]" "Not requested,Requested"
bitfld.long 0x00 1. " [66] ,Transmission Request Bits[66]" "Not requested,Requested"
bitfld.long 0x00 0. " [65] ,Transmission Request Bits[65]" "Not requested,Requested"
rgroup.long 0x94++0x3
line.long 0x0 "TRREQ87,Transmission Request 8_7"
bitfld.long 0x00 31. " TXRQST [128] ,Transmission Request Bits[128]" "Not requested,Requested"
bitfld.long 0x00 30. " [127] ,Transmission Request Bits[127]" "Not requested,Requested"
bitfld.long 0x00 29. " [126] ,Transmission Request Bits[126]" "Not requested,Requested"
bitfld.long 0x00 28. " [125] ,Transmission Request Bits[125]" "Not requested,Requested"
textline " "
bitfld.long 0x00 27. " [124] ,Transmission Request Bits[124]" "Not requested,Requested"
bitfld.long 0x00 26. " [123] ,Transmission Request Bits[123]" "Not requested,Requested"
bitfld.long 0x00 25. " [122] ,Transmission Request Bits[122]" "Not requested,Requested"
bitfld.long 0x00 24. " [121] ,Transmission Request Bits[121]" "Not requested,Requested"
textline " "
bitfld.long 0x00 23. " [120] ,Transmission Request Bits[120]" "Not requested,Requested"
bitfld.long 0x00 22. " [119] ,Transmission Request Bits[119]" "Not requested,Requested"
bitfld.long 0x00 21. " [118] ,Transmission Request Bits[118]" "Not requested,Requested"
bitfld.long 0x00 20. " [117] ,Transmission Request Bits[117]" "Not requested,Requested"
textline " "
bitfld.long 0x00 19. " [116] ,Transmission Request Bits[116]" "Not requested,Requested"
bitfld.long 0x00 18. " [115] ,Transmission Request Bits[115]" "Not requested,Requested"
bitfld.long 0x00 17. " [114] ,Transmission Request Bits[114]" "Not requested,Requested"
bitfld.long 0x00 16. " [113] ,Transmission Request Bits[113]" "Not requested,Requested"
textline " "
bitfld.long 0x00 15. " [112] ,Transmission Request Bits[112]" "Not requested,Requested"
bitfld.long 0x00 14. " [111] ,Transmission Request Bits[111]" "Not requested,Requested"
bitfld.long 0x00 13. " [110] ,Transmission Request Bits[110]" "Not requested,Requested"
bitfld.long 0x00 12. " [109] ,Transmission Request Bits[109]" "Not requested,Requested"
textline " "
bitfld.long 0x00 11. " [108] ,Transmission Request Bits[108]" "Not requested,Requested"
bitfld.long 0x00 10. " [107] ,Transmission Request Bits[107]" "Not requested,Requested"
bitfld.long 0x00 9. " [106] ,Transmission Request Bits[106]" "Not requested,Requested"
bitfld.long 0x00 8. " [105] ,Transmission Request Bits[105]" "Not requested,Requested"
textline " "
bitfld.long 0x00 7. " [104] ,Transmission Request Bits[104]" "Not requested,Requested"
bitfld.long 0x00 6. " [103] ,Transmission Request Bits[103]" "Not requested,Requested"
bitfld.long 0x00 5. " [102] ,Transmission Request Bits[102]" "Not requested,Requested"
bitfld.long 0x00 4. " [101] ,Transmission Request Bits[101]" "Not requested,Requested"
textline " "
bitfld.long 0x00 3. " [100] ,Transmission Request Bits[100]" "Not requested,Requested"
bitfld.long 0x00 2. " [99] ,Transmission Request Bits[99]" "Not requested,Requested"
bitfld.long 0x00 1. " [98] ,Transmission Request Bits[98]" "Not requested,Requested"
bitfld.long 0x00 0. " [97] ,Transmission Request Bits[97]" "Not requested,Requested"
width 12.
rgroup.long 0x98++0x3
line.long 0x0 "NEWDAT,New Data X"
bitfld.long 0x00 14.--15. " NEWDATREG [8] ,New Data 8" "0,1,2,3"
bitfld.long 0x00 12.--13. " [7] ,New Data 7" "0,1,2,3"
bitfld.long 0x00 10.--11. " [6] ,New Data 6" "0,1,2,3"
bitfld.long 0x00 8.--9. " [5] ,New Data 5" "0,1,2,3"
textline " "
bitfld.long 0x00 6.--7. " [4] ,New Data 4" "0,1,2,3"
bitfld.long 0x00 4.--5. " [3] ,New Data 3" "0,1,2,3"
bitfld.long 0x00 2.--3. " [2] ,New Data 2" "0,1,2,3"
bitfld.long 0x00 0.--1. " [1] ,New Data 1" "0,1,2,3"
width 12.
rgroup.long 0x9C++0x3
line.long 0x0 "NEWDAT21,New Data 2_1"
bitfld.long 0x00 31. " NEWDAT [32] ,New Data Bit[32]" "Not requested,Requested"
bitfld.long 0x00 30. " [31] ,New Data Bit[31]" "Not requested,Requested"
bitfld.long 0x00 29. " [30] ,New Data Bit[30]" "Not requested,Requested"
bitfld.long 0x00 28. " [29] ,New Data Bit[29]" "Not requested,Requested"
textline " "
bitfld.long 0x00 27. " [28] ,New Data Bit[28]" "Not requested,Requested"
bitfld.long 0x00 26. " [27] ,New Data Bit[27]" "Not requested,Requested"
bitfld.long 0x00 25. " [26] ,New Data Bit[26]" "Not requested,Requested"
bitfld.long 0x00 24. " [25] ,New Data Bit[25]" "Not requested,Requested"
textline " "
bitfld.long 0x00 23. " [24] ,New Data Bit[24]" "Not requested,Requested"
bitfld.long 0x00 22. " [23] ,New Data Bit[23]" "Not requested,Requested"
bitfld.long 0x00 21. " [22] ,New Data Bit[22]" "Not requested,Requested"
bitfld.long 0x00 20. " [21] ,New Data Bit[21]" "Not requested,Requested"
textline " "
bitfld.long 0x00 19. " [20] ,New Data Bit[20]" "Not requested,Requested"
bitfld.long 0x00 18. " [19] ,New Data Bit[19]" "Not requested,Requested"
bitfld.long 0x00 17. " [18] ,New Data Bit[18]" "Not requested,Requested"
bitfld.long 0x00 16. " [17] ,New Data Bit[17]" "Not requested,Requested"
textline " "
bitfld.long 0x00 15. " [16] ,New Data Bit[16]" "Not requested,Requested"
bitfld.long 0x00 14. " [15] ,New Data Bit[15]" "Not requested,Requested"
bitfld.long 0x00 13. " [14] ,New Data Bit[14]" "Not requested,Requested"
bitfld.long 0x00 12. " [13] ,New Data Bit[13]" "Not requested,Requested"
textline " "
bitfld.long 0x00 11. " [12] ,New Data Bit[12]" "Not requested,Requested"
bitfld.long 0x00 10. " [11] ,New Data Bit[11]" "Not requested,Requested"
bitfld.long 0x00 9. " [10] ,New Data Bit[10]" "Not requested,Requested"
bitfld.long 0x00 8. " [9] ,New Data Bit[9]" "Not requested,Requested"
textline " "
bitfld.long 0x00 7. " [8] ,New Data Bit[8]" "Not requested,Requested"
bitfld.long 0x00 6. " [7] ,New Data Bit[7]" "Not requested,Requested"
bitfld.long 0x00 5. " [6] ,New Data Bit[6]" "Not requested,Requested"
bitfld.long 0x00 4. " [5] ,New Data Bit[5]" "Not requested,Requested"
textline " "
bitfld.long 0x00 3. " [4] ,New Data Bit[4]" "Not requested,Requested"
bitfld.long 0x00 2. " [3] ,New Data Bit[3]" "Not requested,Requested"
bitfld.long 0x00 1. " [2] ,New Data Bit[2]" "Not requested,Requested"
bitfld.long 0x00 0. " [1] ,New Data Bit[1]" "Not requested,Requested"
rgroup.long 0xA0++0x3
line.long 0x0 "NEWDAT43,New Data 4_3"
bitfld.long 0x00 31. " NEWDAT [64] ,New Data Bit[64]" "Not requested,Requested"
bitfld.long 0x00 30. " [63] ,New Data Bit[63]" "Not requested,Requested"
bitfld.long 0x00 29. " [62] ,New Data Bit[62]" "Not requested,Requested"
bitfld.long 0x00 28. " [61] ,New Data Bit[61]" "Not requested,Requested"
textline " "
bitfld.long 0x00 27. " [60] ,New Data Bit[60]" "Not requested,Requested"
bitfld.long 0x00 26. " [59] ,New Data Bit[59]" "Not requested,Requested"
bitfld.long 0x00 25. " [58] ,New Data Bit[58]" "Not requested,Requested"
bitfld.long 0x00 24. " [57] ,New Data Bit[57]" "Not requested,Requested"
textline " "
bitfld.long 0x00 23. " [56] ,New Data Bit[56]" "Not requested,Requested"
bitfld.long 0x00 22. " [55] ,New Data Bit[55]" "Not requested,Requested"
bitfld.long 0x00 21. " [54] ,New Data Bit[54]" "Not requested,Requested"
bitfld.long 0x00 20. " [53] ,New Data Bit[53]" "Not requested,Requested"
textline " "
bitfld.long 0x00 19. " [52] ,New Data Bit[52]" "Not requested,Requested"
bitfld.long 0x00 18. " [51] ,New Data Bit[51]" "Not requested,Requested"
bitfld.long 0x00 17. " [50] ,New Data Bit[50]" "Not requested,Requested"
bitfld.long 0x00 16. " [49] ,New Data Bit[49]" "Not requested,Requested"
textline " "
bitfld.long 0x00 15. " [48] ,New Data Bit[48]" "Not requested,Requested"
bitfld.long 0x00 14. " [47] ,New Data Bit[47]" "Not requested,Requested"
bitfld.long 0x00 13. " [46] ,New Data Bit[46]" "Not requested,Requested"
bitfld.long 0x00 12. " [45] ,New Data Bit[45]" "Not requested,Requested"
textline " "
bitfld.long 0x00 11. " [44] ,New Data Bit[44]" "Not requested,Requested"
bitfld.long 0x00 10. " [43] ,New Data Bit[43]" "Not requested,Requested"
bitfld.long 0x00 9. " [42] ,New Data Bit[42]" "Not requested,Requested"
bitfld.long 0x00 8. " [41] ,New Data Bit[41]" "Not requested,Requested"
textline " "
bitfld.long 0x00 7. " [40] ,New Data Bit[40]" "Not requested,Requested"
bitfld.long 0x00 6. " [39] ,New Data Bit[39]" "Not requested,Requested"
bitfld.long 0x00 5. " [38] ,New Data Bit[38]" "Not requested,Requested"
bitfld.long 0x00 4. " [37] ,New Data Bit[37]" "Not requested,Requested"
textline " "
bitfld.long 0x00 3. " [36] ,New Data Bit[36]" "Not requested,Requested"
bitfld.long 0x00 2. " [35] ,New Data Bit[35]" "Not requested,Requested"
bitfld.long 0x00 1. " [34] ,New Data Bit[34]" "Not requested,Requested"
bitfld.long 0x00 0. " [33] ,New Data Bit[33]" "Not requested,Requested"
rgroup.long 0xA4++0x3
line.long 0x0 "NEWDAT65,New Data 6_5"
bitfld.long 0x00 31. " NEWDAT [96] ,New Data Bit[96]" "Not requested,Requested"
bitfld.long 0x00 30. " [95] ,New Data Bit[95]" "Not requested,Requested"
bitfld.long 0x00 29. " [94] ,New Data Bit[94]" "Not requested,Requested"
bitfld.long 0x00 28. " [93] ,New Data Bit[93]" "Not requested,Requested"
textline " "
bitfld.long 0x00 27. " [92] ,New Data Bit[92]" "Not requested,Requested"
bitfld.long 0x00 26. " [91] ,New Data Bit[91]" "Not requested,Requested"
bitfld.long 0x00 25. " [90] ,New Data Bit[90]" "Not requested,Requested"
bitfld.long 0x00 24. " [89] ,New Data Bit[89]" "Not requested,Requested"
textline " "
bitfld.long 0x00 23. " [88] ,New Data Bit[88]" "Not requested,Requested"
bitfld.long 0x00 22. " [87] ,New Data Bit[87]" "Not requested,Requested"
bitfld.long 0x00 21. " [86] ,New Data Bit[86]" "Not requested,Requested"
bitfld.long 0x00 20. " [85] ,New Data Bit[85]" "Not requested,Requested"
textline " "
bitfld.long 0x00 19. " [84] ,New Data Bit[84]" "Not requested,Requested"
bitfld.long 0x00 18. " [83] ,New Data Bit[83]" "Not requested,Requested"
bitfld.long 0x00 17. " [82] ,New Data Bit[82]" "Not requested,Requested"
bitfld.long 0x00 16. " [81] ,New Data Bit[81]" "Not requested,Requested"
textline " "
bitfld.long 0x00 15. " [80] ,New Data Bit[80]" "Not requested,Requested"
bitfld.long 0x00 14. " [79] ,New Data Bit[79]" "Not requested,Requested"
bitfld.long 0x00 13. " [78] ,New Data Bit[78]" "Not requested,Requested"
bitfld.long 0x00 12. " [77] ,New Data Bit[77]" "Not requested,Requested"
textline " "
bitfld.long 0x00 11. " [76] ,New Data Bit[76]" "Not requested,Requested"
bitfld.long 0x00 10. " [75] ,New Data Bit[75]" "Not requested,Requested"
bitfld.long 0x00 9. " [74] ,New Data Bit[74]" "Not requested,Requested"
bitfld.long 0x00 8. " [73] ,New Data Bit[73]" "Not requested,Requested"
textline " "
bitfld.long 0x00 7. " [72] ,New Data Bit[72]" "Not requested,Requested"
bitfld.long 0x00 6. " [71] ,New Data Bit[71]" "Not requested,Requested"
bitfld.long 0x00 5. " [70] ,New Data Bit[70]" "Not requested,Requested"
bitfld.long 0x00 4. " [69] ,New Data Bit[69]" "Not requested,Requested"
textline " "
bitfld.long 0x00 3. " [68] ,New Data Bit[68]" "Not requested,Requested"
bitfld.long 0x00 2. " [67] ,New Data Bit[67]" "Not requested,Requested"
bitfld.long 0x00 1. " [66] ,New Data Bit[66]" "Not requested,Requested"
bitfld.long 0x00 0. " [65] ,New Data Bit[65]" "Not requested,Requested"
rgroup.long 0xA8++0x3
line.long 0x0 "NEWDAT87,New Data 8_7"
bitfld.long 0x00 31. " NEWDAT [128] ,New Data Bit[128]" "Not requested,Requested"
bitfld.long 0x00 30. " [127] ,New Data Bit[127]" "Not requested,Requested"
bitfld.long 0x00 29. " [126] ,New Data Bit[126]" "Not requested,Requested"
bitfld.long 0x00 28. " [125] ,New Data Bit[125]" "Not requested,Requested"
textline " "
bitfld.long 0x00 27. " [124] ,New Data Bit[124]" "Not requested,Requested"
bitfld.long 0x00 26. " [123] ,New Data Bit[123]" "Not requested,Requested"
bitfld.long 0x00 25. " [122] ,New Data Bit[122]" "Not requested,Requested"
bitfld.long 0x00 24. " [121] ,New Data Bit[121]" "Not requested,Requested"
textline " "
bitfld.long 0x00 23. " [120] ,New Data Bit[120]" "Not requested,Requested"
bitfld.long 0x00 22. " [119] ,New Data Bit[119]" "Not requested,Requested"
bitfld.long 0x00 21. " [118] ,New Data Bit[118]" "Not requested,Requested"
bitfld.long 0x00 20. " [117] ,New Data Bit[117]" "Not requested,Requested"
textline " "
bitfld.long 0x00 19. " [116] ,New Data Bit[116]" "Not requested,Requested"
bitfld.long 0x00 18. " [115] ,New Data Bit[115]" "Not requested,Requested"
bitfld.long 0x00 17. " [114] ,New Data Bit[114]" "Not requested,Requested"
bitfld.long 0x00 16. " [113] ,New Data Bit[113]" "Not requested,Requested"
textline " "
bitfld.long 0x00 15. " [112] ,New Data Bit[112]" "Not requested,Requested"
bitfld.long 0x00 14. " [111] ,New Data Bit[111]" "Not requested,Requested"
bitfld.long 0x00 13. " [110] ,New Data Bit[110]" "Not requested,Requested"
bitfld.long 0x00 12. " [109] ,New Data Bit[109]" "Not requested,Requested"
textline " "
bitfld.long 0x00 11. " [108] ,New Data Bit[108]" "Not requested,Requested"
bitfld.long 0x00 10. " [107] ,New Data Bit[107]" "Not requested,Requested"
bitfld.long 0x00 9. " [106] ,New Data Bit[106]" "Not requested,Requested"
bitfld.long 0x00 8. " [105] ,New Data Bit[105]" "Not requested,Requested"
textline " "
bitfld.long 0x00 7. " [104] ,New Data Bit[104]" "Not requested,Requested"
bitfld.long 0x00 6. " [103] ,New Data Bit[103]" "Not requested,Requested"
bitfld.long 0x00 5. " [102] ,New Data Bit[102]" "Not requested,Requested"
bitfld.long 0x00 4. " [101] ,New Data Bit[101]" "Not requested,Requested"
textline " "
bitfld.long 0x00 3. " [100] ,New Data Bit[100]" "Not requested,Requested"
bitfld.long 0x00 2. " [99] ,New Data Bit[99]" "Not requested,Requested"
bitfld.long 0x00 1. " [98] ,New Data Bit[98]" "Not requested,Requested"
bitfld.long 0x00 0. " [97] ,New Data Bit[97]" "Not requested,Requested"
width 12.
rgroup.long 0xAC++0x3
line.long 0x0 "INTPEN,Interrupt Pending X"
bitfld.long 0x00 14.--15. " INTPENDREG [8] ,Interrupt Pending 8" "0,1,2,3"
bitfld.long 0x00 12.--13. " [7] ,Interrupt Pending 7" "0,1,2,3"
bitfld.long 0x00 10.--11. " [6] ,Interrupt Pending 6" "0,1,2,3"
bitfld.long 0x00 8.--9. " [5] ,Interrupt Pending 5" "0,1,2,3"
textline " "
bitfld.long 0x00 6.--7. " [4] ,Interrupt Pending 4" "0,1,2,3"
bitfld.long 0x00 4.--5. " [3] ,Interrupt Pending 3" "0,1,2,3"
bitfld.long 0x00 2.--3. " [2] ,Interrupt Pending 2" "0,1,2,3"
bitfld.long 0x00 0.--1. " [1] ,Interrupt Pending 1" "0,1,2,3"
width 12.
rgroup.long 0xB0++0x3
line.long 0x0 "INTPEN21,Interrupt Pending 2_1"
bitfld.long 0x00 31. " INTPND [32] ,Interrupt Pending Bit[32]" "No interrupt,Interrupt"
bitfld.long 0x00 30. " [31] ,Interrupt Pending Bit[31]" "No interrupt,Interrupt"
bitfld.long 0x00 29. " [30] ,Interrupt Pending Bit[30]" "No interrupt,Interrupt"
bitfld.long 0x00 28. " [29] ,Interrupt Pending Bit[29]" "No interrupt,Interrupt"
textline " "
bitfld.long 0x00 27. " [28] ,Interrupt Pending Bit[28]" "No interrupt,Interrupt"
bitfld.long 0x00 26. " [27] ,Interrupt Pending Bit[27]" "No interrupt,Interrupt"
bitfld.long 0x00 25. " [26] ,Interrupt Pending Bit[26]" "No interrupt,Interrupt"
bitfld.long 0x00 24. " [25] ,Interrupt Pending Bit[25]" "No interrupt,Interrupt"
textline " "
bitfld.long 0x00 23. " [24] ,Interrupt Pending Bit[24]" "No interrupt,Interrupt"
bitfld.long 0x00 22. " [23] ,Interrupt Pending Bit[23]" "No interrupt,Interrupt"
bitfld.long 0x00 21. " [22] ,Interrupt Pending Bit[22]" "No interrupt,Interrupt"
bitfld.long 0x00 20. " [21] ,Interrupt Pending Bit[21]" "No interrupt,Interrupt"
textline " "
bitfld.long 0x00 19. " [20] ,Interrupt Pending Bit[20]" "No interrupt,Interrupt"
bitfld.long 0x00 18. " [19] ,Interrupt Pending Bit[19]" "No interrupt,Interrupt"
bitfld.long 0x00 17. " [18] ,Interrupt Pending Bit[18]" "No interrupt,Interrupt"
bitfld.long 0x00 16. " [17] ,Interrupt Pending Bit[17]" "No interrupt,Interrupt"
textline " "
bitfld.long 0x00 15. " [16] ,Interrupt Pending Bit[16]" "No interrupt,Interrupt"
bitfld.long 0x00 14. " [15] ,Interrupt Pending Bit[15]" "No interrupt,Interrupt"
bitfld.long 0x00 13. " [14] ,Interrupt Pending Bit[14]" "No interrupt,Interrupt"
bitfld.long 0x00 12. " [13] ,Interrupt Pending Bit[13]" "No interrupt,Interrupt"
textline " "
bitfld.long 0x00 11. " [12] ,Interrupt Pending Bit[12]" "No interrupt,Interrupt"
bitfld.long 0x00 10. " [11] ,Interrupt Pending Bit[11]" "No interrupt,Interrupt"
bitfld.long 0x00 9. " [10] ,Interrupt Pending Bit[10]" "No interrupt,Interrupt"
bitfld.long 0x00 8. " [9] ,Interrupt Pending Bit[9]" "No interrupt,Interrupt"
textline " "
bitfld.long 0x00 7. " [8] ,Interrupt Pending Bit[8]" "No interrupt,Interrupt"
bitfld.long 0x00 6. " [7] ,Interrupt Pending Bit[7]" "No interrupt,Interrupt"
bitfld.long 0x00 5. " [6] ,Interrupt Pending Bit[6]" "No interrupt,Interrupt"
bitfld.long 0x00 4. " [5] ,Interrupt Pending Bit[5]" "No interrupt,Interrupt"
textline " "
bitfld.long 0x00 3. " [4] ,Interrupt Pending Bit[4]" "No interrupt,Interrupt"
bitfld.long 0x00 2. " [3] ,Interrupt Pending Bit[3]" "No interrupt,Interrupt"
bitfld.long 0x00 1. " [2] ,Interrupt Pending Bit[2]" "No interrupt,Interrupt"
bitfld.long 0x00 0. " [1] ,Interrupt Pending Bit[1]" "No interrupt,Interrupt"
rgroup.long 0xB4++0x3
line.long 0x0 "INTPEN43,Interrupt Pending 4_3"
bitfld.long 0x00 31. " INTPND [64] ,Interrupt Pending Bit[64]" "No interrupt,Interrupt"
bitfld.long 0x00 30. " [63] ,Interrupt Pending Bit[63]" "No interrupt,Interrupt"
bitfld.long 0x00 29. " [62] ,Interrupt Pending Bit[62]" "No interrupt,Interrupt"
bitfld.long 0x00 28. " [61] ,Interrupt Pending Bit[61]" "No interrupt,Interrupt"
textline " "
bitfld.long 0x00 27. " [60] ,Interrupt Pending Bit[60]" "No interrupt,Interrupt"
bitfld.long 0x00 26. " [59] ,Interrupt Pending Bit[59]" "No interrupt,Interrupt"
bitfld.long 0x00 25. " [58] ,Interrupt Pending Bit[58]" "No interrupt,Interrupt"
bitfld.long 0x00 24. " [57] ,Interrupt Pending Bit[57]" "No interrupt,Interrupt"
textline " "
bitfld.long 0x00 23. " [56] ,Interrupt Pending Bit[56]" "No interrupt,Interrupt"
bitfld.long 0x00 22. " [55] ,Interrupt Pending Bit[55]" "No interrupt,Interrupt"
bitfld.long 0x00 21. " [54] ,Interrupt Pending Bit[54]" "No interrupt,Interrupt"
bitfld.long 0x00 20. " [53] ,Interrupt Pending Bit[53]" "No interrupt,Interrupt"
textline " "
bitfld.long 0x00 19. " [52] ,Interrupt Pending Bit[52]" "No interrupt,Interrupt"
bitfld.long 0x00 18. " [51] ,Interrupt Pending Bit[51]" "No interrupt,Interrupt"
bitfld.long 0x00 17. " [50] ,Interrupt Pending Bit[50]" "No interrupt,Interrupt"
bitfld.long 0x00 16. " [49] ,Interrupt Pending Bit[49]" "No interrupt,Interrupt"
textline " "
bitfld.long 0x00 15. " [48] ,Interrupt Pending Bit[48]" "No interrupt,Interrupt"
bitfld.long 0x00 14. " [47] ,Interrupt Pending Bit[47]" "No interrupt,Interrupt"
bitfld.long 0x00 13. " [46] ,Interrupt Pending Bit[46]" "No interrupt,Interrupt"
bitfld.long 0x00 12. " [45] ,Interrupt Pending Bit[45]" "No interrupt,Interrupt"
textline " "
bitfld.long 0x00 11. " [44] ,Interrupt Pending Bit[44]" "No interrupt,Interrupt"
bitfld.long 0x00 10. " [43] ,Interrupt Pending Bit[43]" "No interrupt,Interrupt"
bitfld.long 0x00 9. " [42] ,Interrupt Pending Bit[42]" "No interrupt,Interrupt"
bitfld.long 0x00 8. " [41] ,Interrupt Pending Bit[41]" "No interrupt,Interrupt"
textline " "
bitfld.long 0x00 7. " [40] ,Interrupt Pending Bit[40]" "No interrupt,Interrupt"
bitfld.long 0x00 6. " [39] ,Interrupt Pending Bit[39]" "No interrupt,Interrupt"
bitfld.long 0x00 5. " [38] ,Interrupt Pending Bit[38]" "No interrupt,Interrupt"
bitfld.long 0x00 4. " [37] ,Interrupt Pending Bit[37]" "No interrupt,Interrupt"
textline " "
bitfld.long 0x00 3. " [36] ,Interrupt Pending Bit[36]" "No interrupt,Interrupt"
bitfld.long 0x00 2. " [35] ,Interrupt Pending Bit[35]" "No interrupt,Interrupt"
bitfld.long 0x00 1. " [34] ,Interrupt Pending Bit[34]" "No interrupt,Interrupt"
bitfld.long 0x00 0. " [33] ,Interrupt Pending Bit[33]" "No interrupt,Interrupt"
rgroup.long 0xB8++0x3
line.long 0x0 "INTPEN65,Interrupt Pending 6_5"
bitfld.long 0x00 31. " INTPND [96] ,Interrupt Pending Bit[96]" "No interrupt,Interrupt"
bitfld.long 0x00 30. " [95] ,Interrupt Pending Bit[95]" "No interrupt,Interrupt"
bitfld.long 0x00 29. " [94] ,Interrupt Pending Bit[94]" "No interrupt,Interrupt"
bitfld.long 0x00 28. " [93] ,Interrupt Pending Bit[93]" "No interrupt,Interrupt"
textline " "
bitfld.long 0x00 27. " [92] ,Interrupt Pending Bit[92]" "No interrupt,Interrupt"
bitfld.long 0x00 26. " [91] ,Interrupt Pending Bit[91]" "No interrupt,Interrupt"
bitfld.long 0x00 25. " [90] ,Interrupt Pending Bit[90]" "No interrupt,Interrupt"
bitfld.long 0x00 24. " [89] ,Interrupt Pending Bit[89]" "No interrupt,Interrupt"
textline " "
bitfld.long 0x00 23. " [88] ,Interrupt Pending Bit[88]" "No interrupt,Interrupt"
bitfld.long 0x00 22. " [87] ,Interrupt Pending Bit[87]" "No interrupt,Interrupt"
bitfld.long 0x00 21. " [86] ,Interrupt Pending Bit[86]" "No interrupt,Interrupt"
bitfld.long 0x00 20. " [85] ,Interrupt Pending Bit[85]" "No interrupt,Interrupt"
textline " "
bitfld.long 0x00 19. " [84] ,Interrupt Pending Bit[84]" "No interrupt,Interrupt"
bitfld.long 0x00 18. " [83] ,Interrupt Pending Bit[83]" "No interrupt,Interrupt"
bitfld.long 0x00 17. " [82] ,Interrupt Pending Bit[82]" "No interrupt,Interrupt"
bitfld.long 0x00 16. " [81] ,Interrupt Pending Bit[81]" "No interrupt,Interrupt"
textline " "
bitfld.long 0x00 15. " [80] ,Interrupt Pending Bit[80]" "No interrupt,Interrupt"
bitfld.long 0x00 14. " [79] ,Interrupt Pending Bit[79]" "No interrupt,Interrupt"
bitfld.long 0x00 13. " [78] ,Interrupt Pending Bit[78]" "No interrupt,Interrupt"
bitfld.long 0x00 12. " [77] ,Interrupt Pending Bit[77]" "No interrupt,Interrupt"
textline " "
bitfld.long 0x00 11. " [76] ,Interrupt Pending Bit[76]" "No interrupt,Interrupt"
bitfld.long 0x00 10. " [75] ,Interrupt Pending Bit[75]" "No interrupt,Interrupt"
bitfld.long 0x00 9. " [74] ,Interrupt Pending Bit[74]" "No interrupt,Interrupt"
bitfld.long 0x00 8. " [73] ,Interrupt Pending Bit[73]" "No interrupt,Interrupt"
textline " "
bitfld.long 0x00 7. " [72] ,Interrupt Pending Bit[72]" "No interrupt,Interrupt"
bitfld.long 0x00 6. " [71] ,Interrupt Pending Bit[71]" "No interrupt,Interrupt"
bitfld.long 0x00 5. " [70] ,Interrupt Pending Bit[70]" "No interrupt,Interrupt"
bitfld.long 0x00 4. " [69] ,Interrupt Pending Bit[69]" "No interrupt,Interrupt"
textline " "
bitfld.long 0x00 3. " [68] ,Interrupt Pending Bit[68]" "No interrupt,Interrupt"
bitfld.long 0x00 2. " [67] ,Interrupt Pending Bit[67]" "No interrupt,Interrupt"
bitfld.long 0x00 1. " [66] ,Interrupt Pending Bit[66]" "No interrupt,Interrupt"
bitfld.long 0x00 0. " [65] ,Interrupt Pending Bit[65]" "No interrupt,Interrupt"
rgroup.long 0xBC++0x3
line.long 0x0 "INTPEN87,Interrupt Pending 8_7"
bitfld.long 0x00 31. " INTPND [128] ,Interrupt Pending Bit[128]" "No interrupt,Interrupt"
bitfld.long 0x00 30. " [127] ,Interrupt Pending Bit[127]" "No interrupt,Interrupt"
bitfld.long 0x00 29. " [126] ,Interrupt Pending Bit[126]" "No interrupt,Interrupt"
bitfld.long 0x00 28. " [125] ,Interrupt Pending Bit[125]" "No interrupt,Interrupt"
textline " "
bitfld.long 0x00 27. " [124] ,Interrupt Pending Bit[124]" "No interrupt,Interrupt"
bitfld.long 0x00 26. " [123] ,Interrupt Pending Bit[123]" "No interrupt,Interrupt"
bitfld.long 0x00 25. " [122] ,Interrupt Pending Bit[122]" "No interrupt,Interrupt"
bitfld.long 0x00 24. " [121] ,Interrupt Pending Bit[121]" "No interrupt,Interrupt"
textline " "
bitfld.long 0x00 23. " [120] ,Interrupt Pending Bit[120]" "No interrupt,Interrupt"
bitfld.long 0x00 22. " [119] ,Interrupt Pending Bit[119]" "No interrupt,Interrupt"
bitfld.long 0x00 21. " [118] ,Interrupt Pending Bit[118]" "No interrupt,Interrupt"
bitfld.long 0x00 20. " [117] ,Interrupt Pending Bit[117]" "No interrupt,Interrupt"
textline " "
bitfld.long 0x00 19. " [116] ,Interrupt Pending Bit[116]" "No interrupt,Interrupt"
bitfld.long 0x00 18. " [115] ,Interrupt Pending Bit[115]" "No interrupt,Interrupt"
bitfld.long 0x00 17. " [114] ,Interrupt Pending Bit[114]" "No interrupt,Interrupt"
bitfld.long 0x00 16. " [113] ,Interrupt Pending Bit[113]" "No interrupt,Interrupt"
textline " "
bitfld.long 0x00 15. " [112] ,Interrupt Pending Bit[112]" "No interrupt,Interrupt"
bitfld.long 0x00 14. " [111] ,Interrupt Pending Bit[111]" "No interrupt,Interrupt"
bitfld.long 0x00 13. " [110] ,Interrupt Pending Bit[110]" "No interrupt,Interrupt"
bitfld.long 0x00 12. " [109] ,Interrupt Pending Bit[109]" "No interrupt,Interrupt"
textline " "
bitfld.long 0x00 11. " [108] ,Interrupt Pending Bit[108]" "No interrupt,Interrupt"
bitfld.long 0x00 10. " [107] ,Interrupt Pending Bit[107]" "No interrupt,Interrupt"
bitfld.long 0x00 9. " [106] ,Interrupt Pending Bit[106]" "No interrupt,Interrupt"
bitfld.long 0x00 8. " [105] ,Interrupt Pending Bit[105]" "No interrupt,Interrupt"
textline " "
bitfld.long 0x00 7. " [104] ,Interrupt Pending Bit[104]" "No interrupt,Interrupt"
bitfld.long 0x00 6. " [103] ,Interrupt Pending Bit[103]" "No interrupt,Interrupt"
bitfld.long 0x00 5. " [102] ,Interrupt Pending Bit[102]" "No interrupt,Interrupt"
bitfld.long 0x00 4. " [101] ,Interrupt Pending Bit[101]" "No interrupt,Interrupt"
textline " "
bitfld.long 0x00 3. " [100] ,Interrupt Pending Bit[100]" "No interrupt,Interrupt"
bitfld.long 0x00 2. " [99] ,Interrupt Pending Bit[99]" "No interrupt,Interrupt"
bitfld.long 0x00 1. " [98] ,Interrupt Pending Bit[98]" "No interrupt,Interrupt"
bitfld.long 0x00 0. " [97] ,Interrupt Pending Bit[97]" "No interrupt,Interrupt"
width 12.
rgroup.long 0xC0++0x3
line.long 0x0 "MVAL,Message Valid X"
bitfld.long 0x00 14.--15. " MSGVALREG [8] ,Message Valid Register 8" "0,1,2,3"
bitfld.long 0x00 12.--13. " [7] ,Message Valid Register 7" "0,1,2,3"
bitfld.long 0x00 10.--11. " [6] ,Message Valid Register 6" "0,1,2,3"
bitfld.long 0x00 8.--9. " [5] ,Message Valid Register 5" "0,1,2,3"
textline " "
bitfld.long 0x00 6.--7. " [4] ,Message Valid Register 4" "0,1,2,3"
bitfld.long 0x00 4.--5. " [3] ,Message Valid Register 3" "0,1,2,3"
bitfld.long 0x00 2.--3. " [2] ,Message Valid Register 2" "0,1,2,3"
bitfld.long 0x00 0.--1. " [1] ,Message Valid Register 1" "0,1,2,3"
width 12.
rgroup.long 0xC4++0x3
line.long 0x0 "MVAL21,Message Valid 2_1"
bitfld.long 0x00 31. " MSGVAL [32] ,Message Valid Bit[32]" "Ignored,Configured"
bitfld.long 0x00 30. " [31] ,Message Valid Bit[31]" "Ignored,Configured"
bitfld.long 0x00 29. " [30] ,Message Valid Bit[30]" "Ignored,Configured"
bitfld.long 0x00 28. " [29] ,Message Valid Bit[29]" "Ignored,Configured"
textline " "
bitfld.long 0x00 27. " [28] ,Message Valid Bit[28]" "Ignored,Configured"
bitfld.long 0x00 26. " [27] ,Message Valid Bit[27]" "Ignored,Configured"
bitfld.long 0x00 25. " [26] ,Message Valid Bit[26]" "Ignored,Configured"
bitfld.long 0x00 24. " [25] ,Message Valid Bit[25]" "Ignored,Configured"
textline " "
bitfld.long 0x00 23. " [24] ,Message Valid Bit[24]" "Ignored,Configured"
bitfld.long 0x00 22. " [23] ,Message Valid Bit[23]" "Ignored,Configured"
bitfld.long 0x00 21. " [22] ,Message Valid Bit[22]" "Ignored,Configured"
bitfld.long 0x00 20. " [21] ,Message Valid Bit[21]" "Ignored,Configured"
textline " "
bitfld.long 0x00 19. " [20] ,Message Valid Bit[20]" "Ignored,Configured"
bitfld.long 0x00 18. " [19] ,Message Valid Bit[19]" "Ignored,Configured"
bitfld.long 0x00 17. " [18] ,Message Valid Bit[18]" "Ignored,Configured"
bitfld.long 0x00 16. " [17] ,Message Valid Bit[17]" "Ignored,Configured"
textline " "
bitfld.long 0x00 15. " [16] ,Message Valid Bit[16]" "Ignored,Configured"
bitfld.long 0x00 14. " [15] ,Message Valid Bit[15]" "Ignored,Configured"
bitfld.long 0x00 13. " [14] ,Message Valid Bit[14]" "Ignored,Configured"
bitfld.long 0x00 12. " [13] ,Message Valid Bit[13]" "Ignored,Configured"
textline " "
bitfld.long 0x00 11. " [12] ,Message Valid Bit[12]" "Ignored,Configured"
bitfld.long 0x00 10. " [11] ,Message Valid Bit[11]" "Ignored,Configured"
bitfld.long 0x00 9. " [10] ,Message Valid Bit[10]" "Ignored,Configured"
bitfld.long 0x00 8. " [9] ,Message Valid Bit[9]" "Ignored,Configured"
textline " "
bitfld.long 0x00 7. " [8] ,Message Valid Bit[8]" "Ignored,Configured"
bitfld.long 0x00 6. " [7] ,Message Valid Bit[7]" "Ignored,Configured"
bitfld.long 0x00 5. " [6] ,Message Valid Bit[6]" "Ignored,Configured"
bitfld.long 0x00 4. " [5] ,Message Valid Bit[5]" "Ignored,Configured"
textline " "
bitfld.long 0x00 3. " [4] ,Message Valid Bit[4]" "Ignored,Configured"
bitfld.long 0x00 2. " [3] ,Message Valid Bit[3]" "Ignored,Configured"
bitfld.long 0x00 1. " [2] ,Message Valid Bit[2]" "Ignored,Configured"
bitfld.long 0x00 0. " [1] ,Message Valid Bit[1]" "Ignored,Configured"
rgroup.long 0xC8++0x3
line.long 0x0 "MVAL43,Message Valid 4_3"
bitfld.long 0x00 31. " MSGVAL [64] ,Message Valid Bit[64]" "Ignored,Configured"
bitfld.long 0x00 30. " [63] ,Message Valid Bit[63]" "Ignored,Configured"
bitfld.long 0x00 29. " [62] ,Message Valid Bit[62]" "Ignored,Configured"
bitfld.long 0x00 28. " [61] ,Message Valid Bit[61]" "Ignored,Configured"
textline " "
bitfld.long 0x00 27. " [60] ,Message Valid Bit[60]" "Ignored,Configured"
bitfld.long 0x00 26. " [59] ,Message Valid Bit[59]" "Ignored,Configured"
bitfld.long 0x00 25. " [58] ,Message Valid Bit[58]" "Ignored,Configured"
bitfld.long 0x00 24. " [57] ,Message Valid Bit[57]" "Ignored,Configured"
textline " "
bitfld.long 0x00 23. " [56] ,Message Valid Bit[56]" "Ignored,Configured"
bitfld.long 0x00 22. " [55] ,Message Valid Bit[55]" "Ignored,Configured"
bitfld.long 0x00 21. " [54] ,Message Valid Bit[54]" "Ignored,Configured"
bitfld.long 0x00 20. " [53] ,Message Valid Bit[53]" "Ignored,Configured"
textline " "
bitfld.long 0x00 19. " [52] ,Message Valid Bit[52]" "Ignored,Configured"
bitfld.long 0x00 18. " [51] ,Message Valid Bit[51]" "Ignored,Configured"
bitfld.long 0x00 17. " [50] ,Message Valid Bit[50]" "Ignored,Configured"
bitfld.long 0x00 16. " [49] ,Message Valid Bit[49]" "Ignored,Configured"
textline " "
bitfld.long 0x00 15. " [48] ,Message Valid Bit[48]" "Ignored,Configured"
bitfld.long 0x00 14. " [47] ,Message Valid Bit[47]" "Ignored,Configured"
bitfld.long 0x00 13. " [46] ,Message Valid Bit[46]" "Ignored,Configured"
bitfld.long 0x00 12. " [45] ,Message Valid Bit[45]" "Ignored,Configured"
textline " "
bitfld.long 0x00 11. " [44] ,Message Valid Bit[44]" "Ignored,Configured"
bitfld.long 0x00 10. " [43] ,Message Valid Bit[43]" "Ignored,Configured"
bitfld.long 0x00 9. " [42] ,Message Valid Bit[42]" "Ignored,Configured"
bitfld.long 0x00 8. " [41] ,Message Valid Bit[41]" "Ignored,Configured"
textline " "
bitfld.long 0x00 7. " [40] ,Message Valid Bit[40]" "Ignored,Configured"
bitfld.long 0x00 6. " [39] ,Message Valid Bit[39]" "Ignored,Configured"
bitfld.long 0x00 5. " [38] ,Message Valid Bit[38]" "Ignored,Configured"
bitfld.long 0x00 4. " [37] ,Message Valid Bit[37]" "Ignored,Configured"
textline " "
bitfld.long 0x00 3. " [36] ,Message Valid Bit[36]" "Ignored,Configured"
bitfld.long 0x00 2. " [35] ,Message Valid Bit[35]" "Ignored,Configured"
bitfld.long 0x00 1. " [34] ,Message Valid Bit[34]" "Ignored,Configured"
bitfld.long 0x00 0. " [33] ,Message Valid Bit[33]" "Ignored,Configured"
rgroup.long 0xCC++0x3
line.long 0x0 "MVAL65,Message Valid 6_5"
bitfld.long 0x00 31. " MSGVAL [96] ,Message Valid Bit[96]" "Ignored,Configured"
bitfld.long 0x00 30. " [95] ,Message Valid Bit[95]" "Ignored,Configured"
bitfld.long 0x00 29. " [94] ,Message Valid Bit[94]" "Ignored,Configured"
bitfld.long 0x00 28. " [93] ,Message Valid Bit[93]" "Ignored,Configured"
textline " "
bitfld.long 0x00 27. " [92] ,Message Valid Bit[92]" "Ignored,Configured"
bitfld.long 0x00 26. " [91] ,Message Valid Bit[91]" "Ignored,Configured"
bitfld.long 0x00 25. " [90] ,Message Valid Bit[90]" "Ignored,Configured"
bitfld.long 0x00 24. " [89] ,Message Valid Bit[89]" "Ignored,Configured"
textline " "
bitfld.long 0x00 23. " [88] ,Message Valid Bit[88]" "Ignored,Configured"
bitfld.long 0x00 22. " [87] ,Message Valid Bit[87]" "Ignored,Configured"
bitfld.long 0x00 21. " [86] ,Message Valid Bit[86]" "Ignored,Configured"
bitfld.long 0x00 20. " [85] ,Message Valid Bit[85]" "Ignored,Configured"
textline " "
bitfld.long 0x00 19. " [84] ,Message Valid Bit[84]" "Ignored,Configured"
bitfld.long 0x00 18. " [83] ,Message Valid Bit[83]" "Ignored,Configured"
bitfld.long 0x00 17. " [82] ,Message Valid Bit[82]" "Ignored,Configured"
bitfld.long 0x00 16. " [81] ,Message Valid Bit[81]" "Ignored,Configured"
textline " "
bitfld.long 0x00 15. " [80] ,Message Valid Bit[80]" "Ignored,Configured"
bitfld.long 0x00 14. " [79] ,Message Valid Bit[79]" "Ignored,Configured"
bitfld.long 0x00 13. " [78] ,Message Valid Bit[78]" "Ignored,Configured"
bitfld.long 0x00 12. " [77] ,Message Valid Bit[77]" "Ignored,Configured"
textline " "
bitfld.long 0x00 11. " [76] ,Message Valid Bit[76]" "Ignored,Configured"
bitfld.long 0x00 10. " [75] ,Message Valid Bit[75]" "Ignored,Configured"
bitfld.long 0x00 9. " [74] ,Message Valid Bit[74]" "Ignored,Configured"
bitfld.long 0x00 8. " [73] ,Message Valid Bit[73]" "Ignored,Configured"
textline " "
bitfld.long 0x00 7. " [72] ,Message Valid Bit[72]" "Ignored,Configured"
bitfld.long 0x00 6. " [71] ,Message Valid Bit[71]" "Ignored,Configured"
bitfld.long 0x00 5. " [70] ,Message Valid Bit[70]" "Ignored,Configured"
bitfld.long 0x00 4. " [69] ,Message Valid Bit[69]" "Ignored,Configured"
textline " "
bitfld.long 0x00 3. " [68] ,Message Valid Bit[68]" "Ignored,Configured"
bitfld.long 0x00 2. " [67] ,Message Valid Bit[67]" "Ignored,Configured"
bitfld.long 0x00 1. " [66] ,Message Valid Bit[66]" "Ignored,Configured"
bitfld.long 0x00 0. " [65] ,Message Valid Bit[65]" "Ignored,Configured"
rgroup.long 0xD0++0x3
line.long 0x0 "MVAL87,Message Valid 8_7"
bitfld.long 0x00 31. " MSGVAL [128] ,Message Valid Bit[128]" "Ignored,Configured"
bitfld.long 0x00 30. " [127] ,Message Valid Bit[127]" "Ignored,Configured"
bitfld.long 0x00 29. " [126] ,Message Valid Bit[126]" "Ignored,Configured"
bitfld.long 0x00 28. " [125] ,Message Valid Bit[125]" "Ignored,Configured"
textline " "
bitfld.long 0x00 27. " [124] ,Message Valid Bit[124]" "Ignored,Configured"
bitfld.long 0x00 26. " [123] ,Message Valid Bit[123]" "Ignored,Configured"
bitfld.long 0x00 25. " [122] ,Message Valid Bit[122]" "Ignored,Configured"
bitfld.long 0x00 24. " [121] ,Message Valid Bit[121]" "Ignored,Configured"
textline " "
bitfld.long 0x00 23. " [120] ,Message Valid Bit[120]" "Ignored,Configured"
bitfld.long 0x00 22. " [119] ,Message Valid Bit[119]" "Ignored,Configured"
bitfld.long 0x00 21. " [118] ,Message Valid Bit[118]" "Ignored,Configured"
bitfld.long 0x00 20. " [117] ,Message Valid Bit[117]" "Ignored,Configured"
textline " "
bitfld.long 0x00 19. " [116] ,Message Valid Bit[116]" "Ignored,Configured"
bitfld.long 0x00 18. " [115] ,Message Valid Bit[115]" "Ignored,Configured"
bitfld.long 0x00 17. " [114] ,Message Valid Bit[114]" "Ignored,Configured"
bitfld.long 0x00 16. " [113] ,Message Valid Bit[113]" "Ignored,Configured"
textline " "
bitfld.long 0x00 15. " [112] ,Message Valid Bit[112]" "Ignored,Configured"
bitfld.long 0x00 14. " [111] ,Message Valid Bit[111]" "Ignored,Configured"
bitfld.long 0x00 13. " [110] ,Message Valid Bit[110]" "Ignored,Configured"
bitfld.long 0x00 12. " [109] ,Message Valid Bit[109]" "Ignored,Configured"
textline " "
bitfld.long 0x00 11. " [108] ,Message Valid Bit[108]" "Ignored,Configured"
bitfld.long 0x00 10. " [107] ,Message Valid Bit[107]" "Ignored,Configured"
bitfld.long 0x00 9. " [106] ,Message Valid Bit[106]" "Ignored,Configured"
bitfld.long 0x00 8. " [105] ,Message Valid Bit[105]" "Ignored,Configured"
textline " "
bitfld.long 0x00 7. " [104] ,Message Valid Bit[104]" "Ignored,Configured"
bitfld.long 0x00 6. " [103] ,Message Valid Bit[103]" "Ignored,Configured"
bitfld.long 0x00 5. " [102] ,Message Valid Bit[102]" "Ignored,Configured"
bitfld.long 0x00 4. " [101] ,Message Valid Bit[101]" "Ignored,Configured"
textline " "
bitfld.long 0x00 3. " [100] ,Message Valid Bit[100]" "Ignored,Configured"
bitfld.long 0x00 2. " [99] ,Message Valid Bit[99]" "Ignored,Configured"
bitfld.long 0x00 1. " [98] ,Message Valid Bit[98]" "Ignored,Configured"
bitfld.long 0x00 0. " [97] ,Message Valid Bit[97]" "Ignored,Configured"
width 12.
group.long 0xD8++0x3
line.long 0x0 "INTPMX21,IntPndMux 2_1"
bitfld.long 0x00 31. " INTPNDMUX [32] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[32]" "DCAN0INT,DCAN1INT"
bitfld.long 0x00 30. " [31] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[31]" "DCAN0INT,DCAN1INT"
bitfld.long 0x00 29. " [30] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[30]" "DCAN0INT,DCAN1INT"
bitfld.long 0x00 28. " [29] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[29]" "DCAN0INT,DCAN1INT"
textline " "
bitfld.long 0x00 27. " [28] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[28]" "DCAN0INT,DCAN1INT"
bitfld.long 0x00 26. " [27] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[27]" "DCAN0INT,DCAN1INT"
bitfld.long 0x00 25. " [26] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[26]" "DCAN0INT,DCAN1INT"
bitfld.long 0x00 24. " [25] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[25]" "DCAN0INT,DCAN1INT"
textline " "
bitfld.long 0x00 23. " [24] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[24]" "DCAN0INT,DCAN1INT"
bitfld.long 0x00 22. " [23] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[23]" "DCAN0INT,DCAN1INT"
bitfld.long 0x00 21. " [22] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[22]" "DCAN0INT,DCAN1INT"
bitfld.long 0x00 20. " [21] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[21]" "DCAN0INT,DCAN1INT"
textline " "
bitfld.long 0x00 19. " [20] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[20]" "DCAN0INT,DCAN1INT"
bitfld.long 0x00 18. " [19] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[19]" "DCAN0INT,DCAN1INT"
bitfld.long 0x00 17. " [18] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[18]" "DCAN0INT,DCAN1INT"
bitfld.long 0x00 16. " [17] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[17]" "DCAN0INT,DCAN1INT"
textline " "
bitfld.long 0x00 15. " [16] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[16]" "DCAN0INT,DCAN1INT"
bitfld.long 0x00 14. " [15] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[15]" "DCAN0INT,DCAN1INT"
bitfld.long 0x00 13. " [14] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[14]" "DCAN0INT,DCAN1INT"
bitfld.long 0x00 12. " [13] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[13]" "DCAN0INT,DCAN1INT"
textline " "
bitfld.long 0x00 11. " [12] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[12]" "DCAN0INT,DCAN1INT"
bitfld.long 0x00 10. " [11] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[11]" "DCAN0INT,DCAN1INT"
bitfld.long 0x00 9. " [10] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[10]" "DCAN0INT,DCAN1INT"
bitfld.long 0x00 8. " [9] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[9]" "DCAN0INT,DCAN1INT"
textline " "
bitfld.long 0x00 7. " [8] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[8]" "DCAN0INT,DCAN1INT"
bitfld.long 0x00 6. " [7] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[7]" "DCAN0INT,DCAN1INT"
bitfld.long 0x00 5. " [6] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[6]" "DCAN0INT,DCAN1INT"
bitfld.long 0x00 4. " [5] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[5]" "DCAN0INT,DCAN1INT"
textline " "
bitfld.long 0x00 3. " [4] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[4]" "DCAN0INT,DCAN1INT"
bitfld.long 0x00 2. " [3] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[3]" "DCAN0INT,DCAN1INT"
bitfld.long 0x00 1. " [2] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[2]" "DCAN0INT,DCAN1INT"
bitfld.long 0x00 0. " [1] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[1]" "DCAN0INT,DCAN1INT"
group.long 0xDC++0x3
line.long 0x0 "INTPMX43,IntPndMux 4_3"
bitfld.long 0x00 31. " INTPNDMUX [64] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[64]" "DCAN0INT,DCAN1INT"
bitfld.long 0x00 30. " [63] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[63]" "DCAN0INT,DCAN1INT"
bitfld.long 0x00 29. " [62] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[62]" "DCAN0INT,DCAN1INT"
bitfld.long 0x00 28. " [61] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[61]" "DCAN0INT,DCAN1INT"
textline " "
bitfld.long 0x00 27. " [60] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[60]" "DCAN0INT,DCAN1INT"
bitfld.long 0x00 26. " [59] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[59]" "DCAN0INT,DCAN1INT"
bitfld.long 0x00 25. " [58] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[58]" "DCAN0INT,DCAN1INT"
bitfld.long 0x00 24. " [57] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[57]" "DCAN0INT,DCAN1INT"
textline " "
bitfld.long 0x00 23. " [56] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[56]" "DCAN0INT,DCAN1INT"
bitfld.long 0x00 22. " [55] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[55]" "DCAN0INT,DCAN1INT"
bitfld.long 0x00 21. " [54] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[54]" "DCAN0INT,DCAN1INT"
bitfld.long 0x00 20. " [53] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[53]" "DCAN0INT,DCAN1INT"
textline " "
bitfld.long 0x00 19. " [52] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[52]" "DCAN0INT,DCAN1INT"
bitfld.long 0x00 18. " [51] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[51]" "DCAN0INT,DCAN1INT"
bitfld.long 0x00 17. " [50] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[50]" "DCAN0INT,DCAN1INT"
bitfld.long 0x00 16. " [49] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[49]" "DCAN0INT,DCAN1INT"
textline " "
bitfld.long 0x00 15. " [48] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[48]" "DCAN0INT,DCAN1INT"
bitfld.long 0x00 14. " [47] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[47]" "DCAN0INT,DCAN1INT"
bitfld.long 0x00 13. " [46] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[46]" "DCAN0INT,DCAN1INT"
bitfld.long 0x00 12. " [45] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[45]" "DCAN0INT,DCAN1INT"
textline " "
bitfld.long 0x00 11. " [44] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[44]" "DCAN0INT,DCAN1INT"
bitfld.long 0x00 10. " [43] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[43]" "DCAN0INT,DCAN1INT"
bitfld.long 0x00 9. " [42] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[42]" "DCAN0INT,DCAN1INT"
bitfld.long 0x00 8. " [41] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[41]" "DCAN0INT,DCAN1INT"
textline " "
bitfld.long 0x00 7. " [40] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[40]" "DCAN0INT,DCAN1INT"
bitfld.long 0x00 6. " [39] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[39]" "DCAN0INT,DCAN1INT"
bitfld.long 0x00 5. " [38] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[38]" "DCAN0INT,DCAN1INT"
bitfld.long 0x00 4. " [37] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[37]" "DCAN0INT,DCAN1INT"
textline " "
bitfld.long 0x00 3. " [36] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[36]" "DCAN0INT,DCAN1INT"
bitfld.long 0x00 2. " [35] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[35]" "DCAN0INT,DCAN1INT"
bitfld.long 0x00 1. " [34] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[34]" "DCAN0INT,DCAN1INT"
bitfld.long 0x00 0. " [33] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[33]" "DCAN0INT,DCAN1INT"
group.long 0xE0++0x3
line.long 0x0 "INTPMX65,IntPndMux 6_5"
bitfld.long 0x00 31. " INTPNDMUX [96] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[96]" "DCAN0INT,DCAN1INT"
bitfld.long 0x00 30. " [95] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[95]" "DCAN0INT,DCAN1INT"
bitfld.long 0x00 29. " [94] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[94]" "DCAN0INT,DCAN1INT"
bitfld.long 0x00 28. " [93] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[93]" "DCAN0INT,DCAN1INT"
textline " "
bitfld.long 0x00 27. " [92] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[92]" "DCAN0INT,DCAN1INT"
bitfld.long 0x00 26. " [91] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[91]" "DCAN0INT,DCAN1INT"
bitfld.long 0x00 25. " [90] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[90]" "DCAN0INT,DCAN1INT"
bitfld.long 0x00 24. " [89] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[89]" "DCAN0INT,DCAN1INT"
textline " "
bitfld.long 0x00 23. " [88] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[88]" "DCAN0INT,DCAN1INT"
bitfld.long 0x00 22. " [87] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[87]" "DCAN0INT,DCAN1INT"
bitfld.long 0x00 21. " [86] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[86]" "DCAN0INT,DCAN1INT"
bitfld.long 0x00 20. " [85] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[85]" "DCAN0INT,DCAN1INT"
textline " "
bitfld.long 0x00 19. " [84] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[84]" "DCAN0INT,DCAN1INT"
bitfld.long 0x00 18. " [83] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[83]" "DCAN0INT,DCAN1INT"
bitfld.long 0x00 17. " [82] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[82]" "DCAN0INT,DCAN1INT"
bitfld.long 0x00 16. " [81] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[81]" "DCAN0INT,DCAN1INT"
textline " "
bitfld.long 0x00 15. " [80] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[80]" "DCAN0INT,DCAN1INT"
bitfld.long 0x00 14. " [79] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[79]" "DCAN0INT,DCAN1INT"
bitfld.long 0x00 13. " [78] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[78]" "DCAN0INT,DCAN1INT"
bitfld.long 0x00 12. " [77] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[77]" "DCAN0INT,DCAN1INT"
textline " "
bitfld.long 0x00 11. " [76] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[76]" "DCAN0INT,DCAN1INT"
bitfld.long 0x00 10. " [75] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[75]" "DCAN0INT,DCAN1INT"
bitfld.long 0x00 9. " [74] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[74]" "DCAN0INT,DCAN1INT"
bitfld.long 0x00 8. " [73] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[73]" "DCAN0INT,DCAN1INT"
textline " "
bitfld.long 0x00 7. " [72] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[72]" "DCAN0INT,DCAN1INT"
bitfld.long 0x00 6. " [71] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[71]" "DCAN0INT,DCAN1INT"
bitfld.long 0x00 5. " [70] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[70]" "DCAN0INT,DCAN1INT"
bitfld.long 0x00 4. " [69] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[69]" "DCAN0INT,DCAN1INT"
textline " "
bitfld.long 0x00 3. " [68] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[68]" "DCAN0INT,DCAN1INT"
bitfld.long 0x00 2. " [67] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[67]" "DCAN0INT,DCAN1INT"
bitfld.long 0x00 1. " [66] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[66]" "DCAN0INT,DCAN1INT"
bitfld.long 0x00 0. " [65] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[65]" "DCAN0INT,DCAN1INT"
group.long 0xE4++0x3
line.long 0x0 "INTPMX87,IntPndMux 8_7"
bitfld.long 0x00 31. " INTPNDMUX [128] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[128]" "DCAN0INT,DCAN1INT"
bitfld.long 0x00 30. " [127] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[127]" "DCAN0INT,DCAN1INT"
bitfld.long 0x00 29. " [126] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[126]" "DCAN0INT,DCAN1INT"
bitfld.long 0x00 28. " [125] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[125]" "DCAN0INT,DCAN1INT"
textline " "
bitfld.long 0x00 27. " [124] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[124]" "DCAN0INT,DCAN1INT"
bitfld.long 0x00 26. " [123] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[123]" "DCAN0INT,DCAN1INT"
bitfld.long 0x00 25. " [122] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[122]" "DCAN0INT,DCAN1INT"
bitfld.long 0x00 24. " [121] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[121]" "DCAN0INT,DCAN1INT"
textline " "
bitfld.long 0x00 23. " [120] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[120]" "DCAN0INT,DCAN1INT"
bitfld.long 0x00 22. " [119] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[119]" "DCAN0INT,DCAN1INT"
bitfld.long 0x00 21. " [118] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[118]" "DCAN0INT,DCAN1INT"
bitfld.long 0x00 20. " [117] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[117]" "DCAN0INT,DCAN1INT"
textline " "
bitfld.long 0x00 19. " [116] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[116]" "DCAN0INT,DCAN1INT"
bitfld.long 0x00 18. " [115] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[115]" "DCAN0INT,DCAN1INT"
bitfld.long 0x00 17. " [114] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[114]" "DCAN0INT,DCAN1INT"
bitfld.long 0x00 16. " [113] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[113]" "DCAN0INT,DCAN1INT"
textline " "
bitfld.long 0x00 15. " [112] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[112]" "DCAN0INT,DCAN1INT"
bitfld.long 0x00 14. " [111] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[111]" "DCAN0INT,DCAN1INT"
bitfld.long 0x00 13. " [110] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[110]" "DCAN0INT,DCAN1INT"
bitfld.long 0x00 12. " [109] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[109]" "DCAN0INT,DCAN1INT"
textline " "
bitfld.long 0x00 11. " [108] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[108]" "DCAN0INT,DCAN1INT"
bitfld.long 0x00 10. " [107] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[107]" "DCAN0INT,DCAN1INT"
bitfld.long 0x00 9. " [106] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[106]" "DCAN0INT,DCAN1INT"
bitfld.long 0x00 8. " [105] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[105]" "DCAN0INT,DCAN1INT"
textline " "
bitfld.long 0x00 7. " [104] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[104]" "DCAN0INT,DCAN1INT"
bitfld.long 0x00 6. " [103] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[103]" "DCAN0INT,DCAN1INT"
bitfld.long 0x00 5. " [102] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[102]" "DCAN0INT,DCAN1INT"
bitfld.long 0x00 4. " [101] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[101]" "DCAN0INT,DCAN1INT"
textline " "
bitfld.long 0x00 3. " [100] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[100]" "DCAN0INT,DCAN1INT"
bitfld.long 0x00 2. " [99] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[99]" "DCAN0INT,DCAN1INT"
bitfld.long 0x00 1. " [98] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[98]" "DCAN0INT,DCAN1INT"
bitfld.long 0x00 0. " [97] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[97]" "DCAN0INT,DCAN1INT"
width 12.
group.long 0x100++0x3
line.long 0x0 "IF1COM,IF1 Command Mask / Command Request Register"
bitfld.long 0x00 23. " WR/RD ,Write / Read" "Read,Write"
textline " "
width 12.
bitfld.long 0x00 22. " MASK ,Access Mask Bits" "Unchanged,Identifier Mask+MDir+MXtd"
textline " "
bitfld.long 0x00 21. " ARB ,Access Arbitration Bits" "Unchanged,Identifier+Dir+Xtd+MSGVAl"
textline " "
width 12.
bitfld.long 0x00 20. " CONTROL ,Access Control Bits" "Unchanged,Control bits"
bitfld.long 0x00 19. " CLRINTPND ,Clear Interrupt Pending Bit" "Low,High"
textline " "
bitfld.long 0x00 18. " TXRQST/NEWDAT ,Access Transmission Request Bit" "Not requested,Requested"
bitfld.long 0x00 17. " DATA_A ,Access Data Bytes 0-3" "Unchanged,Data bytes 0-3"
textline " "
bitfld.long 0x00 16. " DATA_B ,Access Data Bytes 4-7" "Unchanged,Data bytes 4-7"
bitfld.long 0x00 15. " BUSY ,Busy Flag" "Reset,Set"
textline " "
bitfld.long 0x00 14. " DMAACTIVE ,Activation of DMA Feature for Subsequent Internal IF1 Update" "No active,Active"
hexmask.long.byte 0x00 0.--7. 1. " MESSAGE_NUMBER ,Message Number"
width 12.
if (((d.l((ad:0xFFF7E200+0x108)))&0x40000000)==0x00000000)
group.long 0x104++0x3
line.long 0x0 "IF1MASK,IF1 Mask Register"
bitfld.long 0x00 31. " MXTD ,Mask Extended Identifier" "No effect,Filtering"
bitfld.long 0x00 30. " MDIR ,Mask Message Direction" "No effect,Filtering"
textline " "
bitfld.long 0x00 28. " ID ,Message Identifier bit[28]" "0,1"
bitfld.long 0x00 27. ",Message Identifier bit[27]" "0,1"
bitfld.long 0x00 26. ",Message Identifier bit[26]" "0,1"
bitfld.long 0x00 25. ",Message Identifier bit[25]" "0,1"
bitfld.long 0x00 24. ",Message Identifier bit[24]" "0,1"
bitfld.long 0x00 23. ",Message Identifier bit[23]" "0,1"
bitfld.long 0x00 22. ",Message Identifier bit[22]" "0,1"
bitfld.long 0x00 21. ",Message Identifier bit[21]" "0,1"
bitfld.long 0x00 20. ",Message Identifier bit[20]" "0,1"
bitfld.long 0x00 19. ",Message Identifier bit[19]" "0,1"
bitfld.long 0x00 18. ",Message Identifier bit[18]" "0,1"
else
group.long 0x104++0x3
line.long 0x0 "IF1MASK,IF1 Mask Register"
bitfld.long 0x00 31. " MXTD ,Mask Extended Identifier" "No effect,Filtering"
bitfld.long 0x00 30. " MDIR ,Mask Message Direction" "No effect,Filtering"
textline " "
bitfld.long 0x00 28. " ID ,Message Identifier bit[28]" "0,1"
bitfld.long 0x00 27. ",Message Identifier bit[27]" "0,1"
bitfld.long 0x00 26. ",Message Identifier bit[26]" "0,1"
bitfld.long 0x00 25. ",Message Identifier bit[25]" "0,1"
bitfld.long 0x00 24. ",Message Identifier bit[24]" "0,1"
bitfld.long 0x00 23. ",Message Identifier bit[23]" "0,1"
bitfld.long 0x00 22. ",Message Identifier bit[22]" "0,1"
bitfld.long 0x00 21. ",Message Identifier bit[21]" "0,1"
bitfld.long 0x00 20. ",Message Identifier bit[20]" "0,1"
bitfld.long 0x00 19. ",Message Identifier bit[19]" "0,1"
bitfld.long 0x00 18. ",Message Identifier bit[18]" "0,1"
bitfld.long 0x00 17. ",Message Identifier bit[17]" "0,1"
bitfld.long 0x00 16. ",Message Identifier bit[16]" "0,1"
bitfld.long 0x00 15. ",Message Identifier bit[15]" "0,1"
bitfld.long 0x00 14. ",Message Identifier bit[14]" "0,1"
bitfld.long 0x00 13. ",Message Identifier bit[13]" "0,1"
bitfld.long 0x00 12. ",Message Identifier bit[12]" "0,1"
bitfld.long 0x00 11. ",Message Identifier bit[11]" "0,1"
bitfld.long 0x00 10. ",Message Identifier bit[10]" "0,1"
bitfld.long 0x00 9. ",Message Identifier bit[9]" "0,1"
bitfld.long 0x00 8. ",Message Identifier bit[8]" "0,1"
bitfld.long 0x00 7. ",Message Identifier bit[7]" "0,1"
bitfld.long 0x00 6. ",Message Identifier bit[6]" "0,1"
bitfld.long 0x00 5. ",Message Identifier bit[5]" "0,1"
bitfld.long 0x00 4. ",Message Identifier bit[4]" "0,1"
bitfld.long 0x00 3. ",Message Identifier bit[3]" "0,1"
bitfld.long 0x00 2. ",Message Identifier bit[2]" "0,1"
bitfld.long 0x00 1. ",Message Identifier bit[1]" "0,1"
bitfld.long 0x00 0. ",Message Identifier bit[0]" "0,1"
endif
width 12.
group.long 0x108++0x3
line.long 0x0 "IF1ARB,IF1 Arbitation Register"
bitfld.long 0x00 31. " MSGVAL ,Message Valid" "Ignore,Configure"
bitfld.long 0x00 30. " XTD ,Extended Identifier" "11-bit,29-bit"
bitfld.long 0x00 29. " DIR ,Message Direction" "Receive,Transmit"
hexmask.long 0x00 0.--28. 1. " ID28-0 ,Message Identifier"
width 12.
group.long 0x10C++0x3
line.long 0x0 "IF1MCTRL,IF1 Message Control Register"
bitfld.long 0x00 15. " NEWDAT ,New Data" "No new data,New data"
bitfld.long 0x00 14. " MSGLST ,Message Lost" "Not lost,Lost"
bitfld.long 0x00 13. " INTPND ,Interrupt Pending" "No interrupt,Interrupt"
textline " "
bitfld.long 0x00 12. " UMASK ,Use Acceptance Mask" "Ignored,Masked"
bitfld.long 0x00 11. " TXIE ,Transmit Interrupt Enable" "Unchanged,Set"
bitfld.long 0x00 10. " RXIE ,Receive Interrupt Enable" "Unchanged,Set"
textline " "
bitfld.long 0x00 9. " RMTEN ,Remote Enable" "Disabled,Enabled"
bitfld.long 0x00 8. " TXRQST ,Transmit Request" "Not requested,Requested"
bitfld.long 0x00 7. " EOB ,End of Block" "Single/Last,Not last"
textline " "
bitfld.long 0x00 0.--3. " DLC[3-0] ,Data Length Code" "0 byte,1 bytes,2 bytes,3 bytes,4 bytes,5 bytes,6 bytes,7 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes"
width 12.
group.long 0x110++0x3
line.long 0x0 "IF1DATA,IF1 Data A Register"
hexmask.long.byte 0x00 24.--31. 1. " DATA [3] ,4th data byte of a CAN Data Frame"
hexmask.long.byte 0x00 16.--23. 1. " [2] ,3rd data byte of a CAN Data Frame"
hexmask.long.byte 0x00 8.--15. 1. " [1] ,2nd data byte of a CAN Data Frame"
hexmask.long.byte 0x00 0.--7. 1. " [0] ,1st data byte of a CAN Data Frame"
group.long 0x114++0x3
line.long 0x0 "IF1DATB,IF1 Data B Register"
hexmask.long.byte 0x00 24.--31. 1. " DATA [7] ,8th data byte of a CAN Data Frame"
hexmask.long.byte 0x00 16.--23. 1. " [6] ,7th data byte of a CAN Data Frame"
hexmask.long.byte 0x00 8.--15. 1. " [5] ,6th data byte of a CAN Data Frame"
hexmask.long.byte 0x00 0.--7. 1. " [4] ,5th data byte of a CAN Data Frame"
width 12.
group.long 0x120++0x3
line.long 0x0 "IF2COM,IF2 Command Mask / Command Request Register"
bitfld.long 0x00 23. " WR/RD ,Write / Read" "Read,Write"
textline " "
width 12.
bitfld.long 0x00 22. " MASK ,Access Mask Bits" "Unchanged,Identifier Mask+MDir+MXtd"
textline " "
bitfld.long 0x00 21. " ARB ,Access Arbitration Bits" "Unchanged,Identifier+Dir+Xtd+MSGVAl"
textline " "
width 12.
bitfld.long 0x00 20. " CONTROL ,Access Control Bits" "Unchanged,Control bits"
bitfld.long 0x00 19. " CLRINTPND ,Clear Interrupt Pending Bit" "Low,High"
textline " "
bitfld.long 0x00 18. " TXRQST/NEWDAT ,Access Transmission Request Bit" "Not requested,Requested"
bitfld.long 0x00 17. " DATA_A ,Access Data Bytes 0-3" "Unchanged,Data bytes 0-3"
textline " "
bitfld.long 0x00 16. " DATA_B ,Access Data Bytes 4-7" "Unchanged,Data bytes 4-7"
bitfld.long 0x00 15. " BUSY ,Busy Flag" "Reset,Set"
textline " "
bitfld.long 0x00 14. " DMAACTIVE ,Activation of DMA Feature for Subsequent Internal IF1 Update" "No active,Active"
hexmask.long.byte 0x00 0.--7. 1. " MESSAGE_NUMBER ,Message Number"
width 12.
if (((d.l((ad:0xFFF7E200+0x128)))&0x40000000)==0x00000000)
group.long 0x124++0x3
line.long 0x0 "IF2MASK,IF2 Mask Register"
bitfld.long 0x00 31. " MXTD ,Mask Extended Identifier" "No effect,Filtering"
bitfld.long 0x00 30. " MDIR ,Mask Message Direction" "No effect,Filtering"
textline " "
bitfld.long 0x00 28. " ID ,Message Identifier bit[28]" "0,1"
bitfld.long 0x00 27. ",Message Identifier bit[27]" "0,1"
bitfld.long 0x00 26. ",Message Identifier bit[26]" "0,1"
bitfld.long 0x00 25. ",Message Identifier bit[25]" "0,1"
bitfld.long 0x00 24. ",Message Identifier bit[24]" "0,1"
bitfld.long 0x00 23. ",Message Identifier bit[23]" "0,1"
bitfld.long 0x00 22. ",Message Identifier bit[22]" "0,1"
bitfld.long 0x00 21. ",Message Identifier bit[21]" "0,1"
bitfld.long 0x00 20. ",Message Identifier bit[20]" "0,1"
bitfld.long 0x00 19. ",Message Identifier bit[19]" "0,1"
bitfld.long 0x00 18. ",Message Identifier bit[18]" "0,1"
else
group.long 0x124++0x3
line.long 0x0 "IF2MASK,IF2 Mask Register"
bitfld.long 0x00 31. " MXTD ,Mask Extended Identifier" "No effect,Filtering"
bitfld.long 0x00 30. " MDIR ,Mask Message Direction" "No effect,Filtering"
textline " "
bitfld.long 0x00 28. " ID ,Message Identifier bit[28]" "0,1"
bitfld.long 0x00 27. ",Message Identifier bit[27]" "0,1"
bitfld.long 0x00 26. ",Message Identifier bit[26]" "0,1"
bitfld.long 0x00 25. ",Message Identifier bit[25]" "0,1"
bitfld.long 0x00 24. ",Message Identifier bit[24]" "0,1"
bitfld.long 0x00 23. ",Message Identifier bit[23]" "0,1"
bitfld.long 0x00 22. ",Message Identifier bit[22]" "0,1"
bitfld.long 0x00 21. ",Message Identifier bit[21]" "0,1"
bitfld.long 0x00 20. ",Message Identifier bit[20]" "0,1"
bitfld.long 0x00 19. ",Message Identifier bit[19]" "0,1"
bitfld.long 0x00 18. ",Message Identifier bit[18]" "0,1"
bitfld.long 0x00 17. ",Message Identifier bit[17]" "0,1"
bitfld.long 0x00 16. ",Message Identifier bit[16]" "0,1"
bitfld.long 0x00 15. ",Message Identifier bit[15]" "0,1"
bitfld.long 0x00 14. ",Message Identifier bit[14]" "0,1"
bitfld.long 0x00 13. ",Message Identifier bit[13]" "0,1"
bitfld.long 0x00 12. ",Message Identifier bit[12]" "0,1"
bitfld.long 0x00 11. ",Message Identifier bit[11]" "0,1"
bitfld.long 0x00 10. ",Message Identifier bit[10]" "0,1"
bitfld.long 0x00 9. ",Message Identifier bit[9]" "0,1"
bitfld.long 0x00 8. ",Message Identifier bit[8]" "0,1"
bitfld.long 0x00 7. ",Message Identifier bit[7]" "0,1"
bitfld.long 0x00 6. ",Message Identifier bit[6]" "0,1"
bitfld.long 0x00 5. ",Message Identifier bit[5]" "0,1"
bitfld.long 0x00 4. ",Message Identifier bit[4]" "0,1"
bitfld.long 0x00 3. ",Message Identifier bit[3]" "0,1"
bitfld.long 0x00 2. ",Message Identifier bit[2]" "0,1"
bitfld.long 0x00 1. ",Message Identifier bit[1]" "0,1"
bitfld.long 0x00 0. ",Message Identifier bit[0]" "0,1"
endif
width 12.
group.long 0x128++0x3
line.long 0x0 "IF2ARB,IF2 Arbitation Register"
bitfld.long 0x00 31. " MSGVAL ,Message Valid" "Ignore,Configure"
bitfld.long 0x00 30. " XTD ,Extended Identifier" "11-bit,29-bit"
bitfld.long 0x00 29. " DIR ,Message Direction" "Receive,Transmit"
hexmask.long 0x00 0.--28. 1. " ID28-0 ,Message Identifier"
width 12.
group.long 0x12C++0x3
line.long 0x0 "IF2MCTRL,IF2 Message Control Register"
bitfld.long 0x00 15. " NEWDAT ,New Data" "No new data,New data"
bitfld.long 0x00 14. " MSGLST ,Message Lost" "Not lost,Lost"
bitfld.long 0x00 13. " INTPND ,Interrupt Pending" "No interrupt,Interrupt"
textline " "
bitfld.long 0x00 12. " UMASK ,Use Acceptance Mask" "Ignored,Masked"
bitfld.long 0x00 11. " TXIE ,Transmit Interrupt Enable" "Unchanged,Set"
bitfld.long 0x00 10. " RXIE ,Receive Interrupt Enable" "Unchanged,Set"
textline " "
bitfld.long 0x00 9. " RMTEN ,Remote Enable" "Disabled,Enabled"
bitfld.long 0x00 8. " TXRQST ,Transmit Request" "Not requested,Requested"
bitfld.long 0x00 7. " EOB ,End of Block" "Single/Last,Not last"
textline " "
bitfld.long 0x00 0.--3. " DLC[3-0] ,Data Length Code" "0 byte,1 bytes,2 bytes,3 bytes,4 bytes,5 bytes,6 bytes,7 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes"
width 12.
group.long 0x130++0x3
line.long 0x0 "IF2DATA,IF2 Data A Register"
hexmask.long.byte 0x00 24.--31. 1. " DATA [3] ,4th data byte of a CAN Data Frame"
hexmask.long.byte 0x00 16.--23. 1. " [2] ,3rd data byte of a CAN Data Frame"
hexmask.long.byte 0x00 8.--15. 1. " [1] ,2nd data byte of a CAN Data Frame"
hexmask.long.byte 0x00 0.--7. 1. " [0] ,1st data byte of a CAN Data Frame"
group.long 0x134++0x3
line.long 0x0 "IF2DATB,IF2 Data B Register"
hexmask.long.byte 0x00 24.--31. 1. " DATA [7] ,8th data byte of a CAN Data Frame"
hexmask.long.byte 0x00 16.--23. 1. " [6] ,7th data byte of a CAN Data Frame"
hexmask.long.byte 0x00 8.--15. 1. " [5] ,6th data byte of a CAN Data Frame"
hexmask.long.byte 0x00 0.--7. 1. " [4] ,5th data byte of a CAN Data Frame"
width 12.
group.long 0x140++0x3
line.long 0x0 "IF3OB,IF3 Observation Register"
bitfld.long 0x00 15. " IF3UPD ,IF3 Updata Data" "Not loaded,Loaded"
bitfld.long 0x00 12. " IF3SDB ,IF3 Status of Data B Read Access" "Low,High"
bitfld.long 0x00 11. " IF3SDA ,IF3 Status of Data A Read Access" "Low,High"
textline " "
bitfld.long 0x00 10. " IF3SC ,IF3 Status of Control Bits Read Access" "Low,High"
bitfld.long 0x00 9. " IF3SA ,IF3 Status of Arbitration Data Read Access" "Low,High"
bitfld.long 0x00 8. " IF3SM ,IF3 Status of Mask Data Read Access" "Low,High"
textline " "
bitfld.long 0x00 4. " DATA_B ,Data B Read Observation" "Not read,Read"
bitfld.long 0x00 3. " DATA_A ,Data A Read Observation" "Not read,Read"
bitfld.long 0x00 2. " CTRL ,Ctrl Read Observation" "Not read,Read"
textline " "
bitfld.long 0x00 1. " ARB ,Arbitration Data Read Observation" "Not read,Read"
bitfld.long 0x00 0. " MASK ,Mask Data Read Observation" "Not read,Read"
if (((d.l((ad:0xFFF7E200+0x148)))&0x40000000)==0x00000000)
rgroup.long 0x144++0x3
line.long 0x0 "IF3MASK,IF3 Mask Register"
bitfld.long 0x00 31. " MXTD ,Mask Extended Identifier" "No effect,Filtering"
bitfld.long 0x00 30. " MDIR ,Mask Message Direction" "No effect,Filtering"
textline " "
bitfld.long 0x00 28. " ID ,Message Identifier bit[28]" "0,1"
bitfld.long 0x00 27. ",Message Identifier bit[27]" "0,1"
bitfld.long 0x00 26. ",Message Identifier bit[26]" "0,1"
bitfld.long 0x00 25. ",Message Identifier bit[25]" "0,1"
bitfld.long 0x00 24. ",Message Identifier bit[24]" "0,1"
bitfld.long 0x00 23. ",Message Identifier bit[23]" "0,1"
bitfld.long 0x00 22. ",Message Identifier bit[22]" "0,1"
bitfld.long 0x00 21. ",Message Identifier bit[21]" "0,1"
bitfld.long 0x00 20. ",Message Identifier bit[20]" "0,1"
bitfld.long 0x00 19. ",Message Identifier bit[19]" "0,1"
bitfld.long 0x00 18. ",Message Identifier bit[18]" "0,1"
else
group.long 0x144++0x3
line.long 0x0 "IF3MASK,IF3 Mask Register"
bitfld.long 0x00 31. " MXTD ,Mask Extended Identifier" "No effect,Filtering"
bitfld.long 0x00 30. " MDIR ,Mask Message Direction" "No effect,Filtering"
textline " "
bitfld.long 0x00 28. " ID ,Message Identifier bit[28]" "0,1"
bitfld.long 0x00 27. ",Message Identifier bit[27]" "0,1"
bitfld.long 0x00 26. ",Message Identifier bit[26]" "0,1"
bitfld.long 0x00 25. ",Message Identifier bit[25]" "0,1"
bitfld.long 0x00 24. ",Message Identifier bit[24]" "0,1"
bitfld.long 0x00 23. ",Message Identifier bit[23]" "0,1"
bitfld.long 0x00 22. ",Message Identifier bit[22]" "0,1"
bitfld.long 0x00 21. ",Message Identifier bit[21]" "0,1"
bitfld.long 0x00 20. ",Message Identifier bit[20]" "0,1"
bitfld.long 0x00 19. ",Message Identifier bit[19]" "0,1"
bitfld.long 0x00 18. ",Message Identifier bit[18]" "0,1"
bitfld.long 0x00 17. ",Message Identifier bit[17]" "0,1"
bitfld.long 0x00 16. ",Message Identifier bit[16]" "0,1"
bitfld.long 0x00 15. ",Message Identifier bit[15]" "0,1"
bitfld.long 0x00 14. ",Message Identifier bit[14]" "0,1"
bitfld.long 0x00 13. ",Message Identifier bit[13]" "0,1"
bitfld.long 0x00 12. ",Message Identifier bit[12]" "0,1"
bitfld.long 0x00 11. ",Message Identifier bit[11]" "0,1"
bitfld.long 0x00 10. ",Message Identifier bit[10]" "0,1"
bitfld.long 0x00 9. ",Message Identifier bit[9]" "0,1"
bitfld.long 0x00 8. ",Message Identifier bit[8]" "0,1"
bitfld.long 0x00 7. ",Message Identifier bit[7]" "0,1"
bitfld.long 0x00 6. ",Message Identifier bit[6]" "0,1"
bitfld.long 0x00 5. ",Message Identifier bit[5]" "0,1"
bitfld.long 0x00 4. ",Message Identifier bit[4]" "0,1"
bitfld.long 0x00 3. ",Message Identifier bit[3]" "0,1"
bitfld.long 0x00 2. ",Message Identifier bit[2]" "0,1"
bitfld.long 0x00 1. ",Message Identifier bit[1]" "0,1"
bitfld.long 0x00 0. ",Message Identifier bit[0]" "0,1"
endif
group.long 0x148++0x3
line.long 0x0 "IF3ARB,IF3 Arbitation Register"
bitfld.long 0x00 31. " MSGVAL ,Message Valid" "Ignored,Configured"
bitfld.long 0x00 30. " XTD ,Extended Identifier" "11-bit,29-bit"
bitfld.long 0x00 29. " DIR ,Message Direction" "Receive,Transmit"
textline " "
hexmask.long 0x00 0.--28. 1. " ID[28-0] ,Message Identifier"
group.long 0x14C++0x3
line.long 0x0 "IF3MCTRL,IF3 Message Control Register"
bitfld.long 0x00 15. " NEWDAT ,New Data" "No new data,New data"
bitfld.long 0x00 14. " MSGLST ,Message Lost" "Not lost,Lost"
bitfld.long 0x00 13. " INTPND ,Interrupt Pending" "No interrupt,Interrupt"
textline " "
bitfld.long 0x00 12. " UMASK ,Use Acceptance Mask" "Ignored,Masked"
bitfld.long 0x00 11. " TXIE ,Transmit Interrupt Enable" "Unchanged,Enabled"
bitfld.long 0x00 10. " RXIE ,Receive Interrupt Enable" "Unchanged,Enabled"
textline " "
bitfld.long 0x00 9. " RMTEN ,Remote Enable" "Unchanged,Enabled"
bitfld.long 0x00 8. " TXRQST ,Transmit Request" "Not requested,Requested"
bitfld.long 0x00 7. " EOB ,End of Block" "Not last,Single/Last"
textline " "
bitfld.long 0x00 0.--3. " DLC[3-0] ,Data Length Code" "0 byte,1 byte,2 bytes,3 bytes,4 bytes,5 bytes,6 bytes,7 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes"
width 12.
group.long 0x150++0x3
line.long 0x0 "IF3DATA,IF3 Data A Register"
hexmask.long.byte 0x00 24.--31. 1. " DATA [3] ,4th data byte of a CAN Data Frame"
hexmask.long.byte 0x00 16.--23. 1. " [2] ,3rd data byte of a CAN Data Frame"
hexmask.long.byte 0x00 8.--15. 1. " [1] ,2nd data byte of a CAN Data Frame"
hexmask.long.byte 0x00 0.--7. 1. " [0] ,1st data byte of a CAN Data Frame"
group.long 0x154++0x3
line.long 0x0 "IF3DATB,IF3 Data B Register"
hexmask.long.byte 0x00 24.--31. 1. " DATA [7] ,8th data byte of a CAN Data Frame"
hexmask.long.byte 0x00 16.--23. 1. " [6] ,7th data byte of a CAN Data Frame"
hexmask.long.byte 0x00 8.--15. 1. " [5] ,6th data byte of a CAN Data Frame"
hexmask.long.byte 0x00 0.--7. 1. " ATA [4] ,5th data byte of a CAN Data Frame"
width 12.
group.long 0x160++0x3
line.long 0x0 "IF3UENA2_1,Update Enable 2_1 Register"
bitfld.long 0x00 31. " IF3UPDATEEN [32] ,IF3 Update Enabled Bit[32]" "Disabled,Enabled"
bitfld.long 0x00 30. " [31] ,IF3 Update Enabled Bit[31]" "Disabled,Enabled"
bitfld.long 0x00 29. " [30] ,IF3 Update Enabled Bit[30]" "Disabled,Enabled"
bitfld.long 0x00 28. " [29] ,IF3 Update Enabled Bit[29]" "Disabled,Enabled"
textline " "
bitfld.long 0x00 27. " [28] ,IF3 Update Enabled Bit[28]" "Disabled,Enabled"
bitfld.long 0x00 26. " [27] ,IF3 Update Enabled Bit[27]" "Disabled,Enabled"
bitfld.long 0x00 25. " [26] ,IF3 Update Enabled Bit[26]" "Disabled,Enabled"
bitfld.long 0x00 24. " [25] ,IF3 Update Enabled Bit[25]" "Disabled,Enabled"
textline " "
bitfld.long 0x00 23. " [24] ,IF3 Update Enabled Bit[24]" "Disabled,Enabled"
bitfld.long 0x00 22. " [23] ,IF3 Update Enabled Bit[23]" "Disabled,Enabled"
bitfld.long 0x00 21. " [22] ,IF3 Update Enabled Bit[22]" "Disabled,Enabled"
bitfld.long 0x00 20. " [21] ,IF3 Update Enabled Bit[21]" "Disabled,Enabled"
textline " "
bitfld.long 0x00 19. " [20] ,IF3 Update Enabled Bit[20]" "Disabled,Enabled"
bitfld.long 0x00 18. " [19] ,IF3 Update Enabled Bit[19]" "Disabled,Enabled"
bitfld.long 0x00 17. " [18] ,IF3 Update Enabled Bit[18]" "Disabled,Enabled"
bitfld.long 0x00 16. " [17] ,IF3 Update Enabled Bit[17]" "Disabled,Enabled"
textline " "
bitfld.long 0x00 15. " [16] ,IF3 Update Enabled Bit[16]" "Disabled,Enabled"
bitfld.long 0x00 14. " [15] ,IF3 Update Enabled Bit[15]" "Disabled,Enabled"
bitfld.long 0x00 13. " [14] ,IF3 Update Enabled Bit[14]" "Disabled,Enabled"
bitfld.long 0x00 12. " [13] ,IF3 Update Enabled Bit[13]" "Disabled,Enabled"
textline " "
bitfld.long 0x00 11. " [12] ,IF3 Update Enabled Bit[12]" "Disabled,Enabled"
bitfld.long 0x00 10. " [11] ,IF3 Update Enabled Bit[11]" "Disabled,Enabled"
bitfld.long 0x00 9. " [10] ,IF3 Update Enabled Bit[10]" "Disabled,Enabled"
bitfld.long 0x00 8. " [9] ,IF3 Update Enabled Bit[9]" "Disabled,Enabled"
textline " "
bitfld.long 0x00 7. " [8] ,IF3 Update Enabled Bit[8]" "Disabled,Enabled"
bitfld.long 0x00 6. " [7] ,IF3 Update Enabled Bit[7]" "Disabled,Enabled"
bitfld.long 0x00 5. " [6] ,IF3 Update Enabled Bit[6]" "Disabled,Enabled"
bitfld.long 0x00 4. " [5] ,IF3 Update Enabled Bit[5]" "Disabled,Enabled"
textline " "
bitfld.long 0x00 3. " [4] ,IF3 Update Enabled Bit[4]" "Disabled,Enabled"
bitfld.long 0x00 2. " [3] ,IF3 Update Enabled Bit[3]" "Disabled,Enabled"
bitfld.long 0x00 1. " [2] ,IF3 Update Enabled Bit[2]" "Disabled,Enabled"
bitfld.long 0x00 0. " [1] ,IF3 Update Enabled Bit[1]" "Disabled,Enabled"
group.long 0x164++0x3
line.long 0x0 "IF3UENA4_3,Update Enable 4_3 Register"
bitfld.long 0x00 31. " IF3UPDATEEN [64] ,IF3 Update Enabled Bit[64]" "Disabled,Enabled"
bitfld.long 0x00 30. " [63] ,IF3 Update Enabled Bit[63]" "Disabled,Enabled"
bitfld.long 0x00 29. " [62] ,IF3 Update Enabled Bit[62]" "Disabled,Enabled"
bitfld.long 0x00 28. " [61] ,IF3 Update Enabled Bit[61]" "Disabled,Enabled"
textline " "
bitfld.long 0x00 27. " [60] ,IF3 Update Enabled Bit[60]" "Disabled,Enabled"
bitfld.long 0x00 26. " [59] ,IF3 Update Enabled Bit[59]" "Disabled,Enabled"
bitfld.long 0x00 25. " [58] ,IF3 Update Enabled Bit[58]" "Disabled,Enabled"
bitfld.long 0x00 24. " [57] ,IF3 Update Enabled Bit[57]" "Disabled,Enabled"
textline " "
bitfld.long 0x00 23. " [56] ,IF3 Update Enabled Bit[56]" "Disabled,Enabled"
bitfld.long 0x00 22. " [55] ,IF3 Update Enabled Bit[55]" "Disabled,Enabled"
bitfld.long 0x00 21. " [54] ,IF3 Update Enabled Bit[54]" "Disabled,Enabled"
bitfld.long 0x00 20. " [53] ,IF3 Update Enabled Bit[53]" "Disabled,Enabled"
textline " "
bitfld.long 0x00 19. " [52] ,IF3 Update Enabled Bit[52]" "Disabled,Enabled"
bitfld.long 0x00 18. " [51] ,IF3 Update Enabled Bit[51]" "Disabled,Enabled"
bitfld.long 0x00 17. " [50] ,IF3 Update Enabled Bit[50]" "Disabled,Enabled"
bitfld.long 0x00 16. " [49] ,IF3 Update Enabled Bit[49]" "Disabled,Enabled"
textline " "
bitfld.long 0x00 15. " [48] ,IF3 Update Enabled Bit[48]" "Disabled,Enabled"
bitfld.long 0x00 14. " [47] ,IF3 Update Enabled Bit[47]" "Disabled,Enabled"
bitfld.long 0x00 13. " [46] ,IF3 Update Enabled Bit[46]" "Disabled,Enabled"
bitfld.long 0x00 12. " [45] ,IF3 Update Enabled Bit[45]" "Disabled,Enabled"
textline " "
bitfld.long 0x00 11. " [44] ,IF3 Update Enabled Bit[44]" "Disabled,Enabled"
bitfld.long 0x00 10. " [43] ,IF3 Update Enabled Bit[43]" "Disabled,Enabled"
bitfld.long 0x00 9. " [42] ,IF3 Update Enabled Bit[42]" "Disabled,Enabled"
bitfld.long 0x00 8. " [41] ,IF3 Update Enabled Bit[41]" "Disabled,Enabled"
textline " "
bitfld.long 0x00 7. " [40] ,IF3 Update Enabled Bit[40]" "Disabled,Enabled"
bitfld.long 0x00 6. " [39] ,IF3 Update Enabled Bit[39]" "Disabled,Enabled"
bitfld.long 0x00 5. " [38] ,IF3 Update Enabled Bit[38]" "Disabled,Enabled"
bitfld.long 0x00 4. " [37] ,IF3 Update Enabled Bit[37]" "Disabled,Enabled"
textline " "
bitfld.long 0x00 3. " [36] ,IF3 Update Enabled Bit[36]" "Disabled,Enabled"
bitfld.long 0x00 2. " [35] ,IF3 Update Enabled Bit[35]" "Disabled,Enabled"
bitfld.long 0x00 1. " [34] ,IF3 Update Enabled Bit[34]" "Disabled,Enabled"
bitfld.long 0x00 0. " [33] ,IF3 Update Enabled Bit[33]" "Disabled,Enabled"
group.long 0x168++0x3
line.long 0x0 "IF3UENA6_5,Update Enable 6_5 Register"
bitfld.long 0x00 31. " IF3UPDATEEN [96] ,IF3 Update Enabled Bit[96]" "Disabled,Enabled"
bitfld.long 0x00 30. " [95] ,IF3 Update Enabled Bit[95]" "Disabled,Enabled"
bitfld.long 0x00 29. " [94] ,IF3 Update Enabled Bit[94]" "Disabled,Enabled"
bitfld.long 0x00 28. " [93] ,IF3 Update Enabled Bit[93]" "Disabled,Enabled"
textline " "
bitfld.long 0x00 27. " [92] ,IF3 Update Enabled Bit[92]" "Disabled,Enabled"
bitfld.long 0x00 26. " [91] ,IF3 Update Enabled Bit[91]" "Disabled,Enabled"
bitfld.long 0x00 25. " [90] ,IF3 Update Enabled Bit[90]" "Disabled,Enabled"
bitfld.long 0x00 24. " [89] ,IF3 Update Enabled Bit[89]" "Disabled,Enabled"
textline " "
bitfld.long 0x00 23. " [88] ,IF3 Update Enabled Bit[88]" "Disabled,Enabled"
bitfld.long 0x00 22. " [87] ,IF3 Update Enabled Bit[87]" "Disabled,Enabled"
bitfld.long 0x00 21. " [86] ,IF3 Update Enabled Bit[86]" "Disabled,Enabled"
bitfld.long 0x00 20. " [85] ,IF3 Update Enabled Bit[85]" "Disabled,Enabled"
textline " "
bitfld.long 0x00 19. " [84] ,IF3 Update Enabled Bit[84]" "Disabled,Enabled"
bitfld.long 0x00 18. " [83] ,IF3 Update Enabled Bit[83]" "Disabled,Enabled"
bitfld.long 0x00 17. " [82] ,IF3 Update Enabled Bit[82]" "Disabled,Enabled"
bitfld.long 0x00 16. " [81] ,IF3 Update Enabled Bit[81]" "Disabled,Enabled"
textline " "
bitfld.long 0x00 15. " [80] ,IF3 Update Enabled Bit[80]" "Disabled,Enabled"
bitfld.long 0x00 14. " [79] ,IF3 Update Enabled Bit[79]" "Disabled,Enabled"
bitfld.long 0x00 13. " [78] ,IF3 Update Enabled Bit[78]" "Disabled,Enabled"
bitfld.long 0x00 12. " [77] ,IF3 Update Enabled Bit[77]" "Disabled,Enabled"
textline " "
bitfld.long 0x00 11. " [76] ,IF3 Update Enabled Bit[76]" "Disabled,Enabled"
bitfld.long 0x00 10. " [75] ,IF3 Update Enabled Bit[75]" "Disabled,Enabled"
bitfld.long 0x00 9. " [74] ,IF3 Update Enabled Bit[74]" "Disabled,Enabled"
bitfld.long 0x00 8. " [73] ,IF3 Update Enabled Bit[73]" "Disabled,Enabled"
textline " "
bitfld.long 0x00 7. " [72] ,IF3 Update Enabled Bit[72]" "Disabled,Enabled"
bitfld.long 0x00 6. " [71] ,IF3 Update Enabled Bit[71]" "Disabled,Enabled"
bitfld.long 0x00 5. " [70] ,IF3 Update Enabled Bit[70]" "Disabled,Enabled"
bitfld.long 0x00 4. " [69] ,IF3 Update Enabled Bit[69]" "Disabled,Enabled"
textline " "
bitfld.long 0x00 3. " [68] ,IF3 Update Enabled Bit[68]" "Disabled,Enabled"
bitfld.long 0x00 2. " [67] ,IF3 Update Enabled Bit[67]" "Disabled,Enabled"
bitfld.long 0x00 1. " [66] ,IF3 Update Enabled Bit[66]" "Disabled,Enabled"
bitfld.long 0x00 0. " [65] ,IF3 Update Enabled Bit[65]" "Disabled,Enabled"
group.long 0x16C++0x3
line.long 0x0 "IF3UENA8_7,Update Enable 8_7 Register"
bitfld.long 0x00 31. " IF3UPDATEEN [128] ,IF3 Update Enabled Bit[128]" "Disabled,Enabled"
bitfld.long 0x00 30. " [127] ,IF3 Update Enabled Bit[127]" "Disabled,Enabled"
bitfld.long 0x00 29. " [126] ,IF3 Update Enabled Bit[126]" "Disabled,Enabled"
bitfld.long 0x00 28. " [125] ,IF3 Update Enabled Bit[125]" "Disabled,Enabled"
textline " "
bitfld.long 0x00 27. " [124] ,IF3 Update Enabled Bit[124]" "Disabled,Enabled"
bitfld.long 0x00 26. " [123] ,IF3 Update Enabled Bit[123]" "Disabled,Enabled"
bitfld.long 0x00 25. " [122] ,IF3 Update Enabled Bit[122]" "Disabled,Enabled"
bitfld.long 0x00 24. " [121] ,IF3 Update Enabled Bit[121]" "Disabled,Enabled"
textline " "
bitfld.long 0x00 23. " [120] ,IF3 Update Enabled Bit[120]" "Disabled,Enabled"
bitfld.long 0x00 22. " [119] ,IF3 Update Enabled Bit[119]" "Disabled,Enabled"
bitfld.long 0x00 21. " [118] ,IF3 Update Enabled Bit[118]" "Disabled,Enabled"
bitfld.long 0x00 20. " [117] ,IF3 Update Enabled Bit[117]" "Disabled,Enabled"
textline " "
bitfld.long 0x00 19. " [116] ,IF3 Update Enabled Bit[116]" "Disabled,Enabled"
bitfld.long 0x00 18. " [115] ,IF3 Update Enabled Bit[115]" "Disabled,Enabled"
bitfld.long 0x00 17. " [114] ,IF3 Update Enabled Bit[114]" "Disabled,Enabled"
bitfld.long 0x00 16. " [113] ,IF3 Update Enabled Bit[113]" "Disabled,Enabled"
textline " "
bitfld.long 0x00 15. " [112] ,IF3 Update Enabled Bit[112]" "Disabled,Enabled"
bitfld.long 0x00 14. " [111] ,IF3 Update Enabled Bit[111]" "Disabled,Enabled"
bitfld.long 0x00 13. " [110] ,IF3 Update Enabled Bit[110]" "Disabled,Enabled"
bitfld.long 0x00 12. " [109] ,IF3 Update Enabled Bit[109]" "Disabled,Enabled"
textline " "
bitfld.long 0x00 11. " [108] ,IF3 Update Enabled Bit[108]" "Disabled,Enabled"
bitfld.long 0x00 10. " [107] ,IF3 Update Enabled Bit[107]" "Disabled,Enabled"
bitfld.long 0x00 9. " [106] ,IF3 Update Enabled Bit[106]" "Disabled,Enabled"
bitfld.long 0x00 8. " [105] ,IF3 Update Enabled Bit[105]" "Disabled,Enabled"
textline " "
bitfld.long 0x00 7. " [104] ,IF3 Update Enabled Bit[104]" "Disabled,Enabled"
bitfld.long 0x00 6. " [103] ,IF3 Update Enabled Bit[103]" "Disabled,Enabled"
bitfld.long 0x00 5. " [102] ,IF3 Update Enabled Bit[102]" "Disabled,Enabled"
bitfld.long 0x00 4. " [101] ,IF3 Update Enabled Bit[101]" "Disabled,Enabled"
textline " "
bitfld.long 0x00 3. " [100] ,IF3 Update Enabled Bit[100]" "Disabled,Enabled"
bitfld.long 0x00 2. " [99] ,IF3 Update Enabled Bit[99]" "Disabled,Enabled"
bitfld.long 0x00 1. " [98] ,IF3 Update Enabled Bit[98]" "Disabled,Enabled"
bitfld.long 0x00 0. " [97] ,IF3 Update Enabled Bit[97]" "Disabled,Enabled"
width 12.
group.long 0x1E0++0x3
line.long 0x0 "IOCTRLTX,TX IO Control Register"
bitfld.long 0x00 18. " PU ,Selection of Pull Direction" "Pull down,Pull up"
bitfld.long 0x00 17. " PD ,Pull Functionality Disable" "No,Yes"
bitfld.long 0x00 16. " OD ,Open Drain Mode" "Push pull,Open Drain"
textline " "
bitfld.long 0x00 3. " FUNC ,Functionality of Pin" "General,CAN"
bitfld.long 0x00 2. " DIR ,Direction of Pin" "Input,Output"
bitfld.long 0x00 1. " OUT ,Value to Drive to Pin if Configured for I/O" "Low,High"
textline " "
bitfld.long 0x00 0. " IN ,Value of Pin" "Low,High"
group.long 0x1E4++0x3
line.long 0x0 "IOCTRLRX,RX IO Control Register"
bitfld.long 0x00 18. " PU ,Selection of Pull Direction" "Pull down,Pull up"
bitfld.long 0x00 17. " PD ,Pull Functionality Disable" "No,Yes"
bitfld.long 0x00 16. " OD ,Open Drain Mode" "Push pull,Open Drain"
textline " "
bitfld.long 0x00 3. " FUNC ,Functionality of Pin" "General,CAN"
bitfld.long 0x00 2. " DIR ,Direction of Pin" "Input,Output"
bitfld.long 0x00 1. " OUT ,Value to Drive to Pin if Configured for I/O" "Low,High"
textline " "
bitfld.long 0x00 0. " IN ,Value of Pin" "Low,High"
width 0xb
tree.end
tree.end
tree.open "MibSPI (Multi-Buffered Serial Peripheral Interface Module)"
tree "MibSPI1"
base ad:0xFFF7F400
width 17.
group.long 0x00++0x03
line.long 0x00 "SPIGCR0,SPI Global Control Register 0"
bitfld.long 0x00 0. " NRESET ,Reset bit for the module" "No reset,Reset"
if (((d.l(ad:0xFFF7F400+0x4))&0x3)==0x00)
group.long 0x04++0x03
line.long 0x00 "SPIGCR1,SPI Global Control Register 1"
bitfld.long 0x00 24. " SPIEN ,SPI enable" "Disabled,Enabled"
bitfld.long 0x00 16. " LOOPBACK ,Internal loop-back test mode" "Disabled,Enabled"
bitfld.long 0x00 8. " POWERDOWN ,SPI state machine enters a power-down state" "No power-down,Power-down"
textline " "
bitfld.long 0x00 1. " CLKMOD ,Clock mode" "External,Internally"
bitfld.long 0x00 0. " MASTER ,SPISIMO/SPISOMI pin direction determination" "Input/ouput,Output/input"
else
group.long 0x04++0x03
line.long 0x00 "SPIGCR1,SPI Global Control Register 1"
bitfld.long 0x00 24. " SPIEN ,SPI enable" "Disabled,Enabled"
bitfld.long 0x00 8. " POWERDOWN ,SPI state machine enters a power-down state" "No power-down,Power-down"
bitfld.long 0x00 1. " CLKMOD ,Clock mode" "External,Internally"
textline " "
bitfld.long 0x00 0. " MASTER ,SPISIMO/SPISOMI pin direction determination" "Input/ouput,Output/input"
endif
group.long 0x08++0x03
line.long 0x00 "SPIINT0,SPI Interrupt Register"
bitfld.long 0x00 24. " ENABLEHIGHZ ,SPIENA pin high-impedance enable" "Inactive,Active"
bitfld.long 0x00 16. " DMAREQEN ,DMA request enable" "Disabled,Enabled"
bitfld.long 0x00 9. " TXINTENA ,TX interrupt flag enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 8. " RXINTENA ,RX interrupt flag enable" "Disabled,Enabled"
bitfld.long 0x00 6. " RXOVRNINTENA ,Overrun interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 4. " BITERRENA ,Enables interrupt on bit error" "Disabled,Enabled"
textline " "
bitfld.long 0x00 3. " DESYNCENA ,Enables interrupt on desynchronized slave" "Disabled,Enabled"
bitfld.long 0x00 2. " PARERRENA ,Enables interrupt-on-parity-error" "Disabled,Enabled"
bitfld.long 0x00 1. " TIMEOUTENA ,Enables interrupt on ENA signal time-out" "Disabled,Enabled"
textline " "
bitfld.long 0x00 0. " DLENERRENA ,Data length error interrupt enable" "Disabled,Enabled"
group.long 0x0C++0x03
line.long 0x00 "SPILVL,SPI Interrupt Level Register"
bitfld.long 0x00 9. " TXINTLVL ,Transmit interrupt level" "INT0,INT1"
bitfld.long 0x00 8. " RXINTLVL ,Receive interrupt level" "INT0,INT1"
bitfld.long 0x00 6. " RXOVRNINTLVL ,Receive overrun interrupt level" "INT0,INT1"
textline " "
bitfld.long 0x00 4. " BITERRLVL ,Bit error interrupt level" "INT0,INT1"
bitfld.long 0x00 3. " DESYNCLVL ,Desynchronized slave interrupt level (master mode only)" "INT0,INT1"
bitfld.long 0x00 2. " PARERRLVL ,Parity error interrupt level" "INT0,INT1"
textline " "
bitfld.long 0x00 1. " TIMEOUTLVL ,SPIENA pin time-out interrupt level" "INT0,INT1"
bitfld.long 0x00 0. " DLENERRLVL ,Data length error interrupt level (line) select" "INT0,INT1"
group.long 0x10++0x03
line.long 0x00 "SPIFLG,SPI Flag Register"
rbitfld.long 0x00 24. " BUFINITACTIVE ,Indicates the status of multi-buffer initialization process" "Completed,Not completed"
rbitfld.long 0x00 9. " TXINTFLG ,Transmitter-empty interrupt flag" "No interrupt,Interrupt"
eventfld.long 0x00 8. " RXINTFLG ,Receiver-full interrupt flag" "No interrupt,Interrupt"
textline " "
eventfld.long 0x00 6. " RXOVRNINTFLG ,Overrun interrupt enable" "Disabled,Enabled"
eventfld.long 0x00 4. " BITERRFLG ,Enables interrupt on bit error" "Disabled,Enabled"
eventfld.long 0x00 3. " DESYNCFLG ,Enables interrupt on desynchronized slave" "No interrupt,Interrupt"
textline " "
eventfld.long 0x00 2. " PARITYERRFLG ,Enables interrupt-on-parity-error" "No error,Error"
eventfld.long 0x00 1. " TIMEOUTFLG ,Enables interrupt on ENA signal time-out" "No interrupt,Interrupt"
eventfld.long 0x00 0. " DLENERRFLG ,Data length error interrupt enable" "No interrupt,Interrupt"
textline " "
width 12.
group.long 0x14++0x23
line.long 0x00 "SPIPC0,SPI Pin Control Register 0"
bitfld.long 0x00 31. " SOMIFUN[7] ,SPISOMI[7] pin function" "GIO,SPI"
bitfld.long 0x00 30. " [6] ,SPISOMI[6] pin function" "GIO,SPI"
bitfld.long 0x00 29. " [5] ,SPISOMI[5] pin function" "GIO,SPI"
bitfld.long 0x00 28. " [4] ,SPISOMI[4] pin function" "GIO,SPI"
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bitfld.long 0x00 27. " [3] ,SPISOMI[3] pin function" "GIO,SPI"
bitfld.long 0x00 26. " [2] ,SPISOMI[2] pin function" "GIO,SPI"
bitfld.long 0x00 25. " [1] ,SPISOMI[1] pin function" "GIO,SPI"
bitfld.long 0x00 24. " [0] ,SPISOMI[0] pin function (mirror of bit 11)" "GIO,SPI"
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bitfld.long 0x00 23. " SIMOFUN[7] ,SPISIMO[7] pin function" "GIO,SPI"
bitfld.long 0x00 22. " [6] ,SPISIMO[6] pin function" "GIO,SPI"
bitfld.long 0x00 21. " [5] ,SPISIMO[5] pin function" "GIO,SPI"
bitfld.long 0x00 20. " [4] ,SPISIMO[4] pin function" "GIO,SPI"
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bitfld.long 0x00 19. " [3] ,SPISIMO[3] pin function" "GIO,SPI"
bitfld.long 0x00 18. " [2] ,SPISIMO[2] pin function" "GIO,SPI"
bitfld.long 0x00 17. " [1] ,SPISIMO[1] pin function" "GIO,SPI"
bitfld.long 0x00 16. " [0] ,SPISIMO[0] pin function (mirror of bit 10)" "GIO,SPI"
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bitfld.long 0x00 11. " SOMIFUN[0] ,SPISOMI[0] pin function" "GIO,SPI"
bitfld.long 0x00 10. " SIMOFUN[0] ,SPISIMO[0] pin function" "GIO,SPI"
bitfld.long 0x00 9. " CLKFUN ,SPI clock function" "GIO,SPI"
bitfld.long 0x00 8. " ENAFUN ,SPIENA function" "GIO,SPI"
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bitfld.long 0x00 7. " SCSFUN[7] ,SPISCS7 function 7" "GIO,SPI"
bitfld.long 0x00 6. " [6] ,SPISCS6 function 6" "GIO,SPI"
bitfld.long 0x00 5. " [5] ,SPISCS5 function 5" "GIO,SPI"
bitfld.long 0x00 4. " [4] ,SPISCS4 function 4" "GIO,SPI"
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bitfld.long 0x00 3. " [3] ,SPISCS3 function 3" "GIO,SPI"
bitfld.long 0x00 2. " [2] ,SPISCS2 function 2" "GIO,SPI"
bitfld.long 0x00 1. " [1] ,SPISCS1 function 1" "GIO,SPI"
bitfld.long 0x00 0. " [0] ,SPISCS0 function 0" "GIO,SPI"
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line.long 0x04 "SPIPC1,SPI Pin Control Register 1"
bitfld.long 0x04 31. " SOMIDIR[7] ,SPISOMI[7] pin direction" "GIO,SPI"
bitfld.long 0x04 30. " [6] ,SPISOMI[6] pin direction" "GIO,SPI"
bitfld.long 0x04 29. " [5] ,SPISOMI[5] pin direction" "GIO,SPI"
bitfld.long 0x04 28. " [4] ,SPISOMI[4] pin direction" "GIO,SPI"
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bitfld.long 0x04 27. " [3] ,SPISOMI[3] pin direction" "GIO,SPI"
bitfld.long 0x04 26. " [2] ,SPISOMI[2] pin direction" "GIO,SPI"
bitfld.long 0x04 25. " [1] ,SPISOMI[1] pin direction" "GIO,SPI"
bitfld.long 0x04 24. " [0] ,SPISOMI[0] pin direction (mirror of bit 11)" "GIO,SPI"
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bitfld.long 0x04 23. " SIMODIR[7] ,SPISIMO[7] pin direction" "GIO,SPI"
bitfld.long 0x04 22. " [6] ,SPISIMO[6] pin direction" "GIO,SPI"
bitfld.long 0x04 21. " [5] ,SPISIMO[5] pin direction" "GIO,SPI"
bitfld.long 0x04 20. " [4] ,SPISIMO[4] pin direction" "GIO,SPI"
textline " "
bitfld.long 0x04 19. " [3] ,SPISIMO[3] pin direction" "GIO,SPI"
bitfld.long 0x04 18. " [2] ,SPISIMO[2] pin direction" "GIO,SPI"
bitfld.long 0x04 17. " [1] ,SPISIMO[1] pin direction" "GIO,SPI"
bitfld.long 0x04 16. " [0] ,SPISIMO[0] pin direction (mirror of bit 10)" "GIO,SPI"
textline " "
bitfld.long 0x04 11. " SOMIDIR[0] ,SPISOMI[0] pin direction" "GIO,SPI"
bitfld.long 0x04 10. " SIMODIR[0] ,SPISIMO[0] pin direction" "GIO,SPI"
bitfld.long 0x04 9. " CLKDIR ,SPI clock direction" "GIO,SPI"
bitfld.long 0x04 8. " ENADIR ,SPIENA direction" "GIO,SPI"
textline " "
textline " "
bitfld.long 0x04 7. " SCSDIR[7] ,SPISCS7 direction 7" "GIO,SPI"
bitfld.long 0x04 6. " [6] ,SPISCS6 direction 6" "GIO,SPI"
bitfld.long 0x04 5. " [5] ,SPISCS5 direction 5" "GIO,SPI"
bitfld.long 0x04 4. " [4] ,SPISCS4 direction 4" "GIO,SPI"
textline " "
bitfld.long 0x04 3. " [3] ,SPISCS3 direction 3" "GIO,SPI"
bitfld.long 0x04 2. " [2] ,SPISCS2 direction 2" "GIO,SPI"
bitfld.long 0x04 1. " [1] ,SPISCS1 direction 1" "GIO,SPI"
bitfld.long 0x04 0. " [0] ,SPISCS0 direction 0" "GIO,SPI"
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line.long 0x08 "SPIPC2,SPI Pin Control Register 2"
bitfld.long 0x08 31. " SOMIDIN[7] ,SPISOMI[7] data in" "0,1"
bitfld.long 0x08 30. " [6] ,SPISOMI[6] data in" "0,1"
bitfld.long 0x08 29. " [5] ,SPISOMI[5] data in" "0,1"
bitfld.long 0x08 28. " [4] ,SPISOMI[4] data in" "0,1"
bitfld.long 0x08 27. " [3] ,SPISOMI[3] data in" "0,1"
bitfld.long 0x08 26. " [2] ,SPISOMI[2] data in" "0,1"
bitfld.long 0x08 25. " [1] ,SPISOMI[1] data in" "0,1"
bitfld.long 0x08 24. " [0] ,SPISOMI[0] data in (mirror of bit 11)" "0,1"
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bitfld.long 0x08 23. " SIMODIN[7] ,SPISIMO[7] data in" "0,1"
bitfld.long 0x08 22. " [6] ,SPISIMO[6] data in" "0,1"
bitfld.long 0x08 21. " [5] ,SPISIMO[5] data in" "0,1"
bitfld.long 0x08 20. " [4] ,SPISIMO[4] data in" "0,1"
bitfld.long 0x08 19. " [3] ,SPISIMO[3] data in" "0,1"
bitfld.long 0x08 18. " [2] ,SPISIMO[2] data in" "0,1"
bitfld.long 0x08 17. " [1] ,SPISIMO[1] data in" "0,1"
bitfld.long 0x08 16. " [0] ,SPISIMO[0] data in (mirror of bit 10)" "0,1"
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bitfld.long 0x08 11. " SOMIDIN[0] ,SPISOMI[0] data in" "0,1"
bitfld.long 0x08 10. " SIMODIN[0] ,SPISIMO[0] data in" "0,1"
bitfld.long 0x08 9. " CLKDIN ,SPI clock data in" "0,1"
bitfld.long 0x08 8. " ENADIN ,SPIENA data in" "0,1"
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bitfld.long 0x08 7. " SCSDIN[7] ,SPISCS7 data in" "0,1"
bitfld.long 0x08 6. " [6] ,SPISCS6 data in" "0,1"
bitfld.long 0x08 5. " [5] ,SPISCS5 data in" "0,1"
bitfld.long 0x08 4. " [4] ,SPISCS4 data in" "0,1"
bitfld.long 0x08 3. " [3] ,SPISCS3 data in" "0,1"
bitfld.long 0x08 2. " [2] ,SPISCS2 data in" "0,1"
bitfld.long 0x08 1. " [1] ,SPISCS1 data in" "0,1"
bitfld.long 0x08 0. " [0] ,SPISCS0 direction 0" "0,1"
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line.long 0x0C "SPIPC3,SPI Pin Control Register 3"
bitfld.long 0x0C 31. " SOMIDOUT[7] ,SPISOMI[7] data out write" "0,1"
bitfld.long 0x0C 30. " [6] ,SPISOMI[6] data out write" "0,1"
bitfld.long 0x0C 29. " [5] ,SPISOMI[5] data out write" "0,1"
bitfld.long 0x0C 28. " [4] ,SPISOMI[4] data out write" "0,1"
bitfld.long 0x0C 27. " [3] ,SPISOMI[3] data out write" "0,1"
bitfld.long 0x0C 26. " [2] ,SPISOMI[2] data out write" "0,1"
bitfld.long 0x0C 25. " [1] ,SPISOMI[1] data out write" "0,1"
bitfld.long 0x0C 24. " [0] ,SPISOMI[0] data out write (mirror of bit 11)" "0,1"
textline " "
bitfld.long 0x0C 23. " SIMODOUT[7] ,SPISIMO[7] data out write" "0,1"
bitfld.long 0x0C 22. " [6] ,SPISIMO[6] data out write" "0,1"
bitfld.long 0x0C 21. " [5] ,SPISIMO[5] data out write" "0,1"
bitfld.long 0x0C 20. " [4] ,SPISIMO[4] data out write" "0,1"
bitfld.long 0x0C 19. " [3] ,SPISIMO[3] data out write" "0,1"
bitfld.long 0x0C 18. " [2] ,SPISIMO[2] data out write" "0,1"
bitfld.long 0x0C 17. " [1] ,SPISIMO[1] data out write" "0,1"
bitfld.long 0x0C 16. " [0] ,SPISIMO[0] data out write (mirror of bit 10)" "0,1"
textline " "
bitfld.long 0x0C 11. " SOMIDOUT[0] ,SPISOMI[0] data out write" "0,1"
bitfld.long 0x0C 10. " SIMODOUT[0] ,SPISIMO[0] data out write" "0,1"
bitfld.long 0x0C 9. " CLKDOUT ,SPI clock data out write" "0,1"
bitfld.long 0x0C 8. " ENADOUT ,SPIENA data out write" "0,1"
textline " "
textline " "
bitfld.long 0x0C 7. " SCSDOUT[7] ,SPISCS7 data out write" "0,1"
bitfld.long 0x0C 6. " [6] ,SPISCS6 data out write" "0,1"
bitfld.long 0x0C 5. " [5] ,SPISCS5 data out write" "0,1"
bitfld.long 0x0C 4. " [4] ,SPISCS4 data out write" "0,1"
bitfld.long 0x0C 3. " [3] ,SPISCS3 data out write" "0,1"
bitfld.long 0x0C 2. " [2] ,SPISCS2 data out write" "0,1"
bitfld.long 0x0C 1. " [1] ,SPISCS1 data out write" "0,1"
bitfld.long 0x0C 0. " [0] ,SPISCS0 data out write" "0,1"
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line.long 0x10 "SPIPC4,SPI Pin Control Register 4"
bitfld.long 0x10 31. " SOMISET[7] ,SPISOMI[7] data out set" "0,1"
bitfld.long 0x10 30. " [6] ,SPISOMI[6] data out set" "0,1"
bitfld.long 0x10 29. " [5] ,SPISOMI[5] data out set" "0,1"
bitfld.long 0x10 28. " [4] ,SPISOMI[4] data out set" "0,1"
bitfld.long 0x10 27. " [3] ,SPISOMI[3] data out set" "0,1"
bitfld.long 0x10 26. " [2] ,SPISOMI[2] data out set" "0,1"
bitfld.long 0x10 25. " [1] ,SPISOMI[1] data out set" "0,1"
bitfld.long 0x10 24. " [0] ,SPISOMI[0] data out set (mirror of bit 11)" "0,1"
textline " "
bitfld.long 0x10 23. " SIMOSET[7] ,SPISIMO[7] data out set" "0,1"
bitfld.long 0x10 22. " [6] ,SPISIMO[6] data out set" "0,1"
bitfld.long 0x10 21. " [5] ,SPISIMO[5] data out set" "0,1"
bitfld.long 0x10 20. " [4] ,SPISIMO[4] data out set" "0,1"
bitfld.long 0x10 19. " [3] ,SPISIMO[3] data out set" "0,1"
bitfld.long 0x10 18. " [2] ,SPISIMO[2] data out set" "0,1"
bitfld.long 0x10 17. " [1] ,SPISIMO[1] data out set" "0,1"
bitfld.long 0x10 16. " [0] ,SPISIMO[0] data out set (mirror of bit 10)" "0,1"
textline " "
bitfld.long 0x10 11. " SOMISET[0] ,SPISOMI[0] data out set" "0,1"
bitfld.long 0x10 10. " SIMOSET[0] ,SPISIMO[0] data out set" "0,1"
bitfld.long 0x10 9. " CLKSET ,SPI clock data out set" "0,1"
bitfld.long 0x10 8. " ENASET ,SPIENA data out set" "0,1"
textline " "
textline " "
bitfld.long 0x10 7. " SCSSET[7] ,SPISCS7 data out set" "0,1"
bitfld.long 0x10 6. " [6] ,SPISCS6 data out set" "0,1"
bitfld.long 0x10 5. " [5] ,SPISCS5 data out set" "0,1"
bitfld.long 0x10 4. " [4] ,SPISCS4 data out set" "0,1"
bitfld.long 0x10 3. " [3] ,SPISCS3 data out set" "0,1"
bitfld.long 0x10 2. " [2] ,SPISCS2 data out set" "0,1"
bitfld.long 0x10 1. " [1] ,SPISCS1 data out set" "0,1"
bitfld.long 0x10 0. " [0] ,SPISCS0 data out set" "0,1"
textline " "
line.long 0x14 "SPIPC5,SPI Pin Control Register 5"
bitfld.long 0x14 31. " SOMICLR[7] ,SPISOMI[7] data out clear" "0,1"
bitfld.long 0x14 30. " [6] ,SPISOMI[6] data out clear" "0,1"
bitfld.long 0x14 29. " [5] ,SPISOMI[5] data out clear" "0,1"
bitfld.long 0x14 28. " [4] ,SPISOMI[4] data out clear" "0,1"
bitfld.long 0x14 27. " [3] ,SPISOMI[3] data out clear" "0,1"
bitfld.long 0x14 26. " [2] ,SPISOMI[2] data out clear" "0,1"
bitfld.long 0x14 25. " [1] ,SPISOMI[1] data out clear" "0,1"
bitfld.long 0x14 24. " [0] ,SPISOMI[0] data out clear (mirror of bit 11)" "0,1"
textline " "
bitfld.long 0x14 23. " SIMOCLR[7] ,SPISIMO[7] data out clear" "0,1"
bitfld.long 0x14 22. " [6] ,SPISIMO[6] data out clear" "0,1"
bitfld.long 0x14 21. " [5] ,SPISIMO[5] data out clear" "0,1"
bitfld.long 0x14 20. " [4] ,SPISIMO[4] data out clear" "0,1"
bitfld.long 0x14 19. " [3] ,SPISIMO[3] data out clear" "0,1"
bitfld.long 0x14 18. " [2] ,SPISIMO[2] data out clear" "0,1"
bitfld.long 0x14 17. " [1] ,SPISIMO[1] data out clear" "0,1"
bitfld.long 0x14 16. " [0] ,SPISIMO[0] data out clear (mirror of bit 10)" "0,1"
textline " "
bitfld.long 0x14 11. " SOMICLR[0] ,SPISOMI[0] data out clear" "0,1"
bitfld.long 0x14 10. " SIMOCLR[0] ,SPISIMO[0] data out clear" "0,1"
bitfld.long 0x14 9. " CLKCLR ,SPI clock data out clear" "0,1"
bitfld.long 0x14 8. " ENACLR ,SPIENA data out clear" "0,1"
textline " "
textline " "
bitfld.long 0x14 7. " SCSCLR[7] ,SPISCS7 data out clear" "0,1"
bitfld.long 0x14 6. " [6] ,SPISCS6 data out clear" "0,1"
bitfld.long 0x14 5. " [5] ,SPISCS5 data out clear" "0,1"
bitfld.long 0x14 4. " [4] ,SPISCS4 data out clear" "0,1"
bitfld.long 0x14 3. " [3] ,SPISCS3 data out clear" "0,1"
bitfld.long 0x14 2. " [2] ,SPISCS2 data out clear" "0,1"
bitfld.long 0x14 1. " [1] ,SPISCS1 data out clear" "0,1"
bitfld.long 0x14 0. " [0] ,SPISCS0 data out clear" "0,1"
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line.long 0x18 "SPIPC6,SPI Pin Control Register 6"
bitfld.long 0x18 31. " SOMIPDR[7] ,SPISOMI[7] open drain enable" "Disabled,Enabled"
bitfld.long 0x18 30. " [6] ,SPISOMI[6] open drain enable" "Disabled,Enabled"
bitfld.long 0x18 29. " [5] ,SPISOMI[5] open drain enable" "Disabled,Enabled"
bitfld.long 0x18 28. " [4] ,SPISOMI[4] open drain enable" "Disabled,Enabled"
textline " "
bitfld.long 0x18 27. " [3] ,SPISOMI[3] open drain enable" "Disabled,Enabled"
bitfld.long 0x18 26. " [2] ,SPISOMI[2] open drain enable" "Disabled,Enabled"
bitfld.long 0x18 25. " [1] ,SPISOMI[1] open drain enable" "Disabled,Enabled"
bitfld.long 0x18 24. " [0] ,SPISOMI[0] open drain enable (mirror of bit 11)" "Disabled,Enabled"
textline " "
bitfld.long 0x18 23. " SIMOPDR[7] ,SPISIMO[7] open drain enable" "Disabled,Enabled"
bitfld.long 0x18 22. " [6] ,SPISIMO[6] open drain enable" "Disabled,Enabled"
bitfld.long 0x18 21. " [5] ,SPISIMO[5] open drain enable" "Disabled,Enabled"
bitfld.long 0x18 20. " [4] ,SPISIMO[4] open drain enable" "Disabled,Enabled"
textline " "
bitfld.long 0x18 19. " [3] ,SPISIMO[3] open drain enable" "Disabled,Enabled"
bitfld.long 0x18 18. " [2] ,SPISIMO[2] open drain enable" "Disabled,Enabled"
bitfld.long 0x18 17. " [1] ,SPISIMO[1] open drain enable" "Disabled,Enabled"
bitfld.long 0x18 16. " [0] ,SPISIMO[0] open drain enable (mirror of bit 10)" "Disabled,Enabled"
textline " "
bitfld.long 0x18 11. " SOMIPDR[0] ,SPISOMI[0] open drain enable" "Disabled,Enabled"
bitfld.long 0x18 10. " SIMOPDR[0] ,SPISIMO[0] open drain enable" "Disabled,Enabled"
bitfld.long 0x18 9. " CLKPDR ,SPI clock open drain enable" "Disabled,Enabled"
bitfld.long 0x18 8. " ENAPDR ,SPIENA open drain enable" "Disabled,Enabled"
textline " "
textline " "
bitfld.long 0x18 7. " SCSPDR[7] ,SPISCS7 open drain enable" "Disabled,Enabled"
bitfld.long 0x18 6. " [6] ,SPISCS6 open drain enable" "Disabled,Enabled"
bitfld.long 0x18 5. " [5] ,SPISCS5 open drain enable" "Disabled,Enabled"
bitfld.long 0x18 4. " [4] ,SPISCS4 open drain enable" "Disabled,Enabled"
textline " "
bitfld.long 0x18 3. " [3] ,SPISCS3 open drain enable" "Disabled,Enabled"
bitfld.long 0x18 2. " [2] ,SPISCS2 open drain enable" "Disabled,Enabled"
bitfld.long 0x18 1. " [1] ,SPISCS1 open drain enable" "Disabled,Enabled"
bitfld.long 0x18 0. " [0] ,SPISCS0 open drain enable" "Disabled,Enabled"
textline " "
line.long 0x1C "SPIPC7,SPI Pin Control Register 7"
bitfld.long 0x1C 31. " SOMIPDIS[7] ,SPISOMI[7] pull control enable/disable" "No,Yes"
bitfld.long 0x1C 30. " [6] ,SPISOMI[6] pull control enable/disable" "No,Yes"
bitfld.long 0x1C 29. " [5] ,SPISOMI[5] pull control enable/disable" "No,Yes"
bitfld.long 0x1C 28. " [4] ,SPISOMI[4] pull control enable/disable" "No,Yes"
textline " "
bitfld.long 0x1C 27. " [3] ,SPISOMI[3] pull control enable/disable" "No,Yes"
bitfld.long 0x1C 26. " [2] ,SPISOMI[2] pull control enable/disable" "No,Yes"
bitfld.long 0x1C 25. " [1] ,SPISOMI[1] pull control enable/disable" "No,Yes"
bitfld.long 0x1C 24. " [0] ,SPISOMI[0] pull control enable/disable (mirror of bit 11)" "No,Yes"
textline " "
bitfld.long 0x1C 23. " SIMOPDIS[7] ,SPISIMO[7] pull control enable/disable" "No,Yes"
bitfld.long 0x1C 22. " [6] ,SPISIMO[6] pull control enable/disable" "No,Yes"
bitfld.long 0x1C 21. " [5] ,SPISIMO[5] pull control enable/disable" "No,Yes"
bitfld.long 0x1C 20. " [4] ,SPISIMO[4] pull control enable/disable" "No,Yes"
textline " "
bitfld.long 0x1C 19. " [3] ,SPISIMO[3] pull control enable/disable" "No,Yes"
bitfld.long 0x1C 18. " [2] ,SPISIMO[2] pull control enable/disable" "No,Yes"
bitfld.long 0x1C 17. " [1] ,SPISIMO[1] pull control enable/disable" "No,Yes"
bitfld.long 0x1C 16. " [0] ,SPISIMO[0] pull control enable/disable (mirror of bit 10)" "No,Yes"
textline " "
bitfld.long 0x1C 11. " SOMIPDIS[0] ,SPISOMI[0] pull control enable/disable" "No,Yes"
bitfld.long 0x1C 10. " SIMOPDIS[0] ,SPISIMO[0] pull control enable/disable" "No,Yes"
bitfld.long 0x1C 9. " CLKPDIS ,SPI clock pull control enable/disable" "No,Yes"
bitfld.long 0x1C 8. " ENAPDIS ,SPIENA pull control enable/disable" "No,Yes"
textline " "
textline " "
bitfld.long 0x1C 7. " SCSPDIS[7] ,SPISCS7 pull control enable/disable" "No,Yes"
bitfld.long 0x1C 6. " [6] ,SPISCS6 pull control enable/disable" "No,Yes"
bitfld.long 0x1C 5. " [5] ,SPISCS5 pull control enable/disable" "No,Yes"
bitfld.long 0x1C 4. " [4] ,SPISCS4 pull control enable/disable" "No,Yes"
textline " "
bitfld.long 0x1C 3. " [3] ,SPISCS3 pull control enable/disable" "No,Yes"
bitfld.long 0x1C 2. " [2] ,SPISCS2 pull control enable/disable" "No,Yes"
bitfld.long 0x1C 1. " [1] ,SPISCS1 pull control enable/disable" "No,Yes"
bitfld.long 0x1C 0. " [0] ,SPISCS0 pull control enable/disable" "No,Yes"
textline " "
line.long 0x20 "SPIPC8,SPI Pin Control Register 8"
bitfld.long 0x20 31. " SOMIPSEL[7] ,SPISOMI[7] pull select" "Pull down,Pull up"
bitfld.long 0x20 30. " [6] ,SPISOMI[6] pull select" "Pull down,Pull up"
bitfld.long 0x20 29. " [5] ,SPISOMI[5] pull select" "Pull down,Pull up"
bitfld.long 0x20 28. " [4] ,SPISOMI[4] pull select" "Pull down,Pull up"
textline " "
bitfld.long 0x20 27. " [3] ,SPISOMI[3] pull select" "Pull down,Pull up"
bitfld.long 0x20 26. " [2] ,SPISOMI[2] pull select" "Pull down,Pull up"
bitfld.long 0x20 25. " [1] ,SPISOMI[1] pull select" "Pull down,Pull up"
bitfld.long 0x20 24. " [0] ,SPISOMI[0] pull select (mirror of bit 11)" "Pull down,Pull up"
textline " "
bitfld.long 0x20 23. " SIMOPSEL[7] ,SPISIMO[7] pull select" "Pull down,Pull up"
bitfld.long 0x20 22. " [6] ,SPISIMO[6] pull select" "Pull down,Pull up"
bitfld.long 0x20 21. " [5] ,SPISIMO[5] pull select" "Pull down,Pull up"
bitfld.long 0x20 20. " [4] ,SPISIMO[4] pull select" "Pull down,Pull up"
textline " "
bitfld.long 0x20 19. " [3] ,SPISIMO[3] pull select" "Pull down,Pull up"
bitfld.long 0x20 18. " [2] ,SPISIMO[2] pull select" "Pull down,Pull up"
bitfld.long 0x20 17. " [1] ,SPISIMO[1] pull select" "Pull down,Pull up"
bitfld.long 0x20 16. " [0] ,SPISIMO[0] pull select (mirror of bit 10)" "Pull down,Pull up"
textline " "
bitfld.long 0x20 11. " SOMIPSEL[0] ,SPISOMI[0] pull select" "Pull down,Pull up"
bitfld.long 0x20 10. " SIMOPSEL[0] ,SPISIMO[0] pull select" "Pull down,Pull up"
bitfld.long 0x20 9. " CLKPSEL ,SPI clock pull select" "Pull down,Pull up"
bitfld.long 0x20 8. " ENAPSEL ,SPIENA pull select" "Pull down,Pull up"
textline " "
textline " "
bitfld.long 0x20 7. " SCSPSEL[7] ,SPISCS7 pull select" "Pull down,Pull up"
bitfld.long 0x20 6. " [6] ,SPISCS6 pull select" "Pull down,Pull up"
bitfld.long 0x20 5. " [5] ,SPISCS5 pull select" "Pull down,Pull up"
bitfld.long 0x20 4. " [4] ,SPISCS4 pull select" "Pull down,Pull up"
textline " "
bitfld.long 0x20 3. " [3] ,SPISCS3 pull select" "Pull down,Pull up"
bitfld.long 0x20 2. " [2] ,SPISCS2 pull select" "Pull down,Pull up"
bitfld.long 0x20 1. " [1] ,SPISCS1 pull select" "Pull down,Pull up"
bitfld.long 0x20 0. " [0] ,SPISCS0 pull select" "Pull down,Pull up"
textline " "
group.long 0x38++0x03
line.long 0x00 "SPIDAT0,SPI Transmit Data Register 0"
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,SPI transmit data"
if (((d.l(ad:0xFFF7F400+0x4))&0x3)==0x0)
group.long 0x3C++0x03
line.long 0x00 "SPIDAT1,Transmit Data Register 1"
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Inactive,Active"
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "No delay,After transaction"
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
textline " "
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
else
group.long 0x3C++0x03
line.long 0x00 "SPIDAT1,Transmit Data Register 1"
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Inactive,Active"
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
textline " "
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
endif
width 17.
hgroup.long 0x40++0x03
hide.long 0x00 "SPIBUF,SPI Receive Buffer Register"
in
rgroup.long 0x44++0x03
line.long 0x00 "SPIEMU,SPI Emulation Register"
hexmask.long.word 0x00 0.--15. 1. " EMU_RXDATA ,SPI receive data"
if (((d.l(ad:0xFFF7F400+0x4))&0x1)==0x1)
rgroup.long 0x48++0x03
line.long 0x00 "SPIDELAY,SPI Delay Register"
hexmask.long.byte 0x00 24.--31. 1. " C2TDELAY ,Chip-select-active to transmit-start delay"
hexmask.long.byte 0x00 16.--23. 1. " T2CDELAY ,Transmit-end-to-chip-select-inactive-delay"
hexmask.long.byte 0x00 8.--15. 1. " T2EDELAY ,Transmit-data-finished to ENA-pin-inactive time-out"
textline " "
hexmask.long.byte 0x00 0.--7. 1. " C2EDELAY ,Chip-select-active to ENA-signal-active time-out"
group.long 0x4C++0x03
line.long 0x00 "SPIDEF,SPI Default Chip Select Register"
bitfld.long 0x00 7. " CSDEF[7] ,Chip select default pattern 7" "0,1"
bitfld.long 0x00 6. " [6] ,Chip select default pattern 6" "0,1"
bitfld.long 0x00 5. " [5] ,Chip select default pattern 5" "0,1"
textline " "
bitfld.long 0x00 4. " [4] ,Chip select default pattern 4" "0,1"
bitfld.long 0x00 3. " [3] ,Chip select default pattern 3" "0,1"
bitfld.long 0x00 2. " [2] ,Chip select default pattern 2" "0,1"
textline " "
bitfld.long 0x00 1. " [1] ,Chip select default pattern 1" "0,1"
bitfld.long 0x00 0. " [0] ,Chip select default pattern 0" "0,1"
endif
if (((d.l(ad:0xFFF7F400+0x4))&0x3)==0x0)
group.long 0x50++0x0F
line.long 0x0 "SPIFMT0,SPI Data Format Register 0"
sif cpuis("TMS570LC4357")
hexmask.long.byte 0x0 24.--31. 1. " WDELAY ,Delay in between transmissions for data format 0"
else
bitfld.long 0x0 24.--29. " WDELAY ,Delay in between transmissions for data format 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
endif
bitfld.long 0x0 23. " PARPOL ,Parity polarity: even or odd" "Even,Odd"
textline " "
bitfld.long 0x0 22. " PARITYENA ,Parity enable for data format 0" "Disabled,Enabled"
bitfld.long 0x0 20. " SHIFTDIR ,Shift direction for data format $" "MSB,LSB"
textline " "
sif cpuis("TMS570LC4357")
bitfld.long 0x0 19. " HDUPLEX_ENA0 ,Half Duplex transfer mode enable for Data Format 0" "Normal,TX"
endif
textline " "
bitfld.long 0x0 18. " DISCSTIMERS ,Disable chip-select timers for this format" "No,Yes"
textline " "
bitfld.long 0x0 17. " POLARITY ,SPI data format 0 clock polarity" "Low,High"
bitfld.long 0x0 16. " PHASE ,SPI data format 0 clock delay" "Disabled,Enabled"
textline " "
hexmask.long.byte 0x0 8.--15. 1. " PRESCALE ,SPI data format 0 prescaler"
bitfld.long 0x0 0.--4. " CHARLEN ,SPI data format 0 data-word length" ",,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,?..."
line.long 0x4 "SPIFMT1,SPI Data Format Register 1"
sif cpuis("TMS570LC4357")
hexmask.long.byte 0x4 24.--31. 1. " WDELAY ,Delay in between transmissions for data format 1"
else
bitfld.long 0x4 24.--29. " WDELAY ,Delay in between transmissions for data format 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
endif
bitfld.long 0x4 23. " PARPOL ,Parity polarity: even or odd" "Even,Odd"
textline " "
bitfld.long 0x4 22. " PARITYENA ,Parity enable for data format 1" "Disabled,Enabled"
bitfld.long 0x4 20. " SHIFTDIR ,Shift direction for data format $" "MSB,LSB"
textline " "
sif cpuis("TMS570LC4357")
bitfld.long 0x4 19. " HDUPLEX_ENA1 ,Half Duplex transfer mode enable for Data Format 1" "Normal,TX"
endif
textline " "
bitfld.long 0x4 18. " DISCSTIMERS ,Disable chip-select timers for this format" "No,Yes"
textline " "
bitfld.long 0x4 17. " POLARITY ,SPI data format 1 clock polarity" "Low,High"
bitfld.long 0x4 16. " PHASE ,SPI data format 1 clock delay" "Disabled,Enabled"
textline " "
hexmask.long.byte 0x4 8.--15. 1. " PRESCALE ,SPI data format 1 prescaler"
bitfld.long 0x4 0.--4. " CHARLEN ,SPI data format 1 data-word length" ",,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,?..."
line.long 0x8 "SPIFMT2,SPI Data Format Register 2"
sif cpuis("TMS570LC4357")
hexmask.long.byte 0x8 24.--31. 1. " WDELAY ,Delay in between transmissions for data format 2"
else
bitfld.long 0x8 24.--29. " WDELAY ,Delay in between transmissions for data format 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
endif
bitfld.long 0x8 23. " PARPOL ,Parity polarity: even or odd" "Even,Odd"
textline " "
bitfld.long 0x8 22. " PARITYENA ,Parity enable for data format 2" "Disabled,Enabled"
bitfld.long 0x8 20. " SHIFTDIR ,Shift direction for data format $" "MSB,LSB"
textline " "
sif cpuis("TMS570LC4357")
bitfld.long 0x8 19. " HDUPLEX_ENA2 ,Half Duplex transfer mode enable for Data Format 2" "Normal,TX"
endif
textline " "
bitfld.long 0x8 18. " DISCSTIMERS ,Disable chip-select timers for this format" "No,Yes"
textline " "
bitfld.long 0x8 17. " POLARITY ,SPI data format 2 clock polarity" "Low,High"
bitfld.long 0x8 16. " PHASE ,SPI data format 2 clock delay" "Disabled,Enabled"
textline " "
hexmask.long.byte 0x8 8.--15. 1. " PRESCALE ,SPI data format 2 prescaler"
bitfld.long 0x8 0.--4. " CHARLEN ,SPI data format 2 data-word length" ",,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,?..."
line.long 0xC "SPIFMT3,SPI Data Format Register 3"
sif cpuis("TMS570LC4357")
hexmask.long.byte 0xC 24.--31. 1. " WDELAY ,Delay in between transmissions for data format 3"
else
bitfld.long 0xC 24.--29. " WDELAY ,Delay in between transmissions for data format 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
endif
bitfld.long 0xC 23. " PARPOL ,Parity polarity: even or odd" "Even,Odd"
textline " "
bitfld.long 0xC 22. " PARITYENA ,Parity enable for data format 3" "Disabled,Enabled"
bitfld.long 0xC 20. " SHIFTDIR ,Shift direction for data format $" "MSB,LSB"
textline " "
sif cpuis("TMS570LC4357")
bitfld.long 0xC 19. " HDUPLEX_ENA3 ,Half Duplex transfer mode enable for Data Format 3" "Normal,TX"
endif
textline " "
bitfld.long 0xC 18. " DISCSTIMERS ,Disable chip-select timers for this format" "No,Yes"
textline " "
bitfld.long 0xC 17. " POLARITY ,SPI data format 3 clock polarity" "Low,High"
bitfld.long 0xC 16. " PHASE ,SPI data format 3 clock delay" "Disabled,Enabled"
textline " "
hexmask.long.byte 0xC 8.--15. 1. " PRESCALE ,SPI data format 3 prescaler"
bitfld.long 0xC 0.--4. " CHARLEN ,SPI data format 3 data-word length" ",,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,?..."
else
group.long 0x50++0x0F
line.long 0x0 "SPIFMT0,SPI Data Format Register 0"
sif cpuis("TMS570LC4357")
hexmask.long.byte 0x0 24.--31. 1. " WDELAY ,Delay in between transmissions for data format 0"
else
bitfld.long 0x0 24.--29. " WDELAY ,Delay in between transmissions for data format 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
endif
bitfld.long 0x0 23. " PARPOL ,Parity polarity: even or odd" "Even,Odd"
textline " "
bitfld.long 0x0 22. " PARITYENA ,Parity enable for data format 0" "Disabled,Enabled"
bitfld.long 0x0 21. " WAITENA ,The master waits for the ENA signal from slave for data format 0" "Disabled,Enabled"
textline " "
bitfld.long 0x0 20. " SHIFTDIR ,Shift direction for data format $" "MSB,LSB"
sif cpuis("TMS570LC4357")
bitfld.long 0x0 19. " HDUPLEX_ENA0 ,Half Duplex transfer mode enable for Data Format 0" "Normal,RX"
endif
textline " "
bitfld.long 0x0 18. " DISCSTIMERS ,Disable chip-select timers for this format" "No,Yes"
textline " "
bitfld.long 0x0 17. " POLARITY ,SPI data format 0 clock polarity" "Low,High"
bitfld.long 0x0 16. " PHASE ,SPI data format 0 clock delay" "Disabled,Enabled"
textline " "
hexmask.long.byte 0x0 8.--15. 1. " PRESCALE ,SPI data format 0 prescaler"
bitfld.long 0x0 0.--4. " CHARLEN ,SPI data format 0 data-word length" ",,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,?..."
line.long 0x4 "SPIFMT1,SPI Data Format Register 1"
sif cpuis("TMS570LC4357")
hexmask.long.byte 0x4 24.--31. 1. " WDELAY ,Delay in between transmissions for data format 1"
else
bitfld.long 0x4 24.--29. " WDELAY ,Delay in between transmissions for data format 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
endif
bitfld.long 0x4 23. " PARPOL ,Parity polarity: even or odd" "Even,Odd"
textline " "
bitfld.long 0x4 22. " PARITYENA ,Parity enable for data format 1" "Disabled,Enabled"
bitfld.long 0x4 21. " WAITENA ,The master waits for the ENA signal from slave for data format 1" "Disabled,Enabled"
textline " "
bitfld.long 0x4 20. " SHIFTDIR ,Shift direction for data format $" "MSB,LSB"
sif cpuis("TMS570LC4357")
bitfld.long 0x4 19. " HDUPLEX_ENA1 ,Half Duplex transfer mode enable for Data Format 1" "Normal,RX"
endif
textline " "
bitfld.long 0x4 18. " DISCSTIMERS ,Disable chip-select timers for this format" "No,Yes"
textline " "
bitfld.long 0x4 17. " POLARITY ,SPI data format 1 clock polarity" "Low,High"
bitfld.long 0x4 16. " PHASE ,SPI data format 1 clock delay" "Disabled,Enabled"
textline " "
hexmask.long.byte 0x4 8.--15. 1. " PRESCALE ,SPI data format 1 prescaler"
bitfld.long 0x4 0.--4. " CHARLEN ,SPI data format 1 data-word length" ",,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,?..."
line.long 0x8 "SPIFMT2,SPI Data Format Register 2"
sif cpuis("TMS570LC4357")
hexmask.long.byte 0x8 24.--31. 1. " WDELAY ,Delay in between transmissions for data format 2"
else
bitfld.long 0x8 24.--29. " WDELAY ,Delay in between transmissions for data format 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
endif
bitfld.long 0x8 23. " PARPOL ,Parity polarity: even or odd" "Even,Odd"
textline " "
bitfld.long 0x8 22. " PARITYENA ,Parity enable for data format 2" "Disabled,Enabled"
bitfld.long 0x8 21. " WAITENA ,The master waits for the ENA signal from slave for data format 2" "Disabled,Enabled"
textline " "
bitfld.long 0x8 20. " SHIFTDIR ,Shift direction for data format $" "MSB,LSB"
sif cpuis("TMS570LC4357")
bitfld.long 0x8 19. " HDUPLEX_ENA2 ,Half Duplex transfer mode enable for Data Format 2" "Normal,RX"
endif
textline " "
bitfld.long 0x8 18. " DISCSTIMERS ,Disable chip-select timers for this format" "No,Yes"
textline " "
bitfld.long 0x8 17. " POLARITY ,SPI data format 2 clock polarity" "Low,High"
bitfld.long 0x8 16. " PHASE ,SPI data format 2 clock delay" "Disabled,Enabled"
textline " "
hexmask.long.byte 0x8 8.--15. 1. " PRESCALE ,SPI data format 2 prescaler"
bitfld.long 0x8 0.--4. " CHARLEN ,SPI data format 2 data-word length" ",,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,?..."
line.long 0xC "SPIFMT3,SPI Data Format Register 3"
sif cpuis("TMS570LC4357")
hexmask.long.byte 0xC 24.--31. 1. " WDELAY ,Delay in between transmissions for data format 3"
else
bitfld.long 0xC 24.--29. " WDELAY ,Delay in between transmissions for data format 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
endif
bitfld.long 0xC 23. " PARPOL ,Parity polarity: even or odd" "Even,Odd"
textline " "
bitfld.long 0xC 22. " PARITYENA ,Parity enable for data format 3" "Disabled,Enabled"
bitfld.long 0xC 21. " WAITENA ,The master waits for the ENA signal from slave for data format 3" "Disabled,Enabled"
textline " "
bitfld.long 0xC 20. " SHIFTDIR ,Shift direction for data format $" "MSB,LSB"
sif cpuis("TMS570LC4357")
bitfld.long 0xC 19. " HDUPLEX_ENA3 ,Half Duplex transfer mode enable for Data Format 3" "Normal,RX"
endif
textline " "
bitfld.long 0xC 18. " DISCSTIMERS ,Disable chip-select timers for this format" "No,Yes"
textline " "
bitfld.long 0xC 17. " POLARITY ,SPI data format 3 clock polarity" "Low,High"
bitfld.long 0xC 16. " PHASE ,SPI data format 3 clock delay" "Disabled,Enabled"
textline " "
hexmask.long.byte 0xC 8.--15. 1. " PRESCALE ,SPI data format 3 prescaler"
bitfld.long 0xC 0.--4. " CHARLEN ,SPI data format 3 data-word length" ",,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,?..."
endif
hgroup.long 0x60++0x03
hide.long 0x00 "TGINTVECT0,SPI Interrupt Vector Register 0 / MibSPI Transfer Group Interrupt Vector Register 0"
in
hgroup.long 0x64++0x03
hide.long 0x00 "TGINTVECT1,SPI Interrupt Vector Register 1 / MibSPI Transfer Group Interrupt Vector Register 1"
in
group.long 0x6C++0x07
line.long 0x00 "SPIPMCTRL,SPI Parallel/Modulo Mode Control Register"
bitfld.long 0x00 29. " MODCLKPOL3 ,Modulo mode SPICLK polarity" "Normal,Inverted"
bitfld.long 0x00 26.--28. " MMODE3 ,SPI/MibSPI data lines" "1,2,3,4,5,6,?..."
bitfld.long 0x00 24.--25. " PMODE3 ,Parallel mode data lines" "1,2,4,8"
textline " "
bitfld.long 0x00 21. " MODCLKPOL2 ,Modulo mode SPICLK polarity" "Normal,Inverted"
bitfld.long 0x00 18.--20. " MMODE2 ,SPI/MibSPI data lines" "1,2,3,4,5,6,?..."
bitfld.long 0x00 16.--17. " PMODE2 ,Parallel mode data lines" "1,2,4,8"
textline " "
bitfld.long 0x00 13. " MODCLKPOL1 ,Modulo mode SPICLK polarity" "Normal,Inverted"
bitfld.long 0x00 10.--12. " MMODE1 ,SPI/MibSPI data lines" "1,2,3,4,5,6,?..."
bitfld.long 0x00 8.--9. " PMODE1 ,Parallel mode data lines" "1,2,4,8"
textline " "
bitfld.long 0x00 5. " MODCLKPOL0 ,Modulo mode SPICLK polarity" "Normal,Inverted"
bitfld.long 0x00 2.--4. " MMODE0 ,SPI/MibSPI data lines" "1,2,3,4,5,6,?..."
bitfld.long 0x00 0.--1. " PMODE0 ,Parallel mode data lines" "1,2,4,8"
line.long 0x04 "MIBSPIE,MibSPI Enable Register"
bitfld.long 0x04 16. " RXRAMACCESS ,Receive-RAM access control" "Not writable,Accessible"
bitfld.long 0x04 0. " MIBSPIENA ,Multi-buffer mode enable" "Disabled,Enabled"
textline " "
width 17.
group.long 0x74++0x0F
line.long 0x00 "TGITENST,MibSPI Transfer Group Interrupt Enable Set Register"
bitfld.long 0x00 31. " SETINTENRDY[15] ,TG interrupt set (enable) when transfer finished" "Disabled,Enabled"
bitfld.long 0x00 30. " [14] ,TG interrupt set (enable) when transfer finished" "Disabled,Enabled"
bitfld.long 0x00 29. " [13] ,TG interrupt set (enable) when transfer finished" "Disabled,Enabled"
textline " "
bitfld.long 0x00 28. " [12] ,TG interrupt set (enable) when transfer finished" "Disabled,Enabled"
bitfld.long 0x00 27. " [11] ,TG interrupt set (enable) when transfer finished" "Disabled,Enabled"
bitfld.long 0x00 26. " [10] ,TG interrupt set (enable) when transfer finished" "Disabled,Enabled"
textline " "
bitfld.long 0x00 25. " [9] ,TG interrupt set (enable) when transfer finished" "Disabled,Enabled"
bitfld.long 0x00 24. " [8] ,TG interrupt set (enable) when transfer finished" "Disabled,Enabled"
bitfld.long 0x00 23. " [7] ,TG interrupt set (enable) when transfer finished" "Disabled,Enabled"
textline " "
bitfld.long 0x00 22. " [6] ,TG interrupt set (enable) when transfer finished" "Disabled,Enabled"
bitfld.long 0x00 21. " [5] ,TG interrupt set (enable) when transfer finished" "Disabled,Enabled"
bitfld.long 0x00 20. " [4] ,TG interrupt set (enable) when transfer finished" "Disabled,Enabled"
textline " "
bitfld.long 0x00 19. " [3] ,TG interrupt set (enable) when transfer finished" "Disabled,Enabled"
bitfld.long 0x00 18. " [2] ,TG interrupt set (enable) when transfer finished" "Disabled,Enabled"
bitfld.long 0x00 17. " [1] ,TG interrupt set (enable) when transfer finished" "Disabled,Enabled"
textline " "
bitfld.long 0x00 16. " [0] ,TG interrupt set (enable) when transfer finished" "Disabled,Enabled"
textline " "
bitfld.long 0x00 15. " SETINTENSUS[15] ,TG interrupt set (enabled) when transfer suspended" "Disabled,Enabled"
bitfld.long 0x00 14. " [14] ,TG interrupt set (enabled) when transfer suspended" "Disabled,Enabled"
bitfld.long 0x00 13. " [13] ,TG interrupt set (enabled) when transfer suspended" "Disabled,Enabled"
textline " "
bitfld.long 0x00 12. " [12] ,TG interrupt set (enabled) when transfer suspended" "Disabled,Enabled"
bitfld.long 0x00 11. " [11] ,TG interrupt set (enabled) when transfer suspended" "Disabled,Enabled"
bitfld.long 0x00 10. " [10] ,TG interrupt set (enabled) when transfer suspended" "Disabled,Enabled"
textline " "
bitfld.long 0x00 9. " [9] ,TG interrupt set (enabled) when transfer suspended" "Disabled,Enabled"
bitfld.long 0x00 8. " [8] ,TG interrupt set (enabled) when transfer suspended" "Disabled,Enabled"
bitfld.long 0x00 7. " [7] ,TG interrupt set (enabled) when transfer suspended" "Disabled,Enabled"
textline " "
bitfld.long 0x00 6. " [6] ,TG interrupt set (enabled) when transfer suspended" "Disabled,Enabled"
bitfld.long 0x00 5. " [5] ,TG interrupt set (enabled) when transfer suspended" "Disabled,Enabled"
bitfld.long 0x00 4. " [4] ,TG interrupt set (enabled) when transfer suspended" "Disabled,Enabled"
textline " "
bitfld.long 0x00 3. " [3] ,TG interrupt set (enabled) when transfer suspended" "Disabled,Enabled"
bitfld.long 0x00 2. " [2] ,TG interrupt set (enabled) when transfer suspended" "Disabled,Enabled"
bitfld.long 0x00 1. " [1] ,TG interrupt set (enabled) when transfer suspended" "Disabled,Enabled"
textline " "
bitfld.long 0x00 0. " [0] ,TG interrupt set (enabled) when transfer suspended" "Disabled,Enabled"
line.long 0x04 "TGITENCR,MibSPI Transfer Group Interrupt Enable Clear Register"
bitfld.long 0x04 31. " CLRINTENRDY[15] ,TG interrupt clear (disabled) when transfer finished" "Disabled,Enabled"
bitfld.long 0x04 30. " [14] ,TG interrupt clear (disabled) when transfer finished" "Disabled,Enabled"
bitfld.long 0x04 29. " [13] ,TG interrupt clear (disabled) when transfer finished" "Disabled,Enabled"
textline " "
bitfld.long 0x04 28. " [12] ,TG interrupt clear (disabled) when transfer finished" "Disabled,Enabled"
bitfld.long 0x04 27. " [11] ,TG interrupt clear (disabled) when transfer finished" "Disabled,Enabled"
bitfld.long 0x04 26. " [10] ,TG interrupt clear (disabled) when transfer finished" "Disabled,Enabled"
textline " "
bitfld.long 0x04 25. " [9] ,TG interrupt clear (disabled) when transfer finished" "Disabled,Enabled"
bitfld.long 0x04 24. " [8] ,TG interrupt clear (disabled) when transfer finished" "Disabled,Enabled"
bitfld.long 0x04 23. " [7] ,TG interrupt clear (disabled) when transfer finished" "Disabled,Enabled"
textline " "
bitfld.long 0x04 22. " [6] ,TG interrupt clear (disabled) when transfer finished" "Disabled,Enabled"
bitfld.long 0x04 21. " [5] ,TG interrupt clear (disabled) when transfer finished" "Disabled,Enabled"
bitfld.long 0x04 20. " [4] ,TG interrupt clear (disabled) when transfer finished" "Disabled,Enabled"
textline " "
bitfld.long 0x04 19. " [3] ,TG interrupt clear (disabled) when transfer finished" "Disabled,Enabled"
bitfld.long 0x04 18. " [2] ,TG interrupt clear (disabled) when transfer finished" "Disabled,Enabled"
bitfld.long 0x04 17. " [1] ,TG interrupt clear (disabled) when transfer finished" "Disabled,Enabled"
textline " "
bitfld.long 0x04 16. " [0] ,TG interrupt clear (disabled) when transfer finished" "Disabled,Enabled"
textline " "
bitfld.long 0x04 15. " CLRINTENSUS[15] ,TG interrupt clear (disabled) when transfer suspended" "Disabled,Enabled"
bitfld.long 0x04 14. " [14] ,TG interrupt clear (disabled) when transfer suspended" "Disabled,Enabled"
bitfld.long 0x04 13. " [13] ,TG interrupt clear (disabled) when transfer suspended" "Disabled,Enabled"
textline " "
bitfld.long 0x04 12. " [12] ,TG interrupt clear (disabled) when transfer suspended" "Disabled,Enabled"
bitfld.long 0x04 11. " [11] ,TG interrupt clear (disabled) when transfer suspended" "Disabled,Enabled"
bitfld.long 0x04 10. " [10] ,TG interrupt clear (disabled) when transfer suspended" "Disabled,Enabled"
textline " "
bitfld.long 0x04 9. " [9] ,TG interrupt clear (disabled) when transfer suspended" "Disabled,Enabled"
bitfld.long 0x04 8. " [8] ,TG interrupt clear (disabled) when transfer suspended" "Disabled,Enabled"
bitfld.long 0x04 7. " [7] ,TG interrupt clear (disabled) when transfer suspended" "Disabled,Enabled"
textline " "
bitfld.long 0x04 6. " [6] ,TG interrupt clear (disabled) when transfer suspended" "Disabled,Enabled"
bitfld.long 0x04 5. " [5] ,TG interrupt clear (disabled) when transfer suspended" "Disabled,Enabled"
bitfld.long 0x04 4. " [4] ,TG interrupt clear (disabled) when transfer suspended" "Disabled,Enabled"
textline " "
bitfld.long 0x04 3. " [3] ,TG interrupt clear (disabled) when transfer suspended" "Disabled,Enabled"
bitfld.long 0x04 2. " [2] ,TG interrupt clear (disabled) when transfer suspended" "Disabled,Enabled"
bitfld.long 0x04 1. " [1] ,TG interrupt clear (disabled) when transfer suspended" "Disabled,Enabled"
textline " "
bitfld.long 0x04 0. " [0] ,TG interrupt clear (disabled) when transfer suspended" "Disabled,Enabled"
textline " "
line.long 0x08 "TGITLVST,MibSPI Transfer Group Interrupt Level Set Register"
bitfld.long 0x08 31. " SETINTLVLRDY[15] ,Transfer-group completed interrupt level set" "INT0,INT1"
bitfld.long 0x08 30. " [14] ,Transfer-group completed interrupt level set" "INT0,INT1"
bitfld.long 0x08 29. " [13] ,Transfer-group completed interrupt level set" "INT0,INT1"
bitfld.long 0x08 28. " [12] ,Transfer-group completed interrupt level set" "INT0,INT1"
bitfld.long 0x08 27. " [11] ,Transfer-group completed interrupt level set" "INT0,INT1"
bitfld.long 0x08 26. " [10] ,Transfer-group completed interrupt level set" "INT0,INT1"
textline " "
bitfld.long 0x08 25. " [9] ,Transfer-group completed interrupt level set" "INT0,INT1"
bitfld.long 0x08 24. " [8] ,Transfer-group completed interrupt level set" "INT0,INT1"
bitfld.long 0x08 23. " [7] ,Transfer-group completed interrupt level set" "INT0,INT1"
bitfld.long 0x08 22. " [6] ,Transfer-group completed interrupt level set" "INT0,INT1"
bitfld.long 0x08 21. " [5] ,Transfer-group completed interrupt level set" "INT0,INT1"
bitfld.long 0x08 20. " [4] ,Transfer-group completed interrupt level set" "INT0,INT1"
textline " "
bitfld.long 0x08 19. " [3] ,Transfer-group completed interrupt level set" "INT0,INT1"
bitfld.long 0x08 18. " [2] ,Transfer-group completed interrupt level set" "INT0,INT1"
bitfld.long 0x08 17. " [1] ,Transfer-group completed interrupt level set" "INT0,INT1"
bitfld.long 0x08 16. " [0] ,Transfer-group completed interrupt level set" "INT0,INT1"
textline " "
bitfld.long 0x08 15. " SETINTLVLSUS[15] ,Transfer-group suspended interrupt level set" "INT0,INT1"
bitfld.long 0x08 14. " [14] ,Transfer-group suspended interrupt level set" "INT0,INT1"
bitfld.long 0x08 13. " [13] ,Transfer-group suspended interrupt level set" "INT0,INT1"
bitfld.long 0x08 12. " [12] ,Transfer-group suspended interrupt level set" "INT0,INT1"
bitfld.long 0x08 11. " [11] ,Transfer-group suspended interrupt level set" "INT0,INT1"
bitfld.long 0x08 10. " [10] ,Transfer-group suspended interrupt level set" "INT0,INT1"
textline " "
bitfld.long 0x08 9. " [9] ,Transfer-group suspended interrupt level set" "INT0,INT1"
bitfld.long 0x08 8. " [8] ,Transfer-group suspended interrupt level set" "INT0,INT1"
bitfld.long 0x08 7. " [7] ,Transfer-group suspended interrupt level set" "INT0,INT1"
bitfld.long 0x08 6. " [6] ,Transfer-group suspended interrupt level set" "INT0,INT1"
bitfld.long 0x08 5. " [5] ,Transfer-group suspended interrupt level set" "INT0,INT1"
bitfld.long 0x08 4. " [4] ,Transfer-group suspended interrupt level set" "INT0,INT1"
textline " "
bitfld.long 0x08 3. " [3] ,Transfer-group suspended interrupt level set" "INT0,INT1"
bitfld.long 0x08 2. " [2] ,Transfer-group suspended interrupt level set" "INT0,INT1"
bitfld.long 0x08 1. " [1] ,Transfer-group suspended interrupt level set" "INT0,INT1"
bitfld.long 0x08 0. " [0] ,Transfer-group suspended interrupt level set" "INT0,INT1"
line.long 0x0C "TGITLVCR,MibSPI Transfer Group Interrupt Level Clear Register"
bitfld.long 0x0C 31. " CLRINTLVLRDY[15] ,Transfer-group completed interrupt level clear" "INT0,INT1"
bitfld.long 0x0C 30. " [14] ,Transfer-group completed interrupt level clear" "INT0,INT1"
bitfld.long 0x0C 29. " [13] ,Transfer-group completed interrupt level clear" "INT0,INT1"
bitfld.long 0x0C 28. " [12] ,Transfer-group completed interrupt level clear" "INT0,INT1"
bitfld.long 0x0C 27. " [11] ,Transfer-group completed interrupt level clear" "INT0,INT1"
bitfld.long 0x0C 26. " [10] ,Transfer-group completed interrupt level clear" "INT0,INT1"
textline " "
bitfld.long 0x0C 25. " [9] ,Transfer-group completed interrupt level clear" "INT0,INT1"
bitfld.long 0x0C 24. " [8] ,Transfer-group completed interrupt level clear" "INT0,INT1"
bitfld.long 0x0C 23. " [7] ,Transfer-group completed interrupt level clear" "INT0,INT1"
bitfld.long 0x0C 22. " [6] ,Transfer-group completed interrupt level clear" "INT0,INT1"
bitfld.long 0x0C 21. " [5] ,Transfer-group completed interrupt level clear" "INT0,INT1"
bitfld.long 0x0C 20. " [4] ,Transfer-group completed interrupt level clear" "INT0,INT1"
textline " "
bitfld.long 0x0C 19. " [3] ,Transfer-group completed interrupt level clear" "INT0,INT1"
bitfld.long 0x0C 18. " [2] ,Transfer-group completed interrupt level clear" "INT0,INT1"
bitfld.long 0x0C 17. " [1] ,Transfer-group completed interrupt level clear" "INT0,INT1"
bitfld.long 0x0C 16. " [0] ,Transfer-group completed interrupt level clear" "INT0,INT1"
textline " "
bitfld.long 0x0C 15. " CLRINTLVLSUS[15] ,Transfer group suspended interrupt level clear" "INT0,INT1"
bitfld.long 0x0C 14. " [14] ,Transfer group suspended interrupt level clear" "INT0,INT1"
bitfld.long 0x0C 13. " [13] ,Transfer group suspended interrupt level clear" "INT0,INT1"
bitfld.long 0x0C 12. " [12] ,Transfer group suspended interrupt level clear" "INT0,INT1"
bitfld.long 0x0C 11. " [11] ,Transfer group suspended interrupt level clear" "INT0,INT1"
bitfld.long 0x0C 10. " [10] ,Transfer group suspended interrupt level clear" "INT0,INT1"
textline " "
bitfld.long 0x0C 9. " [9] ,Transfer group suspended interrupt level clear" "INT0,INT1"
bitfld.long 0x0C 8. " [8] ,Transfer group suspended interrupt level clear" "INT0,INT1"
bitfld.long 0x0C 7. " [7] ,Transfer group suspended interrupt level clear" "INT0,INT1"
bitfld.long 0x0C 6. " [6] ,Transfer group suspended interrupt level clear" "INT0,INT1"
bitfld.long 0x0C 5. " [5] ,Transfer group suspended interrupt level clear" "INT0,INT1"
bitfld.long 0x0C 4. " [4] ,Transfer group suspended interrupt level clear" "INT0,INT1"
textline " "
bitfld.long 0x0C 3. " [3] ,Transfer group suspended interrupt level clear" "INT0,INT1"
bitfld.long 0x0C 2. " [2] ,Transfer group suspended interrupt level clear" "INT0,INT1"
bitfld.long 0x0C 1. " [1] ,Transfer group suspended interrupt level clear" "INT0,INT1"
bitfld.long 0x0C 0. " [0] ,Transfer group suspended interrupt level clear" "INT0,INT1"
textline " "
group.long 0x84++0x03
line.long 0x00 "TGITFLG,Transfer Group Interrupt Flag Register"
sif cpuis("TMS570LC4357")
bitfld.long 0x00 31. " INTFLGRDY[15] ,Transfer-group interrupt flag for a transfer-completed interrupt 15" "Disabled,Enabled"
bitfld.long 0x00 30. " [14] ,Transfer-group interrupt flag for a transfer-completed interrupt 14" "Disabled,Enabled"
bitfld.long 0x00 29. " [13] ,Transfer-group interrupt flag for a transfer-completed interrupt 13" "Disabled,Enabled"
bitfld.long 0x00 28. " [12] ,Transfer-group interrupt flag for a transfer-completed interrupt 12" "Disabled,Enabled"
textline " "
bitfld.long 0x00 27. " [11] ,Transfer-group interrupt flag for a transfer-completed interrupt 11" "Disabled,Enabled"
bitfld.long 0x00 26. " [10] ,Transfer-group interrupt flag for a transfer-completed interrupt 10" "Disabled,Enabled"
bitfld.long 0x00 25. " [9] ,Transfer-group interrupt flag for a transfer-completed interrupt 9" "Disabled,Enabled"
bitfld.long 0x00 24. " [8] ,Transfer-group interrupt flag for a transfer-completed interrupt 8" "Disabled,Enabled"
textline " "
bitfld.long 0x00 23. " [7] ,Transfer-group interrupt flag for a transfer-completed interrupt 7" "Disabled,Enabled"
bitfld.long 0x00 22. " [6] ,Transfer-group interrupt flag for a transfer-completed interrupt 6" "Disabled,Enabled"
bitfld.long 0x00 21. " [5] ,Transfer-group interrupt flag for a transfer-completed interrupt 5" "Disabled,Enabled"
bitfld.long 0x00 20. " [4] ,Transfer-group interrupt flag for a transfer-completed interrupt 4" "Disabled,Enabled"
textline " "
bitfld.long 0x00 19. " [3] ,Transfer-group interrupt flag for a transfer-completed interrupt 3" "Disabled,Enabled"
bitfld.long 0x00 18. " [2] ,Transfer-group interrupt flag for a transfer-completed interrupt 2" "Disabled,Enabled"
bitfld.long 0x00 17. " [1] ,Transfer-group interrupt flag for a transfer-completed interrupt 1" "Disabled,Enabled"
bitfld.long 0x00 16. " [0] ,Transfer-group interrupt flag for a transfer-completed interrupt 0" "Disabled,Enabled"
textline " "
endif
bitfld.long 0x00 15. " INTFLGSUS[15] ,Transfer-group interrupt flag for a transfer-suspend interrupt 15" "Disabled,Enabled"
bitfld.long 0x00 14. " [14] ,Transfer-group interrupt flag for a transfer-suspend interrupt 14" "Disabled,Enabled"
bitfld.long 0x00 13. " [13] ,Transfer-group interrupt flag for a transfer-suspend interrupt 13" "Disabled,Enabled"
bitfld.long 0x00 12. " [12] ,Transfer-group interrupt flag for a transfer-suspend interrupt 12" "Disabled,Enabled"
textline " "
bitfld.long 0x00 11. " [11] ,Transfer-group interrupt flag for a transfer-suspend interrupt 11" "Disabled,Enabled"
bitfld.long 0x00 10. " [10] ,Transfer-group interrupt flag for a transfer-suspend interrupt 10" "Disabled,Enabled"
bitfld.long 0x00 9. " [9] ,Transfer-group interrupt flag for a transfer-suspend interrupt 9" "Disabled,Enabled"
bitfld.long 0x00 8. " [8] ,Transfer-group interrupt flag for a transfer-suspend interrupt 8" "Disabled,Enabled"
textline " "
bitfld.long 0x00 7. " [7] ,Transfer-group interrupt flag for a transfer-suspend interrupt 7" "Disabled,Enabled"
bitfld.long 0x00 6. " [6] ,Transfer-group interrupt flag for a transfer-suspend interrupt 6" "Disabled,Enabled"
bitfld.long 0x00 5. " [5] ,Transfer-group interrupt flag for a transfer-suspend interrupt 5" "Disabled,Enabled"
bitfld.long 0x00 4. " [4] ,Transfer-group interrupt flag for a transfer-suspend interrupt 4" "Disabled,Enabled"
textline " "
bitfld.long 0x00 3. " [3] ,Transfer-group interrupt flag for a transfer-suspend interrupt 3" "Disabled,Enabled"
bitfld.long 0x00 2. " [2] ,Transfer-group interrupt flag for a transfer-suspend interrupt 2" "Disabled,Enabled"
bitfld.long 0x00 1. " [1] ,Transfer-group interrupt flag for a transfer-suspend interrupt 1" "Disabled,Enabled"
bitfld.long 0x00 0. " [0] ,Transfer-group interrupt flag for a transfer-suspend interrupt 0" "Disabled,Enabled"
textline " "
group.long 0x90++0x47
line.long 0x00 "TICKCNT,Tick Count Register"
bitfld.long 0x00 31. " TICKENA ,Tick counter enable" "Disabled,Enabled"
bitfld.long 0x00 30. " RELOAD ,Pre-load the tick counter" "No effect,Reload"
bitfld.long 0x00 28.--29. " CLKCTRL ,Tick counter clock source control" "0,1,2,3"
textline " "
hexmask.long.word 0x00 0.--15. 1. " TICKVALUE ,Initial value for the tick counter"
line.long 0x04 "LTGPEND,Last Transfer Group End Pointer Register"
rbitfld.long 0x04 24.--28. " TGINSERVICE ,The TG number currently being serviced by the sequencer" "No TG,TG0,TG1,TG2,TG3,TG4,TG5,TG6,TG7,TG8,TG9,TG10,TG11,TG12,TG13,TG14,TG15,?..."
hexmask.long.byte 0x04 8.--14. 1. " LPEND ,Last TG end pointer"
line.long 0x8 "TG1CTRL,MibSPI Transfer Group Control Register 1"
bitfld.long 0x8 31. " TGENA ,TG enable" "Disabled,Enabled"
bitfld.long 0x8 30. " ONESHOT ,Single transfer for TG" "Disabled,Enabled"
bitfld.long 0x8 29. " PRST ,TG pointer reset mode" "Disabled,Enabled"
textline " "
rbitfld.long 0x8 28. " TGTD ,TG triggered" "Not triggered,Triggered"
bitfld.long 0x8 20.--23. " TRGEVT ,Type of trigger event" "Never,Rising edge,Falling edge,Both edges,,High active,Low-active,Always,?..."
bitfld.long 0x8 16.--19. " TRIGSRC ,Trigger source" "Disabled,EXT[0],EXT[1],EXT[2],EXT[3],EXT[4],EXT[5],EXT[6],EXT[7],EXT[8],EXT[9,EXT[10,EXT[11,EXT[12,EXT[13],TICK"
textline " "
hexmask.long.byte 0x8 8.--14. 1. " PSTART ,TG start address"
hexmask.long.byte 0x8 0.--6. 1. " PCURRENT ,Pointer to current buffer"
line.long 0xC "TG2CTRL,MibSPI Transfer Group Control Register 2"
bitfld.long 0xC 31. " TGENA ,TG enable" "Disabled,Enabled"
bitfld.long 0xC 30. " ONESHOT ,Single transfer for TG" "Disabled,Enabled"
bitfld.long 0xC 29. " PRST ,TG pointer reset mode" "Disabled,Enabled"
textline " "
rbitfld.long 0xC 28. " TGTD ,TG triggered" "Not triggered,Triggered"
bitfld.long 0xC 20.--23. " TRGEVT ,Type of trigger event" "Never,Rising edge,Falling edge,Both edges,,High active,Low-active,Always,?..."
bitfld.long 0xC 16.--19. " TRIGSRC ,Trigger source" "Disabled,EXT[0],EXT[1],EXT[2],EXT[3],EXT[4],EXT[5],EXT[6],EXT[7],EXT[8],EXT[9,EXT[10,EXT[11,EXT[12,EXT[13],TICK"
textline " "
hexmask.long.byte 0xC 8.--14. 1. " PSTART ,TG start address"
hexmask.long.byte 0xC 0.--6. 1. " PCURRENT ,Pointer to current buffer"
line.long 0x10 "TG3CTRL,MibSPI Transfer Group Control Register 3"
bitfld.long 0x10 31. " TGENA ,TG enable" "Disabled,Enabled"
bitfld.long 0x10 30. " ONESHOT ,Single transfer for TG" "Disabled,Enabled"
bitfld.long 0x10 29. " PRST ,TG pointer reset mode" "Disabled,Enabled"
textline " "
rbitfld.long 0x10 28. " TGTD ,TG triggered" "Not triggered,Triggered"
bitfld.long 0x10 20.--23. " TRGEVT ,Type of trigger event" "Never,Rising edge,Falling edge,Both edges,,High active,Low-active,Always,?..."
bitfld.long 0x10 16.--19. " TRIGSRC ,Trigger source" "Disabled,EXT[0],EXT[1],EXT[2],EXT[3],EXT[4],EXT[5],EXT[6],EXT[7],EXT[8],EXT[9,EXT[10,EXT[11,EXT[12,EXT[13],TICK"
textline " "
hexmask.long.byte 0x10 8.--14. 1. " PSTART ,TG start address"
hexmask.long.byte 0x10 0.--6. 1. " PCURRENT ,Pointer to current buffer"
line.long 0x14 "TG4CTRL,MibSPI Transfer Group Control Register 4"
bitfld.long 0x14 31. " TGENA ,TG enable" "Disabled,Enabled"
bitfld.long 0x14 30. " ONESHOT ,Single transfer for TG" "Disabled,Enabled"
bitfld.long 0x14 29. " PRST ,TG pointer reset mode" "Disabled,Enabled"
textline " "
rbitfld.long 0x14 28. " TGTD ,TG triggered" "Not triggered,Triggered"
bitfld.long 0x14 20.--23. " TRGEVT ,Type of trigger event" "Never,Rising edge,Falling edge,Both edges,,High active,Low-active,Always,?..."
bitfld.long 0x14 16.--19. " TRIGSRC ,Trigger source" "Disabled,EXT[0],EXT[1],EXT[2],EXT[3],EXT[4],EXT[5],EXT[6],EXT[7],EXT[8],EXT[9,EXT[10,EXT[11,EXT[12,EXT[13],TICK"
textline " "
hexmask.long.byte 0x14 8.--14. 1. " PSTART ,TG start address"
hexmask.long.byte 0x14 0.--6. 1. " PCURRENT ,Pointer to current buffer"
line.long 0x18 "TG5CTRL,MibSPI Transfer Group Control Register 5"
bitfld.long 0x18 31. " TGENA ,TG enable" "Disabled,Enabled"
bitfld.long 0x18 30. " ONESHOT ,Single transfer for TG" "Disabled,Enabled"
bitfld.long 0x18 29. " PRST ,TG pointer reset mode" "Disabled,Enabled"
textline " "
rbitfld.long 0x18 28. " TGTD ,TG triggered" "Not triggered,Triggered"
bitfld.long 0x18 20.--23. " TRGEVT ,Type of trigger event" "Never,Rising edge,Falling edge,Both edges,,High active,Low-active,Always,?..."
bitfld.long 0x18 16.--19. " TRIGSRC ,Trigger source" "Disabled,EXT[0],EXT[1],EXT[2],EXT[3],EXT[4],EXT[5],EXT[6],EXT[7],EXT[8],EXT[9,EXT[10,EXT[11,EXT[12,EXT[13],TICK"
textline " "
hexmask.long.byte 0x18 8.--14. 1. " PSTART ,TG start address"
hexmask.long.byte 0x18 0.--6. 1. " PCURRENT ,Pointer to current buffer"
line.long 0x1C "TG6CTRL,MibSPI Transfer Group Control Register 6"
bitfld.long 0x1C 31. " TGENA ,TG enable" "Disabled,Enabled"
bitfld.long 0x1C 30. " ONESHOT ,Single transfer for TG" "Disabled,Enabled"
bitfld.long 0x1C 29. " PRST ,TG pointer reset mode" "Disabled,Enabled"
textline " "
rbitfld.long 0x1C 28. " TGTD ,TG triggered" "Not triggered,Triggered"
bitfld.long 0x1C 20.--23. " TRGEVT ,Type of trigger event" "Never,Rising edge,Falling edge,Both edges,,High active,Low-active,Always,?..."
bitfld.long 0x1C 16.--19. " TRIGSRC ,Trigger source" "Disabled,EXT[0],EXT[1],EXT[2],EXT[3],EXT[4],EXT[5],EXT[6],EXT[7],EXT[8],EXT[9,EXT[10,EXT[11,EXT[12,EXT[13],TICK"
textline " "
hexmask.long.byte 0x1C 8.--14. 1. " PSTART ,TG start address"
hexmask.long.byte 0x1C 0.--6. 1. " PCURRENT ,Pointer to current buffer"
line.long 0x20 "TG7CTRL,MibSPI Transfer Group Control Register 7"
bitfld.long 0x20 31. " TGENA ,TG enable" "Disabled,Enabled"
bitfld.long 0x20 30. " ONESHOT ,Single transfer for TG" "Disabled,Enabled"
bitfld.long 0x20 29. " PRST ,TG pointer reset mode" "Disabled,Enabled"
textline " "
rbitfld.long 0x20 28. " TGTD ,TG triggered" "Not triggered,Triggered"
bitfld.long 0x20 20.--23. " TRGEVT ,Type of trigger event" "Never,Rising edge,Falling edge,Both edges,,High active,Low-active,Always,?..."
bitfld.long 0x20 16.--19. " TRIGSRC ,Trigger source" "Disabled,EXT[0],EXT[1],EXT[2],EXT[3],EXT[4],EXT[5],EXT[6],EXT[7],EXT[8],EXT[9,EXT[10,EXT[11,EXT[12,EXT[13],TICK"
textline " "
hexmask.long.byte 0x20 8.--14. 1. " PSTART ,TG start address"
hexmask.long.byte 0x20 0.--6. 1. " PCURRENT ,Pointer to current buffer"
line.long 0x24 "TG8CTRL,MibSPI Transfer Group Control Register 8"
bitfld.long 0x24 31. " TGENA ,TG enable" "Disabled,Enabled"
bitfld.long 0x24 30. " ONESHOT ,Single transfer for TG" "Disabled,Enabled"
bitfld.long 0x24 29. " PRST ,TG pointer reset mode" "Disabled,Enabled"
textline " "
rbitfld.long 0x24 28. " TGTD ,TG triggered" "Not triggered,Triggered"
bitfld.long 0x24 20.--23. " TRGEVT ,Type of trigger event" "Never,Rising edge,Falling edge,Both edges,,High active,Low-active,Always,?..."
bitfld.long 0x24 16.--19. " TRIGSRC ,Trigger source" "Disabled,EXT[0],EXT[1],EXT[2],EXT[3],EXT[4],EXT[5],EXT[6],EXT[7],EXT[8],EXT[9,EXT[10,EXT[11,EXT[12,EXT[13],TICK"
textline " "
hexmask.long.byte 0x24 8.--14. 1. " PSTART ,TG start address"
hexmask.long.byte 0x24 0.--6. 1. " PCURRENT ,Pointer to current buffer"
line.long 0x28 "TG9CTRL,MibSPI Transfer Group Control Register 9"
bitfld.long 0x28 31. " TGENA ,TG enable" "Disabled,Enabled"
bitfld.long 0x28 30. " ONESHOT ,Single transfer for TG" "Disabled,Enabled"
bitfld.long 0x28 29. " PRST ,TG pointer reset mode" "Disabled,Enabled"
textline " "
rbitfld.long 0x28 28. " TGTD ,TG triggered" "Not triggered,Triggered"
bitfld.long 0x28 20.--23. " TRGEVT ,Type of trigger event" "Never,Rising edge,Falling edge,Both edges,,High active,Low-active,Always,?..."
bitfld.long 0x28 16.--19. " TRIGSRC ,Trigger source" "Disabled,EXT[0],EXT[1],EXT[2],EXT[3],EXT[4],EXT[5],EXT[6],EXT[7],EXT[8],EXT[9,EXT[10,EXT[11,EXT[12,EXT[13],TICK"
textline " "
hexmask.long.byte 0x28 8.--14. 1. " PSTART ,TG start address"
hexmask.long.byte 0x28 0.--6. 1. " PCURRENT ,Pointer to current buffer"
line.long 0x2C "TG10CTRL,MibSPI Transfer Group Control Register 10"
bitfld.long 0x2C 31. " TGENA ,TG enable" "Disabled,Enabled"
bitfld.long 0x2C 30. " ONESHOT ,Single transfer for TG" "Disabled,Enabled"
bitfld.long 0x2C 29. " PRST ,TG pointer reset mode" "Disabled,Enabled"
textline " "
rbitfld.long 0x2C 28. " TGTD ,TG triggered" "Not triggered,Triggered"
bitfld.long 0x2C 20.--23. " TRGEVT ,Type of trigger event" "Never,Rising edge,Falling edge,Both edges,,High active,Low-active,Always,?..."
bitfld.long 0x2C 16.--19. " TRIGSRC ,Trigger source" "Disabled,EXT[0],EXT[1],EXT[2],EXT[3],EXT[4],EXT[5],EXT[6],EXT[7],EXT[8],EXT[9,EXT[10,EXT[11,EXT[12,EXT[13],TICK"
textline " "
hexmask.long.byte 0x2C 8.--14. 1. " PSTART ,TG start address"
hexmask.long.byte 0x2C 0.--6. 1. " PCURRENT ,Pointer to current buffer"
line.long 0x30 "TG11CTRL,MibSPI Transfer Group Control Register 11"
bitfld.long 0x30 31. " TGENA ,TG enable" "Disabled,Enabled"
bitfld.long 0x30 30. " ONESHOT ,Single transfer for TG" "Disabled,Enabled"
bitfld.long 0x30 29. " PRST ,TG pointer reset mode" "Disabled,Enabled"
textline " "
rbitfld.long 0x30 28. " TGTD ,TG triggered" "Not triggered,Triggered"
bitfld.long 0x30 20.--23. " TRGEVT ,Type of trigger event" "Never,Rising edge,Falling edge,Both edges,,High active,Low-active,Always,?..."
bitfld.long 0x30 16.--19. " TRIGSRC ,Trigger source" "Disabled,EXT[0],EXT[1],EXT[2],EXT[3],EXT[4],EXT[5],EXT[6],EXT[7],EXT[8],EXT[9,EXT[10,EXT[11,EXT[12,EXT[13],TICK"
textline " "
hexmask.long.byte 0x30 8.--14. 1. " PSTART ,TG start address"
hexmask.long.byte 0x30 0.--6. 1. " PCURRENT ,Pointer to current buffer"
line.long 0x34 "TG12CTRL,MibSPI Transfer Group Control Register 12"
bitfld.long 0x34 31. " TGENA ,TG enable" "Disabled,Enabled"
bitfld.long 0x34 30. " ONESHOT ,Single transfer for TG" "Disabled,Enabled"
bitfld.long 0x34 29. " PRST ,TG pointer reset mode" "Disabled,Enabled"
textline " "
rbitfld.long 0x34 28. " TGTD ,TG triggered" "Not triggered,Triggered"
bitfld.long 0x34 20.--23. " TRGEVT ,Type of trigger event" "Never,Rising edge,Falling edge,Both edges,,High active,Low-active,Always,?..."
bitfld.long 0x34 16.--19. " TRIGSRC ,Trigger source" "Disabled,EXT[0],EXT[1],EXT[2],EXT[3],EXT[4],EXT[5],EXT[6],EXT[7],EXT[8],EXT[9,EXT[10,EXT[11,EXT[12,EXT[13],TICK"
textline " "
hexmask.long.byte 0x34 8.--14. 1. " PSTART ,TG start address"
hexmask.long.byte 0x34 0.--6. 1. " PCURRENT ,Pointer to current buffer"
line.long 0x38 "TG13CTRL,MibSPI Transfer Group Control Register 13"
bitfld.long 0x38 31. " TGENA ,TG enable" "Disabled,Enabled"
bitfld.long 0x38 30. " ONESHOT ,Single transfer for TG" "Disabled,Enabled"
bitfld.long 0x38 29. " PRST ,TG pointer reset mode" "Disabled,Enabled"
textline " "
rbitfld.long 0x38 28. " TGTD ,TG triggered" "Not triggered,Triggered"
bitfld.long 0x38 20.--23. " TRGEVT ,Type of trigger event" "Never,Rising edge,Falling edge,Both edges,,High active,Low-active,Always,?..."
bitfld.long 0x38 16.--19. " TRIGSRC ,Trigger source" "Disabled,EXT[0],EXT[1],EXT[2],EXT[3],EXT[4],EXT[5],EXT[6],EXT[7],EXT[8],EXT[9,EXT[10,EXT[11,EXT[12,EXT[13],TICK"
textline " "
hexmask.long.byte 0x38 8.--14. 1. " PSTART ,TG start address"
hexmask.long.byte 0x38 0.--6. 1. " PCURRENT ,Pointer to current buffer"
line.long 0x3C "TG14CTRL,MibSPI Transfer Group Control Register 14"
bitfld.long 0x3C 31. " TGENA ,TG enable" "Disabled,Enabled"
bitfld.long 0x3C 30. " ONESHOT ,Single transfer for TG" "Disabled,Enabled"
bitfld.long 0x3C 29. " PRST ,TG pointer reset mode" "Disabled,Enabled"
textline " "
rbitfld.long 0x3C 28. " TGTD ,TG triggered" "Not triggered,Triggered"
bitfld.long 0x3C 20.--23. " TRGEVT ,Type of trigger event" "Never,Rising edge,Falling edge,Both edges,,High active,Low-active,Always,?..."
bitfld.long 0x3C 16.--19. " TRIGSRC ,Trigger source" "Disabled,EXT[0],EXT[1],EXT[2],EXT[3],EXT[4],EXT[5],EXT[6],EXT[7],EXT[8],EXT[9,EXT[10,EXT[11,EXT[12,EXT[13],TICK"
textline " "
hexmask.long.byte 0x3C 8.--14. 1. " PSTART ,TG start address"
hexmask.long.byte 0x3C 0.--6. 1. " PCURRENT ,Pointer to current buffer"
line.long 0x40 "TG15CTRL,MibSPI Transfer Group Control Register 15"
bitfld.long 0x40 31. " TGENA ,TG enable" "Disabled,Enabled"
bitfld.long 0x40 30. " ONESHOT ,Single transfer for TG" "Disabled,Enabled"
bitfld.long 0x40 29. " PRST ,TG pointer reset mode" "Disabled,Enabled"
textline " "
rbitfld.long 0x40 28. " TGTD ,TG triggered" "Not triggered,Triggered"
bitfld.long 0x40 20.--23. " TRGEVT ,Type of trigger event" "Never,Rising edge,Falling edge,Both edges,,High active,Low-active,Always,?..."
bitfld.long 0x40 16.--19. " TRIGSRC ,Trigger source" "Disabled,EXT[0],EXT[1],EXT[2],EXT[3],EXT[4],EXT[5],EXT[6],EXT[7],EXT[8],EXT[9,EXT[10,EXT[11,EXT[12,EXT[13],TICK"
textline " "
hexmask.long.byte 0x40 8.--14. 1. " PSTART ,TG start address"
hexmask.long.byte 0x40 0.--6. 1. " PCURRENT ,Pointer to current buffer"
line.long 0x44 "TG16CTRL,MibSPI Transfer Group Control Register 16"
bitfld.long 0x44 31. " TGENA ,TG enable" "Disabled,Enabled"
bitfld.long 0x44 30. " ONESHOT ,Single transfer for TG" "Disabled,Enabled"
bitfld.long 0x44 29. " PRST ,TG pointer reset mode" "Disabled,Enabled"
textline " "
rbitfld.long 0x44 28. " TGTD ,TG triggered" "Not triggered,Triggered"
bitfld.long 0x44 20.--23. " TRGEVT ,Type of trigger event" "Never,Rising edge,Falling edge,Both edges,,High active,Low-active,Always,?..."
bitfld.long 0x44 16.--19. " TRIGSRC ,Trigger source" "Disabled,EXT[0],EXT[1],EXT[2],EXT[3],EXT[4],EXT[5],EXT[6],EXT[7],EXT[8],EXT[9,EXT[10,EXT[11,EXT[12,EXT[13],TICK"
textline " "
hexmask.long.byte 0x44 8.--14. 1. " PSTART ,TG start address"
hexmask.long.byte 0x44 0.--6. 1. " PCURRENT ,Pointer to current buffer"
if (((d.l(ad:0xFFF7F400+0x4))&0x3)==0x0)
group.long 0xD8++0x1F
line.long 0x0 "DMA1CTRL,MibSPI DMA Channel Control Register 1"
bitfld.long 0x0 31. " ONESHOT ,Auto-disable of DMA channel after ICOUNT+1 transfers" "0,1"
hexmask.long.byte 0x0 24.--30. 1. " BUFID ,Buffer utilized for DMA transfer"
bitfld.long 0x0 20.--23. " RXDMA_MAP ,Each MibSPI DMA channel can be linked to two physical DMA" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x0 16.--19. " TXDMA_MAP ,Each MibSPI DMA channel can be linked to two physical DMA" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x0 15. " RXDMAENA ,Receive data DMA channel enable" "Disabled,Enabled"
bitfld.long 0x0 14. " TXDMAENA ,Transmit data DMA channel enable" "Disabled,Enabled"
textline " "
bitfld.long 0x0 8.--12. " ICOUNT ,Initial count of DMA transfers" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32"
rbitfld.long 0x0 6. " COUNTBIT17 ,17th bit of the COUNT field of DMAxCOUNT register" "0,1"
rbitfld.long 0x0 0.--5. " COUNT ,Actual number of remaining DMA transfers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x4 "DMA2CTRL,MibSPI DMA Channel Control Register 1"
bitfld.long 0x4 31. " ONESHOT ,Auto-disable of DMA channel after ICOUNT+1 transfers" "0,1"
hexmask.long.byte 0x4 24.--30. 1. " BUFID ,Buffer utilized for DMA transfer"
bitfld.long 0x4 20.--23. " RXDMA_MAP ,Each MibSPI DMA channel can be linked to two physical DMA" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x4 16.--19. " TXDMA_MAP ,Each MibSPI DMA channel can be linked to two physical DMA" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x4 15. " RXDMAENA ,Receive data DMA channel enable" "Disabled,Enabled"
bitfld.long 0x4 14. " TXDMAENA ,Transmit data DMA channel enable" "Disabled,Enabled"
textline " "
bitfld.long 0x4 8.--12. " ICOUNT ,Initial count of DMA transfers" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32"
rbitfld.long 0x4 6. " COUNTBIT17 ,17th bit of the COUNT field of DMAxCOUNT register" "0,1"
rbitfld.long 0x4 0.--5. " COUNT ,Actual number of remaining DMA transfers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x8 "DMA3CTRL,MibSPI DMA Channel Control Register 1"
bitfld.long 0x8 31. " ONESHOT ,Auto-disable of DMA channel after ICOUNT+1 transfers" "0,1"
hexmask.long.byte 0x8 24.--30. 1. " BUFID ,Buffer utilized for DMA transfer"
bitfld.long 0x8 20.--23. " RXDMA_MAP ,Each MibSPI DMA channel can be linked to two physical DMA" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x8 16.--19. " TXDMA_MAP ,Each MibSPI DMA channel can be linked to two physical DMA" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x8 15. " RXDMAENA ,Receive data DMA channel enable" "Disabled,Enabled"
bitfld.long 0x8 14. " TXDMAENA ,Transmit data DMA channel enable" "Disabled,Enabled"
textline " "
bitfld.long 0x8 8.--12. " ICOUNT ,Initial count of DMA transfers" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32"
rbitfld.long 0x8 6. " COUNTBIT17 ,17th bit of the COUNT field of DMAxCOUNT register" "0,1"
rbitfld.long 0x8 0.--5. " COUNT ,Actual number of remaining DMA transfers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0xC "DMA4CTRL,MibSPI DMA Channel Control Register 1"
bitfld.long 0xC 31. " ONESHOT ,Auto-disable of DMA channel after ICOUNT+1 transfers" "0,1"
hexmask.long.byte 0xC 24.--30. 1. " BUFID ,Buffer utilized for DMA transfer"
bitfld.long 0xC 20.--23. " RXDMA_MAP ,Each MibSPI DMA channel can be linked to two physical DMA" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0xC 16.--19. " TXDMA_MAP ,Each MibSPI DMA channel can be linked to two physical DMA" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0xC 15. " RXDMAENA ,Receive data DMA channel enable" "Disabled,Enabled"
bitfld.long 0xC 14. " TXDMAENA ,Transmit data DMA channel enable" "Disabled,Enabled"
textline " "
bitfld.long 0xC 8.--12. " ICOUNT ,Initial count of DMA transfers" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32"
rbitfld.long 0xC 6. " COUNTBIT17 ,17th bit of the COUNT field of DMAxCOUNT register" "0,1"
rbitfld.long 0xC 0.--5. " COUNT ,Actual number of remaining DMA transfers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x10 "DMA5CTRL,MibSPI DMA Channel Control Register 1"
bitfld.long 0x10 31. " ONESHOT ,Auto-disable of DMA channel after ICOUNT+1 transfers" "0,1"
hexmask.long.byte 0x10 24.--30. 1. " BUFID ,Buffer utilized for DMA transfer"
bitfld.long 0x10 20.--23. " RXDMA_MAP ,Each MibSPI DMA channel can be linked to two physical DMA" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x10 16.--19. " TXDMA_MAP ,Each MibSPI DMA channel can be linked to two physical DMA" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x10 15. " RXDMAENA ,Receive data DMA channel enable" "Disabled,Enabled"
bitfld.long 0x10 14. " TXDMAENA ,Transmit data DMA channel enable" "Disabled,Enabled"
textline " "
bitfld.long 0x10 8.--12. " ICOUNT ,Initial count of DMA transfers" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32"
rbitfld.long 0x10 6. " COUNTBIT17 ,17th bit of the COUNT field of DMAxCOUNT register" "0,1"
rbitfld.long 0x10 0.--5. " COUNT ,Actual number of remaining DMA transfers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x14 "DMA6CTRL,MibSPI DMA Channel Control Register 1"
bitfld.long 0x14 31. " ONESHOT ,Auto-disable of DMA channel after ICOUNT+1 transfers" "0,1"
hexmask.long.byte 0x14 24.--30. 1. " BUFID ,Buffer utilized for DMA transfer"
bitfld.long 0x14 20.--23. " RXDMA_MAP ,Each MibSPI DMA channel can be linked to two physical DMA" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x14 16.--19. " TXDMA_MAP ,Each MibSPI DMA channel can be linked to two physical DMA" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x14 15. " RXDMAENA ,Receive data DMA channel enable" "Disabled,Enabled"
bitfld.long 0x14 14. " TXDMAENA ,Transmit data DMA channel enable" "Disabled,Enabled"
textline " "
bitfld.long 0x14 8.--12. " ICOUNT ,Initial count of DMA transfers" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32"
rbitfld.long 0x14 6. " COUNTBIT17 ,17th bit of the COUNT field of DMAxCOUNT register" "0,1"
rbitfld.long 0x14 0.--5. " COUNT ,Actual number of remaining DMA transfers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x18 "DMA7CTRL,MibSPI DMA Channel Control Register 1"
bitfld.long 0x18 31. " ONESHOT ,Auto-disable of DMA channel after ICOUNT+1 transfers" "0,1"
hexmask.long.byte 0x18 24.--30. 1. " BUFID ,Buffer utilized for DMA transfer"
bitfld.long 0x18 20.--23. " RXDMA_MAP ,Each MibSPI DMA channel can be linked to two physical DMA" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x18 16.--19. " TXDMA_MAP ,Each MibSPI DMA channel can be linked to two physical DMA" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x18 15. " RXDMAENA ,Receive data DMA channel enable" "Disabled,Enabled"
bitfld.long 0x18 14. " TXDMAENA ,Transmit data DMA channel enable" "Disabled,Enabled"
textline " "
bitfld.long 0x18 8.--12. " ICOUNT ,Initial count of DMA transfers" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32"
rbitfld.long 0x18 6. " COUNTBIT17 ,17th bit of the COUNT field of DMAxCOUNT register" "0,1"
rbitfld.long 0x18 0.--5. " COUNT ,Actual number of remaining DMA transfers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x1C "DMA8CTRL,MibSPI DMA Channel Control Register 1"
bitfld.long 0x1C 31. " ONESHOT ,Auto-disable of DMA channel after ICOUNT+1 transfers" "0,1"
hexmask.long.byte 0x1C 24.--30. 1. " BUFID ,Buffer utilized for DMA transfer"
bitfld.long 0x1C 20.--23. " RXDMA_MAP ,Each MibSPI DMA channel can be linked to two physical DMA" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x1C 16.--19. " TXDMA_MAP ,Each MibSPI DMA channel can be linked to two physical DMA" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x1C 15. " RXDMAENA ,Receive data DMA channel enable" "Disabled,Enabled"
bitfld.long 0x1C 14. " TXDMAENA ,Transmit data DMA channel enable" "Disabled,Enabled"
textline " "
bitfld.long 0x1C 8.--12. " ICOUNT ,Initial count of DMA transfers" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32"
rbitfld.long 0x1C 6. " COUNTBIT17 ,17th bit of the COUNT field of DMAxCOUNT register" "0,1"
rbitfld.long 0x1C 0.--5. " COUNT ,Actual number of remaining DMA transfers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
else
group.long 0xD8++0x1F
line.long 0x0 "DMA1CTRL,MibSPI DMA Channel Control Register 1"
bitfld.long 0x0 31. " ONESHOT ,Auto-disable of DMA channel after ICOUNT+1 transfers" "0,1"
hexmask.long.byte 0x0 24.--30. 1. " BUFID ,Buffer utilized for DMA transfer"
bitfld.long 0x0 20.--23. " RXDMA_MAP ,Each MibSPI DMA channel can be linked to two physical DMA" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x0 16.--19. " TXDMA_MAP ,Each MibSPI DMA channel can be linked to two physical DMA" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x0 15. " RXDMAENA ,Receive data DMA channel enable" "Disabled,Enabled"
bitfld.long 0x0 14. " TXDMAENA ,Transmit data DMA channel enable" "Disabled,Enabled"
textline " "
bitfld.long 0x0 13. " NOBRK ,Non-interleaved DMA block transfer" "Not performed,Performed"
bitfld.long 0x0 8.--12. " ICOUNT ,Initial count of DMA transfers" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32"
rbitfld.long 0x0 6. " COUNTBIT17 ,17th bit of the COUNT field of DMAxCOUNT register" "0,1"
textline " "
rbitfld.long 0x0 0.--5. " COUNT ,Actual number of remaining DMA transfers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x4 "DMA2CTRL,MibSPI DMA Channel Control Register 1"
bitfld.long 0x4 31. " ONESHOT ,Auto-disable of DMA channel after ICOUNT+1 transfers" "0,1"
hexmask.long.byte 0x4 24.--30. 1. " BUFID ,Buffer utilized for DMA transfer"
bitfld.long 0x4 20.--23. " RXDMA_MAP ,Each MibSPI DMA channel can be linked to two physical DMA" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x4 16.--19. " TXDMA_MAP ,Each MibSPI DMA channel can be linked to two physical DMA" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x4 15. " RXDMAENA ,Receive data DMA channel enable" "Disabled,Enabled"
bitfld.long 0x4 14. " TXDMAENA ,Transmit data DMA channel enable" "Disabled,Enabled"
textline " "
bitfld.long 0x4 13. " NOBRK ,Non-interleaved DMA block transfer" "Not performed,Performed"
bitfld.long 0x4 8.--12. " ICOUNT ,Initial count of DMA transfers" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32"
rbitfld.long 0x4 6. " COUNTBIT17 ,17th bit of the COUNT field of DMAxCOUNT register" "0,1"
textline " "
rbitfld.long 0x4 0.--5. " COUNT ,Actual number of remaining DMA transfers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x8 "DMA3CTRL,MibSPI DMA Channel Control Register 1"
bitfld.long 0x8 31. " ONESHOT ,Auto-disable of DMA channel after ICOUNT+1 transfers" "0,1"
hexmask.long.byte 0x8 24.--30. 1. " BUFID ,Buffer utilized for DMA transfer"
bitfld.long 0x8 20.--23. " RXDMA_MAP ,Each MibSPI DMA channel can be linked to two physical DMA" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x8 16.--19. " TXDMA_MAP ,Each MibSPI DMA channel can be linked to two physical DMA" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x8 15. " RXDMAENA ,Receive data DMA channel enable" "Disabled,Enabled"
bitfld.long 0x8 14. " TXDMAENA ,Transmit data DMA channel enable" "Disabled,Enabled"
textline " "
bitfld.long 0x8 13. " NOBRK ,Non-interleaved DMA block transfer" "Not performed,Performed"
bitfld.long 0x8 8.--12. " ICOUNT ,Initial count of DMA transfers" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32"
rbitfld.long 0x8 6. " COUNTBIT17 ,17th bit of the COUNT field of DMAxCOUNT register" "0,1"
textline " "
rbitfld.long 0x8 0.--5. " COUNT ,Actual number of remaining DMA transfers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0xC "DMA4CTRL,MibSPI DMA Channel Control Register 1"
bitfld.long 0xC 31. " ONESHOT ,Auto-disable of DMA channel after ICOUNT+1 transfers" "0,1"
hexmask.long.byte 0xC 24.--30. 1. " BUFID ,Buffer utilized for DMA transfer"
bitfld.long 0xC 20.--23. " RXDMA_MAP ,Each MibSPI DMA channel can be linked to two physical DMA" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0xC 16.--19. " TXDMA_MAP ,Each MibSPI DMA channel can be linked to two physical DMA" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0xC 15. " RXDMAENA ,Receive data DMA channel enable" "Disabled,Enabled"
bitfld.long 0xC 14. " TXDMAENA ,Transmit data DMA channel enable" "Disabled,Enabled"
textline " "
bitfld.long 0xC 13. " NOBRK ,Non-interleaved DMA block transfer" "Not performed,Performed"
bitfld.long 0xC 8.--12. " ICOUNT ,Initial count of DMA transfers" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32"
rbitfld.long 0xC 6. " COUNTBIT17 ,17th bit of the COUNT field of DMAxCOUNT register" "0,1"
textline " "
rbitfld.long 0xC 0.--5. " COUNT ,Actual number of remaining DMA transfers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x10 "DMA5CTRL,MibSPI DMA Channel Control Register 1"
bitfld.long 0x10 31. " ONESHOT ,Auto-disable of DMA channel after ICOUNT+1 transfers" "0,1"
hexmask.long.byte 0x10 24.--30. 1. " BUFID ,Buffer utilized for DMA transfer"
bitfld.long 0x10 20.--23. " RXDMA_MAP ,Each MibSPI DMA channel can be linked to two physical DMA" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x10 16.--19. " TXDMA_MAP ,Each MibSPI DMA channel can be linked to two physical DMA" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x10 15. " RXDMAENA ,Receive data DMA channel enable" "Disabled,Enabled"
bitfld.long 0x10 14. " TXDMAENA ,Transmit data DMA channel enable" "Disabled,Enabled"
textline " "
bitfld.long 0x10 13. " NOBRK ,Non-interleaved DMA block transfer" "Not performed,Performed"
bitfld.long 0x10 8.--12. " ICOUNT ,Initial count of DMA transfers" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32"
rbitfld.long 0x10 6. " COUNTBIT17 ,17th bit of the COUNT field of DMAxCOUNT register" "0,1"
textline " "
rbitfld.long 0x10 0.--5. " COUNT ,Actual number of remaining DMA transfers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x14 "DMA6CTRL,MibSPI DMA Channel Control Register 1"
bitfld.long 0x14 31. " ONESHOT ,Auto-disable of DMA channel after ICOUNT+1 transfers" "0,1"
hexmask.long.byte 0x14 24.--30. 1. " BUFID ,Buffer utilized for DMA transfer"
bitfld.long 0x14 20.--23. " RXDMA_MAP ,Each MibSPI DMA channel can be linked to two physical DMA" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x14 16.--19. " TXDMA_MAP ,Each MibSPI DMA channel can be linked to two physical DMA" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x14 15. " RXDMAENA ,Receive data DMA channel enable" "Disabled,Enabled"
bitfld.long 0x14 14. " TXDMAENA ,Transmit data DMA channel enable" "Disabled,Enabled"
textline " "
bitfld.long 0x14 13. " NOBRK ,Non-interleaved DMA block transfer" "Not performed,Performed"
bitfld.long 0x14 8.--12. " ICOUNT ,Initial count of DMA transfers" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32"
rbitfld.long 0x14 6. " COUNTBIT17 ,17th bit of the COUNT field of DMAxCOUNT register" "0,1"
textline " "
rbitfld.long 0x14 0.--5. " COUNT ,Actual number of remaining DMA transfers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x18 "DMA7CTRL,MibSPI DMA Channel Control Register 1"
bitfld.long 0x18 31. " ONESHOT ,Auto-disable of DMA channel after ICOUNT+1 transfers" "0,1"
hexmask.long.byte 0x18 24.--30. 1. " BUFID ,Buffer utilized for DMA transfer"
bitfld.long 0x18 20.--23. " RXDMA_MAP ,Each MibSPI DMA channel can be linked to two physical DMA" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x18 16.--19. " TXDMA_MAP ,Each MibSPI DMA channel can be linked to two physical DMA" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x18 15. " RXDMAENA ,Receive data DMA channel enable" "Disabled,Enabled"
bitfld.long 0x18 14. " TXDMAENA ,Transmit data DMA channel enable" "Disabled,Enabled"
textline " "
bitfld.long 0x18 13. " NOBRK ,Non-interleaved DMA block transfer" "Not performed,Performed"
bitfld.long 0x18 8.--12. " ICOUNT ,Initial count of DMA transfers" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32"
rbitfld.long 0x18 6. " COUNTBIT17 ,17th bit of the COUNT field of DMAxCOUNT register" "0,1"
textline " "
rbitfld.long 0x18 0.--5. " COUNT ,Actual number of remaining DMA transfers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x1C "DMA8CTRL,MibSPI DMA Channel Control Register 1"
bitfld.long 0x1C 31. " ONESHOT ,Auto-disable of DMA channel after ICOUNT+1 transfers" "0,1"
hexmask.long.byte 0x1C 24.--30. 1. " BUFID ,Buffer utilized for DMA transfer"
bitfld.long 0x1C 20.--23. " RXDMA_MAP ,Each MibSPI DMA channel can be linked to two physical DMA" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x1C 16.--19. " TXDMA_MAP ,Each MibSPI DMA channel can be linked to two physical DMA" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x1C 15. " RXDMAENA ,Receive data DMA channel enable" "Disabled,Enabled"
bitfld.long 0x1C 14. " TXDMAENA ,Transmit data DMA channel enable" "Disabled,Enabled"
textline " "
bitfld.long 0x1C 13. " NOBRK ,Non-interleaved DMA block transfer" "Not performed,Performed"
bitfld.long 0x1C 8.--12. " ICOUNT ,Initial count of DMA transfers" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32"
rbitfld.long 0x1C 6. " COUNTBIT17 ,17th bit of the COUNT field of DMAxCOUNT register" "0,1"
textline " "
rbitfld.long 0x1C 0.--5. " COUNT ,Actual number of remaining DMA transfers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
endif
group.long 0xF8++0x1F
line.long 0x0 "DMA0COUNT,MibSPI DMA0COUNT Register"
hexmask.long.word 0x0 16.--31. 1. " ICOUNT0 ,Initial number of DMA transfers"
hexmask.long.word 0x0 0.--15. 1. " COUNT0 ,The actual number of remaining DMA transfers"
line.long 0x4 "DMA1COUNT,MibSPI DMA1COUNT Register"
hexmask.long.word 0x4 16.--31. 1. " ICOUNT1 ,Initial number of DMA transfers"
hexmask.long.word 0x4 0.--15. 1. " COUNT1 ,The actual number of remaining DMA transfers"
line.long 0x8 "DMA2COUNT,MibSPI DMA2COUNT Register"
hexmask.long.word 0x8 16.--31. 1. " ICOUNT2 ,Initial number of DMA transfers"
hexmask.long.word 0x8 0.--15. 1. " COUNT2 ,The actual number of remaining DMA transfers"
line.long 0xC "DMA3COUNT,MibSPI DMA3COUNT Register"
hexmask.long.word 0xC 16.--31. 1. " ICOUNT3 ,Initial number of DMA transfers"
hexmask.long.word 0xC 0.--15. 1. " COUNT3 ,The actual number of remaining DMA transfers"
line.long 0x10 "DMA4COUNT,MibSPI DMA4COUNT Register"
hexmask.long.word 0x10 16.--31. 1. " ICOUNT4 ,Initial number of DMA transfers"
hexmask.long.word 0x10 0.--15. 1. " COUNT4 ,The actual number of remaining DMA transfers"
line.long 0x14 "DMA5COUNT,MibSPI DMA5COUNT Register"
hexmask.long.word 0x14 16.--31. 1. " ICOUNT5 ,Initial number of DMA transfers"
hexmask.long.word 0x14 0.--15. 1. " COUNT5 ,The actual number of remaining DMA transfers"
line.long 0x18 "DMA6COUNT,MibSPI DMA6COUNT Register"
hexmask.long.word 0x18 16.--31. 1. " ICOUNT6 ,Initial number of DMA transfers"
hexmask.long.word 0x18 0.--15. 1. " COUNT6 ,The actual number of remaining DMA transfers"
line.long 0x1C "DMA7COUNT,MibSPI DMA7COUNT Register"
hexmask.long.word 0x1C 16.--31. 1. " ICOUNT7 ,Initial number of DMA transfers"
hexmask.long.word 0x1C 0.--15. 1. " COUNT7 ,The actual number of remaining DMA transfers"
textline " "
group.long 0x118++0x03
line.long 0x00 "DMACNTLEN,MibSPI DMACNTLEN Register"
bitfld.long 0x00 0. " LARGECOUNT ,Counters select" "DMAxCTRL,DMAxCOUNT"
group.long 0x120++0x03
line.long 0x00 "UERRCTRL,Uncorrectable Parity Error Control Register"
sif cpu()=="TMS570LC4357"
bitfld.long 0x00 24.--27. " SBE_EVT_EN ,ECC Single Bit Error Event Enable" ",,,,,Disabled,,,,,Enabled,?..."
bitfld.long 0x00 16.--19. " EDAC_MODE ,ECC Single Bit Error Block Correction" ",,,,,Disabled,,,,,Enabled,?..."
textline " "
endif
bitfld.long 0x00 8. " PTESTEN ,Parity memory test enable" "Disabled,Enabled"
bitfld.long 0x00 0.--3. " EDEN ,Error detection enable" "Enabled,Enabled,Enabled,Enabled,Enabled,Disabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled"
group.long 0x124++0x03
line.long 0x00 "UERRSTAT,Uncorrectable Parity Error Status Register"
sif cpu()=="TMS570LC4357"
eventfld.long 0x00 9. " SBE_FLG1 ,Single Bit Error in RXRAM" "Not occurred,Occurred"
eventfld.long 0x00 8. " SBE_FLG0 ,Single Bit Error in TXRAM" "Not occurred,Occurred"
textline " "
eventfld.long 0x00 1. " EDFLG1 ,Uncorrectable parity error detection flag" "Not occurred,Occurred"
eventfld.long 0x00 0. " EDFLG0 ,Uncorrectable parity error detection flag" "Not occurred,Occurred"
else
eventfld.long 0x00 1. " EDFLG1 ,Uncorrectable parity error detection flag" "Not occurred,Occurred"
eventfld.long 0x00 0. " EDFLG0 ,Uncorrectable parity error detection flag" "Not occurred,Occurred"
endif
width 17.
hgroup.long 0x128++0x03
hide.long 0x00 "UERRADDR1,Uncorrectable Parity Error Address Register"
in
hgroup.long 0x12C++0x03
hide.long 0x00 "UERRADDR0,Uncorrectable Parity Error Address Register"
in
hgroup.long 0x130++0x03
hide.long 0x00 "RXOVRN_BUF_ADDR,Receive RAM Overrun Buffer Address Register"
in
textline " "
width 14.
if (((d.l(ad:0xFFF7F400+0x134))&0x2)==0x2)&&(((d.l(ad:0xFFF7F400+0x134))&0xF00)==0xA00)
group.long 0x134++0x03
line.long 0x00 "IOLPBKTSTCR,SPI IO Loopback Test Control Register"
bitfld.long 0x00 24. " SCSFAILFLG ,Failure on SPISCS pin compare during analog loopback" "Not occurred,Occurred"
bitfld.long 0x00 20. " CTRL_BITERR ,Controls inducing of BITERR during I/O loopback test mode" "Disabled,Enabled"
bitfld.long 0x00 19. " CTRL_DESYNC ,Controls inducing of the desync error during I/O loopback test mode" "No error,Error"
textline " "
bitfld.long 0x00 18. " CTRL_PARERR ,Controls inducing of parity errors during I/O loopback test mode" "No error,Error"
bitfld.long 0x00 17. " CTRL_TIMEOUT ,Controls inducing of the timeout error during I/O loopbacK test mode" "No error,Error"
bitfld.long 0x00 16. " CTRL_DLENERR ,Controls inducing of the data length error during I/O loopback test mode" "No error,Error"
textline " "
bitfld.long 0x00 8.--11. " IOLPBKTSTENA ,Module I/O loopback test enable key" "Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Enabled,Disabled,Disabled,Disabled,Disabled,Disabled"
bitfld.long 0x00 3.--5. " ERRSCSPIN ,Inject error on chip-select pin number" "/SPISCS[0],/SPISCS[1],/SPISCS[2],/SPISCS[3],/SPISCS[4],/SPISCS[5],/SPISCS[6],/SPISCS[7]"
bitfld.long 0x00 2. " CTRLSCSPINERR ,Enable/disable the injection of an error on the SPISCS[3:0] pins" "Disabled,Enabled"
textline " "
bitfld.long 0x00 1. " LPBK_TYPE ,Module I/O loopback type (analog/digital)" "Digital,Analog"
bitfld.long 0x00 0. " RXP_ENA ,Enable analog loopback through the receive pin" "Transmit,Receive"
elif (((d.l(ad:0xFFF7F400+0x134))&0x2)==0x0)&&(((d.l(ad:0xFFF7F400+0x134))&0xF00)==0xA00)
group.long 0x134++0x03
line.long 0x00 "IOLPBKTSTCR,SPI IO Loopback Test Control Register"
eventfld.long 0x00 24. " SCSFAILFLG ,Failure on SPISCS pin compare during analog loopback" "Not occurred,Occurred"
bitfld.long 0x00 20. " CTRL_BITERR ,Controls inducing of BITERR during I/O loopback test mode" "Disabled,Enabled"
bitfld.long 0x00 19. " CTRL_DESYNC ,Controls inducing of the desync error during I/O loopback test mode" "No error,Error"
textline " "
bitfld.long 0x00 18. " CTRL_PARERR ,Controls inducing of parity errors during I/O loopback test mode" "No error,Error"
bitfld.long 0x00 17. " CTRL_TIMEOUT ,Controls inducing of the timeout error during I/O loopbacK test mode" "No error,Error"
bitfld.long 0x00 16. " CTRL_DLENERR ,Controls inducing of the data length error during I/O loopback test mode" "No error,Error"
textline " "
bitfld.long 0x00 8.--11. " IOLPBKTSTENA ,Module I/O loopback test enable key" "Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Enabled,Disabled,Disabled,Disabled,Disabled,Disabled"
bitfld.long 0x00 3.--5. " ERRSCSPIN ,Inject error on chip-select pin number" "/SPISCS[0],/SPISCS[1],/SPISCS[2],/SPISCS[3],/SPISCS[4],/SPISCS[5],/SPISCS[6],/SPISCS[7]"
bitfld.long 0x00 2. " CTRLSCSPINERR ,Enable/disable the injection of an error on the SPISCS[3:0] pins" "Disabled,Enabled"
textline " "
bitfld.long 0x00 1. " LPBK_TYPE ,Module I/O loopback type (analog/digital)" "Digital,Analog"
elif (((d.l(ad:0xFFF7F400+0x134))&0x2)==0x2)&&(((d.l(ad:0xFFF7F400+0x134))&0xF00)!=0xA00)
group.long 0x134++0x03
line.long 0x00 "IOLPBKTSTCR,SPI IO Loopback Test Control Register"
bitfld.long 0x00 8.--11. " IOLPBKTSTENA ,Module I/O loopback test enable key" "Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Enabled,Disabled,Disabled,Disabled,Disabled,Disabled"
bitfld.long 0x00 3.--5. " ERRSCSPIN ,Inject error on chip-select pin number" "/SPISCS[0],/SPISCS[1],/SPISCS[2],/SPISCS[3],/SPISCS[4],/SPISCS[5],/SPISCS[6],/SPISCS[7]"
bitfld.long 0x00 2. " CTRLSCSPINERR ,Enable/disable the injection of an error on the SPISCS[3:0] pins" "Disabled,Enabled"
textline " "
bitfld.long 0x00 1. " LPBK_TYPE ,Module I/O loopback type (analog/digital)" "Digital,Analog"
bitfld.long 0x00 0. " RXP_ENA ,Enable analog loopback through the receive pin" "Transmit,Receive"
else
group.long 0x134++0x03
line.long 0x00 "IOLPBKTSTCR,SPI IO Loopback Test Control Register"
bitfld.long 0x00 8.--11. " IOLPBKTSTENA ,Module I/O loopback test enable key" "Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Enabled,Disabled,Disabled,Disabled,Disabled,Disabled"
bitfld.long 0x00 3.--5. " ERRSCSPIN ,Inject error on chip-select pin number" "/SPISCS[0],/SPISCS[1],/SPISCS[2],/SPISCS[3],/SPISCS[4],/SPISCS[5],/SPISCS[6],/SPISCS[7]"
bitfld.long 0x00 2. " CTRLSCSPINERR ,Enable/disable the injection of an error on the SPISCS[3:0] pins" "Disabled,Enabled"
textline " "
bitfld.long 0x00 1. " LPBK_TYPE ,Module I/O loopback type (analog/digital)" "Digital,Analog"
endif
textline " "
width 21.
group.long 0x138++0x07
line.long 0x00 "EXTENDED_PRESCALE_1,SPI Extended Prescale Register 1"
hexmask.long.word 0x00 16.--26. 1. " EPRESCALE_FMT1 ,Extended Prescale value for SPIFMT1"
hexmask.long.word 0x00 0.--10. 1. " EPRESCALE_FMT0 ,Extended Prescale value for SPIFMT0"
line.long 0x04 "EXTENDED_PRESCALE_2,SPI Extended Prescale Register 2"
hexmask.long.word 0x04 16.--26. 1. " EPRESCALE_FMT3 ,Extended Prescale value for SPIFMT3"
hexmask.long.word 0x04 0.--10. 1. " EPRESCALE_FMT2 ,Extended Prescale value for SPIFMT2"
sif cpu()!="TMS570LC4357"
group.long 0x140++0x03
line.long 0x00 "ECCDIAG_CTRL,ECC Diagnostic Control register"
bitfld.long 0x00 0.--3. " ECCDIAG_EN ,ECC Diagnostic mode Enable Key bits" "Disabled,Disabled,Disabled,Disabled,Disabled,Enabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled"
endif
if ((d.l(ad:0xFFF7F400+0x140)&0x5)==0x5)
group.long 0x144++0x03
line.long 0x00 "ECCDIAG_STAT, ECC Diagnostic Status Register"
eventfld.long 0x00 17. " DEFLG[1] ,Double bit Error is detected for RXRAM" "No error,Error"
eventfld.long 0x00 16. " DEFLG[0] ,Double bit Error is detected for TXRAM" "No error,Error"
eventfld.long 0x00 1. " SEFLG[1] ,Single bit Error is detected for RXRAM" "No error,Error"
eventfld.long 0x00 0. " SEFLG[0] ,Single bit Error is detected for TXRAM" "No error,Error"
else
hgroup.long 0x144++0x03
hide.long 0x00 "ECCDIAG_STAT,ECC Diagnostic Status Register"
in
endif
hgroup.long 0x148++0x03
hide.long 0x00 "SBERRADDR1,Single Bit Error Address Register - RXRAM"
in
hgroup.long 0x14C++0x03
hide.long 0x00 "SBERRADDR0,Single Bit Error Address Register - TXRAM"
in
tree.end
tree "MibSPI2"
base ad:0xFFF7F600
width 17.
group.long 0x00++0x03
line.long 0x00 "SPIGCR0,SPI Global Control Register 0"
bitfld.long 0x00 0. " NRESET ,Reset bit for the module" "No reset,Reset"
if (((d.l(ad:0xFFF7F600+0x4))&0x3)==0x00)
group.long 0x04++0x03
line.long 0x00 "SPIGCR1,SPI Global Control Register 1"
bitfld.long 0x00 24. " SPIEN ,SPI enable" "Disabled,Enabled"
bitfld.long 0x00 16. " LOOPBACK ,Internal loop-back test mode" "Disabled,Enabled"
bitfld.long 0x00 8. " POWERDOWN ,SPI state machine enters a power-down state" "No power-down,Power-down"
textline " "
bitfld.long 0x00 1. " CLKMOD ,Clock mode" "External,Internally"
bitfld.long 0x00 0. " MASTER ,SPISIMO/SPISOMI pin direction determination" "Input/ouput,Output/input"
else
group.long 0x04++0x03
line.long 0x00 "SPIGCR1,SPI Global Control Register 1"
bitfld.long 0x00 24. " SPIEN ,SPI enable" "Disabled,Enabled"
bitfld.long 0x00 8. " POWERDOWN ,SPI state machine enters a power-down state" "No power-down,Power-down"
bitfld.long 0x00 1. " CLKMOD ,Clock mode" "External,Internally"
textline " "
bitfld.long 0x00 0. " MASTER ,SPISIMO/SPISOMI pin direction determination" "Input/ouput,Output/input"
endif
group.long 0x08++0x03
line.long 0x00 "SPIINT0,SPI Interrupt Register"
bitfld.long 0x00 24. " ENABLEHIGHZ ,SPIENA pin high-impedance enable" "Inactive,Active"
bitfld.long 0x00 16. " DMAREQEN ,DMA request enable" "Disabled,Enabled"
bitfld.long 0x00 9. " TXINTENA ,TX interrupt flag enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 8. " RXINTENA ,RX interrupt flag enable" "Disabled,Enabled"
bitfld.long 0x00 6. " RXOVRNINTENA ,Overrun interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 4. " BITERRENA ,Enables interrupt on bit error" "Disabled,Enabled"
textline " "
bitfld.long 0x00 3. " DESYNCENA ,Enables interrupt on desynchronized slave" "Disabled,Enabled"
bitfld.long 0x00 2. " PARERRENA ,Enables interrupt-on-parity-error" "Disabled,Enabled"
bitfld.long 0x00 1. " TIMEOUTENA ,Enables interrupt on ENA signal time-out" "Disabled,Enabled"
textline " "
bitfld.long 0x00 0. " DLENERRENA ,Data length error interrupt enable" "Disabled,Enabled"
group.long 0x0C++0x03
line.long 0x00 "SPILVL,SPI Interrupt Level Register"
bitfld.long 0x00 9. " TXINTLVL ,Transmit interrupt level" "INT0,INT1"
bitfld.long 0x00 8. " RXINTLVL ,Receive interrupt level" "INT0,INT1"
bitfld.long 0x00 6. " RXOVRNINTLVL ,Receive overrun interrupt level" "INT0,INT1"
textline " "
bitfld.long 0x00 4. " BITERRLVL ,Bit error interrupt level" "INT0,INT1"
bitfld.long 0x00 3. " DESYNCLVL ,Desynchronized slave interrupt level (master mode only)" "INT0,INT1"
bitfld.long 0x00 2. " PARERRLVL ,Parity error interrupt level" "INT0,INT1"
textline " "
bitfld.long 0x00 1. " TIMEOUTLVL ,SPIENA pin time-out interrupt level" "INT0,INT1"
bitfld.long 0x00 0. " DLENERRLVL ,Data length error interrupt level (line) select" "INT0,INT1"
group.long 0x10++0x03
line.long 0x00 "SPIFLG,SPI Flag Register"
rbitfld.long 0x00 24. " BUFINITACTIVE ,Indicates the status of multi-buffer initialization process" "Completed,Not completed"
rbitfld.long 0x00 9. " TXINTFLG ,Transmitter-empty interrupt flag" "No interrupt,Interrupt"
eventfld.long 0x00 8. " RXINTFLG ,Receiver-full interrupt flag" "No interrupt,Interrupt"
textline " "
eventfld.long 0x00 6. " RXOVRNINTFLG ,Overrun interrupt enable" "Disabled,Enabled"
eventfld.long 0x00 4. " BITERRFLG ,Enables interrupt on bit error" "Disabled,Enabled"
eventfld.long 0x00 3. " DESYNCFLG ,Enables interrupt on desynchronized slave" "No interrupt,Interrupt"
textline " "
eventfld.long 0x00 2. " PARITYERRFLG ,Enables interrupt-on-parity-error" "No error,Error"
eventfld.long 0x00 1. " TIMEOUTFLG ,Enables interrupt on ENA signal time-out" "No interrupt,Interrupt"
eventfld.long 0x00 0. " DLENERRFLG ,Data length error interrupt enable" "No interrupt,Interrupt"
textline " "
width 12.
group.long 0x14++0x23
line.long 0x00 "SPIPC0,SPI Pin Control Register 0"
bitfld.long 0x00 31. " SOMIFUN[7] ,SPISOMI[7] pin function" "GIO,SPI"
bitfld.long 0x00 30. " [6] ,SPISOMI[6] pin function" "GIO,SPI"
bitfld.long 0x00 29. " [5] ,SPISOMI[5] pin function" "GIO,SPI"
bitfld.long 0x00 28. " [4] ,SPISOMI[4] pin function" "GIO,SPI"
textline " "
bitfld.long 0x00 27. " [3] ,SPISOMI[3] pin function" "GIO,SPI"
bitfld.long 0x00 26. " [2] ,SPISOMI[2] pin function" "GIO,SPI"
bitfld.long 0x00 25. " [1] ,SPISOMI[1] pin function" "GIO,SPI"
bitfld.long 0x00 24. " [0] ,SPISOMI[0] pin function (mirror of bit 11)" "GIO,SPI"
textline " "
bitfld.long 0x00 23. " SIMOFUN[7] ,SPISIMO[7] pin function" "GIO,SPI"
bitfld.long 0x00 22. " [6] ,SPISIMO[6] pin function" "GIO,SPI"
bitfld.long 0x00 21. " [5] ,SPISIMO[5] pin function" "GIO,SPI"
bitfld.long 0x00 20. " [4] ,SPISIMO[4] pin function" "GIO,SPI"
textline " "
bitfld.long 0x00 19. " [3] ,SPISIMO[3] pin function" "GIO,SPI"
bitfld.long 0x00 18. " [2] ,SPISIMO[2] pin function" "GIO,SPI"
bitfld.long 0x00 17. " [1] ,SPISIMO[1] pin function" "GIO,SPI"
bitfld.long 0x00 16. " [0] ,SPISIMO[0] pin function (mirror of bit 10)" "GIO,SPI"
textline " "
bitfld.long 0x00 11. " SOMIFUN[0] ,SPISOMI[0] pin function" "GIO,SPI"
bitfld.long 0x00 10. " SIMOFUN[0] ,SPISIMO[0] pin function" "GIO,SPI"
bitfld.long 0x00 9. " CLKFUN ,SPI clock function" "GIO,SPI"
bitfld.long 0x00 8. " ENAFUN ,SPIENA function" "GIO,SPI"
textline " "
textline " "
bitfld.long 0x00 7. " SCSFUN[7] ,SPISCS7 function 7" "GIO,SPI"
bitfld.long 0x00 6. " [6] ,SPISCS6 function 6" "GIO,SPI"
bitfld.long 0x00 5. " [5] ,SPISCS5 function 5" "GIO,SPI"
bitfld.long 0x00 4. " [4] ,SPISCS4 function 4" "GIO,SPI"
textline " "
bitfld.long 0x00 3. " [3] ,SPISCS3 function 3" "GIO,SPI"
bitfld.long 0x00 2. " [2] ,SPISCS2 function 2" "GIO,SPI"
bitfld.long 0x00 1. " [1] ,SPISCS1 function 1" "GIO,SPI"
bitfld.long 0x00 0. " [0] ,SPISCS0 function 0" "GIO,SPI"
textline " "
line.long 0x04 "SPIPC1,SPI Pin Control Register 1"
bitfld.long 0x04 31. " SOMIDIR[7] ,SPISOMI[7] pin direction" "GIO,SPI"
bitfld.long 0x04 30. " [6] ,SPISOMI[6] pin direction" "GIO,SPI"
bitfld.long 0x04 29. " [5] ,SPISOMI[5] pin direction" "GIO,SPI"
bitfld.long 0x04 28. " [4] ,SPISOMI[4] pin direction" "GIO,SPI"
textline " "
bitfld.long 0x04 27. " [3] ,SPISOMI[3] pin direction" "GIO,SPI"
bitfld.long 0x04 26. " [2] ,SPISOMI[2] pin direction" "GIO,SPI"
bitfld.long 0x04 25. " [1] ,SPISOMI[1] pin direction" "GIO,SPI"
bitfld.long 0x04 24. " [0] ,SPISOMI[0] pin direction (mirror of bit 11)" "GIO,SPI"
textline " "
bitfld.long 0x04 23. " SIMODIR[7] ,SPISIMO[7] pin direction" "GIO,SPI"
bitfld.long 0x04 22. " [6] ,SPISIMO[6] pin direction" "GIO,SPI"
bitfld.long 0x04 21. " [5] ,SPISIMO[5] pin direction" "GIO,SPI"
bitfld.long 0x04 20. " [4] ,SPISIMO[4] pin direction" "GIO,SPI"
textline " "
bitfld.long 0x04 19. " [3] ,SPISIMO[3] pin direction" "GIO,SPI"
bitfld.long 0x04 18. " [2] ,SPISIMO[2] pin direction" "GIO,SPI"
bitfld.long 0x04 17. " [1] ,SPISIMO[1] pin direction" "GIO,SPI"
bitfld.long 0x04 16. " [0] ,SPISIMO[0] pin direction (mirror of bit 10)" "GIO,SPI"
textline " "
bitfld.long 0x04 11. " SOMIDIR[0] ,SPISOMI[0] pin direction" "GIO,SPI"
bitfld.long 0x04 10. " SIMODIR[0] ,SPISIMO[0] pin direction" "GIO,SPI"
bitfld.long 0x04 9. " CLKDIR ,SPI clock direction" "GIO,SPI"
bitfld.long 0x04 8. " ENADIR ,SPIENA direction" "GIO,SPI"
textline " "
textline " "
bitfld.long 0x04 7. " SCSDIR[7] ,SPISCS7 direction 7" "GIO,SPI"
bitfld.long 0x04 6. " [6] ,SPISCS6 direction 6" "GIO,SPI"
bitfld.long 0x04 5. " [5] ,SPISCS5 direction 5" "GIO,SPI"
bitfld.long 0x04 4. " [4] ,SPISCS4 direction 4" "GIO,SPI"
textline " "
bitfld.long 0x04 3. " [3] ,SPISCS3 direction 3" "GIO,SPI"
bitfld.long 0x04 2. " [2] ,SPISCS2 direction 2" "GIO,SPI"
bitfld.long 0x04 1. " [1] ,SPISCS1 direction 1" "GIO,SPI"
bitfld.long 0x04 0. " [0] ,SPISCS0 direction 0" "GIO,SPI"
textline " "
line.long 0x08 "SPIPC2,SPI Pin Control Register 2"
bitfld.long 0x08 31. " SOMIDIN[7] ,SPISOMI[7] data in" "0,1"
bitfld.long 0x08 30. " [6] ,SPISOMI[6] data in" "0,1"
bitfld.long 0x08 29. " [5] ,SPISOMI[5] data in" "0,1"
bitfld.long 0x08 28. " [4] ,SPISOMI[4] data in" "0,1"
bitfld.long 0x08 27. " [3] ,SPISOMI[3] data in" "0,1"
bitfld.long 0x08 26. " [2] ,SPISOMI[2] data in" "0,1"
bitfld.long 0x08 25. " [1] ,SPISOMI[1] data in" "0,1"
bitfld.long 0x08 24. " [0] ,SPISOMI[0] data in (mirror of bit 11)" "0,1"
textline " "
bitfld.long 0x08 23. " SIMODIN[7] ,SPISIMO[7] data in" "0,1"
bitfld.long 0x08 22. " [6] ,SPISIMO[6] data in" "0,1"
bitfld.long 0x08 21. " [5] ,SPISIMO[5] data in" "0,1"
bitfld.long 0x08 20. " [4] ,SPISIMO[4] data in" "0,1"
bitfld.long 0x08 19. " [3] ,SPISIMO[3] data in" "0,1"
bitfld.long 0x08 18. " [2] ,SPISIMO[2] data in" "0,1"
bitfld.long 0x08 17. " [1] ,SPISIMO[1] data in" "0,1"
bitfld.long 0x08 16. " [0] ,SPISIMO[0] data in (mirror of bit 10)" "0,1"
textline " "
bitfld.long 0x08 11. " SOMIDIN[0] ,SPISOMI[0] data in" "0,1"
bitfld.long 0x08 10. " SIMODIN[0] ,SPISIMO[0] data in" "0,1"
bitfld.long 0x08 9. " CLKDIN ,SPI clock data in" "0,1"
bitfld.long 0x08 8. " ENADIN ,SPIENA data in" "0,1"
textline " "
textline " "
bitfld.long 0x08 7. " SCSDIN[7] ,SPISCS7 data in" "0,1"
bitfld.long 0x08 6. " [6] ,SPISCS6 data in" "0,1"
bitfld.long 0x08 5. " [5] ,SPISCS5 data in" "0,1"
bitfld.long 0x08 4. " [4] ,SPISCS4 data in" "0,1"
bitfld.long 0x08 3. " [3] ,SPISCS3 data in" "0,1"
bitfld.long 0x08 2. " [2] ,SPISCS2 data in" "0,1"
bitfld.long 0x08 1. " [1] ,SPISCS1 data in" "0,1"
bitfld.long 0x08 0. " [0] ,SPISCS0 direction 0" "0,1"
textline " "
line.long 0x0C "SPIPC3,SPI Pin Control Register 3"
bitfld.long 0x0C 31. " SOMIDOUT[7] ,SPISOMI[7] data out write" "0,1"
bitfld.long 0x0C 30. " [6] ,SPISOMI[6] data out write" "0,1"
bitfld.long 0x0C 29. " [5] ,SPISOMI[5] data out write" "0,1"
bitfld.long 0x0C 28. " [4] ,SPISOMI[4] data out write" "0,1"
bitfld.long 0x0C 27. " [3] ,SPISOMI[3] data out write" "0,1"
bitfld.long 0x0C 26. " [2] ,SPISOMI[2] data out write" "0,1"
bitfld.long 0x0C 25. " [1] ,SPISOMI[1] data out write" "0,1"
bitfld.long 0x0C 24. " [0] ,SPISOMI[0] data out write (mirror of bit 11)" "0,1"
textline " "
bitfld.long 0x0C 23. " SIMODOUT[7] ,SPISIMO[7] data out write" "0,1"
bitfld.long 0x0C 22. " [6] ,SPISIMO[6] data out write" "0,1"
bitfld.long 0x0C 21. " [5] ,SPISIMO[5] data out write" "0,1"
bitfld.long 0x0C 20. " [4] ,SPISIMO[4] data out write" "0,1"
bitfld.long 0x0C 19. " [3] ,SPISIMO[3] data out write" "0,1"
bitfld.long 0x0C 18. " [2] ,SPISIMO[2] data out write" "0,1"
bitfld.long 0x0C 17. " [1] ,SPISIMO[1] data out write" "0,1"
bitfld.long 0x0C 16. " [0] ,SPISIMO[0] data out write (mirror of bit 10)" "0,1"
textline " "
bitfld.long 0x0C 11. " SOMIDOUT[0] ,SPISOMI[0] data out write" "0,1"
bitfld.long 0x0C 10. " SIMODOUT[0] ,SPISIMO[0] data out write" "0,1"
bitfld.long 0x0C 9. " CLKDOUT ,SPI clock data out write" "0,1"
bitfld.long 0x0C 8. " ENADOUT ,SPIENA data out write" "0,1"
textline " "
textline " "
bitfld.long 0x0C 7. " SCSDOUT[7] ,SPISCS7 data out write" "0,1"
bitfld.long 0x0C 6. " [6] ,SPISCS6 data out write" "0,1"
bitfld.long 0x0C 5. " [5] ,SPISCS5 data out write" "0,1"
bitfld.long 0x0C 4. " [4] ,SPISCS4 data out write" "0,1"
bitfld.long 0x0C 3. " [3] ,SPISCS3 data out write" "0,1"
bitfld.long 0x0C 2. " [2] ,SPISCS2 data out write" "0,1"
bitfld.long 0x0C 1. " [1] ,SPISCS1 data out write" "0,1"
bitfld.long 0x0C 0. " [0] ,SPISCS0 data out write" "0,1"
textline " "
line.long 0x10 "SPIPC4,SPI Pin Control Register 4"
bitfld.long 0x10 31. " SOMISET[7] ,SPISOMI[7] data out set" "0,1"
bitfld.long 0x10 30. " [6] ,SPISOMI[6] data out set" "0,1"
bitfld.long 0x10 29. " [5] ,SPISOMI[5] data out set" "0,1"
bitfld.long 0x10 28. " [4] ,SPISOMI[4] data out set" "0,1"
bitfld.long 0x10 27. " [3] ,SPISOMI[3] data out set" "0,1"
bitfld.long 0x10 26. " [2] ,SPISOMI[2] data out set" "0,1"
bitfld.long 0x10 25. " [1] ,SPISOMI[1] data out set" "0,1"
bitfld.long 0x10 24. " [0] ,SPISOMI[0] data out set (mirror of bit 11)" "0,1"
textline " "
bitfld.long 0x10 23. " SIMOSET[7] ,SPISIMO[7] data out set" "0,1"
bitfld.long 0x10 22. " [6] ,SPISIMO[6] data out set" "0,1"
bitfld.long 0x10 21. " [5] ,SPISIMO[5] data out set" "0,1"
bitfld.long 0x10 20. " [4] ,SPISIMO[4] data out set" "0,1"
bitfld.long 0x10 19. " [3] ,SPISIMO[3] data out set" "0,1"
bitfld.long 0x10 18. " [2] ,SPISIMO[2] data out set" "0,1"
bitfld.long 0x10 17. " [1] ,SPISIMO[1] data out set" "0,1"
bitfld.long 0x10 16. " [0] ,SPISIMO[0] data out set (mirror of bit 10)" "0,1"
textline " "
bitfld.long 0x10 11. " SOMISET[0] ,SPISOMI[0] data out set" "0,1"
bitfld.long 0x10 10. " SIMOSET[0] ,SPISIMO[0] data out set" "0,1"
bitfld.long 0x10 9. " CLKSET ,SPI clock data out set" "0,1"
bitfld.long 0x10 8. " ENASET ,SPIENA data out set" "0,1"
textline " "
textline " "
bitfld.long 0x10 7. " SCSSET[7] ,SPISCS7 data out set" "0,1"
bitfld.long 0x10 6. " [6] ,SPISCS6 data out set" "0,1"
bitfld.long 0x10 5. " [5] ,SPISCS5 data out set" "0,1"
bitfld.long 0x10 4. " [4] ,SPISCS4 data out set" "0,1"
bitfld.long 0x10 3. " [3] ,SPISCS3 data out set" "0,1"
bitfld.long 0x10 2. " [2] ,SPISCS2 data out set" "0,1"
bitfld.long 0x10 1. " [1] ,SPISCS1 data out set" "0,1"
bitfld.long 0x10 0. " [0] ,SPISCS0 data out set" "0,1"
textline " "
line.long 0x14 "SPIPC5,SPI Pin Control Register 5"
bitfld.long 0x14 31. " SOMICLR[7] ,SPISOMI[7] data out clear" "0,1"
bitfld.long 0x14 30. " [6] ,SPISOMI[6] data out clear" "0,1"
bitfld.long 0x14 29. " [5] ,SPISOMI[5] data out clear" "0,1"
bitfld.long 0x14 28. " [4] ,SPISOMI[4] data out clear" "0,1"
bitfld.long 0x14 27. " [3] ,SPISOMI[3] data out clear" "0,1"
bitfld.long 0x14 26. " [2] ,SPISOMI[2] data out clear" "0,1"
bitfld.long 0x14 25. " [1] ,SPISOMI[1] data out clear" "0,1"
bitfld.long 0x14 24. " [0] ,SPISOMI[0] data out clear (mirror of bit 11)" "0,1"
textline " "
bitfld.long 0x14 23. " SIMOCLR[7] ,SPISIMO[7] data out clear" "0,1"
bitfld.long 0x14 22. " [6] ,SPISIMO[6] data out clear" "0,1"
bitfld.long 0x14 21. " [5] ,SPISIMO[5] data out clear" "0,1"
bitfld.long 0x14 20. " [4] ,SPISIMO[4] data out clear" "0,1"
bitfld.long 0x14 19. " [3] ,SPISIMO[3] data out clear" "0,1"
bitfld.long 0x14 18. " [2] ,SPISIMO[2] data out clear" "0,1"
bitfld.long 0x14 17. " [1] ,SPISIMO[1] data out clear" "0,1"
bitfld.long 0x14 16. " [0] ,SPISIMO[0] data out clear (mirror of bit 10)" "0,1"
textline " "
bitfld.long 0x14 11. " SOMICLR[0] ,SPISOMI[0] data out clear" "0,1"
bitfld.long 0x14 10. " SIMOCLR[0] ,SPISIMO[0] data out clear" "0,1"
bitfld.long 0x14 9. " CLKCLR ,SPI clock data out clear" "0,1"
bitfld.long 0x14 8. " ENACLR ,SPIENA data out clear" "0,1"
textline " "
textline " "
bitfld.long 0x14 7. " SCSCLR[7] ,SPISCS7 data out clear" "0,1"
bitfld.long 0x14 6. " [6] ,SPISCS6 data out clear" "0,1"
bitfld.long 0x14 5. " [5] ,SPISCS5 data out clear" "0,1"
bitfld.long 0x14 4. " [4] ,SPISCS4 data out clear" "0,1"
bitfld.long 0x14 3. " [3] ,SPISCS3 data out clear" "0,1"
bitfld.long 0x14 2. " [2] ,SPISCS2 data out clear" "0,1"
bitfld.long 0x14 1. " [1] ,SPISCS1 data out clear" "0,1"
bitfld.long 0x14 0. " [0] ,SPISCS0 data out clear" "0,1"
textline " "
line.long 0x18 "SPIPC6,SPI Pin Control Register 6"
bitfld.long 0x18 31. " SOMIPDR[7] ,SPISOMI[7] open drain enable" "Disabled,Enabled"
bitfld.long 0x18 30. " [6] ,SPISOMI[6] open drain enable" "Disabled,Enabled"
bitfld.long 0x18 29. " [5] ,SPISOMI[5] open drain enable" "Disabled,Enabled"
bitfld.long 0x18 28. " [4] ,SPISOMI[4] open drain enable" "Disabled,Enabled"
textline " "
bitfld.long 0x18 27. " [3] ,SPISOMI[3] open drain enable" "Disabled,Enabled"
bitfld.long 0x18 26. " [2] ,SPISOMI[2] open drain enable" "Disabled,Enabled"
bitfld.long 0x18 25. " [1] ,SPISOMI[1] open drain enable" "Disabled,Enabled"
bitfld.long 0x18 24. " [0] ,SPISOMI[0] open drain enable (mirror of bit 11)" "Disabled,Enabled"
textline " "
bitfld.long 0x18 23. " SIMOPDR[7] ,SPISIMO[7] open drain enable" "Disabled,Enabled"
bitfld.long 0x18 22. " [6] ,SPISIMO[6] open drain enable" "Disabled,Enabled"
bitfld.long 0x18 21. " [5] ,SPISIMO[5] open drain enable" "Disabled,Enabled"
bitfld.long 0x18 20. " [4] ,SPISIMO[4] open drain enable" "Disabled,Enabled"
textline " "
bitfld.long 0x18 19. " [3] ,SPISIMO[3] open drain enable" "Disabled,Enabled"
bitfld.long 0x18 18. " [2] ,SPISIMO[2] open drain enable" "Disabled,Enabled"
bitfld.long 0x18 17. " [1] ,SPISIMO[1] open drain enable" "Disabled,Enabled"
bitfld.long 0x18 16. " [0] ,SPISIMO[0] open drain enable (mirror of bit 10)" "Disabled,Enabled"
textline " "
bitfld.long 0x18 11. " SOMIPDR[0] ,SPISOMI[0] open drain enable" "Disabled,Enabled"
bitfld.long 0x18 10. " SIMOPDR[0] ,SPISIMO[0] open drain enable" "Disabled,Enabled"
bitfld.long 0x18 9. " CLKPDR ,SPI clock open drain enable" "Disabled,Enabled"
bitfld.long 0x18 8. " ENAPDR ,SPIENA open drain enable" "Disabled,Enabled"
textline " "
textline " "
bitfld.long 0x18 7. " SCSPDR[7] ,SPISCS7 open drain enable" "Disabled,Enabled"
bitfld.long 0x18 6. " [6] ,SPISCS6 open drain enable" "Disabled,Enabled"
bitfld.long 0x18 5. " [5] ,SPISCS5 open drain enable" "Disabled,Enabled"
bitfld.long 0x18 4. " [4] ,SPISCS4 open drain enable" "Disabled,Enabled"
textline " "
bitfld.long 0x18 3. " [3] ,SPISCS3 open drain enable" "Disabled,Enabled"
bitfld.long 0x18 2. " [2] ,SPISCS2 open drain enable" "Disabled,Enabled"
bitfld.long 0x18 1. " [1] ,SPISCS1 open drain enable" "Disabled,Enabled"
bitfld.long 0x18 0. " [0] ,SPISCS0 open drain enable" "Disabled,Enabled"
textline " "
line.long 0x1C "SPIPC7,SPI Pin Control Register 7"
bitfld.long 0x1C 31. " SOMIPDIS[7] ,SPISOMI[7] pull control enable/disable" "No,Yes"
bitfld.long 0x1C 30. " [6] ,SPISOMI[6] pull control enable/disable" "No,Yes"
bitfld.long 0x1C 29. " [5] ,SPISOMI[5] pull control enable/disable" "No,Yes"
bitfld.long 0x1C 28. " [4] ,SPISOMI[4] pull control enable/disable" "No,Yes"
textline " "
bitfld.long 0x1C 27. " [3] ,SPISOMI[3] pull control enable/disable" "No,Yes"
bitfld.long 0x1C 26. " [2] ,SPISOMI[2] pull control enable/disable" "No,Yes"
bitfld.long 0x1C 25. " [1] ,SPISOMI[1] pull control enable/disable" "No,Yes"
bitfld.long 0x1C 24. " [0] ,SPISOMI[0] pull control enable/disable (mirror of bit 11)" "No,Yes"
textline " "
bitfld.long 0x1C 23. " SIMOPDIS[7] ,SPISIMO[7] pull control enable/disable" "No,Yes"
bitfld.long 0x1C 22. " [6] ,SPISIMO[6] pull control enable/disable" "No,Yes"
bitfld.long 0x1C 21. " [5] ,SPISIMO[5] pull control enable/disable" "No,Yes"
bitfld.long 0x1C 20. " [4] ,SPISIMO[4] pull control enable/disable" "No,Yes"
textline " "
bitfld.long 0x1C 19. " [3] ,SPISIMO[3] pull control enable/disable" "No,Yes"
bitfld.long 0x1C 18. " [2] ,SPISIMO[2] pull control enable/disable" "No,Yes"
bitfld.long 0x1C 17. " [1] ,SPISIMO[1] pull control enable/disable" "No,Yes"
bitfld.long 0x1C 16. " [0] ,SPISIMO[0] pull control enable/disable (mirror of bit 10)" "No,Yes"
textline " "
bitfld.long 0x1C 11. " SOMIPDIS[0] ,SPISOMI[0] pull control enable/disable" "No,Yes"
bitfld.long 0x1C 10. " SIMOPDIS[0] ,SPISIMO[0] pull control enable/disable" "No,Yes"
bitfld.long 0x1C 9. " CLKPDIS ,SPI clock pull control enable/disable" "No,Yes"
bitfld.long 0x1C 8. " ENAPDIS ,SPIENA pull control enable/disable" "No,Yes"
textline " "
textline " "
bitfld.long 0x1C 7. " SCSPDIS[7] ,SPISCS7 pull control enable/disable" "No,Yes"
bitfld.long 0x1C 6. " [6] ,SPISCS6 pull control enable/disable" "No,Yes"
bitfld.long 0x1C 5. " [5] ,SPISCS5 pull control enable/disable" "No,Yes"
bitfld.long 0x1C 4. " [4] ,SPISCS4 pull control enable/disable" "No,Yes"
textline " "
bitfld.long 0x1C 3. " [3] ,SPISCS3 pull control enable/disable" "No,Yes"
bitfld.long 0x1C 2. " [2] ,SPISCS2 pull control enable/disable" "No,Yes"
bitfld.long 0x1C 1. " [1] ,SPISCS1 pull control enable/disable" "No,Yes"
bitfld.long 0x1C 0. " [0] ,SPISCS0 pull control enable/disable" "No,Yes"
textline " "
line.long 0x20 "SPIPC8,SPI Pin Control Register 8"
bitfld.long 0x20 31. " SOMIPSEL[7] ,SPISOMI[7] pull select" "Pull down,Pull up"
bitfld.long 0x20 30. " [6] ,SPISOMI[6] pull select" "Pull down,Pull up"
bitfld.long 0x20 29. " [5] ,SPISOMI[5] pull select" "Pull down,Pull up"
bitfld.long 0x20 28. " [4] ,SPISOMI[4] pull select" "Pull down,Pull up"
textline " "
bitfld.long 0x20 27. " [3] ,SPISOMI[3] pull select" "Pull down,Pull up"
bitfld.long 0x20 26. " [2] ,SPISOMI[2] pull select" "Pull down,Pull up"
bitfld.long 0x20 25. " [1] ,SPISOMI[1] pull select" "Pull down,Pull up"
bitfld.long 0x20 24. " [0] ,SPISOMI[0] pull select (mirror of bit 11)" "Pull down,Pull up"
textline " "
bitfld.long 0x20 23. " SIMOPSEL[7] ,SPISIMO[7] pull select" "Pull down,Pull up"
bitfld.long 0x20 22. " [6] ,SPISIMO[6] pull select" "Pull down,Pull up"
bitfld.long 0x20 21. " [5] ,SPISIMO[5] pull select" "Pull down,Pull up"
bitfld.long 0x20 20. " [4] ,SPISIMO[4] pull select" "Pull down,Pull up"
textline " "
bitfld.long 0x20 19. " [3] ,SPISIMO[3] pull select" "Pull down,Pull up"
bitfld.long 0x20 18. " [2] ,SPISIMO[2] pull select" "Pull down,Pull up"
bitfld.long 0x20 17. " [1] ,SPISIMO[1] pull select" "Pull down,Pull up"
bitfld.long 0x20 16. " [0] ,SPISIMO[0] pull select (mirror of bit 10)" "Pull down,Pull up"
textline " "
bitfld.long 0x20 11. " SOMIPSEL[0] ,SPISOMI[0] pull select" "Pull down,Pull up"
bitfld.long 0x20 10. " SIMOPSEL[0] ,SPISIMO[0] pull select" "Pull down,Pull up"
bitfld.long 0x20 9. " CLKPSEL ,SPI clock pull select" "Pull down,Pull up"
bitfld.long 0x20 8. " ENAPSEL ,SPIENA pull select" "Pull down,Pull up"
textline " "
textline " "
bitfld.long 0x20 7. " SCSPSEL[7] ,SPISCS7 pull select" "Pull down,Pull up"
bitfld.long 0x20 6. " [6] ,SPISCS6 pull select" "Pull down,Pull up"
bitfld.long 0x20 5. " [5] ,SPISCS5 pull select" "Pull down,Pull up"
bitfld.long 0x20 4. " [4] ,SPISCS4 pull select" "Pull down,Pull up"
textline " "
bitfld.long 0x20 3. " [3] ,SPISCS3 pull select" "Pull down,Pull up"
bitfld.long 0x20 2. " [2] ,SPISCS2 pull select" "Pull down,Pull up"
bitfld.long 0x20 1. " [1] ,SPISCS1 pull select" "Pull down,Pull up"
bitfld.long 0x20 0. " [0] ,SPISCS0 pull select" "Pull down,Pull up"
textline " "
group.long 0x38++0x03
line.long 0x00 "SPIDAT0,SPI Transmit Data Register 0"
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,SPI transmit data"
if (((d.l(ad:0xFFF7F600+0x4))&0x3)==0x0)
group.long 0x3C++0x03
line.long 0x00 "SPIDAT1,Transmit Data Register 1"
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Inactive,Active"
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "No delay,After transaction"
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
textline " "
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
else
group.long 0x3C++0x03
line.long 0x00 "SPIDAT1,Transmit Data Register 1"
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Inactive,Active"
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
textline " "
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
endif
width 17.
hgroup.long 0x40++0x03
hide.long 0x00 "SPIBUF,SPI Receive Buffer Register"
in
rgroup.long 0x44++0x03
line.long 0x00 "SPIEMU,SPI Emulation Register"
hexmask.long.word 0x00 0.--15. 1. " EMU_RXDATA ,SPI receive data"
if (((d.l(ad:0xFFF7F600+0x4))&0x1)==0x1)
rgroup.long 0x48++0x03
line.long 0x00 "SPIDELAY,SPI Delay Register"
hexmask.long.byte 0x00 24.--31. 1. " C2TDELAY ,Chip-select-active to transmit-start delay"
hexmask.long.byte 0x00 16.--23. 1. " T2CDELAY ,Transmit-end-to-chip-select-inactive-delay"
hexmask.long.byte 0x00 8.--15. 1. " T2EDELAY ,Transmit-data-finished to ENA-pin-inactive time-out"
textline " "
hexmask.long.byte 0x00 0.--7. 1. " C2EDELAY ,Chip-select-active to ENA-signal-active time-out"
group.long 0x4C++0x03
line.long 0x00 "SPIDEF,SPI Default Chip Select Register"
bitfld.long 0x00 7. " CSDEF[7] ,Chip select default pattern 7" "0,1"
bitfld.long 0x00 6. " [6] ,Chip select default pattern 6" "0,1"
bitfld.long 0x00 5. " [5] ,Chip select default pattern 5" "0,1"
textline " "
bitfld.long 0x00 4. " [4] ,Chip select default pattern 4" "0,1"
bitfld.long 0x00 3. " [3] ,Chip select default pattern 3" "0,1"
bitfld.long 0x00 2. " [2] ,Chip select default pattern 2" "0,1"
textline " "
bitfld.long 0x00 1. " [1] ,Chip select default pattern 1" "0,1"
bitfld.long 0x00 0. " [0] ,Chip select default pattern 0" "0,1"
endif
if (((d.l(ad:0xFFF7F600+0x4))&0x3)==0x0)
group.long 0x50++0x0F
line.long 0x0 "SPIFMT0,SPI Data Format Register 0"
sif cpuis("TMS570LC4357")
hexmask.long.byte 0x0 24.--31. 1. " WDELAY ,Delay in between transmissions for data format 0"
else
bitfld.long 0x0 24.--29. " WDELAY ,Delay in between transmissions for data format 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
endif
bitfld.long 0x0 23. " PARPOL ,Parity polarity: even or odd" "Even,Odd"
textline " "
bitfld.long 0x0 22. " PARITYENA ,Parity enable for data format 0" "Disabled,Enabled"
bitfld.long 0x0 20. " SHIFTDIR ,Shift direction for data format $" "MSB,LSB"
textline " "
sif cpuis("TMS570LC4357")
bitfld.long 0x0 19. " HDUPLEX_ENA0 ,Half Duplex transfer mode enable for Data Format 0" "Normal,TX"
endif
textline " "
bitfld.long 0x0 18. " DISCSTIMERS ,Disable chip-select timers for this format" "No,Yes"
textline " "
bitfld.long 0x0 17. " POLARITY ,SPI data format 0 clock polarity" "Low,High"
bitfld.long 0x0 16. " PHASE ,SPI data format 0 clock delay" "Disabled,Enabled"
textline " "
hexmask.long.byte 0x0 8.--15. 1. " PRESCALE ,SPI data format 0 prescaler"
bitfld.long 0x0 0.--4. " CHARLEN ,SPI data format 0 data-word length" ",,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,?..."
line.long 0x4 "SPIFMT1,SPI Data Format Register 1"
sif cpuis("TMS570LC4357")
hexmask.long.byte 0x4 24.--31. 1. " WDELAY ,Delay in between transmissions for data format 1"
else
bitfld.long 0x4 24.--29. " WDELAY ,Delay in between transmissions for data format 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
endif
bitfld.long 0x4 23. " PARPOL ,Parity polarity: even or odd" "Even,Odd"
textline " "
bitfld.long 0x4 22. " PARITYENA ,Parity enable for data format 1" "Disabled,Enabled"
bitfld.long 0x4 20. " SHIFTDIR ,Shift direction for data format $" "MSB,LSB"
textline " "
sif cpuis("TMS570LC4357")
bitfld.long 0x4 19. " HDUPLEX_ENA1 ,Half Duplex transfer mode enable for Data Format 1" "Normal,TX"
endif
textline " "
bitfld.long 0x4 18. " DISCSTIMERS ,Disable chip-select timers for this format" "No,Yes"
textline " "
bitfld.long 0x4 17. " POLARITY ,SPI data format 1 clock polarity" "Low,High"
bitfld.long 0x4 16. " PHASE ,SPI data format 1 clock delay" "Disabled,Enabled"
textline " "
hexmask.long.byte 0x4 8.--15. 1. " PRESCALE ,SPI data format 1 prescaler"
bitfld.long 0x4 0.--4. " CHARLEN ,SPI data format 1 data-word length" ",,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,?..."
line.long 0x8 "SPIFMT2,SPI Data Format Register 2"
sif cpuis("TMS570LC4357")
hexmask.long.byte 0x8 24.--31. 1. " WDELAY ,Delay in between transmissions for data format 2"
else
bitfld.long 0x8 24.--29. " WDELAY ,Delay in between transmissions for data format 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
endif
bitfld.long 0x8 23. " PARPOL ,Parity polarity: even or odd" "Even,Odd"
textline " "
bitfld.long 0x8 22. " PARITYENA ,Parity enable for data format 2" "Disabled,Enabled"
bitfld.long 0x8 20. " SHIFTDIR ,Shift direction for data format $" "MSB,LSB"
textline " "
sif cpuis("TMS570LC4357")
bitfld.long 0x8 19. " HDUPLEX_ENA2 ,Half Duplex transfer mode enable for Data Format 2" "Normal,TX"
endif
textline " "
bitfld.long 0x8 18. " DISCSTIMERS ,Disable chip-select timers for this format" "No,Yes"
textline " "
bitfld.long 0x8 17. " POLARITY ,SPI data format 2 clock polarity" "Low,High"
bitfld.long 0x8 16. " PHASE ,SPI data format 2 clock delay" "Disabled,Enabled"
textline " "
hexmask.long.byte 0x8 8.--15. 1. " PRESCALE ,SPI data format 2 prescaler"
bitfld.long 0x8 0.--4. " CHARLEN ,SPI data format 2 data-word length" ",,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,?..."
line.long 0xC "SPIFMT3,SPI Data Format Register 3"
sif cpuis("TMS570LC4357")
hexmask.long.byte 0xC 24.--31. 1. " WDELAY ,Delay in between transmissions for data format 3"
else
bitfld.long 0xC 24.--29. " WDELAY ,Delay in between transmissions for data format 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
endif
bitfld.long 0xC 23. " PARPOL ,Parity polarity: even or odd" "Even,Odd"
textline " "
bitfld.long 0xC 22. " PARITYENA ,Parity enable for data format 3" "Disabled,Enabled"
bitfld.long 0xC 20. " SHIFTDIR ,Shift direction for data format $" "MSB,LSB"
textline " "
sif cpuis("TMS570LC4357")
bitfld.long 0xC 19. " HDUPLEX_ENA3 ,Half Duplex transfer mode enable for Data Format 3" "Normal,TX"
endif
textline " "
bitfld.long 0xC 18. " DISCSTIMERS ,Disable chip-select timers for this format" "No,Yes"
textline " "
bitfld.long 0xC 17. " POLARITY ,SPI data format 3 clock polarity" "Low,High"
bitfld.long 0xC 16. " PHASE ,SPI data format 3 clock delay" "Disabled,Enabled"
textline " "
hexmask.long.byte 0xC 8.--15. 1. " PRESCALE ,SPI data format 3 prescaler"
bitfld.long 0xC 0.--4. " CHARLEN ,SPI data format 3 data-word length" ",,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,?..."
else
group.long 0x50++0x0F
line.long 0x0 "SPIFMT0,SPI Data Format Register 0"
sif cpuis("TMS570LC4357")
hexmask.long.byte 0x0 24.--31. 1. " WDELAY ,Delay in between transmissions for data format 0"
else
bitfld.long 0x0 24.--29. " WDELAY ,Delay in between transmissions for data format 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
endif
bitfld.long 0x0 23. " PARPOL ,Parity polarity: even or odd" "Even,Odd"
textline " "
bitfld.long 0x0 22. " PARITYENA ,Parity enable for data format 0" "Disabled,Enabled"
bitfld.long 0x0 21. " WAITENA ,The master waits for the ENA signal from slave for data format 0" "Disabled,Enabled"
textline " "
bitfld.long 0x0 20. " SHIFTDIR ,Shift direction for data format $" "MSB,LSB"
sif cpuis("TMS570LC4357")
bitfld.long 0x0 19. " HDUPLEX_ENA0 ,Half Duplex transfer mode enable for Data Format 0" "Normal,RX"
endif
textline " "
bitfld.long 0x0 18. " DISCSTIMERS ,Disable chip-select timers for this format" "No,Yes"
textline " "
bitfld.long 0x0 17. " POLARITY ,SPI data format 0 clock polarity" "Low,High"
bitfld.long 0x0 16. " PHASE ,SPI data format 0 clock delay" "Disabled,Enabled"
textline " "
hexmask.long.byte 0x0 8.--15. 1. " PRESCALE ,SPI data format 0 prescaler"
bitfld.long 0x0 0.--4. " CHARLEN ,SPI data format 0 data-word length" ",,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,?..."
line.long 0x4 "SPIFMT1,SPI Data Format Register 1"
sif cpuis("TMS570LC4357")
hexmask.long.byte 0x4 24.--31. 1. " WDELAY ,Delay in between transmissions for data format 1"
else
bitfld.long 0x4 24.--29. " WDELAY ,Delay in between transmissions for data format 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
endif
bitfld.long 0x4 23. " PARPOL ,Parity polarity: even or odd" "Even,Odd"
textline " "
bitfld.long 0x4 22. " PARITYENA ,Parity enable for data format 1" "Disabled,Enabled"
bitfld.long 0x4 21. " WAITENA ,The master waits for the ENA signal from slave for data format 1" "Disabled,Enabled"
textline " "
bitfld.long 0x4 20. " SHIFTDIR ,Shift direction for data format $" "MSB,LSB"
sif cpuis("TMS570LC4357")
bitfld.long 0x4 19. " HDUPLEX_ENA1 ,Half Duplex transfer mode enable for Data Format 1" "Normal,RX"
endif
textline " "
bitfld.long 0x4 18. " DISCSTIMERS ,Disable chip-select timers for this format" "No,Yes"
textline " "
bitfld.long 0x4 17. " POLARITY ,SPI data format 1 clock polarity" "Low,High"
bitfld.long 0x4 16. " PHASE ,SPI data format 1 clock delay" "Disabled,Enabled"
textline " "
hexmask.long.byte 0x4 8.--15. 1. " PRESCALE ,SPI data format 1 prescaler"
bitfld.long 0x4 0.--4. " CHARLEN ,SPI data format 1 data-word length" ",,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,?..."
line.long 0x8 "SPIFMT2,SPI Data Format Register 2"
sif cpuis("TMS570LC4357")
hexmask.long.byte 0x8 24.--31. 1. " WDELAY ,Delay in between transmissions for data format 2"
else
bitfld.long 0x8 24.--29. " WDELAY ,Delay in between transmissions for data format 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
endif
bitfld.long 0x8 23. " PARPOL ,Parity polarity: even or odd" "Even,Odd"
textline " "
bitfld.long 0x8 22. " PARITYENA ,Parity enable for data format 2" "Disabled,Enabled"
bitfld.long 0x8 21. " WAITENA ,The master waits for the ENA signal from slave for data format 2" "Disabled,Enabled"
textline " "
bitfld.long 0x8 20. " SHIFTDIR ,Shift direction for data format $" "MSB,LSB"
sif cpuis("TMS570LC4357")
bitfld.long 0x8 19. " HDUPLEX_ENA2 ,Half Duplex transfer mode enable for Data Format 2" "Normal,RX"
endif
textline " "
bitfld.long 0x8 18. " DISCSTIMERS ,Disable chip-select timers for this format" "No,Yes"
textline " "
bitfld.long 0x8 17. " POLARITY ,SPI data format 2 clock polarity" "Low,High"
bitfld.long 0x8 16. " PHASE ,SPI data format 2 clock delay" "Disabled,Enabled"
textline " "
hexmask.long.byte 0x8 8.--15. 1. " PRESCALE ,SPI data format 2 prescaler"
bitfld.long 0x8 0.--4. " CHARLEN ,SPI data format 2 data-word length" ",,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,?..."
line.long 0xC "SPIFMT3,SPI Data Format Register 3"
sif cpuis("TMS570LC4357")
hexmask.long.byte 0xC 24.--31. 1. " WDELAY ,Delay in between transmissions for data format 3"
else
bitfld.long 0xC 24.--29. " WDELAY ,Delay in between transmissions for data format 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
endif
bitfld.long 0xC 23. " PARPOL ,Parity polarity: even or odd" "Even,Odd"
textline " "
bitfld.long 0xC 22. " PARITYENA ,Parity enable for data format 3" "Disabled,Enabled"
bitfld.long 0xC 21. " WAITENA ,The master waits for the ENA signal from slave for data format 3" "Disabled,Enabled"
textline " "
bitfld.long 0xC 20. " SHIFTDIR ,Shift direction for data format $" "MSB,LSB"
sif cpuis("TMS570LC4357")
bitfld.long 0xC 19. " HDUPLEX_ENA3 ,Half Duplex transfer mode enable for Data Format 3" "Normal,RX"
endif
textline " "
bitfld.long 0xC 18. " DISCSTIMERS ,Disable chip-select timers for this format" "No,Yes"
textline " "
bitfld.long 0xC 17. " POLARITY ,SPI data format 3 clock polarity" "Low,High"
bitfld.long 0xC 16. " PHASE ,SPI data format 3 clock delay" "Disabled,Enabled"
textline " "
hexmask.long.byte 0xC 8.--15. 1. " PRESCALE ,SPI data format 3 prescaler"
bitfld.long 0xC 0.--4. " CHARLEN ,SPI data format 3 data-word length" ",,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,?..."
endif
hgroup.long 0x60++0x03
hide.long 0x00 "TGINTVECT0,SPI Interrupt Vector Register 0 / MibSPI Transfer Group Interrupt Vector Register 0"
in
hgroup.long 0x64++0x03
hide.long 0x00 "TGINTVECT1,SPI Interrupt Vector Register 1 / MibSPI Transfer Group Interrupt Vector Register 1"
in
group.long 0x6C++0x07
line.long 0x00 "SPIPMCTRL,SPI Parallel/Modulo Mode Control Register"
bitfld.long 0x00 29. " MODCLKPOL3 ,Modulo mode SPICLK polarity" "Normal,Inverted"
bitfld.long 0x00 26.--28. " MMODE3 ,SPI/MibSPI data lines" "1,2,3,4,5,6,?..."
bitfld.long 0x00 24.--25. " PMODE3 ,Parallel mode data lines" "1,2,4,8"
textline " "
bitfld.long 0x00 21. " MODCLKPOL2 ,Modulo mode SPICLK polarity" "Normal,Inverted"
bitfld.long 0x00 18.--20. " MMODE2 ,SPI/MibSPI data lines" "1,2,3,4,5,6,?..."
bitfld.long 0x00 16.--17. " PMODE2 ,Parallel mode data lines" "1,2,4,8"
textline " "
bitfld.long 0x00 13. " MODCLKPOL1 ,Modulo mode SPICLK polarity" "Normal,Inverted"
bitfld.long 0x00 10.--12. " MMODE1 ,SPI/MibSPI data lines" "1,2,3,4,5,6,?..."
bitfld.long 0x00 8.--9. " PMODE1 ,Parallel mode data lines" "1,2,4,8"
textline " "
bitfld.long 0x00 5. " MODCLKPOL0 ,Modulo mode SPICLK polarity" "Normal,Inverted"
bitfld.long 0x00 2.--4. " MMODE0 ,SPI/MibSPI data lines" "1,2,3,4,5,6,?..."
bitfld.long 0x00 0.--1. " PMODE0 ,Parallel mode data lines" "1,2,4,8"
line.long 0x04 "MIBSPIE,MibSPI Enable Register"
bitfld.long 0x04 16. " RXRAMACCESS ,Receive-RAM access control" "Not writable,Accessible"
bitfld.long 0x04 0. " MIBSPIENA ,Multi-buffer mode enable" "Disabled,Enabled"
textline " "
width 17.
group.long 0x74++0x0F
line.long 0x00 "TGITENST,MibSPI Transfer Group Interrupt Enable Set Register"
bitfld.long 0x00 31. " SETINTENRDY[15] ,TG interrupt set (enable) when transfer finished" "Disabled,Enabled"
bitfld.long 0x00 30. " [14] ,TG interrupt set (enable) when transfer finished" "Disabled,Enabled"
bitfld.long 0x00 29. " [13] ,TG interrupt set (enable) when transfer finished" "Disabled,Enabled"
textline " "
bitfld.long 0x00 28. " [12] ,TG interrupt set (enable) when transfer finished" "Disabled,Enabled"
bitfld.long 0x00 27. " [11] ,TG interrupt set (enable) when transfer finished" "Disabled,Enabled"
bitfld.long 0x00 26. " [10] ,TG interrupt set (enable) when transfer finished" "Disabled,Enabled"
textline " "
bitfld.long 0x00 25. " [9] ,TG interrupt set (enable) when transfer finished" "Disabled,Enabled"
bitfld.long 0x00 24. " [8] ,TG interrupt set (enable) when transfer finished" "Disabled,Enabled"
bitfld.long 0x00 23. " [7] ,TG interrupt set (enable) when transfer finished" "Disabled,Enabled"
textline " "
bitfld.long 0x00 22. " [6] ,TG interrupt set (enable) when transfer finished" "Disabled,Enabled"
bitfld.long 0x00 21. " [5] ,TG interrupt set (enable) when transfer finished" "Disabled,Enabled"
bitfld.long 0x00 20. " [4] ,TG interrupt set (enable) when transfer finished" "Disabled,Enabled"
textline " "
bitfld.long 0x00 19. " [3] ,TG interrupt set (enable) when transfer finished" "Disabled,Enabled"
bitfld.long 0x00 18. " [2] ,TG interrupt set (enable) when transfer finished" "Disabled,Enabled"
bitfld.long 0x00 17. " [1] ,TG interrupt set (enable) when transfer finished" "Disabled,Enabled"
textline " "
bitfld.long 0x00 16. " [0] ,TG interrupt set (enable) when transfer finished" "Disabled,Enabled"
textline " "
bitfld.long 0x00 15. " SETINTENSUS[15] ,TG interrupt set (enabled) when transfer suspended" "Disabled,Enabled"
bitfld.long 0x00 14. " [14] ,TG interrupt set (enabled) when transfer suspended" "Disabled,Enabled"
bitfld.long 0x00 13. " [13] ,TG interrupt set (enabled) when transfer suspended" "Disabled,Enabled"
textline " "
bitfld.long 0x00 12. " [12] ,TG interrupt set (enabled) when transfer suspended" "Disabled,Enabled"
bitfld.long 0x00 11. " [11] ,TG interrupt set (enabled) when transfer suspended" "Disabled,Enabled"
bitfld.long 0x00 10. " [10] ,TG interrupt set (enabled) when transfer suspended" "Disabled,Enabled"
textline " "
bitfld.long 0x00 9. " [9] ,TG interrupt set (enabled) when transfer suspended" "Disabled,Enabled"
bitfld.long 0x00 8. " [8] ,TG interrupt set (enabled) when transfer suspended" "Disabled,Enabled"
bitfld.long 0x00 7. " [7] ,TG interrupt set (enabled) when transfer suspended" "Disabled,Enabled"
textline " "
bitfld.long 0x00 6. " [6] ,TG interrupt set (enabled) when transfer suspended" "Disabled,Enabled"
bitfld.long 0x00 5. " [5] ,TG interrupt set (enabled) when transfer suspended" "Disabled,Enabled"
bitfld.long 0x00 4. " [4] ,TG interrupt set (enabled) when transfer suspended" "Disabled,Enabled"
textline " "
bitfld.long 0x00 3. " [3] ,TG interrupt set (enabled) when transfer suspended" "Disabled,Enabled"
bitfld.long 0x00 2. " [2] ,TG interrupt set (enabled) when transfer suspended" "Disabled,Enabled"
bitfld.long 0x00 1. " [1] ,TG interrupt set (enabled) when transfer suspended" "Disabled,Enabled"
textline " "
bitfld.long 0x00 0. " [0] ,TG interrupt set (enabled) when transfer suspended" "Disabled,Enabled"
line.long 0x04 "TGITENCR,MibSPI Transfer Group Interrupt Enable Clear Register"
bitfld.long 0x04 31. " CLRINTENRDY[15] ,TG interrupt clear (disabled) when transfer finished" "Disabled,Enabled"
bitfld.long 0x04 30. " [14] ,TG interrupt clear (disabled) when transfer finished" "Disabled,Enabled"
bitfld.long 0x04 29. " [13] ,TG interrupt clear (disabled) when transfer finished" "Disabled,Enabled"
textline " "
bitfld.long 0x04 28. " [12] ,TG interrupt clear (disabled) when transfer finished" "Disabled,Enabled"
bitfld.long 0x04 27. " [11] ,TG interrupt clear (disabled) when transfer finished" "Disabled,Enabled"
bitfld.long 0x04 26. " [10] ,TG interrupt clear (disabled) when transfer finished" "Disabled,Enabled"
textline " "
bitfld.long 0x04 25. " [9] ,TG interrupt clear (disabled) when transfer finished" "Disabled,Enabled"
bitfld.long 0x04 24. " [8] ,TG interrupt clear (disabled) when transfer finished" "Disabled,Enabled"
bitfld.long 0x04 23. " [7] ,TG interrupt clear (disabled) when transfer finished" "Disabled,Enabled"
textline " "
bitfld.long 0x04 22. " [6] ,TG interrupt clear (disabled) when transfer finished" "Disabled,Enabled"
bitfld.long 0x04 21. " [5] ,TG interrupt clear (disabled) when transfer finished" "Disabled,Enabled"
bitfld.long 0x04 20. " [4] ,TG interrupt clear (disabled) when transfer finished" "Disabled,Enabled"
textline " "
bitfld.long 0x04 19. " [3] ,TG interrupt clear (disabled) when transfer finished" "Disabled,Enabled"
bitfld.long 0x04 18. " [2] ,TG interrupt clear (disabled) when transfer finished" "Disabled,Enabled"
bitfld.long 0x04 17. " [1] ,TG interrupt clear (disabled) when transfer finished" "Disabled,Enabled"
textline " "
bitfld.long 0x04 16. " [0] ,TG interrupt clear (disabled) when transfer finished" "Disabled,Enabled"
textline " "
bitfld.long 0x04 15. " CLRINTENSUS[15] ,TG interrupt clear (disabled) when transfer suspended" "Disabled,Enabled"
bitfld.long 0x04 14. " [14] ,TG interrupt clear (disabled) when transfer suspended" "Disabled,Enabled"
bitfld.long 0x04 13. " [13] ,TG interrupt clear (disabled) when transfer suspended" "Disabled,Enabled"
textline " "
bitfld.long 0x04 12. " [12] ,TG interrupt clear (disabled) when transfer suspended" "Disabled,Enabled"
bitfld.long 0x04 11. " [11] ,TG interrupt clear (disabled) when transfer suspended" "Disabled,Enabled"
bitfld.long 0x04 10. " [10] ,TG interrupt clear (disabled) when transfer suspended" "Disabled,Enabled"
textline " "
bitfld.long 0x04 9. " [9] ,TG interrupt clear (disabled) when transfer suspended" "Disabled,Enabled"
bitfld.long 0x04 8. " [8] ,TG interrupt clear (disabled) when transfer suspended" "Disabled,Enabled"
bitfld.long 0x04 7. " [7] ,TG interrupt clear (disabled) when transfer suspended" "Disabled,Enabled"
textline " "
bitfld.long 0x04 6. " [6] ,TG interrupt clear (disabled) when transfer suspended" "Disabled,Enabled"
bitfld.long 0x04 5. " [5] ,TG interrupt clear (disabled) when transfer suspended" "Disabled,Enabled"
bitfld.long 0x04 4. " [4] ,TG interrupt clear (disabled) when transfer suspended" "Disabled,Enabled"
textline " "
bitfld.long 0x04 3. " [3] ,TG interrupt clear (disabled) when transfer suspended" "Disabled,Enabled"
bitfld.long 0x04 2. " [2] ,TG interrupt clear (disabled) when transfer suspended" "Disabled,Enabled"
bitfld.long 0x04 1. " [1] ,TG interrupt clear (disabled) when transfer suspended" "Disabled,Enabled"
textline " "
bitfld.long 0x04 0. " [0] ,TG interrupt clear (disabled) when transfer suspended" "Disabled,Enabled"
textline " "
line.long 0x08 "TGITLVST,MibSPI Transfer Group Interrupt Level Set Register"
bitfld.long 0x08 31. " SETINTLVLRDY[15] ,Transfer-group completed interrupt level set" "INT0,INT1"
bitfld.long 0x08 30. " [14] ,Transfer-group completed interrupt level set" "INT0,INT1"
bitfld.long 0x08 29. " [13] ,Transfer-group completed interrupt level set" "INT0,INT1"
bitfld.long 0x08 28. " [12] ,Transfer-group completed interrupt level set" "INT0,INT1"
bitfld.long 0x08 27. " [11] ,Transfer-group completed interrupt level set" "INT0,INT1"
bitfld.long 0x08 26. " [10] ,Transfer-group completed interrupt level set" "INT0,INT1"
textline " "
bitfld.long 0x08 25. " [9] ,Transfer-group completed interrupt level set" "INT0,INT1"
bitfld.long 0x08 24. " [8] ,Transfer-group completed interrupt level set" "INT0,INT1"
bitfld.long 0x08 23. " [7] ,Transfer-group completed interrupt level set" "INT0,INT1"
bitfld.long 0x08 22. " [6] ,Transfer-group completed interrupt level set" "INT0,INT1"
bitfld.long 0x08 21. " [5] ,Transfer-group completed interrupt level set" "INT0,INT1"
bitfld.long 0x08 20. " [4] ,Transfer-group completed interrupt level set" "INT0,INT1"
textline " "
bitfld.long 0x08 19. " [3] ,Transfer-group completed interrupt level set" "INT0,INT1"
bitfld.long 0x08 18. " [2] ,Transfer-group completed interrupt level set" "INT0,INT1"
bitfld.long 0x08 17. " [1] ,Transfer-group completed interrupt level set" "INT0,INT1"
bitfld.long 0x08 16. " [0] ,Transfer-group completed interrupt level set" "INT0,INT1"
textline " "
bitfld.long 0x08 15. " SETINTLVLSUS[15] ,Transfer-group suspended interrupt level set" "INT0,INT1"
bitfld.long 0x08 14. " [14] ,Transfer-group suspended interrupt level set" "INT0,INT1"
bitfld.long 0x08 13. " [13] ,Transfer-group suspended interrupt level set" "INT0,INT1"
bitfld.long 0x08 12. " [12] ,Transfer-group suspended interrupt level set" "INT0,INT1"
bitfld.long 0x08 11. " [11] ,Transfer-group suspended interrupt level set" "INT0,INT1"
bitfld.long 0x08 10. " [10] ,Transfer-group suspended interrupt level set" "INT0,INT1"
textline " "
bitfld.long 0x08 9. " [9] ,Transfer-group suspended interrupt level set" "INT0,INT1"
bitfld.long 0x08 8. " [8] ,Transfer-group suspended interrupt level set" "INT0,INT1"
bitfld.long 0x08 7. " [7] ,Transfer-group suspended interrupt level set" "INT0,INT1"
bitfld.long 0x08 6. " [6] ,Transfer-group suspended interrupt level set" "INT0,INT1"
bitfld.long 0x08 5. " [5] ,Transfer-group suspended interrupt level set" "INT0,INT1"
bitfld.long 0x08 4. " [4] ,Transfer-group suspended interrupt level set" "INT0,INT1"
textline " "
bitfld.long 0x08 3. " [3] ,Transfer-group suspended interrupt level set" "INT0,INT1"
bitfld.long 0x08 2. " [2] ,Transfer-group suspended interrupt level set" "INT0,INT1"
bitfld.long 0x08 1. " [1] ,Transfer-group suspended interrupt level set" "INT0,INT1"
bitfld.long 0x08 0. " [0] ,Transfer-group suspended interrupt level set" "INT0,INT1"
line.long 0x0C "TGITLVCR,MibSPI Transfer Group Interrupt Level Clear Register"
bitfld.long 0x0C 31. " CLRINTLVLRDY[15] ,Transfer-group completed interrupt level clear" "INT0,INT1"
bitfld.long 0x0C 30. " [14] ,Transfer-group completed interrupt level clear" "INT0,INT1"
bitfld.long 0x0C 29. " [13] ,Transfer-group completed interrupt level clear" "INT0,INT1"
bitfld.long 0x0C 28. " [12] ,Transfer-group completed interrupt level clear" "INT0,INT1"
bitfld.long 0x0C 27. " [11] ,Transfer-group completed interrupt level clear" "INT0,INT1"
bitfld.long 0x0C 26. " [10] ,Transfer-group completed interrupt level clear" "INT0,INT1"
textline " "
bitfld.long 0x0C 25. " [9] ,Transfer-group completed interrupt level clear" "INT0,INT1"
bitfld.long 0x0C 24. " [8] ,Transfer-group completed interrupt level clear" "INT0,INT1"
bitfld.long 0x0C 23. " [7] ,Transfer-group completed interrupt level clear" "INT0,INT1"
bitfld.long 0x0C 22. " [6] ,Transfer-group completed interrupt level clear" "INT0,INT1"
bitfld.long 0x0C 21. " [5] ,Transfer-group completed interrupt level clear" "INT0,INT1"
bitfld.long 0x0C 20. " [4] ,Transfer-group completed interrupt level clear" "INT0,INT1"
textline " "
bitfld.long 0x0C 19. " [3] ,Transfer-group completed interrupt level clear" "INT0,INT1"
bitfld.long 0x0C 18. " [2] ,Transfer-group completed interrupt level clear" "INT0,INT1"
bitfld.long 0x0C 17. " [1] ,Transfer-group completed interrupt level clear" "INT0,INT1"
bitfld.long 0x0C 16. " [0] ,Transfer-group completed interrupt level clear" "INT0,INT1"
textline " "
bitfld.long 0x0C 15. " CLRINTLVLSUS[15] ,Transfer group suspended interrupt level clear" "INT0,INT1"
bitfld.long 0x0C 14. " [14] ,Transfer group suspended interrupt level clear" "INT0,INT1"
bitfld.long 0x0C 13. " [13] ,Transfer group suspended interrupt level clear" "INT0,INT1"
bitfld.long 0x0C 12. " [12] ,Transfer group suspended interrupt level clear" "INT0,INT1"
bitfld.long 0x0C 11. " [11] ,Transfer group suspended interrupt level clear" "INT0,INT1"
bitfld.long 0x0C 10. " [10] ,Transfer group suspended interrupt level clear" "INT0,INT1"
textline " "
bitfld.long 0x0C 9. " [9] ,Transfer group suspended interrupt level clear" "INT0,INT1"
bitfld.long 0x0C 8. " [8] ,Transfer group suspended interrupt level clear" "INT0,INT1"
bitfld.long 0x0C 7. " [7] ,Transfer group suspended interrupt level clear" "INT0,INT1"
bitfld.long 0x0C 6. " [6] ,Transfer group suspended interrupt level clear" "INT0,INT1"
bitfld.long 0x0C 5. " [5] ,Transfer group suspended interrupt level clear" "INT0,INT1"
bitfld.long 0x0C 4. " [4] ,Transfer group suspended interrupt level clear" "INT0,INT1"
textline " "
bitfld.long 0x0C 3. " [3] ,Transfer group suspended interrupt level clear" "INT0,INT1"
bitfld.long 0x0C 2. " [2] ,Transfer group suspended interrupt level clear" "INT0,INT1"
bitfld.long 0x0C 1. " [1] ,Transfer group suspended interrupt level clear" "INT0,INT1"
bitfld.long 0x0C 0. " [0] ,Transfer group suspended interrupt level clear" "INT0,INT1"
textline " "
group.long 0x84++0x03
line.long 0x00 "TGITFLG,Transfer Group Interrupt Flag Register"
sif cpuis("TMS570LC4357")
bitfld.long 0x00 31. " INTFLGRDY[15] ,Transfer-group interrupt flag for a transfer-completed interrupt 15" "Disabled,Enabled"
bitfld.long 0x00 30. " [14] ,Transfer-group interrupt flag for a transfer-completed interrupt 14" "Disabled,Enabled"
bitfld.long 0x00 29. " [13] ,Transfer-group interrupt flag for a transfer-completed interrupt 13" "Disabled,Enabled"
bitfld.long 0x00 28. " [12] ,Transfer-group interrupt flag for a transfer-completed interrupt 12" "Disabled,Enabled"
textline " "
bitfld.long 0x00 27. " [11] ,Transfer-group interrupt flag for a transfer-completed interrupt 11" "Disabled,Enabled"
bitfld.long 0x00 26. " [10] ,Transfer-group interrupt flag for a transfer-completed interrupt 10" "Disabled,Enabled"
bitfld.long 0x00 25. " [9] ,Transfer-group interrupt flag for a transfer-completed interrupt 9" "Disabled,Enabled"
bitfld.long 0x00 24. " [8] ,Transfer-group interrupt flag for a transfer-completed interrupt 8" "Disabled,Enabled"
textline " "
bitfld.long 0x00 23. " [7] ,Transfer-group interrupt flag for a transfer-completed interrupt 7" "Disabled,Enabled"
bitfld.long 0x00 22. " [6] ,Transfer-group interrupt flag for a transfer-completed interrupt 6" "Disabled,Enabled"
bitfld.long 0x00 21. " [5] ,Transfer-group interrupt flag for a transfer-completed interrupt 5" "Disabled,Enabled"
bitfld.long 0x00 20. " [4] ,Transfer-group interrupt flag for a transfer-completed interrupt 4" "Disabled,Enabled"
textline " "
bitfld.long 0x00 19. " [3] ,Transfer-group interrupt flag for a transfer-completed interrupt 3" "Disabled,Enabled"
bitfld.long 0x00 18. " [2] ,Transfer-group interrupt flag for a transfer-completed interrupt 2" "Disabled,Enabled"
bitfld.long 0x00 17. " [1] ,Transfer-group interrupt flag for a transfer-completed interrupt 1" "Disabled,Enabled"
bitfld.long 0x00 16. " [0] ,Transfer-group interrupt flag for a transfer-completed interrupt 0" "Disabled,Enabled"
textline " "
endif
bitfld.long 0x00 15. " INTFLGSUS[15] ,Transfer-group interrupt flag for a transfer-suspend interrupt 15" "Disabled,Enabled"
bitfld.long 0x00 14. " [14] ,Transfer-group interrupt flag for a transfer-suspend interrupt 14" "Disabled,Enabled"
bitfld.long 0x00 13. " [13] ,Transfer-group interrupt flag for a transfer-suspend interrupt 13" "Disabled,Enabled"
bitfld.long 0x00 12. " [12] ,Transfer-group interrupt flag for a transfer-suspend interrupt 12" "Disabled,Enabled"
textline " "
bitfld.long 0x00 11. " [11] ,Transfer-group interrupt flag for a transfer-suspend interrupt 11" "Disabled,Enabled"
bitfld.long 0x00 10. " [10] ,Transfer-group interrupt flag for a transfer-suspend interrupt 10" "Disabled,Enabled"
bitfld.long 0x00 9. " [9] ,Transfer-group interrupt flag for a transfer-suspend interrupt 9" "Disabled,Enabled"
bitfld.long 0x00 8. " [8] ,Transfer-group interrupt flag for a transfer-suspend interrupt 8" "Disabled,Enabled"
textline " "
bitfld.long 0x00 7. " [7] ,Transfer-group interrupt flag for a transfer-suspend interrupt 7" "Disabled,Enabled"
bitfld.long 0x00 6. " [6] ,Transfer-group interrupt flag for a transfer-suspend interrupt 6" "Disabled,Enabled"
bitfld.long 0x00 5. " [5] ,Transfer-group interrupt flag for a transfer-suspend interrupt 5" "Disabled,Enabled"
bitfld.long 0x00 4. " [4] ,Transfer-group interrupt flag for a transfer-suspend interrupt 4" "Disabled,Enabled"
textline " "
bitfld.long 0x00 3. " [3] ,Transfer-group interrupt flag for a transfer-suspend interrupt 3" "Disabled,Enabled"
bitfld.long 0x00 2. " [2] ,Transfer-group interrupt flag for a transfer-suspend interrupt 2" "Disabled,Enabled"
bitfld.long 0x00 1. " [1] ,Transfer-group interrupt flag for a transfer-suspend interrupt 1" "Disabled,Enabled"
bitfld.long 0x00 0. " [0] ,Transfer-group interrupt flag for a transfer-suspend interrupt 0" "Disabled,Enabled"
textline " "
group.long 0x90++0x47
line.long 0x00 "TICKCNT,Tick Count Register"
bitfld.long 0x00 31. " TICKENA ,Tick counter enable" "Disabled,Enabled"
bitfld.long 0x00 30. " RELOAD ,Pre-load the tick counter" "No effect,Reload"
bitfld.long 0x00 28.--29. " CLKCTRL ,Tick counter clock source control" "0,1,2,3"
textline " "
hexmask.long.word 0x00 0.--15. 1. " TICKVALUE ,Initial value for the tick counter"
line.long 0x04 "LTGPEND,Last Transfer Group End Pointer Register"
rbitfld.long 0x04 24.--28. " TGINSERVICE ,The TG number currently being serviced by the sequencer" "No TG,TG0,TG1,TG2,TG3,TG4,TG5,TG6,TG7,TG8,TG9,TG10,TG11,TG12,TG13,TG14,TG15,?..."
hexmask.long.byte 0x04 8.--14. 1. " LPEND ,Last TG end pointer"
line.long 0x8 "TG1CTRL,MibSPI Transfer Group Control Register 1"
bitfld.long 0x8 31. " TGENA ,TG enable" "Disabled,Enabled"
bitfld.long 0x8 30. " ONESHOT ,Single transfer for TG" "Disabled,Enabled"
bitfld.long 0x8 29. " PRST ,TG pointer reset mode" "Disabled,Enabled"
textline " "
rbitfld.long 0x8 28. " TGTD ,TG triggered" "Not triggered,Triggered"
bitfld.long 0x8 20.--23. " TRGEVT ,Type of trigger event" "Never,Rising edge,Falling edge,Both edges,,High active,Low-active,Always,?..."
bitfld.long 0x8 16.--19. " TRIGSRC ,Trigger source" "Disabled,EXT[0],EXT[1],EXT[2],EXT[3],EXT[4],EXT[5],EXT[6],EXT[7],EXT[8],EXT[9,EXT[10,EXT[11,EXT[12,EXT[13],TICK"
textline " "
hexmask.long.byte 0x8 8.--14. 1. " PSTART ,TG start address"
hexmask.long.byte 0x8 0.--6. 1. " PCURRENT ,Pointer to current buffer"
line.long 0xC "TG2CTRL,MibSPI Transfer Group Control Register 2"
bitfld.long 0xC 31. " TGENA ,TG enable" "Disabled,Enabled"
bitfld.long 0xC 30. " ONESHOT ,Single transfer for TG" "Disabled,Enabled"
bitfld.long 0xC 29. " PRST ,TG pointer reset mode" "Disabled,Enabled"
textline " "
rbitfld.long 0xC 28. " TGTD ,TG triggered" "Not triggered,Triggered"
bitfld.long 0xC 20.--23. " TRGEVT ,Type of trigger event" "Never,Rising edge,Falling edge,Both edges,,High active,Low-active,Always,?..."
bitfld.long 0xC 16.--19. " TRIGSRC ,Trigger source" "Disabled,EXT[0],EXT[1],EXT[2],EXT[3],EXT[4],EXT[5],EXT[6],EXT[7],EXT[8],EXT[9,EXT[10,EXT[11,EXT[12,EXT[13],TICK"
textline " "
hexmask.long.byte 0xC 8.--14. 1. " PSTART ,TG start address"
hexmask.long.byte 0xC 0.--6. 1. " PCURRENT ,Pointer to current buffer"
line.long 0x10 "TG3CTRL,MibSPI Transfer Group Control Register 3"
bitfld.long 0x10 31. " TGENA ,TG enable" "Disabled,Enabled"
bitfld.long 0x10 30. " ONESHOT ,Single transfer for TG" "Disabled,Enabled"
bitfld.long 0x10 29. " PRST ,TG pointer reset mode" "Disabled,Enabled"
textline " "
rbitfld.long 0x10 28. " TGTD ,TG triggered" "Not triggered,Triggered"
bitfld.long 0x10 20.--23. " TRGEVT ,Type of trigger event" "Never,Rising edge,Falling edge,Both edges,,High active,Low-active,Always,?..."
bitfld.long 0x10 16.--19. " TRIGSRC ,Trigger source" "Disabled,EXT[0],EXT[1],EXT[2],EXT[3],EXT[4],EXT[5],EXT[6],EXT[7],EXT[8],EXT[9,EXT[10,EXT[11,EXT[12,EXT[13],TICK"
textline " "
hexmask.long.byte 0x10 8.--14. 1. " PSTART ,TG start address"
hexmask.long.byte 0x10 0.--6. 1. " PCURRENT ,Pointer to current buffer"
line.long 0x14 "TG4CTRL,MibSPI Transfer Group Control Register 4"
bitfld.long 0x14 31. " TGENA ,TG enable" "Disabled,Enabled"
bitfld.long 0x14 30. " ONESHOT ,Single transfer for TG" "Disabled,Enabled"
bitfld.long 0x14 29. " PRST ,TG pointer reset mode" "Disabled,Enabled"
textline " "
rbitfld.long 0x14 28. " TGTD ,TG triggered" "Not triggered,Triggered"
bitfld.long 0x14 20.--23. " TRGEVT ,Type of trigger event" "Never,Rising edge,Falling edge,Both edges,,High active,Low-active,Always,?..."
bitfld.long 0x14 16.--19. " TRIGSRC ,Trigger source" "Disabled,EXT[0],EXT[1],EXT[2],EXT[3],EXT[4],EXT[5],EXT[6],EXT[7],EXT[8],EXT[9,EXT[10,EXT[11,EXT[12,EXT[13],TICK"
textline " "
hexmask.long.byte 0x14 8.--14. 1. " PSTART ,TG start address"
hexmask.long.byte 0x14 0.--6. 1. " PCURRENT ,Pointer to current buffer"
line.long 0x18 "TG5CTRL,MibSPI Transfer Group Control Register 5"
bitfld.long 0x18 31. " TGENA ,TG enable" "Disabled,Enabled"
bitfld.long 0x18 30. " ONESHOT ,Single transfer for TG" "Disabled,Enabled"
bitfld.long 0x18 29. " PRST ,TG pointer reset mode" "Disabled,Enabled"
textline " "
rbitfld.long 0x18 28. " TGTD ,TG triggered" "Not triggered,Triggered"
bitfld.long 0x18 20.--23. " TRGEVT ,Type of trigger event" "Never,Rising edge,Falling edge,Both edges,,High active,Low-active,Always,?..."
bitfld.long 0x18 16.--19. " TRIGSRC ,Trigger source" "Disabled,EXT[0],EXT[1],EXT[2],EXT[3],EXT[4],EXT[5],EXT[6],EXT[7],EXT[8],EXT[9,EXT[10,EXT[11,EXT[12,EXT[13],TICK"
textline " "
hexmask.long.byte 0x18 8.--14. 1. " PSTART ,TG start address"
hexmask.long.byte 0x18 0.--6. 1. " PCURRENT ,Pointer to current buffer"
line.long 0x1C "TG6CTRL,MibSPI Transfer Group Control Register 6"
bitfld.long 0x1C 31. " TGENA ,TG enable" "Disabled,Enabled"
bitfld.long 0x1C 30. " ONESHOT ,Single transfer for TG" "Disabled,Enabled"
bitfld.long 0x1C 29. " PRST ,TG pointer reset mode" "Disabled,Enabled"
textline " "
rbitfld.long 0x1C 28. " TGTD ,TG triggered" "Not triggered,Triggered"
bitfld.long 0x1C 20.--23. " TRGEVT ,Type of trigger event" "Never,Rising edge,Falling edge,Both edges,,High active,Low-active,Always,?..."
bitfld.long 0x1C 16.--19. " TRIGSRC ,Trigger source" "Disabled,EXT[0],EXT[1],EXT[2],EXT[3],EXT[4],EXT[5],EXT[6],EXT[7],EXT[8],EXT[9,EXT[10,EXT[11,EXT[12,EXT[13],TICK"
textline " "
hexmask.long.byte 0x1C 8.--14. 1. " PSTART ,TG start address"
hexmask.long.byte 0x1C 0.--6. 1. " PCURRENT ,Pointer to current buffer"
line.long 0x20 "TG7CTRL,MibSPI Transfer Group Control Register 7"
bitfld.long 0x20 31. " TGENA ,TG enable" "Disabled,Enabled"
bitfld.long 0x20 30. " ONESHOT ,Single transfer for TG" "Disabled,Enabled"
bitfld.long 0x20 29. " PRST ,TG pointer reset mode" "Disabled,Enabled"
textline " "
rbitfld.long 0x20 28. " TGTD ,TG triggered" "Not triggered,Triggered"
bitfld.long 0x20 20.--23. " TRGEVT ,Type of trigger event" "Never,Rising edge,Falling edge,Both edges,,High active,Low-active,Always,?..."
bitfld.long 0x20 16.--19. " TRIGSRC ,Trigger source" "Disabled,EXT[0],EXT[1],EXT[2],EXT[3],EXT[4],EXT[5],EXT[6],EXT[7],EXT[8],EXT[9,EXT[10,EXT[11,EXT[12,EXT[13],TICK"
textline " "
hexmask.long.byte 0x20 8.--14. 1. " PSTART ,TG start address"
hexmask.long.byte 0x20 0.--6. 1. " PCURRENT ,Pointer to current buffer"
line.long 0x24 "TG8CTRL,MibSPI Transfer Group Control Register 8"
bitfld.long 0x24 31. " TGENA ,TG enable" "Disabled,Enabled"
bitfld.long 0x24 30. " ONESHOT ,Single transfer for TG" "Disabled,Enabled"
bitfld.long 0x24 29. " PRST ,TG pointer reset mode" "Disabled,Enabled"
textline " "
rbitfld.long 0x24 28. " TGTD ,TG triggered" "Not triggered,Triggered"
bitfld.long 0x24 20.--23. " TRGEVT ,Type of trigger event" "Never,Rising edge,Falling edge,Both edges,,High active,Low-active,Always,?..."
bitfld.long 0x24 16.--19. " TRIGSRC ,Trigger source" "Disabled,EXT[0],EXT[1],EXT[2],EXT[3],EXT[4],EXT[5],EXT[6],EXT[7],EXT[8],EXT[9,EXT[10,EXT[11,EXT[12,EXT[13],TICK"
textline " "
hexmask.long.byte 0x24 8.--14. 1. " PSTART ,TG start address"
hexmask.long.byte 0x24 0.--6. 1. " PCURRENT ,Pointer to current buffer"
line.long 0x28 "TG9CTRL,MibSPI Transfer Group Control Register 9"
bitfld.long 0x28 31. " TGENA ,TG enable" "Disabled,Enabled"
bitfld.long 0x28 30. " ONESHOT ,Single transfer for TG" "Disabled,Enabled"
bitfld.long 0x28 29. " PRST ,TG pointer reset mode" "Disabled,Enabled"
textline " "
rbitfld.long 0x28 28. " TGTD ,TG triggered" "Not triggered,Triggered"
bitfld.long 0x28 20.--23. " TRGEVT ,Type of trigger event" "Never,Rising edge,Falling edge,Both edges,,High active,Low-active,Always,?..."
bitfld.long 0x28 16.--19. " TRIGSRC ,Trigger source" "Disabled,EXT[0],EXT[1],EXT[2],EXT[3],EXT[4],EXT[5],EXT[6],EXT[7],EXT[8],EXT[9,EXT[10,EXT[11,EXT[12,EXT[13],TICK"
textline " "
hexmask.long.byte 0x28 8.--14. 1. " PSTART ,TG start address"
hexmask.long.byte 0x28 0.--6. 1. " PCURRENT ,Pointer to current buffer"
line.long 0x2C "TG10CTRL,MibSPI Transfer Group Control Register 10"
bitfld.long 0x2C 31. " TGENA ,TG enable" "Disabled,Enabled"
bitfld.long 0x2C 30. " ONESHOT ,Single transfer for TG" "Disabled,Enabled"
bitfld.long 0x2C 29. " PRST ,TG pointer reset mode" "Disabled,Enabled"
textline " "
rbitfld.long 0x2C 28. " TGTD ,TG triggered" "Not triggered,Triggered"
bitfld.long 0x2C 20.--23. " TRGEVT ,Type of trigger event" "Never,Rising edge,Falling edge,Both edges,,High active,Low-active,Always,?..."
bitfld.long 0x2C 16.--19. " TRIGSRC ,Trigger source" "Disabled,EXT[0],EXT[1],EXT[2],EXT[3],EXT[4],EXT[5],EXT[6],EXT[7],EXT[8],EXT[9,EXT[10,EXT[11,EXT[12,EXT[13],TICK"
textline " "
hexmask.long.byte 0x2C 8.--14. 1. " PSTART ,TG start address"
hexmask.long.byte 0x2C 0.--6. 1. " PCURRENT ,Pointer to current buffer"
line.long 0x30 "TG11CTRL,MibSPI Transfer Group Control Register 11"
bitfld.long 0x30 31. " TGENA ,TG enable" "Disabled,Enabled"
bitfld.long 0x30 30. " ONESHOT ,Single transfer for TG" "Disabled,Enabled"
bitfld.long 0x30 29. " PRST ,TG pointer reset mode" "Disabled,Enabled"
textline " "
rbitfld.long 0x30 28. " TGTD ,TG triggered" "Not triggered,Triggered"
bitfld.long 0x30 20.--23. " TRGEVT ,Type of trigger event" "Never,Rising edge,Falling edge,Both edges,,High active,Low-active,Always,?..."
bitfld.long 0x30 16.--19. " TRIGSRC ,Trigger source" "Disabled,EXT[0],EXT[1],EXT[2],EXT[3],EXT[4],EXT[5],EXT[6],EXT[7],EXT[8],EXT[9,EXT[10,EXT[11,EXT[12,EXT[13],TICK"
textline " "
hexmask.long.byte 0x30 8.--14. 1. " PSTART ,TG start address"
hexmask.long.byte 0x30 0.--6. 1. " PCURRENT ,Pointer to current buffer"
line.long 0x34 "TG12CTRL,MibSPI Transfer Group Control Register 12"
bitfld.long 0x34 31. " TGENA ,TG enable" "Disabled,Enabled"
bitfld.long 0x34 30. " ONESHOT ,Single transfer for TG" "Disabled,Enabled"
bitfld.long 0x34 29. " PRST ,TG pointer reset mode" "Disabled,Enabled"
textline " "
rbitfld.long 0x34 28. " TGTD ,TG triggered" "Not triggered,Triggered"
bitfld.long 0x34 20.--23. " TRGEVT ,Type of trigger event" "Never,Rising edge,Falling edge,Both edges,,High active,Low-active,Always,?..."
bitfld.long 0x34 16.--19. " TRIGSRC ,Trigger source" "Disabled,EXT[0],EXT[1],EXT[2],EXT[3],EXT[4],EXT[5],EXT[6],EXT[7],EXT[8],EXT[9,EXT[10,EXT[11,EXT[12,EXT[13],TICK"
textline " "
hexmask.long.byte 0x34 8.--14. 1. " PSTART ,TG start address"
hexmask.long.byte 0x34 0.--6. 1. " PCURRENT ,Pointer to current buffer"
line.long 0x38 "TG13CTRL,MibSPI Transfer Group Control Register 13"
bitfld.long 0x38 31. " TGENA ,TG enable" "Disabled,Enabled"
bitfld.long 0x38 30. " ONESHOT ,Single transfer for TG" "Disabled,Enabled"
bitfld.long 0x38 29. " PRST ,TG pointer reset mode" "Disabled,Enabled"
textline " "
rbitfld.long 0x38 28. " TGTD ,TG triggered" "Not triggered,Triggered"
bitfld.long 0x38 20.--23. " TRGEVT ,Type of trigger event" "Never,Rising edge,Falling edge,Both edges,,High active,Low-active,Always,?..."
bitfld.long 0x38 16.--19. " TRIGSRC ,Trigger source" "Disabled,EXT[0],EXT[1],EXT[2],EXT[3],EXT[4],EXT[5],EXT[6],EXT[7],EXT[8],EXT[9,EXT[10,EXT[11,EXT[12,EXT[13],TICK"
textline " "
hexmask.long.byte 0x38 8.--14. 1. " PSTART ,TG start address"
hexmask.long.byte 0x38 0.--6. 1. " PCURRENT ,Pointer to current buffer"
line.long 0x3C "TG14CTRL,MibSPI Transfer Group Control Register 14"
bitfld.long 0x3C 31. " TGENA ,TG enable" "Disabled,Enabled"
bitfld.long 0x3C 30. " ONESHOT ,Single transfer for TG" "Disabled,Enabled"
bitfld.long 0x3C 29. " PRST ,TG pointer reset mode" "Disabled,Enabled"
textline " "
rbitfld.long 0x3C 28. " TGTD ,TG triggered" "Not triggered,Triggered"
bitfld.long 0x3C 20.--23. " TRGEVT ,Type of trigger event" "Never,Rising edge,Falling edge,Both edges,,High active,Low-active,Always,?..."
bitfld.long 0x3C 16.--19. " TRIGSRC ,Trigger source" "Disabled,EXT[0],EXT[1],EXT[2],EXT[3],EXT[4],EXT[5],EXT[6],EXT[7],EXT[8],EXT[9,EXT[10,EXT[11,EXT[12,EXT[13],TICK"
textline " "
hexmask.long.byte 0x3C 8.--14. 1. " PSTART ,TG start address"
hexmask.long.byte 0x3C 0.--6. 1. " PCURRENT ,Pointer to current buffer"
line.long 0x40 "TG15CTRL,MibSPI Transfer Group Control Register 15"
bitfld.long 0x40 31. " TGENA ,TG enable" "Disabled,Enabled"
bitfld.long 0x40 30. " ONESHOT ,Single transfer for TG" "Disabled,Enabled"
bitfld.long 0x40 29. " PRST ,TG pointer reset mode" "Disabled,Enabled"
textline " "
rbitfld.long 0x40 28. " TGTD ,TG triggered" "Not triggered,Triggered"
bitfld.long 0x40 20.--23. " TRGEVT ,Type of trigger event" "Never,Rising edge,Falling edge,Both edges,,High active,Low-active,Always,?..."
bitfld.long 0x40 16.--19. " TRIGSRC ,Trigger source" "Disabled,EXT[0],EXT[1],EXT[2],EXT[3],EXT[4],EXT[5],EXT[6],EXT[7],EXT[8],EXT[9,EXT[10,EXT[11,EXT[12,EXT[13],TICK"
textline " "
hexmask.long.byte 0x40 8.--14. 1. " PSTART ,TG start address"
hexmask.long.byte 0x40 0.--6. 1. " PCURRENT ,Pointer to current buffer"
line.long 0x44 "TG16CTRL,MibSPI Transfer Group Control Register 16"
bitfld.long 0x44 31. " TGENA ,TG enable" "Disabled,Enabled"
bitfld.long 0x44 30. " ONESHOT ,Single transfer for TG" "Disabled,Enabled"
bitfld.long 0x44 29. " PRST ,TG pointer reset mode" "Disabled,Enabled"
textline " "
rbitfld.long 0x44 28. " TGTD ,TG triggered" "Not triggered,Triggered"
bitfld.long 0x44 20.--23. " TRGEVT ,Type of trigger event" "Never,Rising edge,Falling edge,Both edges,,High active,Low-active,Always,?..."
bitfld.long 0x44 16.--19. " TRIGSRC ,Trigger source" "Disabled,EXT[0],EXT[1],EXT[2],EXT[3],EXT[4],EXT[5],EXT[6],EXT[7],EXT[8],EXT[9,EXT[10,EXT[11,EXT[12,EXT[13],TICK"
textline " "
hexmask.long.byte 0x44 8.--14. 1. " PSTART ,TG start address"
hexmask.long.byte 0x44 0.--6. 1. " PCURRENT ,Pointer to current buffer"
if (((d.l(ad:0xFFF7F600+0x4))&0x3)==0x0)
group.long 0xD8++0x1F
line.long 0x0 "DMA1CTRL,MibSPI DMA Channel Control Register 1"
bitfld.long 0x0 31. " ONESHOT ,Auto-disable of DMA channel after ICOUNT+1 transfers" "0,1"
hexmask.long.byte 0x0 24.--30. 1. " BUFID ,Buffer utilized for DMA transfer"
bitfld.long 0x0 20.--23. " RXDMA_MAP ,Each MibSPI DMA channel can be linked to two physical DMA" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x0 16.--19. " TXDMA_MAP ,Each MibSPI DMA channel can be linked to two physical DMA" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x0 15. " RXDMAENA ,Receive data DMA channel enable" "Disabled,Enabled"
bitfld.long 0x0 14. " TXDMAENA ,Transmit data DMA channel enable" "Disabled,Enabled"
textline " "
bitfld.long 0x0 8.--12. " ICOUNT ,Initial count of DMA transfers" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32"
rbitfld.long 0x0 6. " COUNTBIT17 ,17th bit of the COUNT field of DMAxCOUNT register" "0,1"
rbitfld.long 0x0 0.--5. " COUNT ,Actual number of remaining DMA transfers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x4 "DMA2CTRL,MibSPI DMA Channel Control Register 1"
bitfld.long 0x4 31. " ONESHOT ,Auto-disable of DMA channel after ICOUNT+1 transfers" "0,1"
hexmask.long.byte 0x4 24.--30. 1. " BUFID ,Buffer utilized for DMA transfer"
bitfld.long 0x4 20.--23. " RXDMA_MAP ,Each MibSPI DMA channel can be linked to two physical DMA" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x4 16.--19. " TXDMA_MAP ,Each MibSPI DMA channel can be linked to two physical DMA" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x4 15. " RXDMAENA ,Receive data DMA channel enable" "Disabled,Enabled"
bitfld.long 0x4 14. " TXDMAENA ,Transmit data DMA channel enable" "Disabled,Enabled"
textline " "
bitfld.long 0x4 8.--12. " ICOUNT ,Initial count of DMA transfers" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32"
rbitfld.long 0x4 6. " COUNTBIT17 ,17th bit of the COUNT field of DMAxCOUNT register" "0,1"
rbitfld.long 0x4 0.--5. " COUNT ,Actual number of remaining DMA transfers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x8 "DMA3CTRL,MibSPI DMA Channel Control Register 1"
bitfld.long 0x8 31. " ONESHOT ,Auto-disable of DMA channel after ICOUNT+1 transfers" "0,1"
hexmask.long.byte 0x8 24.--30. 1. " BUFID ,Buffer utilized for DMA transfer"
bitfld.long 0x8 20.--23. " RXDMA_MAP ,Each MibSPI DMA channel can be linked to two physical DMA" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x8 16.--19. " TXDMA_MAP ,Each MibSPI DMA channel can be linked to two physical DMA" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x8 15. " RXDMAENA ,Receive data DMA channel enable" "Disabled,Enabled"
bitfld.long 0x8 14. " TXDMAENA ,Transmit data DMA channel enable" "Disabled,Enabled"
textline " "
bitfld.long 0x8 8.--12. " ICOUNT ,Initial count of DMA transfers" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32"
rbitfld.long 0x8 6. " COUNTBIT17 ,17th bit of the COUNT field of DMAxCOUNT register" "0,1"
rbitfld.long 0x8 0.--5. " COUNT ,Actual number of remaining DMA transfers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0xC "DMA4CTRL,MibSPI DMA Channel Control Register 1"
bitfld.long 0xC 31. " ONESHOT ,Auto-disable of DMA channel after ICOUNT+1 transfers" "0,1"
hexmask.long.byte 0xC 24.--30. 1. " BUFID ,Buffer utilized for DMA transfer"
bitfld.long 0xC 20.--23. " RXDMA_MAP ,Each MibSPI DMA channel can be linked to two physical DMA" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0xC 16.--19. " TXDMA_MAP ,Each MibSPI DMA channel can be linked to two physical DMA" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0xC 15. " RXDMAENA ,Receive data DMA channel enable" "Disabled,Enabled"
bitfld.long 0xC 14. " TXDMAENA ,Transmit data DMA channel enable" "Disabled,Enabled"
textline " "
bitfld.long 0xC 8.--12. " ICOUNT ,Initial count of DMA transfers" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32"
rbitfld.long 0xC 6. " COUNTBIT17 ,17th bit of the COUNT field of DMAxCOUNT register" "0,1"
rbitfld.long 0xC 0.--5. " COUNT ,Actual number of remaining DMA transfers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x10 "DMA5CTRL,MibSPI DMA Channel Control Register 1"
bitfld.long 0x10 31. " ONESHOT ,Auto-disable of DMA channel after ICOUNT+1 transfers" "0,1"
hexmask.long.byte 0x10 24.--30. 1. " BUFID ,Buffer utilized for DMA transfer"
bitfld.long 0x10 20.--23. " RXDMA_MAP ,Each MibSPI DMA channel can be linked to two physical DMA" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x10 16.--19. " TXDMA_MAP ,Each MibSPI DMA channel can be linked to two physical DMA" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x10 15. " RXDMAENA ,Receive data DMA channel enable" "Disabled,Enabled"
bitfld.long 0x10 14. " TXDMAENA ,Transmit data DMA channel enable" "Disabled,Enabled"
textline " "
bitfld.long 0x10 8.--12. " ICOUNT ,Initial count of DMA transfers" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32"
rbitfld.long 0x10 6. " COUNTBIT17 ,17th bit of the COUNT field of DMAxCOUNT register" "0,1"
rbitfld.long 0x10 0.--5. " COUNT ,Actual number of remaining DMA transfers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x14 "DMA6CTRL,MibSPI DMA Channel Control Register 1"
bitfld.long 0x14 31. " ONESHOT ,Auto-disable of DMA channel after ICOUNT+1 transfers" "0,1"
hexmask.long.byte 0x14 24.--30. 1. " BUFID ,Buffer utilized for DMA transfer"
bitfld.long 0x14 20.--23. " RXDMA_MAP ,Each MibSPI DMA channel can be linked to two physical DMA" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x14 16.--19. " TXDMA_MAP ,Each MibSPI DMA channel can be linked to two physical DMA" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x14 15. " RXDMAENA ,Receive data DMA channel enable" "Disabled,Enabled"
bitfld.long 0x14 14. " TXDMAENA ,Transmit data DMA channel enable" "Disabled,Enabled"
textline " "
bitfld.long 0x14 8.--12. " ICOUNT ,Initial count of DMA transfers" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32"
rbitfld.long 0x14 6. " COUNTBIT17 ,17th bit of the COUNT field of DMAxCOUNT register" "0,1"
rbitfld.long 0x14 0.--5. " COUNT ,Actual number of remaining DMA transfers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x18 "DMA7CTRL,MibSPI DMA Channel Control Register 1"
bitfld.long 0x18 31. " ONESHOT ,Auto-disable of DMA channel after ICOUNT+1 transfers" "0,1"
hexmask.long.byte 0x18 24.--30. 1. " BUFID ,Buffer utilized for DMA transfer"
bitfld.long 0x18 20.--23. " RXDMA_MAP ,Each MibSPI DMA channel can be linked to two physical DMA" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x18 16.--19. " TXDMA_MAP ,Each MibSPI DMA channel can be linked to two physical DMA" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x18 15. " RXDMAENA ,Receive data DMA channel enable" "Disabled,Enabled"
bitfld.long 0x18 14. " TXDMAENA ,Transmit data DMA channel enable" "Disabled,Enabled"
textline " "
bitfld.long 0x18 8.--12. " ICOUNT ,Initial count of DMA transfers" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32"
rbitfld.long 0x18 6. " COUNTBIT17 ,17th bit of the COUNT field of DMAxCOUNT register" "0,1"
rbitfld.long 0x18 0.--5. " COUNT ,Actual number of remaining DMA transfers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x1C "DMA8CTRL,MibSPI DMA Channel Control Register 1"
bitfld.long 0x1C 31. " ONESHOT ,Auto-disable of DMA channel after ICOUNT+1 transfers" "0,1"
hexmask.long.byte 0x1C 24.--30. 1. " BUFID ,Buffer utilized for DMA transfer"
bitfld.long 0x1C 20.--23. " RXDMA_MAP ,Each MibSPI DMA channel can be linked to two physical DMA" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x1C 16.--19. " TXDMA_MAP ,Each MibSPI DMA channel can be linked to two physical DMA" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x1C 15. " RXDMAENA ,Receive data DMA channel enable" "Disabled,Enabled"
bitfld.long 0x1C 14. " TXDMAENA ,Transmit data DMA channel enable" "Disabled,Enabled"
textline " "
bitfld.long 0x1C 8.--12. " ICOUNT ,Initial count of DMA transfers" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32"
rbitfld.long 0x1C 6. " COUNTBIT17 ,17th bit of the COUNT field of DMAxCOUNT register" "0,1"
rbitfld.long 0x1C 0.--5. " COUNT ,Actual number of remaining DMA transfers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
else
group.long 0xD8++0x1F
line.long 0x0 "DMA1CTRL,MibSPI DMA Channel Control Register 1"
bitfld.long 0x0 31. " ONESHOT ,Auto-disable of DMA channel after ICOUNT+1 transfers" "0,1"
hexmask.long.byte 0x0 24.--30. 1. " BUFID ,Buffer utilized for DMA transfer"
bitfld.long 0x0 20.--23. " RXDMA_MAP ,Each MibSPI DMA channel can be linked to two physical DMA" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x0 16.--19. " TXDMA_MAP ,Each MibSPI DMA channel can be linked to two physical DMA" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x0 15. " RXDMAENA ,Receive data DMA channel enable" "Disabled,Enabled"
bitfld.long 0x0 14. " TXDMAENA ,Transmit data DMA channel enable" "Disabled,Enabled"
textline " "
bitfld.long 0x0 13. " NOBRK ,Non-interleaved DMA block transfer" "Not performed,Performed"
bitfld.long 0x0 8.--12. " ICOUNT ,Initial count of DMA transfers" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32"
rbitfld.long 0x0 6. " COUNTBIT17 ,17th bit of the COUNT field of DMAxCOUNT register" "0,1"
textline " "
rbitfld.long 0x0 0.--5. " COUNT ,Actual number of remaining DMA transfers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x4 "DMA2CTRL,MibSPI DMA Channel Control Register 1"
bitfld.long 0x4 31. " ONESHOT ,Auto-disable of DMA channel after ICOUNT+1 transfers" "0,1"
hexmask.long.byte 0x4 24.--30. 1. " BUFID ,Buffer utilized for DMA transfer"
bitfld.long 0x4 20.--23. " RXDMA_MAP ,Each MibSPI DMA channel can be linked to two physical DMA" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x4 16.--19. " TXDMA_MAP ,Each MibSPI DMA channel can be linked to two physical DMA" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x4 15. " RXDMAENA ,Receive data DMA channel enable" "Disabled,Enabled"
bitfld.long 0x4 14. " TXDMAENA ,Transmit data DMA channel enable" "Disabled,Enabled"
textline " "
bitfld.long 0x4 13. " NOBRK ,Non-interleaved DMA block transfer" "Not performed,Performed"
bitfld.long 0x4 8.--12. " ICOUNT ,Initial count of DMA transfers" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32"
rbitfld.long 0x4 6. " COUNTBIT17 ,17th bit of the COUNT field of DMAxCOUNT register" "0,1"
textline " "
rbitfld.long 0x4 0.--5. " COUNT ,Actual number of remaining DMA transfers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x8 "DMA3CTRL,MibSPI DMA Channel Control Register 1"
bitfld.long 0x8 31. " ONESHOT ,Auto-disable of DMA channel after ICOUNT+1 transfers" "0,1"
hexmask.long.byte 0x8 24.--30. 1. " BUFID ,Buffer utilized for DMA transfer"
bitfld.long 0x8 20.--23. " RXDMA_MAP ,Each MibSPI DMA channel can be linked to two physical DMA" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x8 16.--19. " TXDMA_MAP ,Each MibSPI DMA channel can be linked to two physical DMA" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x8 15. " RXDMAENA ,Receive data DMA channel enable" "Disabled,Enabled"
bitfld.long 0x8 14. " TXDMAENA ,Transmit data DMA channel enable" "Disabled,Enabled"
textline " "
bitfld.long 0x8 13. " NOBRK ,Non-interleaved DMA block transfer" "Not performed,Performed"
bitfld.long 0x8 8.--12. " ICOUNT ,Initial count of DMA transfers" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32"
rbitfld.long 0x8 6. " COUNTBIT17 ,17th bit of the COUNT field of DMAxCOUNT register" "0,1"
textline " "
rbitfld.long 0x8 0.--5. " COUNT ,Actual number of remaining DMA transfers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0xC "DMA4CTRL,MibSPI DMA Channel Control Register 1"
bitfld.long 0xC 31. " ONESHOT ,Auto-disable of DMA channel after ICOUNT+1 transfers" "0,1"
hexmask.long.byte 0xC 24.--30. 1. " BUFID ,Buffer utilized for DMA transfer"
bitfld.long 0xC 20.--23. " RXDMA_MAP ,Each MibSPI DMA channel can be linked to two physical DMA" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0xC 16.--19. " TXDMA_MAP ,Each MibSPI DMA channel can be linked to two physical DMA" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0xC 15. " RXDMAENA ,Receive data DMA channel enable" "Disabled,Enabled"
bitfld.long 0xC 14. " TXDMAENA ,Transmit data DMA channel enable" "Disabled,Enabled"
textline " "
bitfld.long 0xC 13. " NOBRK ,Non-interleaved DMA block transfer" "Not performed,Performed"
bitfld.long 0xC 8.--12. " ICOUNT ,Initial count of DMA transfers" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32"
rbitfld.long 0xC 6. " COUNTBIT17 ,17th bit of the COUNT field of DMAxCOUNT register" "0,1"
textline " "
rbitfld.long 0xC 0.--5. " COUNT ,Actual number of remaining DMA transfers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x10 "DMA5CTRL,MibSPI DMA Channel Control Register 1"
bitfld.long 0x10 31. " ONESHOT ,Auto-disable of DMA channel after ICOUNT+1 transfers" "0,1"
hexmask.long.byte 0x10 24.--30. 1. " BUFID ,Buffer utilized for DMA transfer"
bitfld.long 0x10 20.--23. " RXDMA_MAP ,Each MibSPI DMA channel can be linked to two physical DMA" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x10 16.--19. " TXDMA_MAP ,Each MibSPI DMA channel can be linked to two physical DMA" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x10 15. " RXDMAENA ,Receive data DMA channel enable" "Disabled,Enabled"
bitfld.long 0x10 14. " TXDMAENA ,Transmit data DMA channel enable" "Disabled,Enabled"
textline " "
bitfld.long 0x10 13. " NOBRK ,Non-interleaved DMA block transfer" "Not performed,Performed"
bitfld.long 0x10 8.--12. " ICOUNT ,Initial count of DMA transfers" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32"
rbitfld.long 0x10 6. " COUNTBIT17 ,17th bit of the COUNT field of DMAxCOUNT register" "0,1"
textline " "
rbitfld.long 0x10 0.--5. " COUNT ,Actual number of remaining DMA transfers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x14 "DMA6CTRL,MibSPI DMA Channel Control Register 1"
bitfld.long 0x14 31. " ONESHOT ,Auto-disable of DMA channel after ICOUNT+1 transfers" "0,1"
hexmask.long.byte 0x14 24.--30. 1. " BUFID ,Buffer utilized for DMA transfer"
bitfld.long 0x14 20.--23. " RXDMA_MAP ,Each MibSPI DMA channel can be linked to two physical DMA" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x14 16.--19. " TXDMA_MAP ,Each MibSPI DMA channel can be linked to two physical DMA" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x14 15. " RXDMAENA ,Receive data DMA channel enable" "Disabled,Enabled"
bitfld.long 0x14 14. " TXDMAENA ,Transmit data DMA channel enable" "Disabled,Enabled"
textline " "
bitfld.long 0x14 13. " NOBRK ,Non-interleaved DMA block transfer" "Not performed,Performed"
bitfld.long 0x14 8.--12. " ICOUNT ,Initial count of DMA transfers" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32"
rbitfld.long 0x14 6. " COUNTBIT17 ,17th bit of the COUNT field of DMAxCOUNT register" "0,1"
textline " "
rbitfld.long 0x14 0.--5. " COUNT ,Actual number of remaining DMA transfers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x18 "DMA7CTRL,MibSPI DMA Channel Control Register 1"
bitfld.long 0x18 31. " ONESHOT ,Auto-disable of DMA channel after ICOUNT+1 transfers" "0,1"
hexmask.long.byte 0x18 24.--30. 1. " BUFID ,Buffer utilized for DMA transfer"
bitfld.long 0x18 20.--23. " RXDMA_MAP ,Each MibSPI DMA channel can be linked to two physical DMA" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x18 16.--19. " TXDMA_MAP ,Each MibSPI DMA channel can be linked to two physical DMA" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x18 15. " RXDMAENA ,Receive data DMA channel enable" "Disabled,Enabled"
bitfld.long 0x18 14. " TXDMAENA ,Transmit data DMA channel enable" "Disabled,Enabled"
textline " "
bitfld.long 0x18 13. " NOBRK ,Non-interleaved DMA block transfer" "Not performed,Performed"
bitfld.long 0x18 8.--12. " ICOUNT ,Initial count of DMA transfers" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32"
rbitfld.long 0x18 6. " COUNTBIT17 ,17th bit of the COUNT field of DMAxCOUNT register" "0,1"
textline " "
rbitfld.long 0x18 0.--5. " COUNT ,Actual number of remaining DMA transfers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x1C "DMA8CTRL,MibSPI DMA Channel Control Register 1"
bitfld.long 0x1C 31. " ONESHOT ,Auto-disable of DMA channel after ICOUNT+1 transfers" "0,1"
hexmask.long.byte 0x1C 24.--30. 1. " BUFID ,Buffer utilized for DMA transfer"
bitfld.long 0x1C 20.--23. " RXDMA_MAP ,Each MibSPI DMA channel can be linked to two physical DMA" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x1C 16.--19. " TXDMA_MAP ,Each MibSPI DMA channel can be linked to two physical DMA" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x1C 15. " RXDMAENA ,Receive data DMA channel enable" "Disabled,Enabled"
bitfld.long 0x1C 14. " TXDMAENA ,Transmit data DMA channel enable" "Disabled,Enabled"
textline " "
bitfld.long 0x1C 13. " NOBRK ,Non-interleaved DMA block transfer" "Not performed,Performed"
bitfld.long 0x1C 8.--12. " ICOUNT ,Initial count of DMA transfers" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32"
rbitfld.long 0x1C 6. " COUNTBIT17 ,17th bit of the COUNT field of DMAxCOUNT register" "0,1"
textline " "
rbitfld.long 0x1C 0.--5. " COUNT ,Actual number of remaining DMA transfers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
endif
group.long 0xF8++0x1F
line.long 0x0 "DMA0COUNT,MibSPI DMA0COUNT Register"
hexmask.long.word 0x0 16.--31. 1. " ICOUNT0 ,Initial number of DMA transfers"
hexmask.long.word 0x0 0.--15. 1. " COUNT0 ,The actual number of remaining DMA transfers"
line.long 0x4 "DMA1COUNT,MibSPI DMA1COUNT Register"
hexmask.long.word 0x4 16.--31. 1. " ICOUNT1 ,Initial number of DMA transfers"
hexmask.long.word 0x4 0.--15. 1. " COUNT1 ,The actual number of remaining DMA transfers"
line.long 0x8 "DMA2COUNT,MibSPI DMA2COUNT Register"
hexmask.long.word 0x8 16.--31. 1. " ICOUNT2 ,Initial number of DMA transfers"
hexmask.long.word 0x8 0.--15. 1. " COUNT2 ,The actual number of remaining DMA transfers"
line.long 0xC "DMA3COUNT,MibSPI DMA3COUNT Register"
hexmask.long.word 0xC 16.--31. 1. " ICOUNT3 ,Initial number of DMA transfers"
hexmask.long.word 0xC 0.--15. 1. " COUNT3 ,The actual number of remaining DMA transfers"
line.long 0x10 "DMA4COUNT,MibSPI DMA4COUNT Register"
hexmask.long.word 0x10 16.--31. 1. " ICOUNT4 ,Initial number of DMA transfers"
hexmask.long.word 0x10 0.--15. 1. " COUNT4 ,The actual number of remaining DMA transfers"
line.long 0x14 "DMA5COUNT,MibSPI DMA5COUNT Register"
hexmask.long.word 0x14 16.--31. 1. " ICOUNT5 ,Initial number of DMA transfers"
hexmask.long.word 0x14 0.--15. 1. " COUNT5 ,The actual number of remaining DMA transfers"
line.long 0x18 "DMA6COUNT,MibSPI DMA6COUNT Register"
hexmask.long.word 0x18 16.--31. 1. " ICOUNT6 ,Initial number of DMA transfers"
hexmask.long.word 0x18 0.--15. 1. " COUNT6 ,The actual number of remaining DMA transfers"
line.long 0x1C "DMA7COUNT,MibSPI DMA7COUNT Register"
hexmask.long.word 0x1C 16.--31. 1. " ICOUNT7 ,Initial number of DMA transfers"
hexmask.long.word 0x1C 0.--15. 1. " COUNT7 ,The actual number of remaining DMA transfers"
textline " "
group.long 0x118++0x03
line.long 0x00 "DMACNTLEN,MibSPI DMACNTLEN Register"
bitfld.long 0x00 0. " LARGECOUNT ,Counters select" "DMAxCTRL,DMAxCOUNT"
group.long 0x120++0x03
line.long 0x00 "UERRCTRL,Uncorrectable Parity Error Control Register"
sif cpu()=="TMS570LC4357"
bitfld.long 0x00 24.--27. " SBE_EVT_EN ,ECC Single Bit Error Event Enable" ",,,,,Disabled,,,,,Enabled,?..."
bitfld.long 0x00 16.--19. " EDAC_MODE ,ECC Single Bit Error Block Correction" ",,,,,Disabled,,,,,Enabled,?..."
textline " "
endif
bitfld.long 0x00 8. " PTESTEN ,Parity memory test enable" "Disabled,Enabled"
bitfld.long 0x00 0.--3. " EDEN ,Error detection enable" "Enabled,Enabled,Enabled,Enabled,Enabled,Disabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled"
group.long 0x124++0x03
line.long 0x00 "UERRSTAT,Uncorrectable Parity Error Status Register"
sif cpu()=="TMS570LC4357"
eventfld.long 0x00 9. " SBE_FLG1 ,Single Bit Error in RXRAM" "Not occurred,Occurred"
eventfld.long 0x00 8. " SBE_FLG0 ,Single Bit Error in TXRAM" "Not occurred,Occurred"
textline " "
eventfld.long 0x00 1. " EDFLG1 ,Uncorrectable parity error detection flag" "Not occurred,Occurred"
eventfld.long 0x00 0. " EDFLG0 ,Uncorrectable parity error detection flag" "Not occurred,Occurred"
else
eventfld.long 0x00 1. " EDFLG1 ,Uncorrectable parity error detection flag" "Not occurred,Occurred"
eventfld.long 0x00 0. " EDFLG0 ,Uncorrectable parity error detection flag" "Not occurred,Occurred"
endif
width 17.
hgroup.long 0x128++0x03
hide.long 0x00 "UERRADDR1,Uncorrectable Parity Error Address Register"
in
hgroup.long 0x12C++0x03
hide.long 0x00 "UERRADDR0,Uncorrectable Parity Error Address Register"
in
hgroup.long 0x130++0x03
hide.long 0x00 "RXOVRN_BUF_ADDR,Receive RAM Overrun Buffer Address Register"
in
textline " "
width 14.
if (((d.l(ad:0xFFF7F600+0x134))&0x2)==0x2)&&(((d.l(ad:0xFFF7F600+0x134))&0xF00)==0xA00)
group.long 0x134++0x03
line.long 0x00 "IOLPBKTSTCR,SPI IO Loopback Test Control Register"
bitfld.long 0x00 24. " SCSFAILFLG ,Failure on SPISCS pin compare during analog loopback" "Not occurred,Occurred"
bitfld.long 0x00 20. " CTRL_BITERR ,Controls inducing of BITERR during I/O loopback test mode" "Disabled,Enabled"
bitfld.long 0x00 19. " CTRL_DESYNC ,Controls inducing of the desync error during I/O loopback test mode" "No error,Error"
textline " "
bitfld.long 0x00 18. " CTRL_PARERR ,Controls inducing of parity errors during I/O loopback test mode" "No error,Error"
bitfld.long 0x00 17. " CTRL_TIMEOUT ,Controls inducing of the timeout error during I/O loopbacK test mode" "No error,Error"
bitfld.long 0x00 16. " CTRL_DLENERR ,Controls inducing of the data length error during I/O loopback test mode" "No error,Error"
textline " "
bitfld.long 0x00 8.--11. " IOLPBKTSTENA ,Module I/O loopback test enable key" "Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Enabled,Disabled,Disabled,Disabled,Disabled,Disabled"
bitfld.long 0x00 3.--5. " ERRSCSPIN ,Inject error on chip-select pin number" "/SPISCS[0],/SPISCS[1],/SPISCS[2],/SPISCS[3],/SPISCS[4],/SPISCS[5],/SPISCS[6],/SPISCS[7]"
bitfld.long 0x00 2. " CTRLSCSPINERR ,Enable/disable the injection of an error on the SPISCS[3:0] pins" "Disabled,Enabled"
textline " "
bitfld.long 0x00 1. " LPBK_TYPE ,Module I/O loopback type (analog/digital)" "Digital,Analog"
bitfld.long 0x00 0. " RXP_ENA ,Enable analog loopback through the receive pin" "Transmit,Receive"
elif (((d.l(ad:0xFFF7F600+0x134))&0x2)==0x0)&&(((d.l(ad:0xFFF7F600+0x134))&0xF00)==0xA00)
group.long 0x134++0x03
line.long 0x00 "IOLPBKTSTCR,SPI IO Loopback Test Control Register"
eventfld.long 0x00 24. " SCSFAILFLG ,Failure on SPISCS pin compare during analog loopback" "Not occurred,Occurred"
bitfld.long 0x00 20. " CTRL_BITERR ,Controls inducing of BITERR during I/O loopback test mode" "Disabled,Enabled"
bitfld.long 0x00 19. " CTRL_DESYNC ,Controls inducing of the desync error during I/O loopback test mode" "No error,Error"
textline " "
bitfld.long 0x00 18. " CTRL_PARERR ,Controls inducing of parity errors during I/O loopback test mode" "No error,Error"
bitfld.long 0x00 17. " CTRL_TIMEOUT ,Controls inducing of the timeout error during I/O loopbacK test mode" "No error,Error"
bitfld.long 0x00 16. " CTRL_DLENERR ,Controls inducing of the data length error during I/O loopback test mode" "No error,Error"
textline " "
bitfld.long 0x00 8.--11. " IOLPBKTSTENA ,Module I/O loopback test enable key" "Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Enabled,Disabled,Disabled,Disabled,Disabled,Disabled"
bitfld.long 0x00 3.--5. " ERRSCSPIN ,Inject error on chip-select pin number" "/SPISCS[0],/SPISCS[1],/SPISCS[2],/SPISCS[3],/SPISCS[4],/SPISCS[5],/SPISCS[6],/SPISCS[7]"
bitfld.long 0x00 2. " CTRLSCSPINERR ,Enable/disable the injection of an error on the SPISCS[3:0] pins" "Disabled,Enabled"
textline " "
bitfld.long 0x00 1. " LPBK_TYPE ,Module I/O loopback type (analog/digital)" "Digital,Analog"
elif (((d.l(ad:0xFFF7F600+0x134))&0x2)==0x2)&&(((d.l(ad:0xFFF7F600+0x134))&0xF00)!=0xA00)
group.long 0x134++0x03
line.long 0x00 "IOLPBKTSTCR,SPI IO Loopback Test Control Register"
bitfld.long 0x00 8.--11. " IOLPBKTSTENA ,Module I/O loopback test enable key" "Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Enabled,Disabled,Disabled,Disabled,Disabled,Disabled"
bitfld.long 0x00 3.--5. " ERRSCSPIN ,Inject error on chip-select pin number" "/SPISCS[0],/SPISCS[1],/SPISCS[2],/SPISCS[3],/SPISCS[4],/SPISCS[5],/SPISCS[6],/SPISCS[7]"
bitfld.long 0x00 2. " CTRLSCSPINERR ,Enable/disable the injection of an error on the SPISCS[3:0] pins" "Disabled,Enabled"
textline " "
bitfld.long 0x00 1. " LPBK_TYPE ,Module I/O loopback type (analog/digital)" "Digital,Analog"
bitfld.long 0x00 0. " RXP_ENA ,Enable analog loopback through the receive pin" "Transmit,Receive"
else
group.long 0x134++0x03
line.long 0x00 "IOLPBKTSTCR,SPI IO Loopback Test Control Register"
bitfld.long 0x00 8.--11. " IOLPBKTSTENA ,Module I/O loopback test enable key" "Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Enabled,Disabled,Disabled,Disabled,Disabled,Disabled"
bitfld.long 0x00 3.--5. " ERRSCSPIN ,Inject error on chip-select pin number" "/SPISCS[0],/SPISCS[1],/SPISCS[2],/SPISCS[3],/SPISCS[4],/SPISCS[5],/SPISCS[6],/SPISCS[7]"
bitfld.long 0x00 2. " CTRLSCSPINERR ,Enable/disable the injection of an error on the SPISCS[3:0] pins" "Disabled,Enabled"
textline " "
bitfld.long 0x00 1. " LPBK_TYPE ,Module I/O loopback type (analog/digital)" "Digital,Analog"
endif
textline " "
width 21.
group.long 0x138++0x07
line.long 0x00 "EXTENDED_PRESCALE_1,SPI Extended Prescale Register 1"
hexmask.long.word 0x00 16.--26. 1. " EPRESCALE_FMT1 ,Extended Prescale value for SPIFMT1"
hexmask.long.word 0x00 0.--10. 1. " EPRESCALE_FMT0 ,Extended Prescale value for SPIFMT0"
line.long 0x04 "EXTENDED_PRESCALE_2,SPI Extended Prescale Register 2"
hexmask.long.word 0x04 16.--26. 1. " EPRESCALE_FMT3 ,Extended Prescale value for SPIFMT3"
hexmask.long.word 0x04 0.--10. 1. " EPRESCALE_FMT2 ,Extended Prescale value for SPIFMT2"
sif cpu()!="TMS570LC4357"
group.long 0x140++0x03
line.long 0x00 "ECCDIAG_CTRL,ECC Diagnostic Control register"
bitfld.long 0x00 0.--3. " ECCDIAG_EN ,ECC Diagnostic mode Enable Key bits" "Disabled,Disabled,Disabled,Disabled,Disabled,Enabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled"
endif
if ((d.l(ad:0xFFF7F600+0x140)&0x5)==0x5)
group.long 0x144++0x03
line.long 0x00 "ECCDIAG_STAT, ECC Diagnostic Status Register"
eventfld.long 0x00 17. " DEFLG[1] ,Double bit Error is detected for RXRAM" "No error,Error"
eventfld.long 0x00 16. " DEFLG[0] ,Double bit Error is detected for TXRAM" "No error,Error"
eventfld.long 0x00 1. " SEFLG[1] ,Single bit Error is detected for RXRAM" "No error,Error"
eventfld.long 0x00 0. " SEFLG[0] ,Single bit Error is detected for TXRAM" "No error,Error"
else
hgroup.long 0x144++0x03
hide.long 0x00 "ECCDIAG_STAT,ECC Diagnostic Status Register"
in
endif
hgroup.long 0x148++0x03
hide.long 0x00 "SBERRADDR1,Single Bit Error Address Register - RXRAM"
in
hgroup.long 0x14C++0x03
hide.long 0x00 "SBERRADDR0,Single Bit Error Address Register - TXRAM"
in
tree.end
tree "MibSPI3"
base ad:0xFFF7F800
width 17.
group.long 0x00++0x03
line.long 0x00 "SPIGCR0,SPI Global Control Register 0"
bitfld.long 0x00 0. " NRESET ,Reset bit for the module" "No reset,Reset"
if (((d.l(ad:0xFFF7F800+0x4))&0x3)==0x00)
group.long 0x04++0x03
line.long 0x00 "SPIGCR1,SPI Global Control Register 1"
bitfld.long 0x00 24. " SPIEN ,SPI enable" "Disabled,Enabled"
bitfld.long 0x00 16. " LOOPBACK ,Internal loop-back test mode" "Disabled,Enabled"
bitfld.long 0x00 8. " POWERDOWN ,SPI state machine enters a power-down state" "No power-down,Power-down"
textline " "
bitfld.long 0x00 1. " CLKMOD ,Clock mode" "External,Internally"
bitfld.long 0x00 0. " MASTER ,SPISIMO/SPISOMI pin direction determination" "Input/ouput,Output/input"
else
group.long 0x04++0x03
line.long 0x00 "SPIGCR1,SPI Global Control Register 1"
bitfld.long 0x00 24. " SPIEN ,SPI enable" "Disabled,Enabled"
bitfld.long 0x00 8. " POWERDOWN ,SPI state machine enters a power-down state" "No power-down,Power-down"
bitfld.long 0x00 1. " CLKMOD ,Clock mode" "External,Internally"
textline " "
bitfld.long 0x00 0. " MASTER ,SPISIMO/SPISOMI pin direction determination" "Input/ouput,Output/input"
endif
group.long 0x08++0x03
line.long 0x00 "SPIINT0,SPI Interrupt Register"
bitfld.long 0x00 24. " ENABLEHIGHZ ,SPIENA pin high-impedance enable" "Inactive,Active"
bitfld.long 0x00 16. " DMAREQEN ,DMA request enable" "Disabled,Enabled"
bitfld.long 0x00 9. " TXINTENA ,TX interrupt flag enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 8. " RXINTENA ,RX interrupt flag enable" "Disabled,Enabled"
bitfld.long 0x00 6. " RXOVRNINTENA ,Overrun interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 4. " BITERRENA ,Enables interrupt on bit error" "Disabled,Enabled"
textline " "
bitfld.long 0x00 3. " DESYNCENA ,Enables interrupt on desynchronized slave" "Disabled,Enabled"
bitfld.long 0x00 2. " PARERRENA ,Enables interrupt-on-parity-error" "Disabled,Enabled"
bitfld.long 0x00 1. " TIMEOUTENA ,Enables interrupt on ENA signal time-out" "Disabled,Enabled"
textline " "
bitfld.long 0x00 0. " DLENERRENA ,Data length error interrupt enable" "Disabled,Enabled"
group.long 0x0C++0x03
line.long 0x00 "SPILVL,SPI Interrupt Level Register"
bitfld.long 0x00 9. " TXINTLVL ,Transmit interrupt level" "INT0,INT1"
bitfld.long 0x00 8. " RXINTLVL ,Receive interrupt level" "INT0,INT1"
bitfld.long 0x00 6. " RXOVRNINTLVL ,Receive overrun interrupt level" "INT0,INT1"
textline " "
bitfld.long 0x00 4. " BITERRLVL ,Bit error interrupt level" "INT0,INT1"
bitfld.long 0x00 3. " DESYNCLVL ,Desynchronized slave interrupt level (master mode only)" "INT0,INT1"
bitfld.long 0x00 2. " PARERRLVL ,Parity error interrupt level" "INT0,INT1"
textline " "
bitfld.long 0x00 1. " TIMEOUTLVL ,SPIENA pin time-out interrupt level" "INT0,INT1"
bitfld.long 0x00 0. " DLENERRLVL ,Data length error interrupt level (line) select" "INT0,INT1"
group.long 0x10++0x03
line.long 0x00 "SPIFLG,SPI Flag Register"
rbitfld.long 0x00 24. " BUFINITACTIVE ,Indicates the status of multi-buffer initialization process" "Completed,Not completed"
rbitfld.long 0x00 9. " TXINTFLG ,Transmitter-empty interrupt flag" "No interrupt,Interrupt"
eventfld.long 0x00 8. " RXINTFLG ,Receiver-full interrupt flag" "No interrupt,Interrupt"
textline " "
eventfld.long 0x00 6. " RXOVRNINTFLG ,Overrun interrupt enable" "Disabled,Enabled"
eventfld.long 0x00 4. " BITERRFLG ,Enables interrupt on bit error" "Disabled,Enabled"
eventfld.long 0x00 3. " DESYNCFLG ,Enables interrupt on desynchronized slave" "No interrupt,Interrupt"
textline " "
eventfld.long 0x00 2. " PARITYERRFLG ,Enables interrupt-on-parity-error" "No error,Error"
eventfld.long 0x00 1. " TIMEOUTFLG ,Enables interrupt on ENA signal time-out" "No interrupt,Interrupt"
eventfld.long 0x00 0. " DLENERRFLG ,Data length error interrupt enable" "No interrupt,Interrupt"
textline " "
width 12.
group.long 0x14++0x23
line.long 0x00 "SPIPC0,SPI Pin Control Register 0"
bitfld.long 0x00 31. " SOMIFUN[7] ,SPISOMI[7] pin function" "GIO,SPI"
bitfld.long 0x00 30. " [6] ,SPISOMI[6] pin function" "GIO,SPI"
bitfld.long 0x00 29. " [5] ,SPISOMI[5] pin function" "GIO,SPI"
bitfld.long 0x00 28. " [4] ,SPISOMI[4] pin function" "GIO,SPI"
textline " "
bitfld.long 0x00 27. " [3] ,SPISOMI[3] pin function" "GIO,SPI"
bitfld.long 0x00 26. " [2] ,SPISOMI[2] pin function" "GIO,SPI"
bitfld.long 0x00 25. " [1] ,SPISOMI[1] pin function" "GIO,SPI"
bitfld.long 0x00 24. " [0] ,SPISOMI[0] pin function (mirror of bit 11)" "GIO,SPI"
textline " "
bitfld.long 0x00 23. " SIMOFUN[7] ,SPISIMO[7] pin function" "GIO,SPI"
bitfld.long 0x00 22. " [6] ,SPISIMO[6] pin function" "GIO,SPI"
bitfld.long 0x00 21. " [5] ,SPISIMO[5] pin function" "GIO,SPI"
bitfld.long 0x00 20. " [4] ,SPISIMO[4] pin function" "GIO,SPI"
textline " "
bitfld.long 0x00 19. " [3] ,SPISIMO[3] pin function" "GIO,SPI"
bitfld.long 0x00 18. " [2] ,SPISIMO[2] pin function" "GIO,SPI"
bitfld.long 0x00 17. " [1] ,SPISIMO[1] pin function" "GIO,SPI"
bitfld.long 0x00 16. " [0] ,SPISIMO[0] pin function (mirror of bit 10)" "GIO,SPI"
textline " "
bitfld.long 0x00 11. " SOMIFUN[0] ,SPISOMI[0] pin function" "GIO,SPI"
bitfld.long 0x00 10. " SIMOFUN[0] ,SPISIMO[0] pin function" "GIO,SPI"
bitfld.long 0x00 9. " CLKFUN ,SPI clock function" "GIO,SPI"
bitfld.long 0x00 8. " ENAFUN ,SPIENA function" "GIO,SPI"
textline " "
textline " "
bitfld.long 0x00 7. " SCSFUN[7] ,SPISCS7 function 7" "GIO,SPI"
bitfld.long 0x00 6. " [6] ,SPISCS6 function 6" "GIO,SPI"
bitfld.long 0x00 5. " [5] ,SPISCS5 function 5" "GIO,SPI"
bitfld.long 0x00 4. " [4] ,SPISCS4 function 4" "GIO,SPI"
textline " "
bitfld.long 0x00 3. " [3] ,SPISCS3 function 3" "GIO,SPI"
bitfld.long 0x00 2. " [2] ,SPISCS2 function 2" "GIO,SPI"
bitfld.long 0x00 1. " [1] ,SPISCS1 function 1" "GIO,SPI"
bitfld.long 0x00 0. " [0] ,SPISCS0 function 0" "GIO,SPI"
textline " "
line.long 0x04 "SPIPC1,SPI Pin Control Register 1"
bitfld.long 0x04 31. " SOMIDIR[7] ,SPISOMI[7] pin direction" "GIO,SPI"
bitfld.long 0x04 30. " [6] ,SPISOMI[6] pin direction" "GIO,SPI"
bitfld.long 0x04 29. " [5] ,SPISOMI[5] pin direction" "GIO,SPI"
bitfld.long 0x04 28. " [4] ,SPISOMI[4] pin direction" "GIO,SPI"
textline " "
bitfld.long 0x04 27. " [3] ,SPISOMI[3] pin direction" "GIO,SPI"
bitfld.long 0x04 26. " [2] ,SPISOMI[2] pin direction" "GIO,SPI"
bitfld.long 0x04 25. " [1] ,SPISOMI[1] pin direction" "GIO,SPI"
bitfld.long 0x04 24. " [0] ,SPISOMI[0] pin direction (mirror of bit 11)" "GIO,SPI"
textline " "
bitfld.long 0x04 23. " SIMODIR[7] ,SPISIMO[7] pin direction" "GIO,SPI"
bitfld.long 0x04 22. " [6] ,SPISIMO[6] pin direction" "GIO,SPI"
bitfld.long 0x04 21. " [5] ,SPISIMO[5] pin direction" "GIO,SPI"
bitfld.long 0x04 20. " [4] ,SPISIMO[4] pin direction" "GIO,SPI"
textline " "
bitfld.long 0x04 19. " [3] ,SPISIMO[3] pin direction" "GIO,SPI"
bitfld.long 0x04 18. " [2] ,SPISIMO[2] pin direction" "GIO,SPI"
bitfld.long 0x04 17. " [1] ,SPISIMO[1] pin direction" "GIO,SPI"
bitfld.long 0x04 16. " [0] ,SPISIMO[0] pin direction (mirror of bit 10)" "GIO,SPI"
textline " "
bitfld.long 0x04 11. " SOMIDIR[0] ,SPISOMI[0] pin direction" "GIO,SPI"
bitfld.long 0x04 10. " SIMODIR[0] ,SPISIMO[0] pin direction" "GIO,SPI"
bitfld.long 0x04 9. " CLKDIR ,SPI clock direction" "GIO,SPI"
bitfld.long 0x04 8. " ENADIR ,SPIENA direction" "GIO,SPI"
textline " "
textline " "
bitfld.long 0x04 7. " SCSDIR[7] ,SPISCS7 direction 7" "GIO,SPI"
bitfld.long 0x04 6. " [6] ,SPISCS6 direction 6" "GIO,SPI"
bitfld.long 0x04 5. " [5] ,SPISCS5 direction 5" "GIO,SPI"
bitfld.long 0x04 4. " [4] ,SPISCS4 direction 4" "GIO,SPI"
textline " "
bitfld.long 0x04 3. " [3] ,SPISCS3 direction 3" "GIO,SPI"
bitfld.long 0x04 2. " [2] ,SPISCS2 direction 2" "GIO,SPI"
bitfld.long 0x04 1. " [1] ,SPISCS1 direction 1" "GIO,SPI"
bitfld.long 0x04 0. " [0] ,SPISCS0 direction 0" "GIO,SPI"
textline " "
line.long 0x08 "SPIPC2,SPI Pin Control Register 2"
bitfld.long 0x08 31. " SOMIDIN[7] ,SPISOMI[7] data in" "0,1"
bitfld.long 0x08 30. " [6] ,SPISOMI[6] data in" "0,1"
bitfld.long 0x08 29. " [5] ,SPISOMI[5] data in" "0,1"
bitfld.long 0x08 28. " [4] ,SPISOMI[4] data in" "0,1"
bitfld.long 0x08 27. " [3] ,SPISOMI[3] data in" "0,1"
bitfld.long 0x08 26. " [2] ,SPISOMI[2] data in" "0,1"
bitfld.long 0x08 25. " [1] ,SPISOMI[1] data in" "0,1"
bitfld.long 0x08 24. " [0] ,SPISOMI[0] data in (mirror of bit 11)" "0,1"
textline " "
bitfld.long 0x08 23. " SIMODIN[7] ,SPISIMO[7] data in" "0,1"
bitfld.long 0x08 22. " [6] ,SPISIMO[6] data in" "0,1"
bitfld.long 0x08 21. " [5] ,SPISIMO[5] data in" "0,1"
bitfld.long 0x08 20. " [4] ,SPISIMO[4] data in" "0,1"
bitfld.long 0x08 19. " [3] ,SPISIMO[3] data in" "0,1"
bitfld.long 0x08 18. " [2] ,SPISIMO[2] data in" "0,1"
bitfld.long 0x08 17. " [1] ,SPISIMO[1] data in" "0,1"
bitfld.long 0x08 16. " [0] ,SPISIMO[0] data in (mirror of bit 10)" "0,1"
textline " "
bitfld.long 0x08 11. " SOMIDIN[0] ,SPISOMI[0] data in" "0,1"
bitfld.long 0x08 10. " SIMODIN[0] ,SPISIMO[0] data in" "0,1"
bitfld.long 0x08 9. " CLKDIN ,SPI clock data in" "0,1"
bitfld.long 0x08 8. " ENADIN ,SPIENA data in" "0,1"
textline " "
textline " "
bitfld.long 0x08 7. " SCSDIN[7] ,SPISCS7 data in" "0,1"
bitfld.long 0x08 6. " [6] ,SPISCS6 data in" "0,1"
bitfld.long 0x08 5. " [5] ,SPISCS5 data in" "0,1"
bitfld.long 0x08 4. " [4] ,SPISCS4 data in" "0,1"
bitfld.long 0x08 3. " [3] ,SPISCS3 data in" "0,1"
bitfld.long 0x08 2. " [2] ,SPISCS2 data in" "0,1"
bitfld.long 0x08 1. " [1] ,SPISCS1 data in" "0,1"
bitfld.long 0x08 0. " [0] ,SPISCS0 direction 0" "0,1"
textline " "
line.long 0x0C "SPIPC3,SPI Pin Control Register 3"
bitfld.long 0x0C 31. " SOMIDOUT[7] ,SPISOMI[7] data out write" "0,1"
bitfld.long 0x0C 30. " [6] ,SPISOMI[6] data out write" "0,1"
bitfld.long 0x0C 29. " [5] ,SPISOMI[5] data out write" "0,1"
bitfld.long 0x0C 28. " [4] ,SPISOMI[4] data out write" "0,1"
bitfld.long 0x0C 27. " [3] ,SPISOMI[3] data out write" "0,1"
bitfld.long 0x0C 26. " [2] ,SPISOMI[2] data out write" "0,1"
bitfld.long 0x0C 25. " [1] ,SPISOMI[1] data out write" "0,1"
bitfld.long 0x0C 24. " [0] ,SPISOMI[0] data out write (mirror of bit 11)" "0,1"
textline " "
bitfld.long 0x0C 23. " SIMODOUT[7] ,SPISIMO[7] data out write" "0,1"
bitfld.long 0x0C 22. " [6] ,SPISIMO[6] data out write" "0,1"
bitfld.long 0x0C 21. " [5] ,SPISIMO[5] data out write" "0,1"
bitfld.long 0x0C 20. " [4] ,SPISIMO[4] data out write" "0,1"
bitfld.long 0x0C 19. " [3] ,SPISIMO[3] data out write" "0,1"
bitfld.long 0x0C 18. " [2] ,SPISIMO[2] data out write" "0,1"
bitfld.long 0x0C 17. " [1] ,SPISIMO[1] data out write" "0,1"
bitfld.long 0x0C 16. " [0] ,SPISIMO[0] data out write (mirror of bit 10)" "0,1"
textline " "
bitfld.long 0x0C 11. " SOMIDOUT[0] ,SPISOMI[0] data out write" "0,1"
bitfld.long 0x0C 10. " SIMODOUT[0] ,SPISIMO[0] data out write" "0,1"
bitfld.long 0x0C 9. " CLKDOUT ,SPI clock data out write" "0,1"
bitfld.long 0x0C 8. " ENADOUT ,SPIENA data out write" "0,1"
textline " "
textline " "
bitfld.long 0x0C 7. " SCSDOUT[7] ,SPISCS7 data out write" "0,1"
bitfld.long 0x0C 6. " [6] ,SPISCS6 data out write" "0,1"
bitfld.long 0x0C 5. " [5] ,SPISCS5 data out write" "0,1"
bitfld.long 0x0C 4. " [4] ,SPISCS4 data out write" "0,1"
bitfld.long 0x0C 3. " [3] ,SPISCS3 data out write" "0,1"
bitfld.long 0x0C 2. " [2] ,SPISCS2 data out write" "0,1"
bitfld.long 0x0C 1. " [1] ,SPISCS1 data out write" "0,1"
bitfld.long 0x0C 0. " [0] ,SPISCS0 data out write" "0,1"
textline " "
line.long 0x10 "SPIPC4,SPI Pin Control Register 4"
bitfld.long 0x10 31. " SOMISET[7] ,SPISOMI[7] data out set" "0,1"
bitfld.long 0x10 30. " [6] ,SPISOMI[6] data out set" "0,1"
bitfld.long 0x10 29. " [5] ,SPISOMI[5] data out set" "0,1"
bitfld.long 0x10 28. " [4] ,SPISOMI[4] data out set" "0,1"
bitfld.long 0x10 27. " [3] ,SPISOMI[3] data out set" "0,1"
bitfld.long 0x10 26. " [2] ,SPISOMI[2] data out set" "0,1"
bitfld.long 0x10 25. " [1] ,SPISOMI[1] data out set" "0,1"
bitfld.long 0x10 24. " [0] ,SPISOMI[0] data out set (mirror of bit 11)" "0,1"
textline " "
bitfld.long 0x10 23. " SIMOSET[7] ,SPISIMO[7] data out set" "0,1"
bitfld.long 0x10 22. " [6] ,SPISIMO[6] data out set" "0,1"
bitfld.long 0x10 21. " [5] ,SPISIMO[5] data out set" "0,1"
bitfld.long 0x10 20. " [4] ,SPISIMO[4] data out set" "0,1"
bitfld.long 0x10 19. " [3] ,SPISIMO[3] data out set" "0,1"
bitfld.long 0x10 18. " [2] ,SPISIMO[2] data out set" "0,1"
bitfld.long 0x10 17. " [1] ,SPISIMO[1] data out set" "0,1"
bitfld.long 0x10 16. " [0] ,SPISIMO[0] data out set (mirror of bit 10)" "0,1"
textline " "
bitfld.long 0x10 11. " SOMISET[0] ,SPISOMI[0] data out set" "0,1"
bitfld.long 0x10 10. " SIMOSET[0] ,SPISIMO[0] data out set" "0,1"
bitfld.long 0x10 9. " CLKSET ,SPI clock data out set" "0,1"
bitfld.long 0x10 8. " ENASET ,SPIENA data out set" "0,1"
textline " "
textline " "
bitfld.long 0x10 7. " SCSSET[7] ,SPISCS7 data out set" "0,1"
bitfld.long 0x10 6. " [6] ,SPISCS6 data out set" "0,1"
bitfld.long 0x10 5. " [5] ,SPISCS5 data out set" "0,1"
bitfld.long 0x10 4. " [4] ,SPISCS4 data out set" "0,1"
bitfld.long 0x10 3. " [3] ,SPISCS3 data out set" "0,1"
bitfld.long 0x10 2. " [2] ,SPISCS2 data out set" "0,1"
bitfld.long 0x10 1. " [1] ,SPISCS1 data out set" "0,1"
bitfld.long 0x10 0. " [0] ,SPISCS0 data out set" "0,1"
textline " "
line.long 0x14 "SPIPC5,SPI Pin Control Register 5"
bitfld.long 0x14 31. " SOMICLR[7] ,SPISOMI[7] data out clear" "0,1"
bitfld.long 0x14 30. " [6] ,SPISOMI[6] data out clear" "0,1"
bitfld.long 0x14 29. " [5] ,SPISOMI[5] data out clear" "0,1"
bitfld.long 0x14 28. " [4] ,SPISOMI[4] data out clear" "0,1"
bitfld.long 0x14 27. " [3] ,SPISOMI[3] data out clear" "0,1"
bitfld.long 0x14 26. " [2] ,SPISOMI[2] data out clear" "0,1"
bitfld.long 0x14 25. " [1] ,SPISOMI[1] data out clear" "0,1"
bitfld.long 0x14 24. " [0] ,SPISOMI[0] data out clear (mirror of bit 11)" "0,1"
textline " "
bitfld.long 0x14 23. " SIMOCLR[7] ,SPISIMO[7] data out clear" "0,1"
bitfld.long 0x14 22. " [6] ,SPISIMO[6] data out clear" "0,1"
bitfld.long 0x14 21. " [5] ,SPISIMO[5] data out clear" "0,1"
bitfld.long 0x14 20. " [4] ,SPISIMO[4] data out clear" "0,1"
bitfld.long 0x14 19. " [3] ,SPISIMO[3] data out clear" "0,1"
bitfld.long 0x14 18. " [2] ,SPISIMO[2] data out clear" "0,1"
bitfld.long 0x14 17. " [1] ,SPISIMO[1] data out clear" "0,1"
bitfld.long 0x14 16. " [0] ,SPISIMO[0] data out clear (mirror of bit 10)" "0,1"
textline " "
bitfld.long 0x14 11. " SOMICLR[0] ,SPISOMI[0] data out clear" "0,1"
bitfld.long 0x14 10. " SIMOCLR[0] ,SPISIMO[0] data out clear" "0,1"
bitfld.long 0x14 9. " CLKCLR ,SPI clock data out clear" "0,1"
bitfld.long 0x14 8. " ENACLR ,SPIENA data out clear" "0,1"
textline " "
textline " "
bitfld.long 0x14 7. " SCSCLR[7] ,SPISCS7 data out clear" "0,1"
bitfld.long 0x14 6. " [6] ,SPISCS6 data out clear" "0,1"
bitfld.long 0x14 5. " [5] ,SPISCS5 data out clear" "0,1"
bitfld.long 0x14 4. " [4] ,SPISCS4 data out clear" "0,1"
bitfld.long 0x14 3. " [3] ,SPISCS3 data out clear" "0,1"
bitfld.long 0x14 2. " [2] ,SPISCS2 data out clear" "0,1"
bitfld.long 0x14 1. " [1] ,SPISCS1 data out clear" "0,1"
bitfld.long 0x14 0. " [0] ,SPISCS0 data out clear" "0,1"
textline " "
line.long 0x18 "SPIPC6,SPI Pin Control Register 6"
bitfld.long 0x18 31. " SOMIPDR[7] ,SPISOMI[7] open drain enable" "Disabled,Enabled"
bitfld.long 0x18 30. " [6] ,SPISOMI[6] open drain enable" "Disabled,Enabled"
bitfld.long 0x18 29. " [5] ,SPISOMI[5] open drain enable" "Disabled,Enabled"
bitfld.long 0x18 28. " [4] ,SPISOMI[4] open drain enable" "Disabled,Enabled"
textline " "
bitfld.long 0x18 27. " [3] ,SPISOMI[3] open drain enable" "Disabled,Enabled"
bitfld.long 0x18 26. " [2] ,SPISOMI[2] open drain enable" "Disabled,Enabled"
bitfld.long 0x18 25. " [1] ,SPISOMI[1] open drain enable" "Disabled,Enabled"
bitfld.long 0x18 24. " [0] ,SPISOMI[0] open drain enable (mirror of bit 11)" "Disabled,Enabled"
textline " "
bitfld.long 0x18 23. " SIMOPDR[7] ,SPISIMO[7] open drain enable" "Disabled,Enabled"
bitfld.long 0x18 22. " [6] ,SPISIMO[6] open drain enable" "Disabled,Enabled"
bitfld.long 0x18 21. " [5] ,SPISIMO[5] open drain enable" "Disabled,Enabled"
bitfld.long 0x18 20. " [4] ,SPISIMO[4] open drain enable" "Disabled,Enabled"
textline " "
bitfld.long 0x18 19. " [3] ,SPISIMO[3] open drain enable" "Disabled,Enabled"
bitfld.long 0x18 18. " [2] ,SPISIMO[2] open drain enable" "Disabled,Enabled"
bitfld.long 0x18 17. " [1] ,SPISIMO[1] open drain enable" "Disabled,Enabled"
bitfld.long 0x18 16. " [0] ,SPISIMO[0] open drain enable (mirror of bit 10)" "Disabled,Enabled"
textline " "
bitfld.long 0x18 11. " SOMIPDR[0] ,SPISOMI[0] open drain enable" "Disabled,Enabled"
bitfld.long 0x18 10. " SIMOPDR[0] ,SPISIMO[0] open drain enable" "Disabled,Enabled"
bitfld.long 0x18 9. " CLKPDR ,SPI clock open drain enable" "Disabled,Enabled"
bitfld.long 0x18 8. " ENAPDR ,SPIENA open drain enable" "Disabled,Enabled"
textline " "
textline " "
bitfld.long 0x18 7. " SCSPDR[7] ,SPISCS7 open drain enable" "Disabled,Enabled"
bitfld.long 0x18 6. " [6] ,SPISCS6 open drain enable" "Disabled,Enabled"
bitfld.long 0x18 5. " [5] ,SPISCS5 open drain enable" "Disabled,Enabled"
bitfld.long 0x18 4. " [4] ,SPISCS4 open drain enable" "Disabled,Enabled"
textline " "
bitfld.long 0x18 3. " [3] ,SPISCS3 open drain enable" "Disabled,Enabled"
bitfld.long 0x18 2. " [2] ,SPISCS2 open drain enable" "Disabled,Enabled"
bitfld.long 0x18 1. " [1] ,SPISCS1 open drain enable" "Disabled,Enabled"
bitfld.long 0x18 0. " [0] ,SPISCS0 open drain enable" "Disabled,Enabled"
textline " "
line.long 0x1C "SPIPC7,SPI Pin Control Register 7"
bitfld.long 0x1C 31. " SOMIPDIS[7] ,SPISOMI[7] pull control enable/disable" "No,Yes"
bitfld.long 0x1C 30. " [6] ,SPISOMI[6] pull control enable/disable" "No,Yes"
bitfld.long 0x1C 29. " [5] ,SPISOMI[5] pull control enable/disable" "No,Yes"
bitfld.long 0x1C 28. " [4] ,SPISOMI[4] pull control enable/disable" "No,Yes"
textline " "
bitfld.long 0x1C 27. " [3] ,SPISOMI[3] pull control enable/disable" "No,Yes"
bitfld.long 0x1C 26. " [2] ,SPISOMI[2] pull control enable/disable" "No,Yes"
bitfld.long 0x1C 25. " [1] ,SPISOMI[1] pull control enable/disable" "No,Yes"
bitfld.long 0x1C 24. " [0] ,SPISOMI[0] pull control enable/disable (mirror of bit 11)" "No,Yes"
textline " "
bitfld.long 0x1C 23. " SIMOPDIS[7] ,SPISIMO[7] pull control enable/disable" "No,Yes"
bitfld.long 0x1C 22. " [6] ,SPISIMO[6] pull control enable/disable" "No,Yes"
bitfld.long 0x1C 21. " [5] ,SPISIMO[5] pull control enable/disable" "No,Yes"
bitfld.long 0x1C 20. " [4] ,SPISIMO[4] pull control enable/disable" "No,Yes"
textline " "
bitfld.long 0x1C 19. " [3] ,SPISIMO[3] pull control enable/disable" "No,Yes"
bitfld.long 0x1C 18. " [2] ,SPISIMO[2] pull control enable/disable" "No,Yes"
bitfld.long 0x1C 17. " [1] ,SPISIMO[1] pull control enable/disable" "No,Yes"
bitfld.long 0x1C 16. " [0] ,SPISIMO[0] pull control enable/disable (mirror of bit 10)" "No,Yes"
textline " "
bitfld.long 0x1C 11. " SOMIPDIS[0] ,SPISOMI[0] pull control enable/disable" "No,Yes"
bitfld.long 0x1C 10. " SIMOPDIS[0] ,SPISIMO[0] pull control enable/disable" "No,Yes"
bitfld.long 0x1C 9. " CLKPDIS ,SPI clock pull control enable/disable" "No,Yes"
bitfld.long 0x1C 8. " ENAPDIS ,SPIENA pull control enable/disable" "No,Yes"
textline " "
textline " "
bitfld.long 0x1C 7. " SCSPDIS[7] ,SPISCS7 pull control enable/disable" "No,Yes"
bitfld.long 0x1C 6. " [6] ,SPISCS6 pull control enable/disable" "No,Yes"
bitfld.long 0x1C 5. " [5] ,SPISCS5 pull control enable/disable" "No,Yes"
bitfld.long 0x1C 4. " [4] ,SPISCS4 pull control enable/disable" "No,Yes"
textline " "
bitfld.long 0x1C 3. " [3] ,SPISCS3 pull control enable/disable" "No,Yes"
bitfld.long 0x1C 2. " [2] ,SPISCS2 pull control enable/disable" "No,Yes"
bitfld.long 0x1C 1. " [1] ,SPISCS1 pull control enable/disable" "No,Yes"
bitfld.long 0x1C 0. " [0] ,SPISCS0 pull control enable/disable" "No,Yes"
textline " "
line.long 0x20 "SPIPC8,SPI Pin Control Register 8"
bitfld.long 0x20 31. " SOMIPSEL[7] ,SPISOMI[7] pull select" "Pull down,Pull up"
bitfld.long 0x20 30. " [6] ,SPISOMI[6] pull select" "Pull down,Pull up"
bitfld.long 0x20 29. " [5] ,SPISOMI[5] pull select" "Pull down,Pull up"
bitfld.long 0x20 28. " [4] ,SPISOMI[4] pull select" "Pull down,Pull up"
textline " "
bitfld.long 0x20 27. " [3] ,SPISOMI[3] pull select" "Pull down,Pull up"
bitfld.long 0x20 26. " [2] ,SPISOMI[2] pull select" "Pull down,Pull up"
bitfld.long 0x20 25. " [1] ,SPISOMI[1] pull select" "Pull down,Pull up"
bitfld.long 0x20 24. " [0] ,SPISOMI[0] pull select (mirror of bit 11)" "Pull down,Pull up"
textline " "
bitfld.long 0x20 23. " SIMOPSEL[7] ,SPISIMO[7] pull select" "Pull down,Pull up"
bitfld.long 0x20 22. " [6] ,SPISIMO[6] pull select" "Pull down,Pull up"
bitfld.long 0x20 21. " [5] ,SPISIMO[5] pull select" "Pull down,Pull up"
bitfld.long 0x20 20. " [4] ,SPISIMO[4] pull select" "Pull down,Pull up"
textline " "
bitfld.long 0x20 19. " [3] ,SPISIMO[3] pull select" "Pull down,Pull up"
bitfld.long 0x20 18. " [2] ,SPISIMO[2] pull select" "Pull down,Pull up"
bitfld.long 0x20 17. " [1] ,SPISIMO[1] pull select" "Pull down,Pull up"
bitfld.long 0x20 16. " [0] ,SPISIMO[0] pull select (mirror of bit 10)" "Pull down,Pull up"
textline " "
bitfld.long 0x20 11. " SOMIPSEL[0] ,SPISOMI[0] pull select" "Pull down,Pull up"
bitfld.long 0x20 10. " SIMOPSEL[0] ,SPISIMO[0] pull select" "Pull down,Pull up"
bitfld.long 0x20 9. " CLKPSEL ,SPI clock pull select" "Pull down,Pull up"
bitfld.long 0x20 8. " ENAPSEL ,SPIENA pull select" "Pull down,Pull up"
textline " "
textline " "
bitfld.long 0x20 7. " SCSPSEL[7] ,SPISCS7 pull select" "Pull down,Pull up"
bitfld.long 0x20 6. " [6] ,SPISCS6 pull select" "Pull down,Pull up"
bitfld.long 0x20 5. " [5] ,SPISCS5 pull select" "Pull down,Pull up"
bitfld.long 0x20 4. " [4] ,SPISCS4 pull select" "Pull down,Pull up"
textline " "
bitfld.long 0x20 3. " [3] ,SPISCS3 pull select" "Pull down,Pull up"
bitfld.long 0x20 2. " [2] ,SPISCS2 pull select" "Pull down,Pull up"
bitfld.long 0x20 1. " [1] ,SPISCS1 pull select" "Pull down,Pull up"
bitfld.long 0x20 0. " [0] ,SPISCS0 pull select" "Pull down,Pull up"
textline " "
group.long 0x38++0x03
line.long 0x00 "SPIDAT0,SPI Transmit Data Register 0"
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,SPI transmit data"
if (((d.l(ad:0xFFF7F800+0x4))&0x3)==0x0)
group.long 0x3C++0x03
line.long 0x00 "SPIDAT1,Transmit Data Register 1"
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Inactive,Active"
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "No delay,After transaction"
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
textline " "
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
else
group.long 0x3C++0x03
line.long 0x00 "SPIDAT1,Transmit Data Register 1"
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Inactive,Active"
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
textline " "
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
endif
width 17.
hgroup.long 0x40++0x03
hide.long 0x00 "SPIBUF,SPI Receive Buffer Register"
in
rgroup.long 0x44++0x03
line.long 0x00 "SPIEMU,SPI Emulation Register"
hexmask.long.word 0x00 0.--15. 1. " EMU_RXDATA ,SPI receive data"
if (((d.l(ad:0xFFF7F800+0x4))&0x1)==0x1)
rgroup.long 0x48++0x03
line.long 0x00 "SPIDELAY,SPI Delay Register"
hexmask.long.byte 0x00 24.--31. 1. " C2TDELAY ,Chip-select-active to transmit-start delay"
hexmask.long.byte 0x00 16.--23. 1. " T2CDELAY ,Transmit-end-to-chip-select-inactive-delay"
hexmask.long.byte 0x00 8.--15. 1. " T2EDELAY ,Transmit-data-finished to ENA-pin-inactive time-out"
textline " "
hexmask.long.byte 0x00 0.--7. 1. " C2EDELAY ,Chip-select-active to ENA-signal-active time-out"
group.long 0x4C++0x03
line.long 0x00 "SPIDEF,SPI Default Chip Select Register"
bitfld.long 0x00 7. " CSDEF[7] ,Chip select default pattern 7" "0,1"
bitfld.long 0x00 6. " [6] ,Chip select default pattern 6" "0,1"
bitfld.long 0x00 5. " [5] ,Chip select default pattern 5" "0,1"
textline " "
bitfld.long 0x00 4. " [4] ,Chip select default pattern 4" "0,1"
bitfld.long 0x00 3. " [3] ,Chip select default pattern 3" "0,1"
bitfld.long 0x00 2. " [2] ,Chip select default pattern 2" "0,1"
textline " "
bitfld.long 0x00 1. " [1] ,Chip select default pattern 1" "0,1"
bitfld.long 0x00 0. " [0] ,Chip select default pattern 0" "0,1"
endif
if (((d.l(ad:0xFFF7F800+0x4))&0x3)==0x0)
group.long 0x50++0x0F
line.long 0x0 "SPIFMT0,SPI Data Format Register 0"
sif cpuis("TMS570LC4357")
hexmask.long.byte 0x0 24.--31. 1. " WDELAY ,Delay in between transmissions for data format 0"
else
bitfld.long 0x0 24.--29. " WDELAY ,Delay in between transmissions for data format 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
endif
bitfld.long 0x0 23. " PARPOL ,Parity polarity: even or odd" "Even,Odd"
textline " "
bitfld.long 0x0 22. " PARITYENA ,Parity enable for data format 0" "Disabled,Enabled"
bitfld.long 0x0 20. " SHIFTDIR ,Shift direction for data format $" "MSB,LSB"
textline " "
sif cpuis("TMS570LC4357")
bitfld.long 0x0 19. " HDUPLEX_ENA0 ,Half Duplex transfer mode enable for Data Format 0" "Normal,TX"
endif
textline " "
bitfld.long 0x0 18. " DISCSTIMERS ,Disable chip-select timers for this format" "No,Yes"
textline " "
bitfld.long 0x0 17. " POLARITY ,SPI data format 0 clock polarity" "Low,High"
bitfld.long 0x0 16. " PHASE ,SPI data format 0 clock delay" "Disabled,Enabled"
textline " "
hexmask.long.byte 0x0 8.--15. 1. " PRESCALE ,SPI data format 0 prescaler"
bitfld.long 0x0 0.--4. " CHARLEN ,SPI data format 0 data-word length" ",,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,?..."
line.long 0x4 "SPIFMT1,SPI Data Format Register 1"
sif cpuis("TMS570LC4357")
hexmask.long.byte 0x4 24.--31. 1. " WDELAY ,Delay in between transmissions for data format 1"
else
bitfld.long 0x4 24.--29. " WDELAY ,Delay in between transmissions for data format 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
endif
bitfld.long 0x4 23. " PARPOL ,Parity polarity: even or odd" "Even,Odd"
textline " "
bitfld.long 0x4 22. " PARITYENA ,Parity enable for data format 1" "Disabled,Enabled"
bitfld.long 0x4 20. " SHIFTDIR ,Shift direction for data format $" "MSB,LSB"
textline " "
sif cpuis("TMS570LC4357")
bitfld.long 0x4 19. " HDUPLEX_ENA1 ,Half Duplex transfer mode enable for Data Format 1" "Normal,TX"
endif
textline " "
bitfld.long 0x4 18. " DISCSTIMERS ,Disable chip-select timers for this format" "No,Yes"
textline " "
bitfld.long 0x4 17. " POLARITY ,SPI data format 1 clock polarity" "Low,High"
bitfld.long 0x4 16. " PHASE ,SPI data format 1 clock delay" "Disabled,Enabled"
textline " "
hexmask.long.byte 0x4 8.--15. 1. " PRESCALE ,SPI data format 1 prescaler"
bitfld.long 0x4 0.--4. " CHARLEN ,SPI data format 1 data-word length" ",,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,?..."
line.long 0x8 "SPIFMT2,SPI Data Format Register 2"
sif cpuis("TMS570LC4357")
hexmask.long.byte 0x8 24.--31. 1. " WDELAY ,Delay in between transmissions for data format 2"
else
bitfld.long 0x8 24.--29. " WDELAY ,Delay in between transmissions for data format 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
endif
bitfld.long 0x8 23. " PARPOL ,Parity polarity: even or odd" "Even,Odd"
textline " "
bitfld.long 0x8 22. " PARITYENA ,Parity enable for data format 2" "Disabled,Enabled"
bitfld.long 0x8 20. " SHIFTDIR ,Shift direction for data format $" "MSB,LSB"
textline " "
sif cpuis("TMS570LC4357")
bitfld.long 0x8 19. " HDUPLEX_ENA2 ,Half Duplex transfer mode enable for Data Format 2" "Normal,TX"
endif
textline " "
bitfld.long 0x8 18. " DISCSTIMERS ,Disable chip-select timers for this format" "No,Yes"
textline " "
bitfld.long 0x8 17. " POLARITY ,SPI data format 2 clock polarity" "Low,High"
bitfld.long 0x8 16. " PHASE ,SPI data format 2 clock delay" "Disabled,Enabled"
textline " "
hexmask.long.byte 0x8 8.--15. 1. " PRESCALE ,SPI data format 2 prescaler"
bitfld.long 0x8 0.--4. " CHARLEN ,SPI data format 2 data-word length" ",,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,?..."
line.long 0xC "SPIFMT3,SPI Data Format Register 3"
sif cpuis("TMS570LC4357")
hexmask.long.byte 0xC 24.--31. 1. " WDELAY ,Delay in between transmissions for data format 3"
else
bitfld.long 0xC 24.--29. " WDELAY ,Delay in between transmissions for data format 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
endif
bitfld.long 0xC 23. " PARPOL ,Parity polarity: even or odd" "Even,Odd"
textline " "
bitfld.long 0xC 22. " PARITYENA ,Parity enable for data format 3" "Disabled,Enabled"
bitfld.long 0xC 20. " SHIFTDIR ,Shift direction for data format $" "MSB,LSB"
textline " "
sif cpuis("TMS570LC4357")
bitfld.long 0xC 19. " HDUPLEX_ENA3 ,Half Duplex transfer mode enable for Data Format 3" "Normal,TX"
endif
textline " "
bitfld.long 0xC 18. " DISCSTIMERS ,Disable chip-select timers for this format" "No,Yes"
textline " "
bitfld.long 0xC 17. " POLARITY ,SPI data format 3 clock polarity" "Low,High"
bitfld.long 0xC 16. " PHASE ,SPI data format 3 clock delay" "Disabled,Enabled"
textline " "
hexmask.long.byte 0xC 8.--15. 1. " PRESCALE ,SPI data format 3 prescaler"
bitfld.long 0xC 0.--4. " CHARLEN ,SPI data format 3 data-word length" ",,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,?..."
else
group.long 0x50++0x0F
line.long 0x0 "SPIFMT0,SPI Data Format Register 0"
sif cpuis("TMS570LC4357")
hexmask.long.byte 0x0 24.--31. 1. " WDELAY ,Delay in between transmissions for data format 0"
else
bitfld.long 0x0 24.--29. " WDELAY ,Delay in between transmissions for data format 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
endif
bitfld.long 0x0 23. " PARPOL ,Parity polarity: even or odd" "Even,Odd"
textline " "
bitfld.long 0x0 22. " PARITYENA ,Parity enable for data format 0" "Disabled,Enabled"
bitfld.long 0x0 21. " WAITENA ,The master waits for the ENA signal from slave for data format 0" "Disabled,Enabled"
textline " "
bitfld.long 0x0 20. " SHIFTDIR ,Shift direction for data format $" "MSB,LSB"
sif cpuis("TMS570LC4357")
bitfld.long 0x0 19. " HDUPLEX_ENA0 ,Half Duplex transfer mode enable for Data Format 0" "Normal,RX"
endif
textline " "
bitfld.long 0x0 18. " DISCSTIMERS ,Disable chip-select timers for this format" "No,Yes"
textline " "
bitfld.long 0x0 17. " POLARITY ,SPI data format 0 clock polarity" "Low,High"
bitfld.long 0x0 16. " PHASE ,SPI data format 0 clock delay" "Disabled,Enabled"
textline " "
hexmask.long.byte 0x0 8.--15. 1. " PRESCALE ,SPI data format 0 prescaler"
bitfld.long 0x0 0.--4. " CHARLEN ,SPI data format 0 data-word length" ",,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,?..."
line.long 0x4 "SPIFMT1,SPI Data Format Register 1"
sif cpuis("TMS570LC4357")
hexmask.long.byte 0x4 24.--31. 1. " WDELAY ,Delay in between transmissions for data format 1"
else
bitfld.long 0x4 24.--29. " WDELAY ,Delay in between transmissions for data format 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
endif
bitfld.long 0x4 23. " PARPOL ,Parity polarity: even or odd" "Even,Odd"
textline " "
bitfld.long 0x4 22. " PARITYENA ,Parity enable for data format 1" "Disabled,Enabled"
bitfld.long 0x4 21. " WAITENA ,The master waits for the ENA signal from slave for data format 1" "Disabled,Enabled"
textline " "
bitfld.long 0x4 20. " SHIFTDIR ,Shift direction for data format $" "MSB,LSB"
sif cpuis("TMS570LC4357")
bitfld.long 0x4 19. " HDUPLEX_ENA1 ,Half Duplex transfer mode enable for Data Format 1" "Normal,RX"
endif
textline " "
bitfld.long 0x4 18. " DISCSTIMERS ,Disable chip-select timers for this format" "No,Yes"
textline " "
bitfld.long 0x4 17. " POLARITY ,SPI data format 1 clock polarity" "Low,High"
bitfld.long 0x4 16. " PHASE ,SPI data format 1 clock delay" "Disabled,Enabled"
textline " "
hexmask.long.byte 0x4 8.--15. 1. " PRESCALE ,SPI data format 1 prescaler"
bitfld.long 0x4 0.--4. " CHARLEN ,SPI data format 1 data-word length" ",,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,?..."
line.long 0x8 "SPIFMT2,SPI Data Format Register 2"
sif cpuis("TMS570LC4357")
hexmask.long.byte 0x8 24.--31. 1. " WDELAY ,Delay in between transmissions for data format 2"
else
bitfld.long 0x8 24.--29. " WDELAY ,Delay in between transmissions for data format 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
endif
bitfld.long 0x8 23. " PARPOL ,Parity polarity: even or odd" "Even,Odd"
textline " "
bitfld.long 0x8 22. " PARITYENA ,Parity enable for data format 2" "Disabled,Enabled"
bitfld.long 0x8 21. " WAITENA ,The master waits for the ENA signal from slave for data format 2" "Disabled,Enabled"
textline " "
bitfld.long 0x8 20. " SHIFTDIR ,Shift direction for data format $" "MSB,LSB"
sif cpuis("TMS570LC4357")
bitfld.long 0x8 19. " HDUPLEX_ENA2 ,Half Duplex transfer mode enable for Data Format 2" "Normal,RX"
endif
textline " "
bitfld.long 0x8 18. " DISCSTIMERS ,Disable chip-select timers for this format" "No,Yes"
textline " "
bitfld.long 0x8 17. " POLARITY ,SPI data format 2 clock polarity" "Low,High"
bitfld.long 0x8 16. " PHASE ,SPI data format 2 clock delay" "Disabled,Enabled"
textline " "
hexmask.long.byte 0x8 8.--15. 1. " PRESCALE ,SPI data format 2 prescaler"
bitfld.long 0x8 0.--4. " CHARLEN ,SPI data format 2 data-word length" ",,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,?..."
line.long 0xC "SPIFMT3,SPI Data Format Register 3"
sif cpuis("TMS570LC4357")
hexmask.long.byte 0xC 24.--31. 1. " WDELAY ,Delay in between transmissions for data format 3"
else
bitfld.long 0xC 24.--29. " WDELAY ,Delay in between transmissions for data format 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
endif
bitfld.long 0xC 23. " PARPOL ,Parity polarity: even or odd" "Even,Odd"
textline " "
bitfld.long 0xC 22. " PARITYENA ,Parity enable for data format 3" "Disabled,Enabled"
bitfld.long 0xC 21. " WAITENA ,The master waits for the ENA signal from slave for data format 3" "Disabled,Enabled"
textline " "
bitfld.long 0xC 20. " SHIFTDIR ,Shift direction for data format $" "MSB,LSB"
sif cpuis("TMS570LC4357")
bitfld.long 0xC 19. " HDUPLEX_ENA3 ,Half Duplex transfer mode enable for Data Format 3" "Normal,RX"
endif
textline " "
bitfld.long 0xC 18. " DISCSTIMERS ,Disable chip-select timers for this format" "No,Yes"
textline " "
bitfld.long 0xC 17. " POLARITY ,SPI data format 3 clock polarity" "Low,High"
bitfld.long 0xC 16. " PHASE ,SPI data format 3 clock delay" "Disabled,Enabled"
textline " "
hexmask.long.byte 0xC 8.--15. 1. " PRESCALE ,SPI data format 3 prescaler"
bitfld.long 0xC 0.--4. " CHARLEN ,SPI data format 3 data-word length" ",,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,?..."
endif
hgroup.long 0x60++0x03
hide.long 0x00 "TGINTVECT0,SPI Interrupt Vector Register 0 / MibSPI Transfer Group Interrupt Vector Register 0"
in
hgroup.long 0x64++0x03
hide.long 0x00 "TGINTVECT1,SPI Interrupt Vector Register 1 / MibSPI Transfer Group Interrupt Vector Register 1"
in
group.long 0x6C++0x07
line.long 0x00 "SPIPMCTRL,SPI Parallel/Modulo Mode Control Register"
bitfld.long 0x00 29. " MODCLKPOL3 ,Modulo mode SPICLK polarity" "Normal,Inverted"
bitfld.long 0x00 26.--28. " MMODE3 ,SPI/MibSPI data lines" "1,2,3,4,5,6,?..."
bitfld.long 0x00 24.--25. " PMODE3 ,Parallel mode data lines" "1,2,4,8"
textline " "
bitfld.long 0x00 21. " MODCLKPOL2 ,Modulo mode SPICLK polarity" "Normal,Inverted"
bitfld.long 0x00 18.--20. " MMODE2 ,SPI/MibSPI data lines" "1,2,3,4,5,6,?..."
bitfld.long 0x00 16.--17. " PMODE2 ,Parallel mode data lines" "1,2,4,8"
textline " "
bitfld.long 0x00 13. " MODCLKPOL1 ,Modulo mode SPICLK polarity" "Normal,Inverted"
bitfld.long 0x00 10.--12. " MMODE1 ,SPI/MibSPI data lines" "1,2,3,4,5,6,?..."
bitfld.long 0x00 8.--9. " PMODE1 ,Parallel mode data lines" "1,2,4,8"
textline " "
bitfld.long 0x00 5. " MODCLKPOL0 ,Modulo mode SPICLK polarity" "Normal,Inverted"
bitfld.long 0x00 2.--4. " MMODE0 ,SPI/MibSPI data lines" "1,2,3,4,5,6,?..."
bitfld.long 0x00 0.--1. " PMODE0 ,Parallel mode data lines" "1,2,4,8"
line.long 0x04 "MIBSPIE,MibSPI Enable Register"
bitfld.long 0x04 16. " RXRAMACCESS ,Receive-RAM access control" "Not writable,Accessible"
bitfld.long 0x04 0. " MIBSPIENA ,Multi-buffer mode enable" "Disabled,Enabled"
textline " "
width 17.
group.long 0x74++0x0F
line.long 0x00 "TGITENST,MibSPI Transfer Group Interrupt Enable Set Register"
bitfld.long 0x00 31. " SETINTENRDY[15] ,TG interrupt set (enable) when transfer finished" "Disabled,Enabled"
bitfld.long 0x00 30. " [14] ,TG interrupt set (enable) when transfer finished" "Disabled,Enabled"
bitfld.long 0x00 29. " [13] ,TG interrupt set (enable) when transfer finished" "Disabled,Enabled"
textline " "
bitfld.long 0x00 28. " [12] ,TG interrupt set (enable) when transfer finished" "Disabled,Enabled"
bitfld.long 0x00 27. " [11] ,TG interrupt set (enable) when transfer finished" "Disabled,Enabled"
bitfld.long 0x00 26. " [10] ,TG interrupt set (enable) when transfer finished" "Disabled,Enabled"
textline " "
bitfld.long 0x00 25. " [9] ,TG interrupt set (enable) when transfer finished" "Disabled,Enabled"
bitfld.long 0x00 24. " [8] ,TG interrupt set (enable) when transfer finished" "Disabled,Enabled"
bitfld.long 0x00 23. " [7] ,TG interrupt set (enable) when transfer finished" "Disabled,Enabled"
textline " "
bitfld.long 0x00 22. " [6] ,TG interrupt set (enable) when transfer finished" "Disabled,Enabled"
bitfld.long 0x00 21. " [5] ,TG interrupt set (enable) when transfer finished" "Disabled,Enabled"
bitfld.long 0x00 20. " [4] ,TG interrupt set (enable) when transfer finished" "Disabled,Enabled"
textline " "
bitfld.long 0x00 19. " [3] ,TG interrupt set (enable) when transfer finished" "Disabled,Enabled"
bitfld.long 0x00 18. " [2] ,TG interrupt set (enable) when transfer finished" "Disabled,Enabled"
bitfld.long 0x00 17. " [1] ,TG interrupt set (enable) when transfer finished" "Disabled,Enabled"
textline " "
bitfld.long 0x00 16. " [0] ,TG interrupt set (enable) when transfer finished" "Disabled,Enabled"
textline " "
bitfld.long 0x00 15. " SETINTENSUS[15] ,TG interrupt set (enabled) when transfer suspended" "Disabled,Enabled"
bitfld.long 0x00 14. " [14] ,TG interrupt set (enabled) when transfer suspended" "Disabled,Enabled"
bitfld.long 0x00 13. " [13] ,TG interrupt set (enabled) when transfer suspended" "Disabled,Enabled"
textline " "
bitfld.long 0x00 12. " [12] ,TG interrupt set (enabled) when transfer suspended" "Disabled,Enabled"
bitfld.long 0x00 11. " [11] ,TG interrupt set (enabled) when transfer suspended" "Disabled,Enabled"
bitfld.long 0x00 10. " [10] ,TG interrupt set (enabled) when transfer suspended" "Disabled,Enabled"
textline " "
bitfld.long 0x00 9. " [9] ,TG interrupt set (enabled) when transfer suspended" "Disabled,Enabled"
bitfld.long 0x00 8. " [8] ,TG interrupt set (enabled) when transfer suspended" "Disabled,Enabled"
bitfld.long 0x00 7. " [7] ,TG interrupt set (enabled) when transfer suspended" "Disabled,Enabled"
textline " "
bitfld.long 0x00 6. " [6] ,TG interrupt set (enabled) when transfer suspended" "Disabled,Enabled"
bitfld.long 0x00 5. " [5] ,TG interrupt set (enabled) when transfer suspended" "Disabled,Enabled"
bitfld.long 0x00 4. " [4] ,TG interrupt set (enabled) when transfer suspended" "Disabled,Enabled"
textline " "
bitfld.long 0x00 3. " [3] ,TG interrupt set (enabled) when transfer suspended" "Disabled,Enabled"
bitfld.long 0x00 2. " [2] ,TG interrupt set (enabled) when transfer suspended" "Disabled,Enabled"
bitfld.long 0x00 1. " [1] ,TG interrupt set (enabled) when transfer suspended" "Disabled,Enabled"
textline " "
bitfld.long 0x00 0. " [0] ,TG interrupt set (enabled) when transfer suspended" "Disabled,Enabled"
line.long 0x04 "TGITENCR,MibSPI Transfer Group Interrupt Enable Clear Register"
bitfld.long 0x04 31. " CLRINTENRDY[15] ,TG interrupt clear (disabled) when transfer finished" "Disabled,Enabled"
bitfld.long 0x04 30. " [14] ,TG interrupt clear (disabled) when transfer finished" "Disabled,Enabled"
bitfld.long 0x04 29. " [13] ,TG interrupt clear (disabled) when transfer finished" "Disabled,Enabled"
textline " "
bitfld.long 0x04 28. " [12] ,TG interrupt clear (disabled) when transfer finished" "Disabled,Enabled"
bitfld.long 0x04 27. " [11] ,TG interrupt clear (disabled) when transfer finished" "Disabled,Enabled"
bitfld.long 0x04 26. " [10] ,TG interrupt clear (disabled) when transfer finished" "Disabled,Enabled"
textline " "
bitfld.long 0x04 25. " [9] ,TG interrupt clear (disabled) when transfer finished" "Disabled,Enabled"
bitfld.long 0x04 24. " [8] ,TG interrupt clear (disabled) when transfer finished" "Disabled,Enabled"
bitfld.long 0x04 23. " [7] ,TG interrupt clear (disabled) when transfer finished" "Disabled,Enabled"
textline " "
bitfld.long 0x04 22. " [6] ,TG interrupt clear (disabled) when transfer finished" "Disabled,Enabled"
bitfld.long 0x04 21. " [5] ,TG interrupt clear (disabled) when transfer finished" "Disabled,Enabled"
bitfld.long 0x04 20. " [4] ,TG interrupt clear (disabled) when transfer finished" "Disabled,Enabled"
textline " "
bitfld.long 0x04 19. " [3] ,TG interrupt clear (disabled) when transfer finished" "Disabled,Enabled"
bitfld.long 0x04 18. " [2] ,TG interrupt clear (disabled) when transfer finished" "Disabled,Enabled"
bitfld.long 0x04 17. " [1] ,TG interrupt clear (disabled) when transfer finished" "Disabled,Enabled"
textline " "
bitfld.long 0x04 16. " [0] ,TG interrupt clear (disabled) when transfer finished" "Disabled,Enabled"
textline " "
bitfld.long 0x04 15. " CLRINTENSUS[15] ,TG interrupt clear (disabled) when transfer suspended" "Disabled,Enabled"
bitfld.long 0x04 14. " [14] ,TG interrupt clear (disabled) when transfer suspended" "Disabled,Enabled"
bitfld.long 0x04 13. " [13] ,TG interrupt clear (disabled) when transfer suspended" "Disabled,Enabled"
textline " "
bitfld.long 0x04 12. " [12] ,TG interrupt clear (disabled) when transfer suspended" "Disabled,Enabled"
bitfld.long 0x04 11. " [11] ,TG interrupt clear (disabled) when transfer suspended" "Disabled,Enabled"
bitfld.long 0x04 10. " [10] ,TG interrupt clear (disabled) when transfer suspended" "Disabled,Enabled"
textline " "
bitfld.long 0x04 9. " [9] ,TG interrupt clear (disabled) when transfer suspended" "Disabled,Enabled"
bitfld.long 0x04 8. " [8] ,TG interrupt clear (disabled) when transfer suspended" "Disabled,Enabled"
bitfld.long 0x04 7. " [7] ,TG interrupt clear (disabled) when transfer suspended" "Disabled,Enabled"
textline " "
bitfld.long 0x04 6. " [6] ,TG interrupt clear (disabled) when transfer suspended" "Disabled,Enabled"
bitfld.long 0x04 5. " [5] ,TG interrupt clear (disabled) when transfer suspended" "Disabled,Enabled"
bitfld.long 0x04 4. " [4] ,TG interrupt clear (disabled) when transfer suspended" "Disabled,Enabled"
textline " "
bitfld.long 0x04 3. " [3] ,TG interrupt clear (disabled) when transfer suspended" "Disabled,Enabled"
bitfld.long 0x04 2. " [2] ,TG interrupt clear (disabled) when transfer suspended" "Disabled,Enabled"
bitfld.long 0x04 1. " [1] ,TG interrupt clear (disabled) when transfer suspended" "Disabled,Enabled"
textline " "
bitfld.long 0x04 0. " [0] ,TG interrupt clear (disabled) when transfer suspended" "Disabled,Enabled"
textline " "
line.long 0x08 "TGITLVST,MibSPI Transfer Group Interrupt Level Set Register"
bitfld.long 0x08 31. " SETINTLVLRDY[15] ,Transfer-group completed interrupt level set" "INT0,INT1"
bitfld.long 0x08 30. " [14] ,Transfer-group completed interrupt level set" "INT0,INT1"
bitfld.long 0x08 29. " [13] ,Transfer-group completed interrupt level set" "INT0,INT1"
bitfld.long 0x08 28. " [12] ,Transfer-group completed interrupt level set" "INT0,INT1"
bitfld.long 0x08 27. " [11] ,Transfer-group completed interrupt level set" "INT0,INT1"
bitfld.long 0x08 26. " [10] ,Transfer-group completed interrupt level set" "INT0,INT1"
textline " "
bitfld.long 0x08 25. " [9] ,Transfer-group completed interrupt level set" "INT0,INT1"
bitfld.long 0x08 24. " [8] ,Transfer-group completed interrupt level set" "INT0,INT1"
bitfld.long 0x08 23. " [7] ,Transfer-group completed interrupt level set" "INT0,INT1"
bitfld.long 0x08 22. " [6] ,Transfer-group completed interrupt level set" "INT0,INT1"
bitfld.long 0x08 21. " [5] ,Transfer-group completed interrupt level set" "INT0,INT1"
bitfld.long 0x08 20. " [4] ,Transfer-group completed interrupt level set" "INT0,INT1"
textline " "
bitfld.long 0x08 19. " [3] ,Transfer-group completed interrupt level set" "INT0,INT1"
bitfld.long 0x08 18. " [2] ,Transfer-group completed interrupt level set" "INT0,INT1"
bitfld.long 0x08 17. " [1] ,Transfer-group completed interrupt level set" "INT0,INT1"
bitfld.long 0x08 16. " [0] ,Transfer-group completed interrupt level set" "INT0,INT1"
textline " "
bitfld.long 0x08 15. " SETINTLVLSUS[15] ,Transfer-group suspended interrupt level set" "INT0,INT1"
bitfld.long 0x08 14. " [14] ,Transfer-group suspended interrupt level set" "INT0,INT1"
bitfld.long 0x08 13. " [13] ,Transfer-group suspended interrupt level set" "INT0,INT1"
bitfld.long 0x08 12. " [12] ,Transfer-group suspended interrupt level set" "INT0,INT1"
bitfld.long 0x08 11. " [11] ,Transfer-group suspended interrupt level set" "INT0,INT1"
bitfld.long 0x08 10. " [10] ,Transfer-group suspended interrupt level set" "INT0,INT1"
textline " "
bitfld.long 0x08 9. " [9] ,Transfer-group suspended interrupt level set" "INT0,INT1"
bitfld.long 0x08 8. " [8] ,Transfer-group suspended interrupt level set" "INT0,INT1"
bitfld.long 0x08 7. " [7] ,Transfer-group suspended interrupt level set" "INT0,INT1"
bitfld.long 0x08 6. " [6] ,Transfer-group suspended interrupt level set" "INT0,INT1"
bitfld.long 0x08 5. " [5] ,Transfer-group suspended interrupt level set" "INT0,INT1"
bitfld.long 0x08 4. " [4] ,Transfer-group suspended interrupt level set" "INT0,INT1"
textline " "
bitfld.long 0x08 3. " [3] ,Transfer-group suspended interrupt level set" "INT0,INT1"
bitfld.long 0x08 2. " [2] ,Transfer-group suspended interrupt level set" "INT0,INT1"
bitfld.long 0x08 1. " [1] ,Transfer-group suspended interrupt level set" "INT0,INT1"
bitfld.long 0x08 0. " [0] ,Transfer-group suspended interrupt level set" "INT0,INT1"
line.long 0x0C "TGITLVCR,MibSPI Transfer Group Interrupt Level Clear Register"
bitfld.long 0x0C 31. " CLRINTLVLRDY[15] ,Transfer-group completed interrupt level clear" "INT0,INT1"
bitfld.long 0x0C 30. " [14] ,Transfer-group completed interrupt level clear" "INT0,INT1"
bitfld.long 0x0C 29. " [13] ,Transfer-group completed interrupt level clear" "INT0,INT1"
bitfld.long 0x0C 28. " [12] ,Transfer-group completed interrupt level clear" "INT0,INT1"
bitfld.long 0x0C 27. " [11] ,Transfer-group completed interrupt level clear" "INT0,INT1"
bitfld.long 0x0C 26. " [10] ,Transfer-group completed interrupt level clear" "INT0,INT1"
textline " "
bitfld.long 0x0C 25. " [9] ,Transfer-group completed interrupt level clear" "INT0,INT1"
bitfld.long 0x0C 24. " [8] ,Transfer-group completed interrupt level clear" "INT0,INT1"
bitfld.long 0x0C 23. " [7] ,Transfer-group completed interrupt level clear" "INT0,INT1"
bitfld.long 0x0C 22. " [6] ,Transfer-group completed interrupt level clear" "INT0,INT1"
bitfld.long 0x0C 21. " [5] ,Transfer-group completed interrupt level clear" "INT0,INT1"
bitfld.long 0x0C 20. " [4] ,Transfer-group completed interrupt level clear" "INT0,INT1"
textline " "
bitfld.long 0x0C 19. " [3] ,Transfer-group completed interrupt level clear" "INT0,INT1"
bitfld.long 0x0C 18. " [2] ,Transfer-group completed interrupt level clear" "INT0,INT1"
bitfld.long 0x0C 17. " [1] ,Transfer-group completed interrupt level clear" "INT0,INT1"
bitfld.long 0x0C 16. " [0] ,Transfer-group completed interrupt level clear" "INT0,INT1"
textline " "
bitfld.long 0x0C 15. " CLRINTLVLSUS[15] ,Transfer group suspended interrupt level clear" "INT0,INT1"
bitfld.long 0x0C 14. " [14] ,Transfer group suspended interrupt level clear" "INT0,INT1"
bitfld.long 0x0C 13. " [13] ,Transfer group suspended interrupt level clear" "INT0,INT1"
bitfld.long 0x0C 12. " [12] ,Transfer group suspended interrupt level clear" "INT0,INT1"
bitfld.long 0x0C 11. " [11] ,Transfer group suspended interrupt level clear" "INT0,INT1"
bitfld.long 0x0C 10. " [10] ,Transfer group suspended interrupt level clear" "INT0,INT1"
textline " "
bitfld.long 0x0C 9. " [9] ,Transfer group suspended interrupt level clear" "INT0,INT1"
bitfld.long 0x0C 8. " [8] ,Transfer group suspended interrupt level clear" "INT0,INT1"
bitfld.long 0x0C 7. " [7] ,Transfer group suspended interrupt level clear" "INT0,INT1"
bitfld.long 0x0C 6. " [6] ,Transfer group suspended interrupt level clear" "INT0,INT1"
bitfld.long 0x0C 5. " [5] ,Transfer group suspended interrupt level clear" "INT0,INT1"
bitfld.long 0x0C 4. " [4] ,Transfer group suspended interrupt level clear" "INT0,INT1"
textline " "
bitfld.long 0x0C 3. " [3] ,Transfer group suspended interrupt level clear" "INT0,INT1"
bitfld.long 0x0C 2. " [2] ,Transfer group suspended interrupt level clear" "INT0,INT1"
bitfld.long 0x0C 1. " [1] ,Transfer group suspended interrupt level clear" "INT0,INT1"
bitfld.long 0x0C 0. " [0] ,Transfer group suspended interrupt level clear" "INT0,INT1"
textline " "
group.long 0x84++0x03
line.long 0x00 "TGITFLG,Transfer Group Interrupt Flag Register"
sif cpuis("TMS570LC4357")
bitfld.long 0x00 31. " INTFLGRDY[15] ,Transfer-group interrupt flag for a transfer-completed interrupt 15" "Disabled,Enabled"
bitfld.long 0x00 30. " [14] ,Transfer-group interrupt flag for a transfer-completed interrupt 14" "Disabled,Enabled"
bitfld.long 0x00 29. " [13] ,Transfer-group interrupt flag for a transfer-completed interrupt 13" "Disabled,Enabled"
bitfld.long 0x00 28. " [12] ,Transfer-group interrupt flag for a transfer-completed interrupt 12" "Disabled,Enabled"
textline " "
bitfld.long 0x00 27. " [11] ,Transfer-group interrupt flag for a transfer-completed interrupt 11" "Disabled,Enabled"
bitfld.long 0x00 26. " [10] ,Transfer-group interrupt flag for a transfer-completed interrupt 10" "Disabled,Enabled"
bitfld.long 0x00 25. " [9] ,Transfer-group interrupt flag for a transfer-completed interrupt 9" "Disabled,Enabled"
bitfld.long 0x00 24. " [8] ,Transfer-group interrupt flag for a transfer-completed interrupt 8" "Disabled,Enabled"
textline " "
bitfld.long 0x00 23. " [7] ,Transfer-group interrupt flag for a transfer-completed interrupt 7" "Disabled,Enabled"
bitfld.long 0x00 22. " [6] ,Transfer-group interrupt flag for a transfer-completed interrupt 6" "Disabled,Enabled"
bitfld.long 0x00 21. " [5] ,Transfer-group interrupt flag for a transfer-completed interrupt 5" "Disabled,Enabled"
bitfld.long 0x00 20. " [4] ,Transfer-group interrupt flag for a transfer-completed interrupt 4" "Disabled,Enabled"
textline " "
bitfld.long 0x00 19. " [3] ,Transfer-group interrupt flag for a transfer-completed interrupt 3" "Disabled,Enabled"
bitfld.long 0x00 18. " [2] ,Transfer-group interrupt flag for a transfer-completed interrupt 2" "Disabled,Enabled"
bitfld.long 0x00 17. " [1] ,Transfer-group interrupt flag for a transfer-completed interrupt 1" "Disabled,Enabled"
bitfld.long 0x00 16. " [0] ,Transfer-group interrupt flag for a transfer-completed interrupt 0" "Disabled,Enabled"
textline " "
endif
bitfld.long 0x00 15. " INTFLGSUS[15] ,Transfer-group interrupt flag for a transfer-suspend interrupt 15" "Disabled,Enabled"
bitfld.long 0x00 14. " [14] ,Transfer-group interrupt flag for a transfer-suspend interrupt 14" "Disabled,Enabled"
bitfld.long 0x00 13. " [13] ,Transfer-group interrupt flag for a transfer-suspend interrupt 13" "Disabled,Enabled"
bitfld.long 0x00 12. " [12] ,Transfer-group interrupt flag for a transfer-suspend interrupt 12" "Disabled,Enabled"
textline " "
bitfld.long 0x00 11. " [11] ,Transfer-group interrupt flag for a transfer-suspend interrupt 11" "Disabled,Enabled"
bitfld.long 0x00 10. " [10] ,Transfer-group interrupt flag for a transfer-suspend interrupt 10" "Disabled,Enabled"
bitfld.long 0x00 9. " [9] ,Transfer-group interrupt flag for a transfer-suspend interrupt 9" "Disabled,Enabled"
bitfld.long 0x00 8. " [8] ,Transfer-group interrupt flag for a transfer-suspend interrupt 8" "Disabled,Enabled"
textline " "
bitfld.long 0x00 7. " [7] ,Transfer-group interrupt flag for a transfer-suspend interrupt 7" "Disabled,Enabled"
bitfld.long 0x00 6. " [6] ,Transfer-group interrupt flag for a transfer-suspend interrupt 6" "Disabled,Enabled"
bitfld.long 0x00 5. " [5] ,Transfer-group interrupt flag for a transfer-suspend interrupt 5" "Disabled,Enabled"
bitfld.long 0x00 4. " [4] ,Transfer-group interrupt flag for a transfer-suspend interrupt 4" "Disabled,Enabled"
textline " "
bitfld.long 0x00 3. " [3] ,Transfer-group interrupt flag for a transfer-suspend interrupt 3" "Disabled,Enabled"
bitfld.long 0x00 2. " [2] ,Transfer-group interrupt flag for a transfer-suspend interrupt 2" "Disabled,Enabled"
bitfld.long 0x00 1. " [1] ,Transfer-group interrupt flag for a transfer-suspend interrupt 1" "Disabled,Enabled"
bitfld.long 0x00 0. " [0] ,Transfer-group interrupt flag for a transfer-suspend interrupt 0" "Disabled,Enabled"
textline " "
group.long 0x90++0x47
line.long 0x00 "TICKCNT,Tick Count Register"
bitfld.long 0x00 31. " TICKENA ,Tick counter enable" "Disabled,Enabled"
bitfld.long 0x00 30. " RELOAD ,Pre-load the tick counter" "No effect,Reload"
bitfld.long 0x00 28.--29. " CLKCTRL ,Tick counter clock source control" "0,1,2,3"
textline " "
hexmask.long.word 0x00 0.--15. 1. " TICKVALUE ,Initial value for the tick counter"
line.long 0x04 "LTGPEND,Last Transfer Group End Pointer Register"
rbitfld.long 0x04 24.--28. " TGINSERVICE ,The TG number currently being serviced by the sequencer" "No TG,TG0,TG1,TG2,TG3,TG4,TG5,TG6,TG7,TG8,TG9,TG10,TG11,TG12,TG13,TG14,TG15,?..."
hexmask.long.byte 0x04 8.--14. 1. " LPEND ,Last TG end pointer"
line.long 0x8 "TG1CTRL,MibSPI Transfer Group Control Register 1"
bitfld.long 0x8 31. " TGENA ,TG enable" "Disabled,Enabled"
bitfld.long 0x8 30. " ONESHOT ,Single transfer for TG" "Disabled,Enabled"
bitfld.long 0x8 29. " PRST ,TG pointer reset mode" "Disabled,Enabled"
textline " "
rbitfld.long 0x8 28. " TGTD ,TG triggered" "Not triggered,Triggered"
bitfld.long 0x8 20.--23. " TRGEVT ,Type of trigger event" "Never,Rising edge,Falling edge,Both edges,,High active,Low-active,Always,?..."
bitfld.long 0x8 16.--19. " TRIGSRC ,Trigger source" "Disabled,EXT[0],EXT[1],EXT[2],EXT[3],EXT[4],EXT[5],EXT[6],EXT[7],EXT[8],EXT[9,EXT[10,EXT[11,EXT[12,EXT[13],TICK"
textline " "
hexmask.long.byte 0x8 8.--14. 1. " PSTART ,TG start address"
hexmask.long.byte 0x8 0.--6. 1. " PCURRENT ,Pointer to current buffer"
line.long 0xC "TG2CTRL,MibSPI Transfer Group Control Register 2"
bitfld.long 0xC 31. " TGENA ,TG enable" "Disabled,Enabled"
bitfld.long 0xC 30. " ONESHOT ,Single transfer for TG" "Disabled,Enabled"
bitfld.long 0xC 29. " PRST ,TG pointer reset mode" "Disabled,Enabled"
textline " "
rbitfld.long 0xC 28. " TGTD ,TG triggered" "Not triggered,Triggered"
bitfld.long 0xC 20.--23. " TRGEVT ,Type of trigger event" "Never,Rising edge,Falling edge,Both edges,,High active,Low-active,Always,?..."
bitfld.long 0xC 16.--19. " TRIGSRC ,Trigger source" "Disabled,EXT[0],EXT[1],EXT[2],EXT[3],EXT[4],EXT[5],EXT[6],EXT[7],EXT[8],EXT[9,EXT[10,EXT[11,EXT[12,EXT[13],TICK"
textline " "
hexmask.long.byte 0xC 8.--14. 1. " PSTART ,TG start address"
hexmask.long.byte 0xC 0.--6. 1. " PCURRENT ,Pointer to current buffer"
line.long 0x10 "TG3CTRL,MibSPI Transfer Group Control Register 3"
bitfld.long 0x10 31. " TGENA ,TG enable" "Disabled,Enabled"
bitfld.long 0x10 30. " ONESHOT ,Single transfer for TG" "Disabled,Enabled"
bitfld.long 0x10 29. " PRST ,TG pointer reset mode" "Disabled,Enabled"
textline " "
rbitfld.long 0x10 28. " TGTD ,TG triggered" "Not triggered,Triggered"
bitfld.long 0x10 20.--23. " TRGEVT ,Type of trigger event" "Never,Rising edge,Falling edge,Both edges,,High active,Low-active,Always,?..."
bitfld.long 0x10 16.--19. " TRIGSRC ,Trigger source" "Disabled,EXT[0],EXT[1],EXT[2],EXT[3],EXT[4],EXT[5],EXT[6],EXT[7],EXT[8],EXT[9,EXT[10,EXT[11,EXT[12,EXT[13],TICK"
textline " "
hexmask.long.byte 0x10 8.--14. 1. " PSTART ,TG start address"
hexmask.long.byte 0x10 0.--6. 1. " PCURRENT ,Pointer to current buffer"
line.long 0x14 "TG4CTRL,MibSPI Transfer Group Control Register 4"
bitfld.long 0x14 31. " TGENA ,TG enable" "Disabled,Enabled"
bitfld.long 0x14 30. " ONESHOT ,Single transfer for TG" "Disabled,Enabled"
bitfld.long 0x14 29. " PRST ,TG pointer reset mode" "Disabled,Enabled"
textline " "
rbitfld.long 0x14 28. " TGTD ,TG triggered" "Not triggered,Triggered"
bitfld.long 0x14 20.--23. " TRGEVT ,Type of trigger event" "Never,Rising edge,Falling edge,Both edges,,High active,Low-active,Always,?..."
bitfld.long 0x14 16.--19. " TRIGSRC ,Trigger source" "Disabled,EXT[0],EXT[1],EXT[2],EXT[3],EXT[4],EXT[5],EXT[6],EXT[7],EXT[8],EXT[9,EXT[10,EXT[11,EXT[12,EXT[13],TICK"
textline " "
hexmask.long.byte 0x14 8.--14. 1. " PSTART ,TG start address"
hexmask.long.byte 0x14 0.--6. 1. " PCURRENT ,Pointer to current buffer"
line.long 0x18 "TG5CTRL,MibSPI Transfer Group Control Register 5"
bitfld.long 0x18 31. " TGENA ,TG enable" "Disabled,Enabled"
bitfld.long 0x18 30. " ONESHOT ,Single transfer for TG" "Disabled,Enabled"
bitfld.long 0x18 29. " PRST ,TG pointer reset mode" "Disabled,Enabled"
textline " "
rbitfld.long 0x18 28. " TGTD ,TG triggered" "Not triggered,Triggered"
bitfld.long 0x18 20.--23. " TRGEVT ,Type of trigger event" "Never,Rising edge,Falling edge,Both edges,,High active,Low-active,Always,?..."
bitfld.long 0x18 16.--19. " TRIGSRC ,Trigger source" "Disabled,EXT[0],EXT[1],EXT[2],EXT[3],EXT[4],EXT[5],EXT[6],EXT[7],EXT[8],EXT[9,EXT[10,EXT[11,EXT[12,EXT[13],TICK"
textline " "
hexmask.long.byte 0x18 8.--14. 1. " PSTART ,TG start address"
hexmask.long.byte 0x18 0.--6. 1. " PCURRENT ,Pointer to current buffer"
line.long 0x1C "TG6CTRL,MibSPI Transfer Group Control Register 6"
bitfld.long 0x1C 31. " TGENA ,TG enable" "Disabled,Enabled"
bitfld.long 0x1C 30. " ONESHOT ,Single transfer for TG" "Disabled,Enabled"
bitfld.long 0x1C 29. " PRST ,TG pointer reset mode" "Disabled,Enabled"
textline " "
rbitfld.long 0x1C 28. " TGTD ,TG triggered" "Not triggered,Triggered"
bitfld.long 0x1C 20.--23. " TRGEVT ,Type of trigger event" "Never,Rising edge,Falling edge,Both edges,,High active,Low-active,Always,?..."
bitfld.long 0x1C 16.--19. " TRIGSRC ,Trigger source" "Disabled,EXT[0],EXT[1],EXT[2],EXT[3],EXT[4],EXT[5],EXT[6],EXT[7],EXT[8],EXT[9,EXT[10,EXT[11,EXT[12,EXT[13],TICK"
textline " "
hexmask.long.byte 0x1C 8.--14. 1. " PSTART ,TG start address"
hexmask.long.byte 0x1C 0.--6. 1. " PCURRENT ,Pointer to current buffer"
line.long 0x20 "TG7CTRL,MibSPI Transfer Group Control Register 7"
bitfld.long 0x20 31. " TGENA ,TG enable" "Disabled,Enabled"
bitfld.long 0x20 30. " ONESHOT ,Single transfer for TG" "Disabled,Enabled"
bitfld.long 0x20 29. " PRST ,TG pointer reset mode" "Disabled,Enabled"
textline " "
rbitfld.long 0x20 28. " TGTD ,TG triggered" "Not triggered,Triggered"
bitfld.long 0x20 20.--23. " TRGEVT ,Type of trigger event" "Never,Rising edge,Falling edge,Both edges,,High active,Low-active,Always,?..."
bitfld.long 0x20 16.--19. " TRIGSRC ,Trigger source" "Disabled,EXT[0],EXT[1],EXT[2],EXT[3],EXT[4],EXT[5],EXT[6],EXT[7],EXT[8],EXT[9,EXT[10,EXT[11,EXT[12,EXT[13],TICK"
textline " "
hexmask.long.byte 0x20 8.--14. 1. " PSTART ,TG start address"
hexmask.long.byte 0x20 0.--6. 1. " PCURRENT ,Pointer to current buffer"
line.long 0x24 "TG8CTRL,MibSPI Transfer Group Control Register 8"
bitfld.long 0x24 31. " TGENA ,TG enable" "Disabled,Enabled"
bitfld.long 0x24 30. " ONESHOT ,Single transfer for TG" "Disabled,Enabled"
bitfld.long 0x24 29. " PRST ,TG pointer reset mode" "Disabled,Enabled"
textline " "
rbitfld.long 0x24 28. " TGTD ,TG triggered" "Not triggered,Triggered"
bitfld.long 0x24 20.--23. " TRGEVT ,Type of trigger event" "Never,Rising edge,Falling edge,Both edges,,High active,Low-active,Always,?..."
bitfld.long 0x24 16.--19. " TRIGSRC ,Trigger source" "Disabled,EXT[0],EXT[1],EXT[2],EXT[3],EXT[4],EXT[5],EXT[6],EXT[7],EXT[8],EXT[9,EXT[10,EXT[11,EXT[12,EXT[13],TICK"
textline " "
hexmask.long.byte 0x24 8.--14. 1. " PSTART ,TG start address"
hexmask.long.byte 0x24 0.--6. 1. " PCURRENT ,Pointer to current buffer"
line.long 0x28 "TG9CTRL,MibSPI Transfer Group Control Register 9"
bitfld.long 0x28 31. " TGENA ,TG enable" "Disabled,Enabled"
bitfld.long 0x28 30. " ONESHOT ,Single transfer for TG" "Disabled,Enabled"
bitfld.long 0x28 29. " PRST ,TG pointer reset mode" "Disabled,Enabled"
textline " "
rbitfld.long 0x28 28. " TGTD ,TG triggered" "Not triggered,Triggered"
bitfld.long 0x28 20.--23. " TRGEVT ,Type of trigger event" "Never,Rising edge,Falling edge,Both edges,,High active,Low-active,Always,?..."
bitfld.long 0x28 16.--19. " TRIGSRC ,Trigger source" "Disabled,EXT[0],EXT[1],EXT[2],EXT[3],EXT[4],EXT[5],EXT[6],EXT[7],EXT[8],EXT[9,EXT[10,EXT[11,EXT[12,EXT[13],TICK"
textline " "
hexmask.long.byte 0x28 8.--14. 1. " PSTART ,TG start address"
hexmask.long.byte 0x28 0.--6. 1. " PCURRENT ,Pointer to current buffer"
line.long 0x2C "TG10CTRL,MibSPI Transfer Group Control Register 10"
bitfld.long 0x2C 31. " TGENA ,TG enable" "Disabled,Enabled"
bitfld.long 0x2C 30. " ONESHOT ,Single transfer for TG" "Disabled,Enabled"
bitfld.long 0x2C 29. " PRST ,TG pointer reset mode" "Disabled,Enabled"
textline " "
rbitfld.long 0x2C 28. " TGTD ,TG triggered" "Not triggered,Triggered"
bitfld.long 0x2C 20.--23. " TRGEVT ,Type of trigger event" "Never,Rising edge,Falling edge,Both edges,,High active,Low-active,Always,?..."
bitfld.long 0x2C 16.--19. " TRIGSRC ,Trigger source" "Disabled,EXT[0],EXT[1],EXT[2],EXT[3],EXT[4],EXT[5],EXT[6],EXT[7],EXT[8],EXT[9,EXT[10,EXT[11,EXT[12,EXT[13],TICK"
textline " "
hexmask.long.byte 0x2C 8.--14. 1. " PSTART ,TG start address"
hexmask.long.byte 0x2C 0.--6. 1. " PCURRENT ,Pointer to current buffer"
line.long 0x30 "TG11CTRL,MibSPI Transfer Group Control Register 11"
bitfld.long 0x30 31. " TGENA ,TG enable" "Disabled,Enabled"
bitfld.long 0x30 30. " ONESHOT ,Single transfer for TG" "Disabled,Enabled"
bitfld.long 0x30 29. " PRST ,TG pointer reset mode" "Disabled,Enabled"
textline " "
rbitfld.long 0x30 28. " TGTD ,TG triggered" "Not triggered,Triggered"
bitfld.long 0x30 20.--23. " TRGEVT ,Type of trigger event" "Never,Rising edge,Falling edge,Both edges,,High active,Low-active,Always,?..."
bitfld.long 0x30 16.--19. " TRIGSRC ,Trigger source" "Disabled,EXT[0],EXT[1],EXT[2],EXT[3],EXT[4],EXT[5],EXT[6],EXT[7],EXT[8],EXT[9,EXT[10,EXT[11,EXT[12,EXT[13],TICK"
textline " "
hexmask.long.byte 0x30 8.--14. 1. " PSTART ,TG start address"
hexmask.long.byte 0x30 0.--6. 1. " PCURRENT ,Pointer to current buffer"
line.long 0x34 "TG12CTRL,MibSPI Transfer Group Control Register 12"
bitfld.long 0x34 31. " TGENA ,TG enable" "Disabled,Enabled"
bitfld.long 0x34 30. " ONESHOT ,Single transfer for TG" "Disabled,Enabled"
bitfld.long 0x34 29. " PRST ,TG pointer reset mode" "Disabled,Enabled"
textline " "
rbitfld.long 0x34 28. " TGTD ,TG triggered" "Not triggered,Triggered"
bitfld.long 0x34 20.--23. " TRGEVT ,Type of trigger event" "Never,Rising edge,Falling edge,Both edges,,High active,Low-active,Always,?..."
bitfld.long 0x34 16.--19. " TRIGSRC ,Trigger source" "Disabled,EXT[0],EXT[1],EXT[2],EXT[3],EXT[4],EXT[5],EXT[6],EXT[7],EXT[8],EXT[9,EXT[10,EXT[11,EXT[12,EXT[13],TICK"
textline " "
hexmask.long.byte 0x34 8.--14. 1. " PSTART ,TG start address"
hexmask.long.byte 0x34 0.--6. 1. " PCURRENT ,Pointer to current buffer"
line.long 0x38 "TG13CTRL,MibSPI Transfer Group Control Register 13"
bitfld.long 0x38 31. " TGENA ,TG enable" "Disabled,Enabled"
bitfld.long 0x38 30. " ONESHOT ,Single transfer for TG" "Disabled,Enabled"
bitfld.long 0x38 29. " PRST ,TG pointer reset mode" "Disabled,Enabled"
textline " "
rbitfld.long 0x38 28. " TGTD ,TG triggered" "Not triggered,Triggered"
bitfld.long 0x38 20.--23. " TRGEVT ,Type of trigger event" "Never,Rising edge,Falling edge,Both edges,,High active,Low-active,Always,?..."
bitfld.long 0x38 16.--19. " TRIGSRC ,Trigger source" "Disabled,EXT[0],EXT[1],EXT[2],EXT[3],EXT[4],EXT[5],EXT[6],EXT[7],EXT[8],EXT[9,EXT[10,EXT[11,EXT[12,EXT[13],TICK"
textline " "
hexmask.long.byte 0x38 8.--14. 1. " PSTART ,TG start address"
hexmask.long.byte 0x38 0.--6. 1. " PCURRENT ,Pointer to current buffer"
line.long 0x3C "TG14CTRL,MibSPI Transfer Group Control Register 14"
bitfld.long 0x3C 31. " TGENA ,TG enable" "Disabled,Enabled"
bitfld.long 0x3C 30. " ONESHOT ,Single transfer for TG" "Disabled,Enabled"
bitfld.long 0x3C 29. " PRST ,TG pointer reset mode" "Disabled,Enabled"
textline " "
rbitfld.long 0x3C 28. " TGTD ,TG triggered" "Not triggered,Triggered"
bitfld.long 0x3C 20.--23. " TRGEVT ,Type of trigger event" "Never,Rising edge,Falling edge,Both edges,,High active,Low-active,Always,?..."
bitfld.long 0x3C 16.--19. " TRIGSRC ,Trigger source" "Disabled,EXT[0],EXT[1],EXT[2],EXT[3],EXT[4],EXT[5],EXT[6],EXT[7],EXT[8],EXT[9,EXT[10,EXT[11,EXT[12,EXT[13],TICK"
textline " "
hexmask.long.byte 0x3C 8.--14. 1. " PSTART ,TG start address"
hexmask.long.byte 0x3C 0.--6. 1. " PCURRENT ,Pointer to current buffer"
line.long 0x40 "TG15CTRL,MibSPI Transfer Group Control Register 15"
bitfld.long 0x40 31. " TGENA ,TG enable" "Disabled,Enabled"
bitfld.long 0x40 30. " ONESHOT ,Single transfer for TG" "Disabled,Enabled"
bitfld.long 0x40 29. " PRST ,TG pointer reset mode" "Disabled,Enabled"
textline " "
rbitfld.long 0x40 28. " TGTD ,TG triggered" "Not triggered,Triggered"
bitfld.long 0x40 20.--23. " TRGEVT ,Type of trigger event" "Never,Rising edge,Falling edge,Both edges,,High active,Low-active,Always,?..."
bitfld.long 0x40 16.--19. " TRIGSRC ,Trigger source" "Disabled,EXT[0],EXT[1],EXT[2],EXT[3],EXT[4],EXT[5],EXT[6],EXT[7],EXT[8],EXT[9,EXT[10,EXT[11,EXT[12,EXT[13],TICK"
textline " "
hexmask.long.byte 0x40 8.--14. 1. " PSTART ,TG start address"
hexmask.long.byte 0x40 0.--6. 1. " PCURRENT ,Pointer to current buffer"
line.long 0x44 "TG16CTRL,MibSPI Transfer Group Control Register 16"
bitfld.long 0x44 31. " TGENA ,TG enable" "Disabled,Enabled"
bitfld.long 0x44 30. " ONESHOT ,Single transfer for TG" "Disabled,Enabled"
bitfld.long 0x44 29. " PRST ,TG pointer reset mode" "Disabled,Enabled"
textline " "
rbitfld.long 0x44 28. " TGTD ,TG triggered" "Not triggered,Triggered"
bitfld.long 0x44 20.--23. " TRGEVT ,Type of trigger event" "Never,Rising edge,Falling edge,Both edges,,High active,Low-active,Always,?..."
bitfld.long 0x44 16.--19. " TRIGSRC ,Trigger source" "Disabled,EXT[0],EXT[1],EXT[2],EXT[3],EXT[4],EXT[5],EXT[6],EXT[7],EXT[8],EXT[9,EXT[10,EXT[11,EXT[12,EXT[13],TICK"
textline " "
hexmask.long.byte 0x44 8.--14. 1. " PSTART ,TG start address"
hexmask.long.byte 0x44 0.--6. 1. " PCURRENT ,Pointer to current buffer"
if (((d.l(ad:0xFFF7F800+0x4))&0x3)==0x0)
group.long 0xD8++0x1F
line.long 0x0 "DMA1CTRL,MibSPI DMA Channel Control Register 1"
bitfld.long 0x0 31. " ONESHOT ,Auto-disable of DMA channel after ICOUNT+1 transfers" "0,1"
hexmask.long.byte 0x0 24.--30. 1. " BUFID ,Buffer utilized for DMA transfer"
bitfld.long 0x0 20.--23. " RXDMA_MAP ,Each MibSPI DMA channel can be linked to two physical DMA" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x0 16.--19. " TXDMA_MAP ,Each MibSPI DMA channel can be linked to two physical DMA" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x0 15. " RXDMAENA ,Receive data DMA channel enable" "Disabled,Enabled"
bitfld.long 0x0 14. " TXDMAENA ,Transmit data DMA channel enable" "Disabled,Enabled"
textline " "
bitfld.long 0x0 8.--12. " ICOUNT ,Initial count of DMA transfers" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32"
rbitfld.long 0x0 6. " COUNTBIT17 ,17th bit of the COUNT field of DMAxCOUNT register" "0,1"
rbitfld.long 0x0 0.--5. " COUNT ,Actual number of remaining DMA transfers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x4 "DMA2CTRL,MibSPI DMA Channel Control Register 1"
bitfld.long 0x4 31. " ONESHOT ,Auto-disable of DMA channel after ICOUNT+1 transfers" "0,1"
hexmask.long.byte 0x4 24.--30. 1. " BUFID ,Buffer utilized for DMA transfer"
bitfld.long 0x4 20.--23. " RXDMA_MAP ,Each MibSPI DMA channel can be linked to two physical DMA" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x4 16.--19. " TXDMA_MAP ,Each MibSPI DMA channel can be linked to two physical DMA" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x4 15. " RXDMAENA ,Receive data DMA channel enable" "Disabled,Enabled"
bitfld.long 0x4 14. " TXDMAENA ,Transmit data DMA channel enable" "Disabled,Enabled"
textline " "
bitfld.long 0x4 8.--12. " ICOUNT ,Initial count of DMA transfers" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32"
rbitfld.long 0x4 6. " COUNTBIT17 ,17th bit of the COUNT field of DMAxCOUNT register" "0,1"
rbitfld.long 0x4 0.--5. " COUNT ,Actual number of remaining DMA transfers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x8 "DMA3CTRL,MibSPI DMA Channel Control Register 1"
bitfld.long 0x8 31. " ONESHOT ,Auto-disable of DMA channel after ICOUNT+1 transfers" "0,1"
hexmask.long.byte 0x8 24.--30. 1. " BUFID ,Buffer utilized for DMA transfer"
bitfld.long 0x8 20.--23. " RXDMA_MAP ,Each MibSPI DMA channel can be linked to two physical DMA" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x8 16.--19. " TXDMA_MAP ,Each MibSPI DMA channel can be linked to two physical DMA" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x8 15. " RXDMAENA ,Receive data DMA channel enable" "Disabled,Enabled"
bitfld.long 0x8 14. " TXDMAENA ,Transmit data DMA channel enable" "Disabled,Enabled"
textline " "
bitfld.long 0x8 8.--12. " ICOUNT ,Initial count of DMA transfers" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32"
rbitfld.long 0x8 6. " COUNTBIT17 ,17th bit of the COUNT field of DMAxCOUNT register" "0,1"
rbitfld.long 0x8 0.--5. " COUNT ,Actual number of remaining DMA transfers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0xC "DMA4CTRL,MibSPI DMA Channel Control Register 1"
bitfld.long 0xC 31. " ONESHOT ,Auto-disable of DMA channel after ICOUNT+1 transfers" "0,1"
hexmask.long.byte 0xC 24.--30. 1. " BUFID ,Buffer utilized for DMA transfer"
bitfld.long 0xC 20.--23. " RXDMA_MAP ,Each MibSPI DMA channel can be linked to two physical DMA" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0xC 16.--19. " TXDMA_MAP ,Each MibSPI DMA channel can be linked to two physical DMA" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0xC 15. " RXDMAENA ,Receive data DMA channel enable" "Disabled,Enabled"
bitfld.long 0xC 14. " TXDMAENA ,Transmit data DMA channel enable" "Disabled,Enabled"
textline " "
bitfld.long 0xC 8.--12. " ICOUNT ,Initial count of DMA transfers" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32"
rbitfld.long 0xC 6. " COUNTBIT17 ,17th bit of the COUNT field of DMAxCOUNT register" "0,1"
rbitfld.long 0xC 0.--5. " COUNT ,Actual number of remaining DMA transfers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x10 "DMA5CTRL,MibSPI DMA Channel Control Register 1"
bitfld.long 0x10 31. " ONESHOT ,Auto-disable of DMA channel after ICOUNT+1 transfers" "0,1"
hexmask.long.byte 0x10 24.--30. 1. " BUFID ,Buffer utilized for DMA transfer"
bitfld.long 0x10 20.--23. " RXDMA_MAP ,Each MibSPI DMA channel can be linked to two physical DMA" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x10 16.--19. " TXDMA_MAP ,Each MibSPI DMA channel can be linked to two physical DMA" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x10 15. " RXDMAENA ,Receive data DMA channel enable" "Disabled,Enabled"
bitfld.long 0x10 14. " TXDMAENA ,Transmit data DMA channel enable" "Disabled,Enabled"
textline " "
bitfld.long 0x10 8.--12. " ICOUNT ,Initial count of DMA transfers" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32"
rbitfld.long 0x10 6. " COUNTBIT17 ,17th bit of the COUNT field of DMAxCOUNT register" "0,1"
rbitfld.long 0x10 0.--5. " COUNT ,Actual number of remaining DMA transfers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x14 "DMA6CTRL,MibSPI DMA Channel Control Register 1"
bitfld.long 0x14 31. " ONESHOT ,Auto-disable of DMA channel after ICOUNT+1 transfers" "0,1"
hexmask.long.byte 0x14 24.--30. 1. " BUFID ,Buffer utilized for DMA transfer"
bitfld.long 0x14 20.--23. " RXDMA_MAP ,Each MibSPI DMA channel can be linked to two physical DMA" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x14 16.--19. " TXDMA_MAP ,Each MibSPI DMA channel can be linked to two physical DMA" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x14 15. " RXDMAENA ,Receive data DMA channel enable" "Disabled,Enabled"
bitfld.long 0x14 14. " TXDMAENA ,Transmit data DMA channel enable" "Disabled,Enabled"
textline " "
bitfld.long 0x14 8.--12. " ICOUNT ,Initial count of DMA transfers" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32"
rbitfld.long 0x14 6. " COUNTBIT17 ,17th bit of the COUNT field of DMAxCOUNT register" "0,1"
rbitfld.long 0x14 0.--5. " COUNT ,Actual number of remaining DMA transfers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x18 "DMA7CTRL,MibSPI DMA Channel Control Register 1"
bitfld.long 0x18 31. " ONESHOT ,Auto-disable of DMA channel after ICOUNT+1 transfers" "0,1"
hexmask.long.byte 0x18 24.--30. 1. " BUFID ,Buffer utilized for DMA transfer"
bitfld.long 0x18 20.--23. " RXDMA_MAP ,Each MibSPI DMA channel can be linked to two physical DMA" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x18 16.--19. " TXDMA_MAP ,Each MibSPI DMA channel can be linked to two physical DMA" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x18 15. " RXDMAENA ,Receive data DMA channel enable" "Disabled,Enabled"
bitfld.long 0x18 14. " TXDMAENA ,Transmit data DMA channel enable" "Disabled,Enabled"
textline " "
bitfld.long 0x18 8.--12. " ICOUNT ,Initial count of DMA transfers" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32"
rbitfld.long 0x18 6. " COUNTBIT17 ,17th bit of the COUNT field of DMAxCOUNT register" "0,1"
rbitfld.long 0x18 0.--5. " COUNT ,Actual number of remaining DMA transfers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x1C "DMA8CTRL,MibSPI DMA Channel Control Register 1"
bitfld.long 0x1C 31. " ONESHOT ,Auto-disable of DMA channel after ICOUNT+1 transfers" "0,1"
hexmask.long.byte 0x1C 24.--30. 1. " BUFID ,Buffer utilized for DMA transfer"
bitfld.long 0x1C 20.--23. " RXDMA_MAP ,Each MibSPI DMA channel can be linked to two physical DMA" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x1C 16.--19. " TXDMA_MAP ,Each MibSPI DMA channel can be linked to two physical DMA" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x1C 15. " RXDMAENA ,Receive data DMA channel enable" "Disabled,Enabled"
bitfld.long 0x1C 14. " TXDMAENA ,Transmit data DMA channel enable" "Disabled,Enabled"
textline " "
bitfld.long 0x1C 8.--12. " ICOUNT ,Initial count of DMA transfers" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32"
rbitfld.long 0x1C 6. " COUNTBIT17 ,17th bit of the COUNT field of DMAxCOUNT register" "0,1"
rbitfld.long 0x1C 0.--5. " COUNT ,Actual number of remaining DMA transfers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
else
group.long 0xD8++0x1F
line.long 0x0 "DMA1CTRL,MibSPI DMA Channel Control Register 1"
bitfld.long 0x0 31. " ONESHOT ,Auto-disable of DMA channel after ICOUNT+1 transfers" "0,1"
hexmask.long.byte 0x0 24.--30. 1. " BUFID ,Buffer utilized for DMA transfer"
bitfld.long 0x0 20.--23. " RXDMA_MAP ,Each MibSPI DMA channel can be linked to two physical DMA" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x0 16.--19. " TXDMA_MAP ,Each MibSPI DMA channel can be linked to two physical DMA" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x0 15. " RXDMAENA ,Receive data DMA channel enable" "Disabled,Enabled"
bitfld.long 0x0 14. " TXDMAENA ,Transmit data DMA channel enable" "Disabled,Enabled"
textline " "
bitfld.long 0x0 13. " NOBRK ,Non-interleaved DMA block transfer" "Not performed,Performed"
bitfld.long 0x0 8.--12. " ICOUNT ,Initial count of DMA transfers" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32"
rbitfld.long 0x0 6. " COUNTBIT17 ,17th bit of the COUNT field of DMAxCOUNT register" "0,1"
textline " "
rbitfld.long 0x0 0.--5. " COUNT ,Actual number of remaining DMA transfers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x4 "DMA2CTRL,MibSPI DMA Channel Control Register 1"
bitfld.long 0x4 31. " ONESHOT ,Auto-disable of DMA channel after ICOUNT+1 transfers" "0,1"
hexmask.long.byte 0x4 24.--30. 1. " BUFID ,Buffer utilized for DMA transfer"
bitfld.long 0x4 20.--23. " RXDMA_MAP ,Each MibSPI DMA channel can be linked to two physical DMA" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x4 16.--19. " TXDMA_MAP ,Each MibSPI DMA channel can be linked to two physical DMA" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x4 15. " RXDMAENA ,Receive data DMA channel enable" "Disabled,Enabled"
bitfld.long 0x4 14. " TXDMAENA ,Transmit data DMA channel enable" "Disabled,Enabled"
textline " "
bitfld.long 0x4 13. " NOBRK ,Non-interleaved DMA block transfer" "Not performed,Performed"
bitfld.long 0x4 8.--12. " ICOUNT ,Initial count of DMA transfers" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32"
rbitfld.long 0x4 6. " COUNTBIT17 ,17th bit of the COUNT field of DMAxCOUNT register" "0,1"
textline " "
rbitfld.long 0x4 0.--5. " COUNT ,Actual number of remaining DMA transfers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x8 "DMA3CTRL,MibSPI DMA Channel Control Register 1"
bitfld.long 0x8 31. " ONESHOT ,Auto-disable of DMA channel after ICOUNT+1 transfers" "0,1"
hexmask.long.byte 0x8 24.--30. 1. " BUFID ,Buffer utilized for DMA transfer"
bitfld.long 0x8 20.--23. " RXDMA_MAP ,Each MibSPI DMA channel can be linked to two physical DMA" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x8 16.--19. " TXDMA_MAP ,Each MibSPI DMA channel can be linked to two physical DMA" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x8 15. " RXDMAENA ,Receive data DMA channel enable" "Disabled,Enabled"
bitfld.long 0x8 14. " TXDMAENA ,Transmit data DMA channel enable" "Disabled,Enabled"
textline " "
bitfld.long 0x8 13. " NOBRK ,Non-interleaved DMA block transfer" "Not performed,Performed"
bitfld.long 0x8 8.--12. " ICOUNT ,Initial count of DMA transfers" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32"
rbitfld.long 0x8 6. " COUNTBIT17 ,17th bit of the COUNT field of DMAxCOUNT register" "0,1"
textline " "
rbitfld.long 0x8 0.--5. " COUNT ,Actual number of remaining DMA transfers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0xC "DMA4CTRL,MibSPI DMA Channel Control Register 1"
bitfld.long 0xC 31. " ONESHOT ,Auto-disable of DMA channel after ICOUNT+1 transfers" "0,1"
hexmask.long.byte 0xC 24.--30. 1. " BUFID ,Buffer utilized for DMA transfer"
bitfld.long 0xC 20.--23. " RXDMA_MAP ,Each MibSPI DMA channel can be linked to two physical DMA" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0xC 16.--19. " TXDMA_MAP ,Each MibSPI DMA channel can be linked to two physical DMA" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0xC 15. " RXDMAENA ,Receive data DMA channel enable" "Disabled,Enabled"
bitfld.long 0xC 14. " TXDMAENA ,Transmit data DMA channel enable" "Disabled,Enabled"
textline " "
bitfld.long 0xC 13. " NOBRK ,Non-interleaved DMA block transfer" "Not performed,Performed"
bitfld.long 0xC 8.--12. " ICOUNT ,Initial count of DMA transfers" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32"
rbitfld.long 0xC 6. " COUNTBIT17 ,17th bit of the COUNT field of DMAxCOUNT register" "0,1"
textline " "
rbitfld.long 0xC 0.--5. " COUNT ,Actual number of remaining DMA transfers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x10 "DMA5CTRL,MibSPI DMA Channel Control Register 1"
bitfld.long 0x10 31. " ONESHOT ,Auto-disable of DMA channel after ICOUNT+1 transfers" "0,1"
hexmask.long.byte 0x10 24.--30. 1. " BUFID ,Buffer utilized for DMA transfer"
bitfld.long 0x10 20.--23. " RXDMA_MAP ,Each MibSPI DMA channel can be linked to two physical DMA" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x10 16.--19. " TXDMA_MAP ,Each MibSPI DMA channel can be linked to two physical DMA" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x10 15. " RXDMAENA ,Receive data DMA channel enable" "Disabled,Enabled"
bitfld.long 0x10 14. " TXDMAENA ,Transmit data DMA channel enable" "Disabled,Enabled"
textline " "
bitfld.long 0x10 13. " NOBRK ,Non-interleaved DMA block transfer" "Not performed,Performed"
bitfld.long 0x10 8.--12. " ICOUNT ,Initial count of DMA transfers" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32"
rbitfld.long 0x10 6. " COUNTBIT17 ,17th bit of the COUNT field of DMAxCOUNT register" "0,1"
textline " "
rbitfld.long 0x10 0.--5. " COUNT ,Actual number of remaining DMA transfers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x14 "DMA6CTRL,MibSPI DMA Channel Control Register 1"
bitfld.long 0x14 31. " ONESHOT ,Auto-disable of DMA channel after ICOUNT+1 transfers" "0,1"
hexmask.long.byte 0x14 24.--30. 1. " BUFID ,Buffer utilized for DMA transfer"
bitfld.long 0x14 20.--23. " RXDMA_MAP ,Each MibSPI DMA channel can be linked to two physical DMA" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x14 16.--19. " TXDMA_MAP ,Each MibSPI DMA channel can be linked to two physical DMA" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x14 15. " RXDMAENA ,Receive data DMA channel enable" "Disabled,Enabled"
bitfld.long 0x14 14. " TXDMAENA ,Transmit data DMA channel enable" "Disabled,Enabled"
textline " "
bitfld.long 0x14 13. " NOBRK ,Non-interleaved DMA block transfer" "Not performed,Performed"
bitfld.long 0x14 8.--12. " ICOUNT ,Initial count of DMA transfers" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32"
rbitfld.long 0x14 6. " COUNTBIT17 ,17th bit of the COUNT field of DMAxCOUNT register" "0,1"
textline " "
rbitfld.long 0x14 0.--5. " COUNT ,Actual number of remaining DMA transfers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x18 "DMA7CTRL,MibSPI DMA Channel Control Register 1"
bitfld.long 0x18 31. " ONESHOT ,Auto-disable of DMA channel after ICOUNT+1 transfers" "0,1"
hexmask.long.byte 0x18 24.--30. 1. " BUFID ,Buffer utilized for DMA transfer"
bitfld.long 0x18 20.--23. " RXDMA_MAP ,Each MibSPI DMA channel can be linked to two physical DMA" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x18 16.--19. " TXDMA_MAP ,Each MibSPI DMA channel can be linked to two physical DMA" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x18 15. " RXDMAENA ,Receive data DMA channel enable" "Disabled,Enabled"
bitfld.long 0x18 14. " TXDMAENA ,Transmit data DMA channel enable" "Disabled,Enabled"
textline " "
bitfld.long 0x18 13. " NOBRK ,Non-interleaved DMA block transfer" "Not performed,Performed"
bitfld.long 0x18 8.--12. " ICOUNT ,Initial count of DMA transfers" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32"
rbitfld.long 0x18 6. " COUNTBIT17 ,17th bit of the COUNT field of DMAxCOUNT register" "0,1"
textline " "
rbitfld.long 0x18 0.--5. " COUNT ,Actual number of remaining DMA transfers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x1C "DMA8CTRL,MibSPI DMA Channel Control Register 1"
bitfld.long 0x1C 31. " ONESHOT ,Auto-disable of DMA channel after ICOUNT+1 transfers" "0,1"
hexmask.long.byte 0x1C 24.--30. 1. " BUFID ,Buffer utilized for DMA transfer"
bitfld.long 0x1C 20.--23. " RXDMA_MAP ,Each MibSPI DMA channel can be linked to two physical DMA" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x1C 16.--19. " TXDMA_MAP ,Each MibSPI DMA channel can be linked to two physical DMA" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x1C 15. " RXDMAENA ,Receive data DMA channel enable" "Disabled,Enabled"
bitfld.long 0x1C 14. " TXDMAENA ,Transmit data DMA channel enable" "Disabled,Enabled"
textline " "
bitfld.long 0x1C 13. " NOBRK ,Non-interleaved DMA block transfer" "Not performed,Performed"
bitfld.long 0x1C 8.--12. " ICOUNT ,Initial count of DMA transfers" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32"
rbitfld.long 0x1C 6. " COUNTBIT17 ,17th bit of the COUNT field of DMAxCOUNT register" "0,1"
textline " "
rbitfld.long 0x1C 0.--5. " COUNT ,Actual number of remaining DMA transfers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
endif
group.long 0xF8++0x1F
line.long 0x0 "DMA0COUNT,MibSPI DMA0COUNT Register"
hexmask.long.word 0x0 16.--31. 1. " ICOUNT0 ,Initial number of DMA transfers"
hexmask.long.word 0x0 0.--15. 1. " COUNT0 ,The actual number of remaining DMA transfers"
line.long 0x4 "DMA1COUNT,MibSPI DMA1COUNT Register"
hexmask.long.word 0x4 16.--31. 1. " ICOUNT1 ,Initial number of DMA transfers"
hexmask.long.word 0x4 0.--15. 1. " COUNT1 ,The actual number of remaining DMA transfers"
line.long 0x8 "DMA2COUNT,MibSPI DMA2COUNT Register"
hexmask.long.word 0x8 16.--31. 1. " ICOUNT2 ,Initial number of DMA transfers"
hexmask.long.word 0x8 0.--15. 1. " COUNT2 ,The actual number of remaining DMA transfers"
line.long 0xC "DMA3COUNT,MibSPI DMA3COUNT Register"
hexmask.long.word 0xC 16.--31. 1. " ICOUNT3 ,Initial number of DMA transfers"
hexmask.long.word 0xC 0.--15. 1. " COUNT3 ,The actual number of remaining DMA transfers"
line.long 0x10 "DMA4COUNT,MibSPI DMA4COUNT Register"
hexmask.long.word 0x10 16.--31. 1. " ICOUNT4 ,Initial number of DMA transfers"
hexmask.long.word 0x10 0.--15. 1. " COUNT4 ,The actual number of remaining DMA transfers"
line.long 0x14 "DMA5COUNT,MibSPI DMA5COUNT Register"
hexmask.long.word 0x14 16.--31. 1. " ICOUNT5 ,Initial number of DMA transfers"
hexmask.long.word 0x14 0.--15. 1. " COUNT5 ,The actual number of remaining DMA transfers"
line.long 0x18 "DMA6COUNT,MibSPI DMA6COUNT Register"
hexmask.long.word 0x18 16.--31. 1. " ICOUNT6 ,Initial number of DMA transfers"
hexmask.long.word 0x18 0.--15. 1. " COUNT6 ,The actual number of remaining DMA transfers"
line.long 0x1C "DMA7COUNT,MibSPI DMA7COUNT Register"
hexmask.long.word 0x1C 16.--31. 1. " ICOUNT7 ,Initial number of DMA transfers"
hexmask.long.word 0x1C 0.--15. 1. " COUNT7 ,The actual number of remaining DMA transfers"
textline " "
group.long 0x118++0x03
line.long 0x00 "DMACNTLEN,MibSPI DMACNTLEN Register"
bitfld.long 0x00 0. " LARGECOUNT ,Counters select" "DMAxCTRL,DMAxCOUNT"
group.long 0x120++0x03
line.long 0x00 "UERRCTRL,Uncorrectable Parity Error Control Register"
sif cpu()=="TMS570LC4357"
bitfld.long 0x00 24.--27. " SBE_EVT_EN ,ECC Single Bit Error Event Enable" ",,,,,Disabled,,,,,Enabled,?..."
bitfld.long 0x00 16.--19. " EDAC_MODE ,ECC Single Bit Error Block Correction" ",,,,,Disabled,,,,,Enabled,?..."
textline " "
endif
bitfld.long 0x00 8. " PTESTEN ,Parity memory test enable" "Disabled,Enabled"
bitfld.long 0x00 0.--3. " EDEN ,Error detection enable" "Enabled,Enabled,Enabled,Enabled,Enabled,Disabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled"
group.long 0x124++0x03
line.long 0x00 "UERRSTAT,Uncorrectable Parity Error Status Register"
sif cpu()=="TMS570LC4357"
eventfld.long 0x00 9. " SBE_FLG1 ,Single Bit Error in RXRAM" "Not occurred,Occurred"
eventfld.long 0x00 8. " SBE_FLG0 ,Single Bit Error in TXRAM" "Not occurred,Occurred"
textline " "
eventfld.long 0x00 1. " EDFLG1 ,Uncorrectable parity error detection flag" "Not occurred,Occurred"
eventfld.long 0x00 0. " EDFLG0 ,Uncorrectable parity error detection flag" "Not occurred,Occurred"
else
eventfld.long 0x00 1. " EDFLG1 ,Uncorrectable parity error detection flag" "Not occurred,Occurred"
eventfld.long 0x00 0. " EDFLG0 ,Uncorrectable parity error detection flag" "Not occurred,Occurred"
endif
width 17.
hgroup.long 0x128++0x03
hide.long 0x00 "UERRADDR1,Uncorrectable Parity Error Address Register"
in
hgroup.long 0x12C++0x03
hide.long 0x00 "UERRADDR0,Uncorrectable Parity Error Address Register"
in
hgroup.long 0x130++0x03
hide.long 0x00 "RXOVRN_BUF_ADDR,Receive RAM Overrun Buffer Address Register"
in
textline " "
width 14.
if (((d.l(ad:0xFFF7F800+0x134))&0x2)==0x2)&&(((d.l(ad:0xFFF7F800+0x134))&0xF00)==0xA00)
group.long 0x134++0x03
line.long 0x00 "IOLPBKTSTCR,SPI IO Loopback Test Control Register"
bitfld.long 0x00 24. " SCSFAILFLG ,Failure on SPISCS pin compare during analog loopback" "Not occurred,Occurred"
bitfld.long 0x00 20. " CTRL_BITERR ,Controls inducing of BITERR during I/O loopback test mode" "Disabled,Enabled"
bitfld.long 0x00 19. " CTRL_DESYNC ,Controls inducing of the desync error during I/O loopback test mode" "No error,Error"
textline " "
bitfld.long 0x00 18. " CTRL_PARERR ,Controls inducing of parity errors during I/O loopback test mode" "No error,Error"
bitfld.long 0x00 17. " CTRL_TIMEOUT ,Controls inducing of the timeout error during I/O loopbacK test mode" "No error,Error"
bitfld.long 0x00 16. " CTRL_DLENERR ,Controls inducing of the data length error during I/O loopback test mode" "No error,Error"
textline " "
bitfld.long 0x00 8.--11. " IOLPBKTSTENA ,Module I/O loopback test enable key" "Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Enabled,Disabled,Disabled,Disabled,Disabled,Disabled"
bitfld.long 0x00 3.--5. " ERRSCSPIN ,Inject error on chip-select pin number" "/SPISCS[0],/SPISCS[1],/SPISCS[2],/SPISCS[3],/SPISCS[4],/SPISCS[5],/SPISCS[6],/SPISCS[7]"
bitfld.long 0x00 2. " CTRLSCSPINERR ,Enable/disable the injection of an error on the SPISCS[3:0] pins" "Disabled,Enabled"
textline " "
bitfld.long 0x00 1. " LPBK_TYPE ,Module I/O loopback type (analog/digital)" "Digital,Analog"
bitfld.long 0x00 0. " RXP_ENA ,Enable analog loopback through the receive pin" "Transmit,Receive"
elif (((d.l(ad:0xFFF7F800+0x134))&0x2)==0x0)&&(((d.l(ad:0xFFF7F800+0x134))&0xF00)==0xA00)
group.long 0x134++0x03
line.long 0x00 "IOLPBKTSTCR,SPI IO Loopback Test Control Register"
eventfld.long 0x00 24. " SCSFAILFLG ,Failure on SPISCS pin compare during analog loopback" "Not occurred,Occurred"
bitfld.long 0x00 20. " CTRL_BITERR ,Controls inducing of BITERR during I/O loopback test mode" "Disabled,Enabled"
bitfld.long 0x00 19. " CTRL_DESYNC ,Controls inducing of the desync error during I/O loopback test mode" "No error,Error"
textline " "
bitfld.long 0x00 18. " CTRL_PARERR ,Controls inducing of parity errors during I/O loopback test mode" "No error,Error"
bitfld.long 0x00 17. " CTRL_TIMEOUT ,Controls inducing of the timeout error during I/O loopbacK test mode" "No error,Error"
bitfld.long 0x00 16. " CTRL_DLENERR ,Controls inducing of the data length error during I/O loopback test mode" "No error,Error"
textline " "
bitfld.long 0x00 8.--11. " IOLPBKTSTENA ,Module I/O loopback test enable key" "Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Enabled,Disabled,Disabled,Disabled,Disabled,Disabled"
bitfld.long 0x00 3.--5. " ERRSCSPIN ,Inject error on chip-select pin number" "/SPISCS[0],/SPISCS[1],/SPISCS[2],/SPISCS[3],/SPISCS[4],/SPISCS[5],/SPISCS[6],/SPISCS[7]"
bitfld.long 0x00 2. " CTRLSCSPINERR ,Enable/disable the injection of an error on the SPISCS[3:0] pins" "Disabled,Enabled"
textline " "
bitfld.long 0x00 1. " LPBK_TYPE ,Module I/O loopback type (analog/digital)" "Digital,Analog"
elif (((d.l(ad:0xFFF7F800+0x134))&0x2)==0x2)&&(((d.l(ad:0xFFF7F800+0x134))&0xF00)!=0xA00)
group.long 0x134++0x03
line.long 0x00 "IOLPBKTSTCR,SPI IO Loopback Test Control Register"
bitfld.long 0x00 8.--11. " IOLPBKTSTENA ,Module I/O loopback test enable key" "Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Enabled,Disabled,Disabled,Disabled,Disabled,Disabled"
bitfld.long 0x00 3.--5. " ERRSCSPIN ,Inject error on chip-select pin number" "/SPISCS[0],/SPISCS[1],/SPISCS[2],/SPISCS[3],/SPISCS[4],/SPISCS[5],/SPISCS[6],/SPISCS[7]"
bitfld.long 0x00 2. " CTRLSCSPINERR ,Enable/disable the injection of an error on the SPISCS[3:0] pins" "Disabled,Enabled"
textline " "
bitfld.long 0x00 1. " LPBK_TYPE ,Module I/O loopback type (analog/digital)" "Digital,Analog"
bitfld.long 0x00 0. " RXP_ENA ,Enable analog loopback through the receive pin" "Transmit,Receive"
else
group.long 0x134++0x03
line.long 0x00 "IOLPBKTSTCR,SPI IO Loopback Test Control Register"
bitfld.long 0x00 8.--11. " IOLPBKTSTENA ,Module I/O loopback test enable key" "Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Enabled,Disabled,Disabled,Disabled,Disabled,Disabled"
bitfld.long 0x00 3.--5. " ERRSCSPIN ,Inject error on chip-select pin number" "/SPISCS[0],/SPISCS[1],/SPISCS[2],/SPISCS[3],/SPISCS[4],/SPISCS[5],/SPISCS[6],/SPISCS[7]"
bitfld.long 0x00 2. " CTRLSCSPINERR ,Enable/disable the injection of an error on the SPISCS[3:0] pins" "Disabled,Enabled"
textline " "
bitfld.long 0x00 1. " LPBK_TYPE ,Module I/O loopback type (analog/digital)" "Digital,Analog"
endif
textline " "
width 21.
group.long 0x138++0x07
line.long 0x00 "EXTENDED_PRESCALE_1,SPI Extended Prescale Register 1"
hexmask.long.word 0x00 16.--26. 1. " EPRESCALE_FMT1 ,Extended Prescale value for SPIFMT1"
hexmask.long.word 0x00 0.--10. 1. " EPRESCALE_FMT0 ,Extended Prescale value for SPIFMT0"
line.long 0x04 "EXTENDED_PRESCALE_2,SPI Extended Prescale Register 2"
hexmask.long.word 0x04 16.--26. 1. " EPRESCALE_FMT3 ,Extended Prescale value for SPIFMT3"
hexmask.long.word 0x04 0.--10. 1. " EPRESCALE_FMT2 ,Extended Prescale value for SPIFMT2"
sif cpu()!="TMS570LC4357"
group.long 0x140++0x03
line.long 0x00 "ECCDIAG_CTRL,ECC Diagnostic Control register"
bitfld.long 0x00 0.--3. " ECCDIAG_EN ,ECC Diagnostic mode Enable Key bits" "Disabled,Disabled,Disabled,Disabled,Disabled,Enabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled"
endif
if ((d.l(ad:0xFFF7F800+0x140)&0x5)==0x5)
group.long 0x144++0x03
line.long 0x00 "ECCDIAG_STAT, ECC Diagnostic Status Register"
eventfld.long 0x00 17. " DEFLG[1] ,Double bit Error is detected for RXRAM" "No error,Error"
eventfld.long 0x00 16. " DEFLG[0] ,Double bit Error is detected for TXRAM" "No error,Error"
eventfld.long 0x00 1. " SEFLG[1] ,Single bit Error is detected for RXRAM" "No error,Error"
eventfld.long 0x00 0. " SEFLG[0] ,Single bit Error is detected for TXRAM" "No error,Error"
else
hgroup.long 0x144++0x03
hide.long 0x00 "ECCDIAG_STAT,ECC Diagnostic Status Register"
in
endif
hgroup.long 0x148++0x03
hide.long 0x00 "SBERRADDR1,Single Bit Error Address Register - RXRAM"
in
hgroup.long 0x14C++0x03
hide.long 0x00 "SBERRADDR0,Single Bit Error Address Register - TXRAM"
in
tree.end
tree "MibSPI4"
base ad:0xFFF7FA00
width 17.
group.long 0x00++0x03
line.long 0x00 "SPIGCR0,SPI Global Control Register 0"
bitfld.long 0x00 0. " NRESET ,Reset bit for the module" "No reset,Reset"
if (((d.l(ad:0xFFF7FA00+0x4))&0x3)==0x00)
group.long 0x04++0x03
line.long 0x00 "SPIGCR1,SPI Global Control Register 1"
bitfld.long 0x00 24. " SPIEN ,SPI enable" "Disabled,Enabled"
bitfld.long 0x00 16. " LOOPBACK ,Internal loop-back test mode" "Disabled,Enabled"
bitfld.long 0x00 8. " POWERDOWN ,SPI state machine enters a power-down state" "No power-down,Power-down"
textline " "
bitfld.long 0x00 1. " CLKMOD ,Clock mode" "External,Internally"
bitfld.long 0x00 0. " MASTER ,SPISIMO/SPISOMI pin direction determination" "Input/ouput,Output/input"
else
group.long 0x04++0x03
line.long 0x00 "SPIGCR1,SPI Global Control Register 1"
bitfld.long 0x00 24. " SPIEN ,SPI enable" "Disabled,Enabled"
bitfld.long 0x00 8. " POWERDOWN ,SPI state machine enters a power-down state" "No power-down,Power-down"
bitfld.long 0x00 1. " CLKMOD ,Clock mode" "External,Internally"
textline " "
bitfld.long 0x00 0. " MASTER ,SPISIMO/SPISOMI pin direction determination" "Input/ouput,Output/input"
endif
group.long 0x08++0x03
line.long 0x00 "SPIINT0,SPI Interrupt Register"
bitfld.long 0x00 24. " ENABLEHIGHZ ,SPIENA pin high-impedance enable" "Inactive,Active"
bitfld.long 0x00 16. " DMAREQEN ,DMA request enable" "Disabled,Enabled"
bitfld.long 0x00 9. " TXINTENA ,TX interrupt flag enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 8. " RXINTENA ,RX interrupt flag enable" "Disabled,Enabled"
bitfld.long 0x00 6. " RXOVRNINTENA ,Overrun interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 4. " BITERRENA ,Enables interrupt on bit error" "Disabled,Enabled"
textline " "
bitfld.long 0x00 3. " DESYNCENA ,Enables interrupt on desynchronized slave" "Disabled,Enabled"
bitfld.long 0x00 2. " PARERRENA ,Enables interrupt-on-parity-error" "Disabled,Enabled"
bitfld.long 0x00 1. " TIMEOUTENA ,Enables interrupt on ENA signal time-out" "Disabled,Enabled"
textline " "
bitfld.long 0x00 0. " DLENERRENA ,Data length error interrupt enable" "Disabled,Enabled"
group.long 0x0C++0x03
line.long 0x00 "SPILVL,SPI Interrupt Level Register"
bitfld.long 0x00 9. " TXINTLVL ,Transmit interrupt level" "INT0,INT1"
bitfld.long 0x00 8. " RXINTLVL ,Receive interrupt level" "INT0,INT1"
bitfld.long 0x00 6. " RXOVRNINTLVL ,Receive overrun interrupt level" "INT0,INT1"
textline " "
bitfld.long 0x00 4. " BITERRLVL ,Bit error interrupt level" "INT0,INT1"
bitfld.long 0x00 3. " DESYNCLVL ,Desynchronized slave interrupt level (master mode only)" "INT0,INT1"
bitfld.long 0x00 2. " PARERRLVL ,Parity error interrupt level" "INT0,INT1"
textline " "
bitfld.long 0x00 1. " TIMEOUTLVL ,SPIENA pin time-out interrupt level" "INT0,INT1"
bitfld.long 0x00 0. " DLENERRLVL ,Data length error interrupt level (line) select" "INT0,INT1"
group.long 0x10++0x03
line.long 0x00 "SPIFLG,SPI Flag Register"
rbitfld.long 0x00 24. " BUFINITACTIVE ,Indicates the status of multi-buffer initialization process" "Completed,Not completed"
rbitfld.long 0x00 9. " TXINTFLG ,Transmitter-empty interrupt flag" "No interrupt,Interrupt"
eventfld.long 0x00 8. " RXINTFLG ,Receiver-full interrupt flag" "No interrupt,Interrupt"
textline " "
eventfld.long 0x00 6. " RXOVRNINTFLG ,Overrun interrupt enable" "Disabled,Enabled"
eventfld.long 0x00 4. " BITERRFLG ,Enables interrupt on bit error" "Disabled,Enabled"
eventfld.long 0x00 3. " DESYNCFLG ,Enables interrupt on desynchronized slave" "No interrupt,Interrupt"
textline " "
eventfld.long 0x00 2. " PARITYERRFLG ,Enables interrupt-on-parity-error" "No error,Error"
eventfld.long 0x00 1. " TIMEOUTFLG ,Enables interrupt on ENA signal time-out" "No interrupt,Interrupt"
eventfld.long 0x00 0. " DLENERRFLG ,Data length error interrupt enable" "No interrupt,Interrupt"
textline " "
width 12.
group.long 0x14++0x23
line.long 0x00 "SPIPC0,SPI Pin Control Register 0"
bitfld.long 0x00 31. " SOMIFUN[7] ,SPISOMI[7] pin function" "GIO,SPI"
bitfld.long 0x00 30. " [6] ,SPISOMI[6] pin function" "GIO,SPI"
bitfld.long 0x00 29. " [5] ,SPISOMI[5] pin function" "GIO,SPI"
bitfld.long 0x00 28. " [4] ,SPISOMI[4] pin function" "GIO,SPI"
textline " "
bitfld.long 0x00 27. " [3] ,SPISOMI[3] pin function" "GIO,SPI"
bitfld.long 0x00 26. " [2] ,SPISOMI[2] pin function" "GIO,SPI"
bitfld.long 0x00 25. " [1] ,SPISOMI[1] pin function" "GIO,SPI"
bitfld.long 0x00 24. " [0] ,SPISOMI[0] pin function (mirror of bit 11)" "GIO,SPI"
textline " "
bitfld.long 0x00 23. " SIMOFUN[7] ,SPISIMO[7] pin function" "GIO,SPI"
bitfld.long 0x00 22. " [6] ,SPISIMO[6] pin function" "GIO,SPI"
bitfld.long 0x00 21. " [5] ,SPISIMO[5] pin function" "GIO,SPI"
bitfld.long 0x00 20. " [4] ,SPISIMO[4] pin function" "GIO,SPI"
textline " "
bitfld.long 0x00 19. " [3] ,SPISIMO[3] pin function" "GIO,SPI"
bitfld.long 0x00 18. " [2] ,SPISIMO[2] pin function" "GIO,SPI"
bitfld.long 0x00 17. " [1] ,SPISIMO[1] pin function" "GIO,SPI"
bitfld.long 0x00 16. " [0] ,SPISIMO[0] pin function (mirror of bit 10)" "GIO,SPI"
textline " "
bitfld.long 0x00 11. " SOMIFUN[0] ,SPISOMI[0] pin function" "GIO,SPI"
bitfld.long 0x00 10. " SIMOFUN[0] ,SPISIMO[0] pin function" "GIO,SPI"
bitfld.long 0x00 9. " CLKFUN ,SPI clock function" "GIO,SPI"
bitfld.long 0x00 8. " ENAFUN ,SPIENA function" "GIO,SPI"
textline " "
textline " "
bitfld.long 0x00 7. " SCSFUN[7] ,SPISCS7 function 7" "GIO,SPI"
bitfld.long 0x00 6. " [6] ,SPISCS6 function 6" "GIO,SPI"
bitfld.long 0x00 5. " [5] ,SPISCS5 function 5" "GIO,SPI"
bitfld.long 0x00 4. " [4] ,SPISCS4 function 4" "GIO,SPI"
textline " "
bitfld.long 0x00 3. " [3] ,SPISCS3 function 3" "GIO,SPI"
bitfld.long 0x00 2. " [2] ,SPISCS2 function 2" "GIO,SPI"
bitfld.long 0x00 1. " [1] ,SPISCS1 function 1" "GIO,SPI"
bitfld.long 0x00 0. " [0] ,SPISCS0 function 0" "GIO,SPI"
textline " "
line.long 0x04 "SPIPC1,SPI Pin Control Register 1"
bitfld.long 0x04 31. " SOMIDIR[7] ,SPISOMI[7] pin direction" "GIO,SPI"
bitfld.long 0x04 30. " [6] ,SPISOMI[6] pin direction" "GIO,SPI"
bitfld.long 0x04 29. " [5] ,SPISOMI[5] pin direction" "GIO,SPI"
bitfld.long 0x04 28. " [4] ,SPISOMI[4] pin direction" "GIO,SPI"
textline " "
bitfld.long 0x04 27. " [3] ,SPISOMI[3] pin direction" "GIO,SPI"
bitfld.long 0x04 26. " [2] ,SPISOMI[2] pin direction" "GIO,SPI"
bitfld.long 0x04 25. " [1] ,SPISOMI[1] pin direction" "GIO,SPI"
bitfld.long 0x04 24. " [0] ,SPISOMI[0] pin direction (mirror of bit 11)" "GIO,SPI"
textline " "
bitfld.long 0x04 23. " SIMODIR[7] ,SPISIMO[7] pin direction" "GIO,SPI"
bitfld.long 0x04 22. " [6] ,SPISIMO[6] pin direction" "GIO,SPI"
bitfld.long 0x04 21. " [5] ,SPISIMO[5] pin direction" "GIO,SPI"
bitfld.long 0x04 20. " [4] ,SPISIMO[4] pin direction" "GIO,SPI"
textline " "
bitfld.long 0x04 19. " [3] ,SPISIMO[3] pin direction" "GIO,SPI"
bitfld.long 0x04 18. " [2] ,SPISIMO[2] pin direction" "GIO,SPI"
bitfld.long 0x04 17. " [1] ,SPISIMO[1] pin direction" "GIO,SPI"
bitfld.long 0x04 16. " [0] ,SPISIMO[0] pin direction (mirror of bit 10)" "GIO,SPI"
textline " "
bitfld.long 0x04 11. " SOMIDIR[0] ,SPISOMI[0] pin direction" "GIO,SPI"
bitfld.long 0x04 10. " SIMODIR[0] ,SPISIMO[0] pin direction" "GIO,SPI"
bitfld.long 0x04 9. " CLKDIR ,SPI clock direction" "GIO,SPI"
bitfld.long 0x04 8. " ENADIR ,SPIENA direction" "GIO,SPI"
textline " "
textline " "
bitfld.long 0x04 7. " SCSDIR[7] ,SPISCS7 direction 7" "GIO,SPI"
bitfld.long 0x04 6. " [6] ,SPISCS6 direction 6" "GIO,SPI"
bitfld.long 0x04 5. " [5] ,SPISCS5 direction 5" "GIO,SPI"
bitfld.long 0x04 4. " [4] ,SPISCS4 direction 4" "GIO,SPI"
textline " "
bitfld.long 0x04 3. " [3] ,SPISCS3 direction 3" "GIO,SPI"
bitfld.long 0x04 2. " [2] ,SPISCS2 direction 2" "GIO,SPI"
bitfld.long 0x04 1. " [1] ,SPISCS1 direction 1" "GIO,SPI"
bitfld.long 0x04 0. " [0] ,SPISCS0 direction 0" "GIO,SPI"
textline " "
line.long 0x08 "SPIPC2,SPI Pin Control Register 2"
bitfld.long 0x08 31. " SOMIDIN[7] ,SPISOMI[7] data in" "0,1"
bitfld.long 0x08 30. " [6] ,SPISOMI[6] data in" "0,1"
bitfld.long 0x08 29. " [5] ,SPISOMI[5] data in" "0,1"
bitfld.long 0x08 28. " [4] ,SPISOMI[4] data in" "0,1"
bitfld.long 0x08 27. " [3] ,SPISOMI[3] data in" "0,1"
bitfld.long 0x08 26. " [2] ,SPISOMI[2] data in" "0,1"
bitfld.long 0x08 25. " [1] ,SPISOMI[1] data in" "0,1"
bitfld.long 0x08 24. " [0] ,SPISOMI[0] data in (mirror of bit 11)" "0,1"
textline " "
bitfld.long 0x08 23. " SIMODIN[7] ,SPISIMO[7] data in" "0,1"
bitfld.long 0x08 22. " [6] ,SPISIMO[6] data in" "0,1"
bitfld.long 0x08 21. " [5] ,SPISIMO[5] data in" "0,1"
bitfld.long 0x08 20. " [4] ,SPISIMO[4] data in" "0,1"
bitfld.long 0x08 19. " [3] ,SPISIMO[3] data in" "0,1"
bitfld.long 0x08 18. " [2] ,SPISIMO[2] data in" "0,1"
bitfld.long 0x08 17. " [1] ,SPISIMO[1] data in" "0,1"
bitfld.long 0x08 16. " [0] ,SPISIMO[0] data in (mirror of bit 10)" "0,1"
textline " "
bitfld.long 0x08 11. " SOMIDIN[0] ,SPISOMI[0] data in" "0,1"
bitfld.long 0x08 10. " SIMODIN[0] ,SPISIMO[0] data in" "0,1"
bitfld.long 0x08 9. " CLKDIN ,SPI clock data in" "0,1"
bitfld.long 0x08 8. " ENADIN ,SPIENA data in" "0,1"
textline " "
textline " "
bitfld.long 0x08 7. " SCSDIN[7] ,SPISCS7 data in" "0,1"
bitfld.long 0x08 6. " [6] ,SPISCS6 data in" "0,1"
bitfld.long 0x08 5. " [5] ,SPISCS5 data in" "0,1"
bitfld.long 0x08 4. " [4] ,SPISCS4 data in" "0,1"
bitfld.long 0x08 3. " [3] ,SPISCS3 data in" "0,1"
bitfld.long 0x08 2. " [2] ,SPISCS2 data in" "0,1"
bitfld.long 0x08 1. " [1] ,SPISCS1 data in" "0,1"
bitfld.long 0x08 0. " [0] ,SPISCS0 direction 0" "0,1"
textline " "
line.long 0x0C "SPIPC3,SPI Pin Control Register 3"
bitfld.long 0x0C 31. " SOMIDOUT[7] ,SPISOMI[7] data out write" "0,1"
bitfld.long 0x0C 30. " [6] ,SPISOMI[6] data out write" "0,1"
bitfld.long 0x0C 29. " [5] ,SPISOMI[5] data out write" "0,1"
bitfld.long 0x0C 28. " [4] ,SPISOMI[4] data out write" "0,1"
bitfld.long 0x0C 27. " [3] ,SPISOMI[3] data out write" "0,1"
bitfld.long 0x0C 26. " [2] ,SPISOMI[2] data out write" "0,1"
bitfld.long 0x0C 25. " [1] ,SPISOMI[1] data out write" "0,1"
bitfld.long 0x0C 24. " [0] ,SPISOMI[0] data out write (mirror of bit 11)" "0,1"
textline " "
bitfld.long 0x0C 23. " SIMODOUT[7] ,SPISIMO[7] data out write" "0,1"
bitfld.long 0x0C 22. " [6] ,SPISIMO[6] data out write" "0,1"
bitfld.long 0x0C 21. " [5] ,SPISIMO[5] data out write" "0,1"
bitfld.long 0x0C 20. " [4] ,SPISIMO[4] data out write" "0,1"
bitfld.long 0x0C 19. " [3] ,SPISIMO[3] data out write" "0,1"
bitfld.long 0x0C 18. " [2] ,SPISIMO[2] data out write" "0,1"
bitfld.long 0x0C 17. " [1] ,SPISIMO[1] data out write" "0,1"
bitfld.long 0x0C 16. " [0] ,SPISIMO[0] data out write (mirror of bit 10)" "0,1"
textline " "
bitfld.long 0x0C 11. " SOMIDOUT[0] ,SPISOMI[0] data out write" "0,1"
bitfld.long 0x0C 10. " SIMODOUT[0] ,SPISIMO[0] data out write" "0,1"
bitfld.long 0x0C 9. " CLKDOUT ,SPI clock data out write" "0,1"
bitfld.long 0x0C 8. " ENADOUT ,SPIENA data out write" "0,1"
textline " "
textline " "
bitfld.long 0x0C 7. " SCSDOUT[7] ,SPISCS7 data out write" "0,1"
bitfld.long 0x0C 6. " [6] ,SPISCS6 data out write" "0,1"
bitfld.long 0x0C 5. " [5] ,SPISCS5 data out write" "0,1"
bitfld.long 0x0C 4. " [4] ,SPISCS4 data out write" "0,1"
bitfld.long 0x0C 3. " [3] ,SPISCS3 data out write" "0,1"
bitfld.long 0x0C 2. " [2] ,SPISCS2 data out write" "0,1"
bitfld.long 0x0C 1. " [1] ,SPISCS1 data out write" "0,1"
bitfld.long 0x0C 0. " [0] ,SPISCS0 data out write" "0,1"
textline " "
line.long 0x10 "SPIPC4,SPI Pin Control Register 4"
bitfld.long 0x10 31. " SOMISET[7] ,SPISOMI[7] data out set" "0,1"
bitfld.long 0x10 30. " [6] ,SPISOMI[6] data out set" "0,1"
bitfld.long 0x10 29. " [5] ,SPISOMI[5] data out set" "0,1"
bitfld.long 0x10 28. " [4] ,SPISOMI[4] data out set" "0,1"
bitfld.long 0x10 27. " [3] ,SPISOMI[3] data out set" "0,1"
bitfld.long 0x10 26. " [2] ,SPISOMI[2] data out set" "0,1"
bitfld.long 0x10 25. " [1] ,SPISOMI[1] data out set" "0,1"
bitfld.long 0x10 24. " [0] ,SPISOMI[0] data out set (mirror of bit 11)" "0,1"
textline " "
bitfld.long 0x10 23. " SIMOSET[7] ,SPISIMO[7] data out set" "0,1"
bitfld.long 0x10 22. " [6] ,SPISIMO[6] data out set" "0,1"
bitfld.long 0x10 21. " [5] ,SPISIMO[5] data out set" "0,1"
bitfld.long 0x10 20. " [4] ,SPISIMO[4] data out set" "0,1"
bitfld.long 0x10 19. " [3] ,SPISIMO[3] data out set" "0,1"
bitfld.long 0x10 18. " [2] ,SPISIMO[2] data out set" "0,1"
bitfld.long 0x10 17. " [1] ,SPISIMO[1] data out set" "0,1"
bitfld.long 0x10 16. " [0] ,SPISIMO[0] data out set (mirror of bit 10)" "0,1"
textline " "
bitfld.long 0x10 11. " SOMISET[0] ,SPISOMI[0] data out set" "0,1"
bitfld.long 0x10 10. " SIMOSET[0] ,SPISIMO[0] data out set" "0,1"
bitfld.long 0x10 9. " CLKSET ,SPI clock data out set" "0,1"
bitfld.long 0x10 8. " ENASET ,SPIENA data out set" "0,1"
textline " "
textline " "
bitfld.long 0x10 7. " SCSSET[7] ,SPISCS7 data out set" "0,1"
bitfld.long 0x10 6. " [6] ,SPISCS6 data out set" "0,1"
bitfld.long 0x10 5. " [5] ,SPISCS5 data out set" "0,1"
bitfld.long 0x10 4. " [4] ,SPISCS4 data out set" "0,1"
bitfld.long 0x10 3. " [3] ,SPISCS3 data out set" "0,1"
bitfld.long 0x10 2. " [2] ,SPISCS2 data out set" "0,1"
bitfld.long 0x10 1. " [1] ,SPISCS1 data out set" "0,1"
bitfld.long 0x10 0. " [0] ,SPISCS0 data out set" "0,1"
textline " "
line.long 0x14 "SPIPC5,SPI Pin Control Register 5"
bitfld.long 0x14 31. " SOMICLR[7] ,SPISOMI[7] data out clear" "0,1"
bitfld.long 0x14 30. " [6] ,SPISOMI[6] data out clear" "0,1"
bitfld.long 0x14 29. " [5] ,SPISOMI[5] data out clear" "0,1"
bitfld.long 0x14 28. " [4] ,SPISOMI[4] data out clear" "0,1"
bitfld.long 0x14 27. " [3] ,SPISOMI[3] data out clear" "0,1"
bitfld.long 0x14 26. " [2] ,SPISOMI[2] data out clear" "0,1"
bitfld.long 0x14 25. " [1] ,SPISOMI[1] data out clear" "0,1"
bitfld.long 0x14 24. " [0] ,SPISOMI[0] data out clear (mirror of bit 11)" "0,1"
textline " "
bitfld.long 0x14 23. " SIMOCLR[7] ,SPISIMO[7] data out clear" "0,1"
bitfld.long 0x14 22. " [6] ,SPISIMO[6] data out clear" "0,1"
bitfld.long 0x14 21. " [5] ,SPISIMO[5] data out clear" "0,1"
bitfld.long 0x14 20. " [4] ,SPISIMO[4] data out clear" "0,1"
bitfld.long 0x14 19. " [3] ,SPISIMO[3] data out clear" "0,1"
bitfld.long 0x14 18. " [2] ,SPISIMO[2] data out clear" "0,1"
bitfld.long 0x14 17. " [1] ,SPISIMO[1] data out clear" "0,1"
bitfld.long 0x14 16. " [0] ,SPISIMO[0] data out clear (mirror of bit 10)" "0,1"
textline " "
bitfld.long 0x14 11. " SOMICLR[0] ,SPISOMI[0] data out clear" "0,1"
bitfld.long 0x14 10. " SIMOCLR[0] ,SPISIMO[0] data out clear" "0,1"
bitfld.long 0x14 9. " CLKCLR ,SPI clock data out clear" "0,1"
bitfld.long 0x14 8. " ENACLR ,SPIENA data out clear" "0,1"
textline " "
textline " "
bitfld.long 0x14 7. " SCSCLR[7] ,SPISCS7 data out clear" "0,1"
bitfld.long 0x14 6. " [6] ,SPISCS6 data out clear" "0,1"
bitfld.long 0x14 5. " [5] ,SPISCS5 data out clear" "0,1"
bitfld.long 0x14 4. " [4] ,SPISCS4 data out clear" "0,1"
bitfld.long 0x14 3. " [3] ,SPISCS3 data out clear" "0,1"
bitfld.long 0x14 2. " [2] ,SPISCS2 data out clear" "0,1"
bitfld.long 0x14 1. " [1] ,SPISCS1 data out clear" "0,1"
bitfld.long 0x14 0. " [0] ,SPISCS0 data out clear" "0,1"
textline " "
line.long 0x18 "SPIPC6,SPI Pin Control Register 6"
bitfld.long 0x18 31. " SOMIPDR[7] ,SPISOMI[7] open drain enable" "Disabled,Enabled"
bitfld.long 0x18 30. " [6] ,SPISOMI[6] open drain enable" "Disabled,Enabled"
bitfld.long 0x18 29. " [5] ,SPISOMI[5] open drain enable" "Disabled,Enabled"
bitfld.long 0x18 28. " [4] ,SPISOMI[4] open drain enable" "Disabled,Enabled"
textline " "
bitfld.long 0x18 27. " [3] ,SPISOMI[3] open drain enable" "Disabled,Enabled"
bitfld.long 0x18 26. " [2] ,SPISOMI[2] open drain enable" "Disabled,Enabled"
bitfld.long 0x18 25. " [1] ,SPISOMI[1] open drain enable" "Disabled,Enabled"
bitfld.long 0x18 24. " [0] ,SPISOMI[0] open drain enable (mirror of bit 11)" "Disabled,Enabled"
textline " "
bitfld.long 0x18 23. " SIMOPDR[7] ,SPISIMO[7] open drain enable" "Disabled,Enabled"
bitfld.long 0x18 22. " [6] ,SPISIMO[6] open drain enable" "Disabled,Enabled"
bitfld.long 0x18 21. " [5] ,SPISIMO[5] open drain enable" "Disabled,Enabled"
bitfld.long 0x18 20. " [4] ,SPISIMO[4] open drain enable" "Disabled,Enabled"
textline " "
bitfld.long 0x18 19. " [3] ,SPISIMO[3] open drain enable" "Disabled,Enabled"
bitfld.long 0x18 18. " [2] ,SPISIMO[2] open drain enable" "Disabled,Enabled"
bitfld.long 0x18 17. " [1] ,SPISIMO[1] open drain enable" "Disabled,Enabled"
bitfld.long 0x18 16. " [0] ,SPISIMO[0] open drain enable (mirror of bit 10)" "Disabled,Enabled"
textline " "
bitfld.long 0x18 11. " SOMIPDR[0] ,SPISOMI[0] open drain enable" "Disabled,Enabled"
bitfld.long 0x18 10. " SIMOPDR[0] ,SPISIMO[0] open drain enable" "Disabled,Enabled"
bitfld.long 0x18 9. " CLKPDR ,SPI clock open drain enable" "Disabled,Enabled"
bitfld.long 0x18 8. " ENAPDR ,SPIENA open drain enable" "Disabled,Enabled"
textline " "
textline " "
bitfld.long 0x18 7. " SCSPDR[7] ,SPISCS7 open drain enable" "Disabled,Enabled"
bitfld.long 0x18 6. " [6] ,SPISCS6 open drain enable" "Disabled,Enabled"
bitfld.long 0x18 5. " [5] ,SPISCS5 open drain enable" "Disabled,Enabled"
bitfld.long 0x18 4. " [4] ,SPISCS4 open drain enable" "Disabled,Enabled"
textline " "
bitfld.long 0x18 3. " [3] ,SPISCS3 open drain enable" "Disabled,Enabled"
bitfld.long 0x18 2. " [2] ,SPISCS2 open drain enable" "Disabled,Enabled"
bitfld.long 0x18 1. " [1] ,SPISCS1 open drain enable" "Disabled,Enabled"
bitfld.long 0x18 0. " [0] ,SPISCS0 open drain enable" "Disabled,Enabled"
textline " "
line.long 0x1C "SPIPC7,SPI Pin Control Register 7"
bitfld.long 0x1C 31. " SOMIPDIS[7] ,SPISOMI[7] pull control enable/disable" "No,Yes"
bitfld.long 0x1C 30. " [6] ,SPISOMI[6] pull control enable/disable" "No,Yes"
bitfld.long 0x1C 29. " [5] ,SPISOMI[5] pull control enable/disable" "No,Yes"
bitfld.long 0x1C 28. " [4] ,SPISOMI[4] pull control enable/disable" "No,Yes"
textline " "
bitfld.long 0x1C 27. " [3] ,SPISOMI[3] pull control enable/disable" "No,Yes"
bitfld.long 0x1C 26. " [2] ,SPISOMI[2] pull control enable/disable" "No,Yes"
bitfld.long 0x1C 25. " [1] ,SPISOMI[1] pull control enable/disable" "No,Yes"
bitfld.long 0x1C 24. " [0] ,SPISOMI[0] pull control enable/disable (mirror of bit 11)" "No,Yes"
textline " "
bitfld.long 0x1C 23. " SIMOPDIS[7] ,SPISIMO[7] pull control enable/disable" "No,Yes"
bitfld.long 0x1C 22. " [6] ,SPISIMO[6] pull control enable/disable" "No,Yes"
bitfld.long 0x1C 21. " [5] ,SPISIMO[5] pull control enable/disable" "No,Yes"
bitfld.long 0x1C 20. " [4] ,SPISIMO[4] pull control enable/disable" "No,Yes"
textline " "
bitfld.long 0x1C 19. " [3] ,SPISIMO[3] pull control enable/disable" "No,Yes"
bitfld.long 0x1C 18. " [2] ,SPISIMO[2] pull control enable/disable" "No,Yes"
bitfld.long 0x1C 17. " [1] ,SPISIMO[1] pull control enable/disable" "No,Yes"
bitfld.long 0x1C 16. " [0] ,SPISIMO[0] pull control enable/disable (mirror of bit 10)" "No,Yes"
textline " "
bitfld.long 0x1C 11. " SOMIPDIS[0] ,SPISOMI[0] pull control enable/disable" "No,Yes"
bitfld.long 0x1C 10. " SIMOPDIS[0] ,SPISIMO[0] pull control enable/disable" "No,Yes"
bitfld.long 0x1C 9. " CLKPDIS ,SPI clock pull control enable/disable" "No,Yes"
bitfld.long 0x1C 8. " ENAPDIS ,SPIENA pull control enable/disable" "No,Yes"
textline " "
textline " "
bitfld.long 0x1C 7. " SCSPDIS[7] ,SPISCS7 pull control enable/disable" "No,Yes"
bitfld.long 0x1C 6. " [6] ,SPISCS6 pull control enable/disable" "No,Yes"
bitfld.long 0x1C 5. " [5] ,SPISCS5 pull control enable/disable" "No,Yes"
bitfld.long 0x1C 4. " [4] ,SPISCS4 pull control enable/disable" "No,Yes"
textline " "
bitfld.long 0x1C 3. " [3] ,SPISCS3 pull control enable/disable" "No,Yes"
bitfld.long 0x1C 2. " [2] ,SPISCS2 pull control enable/disable" "No,Yes"
bitfld.long 0x1C 1. " [1] ,SPISCS1 pull control enable/disable" "No,Yes"
bitfld.long 0x1C 0. " [0] ,SPISCS0 pull control enable/disable" "No,Yes"
textline " "
line.long 0x20 "SPIPC8,SPI Pin Control Register 8"
bitfld.long 0x20 31. " SOMIPSEL[7] ,SPISOMI[7] pull select" "Pull down,Pull up"
bitfld.long 0x20 30. " [6] ,SPISOMI[6] pull select" "Pull down,Pull up"
bitfld.long 0x20 29. " [5] ,SPISOMI[5] pull select" "Pull down,Pull up"
bitfld.long 0x20 28. " [4] ,SPISOMI[4] pull select" "Pull down,Pull up"
textline " "
bitfld.long 0x20 27. " [3] ,SPISOMI[3] pull select" "Pull down,Pull up"
bitfld.long 0x20 26. " [2] ,SPISOMI[2] pull select" "Pull down,Pull up"
bitfld.long 0x20 25. " [1] ,SPISOMI[1] pull select" "Pull down,Pull up"
bitfld.long 0x20 24. " [0] ,SPISOMI[0] pull select (mirror of bit 11)" "Pull down,Pull up"
textline " "
bitfld.long 0x20 23. " SIMOPSEL[7] ,SPISIMO[7] pull select" "Pull down,Pull up"
bitfld.long 0x20 22. " [6] ,SPISIMO[6] pull select" "Pull down,Pull up"
bitfld.long 0x20 21. " [5] ,SPISIMO[5] pull select" "Pull down,Pull up"
bitfld.long 0x20 20. " [4] ,SPISIMO[4] pull select" "Pull down,Pull up"
textline " "
bitfld.long 0x20 19. " [3] ,SPISIMO[3] pull select" "Pull down,Pull up"
bitfld.long 0x20 18. " [2] ,SPISIMO[2] pull select" "Pull down,Pull up"
bitfld.long 0x20 17. " [1] ,SPISIMO[1] pull select" "Pull down,Pull up"
bitfld.long 0x20 16. " [0] ,SPISIMO[0] pull select (mirror of bit 10)" "Pull down,Pull up"
textline " "
bitfld.long 0x20 11. " SOMIPSEL[0] ,SPISOMI[0] pull select" "Pull down,Pull up"
bitfld.long 0x20 10. " SIMOPSEL[0] ,SPISIMO[0] pull select" "Pull down,Pull up"
bitfld.long 0x20 9. " CLKPSEL ,SPI clock pull select" "Pull down,Pull up"
bitfld.long 0x20 8. " ENAPSEL ,SPIENA pull select" "Pull down,Pull up"
textline " "
textline " "
bitfld.long 0x20 7. " SCSPSEL[7] ,SPISCS7 pull select" "Pull down,Pull up"
bitfld.long 0x20 6. " [6] ,SPISCS6 pull select" "Pull down,Pull up"
bitfld.long 0x20 5. " [5] ,SPISCS5 pull select" "Pull down,Pull up"
bitfld.long 0x20 4. " [4] ,SPISCS4 pull select" "Pull down,Pull up"
textline " "
bitfld.long 0x20 3. " [3] ,SPISCS3 pull select" "Pull down,Pull up"
bitfld.long 0x20 2. " [2] ,SPISCS2 pull select" "Pull down,Pull up"
bitfld.long 0x20 1. " [1] ,SPISCS1 pull select" "Pull down,Pull up"
bitfld.long 0x20 0. " [0] ,SPISCS0 pull select" "Pull down,Pull up"
textline " "
group.long 0x38++0x03
line.long 0x00 "SPIDAT0,SPI Transmit Data Register 0"
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,SPI transmit data"
if (((d.l(ad:0xFFF7FA00+0x4))&0x3)==0x0)
group.long 0x3C++0x03
line.long 0x00 "SPIDAT1,Transmit Data Register 1"
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Inactive,Active"
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "No delay,After transaction"
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
textline " "
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
else
group.long 0x3C++0x03
line.long 0x00 "SPIDAT1,Transmit Data Register 1"
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Inactive,Active"
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
textline " "
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
endif
width 17.
hgroup.long 0x40++0x03
hide.long 0x00 "SPIBUF,SPI Receive Buffer Register"
in
rgroup.long 0x44++0x03
line.long 0x00 "SPIEMU,SPI Emulation Register"
hexmask.long.word 0x00 0.--15. 1. " EMU_RXDATA ,SPI receive data"
if (((d.l(ad:0xFFF7FA00+0x4))&0x1)==0x1)
rgroup.long 0x48++0x03
line.long 0x00 "SPIDELAY,SPI Delay Register"
hexmask.long.byte 0x00 24.--31. 1. " C2TDELAY ,Chip-select-active to transmit-start delay"
hexmask.long.byte 0x00 16.--23. 1. " T2CDELAY ,Transmit-end-to-chip-select-inactive-delay"
hexmask.long.byte 0x00 8.--15. 1. " T2EDELAY ,Transmit-data-finished to ENA-pin-inactive time-out"
textline " "
hexmask.long.byte 0x00 0.--7. 1. " C2EDELAY ,Chip-select-active to ENA-signal-active time-out"
group.long 0x4C++0x03
line.long 0x00 "SPIDEF,SPI Default Chip Select Register"
bitfld.long 0x00 7. " CSDEF[7] ,Chip select default pattern 7" "0,1"
bitfld.long 0x00 6. " [6] ,Chip select default pattern 6" "0,1"
bitfld.long 0x00 5. " [5] ,Chip select default pattern 5" "0,1"
textline " "
bitfld.long 0x00 4. " [4] ,Chip select default pattern 4" "0,1"
bitfld.long 0x00 3. " [3] ,Chip select default pattern 3" "0,1"
bitfld.long 0x00 2. " [2] ,Chip select default pattern 2" "0,1"
textline " "
bitfld.long 0x00 1. " [1] ,Chip select default pattern 1" "0,1"
bitfld.long 0x00 0. " [0] ,Chip select default pattern 0" "0,1"
endif
if (((d.l(ad:0xFFF7FA00+0x4))&0x3)==0x0)
group.long 0x50++0x0F
line.long 0x0 "SPIFMT0,SPI Data Format Register 0"
sif cpuis("TMS570LC4357")
hexmask.long.byte 0x0 24.--31. 1. " WDELAY ,Delay in between transmissions for data format 0"
else
bitfld.long 0x0 24.--29. " WDELAY ,Delay in between transmissions for data format 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
endif
bitfld.long 0x0 23. " PARPOL ,Parity polarity: even or odd" "Even,Odd"
textline " "
bitfld.long 0x0 22. " PARITYENA ,Parity enable for data format 0" "Disabled,Enabled"
bitfld.long 0x0 20. " SHIFTDIR ,Shift direction for data format $" "MSB,LSB"
textline " "
sif cpuis("TMS570LC4357")
bitfld.long 0x0 19. " HDUPLEX_ENA0 ,Half Duplex transfer mode enable for Data Format 0" "Normal,TX"
endif
textline " "
bitfld.long 0x0 18. " DISCSTIMERS ,Disable chip-select timers for this format" "No,Yes"
textline " "
bitfld.long 0x0 17. " POLARITY ,SPI data format 0 clock polarity" "Low,High"
bitfld.long 0x0 16. " PHASE ,SPI data format 0 clock delay" "Disabled,Enabled"
textline " "
hexmask.long.byte 0x0 8.--15. 1. " PRESCALE ,SPI data format 0 prescaler"
bitfld.long 0x0 0.--4. " CHARLEN ,SPI data format 0 data-word length" ",,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,?..."
line.long 0x4 "SPIFMT1,SPI Data Format Register 1"
sif cpuis("TMS570LC4357")
hexmask.long.byte 0x4 24.--31. 1. " WDELAY ,Delay in between transmissions for data format 1"
else
bitfld.long 0x4 24.--29. " WDELAY ,Delay in between transmissions for data format 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
endif
bitfld.long 0x4 23. " PARPOL ,Parity polarity: even or odd" "Even,Odd"
textline " "
bitfld.long 0x4 22. " PARITYENA ,Parity enable for data format 1" "Disabled,Enabled"
bitfld.long 0x4 20. " SHIFTDIR ,Shift direction for data format $" "MSB,LSB"
textline " "
sif cpuis("TMS570LC4357")
bitfld.long 0x4 19. " HDUPLEX_ENA1 ,Half Duplex transfer mode enable for Data Format 1" "Normal,TX"
endif
textline " "
bitfld.long 0x4 18. " DISCSTIMERS ,Disable chip-select timers for this format" "No,Yes"
textline " "
bitfld.long 0x4 17. " POLARITY ,SPI data format 1 clock polarity" "Low,High"
bitfld.long 0x4 16. " PHASE ,SPI data format 1 clock delay" "Disabled,Enabled"
textline " "
hexmask.long.byte 0x4 8.--15. 1. " PRESCALE ,SPI data format 1 prescaler"
bitfld.long 0x4 0.--4. " CHARLEN ,SPI data format 1 data-word length" ",,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,?..."
line.long 0x8 "SPIFMT2,SPI Data Format Register 2"
sif cpuis("TMS570LC4357")
hexmask.long.byte 0x8 24.--31. 1. " WDELAY ,Delay in between transmissions for data format 2"
else
bitfld.long 0x8 24.--29. " WDELAY ,Delay in between transmissions for data format 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
endif
bitfld.long 0x8 23. " PARPOL ,Parity polarity: even or odd" "Even,Odd"
textline " "
bitfld.long 0x8 22. " PARITYENA ,Parity enable for data format 2" "Disabled,Enabled"
bitfld.long 0x8 20. " SHIFTDIR ,Shift direction for data format $" "MSB,LSB"
textline " "
sif cpuis("TMS570LC4357")
bitfld.long 0x8 19. " HDUPLEX_ENA2 ,Half Duplex transfer mode enable for Data Format 2" "Normal,TX"
endif
textline " "
bitfld.long 0x8 18. " DISCSTIMERS ,Disable chip-select timers for this format" "No,Yes"
textline " "
bitfld.long 0x8 17. " POLARITY ,SPI data format 2 clock polarity" "Low,High"
bitfld.long 0x8 16. " PHASE ,SPI data format 2 clock delay" "Disabled,Enabled"
textline " "
hexmask.long.byte 0x8 8.--15. 1. " PRESCALE ,SPI data format 2 prescaler"
bitfld.long 0x8 0.--4. " CHARLEN ,SPI data format 2 data-word length" ",,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,?..."
line.long 0xC "SPIFMT3,SPI Data Format Register 3"
sif cpuis("TMS570LC4357")
hexmask.long.byte 0xC 24.--31. 1. " WDELAY ,Delay in between transmissions for data format 3"
else
bitfld.long 0xC 24.--29. " WDELAY ,Delay in between transmissions for data format 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
endif
bitfld.long 0xC 23. " PARPOL ,Parity polarity: even or odd" "Even,Odd"
textline " "
bitfld.long 0xC 22. " PARITYENA ,Parity enable for data format 3" "Disabled,Enabled"
bitfld.long 0xC 20. " SHIFTDIR ,Shift direction for data format $" "MSB,LSB"
textline " "
sif cpuis("TMS570LC4357")
bitfld.long 0xC 19. " HDUPLEX_ENA3 ,Half Duplex transfer mode enable for Data Format 3" "Normal,TX"
endif
textline " "
bitfld.long 0xC 18. " DISCSTIMERS ,Disable chip-select timers for this format" "No,Yes"
textline " "
bitfld.long 0xC 17. " POLARITY ,SPI data format 3 clock polarity" "Low,High"
bitfld.long 0xC 16. " PHASE ,SPI data format 3 clock delay" "Disabled,Enabled"
textline " "
hexmask.long.byte 0xC 8.--15. 1. " PRESCALE ,SPI data format 3 prescaler"
bitfld.long 0xC 0.--4. " CHARLEN ,SPI data format 3 data-word length" ",,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,?..."
else
group.long 0x50++0x0F
line.long 0x0 "SPIFMT0,SPI Data Format Register 0"
sif cpuis("TMS570LC4357")
hexmask.long.byte 0x0 24.--31. 1. " WDELAY ,Delay in between transmissions for data format 0"
else
bitfld.long 0x0 24.--29. " WDELAY ,Delay in between transmissions for data format 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
endif
bitfld.long 0x0 23. " PARPOL ,Parity polarity: even or odd" "Even,Odd"
textline " "
bitfld.long 0x0 22. " PARITYENA ,Parity enable for data format 0" "Disabled,Enabled"
bitfld.long 0x0 21. " WAITENA ,The master waits for the ENA signal from slave for data format 0" "Disabled,Enabled"
textline " "
bitfld.long 0x0 20. " SHIFTDIR ,Shift direction for data format $" "MSB,LSB"
sif cpuis("TMS570LC4357")
bitfld.long 0x0 19. " HDUPLEX_ENA0 ,Half Duplex transfer mode enable for Data Format 0" "Normal,RX"
endif
textline " "
bitfld.long 0x0 18. " DISCSTIMERS ,Disable chip-select timers for this format" "No,Yes"
textline " "
bitfld.long 0x0 17. " POLARITY ,SPI data format 0 clock polarity" "Low,High"
bitfld.long 0x0 16. " PHASE ,SPI data format 0 clock delay" "Disabled,Enabled"
textline " "
hexmask.long.byte 0x0 8.--15. 1. " PRESCALE ,SPI data format 0 prescaler"
bitfld.long 0x0 0.--4. " CHARLEN ,SPI data format 0 data-word length" ",,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,?..."
line.long 0x4 "SPIFMT1,SPI Data Format Register 1"
sif cpuis("TMS570LC4357")
hexmask.long.byte 0x4 24.--31. 1. " WDELAY ,Delay in between transmissions for data format 1"
else
bitfld.long 0x4 24.--29. " WDELAY ,Delay in between transmissions for data format 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
endif
bitfld.long 0x4 23. " PARPOL ,Parity polarity: even or odd" "Even,Odd"
textline " "
bitfld.long 0x4 22. " PARITYENA ,Parity enable for data format 1" "Disabled,Enabled"
bitfld.long 0x4 21. " WAITENA ,The master waits for the ENA signal from slave for data format 1" "Disabled,Enabled"
textline " "
bitfld.long 0x4 20. " SHIFTDIR ,Shift direction for data format $" "MSB,LSB"
sif cpuis("TMS570LC4357")
bitfld.long 0x4 19. " HDUPLEX_ENA1 ,Half Duplex transfer mode enable for Data Format 1" "Normal,RX"
endif
textline " "
bitfld.long 0x4 18. " DISCSTIMERS ,Disable chip-select timers for this format" "No,Yes"
textline " "
bitfld.long 0x4 17. " POLARITY ,SPI data format 1 clock polarity" "Low,High"
bitfld.long 0x4 16. " PHASE ,SPI data format 1 clock delay" "Disabled,Enabled"
textline " "
hexmask.long.byte 0x4 8.--15. 1. " PRESCALE ,SPI data format 1 prescaler"
bitfld.long 0x4 0.--4. " CHARLEN ,SPI data format 1 data-word length" ",,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,?..."
line.long 0x8 "SPIFMT2,SPI Data Format Register 2"
sif cpuis("TMS570LC4357")
hexmask.long.byte 0x8 24.--31. 1. " WDELAY ,Delay in between transmissions for data format 2"
else
bitfld.long 0x8 24.--29. " WDELAY ,Delay in between transmissions for data format 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
endif
bitfld.long 0x8 23. " PARPOL ,Parity polarity: even or odd" "Even,Odd"
textline " "
bitfld.long 0x8 22. " PARITYENA ,Parity enable for data format 2" "Disabled,Enabled"
bitfld.long 0x8 21. " WAITENA ,The master waits for the ENA signal from slave for data format 2" "Disabled,Enabled"
textline " "
bitfld.long 0x8 20. " SHIFTDIR ,Shift direction for data format $" "MSB,LSB"
sif cpuis("TMS570LC4357")
bitfld.long 0x8 19. " HDUPLEX_ENA2 ,Half Duplex transfer mode enable for Data Format 2" "Normal,RX"
endif
textline " "
bitfld.long 0x8 18. " DISCSTIMERS ,Disable chip-select timers for this format" "No,Yes"
textline " "
bitfld.long 0x8 17. " POLARITY ,SPI data format 2 clock polarity" "Low,High"
bitfld.long 0x8 16. " PHASE ,SPI data format 2 clock delay" "Disabled,Enabled"
textline " "
hexmask.long.byte 0x8 8.--15. 1. " PRESCALE ,SPI data format 2 prescaler"
bitfld.long 0x8 0.--4. " CHARLEN ,SPI data format 2 data-word length" ",,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,?..."
line.long 0xC "SPIFMT3,SPI Data Format Register 3"
sif cpuis("TMS570LC4357")
hexmask.long.byte 0xC 24.--31. 1. " WDELAY ,Delay in between transmissions for data format 3"
else
bitfld.long 0xC 24.--29. " WDELAY ,Delay in between transmissions for data format 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
endif
bitfld.long 0xC 23. " PARPOL ,Parity polarity: even or odd" "Even,Odd"
textline " "
bitfld.long 0xC 22. " PARITYENA ,Parity enable for data format 3" "Disabled,Enabled"
bitfld.long 0xC 21. " WAITENA ,The master waits for the ENA signal from slave for data format 3" "Disabled,Enabled"
textline " "
bitfld.long 0xC 20. " SHIFTDIR ,Shift direction for data format $" "MSB,LSB"
sif cpuis("TMS570LC4357")
bitfld.long 0xC 19. " HDUPLEX_ENA3 ,Half Duplex transfer mode enable for Data Format 3" "Normal,RX"
endif
textline " "
bitfld.long 0xC 18. " DISCSTIMERS ,Disable chip-select timers for this format" "No,Yes"
textline " "
bitfld.long 0xC 17. " POLARITY ,SPI data format 3 clock polarity" "Low,High"
bitfld.long 0xC 16. " PHASE ,SPI data format 3 clock delay" "Disabled,Enabled"
textline " "
hexmask.long.byte 0xC 8.--15. 1. " PRESCALE ,SPI data format 3 prescaler"
bitfld.long 0xC 0.--4. " CHARLEN ,SPI data format 3 data-word length" ",,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,?..."
endif
hgroup.long 0x60++0x03
hide.long 0x00 "TGINTVECT0,SPI Interrupt Vector Register 0 / MibSPI Transfer Group Interrupt Vector Register 0"
in
hgroup.long 0x64++0x03
hide.long 0x00 "TGINTVECT1,SPI Interrupt Vector Register 1 / MibSPI Transfer Group Interrupt Vector Register 1"
in
group.long 0x6C++0x07
line.long 0x00 "SPIPMCTRL,SPI Parallel/Modulo Mode Control Register"
bitfld.long 0x00 29. " MODCLKPOL3 ,Modulo mode SPICLK polarity" "Normal,Inverted"
bitfld.long 0x00 26.--28. " MMODE3 ,SPI/MibSPI data lines" "1,2,3,4,5,6,?..."
bitfld.long 0x00 24.--25. " PMODE3 ,Parallel mode data lines" "1,2,4,8"
textline " "
bitfld.long 0x00 21. " MODCLKPOL2 ,Modulo mode SPICLK polarity" "Normal,Inverted"
bitfld.long 0x00 18.--20. " MMODE2 ,SPI/MibSPI data lines" "1,2,3,4,5,6,?..."
bitfld.long 0x00 16.--17. " PMODE2 ,Parallel mode data lines" "1,2,4,8"
textline " "
bitfld.long 0x00 13. " MODCLKPOL1 ,Modulo mode SPICLK polarity" "Normal,Inverted"
bitfld.long 0x00 10.--12. " MMODE1 ,SPI/MibSPI data lines" "1,2,3,4,5,6,?..."
bitfld.long 0x00 8.--9. " PMODE1 ,Parallel mode data lines" "1,2,4,8"
textline " "
bitfld.long 0x00 5. " MODCLKPOL0 ,Modulo mode SPICLK polarity" "Normal,Inverted"
bitfld.long 0x00 2.--4. " MMODE0 ,SPI/MibSPI data lines" "1,2,3,4,5,6,?..."
bitfld.long 0x00 0.--1. " PMODE0 ,Parallel mode data lines" "1,2,4,8"
line.long 0x04 "MIBSPIE,MibSPI Enable Register"
bitfld.long 0x04 16. " RXRAMACCESS ,Receive-RAM access control" "Not writable,Accessible"
bitfld.long 0x04 0. " MIBSPIENA ,Multi-buffer mode enable" "Disabled,Enabled"
textline " "
width 17.
group.long 0x74++0x0F
line.long 0x00 "TGITENST,MibSPI Transfer Group Interrupt Enable Set Register"
bitfld.long 0x00 31. " SETINTENRDY[15] ,TG interrupt set (enable) when transfer finished" "Disabled,Enabled"
bitfld.long 0x00 30. " [14] ,TG interrupt set (enable) when transfer finished" "Disabled,Enabled"
bitfld.long 0x00 29. " [13] ,TG interrupt set (enable) when transfer finished" "Disabled,Enabled"
textline " "
bitfld.long 0x00 28. " [12] ,TG interrupt set (enable) when transfer finished" "Disabled,Enabled"
bitfld.long 0x00 27. " [11] ,TG interrupt set (enable) when transfer finished" "Disabled,Enabled"
bitfld.long 0x00 26. " [10] ,TG interrupt set (enable) when transfer finished" "Disabled,Enabled"
textline " "
bitfld.long 0x00 25. " [9] ,TG interrupt set (enable) when transfer finished" "Disabled,Enabled"
bitfld.long 0x00 24. " [8] ,TG interrupt set (enable) when transfer finished" "Disabled,Enabled"
bitfld.long 0x00 23. " [7] ,TG interrupt set (enable) when transfer finished" "Disabled,Enabled"
textline " "
bitfld.long 0x00 22. " [6] ,TG interrupt set (enable) when transfer finished" "Disabled,Enabled"
bitfld.long 0x00 21. " [5] ,TG interrupt set (enable) when transfer finished" "Disabled,Enabled"
bitfld.long 0x00 20. " [4] ,TG interrupt set (enable) when transfer finished" "Disabled,Enabled"
textline " "
bitfld.long 0x00 19. " [3] ,TG interrupt set (enable) when transfer finished" "Disabled,Enabled"
bitfld.long 0x00 18. " [2] ,TG interrupt set (enable) when transfer finished" "Disabled,Enabled"
bitfld.long 0x00 17. " [1] ,TG interrupt set (enable) when transfer finished" "Disabled,Enabled"
textline " "
bitfld.long 0x00 16. " [0] ,TG interrupt set (enable) when transfer finished" "Disabled,Enabled"
textline " "
bitfld.long 0x00 15. " SETINTENSUS[15] ,TG interrupt set (enabled) when transfer suspended" "Disabled,Enabled"
bitfld.long 0x00 14. " [14] ,TG interrupt set (enabled) when transfer suspended" "Disabled,Enabled"
bitfld.long 0x00 13. " [13] ,TG interrupt set (enabled) when transfer suspended" "Disabled,Enabled"
textline " "
bitfld.long 0x00 12. " [12] ,TG interrupt set (enabled) when transfer suspended" "Disabled,Enabled"
bitfld.long 0x00 11. " [11] ,TG interrupt set (enabled) when transfer suspended" "Disabled,Enabled"
bitfld.long 0x00 10. " [10] ,TG interrupt set (enabled) when transfer suspended" "Disabled,Enabled"
textline " "
bitfld.long 0x00 9. " [9] ,TG interrupt set (enabled) when transfer suspended" "Disabled,Enabled"
bitfld.long 0x00 8. " [8] ,TG interrupt set (enabled) when transfer suspended" "Disabled,Enabled"
bitfld.long 0x00 7. " [7] ,TG interrupt set (enabled) when transfer suspended" "Disabled,Enabled"
textline " "
bitfld.long 0x00 6. " [6] ,TG interrupt set (enabled) when transfer suspended" "Disabled,Enabled"
bitfld.long 0x00 5. " [5] ,TG interrupt set (enabled) when transfer suspended" "Disabled,Enabled"
bitfld.long 0x00 4. " [4] ,TG interrupt set (enabled) when transfer suspended" "Disabled,Enabled"
textline " "
bitfld.long 0x00 3. " [3] ,TG interrupt set (enabled) when transfer suspended" "Disabled,Enabled"
bitfld.long 0x00 2. " [2] ,TG interrupt set (enabled) when transfer suspended" "Disabled,Enabled"
bitfld.long 0x00 1. " [1] ,TG interrupt set (enabled) when transfer suspended" "Disabled,Enabled"
textline " "
bitfld.long 0x00 0. " [0] ,TG interrupt set (enabled) when transfer suspended" "Disabled,Enabled"
line.long 0x04 "TGITENCR,MibSPI Transfer Group Interrupt Enable Clear Register"
bitfld.long 0x04 31. " CLRINTENRDY[15] ,TG interrupt clear (disabled) when transfer finished" "Disabled,Enabled"
bitfld.long 0x04 30. " [14] ,TG interrupt clear (disabled) when transfer finished" "Disabled,Enabled"
bitfld.long 0x04 29. " [13] ,TG interrupt clear (disabled) when transfer finished" "Disabled,Enabled"
textline " "
bitfld.long 0x04 28. " [12] ,TG interrupt clear (disabled) when transfer finished" "Disabled,Enabled"
bitfld.long 0x04 27. " [11] ,TG interrupt clear (disabled) when transfer finished" "Disabled,Enabled"
bitfld.long 0x04 26. " [10] ,TG interrupt clear (disabled) when transfer finished" "Disabled,Enabled"
textline " "
bitfld.long 0x04 25. " [9] ,TG interrupt clear (disabled) when transfer finished" "Disabled,Enabled"
bitfld.long 0x04 24. " [8] ,TG interrupt clear (disabled) when transfer finished" "Disabled,Enabled"
bitfld.long 0x04 23. " [7] ,TG interrupt clear (disabled) when transfer finished" "Disabled,Enabled"
textline " "
bitfld.long 0x04 22. " [6] ,TG interrupt clear (disabled) when transfer finished" "Disabled,Enabled"
bitfld.long 0x04 21. " [5] ,TG interrupt clear (disabled) when transfer finished" "Disabled,Enabled"
bitfld.long 0x04 20. " [4] ,TG interrupt clear (disabled) when transfer finished" "Disabled,Enabled"
textline " "
bitfld.long 0x04 19. " [3] ,TG interrupt clear (disabled) when transfer finished" "Disabled,Enabled"
bitfld.long 0x04 18. " [2] ,TG interrupt clear (disabled) when transfer finished" "Disabled,Enabled"
bitfld.long 0x04 17. " [1] ,TG interrupt clear (disabled) when transfer finished" "Disabled,Enabled"
textline " "
bitfld.long 0x04 16. " [0] ,TG interrupt clear (disabled) when transfer finished" "Disabled,Enabled"
textline " "
bitfld.long 0x04 15. " CLRINTENSUS[15] ,TG interrupt clear (disabled) when transfer suspended" "Disabled,Enabled"
bitfld.long 0x04 14. " [14] ,TG interrupt clear (disabled) when transfer suspended" "Disabled,Enabled"
bitfld.long 0x04 13. " [13] ,TG interrupt clear (disabled) when transfer suspended" "Disabled,Enabled"
textline " "
bitfld.long 0x04 12. " [12] ,TG interrupt clear (disabled) when transfer suspended" "Disabled,Enabled"
bitfld.long 0x04 11. " [11] ,TG interrupt clear (disabled) when transfer suspended" "Disabled,Enabled"
bitfld.long 0x04 10. " [10] ,TG interrupt clear (disabled) when transfer suspended" "Disabled,Enabled"
textline " "
bitfld.long 0x04 9. " [9] ,TG interrupt clear (disabled) when transfer suspended" "Disabled,Enabled"
bitfld.long 0x04 8. " [8] ,TG interrupt clear (disabled) when transfer suspended" "Disabled,Enabled"
bitfld.long 0x04 7. " [7] ,TG interrupt clear (disabled) when transfer suspended" "Disabled,Enabled"
textline " "
bitfld.long 0x04 6. " [6] ,TG interrupt clear (disabled) when transfer suspended" "Disabled,Enabled"
bitfld.long 0x04 5. " [5] ,TG interrupt clear (disabled) when transfer suspended" "Disabled,Enabled"
bitfld.long 0x04 4. " [4] ,TG interrupt clear (disabled) when transfer suspended" "Disabled,Enabled"
textline " "
bitfld.long 0x04 3. " [3] ,TG interrupt clear (disabled) when transfer suspended" "Disabled,Enabled"
bitfld.long 0x04 2. " [2] ,TG interrupt clear (disabled) when transfer suspended" "Disabled,Enabled"
bitfld.long 0x04 1. " [1] ,TG interrupt clear (disabled) when transfer suspended" "Disabled,Enabled"
textline " "
bitfld.long 0x04 0. " [0] ,TG interrupt clear (disabled) when transfer suspended" "Disabled,Enabled"
textline " "
line.long 0x08 "TGITLVST,MibSPI Transfer Group Interrupt Level Set Register"
bitfld.long 0x08 31. " SETINTLVLRDY[15] ,Transfer-group completed interrupt level set" "INT0,INT1"
bitfld.long 0x08 30. " [14] ,Transfer-group completed interrupt level set" "INT0,INT1"
bitfld.long 0x08 29. " [13] ,Transfer-group completed interrupt level set" "INT0,INT1"
bitfld.long 0x08 28. " [12] ,Transfer-group completed interrupt level set" "INT0,INT1"
bitfld.long 0x08 27. " [11] ,Transfer-group completed interrupt level set" "INT0,INT1"
bitfld.long 0x08 26. " [10] ,Transfer-group completed interrupt level set" "INT0,INT1"
textline " "
bitfld.long 0x08 25. " [9] ,Transfer-group completed interrupt level set" "INT0,INT1"
bitfld.long 0x08 24. " [8] ,Transfer-group completed interrupt level set" "INT0,INT1"
bitfld.long 0x08 23. " [7] ,Transfer-group completed interrupt level set" "INT0,INT1"
bitfld.long 0x08 22. " [6] ,Transfer-group completed interrupt level set" "INT0,INT1"
bitfld.long 0x08 21. " [5] ,Transfer-group completed interrupt level set" "INT0,INT1"
bitfld.long 0x08 20. " [4] ,Transfer-group completed interrupt level set" "INT0,INT1"
textline " "
bitfld.long 0x08 19. " [3] ,Transfer-group completed interrupt level set" "INT0,INT1"
bitfld.long 0x08 18. " [2] ,Transfer-group completed interrupt level set" "INT0,INT1"
bitfld.long 0x08 17. " [1] ,Transfer-group completed interrupt level set" "INT0,INT1"
bitfld.long 0x08 16. " [0] ,Transfer-group completed interrupt level set" "INT0,INT1"
textline " "
bitfld.long 0x08 15. " SETINTLVLSUS[15] ,Transfer-group suspended interrupt level set" "INT0,INT1"
bitfld.long 0x08 14. " [14] ,Transfer-group suspended interrupt level set" "INT0,INT1"
bitfld.long 0x08 13. " [13] ,Transfer-group suspended interrupt level set" "INT0,INT1"
bitfld.long 0x08 12. " [12] ,Transfer-group suspended interrupt level set" "INT0,INT1"
bitfld.long 0x08 11. " [11] ,Transfer-group suspended interrupt level set" "INT0,INT1"
bitfld.long 0x08 10. " [10] ,Transfer-group suspended interrupt level set" "INT0,INT1"
textline " "
bitfld.long 0x08 9. " [9] ,Transfer-group suspended interrupt level set" "INT0,INT1"
bitfld.long 0x08 8. " [8] ,Transfer-group suspended interrupt level set" "INT0,INT1"
bitfld.long 0x08 7. " [7] ,Transfer-group suspended interrupt level set" "INT0,INT1"
bitfld.long 0x08 6. " [6] ,Transfer-group suspended interrupt level set" "INT0,INT1"
bitfld.long 0x08 5. " [5] ,Transfer-group suspended interrupt level set" "INT0,INT1"
bitfld.long 0x08 4. " [4] ,Transfer-group suspended interrupt level set" "INT0,INT1"
textline " "
bitfld.long 0x08 3. " [3] ,Transfer-group suspended interrupt level set" "INT0,INT1"
bitfld.long 0x08 2. " [2] ,Transfer-group suspended interrupt level set" "INT0,INT1"
bitfld.long 0x08 1. " [1] ,Transfer-group suspended interrupt level set" "INT0,INT1"
bitfld.long 0x08 0. " [0] ,Transfer-group suspended interrupt level set" "INT0,INT1"
line.long 0x0C "TGITLVCR,MibSPI Transfer Group Interrupt Level Clear Register"
bitfld.long 0x0C 31. " CLRINTLVLRDY[15] ,Transfer-group completed interrupt level clear" "INT0,INT1"
bitfld.long 0x0C 30. " [14] ,Transfer-group completed interrupt level clear" "INT0,INT1"
bitfld.long 0x0C 29. " [13] ,Transfer-group completed interrupt level clear" "INT0,INT1"
bitfld.long 0x0C 28. " [12] ,Transfer-group completed interrupt level clear" "INT0,INT1"
bitfld.long 0x0C 27. " [11] ,Transfer-group completed interrupt level clear" "INT0,INT1"
bitfld.long 0x0C 26. " [10] ,Transfer-group completed interrupt level clear" "INT0,INT1"
textline " "
bitfld.long 0x0C 25. " [9] ,Transfer-group completed interrupt level clear" "INT0,INT1"
bitfld.long 0x0C 24. " [8] ,Transfer-group completed interrupt level clear" "INT0,INT1"
bitfld.long 0x0C 23. " [7] ,Transfer-group completed interrupt level clear" "INT0,INT1"
bitfld.long 0x0C 22. " [6] ,Transfer-group completed interrupt level clear" "INT0,INT1"
bitfld.long 0x0C 21. " [5] ,Transfer-group completed interrupt level clear" "INT0,INT1"
bitfld.long 0x0C 20. " [4] ,Transfer-group completed interrupt level clear" "INT0,INT1"
textline " "
bitfld.long 0x0C 19. " [3] ,Transfer-group completed interrupt level clear" "INT0,INT1"
bitfld.long 0x0C 18. " [2] ,Transfer-group completed interrupt level clear" "INT0,INT1"
bitfld.long 0x0C 17. " [1] ,Transfer-group completed interrupt level clear" "INT0,INT1"
bitfld.long 0x0C 16. " [0] ,Transfer-group completed interrupt level clear" "INT0,INT1"
textline " "
bitfld.long 0x0C 15. " CLRINTLVLSUS[15] ,Transfer group suspended interrupt level clear" "INT0,INT1"
bitfld.long 0x0C 14. " [14] ,Transfer group suspended interrupt level clear" "INT0,INT1"
bitfld.long 0x0C 13. " [13] ,Transfer group suspended interrupt level clear" "INT0,INT1"
bitfld.long 0x0C 12. " [12] ,Transfer group suspended interrupt level clear" "INT0,INT1"
bitfld.long 0x0C 11. " [11] ,Transfer group suspended interrupt level clear" "INT0,INT1"
bitfld.long 0x0C 10. " [10] ,Transfer group suspended interrupt level clear" "INT0,INT1"
textline " "
bitfld.long 0x0C 9. " [9] ,Transfer group suspended interrupt level clear" "INT0,INT1"
bitfld.long 0x0C 8. " [8] ,Transfer group suspended interrupt level clear" "INT0,INT1"
bitfld.long 0x0C 7. " [7] ,Transfer group suspended interrupt level clear" "INT0,INT1"
bitfld.long 0x0C 6. " [6] ,Transfer group suspended interrupt level clear" "INT0,INT1"
bitfld.long 0x0C 5. " [5] ,Transfer group suspended interrupt level clear" "INT0,INT1"
bitfld.long 0x0C 4. " [4] ,Transfer group suspended interrupt level clear" "INT0,INT1"
textline " "
bitfld.long 0x0C 3. " [3] ,Transfer group suspended interrupt level clear" "INT0,INT1"
bitfld.long 0x0C 2. " [2] ,Transfer group suspended interrupt level clear" "INT0,INT1"
bitfld.long 0x0C 1. " [1] ,Transfer group suspended interrupt level clear" "INT0,INT1"
bitfld.long 0x0C 0. " [0] ,Transfer group suspended interrupt level clear" "INT0,INT1"
textline " "
group.long 0x84++0x03
line.long 0x00 "TGITFLG,Transfer Group Interrupt Flag Register"
sif cpuis("TMS570LC4357")
bitfld.long 0x00 31. " INTFLGRDY[15] ,Transfer-group interrupt flag for a transfer-completed interrupt 15" "Disabled,Enabled"
bitfld.long 0x00 30. " [14] ,Transfer-group interrupt flag for a transfer-completed interrupt 14" "Disabled,Enabled"
bitfld.long 0x00 29. " [13] ,Transfer-group interrupt flag for a transfer-completed interrupt 13" "Disabled,Enabled"
bitfld.long 0x00 28. " [12] ,Transfer-group interrupt flag for a transfer-completed interrupt 12" "Disabled,Enabled"
textline " "
bitfld.long 0x00 27. " [11] ,Transfer-group interrupt flag for a transfer-completed interrupt 11" "Disabled,Enabled"
bitfld.long 0x00 26. " [10] ,Transfer-group interrupt flag for a transfer-completed interrupt 10" "Disabled,Enabled"
bitfld.long 0x00 25. " [9] ,Transfer-group interrupt flag for a transfer-completed interrupt 9" "Disabled,Enabled"
bitfld.long 0x00 24. " [8] ,Transfer-group interrupt flag for a transfer-completed interrupt 8" "Disabled,Enabled"
textline " "
bitfld.long 0x00 23. " [7] ,Transfer-group interrupt flag for a transfer-completed interrupt 7" "Disabled,Enabled"
bitfld.long 0x00 22. " [6] ,Transfer-group interrupt flag for a transfer-completed interrupt 6" "Disabled,Enabled"
bitfld.long 0x00 21. " [5] ,Transfer-group interrupt flag for a transfer-completed interrupt 5" "Disabled,Enabled"
bitfld.long 0x00 20. " [4] ,Transfer-group interrupt flag for a transfer-completed interrupt 4" "Disabled,Enabled"
textline " "
bitfld.long 0x00 19. " [3] ,Transfer-group interrupt flag for a transfer-completed interrupt 3" "Disabled,Enabled"
bitfld.long 0x00 18. " [2] ,Transfer-group interrupt flag for a transfer-completed interrupt 2" "Disabled,Enabled"
bitfld.long 0x00 17. " [1] ,Transfer-group interrupt flag for a transfer-completed interrupt 1" "Disabled,Enabled"
bitfld.long 0x00 16. " [0] ,Transfer-group interrupt flag for a transfer-completed interrupt 0" "Disabled,Enabled"
textline " "
endif
bitfld.long 0x00 15. " INTFLGSUS[15] ,Transfer-group interrupt flag for a transfer-suspend interrupt 15" "Disabled,Enabled"
bitfld.long 0x00 14. " [14] ,Transfer-group interrupt flag for a transfer-suspend interrupt 14" "Disabled,Enabled"
bitfld.long 0x00 13. " [13] ,Transfer-group interrupt flag for a transfer-suspend interrupt 13" "Disabled,Enabled"
bitfld.long 0x00 12. " [12] ,Transfer-group interrupt flag for a transfer-suspend interrupt 12" "Disabled,Enabled"
textline " "
bitfld.long 0x00 11. " [11] ,Transfer-group interrupt flag for a transfer-suspend interrupt 11" "Disabled,Enabled"
bitfld.long 0x00 10. " [10] ,Transfer-group interrupt flag for a transfer-suspend interrupt 10" "Disabled,Enabled"
bitfld.long 0x00 9. " [9] ,Transfer-group interrupt flag for a transfer-suspend interrupt 9" "Disabled,Enabled"
bitfld.long 0x00 8. " [8] ,Transfer-group interrupt flag for a transfer-suspend interrupt 8" "Disabled,Enabled"
textline " "
bitfld.long 0x00 7. " [7] ,Transfer-group interrupt flag for a transfer-suspend interrupt 7" "Disabled,Enabled"
bitfld.long 0x00 6. " [6] ,Transfer-group interrupt flag for a transfer-suspend interrupt 6" "Disabled,Enabled"
bitfld.long 0x00 5. " [5] ,Transfer-group interrupt flag for a transfer-suspend interrupt 5" "Disabled,Enabled"
bitfld.long 0x00 4. " [4] ,Transfer-group interrupt flag for a transfer-suspend interrupt 4" "Disabled,Enabled"
textline " "
bitfld.long 0x00 3. " [3] ,Transfer-group interrupt flag for a transfer-suspend interrupt 3" "Disabled,Enabled"
bitfld.long 0x00 2. " [2] ,Transfer-group interrupt flag for a transfer-suspend interrupt 2" "Disabled,Enabled"
bitfld.long 0x00 1. " [1] ,Transfer-group interrupt flag for a transfer-suspend interrupt 1" "Disabled,Enabled"
bitfld.long 0x00 0. " [0] ,Transfer-group interrupt flag for a transfer-suspend interrupt 0" "Disabled,Enabled"
textline " "
group.long 0x90++0x47
line.long 0x00 "TICKCNT,Tick Count Register"
bitfld.long 0x00 31. " TICKENA ,Tick counter enable" "Disabled,Enabled"
bitfld.long 0x00 30. " RELOAD ,Pre-load the tick counter" "No effect,Reload"
bitfld.long 0x00 28.--29. " CLKCTRL ,Tick counter clock source control" "0,1,2,3"
textline " "
hexmask.long.word 0x00 0.--15. 1. " TICKVALUE ,Initial value for the tick counter"
line.long 0x04 "LTGPEND,Last Transfer Group End Pointer Register"
rbitfld.long 0x04 24.--28. " TGINSERVICE ,The TG number currently being serviced by the sequencer" "No TG,TG0,TG1,TG2,TG3,TG4,TG5,TG6,TG7,TG8,TG9,TG10,TG11,TG12,TG13,TG14,TG15,?..."
hexmask.long.byte 0x04 8.--14. 1. " LPEND ,Last TG end pointer"
line.long 0x8 "TG1CTRL,MibSPI Transfer Group Control Register 1"
bitfld.long 0x8 31. " TGENA ,TG enable" "Disabled,Enabled"
bitfld.long 0x8 30. " ONESHOT ,Single transfer for TG" "Disabled,Enabled"
bitfld.long 0x8 29. " PRST ,TG pointer reset mode" "Disabled,Enabled"
textline " "
rbitfld.long 0x8 28. " TGTD ,TG triggered" "Not triggered,Triggered"
bitfld.long 0x8 20.--23. " TRGEVT ,Type of trigger event" "Never,Rising edge,Falling edge,Both edges,,High active,Low-active,Always,?..."
bitfld.long 0x8 16.--19. " TRIGSRC ,Trigger source" "Disabled,EXT[0],EXT[1],EXT[2],EXT[3],EXT[4],EXT[5],EXT[6],EXT[7],EXT[8],EXT[9,EXT[10,EXT[11,EXT[12,EXT[13],TICK"
textline " "
hexmask.long.byte 0x8 8.--14. 1. " PSTART ,TG start address"
hexmask.long.byte 0x8 0.--6. 1. " PCURRENT ,Pointer to current buffer"
line.long 0xC "TG2CTRL,MibSPI Transfer Group Control Register 2"
bitfld.long 0xC 31. " TGENA ,TG enable" "Disabled,Enabled"
bitfld.long 0xC 30. " ONESHOT ,Single transfer for TG" "Disabled,Enabled"
bitfld.long 0xC 29. " PRST ,TG pointer reset mode" "Disabled,Enabled"
textline " "
rbitfld.long 0xC 28. " TGTD ,TG triggered" "Not triggered,Triggered"
bitfld.long 0xC 20.--23. " TRGEVT ,Type of trigger event" "Never,Rising edge,Falling edge,Both edges,,High active,Low-active,Always,?..."
bitfld.long 0xC 16.--19. " TRIGSRC ,Trigger source" "Disabled,EXT[0],EXT[1],EXT[2],EXT[3],EXT[4],EXT[5],EXT[6],EXT[7],EXT[8],EXT[9,EXT[10,EXT[11,EXT[12,EXT[13],TICK"
textline " "
hexmask.long.byte 0xC 8.--14. 1. " PSTART ,TG start address"
hexmask.long.byte 0xC 0.--6. 1. " PCURRENT ,Pointer to current buffer"
line.long 0x10 "TG3CTRL,MibSPI Transfer Group Control Register 3"
bitfld.long 0x10 31. " TGENA ,TG enable" "Disabled,Enabled"
bitfld.long 0x10 30. " ONESHOT ,Single transfer for TG" "Disabled,Enabled"
bitfld.long 0x10 29. " PRST ,TG pointer reset mode" "Disabled,Enabled"
textline " "
rbitfld.long 0x10 28. " TGTD ,TG triggered" "Not triggered,Triggered"
bitfld.long 0x10 20.--23. " TRGEVT ,Type of trigger event" "Never,Rising edge,Falling edge,Both edges,,High active,Low-active,Always,?..."
bitfld.long 0x10 16.--19. " TRIGSRC ,Trigger source" "Disabled,EXT[0],EXT[1],EXT[2],EXT[3],EXT[4],EXT[5],EXT[6],EXT[7],EXT[8],EXT[9,EXT[10,EXT[11,EXT[12,EXT[13],TICK"
textline " "
hexmask.long.byte 0x10 8.--14. 1. " PSTART ,TG start address"
hexmask.long.byte 0x10 0.--6. 1. " PCURRENT ,Pointer to current buffer"
line.long 0x14 "TG4CTRL,MibSPI Transfer Group Control Register 4"
bitfld.long 0x14 31. " TGENA ,TG enable" "Disabled,Enabled"
bitfld.long 0x14 30. " ONESHOT ,Single transfer for TG" "Disabled,Enabled"
bitfld.long 0x14 29. " PRST ,TG pointer reset mode" "Disabled,Enabled"
textline " "
rbitfld.long 0x14 28. " TGTD ,TG triggered" "Not triggered,Triggered"
bitfld.long 0x14 20.--23. " TRGEVT ,Type of trigger event" "Never,Rising edge,Falling edge,Both edges,,High active,Low-active,Always,?..."
bitfld.long 0x14 16.--19. " TRIGSRC ,Trigger source" "Disabled,EXT[0],EXT[1],EXT[2],EXT[3],EXT[4],EXT[5],EXT[6],EXT[7],EXT[8],EXT[9,EXT[10,EXT[11,EXT[12,EXT[13],TICK"
textline " "
hexmask.long.byte 0x14 8.--14. 1. " PSTART ,TG start address"
hexmask.long.byte 0x14 0.--6. 1. " PCURRENT ,Pointer to current buffer"
line.long 0x18 "TG5CTRL,MibSPI Transfer Group Control Register 5"
bitfld.long 0x18 31. " TGENA ,TG enable" "Disabled,Enabled"
bitfld.long 0x18 30. " ONESHOT ,Single transfer for TG" "Disabled,Enabled"
bitfld.long 0x18 29. " PRST ,TG pointer reset mode" "Disabled,Enabled"
textline " "
rbitfld.long 0x18 28. " TGTD ,TG triggered" "Not triggered,Triggered"
bitfld.long 0x18 20.--23. " TRGEVT ,Type of trigger event" "Never,Rising edge,Falling edge,Both edges,,High active,Low-active,Always,?..."
bitfld.long 0x18 16.--19. " TRIGSRC ,Trigger source" "Disabled,EXT[0],EXT[1],EXT[2],EXT[3],EXT[4],EXT[5],EXT[6],EXT[7],EXT[8],EXT[9,EXT[10,EXT[11,EXT[12,EXT[13],TICK"
textline " "
hexmask.long.byte 0x18 8.--14. 1. " PSTART ,TG start address"
hexmask.long.byte 0x18 0.--6. 1. " PCURRENT ,Pointer to current buffer"
line.long 0x1C "TG6CTRL,MibSPI Transfer Group Control Register 6"
bitfld.long 0x1C 31. " TGENA ,TG enable" "Disabled,Enabled"
bitfld.long 0x1C 30. " ONESHOT ,Single transfer for TG" "Disabled,Enabled"
bitfld.long 0x1C 29. " PRST ,TG pointer reset mode" "Disabled,Enabled"
textline " "
rbitfld.long 0x1C 28. " TGTD ,TG triggered" "Not triggered,Triggered"
bitfld.long 0x1C 20.--23. " TRGEVT ,Type of trigger event" "Never,Rising edge,Falling edge,Both edges,,High active,Low-active,Always,?..."
bitfld.long 0x1C 16.--19. " TRIGSRC ,Trigger source" "Disabled,EXT[0],EXT[1],EXT[2],EXT[3],EXT[4],EXT[5],EXT[6],EXT[7],EXT[8],EXT[9,EXT[10,EXT[11,EXT[12,EXT[13],TICK"
textline " "
hexmask.long.byte 0x1C 8.--14. 1. " PSTART ,TG start address"
hexmask.long.byte 0x1C 0.--6. 1. " PCURRENT ,Pointer to current buffer"
line.long 0x20 "TG7CTRL,MibSPI Transfer Group Control Register 7"
bitfld.long 0x20 31. " TGENA ,TG enable" "Disabled,Enabled"
bitfld.long 0x20 30. " ONESHOT ,Single transfer for TG" "Disabled,Enabled"
bitfld.long 0x20 29. " PRST ,TG pointer reset mode" "Disabled,Enabled"
textline " "
rbitfld.long 0x20 28. " TGTD ,TG triggered" "Not triggered,Triggered"
bitfld.long 0x20 20.--23. " TRGEVT ,Type of trigger event" "Never,Rising edge,Falling edge,Both edges,,High active,Low-active,Always,?..."
bitfld.long 0x20 16.--19. " TRIGSRC ,Trigger source" "Disabled,EXT[0],EXT[1],EXT[2],EXT[3],EXT[4],EXT[5],EXT[6],EXT[7],EXT[8],EXT[9,EXT[10,EXT[11,EXT[12,EXT[13],TICK"
textline " "
hexmask.long.byte 0x20 8.--14. 1. " PSTART ,TG start address"
hexmask.long.byte 0x20 0.--6. 1. " PCURRENT ,Pointer to current buffer"
line.long 0x24 "TG8CTRL,MibSPI Transfer Group Control Register 8"
bitfld.long 0x24 31. " TGENA ,TG enable" "Disabled,Enabled"
bitfld.long 0x24 30. " ONESHOT ,Single transfer for TG" "Disabled,Enabled"
bitfld.long 0x24 29. " PRST ,TG pointer reset mode" "Disabled,Enabled"
textline " "
rbitfld.long 0x24 28. " TGTD ,TG triggered" "Not triggered,Triggered"
bitfld.long 0x24 20.--23. " TRGEVT ,Type of trigger event" "Never,Rising edge,Falling edge,Both edges,,High active,Low-active,Always,?..."
bitfld.long 0x24 16.--19. " TRIGSRC ,Trigger source" "Disabled,EXT[0],EXT[1],EXT[2],EXT[3],EXT[4],EXT[5],EXT[6],EXT[7],EXT[8],EXT[9,EXT[10,EXT[11,EXT[12,EXT[13],TICK"
textline " "
hexmask.long.byte 0x24 8.--14. 1. " PSTART ,TG start address"
hexmask.long.byte 0x24 0.--6. 1. " PCURRENT ,Pointer to current buffer"
line.long 0x28 "TG9CTRL,MibSPI Transfer Group Control Register 9"
bitfld.long 0x28 31. " TGENA ,TG enable" "Disabled,Enabled"
bitfld.long 0x28 30. " ONESHOT ,Single transfer for TG" "Disabled,Enabled"
bitfld.long 0x28 29. " PRST ,TG pointer reset mode" "Disabled,Enabled"
textline " "
rbitfld.long 0x28 28. " TGTD ,TG triggered" "Not triggered,Triggered"
bitfld.long 0x28 20.--23. " TRGEVT ,Type of trigger event" "Never,Rising edge,Falling edge,Both edges,,High active,Low-active,Always,?..."
bitfld.long 0x28 16.--19. " TRIGSRC ,Trigger source" "Disabled,EXT[0],EXT[1],EXT[2],EXT[3],EXT[4],EXT[5],EXT[6],EXT[7],EXT[8],EXT[9,EXT[10,EXT[11,EXT[12,EXT[13],TICK"
textline " "
hexmask.long.byte 0x28 8.--14. 1. " PSTART ,TG start address"
hexmask.long.byte 0x28 0.--6. 1. " PCURRENT ,Pointer to current buffer"
line.long 0x2C "TG10CTRL,MibSPI Transfer Group Control Register 10"
bitfld.long 0x2C 31. " TGENA ,TG enable" "Disabled,Enabled"
bitfld.long 0x2C 30. " ONESHOT ,Single transfer for TG" "Disabled,Enabled"
bitfld.long 0x2C 29. " PRST ,TG pointer reset mode" "Disabled,Enabled"
textline " "
rbitfld.long 0x2C 28. " TGTD ,TG triggered" "Not triggered,Triggered"
bitfld.long 0x2C 20.--23. " TRGEVT ,Type of trigger event" "Never,Rising edge,Falling edge,Both edges,,High active,Low-active,Always,?..."
bitfld.long 0x2C 16.--19. " TRIGSRC ,Trigger source" "Disabled,EXT[0],EXT[1],EXT[2],EXT[3],EXT[4],EXT[5],EXT[6],EXT[7],EXT[8],EXT[9,EXT[10,EXT[11,EXT[12,EXT[13],TICK"
textline " "
hexmask.long.byte 0x2C 8.--14. 1. " PSTART ,TG start address"
hexmask.long.byte 0x2C 0.--6. 1. " PCURRENT ,Pointer to current buffer"
line.long 0x30 "TG11CTRL,MibSPI Transfer Group Control Register 11"
bitfld.long 0x30 31. " TGENA ,TG enable" "Disabled,Enabled"
bitfld.long 0x30 30. " ONESHOT ,Single transfer for TG" "Disabled,Enabled"
bitfld.long 0x30 29. " PRST ,TG pointer reset mode" "Disabled,Enabled"
textline " "
rbitfld.long 0x30 28. " TGTD ,TG triggered" "Not triggered,Triggered"
bitfld.long 0x30 20.--23. " TRGEVT ,Type of trigger event" "Never,Rising edge,Falling edge,Both edges,,High active,Low-active,Always,?..."
bitfld.long 0x30 16.--19. " TRIGSRC ,Trigger source" "Disabled,EXT[0],EXT[1],EXT[2],EXT[3],EXT[4],EXT[5],EXT[6],EXT[7],EXT[8],EXT[9,EXT[10,EXT[11,EXT[12,EXT[13],TICK"
textline " "
hexmask.long.byte 0x30 8.--14. 1. " PSTART ,TG start address"
hexmask.long.byte 0x30 0.--6. 1. " PCURRENT ,Pointer to current buffer"
line.long 0x34 "TG12CTRL,MibSPI Transfer Group Control Register 12"
bitfld.long 0x34 31. " TGENA ,TG enable" "Disabled,Enabled"
bitfld.long 0x34 30. " ONESHOT ,Single transfer for TG" "Disabled,Enabled"
bitfld.long 0x34 29. " PRST ,TG pointer reset mode" "Disabled,Enabled"
textline " "
rbitfld.long 0x34 28. " TGTD ,TG triggered" "Not triggered,Triggered"
bitfld.long 0x34 20.--23. " TRGEVT ,Type of trigger event" "Never,Rising edge,Falling edge,Both edges,,High active,Low-active,Always,?..."
bitfld.long 0x34 16.--19. " TRIGSRC ,Trigger source" "Disabled,EXT[0],EXT[1],EXT[2],EXT[3],EXT[4],EXT[5],EXT[6],EXT[7],EXT[8],EXT[9,EXT[10,EXT[11,EXT[12,EXT[13],TICK"
textline " "
hexmask.long.byte 0x34 8.--14. 1. " PSTART ,TG start address"
hexmask.long.byte 0x34 0.--6. 1. " PCURRENT ,Pointer to current buffer"
line.long 0x38 "TG13CTRL,MibSPI Transfer Group Control Register 13"
bitfld.long 0x38 31. " TGENA ,TG enable" "Disabled,Enabled"
bitfld.long 0x38 30. " ONESHOT ,Single transfer for TG" "Disabled,Enabled"
bitfld.long 0x38 29. " PRST ,TG pointer reset mode" "Disabled,Enabled"
textline " "
rbitfld.long 0x38 28. " TGTD ,TG triggered" "Not triggered,Triggered"
bitfld.long 0x38 20.--23. " TRGEVT ,Type of trigger event" "Never,Rising edge,Falling edge,Both edges,,High active,Low-active,Always,?..."
bitfld.long 0x38 16.--19. " TRIGSRC ,Trigger source" "Disabled,EXT[0],EXT[1],EXT[2],EXT[3],EXT[4],EXT[5],EXT[6],EXT[7],EXT[8],EXT[9,EXT[10,EXT[11,EXT[12,EXT[13],TICK"
textline " "
hexmask.long.byte 0x38 8.--14. 1. " PSTART ,TG start address"
hexmask.long.byte 0x38 0.--6. 1. " PCURRENT ,Pointer to current buffer"
line.long 0x3C "TG14CTRL,MibSPI Transfer Group Control Register 14"
bitfld.long 0x3C 31. " TGENA ,TG enable" "Disabled,Enabled"
bitfld.long 0x3C 30. " ONESHOT ,Single transfer for TG" "Disabled,Enabled"
bitfld.long 0x3C 29. " PRST ,TG pointer reset mode" "Disabled,Enabled"
textline " "
rbitfld.long 0x3C 28. " TGTD ,TG triggered" "Not triggered,Triggered"
bitfld.long 0x3C 20.--23. " TRGEVT ,Type of trigger event" "Never,Rising edge,Falling edge,Both edges,,High active,Low-active,Always,?..."
bitfld.long 0x3C 16.--19. " TRIGSRC ,Trigger source" "Disabled,EXT[0],EXT[1],EXT[2],EXT[3],EXT[4],EXT[5],EXT[6],EXT[7],EXT[8],EXT[9,EXT[10,EXT[11,EXT[12,EXT[13],TICK"
textline " "
hexmask.long.byte 0x3C 8.--14. 1. " PSTART ,TG start address"
hexmask.long.byte 0x3C 0.--6. 1. " PCURRENT ,Pointer to current buffer"
line.long 0x40 "TG15CTRL,MibSPI Transfer Group Control Register 15"
bitfld.long 0x40 31. " TGENA ,TG enable" "Disabled,Enabled"
bitfld.long 0x40 30. " ONESHOT ,Single transfer for TG" "Disabled,Enabled"
bitfld.long 0x40 29. " PRST ,TG pointer reset mode" "Disabled,Enabled"
textline " "
rbitfld.long 0x40 28. " TGTD ,TG triggered" "Not triggered,Triggered"
bitfld.long 0x40 20.--23. " TRGEVT ,Type of trigger event" "Never,Rising edge,Falling edge,Both edges,,High active,Low-active,Always,?..."
bitfld.long 0x40 16.--19. " TRIGSRC ,Trigger source" "Disabled,EXT[0],EXT[1],EXT[2],EXT[3],EXT[4],EXT[5],EXT[6],EXT[7],EXT[8],EXT[9,EXT[10,EXT[11,EXT[12,EXT[13],TICK"
textline " "
hexmask.long.byte 0x40 8.--14. 1. " PSTART ,TG start address"
hexmask.long.byte 0x40 0.--6. 1. " PCURRENT ,Pointer to current buffer"
line.long 0x44 "TG16CTRL,MibSPI Transfer Group Control Register 16"
bitfld.long 0x44 31. " TGENA ,TG enable" "Disabled,Enabled"
bitfld.long 0x44 30. " ONESHOT ,Single transfer for TG" "Disabled,Enabled"
bitfld.long 0x44 29. " PRST ,TG pointer reset mode" "Disabled,Enabled"
textline " "
rbitfld.long 0x44 28. " TGTD ,TG triggered" "Not triggered,Triggered"
bitfld.long 0x44 20.--23. " TRGEVT ,Type of trigger event" "Never,Rising edge,Falling edge,Both edges,,High active,Low-active,Always,?..."
bitfld.long 0x44 16.--19. " TRIGSRC ,Trigger source" "Disabled,EXT[0],EXT[1],EXT[2],EXT[3],EXT[4],EXT[5],EXT[6],EXT[7],EXT[8],EXT[9,EXT[10,EXT[11,EXT[12,EXT[13],TICK"
textline " "
hexmask.long.byte 0x44 8.--14. 1. " PSTART ,TG start address"
hexmask.long.byte 0x44 0.--6. 1. " PCURRENT ,Pointer to current buffer"
if (((d.l(ad:0xFFF7FA00+0x4))&0x3)==0x0)
group.long 0xD8++0x1F
line.long 0x0 "DMA1CTRL,MibSPI DMA Channel Control Register 1"
bitfld.long 0x0 31. " ONESHOT ,Auto-disable of DMA channel after ICOUNT+1 transfers" "0,1"
hexmask.long.byte 0x0 24.--30. 1. " BUFID ,Buffer utilized for DMA transfer"
bitfld.long 0x0 20.--23. " RXDMA_MAP ,Each MibSPI DMA channel can be linked to two physical DMA" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x0 16.--19. " TXDMA_MAP ,Each MibSPI DMA channel can be linked to two physical DMA" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x0 15. " RXDMAENA ,Receive data DMA channel enable" "Disabled,Enabled"
bitfld.long 0x0 14. " TXDMAENA ,Transmit data DMA channel enable" "Disabled,Enabled"
textline " "
bitfld.long 0x0 8.--12. " ICOUNT ,Initial count of DMA transfers" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32"
rbitfld.long 0x0 6. " COUNTBIT17 ,17th bit of the COUNT field of DMAxCOUNT register" "0,1"
rbitfld.long 0x0 0.--5. " COUNT ,Actual number of remaining DMA transfers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x4 "DMA2CTRL,MibSPI DMA Channel Control Register 1"
bitfld.long 0x4 31. " ONESHOT ,Auto-disable of DMA channel after ICOUNT+1 transfers" "0,1"
hexmask.long.byte 0x4 24.--30. 1. " BUFID ,Buffer utilized for DMA transfer"
bitfld.long 0x4 20.--23. " RXDMA_MAP ,Each MibSPI DMA channel can be linked to two physical DMA" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x4 16.--19. " TXDMA_MAP ,Each MibSPI DMA channel can be linked to two physical DMA" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x4 15. " RXDMAENA ,Receive data DMA channel enable" "Disabled,Enabled"
bitfld.long 0x4 14. " TXDMAENA ,Transmit data DMA channel enable" "Disabled,Enabled"
textline " "
bitfld.long 0x4 8.--12. " ICOUNT ,Initial count of DMA transfers" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32"
rbitfld.long 0x4 6. " COUNTBIT17 ,17th bit of the COUNT field of DMAxCOUNT register" "0,1"
rbitfld.long 0x4 0.--5. " COUNT ,Actual number of remaining DMA transfers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x8 "DMA3CTRL,MibSPI DMA Channel Control Register 1"
bitfld.long 0x8 31. " ONESHOT ,Auto-disable of DMA channel after ICOUNT+1 transfers" "0,1"
hexmask.long.byte 0x8 24.--30. 1. " BUFID ,Buffer utilized for DMA transfer"
bitfld.long 0x8 20.--23. " RXDMA_MAP ,Each MibSPI DMA channel can be linked to two physical DMA" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x8 16.--19. " TXDMA_MAP ,Each MibSPI DMA channel can be linked to two physical DMA" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x8 15. " RXDMAENA ,Receive data DMA channel enable" "Disabled,Enabled"
bitfld.long 0x8 14. " TXDMAENA ,Transmit data DMA channel enable" "Disabled,Enabled"
textline " "
bitfld.long 0x8 8.--12. " ICOUNT ,Initial count of DMA transfers" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32"
rbitfld.long 0x8 6. " COUNTBIT17 ,17th bit of the COUNT field of DMAxCOUNT register" "0,1"
rbitfld.long 0x8 0.--5. " COUNT ,Actual number of remaining DMA transfers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0xC "DMA4CTRL,MibSPI DMA Channel Control Register 1"
bitfld.long 0xC 31. " ONESHOT ,Auto-disable of DMA channel after ICOUNT+1 transfers" "0,1"
hexmask.long.byte 0xC 24.--30. 1. " BUFID ,Buffer utilized for DMA transfer"
bitfld.long 0xC 20.--23. " RXDMA_MAP ,Each MibSPI DMA channel can be linked to two physical DMA" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0xC 16.--19. " TXDMA_MAP ,Each MibSPI DMA channel can be linked to two physical DMA" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0xC 15. " RXDMAENA ,Receive data DMA channel enable" "Disabled,Enabled"
bitfld.long 0xC 14. " TXDMAENA ,Transmit data DMA channel enable" "Disabled,Enabled"
textline " "
bitfld.long 0xC 8.--12. " ICOUNT ,Initial count of DMA transfers" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32"
rbitfld.long 0xC 6. " COUNTBIT17 ,17th bit of the COUNT field of DMAxCOUNT register" "0,1"
rbitfld.long 0xC 0.--5. " COUNT ,Actual number of remaining DMA transfers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x10 "DMA5CTRL,MibSPI DMA Channel Control Register 1"
bitfld.long 0x10 31. " ONESHOT ,Auto-disable of DMA channel after ICOUNT+1 transfers" "0,1"
hexmask.long.byte 0x10 24.--30. 1. " BUFID ,Buffer utilized for DMA transfer"
bitfld.long 0x10 20.--23. " RXDMA_MAP ,Each MibSPI DMA channel can be linked to two physical DMA" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x10 16.--19. " TXDMA_MAP ,Each MibSPI DMA channel can be linked to two physical DMA" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x10 15. " RXDMAENA ,Receive data DMA channel enable" "Disabled,Enabled"
bitfld.long 0x10 14. " TXDMAENA ,Transmit data DMA channel enable" "Disabled,Enabled"
textline " "
bitfld.long 0x10 8.--12. " ICOUNT ,Initial count of DMA transfers" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32"
rbitfld.long 0x10 6. " COUNTBIT17 ,17th bit of the COUNT field of DMAxCOUNT register" "0,1"
rbitfld.long 0x10 0.--5. " COUNT ,Actual number of remaining DMA transfers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x14 "DMA6CTRL,MibSPI DMA Channel Control Register 1"
bitfld.long 0x14 31. " ONESHOT ,Auto-disable of DMA channel after ICOUNT+1 transfers" "0,1"
hexmask.long.byte 0x14 24.--30. 1. " BUFID ,Buffer utilized for DMA transfer"
bitfld.long 0x14 20.--23. " RXDMA_MAP ,Each MibSPI DMA channel can be linked to two physical DMA" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x14 16.--19. " TXDMA_MAP ,Each MibSPI DMA channel can be linked to two physical DMA" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x14 15. " RXDMAENA ,Receive data DMA channel enable" "Disabled,Enabled"
bitfld.long 0x14 14. " TXDMAENA ,Transmit data DMA channel enable" "Disabled,Enabled"
textline " "
bitfld.long 0x14 8.--12. " ICOUNT ,Initial count of DMA transfers" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32"
rbitfld.long 0x14 6. " COUNTBIT17 ,17th bit of the COUNT field of DMAxCOUNT register" "0,1"
rbitfld.long 0x14 0.--5. " COUNT ,Actual number of remaining DMA transfers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x18 "DMA7CTRL,MibSPI DMA Channel Control Register 1"
bitfld.long 0x18 31. " ONESHOT ,Auto-disable of DMA channel after ICOUNT+1 transfers" "0,1"
hexmask.long.byte 0x18 24.--30. 1. " BUFID ,Buffer utilized for DMA transfer"
bitfld.long 0x18 20.--23. " RXDMA_MAP ,Each MibSPI DMA channel can be linked to two physical DMA" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x18 16.--19. " TXDMA_MAP ,Each MibSPI DMA channel can be linked to two physical DMA" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x18 15. " RXDMAENA ,Receive data DMA channel enable" "Disabled,Enabled"
bitfld.long 0x18 14. " TXDMAENA ,Transmit data DMA channel enable" "Disabled,Enabled"
textline " "
bitfld.long 0x18 8.--12. " ICOUNT ,Initial count of DMA transfers" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32"
rbitfld.long 0x18 6. " COUNTBIT17 ,17th bit of the COUNT field of DMAxCOUNT register" "0,1"
rbitfld.long 0x18 0.--5. " COUNT ,Actual number of remaining DMA transfers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x1C "DMA8CTRL,MibSPI DMA Channel Control Register 1"
bitfld.long 0x1C 31. " ONESHOT ,Auto-disable of DMA channel after ICOUNT+1 transfers" "0,1"
hexmask.long.byte 0x1C 24.--30. 1. " BUFID ,Buffer utilized for DMA transfer"
bitfld.long 0x1C 20.--23. " RXDMA_MAP ,Each MibSPI DMA channel can be linked to two physical DMA" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x1C 16.--19. " TXDMA_MAP ,Each MibSPI DMA channel can be linked to two physical DMA" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x1C 15. " RXDMAENA ,Receive data DMA channel enable" "Disabled,Enabled"
bitfld.long 0x1C 14. " TXDMAENA ,Transmit data DMA channel enable" "Disabled,Enabled"
textline " "
bitfld.long 0x1C 8.--12. " ICOUNT ,Initial count of DMA transfers" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32"
rbitfld.long 0x1C 6. " COUNTBIT17 ,17th bit of the COUNT field of DMAxCOUNT register" "0,1"
rbitfld.long 0x1C 0.--5. " COUNT ,Actual number of remaining DMA transfers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
else
group.long 0xD8++0x1F
line.long 0x0 "DMA1CTRL,MibSPI DMA Channel Control Register 1"
bitfld.long 0x0 31. " ONESHOT ,Auto-disable of DMA channel after ICOUNT+1 transfers" "0,1"
hexmask.long.byte 0x0 24.--30. 1. " BUFID ,Buffer utilized for DMA transfer"
bitfld.long 0x0 20.--23. " RXDMA_MAP ,Each MibSPI DMA channel can be linked to two physical DMA" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x0 16.--19. " TXDMA_MAP ,Each MibSPI DMA channel can be linked to two physical DMA" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x0 15. " RXDMAENA ,Receive data DMA channel enable" "Disabled,Enabled"
bitfld.long 0x0 14. " TXDMAENA ,Transmit data DMA channel enable" "Disabled,Enabled"
textline " "
bitfld.long 0x0 13. " NOBRK ,Non-interleaved DMA block transfer" "Not performed,Performed"
bitfld.long 0x0 8.--12. " ICOUNT ,Initial count of DMA transfers" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32"
rbitfld.long 0x0 6. " COUNTBIT17 ,17th bit of the COUNT field of DMAxCOUNT register" "0,1"
textline " "
rbitfld.long 0x0 0.--5. " COUNT ,Actual number of remaining DMA transfers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x4 "DMA2CTRL,MibSPI DMA Channel Control Register 1"
bitfld.long 0x4 31. " ONESHOT ,Auto-disable of DMA channel after ICOUNT+1 transfers" "0,1"
hexmask.long.byte 0x4 24.--30. 1. " BUFID ,Buffer utilized for DMA transfer"
bitfld.long 0x4 20.--23. " RXDMA_MAP ,Each MibSPI DMA channel can be linked to two physical DMA" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x4 16.--19. " TXDMA_MAP ,Each MibSPI DMA channel can be linked to two physical DMA" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x4 15. " RXDMAENA ,Receive data DMA channel enable" "Disabled,Enabled"
bitfld.long 0x4 14. " TXDMAENA ,Transmit data DMA channel enable" "Disabled,Enabled"
textline " "
bitfld.long 0x4 13. " NOBRK ,Non-interleaved DMA block transfer" "Not performed,Performed"
bitfld.long 0x4 8.--12. " ICOUNT ,Initial count of DMA transfers" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32"
rbitfld.long 0x4 6. " COUNTBIT17 ,17th bit of the COUNT field of DMAxCOUNT register" "0,1"
textline " "
rbitfld.long 0x4 0.--5. " COUNT ,Actual number of remaining DMA transfers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x8 "DMA3CTRL,MibSPI DMA Channel Control Register 1"
bitfld.long 0x8 31. " ONESHOT ,Auto-disable of DMA channel after ICOUNT+1 transfers" "0,1"
hexmask.long.byte 0x8 24.--30. 1. " BUFID ,Buffer utilized for DMA transfer"
bitfld.long 0x8 20.--23. " RXDMA_MAP ,Each MibSPI DMA channel can be linked to two physical DMA" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x8 16.--19. " TXDMA_MAP ,Each MibSPI DMA channel can be linked to two physical DMA" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x8 15. " RXDMAENA ,Receive data DMA channel enable" "Disabled,Enabled"
bitfld.long 0x8 14. " TXDMAENA ,Transmit data DMA channel enable" "Disabled,Enabled"
textline " "
bitfld.long 0x8 13. " NOBRK ,Non-interleaved DMA block transfer" "Not performed,Performed"
bitfld.long 0x8 8.--12. " ICOUNT ,Initial count of DMA transfers" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32"
rbitfld.long 0x8 6. " COUNTBIT17 ,17th bit of the COUNT field of DMAxCOUNT register" "0,1"
textline " "
rbitfld.long 0x8 0.--5. " COUNT ,Actual number of remaining DMA transfers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0xC "DMA4CTRL,MibSPI DMA Channel Control Register 1"
bitfld.long 0xC 31. " ONESHOT ,Auto-disable of DMA channel after ICOUNT+1 transfers" "0,1"
hexmask.long.byte 0xC 24.--30. 1. " BUFID ,Buffer utilized for DMA transfer"
bitfld.long 0xC 20.--23. " RXDMA_MAP ,Each MibSPI DMA channel can be linked to two physical DMA" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0xC 16.--19. " TXDMA_MAP ,Each MibSPI DMA channel can be linked to two physical DMA" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0xC 15. " RXDMAENA ,Receive data DMA channel enable" "Disabled,Enabled"
bitfld.long 0xC 14. " TXDMAENA ,Transmit data DMA channel enable" "Disabled,Enabled"
textline " "
bitfld.long 0xC 13. " NOBRK ,Non-interleaved DMA block transfer" "Not performed,Performed"
bitfld.long 0xC 8.--12. " ICOUNT ,Initial count of DMA transfers" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32"
rbitfld.long 0xC 6. " COUNTBIT17 ,17th bit of the COUNT field of DMAxCOUNT register" "0,1"
textline " "
rbitfld.long 0xC 0.--5. " COUNT ,Actual number of remaining DMA transfers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x10 "DMA5CTRL,MibSPI DMA Channel Control Register 1"
bitfld.long 0x10 31. " ONESHOT ,Auto-disable of DMA channel after ICOUNT+1 transfers" "0,1"
hexmask.long.byte 0x10 24.--30. 1. " BUFID ,Buffer utilized for DMA transfer"
bitfld.long 0x10 20.--23. " RXDMA_MAP ,Each MibSPI DMA channel can be linked to two physical DMA" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x10 16.--19. " TXDMA_MAP ,Each MibSPI DMA channel can be linked to two physical DMA" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x10 15. " RXDMAENA ,Receive data DMA channel enable" "Disabled,Enabled"
bitfld.long 0x10 14. " TXDMAENA ,Transmit data DMA channel enable" "Disabled,Enabled"
textline " "
bitfld.long 0x10 13. " NOBRK ,Non-interleaved DMA block transfer" "Not performed,Performed"
bitfld.long 0x10 8.--12. " ICOUNT ,Initial count of DMA transfers" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32"
rbitfld.long 0x10 6. " COUNTBIT17 ,17th bit of the COUNT field of DMAxCOUNT register" "0,1"
textline " "
rbitfld.long 0x10 0.--5. " COUNT ,Actual number of remaining DMA transfers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x14 "DMA6CTRL,MibSPI DMA Channel Control Register 1"
bitfld.long 0x14 31. " ONESHOT ,Auto-disable of DMA channel after ICOUNT+1 transfers" "0,1"
hexmask.long.byte 0x14 24.--30. 1. " BUFID ,Buffer utilized for DMA transfer"
bitfld.long 0x14 20.--23. " RXDMA_MAP ,Each MibSPI DMA channel can be linked to two physical DMA" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x14 16.--19. " TXDMA_MAP ,Each MibSPI DMA channel can be linked to two physical DMA" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x14 15. " RXDMAENA ,Receive data DMA channel enable" "Disabled,Enabled"
bitfld.long 0x14 14. " TXDMAENA ,Transmit data DMA channel enable" "Disabled,Enabled"
textline " "
bitfld.long 0x14 13. " NOBRK ,Non-interleaved DMA block transfer" "Not performed,Performed"
bitfld.long 0x14 8.--12. " ICOUNT ,Initial count of DMA transfers" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32"
rbitfld.long 0x14 6. " COUNTBIT17 ,17th bit of the COUNT field of DMAxCOUNT register" "0,1"
textline " "
rbitfld.long 0x14 0.--5. " COUNT ,Actual number of remaining DMA transfers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x18 "DMA7CTRL,MibSPI DMA Channel Control Register 1"
bitfld.long 0x18 31. " ONESHOT ,Auto-disable of DMA channel after ICOUNT+1 transfers" "0,1"
hexmask.long.byte 0x18 24.--30. 1. " BUFID ,Buffer utilized for DMA transfer"
bitfld.long 0x18 20.--23. " RXDMA_MAP ,Each MibSPI DMA channel can be linked to two physical DMA" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x18 16.--19. " TXDMA_MAP ,Each MibSPI DMA channel can be linked to two physical DMA" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x18 15. " RXDMAENA ,Receive data DMA channel enable" "Disabled,Enabled"
bitfld.long 0x18 14. " TXDMAENA ,Transmit data DMA channel enable" "Disabled,Enabled"
textline " "
bitfld.long 0x18 13. " NOBRK ,Non-interleaved DMA block transfer" "Not performed,Performed"
bitfld.long 0x18 8.--12. " ICOUNT ,Initial count of DMA transfers" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32"
rbitfld.long 0x18 6. " COUNTBIT17 ,17th bit of the COUNT field of DMAxCOUNT register" "0,1"
textline " "
rbitfld.long 0x18 0.--5. " COUNT ,Actual number of remaining DMA transfers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x1C "DMA8CTRL,MibSPI DMA Channel Control Register 1"
bitfld.long 0x1C 31. " ONESHOT ,Auto-disable of DMA channel after ICOUNT+1 transfers" "0,1"
hexmask.long.byte 0x1C 24.--30. 1. " BUFID ,Buffer utilized for DMA transfer"
bitfld.long 0x1C 20.--23. " RXDMA_MAP ,Each MibSPI DMA channel can be linked to two physical DMA" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x1C 16.--19. " TXDMA_MAP ,Each MibSPI DMA channel can be linked to two physical DMA" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x1C 15. " RXDMAENA ,Receive data DMA channel enable" "Disabled,Enabled"
bitfld.long 0x1C 14. " TXDMAENA ,Transmit data DMA channel enable" "Disabled,Enabled"
textline " "
bitfld.long 0x1C 13. " NOBRK ,Non-interleaved DMA block transfer" "Not performed,Performed"
bitfld.long 0x1C 8.--12. " ICOUNT ,Initial count of DMA transfers" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32"
rbitfld.long 0x1C 6. " COUNTBIT17 ,17th bit of the COUNT field of DMAxCOUNT register" "0,1"
textline " "
rbitfld.long 0x1C 0.--5. " COUNT ,Actual number of remaining DMA transfers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
endif
group.long 0xF8++0x1F
line.long 0x0 "DMA0COUNT,MibSPI DMA0COUNT Register"
hexmask.long.word 0x0 16.--31. 1. " ICOUNT0 ,Initial number of DMA transfers"
hexmask.long.word 0x0 0.--15. 1. " COUNT0 ,The actual number of remaining DMA transfers"
line.long 0x4 "DMA1COUNT,MibSPI DMA1COUNT Register"
hexmask.long.word 0x4 16.--31. 1. " ICOUNT1 ,Initial number of DMA transfers"
hexmask.long.word 0x4 0.--15. 1. " COUNT1 ,The actual number of remaining DMA transfers"
line.long 0x8 "DMA2COUNT,MibSPI DMA2COUNT Register"
hexmask.long.word 0x8 16.--31. 1. " ICOUNT2 ,Initial number of DMA transfers"
hexmask.long.word 0x8 0.--15. 1. " COUNT2 ,The actual number of remaining DMA transfers"
line.long 0xC "DMA3COUNT,MibSPI DMA3COUNT Register"
hexmask.long.word 0xC 16.--31. 1. " ICOUNT3 ,Initial number of DMA transfers"
hexmask.long.word 0xC 0.--15. 1. " COUNT3 ,The actual number of remaining DMA transfers"
line.long 0x10 "DMA4COUNT,MibSPI DMA4COUNT Register"
hexmask.long.word 0x10 16.--31. 1. " ICOUNT4 ,Initial number of DMA transfers"
hexmask.long.word 0x10 0.--15. 1. " COUNT4 ,The actual number of remaining DMA transfers"
line.long 0x14 "DMA5COUNT,MibSPI DMA5COUNT Register"
hexmask.long.word 0x14 16.--31. 1. " ICOUNT5 ,Initial number of DMA transfers"
hexmask.long.word 0x14 0.--15. 1. " COUNT5 ,The actual number of remaining DMA transfers"
line.long 0x18 "DMA6COUNT,MibSPI DMA6COUNT Register"
hexmask.long.word 0x18 16.--31. 1. " ICOUNT6 ,Initial number of DMA transfers"
hexmask.long.word 0x18 0.--15. 1. " COUNT6 ,The actual number of remaining DMA transfers"
line.long 0x1C "DMA7COUNT,MibSPI DMA7COUNT Register"
hexmask.long.word 0x1C 16.--31. 1. " ICOUNT7 ,Initial number of DMA transfers"
hexmask.long.word 0x1C 0.--15. 1. " COUNT7 ,The actual number of remaining DMA transfers"
textline " "
group.long 0x118++0x03
line.long 0x00 "DMACNTLEN,MibSPI DMACNTLEN Register"
bitfld.long 0x00 0. " LARGECOUNT ,Counters select" "DMAxCTRL,DMAxCOUNT"
group.long 0x120++0x03
line.long 0x00 "UERRCTRL,Uncorrectable Parity Error Control Register"
sif cpu()=="TMS570LC4357"
bitfld.long 0x00 24.--27. " SBE_EVT_EN ,ECC Single Bit Error Event Enable" ",,,,,Disabled,,,,,Enabled,?..."
bitfld.long 0x00 16.--19. " EDAC_MODE ,ECC Single Bit Error Block Correction" ",,,,,Disabled,,,,,Enabled,?..."
textline " "
endif
bitfld.long 0x00 8. " PTESTEN ,Parity memory test enable" "Disabled,Enabled"
bitfld.long 0x00 0.--3. " EDEN ,Error detection enable" "Enabled,Enabled,Enabled,Enabled,Enabled,Disabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled"
group.long 0x124++0x03
line.long 0x00 "UERRSTAT,Uncorrectable Parity Error Status Register"
sif cpu()=="TMS570LC4357"
eventfld.long 0x00 9. " SBE_FLG1 ,Single Bit Error in RXRAM" "Not occurred,Occurred"
eventfld.long 0x00 8. " SBE_FLG0 ,Single Bit Error in TXRAM" "Not occurred,Occurred"
textline " "
eventfld.long 0x00 1. " EDFLG1 ,Uncorrectable parity error detection flag" "Not occurred,Occurred"
eventfld.long 0x00 0. " EDFLG0 ,Uncorrectable parity error detection flag" "Not occurred,Occurred"
else
eventfld.long 0x00 1. " EDFLG1 ,Uncorrectable parity error detection flag" "Not occurred,Occurred"
eventfld.long 0x00 0. " EDFLG0 ,Uncorrectable parity error detection flag" "Not occurred,Occurred"
endif
width 17.
hgroup.long 0x128++0x03
hide.long 0x00 "UERRADDR1,Uncorrectable Parity Error Address Register"
in
hgroup.long 0x12C++0x03
hide.long 0x00 "UERRADDR0,Uncorrectable Parity Error Address Register"
in
hgroup.long 0x130++0x03
hide.long 0x00 "RXOVRN_BUF_ADDR,Receive RAM Overrun Buffer Address Register"
in
textline " "
width 14.
if (((d.l(ad:0xFFF7FA00+0x134))&0x2)==0x2)&&(((d.l(ad:0xFFF7FA00+0x134))&0xF00)==0xA00)
group.long 0x134++0x03
line.long 0x00 "IOLPBKTSTCR,SPI IO Loopback Test Control Register"
bitfld.long 0x00 24. " SCSFAILFLG ,Failure on SPISCS pin compare during analog loopback" "Not occurred,Occurred"
bitfld.long 0x00 20. " CTRL_BITERR ,Controls inducing of BITERR during I/O loopback test mode" "Disabled,Enabled"
bitfld.long 0x00 19. " CTRL_DESYNC ,Controls inducing of the desync error during I/O loopback test mode" "No error,Error"
textline " "
bitfld.long 0x00 18. " CTRL_PARERR ,Controls inducing of parity errors during I/O loopback test mode" "No error,Error"
bitfld.long 0x00 17. " CTRL_TIMEOUT ,Controls inducing of the timeout error during I/O loopbacK test mode" "No error,Error"
bitfld.long 0x00 16. " CTRL_DLENERR ,Controls inducing of the data length error during I/O loopback test mode" "No error,Error"
textline " "
bitfld.long 0x00 8.--11. " IOLPBKTSTENA ,Module I/O loopback test enable key" "Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Enabled,Disabled,Disabled,Disabled,Disabled,Disabled"
bitfld.long 0x00 3.--5. " ERRSCSPIN ,Inject error on chip-select pin number" "/SPISCS[0],/SPISCS[1],/SPISCS[2],/SPISCS[3],/SPISCS[4],/SPISCS[5],/SPISCS[6],/SPISCS[7]"
bitfld.long 0x00 2. " CTRLSCSPINERR ,Enable/disable the injection of an error on the SPISCS[3:0] pins" "Disabled,Enabled"
textline " "
bitfld.long 0x00 1. " LPBK_TYPE ,Module I/O loopback type (analog/digital)" "Digital,Analog"
bitfld.long 0x00 0. " RXP_ENA ,Enable analog loopback through the receive pin" "Transmit,Receive"
elif (((d.l(ad:0xFFF7FA00+0x134))&0x2)==0x0)&&(((d.l(ad:0xFFF7FA00+0x134))&0xF00)==0xA00)
group.long 0x134++0x03
line.long 0x00 "IOLPBKTSTCR,SPI IO Loopback Test Control Register"
eventfld.long 0x00 24. " SCSFAILFLG ,Failure on SPISCS pin compare during analog loopback" "Not occurred,Occurred"
bitfld.long 0x00 20. " CTRL_BITERR ,Controls inducing of BITERR during I/O loopback test mode" "Disabled,Enabled"
bitfld.long 0x00 19. " CTRL_DESYNC ,Controls inducing of the desync error during I/O loopback test mode" "No error,Error"
textline " "
bitfld.long 0x00 18. " CTRL_PARERR ,Controls inducing of parity errors during I/O loopback test mode" "No error,Error"
bitfld.long 0x00 17. " CTRL_TIMEOUT ,Controls inducing of the timeout error during I/O loopbacK test mode" "No error,Error"
bitfld.long 0x00 16. " CTRL_DLENERR ,Controls inducing of the data length error during I/O loopback test mode" "No error,Error"
textline " "
bitfld.long 0x00 8.--11. " IOLPBKTSTENA ,Module I/O loopback test enable key" "Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Enabled,Disabled,Disabled,Disabled,Disabled,Disabled"
bitfld.long 0x00 3.--5. " ERRSCSPIN ,Inject error on chip-select pin number" "/SPISCS[0],/SPISCS[1],/SPISCS[2],/SPISCS[3],/SPISCS[4],/SPISCS[5],/SPISCS[6],/SPISCS[7]"
bitfld.long 0x00 2. " CTRLSCSPINERR ,Enable/disable the injection of an error on the SPISCS[3:0] pins" "Disabled,Enabled"
textline " "
bitfld.long 0x00 1. " LPBK_TYPE ,Module I/O loopback type (analog/digital)" "Digital,Analog"
elif (((d.l(ad:0xFFF7FA00+0x134))&0x2)==0x2)&&(((d.l(ad:0xFFF7FA00+0x134))&0xF00)!=0xA00)
group.long 0x134++0x03
line.long 0x00 "IOLPBKTSTCR,SPI IO Loopback Test Control Register"
bitfld.long 0x00 8.--11. " IOLPBKTSTENA ,Module I/O loopback test enable key" "Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Enabled,Disabled,Disabled,Disabled,Disabled,Disabled"
bitfld.long 0x00 3.--5. " ERRSCSPIN ,Inject error on chip-select pin number" "/SPISCS[0],/SPISCS[1],/SPISCS[2],/SPISCS[3],/SPISCS[4],/SPISCS[5],/SPISCS[6],/SPISCS[7]"
bitfld.long 0x00 2. " CTRLSCSPINERR ,Enable/disable the injection of an error on the SPISCS[3:0] pins" "Disabled,Enabled"
textline " "
bitfld.long 0x00 1. " LPBK_TYPE ,Module I/O loopback type (analog/digital)" "Digital,Analog"
bitfld.long 0x00 0. " RXP_ENA ,Enable analog loopback through the receive pin" "Transmit,Receive"
else
group.long 0x134++0x03
line.long 0x00 "IOLPBKTSTCR,SPI IO Loopback Test Control Register"
bitfld.long 0x00 8.--11. " IOLPBKTSTENA ,Module I/O loopback test enable key" "Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Enabled,Disabled,Disabled,Disabled,Disabled,Disabled"
bitfld.long 0x00 3.--5. " ERRSCSPIN ,Inject error on chip-select pin number" "/SPISCS[0],/SPISCS[1],/SPISCS[2],/SPISCS[3],/SPISCS[4],/SPISCS[5],/SPISCS[6],/SPISCS[7]"
bitfld.long 0x00 2. " CTRLSCSPINERR ,Enable/disable the injection of an error on the SPISCS[3:0] pins" "Disabled,Enabled"
textline " "
bitfld.long 0x00 1. " LPBK_TYPE ,Module I/O loopback type (analog/digital)" "Digital,Analog"
endif
textline " "
width 21.
group.long 0x138++0x07
line.long 0x00 "EXTENDED_PRESCALE_1,SPI Extended Prescale Register 1"
hexmask.long.word 0x00 16.--26. 1. " EPRESCALE_FMT1 ,Extended Prescale value for SPIFMT1"
hexmask.long.word 0x00 0.--10. 1. " EPRESCALE_FMT0 ,Extended Prescale value for SPIFMT0"
line.long 0x04 "EXTENDED_PRESCALE_2,SPI Extended Prescale Register 2"
hexmask.long.word 0x04 16.--26. 1. " EPRESCALE_FMT3 ,Extended Prescale value for SPIFMT3"
hexmask.long.word 0x04 0.--10. 1. " EPRESCALE_FMT2 ,Extended Prescale value for SPIFMT2"
sif cpu()!="TMS570LC4357"
group.long 0x140++0x03
line.long 0x00 "ECCDIAG_CTRL,ECC Diagnostic Control register"
bitfld.long 0x00 0.--3. " ECCDIAG_EN ,ECC Diagnostic mode Enable Key bits" "Disabled,Disabled,Disabled,Disabled,Disabled,Enabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled"
endif
if ((d.l(ad:0xFFF7FA00+0x140)&0x5)==0x5)
group.long 0x144++0x03
line.long 0x00 "ECCDIAG_STAT, ECC Diagnostic Status Register"
eventfld.long 0x00 17. " DEFLG[1] ,Double bit Error is detected for RXRAM" "No error,Error"
eventfld.long 0x00 16. " DEFLG[0] ,Double bit Error is detected for TXRAM" "No error,Error"
eventfld.long 0x00 1. " SEFLG[1] ,Single bit Error is detected for RXRAM" "No error,Error"
eventfld.long 0x00 0. " SEFLG[0] ,Single bit Error is detected for TXRAM" "No error,Error"
else
hgroup.long 0x144++0x03
hide.long 0x00 "ECCDIAG_STAT,ECC Diagnostic Status Register"
in
endif
hgroup.long 0x148++0x03
hide.long 0x00 "SBERRADDR1,Single Bit Error Address Register - RXRAM"
in
hgroup.long 0x14C++0x03
hide.long 0x00 "SBERRADDR0,Single Bit Error Address Register - TXRAM"
in
tree.end
tree "MibSPI5"
base ad:0xFFF7FC00
width 17.
group.long 0x00++0x03
line.long 0x00 "SPIGCR0,SPI Global Control Register 0"
bitfld.long 0x00 0. " NRESET ,Reset bit for the module" "No reset,Reset"
if (((d.l(ad:0xFFF7FC00+0x4))&0x3)==0x00)
group.long 0x04++0x03
line.long 0x00 "SPIGCR1,SPI Global Control Register 1"
bitfld.long 0x00 24. " SPIEN ,SPI enable" "Disabled,Enabled"
bitfld.long 0x00 16. " LOOPBACK ,Internal loop-back test mode" "Disabled,Enabled"
bitfld.long 0x00 8. " POWERDOWN ,SPI state machine enters a power-down state" "No power-down,Power-down"
textline " "
bitfld.long 0x00 1. " CLKMOD ,Clock mode" "External,Internally"
bitfld.long 0x00 0. " MASTER ,SPISIMO/SPISOMI pin direction determination" "Input/ouput,Output/input"
else
group.long 0x04++0x03
line.long 0x00 "SPIGCR1,SPI Global Control Register 1"
bitfld.long 0x00 24. " SPIEN ,SPI enable" "Disabled,Enabled"
bitfld.long 0x00 8. " POWERDOWN ,SPI state machine enters a power-down state" "No power-down,Power-down"
bitfld.long 0x00 1. " CLKMOD ,Clock mode" "External,Internally"
textline " "
bitfld.long 0x00 0. " MASTER ,SPISIMO/SPISOMI pin direction determination" "Input/ouput,Output/input"
endif
group.long 0x08++0x03
line.long 0x00 "SPIINT0,SPI Interrupt Register"
bitfld.long 0x00 24. " ENABLEHIGHZ ,SPIENA pin high-impedance enable" "Inactive,Active"
bitfld.long 0x00 16. " DMAREQEN ,DMA request enable" "Disabled,Enabled"
bitfld.long 0x00 9. " TXINTENA ,TX interrupt flag enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 8. " RXINTENA ,RX interrupt flag enable" "Disabled,Enabled"
bitfld.long 0x00 6. " RXOVRNINTENA ,Overrun interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 4. " BITERRENA ,Enables interrupt on bit error" "Disabled,Enabled"
textline " "
bitfld.long 0x00 3. " DESYNCENA ,Enables interrupt on desynchronized slave" "Disabled,Enabled"
bitfld.long 0x00 2. " PARERRENA ,Enables interrupt-on-parity-error" "Disabled,Enabled"
bitfld.long 0x00 1. " TIMEOUTENA ,Enables interrupt on ENA signal time-out" "Disabled,Enabled"
textline " "
bitfld.long 0x00 0. " DLENERRENA ,Data length error interrupt enable" "Disabled,Enabled"
group.long 0x0C++0x03
line.long 0x00 "SPILVL,SPI Interrupt Level Register"
bitfld.long 0x00 9. " TXINTLVL ,Transmit interrupt level" "INT0,INT1"
bitfld.long 0x00 8. " RXINTLVL ,Receive interrupt level" "INT0,INT1"
bitfld.long 0x00 6. " RXOVRNINTLVL ,Receive overrun interrupt level" "INT0,INT1"
textline " "
bitfld.long 0x00 4. " BITERRLVL ,Bit error interrupt level" "INT0,INT1"
bitfld.long 0x00 3. " DESYNCLVL ,Desynchronized slave interrupt level (master mode only)" "INT0,INT1"
bitfld.long 0x00 2. " PARERRLVL ,Parity error interrupt level" "INT0,INT1"
textline " "
bitfld.long 0x00 1. " TIMEOUTLVL ,SPIENA pin time-out interrupt level" "INT0,INT1"
bitfld.long 0x00 0. " DLENERRLVL ,Data length error interrupt level (line) select" "INT0,INT1"
group.long 0x10++0x03
line.long 0x00 "SPIFLG,SPI Flag Register"
rbitfld.long 0x00 24. " BUFINITACTIVE ,Indicates the status of multi-buffer initialization process" "Completed,Not completed"
rbitfld.long 0x00 9. " TXINTFLG ,Transmitter-empty interrupt flag" "No interrupt,Interrupt"
eventfld.long 0x00 8. " RXINTFLG ,Receiver-full interrupt flag" "No interrupt,Interrupt"
textline " "
eventfld.long 0x00 6. " RXOVRNINTFLG ,Overrun interrupt enable" "Disabled,Enabled"
eventfld.long 0x00 4. " BITERRFLG ,Enables interrupt on bit error" "Disabled,Enabled"
eventfld.long 0x00 3. " DESYNCFLG ,Enables interrupt on desynchronized slave" "No interrupt,Interrupt"
textline " "
eventfld.long 0x00 2. " PARITYERRFLG ,Enables interrupt-on-parity-error" "No error,Error"
eventfld.long 0x00 1. " TIMEOUTFLG ,Enables interrupt on ENA signal time-out" "No interrupt,Interrupt"
eventfld.long 0x00 0. " DLENERRFLG ,Data length error interrupt enable" "No interrupt,Interrupt"
textline " "
width 12.
group.long 0x14++0x23
line.long 0x00 "SPIPC0,SPI Pin Control Register 0"
bitfld.long 0x00 31. " SOMIFUN[7] ,SPISOMI[7] pin function" "GIO,SPI"
bitfld.long 0x00 30. " [6] ,SPISOMI[6] pin function" "GIO,SPI"
bitfld.long 0x00 29. " [5] ,SPISOMI[5] pin function" "GIO,SPI"
bitfld.long 0x00 28. " [4] ,SPISOMI[4] pin function" "GIO,SPI"
textline " "
bitfld.long 0x00 27. " [3] ,SPISOMI[3] pin function" "GIO,SPI"
bitfld.long 0x00 26. " [2] ,SPISOMI[2] pin function" "GIO,SPI"
bitfld.long 0x00 25. " [1] ,SPISOMI[1] pin function" "GIO,SPI"
bitfld.long 0x00 24. " [0] ,SPISOMI[0] pin function (mirror of bit 11)" "GIO,SPI"
textline " "
bitfld.long 0x00 23. " SIMOFUN[7] ,SPISIMO[7] pin function" "GIO,SPI"
bitfld.long 0x00 22. " [6] ,SPISIMO[6] pin function" "GIO,SPI"
bitfld.long 0x00 21. " [5] ,SPISIMO[5] pin function" "GIO,SPI"
bitfld.long 0x00 20. " [4] ,SPISIMO[4] pin function" "GIO,SPI"
textline " "
bitfld.long 0x00 19. " [3] ,SPISIMO[3] pin function" "GIO,SPI"
bitfld.long 0x00 18. " [2] ,SPISIMO[2] pin function" "GIO,SPI"
bitfld.long 0x00 17. " [1] ,SPISIMO[1] pin function" "GIO,SPI"
bitfld.long 0x00 16. " [0] ,SPISIMO[0] pin function (mirror of bit 10)" "GIO,SPI"
textline " "
bitfld.long 0x00 11. " SOMIFUN[0] ,SPISOMI[0] pin function" "GIO,SPI"
bitfld.long 0x00 10. " SIMOFUN[0] ,SPISIMO[0] pin function" "GIO,SPI"
bitfld.long 0x00 9. " CLKFUN ,SPI clock function" "GIO,SPI"
bitfld.long 0x00 8. " ENAFUN ,SPIENA function" "GIO,SPI"
textline " "
textline " "
bitfld.long 0x00 7. " SCSFUN[7] ,SPISCS7 function 7" "GIO,SPI"
bitfld.long 0x00 6. " [6] ,SPISCS6 function 6" "GIO,SPI"
bitfld.long 0x00 5. " [5] ,SPISCS5 function 5" "GIO,SPI"
bitfld.long 0x00 4. " [4] ,SPISCS4 function 4" "GIO,SPI"
textline " "
bitfld.long 0x00 3. " [3] ,SPISCS3 function 3" "GIO,SPI"
bitfld.long 0x00 2. " [2] ,SPISCS2 function 2" "GIO,SPI"
bitfld.long 0x00 1. " [1] ,SPISCS1 function 1" "GIO,SPI"
bitfld.long 0x00 0. " [0] ,SPISCS0 function 0" "GIO,SPI"
textline " "
line.long 0x04 "SPIPC1,SPI Pin Control Register 1"
bitfld.long 0x04 31. " SOMIDIR[7] ,SPISOMI[7] pin direction" "GIO,SPI"
bitfld.long 0x04 30. " [6] ,SPISOMI[6] pin direction" "GIO,SPI"
bitfld.long 0x04 29. " [5] ,SPISOMI[5] pin direction" "GIO,SPI"
bitfld.long 0x04 28. " [4] ,SPISOMI[4] pin direction" "GIO,SPI"
textline " "
bitfld.long 0x04 27. " [3] ,SPISOMI[3] pin direction" "GIO,SPI"
bitfld.long 0x04 26. " [2] ,SPISOMI[2] pin direction" "GIO,SPI"
bitfld.long 0x04 25. " [1] ,SPISOMI[1] pin direction" "GIO,SPI"
bitfld.long 0x04 24. " [0] ,SPISOMI[0] pin direction (mirror of bit 11)" "GIO,SPI"
textline " "
bitfld.long 0x04 23. " SIMODIR[7] ,SPISIMO[7] pin direction" "GIO,SPI"
bitfld.long 0x04 22. " [6] ,SPISIMO[6] pin direction" "GIO,SPI"
bitfld.long 0x04 21. " [5] ,SPISIMO[5] pin direction" "GIO,SPI"
bitfld.long 0x04 20. " [4] ,SPISIMO[4] pin direction" "GIO,SPI"
textline " "
bitfld.long 0x04 19. " [3] ,SPISIMO[3] pin direction" "GIO,SPI"
bitfld.long 0x04 18. " [2] ,SPISIMO[2] pin direction" "GIO,SPI"
bitfld.long 0x04 17. " [1] ,SPISIMO[1] pin direction" "GIO,SPI"
bitfld.long 0x04 16. " [0] ,SPISIMO[0] pin direction (mirror of bit 10)" "GIO,SPI"
textline " "
bitfld.long 0x04 11. " SOMIDIR[0] ,SPISOMI[0] pin direction" "GIO,SPI"
bitfld.long 0x04 10. " SIMODIR[0] ,SPISIMO[0] pin direction" "GIO,SPI"
bitfld.long 0x04 9. " CLKDIR ,SPI clock direction" "GIO,SPI"
bitfld.long 0x04 8. " ENADIR ,SPIENA direction" "GIO,SPI"
textline " "
textline " "
bitfld.long 0x04 7. " SCSDIR[7] ,SPISCS7 direction 7" "GIO,SPI"
bitfld.long 0x04 6. " [6] ,SPISCS6 direction 6" "GIO,SPI"
bitfld.long 0x04 5. " [5] ,SPISCS5 direction 5" "GIO,SPI"
bitfld.long 0x04 4. " [4] ,SPISCS4 direction 4" "GIO,SPI"
textline " "
bitfld.long 0x04 3. " [3] ,SPISCS3 direction 3" "GIO,SPI"
bitfld.long 0x04 2. " [2] ,SPISCS2 direction 2" "GIO,SPI"
bitfld.long 0x04 1. " [1] ,SPISCS1 direction 1" "GIO,SPI"
bitfld.long 0x04 0. " [0] ,SPISCS0 direction 0" "GIO,SPI"
textline " "
line.long 0x08 "SPIPC2,SPI Pin Control Register 2"
bitfld.long 0x08 31. " SOMIDIN[7] ,SPISOMI[7] data in" "0,1"
bitfld.long 0x08 30. " [6] ,SPISOMI[6] data in" "0,1"
bitfld.long 0x08 29. " [5] ,SPISOMI[5] data in" "0,1"
bitfld.long 0x08 28. " [4] ,SPISOMI[4] data in" "0,1"
bitfld.long 0x08 27. " [3] ,SPISOMI[3] data in" "0,1"
bitfld.long 0x08 26. " [2] ,SPISOMI[2] data in" "0,1"
bitfld.long 0x08 25. " [1] ,SPISOMI[1] data in" "0,1"
bitfld.long 0x08 24. " [0] ,SPISOMI[0] data in (mirror of bit 11)" "0,1"
textline " "
bitfld.long 0x08 23. " SIMODIN[7] ,SPISIMO[7] data in" "0,1"
bitfld.long 0x08 22. " [6] ,SPISIMO[6] data in" "0,1"
bitfld.long 0x08 21. " [5] ,SPISIMO[5] data in" "0,1"
bitfld.long 0x08 20. " [4] ,SPISIMO[4] data in" "0,1"
bitfld.long 0x08 19. " [3] ,SPISIMO[3] data in" "0,1"
bitfld.long 0x08 18. " [2] ,SPISIMO[2] data in" "0,1"
bitfld.long 0x08 17. " [1] ,SPISIMO[1] data in" "0,1"
bitfld.long 0x08 16. " [0] ,SPISIMO[0] data in (mirror of bit 10)" "0,1"
textline " "
bitfld.long 0x08 11. " SOMIDIN[0] ,SPISOMI[0] data in" "0,1"
bitfld.long 0x08 10. " SIMODIN[0] ,SPISIMO[0] data in" "0,1"
bitfld.long 0x08 9. " CLKDIN ,SPI clock data in" "0,1"
bitfld.long 0x08 8. " ENADIN ,SPIENA data in" "0,1"
textline " "
textline " "
bitfld.long 0x08 7. " SCSDIN[7] ,SPISCS7 data in" "0,1"
bitfld.long 0x08 6. " [6] ,SPISCS6 data in" "0,1"
bitfld.long 0x08 5. " [5] ,SPISCS5 data in" "0,1"
bitfld.long 0x08 4. " [4] ,SPISCS4 data in" "0,1"
bitfld.long 0x08 3. " [3] ,SPISCS3 data in" "0,1"
bitfld.long 0x08 2. " [2] ,SPISCS2 data in" "0,1"
bitfld.long 0x08 1. " [1] ,SPISCS1 data in" "0,1"
bitfld.long 0x08 0. " [0] ,SPISCS0 direction 0" "0,1"
textline " "
line.long 0x0C "SPIPC3,SPI Pin Control Register 3"
bitfld.long 0x0C 31. " SOMIDOUT[7] ,SPISOMI[7] data out write" "0,1"
bitfld.long 0x0C 30. " [6] ,SPISOMI[6] data out write" "0,1"
bitfld.long 0x0C 29. " [5] ,SPISOMI[5] data out write" "0,1"
bitfld.long 0x0C 28. " [4] ,SPISOMI[4] data out write" "0,1"
bitfld.long 0x0C 27. " [3] ,SPISOMI[3] data out write" "0,1"
bitfld.long 0x0C 26. " [2] ,SPISOMI[2] data out write" "0,1"
bitfld.long 0x0C 25. " [1] ,SPISOMI[1] data out write" "0,1"
bitfld.long 0x0C 24. " [0] ,SPISOMI[0] data out write (mirror of bit 11)" "0,1"
textline " "
bitfld.long 0x0C 23. " SIMODOUT[7] ,SPISIMO[7] data out write" "0,1"
bitfld.long 0x0C 22. " [6] ,SPISIMO[6] data out write" "0,1"
bitfld.long 0x0C 21. " [5] ,SPISIMO[5] data out write" "0,1"
bitfld.long 0x0C 20. " [4] ,SPISIMO[4] data out write" "0,1"
bitfld.long 0x0C 19. " [3] ,SPISIMO[3] data out write" "0,1"
bitfld.long 0x0C 18. " [2] ,SPISIMO[2] data out write" "0,1"
bitfld.long 0x0C 17. " [1] ,SPISIMO[1] data out write" "0,1"
bitfld.long 0x0C 16. " [0] ,SPISIMO[0] data out write (mirror of bit 10)" "0,1"
textline " "
bitfld.long 0x0C 11. " SOMIDOUT[0] ,SPISOMI[0] data out write" "0,1"
bitfld.long 0x0C 10. " SIMODOUT[0] ,SPISIMO[0] data out write" "0,1"
bitfld.long 0x0C 9. " CLKDOUT ,SPI clock data out write" "0,1"
bitfld.long 0x0C 8. " ENADOUT ,SPIENA data out write" "0,1"
textline " "
textline " "
bitfld.long 0x0C 7. " SCSDOUT[7] ,SPISCS7 data out write" "0,1"
bitfld.long 0x0C 6. " [6] ,SPISCS6 data out write" "0,1"
bitfld.long 0x0C 5. " [5] ,SPISCS5 data out write" "0,1"
bitfld.long 0x0C 4. " [4] ,SPISCS4 data out write" "0,1"
bitfld.long 0x0C 3. " [3] ,SPISCS3 data out write" "0,1"
bitfld.long 0x0C 2. " [2] ,SPISCS2 data out write" "0,1"
bitfld.long 0x0C 1. " [1] ,SPISCS1 data out write" "0,1"
bitfld.long 0x0C 0. " [0] ,SPISCS0 data out write" "0,1"
textline " "
line.long 0x10 "SPIPC4,SPI Pin Control Register 4"
bitfld.long 0x10 31. " SOMISET[7] ,SPISOMI[7] data out set" "0,1"
bitfld.long 0x10 30. " [6] ,SPISOMI[6] data out set" "0,1"
bitfld.long 0x10 29. " [5] ,SPISOMI[5] data out set" "0,1"
bitfld.long 0x10 28. " [4] ,SPISOMI[4] data out set" "0,1"
bitfld.long 0x10 27. " [3] ,SPISOMI[3] data out set" "0,1"
bitfld.long 0x10 26. " [2] ,SPISOMI[2] data out set" "0,1"
bitfld.long 0x10 25. " [1] ,SPISOMI[1] data out set" "0,1"
bitfld.long 0x10 24. " [0] ,SPISOMI[0] data out set (mirror of bit 11)" "0,1"
textline " "
bitfld.long 0x10 23. " SIMOSET[7] ,SPISIMO[7] data out set" "0,1"
bitfld.long 0x10 22. " [6] ,SPISIMO[6] data out set" "0,1"
bitfld.long 0x10 21. " [5] ,SPISIMO[5] data out set" "0,1"
bitfld.long 0x10 20. " [4] ,SPISIMO[4] data out set" "0,1"
bitfld.long 0x10 19. " [3] ,SPISIMO[3] data out set" "0,1"
bitfld.long 0x10 18. " [2] ,SPISIMO[2] data out set" "0,1"
bitfld.long 0x10 17. " [1] ,SPISIMO[1] data out set" "0,1"
bitfld.long 0x10 16. " [0] ,SPISIMO[0] data out set (mirror of bit 10)" "0,1"
textline " "
bitfld.long 0x10 11. " SOMISET[0] ,SPISOMI[0] data out set" "0,1"
bitfld.long 0x10 10. " SIMOSET[0] ,SPISIMO[0] data out set" "0,1"
bitfld.long 0x10 9. " CLKSET ,SPI clock data out set" "0,1"
bitfld.long 0x10 8. " ENASET ,SPIENA data out set" "0,1"
textline " "
textline " "
bitfld.long 0x10 7. " SCSSET[7] ,SPISCS7 data out set" "0,1"
bitfld.long 0x10 6. " [6] ,SPISCS6 data out set" "0,1"
bitfld.long 0x10 5. " [5] ,SPISCS5 data out set" "0,1"
bitfld.long 0x10 4. " [4] ,SPISCS4 data out set" "0,1"
bitfld.long 0x10 3. " [3] ,SPISCS3 data out set" "0,1"
bitfld.long 0x10 2. " [2] ,SPISCS2 data out set" "0,1"
bitfld.long 0x10 1. " [1] ,SPISCS1 data out set" "0,1"
bitfld.long 0x10 0. " [0] ,SPISCS0 data out set" "0,1"
textline " "
line.long 0x14 "SPIPC5,SPI Pin Control Register 5"
bitfld.long 0x14 31. " SOMICLR[7] ,SPISOMI[7] data out clear" "0,1"
bitfld.long 0x14 30. " [6] ,SPISOMI[6] data out clear" "0,1"
bitfld.long 0x14 29. " [5] ,SPISOMI[5] data out clear" "0,1"
bitfld.long 0x14 28. " [4] ,SPISOMI[4] data out clear" "0,1"
bitfld.long 0x14 27. " [3] ,SPISOMI[3] data out clear" "0,1"
bitfld.long 0x14 26. " [2] ,SPISOMI[2] data out clear" "0,1"
bitfld.long 0x14 25. " [1] ,SPISOMI[1] data out clear" "0,1"
bitfld.long 0x14 24. " [0] ,SPISOMI[0] data out clear (mirror of bit 11)" "0,1"
textline " "
bitfld.long 0x14 23. " SIMOCLR[7] ,SPISIMO[7] data out clear" "0,1"
bitfld.long 0x14 22. " [6] ,SPISIMO[6] data out clear" "0,1"
bitfld.long 0x14 21. " [5] ,SPISIMO[5] data out clear" "0,1"
bitfld.long 0x14 20. " [4] ,SPISIMO[4] data out clear" "0,1"
bitfld.long 0x14 19. " [3] ,SPISIMO[3] data out clear" "0,1"
bitfld.long 0x14 18. " [2] ,SPISIMO[2] data out clear" "0,1"
bitfld.long 0x14 17. " [1] ,SPISIMO[1] data out clear" "0,1"
bitfld.long 0x14 16. " [0] ,SPISIMO[0] data out clear (mirror of bit 10)" "0,1"
textline " "
bitfld.long 0x14 11. " SOMICLR[0] ,SPISOMI[0] data out clear" "0,1"
bitfld.long 0x14 10. " SIMOCLR[0] ,SPISIMO[0] data out clear" "0,1"
bitfld.long 0x14 9. " CLKCLR ,SPI clock data out clear" "0,1"
bitfld.long 0x14 8. " ENACLR ,SPIENA data out clear" "0,1"
textline " "
textline " "
bitfld.long 0x14 7. " SCSCLR[7] ,SPISCS7 data out clear" "0,1"
bitfld.long 0x14 6. " [6] ,SPISCS6 data out clear" "0,1"
bitfld.long 0x14 5. " [5] ,SPISCS5 data out clear" "0,1"
bitfld.long 0x14 4. " [4] ,SPISCS4 data out clear" "0,1"
bitfld.long 0x14 3. " [3] ,SPISCS3 data out clear" "0,1"
bitfld.long 0x14 2. " [2] ,SPISCS2 data out clear" "0,1"
bitfld.long 0x14 1. " [1] ,SPISCS1 data out clear" "0,1"
bitfld.long 0x14 0. " [0] ,SPISCS0 data out clear" "0,1"
textline " "
line.long 0x18 "SPIPC6,SPI Pin Control Register 6"
bitfld.long 0x18 31. " SOMIPDR[7] ,SPISOMI[7] open drain enable" "Disabled,Enabled"
bitfld.long 0x18 30. " [6] ,SPISOMI[6] open drain enable" "Disabled,Enabled"
bitfld.long 0x18 29. " [5] ,SPISOMI[5] open drain enable" "Disabled,Enabled"
bitfld.long 0x18 28. " [4] ,SPISOMI[4] open drain enable" "Disabled,Enabled"
textline " "
bitfld.long 0x18 27. " [3] ,SPISOMI[3] open drain enable" "Disabled,Enabled"
bitfld.long 0x18 26. " [2] ,SPISOMI[2] open drain enable" "Disabled,Enabled"
bitfld.long 0x18 25. " [1] ,SPISOMI[1] open drain enable" "Disabled,Enabled"
bitfld.long 0x18 24. " [0] ,SPISOMI[0] open drain enable (mirror of bit 11)" "Disabled,Enabled"
textline " "
bitfld.long 0x18 23. " SIMOPDR[7] ,SPISIMO[7] open drain enable" "Disabled,Enabled"
bitfld.long 0x18 22. " [6] ,SPISIMO[6] open drain enable" "Disabled,Enabled"
bitfld.long 0x18 21. " [5] ,SPISIMO[5] open drain enable" "Disabled,Enabled"
bitfld.long 0x18 20. " [4] ,SPISIMO[4] open drain enable" "Disabled,Enabled"
textline " "
bitfld.long 0x18 19. " [3] ,SPISIMO[3] open drain enable" "Disabled,Enabled"
bitfld.long 0x18 18. " [2] ,SPISIMO[2] open drain enable" "Disabled,Enabled"
bitfld.long 0x18 17. " [1] ,SPISIMO[1] open drain enable" "Disabled,Enabled"
bitfld.long 0x18 16. " [0] ,SPISIMO[0] open drain enable (mirror of bit 10)" "Disabled,Enabled"
textline " "
bitfld.long 0x18 11. " SOMIPDR[0] ,SPISOMI[0] open drain enable" "Disabled,Enabled"
bitfld.long 0x18 10. " SIMOPDR[0] ,SPISIMO[0] open drain enable" "Disabled,Enabled"
bitfld.long 0x18 9. " CLKPDR ,SPI clock open drain enable" "Disabled,Enabled"
bitfld.long 0x18 8. " ENAPDR ,SPIENA open drain enable" "Disabled,Enabled"
textline " "
textline " "
bitfld.long 0x18 7. " SCSPDR[7] ,SPISCS7 open drain enable" "Disabled,Enabled"
bitfld.long 0x18 6. " [6] ,SPISCS6 open drain enable" "Disabled,Enabled"
bitfld.long 0x18 5. " [5] ,SPISCS5 open drain enable" "Disabled,Enabled"
bitfld.long 0x18 4. " [4] ,SPISCS4 open drain enable" "Disabled,Enabled"
textline " "
bitfld.long 0x18 3. " [3] ,SPISCS3 open drain enable" "Disabled,Enabled"
bitfld.long 0x18 2. " [2] ,SPISCS2 open drain enable" "Disabled,Enabled"
bitfld.long 0x18 1. " [1] ,SPISCS1 open drain enable" "Disabled,Enabled"
bitfld.long 0x18 0. " [0] ,SPISCS0 open drain enable" "Disabled,Enabled"
textline " "
line.long 0x1C "SPIPC7,SPI Pin Control Register 7"
bitfld.long 0x1C 31. " SOMIPDIS[7] ,SPISOMI[7] pull control enable/disable" "No,Yes"
bitfld.long 0x1C 30. " [6] ,SPISOMI[6] pull control enable/disable" "No,Yes"
bitfld.long 0x1C 29. " [5] ,SPISOMI[5] pull control enable/disable" "No,Yes"
bitfld.long 0x1C 28. " [4] ,SPISOMI[4] pull control enable/disable" "No,Yes"
textline " "
bitfld.long 0x1C 27. " [3] ,SPISOMI[3] pull control enable/disable" "No,Yes"
bitfld.long 0x1C 26. " [2] ,SPISOMI[2] pull control enable/disable" "No,Yes"
bitfld.long 0x1C 25. " [1] ,SPISOMI[1] pull control enable/disable" "No,Yes"
bitfld.long 0x1C 24. " [0] ,SPISOMI[0] pull control enable/disable (mirror of bit 11)" "No,Yes"
textline " "
bitfld.long 0x1C 23. " SIMOPDIS[7] ,SPISIMO[7] pull control enable/disable" "No,Yes"
bitfld.long 0x1C 22. " [6] ,SPISIMO[6] pull control enable/disable" "No,Yes"
bitfld.long 0x1C 21. " [5] ,SPISIMO[5] pull control enable/disable" "No,Yes"
bitfld.long 0x1C 20. " [4] ,SPISIMO[4] pull control enable/disable" "No,Yes"
textline " "
bitfld.long 0x1C 19. " [3] ,SPISIMO[3] pull control enable/disable" "No,Yes"
bitfld.long 0x1C 18. " [2] ,SPISIMO[2] pull control enable/disable" "No,Yes"
bitfld.long 0x1C 17. " [1] ,SPISIMO[1] pull control enable/disable" "No,Yes"
bitfld.long 0x1C 16. " [0] ,SPISIMO[0] pull control enable/disable (mirror of bit 10)" "No,Yes"
textline " "
bitfld.long 0x1C 11. " SOMIPDIS[0] ,SPISOMI[0] pull control enable/disable" "No,Yes"
bitfld.long 0x1C 10. " SIMOPDIS[0] ,SPISIMO[0] pull control enable/disable" "No,Yes"
bitfld.long 0x1C 9. " CLKPDIS ,SPI clock pull control enable/disable" "No,Yes"
bitfld.long 0x1C 8. " ENAPDIS ,SPIENA pull control enable/disable" "No,Yes"
textline " "
textline " "
bitfld.long 0x1C 7. " SCSPDIS[7] ,SPISCS7 pull control enable/disable" "No,Yes"
bitfld.long 0x1C 6. " [6] ,SPISCS6 pull control enable/disable" "No,Yes"
bitfld.long 0x1C 5. " [5] ,SPISCS5 pull control enable/disable" "No,Yes"
bitfld.long 0x1C 4. " [4] ,SPISCS4 pull control enable/disable" "No,Yes"
textline " "
bitfld.long 0x1C 3. " [3] ,SPISCS3 pull control enable/disable" "No,Yes"
bitfld.long 0x1C 2. " [2] ,SPISCS2 pull control enable/disable" "No,Yes"
bitfld.long 0x1C 1. " [1] ,SPISCS1 pull control enable/disable" "No,Yes"
bitfld.long 0x1C 0. " [0] ,SPISCS0 pull control enable/disable" "No,Yes"
textline " "
line.long 0x20 "SPIPC8,SPI Pin Control Register 8"
bitfld.long 0x20 31. " SOMIPSEL[7] ,SPISOMI[7] pull select" "Pull down,Pull up"
bitfld.long 0x20 30. " [6] ,SPISOMI[6] pull select" "Pull down,Pull up"
bitfld.long 0x20 29. " [5] ,SPISOMI[5] pull select" "Pull down,Pull up"
bitfld.long 0x20 28. " [4] ,SPISOMI[4] pull select" "Pull down,Pull up"
textline " "
bitfld.long 0x20 27. " [3] ,SPISOMI[3] pull select" "Pull down,Pull up"
bitfld.long 0x20 26. " [2] ,SPISOMI[2] pull select" "Pull down,Pull up"
bitfld.long 0x20 25. " [1] ,SPISOMI[1] pull select" "Pull down,Pull up"
bitfld.long 0x20 24. " [0] ,SPISOMI[0] pull select (mirror of bit 11)" "Pull down,Pull up"
textline " "
bitfld.long 0x20 23. " SIMOPSEL[7] ,SPISIMO[7] pull select" "Pull down,Pull up"
bitfld.long 0x20 22. " [6] ,SPISIMO[6] pull select" "Pull down,Pull up"
bitfld.long 0x20 21. " [5] ,SPISIMO[5] pull select" "Pull down,Pull up"
bitfld.long 0x20 20. " [4] ,SPISIMO[4] pull select" "Pull down,Pull up"
textline " "
bitfld.long 0x20 19. " [3] ,SPISIMO[3] pull select" "Pull down,Pull up"
bitfld.long 0x20 18. " [2] ,SPISIMO[2] pull select" "Pull down,Pull up"
bitfld.long 0x20 17. " [1] ,SPISIMO[1] pull select" "Pull down,Pull up"
bitfld.long 0x20 16. " [0] ,SPISIMO[0] pull select (mirror of bit 10)" "Pull down,Pull up"
textline " "
bitfld.long 0x20 11. " SOMIPSEL[0] ,SPISOMI[0] pull select" "Pull down,Pull up"
bitfld.long 0x20 10. " SIMOPSEL[0] ,SPISIMO[0] pull select" "Pull down,Pull up"
bitfld.long 0x20 9. " CLKPSEL ,SPI clock pull select" "Pull down,Pull up"
bitfld.long 0x20 8. " ENAPSEL ,SPIENA pull select" "Pull down,Pull up"
textline " "
textline " "
bitfld.long 0x20 7. " SCSPSEL[7] ,SPISCS7 pull select" "Pull down,Pull up"
bitfld.long 0x20 6. " [6] ,SPISCS6 pull select" "Pull down,Pull up"
bitfld.long 0x20 5. " [5] ,SPISCS5 pull select" "Pull down,Pull up"
bitfld.long 0x20 4. " [4] ,SPISCS4 pull select" "Pull down,Pull up"
textline " "
bitfld.long 0x20 3. " [3] ,SPISCS3 pull select" "Pull down,Pull up"
bitfld.long 0x20 2. " [2] ,SPISCS2 pull select" "Pull down,Pull up"
bitfld.long 0x20 1. " [1] ,SPISCS1 pull select" "Pull down,Pull up"
bitfld.long 0x20 0. " [0] ,SPISCS0 pull select" "Pull down,Pull up"
textline " "
group.long 0x38++0x03
line.long 0x00 "SPIDAT0,SPI Transmit Data Register 0"
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,SPI transmit data"
if (((d.l(ad:0xFFF7FC00+0x4))&0x3)==0x0)
group.long 0x3C++0x03
line.long 0x00 "SPIDAT1,Transmit Data Register 1"
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Inactive,Active"
bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "No delay,After transaction"
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
textline " "
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
else
group.long 0x3C++0x03
line.long 0x00 "SPIDAT1,Transmit Data Register 1"
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Inactive,Active"
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
textline " "
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
endif
width 17.
hgroup.long 0x40++0x03
hide.long 0x00 "SPIBUF,SPI Receive Buffer Register"
in
rgroup.long 0x44++0x03
line.long 0x00 "SPIEMU,SPI Emulation Register"
hexmask.long.word 0x00 0.--15. 1. " EMU_RXDATA ,SPI receive data"
if (((d.l(ad:0xFFF7FC00+0x4))&0x1)==0x1)
rgroup.long 0x48++0x03
line.long 0x00 "SPIDELAY,SPI Delay Register"
hexmask.long.byte 0x00 24.--31. 1. " C2TDELAY ,Chip-select-active to transmit-start delay"
hexmask.long.byte 0x00 16.--23. 1. " T2CDELAY ,Transmit-end-to-chip-select-inactive-delay"
hexmask.long.byte 0x00 8.--15. 1. " T2EDELAY ,Transmit-data-finished to ENA-pin-inactive time-out"
textline " "
hexmask.long.byte 0x00 0.--7. 1. " C2EDELAY ,Chip-select-active to ENA-signal-active time-out"
group.long 0x4C++0x03
line.long 0x00 "SPIDEF,SPI Default Chip Select Register"
bitfld.long 0x00 7. " CSDEF[7] ,Chip select default pattern 7" "0,1"
bitfld.long 0x00 6. " [6] ,Chip select default pattern 6" "0,1"
bitfld.long 0x00 5. " [5] ,Chip select default pattern 5" "0,1"
textline " "
bitfld.long 0x00 4. " [4] ,Chip select default pattern 4" "0,1"
bitfld.long 0x00 3. " [3] ,Chip select default pattern 3" "0,1"
bitfld.long 0x00 2. " [2] ,Chip select default pattern 2" "0,1"
textline " "
bitfld.long 0x00 1. " [1] ,Chip select default pattern 1" "0,1"
bitfld.long 0x00 0. " [0] ,Chip select default pattern 0" "0,1"
endif
if (((d.l(ad:0xFFF7FC00+0x4))&0x3)==0x0)
group.long 0x50++0x0F
line.long 0x0 "SPIFMT0,SPI Data Format Register 0"
sif cpuis("TMS570LC4357")
hexmask.long.byte 0x0 24.--31. 1. " WDELAY ,Delay in between transmissions for data format 0"
else
bitfld.long 0x0 24.--29. " WDELAY ,Delay in between transmissions for data format 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
endif
bitfld.long 0x0 23. " PARPOL ,Parity polarity: even or odd" "Even,Odd"
textline " "
bitfld.long 0x0 22. " PARITYENA ,Parity enable for data format 0" "Disabled,Enabled"
bitfld.long 0x0 20. " SHIFTDIR ,Shift direction for data format $" "MSB,LSB"
textline " "
sif cpuis("TMS570LC4357")
bitfld.long 0x0 19. " HDUPLEX_ENA0 ,Half Duplex transfer mode enable for Data Format 0" "Normal,TX"
endif
textline " "
bitfld.long 0x0 18. " DISCSTIMERS ,Disable chip-select timers for this format" "No,Yes"
textline " "
bitfld.long 0x0 17. " POLARITY ,SPI data format 0 clock polarity" "Low,High"
bitfld.long 0x0 16. " PHASE ,SPI data format 0 clock delay" "Disabled,Enabled"
textline " "
hexmask.long.byte 0x0 8.--15. 1. " PRESCALE ,SPI data format 0 prescaler"
bitfld.long 0x0 0.--4. " CHARLEN ,SPI data format 0 data-word length" ",,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,?..."
line.long 0x4 "SPIFMT1,SPI Data Format Register 1"
sif cpuis("TMS570LC4357")
hexmask.long.byte 0x4 24.--31. 1. " WDELAY ,Delay in between transmissions for data format 1"
else
bitfld.long 0x4 24.--29. " WDELAY ,Delay in between transmissions for data format 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
endif
bitfld.long 0x4 23. " PARPOL ,Parity polarity: even or odd" "Even,Odd"
textline " "
bitfld.long 0x4 22. " PARITYENA ,Parity enable for data format 1" "Disabled,Enabled"
bitfld.long 0x4 20. " SHIFTDIR ,Shift direction for data format $" "MSB,LSB"
textline " "
sif cpuis("TMS570LC4357")
bitfld.long 0x4 19. " HDUPLEX_ENA1 ,Half Duplex transfer mode enable for Data Format 1" "Normal,TX"
endif
textline " "
bitfld.long 0x4 18. " DISCSTIMERS ,Disable chip-select timers for this format" "No,Yes"
textline " "
bitfld.long 0x4 17. " POLARITY ,SPI data format 1 clock polarity" "Low,High"
bitfld.long 0x4 16. " PHASE ,SPI data format 1 clock delay" "Disabled,Enabled"
textline " "
hexmask.long.byte 0x4 8.--15. 1. " PRESCALE ,SPI data format 1 prescaler"
bitfld.long 0x4 0.--4. " CHARLEN ,SPI data format 1 data-word length" ",,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,?..."
line.long 0x8 "SPIFMT2,SPI Data Format Register 2"
sif cpuis("TMS570LC4357")
hexmask.long.byte 0x8 24.--31. 1. " WDELAY ,Delay in between transmissions for data format 2"
else
bitfld.long 0x8 24.--29. " WDELAY ,Delay in between transmissions for data format 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
endif
bitfld.long 0x8 23. " PARPOL ,Parity polarity: even or odd" "Even,Odd"
textline " "
bitfld.long 0x8 22. " PARITYENA ,Parity enable for data format 2" "Disabled,Enabled"
bitfld.long 0x8 20. " SHIFTDIR ,Shift direction for data format $" "MSB,LSB"
textline " "
sif cpuis("TMS570LC4357")
bitfld.long 0x8 19. " HDUPLEX_ENA2 ,Half Duplex transfer mode enable for Data Format 2" "Normal,TX"
endif
textline " "
bitfld.long 0x8 18. " DISCSTIMERS ,Disable chip-select timers for this format" "No,Yes"
textline " "
bitfld.long 0x8 17. " POLARITY ,SPI data format 2 clock polarity" "Low,High"
bitfld.long 0x8 16. " PHASE ,SPI data format 2 clock delay" "Disabled,Enabled"
textline " "
hexmask.long.byte 0x8 8.--15. 1. " PRESCALE ,SPI data format 2 prescaler"
bitfld.long 0x8 0.--4. " CHARLEN ,SPI data format 2 data-word length" ",,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,?..."
line.long 0xC "SPIFMT3,SPI Data Format Register 3"
sif cpuis("TMS570LC4357")
hexmask.long.byte 0xC 24.--31. 1. " WDELAY ,Delay in between transmissions for data format 3"
else
bitfld.long 0xC 24.--29. " WDELAY ,Delay in between transmissions for data format 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
endif
bitfld.long 0xC 23. " PARPOL ,Parity polarity: even or odd" "Even,Odd"
textline " "
bitfld.long 0xC 22. " PARITYENA ,Parity enable for data format 3" "Disabled,Enabled"
bitfld.long 0xC 20. " SHIFTDIR ,Shift direction for data format $" "MSB,LSB"
textline " "
sif cpuis("TMS570LC4357")
bitfld.long 0xC 19. " HDUPLEX_ENA3 ,Half Duplex transfer mode enable for Data Format 3" "Normal,TX"
endif
textline " "
bitfld.long 0xC 18. " DISCSTIMERS ,Disable chip-select timers for this format" "No,Yes"
textline " "
bitfld.long 0xC 17. " POLARITY ,SPI data format 3 clock polarity" "Low,High"
bitfld.long 0xC 16. " PHASE ,SPI data format 3 clock delay" "Disabled,Enabled"
textline " "
hexmask.long.byte 0xC 8.--15. 1. " PRESCALE ,SPI data format 3 prescaler"
bitfld.long 0xC 0.--4. " CHARLEN ,SPI data format 3 data-word length" ",,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,?..."
else
group.long 0x50++0x0F
line.long 0x0 "SPIFMT0,SPI Data Format Register 0"
sif cpuis("TMS570LC4357")
hexmask.long.byte 0x0 24.--31. 1. " WDELAY ,Delay in between transmissions for data format 0"
else
bitfld.long 0x0 24.--29. " WDELAY ,Delay in between transmissions for data format 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
endif
bitfld.long 0x0 23. " PARPOL ,Parity polarity: even or odd" "Even,Odd"
textline " "
bitfld.long 0x0 22. " PARITYENA ,Parity enable for data format 0" "Disabled,Enabled"
bitfld.long 0x0 21. " WAITENA ,The master waits for the ENA signal from slave for data format 0" "Disabled,Enabled"
textline " "
bitfld.long 0x0 20. " SHIFTDIR ,Shift direction for data format $" "MSB,LSB"
sif cpuis("TMS570LC4357")
bitfld.long 0x0 19. " HDUPLEX_ENA0 ,Half Duplex transfer mode enable for Data Format 0" "Normal,RX"
endif
textline " "
bitfld.long 0x0 18. " DISCSTIMERS ,Disable chip-select timers for this format" "No,Yes"
textline " "
bitfld.long 0x0 17. " POLARITY ,SPI data format 0 clock polarity" "Low,High"
bitfld.long 0x0 16. " PHASE ,SPI data format 0 clock delay" "Disabled,Enabled"
textline " "
hexmask.long.byte 0x0 8.--15. 1. " PRESCALE ,SPI data format 0 prescaler"
bitfld.long 0x0 0.--4. " CHARLEN ,SPI data format 0 data-word length" ",,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,?..."
line.long 0x4 "SPIFMT1,SPI Data Format Register 1"
sif cpuis("TMS570LC4357")
hexmask.long.byte 0x4 24.--31. 1. " WDELAY ,Delay in between transmissions for data format 1"
else
bitfld.long 0x4 24.--29. " WDELAY ,Delay in between transmissions for data format 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
endif
bitfld.long 0x4 23. " PARPOL ,Parity polarity: even or odd" "Even,Odd"
textline " "
bitfld.long 0x4 22. " PARITYENA ,Parity enable for data format 1" "Disabled,Enabled"
bitfld.long 0x4 21. " WAITENA ,The master waits for the ENA signal from slave for data format 1" "Disabled,Enabled"
textline " "
bitfld.long 0x4 20. " SHIFTDIR ,Shift direction for data format $" "MSB,LSB"
sif cpuis("TMS570LC4357")
bitfld.long 0x4 19. " HDUPLEX_ENA1 ,Half Duplex transfer mode enable for Data Format 1" "Normal,RX"
endif
textline " "
bitfld.long 0x4 18. " DISCSTIMERS ,Disable chip-select timers for this format" "No,Yes"
textline " "
bitfld.long 0x4 17. " POLARITY ,SPI data format 1 clock polarity" "Low,High"
bitfld.long 0x4 16. " PHASE ,SPI data format 1 clock delay" "Disabled,Enabled"
textline " "
hexmask.long.byte 0x4 8.--15. 1. " PRESCALE ,SPI data format 1 prescaler"
bitfld.long 0x4 0.--4. " CHARLEN ,SPI data format 1 data-word length" ",,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,?..."
line.long 0x8 "SPIFMT2,SPI Data Format Register 2"
sif cpuis("TMS570LC4357")
hexmask.long.byte 0x8 24.--31. 1. " WDELAY ,Delay in between transmissions for data format 2"
else
bitfld.long 0x8 24.--29. " WDELAY ,Delay in between transmissions for data format 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
endif
bitfld.long 0x8 23. " PARPOL ,Parity polarity: even or odd" "Even,Odd"
textline " "
bitfld.long 0x8 22. " PARITYENA ,Parity enable for data format 2" "Disabled,Enabled"
bitfld.long 0x8 21. " WAITENA ,The master waits for the ENA signal from slave for data format 2" "Disabled,Enabled"
textline " "
bitfld.long 0x8 20. " SHIFTDIR ,Shift direction for data format $" "MSB,LSB"
sif cpuis("TMS570LC4357")
bitfld.long 0x8 19. " HDUPLEX_ENA2 ,Half Duplex transfer mode enable for Data Format 2" "Normal,RX"
endif
textline " "
bitfld.long 0x8 18. " DISCSTIMERS ,Disable chip-select timers for this format" "No,Yes"
textline " "
bitfld.long 0x8 17. " POLARITY ,SPI data format 2 clock polarity" "Low,High"
bitfld.long 0x8 16. " PHASE ,SPI data format 2 clock delay" "Disabled,Enabled"
textline " "
hexmask.long.byte 0x8 8.--15. 1. " PRESCALE ,SPI data format 2 prescaler"
bitfld.long 0x8 0.--4. " CHARLEN ,SPI data format 2 data-word length" ",,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,?..."
line.long 0xC "SPIFMT3,SPI Data Format Register 3"
sif cpuis("TMS570LC4357")
hexmask.long.byte 0xC 24.--31. 1. " WDELAY ,Delay in between transmissions for data format 3"
else
bitfld.long 0xC 24.--29. " WDELAY ,Delay in between transmissions for data format 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
endif
bitfld.long 0xC 23. " PARPOL ,Parity polarity: even or odd" "Even,Odd"
textline " "
bitfld.long 0xC 22. " PARITYENA ,Parity enable for data format 3" "Disabled,Enabled"
bitfld.long 0xC 21. " WAITENA ,The master waits for the ENA signal from slave for data format 3" "Disabled,Enabled"
textline " "
bitfld.long 0xC 20. " SHIFTDIR ,Shift direction for data format $" "MSB,LSB"
sif cpuis("TMS570LC4357")
bitfld.long 0xC 19. " HDUPLEX_ENA3 ,Half Duplex transfer mode enable for Data Format 3" "Normal,RX"
endif
textline " "
bitfld.long 0xC 18. " DISCSTIMERS ,Disable chip-select timers for this format" "No,Yes"
textline " "
bitfld.long 0xC 17. " POLARITY ,SPI data format 3 clock polarity" "Low,High"
bitfld.long 0xC 16. " PHASE ,SPI data format 3 clock delay" "Disabled,Enabled"
textline " "
hexmask.long.byte 0xC 8.--15. 1. " PRESCALE ,SPI data format 3 prescaler"
bitfld.long 0xC 0.--4. " CHARLEN ,SPI data format 3 data-word length" ",,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,?..."
endif
hgroup.long 0x60++0x03
hide.long 0x00 "TGINTVECT0,SPI Interrupt Vector Register 0 / MibSPI Transfer Group Interrupt Vector Register 0"
in
hgroup.long 0x64++0x03
hide.long 0x00 "TGINTVECT1,SPI Interrupt Vector Register 1 / MibSPI Transfer Group Interrupt Vector Register 1"
in
group.long 0x6C++0x07
line.long 0x00 "SPIPMCTRL,SPI Parallel/Modulo Mode Control Register"
bitfld.long 0x00 29. " MODCLKPOL3 ,Modulo mode SPICLK polarity" "Normal,Inverted"
bitfld.long 0x00 26.--28. " MMODE3 ,SPI/MibSPI data lines" "1,2,3,4,5,6,?..."
bitfld.long 0x00 24.--25. " PMODE3 ,Parallel mode data lines" "1,2,4,8"
textline " "
bitfld.long 0x00 21. " MODCLKPOL2 ,Modulo mode SPICLK polarity" "Normal,Inverted"
bitfld.long 0x00 18.--20. " MMODE2 ,SPI/MibSPI data lines" "1,2,3,4,5,6,?..."
bitfld.long 0x00 16.--17. " PMODE2 ,Parallel mode data lines" "1,2,4,8"
textline " "
bitfld.long 0x00 13. " MODCLKPOL1 ,Modulo mode SPICLK polarity" "Normal,Inverted"
bitfld.long 0x00 10.--12. " MMODE1 ,SPI/MibSPI data lines" "1,2,3,4,5,6,?..."
bitfld.long 0x00 8.--9. " PMODE1 ,Parallel mode data lines" "1,2,4,8"
textline " "
bitfld.long 0x00 5. " MODCLKPOL0 ,Modulo mode SPICLK polarity" "Normal,Inverted"
bitfld.long 0x00 2.--4. " MMODE0 ,SPI/MibSPI data lines" "1,2,3,4,5,6,?..."
bitfld.long 0x00 0.--1. " PMODE0 ,Parallel mode data lines" "1,2,4,8"
line.long 0x04 "MIBSPIE,MibSPI Enable Register"
bitfld.long 0x04 16. " RXRAMACCESS ,Receive-RAM access control" "Not writable,Accessible"
bitfld.long 0x04 0. " MIBSPIENA ,Multi-buffer mode enable" "Disabled,Enabled"
textline " "
width 17.
group.long 0x74++0x0F
line.long 0x00 "TGITENST,MibSPI Transfer Group Interrupt Enable Set Register"
bitfld.long 0x00 31. " SETINTENRDY[15] ,TG interrupt set (enable) when transfer finished" "Disabled,Enabled"
bitfld.long 0x00 30. " [14] ,TG interrupt set (enable) when transfer finished" "Disabled,Enabled"
bitfld.long 0x00 29. " [13] ,TG interrupt set (enable) when transfer finished" "Disabled,Enabled"
textline " "
bitfld.long 0x00 28. " [12] ,TG interrupt set (enable) when transfer finished" "Disabled,Enabled"
bitfld.long 0x00 27. " [11] ,TG interrupt set (enable) when transfer finished" "Disabled,Enabled"
bitfld.long 0x00 26. " [10] ,TG interrupt set (enable) when transfer finished" "Disabled,Enabled"
textline " "
bitfld.long 0x00 25. " [9] ,TG interrupt set (enable) when transfer finished" "Disabled,Enabled"
bitfld.long 0x00 24. " [8] ,TG interrupt set (enable) when transfer finished" "Disabled,Enabled"
bitfld.long 0x00 23. " [7] ,TG interrupt set (enable) when transfer finished" "Disabled,Enabled"
textline " "
bitfld.long 0x00 22. " [6] ,TG interrupt set (enable) when transfer finished" "Disabled,Enabled"
bitfld.long 0x00 21. " [5] ,TG interrupt set (enable) when transfer finished" "Disabled,Enabled"
bitfld.long 0x00 20. " [4] ,TG interrupt set (enable) when transfer finished" "Disabled,Enabled"
textline " "
bitfld.long 0x00 19. " [3] ,TG interrupt set (enable) when transfer finished" "Disabled,Enabled"
bitfld.long 0x00 18. " [2] ,TG interrupt set (enable) when transfer finished" "Disabled,Enabled"
bitfld.long 0x00 17. " [1] ,TG interrupt set (enable) when transfer finished" "Disabled,Enabled"
textline " "
bitfld.long 0x00 16. " [0] ,TG interrupt set (enable) when transfer finished" "Disabled,Enabled"
textline " "
bitfld.long 0x00 15. " SETINTENSUS[15] ,TG interrupt set (enabled) when transfer suspended" "Disabled,Enabled"
bitfld.long 0x00 14. " [14] ,TG interrupt set (enabled) when transfer suspended" "Disabled,Enabled"
bitfld.long 0x00 13. " [13] ,TG interrupt set (enabled) when transfer suspended" "Disabled,Enabled"
textline " "
bitfld.long 0x00 12. " [12] ,TG interrupt set (enabled) when transfer suspended" "Disabled,Enabled"
bitfld.long 0x00 11. " [11] ,TG interrupt set (enabled) when transfer suspended" "Disabled,Enabled"
bitfld.long 0x00 10. " [10] ,TG interrupt set (enabled) when transfer suspended" "Disabled,Enabled"
textline " "
bitfld.long 0x00 9. " [9] ,TG interrupt set (enabled) when transfer suspended" "Disabled,Enabled"
bitfld.long 0x00 8. " [8] ,TG interrupt set (enabled) when transfer suspended" "Disabled,Enabled"
bitfld.long 0x00 7. " [7] ,TG interrupt set (enabled) when transfer suspended" "Disabled,Enabled"
textline " "
bitfld.long 0x00 6. " [6] ,TG interrupt set (enabled) when transfer suspended" "Disabled,Enabled"
bitfld.long 0x00 5. " [5] ,TG interrupt set (enabled) when transfer suspended" "Disabled,Enabled"
bitfld.long 0x00 4. " [4] ,TG interrupt set (enabled) when transfer suspended" "Disabled,Enabled"
textline " "
bitfld.long 0x00 3. " [3] ,TG interrupt set (enabled) when transfer suspended" "Disabled,Enabled"
bitfld.long 0x00 2. " [2] ,TG interrupt set (enabled) when transfer suspended" "Disabled,Enabled"
bitfld.long 0x00 1. " [1] ,TG interrupt set (enabled) when transfer suspended" "Disabled,Enabled"
textline " "
bitfld.long 0x00 0. " [0] ,TG interrupt set (enabled) when transfer suspended" "Disabled,Enabled"
line.long 0x04 "TGITENCR,MibSPI Transfer Group Interrupt Enable Clear Register"
bitfld.long 0x04 31. " CLRINTENRDY[15] ,TG interrupt clear (disabled) when transfer finished" "Disabled,Enabled"
bitfld.long 0x04 30. " [14] ,TG interrupt clear (disabled) when transfer finished" "Disabled,Enabled"
bitfld.long 0x04 29. " [13] ,TG interrupt clear (disabled) when transfer finished" "Disabled,Enabled"
textline " "
bitfld.long 0x04 28. " [12] ,TG interrupt clear (disabled) when transfer finished" "Disabled,Enabled"
bitfld.long 0x04 27. " [11] ,TG interrupt clear (disabled) when transfer finished" "Disabled,Enabled"
bitfld.long 0x04 26. " [10] ,TG interrupt clear (disabled) when transfer finished" "Disabled,Enabled"
textline " "
bitfld.long 0x04 25. " [9] ,TG interrupt clear (disabled) when transfer finished" "Disabled,Enabled"
bitfld.long 0x04 24. " [8] ,TG interrupt clear (disabled) when transfer finished" "Disabled,Enabled"
bitfld.long 0x04 23. " [7] ,TG interrupt clear (disabled) when transfer finished" "Disabled,Enabled"
textline " "
bitfld.long 0x04 22. " [6] ,TG interrupt clear (disabled) when transfer finished" "Disabled,Enabled"
bitfld.long 0x04 21. " [5] ,TG interrupt clear (disabled) when transfer finished" "Disabled,Enabled"
bitfld.long 0x04 20. " [4] ,TG interrupt clear (disabled) when transfer finished" "Disabled,Enabled"
textline " "
bitfld.long 0x04 19. " [3] ,TG interrupt clear (disabled) when transfer finished" "Disabled,Enabled"
bitfld.long 0x04 18. " [2] ,TG interrupt clear (disabled) when transfer finished" "Disabled,Enabled"
bitfld.long 0x04 17. " [1] ,TG interrupt clear (disabled) when transfer finished" "Disabled,Enabled"
textline " "
bitfld.long 0x04 16. " [0] ,TG interrupt clear (disabled) when transfer finished" "Disabled,Enabled"
textline " "
bitfld.long 0x04 15. " CLRINTENSUS[15] ,TG interrupt clear (disabled) when transfer suspended" "Disabled,Enabled"
bitfld.long 0x04 14. " [14] ,TG interrupt clear (disabled) when transfer suspended" "Disabled,Enabled"
bitfld.long 0x04 13. " [13] ,TG interrupt clear (disabled) when transfer suspended" "Disabled,Enabled"
textline " "
bitfld.long 0x04 12. " [12] ,TG interrupt clear (disabled) when transfer suspended" "Disabled,Enabled"
bitfld.long 0x04 11. " [11] ,TG interrupt clear (disabled) when transfer suspended" "Disabled,Enabled"
bitfld.long 0x04 10. " [10] ,TG interrupt clear (disabled) when transfer suspended" "Disabled,Enabled"
textline " "
bitfld.long 0x04 9. " [9] ,TG interrupt clear (disabled) when transfer suspended" "Disabled,Enabled"
bitfld.long 0x04 8. " [8] ,TG interrupt clear (disabled) when transfer suspended" "Disabled,Enabled"
bitfld.long 0x04 7. " [7] ,TG interrupt clear (disabled) when transfer suspended" "Disabled,Enabled"
textline " "
bitfld.long 0x04 6. " [6] ,TG interrupt clear (disabled) when transfer suspended" "Disabled,Enabled"
bitfld.long 0x04 5. " [5] ,TG interrupt clear (disabled) when transfer suspended" "Disabled,Enabled"
bitfld.long 0x04 4. " [4] ,TG interrupt clear (disabled) when transfer suspended" "Disabled,Enabled"
textline " "
bitfld.long 0x04 3. " [3] ,TG interrupt clear (disabled) when transfer suspended" "Disabled,Enabled"
bitfld.long 0x04 2. " [2] ,TG interrupt clear (disabled) when transfer suspended" "Disabled,Enabled"
bitfld.long 0x04 1. " [1] ,TG interrupt clear (disabled) when transfer suspended" "Disabled,Enabled"
textline " "
bitfld.long 0x04 0. " [0] ,TG interrupt clear (disabled) when transfer suspended" "Disabled,Enabled"
textline " "
line.long 0x08 "TGITLVST,MibSPI Transfer Group Interrupt Level Set Register"
bitfld.long 0x08 31. " SETINTLVLRDY[15] ,Transfer-group completed interrupt level set" "INT0,INT1"
bitfld.long 0x08 30. " [14] ,Transfer-group completed interrupt level set" "INT0,INT1"
bitfld.long 0x08 29. " [13] ,Transfer-group completed interrupt level set" "INT0,INT1"
bitfld.long 0x08 28. " [12] ,Transfer-group completed interrupt level set" "INT0,INT1"
bitfld.long 0x08 27. " [11] ,Transfer-group completed interrupt level set" "INT0,INT1"
bitfld.long 0x08 26. " [10] ,Transfer-group completed interrupt level set" "INT0,INT1"
textline " "
bitfld.long 0x08 25. " [9] ,Transfer-group completed interrupt level set" "INT0,INT1"
bitfld.long 0x08 24. " [8] ,Transfer-group completed interrupt level set" "INT0,INT1"
bitfld.long 0x08 23. " [7] ,Transfer-group completed interrupt level set" "INT0,INT1"
bitfld.long 0x08 22. " [6] ,Transfer-group completed interrupt level set" "INT0,INT1"
bitfld.long 0x08 21. " [5] ,Transfer-group completed interrupt level set" "INT0,INT1"
bitfld.long 0x08 20. " [4] ,Transfer-group completed interrupt level set" "INT0,INT1"
textline " "
bitfld.long 0x08 19. " [3] ,Transfer-group completed interrupt level set" "INT0,INT1"
bitfld.long 0x08 18. " [2] ,Transfer-group completed interrupt level set" "INT0,INT1"
bitfld.long 0x08 17. " [1] ,Transfer-group completed interrupt level set" "INT0,INT1"
bitfld.long 0x08 16. " [0] ,Transfer-group completed interrupt level set" "INT0,INT1"
textline " "
bitfld.long 0x08 15. " SETINTLVLSUS[15] ,Transfer-group suspended interrupt level set" "INT0,INT1"
bitfld.long 0x08 14. " [14] ,Transfer-group suspended interrupt level set" "INT0,INT1"
bitfld.long 0x08 13. " [13] ,Transfer-group suspended interrupt level set" "INT0,INT1"
bitfld.long 0x08 12. " [12] ,Transfer-group suspended interrupt level set" "INT0,INT1"
bitfld.long 0x08 11. " [11] ,Transfer-group suspended interrupt level set" "INT0,INT1"
bitfld.long 0x08 10. " [10] ,Transfer-group suspended interrupt level set" "INT0,INT1"
textline " "
bitfld.long 0x08 9. " [9] ,Transfer-group suspended interrupt level set" "INT0,INT1"
bitfld.long 0x08 8. " [8] ,Transfer-group suspended interrupt level set" "INT0,INT1"
bitfld.long 0x08 7. " [7] ,Transfer-group suspended interrupt level set" "INT0,INT1"
bitfld.long 0x08 6. " [6] ,Transfer-group suspended interrupt level set" "INT0,INT1"
bitfld.long 0x08 5. " [5] ,Transfer-group suspended interrupt level set" "INT0,INT1"
bitfld.long 0x08 4. " [4] ,Transfer-group suspended interrupt level set" "INT0,INT1"
textline " "
bitfld.long 0x08 3. " [3] ,Transfer-group suspended interrupt level set" "INT0,INT1"
bitfld.long 0x08 2. " [2] ,Transfer-group suspended interrupt level set" "INT0,INT1"
bitfld.long 0x08 1. " [1] ,Transfer-group suspended interrupt level set" "INT0,INT1"
bitfld.long 0x08 0. " [0] ,Transfer-group suspended interrupt level set" "INT0,INT1"
line.long 0x0C "TGITLVCR,MibSPI Transfer Group Interrupt Level Clear Register"
bitfld.long 0x0C 31. " CLRINTLVLRDY[15] ,Transfer-group completed interrupt level clear" "INT0,INT1"
bitfld.long 0x0C 30. " [14] ,Transfer-group completed interrupt level clear" "INT0,INT1"
bitfld.long 0x0C 29. " [13] ,Transfer-group completed interrupt level clear" "INT0,INT1"
bitfld.long 0x0C 28. " [12] ,Transfer-group completed interrupt level clear" "INT0,INT1"
bitfld.long 0x0C 27. " [11] ,Transfer-group completed interrupt level clear" "INT0,INT1"
bitfld.long 0x0C 26. " [10] ,Transfer-group completed interrupt level clear" "INT0,INT1"
textline " "
bitfld.long 0x0C 25. " [9] ,Transfer-group completed interrupt level clear" "INT0,INT1"
bitfld.long 0x0C 24. " [8] ,Transfer-group completed interrupt level clear" "INT0,INT1"
bitfld.long 0x0C 23. " [7] ,Transfer-group completed interrupt level clear" "INT0,INT1"
bitfld.long 0x0C 22. " [6] ,Transfer-group completed interrupt level clear" "INT0,INT1"
bitfld.long 0x0C 21. " [5] ,Transfer-group completed interrupt level clear" "INT0,INT1"
bitfld.long 0x0C 20. " [4] ,Transfer-group completed interrupt level clear" "INT0,INT1"
textline " "
bitfld.long 0x0C 19. " [3] ,Transfer-group completed interrupt level clear" "INT0,INT1"
bitfld.long 0x0C 18. " [2] ,Transfer-group completed interrupt level clear" "INT0,INT1"
bitfld.long 0x0C 17. " [1] ,Transfer-group completed interrupt level clear" "INT0,INT1"
bitfld.long 0x0C 16. " [0] ,Transfer-group completed interrupt level clear" "INT0,INT1"
textline " "
bitfld.long 0x0C 15. " CLRINTLVLSUS[15] ,Transfer group suspended interrupt level clear" "INT0,INT1"
bitfld.long 0x0C 14. " [14] ,Transfer group suspended interrupt level clear" "INT0,INT1"
bitfld.long 0x0C 13. " [13] ,Transfer group suspended interrupt level clear" "INT0,INT1"
bitfld.long 0x0C 12. " [12] ,Transfer group suspended interrupt level clear" "INT0,INT1"
bitfld.long 0x0C 11. " [11] ,Transfer group suspended interrupt level clear" "INT0,INT1"
bitfld.long 0x0C 10. " [10] ,Transfer group suspended interrupt level clear" "INT0,INT1"
textline " "
bitfld.long 0x0C 9. " [9] ,Transfer group suspended interrupt level clear" "INT0,INT1"
bitfld.long 0x0C 8. " [8] ,Transfer group suspended interrupt level clear" "INT0,INT1"
bitfld.long 0x0C 7. " [7] ,Transfer group suspended interrupt level clear" "INT0,INT1"
bitfld.long 0x0C 6. " [6] ,Transfer group suspended interrupt level clear" "INT0,INT1"
bitfld.long 0x0C 5. " [5] ,Transfer group suspended interrupt level clear" "INT0,INT1"
bitfld.long 0x0C 4. " [4] ,Transfer group suspended interrupt level clear" "INT0,INT1"
textline " "
bitfld.long 0x0C 3. " [3] ,Transfer group suspended interrupt level clear" "INT0,INT1"
bitfld.long 0x0C 2. " [2] ,Transfer group suspended interrupt level clear" "INT0,INT1"
bitfld.long 0x0C 1. " [1] ,Transfer group suspended interrupt level clear" "INT0,INT1"
bitfld.long 0x0C 0. " [0] ,Transfer group suspended interrupt level clear" "INT0,INT1"
textline " "
group.long 0x84++0x03
line.long 0x00 "TGITFLG,Transfer Group Interrupt Flag Register"
sif cpuis("TMS570LC4357")
bitfld.long 0x00 31. " INTFLGRDY[15] ,Transfer-group interrupt flag for a transfer-completed interrupt 15" "Disabled,Enabled"
bitfld.long 0x00 30. " [14] ,Transfer-group interrupt flag for a transfer-completed interrupt 14" "Disabled,Enabled"
bitfld.long 0x00 29. " [13] ,Transfer-group interrupt flag for a transfer-completed interrupt 13" "Disabled,Enabled"
bitfld.long 0x00 28. " [12] ,Transfer-group interrupt flag for a transfer-completed interrupt 12" "Disabled,Enabled"
textline " "
bitfld.long 0x00 27. " [11] ,Transfer-group interrupt flag for a transfer-completed interrupt 11" "Disabled,Enabled"
bitfld.long 0x00 26. " [10] ,Transfer-group interrupt flag for a transfer-completed interrupt 10" "Disabled,Enabled"
bitfld.long 0x00 25. " [9] ,Transfer-group interrupt flag for a transfer-completed interrupt 9" "Disabled,Enabled"
bitfld.long 0x00 24. " [8] ,Transfer-group interrupt flag for a transfer-completed interrupt 8" "Disabled,Enabled"
textline " "
bitfld.long 0x00 23. " [7] ,Transfer-group interrupt flag for a transfer-completed interrupt 7" "Disabled,Enabled"
bitfld.long 0x00 22. " [6] ,Transfer-group interrupt flag for a transfer-completed interrupt 6" "Disabled,Enabled"
bitfld.long 0x00 21. " [5] ,Transfer-group interrupt flag for a transfer-completed interrupt 5" "Disabled,Enabled"
bitfld.long 0x00 20. " [4] ,Transfer-group interrupt flag for a transfer-completed interrupt 4" "Disabled,Enabled"
textline " "
bitfld.long 0x00 19. " [3] ,Transfer-group interrupt flag for a transfer-completed interrupt 3" "Disabled,Enabled"
bitfld.long 0x00 18. " [2] ,Transfer-group interrupt flag for a transfer-completed interrupt 2" "Disabled,Enabled"
bitfld.long 0x00 17. " [1] ,Transfer-group interrupt flag for a transfer-completed interrupt 1" "Disabled,Enabled"
bitfld.long 0x00 16. " [0] ,Transfer-group interrupt flag for a transfer-completed interrupt 0" "Disabled,Enabled"
textline " "
endif
bitfld.long 0x00 15. " INTFLGSUS[15] ,Transfer-group interrupt flag for a transfer-suspend interrupt 15" "Disabled,Enabled"
bitfld.long 0x00 14. " [14] ,Transfer-group interrupt flag for a transfer-suspend interrupt 14" "Disabled,Enabled"
bitfld.long 0x00 13. " [13] ,Transfer-group interrupt flag for a transfer-suspend interrupt 13" "Disabled,Enabled"
bitfld.long 0x00 12. " [12] ,Transfer-group interrupt flag for a transfer-suspend interrupt 12" "Disabled,Enabled"
textline " "
bitfld.long 0x00 11. " [11] ,Transfer-group interrupt flag for a transfer-suspend interrupt 11" "Disabled,Enabled"
bitfld.long 0x00 10. " [10] ,Transfer-group interrupt flag for a transfer-suspend interrupt 10" "Disabled,Enabled"
bitfld.long 0x00 9. " [9] ,Transfer-group interrupt flag for a transfer-suspend interrupt 9" "Disabled,Enabled"
bitfld.long 0x00 8. " [8] ,Transfer-group interrupt flag for a transfer-suspend interrupt 8" "Disabled,Enabled"
textline " "
bitfld.long 0x00 7. " [7] ,Transfer-group interrupt flag for a transfer-suspend interrupt 7" "Disabled,Enabled"
bitfld.long 0x00 6. " [6] ,Transfer-group interrupt flag for a transfer-suspend interrupt 6" "Disabled,Enabled"
bitfld.long 0x00 5. " [5] ,Transfer-group interrupt flag for a transfer-suspend interrupt 5" "Disabled,Enabled"
bitfld.long 0x00 4. " [4] ,Transfer-group interrupt flag for a transfer-suspend interrupt 4" "Disabled,Enabled"
textline " "
bitfld.long 0x00 3. " [3] ,Transfer-group interrupt flag for a transfer-suspend interrupt 3" "Disabled,Enabled"
bitfld.long 0x00 2. " [2] ,Transfer-group interrupt flag for a transfer-suspend interrupt 2" "Disabled,Enabled"
bitfld.long 0x00 1. " [1] ,Transfer-group interrupt flag for a transfer-suspend interrupt 1" "Disabled,Enabled"
bitfld.long 0x00 0. " [0] ,Transfer-group interrupt flag for a transfer-suspend interrupt 0" "Disabled,Enabled"
textline " "
group.long 0x90++0x47
line.long 0x00 "TICKCNT,Tick Count Register"
bitfld.long 0x00 31. " TICKENA ,Tick counter enable" "Disabled,Enabled"
bitfld.long 0x00 30. " RELOAD ,Pre-load the tick counter" "No effect,Reload"
bitfld.long 0x00 28.--29. " CLKCTRL ,Tick counter clock source control" "0,1,2,3"
textline " "
hexmask.long.word 0x00 0.--15. 1. " TICKVALUE ,Initial value for the tick counter"
line.long 0x04 "LTGPEND,Last Transfer Group End Pointer Register"
rbitfld.long 0x04 24.--28. " TGINSERVICE ,The TG number currently being serviced by the sequencer" "No TG,TG0,TG1,TG2,TG3,TG4,TG5,TG6,TG7,TG8,TG9,TG10,TG11,TG12,TG13,TG14,TG15,?..."
hexmask.long.byte 0x04 8.--14. 1. " LPEND ,Last TG end pointer"
line.long 0x8 "TG1CTRL,MibSPI Transfer Group Control Register 1"
bitfld.long 0x8 31. " TGENA ,TG enable" "Disabled,Enabled"
bitfld.long 0x8 30. " ONESHOT ,Single transfer for TG" "Disabled,Enabled"
bitfld.long 0x8 29. " PRST ,TG pointer reset mode" "Disabled,Enabled"
textline " "
rbitfld.long 0x8 28. " TGTD ,TG triggered" "Not triggered,Triggered"
bitfld.long 0x8 20.--23. " TRGEVT ,Type of trigger event" "Never,Rising edge,Falling edge,Both edges,,High active,Low-active,Always,?..."
bitfld.long 0x8 16.--19. " TRIGSRC ,Trigger source" "Disabled,EXT[0],EXT[1],EXT[2],EXT[3],EXT[4],EXT[5],EXT[6],EXT[7],EXT[8],EXT[9,EXT[10,EXT[11,EXT[12,EXT[13],TICK"
textline " "
hexmask.long.byte 0x8 8.--14. 1. " PSTART ,TG start address"
hexmask.long.byte 0x8 0.--6. 1. " PCURRENT ,Pointer to current buffer"
line.long 0xC "TG2CTRL,MibSPI Transfer Group Control Register 2"
bitfld.long 0xC 31. " TGENA ,TG enable" "Disabled,Enabled"
bitfld.long 0xC 30. " ONESHOT ,Single transfer for TG" "Disabled,Enabled"
bitfld.long 0xC 29. " PRST ,TG pointer reset mode" "Disabled,Enabled"
textline " "
rbitfld.long 0xC 28. " TGTD ,TG triggered" "Not triggered,Triggered"
bitfld.long 0xC 20.--23. " TRGEVT ,Type of trigger event" "Never,Rising edge,Falling edge,Both edges,,High active,Low-active,Always,?..."
bitfld.long 0xC 16.--19. " TRIGSRC ,Trigger source" "Disabled,EXT[0],EXT[1],EXT[2],EXT[3],EXT[4],EXT[5],EXT[6],EXT[7],EXT[8],EXT[9,EXT[10,EXT[11,EXT[12,EXT[13],TICK"
textline " "
hexmask.long.byte 0xC 8.--14. 1. " PSTART ,TG start address"
hexmask.long.byte 0xC 0.--6. 1. " PCURRENT ,Pointer to current buffer"
line.long 0x10 "TG3CTRL,MibSPI Transfer Group Control Register 3"
bitfld.long 0x10 31. " TGENA ,TG enable" "Disabled,Enabled"
bitfld.long 0x10 30. " ONESHOT ,Single transfer for TG" "Disabled,Enabled"
bitfld.long 0x10 29. " PRST ,TG pointer reset mode" "Disabled,Enabled"
textline " "
rbitfld.long 0x10 28. " TGTD ,TG triggered" "Not triggered,Triggered"
bitfld.long 0x10 20.--23. " TRGEVT ,Type of trigger event" "Never,Rising edge,Falling edge,Both edges,,High active,Low-active,Always,?..."
bitfld.long 0x10 16.--19. " TRIGSRC ,Trigger source" "Disabled,EXT[0],EXT[1],EXT[2],EXT[3],EXT[4],EXT[5],EXT[6],EXT[7],EXT[8],EXT[9,EXT[10,EXT[11,EXT[12,EXT[13],TICK"
textline " "
hexmask.long.byte 0x10 8.--14. 1. " PSTART ,TG start address"
hexmask.long.byte 0x10 0.--6. 1. " PCURRENT ,Pointer to current buffer"
line.long 0x14 "TG4CTRL,MibSPI Transfer Group Control Register 4"
bitfld.long 0x14 31. " TGENA ,TG enable" "Disabled,Enabled"
bitfld.long 0x14 30. " ONESHOT ,Single transfer for TG" "Disabled,Enabled"
bitfld.long 0x14 29. " PRST ,TG pointer reset mode" "Disabled,Enabled"
textline " "
rbitfld.long 0x14 28. " TGTD ,TG triggered" "Not triggered,Triggered"
bitfld.long 0x14 20.--23. " TRGEVT ,Type of trigger event" "Never,Rising edge,Falling edge,Both edges,,High active,Low-active,Always,?..."
bitfld.long 0x14 16.--19. " TRIGSRC ,Trigger source" "Disabled,EXT[0],EXT[1],EXT[2],EXT[3],EXT[4],EXT[5],EXT[6],EXT[7],EXT[8],EXT[9,EXT[10,EXT[11,EXT[12,EXT[13],TICK"
textline " "
hexmask.long.byte 0x14 8.--14. 1. " PSTART ,TG start address"
hexmask.long.byte 0x14 0.--6. 1. " PCURRENT ,Pointer to current buffer"
line.long 0x18 "TG5CTRL,MibSPI Transfer Group Control Register 5"
bitfld.long 0x18 31. " TGENA ,TG enable" "Disabled,Enabled"
bitfld.long 0x18 30. " ONESHOT ,Single transfer for TG" "Disabled,Enabled"
bitfld.long 0x18 29. " PRST ,TG pointer reset mode" "Disabled,Enabled"
textline " "
rbitfld.long 0x18 28. " TGTD ,TG triggered" "Not triggered,Triggered"
bitfld.long 0x18 20.--23. " TRGEVT ,Type of trigger event" "Never,Rising edge,Falling edge,Both edges,,High active,Low-active,Always,?..."
bitfld.long 0x18 16.--19. " TRIGSRC ,Trigger source" "Disabled,EXT[0],EXT[1],EXT[2],EXT[3],EXT[4],EXT[5],EXT[6],EXT[7],EXT[8],EXT[9,EXT[10,EXT[11,EXT[12,EXT[13],TICK"
textline " "
hexmask.long.byte 0x18 8.--14. 1. " PSTART ,TG start address"
hexmask.long.byte 0x18 0.--6. 1. " PCURRENT ,Pointer to current buffer"
line.long 0x1C "TG6CTRL,MibSPI Transfer Group Control Register 6"
bitfld.long 0x1C 31. " TGENA ,TG enable" "Disabled,Enabled"
bitfld.long 0x1C 30. " ONESHOT ,Single transfer for TG" "Disabled,Enabled"
bitfld.long 0x1C 29. " PRST ,TG pointer reset mode" "Disabled,Enabled"
textline " "
rbitfld.long 0x1C 28. " TGTD ,TG triggered" "Not triggered,Triggered"
bitfld.long 0x1C 20.--23. " TRGEVT ,Type of trigger event" "Never,Rising edge,Falling edge,Both edges,,High active,Low-active,Always,?..."
bitfld.long 0x1C 16.--19. " TRIGSRC ,Trigger source" "Disabled,EXT[0],EXT[1],EXT[2],EXT[3],EXT[4],EXT[5],EXT[6],EXT[7],EXT[8],EXT[9,EXT[10,EXT[11,EXT[12,EXT[13],TICK"
textline " "
hexmask.long.byte 0x1C 8.--14. 1. " PSTART ,TG start address"
hexmask.long.byte 0x1C 0.--6. 1. " PCURRENT ,Pointer to current buffer"
line.long 0x20 "TG7CTRL,MibSPI Transfer Group Control Register 7"
bitfld.long 0x20 31. " TGENA ,TG enable" "Disabled,Enabled"
bitfld.long 0x20 30. " ONESHOT ,Single transfer for TG" "Disabled,Enabled"
bitfld.long 0x20 29. " PRST ,TG pointer reset mode" "Disabled,Enabled"
textline " "
rbitfld.long 0x20 28. " TGTD ,TG triggered" "Not triggered,Triggered"
bitfld.long 0x20 20.--23. " TRGEVT ,Type of trigger event" "Never,Rising edge,Falling edge,Both edges,,High active,Low-active,Always,?..."
bitfld.long 0x20 16.--19. " TRIGSRC ,Trigger source" "Disabled,EXT[0],EXT[1],EXT[2],EXT[3],EXT[4],EXT[5],EXT[6],EXT[7],EXT[8],EXT[9,EXT[10,EXT[11,EXT[12,EXT[13],TICK"
textline " "
hexmask.long.byte 0x20 8.--14. 1. " PSTART ,TG start address"
hexmask.long.byte 0x20 0.--6. 1. " PCURRENT ,Pointer to current buffer"
line.long 0x24 "TG8CTRL,MibSPI Transfer Group Control Register 8"
bitfld.long 0x24 31. " TGENA ,TG enable" "Disabled,Enabled"
bitfld.long 0x24 30. " ONESHOT ,Single transfer for TG" "Disabled,Enabled"
bitfld.long 0x24 29. " PRST ,TG pointer reset mode" "Disabled,Enabled"
textline " "
rbitfld.long 0x24 28. " TGTD ,TG triggered" "Not triggered,Triggered"
bitfld.long 0x24 20.--23. " TRGEVT ,Type of trigger event" "Never,Rising edge,Falling edge,Both edges,,High active,Low-active,Always,?..."
bitfld.long 0x24 16.--19. " TRIGSRC ,Trigger source" "Disabled,EXT[0],EXT[1],EXT[2],EXT[3],EXT[4],EXT[5],EXT[6],EXT[7],EXT[8],EXT[9,EXT[10,EXT[11,EXT[12,EXT[13],TICK"
textline " "
hexmask.long.byte 0x24 8.--14. 1. " PSTART ,TG start address"
hexmask.long.byte 0x24 0.--6. 1. " PCURRENT ,Pointer to current buffer"
line.long 0x28 "TG9CTRL,MibSPI Transfer Group Control Register 9"
bitfld.long 0x28 31. " TGENA ,TG enable" "Disabled,Enabled"
bitfld.long 0x28 30. " ONESHOT ,Single transfer for TG" "Disabled,Enabled"
bitfld.long 0x28 29. " PRST ,TG pointer reset mode" "Disabled,Enabled"
textline " "
rbitfld.long 0x28 28. " TGTD ,TG triggered" "Not triggered,Triggered"
bitfld.long 0x28 20.--23. " TRGEVT ,Type of trigger event" "Never,Rising edge,Falling edge,Both edges,,High active,Low-active,Always,?..."
bitfld.long 0x28 16.--19. " TRIGSRC ,Trigger source" "Disabled,EXT[0],EXT[1],EXT[2],EXT[3],EXT[4],EXT[5],EXT[6],EXT[7],EXT[8],EXT[9,EXT[10,EXT[11,EXT[12,EXT[13],TICK"
textline " "
hexmask.long.byte 0x28 8.--14. 1. " PSTART ,TG start address"
hexmask.long.byte 0x28 0.--6. 1. " PCURRENT ,Pointer to current buffer"
line.long 0x2C "TG10CTRL,MibSPI Transfer Group Control Register 10"
bitfld.long 0x2C 31. " TGENA ,TG enable" "Disabled,Enabled"
bitfld.long 0x2C 30. " ONESHOT ,Single transfer for TG" "Disabled,Enabled"
bitfld.long 0x2C 29. " PRST ,TG pointer reset mode" "Disabled,Enabled"
textline " "
rbitfld.long 0x2C 28. " TGTD ,TG triggered" "Not triggered,Triggered"
bitfld.long 0x2C 20.--23. " TRGEVT ,Type of trigger event" "Never,Rising edge,Falling edge,Both edges,,High active,Low-active,Always,?..."
bitfld.long 0x2C 16.--19. " TRIGSRC ,Trigger source" "Disabled,EXT[0],EXT[1],EXT[2],EXT[3],EXT[4],EXT[5],EXT[6],EXT[7],EXT[8],EXT[9,EXT[10,EXT[11,EXT[12,EXT[13],TICK"
textline " "
hexmask.long.byte 0x2C 8.--14. 1. " PSTART ,TG start address"
hexmask.long.byte 0x2C 0.--6. 1. " PCURRENT ,Pointer to current buffer"
line.long 0x30 "TG11CTRL,MibSPI Transfer Group Control Register 11"
bitfld.long 0x30 31. " TGENA ,TG enable" "Disabled,Enabled"
bitfld.long 0x30 30. " ONESHOT ,Single transfer for TG" "Disabled,Enabled"
bitfld.long 0x30 29. " PRST ,TG pointer reset mode" "Disabled,Enabled"
textline " "
rbitfld.long 0x30 28. " TGTD ,TG triggered" "Not triggered,Triggered"
bitfld.long 0x30 20.--23. " TRGEVT ,Type of trigger event" "Never,Rising edge,Falling edge,Both edges,,High active,Low-active,Always,?..."
bitfld.long 0x30 16.--19. " TRIGSRC ,Trigger source" "Disabled,EXT[0],EXT[1],EXT[2],EXT[3],EXT[4],EXT[5],EXT[6],EXT[7],EXT[8],EXT[9,EXT[10,EXT[11,EXT[12,EXT[13],TICK"
textline " "
hexmask.long.byte 0x30 8.--14. 1. " PSTART ,TG start address"
hexmask.long.byte 0x30 0.--6. 1. " PCURRENT ,Pointer to current buffer"
line.long 0x34 "TG12CTRL,MibSPI Transfer Group Control Register 12"
bitfld.long 0x34 31. " TGENA ,TG enable" "Disabled,Enabled"
bitfld.long 0x34 30. " ONESHOT ,Single transfer for TG" "Disabled,Enabled"
bitfld.long 0x34 29. " PRST ,TG pointer reset mode" "Disabled,Enabled"
textline " "
rbitfld.long 0x34 28. " TGTD ,TG triggered" "Not triggered,Triggered"
bitfld.long 0x34 20.--23. " TRGEVT ,Type of trigger event" "Never,Rising edge,Falling edge,Both edges,,High active,Low-active,Always,?..."
bitfld.long 0x34 16.--19. " TRIGSRC ,Trigger source" "Disabled,EXT[0],EXT[1],EXT[2],EXT[3],EXT[4],EXT[5],EXT[6],EXT[7],EXT[8],EXT[9,EXT[10,EXT[11,EXT[12,EXT[13],TICK"
textline " "
hexmask.long.byte 0x34 8.--14. 1. " PSTART ,TG start address"
hexmask.long.byte 0x34 0.--6. 1. " PCURRENT ,Pointer to current buffer"
line.long 0x38 "TG13CTRL,MibSPI Transfer Group Control Register 13"
bitfld.long 0x38 31. " TGENA ,TG enable" "Disabled,Enabled"
bitfld.long 0x38 30. " ONESHOT ,Single transfer for TG" "Disabled,Enabled"
bitfld.long 0x38 29. " PRST ,TG pointer reset mode" "Disabled,Enabled"
textline " "
rbitfld.long 0x38 28. " TGTD ,TG triggered" "Not triggered,Triggered"
bitfld.long 0x38 20.--23. " TRGEVT ,Type of trigger event" "Never,Rising edge,Falling edge,Both edges,,High active,Low-active,Always,?..."
bitfld.long 0x38 16.--19. " TRIGSRC ,Trigger source" "Disabled,EXT[0],EXT[1],EXT[2],EXT[3],EXT[4],EXT[5],EXT[6],EXT[7],EXT[8],EXT[9,EXT[10,EXT[11,EXT[12,EXT[13],TICK"
textline " "
hexmask.long.byte 0x38 8.--14. 1. " PSTART ,TG start address"
hexmask.long.byte 0x38 0.--6. 1. " PCURRENT ,Pointer to current buffer"
line.long 0x3C "TG14CTRL,MibSPI Transfer Group Control Register 14"
bitfld.long 0x3C 31. " TGENA ,TG enable" "Disabled,Enabled"
bitfld.long 0x3C 30. " ONESHOT ,Single transfer for TG" "Disabled,Enabled"
bitfld.long 0x3C 29. " PRST ,TG pointer reset mode" "Disabled,Enabled"
textline " "
rbitfld.long 0x3C 28. " TGTD ,TG triggered" "Not triggered,Triggered"
bitfld.long 0x3C 20.--23. " TRGEVT ,Type of trigger event" "Never,Rising edge,Falling edge,Both edges,,High active,Low-active,Always,?..."
bitfld.long 0x3C 16.--19. " TRIGSRC ,Trigger source" "Disabled,EXT[0],EXT[1],EXT[2],EXT[3],EXT[4],EXT[5],EXT[6],EXT[7],EXT[8],EXT[9,EXT[10,EXT[11,EXT[12,EXT[13],TICK"
textline " "
hexmask.long.byte 0x3C 8.--14. 1. " PSTART ,TG start address"
hexmask.long.byte 0x3C 0.--6. 1. " PCURRENT ,Pointer to current buffer"
line.long 0x40 "TG15CTRL,MibSPI Transfer Group Control Register 15"
bitfld.long 0x40 31. " TGENA ,TG enable" "Disabled,Enabled"
bitfld.long 0x40 30. " ONESHOT ,Single transfer for TG" "Disabled,Enabled"
bitfld.long 0x40 29. " PRST ,TG pointer reset mode" "Disabled,Enabled"
textline " "
rbitfld.long 0x40 28. " TGTD ,TG triggered" "Not triggered,Triggered"
bitfld.long 0x40 20.--23. " TRGEVT ,Type of trigger event" "Never,Rising edge,Falling edge,Both edges,,High active,Low-active,Always,?..."
bitfld.long 0x40 16.--19. " TRIGSRC ,Trigger source" "Disabled,EXT[0],EXT[1],EXT[2],EXT[3],EXT[4],EXT[5],EXT[6],EXT[7],EXT[8],EXT[9,EXT[10,EXT[11,EXT[12,EXT[13],TICK"
textline " "
hexmask.long.byte 0x40 8.--14. 1. " PSTART ,TG start address"
hexmask.long.byte 0x40 0.--6. 1. " PCURRENT ,Pointer to current buffer"
line.long 0x44 "TG16CTRL,MibSPI Transfer Group Control Register 16"
bitfld.long 0x44 31. " TGENA ,TG enable" "Disabled,Enabled"
bitfld.long 0x44 30. " ONESHOT ,Single transfer for TG" "Disabled,Enabled"
bitfld.long 0x44 29. " PRST ,TG pointer reset mode" "Disabled,Enabled"
textline " "
rbitfld.long 0x44 28. " TGTD ,TG triggered" "Not triggered,Triggered"
bitfld.long 0x44 20.--23. " TRGEVT ,Type of trigger event" "Never,Rising edge,Falling edge,Both edges,,High active,Low-active,Always,?..."
bitfld.long 0x44 16.--19. " TRIGSRC ,Trigger source" "Disabled,EXT[0],EXT[1],EXT[2],EXT[3],EXT[4],EXT[5],EXT[6],EXT[7],EXT[8],EXT[9,EXT[10,EXT[11,EXT[12,EXT[13],TICK"
textline " "
hexmask.long.byte 0x44 8.--14. 1. " PSTART ,TG start address"
hexmask.long.byte 0x44 0.--6. 1. " PCURRENT ,Pointer to current buffer"
if (((d.l(ad:0xFFF7FC00+0x4))&0x3)==0x0)
group.long 0xD8++0x1F
line.long 0x0 "DMA1CTRL,MibSPI DMA Channel Control Register 1"
bitfld.long 0x0 31. " ONESHOT ,Auto-disable of DMA channel after ICOUNT+1 transfers" "0,1"
hexmask.long.byte 0x0 24.--30. 1. " BUFID ,Buffer utilized for DMA transfer"
bitfld.long 0x0 20.--23. " RXDMA_MAP ,Each MibSPI DMA channel can be linked to two physical DMA" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x0 16.--19. " TXDMA_MAP ,Each MibSPI DMA channel can be linked to two physical DMA" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x0 15. " RXDMAENA ,Receive data DMA channel enable" "Disabled,Enabled"
bitfld.long 0x0 14. " TXDMAENA ,Transmit data DMA channel enable" "Disabled,Enabled"
textline " "
bitfld.long 0x0 8.--12. " ICOUNT ,Initial count of DMA transfers" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32"
rbitfld.long 0x0 6. " COUNTBIT17 ,17th bit of the COUNT field of DMAxCOUNT register" "0,1"
rbitfld.long 0x0 0.--5. " COUNT ,Actual number of remaining DMA transfers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x4 "DMA2CTRL,MibSPI DMA Channel Control Register 1"
bitfld.long 0x4 31. " ONESHOT ,Auto-disable of DMA channel after ICOUNT+1 transfers" "0,1"
hexmask.long.byte 0x4 24.--30. 1. " BUFID ,Buffer utilized for DMA transfer"
bitfld.long 0x4 20.--23. " RXDMA_MAP ,Each MibSPI DMA channel can be linked to two physical DMA" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x4 16.--19. " TXDMA_MAP ,Each MibSPI DMA channel can be linked to two physical DMA" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x4 15. " RXDMAENA ,Receive data DMA channel enable" "Disabled,Enabled"
bitfld.long 0x4 14. " TXDMAENA ,Transmit data DMA channel enable" "Disabled,Enabled"
textline " "
bitfld.long 0x4 8.--12. " ICOUNT ,Initial count of DMA transfers" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32"
rbitfld.long 0x4 6. " COUNTBIT17 ,17th bit of the COUNT field of DMAxCOUNT register" "0,1"
rbitfld.long 0x4 0.--5. " COUNT ,Actual number of remaining DMA transfers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x8 "DMA3CTRL,MibSPI DMA Channel Control Register 1"
bitfld.long 0x8 31. " ONESHOT ,Auto-disable of DMA channel after ICOUNT+1 transfers" "0,1"
hexmask.long.byte 0x8 24.--30. 1. " BUFID ,Buffer utilized for DMA transfer"
bitfld.long 0x8 20.--23. " RXDMA_MAP ,Each MibSPI DMA channel can be linked to two physical DMA" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x8 16.--19. " TXDMA_MAP ,Each MibSPI DMA channel can be linked to two physical DMA" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x8 15. " RXDMAENA ,Receive data DMA channel enable" "Disabled,Enabled"
bitfld.long 0x8 14. " TXDMAENA ,Transmit data DMA channel enable" "Disabled,Enabled"
textline " "
bitfld.long 0x8 8.--12. " ICOUNT ,Initial count of DMA transfers" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32"
rbitfld.long 0x8 6. " COUNTBIT17 ,17th bit of the COUNT field of DMAxCOUNT register" "0,1"
rbitfld.long 0x8 0.--5. " COUNT ,Actual number of remaining DMA transfers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0xC "DMA4CTRL,MibSPI DMA Channel Control Register 1"
bitfld.long 0xC 31. " ONESHOT ,Auto-disable of DMA channel after ICOUNT+1 transfers" "0,1"
hexmask.long.byte 0xC 24.--30. 1. " BUFID ,Buffer utilized for DMA transfer"
bitfld.long 0xC 20.--23. " RXDMA_MAP ,Each MibSPI DMA channel can be linked to two physical DMA" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0xC 16.--19. " TXDMA_MAP ,Each MibSPI DMA channel can be linked to two physical DMA" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0xC 15. " RXDMAENA ,Receive data DMA channel enable" "Disabled,Enabled"
bitfld.long 0xC 14. " TXDMAENA ,Transmit data DMA channel enable" "Disabled,Enabled"
textline " "
bitfld.long 0xC 8.--12. " ICOUNT ,Initial count of DMA transfers" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32"
rbitfld.long 0xC 6. " COUNTBIT17 ,17th bit of the COUNT field of DMAxCOUNT register" "0,1"
rbitfld.long 0xC 0.--5. " COUNT ,Actual number of remaining DMA transfers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x10 "DMA5CTRL,MibSPI DMA Channel Control Register 1"
bitfld.long 0x10 31. " ONESHOT ,Auto-disable of DMA channel after ICOUNT+1 transfers" "0,1"
hexmask.long.byte 0x10 24.--30. 1. " BUFID ,Buffer utilized for DMA transfer"
bitfld.long 0x10 20.--23. " RXDMA_MAP ,Each MibSPI DMA channel can be linked to two physical DMA" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x10 16.--19. " TXDMA_MAP ,Each MibSPI DMA channel can be linked to two physical DMA" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x10 15. " RXDMAENA ,Receive data DMA channel enable" "Disabled,Enabled"
bitfld.long 0x10 14. " TXDMAENA ,Transmit data DMA channel enable" "Disabled,Enabled"
textline " "
bitfld.long 0x10 8.--12. " ICOUNT ,Initial count of DMA transfers" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32"
rbitfld.long 0x10 6. " COUNTBIT17 ,17th bit of the COUNT field of DMAxCOUNT register" "0,1"
rbitfld.long 0x10 0.--5. " COUNT ,Actual number of remaining DMA transfers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x14 "DMA6CTRL,MibSPI DMA Channel Control Register 1"
bitfld.long 0x14 31. " ONESHOT ,Auto-disable of DMA channel after ICOUNT+1 transfers" "0,1"
hexmask.long.byte 0x14 24.--30. 1. " BUFID ,Buffer utilized for DMA transfer"
bitfld.long 0x14 20.--23. " RXDMA_MAP ,Each MibSPI DMA channel can be linked to two physical DMA" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x14 16.--19. " TXDMA_MAP ,Each MibSPI DMA channel can be linked to two physical DMA" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x14 15. " RXDMAENA ,Receive data DMA channel enable" "Disabled,Enabled"
bitfld.long 0x14 14. " TXDMAENA ,Transmit data DMA channel enable" "Disabled,Enabled"
textline " "
bitfld.long 0x14 8.--12. " ICOUNT ,Initial count of DMA transfers" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32"
rbitfld.long 0x14 6. " COUNTBIT17 ,17th bit of the COUNT field of DMAxCOUNT register" "0,1"
rbitfld.long 0x14 0.--5. " COUNT ,Actual number of remaining DMA transfers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x18 "DMA7CTRL,MibSPI DMA Channel Control Register 1"
bitfld.long 0x18 31. " ONESHOT ,Auto-disable of DMA channel after ICOUNT+1 transfers" "0,1"
hexmask.long.byte 0x18 24.--30. 1. " BUFID ,Buffer utilized for DMA transfer"
bitfld.long 0x18 20.--23. " RXDMA_MAP ,Each MibSPI DMA channel can be linked to two physical DMA" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x18 16.--19. " TXDMA_MAP ,Each MibSPI DMA channel can be linked to two physical DMA" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x18 15. " RXDMAENA ,Receive data DMA channel enable" "Disabled,Enabled"
bitfld.long 0x18 14. " TXDMAENA ,Transmit data DMA channel enable" "Disabled,Enabled"
textline " "
bitfld.long 0x18 8.--12. " ICOUNT ,Initial count of DMA transfers" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32"
rbitfld.long 0x18 6. " COUNTBIT17 ,17th bit of the COUNT field of DMAxCOUNT register" "0,1"
rbitfld.long 0x18 0.--5. " COUNT ,Actual number of remaining DMA transfers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x1C "DMA8CTRL,MibSPI DMA Channel Control Register 1"
bitfld.long 0x1C 31. " ONESHOT ,Auto-disable of DMA channel after ICOUNT+1 transfers" "0,1"
hexmask.long.byte 0x1C 24.--30. 1. " BUFID ,Buffer utilized for DMA transfer"
bitfld.long 0x1C 20.--23. " RXDMA_MAP ,Each MibSPI DMA channel can be linked to two physical DMA" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x1C 16.--19. " TXDMA_MAP ,Each MibSPI DMA channel can be linked to two physical DMA" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x1C 15. " RXDMAENA ,Receive data DMA channel enable" "Disabled,Enabled"
bitfld.long 0x1C 14. " TXDMAENA ,Transmit data DMA channel enable" "Disabled,Enabled"
textline " "
bitfld.long 0x1C 8.--12. " ICOUNT ,Initial count of DMA transfers" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32"
rbitfld.long 0x1C 6. " COUNTBIT17 ,17th bit of the COUNT field of DMAxCOUNT register" "0,1"
rbitfld.long 0x1C 0.--5. " COUNT ,Actual number of remaining DMA transfers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
else
group.long 0xD8++0x1F
line.long 0x0 "DMA1CTRL,MibSPI DMA Channel Control Register 1"
bitfld.long 0x0 31. " ONESHOT ,Auto-disable of DMA channel after ICOUNT+1 transfers" "0,1"
hexmask.long.byte 0x0 24.--30. 1. " BUFID ,Buffer utilized for DMA transfer"
bitfld.long 0x0 20.--23. " RXDMA_MAP ,Each MibSPI DMA channel can be linked to two physical DMA" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x0 16.--19. " TXDMA_MAP ,Each MibSPI DMA channel can be linked to two physical DMA" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x0 15. " RXDMAENA ,Receive data DMA channel enable" "Disabled,Enabled"
bitfld.long 0x0 14. " TXDMAENA ,Transmit data DMA channel enable" "Disabled,Enabled"
textline " "
bitfld.long 0x0 13. " NOBRK ,Non-interleaved DMA block transfer" "Not performed,Performed"
bitfld.long 0x0 8.--12. " ICOUNT ,Initial count of DMA transfers" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32"
rbitfld.long 0x0 6. " COUNTBIT17 ,17th bit of the COUNT field of DMAxCOUNT register" "0,1"
textline " "
rbitfld.long 0x0 0.--5. " COUNT ,Actual number of remaining DMA transfers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x4 "DMA2CTRL,MibSPI DMA Channel Control Register 1"
bitfld.long 0x4 31. " ONESHOT ,Auto-disable of DMA channel after ICOUNT+1 transfers" "0,1"
hexmask.long.byte 0x4 24.--30. 1. " BUFID ,Buffer utilized for DMA transfer"
bitfld.long 0x4 20.--23. " RXDMA_MAP ,Each MibSPI DMA channel can be linked to two physical DMA" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x4 16.--19. " TXDMA_MAP ,Each MibSPI DMA channel can be linked to two physical DMA" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x4 15. " RXDMAENA ,Receive data DMA channel enable" "Disabled,Enabled"
bitfld.long 0x4 14. " TXDMAENA ,Transmit data DMA channel enable" "Disabled,Enabled"
textline " "
bitfld.long 0x4 13. " NOBRK ,Non-interleaved DMA block transfer" "Not performed,Performed"
bitfld.long 0x4 8.--12. " ICOUNT ,Initial count of DMA transfers" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32"
rbitfld.long 0x4 6. " COUNTBIT17 ,17th bit of the COUNT field of DMAxCOUNT register" "0,1"
textline " "
rbitfld.long 0x4 0.--5. " COUNT ,Actual number of remaining DMA transfers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x8 "DMA3CTRL,MibSPI DMA Channel Control Register 1"
bitfld.long 0x8 31. " ONESHOT ,Auto-disable of DMA channel after ICOUNT+1 transfers" "0,1"
hexmask.long.byte 0x8 24.--30. 1. " BUFID ,Buffer utilized for DMA transfer"
bitfld.long 0x8 20.--23. " RXDMA_MAP ,Each MibSPI DMA channel can be linked to two physical DMA" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x8 16.--19. " TXDMA_MAP ,Each MibSPI DMA channel can be linked to two physical DMA" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x8 15. " RXDMAENA ,Receive data DMA channel enable" "Disabled,Enabled"
bitfld.long 0x8 14. " TXDMAENA ,Transmit data DMA channel enable" "Disabled,Enabled"
textline " "
bitfld.long 0x8 13. " NOBRK ,Non-interleaved DMA block transfer" "Not performed,Performed"
bitfld.long 0x8 8.--12. " ICOUNT ,Initial count of DMA transfers" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32"
rbitfld.long 0x8 6. " COUNTBIT17 ,17th bit of the COUNT field of DMAxCOUNT register" "0,1"
textline " "
rbitfld.long 0x8 0.--5. " COUNT ,Actual number of remaining DMA transfers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0xC "DMA4CTRL,MibSPI DMA Channel Control Register 1"
bitfld.long 0xC 31. " ONESHOT ,Auto-disable of DMA channel after ICOUNT+1 transfers" "0,1"
hexmask.long.byte 0xC 24.--30. 1. " BUFID ,Buffer utilized for DMA transfer"
bitfld.long 0xC 20.--23. " RXDMA_MAP ,Each MibSPI DMA channel can be linked to two physical DMA" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0xC 16.--19. " TXDMA_MAP ,Each MibSPI DMA channel can be linked to two physical DMA" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0xC 15. " RXDMAENA ,Receive data DMA channel enable" "Disabled,Enabled"
bitfld.long 0xC 14. " TXDMAENA ,Transmit data DMA channel enable" "Disabled,Enabled"
textline " "
bitfld.long 0xC 13. " NOBRK ,Non-interleaved DMA block transfer" "Not performed,Performed"
bitfld.long 0xC 8.--12. " ICOUNT ,Initial count of DMA transfers" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32"
rbitfld.long 0xC 6. " COUNTBIT17 ,17th bit of the COUNT field of DMAxCOUNT register" "0,1"
textline " "
rbitfld.long 0xC 0.--5. " COUNT ,Actual number of remaining DMA transfers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x10 "DMA5CTRL,MibSPI DMA Channel Control Register 1"
bitfld.long 0x10 31. " ONESHOT ,Auto-disable of DMA channel after ICOUNT+1 transfers" "0,1"
hexmask.long.byte 0x10 24.--30. 1. " BUFID ,Buffer utilized for DMA transfer"
bitfld.long 0x10 20.--23. " RXDMA_MAP ,Each MibSPI DMA channel can be linked to two physical DMA" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x10 16.--19. " TXDMA_MAP ,Each MibSPI DMA channel can be linked to two physical DMA" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x10 15. " RXDMAENA ,Receive data DMA channel enable" "Disabled,Enabled"
bitfld.long 0x10 14. " TXDMAENA ,Transmit data DMA channel enable" "Disabled,Enabled"
textline " "
bitfld.long 0x10 13. " NOBRK ,Non-interleaved DMA block transfer" "Not performed,Performed"
bitfld.long 0x10 8.--12. " ICOUNT ,Initial count of DMA transfers" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32"
rbitfld.long 0x10 6. " COUNTBIT17 ,17th bit of the COUNT field of DMAxCOUNT register" "0,1"
textline " "
rbitfld.long 0x10 0.--5. " COUNT ,Actual number of remaining DMA transfers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x14 "DMA6CTRL,MibSPI DMA Channel Control Register 1"
bitfld.long 0x14 31. " ONESHOT ,Auto-disable of DMA channel after ICOUNT+1 transfers" "0,1"
hexmask.long.byte 0x14 24.--30. 1. " BUFID ,Buffer utilized for DMA transfer"
bitfld.long 0x14 20.--23. " RXDMA_MAP ,Each MibSPI DMA channel can be linked to two physical DMA" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x14 16.--19. " TXDMA_MAP ,Each MibSPI DMA channel can be linked to two physical DMA" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x14 15. " RXDMAENA ,Receive data DMA channel enable" "Disabled,Enabled"
bitfld.long 0x14 14. " TXDMAENA ,Transmit data DMA channel enable" "Disabled,Enabled"
textline " "
bitfld.long 0x14 13. " NOBRK ,Non-interleaved DMA block transfer" "Not performed,Performed"
bitfld.long 0x14 8.--12. " ICOUNT ,Initial count of DMA transfers" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32"
rbitfld.long 0x14 6. " COUNTBIT17 ,17th bit of the COUNT field of DMAxCOUNT register" "0,1"
textline " "
rbitfld.long 0x14 0.--5. " COUNT ,Actual number of remaining DMA transfers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x18 "DMA7CTRL,MibSPI DMA Channel Control Register 1"
bitfld.long 0x18 31. " ONESHOT ,Auto-disable of DMA channel after ICOUNT+1 transfers" "0,1"
hexmask.long.byte 0x18 24.--30. 1. " BUFID ,Buffer utilized for DMA transfer"
bitfld.long 0x18 20.--23. " RXDMA_MAP ,Each MibSPI DMA channel can be linked to two physical DMA" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x18 16.--19. " TXDMA_MAP ,Each MibSPI DMA channel can be linked to two physical DMA" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x18 15. " RXDMAENA ,Receive data DMA channel enable" "Disabled,Enabled"
bitfld.long 0x18 14. " TXDMAENA ,Transmit data DMA channel enable" "Disabled,Enabled"
textline " "
bitfld.long 0x18 13. " NOBRK ,Non-interleaved DMA block transfer" "Not performed,Performed"
bitfld.long 0x18 8.--12. " ICOUNT ,Initial count of DMA transfers" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32"
rbitfld.long 0x18 6. " COUNTBIT17 ,17th bit of the COUNT field of DMAxCOUNT register" "0,1"
textline " "
rbitfld.long 0x18 0.--5. " COUNT ,Actual number of remaining DMA transfers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x1C "DMA8CTRL,MibSPI DMA Channel Control Register 1"
bitfld.long 0x1C 31. " ONESHOT ,Auto-disable of DMA channel after ICOUNT+1 transfers" "0,1"
hexmask.long.byte 0x1C 24.--30. 1. " BUFID ,Buffer utilized for DMA transfer"
bitfld.long 0x1C 20.--23. " RXDMA_MAP ,Each MibSPI DMA channel can be linked to two physical DMA" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x1C 16.--19. " TXDMA_MAP ,Each MibSPI DMA channel can be linked to two physical DMA" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x1C 15. " RXDMAENA ,Receive data DMA channel enable" "Disabled,Enabled"
bitfld.long 0x1C 14. " TXDMAENA ,Transmit data DMA channel enable" "Disabled,Enabled"
textline " "
bitfld.long 0x1C 13. " NOBRK ,Non-interleaved DMA block transfer" "Not performed,Performed"
bitfld.long 0x1C 8.--12. " ICOUNT ,Initial count of DMA transfers" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32"
rbitfld.long 0x1C 6. " COUNTBIT17 ,17th bit of the COUNT field of DMAxCOUNT register" "0,1"
textline " "
rbitfld.long 0x1C 0.--5. " COUNT ,Actual number of remaining DMA transfers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
endif
group.long 0xF8++0x1F
line.long 0x0 "DMA0COUNT,MibSPI DMA0COUNT Register"
hexmask.long.word 0x0 16.--31. 1. " ICOUNT0 ,Initial number of DMA transfers"
hexmask.long.word 0x0 0.--15. 1. " COUNT0 ,The actual number of remaining DMA transfers"
line.long 0x4 "DMA1COUNT,MibSPI DMA1COUNT Register"
hexmask.long.word 0x4 16.--31. 1. " ICOUNT1 ,Initial number of DMA transfers"
hexmask.long.word 0x4 0.--15. 1. " COUNT1 ,The actual number of remaining DMA transfers"
line.long 0x8 "DMA2COUNT,MibSPI DMA2COUNT Register"
hexmask.long.word 0x8 16.--31. 1. " ICOUNT2 ,Initial number of DMA transfers"
hexmask.long.word 0x8 0.--15. 1. " COUNT2 ,The actual number of remaining DMA transfers"
line.long 0xC "DMA3COUNT,MibSPI DMA3COUNT Register"
hexmask.long.word 0xC 16.--31. 1. " ICOUNT3 ,Initial number of DMA transfers"
hexmask.long.word 0xC 0.--15. 1. " COUNT3 ,The actual number of remaining DMA transfers"
line.long 0x10 "DMA4COUNT,MibSPI DMA4COUNT Register"
hexmask.long.word 0x10 16.--31. 1. " ICOUNT4 ,Initial number of DMA transfers"
hexmask.long.word 0x10 0.--15. 1. " COUNT4 ,The actual number of remaining DMA transfers"
line.long 0x14 "DMA5COUNT,MibSPI DMA5COUNT Register"
hexmask.long.word 0x14 16.--31. 1. " ICOUNT5 ,Initial number of DMA transfers"
hexmask.long.word 0x14 0.--15. 1. " COUNT5 ,The actual number of remaining DMA transfers"
line.long 0x18 "DMA6COUNT,MibSPI DMA6COUNT Register"
hexmask.long.word 0x18 16.--31. 1. " ICOUNT6 ,Initial number of DMA transfers"
hexmask.long.word 0x18 0.--15. 1. " COUNT6 ,The actual number of remaining DMA transfers"
line.long 0x1C "DMA7COUNT,MibSPI DMA7COUNT Register"
hexmask.long.word 0x1C 16.--31. 1. " ICOUNT7 ,Initial number of DMA transfers"
hexmask.long.word 0x1C 0.--15. 1. " COUNT7 ,The actual number of remaining DMA transfers"
textline " "
group.long 0x118++0x03
line.long 0x00 "DMACNTLEN,MibSPI DMACNTLEN Register"
bitfld.long 0x00 0. " LARGECOUNT ,Counters select" "DMAxCTRL,DMAxCOUNT"
group.long 0x120++0x03
line.long 0x00 "UERRCTRL,Uncorrectable Parity Error Control Register"
sif cpu()=="TMS570LC4357"
bitfld.long 0x00 24.--27. " SBE_EVT_EN ,ECC Single Bit Error Event Enable" ",,,,,Disabled,,,,,Enabled,?..."
bitfld.long 0x00 16.--19. " EDAC_MODE ,ECC Single Bit Error Block Correction" ",,,,,Disabled,,,,,Enabled,?..."
textline " "
endif
bitfld.long 0x00 8. " PTESTEN ,Parity memory test enable" "Disabled,Enabled"
bitfld.long 0x00 0.--3. " EDEN ,Error detection enable" "Enabled,Enabled,Enabled,Enabled,Enabled,Disabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled"
group.long 0x124++0x03
line.long 0x00 "UERRSTAT,Uncorrectable Parity Error Status Register"
sif cpu()=="TMS570LC4357"
eventfld.long 0x00 9. " SBE_FLG1 ,Single Bit Error in RXRAM" "Not occurred,Occurred"
eventfld.long 0x00 8. " SBE_FLG0 ,Single Bit Error in TXRAM" "Not occurred,Occurred"
textline " "
eventfld.long 0x00 1. " EDFLG1 ,Uncorrectable parity error detection flag" "Not occurred,Occurred"
eventfld.long 0x00 0. " EDFLG0 ,Uncorrectable parity error detection flag" "Not occurred,Occurred"
else
eventfld.long 0x00 1. " EDFLG1 ,Uncorrectable parity error detection flag" "Not occurred,Occurred"
eventfld.long 0x00 0. " EDFLG0 ,Uncorrectable parity error detection flag" "Not occurred,Occurred"
endif
width 17.
hgroup.long 0x128++0x03
hide.long 0x00 "UERRADDR1,Uncorrectable Parity Error Address Register"
in
hgroup.long 0x12C++0x03
hide.long 0x00 "UERRADDR0,Uncorrectable Parity Error Address Register"
in
hgroup.long 0x130++0x03
hide.long 0x00 "RXOVRN_BUF_ADDR,Receive RAM Overrun Buffer Address Register"
in
textline " "
width 14.
if (((d.l(ad:0xFFF7FC00+0x134))&0x2)==0x2)&&(((d.l(ad:0xFFF7FC00+0x134))&0xF00)==0xA00)
group.long 0x134++0x03
line.long 0x00 "IOLPBKTSTCR,SPI IO Loopback Test Control Register"
bitfld.long 0x00 24. " SCSFAILFLG ,Failure on SPISCS pin compare during analog loopback" "Not occurred,Occurred"
bitfld.long 0x00 20. " CTRL_BITERR ,Controls inducing of BITERR during I/O loopback test mode" "Disabled,Enabled"
bitfld.long 0x00 19. " CTRL_DESYNC ,Controls inducing of the desync error during I/O loopback test mode" "No error,Error"
textline " "
bitfld.long 0x00 18. " CTRL_PARERR ,Controls inducing of parity errors during I/O loopback test mode" "No error,Error"
bitfld.long 0x00 17. " CTRL_TIMEOUT ,Controls inducing of the timeout error during I/O loopbacK test mode" "No error,Error"
bitfld.long 0x00 16. " CTRL_DLENERR ,Controls inducing of the data length error during I/O loopback test mode" "No error,Error"
textline " "
bitfld.long 0x00 8.--11. " IOLPBKTSTENA ,Module I/O loopback test enable key" "Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Enabled,Disabled,Disabled,Disabled,Disabled,Disabled"
bitfld.long 0x00 3.--5. " ERRSCSPIN ,Inject error on chip-select pin number" "/SPISCS[0],/SPISCS[1],/SPISCS[2],/SPISCS[3],/SPISCS[4],/SPISCS[5],/SPISCS[6],/SPISCS[7]"
bitfld.long 0x00 2. " CTRLSCSPINERR ,Enable/disable the injection of an error on the SPISCS[3:0] pins" "Disabled,Enabled"
textline " "
bitfld.long 0x00 1. " LPBK_TYPE ,Module I/O loopback type (analog/digital)" "Digital,Analog"
bitfld.long 0x00 0. " RXP_ENA ,Enable analog loopback through the receive pin" "Transmit,Receive"
elif (((d.l(ad:0xFFF7FC00+0x134))&0x2)==0x0)&&(((d.l(ad:0xFFF7FC00+0x134))&0xF00)==0xA00)
group.long 0x134++0x03
line.long 0x00 "IOLPBKTSTCR,SPI IO Loopback Test Control Register"
eventfld.long 0x00 24. " SCSFAILFLG ,Failure on SPISCS pin compare during analog loopback" "Not occurred,Occurred"
bitfld.long 0x00 20. " CTRL_BITERR ,Controls inducing of BITERR during I/O loopback test mode" "Disabled,Enabled"
bitfld.long 0x00 19. " CTRL_DESYNC ,Controls inducing of the desync error during I/O loopback test mode" "No error,Error"
textline " "
bitfld.long 0x00 18. " CTRL_PARERR ,Controls inducing of parity errors during I/O loopback test mode" "No error,Error"
bitfld.long 0x00 17. " CTRL_TIMEOUT ,Controls inducing of the timeout error during I/O loopbacK test mode" "No error,Error"
bitfld.long 0x00 16. " CTRL_DLENERR ,Controls inducing of the data length error during I/O loopback test mode" "No error,Error"
textline " "
bitfld.long 0x00 8.--11. " IOLPBKTSTENA ,Module I/O loopback test enable key" "Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Enabled,Disabled,Disabled,Disabled,Disabled,Disabled"
bitfld.long 0x00 3.--5. " ERRSCSPIN ,Inject error on chip-select pin number" "/SPISCS[0],/SPISCS[1],/SPISCS[2],/SPISCS[3],/SPISCS[4],/SPISCS[5],/SPISCS[6],/SPISCS[7]"
bitfld.long 0x00 2. " CTRLSCSPINERR ,Enable/disable the injection of an error on the SPISCS[3:0] pins" "Disabled,Enabled"
textline " "
bitfld.long 0x00 1. " LPBK_TYPE ,Module I/O loopback type (analog/digital)" "Digital,Analog"
elif (((d.l(ad:0xFFF7FC00+0x134))&0x2)==0x2)&&(((d.l(ad:0xFFF7FC00+0x134))&0xF00)!=0xA00)
group.long 0x134++0x03
line.long 0x00 "IOLPBKTSTCR,SPI IO Loopback Test Control Register"
bitfld.long 0x00 8.--11. " IOLPBKTSTENA ,Module I/O loopback test enable key" "Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Enabled,Disabled,Disabled,Disabled,Disabled,Disabled"
bitfld.long 0x00 3.--5. " ERRSCSPIN ,Inject error on chip-select pin number" "/SPISCS[0],/SPISCS[1],/SPISCS[2],/SPISCS[3],/SPISCS[4],/SPISCS[5],/SPISCS[6],/SPISCS[7]"
bitfld.long 0x00 2. " CTRLSCSPINERR ,Enable/disable the injection of an error on the SPISCS[3:0] pins" "Disabled,Enabled"
textline " "
bitfld.long 0x00 1. " LPBK_TYPE ,Module I/O loopback type (analog/digital)" "Digital,Analog"
bitfld.long 0x00 0. " RXP_ENA ,Enable analog loopback through the receive pin" "Transmit,Receive"
else
group.long 0x134++0x03
line.long 0x00 "IOLPBKTSTCR,SPI IO Loopback Test Control Register"
bitfld.long 0x00 8.--11. " IOLPBKTSTENA ,Module I/O loopback test enable key" "Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Enabled,Disabled,Disabled,Disabled,Disabled,Disabled"
bitfld.long 0x00 3.--5. " ERRSCSPIN ,Inject error on chip-select pin number" "/SPISCS[0],/SPISCS[1],/SPISCS[2],/SPISCS[3],/SPISCS[4],/SPISCS[5],/SPISCS[6],/SPISCS[7]"
bitfld.long 0x00 2. " CTRLSCSPINERR ,Enable/disable the injection of an error on the SPISCS[3:0] pins" "Disabled,Enabled"
textline " "
bitfld.long 0x00 1. " LPBK_TYPE ,Module I/O loopback type (analog/digital)" "Digital,Analog"
endif
textline " "
width 21.
group.long 0x138++0x07
line.long 0x00 "EXTENDED_PRESCALE_1,SPI Extended Prescale Register 1"
hexmask.long.word 0x00 16.--26. 1. " EPRESCALE_FMT1 ,Extended Prescale value for SPIFMT1"
hexmask.long.word 0x00 0.--10. 1. " EPRESCALE_FMT0 ,Extended Prescale value for SPIFMT0"
line.long 0x04 "EXTENDED_PRESCALE_2,SPI Extended Prescale Register 2"
hexmask.long.word 0x04 16.--26. 1. " EPRESCALE_FMT3 ,Extended Prescale value for SPIFMT3"
hexmask.long.word 0x04 0.--10. 1. " EPRESCALE_FMT2 ,Extended Prescale value for SPIFMT2"
sif cpu()!="TMS570LC4357"
group.long 0x140++0x03
line.long 0x00 "ECCDIAG_CTRL,ECC Diagnostic Control register"
bitfld.long 0x00 0.--3. " ECCDIAG_EN ,ECC Diagnostic mode Enable Key bits" "Disabled,Disabled,Disabled,Disabled,Disabled,Enabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled"
endif
if ((d.l(ad:0xFFF7FC00+0x140)&0x5)==0x5)
group.long 0x144++0x03
line.long 0x00 "ECCDIAG_STAT, ECC Diagnostic Status Register"
eventfld.long 0x00 17. " DEFLG[1] ,Double bit Error is detected for RXRAM" "No error,Error"
eventfld.long 0x00 16. " DEFLG[0] ,Double bit Error is detected for TXRAM" "No error,Error"
eventfld.long 0x00 1. " SEFLG[1] ,Single bit Error is detected for RXRAM" "No error,Error"
eventfld.long 0x00 0. " SEFLG[0] ,Single bit Error is detected for TXRAM" "No error,Error"
else
hgroup.long 0x144++0x03
hide.long 0x00 "ECCDIAG_STAT,ECC Diagnostic Status Register"
in
endif
hgroup.long 0x148++0x03
hide.long 0x00 "SBERRADDR1,Single Bit Error Address Register - RXRAM"
in
hgroup.long 0x14C++0x03
hide.long 0x00 "SBERRADDR0,Single Bit Error Address Register - TXRAM"
in
tree.end
tree.end
tree.open "SCI/LIN (Serial Communications Interface/Local Interconnect Network Module)"
tree "SCI/LIN1"
base ad:0xFFF7E400
width 8.
group.long 0x00++0x03
line.long 0x00 "GCR0,Global Control Register"
bitfld.long 0x00 0. " RESET ,SCI/LIN module reset" "Under reset,Out of reset"
if ((d.l(ad:0xFFF7E400+0x04)&0x044)==0x044)
group.long 0x04++0x03
line.long 0x00 "GCR1,Global Control Register"
bitfld.long 0x00 25. " TXENA ,SCI transmitter enable" "Disabled,Enabled"
bitfld.long 0x00 24. " RXENA ,SCI receiver enable" "Prevented,Allowed"
bitfld.long 0x00 17. " CONT ,Continue on suspend" "Frozen,Continue"
bitfld.long 0x00 16. " LOOP_BACK ,LOOP BACK enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 13. " STOP_EXT_FRAME ,Stop extended frame communication" "Not stopped,Stopped"
bitfld.long 0x00 12. " HGEN_CTRL ,LIN mode bit (Type of mask filtering comparison)" "Id-byte,ID-Slave task byte"
bitfld.long 0x00 11. " CTYPE ,Checksum type" "Classic,Enhanced"
bitfld.long 0x00 10. " MBUF_MODE ,Receive/transmit buffer enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 9. " ADAPT ,LIN mode bit (Automatic baudrate adjustment)" "Disabled,Enabled"
bitfld.long 0x00 8. " SLEEP ,SCI sleep enable" "Disabled,Enabled"
bitfld.long 0x00 7. " SW_NRESET ,Software reset" "Reset,Ready"
bitfld.long 0x00 6. " LIN_MODE ,LIN MODE enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 5. " CLOCK ,SCI internal clock enable" "Slave,Master"
bitfld.long 0x00 4. " STOP ,SCI number of stop bits" "1 bit,2 bits"
bitfld.long 0x00 3. " PARITY ,SCI parity odd/even selection" "Odd,Even"
bitfld.long 0x00 2. " PARITY_ENA ,ID-Parity enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 1. " TIMING_MODE ,SCI timing mode bit" "Synchronous,Asynchronous"
bitfld.long 0x00 0. " COMM_MODE ,SCI/BLIN communication mode bit ID4 and ID5 use" "Not used,Used"
elif ((d.l(ad:0xFFF7E400+0x04)&0x044)==0x040)
group.long 0x04++0x03
line.long 0x00 "GCR1,Global Control Register"
bitfld.long 0x00 25. " TXENA ,SCI transmitter enable" "Disabled,Enabled"
bitfld.long 0x00 24. " RXENA ,SCI receiver enable" "Prevented,Allowed"
bitfld.long 0x00 17. " CONT ,Continue on suspend" "Frozen,Continue"
bitfld.long 0x00 16. " LOOP_BACK ,LOOP BACK enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 13. " STOP_EXT_FRAME ,Stop extended frame communication" "Not stopped,Stopped"
bitfld.long 0x00 12. " HGEN_CTRL ,LIN mode bit (Type of mask filtering comparison)" "Id-byte,Id-slavetask"
bitfld.long 0x00 11. " CTYPE ,Checksum type" "Classic,Enhanced"
bitfld.long 0x00 10. " MBUF_MODE ,Receive/transmit buffer enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 9. " ADAPT ,LIN mode bit (Automatic baudrate adjustment)" "Disabled,Enabled"
bitfld.long 0x00 8. " SLEEP ,SCI sleep enable" "Disabled,Enabled"
bitfld.long 0x00 7. " SW_NRESET ,Software reset" "Reset,Ready"
bitfld.long 0x00 6. " LIN_MODE ,LIN MODE enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 5. " CLOCK ,SCI internal clock enable" "Slave,Master"
bitfld.long 0x00 4. " STOP ,SCI number of stop bits" "1 bit,2 bits"
bitfld.long 0x00 2. " PARITY_ENA ,ID-Parity enable" "Disabled,Enabled"
bitfld.long 0x00 1. " TIMING_MODE ,SCI timing mode bit" "Synchronous,Asynchronous"
textline " "
bitfld.long 0x00 0. " COMM_MODE ,SCI/BLIN communication mode bit ID4 and ID5 use" "Not used,Used"
elif (((d.l((ad:0xFFF7E400+0x04)))&0x044)==0x04)
group.long 0x04++0x03
line.long 0x00 "GCR1,Global Control Register"
bitfld.long 0x00 25. " TXENA ,SCI transmitter enable" "Disabled,Enabled"
bitfld.long 0x00 24. " RXENA ,SCI receiver enable" "Prevented,Allowed"
bitfld.long 0x00 17. " CONT ,Continue on suspend" "Frozen,Continue"
bitfld.long 0x00 16. " LOOP_BACK ,LOOP BACK enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 10. " MBUF_MODE ,Receive/transmit buffer enable" "Disabled,Enabled"
bitfld.long 0x00 8. " SLEEP ,SCI sleep enable" "Disabled,Enabled"
bitfld.long 0x00 7. " SW_NRESET ,Software reset" "Reset,Ready"
bitfld.long 0x00 6. " LIN_MODE ,LIN MODE enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 5. " CLOCK ,SCI internal clock enable" "External,Internal"
bitfld.long 0x00 4. " STOP ,SCI number of stop bits" "1 bit,2 bits"
bitfld.long 0x00 3. " PARITY ,SCI parity odd/even selection" "Odd,Even"
bitfld.long 0x00 2. " PARITY_ENA ,Parity enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 1. " TIMING_MODE ,SCI timing mode bit" "Synchronous,Asynchronous"
bitfld.long 0x00 0. " COMM_MODE ,SCI/BLIN communication mode bit" "Idle-line,Address-bit"
else
group.long 0x04++0x03
line.long 0x00 "GCR1,Global Control Register"
bitfld.long 0x00 25. " TXENA ,SCI transmitter enable" "Disabled,Enabled"
bitfld.long 0x00 24. " RXENA ,SCI receiver enable" "Prevented,Allowed"
bitfld.long 0x00 17. " CONT ,Continue on suspend" "Frozen,Continue"
bitfld.long 0x00 16. " LOOP_BACK ,LOOP BACK enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 10. " MBUF_MODE ,Receive/transmit buffer enable" "Disabled,Enabled"
bitfld.long 0x00 8. " SLEEP ,SCI sleep enable" "Disabled,Enabled"
bitfld.long 0x00 7. " SW_NRESET ,Software reset" "Reset,Ready"
bitfld.long 0x00 6. " LIN_MODE ,LIN MODE enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 5. " CLOCK ,SCI internal clock enable" "External,Internal"
bitfld.long 0x00 4. " STOP ,SCI number of stop bits" "1 bit,2 bits"
bitfld.long 0x00 2. " PARITY_ENA ,Parity enable" "Disabled,Enabled"
bitfld.long 0x00 1. " TIMING_MODE ,SCI timing mode bit" "Synchronous,Asynchronous"
textline " "
bitfld.long 0x00 0. " COMM_MODE ,SCI/BLIN communication mode bit" "Idle-line,Address-bit"
endif
if ((d.l(ad:0xFFF7E400+0x04)&0x040)==0x040)
group.long 0x08++0x03
line.long 0x00 "GCR2,Global Control Register"
bitfld.long 0x00 17. " CC ,Compare checksum" "No effect,Compared"
bitfld.long 0x00 16. " SC ,Send checksum" "No effect,Compared"
bitfld.long 0x00 8. " GEN_WU ,Generate wakeup signal" "No effect,Generated"
bitfld.long 0x00 0. " POWERDOWN ,POWERDOWN" "Normal,Local low-power"
else
group.long 0x08++0x03
line.long 0x00 "GCR2,Global Control Register"
bitfld.long 0x00 0. " POWERDOWN ,POWERDOWN" "Normal,Local low-power"
endif
width 11.
tree "SCI Interrupt Registers"
if ((d.l(ad:0xFFF7E400+0x04)&0x040)==0x040)
group.long 0x0C++0x03
line.long 0x00 "SETINT,Interrupt Register"
setclrfld.long 0x00 31. 0x00 31. 0x04 31. " BE_INT_SET/CLR ,Bit error interrupt" "Disabled,Enabled"
setclrfld.long 0x00 30. 0x00 30. 0x04 30. " PBE_INT_SET/CLR ,Physical bus error interrupt" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 29. 0x00 29. 0x04 29. " CE_INT_SET/CLR ,Checksum-Error interrupt" "Disabled,Enabled"
setclrfld.long 0x00 28. 0x00 28. 0x04 28. " ISFE_INT_SET/CLR ,Inconsistent-Synch-Field-Error interrupt" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 27. 0x00 27. 0x04 27. " NRE_INT_SET/CLR ,No-Reponse-Error interrupt" "Disabled,Enabled"
setclrfld.long 0x00 26. 0x00 26. 0x04 26. " FE_INT_SET/CLR ,Framing-Error interrupt" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 25. 0x00 25. 0x04 25. " OE_INT_SET/CLR ,Overrun-Error interrupt" "Disabled,Enabled"
setclrfld.long 0x00 24. 0x00 24. 0x04 24. " PE_INT_SET/CLR ,Parity interrupt" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 17. 0x00 17. 0x04 17. " RX_DMA_SET/CLR ,Receive DMA" "Disabled,Enabled"
setclrfld.long 0x00 16. 0x00 16. 0x04 16. " TX_DMA_SET/CLR ,Transmit DMA" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 13. 0x00 13. 0x04 13. " ID_INT_SET/CLR ,ID interrupt" "Disabled,Enabled"
setclrfld.long 0x00 9. 0x00 9. 0x04 9. " RX_INT_SET/CLR ,Receiver interrupt enable" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 8. 0x00 8. 0x04 8. " TX_INT_SET/CLR ,Transmitter interrupt" "Disabled,Enabled"
setclrfld.long 0x00 7. 0x00 7. 0x04 7. " TOA3WUS_INT_SET/CLR ,Timeout after 3 wakeup signals interrupt" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 6. 0x00 6. 0x04 6. " TOAWUS_INT_SET/CLR ,Timeout after wakeup signal interrupt" "Disabled,Enabled"
setclrfld.long 0x00 4. 0x00 4. 0x04 4. " TIMEOUT_INT_SET/CLR ,Timeout interrupt" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 1. 0x00 1. 0x04 1. " WAKEUP_INT_SET/CLR ,Wake-up interrupt" "Disabled,Enabled"
else
group.long 0x0C++0x03
line.long 0x00 "SETINT,Interrupt Register"
setclrfld.long 0x00 26. 0x00 26. 0x04 26. " FE_INT_SET/CLR ,Framing-Error interrupt" "Disabled,Enabled"
setclrfld.long 0x00 25. 0x00 25. 0x04 25. " OE_INT_SET/CLR ,Overrun-Error interrupt" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 24. 0x00 24. 0x04 24. " PE_INT_SET/CLR ,Parity interrupt" "Disabled,Enabled"
setclrfld.long 0x00 18. 0x00 18. 0x04 18. " RX_DMA_ALL_SET/CLR ,Receive DMA all" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 17. 0x00 17. 0x04 17. " RX_DMA_SET/CLR ,Receive DMA" "Disabled,Enabled"
setclrfld.long 0x00 16. 0x00 16. 0x04 16. " TX_DMA_SET/CLR ,Transmit DMA" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 9. 0x00 9. 0x04 9. " RX_INT_SET/CLR ,Receiver interrupt enable" "Disabled,Enabled"
setclrfld.long 0x00 8. 0x00 8. 0x04 8. " TX_INT_SET/CLR ,Transmitter interrupt" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 1. 0x00 1. 0x04 1. " WAKEUP_INT_SET/CLR ,Wake-up interrupt" "Disabled,Enabled"
setclrfld.long 0x00 0. 0x00 0. 0x04 0. " BRKDT_INT_SET/CLR ,Break-detect interrupt" "Disabled,Enabled"
endif
if ((d.l(ad:0xFFF7E400+0x04)&0x040)==0x040)
group.long 0x14++0x03
line.long 0x00 "SETINTLVL,Interrupt Level Register"
setclrfld.long 0x00 31. 0x00 31. 0x04 31. " BE_INT_LVL_SET/CLR ,Bit error interrupt level" "INT0,INT1"
setclrfld.long 0x00 30. 0x00 30. 0x04 30. " PBE_INT_LVL_SET/CLR ,Physical bus error interrupt level" "INT0,INT1"
textline " "
setclrfld.long 0x00 29. 0x00 29. 0x04 29. " CE_INT_LVL_SET/CLR ,Checksum-Error interrupt level" "INT0,INT1"
setclrfld.long 0x00 28. 0x00 28. 0x04 28. " ISFE_INT_LVL_SET/CLR ,Inconsistent-Synch-Field-Error interrupt level" "INT0,INT1"
textline " "
setclrfld.long 0x00 27. 0x00 27. 0x04 27. " NRE_INT_LVL_SET/CLR ,No-Reponse-Error interrupt level" "INT0,INT1"
setclrfld.long 0x00 26. 0x00 26. 0x04 26. " FE_INT_LVL_SET/CLR ,Framing-Error interrupt level" "INT0,INT1"
textline " "
setclrfld.long 0x00 25. 0x00 25. 0x04 25. " OE_INT_LVL_SET/CLR ,Overrun-Error interrupt level" "INT0,INT1"
setclrfld.long 0x00 24. 0x00 24. 0x04 24. " PE_INT_LVL_SET/CLR ,Parity error interrupt level" "INT0,INT1"
textline " "
setclrfld.long 0x00 13. 0x00 13. 0x04 13. " ID_INT_LVL_SET/CLR ,ID interrupt level" "INT0,INT1"
setclrfld.long 0x00 9. 0x00 9. 0x04 9. " RX_INT_LVL_SET/CLR ,Receiver interrupt level" "INT0,INT1"
textline " "
setclrfld.long 0x00 8. 0x00 8. 0x04 8. " TX_INT_LVL_SET/CLR ,Transmitter interrupt level" "INT0,INT1"
setclrfld.long 0x00 7. 0x00 7. 0x04 7. " TOA3WUS_INT_LVL_SET/CLR ,Timeout after 3 wakeup signals interrupt" "INT0,INT1"
textline " "
setclrfld.long 0x00 6. 0x00 6. 0x04 6. " TOAWUS_INT_LVL_SET/CLR ,Timeout after wakeup signal interrupt level" "INT0,INT1"
setclrfld.long 0x00 4. 0x00 4. 0x04 4. " TIMEOUT_INT_LVL_SET/CLR ,Timeout interrupt level" "INT0,INT1"
textline " "
setclrfld.long 0x00 1. 0x00 1. 0x04 1. " WAKEUP_INT_LVL_SET/CLR ,Wake-up interrupt level" "INT0,INT1"
else
group.long 0x14++0x03
line.long 0x00 "SETINTLVL,Interrupt Level Register"
setclrfld.long 0x00 26. 0x00 26. 0x04 26. " FE_INT_LVL_SET/CLR ,Framing-Error interrupt level" "INT0,INT1"
setclrfld.long 0x00 25. 0x00 25. 0x04 25. " OE_INT_LVL_SET/CLR ,Overrun-Error interrupt level" "INT0,INT1"
textline " "
setclrfld.long 0x00 24. 0x00 24. 0x04 24. " PE_INT_LVL_SET/CLR ,Parity error interrupt level" "INT0,INT1"
setclrfld.long 0x00 18. 0x00 18. 0x04 18. " RX_DMA_ALL_INT_LVL_SET/CLR ,Receive DMA all interrupt level" "INT0,INT1"
textline " "
setclrfld.long 0x00 9. 0x00 9. 0x04 9. " RX_INT_LVL_SET/CLR ,Receiver interrupt level" "INT0,INT1"
setclrfld.long 0x00 8. 0x00 8. 0x04 8. " TX_INT_LVL_SET/CLR ,Transmitter interrupt level" "INT0,INT1"
textline " "
setclrfld.long 0x00 1. 0x00 1. 0x04 1. " WAKEUP_INT_LVL_SET/CLR ,Wake-up interrupt level" "INT0,INT1"
setclrfld.long 0x00 0. 0x00 0. 0x04 0. " BRKDT_INT_SET/CLR ,Break-Detect interrupt level" "INT0,INT1"
endif
tree.end
width 8.
textline " "
if ((d.l(ad:0xFFF7E400+0x04)&0x040)==0x040)
group.long 0x1C++0x03
line.long 0x00 "FLR,Flags Register"
eventfld.long 0x00 31. " BE ,Bit error flag" "Not detected,Detected"
eventfld.long 0x00 30. " PBE ,Physiscal bus error flag" "Not detected,Detected"
eventfld.long 0x00 29. " CE ,Checksum error flag" "Not detected,Detected"
eventfld.long 0x00 28. " ISFE ,Inconsistent synch field error flag" "Not detected,Detected"
textline " "
eventfld.long 0x00 27. " NRE ,No-Response error flag" "Not detected,Detected"
eventfld.long 0x00 26. " FE ,Framing error flag" "Not detected,Detected"
eventfld.long 0x00 25. " OE ,Overrun error flag" "Not detected,Detected"
eventfld.long 0x00 24. " PE ,Parity error flag" "Not detected,Detected"
textline " "
eventfld.long 0x00 14. " ID_RX_FLAG ,Identifier on receive flag" "Not received,Received"
eventfld.long 0x00 13. " ID_TX_FLAG ,Identifier on transmit flag" "Not received,Received"
bitfld.long 0x00 11. " TX_EMPTY ,Transmitter empty flag" "Not empty,Empty"
eventfld.long 0x00 9. " RXRDY ,Receiver ready flag" "Not ready,Ready"
textline " "
bitfld.long 0x00 8. " TXRDY ,Transmitter buffer register ready flag" "Full,Ready"
eventfld.long 0x00 7. " TOA3WUS ,Timeout after 3 wakeup signals flag" "No timeout,Timeout"
eventfld.long 0x00 6. " TOAWUS ,Timeout after wakeup signal flag" "No timeout,Timeout"
eventfld.long 0x00 4. " TIMEOUT ,LIN bus IDLE timeout flag" "Not detected,Detected"
textline " "
bitfld.long 0x00 3. " BUSY_FLAG ,BUSY flag" "Not busy,Busy"
eventfld.long 0x00 1. " WAKEUP ,Wake-up flag" "No wake up,Wake up"
else
group.long 0x1C++0x03
line.long 0x00 "FLR,Flags Register"
eventfld.long 0x00 31. " BE ,Bit error flag" "Not detected,Detected"
eventfld.long 0x00 26. " FE ,Framing error flag" "Not detected,Detected"
eventfld.long 0x00 25. " OE ,Overrun error flag" "Not detected,Detected"
eventfld.long 0x00 24. " PE ,Parity error flag" "Not detected,Detected"
textline " "
bitfld.long 0x00 12. " RXWAKE ,Receiver wakeup detect flag" "Not address,Address"
bitfld.long 0x00 11. " TX_EMPTY ,Transmitter empty flag" "Not empty,Empty"
bitfld.long 0x00 10. " TXWAKE ,SCI transmitter wakeup method select" "Data,Address"
eventfld.long 0x00 9. " RXRDY ,Receiver ready flag" "Not ready,Ready"
textline " "
bitfld.long 0x00 8. " TXRDY ,Transmitter buffer register ready flag (Scitd)" "Full,Ready"
bitfld.long 0x00 3. " BUSY_FLAG ,BUSY flag" "Not busy,Busy"
rbitfld.long 0x00 2. " IDLE ,SCI receiver in idle state" "Not detected,Detected"
eventfld.long 0x00 0. " BRKDT ,SCI Break-Detect flag" "Not detected,Detected"
endif
width 9.
tree "SCI Interrupt Vector Offset Registers"
hgroup.long 0x20++0x03
hide.long 0x00 "INVECT0,Interrupt Vector Offset 0"
in
hgroup.long 0x24++0x03
hide.long 0x00 "INVECT1,Interrupt Vector Offset 1"
in
tree.end
textline " "
if ((d.l(ad:0xFFF7E400+0x04)&0x040)==0x040)
group.long 0x28++0x03
line.long 0x00 "FORMAT,Format Control Register"
bitfld.long 0x00 16.--18. " LENGTH ,Frame length control bits" "1 byte,2 bytes,3 bytes,4 bytes,5 bytes,6 bytes,7 bytes,8 bytes"
elif (((d.l(ad:0xFFF7E400+0x04)&0x040)==0x00)&&(((d.l((ad:0xFFF7E400+0x004)))&0x00400)==0x00400))
group.long 0x28++0x03
line.long 0x00 "FORMAT,Format Control Register"
bitfld.long 0x00 16.--18. " LENGTH ,Frame length control bits" "1 character,2 characters,3 characters,4 characters,5 characters,6 characters,7 characters,8 characters"
bitfld.long 0x00 0.--2. " CHAR ,Character length control bits" "1 bit,2 bits,3 bits,4 bits,5 bits,6 bits,7 bits,8 bits"
else
group.long 0x28++0x03
line.long 0x00 "FORMAT,Format Control Register"
bitfld.long 0x00 0.--2. " CHAR ,Character length control bits" "1 bit,2 bits,3 bits,4 bits,5 bits,6 bits,7 bits,8 bits"
endif
if (((d.l(ad:0xFFF7E400+0x04))&0x02)==0x02)
group.long 0x2C++0x03
line.long 0x00 "BRSR,Baud Rate Selection Register"
hexmask.long.byte 0x00 28.--30. 1. " U ,SCI/BLIN super fractional divider selection"
hexmask.long.byte 0x00 24.--27. 1. " M ,SCI/BLIN 4-bit fractional divider selection"
hexmask.long.tbyte 0x00 0.--23. 1. " PRESCALER_P ,SCI/BLIN 24-bit integer prescaler selection"
else
group.long 0x2C++0x03
line.long 0x00 "BRSR,Baud Rate Selection Register"
hexmask.long.byte 0x00 28.--30. 1. " U ,SCI/BLIN super fractional divider selection"
hexmask.long.byte 0x00 24.--27. 1. " M ,SCI/BLIN 4-bit fractional divider selection"
endif
tree "SCI Data Buffer Registers"
if ((d.l(ad:0xFFF7E400+0x04)&0x040)==0x00)
rgroup.long 0x30++0x03
line.long 0x00 "ED,SCI Data Buffer"
hexmask.long.byte 0x00 0.--7. 1. " ED ,Emulation data"
hgroup.long 0x34++0x03
hide.long 0x00 "RD,SCI Data Buffer"
in
group.long 0x38++0x03
line.long 0x00 "TD,SCI Data Buffer"
hexmask.long.byte 0x00 0.--7. 1. " TD ,Transmit data"
else
hgroup.long 0x30++0x03
hide.long 0x00 "ED,SCI Data Buffer"
in
hgroup.long 0x34++0x03
hide.long 0x00 "RD,SCI Data Buffer"
in
hgroup.long 0x38++0x03
hide.long 0x00 "TD,SCI Data Buffer"
in
endif
tree.end
width 6.
tree "SCI Pin I/O Control Registers"
group.long 0x3C++0x03
line.long 0x00 "PIO0,Pin I/O Control Register 0"
bitfld.long 0x00 2. " TX_FUNC ,Defines the function of pin SCITX" "GPIO,SCITX"
bitfld.long 0x00 1. " RX_FUNC ,Defines the function of pin SCIRX" "GPIO,SCIRX"
group.long 0x40++0x03
line.long 0x00 "PIO1,Pin I/O Control Register 1"
bitfld.long 0x00 2. " TX_DIR ,Transmit direction" "Input,Output"
bitfld.long 0x00 1. " RX_DIR ,Receive direction" "Input,Output"
rgroup.long 0x44++0x03
line.long 0x00 "PIO2,Pin I/O Control Register 2"
bitfld.long 0x00 2. " TX_IN ,Contains current value on the SCITX pin" "Low,High"
bitfld.long 0x00 1. " RX_IN ,Contains current value on the SCIRX pin" "Low,High"
group.long 0x48++0x03
line.long 0x00 "PIO3,Pin I/O Control Register 3"
setclrfld.long 0x00 2. 0x04 2. 0x08 2. " TX_OUT_SET/CLR ,SCITX pin data output" "Low,High"
setclrfld.long 0x00 1. 0x04 1. 0x08 1. " RX_OUT_SET/CLR ,SCIRX pin data output" "Low,High"
group.long 0x54++0x03
line.long 0x00 "PIO6,Pin I/O Control Register 6"
bitfld.long 0x00 2. " TX_PDR ,TX open drain enable" "Disabled,Enabled"
bitfld.long 0x00 1. " RX_PDR ,RX open drain enable" "Disabled,Enabled"
group.long 0x58++0x03
line.long 0x00 "PIO7,Pin I/O Control Register 7"
bitfld.long 0x00 2. " TX_PD ,TX pin pull control disable" "Enabled,Disabled"
bitfld.long 0x00 1. " RX_PD ,RX pin pull control disable" "Enabled,Disabled"
group.long 0x5C++0x03
line.long 0x00 "PIO8,Pin I/O Control Register 8"
bitfld.long 0x00 2. " TX_PSL ,TX pin pull select" "Pull down,Pull up"
bitfld.long 0x00 1. " RX_PSL ,RX pin pull select" "Pull down,Pull up"
tree.end
width 9.
tree "BLIN Registers"
if ((d.l(ad:0xFFF7E400+0x04)&0x040)==0x040)
group.long 0x60++0x03
line.long 0x00 "LINCOMP,BLINCOMPARE Register"
bitfld.long 0x00 8.--9. " SDEL ,2-bit synch delimiter compare" "1 bit,2 bits,3 bits,4 bits"
bitfld.long 0x00 0.--2. " SBREAK ,3-bit synch break extend" "Not extended,1 bit,2 bits,3 bits,4 bits,5 bits,6 bits,7 bits"
else
hgroup.long 0x60++0x03
hide.long 0x00 "LINCOMP,BLINCOMPARE Register"
endif
rgroup.long 0x64++0x03
line.long 0x00 "LINRD0,LINRD0 Register"
hexmask.long.byte 0x00 24.--31. 0x01 " RD0 ,Receive buffer 0"
hexmask.long.byte 0x00 16.--23. 0x01 " RD1 ,Receive buffer 1"
hexmask.long.byte 0x00 8.--15. 0x01 " RD2 ,Receive buffer 2"
hexmask.long.byte 0x00 0.--7. 0x01 " RD3 ,Receive buffer 3"
rgroup.long 0x68++0x03
line.long 0x00 "LINRD1,LINRD1 Register"
hexmask.long.byte 0x00 24.--31. 0x01 " RD4 ,Receive buffer 4"
hexmask.long.byte 0x00 16.--23. 0x01 " RD5 ,Receive buffer 5"
hexmask.long.byte 0x00 8.--15. 0x01 " RD6 ,Receive buffer 6"
hexmask.long.byte 0x00 0.--7. 0x01 " RD7 ,Receive buffer 7"
if ((d.l(ad:0xFFF7E400+0x04)&0x040)==0x040)
group.long 0x6C++0x03
line.long 0x00 "LINMASK,LINMASK Register"
bitfld.long 0x00 23. " RX_ID_MASK7 ,RX ID mask 7" "Not masked,Masked"
bitfld.long 0x00 22. " RX_ID_MASK6 ,RX ID mask 6" "Not masked,Masked"
bitfld.long 0x00 21. " RX_ID_MASK5 ,RX ID mask 5" "Not masked,Masked"
bitfld.long 0x00 20. " RX_ID_MASK4 ,RX ID mask 4" "Not masked,Masked"
textline " "
bitfld.long 0x00 19. " RX_ID_MASK3 ,RX ID mask 3" "Not masked,Masked"
bitfld.long 0x00 18. " RX_ID_MASK2 ,RX ID mask 2" "Not masked,Masked"
bitfld.long 0x00 17. " RX_ID_MASK1 ,RX ID mask 1" "Not masked,Masked"
bitfld.long 0x00 16. " RX_ID_MASK0 ,RX ID mask 0" "Not masked,Masked"
textline " "
bitfld.long 0x00 7. " TX_ID_MASK7 ,TX ID mask 7" "Not masked,Masked"
bitfld.long 0x00 6. " TX_ID_MASK6 ,TX ID mask 6" "Not masked,Masked"
bitfld.long 0x00 5. " TX_ID_MASK5 ,TX ID mask 5" "Not masked,Masked"
bitfld.long 0x00 4. " TX_ID_MASK4 ,TX ID mask 4" "Not masked,Masked"
textline " "
bitfld.long 0x00 3. " TX_ID_MASK3 ,TX ID mask 3" "Not masked,Masked"
bitfld.long 0x00 2. " TX_ID_MASK2 ,TX ID mask 2" "Not masked,Masked"
bitfld.long 0x00 1. " TX_ID_MASK1 ,TX ID mask 1" "Not masked,Masked"
bitfld.long 0x00 0. " TX_ID_MASK0 ,TX ID mask 0" "Not masked,Masked"
else
hgroup.long 0x6C++0x03
hide.long 0x00 "LINMASK,LINMASK Register"
endif
if ((d.l(ad:0xFFF7E400+0x04)&0x040)==0x040)
group.long 0x70++0x03
line.long 0x00 "LINID,LINID Register"
hexmask.long.byte 0x00 16.--23. 1. " RECEIVED_ID ,Received identifier"
hexmask.long.byte 0x00 8.--15. 1. " ID_SLAVETASK_BYTE ,Identifier slave task byte"
hexmask.long.byte 0x00 0.--7. 1. " ID_BYTE ,Identifier byte"
else
hgroup.long 0x70++0x03
hide.long 0x00 "LINID,LINID Register"
endif
group.long 0x74++0x03
line.long 0x00 "LINTD0,LINTD0 Register"
hexmask.long.byte 0x00 24.--31. 1. " TD0 ,8-bit transmit buffer 0"
hexmask.long.byte 0x00 16.--23. 1. " TD1 ,8-bit transmit buffer 1"
hexmask.long.byte 0x00 8.--15. 1. " TD2 ,8-bit transmit buffer 2"
hexmask.long.byte 0x00 0.--7. 1. " TD3 ,8-bit transmit buffer 3"
group.long 0x78++0x03
line.long 0x00 "LINTD1,LINTD1 Register"
hexmask.long.byte 0x00 24.--31. 1. " TD4 ,8-bit transmit buffer 4"
hexmask.long.byte 0x00 16.--23. 1. " TD5 ,8-bit transmit buffer 5"
hexmask.long.byte 0x00 8.--15. 1. " TD6 ,8-bit transmit buffer 6"
hexmask.long.byte 0x00 0.--7. 1. " TD7 ,8-bit transmit buffer 7"
tree.end
width 11.
if ((d.l(ad:0xFFF7E400+0x04)&0x040)==0x040)
group.long 0x7C++0x03
line.long 0x00 "MBRSR,Maximum Baud Rate Selection Register"
hexmask.long.word 0x00 0.--12. 1. " MBR ,Maximum baud rate prescaler"
else
hgroup.long 0x7C++0x03
hide.long 0x00 "MBRSR,Maximum Baud Rate Selection Register"
endif
if (((d.l(ad:0xFFF7E400+0x04))&0x040)==0x040)&&(((d.l(ad:0xFFF7E400+0x90))&0xF00)==0xA00)
group.long 0x90++0x03
line.long 0x00 "IODFTCTRL,Input/output Error Enable Register"
bitfld.long 0x00 31. " BEN ,Bit error enable" "Disabled,Enabled"
bitfld.long 0x00 30. " PBEN ,Physical bus error enable" "Disabled,Enabled"
bitfld.long 0x00 29. " CEN ,Checksum error enable" "Disabled,Enabled"
bitfld.long 0x00 28. " ISFE ,Inconsistent synch field error enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 26. " FEN ,Frame error enable" "Disabled,Enabled"
bitfld.long 0x00 19.--20. " PIN_SAMPLE_MASK ,PIN SAMPLE MASK" "No mask,TBIT_CENTER,TBIT_CENTER + SCLK,TBIT_CENTER + 2 SCLK"
bitfld.long 0x00 16.--18. " TX_SHIFT ,Transmit shift" "No delay,1 SCLK,2 sclks,3 sclks,4 sclks,5 sclks,6 sclks,7 sclks"
bitfld.long 0x00 8.--11. " IODFTENA ,IO DFT enable key" "Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Enabled,Disabled,Disabled,Disabled,Disabled,Disabled"
textline " "
bitfld.long 0x00 1. " LPBENA ,Module loopback enable" "Digital,Analog"
bitfld.long 0x00 0. " RXPENA ,Module analog loopback through receive/transmit pin enable" "Transmit,Receive"
elif (((d.l(ad:0xFFF7E400+0x04))&0x040)==0x00)&&(((d.l(ad:0xFFF7E400+0x90))&0xF00)==0xA00)
group.long 0x90++0x03
line.long 0x00 "IODFTCTRL,Input/output Error Enable Register"
bitfld.long 0x00 26. " FEN ,Frame error enable" "Disabled,Enabled"
bitfld.long 0x00 19.--20. " PIN_SAMPLE_MASK ,PIN SAMPLE MASK" "No mask,TBIT_CENTER,TBIT_CENTER + SCLK,TBIT_CENTER + 2 SCLK"
bitfld.long 0x00 16.--18. " TX_SHIFT ,Transmit shift" "No delay,1 SCLK,2 sclks,3 sclks,4 sclks,5 sclks,6 sclks,7 sclks"
bitfld.long 0x00 8.--11. " IODFTENA ,IO DFT enable key" "Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Enabled,Disabled,Disabled,Disabled,Disabled,Disabled"
textline " "
bitfld.long 0x00 1. " LPBENA ,Module loopback enable" "Digital,Analog"
bitfld.long 0x00 0. " RXPENA ,Module analog loopback through receive/transmit pin enable" "Transmit,Receive"
elif (((d.l(ad:0xFFF7E400+0x04))&0x040)==0x00)&&(((d.l(ad:0xFFF7E400+0x90))&0xF00)!=0xA00)
group.long 0x90++0x03
line.long 0x00 "IODFTCTRL,Input/output Error Enable Register"
bitfld.long 0x00 26. " FEN ,Frame error enable" "Disabled,Enabled"
textline " "
sif cpu()=="RM57L843-ZWT"
bitfld.long 0x00 25. " PEN ,Parity error enable" "Disabled,Enabled"
textline " "
endif
bitfld.long 0x00 19.--20. " PIN_SAMPLE_MASK ,PIN SAMPLE MASK" "No mask,TBIT_CENTER,TBIT_CENTER + SCLK,TBIT_CENTER + 2 SCLK"
bitfld.long 0x00 16.--18. " TX_SHIFT ,Transmit shift" "No delay,1 SCLK,2 sclks,3 sclks,4 sclks,5 sclks,6 sclks,7 sclks"
bitfld.long 0x00 8.--11. " IODFTENA ,IO DFT enable key" "Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Enabled,Disabled,Disabled,Disabled,Disabled,Disabled"
textline " "
bitfld.long 0x00 1. " LPBENA ,Module loopback enable" "Digital,?..."
else
group.long 0x90++0x03
line.long 0x00 "IODFTCTRL,Input/output Error Enable Register"
bitfld.long 0x00 31. " BEN ,Bit error enable" "Disabled,Enabled"
bitfld.long 0x00 30. " PBEN ,Physical bus error enable" "Disabled,Enabled"
bitfld.long 0x00 29. " CEN ,Checksum error enable" "Disabled,Enabled"
bitfld.long 0x00 28. " ISFE ,Inconsistent synch field error enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 26. " FEN ,Frame error enable" "Disabled,Enabled"
bitfld.long 0x00 19.--20. " PIN_SAMPLE_MASK ,PIN SAMPLE MASK" "No mask,TBIT_CENTER,TBIT_CENTER + SCLK,TBIT_CENTER + 2 SCLK"
bitfld.long 0x00 16.--18. " TX_SHIFT ,Transmit shift" "No delay,1 SCLK,2 sclks,3 sclks,4 sclks,5 sclks,6 sclks,7 sclks"
bitfld.long 0x00 8.--11. " IODFTENA ,IO DFT enable key" "Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Enabled,Disabled,Disabled,Disabled,Disabled,Disabled"
textline " "
bitfld.long 0x00 1. " LPBENA ,Module loopback enable" "Digital,?..."
endif
width 0x0B
tree.end
tree "SCI/LIN2"
base ad:0xFFF7E600
width 8.
group.long 0x00++0x03
line.long 0x00 "GCR0,Global Control Register"
bitfld.long 0x00 0. " RESET ,SCI/LIN module reset" "Under reset,Out of reset"
if ((d.l(ad:0xFFF7E600+0x04)&0x044)==0x044)
group.long 0x04++0x03
line.long 0x00 "GCR1,Global Control Register"
bitfld.long 0x00 25. " TXENA ,SCI transmitter enable" "Disabled,Enabled"
bitfld.long 0x00 24. " RXENA ,SCI receiver enable" "Prevented,Allowed"
bitfld.long 0x00 17. " CONT ,Continue on suspend" "Frozen,Continue"
bitfld.long 0x00 16. " LOOP_BACK ,LOOP BACK enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 13. " STOP_EXT_FRAME ,Stop extended frame communication" "Not stopped,Stopped"
bitfld.long 0x00 12. " HGEN_CTRL ,LIN mode bit (Type of mask filtering comparison)" "Id-byte,ID-Slave task byte"
bitfld.long 0x00 11. " CTYPE ,Checksum type" "Classic,Enhanced"
bitfld.long 0x00 10. " MBUF_MODE ,Receive/transmit buffer enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 9. " ADAPT ,LIN mode bit (Automatic baudrate adjustment)" "Disabled,Enabled"
bitfld.long 0x00 8. " SLEEP ,SCI sleep enable" "Disabled,Enabled"
bitfld.long 0x00 7. " SW_NRESET ,Software reset" "Reset,Ready"
bitfld.long 0x00 6. " LIN_MODE ,LIN MODE enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 5. " CLOCK ,SCI internal clock enable" "Slave,Master"
bitfld.long 0x00 4. " STOP ,SCI number of stop bits" "1 bit,2 bits"
bitfld.long 0x00 3. " PARITY ,SCI parity odd/even selection" "Odd,Even"
bitfld.long 0x00 2. " PARITY_ENA ,ID-Parity enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 1. " TIMING_MODE ,SCI timing mode bit" "Synchronous,Asynchronous"
bitfld.long 0x00 0. " COMM_MODE ,SCI/BLIN communication mode bit ID4 and ID5 use" "Not used,Used"
elif ((d.l(ad:0xFFF7E600+0x04)&0x044)==0x040)
group.long 0x04++0x03
line.long 0x00 "GCR1,Global Control Register"
bitfld.long 0x00 25. " TXENA ,SCI transmitter enable" "Disabled,Enabled"
bitfld.long 0x00 24. " RXENA ,SCI receiver enable" "Prevented,Allowed"
bitfld.long 0x00 17. " CONT ,Continue on suspend" "Frozen,Continue"
bitfld.long 0x00 16. " LOOP_BACK ,LOOP BACK enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 13. " STOP_EXT_FRAME ,Stop extended frame communication" "Not stopped,Stopped"
bitfld.long 0x00 12. " HGEN_CTRL ,LIN mode bit (Type of mask filtering comparison)" "Id-byte,Id-slavetask"
bitfld.long 0x00 11. " CTYPE ,Checksum type" "Classic,Enhanced"
bitfld.long 0x00 10. " MBUF_MODE ,Receive/transmit buffer enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 9. " ADAPT ,LIN mode bit (Automatic baudrate adjustment)" "Disabled,Enabled"
bitfld.long 0x00 8. " SLEEP ,SCI sleep enable" "Disabled,Enabled"
bitfld.long 0x00 7. " SW_NRESET ,Software reset" "Reset,Ready"
bitfld.long 0x00 6. " LIN_MODE ,LIN MODE enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 5. " CLOCK ,SCI internal clock enable" "Slave,Master"
bitfld.long 0x00 4. " STOP ,SCI number of stop bits" "1 bit,2 bits"
bitfld.long 0x00 2. " PARITY_ENA ,ID-Parity enable" "Disabled,Enabled"
bitfld.long 0x00 1. " TIMING_MODE ,SCI timing mode bit" "Synchronous,Asynchronous"
textline " "
bitfld.long 0x00 0. " COMM_MODE ,SCI/BLIN communication mode bit ID4 and ID5 use" "Not used,Used"
elif (((d.l((ad:0xFFF7E600+0x04)))&0x044)==0x04)
group.long 0x04++0x03
line.long 0x00 "GCR1,Global Control Register"
bitfld.long 0x00 25. " TXENA ,SCI transmitter enable" "Disabled,Enabled"
bitfld.long 0x00 24. " RXENA ,SCI receiver enable" "Prevented,Allowed"
bitfld.long 0x00 17. " CONT ,Continue on suspend" "Frozen,Continue"
bitfld.long 0x00 16. " LOOP_BACK ,LOOP BACK enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 10. " MBUF_MODE ,Receive/transmit buffer enable" "Disabled,Enabled"
bitfld.long 0x00 8. " SLEEP ,SCI sleep enable" "Disabled,Enabled"
bitfld.long 0x00 7. " SW_NRESET ,Software reset" "Reset,Ready"
bitfld.long 0x00 6. " LIN_MODE ,LIN MODE enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 5. " CLOCK ,SCI internal clock enable" "External,Internal"
bitfld.long 0x00 4. " STOP ,SCI number of stop bits" "1 bit,2 bits"
bitfld.long 0x00 3. " PARITY ,SCI parity odd/even selection" "Odd,Even"
bitfld.long 0x00 2. " PARITY_ENA ,Parity enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 1. " TIMING_MODE ,SCI timing mode bit" "Synchronous,Asynchronous"
bitfld.long 0x00 0. " COMM_MODE ,SCI/BLIN communication mode bit" "Idle-line,Address-bit"
else
group.long 0x04++0x03
line.long 0x00 "GCR1,Global Control Register"
bitfld.long 0x00 25. " TXENA ,SCI transmitter enable" "Disabled,Enabled"
bitfld.long 0x00 24. " RXENA ,SCI receiver enable" "Prevented,Allowed"
bitfld.long 0x00 17. " CONT ,Continue on suspend" "Frozen,Continue"
bitfld.long 0x00 16. " LOOP_BACK ,LOOP BACK enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 10. " MBUF_MODE ,Receive/transmit buffer enable" "Disabled,Enabled"
bitfld.long 0x00 8. " SLEEP ,SCI sleep enable" "Disabled,Enabled"
bitfld.long 0x00 7. " SW_NRESET ,Software reset" "Reset,Ready"
bitfld.long 0x00 6. " LIN_MODE ,LIN MODE enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 5. " CLOCK ,SCI internal clock enable" "External,Internal"
bitfld.long 0x00 4. " STOP ,SCI number of stop bits" "1 bit,2 bits"
bitfld.long 0x00 2. " PARITY_ENA ,Parity enable" "Disabled,Enabled"
bitfld.long 0x00 1. " TIMING_MODE ,SCI timing mode bit" "Synchronous,Asynchronous"
textline " "
bitfld.long 0x00 0. " COMM_MODE ,SCI/BLIN communication mode bit" "Idle-line,Address-bit"
endif
if ((d.l(ad:0xFFF7E600+0x04)&0x040)==0x040)
group.long 0x08++0x03
line.long 0x00 "GCR2,Global Control Register"
bitfld.long 0x00 17. " CC ,Compare checksum" "No effect,Compared"
bitfld.long 0x00 16. " SC ,Send checksum" "No effect,Compared"
bitfld.long 0x00 8. " GEN_WU ,Generate wakeup signal" "No effect,Generated"
bitfld.long 0x00 0. " POWERDOWN ,POWERDOWN" "Normal,Local low-power"
else
group.long 0x08++0x03
line.long 0x00 "GCR2,Global Control Register"
bitfld.long 0x00 0. " POWERDOWN ,POWERDOWN" "Normal,Local low-power"
endif
width 11.
tree "SCI Interrupt Registers"
if ((d.l(ad:0xFFF7E600+0x04)&0x040)==0x040)
group.long 0x0C++0x03
line.long 0x00 "SETINT,Interrupt Register"
setclrfld.long 0x00 31. 0x00 31. 0x04 31. " BE_INT_SET/CLR ,Bit error interrupt" "Disabled,Enabled"
setclrfld.long 0x00 30. 0x00 30. 0x04 30. " PBE_INT_SET/CLR ,Physical bus error interrupt" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 29. 0x00 29. 0x04 29. " CE_INT_SET/CLR ,Checksum-Error interrupt" "Disabled,Enabled"
setclrfld.long 0x00 28. 0x00 28. 0x04 28. " ISFE_INT_SET/CLR ,Inconsistent-Synch-Field-Error interrupt" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 27. 0x00 27. 0x04 27. " NRE_INT_SET/CLR ,No-Reponse-Error interrupt" "Disabled,Enabled"
setclrfld.long 0x00 26. 0x00 26. 0x04 26. " FE_INT_SET/CLR ,Framing-Error interrupt" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 25. 0x00 25. 0x04 25. " OE_INT_SET/CLR ,Overrun-Error interrupt" "Disabled,Enabled"
setclrfld.long 0x00 24. 0x00 24. 0x04 24. " PE_INT_SET/CLR ,Parity interrupt" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 17. 0x00 17. 0x04 17. " RX_DMA_SET/CLR ,Receive DMA" "Disabled,Enabled"
setclrfld.long 0x00 16. 0x00 16. 0x04 16. " TX_DMA_SET/CLR ,Transmit DMA" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 13. 0x00 13. 0x04 13. " ID_INT_SET/CLR ,ID interrupt" "Disabled,Enabled"
setclrfld.long 0x00 9. 0x00 9. 0x04 9. " RX_INT_SET/CLR ,Receiver interrupt enable" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 8. 0x00 8. 0x04 8. " TX_INT_SET/CLR ,Transmitter interrupt" "Disabled,Enabled"
setclrfld.long 0x00 7. 0x00 7. 0x04 7. " TOA3WUS_INT_SET/CLR ,Timeout after 3 wakeup signals interrupt" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 6. 0x00 6. 0x04 6. " TOAWUS_INT_SET/CLR ,Timeout after wakeup signal interrupt" "Disabled,Enabled"
setclrfld.long 0x00 4. 0x00 4. 0x04 4. " TIMEOUT_INT_SET/CLR ,Timeout interrupt" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 1. 0x00 1. 0x04 1. " WAKEUP_INT_SET/CLR ,Wake-up interrupt" "Disabled,Enabled"
else
group.long 0x0C++0x03
line.long 0x00 "SETINT,Interrupt Register"
setclrfld.long 0x00 26. 0x00 26. 0x04 26. " FE_INT_SET/CLR ,Framing-Error interrupt" "Disabled,Enabled"
setclrfld.long 0x00 25. 0x00 25. 0x04 25. " OE_INT_SET/CLR ,Overrun-Error interrupt" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 24. 0x00 24. 0x04 24. " PE_INT_SET/CLR ,Parity interrupt" "Disabled,Enabled"
setclrfld.long 0x00 18. 0x00 18. 0x04 18. " RX_DMA_ALL_SET/CLR ,Receive DMA all" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 17. 0x00 17. 0x04 17. " RX_DMA_SET/CLR ,Receive DMA" "Disabled,Enabled"
setclrfld.long 0x00 16. 0x00 16. 0x04 16. " TX_DMA_SET/CLR ,Transmit DMA" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 9. 0x00 9. 0x04 9. " RX_INT_SET/CLR ,Receiver interrupt enable" "Disabled,Enabled"
setclrfld.long 0x00 8. 0x00 8. 0x04 8. " TX_INT_SET/CLR ,Transmitter interrupt" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 1. 0x00 1. 0x04 1. " WAKEUP_INT_SET/CLR ,Wake-up interrupt" "Disabled,Enabled"
setclrfld.long 0x00 0. 0x00 0. 0x04 0. " BRKDT_INT_SET/CLR ,Break-detect interrupt" "Disabled,Enabled"
endif
if ((d.l(ad:0xFFF7E600+0x04)&0x040)==0x040)
group.long 0x14++0x03
line.long 0x00 "SETINTLVL,Interrupt Level Register"
setclrfld.long 0x00 31. 0x00 31. 0x04 31. " BE_INT_LVL_SET/CLR ,Bit error interrupt level" "INT0,INT1"
setclrfld.long 0x00 30. 0x00 30. 0x04 30. " PBE_INT_LVL_SET/CLR ,Physical bus error interrupt level" "INT0,INT1"
textline " "
setclrfld.long 0x00 29. 0x00 29. 0x04 29. " CE_INT_LVL_SET/CLR ,Checksum-Error interrupt level" "INT0,INT1"
setclrfld.long 0x00 28. 0x00 28. 0x04 28. " ISFE_INT_LVL_SET/CLR ,Inconsistent-Synch-Field-Error interrupt level" "INT0,INT1"
textline " "
setclrfld.long 0x00 27. 0x00 27. 0x04 27. " NRE_INT_LVL_SET/CLR ,No-Reponse-Error interrupt level" "INT0,INT1"
setclrfld.long 0x00 26. 0x00 26. 0x04 26. " FE_INT_LVL_SET/CLR ,Framing-Error interrupt level" "INT0,INT1"
textline " "
setclrfld.long 0x00 25. 0x00 25. 0x04 25. " OE_INT_LVL_SET/CLR ,Overrun-Error interrupt level" "INT0,INT1"
setclrfld.long 0x00 24. 0x00 24. 0x04 24. " PE_INT_LVL_SET/CLR ,Parity error interrupt level" "INT0,INT1"
textline " "
setclrfld.long 0x00 13. 0x00 13. 0x04 13. " ID_INT_LVL_SET/CLR ,ID interrupt level" "INT0,INT1"
setclrfld.long 0x00 9. 0x00 9. 0x04 9. " RX_INT_LVL_SET/CLR ,Receiver interrupt level" "INT0,INT1"
textline " "
setclrfld.long 0x00 8. 0x00 8. 0x04 8. " TX_INT_LVL_SET/CLR ,Transmitter interrupt level" "INT0,INT1"
setclrfld.long 0x00 7. 0x00 7. 0x04 7. " TOA3WUS_INT_LVL_SET/CLR ,Timeout after 3 wakeup signals interrupt" "INT0,INT1"
textline " "
setclrfld.long 0x00 6. 0x00 6. 0x04 6. " TOAWUS_INT_LVL_SET/CLR ,Timeout after wakeup signal interrupt level" "INT0,INT1"
setclrfld.long 0x00 4. 0x00 4. 0x04 4. " TIMEOUT_INT_LVL_SET/CLR ,Timeout interrupt level" "INT0,INT1"
textline " "
setclrfld.long 0x00 1. 0x00 1. 0x04 1. " WAKEUP_INT_LVL_SET/CLR ,Wake-up interrupt level" "INT0,INT1"
else
group.long 0x14++0x03
line.long 0x00 "SETINTLVL,Interrupt Level Register"
setclrfld.long 0x00 26. 0x00 26. 0x04 26. " FE_INT_LVL_SET/CLR ,Framing-Error interrupt level" "INT0,INT1"
setclrfld.long 0x00 25. 0x00 25. 0x04 25. " OE_INT_LVL_SET/CLR ,Overrun-Error interrupt level" "INT0,INT1"
textline " "
setclrfld.long 0x00 24. 0x00 24. 0x04 24. " PE_INT_LVL_SET/CLR ,Parity error interrupt level" "INT0,INT1"
setclrfld.long 0x00 18. 0x00 18. 0x04 18. " RX_DMA_ALL_INT_LVL_SET/CLR ,Receive DMA all interrupt level" "INT0,INT1"
textline " "
setclrfld.long 0x00 9. 0x00 9. 0x04 9. " RX_INT_LVL_SET/CLR ,Receiver interrupt level" "INT0,INT1"
setclrfld.long 0x00 8. 0x00 8. 0x04 8. " TX_INT_LVL_SET/CLR ,Transmitter interrupt level" "INT0,INT1"
textline " "
setclrfld.long 0x00 1. 0x00 1. 0x04 1. " WAKEUP_INT_LVL_SET/CLR ,Wake-up interrupt level" "INT0,INT1"
setclrfld.long 0x00 0. 0x00 0. 0x04 0. " BRKDT_INT_SET/CLR ,Break-Detect interrupt level" "INT0,INT1"
endif
tree.end
width 8.
textline " "
if ((d.l(ad:0xFFF7E600+0x04)&0x040)==0x040)
group.long 0x1C++0x03
line.long 0x00 "FLR,Flags Register"
eventfld.long 0x00 31. " BE ,Bit error flag" "Not detected,Detected"
eventfld.long 0x00 30. " PBE ,Physiscal bus error flag" "Not detected,Detected"
eventfld.long 0x00 29. " CE ,Checksum error flag" "Not detected,Detected"
eventfld.long 0x00 28. " ISFE ,Inconsistent synch field error flag" "Not detected,Detected"
textline " "
eventfld.long 0x00 27. " NRE ,No-Response error flag" "Not detected,Detected"
eventfld.long 0x00 26. " FE ,Framing error flag" "Not detected,Detected"
eventfld.long 0x00 25. " OE ,Overrun error flag" "Not detected,Detected"
eventfld.long 0x00 24. " PE ,Parity error flag" "Not detected,Detected"
textline " "
eventfld.long 0x00 14. " ID_RX_FLAG ,Identifier on receive flag" "Not received,Received"
eventfld.long 0x00 13. " ID_TX_FLAG ,Identifier on transmit flag" "Not received,Received"
bitfld.long 0x00 11. " TX_EMPTY ,Transmitter empty flag" "Not empty,Empty"
eventfld.long 0x00 9. " RXRDY ,Receiver ready flag" "Not ready,Ready"
textline " "
bitfld.long 0x00 8. " TXRDY ,Transmitter buffer register ready flag" "Full,Ready"
eventfld.long 0x00 7. " TOA3WUS ,Timeout after 3 wakeup signals flag" "No timeout,Timeout"
eventfld.long 0x00 6. " TOAWUS ,Timeout after wakeup signal flag" "No timeout,Timeout"
eventfld.long 0x00 4. " TIMEOUT ,LIN bus IDLE timeout flag" "Not detected,Detected"
textline " "
bitfld.long 0x00 3. " BUSY_FLAG ,BUSY flag" "Not busy,Busy"
eventfld.long 0x00 1. " WAKEUP ,Wake-up flag" "No wake up,Wake up"
else
group.long 0x1C++0x03
line.long 0x00 "FLR,Flags Register"
eventfld.long 0x00 31. " BE ,Bit error flag" "Not detected,Detected"
eventfld.long 0x00 26. " FE ,Framing error flag" "Not detected,Detected"
eventfld.long 0x00 25. " OE ,Overrun error flag" "Not detected,Detected"
eventfld.long 0x00 24. " PE ,Parity error flag" "Not detected,Detected"
textline " "
bitfld.long 0x00 12. " RXWAKE ,Receiver wakeup detect flag" "Not address,Address"
bitfld.long 0x00 11. " TX_EMPTY ,Transmitter empty flag" "Not empty,Empty"
bitfld.long 0x00 10. " TXWAKE ,SCI transmitter wakeup method select" "Data,Address"
eventfld.long 0x00 9. " RXRDY ,Receiver ready flag" "Not ready,Ready"
textline " "
bitfld.long 0x00 8. " TXRDY ,Transmitter buffer register ready flag (Scitd)" "Full,Ready"
bitfld.long 0x00 3. " BUSY_FLAG ,BUSY flag" "Not busy,Busy"
rbitfld.long 0x00 2. " IDLE ,SCI receiver in idle state" "Not detected,Detected"
eventfld.long 0x00 0. " BRKDT ,SCI Break-Detect flag" "Not detected,Detected"
endif
width 9.
tree "SCI Interrupt Vector Offset Registers"
hgroup.long 0x20++0x03
hide.long 0x00 "INVECT0,Interrupt Vector Offset 0"
in
hgroup.long 0x24++0x03
hide.long 0x00 "INVECT1,Interrupt Vector Offset 1"
in
tree.end
textline " "
if ((d.l(ad:0xFFF7E600+0x04)&0x040)==0x040)
group.long 0x28++0x03
line.long 0x00 "FORMAT,Format Control Register"
bitfld.long 0x00 16.--18. " LENGTH ,Frame length control bits" "1 byte,2 bytes,3 bytes,4 bytes,5 bytes,6 bytes,7 bytes,8 bytes"
elif (((d.l(ad:0xFFF7E600+0x04)&0x040)==0x00)&&(((d.l((ad:0xFFF7E600+0x004)))&0x00400)==0x00400))
group.long 0x28++0x03
line.long 0x00 "FORMAT,Format Control Register"
bitfld.long 0x00 16.--18. " LENGTH ,Frame length control bits" "1 character,2 characters,3 characters,4 characters,5 characters,6 characters,7 characters,8 characters"
bitfld.long 0x00 0.--2. " CHAR ,Character length control bits" "1 bit,2 bits,3 bits,4 bits,5 bits,6 bits,7 bits,8 bits"
else
group.long 0x28++0x03
line.long 0x00 "FORMAT,Format Control Register"
bitfld.long 0x00 0.--2. " CHAR ,Character length control bits" "1 bit,2 bits,3 bits,4 bits,5 bits,6 bits,7 bits,8 bits"
endif
if (((d.l(ad:0xFFF7E600+0x04))&0x02)==0x02)
group.long 0x2C++0x03
line.long 0x00 "BRSR,Baud Rate Selection Register"
hexmask.long.byte 0x00 28.--30. 1. " U ,SCI/BLIN super fractional divider selection"
hexmask.long.byte 0x00 24.--27. 1. " M ,SCI/BLIN 4-bit fractional divider selection"
hexmask.long.tbyte 0x00 0.--23. 1. " PRESCALER_P ,SCI/BLIN 24-bit integer prescaler selection"
else
group.long 0x2C++0x03
line.long 0x00 "BRSR,Baud Rate Selection Register"
hexmask.long.byte 0x00 28.--30. 1. " U ,SCI/BLIN super fractional divider selection"
hexmask.long.byte 0x00 24.--27. 1. " M ,SCI/BLIN 4-bit fractional divider selection"
endif
tree "SCI Data Buffer Registers"
if ((d.l(ad:0xFFF7E600+0x04)&0x040)==0x00)
rgroup.long 0x30++0x03
line.long 0x00 "ED,SCI Data Buffer"
hexmask.long.byte 0x00 0.--7. 1. " ED ,Emulation data"
hgroup.long 0x34++0x03
hide.long 0x00 "RD,SCI Data Buffer"
in
group.long 0x38++0x03
line.long 0x00 "TD,SCI Data Buffer"
hexmask.long.byte 0x00 0.--7. 1. " TD ,Transmit data"
else
hgroup.long 0x30++0x03
hide.long 0x00 "ED,SCI Data Buffer"
in
hgroup.long 0x34++0x03
hide.long 0x00 "RD,SCI Data Buffer"
in
hgroup.long 0x38++0x03
hide.long 0x00 "TD,SCI Data Buffer"
in
endif
tree.end
width 6.
tree "SCI Pin I/O Control Registers"
group.long 0x3C++0x03
line.long 0x00 "PIO0,Pin I/O Control Register 0"
bitfld.long 0x00 2. " TX_FUNC ,Defines the function of pin SCITX" "GPIO,SCITX"
bitfld.long 0x00 1. " RX_FUNC ,Defines the function of pin SCIRX" "GPIO,SCIRX"
group.long 0x40++0x03
line.long 0x00 "PIO1,Pin I/O Control Register 1"
bitfld.long 0x00 2. " TX_DIR ,Transmit direction" "Input,Output"
bitfld.long 0x00 1. " RX_DIR ,Receive direction" "Input,Output"
rgroup.long 0x44++0x03
line.long 0x00 "PIO2,Pin I/O Control Register 2"
bitfld.long 0x00 2. " TX_IN ,Contains current value on the SCITX pin" "Low,High"
bitfld.long 0x00 1. " RX_IN ,Contains current value on the SCIRX pin" "Low,High"
group.long 0x48++0x03
line.long 0x00 "PIO3,Pin I/O Control Register 3"
setclrfld.long 0x00 2. 0x04 2. 0x08 2. " TX_OUT_SET/CLR ,SCITX pin data output" "Low,High"
setclrfld.long 0x00 1. 0x04 1. 0x08 1. " RX_OUT_SET/CLR ,SCIRX pin data output" "Low,High"
group.long 0x54++0x03
line.long 0x00 "PIO6,Pin I/O Control Register 6"
bitfld.long 0x00 2. " TX_PDR ,TX open drain enable" "Disabled,Enabled"
bitfld.long 0x00 1. " RX_PDR ,RX open drain enable" "Disabled,Enabled"
group.long 0x58++0x03
line.long 0x00 "PIO7,Pin I/O Control Register 7"
bitfld.long 0x00 2. " TX_PD ,TX pin pull control disable" "Enabled,Disabled"
bitfld.long 0x00 1. " RX_PD ,RX pin pull control disable" "Enabled,Disabled"
group.long 0x5C++0x03
line.long 0x00 "PIO8,Pin I/O Control Register 8"
bitfld.long 0x00 2. " TX_PSL ,TX pin pull select" "Pull down,Pull up"
bitfld.long 0x00 1. " RX_PSL ,RX pin pull select" "Pull down,Pull up"
tree.end
width 9.
tree "BLIN Registers"
if ((d.l(ad:0xFFF7E600+0x04)&0x040)==0x040)
group.long 0x60++0x03
line.long 0x00 "LINCOMP,BLINCOMPARE Register"
bitfld.long 0x00 8.--9. " SDEL ,2-bit synch delimiter compare" "1 bit,2 bits,3 bits,4 bits"
bitfld.long 0x00 0.--2. " SBREAK ,3-bit synch break extend" "Not extended,1 bit,2 bits,3 bits,4 bits,5 bits,6 bits,7 bits"
else
hgroup.long 0x60++0x03
hide.long 0x00 "LINCOMP,BLINCOMPARE Register"
endif
rgroup.long 0x64++0x03
line.long 0x00 "LINRD0,LINRD0 Register"
hexmask.long.byte 0x00 24.--31. 0x01 " RD0 ,Receive buffer 0"
hexmask.long.byte 0x00 16.--23. 0x01 " RD1 ,Receive buffer 1"
hexmask.long.byte 0x00 8.--15. 0x01 " RD2 ,Receive buffer 2"
hexmask.long.byte 0x00 0.--7. 0x01 " RD3 ,Receive buffer 3"
rgroup.long 0x68++0x03
line.long 0x00 "LINRD1,LINRD1 Register"
hexmask.long.byte 0x00 24.--31. 0x01 " RD4 ,Receive buffer 4"
hexmask.long.byte 0x00 16.--23. 0x01 " RD5 ,Receive buffer 5"
hexmask.long.byte 0x00 8.--15. 0x01 " RD6 ,Receive buffer 6"
hexmask.long.byte 0x00 0.--7. 0x01 " RD7 ,Receive buffer 7"
if ((d.l(ad:0xFFF7E600+0x04)&0x040)==0x040)
group.long 0x6C++0x03
line.long 0x00 "LINMASK,LINMASK Register"
bitfld.long 0x00 23. " RX_ID_MASK7 ,RX ID mask 7" "Not masked,Masked"
bitfld.long 0x00 22. " RX_ID_MASK6 ,RX ID mask 6" "Not masked,Masked"
bitfld.long 0x00 21. " RX_ID_MASK5 ,RX ID mask 5" "Not masked,Masked"
bitfld.long 0x00 20. " RX_ID_MASK4 ,RX ID mask 4" "Not masked,Masked"
textline " "
bitfld.long 0x00 19. " RX_ID_MASK3 ,RX ID mask 3" "Not masked,Masked"
bitfld.long 0x00 18. " RX_ID_MASK2 ,RX ID mask 2" "Not masked,Masked"
bitfld.long 0x00 17. " RX_ID_MASK1 ,RX ID mask 1" "Not masked,Masked"
bitfld.long 0x00 16. " RX_ID_MASK0 ,RX ID mask 0" "Not masked,Masked"
textline " "
bitfld.long 0x00 7. " TX_ID_MASK7 ,TX ID mask 7" "Not masked,Masked"
bitfld.long 0x00 6. " TX_ID_MASK6 ,TX ID mask 6" "Not masked,Masked"
bitfld.long 0x00 5. " TX_ID_MASK5 ,TX ID mask 5" "Not masked,Masked"
bitfld.long 0x00 4. " TX_ID_MASK4 ,TX ID mask 4" "Not masked,Masked"
textline " "
bitfld.long 0x00 3. " TX_ID_MASK3 ,TX ID mask 3" "Not masked,Masked"
bitfld.long 0x00 2. " TX_ID_MASK2 ,TX ID mask 2" "Not masked,Masked"
bitfld.long 0x00 1. " TX_ID_MASK1 ,TX ID mask 1" "Not masked,Masked"
bitfld.long 0x00 0. " TX_ID_MASK0 ,TX ID mask 0" "Not masked,Masked"
else
hgroup.long 0x6C++0x03
hide.long 0x00 "LINMASK,LINMASK Register"
endif
if ((d.l(ad:0xFFF7E600+0x04)&0x040)==0x040)
group.long 0x70++0x03
line.long 0x00 "LINID,LINID Register"
hexmask.long.byte 0x00 16.--23. 1. " RECEIVED_ID ,Received identifier"
hexmask.long.byte 0x00 8.--15. 1. " ID_SLAVETASK_BYTE ,Identifier slave task byte"
hexmask.long.byte 0x00 0.--7. 1. " ID_BYTE ,Identifier byte"
else
hgroup.long 0x70++0x03
hide.long 0x00 "LINID,LINID Register"
endif
group.long 0x74++0x03
line.long 0x00 "LINTD0,LINTD0 Register"
hexmask.long.byte 0x00 24.--31. 1. " TD0 ,8-bit transmit buffer 0"
hexmask.long.byte 0x00 16.--23. 1. " TD1 ,8-bit transmit buffer 1"
hexmask.long.byte 0x00 8.--15. 1. " TD2 ,8-bit transmit buffer 2"
hexmask.long.byte 0x00 0.--7. 1. " TD3 ,8-bit transmit buffer 3"
group.long 0x78++0x03
line.long 0x00 "LINTD1,LINTD1 Register"
hexmask.long.byte 0x00 24.--31. 1. " TD4 ,8-bit transmit buffer 4"
hexmask.long.byte 0x00 16.--23. 1. " TD5 ,8-bit transmit buffer 5"
hexmask.long.byte 0x00 8.--15. 1. " TD6 ,8-bit transmit buffer 6"
hexmask.long.byte 0x00 0.--7. 1. " TD7 ,8-bit transmit buffer 7"
tree.end
width 11.
if ((d.l(ad:0xFFF7E600+0x04)&0x040)==0x040)
group.long 0x7C++0x03
line.long 0x00 "MBRSR,Maximum Baud Rate Selection Register"
hexmask.long.word 0x00 0.--12. 1. " MBR ,Maximum baud rate prescaler"
else
hgroup.long 0x7C++0x03
hide.long 0x00 "MBRSR,Maximum Baud Rate Selection Register"
endif
if (((d.l(ad:0xFFF7E600+0x04))&0x040)==0x040)&&(((d.l(ad:0xFFF7E600+0x90))&0xF00)==0xA00)
group.long 0x90++0x03
line.long 0x00 "IODFTCTRL,Input/output Error Enable Register"
bitfld.long 0x00 31. " BEN ,Bit error enable" "Disabled,Enabled"
bitfld.long 0x00 30. " PBEN ,Physical bus error enable" "Disabled,Enabled"
bitfld.long 0x00 29. " CEN ,Checksum error enable" "Disabled,Enabled"
bitfld.long 0x00 28. " ISFE ,Inconsistent synch field error enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 26. " FEN ,Frame error enable" "Disabled,Enabled"
bitfld.long 0x00 19.--20. " PIN_SAMPLE_MASK ,PIN SAMPLE MASK" "No mask,TBIT_CENTER,TBIT_CENTER + SCLK,TBIT_CENTER + 2 SCLK"
bitfld.long 0x00 16.--18. " TX_SHIFT ,Transmit shift" "No delay,1 SCLK,2 sclks,3 sclks,4 sclks,5 sclks,6 sclks,7 sclks"
bitfld.long 0x00 8.--11. " IODFTENA ,IO DFT enable key" "Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Enabled,Disabled,Disabled,Disabled,Disabled,Disabled"
textline " "
bitfld.long 0x00 1. " LPBENA ,Module loopback enable" "Digital,Analog"
bitfld.long 0x00 0. " RXPENA ,Module analog loopback through receive/transmit pin enable" "Transmit,Receive"
elif (((d.l(ad:0xFFF7E600+0x04))&0x040)==0x00)&&(((d.l(ad:0xFFF7E600+0x90))&0xF00)==0xA00)
group.long 0x90++0x03
line.long 0x00 "IODFTCTRL,Input/output Error Enable Register"
bitfld.long 0x00 26. " FEN ,Frame error enable" "Disabled,Enabled"
bitfld.long 0x00 19.--20. " PIN_SAMPLE_MASK ,PIN SAMPLE MASK" "No mask,TBIT_CENTER,TBIT_CENTER + SCLK,TBIT_CENTER + 2 SCLK"
bitfld.long 0x00 16.--18. " TX_SHIFT ,Transmit shift" "No delay,1 SCLK,2 sclks,3 sclks,4 sclks,5 sclks,6 sclks,7 sclks"
bitfld.long 0x00 8.--11. " IODFTENA ,IO DFT enable key" "Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Enabled,Disabled,Disabled,Disabled,Disabled,Disabled"
textline " "
bitfld.long 0x00 1. " LPBENA ,Module loopback enable" "Digital,Analog"
bitfld.long 0x00 0. " RXPENA ,Module analog loopback through receive/transmit pin enable" "Transmit,Receive"
elif (((d.l(ad:0xFFF7E600+0x04))&0x040)==0x00)&&(((d.l(ad:0xFFF7E600+0x90))&0xF00)!=0xA00)
group.long 0x90++0x03
line.long 0x00 "IODFTCTRL,Input/output Error Enable Register"
bitfld.long 0x00 26. " FEN ,Frame error enable" "Disabled,Enabled"
textline " "
sif cpu()=="RM57L843-ZWT"
bitfld.long 0x00 25. " PEN ,Parity error enable" "Disabled,Enabled"
textline " "
endif
bitfld.long 0x00 19.--20. " PIN_SAMPLE_MASK ,PIN SAMPLE MASK" "No mask,TBIT_CENTER,TBIT_CENTER + SCLK,TBIT_CENTER + 2 SCLK"
bitfld.long 0x00 16.--18. " TX_SHIFT ,Transmit shift" "No delay,1 SCLK,2 sclks,3 sclks,4 sclks,5 sclks,6 sclks,7 sclks"
bitfld.long 0x00 8.--11. " IODFTENA ,IO DFT enable key" "Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Enabled,Disabled,Disabled,Disabled,Disabled,Disabled"
textline " "
bitfld.long 0x00 1. " LPBENA ,Module loopback enable" "Digital,?..."
else
group.long 0x90++0x03
line.long 0x00 "IODFTCTRL,Input/output Error Enable Register"
bitfld.long 0x00 31. " BEN ,Bit error enable" "Disabled,Enabled"
bitfld.long 0x00 30. " PBEN ,Physical bus error enable" "Disabled,Enabled"
bitfld.long 0x00 29. " CEN ,Checksum error enable" "Disabled,Enabled"
bitfld.long 0x00 28. " ISFE ,Inconsistent synch field error enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 26. " FEN ,Frame error enable" "Disabled,Enabled"
bitfld.long 0x00 19.--20. " PIN_SAMPLE_MASK ,PIN SAMPLE MASK" "No mask,TBIT_CENTER,TBIT_CENTER + SCLK,TBIT_CENTER + 2 SCLK"
bitfld.long 0x00 16.--18. " TX_SHIFT ,Transmit shift" "No delay,1 SCLK,2 sclks,3 sclks,4 sclks,5 sclks,6 sclks,7 sclks"
bitfld.long 0x00 8.--11. " IODFTENA ,IO DFT enable key" "Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Enabled,Disabled,Disabled,Disabled,Disabled,Disabled"
textline " "
bitfld.long 0x00 1. " LPBENA ,Module loopback enable" "Digital,?..."
endif
width 0x0B
tree.end
tree.end
tree.open "SCI (Serial Communication Interface Module)"
tree "SCI3"
base ad:0xFFF7E500
width 8.
group.long 0x00++0x03
line.long 0x00 "GCR0,Global Control Register"
bitfld.long 0x00 0. " RESET ,SCI module reset" "Under reset,Out of reset"
if ((d.l(ad:0xFFF7E500+0x04)&0x04)==0x04)
group.long 0x04++0x03
line.long 0x00 "GCR1,Global Control Register"
bitfld.long 0x00 25. " TXENA ,SCI transmitter enable" "Disabled,Enabled"
bitfld.long 0x00 24. " RXENA ,SCI receiver enable" "Prevented,Allowed"
bitfld.long 0x00 17. " CONT ,Continue on suspend" "Frozen,Continue"
bitfld.long 0x00 16. " LOOP_BACK ,LOOP BACK enable" "Disabled,Enabled"
textline " "
sif cpu()=="RM57L843-ZWT"
bitfld.long 0x00 9. " POWERDOWN ,Power down" "Disabled,Enabled"
else
bitfld.long 0x00 9. " ADAPT ,LIN mode bit (Automatic baudrate adjustment)" "Disabled,Enabled"
endif
bitfld.long 0x00 8. " SLEEP ,SCI sleep enable" "Disabled,Enabled"
bitfld.long 0x00 7. " SW_NRESET ,Software reset" "Reset,Ready"
bitfld.long 0x00 5. " CLOCK ,SCI internal clock enable" "Slave,Master"
textline " "
bitfld.long 0x00 4. " STOP ,SCI number of stop bits" "1 bit,2 bits"
bitfld.long 0x00 3. " PARITY ,SCI parity odd/even selection" "Odd,Even"
bitfld.long 0x00 2. " PARITY_ENA ,ID-Parity enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 1. " TIMING_MODE ,SCI timing mode bit" "Synchronous,Asynchronous"
bitfld.long 0x00 0. " COMM_MODE ,SCI/BLIN communication mode bit ID4 and ID5 use" "Not used,Used"
else
group.long 0x04++0x03
line.long 0x00 "GCR1,Global Control Register"
bitfld.long 0x00 25. " TXENA ,SCI transmitter enable" "Disabled,Enabled"
bitfld.long 0x00 24. " RXENA ,SCI receiver enable" "Prevented,Allowed"
bitfld.long 0x00 17. " CONT ,Continue on suspend" "Frozen,Continue"
bitfld.long 0x00 16. " LOOP_BACK ,LOOP BACK enable" "Disabled,Enabled"
textline " "
sif cpu()=="RM57L843-ZWT"
bitfld.long 0x00 9. " POWERDOWN ,Power down" "Disabled,Enabled"
else
bitfld.long 0x00 9. " ADAPT ,LIN mode bit (Automatic baudrate adjustment)" "Disabled,Enabled"
endif
bitfld.long 0x00 8. " SLEEP ,SCI sleep enable" "Disabled,Enabled"
bitfld.long 0x00 7. " SW_NRESET ,Software reset" "Reset,Ready"
bitfld.long 0x00 5. " CLOCK ,SCI internal clock enable" "Slave,Master"
textline " "
bitfld.long 0x00 4. " STOP ,SCI number of stop bits" "1 bit,2 bits"
bitfld.long 0x00 2. " PARITY_ENA ,ID-Parity enable" "Disabled,Enabled"
bitfld.long 0x00 1. " TIMING_MODE ,SCI timing mode bit" "Synchronous,Asynchronous"
textline " "
bitfld.long 0x00 0. " COMM_MODE ,SCI/BLIN communication mode bit ID4 and ID5 use" "Not used,Used"
endif
width 11.
tree "SCI Interrupt Registers"
group.long 0x0C++0x03
line.long 0x00 "SETINT,Interrupt Register"
setclrfld.long 0x00 26. 0x00 26. 0x04 26. " FE_INT_SET/CLR ,Framing-Error interrupt" "Disabled,Enabled"
setclrfld.long 0x00 25. 0x00 25. 0x04 25. " OE_INT_SET/CLR ,Overrun-Error interrupt" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 24. 0x00 24. 0x04 24. " PE_INT_SET/CLR ,Parity interrupt" "Disabled,Enabled"
setclrfld.long 0x00 18. 0x00 18. 0x04 18. " RX_DMA_ALL_SET/CLR ,Receive DMA all" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 17. 0x00 17. 0x04 17. " RX_DMA_SET/CLR ,Receive DMA" "Disabled,Enabled"
setclrfld.long 0x00 16. 0x00 16. 0x04 16. " TX_DMA_SET/CLR ,Transmit DMA" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 9. 0x00 9. 0x04 9. " RX_INT_SET/CLR ,Receiver interrupt enable" "Disabled,Enabled"
setclrfld.long 0x00 8. 0x00 8. 0x04 8. " TX_INT_SET/CLR ,Transmitter interrupt" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 1. 0x00 1. 0x04 1. " WAKEUP_INT_SET/CLR ,Wake-up interrupt" "Disabled,Enabled"
setclrfld.long 0x00 0. 0x00 0. 0x04 0. " BRKDT_INT_SET/CLR ,Break-detect interrupt" "Disabled,Enabled"
group.long 0x14++0x03
line.long 0x00 "SETINTLVL,Interrupt Level Register"
setclrfld.long 0x00 26. 0x00 26. 0x04 26. " FE_INT_LVL_SET/CLR ,Framing-Error interrupt level" "INT0,INT1"
setclrfld.long 0x00 25. 0x00 25. 0x04 25. " OE_INT_LVL_SET/CLR ,Overrun-Error interrupt level" "INT0,INT1"
textline " "
setclrfld.long 0x00 24. 0x00 24. 0x04 24. " PE_INT_LVL_SET/CLR ,Parity error interrupt level" "INT0,INT1"
setclrfld.long 0x00 18. 0x00 18. 0x04 18. " RX_DMA_ALL_INT_LVL_SET/CLR ,Receive DMA all interrupt level" "INT0,INT1"
textline " "
setclrfld.long 0x00 9. 0x00 9. 0x04 9. " RX_INT_LVL_SET/CLR ,Receiver interrupt level" "INT0,INT1"
setclrfld.long 0x00 8. 0x00 8. 0x04 8. " TX_INT_LVL_SET/CLR ,Transmitter interrupt level" "INT0,INT1"
textline " "
setclrfld.long 0x00 1. 0x00 1. 0x04 1. " WAKEUP_INT_LVL_SET/CLR ,Wake-up interrupt level" "INT0,INT1"
setclrfld.long 0x00 0. 0x00 0. 0x04 0. " BRKDT_INT_SET/CLR ,Break-Detect interrupt level" "INT0,INT1"
tree.end
width 5.
textline " "
sif cpu()=="RM57L843-ZWT"
group.long 0x1C++0x03
line.long 0x00 "FLR,Flags Register"
eventfld.long 0x00 26. " FE ,Framing error flag" "Not detected,Detected"
eventfld.long 0x00 25. " OE ,Overrun error flag" "Not detected,Detected"
eventfld.long 0x00 24. " PE ,Parity error flag" "Not detected,Detected"
textline " "
bitfld.long 0x00 12. " RXWAKE ,Receiver wakeup detect flag" "Not address,Address"
bitfld.long 0x00 11. " TX_EMPTY ,Transmitter empty flag" "Not empty,Empty"
bitfld.long 0x00 10. " TXWAKE ,SCI transmitter wakeup method select" "Data,Address"
textline " "
eventfld.long 0x00 9. " RXRDY ,Receiver ready flag" "Not ready,Ready"
bitfld.long 0x00 8. " TXRDY ,Transmitter buffer register ready flag" "Full,Ready"
bitfld.long 0x00 3. " BUSY_FLAG ,BUSY flag" "Not busy,Busy"
textline " "
bitfld.long 0x00 2. " IDLE ,SCI receiver in idle state" "Not detected,Detected"
eventfld.long 0x00 1. " WAKEUP ,Wake-up flag" "No wake up,Wake up"
eventfld.long 0x00 0. " BRKDT ,SCI Break-Detect flag" "Not detected,Detected"
else
group.long 0x1C++0x03
line.long 0x00 "FLR,Flags Register"
eventfld.long 0x00 31. " BE ,Bit error flag" "Not detected,Detected"
eventfld.long 0x00 30. " PBE ,Physiscal bus error flag" "Not detected,Detected"
eventfld.long 0x00 29. " CE ,Checksum error flag" "Not detected,Detected"
eventfld.long 0x00 28. " ISFE ,Inconsistent synch field error flag" "Not detected,Detected"
textline " "
eventfld.long 0x00 27. " NRE ,No-Response error flag" "Not detected,Detected"
eventfld.long 0x00 26. " FE ,Framing error flag" "Not detected,Detected"
eventfld.long 0x00 25. " OE ,Overrun error flag" "Not detected,Detected"
eventfld.long 0x00 24. " PE ,Parity error flag" "Not detected,Detected"
textline " "
eventfld.long 0x00 14. " ID_RX_FLAG ,Identifier on receive flag" "Not received,Received"
eventfld.long 0x00 13. " ID_TX_FLAG ,Identifier on transmit flag" "Not received,Received"
bitfld.long 0x00 12. " RXWAKE ,Receiver wakeup detect flag" "Not address,Address"
bitfld.long 0x00 11. " TX_EMPTY ,Transmitter empty flag" "Not empty,Empty"
textline " "
bitfld.long 0x00 10. " TXWAKE ,SCI transmitter wakeup method select" "Data,Address"
eventfld.long 0x00 9. " RXRDY ,Receiver ready flag" "Not ready,Ready"
bitfld.long 0x00 8. " TXRDY ,Transmitter buffer register ready flag" "Full,Ready"
eventfld.long 0x00 7. " TOA3WUS ,Timeout after 3 wakeup signals flag" "No timeout,Timeout"
textline " "
eventfld.long 0x00 6. " TOAWUS ,Timeout after wakeup signal flag" "No timeout,Timeout"
eventfld.long 0x00 4. " TIMEOUT ,LIN bus IDLE timeout flag" "Not detected,Detected"
bitfld.long 0x00 3. " BUSY_FLAG ,BUSY flag" "Not busy,Busy"
bitfld.long 0x00 2. " IDLE ,SCI receiver in idle state" "Not detected,Detected"
textline " "
eventfld.long 0x00 1. " WAKEUP ,Wake-up flag" "No wake up,Wake up"
eventfld.long 0x00 0. " BRKDT ,SCI Break-Detect flag" "Not detected,Detected"
endif
width 9.
tree "SCI Interrupt Vector Offset Registers"
hgroup.long 0x20++0x03
hide.long 0x00 "INVECT0,Interrupt Vector Offset 0"
in
hgroup.long 0x24++0x03
hide.long 0x00 "INVECT1,Interrupt Vector Offset 1"
in
tree.end
width 8.
textline " "
group.long 0x28++0x03
line.long 0x00 "FORMAT,Format Control Register"
bitfld.long 0x00 0.--2. " CHAR ,Character length control bits" "1 bit,2 bits,3 bits,4 bits,5 bits,6 bits,7 bits,8 bits"
group.long 0x2C++0x03
line.long 0x00 "BRSR,Baud Rate Selection Register"
hexmask.long.tbyte 0x00 0.--23. 1. " BAUD ,SCI 24-bit baud selection"
width 4.
tree "SCI Data Buffer Registers"
rgroup.long 0x30++0x03
line.long 0x00 "ED,SCI Data Buffer"
hexmask.long.byte 0x00 0.--7. 1. " ED ,Emulation data"
hgroup.long 0x34++0x03
hide.long 0x00 "RD,SCI Data Buffer"
in
group.long 0x38++0x03
line.long 0x00 "TD,SCI Data Buffer"
hexmask.long.byte 0x00 0.--7. 1. " TD ,Transmit data"
tree.end
width 6.
tree "SCI Pin I/O Control Registers"
group.long 0x3C++0x03
line.long 0x00 "PIO0,Pin I/O Control Register 0"
bitfld.long 0x00 2. " TX_FUNC ,Defines the function of pin SCITX" "GPIO,SCITX"
bitfld.long 0x00 1. " RX_FUNC ,Defines the function of pin SCIRX" "GPIO,SCIRX"
group.long 0x40++0x03
line.long 0x00 "PIO1,Pin I/O Control Register 1"
bitfld.long 0x00 2. " TX_DIR ,Transmit direction" "Input,Output"
bitfld.long 0x00 1. " RX_DIR ,Receive direction" "Input,Output"
rgroup.long 0x44++0x03
line.long 0x00 "PIO2,Pin I/O Control Register 2"
bitfld.long 0x00 2. " TX_IN ,Contains current value on the SCITX pin" "Low,High"
bitfld.long 0x00 1. " RX_IN ,Contains current value on the SCIRX pin" "Low,High"
group.long 0x48++0x03
line.long 0x00 "PIO3,Pin I/O Control Register 3"
setclrfld.long 0x00 2. 0x04 2. 0x08 2. " TX_OUT_SET/CLR ,SCITX pin data output" "Low,High"
setclrfld.long 0x00 1. 0x04 1. 0x08 1. " RX_OUT_SET/CLR ,SCIRX pin data output" "Low,High"
group.long 0x54++0x03
line.long 0x00 "PIO6,Pin I/O Control Register 6"
bitfld.long 0x00 2. " TX_PDR ,TX pin open drain enable" "Disabled,Enabled"
bitfld.long 0x00 1. " RX_PDR ,RX pin open drain enable" "Disabled,Enabled"
group.long 0x58++0x03
line.long 0x00 "PIO7,Pin I/O Control Register 7"
bitfld.long 0x00 2. " TX_PD ,TX pin pull control disable" "No,Yes"
bitfld.long 0x00 1. " RX_PD ,RX pin pull control disable" "No,Yes"
group.long 0x5C++0x03
line.long 0x00 "PIO8,Pin I/O Control Register 8"
bitfld.long 0x00 2. " TX_PSL ,TX pin pull select" "Pull down,Pull up"
bitfld.long 0x00 1. " RX_PSL ,RX pin pull select" "Pull down,Pull up"
tree.end
width 11.
textline " "
if (((d.l(ad:0xFFF7E500+0x90))&0xF00)==0xA00)
group.long 0x90++0x03
line.long 0x00 "IODFTCTRL,Input/output Error Enable Register"
bitfld.long 0x00 26. " FEEN ,Frame error enable" "Disabled,Enabled"
bitfld.long 0x00 25. " PEEN ,Parity error enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 24. " BDEEN ,Break detect error enable" "Disabled,Enabled"
bitfld.long 0x00 19.--20. " PSM ,PIN SAMPLE MASK" "No mask,Invert at 7th SCLK,Invert at 8th SCLK,Invert at 9th SCLK"
textline " "
bitfld.long 0x00 16.--18. " TX_SHIFT ,Transmit shift" "No delay,1 SCLK,2 sclks,3 sclks,4 sclks,5 sclks,6 sclks,?..."
bitfld.long 0x00 8.--11. " IODFTENA ,IO DFT enable key" "Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Enabled,Disabled,Disabled,Disabled,Disabled,Disabled"
textline " "
bitfld.long 0x00 1. " LPBENA ,Module loopback enable" "Digital,Analog"
bitfld.long 0x00 0. " RXPENA ,Module analog loopback through receive/transmit pin enable" "Transmit,Receive"
else
group.long 0x90++0x03
line.long 0x00 "IODFTCTRL,Input/output Error Enable Register"
bitfld.long 0x00 26. " FEEN ,Frame error enable" "Disabled,Enabled"
bitfld.long 0x00 25. " PEEN ,Parity error enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 24. " BDEEN ,Break detect error enable" "Disabled,Enabled"
bitfld.long 0x00 19.--20. " PSM ,PIN SAMPLE MASK" "No mask,Invert at 7th SCLK,Invert at 8th SCLK,Invert at 9th SCLK"
textline " "
bitfld.long 0x00 16.--18. " TX_SHIFT ,Transmit shift" "No delay,1 SCLK,2 sclks,3 sclks,4 sclks,5 sclks,6 sclks,?..."
bitfld.long 0x00 8.--11. " IODFTENA ,IO DFT enable key" "Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Enabled,Disabled,Disabled,Disabled,Disabled,Disabled"
textline " "
bitfld.long 0x00 1. " LPBENA ,Module loopback enable" "Digital,?..."
endif
width 0x0B
tree.end
tree "SCI4"
base ad:0xFFF7E700
width 8.
group.long 0x00++0x03
line.long 0x00 "GCR0,Global Control Register"
bitfld.long 0x00 0. " RESET ,SCI module reset" "Under reset,Out of reset"
if ((d.l(ad:0xFFF7E700+0x04)&0x04)==0x04)
group.long 0x04++0x03
line.long 0x00 "GCR1,Global Control Register"
bitfld.long 0x00 25. " TXENA ,SCI transmitter enable" "Disabled,Enabled"
bitfld.long 0x00 24. " RXENA ,SCI receiver enable" "Prevented,Allowed"
bitfld.long 0x00 17. " CONT ,Continue on suspend" "Frozen,Continue"
bitfld.long 0x00 16. " LOOP_BACK ,LOOP BACK enable" "Disabled,Enabled"
textline " "
sif cpu()=="RM57L843-ZWT"
bitfld.long 0x00 9. " POWERDOWN ,Power down" "Disabled,Enabled"
else
bitfld.long 0x00 9. " ADAPT ,LIN mode bit (Automatic baudrate adjustment)" "Disabled,Enabled"
endif
bitfld.long 0x00 8. " SLEEP ,SCI sleep enable" "Disabled,Enabled"
bitfld.long 0x00 7. " SW_NRESET ,Software reset" "Reset,Ready"
bitfld.long 0x00 5. " CLOCK ,SCI internal clock enable" "Slave,Master"
textline " "
bitfld.long 0x00 4. " STOP ,SCI number of stop bits" "1 bit,2 bits"
bitfld.long 0x00 3. " PARITY ,SCI parity odd/even selection" "Odd,Even"
bitfld.long 0x00 2. " PARITY_ENA ,ID-Parity enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 1. " TIMING_MODE ,SCI timing mode bit" "Synchronous,Asynchronous"
bitfld.long 0x00 0. " COMM_MODE ,SCI/BLIN communication mode bit ID4 and ID5 use" "Not used,Used"
else
group.long 0x04++0x03
line.long 0x00 "GCR1,Global Control Register"
bitfld.long 0x00 25. " TXENA ,SCI transmitter enable" "Disabled,Enabled"
bitfld.long 0x00 24. " RXENA ,SCI receiver enable" "Prevented,Allowed"
bitfld.long 0x00 17. " CONT ,Continue on suspend" "Frozen,Continue"
bitfld.long 0x00 16. " LOOP_BACK ,LOOP BACK enable" "Disabled,Enabled"
textline " "
sif cpu()=="RM57L843-ZWT"
bitfld.long 0x00 9. " POWERDOWN ,Power down" "Disabled,Enabled"
else
bitfld.long 0x00 9. " ADAPT ,LIN mode bit (Automatic baudrate adjustment)" "Disabled,Enabled"
endif
bitfld.long 0x00 8. " SLEEP ,SCI sleep enable" "Disabled,Enabled"
bitfld.long 0x00 7. " SW_NRESET ,Software reset" "Reset,Ready"
bitfld.long 0x00 5. " CLOCK ,SCI internal clock enable" "Slave,Master"
textline " "
bitfld.long 0x00 4. " STOP ,SCI number of stop bits" "1 bit,2 bits"
bitfld.long 0x00 2. " PARITY_ENA ,ID-Parity enable" "Disabled,Enabled"
bitfld.long 0x00 1. " TIMING_MODE ,SCI timing mode bit" "Synchronous,Asynchronous"
textline " "
bitfld.long 0x00 0. " COMM_MODE ,SCI/BLIN communication mode bit ID4 and ID5 use" "Not used,Used"
endif
width 11.
tree "SCI Interrupt Registers"
group.long 0x0C++0x03
line.long 0x00 "SETINT,Interrupt Register"
setclrfld.long 0x00 26. 0x00 26. 0x04 26. " FE_INT_SET/CLR ,Framing-Error interrupt" "Disabled,Enabled"
setclrfld.long 0x00 25. 0x00 25. 0x04 25. " OE_INT_SET/CLR ,Overrun-Error interrupt" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 24. 0x00 24. 0x04 24. " PE_INT_SET/CLR ,Parity interrupt" "Disabled,Enabled"
setclrfld.long 0x00 18. 0x00 18. 0x04 18. " RX_DMA_ALL_SET/CLR ,Receive DMA all" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 17. 0x00 17. 0x04 17. " RX_DMA_SET/CLR ,Receive DMA" "Disabled,Enabled"
setclrfld.long 0x00 16. 0x00 16. 0x04 16. " TX_DMA_SET/CLR ,Transmit DMA" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 9. 0x00 9. 0x04 9. " RX_INT_SET/CLR ,Receiver interrupt enable" "Disabled,Enabled"
setclrfld.long 0x00 8. 0x00 8. 0x04 8. " TX_INT_SET/CLR ,Transmitter interrupt" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 1. 0x00 1. 0x04 1. " WAKEUP_INT_SET/CLR ,Wake-up interrupt" "Disabled,Enabled"
setclrfld.long 0x00 0. 0x00 0. 0x04 0. " BRKDT_INT_SET/CLR ,Break-detect interrupt" "Disabled,Enabled"
group.long 0x14++0x03
line.long 0x00 "SETINTLVL,Interrupt Level Register"
setclrfld.long 0x00 26. 0x00 26. 0x04 26. " FE_INT_LVL_SET/CLR ,Framing-Error interrupt level" "INT0,INT1"
setclrfld.long 0x00 25. 0x00 25. 0x04 25. " OE_INT_LVL_SET/CLR ,Overrun-Error interrupt level" "INT0,INT1"
textline " "
setclrfld.long 0x00 24. 0x00 24. 0x04 24. " PE_INT_LVL_SET/CLR ,Parity error interrupt level" "INT0,INT1"
setclrfld.long 0x00 18. 0x00 18. 0x04 18. " RX_DMA_ALL_INT_LVL_SET/CLR ,Receive DMA all interrupt level" "INT0,INT1"
textline " "
setclrfld.long 0x00 9. 0x00 9. 0x04 9. " RX_INT_LVL_SET/CLR ,Receiver interrupt level" "INT0,INT1"
setclrfld.long 0x00 8. 0x00 8. 0x04 8. " TX_INT_LVL_SET/CLR ,Transmitter interrupt level" "INT0,INT1"
textline " "
setclrfld.long 0x00 1. 0x00 1. 0x04 1. " WAKEUP_INT_LVL_SET/CLR ,Wake-up interrupt level" "INT0,INT1"
setclrfld.long 0x00 0. 0x00 0. 0x04 0. " BRKDT_INT_SET/CLR ,Break-Detect interrupt level" "INT0,INT1"
tree.end
width 5.
textline " "
sif cpu()=="RM57L843-ZWT"
group.long 0x1C++0x03
line.long 0x00 "FLR,Flags Register"
eventfld.long 0x00 26. " FE ,Framing error flag" "Not detected,Detected"
eventfld.long 0x00 25. " OE ,Overrun error flag" "Not detected,Detected"
eventfld.long 0x00 24. " PE ,Parity error flag" "Not detected,Detected"
textline " "
bitfld.long 0x00 12. " RXWAKE ,Receiver wakeup detect flag" "Not address,Address"
bitfld.long 0x00 11. " TX_EMPTY ,Transmitter empty flag" "Not empty,Empty"
bitfld.long 0x00 10. " TXWAKE ,SCI transmitter wakeup method select" "Data,Address"
textline " "
eventfld.long 0x00 9. " RXRDY ,Receiver ready flag" "Not ready,Ready"
bitfld.long 0x00 8. " TXRDY ,Transmitter buffer register ready flag" "Full,Ready"
bitfld.long 0x00 3. " BUSY_FLAG ,BUSY flag" "Not busy,Busy"
textline " "
bitfld.long 0x00 2. " IDLE ,SCI receiver in idle state" "Not detected,Detected"
eventfld.long 0x00 1. " WAKEUP ,Wake-up flag" "No wake up,Wake up"
eventfld.long 0x00 0. " BRKDT ,SCI Break-Detect flag" "Not detected,Detected"
else
group.long 0x1C++0x03
line.long 0x00 "FLR,Flags Register"
eventfld.long 0x00 31. " BE ,Bit error flag" "Not detected,Detected"
eventfld.long 0x00 30. " PBE ,Physiscal bus error flag" "Not detected,Detected"
eventfld.long 0x00 29. " CE ,Checksum error flag" "Not detected,Detected"
eventfld.long 0x00 28. " ISFE ,Inconsistent synch field error flag" "Not detected,Detected"
textline " "
eventfld.long 0x00 27. " NRE ,No-Response error flag" "Not detected,Detected"
eventfld.long 0x00 26. " FE ,Framing error flag" "Not detected,Detected"
eventfld.long 0x00 25. " OE ,Overrun error flag" "Not detected,Detected"
eventfld.long 0x00 24. " PE ,Parity error flag" "Not detected,Detected"
textline " "
eventfld.long 0x00 14. " ID_RX_FLAG ,Identifier on receive flag" "Not received,Received"
eventfld.long 0x00 13. " ID_TX_FLAG ,Identifier on transmit flag" "Not received,Received"
bitfld.long 0x00 12. " RXWAKE ,Receiver wakeup detect flag" "Not address,Address"
bitfld.long 0x00 11. " TX_EMPTY ,Transmitter empty flag" "Not empty,Empty"
textline " "
bitfld.long 0x00 10. " TXWAKE ,SCI transmitter wakeup method select" "Data,Address"
eventfld.long 0x00 9. " RXRDY ,Receiver ready flag" "Not ready,Ready"
bitfld.long 0x00 8. " TXRDY ,Transmitter buffer register ready flag" "Full,Ready"
eventfld.long 0x00 7. " TOA3WUS ,Timeout after 3 wakeup signals flag" "No timeout,Timeout"
textline " "
eventfld.long 0x00 6. " TOAWUS ,Timeout after wakeup signal flag" "No timeout,Timeout"
eventfld.long 0x00 4. " TIMEOUT ,LIN bus IDLE timeout flag" "Not detected,Detected"
bitfld.long 0x00 3. " BUSY_FLAG ,BUSY flag" "Not busy,Busy"
bitfld.long 0x00 2. " IDLE ,SCI receiver in idle state" "Not detected,Detected"
textline " "
eventfld.long 0x00 1. " WAKEUP ,Wake-up flag" "No wake up,Wake up"
eventfld.long 0x00 0. " BRKDT ,SCI Break-Detect flag" "Not detected,Detected"
endif
width 9.
tree "SCI Interrupt Vector Offset Registers"
hgroup.long 0x20++0x03
hide.long 0x00 "INVECT0,Interrupt Vector Offset 0"
in
hgroup.long 0x24++0x03
hide.long 0x00 "INVECT1,Interrupt Vector Offset 1"
in
tree.end
width 8.
textline " "
group.long 0x28++0x03
line.long 0x00 "FORMAT,Format Control Register"
bitfld.long 0x00 0.--2. " CHAR ,Character length control bits" "1 bit,2 bits,3 bits,4 bits,5 bits,6 bits,7 bits,8 bits"
group.long 0x2C++0x03
line.long 0x00 "BRSR,Baud Rate Selection Register"
hexmask.long.tbyte 0x00 0.--23. 1. " BAUD ,SCI 24-bit baud selection"
width 4.
tree "SCI Data Buffer Registers"
rgroup.long 0x30++0x03
line.long 0x00 "ED,SCI Data Buffer"
hexmask.long.byte 0x00 0.--7. 1. " ED ,Emulation data"
hgroup.long 0x34++0x03
hide.long 0x00 "RD,SCI Data Buffer"
in
group.long 0x38++0x03
line.long 0x00 "TD,SCI Data Buffer"
hexmask.long.byte 0x00 0.--7. 1. " TD ,Transmit data"
tree.end
width 6.
tree "SCI Pin I/O Control Registers"
group.long 0x3C++0x03
line.long 0x00 "PIO0,Pin I/O Control Register 0"
bitfld.long 0x00 2. " TX_FUNC ,Defines the function of pin SCITX" "GPIO,SCITX"
bitfld.long 0x00 1. " RX_FUNC ,Defines the function of pin SCIRX" "GPIO,SCIRX"
group.long 0x40++0x03
line.long 0x00 "PIO1,Pin I/O Control Register 1"
bitfld.long 0x00 2. " TX_DIR ,Transmit direction" "Input,Output"
bitfld.long 0x00 1. " RX_DIR ,Receive direction" "Input,Output"
rgroup.long 0x44++0x03
line.long 0x00 "PIO2,Pin I/O Control Register 2"
bitfld.long 0x00 2. " TX_IN ,Contains current value on the SCITX pin" "Low,High"
bitfld.long 0x00 1. " RX_IN ,Contains current value on the SCIRX pin" "Low,High"
group.long 0x48++0x03
line.long 0x00 "PIO3,Pin I/O Control Register 3"
setclrfld.long 0x00 2. 0x04 2. 0x08 2. " TX_OUT_SET/CLR ,SCITX pin data output" "Low,High"
setclrfld.long 0x00 1. 0x04 1. 0x08 1. " RX_OUT_SET/CLR ,SCIRX pin data output" "Low,High"
group.long 0x54++0x03
line.long 0x00 "PIO6,Pin I/O Control Register 6"
bitfld.long 0x00 2. " TX_PDR ,TX pin open drain enable" "Disabled,Enabled"
bitfld.long 0x00 1. " RX_PDR ,RX pin open drain enable" "Disabled,Enabled"
group.long 0x58++0x03
line.long 0x00 "PIO7,Pin I/O Control Register 7"
bitfld.long 0x00 2. " TX_PD ,TX pin pull control disable" "No,Yes"
bitfld.long 0x00 1. " RX_PD ,RX pin pull control disable" "No,Yes"
group.long 0x5C++0x03
line.long 0x00 "PIO8,Pin I/O Control Register 8"
bitfld.long 0x00 2. " TX_PSL ,TX pin pull select" "Pull down,Pull up"
bitfld.long 0x00 1. " RX_PSL ,RX pin pull select" "Pull down,Pull up"
tree.end
width 11.
textline " "
if (((d.l(ad:0xFFF7E700+0x90))&0xF00)==0xA00)
group.long 0x90++0x03
line.long 0x00 "IODFTCTRL,Input/output Error Enable Register"
bitfld.long 0x00 26. " FEEN ,Frame error enable" "Disabled,Enabled"
bitfld.long 0x00 25. " PEEN ,Parity error enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 24. " BDEEN ,Break detect error enable" "Disabled,Enabled"
bitfld.long 0x00 19.--20. " PSM ,PIN SAMPLE MASK" "No mask,Invert at 7th SCLK,Invert at 8th SCLK,Invert at 9th SCLK"
textline " "
bitfld.long 0x00 16.--18. " TX_SHIFT ,Transmit shift" "No delay,1 SCLK,2 sclks,3 sclks,4 sclks,5 sclks,6 sclks,?..."
bitfld.long 0x00 8.--11. " IODFTENA ,IO DFT enable key" "Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Enabled,Disabled,Disabled,Disabled,Disabled,Disabled"
textline " "
bitfld.long 0x00 1. " LPBENA ,Module loopback enable" "Digital,Analog"
bitfld.long 0x00 0. " RXPENA ,Module analog loopback through receive/transmit pin enable" "Transmit,Receive"
else
group.long 0x90++0x03
line.long 0x00 "IODFTCTRL,Input/output Error Enable Register"
bitfld.long 0x00 26. " FEEN ,Frame error enable" "Disabled,Enabled"
bitfld.long 0x00 25. " PEEN ,Parity error enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 24. " BDEEN ,Break detect error enable" "Disabled,Enabled"
bitfld.long 0x00 19.--20. " PSM ,PIN SAMPLE MASK" "No mask,Invert at 7th SCLK,Invert at 8th SCLK,Invert at 9th SCLK"
textline " "
bitfld.long 0x00 16.--18. " TX_SHIFT ,Transmit shift" "No delay,1 SCLK,2 sclks,3 sclks,4 sclks,5 sclks,6 sclks,?..."
bitfld.long 0x00 8.--11. " IODFTENA ,IO DFT enable key" "Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Enabled,Disabled,Disabled,Disabled,Disabled,Disabled"
textline " "
bitfld.long 0x00 1. " LPBENA ,Module loopback enable" "Digital,?..."
endif
width 0x0B
tree.end
tree.end
tree.open "I2C (Inter-Integrated Circuit Module)"
tree "I2C1"
base ad:0xFFF7D400
width 10.
if (((d.l(ad:0xFFF7D400+0x24))&0x100)==0x100)
group.long 0x00++0x03
line.long 0x00 "I2COAR,I2C Own Address Manager"
hexmask.long.word 0x00 0.--9. 1. " OA(9-0) ,Own address"
else
group.long 0x00++0x03
line.long 0x00 "I2COAR,I2C Own Address Manager"
hexmask.long.byte 0x00 0.--6. 1. " OA(6-0) ,Own address"
endif
group.long 0x04++0x03
line.long 0x00 "I2CIMR,I2C Interrupt Mask Register"
bitfld.long 0x00 6. " AASEN ,Address as slave interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 5. " SCDEN ,Stop condition interrupt enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 4. " TXRDYEN ,Transmit data ready interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 3. " RXRDYEN ,Receive data ready interrupt enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 2. " ARDYEN ,Register access ready interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 1. " NACKEN ,No acknowledgement interrupt enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 0. " ALEN ,Arbitration lost interrupt enable" "Disabled,Enabled"
group.long 0x08++0x03
line.long 0x00 "I2CSTR,I2C Status Register"
eventfld.long 0x00 14. " SDIR ,Slave transmitter direction enable" "Disabled,Enabled"
eventfld.long 0x00 13. " NACKSNT ,No acknowledge sent" "Not sent,Sent"
textline " "
rbitfld.long 0x00 12. " BB ,Bus busy" "Not busy,Busy"
rbitfld.long 0x00 11. " RSFULL ,Receiver shift full" "Not full,Full"
textline " "
bitfld.long 0x00 10. " XSMT ,Transmit shift empty not" "Empty,Not empty"
rbitfld.long 0x00 9. " AAS ,Address as slave" "Disabled,Enabled"
textline " "
rbitfld.long 0x00 8. " AD0 ,Address zero status" "Not detected,Detected"
eventfld.long 0x00 5. " SCD ,Stop condition detect interrupt flag" "No interrupt,Interrupt"
textline " "
eventfld.long 0x00 4. " TXRDY ,Transmit data ready interrupt flag" "No interrupt,Interrupt"
eventfld.long 0x00 3. " RXRDY ,Receive data ready interrupt flag" "No interrupt,Interrupt"
textline " "
eventfld.long 0x00 2. " ARDY ,Register access ready interrupt flag" "No interrupt,Interrupt"
eventfld.long 0x00 1. " NACK ,No acknowledgement interrupt" "No interrupt,Interrupt"
textline " "
eventfld.long 0x00 0. " AL ,Arbitration lost interrupt flag" "No interrupt,Interrupt"
if (((d.l(ad:0xFFF7D400+0x24))&0x20)==0x20)
group.long 0x0C++0x03
line.long 0x00 "I2CCKL,I2C Clock Divider Low Register"
group.long 0x10++0x03
line.long 0x00 "I2CCKH,I2C Clock Control High Register"
else
rgroup.long 0x0C++0x03
line.long 0x00 "I2CCKL,I2C Clock Divider Low Register"
rgroup.long 0x10++0x03
line.long 0x00 "I2CCKH,I2C Clock Control High Register"
endif
group.long 0x14++0x03
line.long 0x00 "I2CCNT,I2C Data Count Register"
hgroup.long 0x18++0x03
hide.long 0x00 "I2CDRR,I2C Data Receive Register"
in
if (((d.l(ad:0xFFF7D400+0x24))&0x100)==0x100)
group.long 0x1C++0x03
line.long 0x00 "I2CSAR,I2C Slave Address Register"
hexmask.long.word 0x00 0.--9. 1. " SA ,Receive data"
else
group.long 0x1C++0x03
line.long 0x00 "I2CSAR,I2C Slave Address Register"
hexmask.long.byte 0x00 0.--6. 1. " SA ,Receive data"
endif
group.long 0x20++0x03
line.long 0x00 "I2CDXR,I2C Data Transmit Register"
hexmask.long.byte 0x00 0.--7. 1. " DATATX ,Transmit data"
if (((d.l(ad:0xFFF7D400+0x24))&0x608)==0x00)
group.long 0x24++0x03
line.long 0x00 "I2CMDR,I2C Mode Register"
bitfld.long 0x00 15. " NACKMOD ,No-acknowledge (Nack) mode" "Disabled,Enabled"
bitfld.long 0x00 14. " FREE ,Free running bit" "Disabled,Enabled"
textline " "
bitfld.long 0x00 10. " MST ,Master/slave mode bit" "Slave,Master"
bitfld.long 0x00 9. " TRX ,Transmit/receive bit" "Receive,Transmit"
textline " "
bitfld.long 0x00 8. " XA ,Expand address enable bit" "7-bit addressing,10-bit addressing"
textline " "
bitfld.long 0x00 5. " NIRS ,I2C reset enable bit" "Disabled,Enabled"
textline " "
bitfld.long 0x00 3. " FDF ,Free data format enable bit (Not supported in digital loop back mode [this.dlb = 1])" "Disabled,Enabled"
textline " "
bitfld.long 0x00 0.--2. " BC[2-0] ,Bit count" "9,,3,4,5,6,7,8"
elif (((d.l(ad:0xFFF7D400+0x24))&0x608)==0x08)
group.long 0x24++0x03
line.long 0x00 "I2CMDR,I2C Mode Register"
bitfld.long 0x00 15. " NACKMOD ,No-acknowledge (Nack) mode" "Disabled,Enabled"
bitfld.long 0x00 14. " FREE ,Free running bit" "Disabled,Enabled"
textline " "
bitfld.long 0x00 10. " MST ,Master/slave mode bit" "Slave,Master"
bitfld.long 0x00 9. " TRX ,Transmit/receive bit" "Receive,Transmit"
textline " "
bitfld.long 0x00 8. " XA ,Expand address enable bit" "7-bit addressing,10-bit addressing"
textline " "
bitfld.long 0x00 5. " NIRS ,I2C reset enable bit" "Disabled,Enabled"
textline " "
bitfld.long 0x00 3. " FDF ,Free data format enable bit (Not supported in digital loop back mode [this.dlb = 1])" "Disabled,Enabled"
textline " "
bitfld.long 0x00 0.--2. " BC[2-0] ,Bit count" "8,,2,3,4,5,6,7"
elif (((d.l(ad:0xFFF7D400+0x24))&0x608)==0x408)
group.long 0x24++0x03
line.long 0x00 "I2CMDR,I2C Mode Register"
bitfld.long 0x00 15. " NACKMOD ,No-acknowledge (Nack) mode" "Disabled,Enabled"
bitfld.long 0x00 14. " FREE ,Free running bit" "Disabled,Enabled"
textline " "
bitfld.long 0x00 13. " STT ,Start condition" "Disabled,Enabled"
bitfld.long 0x00 11. " STP ,Stop condition" "Disabled,Enabled"
textline " "
bitfld.long 0x00 10. " MST ,Master/slave mode bit" "Slave,Master"
bitfld.long 0x00 9. " TRX ,Transmit/receive bit" "Receive,Transmit"
textline " "
bitfld.long 0x00 8. " XA ,Expand address enable bit" "7-bit addressing,10-bit addressing"
bitfld.long 0x00 7. " RM ,Repeat mode enable bit" "Disabled,Enabled"
textline " "
bitfld.long 0x00 5. " NIRS ,I2C reset enable bit" "Disabled,Enabled"
textline " "
bitfld.long 0x00 4. " STB ,Start byte mode enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 3. " FDF ,Free data format enable bit (Not supported in digital loop back mode [this.dlb = 1])" "Disabled,Enabled"
textline " "
bitfld.long 0x00 0.--2. " BC[2-0] ,Bit count" "8,,2,3,4,5,6,7"
elif (((d.l(ad:0xFFF7D400+0x24))&0x608)==0x400)
group.long 0x24++0x03
line.long 0x00 "I2CMDR,I2C Mode Register"
bitfld.long 0x00 15. " NACKMOD ,No-acknowledge (Nack) mode" "Disabled,Enabled"
bitfld.long 0x00 14. " FREE ,Free running bit" "Disabled,Enabled"
textline " "
bitfld.long 0x00 13. " STT ,Start condition" "Disabled,Enabled"
bitfld.long 0x00 11. " STP ,Stop condition" "Disabled,Enabled"
textline " "
bitfld.long 0x00 10. " MST ,Master/slave mode bit" "Slave,Master"
bitfld.long 0x00 9. " TRX ,Transmit/receive bit" "Receive,Transmit"
textline " "
bitfld.long 0x00 8. " XA ,Expand address enable bit" "7-bit addressing,10-bit addressing"
bitfld.long 0x00 7. " RM ,Repeat mode enable bit" "Disabled,Enabled"
textline " "
bitfld.long 0x00 5. " NIRS ,I2C reset enable bit" "Disabled,Enabled"
textline " "
bitfld.long 0x00 4. " STB ,Start byte mode enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 3. " FDF ,Free data format enable bit (Not supported in digital loop back mode [this.dlb = 1])" "Disabled,Enabled"
textline " "
bitfld.long 0x00 0.--2. " BC[2-0] ,Bit count" "9,,3,4,5,6,7,8"
elif (((d.l(ad:0xFFF7D400+0x24))&0x608)==0x600)
group.long 0x24++0x03
line.long 0x00 "I2CMDR,I2C Mode Register"
bitfld.long 0x00 14. " FREE ,Free running bit" "Disabled,Enabled"
textline " "
bitfld.long 0x00 13. " STT ,Start condition" "Disabled,Enabled"
bitfld.long 0x00 11. " STP ,Stop condition" "Disabled,Enabled"
textline " "
bitfld.long 0x00 10. " MST ,Master/slave mode bit" "Slave,Master"
bitfld.long 0x00 9. " TRX ,Transmit/receive bit" "Receive,Transmit"
textline " "
bitfld.long 0x00 8. " XA ,Expand address enable bit" "7-bit addressing,10-bit addressing"
bitfld.long 0x00 7. " RM ,Repeat mode enable bit" "Disabled,Enabled"
textline " "
bitfld.long 0x00 6. " DLB ,Digital loop back enable bit" "Disabled,Enabled"
bitfld.long 0x00 5. " NIRS ,I2C reset enable bit" "Disabled,Enabled"
textline " "
bitfld.long 0x00 4. " STB ,Start byte mode enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 3. " FDF ,Free data format enable bit (Not supported in digital loop back mode [this.dlb = 1])" "Disabled,Enabled"
textline " "
bitfld.long 0x00 0.--2. " BC[2-0] ,Bit count" "9,,3,4,5,6,7,8"
elif (((d.l(ad:0xFFF7D400+0x24))&0x608)==0x608)
group.long 0x24++0x03
line.long 0x00 "I2CMDR,I2C Mode Register"
bitfld.long 0x00 14. " FREE ,Free running bit" "Disabled,Enabled"
textline " "
bitfld.long 0x00 13. " STT ,Start condition" "Disabled,Enabled"
bitfld.long 0x00 11. " STP ,Stop condition" "Disabled,Enabled"
textline " "
bitfld.long 0x00 10. " MST ,Master/slave mode bit" "Slave,Master"
bitfld.long 0x00 9. " TRX ,Transmit/receive bit" "Receive,Transmit"
textline " "
bitfld.long 0x00 8. " XA ,Expand address enable bit" "7-bit addressing,10-bit addressing"
bitfld.long 0x00 7. " RM ,Repeat mode enable bit" "Disabled,Enabled"
textline " "
bitfld.long 0x00 6. " DLB ,Digital loop back enable bit" "Disabled,Enabled"
bitfld.long 0x00 5. " NIRS ,I2C reset enable bit" "Disabled,Enabled"
textline " "
bitfld.long 0x00 4. " STB ,Start byte mode enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 3. " FDF ,Free data format enable bit (Not supported in digital loop back mode [this.dlb = 1])" "Disabled,Enabled"
textline " "
bitfld.long 0x00 0.--2. " BC[2-0] ,Bit count" "8,,2,3,4,5,6,7"
elif (((d.l(ad:0xFFF7D400+0x24))&0x608)==0x208)
group.long 0x24++0x03
line.long 0x00 "I2CMDR,I2C Mode Register"
bitfld.long 0x00 14. " FREE ,Free running bit" "Disabled,Enabled"
textline " "
bitfld.long 0x00 10. " MST ,Master/slave mode bit" "Slave,Master"
bitfld.long 0x00 9. " TRX ,Transmit/receive bit" "Receive,Transmit"
textline " "
bitfld.long 0x00 8. " XA ,Expand address enable bit" "7-bit addressing,10-bit addressing"
textline " "
bitfld.long 0x00 5. " NIRS ,I2C reset enable bit" "Disabled,Enabled"
textline " "
bitfld.long 0x00 3. " FDF ,Free data format enable bit (Not supported in digital loop back mode [this.dlb = 1])" "Disabled,Enabled"
textline " "
bitfld.long 0x00 0.--2. " BC[2-0] ,Bit count" "8,,2,3,4,5,6,7"
else
group.long 0x24++0x03
line.long 0x00 "I2CMDR,I2C Mode Register"
bitfld.long 0x00 14. " FREE ,Free running bit" "Disabled,Enabled"
textline " "
bitfld.long 0x00 10. " MST ,Master/slave mode bit" "Slave,Master"
bitfld.long 0x00 9. " TRX ,Transmit/receive bit" "Receive,Transmit"
textline " "
bitfld.long 0x00 8. " XA ,Expand address enable bit" "7-bit addressing,10-bit addressing"
textline " "
bitfld.long 0x00 5. " NIRS ,I2C reset enable bit" "Disabled,Enabled"
textline " "
bitfld.long 0x00 3. " FDF ,Free data format enable bit (Not supported in digital loop back mode [this.dlb = 1])" "Disabled,Enabled"
textline " "
bitfld.long 0x00 0.--2. " BC[2-0] ,Bit count" "9,,3,4,5,6,7,8"
endif
hgroup.long 0x28++0x03
hide.long 0x00 "I2CIVR,I2C Interrupt Vector Register"
in
group.long 0x2C++0x03
line.long 0x00 "I2CEMDR,I2C Extended Mode Register"
bitfld.long 0x00 1. " IGNACK ,Ignore NACK mode" "Disabled,Enabled"
bitfld.long 0x00 0. " BCM ,Backwards compatibility mode" "Disabled,Enabled"
group.long 0x30++0x03
line.long 0x00 "I2CPSC,I2C Prescale Register"
hexmask.long.byte 0x00 0.--7. 1. " PSC ,Prescale"
rgroup.long 0x34++0x03
line.long 0x00 "I2CPID1,I2C Peripheral ID Register 1"
hexmask.long.byte 0x00 8.--15. 1. " CLASS ,Peripheral class"
hexmask.long.byte 0x00 0.--7. 1. " REVISION ,Revision level of the I2C"
group.long 0x38++0x03
line.long 0x00 "I2CPID2,I2C Peripheral ID Register 2"
hexmask.long.byte 0x00 0.--7. 1. " TYPE ,Peripheral type"
group.long 0x3C++0x03
line.long 0x00 "I2CDMACR,I2C DMA Control Register"
bitfld.long 0x00 1. " TXDMAEN ,Transmitter DMA enable" "Disabled,Enabled"
bitfld.long 0x00 0. " RXDMAEN ,Receive DMA enable" "Disabled,Enabled"
group.long 0x48++0x03
line.long 0x00 "I2CPFNC,I2C Pin Function Register"
bitfld.long 0x00 0. " PINFUNC ,SDA and SCL pin function" "I2C,I/O"
group.long 0x4C++0x03
line.long 0x00 "I2CPDIR,I2C Pin Direction Register"
bitfld.long 0x00 1. " SDADIR ,SDA direction" "Input,Output"
bitfld.long 0x00 0. " SCLDIR ,SCL direction" "Input,Output"
rgroup.long 0x50++0x03
line.long 0x00 "I2CDIN,I2C Data Input Register"
bitfld.long 0x00 1. " SDAIN ,Serial data in" "Low,High"
bitfld.long 0x00 0. " SCLSIN ,Serial clock data in" "Low,High"
group.long 0x54++0x03
line.long 0x00 "I2CDOUT,I2C Data Output Register"
bitfld.long 0x00 1. " SDAOUT ,SDA data output" "Low,High"
bitfld.long 0x00 0. " SCLOUT ,SCL data output" "Low,High"
group.long 0x58++0x03
line.long 0x00 "I2CDSET,I2C Data Set Register"
bitfld.long 0x00 1. " SDASET ,Serial data set" "Low,High"
bitfld.long 0x00 0. " SCLSET ,Serial clock set" "Low,High"
group.long 0x5C++0x03
line.long 0x00 "I2CDCLR,I2C Data Clear Register"
bitfld.long 0x00 1. " SDACLR ,Serial data clear" "No effect,Low"
bitfld.long 0x00 0. " SCLCLR ,Serial clock clear" "No effect,Low"
group.long 0x60++0x03
line.long 0x00 "I2CPDR,I2C Pin Open Drain Register"
bitfld.long 0x00 1. " SDAPDR ,SDA pin open drain disable" "No,Yes"
bitfld.long 0x00 0. " SCLPDR ,SCL pin open drain disable" "No,Yes"
group.long 0x64++0x03
line.long 0x00 "I2CPDIS,I2C Pull Disable Register"
bitfld.long 0x00 1. " SDAPDIS ,SDA pull disable" "No,Yes"
bitfld.long 0x00 0. " SCLPDIS ,SCL pull disable" "No,Yes"
group.long 0x68++0x03
line.long 0x00 "I2CPSEL,I2C Pull Select Register"
bitfld.long 0x00 1. " SDAPSEL ,SDA pull select" "Pull down,Pull up"
bitfld.long 0x00 0. " SCLPSEL ,SCL pull select" "Pull down,Pull up"
group.long 0x6C++0x03
line.long 0x00 "I2CSRS,I2C Pins Slew Rate Select Register"
bitfld.long 0x00 1. " SDASRS ,SDA slew rate select" "Slow,Normal"
bitfld.long 0x00 0. " SCLSRS ,SCL slew rate select" "Slow,Normal"
width 0x0B
tree.end
tree "I2C2"
base ad:0xFFF7D500
width 10.
if (((d.l(ad:0xFFF7D500+0x24))&0x100)==0x100)
group.long 0x00++0x03
line.long 0x00 "I2COAR,I2C Own Address Manager"
hexmask.long.word 0x00 0.--9. 1. " OA(9-0) ,Own address"
else
group.long 0x00++0x03
line.long 0x00 "I2COAR,I2C Own Address Manager"
hexmask.long.byte 0x00 0.--6. 1. " OA(6-0) ,Own address"
endif
group.long 0x04++0x03
line.long 0x00 "I2CIMR,I2C Interrupt Mask Register"
bitfld.long 0x00 6. " AASEN ,Address as slave interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 5. " SCDEN ,Stop condition interrupt enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 4. " TXRDYEN ,Transmit data ready interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 3. " RXRDYEN ,Receive data ready interrupt enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 2. " ARDYEN ,Register access ready interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 1. " NACKEN ,No acknowledgement interrupt enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 0. " ALEN ,Arbitration lost interrupt enable" "Disabled,Enabled"
group.long 0x08++0x03
line.long 0x00 "I2CSTR,I2C Status Register"
eventfld.long 0x00 14. " SDIR ,Slave transmitter direction enable" "Disabled,Enabled"
eventfld.long 0x00 13. " NACKSNT ,No acknowledge sent" "Not sent,Sent"
textline " "
rbitfld.long 0x00 12. " BB ,Bus busy" "Not busy,Busy"
rbitfld.long 0x00 11. " RSFULL ,Receiver shift full" "Not full,Full"
textline " "
bitfld.long 0x00 10. " XSMT ,Transmit shift empty not" "Empty,Not empty"
rbitfld.long 0x00 9. " AAS ,Address as slave" "Disabled,Enabled"
textline " "
rbitfld.long 0x00 8. " AD0 ,Address zero status" "Not detected,Detected"
eventfld.long 0x00 5. " SCD ,Stop condition detect interrupt flag" "No interrupt,Interrupt"
textline " "
eventfld.long 0x00 4. " TXRDY ,Transmit data ready interrupt flag" "No interrupt,Interrupt"
eventfld.long 0x00 3. " RXRDY ,Receive data ready interrupt flag" "No interrupt,Interrupt"
textline " "
eventfld.long 0x00 2. " ARDY ,Register access ready interrupt flag" "No interrupt,Interrupt"
eventfld.long 0x00 1. " NACK ,No acknowledgement interrupt" "No interrupt,Interrupt"
textline " "
eventfld.long 0x00 0. " AL ,Arbitration lost interrupt flag" "No interrupt,Interrupt"
if (((d.l(ad:0xFFF7D500+0x24))&0x20)==0x20)
group.long 0x0C++0x03
line.long 0x00 "I2CCKL,I2C Clock Divider Low Register"
group.long 0x10++0x03
line.long 0x00 "I2CCKH,I2C Clock Control High Register"
else
rgroup.long 0x0C++0x03
line.long 0x00 "I2CCKL,I2C Clock Divider Low Register"
rgroup.long 0x10++0x03
line.long 0x00 "I2CCKH,I2C Clock Control High Register"
endif
group.long 0x14++0x03
line.long 0x00 "I2CCNT,I2C Data Count Register"
hgroup.long 0x18++0x03
hide.long 0x00 "I2CDRR,I2C Data Receive Register"
in
if (((d.l(ad:0xFFF7D500+0x24))&0x100)==0x100)
group.long 0x1C++0x03
line.long 0x00 "I2CSAR,I2C Slave Address Register"
hexmask.long.word 0x00 0.--9. 1. " SA ,Receive data"
else
group.long 0x1C++0x03
line.long 0x00 "I2CSAR,I2C Slave Address Register"
hexmask.long.byte 0x00 0.--6. 1. " SA ,Receive data"
endif
group.long 0x20++0x03
line.long 0x00 "I2CDXR,I2C Data Transmit Register"
hexmask.long.byte 0x00 0.--7. 1. " DATATX ,Transmit data"
if (((d.l(ad:0xFFF7D500+0x24))&0x608)==0x00)
group.long 0x24++0x03
line.long 0x00 "I2CMDR,I2C Mode Register"
bitfld.long 0x00 15. " NACKMOD ,No-acknowledge (Nack) mode" "Disabled,Enabled"
bitfld.long 0x00 14. " FREE ,Free running bit" "Disabled,Enabled"
textline " "
bitfld.long 0x00 10. " MST ,Master/slave mode bit" "Slave,Master"
bitfld.long 0x00 9. " TRX ,Transmit/receive bit" "Receive,Transmit"
textline " "
bitfld.long 0x00 8. " XA ,Expand address enable bit" "7-bit addressing,10-bit addressing"
textline " "
bitfld.long 0x00 5. " NIRS ,I2C reset enable bit" "Disabled,Enabled"
textline " "
bitfld.long 0x00 3. " FDF ,Free data format enable bit (Not supported in digital loop back mode [this.dlb = 1])" "Disabled,Enabled"
textline " "
bitfld.long 0x00 0.--2. " BC[2-0] ,Bit count" "9,,3,4,5,6,7,8"
elif (((d.l(ad:0xFFF7D500+0x24))&0x608)==0x08)
group.long 0x24++0x03
line.long 0x00 "I2CMDR,I2C Mode Register"
bitfld.long 0x00 15. " NACKMOD ,No-acknowledge (Nack) mode" "Disabled,Enabled"
bitfld.long 0x00 14. " FREE ,Free running bit" "Disabled,Enabled"
textline " "
bitfld.long 0x00 10. " MST ,Master/slave mode bit" "Slave,Master"
bitfld.long 0x00 9. " TRX ,Transmit/receive bit" "Receive,Transmit"
textline " "
bitfld.long 0x00 8. " XA ,Expand address enable bit" "7-bit addressing,10-bit addressing"
textline " "
bitfld.long 0x00 5. " NIRS ,I2C reset enable bit" "Disabled,Enabled"
textline " "
bitfld.long 0x00 3. " FDF ,Free data format enable bit (Not supported in digital loop back mode [this.dlb = 1])" "Disabled,Enabled"
textline " "
bitfld.long 0x00 0.--2. " BC[2-0] ,Bit count" "8,,2,3,4,5,6,7"
elif (((d.l(ad:0xFFF7D500+0x24))&0x608)==0x408)
group.long 0x24++0x03
line.long 0x00 "I2CMDR,I2C Mode Register"
bitfld.long 0x00 15. " NACKMOD ,No-acknowledge (Nack) mode" "Disabled,Enabled"
bitfld.long 0x00 14. " FREE ,Free running bit" "Disabled,Enabled"
textline " "
bitfld.long 0x00 13. " STT ,Start condition" "Disabled,Enabled"
bitfld.long 0x00 11. " STP ,Stop condition" "Disabled,Enabled"
textline " "
bitfld.long 0x00 10. " MST ,Master/slave mode bit" "Slave,Master"
bitfld.long 0x00 9. " TRX ,Transmit/receive bit" "Receive,Transmit"
textline " "
bitfld.long 0x00 8. " XA ,Expand address enable bit" "7-bit addressing,10-bit addressing"
bitfld.long 0x00 7. " RM ,Repeat mode enable bit" "Disabled,Enabled"
textline " "
bitfld.long 0x00 5. " NIRS ,I2C reset enable bit" "Disabled,Enabled"
textline " "
bitfld.long 0x00 4. " STB ,Start byte mode enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 3. " FDF ,Free data format enable bit (Not supported in digital loop back mode [this.dlb = 1])" "Disabled,Enabled"
textline " "
bitfld.long 0x00 0.--2. " BC[2-0] ,Bit count" "8,,2,3,4,5,6,7"
elif (((d.l(ad:0xFFF7D500+0x24))&0x608)==0x400)
group.long 0x24++0x03
line.long 0x00 "I2CMDR,I2C Mode Register"
bitfld.long 0x00 15. " NACKMOD ,No-acknowledge (Nack) mode" "Disabled,Enabled"
bitfld.long 0x00 14. " FREE ,Free running bit" "Disabled,Enabled"
textline " "
bitfld.long 0x00 13. " STT ,Start condition" "Disabled,Enabled"
bitfld.long 0x00 11. " STP ,Stop condition" "Disabled,Enabled"
textline " "
bitfld.long 0x00 10. " MST ,Master/slave mode bit" "Slave,Master"
bitfld.long 0x00 9. " TRX ,Transmit/receive bit" "Receive,Transmit"
textline " "
bitfld.long 0x00 8. " XA ,Expand address enable bit" "7-bit addressing,10-bit addressing"
bitfld.long 0x00 7. " RM ,Repeat mode enable bit" "Disabled,Enabled"
textline " "
bitfld.long 0x00 5. " NIRS ,I2C reset enable bit" "Disabled,Enabled"
textline " "
bitfld.long 0x00 4. " STB ,Start byte mode enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 3. " FDF ,Free data format enable bit (Not supported in digital loop back mode [this.dlb = 1])" "Disabled,Enabled"
textline " "
bitfld.long 0x00 0.--2. " BC[2-0] ,Bit count" "9,,3,4,5,6,7,8"
elif (((d.l(ad:0xFFF7D500+0x24))&0x608)==0x600)
group.long 0x24++0x03
line.long 0x00 "I2CMDR,I2C Mode Register"
bitfld.long 0x00 14. " FREE ,Free running bit" "Disabled,Enabled"
textline " "
bitfld.long 0x00 13. " STT ,Start condition" "Disabled,Enabled"
bitfld.long 0x00 11. " STP ,Stop condition" "Disabled,Enabled"
textline " "
bitfld.long 0x00 10. " MST ,Master/slave mode bit" "Slave,Master"
bitfld.long 0x00 9. " TRX ,Transmit/receive bit" "Receive,Transmit"
textline " "
bitfld.long 0x00 8. " XA ,Expand address enable bit" "7-bit addressing,10-bit addressing"
bitfld.long 0x00 7. " RM ,Repeat mode enable bit" "Disabled,Enabled"
textline " "
bitfld.long 0x00 6. " DLB ,Digital loop back enable bit" "Disabled,Enabled"
bitfld.long 0x00 5. " NIRS ,I2C reset enable bit" "Disabled,Enabled"
textline " "
bitfld.long 0x00 4. " STB ,Start byte mode enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 3. " FDF ,Free data format enable bit (Not supported in digital loop back mode [this.dlb = 1])" "Disabled,Enabled"
textline " "
bitfld.long 0x00 0.--2. " BC[2-0] ,Bit count" "9,,3,4,5,6,7,8"
elif (((d.l(ad:0xFFF7D500+0x24))&0x608)==0x608)
group.long 0x24++0x03
line.long 0x00 "I2CMDR,I2C Mode Register"
bitfld.long 0x00 14. " FREE ,Free running bit" "Disabled,Enabled"
textline " "
bitfld.long 0x00 13. " STT ,Start condition" "Disabled,Enabled"
bitfld.long 0x00 11. " STP ,Stop condition" "Disabled,Enabled"
textline " "
bitfld.long 0x00 10. " MST ,Master/slave mode bit" "Slave,Master"
bitfld.long 0x00 9. " TRX ,Transmit/receive bit" "Receive,Transmit"
textline " "
bitfld.long 0x00 8. " XA ,Expand address enable bit" "7-bit addressing,10-bit addressing"
bitfld.long 0x00 7. " RM ,Repeat mode enable bit" "Disabled,Enabled"
textline " "
bitfld.long 0x00 6. " DLB ,Digital loop back enable bit" "Disabled,Enabled"
bitfld.long 0x00 5. " NIRS ,I2C reset enable bit" "Disabled,Enabled"
textline " "
bitfld.long 0x00 4. " STB ,Start byte mode enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 3. " FDF ,Free data format enable bit (Not supported in digital loop back mode [this.dlb = 1])" "Disabled,Enabled"
textline " "
bitfld.long 0x00 0.--2. " BC[2-0] ,Bit count" "8,,2,3,4,5,6,7"
elif (((d.l(ad:0xFFF7D500+0x24))&0x608)==0x208)
group.long 0x24++0x03
line.long 0x00 "I2CMDR,I2C Mode Register"
bitfld.long 0x00 14. " FREE ,Free running bit" "Disabled,Enabled"
textline " "
bitfld.long 0x00 10. " MST ,Master/slave mode bit" "Slave,Master"
bitfld.long 0x00 9. " TRX ,Transmit/receive bit" "Receive,Transmit"
textline " "
bitfld.long 0x00 8. " XA ,Expand address enable bit" "7-bit addressing,10-bit addressing"
textline " "
bitfld.long 0x00 5. " NIRS ,I2C reset enable bit" "Disabled,Enabled"
textline " "
bitfld.long 0x00 3. " FDF ,Free data format enable bit (Not supported in digital loop back mode [this.dlb = 1])" "Disabled,Enabled"
textline " "
bitfld.long 0x00 0.--2. " BC[2-0] ,Bit count" "8,,2,3,4,5,6,7"
else
group.long 0x24++0x03
line.long 0x00 "I2CMDR,I2C Mode Register"
bitfld.long 0x00 14. " FREE ,Free running bit" "Disabled,Enabled"
textline " "
bitfld.long 0x00 10. " MST ,Master/slave mode bit" "Slave,Master"
bitfld.long 0x00 9. " TRX ,Transmit/receive bit" "Receive,Transmit"
textline " "
bitfld.long 0x00 8. " XA ,Expand address enable bit" "7-bit addressing,10-bit addressing"
textline " "
bitfld.long 0x00 5. " NIRS ,I2C reset enable bit" "Disabled,Enabled"
textline " "
bitfld.long 0x00 3. " FDF ,Free data format enable bit (Not supported in digital loop back mode [this.dlb = 1])" "Disabled,Enabled"
textline " "
bitfld.long 0x00 0.--2. " BC[2-0] ,Bit count" "9,,3,4,5,6,7,8"
endif
hgroup.long 0x28++0x03
hide.long 0x00 "I2CIVR,I2C Interrupt Vector Register"
in
group.long 0x2C++0x03
line.long 0x00 "I2CEMDR,I2C Extended Mode Register"
bitfld.long 0x00 1. " IGNACK ,Ignore NACK mode" "Disabled,Enabled"
bitfld.long 0x00 0. " BCM ,Backwards compatibility mode" "Disabled,Enabled"
group.long 0x30++0x03
line.long 0x00 "I2CPSC,I2C Prescale Register"
hexmask.long.byte 0x00 0.--7. 1. " PSC ,Prescale"
rgroup.long 0x34++0x03
line.long 0x00 "I2CPID1,I2C Peripheral ID Register 1"
hexmask.long.byte 0x00 8.--15. 1. " CLASS ,Peripheral class"
hexmask.long.byte 0x00 0.--7. 1. " REVISION ,Revision level of the I2C"
group.long 0x38++0x03
line.long 0x00 "I2CPID2,I2C Peripheral ID Register 2"
hexmask.long.byte 0x00 0.--7. 1. " TYPE ,Peripheral type"
group.long 0x3C++0x03
line.long 0x00 "I2CDMACR,I2C DMA Control Register"
bitfld.long 0x00 1. " TXDMAEN ,Transmitter DMA enable" "Disabled,Enabled"
bitfld.long 0x00 0. " RXDMAEN ,Receive DMA enable" "Disabled,Enabled"
group.long 0x48++0x03
line.long 0x00 "I2CPFNC,I2C Pin Function Register"
bitfld.long 0x00 0. " PINFUNC ,SDA and SCL pin function" "I2C,I/O"
group.long 0x4C++0x03
line.long 0x00 "I2CPDIR,I2C Pin Direction Register"
bitfld.long 0x00 1. " SDADIR ,SDA direction" "Input,Output"
bitfld.long 0x00 0. " SCLDIR ,SCL direction" "Input,Output"
rgroup.long 0x50++0x03
line.long 0x00 "I2CDIN,I2C Data Input Register"
bitfld.long 0x00 1. " SDAIN ,Serial data in" "Low,High"
bitfld.long 0x00 0. " SCLSIN ,Serial clock data in" "Low,High"
group.long 0x54++0x03
line.long 0x00 "I2CDOUT,I2C Data Output Register"
bitfld.long 0x00 1. " SDAOUT ,SDA data output" "Low,High"
bitfld.long 0x00 0. " SCLOUT ,SCL data output" "Low,High"
group.long 0x58++0x03
line.long 0x00 "I2CDSET,I2C Data Set Register"
bitfld.long 0x00 1. " SDASET ,Serial data set" "Low,High"
bitfld.long 0x00 0. " SCLSET ,Serial clock set" "Low,High"
group.long 0x5C++0x03
line.long 0x00 "I2CDCLR,I2C Data Clear Register"
bitfld.long 0x00 1. " SDACLR ,Serial data clear" "No effect,Low"
bitfld.long 0x00 0. " SCLCLR ,Serial clock clear" "No effect,Low"
group.long 0x60++0x03
line.long 0x00 "I2CPDR,I2C Pin Open Drain Register"
bitfld.long 0x00 1. " SDAPDR ,SDA pin open drain disable" "No,Yes"
bitfld.long 0x00 0. " SCLPDR ,SCL pin open drain disable" "No,Yes"
group.long 0x64++0x03
line.long 0x00 "I2CPDIS,I2C Pull Disable Register"
bitfld.long 0x00 1. " SDAPDIS ,SDA pull disable" "No,Yes"
bitfld.long 0x00 0. " SCLPDIS ,SCL pull disable" "No,Yes"
group.long 0x68++0x03
line.long 0x00 "I2CPSEL,I2C Pull Select Register"
bitfld.long 0x00 1. " SDAPSEL ,SDA pull select" "Pull down,Pull up"
bitfld.long 0x00 0. " SCLPSEL ,SCL pull select" "Pull down,Pull up"
group.long 0x6C++0x03
line.long 0x00 "I2CSRS,I2C Pins Slew Rate Select Register"
bitfld.long 0x00 1. " SDASRS ,SDA slew rate select" "Slow,Normal"
bitfld.long 0x00 0. " SCLSRS ,SCL slew rate select" "Slow,Normal"
width 0x0B
tree.end
tree.end
tree.open "EMAC (EMAC/MDIO Module)"
tree "Control Module Registers"
base ad:0xFCF78800
width 16.
rgroup.long 0x0++0x3
line.long 0x0 "REVID,Transmit Identification and Version Register"
hexmask.long 0x0 0.--31. 1. " REV ,REV ID"
group.long 0x4++0x3
line.long 0x0 "SOFTRESET,Software Reset Register"
bitfld.long 0x0 0. " RESET ,Soft Reset for CPGMACSS_R modules INT, REGS, CPPI" "No reset,Reset"
group.long 0xC++0x3
line.long 0x0 "INTCONTROL,Interrupt Control Register"
sif (cpu()!="TMS570LC4357")
bitfld.long 0x0 21. " C2TXPACEEN ,C2_TX_PULSE Pacing" "No interrupt,Interrupt"
bitfld.long 0x0 20. " C2RXPACEEN ,C2_RX_PULSE Pacing" "No interrupt,Interrupt"
textline " "
bitfld.long 0x0 19. " C1TXPACEEN ,C1_TX_PULSE Pacing" "No interrupt,Interrupt"
bitfld.long 0x0 18. " C1RXPACEEN ,C1_RX_PULSE Pacing" "No interrupt,Interrupt"
textline " "
endif
bitfld.long 0x0 17. " C0TXPACEEN ,C0_TX_PULSE Pacing" "No interrupt,Interrupt"
bitfld.long 0x0 16. " C0RXPACEEN ,C0_RX_PULSE Pacing" "No interrupt,Interrupt"
textline " "
hexmask.long.word 0x0 0.--11. 1. " INTPRESCALE ,Interrupt Counter Prescaler (Number of 4us VBUSP_CLKs)"
group.long 0x10++0x3
line.long 0x0 "C0RXTHRESHEN,Core 0 Receive Threshold Enable Register"
bitfld.long 0x0 7. " RXCH7THRESHEN ,Corresponds to the interrupt for RXCH7THRESH" "Disabled,Enabled"
bitfld.long 0x0 6. " RXCH6THRESHEN ,Corresponds to the interrupt for RXCH6THRESH" "Disabled,Enabled"
textline " "
bitfld.long 0x0 5. " RXCH5THRESHEN ,Corresponds to the interrupt for RXCH5THRESH" "Disabled,Enabled"
bitfld.long 0x0 4. " RXCH4THRESHEN ,Corresponds to the interrupt for RXCH4THRESH" "Disabled,Enabled"
textline " "
bitfld.long 0x0 3. " RXCH3THRESHEN ,Corresponds to the interrupt for RXCH3THRESH" "Disabled,Enabled"
bitfld.long 0x0 2. " RXCH2THRESHEN ,Corresponds to the interrupt for RXCH2THRESH" "Disabled,Enabled"
textline " "
bitfld.long 0x0 1. " RXCH1THRESHEN ,Corresponds to the interrupt for RXCH1THRESH" "Disabled,Enabled"
bitfld.long 0x0 0. " RXCH0THRESHEN ,Corresponds to the interrupt for RXCH0THRESH" "Disabled,Enabled"
group.long 0x14++0x3
line.long 0x0 "C0RXEN,Core 0 Receive Enable Register"
bitfld.long 0x0 7. " RXCH7EN ,Corresponds to the interrupt for RXCH7EN" "Disabled,Enabled"
bitfld.long 0x0 6. " RXCH6EN ,Corresponds to the interrupt for RXCH6EN" "Disabled,Enabled"
textline " "
bitfld.long 0x0 5. " RXCH5EN ,Corresponds to the interrupt for RXCH5EN" "Disabled,Enabled"
bitfld.long 0x0 4. " RXCH4EN ,Corresponds to the interrupt for RXCH4EN" "Disabled,Enabled"
textline " "
bitfld.long 0x0 3. " RXCH3EN ,Corresponds to the interrupt for RXCH3EN" "Disabled,Enabled"
bitfld.long 0x0 2. " RXCH2EN ,Corresponds to the interrupt for RXCH2EN" "Disabled,Enabled"
textline " "
bitfld.long 0x0 1. " RXCH1EN ,Corresponds to the interrupt for RXCH1EN" "Disabled,Enabled"
bitfld.long 0x0 0. " RXCH0EN ,Corresponds to the interrupt for RXCH0EN" "Disabled,Enabled"
group.long 0x18++0x3
line.long 0x0 "C0TXEN,Core 0 Transmit Enable Register"
bitfld.long 0x0 7. " TXCH7EN ,Corresponds to the interrupt for TXCH7EN" "Disabled,Enabled"
bitfld.long 0x0 6. " TXCH6EN ,Corresponds to the interrupt for TXCH6EN" "Disabled,Enabled"
textline " "
bitfld.long 0x0 5. " TXCH5EN ,Corresponds to the interrupt for TXCH5EN" "Disabled,Enabled"
bitfld.long 0x0 4. " TXCH4EN ,Corresponds to the interrupt for TXCH4EN" "Disabled,Enabled"
textline " "
bitfld.long 0x0 3. " TXCH3EN ,Corresponds to the interrupt for TXCH3EN" "Disabled,Enabled"
bitfld.long 0x0 2. " TXCH2EN ,Corresponds to the interrupt for TXCH2EN" "Disabled,Enabled"
textline " "
bitfld.long 0x0 1. " TXCH1EN ,Corresponds to the interrupt for TXCH1EN" "Disabled,Enabled"
bitfld.long 0x0 0. " TXCH0EN ,Corresponds to the interrupt for TXCH0EN" "Disabled,Enabled"
group.long 0x1C++0x3
line.long 0x0 "C0MISCEN,Core 0 Misc Interrupt Enable Register"
bitfld.long 0x0 3. " STATPENDEN ,Status Pending Interrupt" "Disabled,Enabled"
bitfld.long 0x0 2. " HOSTPENDEN ,Host Pending Interrupt" "Disabled,Enabled"
textline " "
bitfld.long 0x0 1. " LINKINT0EN ,MDIO LINKINT[0]" "Disabled,Enabled"
bitfld.long 0x0 0. " USERINT0EN ,MDIO USERINT[0]" "Disabled,Enabled"
sif (cpu()!="TMS570LC4357"&&cpu()!="RM57L843-ZWT")
group.long 0x20++0x3
line.long 0x0 "C1RXTHRESHEN,Core 1 Receive Threshold Enable Register"
bitfld.long 0x0 7. " RXCH7THRESHEN ,Corresponds to the interrupt for RXCH7THRESH" "Disabled,Enabled"
bitfld.long 0x0 6. " RXCH6THRESHEN ,Corresponds to the interrupt for RXCH6THRESH" "Disabled,Enabled"
textline " "
bitfld.long 0x0 5. " RXCH5THRESHEN ,Corresponds to the interrupt for RXCH5THRESH" "Disabled,Enabled"
bitfld.long 0x0 4. " RXCH4THRESHEN ,Corresponds to the interrupt for RXCH4THRESH" "Disabled,Enabled"
textline " "
bitfld.long 0x0 3. " RXCH3THRESHEN ,Corresponds to the interrupt for RXCH3THRESH" "Disabled,Enabled"
bitfld.long 0x0 2. " RXCH2THRESHEN ,Corresponds to the interrupt for RXCH2THRESH" "Disabled,Enabled"
textline " "
bitfld.long 0x0 1. " RXCH1THRESHEN ,Corresponds to the interrupt for RXCH1THRESH" "Disabled,Enabled"
bitfld.long 0x0 0. " RXCH0THRESHEN ,Corresponds to the interrupt for RXCH0THRESH" "Disabled,Enabled"
group.long 0x24++0x3
line.long 0x0 "C1RXEN,Core 1 Receive Enable Register"
bitfld.long 0x0 7. " RXCH7EN ,Corresponds to the interrupt for RXCH7EN" "Disabled,Enabled"
bitfld.long 0x0 6. " RXCH6EN ,Corresponds to the interrupt for RXCH6EN" "Disabled,Enabled"
textline " "
bitfld.long 0x0 5. " RXCH5EN ,Corresponds to the interrupt for RXCH5EN" "Disabled,Enabled"
bitfld.long 0x0 4. " RXCH4EN ,Corresponds to the interrupt for RXCH4EN" "Disabled,Enabled"
textline " "
bitfld.long 0x0 3. " RXCH3EN ,Corresponds to the interrupt for RXCH3EN" "Disabled,Enabled"
bitfld.long 0x0 2. " RXCH2EN ,Corresponds to the interrupt for RXCH2EN" "Disabled,Enabled"
textline " "
bitfld.long 0x0 1. " RXCH1EN ,Corresponds to the interrupt for RXCH1EN" "Disabled,Enabled"
bitfld.long 0x0 0. " RXCH0EN ,Corresponds to the interrupt for RXCH0EN" "Disabled,Enabled"
group.long 0x28++0x3
line.long 0x0 "C1TXEN,Core 1 Transmit Enable Register"
bitfld.long 0x0 7. " TXCH7EN ,Corresponds to the interrupt for TXCH7EN" "Disabled,Enabled"
bitfld.long 0x0 6. " TXCH6EN ,Corresponds to the interrupt for TXCH6EN" "Disabled,Enabled"
textline " "
bitfld.long 0x0 5. " TXCH5EN ,Corresponds to the interrupt for TXCH5EN" "Disabled,Enabled"
bitfld.long 0x0 4. " TXCH4EN ,Corresponds to the interrupt for TXCH4EN" "Disabled,Enabled"
textline " "
bitfld.long 0x0 3. " TXCH3EN ,Corresponds to the interrupt for TXCH3EN" "Disabled,Enabled"
bitfld.long 0x0 2. " TXCH2EN ,Corresponds to the interrupt for TXCH2EN" "Disabled,Enabled"
textline " "
bitfld.long 0x0 1. " TXCH1EN ,Corresponds to the interrupt for TXCH1EN" "Disabled,Enabled"
bitfld.long 0x0 0. " TXCH0EN ,Corresponds to the interrupt for TXCH0EN" "Disabled,Enabled"
group.long 0x2C++0x3
line.long 0x0 "C1MISCEN,Core 1 Misc Enable Register"
bitfld.long 0x0 3. " STATPENDEN ,Status Pending Interrupt" "Disabled,Enabled"
bitfld.long 0x0 2. " HOSTPENDEN ,Host Pending Interrupt" "Disabled,Enabled"
textline " "
bitfld.long 0x0 1. " LINKINT0EN ,MDIO LINKINT[0]" "Disabled,Enabled"
bitfld.long 0x0 0. " USERINT0EN ,MDIO USERINT[0]" "Disabled,Enabled"
group.long 0x30++0x3
line.long 0x0 "C2RXTHRESHEN,Core 2 Receive Threshold Enable Register"
bitfld.long 0x0 7. " RXCH7THRESHEN ,Corresponds to the interrupt for RXCH7THRESH" "Disabled,Enabled"
bitfld.long 0x0 6. " RXCH6THRESHEN ,Corresponds to the interrupt for RXCH6THRESH" "Disabled,Enabled"
textline " "
bitfld.long 0x0 5. " RXCH5THRESHEN ,Corresponds to the interrupt for RXCH5THRESH" "Disabled,Enabled"
bitfld.long 0x0 4. " RXCH4THRESHEN ,Corresponds to the interrupt for RXCH4THRESH" "Disabled,Enabled"
textline " "
bitfld.long 0x0 3. " RXCH3THRESHEN ,Corresponds to the interrupt for RXCH3THRESH" "Disabled,Enabled"
bitfld.long 0x0 2. " RXCH2THRESHEN ,Corresponds to the interrupt for RXCH2THRESH" "Disabled,Enabled"
textline " "
bitfld.long 0x0 1. " RXCH1THRESHEN ,Corresponds to the interrupt for RXCH1THRESH" "Disabled,Enabled"
bitfld.long 0x0 0. " RXCH0THRESHEN ,Corresponds to the interrupt for RXCH0THRESH" "Disabled,Enabled"
group.long 0x34++0x3
line.long 0x0 "C2RXEN,Core 2 Receive Enable Register"
bitfld.long 0x0 7. " RXCH7EN ,Corresponds to the interrupt for RXCH7EN" "Disabled,Enabled"
bitfld.long 0x0 6. " RXCH6EN ,Corresponds to the interrupt for RXCH6EN" "Disabled,Enabled"
textline " "
bitfld.long 0x0 5. " RXCH5EN ,Corresponds to the interrupt for RXCH5EN" "Disabled,Enabled"
bitfld.long 0x0 4. " RXCH4EN ,Corresponds to the interrupt for RXCH4EN" "Disabled,Enabled"
textline " "
bitfld.long 0x0 3. " RXCH3EN ,Corresponds to the interrupt for RXCH3EN" "Disabled,Enabled"
bitfld.long 0x0 2. " RXCH2EN ,Corresponds to the interrupt for RXCH2EN" "Disabled,Enabled"
textline " "
bitfld.long 0x0 1. " RXCH1EN ,Corresponds to the interrupt for RXCH1EN" "Disabled,Enabled"
bitfld.long 0x0 0. " RXCH0EN ,Corresponds to the interrupt for RXCH0EN" "Disabled,Enabled"
group.long 0x38++0x3
line.long 0x0 "C2TXEN,Core 2 Transmit Enable Register"
bitfld.long 0x0 7. " TXCH7EN ,Corresponds to the interrupt for TXCH7EN" "Disabled,Enabled"
bitfld.long 0x0 6. " TXCH6EN ,Corresponds to the interrupt for TXCH6EN" "Disabled,Enabled"
textline " "
bitfld.long 0x0 5. " TXCH5EN ,Corresponds to the interrupt for TXCH5EN" "Disabled,Enabled"
bitfld.long 0x0 4. " TXCH4EN ,Corresponds to the interrupt for TXCH4EN" "Disabled,Enabled"
textline " "
bitfld.long 0x0 3. " TXCH3EN ,Corresponds to the interrupt for TXCH3EN" "Disabled,Enabled"
bitfld.long 0x0 2. " TXCH2EN ,Corresponds to the interrupt for TXCH2EN" "Disabled,Enabled"
textline " "
bitfld.long 0x0 1. " TXCH1EN ,Corresponds to the interrupt for TXCH1EN" "Disabled,Enabled"
bitfld.long 0x0 0. " TXCH0EN ,Corresponds to the interrupt for TXCH0EN" "Disabled,Enabled"
group.long 0x3C++0x3
line.long 0x0 "C2MISCEN,Core 2 Misc Enable Register"
bitfld.long 0x0 3. " STATPENDEN ,Status Pending Interrupt" "Disabled,Enabled"
bitfld.long 0x0 2. " HOSTPENDEN ,Host Pending Interrupt" "Disabled,Enabled"
textline " "
bitfld.long 0x0 1. " LINKINT0EN ,MDIO LINKINT[0]" "Disabled,Enabled"
bitfld.long 0x0 0. " USERINT0EN ,MDIO USERINT[0]" "Disabled,Enabled"
endif
rgroup.long 0x40++0x3
line.long 0x0 "C0RXTHRESHSTAT,Core 0 Receive Threshold Status Register"
bitfld.long 0x0 7. " RXCH7THRESHSTAT ,Corresponds to the interrupt for RXCH7THRESH" "Disabled,Enabled"
bitfld.long 0x0 6. " RXCH6THRESHSTAT ,Corresponds to the interrupt for RXCH6THRESH" "Disabled,Enabled"
textline " "
bitfld.long 0x0 5. " RXCH5THRESHSTAT ,Corresponds to the interrupt for RXCH5THRESH" "Disabled,Enabled"
bitfld.long 0x0 4. " RXCH4THRESHSTAT ,Corresponds to the interrupt for RXCH4THRESH" "Disabled,Enabled"
textline " "
bitfld.long 0x0 3. " RXCH3THRESHSTAT ,Corresponds to the interrupt for RXCH3THRESH" "Disabled,Enabled"
bitfld.long 0x0 2. " RXCH2THRESHSTAT ,Corresponds to the interrupt for RXCH2THRESH" "Disabled,Enabled"
textline " "
bitfld.long 0x0 1. " RXCH1THRESHSTAT ,Corresponds to the interrupt for RXCH1THRESH" "Disabled,Enabled"
bitfld.long 0x0 0. " RXCH0THRESHSTAT ,Corresponds to the interrupt for RXCH0THRESH" "Disabled,Enabled"
rgroup.long 0x44++0x3
line.long 0x0 "C0RXSTAT,Core 0 Receive Status Register"
bitfld.long 0x0 7. " RXCH7STAT ,Corresponds to the interrupt for RXCH7STAT" "Disabled,Enabled"
bitfld.long 0x0 6. " RXCH6STAT ,Corresponds to the interrupt for RXCH6STAT" "Disabled,Enabled"
textline " "
bitfld.long 0x0 5. " RXCH5STAT ,Corresponds to the interrupt for RXCH5STAT" "Disabled,Enabled"
bitfld.long 0x0 4. " RXCH4STAT ,Corresponds to the interrupt for RXCH4STAT" "Disabled,Enabled"
textline " "
bitfld.long 0x0 3. " RXCH3STAT ,Corresponds to the interrupt for RXCH3STAT" "Disabled,Enabled"
bitfld.long 0x0 2. " RXCH2STAT ,Corresponds to the interrupt for RXCH2STAT" "Disabled,Enabled"
textline " "
bitfld.long 0x0 1. " RXCH1STAT ,Corresponds to the interrupt for RXCH1STAT" "Disabled,Enabled"
bitfld.long 0x0 0. " RXCH0STAT ,Corresponds to the interrupt for RXCH0STAT" "Disabled,Enabled"
rgroup.long 0x48++0x3
line.long 0x0 "C0TXSTAT,Core 0 Transmit Status Register"
bitfld.long 0x0 7. " TXCH7STAT ,Corresponds to the interrupt for TXCH7STAT" "Disabled,Enabled"
bitfld.long 0x0 6. " TXCH6STAT ,Corresponds to the interrupt for TXCH6STAT" "Disabled,Enabled"
textline " "
bitfld.long 0x0 5. " TXCH5STAT ,Corresponds to the interrupt for TXCH5STAT" "Disabled,Enabled"
bitfld.long 0x0 4. " TXCH4STAT ,Corresponds to the interrupt for TXCH4STAT" "Disabled,Enabled"
textline " "
bitfld.long 0x0 3. " TXCH3STAT ,Corresponds to the interrupt for TXCH3STAT" "Disabled,Enabled"
bitfld.long 0x0 2. " TXCH2STAT ,Corresponds to the interrupt for TXCH2STAT" "Disabled,Enabled"
textline " "
bitfld.long 0x0 1. " TXCH1STAT ,Corresponds to the interrupt for TXCH1STAT" "Disabled,Enabled"
bitfld.long 0x0 0. " TXCH0STAT ,Corresponds to the interrupt for TXCH0STAT" "Disabled,Enabled"
rgroup.long 0x4C++0x3
line.long 0x0 "C0MISCSTAT,Core 0 Misc Interrupt Status Register"
bitfld.long 0x0 3. " STATPENDSTAT ,Interrupt status for EMAC STATPEND masked by the C0MISCEN register" "No interrupt,Interrupt"
bitfld.long 0x0 2. " HOSTPENDSTAT ,Interrupt status for EMAC HOSTPEND masked by the C0MISCEN register" "No interrupt,Interrupt"
textline " "
bitfld.long 0x0 1. " LINKINT0STAT ,Interrupt status for MDIO LINKINT0 masked by the C0MISCEN register" "No interrupt,Interrupt"
bitfld.long 0x0 0. " USERINT0STAT ,Interrupt status for MDIO USERINT0 masked by the C0MISCEN register" "No interrupt,Interrupt"
sif (cpu()!="TMS570LC4357"&&!cpuis("RM57L843-ZWT"))
group.long 0x50++0x3
line.long 0x0 "C1RXTHRESHSTAT,Core 1 Receive Threshold Status Register"
bitfld.long 0x0 7. " RXCH7THRESHSTAT ,Corresponds to the interrupt for RXCH7THRESH" "Disabled,Enabled"
bitfld.long 0x0 6. " RXCH6THRESHSTAT ,Corresponds to the interrupt for RXCH6THRESH" "Disabled,Enabled"
textline " "
bitfld.long 0x0 5. " RXCH5THRESHSTAT ,Corresponds to the interrupt for RXCH5THRESH" "Disabled,Enabled"
bitfld.long 0x0 4. " RXCH4THRESHSTAT ,Corresponds to the interrupt for RXCH4THRESH" "Disabled,Enabled"
textline " "
bitfld.long 0x0 3. " RXCH3THRESHSTAT ,Corresponds to the interrupt for RXCH3THRESH" "Disabled,Enabled"
bitfld.long 0x0 2. " RXCH2THRESHSTAT ,Corresponds to the interrupt for RXCH2THRESH" "Disabled,Enabled"
textline " "
bitfld.long 0x0 1. " RXCH1THRESHSTAT ,Corresponds to the interrupt for RXCH1THRESH" "Disabled,Enabled"
bitfld.long 0x0 0. " RXCH0THRESHSTAT ,Corresponds to the interrupt for RXCH0THRESH" "Disabled,Enabled"
group.long 0x54++0x3
line.long 0x0 "C1RXSTAT,Core 1 Receive Status Register"
bitfld.long 0x0 7. " RXCH7STAT ,Corresponds to the interrupt for RXCH7STAT" "Disabled,Enabled"
bitfld.long 0x0 6. " RXCH6STAT ,Corresponds to the interrupt for RXCH6STAT" "Disabled,Enabled"
textline " "
bitfld.long 0x0 5. " RXCH5STAT ,Corresponds to the interrupt for RXCH5STAT" "Disabled,Enabled"
bitfld.long 0x0 4. " RXCH4STAT ,Corresponds to the interrupt for RXCH4STAT" "Disabled,Enabled"
textline " "
bitfld.long 0x0 3. " RXCH3STAT ,Corresponds to the interrupt for RXCH3STAT" "Disabled,Enabled"
bitfld.long 0x0 2. " RXCH2STAT ,Corresponds to the interrupt for RXCH2STAT" "Disabled,Enabled"
textline " "
bitfld.long 0x0 1. " RXCH1STAT ,Corresponds to the interrupt for RXCH1STAT" "Disabled,Enabled"
bitfld.long 0x0 0. " RXCH0STAT ,Corresponds to the interrupt for RXCH0STAT" "Disabled,Enabled"
group.long 0x58++0x3
line.long 0x0 "C1TXSTAT,Core 1 Transmit Status Register"
bitfld.long 0x0 7. " TXCH7STAT ,Corresponds to the interrupt for TXCH7STAT" "Disabled,Enabled"
bitfld.long 0x0 6. " TXCH6STAT ,Corresponds to the interrupt for TXCH6STAT" "Disabled,Enabled"
textline " "
bitfld.long 0x0 5. " TXCH5STAT ,Corresponds to the interrupt for TXCH5STAT" "Disabled,Enabled"
bitfld.long 0x0 4. " TXCH4STAT ,Corresponds to the interrupt for TXCH4STAT" "Disabled,Enabled"
textline " "
bitfld.long 0x0 3. " TXCH3STAT ,Corresponds to the interrupt for TXCH3STAT" "Disabled,Enabled"
bitfld.long 0x0 2. " TXCH2STAT ,Corresponds to the interrupt for TXCH2STAT" "Disabled,Enabled"
textline " "
bitfld.long 0x0 1. " TXCH1STAT ,Corresponds to the interrupt for TXCH1STAT" "Disabled,Enabled"
bitfld.long 0x0 0. " TXCH0STAT ,Corresponds to the interrupt for TXCH0STAT" "Disabled,Enabled"
group.long 0x5C++0x3
line.long 0x0 "C1MISCSTAT,Core 1 Misc Interrupt Status Register"
bitfld.long 0x0 3. " STATPENDSTAT ,STATPENDSTAT" "Disabled,Enabled"
bitfld.long 0x0 2. " HOSTPENDSTAT ,HOSTPENDSTAT" "Disabled,Enabled"
textline " "
bitfld.long 0x0 1. " LINKINT0STAT ,LINKINT0STAT" "Disabled,Enabled"
bitfld.long 0x0 0. " USERINT0STAT ,USERINT0STAT" "Disabled,Enabled"
group.long 0x60++0x3
line.long 0x0 "C2RXTHRESHSTAT,Core 2 Receive Threshold Status Register"
bitfld.long 0x0 7. " RXCH7THRESHSTAT ,Corresponds to the interrupt for RXCH7THRESH" "Disabled,Enabled"
bitfld.long 0x0 6. " RXCH6THRESHSTAT ,Corresponds to the interrupt for RXCH6THRESH" "Disabled,Enabled"
textline " "
bitfld.long 0x0 5. " RXCH5THRESHSTAT ,Corresponds to the interrupt for RXCH5THRESH" "Disabled,Enabled"
bitfld.long 0x0 4. " RXCH4THRESHSTAT ,Corresponds to the interrupt for RXCH4THRESH" "Disabled,Enabled"
textline " "
bitfld.long 0x0 3. " RXCH3THRESHSTAT ,Corresponds to the interrupt for RXCH3THRESH" "Disabled,Enabled"
bitfld.long 0x0 2. " RXCH2THRESHSTAT ,Corresponds to the interrupt for RXCH2THRESH" "Disabled,Enabled"
textline " "
bitfld.long 0x0 1. " RXCH1THRESHSTAT ,Corresponds to the interrupt for RXCH1THRESH" "Disabled,Enabled"
bitfld.long 0x0 0. " RXCH0THRESHSTAT ,Corresponds to the interrupt for RXCH0THRESH" "Disabled,Enabled"
group.long 0x64++0x3
line.long 0x0 "C2RXSTAT,Core 2 Receive Status Register"
bitfld.long 0x0 7. " RXCH7STAT ,Corresponds to the interrupt for RXCH7STAT" "Disabled,Enabled"
bitfld.long 0x0 6. " RXCH6STAT ,Corresponds to the interrupt for RXCH6STAT" "Disabled,Enabled"
textline " "
bitfld.long 0x0 5. " RXCH5STAT ,Corresponds to the interrupt for RXCH5STAT" "Disabled,Enabled"
bitfld.long 0x0 4. " RXCH4STAT ,Corresponds to the interrupt for RXCH4STAT" "Disabled,Enabled"
textline " "
bitfld.long 0x0 3. " RXCH3STAT ,Corresponds to the interrupt for RXCH3STAT" "Disabled,Enabled"
bitfld.long 0x0 2. " RXCH2STAT ,Corresponds to the interrupt for RXCH2STAT" "Disabled,Enabled"
textline " "
bitfld.long 0x0 1. " RXCH1STAT ,Corresponds to the interrupt for RXCH1STAT" "Disabled,Enabled"
bitfld.long 0x0 0. " RXCH0STAT ,Corresponds to the interrupt for RXCH0STAT" "Disabled,Enabled"
group.long 0x68++0x3
line.long 0x0 "C2TXSTAT,Core 2 Transmit Status Register"
bitfld.long 0x0 7. " TXCH7STAT ,Corresponds to the interrupt for TXCH7STAT" "Disabled,Enabled"
bitfld.long 0x0 6. " TXCH6STAT ,Corresponds to the interrupt for TXCH6STAT" "Disabled,Enabled"
textline " "
bitfld.long 0x0 5. " TXCH5STAT ,Corresponds to the interrupt for TXCH5STAT" "Disabled,Enabled"
bitfld.long 0x0 4. " TXCH4STAT ,Corresponds to the interrupt for TXCH4STAT" "Disabled,Enabled"
textline " "
bitfld.long 0x0 3. " TXCH3STAT ,Corresponds to the interrupt for TXCH3STAT" "Disabled,Enabled"
bitfld.long 0x0 2. " TXCH2STAT ,Corresponds to the interrupt for TXCH2STAT" "Disabled,Enabled"
textline " "
bitfld.long 0x0 1. " TXCH1STAT ,Corresponds to the interrupt for TXCH1STAT" "Disabled,Enabled"
bitfld.long 0x0 0. " TXCH0STAT ,Corresponds to the interrupt for TXCH0STAT" "Disabled,Enabled"
group.long 0x6C++0x3
line.long 0x0 "C2MISCSTAT,Core 2 Misc Interrupt Status Register"
bitfld.long 0x0 3. " STATPENDSTAT ," "Disabled,Enabled"
bitfld.long 0x0 2. " HOSTPENDSTAT ," "Disabled,Enabled"
textline " "
bitfld.long 0x0 1. " LINKINT0STAT ," "Disabled,Enabled"
bitfld.long 0x0 0. " USERINT0STAT ," "Disabled,Enabled"
endif
group.long 0x70++0x3
line.long 0x0 "C0RXIMAX,Core 0 Receive Interrupts per Millisecond Register"
bitfld.long 0x0 0.--5. " RXIMAX ,Core 0 Receive Interrupts per Millisecond for C0RXPULSE" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x74++0x3
line.long 0x0 "C0TXIMAX,Core 0 Transmit Interrupts per Millisecond Register"
bitfld.long 0x0 0.--5. " TXIMAX ,Core 0 Receive Interrupts per Millisecond for C0TXPULSE" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
sif (cpu()!="TMS570LC4357"&&!cpuis("RM57L843-ZWT"))
group.long 0x78++0x3
line.long 0x0 "C1RXIMAX,Core 1 Receive Interrupts per Millisecond Register"
bitfld.long 0x0 0.--5. " RXIMAX ,Core 1 Receive Interrupts per Millisecond for C1RXPULSE" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x7C++0x3
line.long 0x0 "C1TXIMAX,Core 1 Transmit Interrupts per Millisecond Register"
bitfld.long 0x0 0.--5. " TXIMAX ,Core 1 Receive Interrupts per Millisecond for C1TXPULSE" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x80++0x3
line.long 0x0 "C2RXIMAX,Core 2 Receive Interrupts per Millisecond Register"
bitfld.long 0x0 0.--5. " RXIMAX ,Core 1 Receive Interrupts per Millisecond for C1RXPULSE" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x84++0x3
line.long 0x0 "C2TXIMAX,Core 2 Transmit Interrupts per Millisecond Register"
bitfld.long 0x0 0.--5. " TXIMAX ,Core 1 Receive Interrupts per Millisecond for C1TXPULSE" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
endif
width 0x0b
tree.end
tree "MDIO Registers"
base ad:0xFCF78900
width 18.
rgroup.long 0x00++0x03
line.long 0x00 "REV,MDIO Version Register"
sif (cpuis("TMS570LS1227*")||cpuis("TMS570LC4357")||cpu()=="RM57L843-ZWT")
group.long 0x04++0x03
line.long 0x00 "CONTROL,MDIO Control Register"
rbitfld.long 0x00 31. " IDLE ,State machine IDLE status bit" "Not idle,Idle"
bitfld.long 0x00 30. " ENABLE ,State machine enable control bit" "Disabled,Enabled"
textline " "
rbitfld.long 0x00 24.--28. " HIGHEST_USER_CHANNEL ,Highest user channel that is available in the module" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 20. " PREAMBLE ,Preamble disable" "No,Yes"
textline " "
eventfld.long 0x00 19. " FAULT ,Fault indicator" "No error,Error"
bitfld.long 0x00 18. " FAULTENB ,Fault detect enable" "Disabled,Enabled"
textline " "
hexmask.long.word 0x00 0.--15. 1. " CLKDIV ,Clock divider bits"
else
group.long 0x04++0x03
line.long 0x00 "CONTROL,MDIO Control Register"
bitfld.long 0x00 31. " IDLE ,State machine IDLE status bit" "Not idle,Idle"
bitfld.long 0x00 30. " ENABLE ,State machine enable control bit" "Disabled,Enabled"
textline " "
bitfld.long 0x00 24.--28. " HIGHEST_USER_CHANNEL ,Highest user channel that is available in the module" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 20. " PREAMBLE ,Preamble disable" "No,Yes"
textline " "
eventfld.long 0x00 19. " FAULT ,Fault indicator" "No error,Error"
bitfld.long 0x00 18. " FAULTENB ,Fault detect enable" "Disabled,Enabled"
textline " "
hexmask.long.word 0x00 0.--15. 1. " CLKDIV ,Clock divider bits"
endif
textline " "
group.long 0x08++0x03
line.long 0x00 "ALIVE,PHY Acknowledge Status Register"
eventfld.long 0x00 31. " ALIVE[31] ,PHY access acknowledge bit 31" "Not acknowledged,Acknowledged"
eventfld.long 0x00 30. " [30] ,PHY access acknowledge bit 30" "Not acknowledged,Acknowledged"
eventfld.long 0x00 29. " [29] ,PHY access acknowledge bit 29" "Not acknowledged,Acknowledged"
eventfld.long 0x00 28. " [28] ,PHY access acknowledge bit 28" "Not acknowledged,Acknowledged"
textline " "
eventfld.long 0x00 27. " [27] ,PHY access acknowledge bit 27" "Not acknowledged,Acknowledged"
eventfld.long 0x00 26. " [26] ,PHY access acknowledge bit 26" "Not acknowledged,Acknowledged"
eventfld.long 0x00 25. " [25] ,PHY access acknowledge bit 25" "Not acknowledged,Acknowledged"
eventfld.long 0x00 24. " [24] ,PHY access acknowledge bit 24" "Not acknowledged,Acknowledged"
textline " "
eventfld.long 0x00 23. " [23] ,PHY access acknowledge bit 23" "Not acknowledged,Acknowledged"
eventfld.long 0x00 22. " [22] ,PHY access acknowledge bit 22" "Not acknowledged,Acknowledged"
eventfld.long 0x00 21. " [21] ,PHY access acknowledge bit 21" "Not acknowledged,Acknowledged"
eventfld.long 0x00 20. " [20] ,PHY access acknowledge bit 20" "Not acknowledged,Acknowledged"
textline " "
eventfld.long 0x00 19. " [19] ,PHY access acknowledge bit 19" "Not acknowledged,Acknowledged"
eventfld.long 0x00 18. " [18] ,PHY access acknowledge bit 18" "Not acknowledged,Acknowledged"
eventfld.long 0x00 17. " [17] ,PHY access acknowledge bit 17" "Not acknowledged,Acknowledged"
eventfld.long 0x00 16. " [16] ,PHY access acknowledge bit 16" "Not acknowledged,Acknowledged"
textline " "
eventfld.long 0x00 15. " [15] ,PHY access acknowledge bit 15" "Not acknowledged,Acknowledged"
eventfld.long 0x00 14. " [14] ,PHY access acknowledge bit 14" "Not acknowledged,Acknowledged"
eventfld.long 0x00 13. " [13] ,PHY access acknowledge bit 13" "Not acknowledged,Acknowledged"
eventfld.long 0x00 12. " [12] ,PHY access acknowledge bit 12" "Not acknowledged,Acknowledged"
textline " "
eventfld.long 0x00 11. " [11] ,PHY access acknowledge bit 11" "Not acknowledged,Acknowledged"
eventfld.long 0x00 10. " [10] ,PHY access acknowledge bit 10" "Not acknowledged,Acknowledged"
eventfld.long 0x00 9. " [9] ,PHY access acknowledge bit 9" "Not acknowledged,Acknowledged"
eventfld.long 0x00 8. " [8] ,PHY access acknowledge bit 8" "Not acknowledged,Acknowledged"
textline " "
eventfld.long 0x00 7. " [7] ,PHY access acknowledge bit 7" "Not acknowledged,Acknowledged"
eventfld.long 0x00 6. " [6] ,PHY access acknowledge bit 6" "Not acknowledged,Acknowledged"
eventfld.long 0x00 5. " [5] ,PHY access acknowledge bit 5" "Not acknowledged,Acknowledged"
eventfld.long 0x00 4. " [4] ,PHY access acknowledge bit 4" "Not acknowledged,Acknowledged"
textline " "
eventfld.long 0x00 3. " [3] ,PHY access acknowledge bit 3" "Not acknowledged,Acknowledged"
eventfld.long 0x00 2. " [2] ,PHY access acknowledge bit 2" "Not acknowledged,Acknowledged"
eventfld.long 0x00 1. " [1] ,PHY access acknowledge bit 1" "Not acknowledged,Acknowledged"
eventfld.long 0x00 0. " [0] ,PHY access acknowledge bit 0" "Not acknowledged,Acknowledged"
textline " "
rgroup.long 0x0C++0x03
line.long 0x00 "LINK,PHY Link Status Register"
bitfld.long 0x00 31. " LINK[31] ,PHY read transaction acknowledge bit 31" "Not acknowledged,Acknowledged"
bitfld.long 0x00 30. " [30] ,PHY read transaction acknowledge bit 30" "Not acknowledged,Acknowledged"
bitfld.long 0x00 29. " [29] ,PHY read transaction acknowledge bit 29" "Not acknowledged,Acknowledged"
bitfld.long 0x00 28. " [28] ,PHY read transaction acknowledge bit 28" "Not acknowledged,Acknowledged"
textline " "
bitfld.long 0x00 27. " [27] ,PHY read transaction acknowledge bit 27" "Not acknowledged,Acknowledged"
bitfld.long 0x00 26. " [26] ,PHY read transaction acknowledge bit 26" "Not acknowledged,Acknowledged"
bitfld.long 0x00 25. " [25] ,PHY read transaction acknowledge bit 25" "Not acknowledged,Acknowledged"
bitfld.long 0x00 24. " [24] ,PHY read transaction acknowledge bit 24" "Not acknowledged,Acknowledged"
textline " "
bitfld.long 0x00 23. " [23] ,PHY read transaction acknowledge bit 23" "Not acknowledged,Acknowledged"
bitfld.long 0x00 22. " [22] ,PHY read transaction acknowledge bit 22" "Not acknowledged,Acknowledged"
bitfld.long 0x00 21. " [21] ,PHY read transaction acknowledge bit 21" "Not acknowledged,Acknowledged"
bitfld.long 0x00 20. " [20] ,PHY read transaction acknowledge bit 20" "Not acknowledged,Acknowledged"
textline " "
bitfld.long 0x00 19. " [19] ,PHY read transaction acknowledge bit 19" "Not acknowledged,Acknowledged"
bitfld.long 0x00 18. " [18] ,PHY read transaction acknowledge bit 18" "Not acknowledged,Acknowledged"
bitfld.long 0x00 17. " [17] ,PHY read transaction acknowledge bit 17" "Not acknowledged,Acknowledged"
bitfld.long 0x00 16. " [16] ,PHY read transaction acknowledge bit 16" "Not acknowledged,Acknowledged"
textline " "
bitfld.long 0x00 15. " [15] ,PHY read transaction acknowledge bit 15" "Not acknowledged,Acknowledged"
bitfld.long 0x00 14. " [14] ,PHY read transaction acknowledge bit 14" "Not acknowledged,Acknowledged"
bitfld.long 0x00 13. " [13] ,PHY read transaction acknowledge bit 13" "Not acknowledged,Acknowledged"
bitfld.long 0x00 12. " [12] ,PHY read transaction acknowledge bit 12" "Not acknowledged,Acknowledged"
textline " "
bitfld.long 0x00 11. " [11] ,PHY read transaction acknowledge bit 11" "Not acknowledged,Acknowledged"
bitfld.long 0x00 10. " [10] ,PHY read transaction acknowledge bit 10" "Not acknowledged,Acknowledged"
bitfld.long 0x00 9. " [9] ,PHY read transaction acknowledge bit 9" "Not acknowledged,Acknowledged"
bitfld.long 0x00 8. " [8] ,PHY read transaction acknowledge bit 8" "Not acknowledged,Acknowledged"
textline " "
bitfld.long 0x00 7. " [7] ,PHY read transaction acknowledge bit 7" "Not acknowledged,Acknowledged"
bitfld.long 0x00 6. " [6] ,PHY read transaction acknowledge bit 6" "Not acknowledged,Acknowledged"
bitfld.long 0x00 5. " [5] ,PHY read transaction acknowledge bit 5" "Not acknowledged,Acknowledged"
bitfld.long 0x00 4. " [4] ,PHY read transaction acknowledge bit 4" "Not acknowledged,Acknowledged"
textline " "
bitfld.long 0x00 3. " [3] ,PHY read transaction acknowledge bit 3" "Not acknowledged,Acknowledged"
bitfld.long 0x00 2. " [2] ,PHY read transaction acknowledge bit 2" "Not acknowledged,Acknowledged"
bitfld.long 0x00 1. " [1] ,PHY read transaction acknowledge bit 1" "Not acknowledged,Acknowledged"
bitfld.long 0x00 0. " [0] ,PHY read transaction acknowledge bit 0" "Not acknowledged,Acknowledged"
textline " "
group.long 0x10++0x03
line.long 0x00 "LINKINTRAW,MDIO Link Interrupt Raw Register"
eventfld.long 0x00 1. " USERPHY1 ,MDIO link change event raw value" "Not changed,Changed"
eventfld.long 0x00 0. " USERPHY0 ,MDIO link change event raw value" "Not changed,Changed"
group.long 0x14++0x03
line.long 0x00 "LINKINTMASKED,MDIO Link Interrupt Masked Register"
eventfld.long 0x00 1. " USERPHY1 ,MDIO link change interrupt masked value" "Not changed,Changed"
eventfld.long 0x00 0. " USERPHY0 ,MDIO link change interrupt masked value" "Not changed,Changed"
group.long 0x20++0x03
line.long 0x00 "USERINTRAW,MDIO User Interrupt Raw Register"
eventfld.long 0x00 1. " USERACCESS1 ,MDIO user command complete event bit" "Not completed,Completed"
eventfld.long 0x00 0. " USERACCESS0 ,MDIO user command complete event bit" "Not completed,Completed"
group.long 0x24++0x03
line.long 0x00 "USERINTMASKED,MDIO User Interrupt Masked Register Set/clr"
setclrfld.long 0x00 1. 0x04 1. 0x08 1. " USERACCESS1_SET/CLR ,Masked value of MDIO user command complete interrupt" "Not completed,Completed"
setclrfld.long 0x00 0. 0x04 0. 0x08 0. " USERACCESS0_SET/CLR ,Masked value of MDIO user command complete interrupt" "Not completed,Completed"
group.long 0x80++0x03
line.long 0x00 "USERACCESS0,MDIO User Access Register 0"
bitfld.long 0x00 31. " GO ,Writing a 1 causes MDIO state machine to start an MDIO access sequence" "0,1"
bitfld.long 0x00 30. " WRITE ,Write enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 29. " ACK ,PHY ACK of read transaction" "0,1"
bitfld.long 0x00 21.--25. " REGADR ,Register address. Specifies PHY register to be accessed for transaction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline " "
bitfld.long 0x00 16.--20. " PHYADR ,PHY address. Specifies PHY to be accessed for transaction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
hexmask.long.word 0x00 0.--15. 1. " DATA ,User data. Data to be read or written to PHY register"
group.long 0x84++0x03
line.long 0x00 "USERPHYSEL0,MDIO User PHY Select REG0"
bitfld.long 0x00 7. " LINKSEL ,Link status determination; 1 to determine link status using MLINK pin" "0,1"
bitfld.long 0x00 6. " LINKINTENB ,Link change interrupt enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 0.--4. " PHYADRMON ,Register address. Specifies PHY register to be accessed for transaction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x88++0x03
line.long 0x00 "USERACCESS1,MDIO User Access Register 1"
bitfld.long 0x00 31. " GO ,Writing a 1 causes MDIO state machine to start an MDIO access sequence" "0,1"
bitfld.long 0x00 30. " WRITE ,Write enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 29. " ACK ,PHY ACK of read transaction" "0,1"
bitfld.long 0x00 21.--25. " REGADR ,Register address. Specifies PHY register to be accessed for transaction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline " "
bitfld.long 0x00 16.--20. " PHYADR ,PHY address. Specifies PHY to be accessed for transaction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
hexmask.long.word 0x00 0.--15. 1. " DATA ,User data. Data to be read or written to PHY register"
group.long 0x8C++0x03
line.long 0x00 "USERPHYSEL1,MDIO User PHY Select REG1"
bitfld.long 0x00 7. " LINKSEL ,Link status determination; 1 to determine link status using MLINK pin" "0,1"
bitfld.long 0x00 6. " LINKINTENB ,Link change interrupt enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 0.--4. " PHYADRMON ,Register address. Specifies PHY register to be accessed for transaction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
width 0x0B
tree.end
tree "Module Registers"
base ad:0xFCF78000
width 19.
rgroup.long 0x00++0x03
line.long 0x00 "TXREVID,Transmit Identification And Version Register"
group.long 0x04++0x03
line.long 0x00 "TXCONTROL,Transmit Control Register"
bitfld.long 0x00 0. " TXEN ,Transmit enable" "Disabled,Enabled"
group.long 0x08++0x03
line.long 0x00 "TXTEARDOWN,Transmit Teardown Register"
bitfld.long 0x00 0.--2. " TXTDNCH ,TX teardown channed" "0,1,2,3,4,5,6,7"
rgroup.long 0x10++0x03
line.long 0x00 "RXREVID,RX Identification And Version Register"
group.long 0x14++0x03
line.long 0x00 "RXCONTROL,RX Control Register"
bitfld.long 0x00 0. " RXEN ,RX DMA enable" "Disabled,Enabled"
group.long 0x18++0x03
line.long 0x00 "RXTEARDOWN,RX Teardown Register"
bitfld.long 0x00 0.--2. " RXTDNCH ,RX teardown channel" "0,1,2,3,4,5,6,7"
rgroup.long 0x80++0x03
line.long 0x00 "TXINTSTATRAW,Transmit Interrupt Status Register"
bitfld.long 0x00 7. " TX7PEND ,TX7PEND raw interrupt read (Before mask)" "No interrupt,Interrupt"
bitfld.long 0x00 6. " TX6PEND ,TX6PEND raw interrupt read (Before mask)" "No interrupt,Interrupt"
textline " "
bitfld.long 0x00 5. " TX5PEND ,TX5PEND raw interrupt read (Before mask)" "No interrupt,Interrupt"
bitfld.long 0x00 4. " TX4PEND ,TX4PEND raw interrupt read (Before mask)" "No interrupt,Interrupt"
textline " "
bitfld.long 0x00 3. " TX3PEND ,TX3PEND raw interrupt read (Before mask)" "No interrupt,Interrupt"
bitfld.long 0x00 2. " TX2PEND ,TX2PEND raw interrupt read (Before mask)" "No interrupt,Interrupt"
textline " "
bitfld.long 0x00 1. " TX1PEND ,TX1PEND raw interrupt read (Before mask)" "No interrupt,Interrupt"
bitfld.long 0x00 0. " TX0PEND ,TX0PEND raw interrupt read (Before mask)" "No interrupt,Interrupt"
group.long 0x84++0x03
line.long 0x00 "TXINTSTATMASKED,Transmit Interrupt Status Register Masked"
setclrfld.long 0x00 7. 0x04 7. 0x08 7. " TX7PEND_SETCLR ,TX7PEND masked interrupt read" "No interrupt,Interrupt"
setclrfld.long 0x00 6. 0x04 6. 0x08 6. " TX6PEND_SETCLR ,TX6PEND masked interrupt read" "No interrupt,Interrupt"
textline " "
setclrfld.long 0x00 5. 0x04 5. 0x08 5. " TX5PEND_SETCLR ,TX5PEND masked interrupt read" "No interrupt,Interrupt"
setclrfld.long 0x00 4. 0x04 4. 0x08 4. " TX4PEND_SETCLR ,TX4PEND masked interrupt read" "No interrupt,Interrupt"
textline " "
setclrfld.long 0x00 3. 0x04 3. 0x08 3. " TX3PEND_SETCLR ,TX3PEND masked interrupt read" "No interrupt,Interrupt"
setclrfld.long 0x00 2. 0x04 2. 0x08 2. " TX2PEND_SETCLR ,TX2PEND masked interrupt read" "No interrupt,Interrupt"
textline " "
setclrfld.long 0x00 1. 0x04 1. 0x08 1. " TX1PEND_SETCLR ,TX1PEND masked interrupt read" "No interrupt,Interrupt"
setclrfld.long 0x00 0. 0x04 0. 0x08 0. " TX0PEND_SETCLR ,TX0PEND masked interrupt read" "No interrupt,Interrupt"
sif (cpuis("TMS570LC4357")||cpu()=="RM57L843-ZWT")
rgroup.long 0x90++0x03
else
group.long 0x90++0x03
endif
line.long 0x00 "MACINVECTOR,MAC Input Vector Register"
bitfld.long 0x00 27. " STATPEND ,Status pending" "0,1"
bitfld.long 0x00 26. " HOSTPEND ,Host pending" "0,1"
textline " "
bitfld.long 0x00 25. " LINKINT0 ,MDIO link int" "0,1"
bitfld.long 0x00 24. " USERINT0 ,MDIO user int" "0,1"
textline " "
hexmask.long.byte 0x00 16.--23. 1. " TXPEND ,TX pend[7:0]"
hexmask.long.byte 0x00 8.--15. 1. " RXTHRESHPEND ,RX thresh pend[7:0]"
textline " "
hexmask.long.byte 0x00 0.--7. 1. " RXPEND ,RX pend[7:0]"
group.long 0x94++0x03
line.long 0x00 "MACEOIVECTOR,MAC End Of Interrupt Vector"
bitfld.long 0x00 0.--4. " INTVECT ,MAC end of interrupt vector" "C0RXTHRESH,C0RX,C0TX,C0MISC,C1RXTHRESH,C1RX,C1TX,C1MISC,C2RXTHRESH,C2RX,C2TX,C2MISC,?..."
textline " "
sif (cpuis("TMS570LC4357")||cpu()=="RM57L843-ZWT")
rgroup.long 0xA0++0x03
else
group.long 0xA0++0x03
endif
line.long 0x00 "RXINTSTATRAW,Receive Interrupt Status Register Raw"
bitfld.long 0x00 15. " RX7THRESHPEND ,RX7THRESHPEND raw interrupt read (Before mask)" "No interrupt,Interrupt"
bitfld.long 0x00 14. " RX6THRESHPEND ,RX6THRESHPEND raw interrupt read (Before mask)" "No interrupt,Interrupt"
bitfld.long 0x00 13. " RX5THRESHPEND ,RX5THRESHPEND raw interrupt read (Before mask)" "No interrupt,Interrupt"
textline " "
bitfld.long 0x00 12. " RX4THRESHPEND ,RX4THRESHPEND raw interrupt read (Before mask)" "No interrupt,Interrupt"
bitfld.long 0x00 11. " RX3THRESHPEND ,RX3THRESHPEND raw interrupt read (Before mask)" "No interrupt,Interrupt"
bitfld.long 0x00 10. " RX2THRESHPEND ,RX2THRESHPEND raw interrupt read (Before mask)" "No interrupt,Interrupt"
textline " "
bitfld.long 0x00 9. " RX1THRESHPEND ,RX1THRESHPEND raw interrupt read (Before mask)" "No interrupt,Interrupt"
bitfld.long 0x00 8. " RX0THRESHPEND ,RX0THRESHPEND raw interrupt read (Before mask)" "No interrupt,Interrupt"
bitfld.long 0x00 7. " RX7PEND ,RX7PEND raw interrupt read (Before mask)" "No interrupt,Interrupt"
textline " "
bitfld.long 0x00 6. " RX6PEND ,RX6PEND raw interrupt read (Before mask)" "No interrupt,Interrupt"
bitfld.long 0x00 5. " RX5PEND ,RX5PEND raw interrupt read (Before mask)" "No interrupt,Interrupt"
bitfld.long 0x00 4. " RX4PEND ,RX4PEND raw interrupt read (Before mask)" "No interrupt,Interrupt"
textline " "
bitfld.long 0x00 3. " RX3PEND ,RX3PEND raw interrupt read (Before mask)" "No interrupt,Interrupt"
bitfld.long 0x00 2. " RX2PEND ,RX2PEND raw interrupt read (Before mask)" "No interrupt,Interrupt"
bitfld.long 0x00 1. " RX1PEND ,RX1PEND raw interrupt read (Before mask)" "No interrupt,Interrupt"
textline " "
bitfld.long 0x00 0. " RX0PEND ,RX0PEND raw interrupt read (Before mask)" "No interrupt,Interrupt"
textline " "
group.long 0xA4++0x03
line.long 0x00 "RXINTSTATMASKED,Receive Interrupt Status Register Masked"
setclrfld.long 0x00 15. 0x04 15. 0x08 15. " RX7THRESHPEND_SETCLR ,RX7THRESHPEND masked interrupt read" "No interrupt,Interrupt"
setclrfld.long 0x00 14. 0x04 14. 0x08 14. " RX6THRESHPEND_SETCLR ,RX6THRESHPEND masked interrupt read" "No interrupt,Interrupt"
setclrfld.long 0x00 13. 0x04 13. 0x08 13. " RX5THRESHPEND_SETCLR ,RX5THRESHPEND masked interrupt read" "No interrupt,Interrupt"
textline " "
setclrfld.long 0x00 12. 0x04 12. 0x08 12. " RX4THRESHPEND_SETCLR ,RX4THRESHPEND masked interrupt read" "No interrupt,Interrupt"
setclrfld.long 0x00 11. 0x04 11. 0x08 11. " RX3THRESHPEND_SETCLR ,RX3THRESHPEND masked interrupt read" "No interrupt,Interrupt"
setclrfld.long 0x00 10. 0x04 10. 0x08 10. " RX2THRESHPEND_SETCLR ,RX2THRESHPEND masked interrupt read" "No interrupt,Interrupt"
textline " "
setclrfld.long 0x00 9. 0x04 9. 0x08 9. " RX1THRESHPEND_SETCLR ,RX1THRESHPEND masked interrupt read" "No interrupt,Interrupt"
setclrfld.long 0x00 8. 0x04 8. 0x08 8. " RX0THRESHPEND_SETCLR ,RX0THRESHPEND masked interrupt read" "No interrupt,Interrupt"
setclrfld.long 0x00 7. 0x04 7. 0x08 7. " RX7PEND_SETCLR ,RX7PEND masked interrupt read" "No interrupt,Interrupt"
textline " "
setclrfld.long 0x00 6. 0x04 6. 0x08 6. " RX6PEND_SETCLR ,RX6PEND masked interrupt read" "No interrupt,Interrupt"
setclrfld.long 0x00 5. 0x04 5. 0x08 5. " RX5PEND_SETCLR ,RX5PEND masked interrupt read" "No interrupt,Interrupt"
setclrfld.long 0x00 4. 0x04 4. 0x08 4. " RX4PEND_SETCLR ,RX4PEND masked interrupt read" "No interrupt,Interrupt"
textline " "
setclrfld.long 0x00 3. 0x04 3. 0x08 3. " RX3PEND_SETCLR ,RX3PEND masked interrupt read" "No interrupt,Interrupt"
setclrfld.long 0x00 2. 0x04 2. 0x08 2. " RX2PEND_SETCLR ,RX2PEND masked interrupt read" "No interrupt,Interrupt"
setclrfld.long 0x00 1. 0x04 1. 0x08 1. " RX1PEND_SETCLR ,RX1PEND masked interrupt read" "No interrupt,Interrupt"
textline " "
setclrfld.long 0x00 0. 0x04 0. 0x08 0. " RX0PEND_SETCLR ,RX0PEND masked interrupt read" "No interrupt,Interrupt"
rgroup.long 0xB0++0x03
line.long 0x00 "MACINTSTATRAW,MAC Interrupt Status Register Raw (Unmasked)"
bitfld.long 0x00 1. " HOSTPEND ,Host pending interrupt (Hostpend); raw interrupt read (Before mask)" "No interrupt,Interrupt"
bitfld.long 0x00 0. " STATPEND ,Statistics pending interrupt (Statpend); raw interrupt read (Before mask)" "No interrupt,Interrupt"
group.long 0xB4++0x03
line.long 0x00 "MACINTSTATMASKED,MAC Interrupt Status Register Masked"
setclrfld.long 0x00 1. 0x04 1. 0x08 1. " HOSTPEND_SETCLR ,Host pending interrupt (Hostpend); masked interrupt read" "No interrupt,Interrupt"
setclrfld.long 0x00 0. 0x04 0. 0x08 0. " STATPEND_SETCLR ,Statistics pending interrupt (Statpend); masked interrupt read" "No interrupt,Interrupt"
group.long 0x100++0x03
line.long 0x00 "RXMBPENABLE,Receive Multicast/broadcast/promiscuous Channel Enable Register"
bitfld.long 0x00 30. " RXPASSCRC ,Pass receive CRC enable" "Disabled,Enabled"
bitfld.long 0x00 29. " RXQOSEN ,Receive quality of service enable" "Disabled,Enabled"
bitfld.long 0x00 28. " RXNOCHAIN ,Receive no buffer chaining" "Multiple,Single"
textline " "
bitfld.long 0x00 24. " RXCMFEN ,Receive copy MAC control frames enable" "Disabled,Enabled"
bitfld.long 0x00 23. " RXCSFEN ,Receive copy short frames enable" "Disabled,Enabled"
bitfld.long 0x00 22. " RXCEFEN ,Receive copy error frames enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 21. " RXCAFEN ,Receive copy all frames enable" "Disabled,Enabled"
bitfld.long 0x00 16.--18. " RXPROMCH ,Receive promiscuous channel select" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 13. " RXBROADEN ,Receive broadcast enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 8.--10. " RXBROADCH ,Receive broadcast channel select" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 5. " RXMULTEN ,RX multicast enable" "Disabled,Enabled"
bitfld.long 0x00 0.--2. " RXMULTCH ,RX multicast channel select" "0,1,2,3,4,5,6,7"
group.long 0x104++0x03
line.long 0x00 "RXUNICASTSET,Receive Unicast Enable Set Register"
bitfld.long 0x00 7. " RXCH7EN ,RX channel 7 unicast enable set" "No effect,Set"
bitfld.long 0x00 6. " RXCH6EN ,RX channel 6 unicast enable set" "No effect,Set"
bitfld.long 0x00 5. " RXCH5EN ,RX channel 5 unicast enable set" "No effect,Set"
textline " "
bitfld.long 0x00 4. " RXCH4EN ,RX channel 4 unicast enable set" "No effect,Set"
bitfld.long 0x00 3. " RXCH3EN ,RX channel 3 unicast enable set" "No effect,Set"
bitfld.long 0x00 2. " RXCH2EN ,RX channel 2 unicast enable set" "No effect,Set"
textline " "
bitfld.long 0x00 1. " RXCH1EN ,RX channel 1 unicast enable set" "No effect,Set"
bitfld.long 0x00 0. " RXCH0EN ,RX channel 0 unicast enable set" "No effect,Set"
group.long 0x108++0x03
line.long 0x00 "RXUNICASTCLEAR,Receive Unicast Clear Register"
bitfld.long 0x00 7. " RXCH7EN ,RX channel 7 unicast enable clear" "No effect,Clear"
bitfld.long 0x00 6. " RXCH6EN ,RX channel 6 unicast enable clear" "No effect,Clear"
bitfld.long 0x00 5. " RXCH5EN ,RX channel 5 unicast enable clear" "No effect,Clear"
textline " "
bitfld.long 0x00 4. " RXCH4EN ,RX channel 4 unicast enable clear" "No effect,Clear"
bitfld.long 0x00 3. " RXCH3EN ,RX channel 3 unicast enable clear" "No effect,Clear"
bitfld.long 0x00 2. " RXCH2EN ,RX channel 2 unicast enable clear" "No effect,Clear"
textline " "
bitfld.long 0x00 1. " RXCH1EN ,RX channel 1 unicast enable clear" "No effect,Clear"
bitfld.long 0x00 0. " RXCH0EN ,RX channel 0 unicast enable clear" "No effect,Clear"
group.long 0x10C++0x03
line.long 0x00 "RXMAXLEN,Receive Maximum Length Register"
hexmask.long.word 0x00 0.--15. 1. " RXMAXLEN ,RX maximum frame length"
group.long 0x110++0x03
line.long 0x00 "RXBUFFEROFFSET,Receive Buffer Offset Register"
hexmask.long.word 0x00 0.--15. 1. " RXBUFFEROFFSET ,RX buffer offset value"
group.long 0x114++0x03
line.long 0x00 "RXFILTERLOWTHRESH,Receive Filter Low Priority Frame Threshold Register"
hexmask.long.byte 0x00 0.--7. 1. " RXFILTERTHRESH ,RX filter low threshold"
width 15.
tree "Flow Thresh"
group.long 0x120++0x03
line.long 0x00 "RX0FLOWTHRESH,Receive Channel 0 Flow Control Threshold Register"
hexmask.long.byte 0x00 0.--7. 1. " RX0FLOWTHRESH ,RX flow threshold"
group.long 0x124++0x03
line.long 0x00 "RX1FLOWTHRESH,Receive Channel 1 Flow Control Threshold Register"
hexmask.long.byte 0x00 0.--7. 1. " RX1FLOWTHRESH ,RX flow threshold"
group.long 0x128++0x03
line.long 0x00 "RX2FLOWTHRESH,Receive Channel 2 Flow Control Threshold Register"
hexmask.long.byte 0x00 0.--7. 1. " RX2FLOWTHRESH ,RX flow threshold"
group.long 0x12C++0x03
line.long 0x00 "RX3FLOWTHRESH,Receive Channel 3 Flow Control Threshold Register"
hexmask.long.byte 0x00 0.--7. 1. " RX3FLOWTHRESH ,RX flow threshold"
group.long 0x130++0x03
line.long 0x00 "RX4FLOWTHRESH,Receive Channel 4 Flow Control Threshold Register"
hexmask.long.byte 0x00 0.--7. 1. " RX4FLOWTHRESH ,RX flow threshold"
group.long 0x134++0x03
line.long 0x00 "RX5FLOWTHRESH,Receive Channel 5 Flow Control Threshold Register"
hexmask.long.byte 0x00 0.--7. 1. " RX5FLOWTHRESH ,RX flow threshold"
group.long 0x138++0x03
line.long 0x00 "RX6FLOWTHRESH,Receive Channel 6 Flow Control Threshold Register"
hexmask.long.byte 0x00 0.--7. 1. " RX6FLOWTHRESH ,RX flow threshold"
group.long 0x13C++0x03
line.long 0x00 "RX7FLOWTHRESH,Receive Channel 7 Flow Control Threshold Register"
hexmask.long.byte 0x00 0.--7. 1. " RX7FLOWTHRESH ,RX flow threshold"
tree.end
width 15.
tree "Free Buffer"
group.long 0x140++0x03
line.long 0x00 "RX0FREEBUFFER,Receive Channel 0 Free Buffer Count Register"
hexmask.long.word 0x00 0.--15. 1. " RX0FREEBUF ,RX free buffer count; write to increment"
group.long 0x144++0x03
line.long 0x00 "RX1FREEBUFFER,Receive Channel 1 Free Buffer Count Register"
hexmask.long.word 0x00 0.--15. 1. " RX1FREEBUF ,RX free buffer count; write to increment"
group.long 0x148++0x03
line.long 0x00 "RX2FREEBUFFER,Receive Channel 2 Free Buffer Count Register"
hexmask.long.word 0x00 0.--15. 1. " RX2FREEBUF ,RX free buffer count; write to increment"
group.long 0x14C++0x03
line.long 0x00 "RX3FREEBUFFER,Receive Channel 3 Free Buffer Count Register"
hexmask.long.word 0x00 0.--15. 1. " RX3FREEBUF ,RX free buffer count; write to increment"
group.long 0x150++0x03
line.long 0x00 "RX4FREEBUFFER,Receive Channel 4 Free Buffer Count Register"
hexmask.long.word 0x00 0.--15. 1. " RX4FREEBUF ,RX free buffer count; write to increment"
group.long 0x154++0x03
line.long 0x00 "RX5FREEBUFFER,Receive Channel 5 Free Buffer Count Register"
hexmask.long.word 0x00 0.--15. 1. " RX5FREEBUF ,RX free buffer count; write to increment"
group.long 0x158++0x03
line.long 0x00 "RX6FREEBUFFER,Receive Channel 6 Free Buffer Count Register"
hexmask.long.word 0x00 0.--15. 1. " RX6FREEBUF ,RX free buffer count; write to increment"
group.long 0x15C++0x03
line.long 0x00 "RX7FREEBUFFER,Receive Channel 7 Free Buffer Count Register"
hexmask.long.word 0x00 0.--15. 1. " RX7FREEBUF ,RX free buffer count; write to increment"
tree.end
textline " "
group.long 0x160++0x03
line.long 0x00 "MACCONTROL,MAC Control Register"
bitfld.long 0x00 15. " RMIISPEED ,RMII 10/100 speed select (Ifctla)" "10,100"
bitfld.long 0x00 14. " RXOFFLENBLOCK ,Receive offset / length word write block" "Not blocked/length word,Blocked/during processing"
textline " "
bitfld.long 0x00 13. " RXOWNERSHIP ,Receive ownership write bit value" "0,1"
bitfld.long 0x00 11. " CMDIDLE ,Command idle" "Disabled,Enabled"
bitfld.long 0x00 10. " TXSHORTGAPEN ,Transmit short gap enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 9. " TXPTYPE ,Transmit queue priority type" "Disabled,Enabled"
bitfld.long 0x00 6. " TXPACE ,Transmit pacing enable" "Disabled,Enabled"
bitfld.long 0x00 5. " GMIIEN ,GMII enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 4. " TXFLOWEN ,Transmit flow control enable" "Disabled,Enabled"
bitfld.long 0x00 3. " RXBUFFERFLOWEN ,Receive buffer flow control enable" "Disabled,Enabled"
bitfld.long 0x00 1. " LOOPBACK ,Loopback mode" "Disabled,Enabled"
textline " "
bitfld.long 0x00 0. " FULLDUPLEX ,Full duplex mode; gigabit mode forces full duplex mode regardless of whether the fullduplex bit isset or not" "Disabled,Enabled"
sif (cpuis("TMS570LC4357")||cpu()=="RM57L843-ZWT")
rgroup.long 0x164++0x03
else
group.long 0x164++0x03
endif
line.long 0x00 "MACSTATUS,MAC Status Register"
bitfld.long 0x00 31. " IDLE ,CPGMAC idle" "Not idle,Idle"
bitfld.long 0x00 20.--23. " TXERRCODE ,TX host error code" "No error,SOP error,Ownership bit not set in SOP buffer,Zero next buffer descriptor pointer without EOP,Zero buffer pointer,Zero buffer length,Packet length error,?..."
textline " "
bitfld.long 0x00 16.--18. " TXERRCH ,TX host error channel" "0,1,2,3,4,5,6,7"
textline " "
bitfld.long 0x00 12.--15. " RXERRCODE ,RX host error code" "No error,,Ownership bit not set in SOP buffer,,Zero buffer pointer,?..."
textline " "
bitfld.long 0x00 8.--10. " RXERRCH ,RX host error channel" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 2. " RXQOSACT ,RX quality of service active" "Disabled,Enabled"
textline " "
bitfld.long 0x00 1. " RXFLOWACT ,RX flow control active" "Not active,Active"
bitfld.long 0x00 0. " TXFLOWACT ,TX flow control active" "Not active,Active"
group.long 0x168++0x03
line.long 0x00 "EMCONTROL,Emulation Control Register"
bitfld.long 0x00 1. " SOFT ,Emulation soft bit" "Disabled,Enabled"
bitfld.long 0x00 0. " FREE ,Emulation free bit" "Disabled,Enabled"
group.long 0x16C++0x03
line.long 0x00 "FIFOCONTROL,FIFO Control Register"
bitfld.long 0x00 0.--1. " TXCELLTHRESH ,TX FIFO cell threshold" ",,Two packet cells,Three packet cells"
rgroup.long 0x170++0x03
line.long 0x00 "MACCONFIG,MAC Configuration Register"
hexmask.long.byte 0x00 24.--31. 1. " TXCELLDEPTH ,TX cell depth - the number of cells in the transmit FIFO"
hexmask.long.byte 0x00 16.--23. 1. " RXCELLDEPTH ,RX cell depth - the number of cells in the receive FIFO"
textline " "
hexmask.long.byte 0x00 8.--15. 1. " ADDRESSTYPE ,Address type in the design"
hexmask.long.byte 0x00 0.--7. 1. " MACCFIG ,MAC configuration value"
group.long 0x174++0x03
line.long 0x00 "SOFTRESET,Soft Reset Register"
bitfld.long 0x00 0. " SOFTRESET ,Software reset" "No reset,Reset"
group.long 0x1D0++0x03
line.long 0x00 "MACSRCADDRLO,MAC Source Address Low"
hexmask.long.byte 0x00 8.--15. 1. " MACSRCADDR0 ,MAC source address lower 8 bits MACADDR[7:0]"
hexmask.long.byte 0x00 0.--7. 1. " MACSRCADDR1 ,MAC source address bits 15:9 MACADDR[15:8]"
group.long 0x1D4++0x03
line.long 0x00 "MACSRCADDRHI,MAC Source Address High"
hexmask.long.byte 0x00 24.--31. 1. " MACSRCADDR2 ,MAC source address bits 23:16 (Byte 2)"
hexmask.long.byte 0x00 16.--23. 1. " MACSRCADDR3 ,MAC source address bits 31:23 (Byte 3)"
textline " "
hexmask.long.byte 0x00 8.--15. 1. " MACSRCADDR4 ,MAC source address bits 39:32 (Byte 4)"
hexmask.long.byte 0x00 0.--7. 1. " MACSRCADDR5 ,MAC source address bits 47:40 (Byte 5)"
group.long 0x1D8++0x03
line.long 0x00 "MACHASH1,MAC Hash Address Register 1"
group.long 0x1DC++0x03
line.long 0x00 "MACHASH2,MAC Hash Address Register 2"
rgroup.long 0x1E0++0x03
line.long 0x00 "BOFFTEST,Back Off Test Register"
hexmask.long.word 0x00 16.--25. 1. " RNDNUM ,Backoff random number generator"
bitfld.long 0x00 12.--15. " COLLCOUNT ,Collision count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
hexmask.long.word 0x00 0.--9. 1. " TXBACKOFF ,Backoff count"
rgroup.long 0x1E4++0x03
line.long 0x00 "TPACETEST,Transmit Pacing Algorithm Test Register"
bitfld.long 0x00 0.--4. " PACEVAL ,Pacing register current value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
rgroup.long 0x1E8++0x03
line.long 0x00 "RXPAUSE,Receive Pause Timer Register"
hexmask.long.word 0x00 0.--15. 1. " PAUSETIMER ,RX pause timer value"
rgroup.long 0x1EC++0x03
line.long 0x00 "TXPAUSE,Transmit Pause Timer Register"
hexmask.long.word 0x00 0.--15. 1. " PAUSETIMER ,TX pause timer value"
group.long 0x500++0x03
line.long 0x00 "MACADDRLO,MAC Address Low - From Receive Address Matching Memory Map"
bitfld.long 0x00 20. " VALID ,Address valid bit" "Not valid,Valid"
bitfld.long 0x00 19. " MATCHFILT ,Match or filter bit" "Filter,Match"
textline " "
bitfld.long 0x00 16.--18. " CHANNEL ,Channel select" "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x00 8.--15. 1. " MACADDR0 ,MAC addres lower 8 bits (Byte 0)"
textline " "
hexmask.long.byte 0x00 0.--7. 1. " MACADDR1 ,MAC addres bits 15:8 (Byte 1)"
group.long 0x504++0x03
line.long 0x00 "MACADDRHI,MAC Address High - Receive Address Matching"
hexmask.long.byte 0x00 24.--31. 1. " MACADDR2 ,MAC source address bits 23:16 (Byte 2)"
hexmask.long.byte 0x00 16.--23. 1. " MACADDR3 ,MAC source address bits 31:23 (Byte 3)"
textline " "
hexmask.long.byte 0x00 8.--15. 1. " MACADDR4 ,MAC source address bits 39:32 (Byte 4)"
hexmask.long.byte 0x00 0.--7. 1. " MACADDR5 ,MAC source address bits 47:40 (Byte 5)"
group.long 0x508++0x03
line.long 0x00 "MACINDEX,MAC Index Register"
bitfld.long 0x00 0.--4. " MACINDEX ,MAC address index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
width 8.
tree "Transmit/receive Channels"
group.long 0x600++0x03
line.long 0x00 "TX0HDP,Transmit Channel 0 DMA Head Descriptor Pointer Register"
group.long 0x604++0x03
line.long 0x00 "TX1HDP,Transmit Channel 1 DMA Head Descriptor Pointer Register"
group.long 0x608++0x03
line.long 0x00 "TX2HDP,Transmit Channel 2 DMA Head Descriptor Pointer Register"
group.long 0x60C++0x03
line.long 0x00 "TX3HDP,Transmit Channel 3 DMA Head Descriptor Pointer Register"
group.long 0x610++0x03
line.long 0x00 "TX4HDP,Transmit Channel 4 DMA Head Descriptor Pointer Register"
group.long 0x614++0x03
line.long 0x00 "TX5HDP,Transmit Channel 5 DMA Head Descriptor Pointer Register"
group.long 0x618++0x03
line.long 0x00 "TX6HDP,Transmit Channel 6 DMA Head Descriptor Pointer Register"
group.long 0x61C++0x03
line.long 0x00 "TX7HDP,Transmit Channel 7 DMA Head Descriptor Pointer Register"
group.long 0x620++0x03
line.long 0x00 "RX0HDP,Receive Channel 0 DMA Head Descriptor Pointer Register"
group.long 0x624++0x03
line.long 0x00 "RX1HDP,Receive Channel 1 DMA Head Descriptor Pointer Register"
group.long 0x628++0x03
line.long 0x00 "RX2HDP,Receive Channel 2 DMA Head Descriptor Pointer Register"
group.long 0x62C++0x03
line.long 0x00 "RX3HDP,Receive Channel 3 DMA Head Descriptor Pointer Register"
group.long 0x630++0x03
line.long 0x00 "RX4HDP,Receive Channel 4 DMA Head Descriptor Pointer Register"
group.long 0x634++0x03
line.long 0x00 "RX5HDP,Receive Channel 5 DMA Head Descriptor Pointer Register"
group.long 0x638++0x03
line.long 0x00 "RX6HDP,Receive Channel 6 DMA Head Descriptor Pointer Register"
group.long 0x63C++0x03
line.long 0x00 "RX7HDP,Receive Channel 7 DMA Head Descriptor Pointer Register"
group.long 0x640++0x03
line.long 0x00 "TX0CP,Transmit Channel 0 Completion Pointer (Interrupt Ack) Register"
group.long 0x644++0x03
line.long 0x00 "TX1CP,Transmit Channel 1 Completion Pointer Register"
group.long 0x648++0x03
line.long 0x00 "TX2CP,Transmit Channel 2 Completion Pointer Register"
group.long 0x64C++0x03
line.long 0x00 "TX3CP,Transmit Channel 3 Completion Pointer Register"
group.long 0x650++0x03
line.long 0x00 "TX4CP,Transmit Channel 4 Completion Pointer Register"
group.long 0x654++0x03
line.long 0x00 "TX5CP,Transmit Channel 5 Completion Pointer Register"
group.long 0x658++0x03
line.long 0x00 "TX6CP,Transmit Channel 6 Completion Pointer Register"
group.long 0x65C++0x03
line.long 0x00 "TX7CP,Transmit Channel 7 Completion Pointer Register"
group.long 0x660++0x03
line.long 0x00 "RX0CP,Receive Channel 0 Completion Pointer (Interrupt Ack) Register"
group.long 0x664++0x03
line.long 0x00 "RX1CP,Receive Channel 1 Completion Pointer (Interrupt Ack) Register"
group.long 0x668++0x03
line.long 0x00 "RX2CP,Receive Channel 2 Completion Pointer (Interrupt Ack) Register"
group.long 0x66C++0x03
line.long 0x00 "RX3CP,Receive Channel 3 Completion Pointer (Interrupt Ack) Register"
group.long 0x670++0x03
line.long 0x00 "RX4CP,Receive Channel 4 Completion Pointer (Interrupt Ack) Register"
group.long 0x674++0x03
line.long 0x00 "RX5CP,Receive Channel 5 Completion Pointer (Interrupt Ack) Register"
group.long 0x678++0x03
line.long 0x00 "RX6CP,Receive Channel 6 Completion Pointer (Interrupt Ack) Register"
group.long 0x67C++0x03
line.long 0x00 "RX7CP,Receive Channel 7 Completion Pointer (Interrupt Ack) Register"
tree.end
width 19.
tree "Frame Options"
group.long 0x200++0x03
line.long 0x00 "RXGOODFRAMES,Good RX Frames"
group.long 0x204++0x03
line.long 0x00 "RXBCASTFRAMES,Total Number Of Good Broadcast Frames Received"
group.long 0x208++0x03
line.long 0x00 "RXMCASTFRAMES,Total Number Of Good Multicast Frames Received"
group.long 0x20C++0x03
line.long 0x00 "RXPAUSEFRAMES,Pause RX Frames Register"
group.long 0x210++0x03
line.long 0x00 "RXCRCERRORS,Total Number Of Frames Received With CRC Errors"
group.long 0x214++0x03
line.long 0x00 "RXALIGNCODEERRORS,Total Number Of Frames Received With Alignment/code Errors"
group.long 0x218++0x03
line.long 0x00 "RXOVERSIZED,Total Number Of Oversized Frames Received"
group.long 0x21C++0x03
line.long 0x00 "RXJABBER,Total Number Of Jabber Frames Received"
group.long 0x220++0x03
line.long 0x00 "RXUNDERSIZED,Total Number Of Undersized Frames Received"
group.long 0x224++0x03
line.long 0x00 "RXFRAGMENTS,RX Frame Fragments Register"
group.long 0x228++0x03
line.long 0x00 "RXFILTERED,Filtered Receive Frames"
group.long 0x22C++0x03
line.long 0x00 "RXQOSFILTERED,Received Frames Filtered By QOS"
group.long 0x230++0x03
line.long 0x00 "RXOCTETS,Total Number Of Received Bytes In Good Frames"
group.long 0x234++0x03
line.long 0x00 "TXGOODFRAMES,Total Number Of Good Frames Transmitted"
group.long 0x238++0x03
line.long 0x00 "TXBCASTFRAMES,Broadcast TX Frames Register"
group.long 0x23C++0x03
line.long 0x00 "TXMCASTFRAMES,Multicast TX Frames Register"
group.long 0x240++0x03
line.long 0x00 "TXPAUSEFRAMES,Pause TX Frames Register"
group.long 0x244++0x03
line.long 0x00 "TXDEFERRED,Deferred TX Frames Register"
group.long 0x248++0x03
line.long 0x00 "TXCOLLISION,TX Collision Frames Register"
group.long 0x24C++0x03
line.long 0x00 "TXSINGLECOLL,TX Single Collision Frames Register"
group.long 0x250++0x03
line.long 0x00 "TXMULTICOLL,TX Multiple Collision Frames Register"
group.long 0x254++0x03
line.long 0x00 "TXEXCESSIVECOLL,TX Excessive Collision Frames Register"
group.long 0x258++0x03
line.long 0x00 "TXLATECOLL,TX Late Collision Frames Register"
group.long 0x25C++0x03
line.long 0x00 "TXUNDERRUN,TX Underrun Error Register"
group.long 0x260++0x03
line.long 0x00 "TXCARRIERSENSE,TX Carrier Sense Errors Register"
group.long 0x264++0x03
line.long 0x00 "TXOCTETS,TX Octet Frames Register"
group.long 0x268++0x03
line.long 0x00 "FRAME64,Transmit And Receive 64 Octet Frames Register"
group.long 0x26C++0x03
line.long 0x00 "FRAME65T127,Transmit And Receive 65 To 127 Octet Frames Register"
group.long 0x270++0x03
line.long 0x00 "FRAME128T255,Transmit And Receive 128 To 255 Octet Frames Register"
group.long 0x274++0x03
line.long 0x00 "FRAME256T511,Transmit And Receive 256 To 511 Octet Frames Register"
group.long 0x278++0x03
line.long 0x00 "FRAME512T1023,Transmit And Receive 512 To 1023 Octet Frames Register"
group.long 0x27C++0x03
line.long 0x00 "FRAME1024TUP,Transmit And Receive 1024 To 1518 Octet Frames Register"
group.long 0x280++0x03
line.long 0x00 "NETOCTETS,Network Octet Frames Register"
group.long 0x284++0x03
line.long 0x00 "RXSOFOVERRUNS,Receive FIFO Or DMA Start Of Frame Overruns Register"
group.long 0x288++0x03
line.long 0x00 "RXMOFOVERRUNS,Receive FIFO Or DMA Middle Of Frame Overruns Register"
group.long 0x28C++0x03
line.long 0x00 "RXDMAOVERRUNS,Receive DMA Start Of Frame And Middle Of Frame Overruns Register"
tree.end
width 0x0B
tree.end
tree.end
tree.open "eCAP (Enhanced Capture Module)"
tree "eCAP 1"
base ad:0xFCF79300
width 11.
group.long 0x00++0x17
line.long 0x00 "TSCTR,Time-Stamp Counter Register"
line.long 0x04 "CTRPHS,Counter Phase Control Register"
line.long 0x08 "CAP1,Capture-1 Register"
line.long 0x0C "CAP2,Capture-2 Register"
line.long 0x10 "CAP3,Capture-3 Register"
line.long 0x14 "CAP4,Capture-4 Register"
sif cpu()=="RM57L843-ZWT"
if (((d.w(ad:0xFCF79300+0x2A))&0x201)==0x200)
group.word 0x2A++0x01
line.word 0x00 "ECCTL2,ECAP Control Register 2"
bitfld.word 0x00 10. " APWMPOL ,APWM output polarity select" "High,Low"
bitfld.word 0x00 9. " CAP_APWM ,CAP/APWM operating mode select" "Capture mode,APWM mode"
textline " "
bitfld.word 0x00 8. " SWSYNC ,Software-forced counter TSCTR synchronizing" "No effect,Forced"
bitfld.word 0x00 6.--7. " SYNCO_SEL ,Sync-Out select" "Pass through,CTR = PRD,Disabled,Disabled"
textline " "
bitfld.word 0x00 5. " SYNCI_EN ,Counter TSCTR Sync-In select mode" "Disabled,Enabled"
bitfld.word 0x00 4. " TSCTRSTOP ,Time stamp TSCTR counter stop control" "Stopped,Free-running"
textline " "
bitfld.word 0x00 3. " REARM ,One-Shot Re-Arming control" "No effect,One-shot sequence"
bitfld.word 0x00 1.--2. " STOP_WRAP ,Wrap value for one-shot mode" "Capture event 1,Capture event 2,Capture event 3,Capture event 4"
textline " "
bitfld.word 0x00 0. " CONT_ONESHT ,Continuous or one-shot mode control" "Continuous,One-shot"
elif (((d.w(ad:0xFCF79300+0x2A))&0x201)==0x201)
group.word 0x2A++0x01
line.word 0x00 "ECCTL2,ECAP Control Register 2"
bitfld.word 0x00 10. " APWMPOL ,APWM output polarity select" "High,Low"
bitfld.word 0x00 9. " CAP_APWM ,CAP/APWM operating mode select" "Capture mode,APWM mode"
textline " "
bitfld.word 0x00 8. " SWSYNC ,Software-forced counter TSCTR synchronizing" "No effect,Forced"
bitfld.word 0x00 6.--7. " SYNCO_SEL ,Sync-Out select" "Pass through,CTR = PRD,Disabled,Disabled"
textline " "
bitfld.word 0x00 5. " SYNCI_EN ,Counter TSCTR Sync-In select mode" "Disabled,Enabled"
bitfld.word 0x00 4. " TSCTRSTOP ,Time stamp TSCTR counter stop control" "Stopped,Free-running"
textline " "
bitfld.word 0x00 3. " REARM ,One-Shot Re-Arming control" "No effect,One-shot sequence"
bitfld.word 0x00 1.--2. " STOP_WRAP ,Stop value for one-shot mode" "Capture event 1,Capture event 2,Capture event 3,Capture event 4"
textline " "
bitfld.word 0x00 0. " CONT_ONESHT ,Continuous or one-shot mode control" "Continuous,One-shot"
elif (((d.w(ad:0xFCF79300+0x2A))&0x201)==0x01)
group.word 0x2A++0x01
line.word 0x00 "ECCTL2,ECAP Control Register 2"
bitfld.word 0x00 9. " CAP_APWM ,CAP/APWM operating mode select" "Capture mode,APWM mode"
textline " "
bitfld.word 0x00 8. " SWSYNC ,Software-forced counter TSCTR synchronizing" "No effect,Forced"
bitfld.word 0x00 6.--7. " SYNCO_SEL ,Sync-Out select" "Pass through,CTR = PRD,Disabled,Disabled"
textline " "
bitfld.word 0x00 5. " SYNCI_EN ,Counter TSCTR Sync-In select mode" "Disabled,Enabled"
bitfld.word 0x00 4. " TSCTRSTOP ,Time stamp TSCTR counter stop control" "Stopped,Free-running"
textline " "
bitfld.word 0x00 3. " REARM ,One-Shot Re-Arming control" "No effect,One-shot sequence"
bitfld.word 0x00 1.--2. " STOP_WRAP ,Stop value for one-shot mode" "Capture event 1,Capture event 2,Capture event 3,Capture event 4"
textline " "
bitfld.word 0x00 0. " CONT_ONESHT ,Continuous or one-shot mode control" "Continuous,One-shot"
else
group.word 0x2A++0x01
line.word 0x00 "ECCTL2,ECAP Control Register 2"
bitfld.word 0x00 9. " CAP_APWM ,CAP/APWM operating mode select" "Capture mode,APWM mode"
textline " "
bitfld.word 0x00 8. " SWSYNC ,Software-forced counter TSCTR synchronizing" "No effect,Forced"
bitfld.word 0x00 6.--7. " SYNCO_SEL ,Sync-Out select" "Pass through,CTR = PRD,Disabled,Disabled"
textline " "
bitfld.word 0x00 5. " SYNCI_EN ,Counter TSCTR Sync-In select mode" "Disabled,Enabled"
bitfld.word 0x00 4. " TSCTRSTOP ,Time stamp TSCTR counter stop control" "Stopped,Free-running"
textline " "
bitfld.word 0x00 3. " REARM ,One-Shot Re-Arming control" "No effect,One-shot sequence"
bitfld.word 0x00 1.--2. " STOP_WRAP ,Wrap value for one-shot mode" "Capture event 1,Capture event 2,Capture event 3,Capture event 4"
textline " "
bitfld.word 0x00 0. " CONT_ONESHT ,Continuous or one-shot mode control" "Continuous,One-shot"
endif
group.word 0x28++0x01
line.word 0x00 "ECCTL1,ECAP Control Regiser 1"
bitfld.word 0x00 14.--15. " FREE/SOFT ,Emulation control" "Stopped immediately,Run until = 0,Run free,Run free"
bitfld.word 0x00 9.--13. " PRESCALE ,Event filter prescale sel" "/1,/2,/4,/6,/8,/10,/12,/14,/16,/18,/20,/22,/24,/26,/28,/30,/32,/34,/36,/38,/40,/42,/44,/46,/48,/50,/52,/54,/56,/58,/60,/62"
textline " "
bitfld.word 0x00 8. " CAPLDEN ,Enable loading of CAP1-4 registers on a capture event" "Disabled,Enabled"
bitfld.word 0x00 7. " CTRRST4 ,Counter reset on capture event 4" "Not reset,Reset"
textline " "
bitfld.word 0x00 6. " CAP4POL ,Capture event 4 polarity select" "RE,FE"
bitfld.word 0x00 5. " CTRRST3 ,Counter reset on capture event 3" "Not reset,Reset"
textline " "
bitfld.word 0x00 4. " CAP3POL ,Capture event 3 polarity select" "RE,FE"
bitfld.word 0x00 3. " CTRRST2 ,Counter reset on capture event 2" "Not reset,Reset"
textline " "
bitfld.word 0x00 2. " CAP2POL ,Capture event 2 polarity select" "RE,FE"
bitfld.word 0x00 1. " CTRRST1 ,Counter reset on capture event 1" "Not reset,Reset"
textline " "
bitfld.word 0x00 0. " CAP1POL ,Capture event 1 polarity select" "RE,FE"
else
if (((d.w(ad:0xFCF79300+0x28))&0x201)==0x200)
group.word 0x28++0x01
line.word 0x00 "ECCTL2,ECAP Control Register 2"
bitfld.word 0x00 10. " APWMPOL ,APWM output polarity select" "High,Low"
bitfld.word 0x00 9. " CAP_APWM ,CAP/APWM operating mode select" "Capture mode,APWM mode"
textline " "
bitfld.word 0x00 8. " SWSYNC ,Software-forced counter TSCTR synchronizing" "No effect,Forced"
bitfld.word 0x00 6.--7. " SYNCO_SEL ,Sync-Out select" "Pass through,CTR = PRD,Disabled,Disabled"
textline " "
bitfld.word 0x00 5. " SYNCI_EN ,Counter TSCTR Sync-In select mode" "Disabled,Enabled"
bitfld.word 0x00 4. " TSCTRSTOP ,Time stamp TSCTR counter stop control" "Stopped,Free-running"
textline " "
bitfld.word 0x00 3. " REARM ,One-Shot Re-Arming control" "No effect,One-shot sequence"
bitfld.word 0x00 1.--2. " STOP_WRAP ,Wrap value for one-shot mode" "Capture event 1,Capture event 2,Capture event 3,Capture event 4"
textline " "
bitfld.word 0x00 0. " CONT_ONESHT ,Continuous or one-shot mode control" "Continuous,One-shot"
elif (((d.w(ad:0xFCF79300+0x28))&0x201)==0x201)
group.word 0x28++0x01
line.word 0x00 "ECCTL2,ECAP Control Register 2"
bitfld.word 0x00 10. " APWMPOL ,APWM output polarity select" "High,Low"
bitfld.word 0x00 9. " CAP_APWM ,CAP/APWM operating mode select" "Capture mode,APWM mode"
textline " "
bitfld.word 0x00 8. " SWSYNC ,Software-forced counter TSCTR synchronizing" "No effect,Forced"
bitfld.word 0x00 6.--7. " SYNCO_SEL ,Sync-Out select" "Pass through,CTR = PRD,Disabled,Disabled"
textline " "
bitfld.word 0x00 5. " SYNCI_EN ,Counter TSCTR Sync-In select mode" "Disabled,Enabled"
bitfld.word 0x00 4. " TSCTRSTOP ,Time stamp TSCTR counter stop control" "Stopped,Free-running"
textline " "
bitfld.word 0x00 3. " REARM ,One-Shot Re-Arming control" "No effect,One-shot sequence"
bitfld.word 0x00 1.--2. " STOP_WRAP ,Stop value for one-shot mode" "Capture event 1,Capture event 2,Capture event 3,Capture event 4"
textline " "
bitfld.word 0x00 0. " CONT_ONESHT ,Continuous or one-shot mode control" "Continuous,One-shot"
elif (((d.w(ad:0xFCF79300+0x28))&0x201)==0x01)
group.word 0x28++0x01
line.word 0x00 "ECCTL2,ECAP Control Register 2"
bitfld.word 0x00 9. " CAP_APWM ,CAP/APWM operating mode select" "Capture mode,APWM mode"
textline " "
bitfld.word 0x00 8. " SWSYNC ,Software-forced counter TSCTR synchronizing" "No effect,Forced"
bitfld.word 0x00 6.--7. " SYNCO_SEL ,Sync-Out select" "Pass through,CTR = PRD,Disabled,Disabled"
textline " "
bitfld.word 0x00 5. " SYNCI_EN ,Counter TSCTR Sync-In select mode" "Disabled,Enabled"
bitfld.word 0x00 4. " TSCTRSTOP ,Time stamp TSCTR counter stop control" "Stopped,Free-running"
textline " "
bitfld.word 0x00 3. " REARM ,One-Shot Re-Arming control" "No effect,One-shot sequence"
bitfld.word 0x00 1.--2. " STOP_WRAP ,Stop value for one-shot mode" "Capture event 1,Capture event 2,Capture event 3,Capture event 4"
textline " "
bitfld.word 0x00 0. " CONT_ONESHT ,Continuous or one-shot mode control" "Continuous,One-shot"
else
group.word 0x28++0x01
line.word 0x00 "ECCTL2,ECAP Control Register 2"
bitfld.word 0x00 9. " CAP_APWM ,CAP/APWM operating mode select" "Capture mode,APWM mode"
textline " "
bitfld.word 0x00 8. " SWSYNC ,Software-forced counter TSCTR synchronizing" "No effect,Forced"
bitfld.word 0x00 6.--7. " SYNCO_SEL ,Sync-Out select" "Pass through,CTR = PRD,Disabled,Disabled"
textline " "
bitfld.word 0x00 5. " SYNCI_EN ,Counter TSCTR Sync-In select mode" "Disabled,Enabled"
bitfld.word 0x00 4. " TSCTRSTOP ,Time stamp TSCTR counter stop control" "Stopped,Free-running"
textline " "
bitfld.word 0x00 3. " REARM ,One-Shot Re-Arming control" "No effect,One-shot sequence"
bitfld.word 0x00 1.--2. " STOP_WRAP ,Wrap value for one-shot mode" "Capture event 1,Capture event 2,Capture event 3,Capture event 4"
textline " "
bitfld.word 0x00 0. " CONT_ONESHT ,Continuous or one-shot mode control" "Continuous,One-shot"
endif
group.word 0x2A++0x01
line.word 0x00 "ECCTL1,ECAP Control Regiser 1"
bitfld.word 0x00 14.--15. " FREE/SOFT ,Emulation control" "Stopped immediately,Run until = 0,Run free,Run free"
bitfld.word 0x00 9.--13. " PRESCALE ,Event filter prescale sel" "/1,/2,/4,/6,/8,/10,/12,/14,/16,/18,/20,/22,/24,/26,/28,/30,/32,/34,/36,/38,/40,/42,/44,/46,/48,/50,/52,/54,/56,/58,/60,/62"
textline " "
bitfld.word 0x00 8. " CAPLDEN ,Enable loading of CAP1-4 registers on a capture event" "Disabled,Enabled"
bitfld.word 0x00 7. " CTRRST4 ,Counter reset on capture event 4" "Not reset,Reset"
textline " "
bitfld.word 0x00 6. " CAP4POL ,Capture event 4 polarity select" "RE,FE"
bitfld.word 0x00 5. " CTRRST3 ,Counter reset on capture event 3" "Not reset,Reset"
textline " "
bitfld.word 0x00 4. " CAP3POL ,Capture event 3 polarity select" "RE,FE"
bitfld.word 0x00 3. " CTRRST2 ,Counter reset on capture event 2" "Not reset,Reset"
textline " "
bitfld.word 0x00 2. " CAP2POL ,Capture event 2 polarity select" "RE,FE"
bitfld.word 0x00 1. " CTRRST1 ,Counter reset on capture event 1" "Not reset,Reset"
textline " "
bitfld.word 0x00 0. " CAP1POL ,Capture event 1 polarity select" "RE,FE"
endif
sif cpu()=="RM57L843-ZWT"
group.word 0x2E++0x01
line.word 0x00 "ECFLG,ECAP Interrupt Flag Register"
setclrfld.word 0x00 7. -0x02 7. 0x02 7. " CTR_CMP_SET/CLR ,Compare equal compare status flag" "Not occurred,Occurred"
setclrfld.word 0x00 6. -0x02 6. 0x02 6. " CTR_PRD_SET/CLR ,Counter equal period interrupt enable" "Not occurred,Occurred"
textline " "
setclrfld.word 0x00 5. -0x02 5. 0x02 5. " CTROVF_SET/CLR ,Counter equal period status flag" "Not occurred,Occurred"
setclrfld.word 0x00 4. -0x02 4. 0x02 4. " CEVT4_SET/CLR ,Counter overflow status flag" "Not occurred,Occurred"
textline " "
setclrfld.word 0x00 3. -0x02 3. 0x02 3. " CEVT3_SET/CLR ,Capture event 4 status flag" "Not occurred,Occurred"
setclrfld.word 0x00 2. -0x02 2. 0x02 2. " CEVT2_SET/CLR ,Capture event 2 status flag" "Not occurred,Occurred"
textline " "
setclrfld.word 0x00 1. -0x02 1. 0x02 1. " CEVT1_SET/CLR ,Capture event 1 interrupt enable" "Not occurred,Occurred"
setclrfld.word 0x00 0. -0x02 0. 0x02 0. " INT_SET/CLR ,Global interrupt status flag" "Not generated,Generated"
group.word 0x32++0x01
line.word 0x00 "ECFRC,ECAP Interrupt Forcing Register"
bitfld.word 0x00 7. " CTR_CMP ,Force counter equal compare interrupt" "No effect,Forced"
bitfld.word 0x00 6. " CTR_PRD ,Force counter equal period interrupt" "No effect,Forced"
textline " "
bitfld.word 0x00 5. " CTROVF ,Force counter overflow" "No effect,Forced"
bitfld.word 0x00 4. " CEVT4 ,Force capture event 4" "No effect,Forced"
textline " "
bitfld.word 0x00 3. " CEVT3 ,Force capture event 3" "No effect,Forced"
bitfld.word 0x00 2. " CEVT2 ,Force capture event 2" "No effect,Forced"
textline " "
bitfld.word 0x00 1. " CEVT1 ,Force capture event 1" "No effect,Forced"
else
group.word 0x2C++0x01
line.word 0x00 "ECFLG,ECAP Interrupt Flag Register"
setclrfld.word 0x00 7. 0x02 7. 0x06 7. " CTR_CMP_SET/CLR ,Compare equal compare status flag" "Not occurred,Occurred"
setclrfld.word 0x00 6. 0x02 6. 0x06 6. " CTR_PRD_SET/CLR ,Counter equal period interrupt enable" "Not occurred,Occurred"
textline " "
setclrfld.word 0x00 5. 0x02 5. 0x06 5. " CTROVF_SET/CLR ,Counter equal period status flag" "Not occurred,Occurred"
setclrfld.word 0x00 4. 0x02 4. 0x06 4. " CEVT4_SET/CLR ,Counter overflow status flag" "Not occurred,Occurred"
textline " "
setclrfld.word 0x00 3. 0x02 3. 0x06 3. " CEVT3_SET/CLR ,Capture event 4 status flag" "Not occurred,Occurred"
setclrfld.word 0x00 2. 0x02 2. 0x06 2. " CEVT2_SET/CLR ,Capture event 2 status flag" "Not occurred,Occurred"
textline " "
setclrfld.word 0x00 1. 0x02 1. 0x06 1. " CEVT1_SET/CLR ,Capture event 1 interrupt enable" "Not occurred,Occurred"
setclrfld.word 0x00 0. 0x02 0. 0x06 0. " INT_SET/CLR ,Global interrupt status flag" "Not generated,Generated"
group.word 0x30++0x01
line.word 0x00 "ECFRC,ECAP Interrupt Forcing Register"
bitfld.word 0x00 7. " CTR_CMP ,Force counter equal compare interrupt" "No effect,Forced"
bitfld.word 0x00 6. " CTR_PRD ,Force counter equal period interrupt" "No effect,Forced"
textline " "
bitfld.word 0x00 5. " CTROVF ,Force counter overflow" "No effect,Forced"
bitfld.word 0x00 4. " CEVT4 ,Force capture event 4" "No effect,Forced"
textline " "
bitfld.word 0x00 3. " CEVT3 ,Force capture event 3" "No effect,Forced"
bitfld.word 0x00 2. " CEVT2 ,Force capture event 2" "No effect,Forced"
textline " "
bitfld.word 0x00 1. " CEVT1 ,Force capture event 1" "No effect,Forced"
endif
width 0x0B
tree.end
tree "eCAP 2"
base ad:0xFCF79400
width 11.
group.long 0x00++0x17
line.long 0x00 "TSCTR,Time-Stamp Counter Register"
line.long 0x04 "CTRPHS,Counter Phase Control Register"
line.long 0x08 "CAP1,Capture-1 Register"
line.long 0x0C "CAP2,Capture-2 Register"
line.long 0x10 "CAP3,Capture-3 Register"
line.long 0x14 "CAP4,Capture-4 Register"
sif cpu()=="RM57L843-ZWT"
if (((d.w(ad:0xFCF79400+0x2A))&0x201)==0x200)
group.word 0x2A++0x01
line.word 0x00 "ECCTL2,ECAP Control Register 2"
bitfld.word 0x00 10. " APWMPOL ,APWM output polarity select" "High,Low"
bitfld.word 0x00 9. " CAP_APWM ,CAP/APWM operating mode select" "Capture mode,APWM mode"
textline " "
bitfld.word 0x00 8. " SWSYNC ,Software-forced counter TSCTR synchronizing" "No effect,Forced"
bitfld.word 0x00 6.--7. " SYNCO_SEL ,Sync-Out select" "Pass through,CTR = PRD,Disabled,Disabled"
textline " "
bitfld.word 0x00 5. " SYNCI_EN ,Counter TSCTR Sync-In select mode" "Disabled,Enabled"
bitfld.word 0x00 4. " TSCTRSTOP ,Time stamp TSCTR counter stop control" "Stopped,Free-running"
textline " "
bitfld.word 0x00 3. " REARM ,One-Shot Re-Arming control" "No effect,One-shot sequence"
bitfld.word 0x00 1.--2. " STOP_WRAP ,Wrap value for one-shot mode" "Capture event 1,Capture event 2,Capture event 3,Capture event 4"
textline " "
bitfld.word 0x00 0. " CONT_ONESHT ,Continuous or one-shot mode control" "Continuous,One-shot"
elif (((d.w(ad:0xFCF79400+0x2A))&0x201)==0x201)
group.word 0x2A++0x01
line.word 0x00 "ECCTL2,ECAP Control Register 2"
bitfld.word 0x00 10. " APWMPOL ,APWM output polarity select" "High,Low"
bitfld.word 0x00 9. " CAP_APWM ,CAP/APWM operating mode select" "Capture mode,APWM mode"
textline " "
bitfld.word 0x00 8. " SWSYNC ,Software-forced counter TSCTR synchronizing" "No effect,Forced"
bitfld.word 0x00 6.--7. " SYNCO_SEL ,Sync-Out select" "Pass through,CTR = PRD,Disabled,Disabled"
textline " "
bitfld.word 0x00 5. " SYNCI_EN ,Counter TSCTR Sync-In select mode" "Disabled,Enabled"
bitfld.word 0x00 4. " TSCTRSTOP ,Time stamp TSCTR counter stop control" "Stopped,Free-running"
textline " "
bitfld.word 0x00 3. " REARM ,One-Shot Re-Arming control" "No effect,One-shot sequence"
bitfld.word 0x00 1.--2. " STOP_WRAP ,Stop value for one-shot mode" "Capture event 1,Capture event 2,Capture event 3,Capture event 4"
textline " "
bitfld.word 0x00 0. " CONT_ONESHT ,Continuous or one-shot mode control" "Continuous,One-shot"
elif (((d.w(ad:0xFCF79400+0x2A))&0x201)==0x01)
group.word 0x2A++0x01
line.word 0x00 "ECCTL2,ECAP Control Register 2"
bitfld.word 0x00 9. " CAP_APWM ,CAP/APWM operating mode select" "Capture mode,APWM mode"
textline " "
bitfld.word 0x00 8. " SWSYNC ,Software-forced counter TSCTR synchronizing" "No effect,Forced"
bitfld.word 0x00 6.--7. " SYNCO_SEL ,Sync-Out select" "Pass through,CTR = PRD,Disabled,Disabled"
textline " "
bitfld.word 0x00 5. " SYNCI_EN ,Counter TSCTR Sync-In select mode" "Disabled,Enabled"
bitfld.word 0x00 4. " TSCTRSTOP ,Time stamp TSCTR counter stop control" "Stopped,Free-running"
textline " "
bitfld.word 0x00 3. " REARM ,One-Shot Re-Arming control" "No effect,One-shot sequence"
bitfld.word 0x00 1.--2. " STOP_WRAP ,Stop value for one-shot mode" "Capture event 1,Capture event 2,Capture event 3,Capture event 4"
textline " "
bitfld.word 0x00 0. " CONT_ONESHT ,Continuous or one-shot mode control" "Continuous,One-shot"
else
group.word 0x2A++0x01
line.word 0x00 "ECCTL2,ECAP Control Register 2"
bitfld.word 0x00 9. " CAP_APWM ,CAP/APWM operating mode select" "Capture mode,APWM mode"
textline " "
bitfld.word 0x00 8. " SWSYNC ,Software-forced counter TSCTR synchronizing" "No effect,Forced"
bitfld.word 0x00 6.--7. " SYNCO_SEL ,Sync-Out select" "Pass through,CTR = PRD,Disabled,Disabled"
textline " "
bitfld.word 0x00 5. " SYNCI_EN ,Counter TSCTR Sync-In select mode" "Disabled,Enabled"
bitfld.word 0x00 4. " TSCTRSTOP ,Time stamp TSCTR counter stop control" "Stopped,Free-running"
textline " "
bitfld.word 0x00 3. " REARM ,One-Shot Re-Arming control" "No effect,One-shot sequence"
bitfld.word 0x00 1.--2. " STOP_WRAP ,Wrap value for one-shot mode" "Capture event 1,Capture event 2,Capture event 3,Capture event 4"
textline " "
bitfld.word 0x00 0. " CONT_ONESHT ,Continuous or one-shot mode control" "Continuous,One-shot"
endif
group.word 0x28++0x01
line.word 0x00 "ECCTL1,ECAP Control Regiser 1"
bitfld.word 0x00 14.--15. " FREE/SOFT ,Emulation control" "Stopped immediately,Run until = 0,Run free,Run free"
bitfld.word 0x00 9.--13. " PRESCALE ,Event filter prescale sel" "/1,/2,/4,/6,/8,/10,/12,/14,/16,/18,/20,/22,/24,/26,/28,/30,/32,/34,/36,/38,/40,/42,/44,/46,/48,/50,/52,/54,/56,/58,/60,/62"
textline " "
bitfld.word 0x00 8. " CAPLDEN ,Enable loading of CAP1-4 registers on a capture event" "Disabled,Enabled"
bitfld.word 0x00 7. " CTRRST4 ,Counter reset on capture event 4" "Not reset,Reset"
textline " "
bitfld.word 0x00 6. " CAP4POL ,Capture event 4 polarity select" "RE,FE"
bitfld.word 0x00 5. " CTRRST3 ,Counter reset on capture event 3" "Not reset,Reset"
textline " "
bitfld.word 0x00 4. " CAP3POL ,Capture event 3 polarity select" "RE,FE"
bitfld.word 0x00 3. " CTRRST2 ,Counter reset on capture event 2" "Not reset,Reset"
textline " "
bitfld.word 0x00 2. " CAP2POL ,Capture event 2 polarity select" "RE,FE"
bitfld.word 0x00 1. " CTRRST1 ,Counter reset on capture event 1" "Not reset,Reset"
textline " "
bitfld.word 0x00 0. " CAP1POL ,Capture event 1 polarity select" "RE,FE"
else
if (((d.w(ad:0xFCF79400+0x28))&0x201)==0x200)
group.word 0x28++0x01
line.word 0x00 "ECCTL2,ECAP Control Register 2"
bitfld.word 0x00 10. " APWMPOL ,APWM output polarity select" "High,Low"
bitfld.word 0x00 9. " CAP_APWM ,CAP/APWM operating mode select" "Capture mode,APWM mode"
textline " "
bitfld.word 0x00 8. " SWSYNC ,Software-forced counter TSCTR synchronizing" "No effect,Forced"
bitfld.word 0x00 6.--7. " SYNCO_SEL ,Sync-Out select" "Pass through,CTR = PRD,Disabled,Disabled"
textline " "
bitfld.word 0x00 5. " SYNCI_EN ,Counter TSCTR Sync-In select mode" "Disabled,Enabled"
bitfld.word 0x00 4. " TSCTRSTOP ,Time stamp TSCTR counter stop control" "Stopped,Free-running"
textline " "
bitfld.word 0x00 3. " REARM ,One-Shot Re-Arming control" "No effect,One-shot sequence"
bitfld.word 0x00 1.--2. " STOP_WRAP ,Wrap value for one-shot mode" "Capture event 1,Capture event 2,Capture event 3,Capture event 4"
textline " "
bitfld.word 0x00 0. " CONT_ONESHT ,Continuous or one-shot mode control" "Continuous,One-shot"
elif (((d.w(ad:0xFCF79400+0x28))&0x201)==0x201)
group.word 0x28++0x01
line.word 0x00 "ECCTL2,ECAP Control Register 2"
bitfld.word 0x00 10. " APWMPOL ,APWM output polarity select" "High,Low"
bitfld.word 0x00 9. " CAP_APWM ,CAP/APWM operating mode select" "Capture mode,APWM mode"
textline " "
bitfld.word 0x00 8. " SWSYNC ,Software-forced counter TSCTR synchronizing" "No effect,Forced"
bitfld.word 0x00 6.--7. " SYNCO_SEL ,Sync-Out select" "Pass through,CTR = PRD,Disabled,Disabled"
textline " "
bitfld.word 0x00 5. " SYNCI_EN ,Counter TSCTR Sync-In select mode" "Disabled,Enabled"
bitfld.word 0x00 4. " TSCTRSTOP ,Time stamp TSCTR counter stop control" "Stopped,Free-running"
textline " "
bitfld.word 0x00 3. " REARM ,One-Shot Re-Arming control" "No effect,One-shot sequence"
bitfld.word 0x00 1.--2. " STOP_WRAP ,Stop value for one-shot mode" "Capture event 1,Capture event 2,Capture event 3,Capture event 4"
textline " "
bitfld.word 0x00 0. " CONT_ONESHT ,Continuous or one-shot mode control" "Continuous,One-shot"
elif (((d.w(ad:0xFCF79400+0x28))&0x201)==0x01)
group.word 0x28++0x01
line.word 0x00 "ECCTL2,ECAP Control Register 2"
bitfld.word 0x00 9. " CAP_APWM ,CAP/APWM operating mode select" "Capture mode,APWM mode"
textline " "
bitfld.word 0x00 8. " SWSYNC ,Software-forced counter TSCTR synchronizing" "No effect,Forced"
bitfld.word 0x00 6.--7. " SYNCO_SEL ,Sync-Out select" "Pass through,CTR = PRD,Disabled,Disabled"
textline " "
bitfld.word 0x00 5. " SYNCI_EN ,Counter TSCTR Sync-In select mode" "Disabled,Enabled"
bitfld.word 0x00 4. " TSCTRSTOP ,Time stamp TSCTR counter stop control" "Stopped,Free-running"
textline " "
bitfld.word 0x00 3. " REARM ,One-Shot Re-Arming control" "No effect,One-shot sequence"
bitfld.word 0x00 1.--2. " STOP_WRAP ,Stop value for one-shot mode" "Capture event 1,Capture event 2,Capture event 3,Capture event 4"
textline " "
bitfld.word 0x00 0. " CONT_ONESHT ,Continuous or one-shot mode control" "Continuous,One-shot"
else
group.word 0x28++0x01
line.word 0x00 "ECCTL2,ECAP Control Register 2"
bitfld.word 0x00 9. " CAP_APWM ,CAP/APWM operating mode select" "Capture mode,APWM mode"
textline " "
bitfld.word 0x00 8. " SWSYNC ,Software-forced counter TSCTR synchronizing" "No effect,Forced"
bitfld.word 0x00 6.--7. " SYNCO_SEL ,Sync-Out select" "Pass through,CTR = PRD,Disabled,Disabled"
textline " "
bitfld.word 0x00 5. " SYNCI_EN ,Counter TSCTR Sync-In select mode" "Disabled,Enabled"
bitfld.word 0x00 4. " TSCTRSTOP ,Time stamp TSCTR counter stop control" "Stopped,Free-running"
textline " "
bitfld.word 0x00 3. " REARM ,One-Shot Re-Arming control" "No effect,One-shot sequence"
bitfld.word 0x00 1.--2. " STOP_WRAP ,Wrap value for one-shot mode" "Capture event 1,Capture event 2,Capture event 3,Capture event 4"
textline " "
bitfld.word 0x00 0. " CONT_ONESHT ,Continuous or one-shot mode control" "Continuous,One-shot"
endif
group.word 0x2A++0x01
line.word 0x00 "ECCTL1,ECAP Control Regiser 1"
bitfld.word 0x00 14.--15. " FREE/SOFT ,Emulation control" "Stopped immediately,Run until = 0,Run free,Run free"
bitfld.word 0x00 9.--13. " PRESCALE ,Event filter prescale sel" "/1,/2,/4,/6,/8,/10,/12,/14,/16,/18,/20,/22,/24,/26,/28,/30,/32,/34,/36,/38,/40,/42,/44,/46,/48,/50,/52,/54,/56,/58,/60,/62"
textline " "
bitfld.word 0x00 8. " CAPLDEN ,Enable loading of CAP1-4 registers on a capture event" "Disabled,Enabled"
bitfld.word 0x00 7. " CTRRST4 ,Counter reset on capture event 4" "Not reset,Reset"
textline " "
bitfld.word 0x00 6. " CAP4POL ,Capture event 4 polarity select" "RE,FE"
bitfld.word 0x00 5. " CTRRST3 ,Counter reset on capture event 3" "Not reset,Reset"
textline " "
bitfld.word 0x00 4. " CAP3POL ,Capture event 3 polarity select" "RE,FE"
bitfld.word 0x00 3. " CTRRST2 ,Counter reset on capture event 2" "Not reset,Reset"
textline " "
bitfld.word 0x00 2. " CAP2POL ,Capture event 2 polarity select" "RE,FE"
bitfld.word 0x00 1. " CTRRST1 ,Counter reset on capture event 1" "Not reset,Reset"
textline " "
bitfld.word 0x00 0. " CAP1POL ,Capture event 1 polarity select" "RE,FE"
endif
sif cpu()=="RM57L843-ZWT"
group.word 0x2E++0x01
line.word 0x00 "ECFLG,ECAP Interrupt Flag Register"
setclrfld.word 0x00 7. -0x02 7. 0x02 7. " CTR_CMP_SET/CLR ,Compare equal compare status flag" "Not occurred,Occurred"
setclrfld.word 0x00 6. -0x02 6. 0x02 6. " CTR_PRD_SET/CLR ,Counter equal period interrupt enable" "Not occurred,Occurred"
textline " "
setclrfld.word 0x00 5. -0x02 5. 0x02 5. " CTROVF_SET/CLR ,Counter equal period status flag" "Not occurred,Occurred"
setclrfld.word 0x00 4. -0x02 4. 0x02 4. " CEVT4_SET/CLR ,Counter overflow status flag" "Not occurred,Occurred"
textline " "
setclrfld.word 0x00 3. -0x02 3. 0x02 3. " CEVT3_SET/CLR ,Capture event 4 status flag" "Not occurred,Occurred"
setclrfld.word 0x00 2. -0x02 2. 0x02 2. " CEVT2_SET/CLR ,Capture event 2 status flag" "Not occurred,Occurred"
textline " "
setclrfld.word 0x00 1. -0x02 1. 0x02 1. " CEVT1_SET/CLR ,Capture event 1 interrupt enable" "Not occurred,Occurred"
setclrfld.word 0x00 0. -0x02 0. 0x02 0. " INT_SET/CLR ,Global interrupt status flag" "Not generated,Generated"
group.word 0x32++0x01
line.word 0x00 "ECFRC,ECAP Interrupt Forcing Register"
bitfld.word 0x00 7. " CTR_CMP ,Force counter equal compare interrupt" "No effect,Forced"
bitfld.word 0x00 6. " CTR_PRD ,Force counter equal period interrupt" "No effect,Forced"
textline " "
bitfld.word 0x00 5. " CTROVF ,Force counter overflow" "No effect,Forced"
bitfld.word 0x00 4. " CEVT4 ,Force capture event 4" "No effect,Forced"
textline " "
bitfld.word 0x00 3. " CEVT3 ,Force capture event 3" "No effect,Forced"
bitfld.word 0x00 2. " CEVT2 ,Force capture event 2" "No effect,Forced"
textline " "
bitfld.word 0x00 1. " CEVT1 ,Force capture event 1" "No effect,Forced"
else
group.word 0x2C++0x01
line.word 0x00 "ECFLG,ECAP Interrupt Flag Register"
setclrfld.word 0x00 7. 0x02 7. 0x06 7. " CTR_CMP_SET/CLR ,Compare equal compare status flag" "Not occurred,Occurred"
setclrfld.word 0x00 6. 0x02 6. 0x06 6. " CTR_PRD_SET/CLR ,Counter equal period interrupt enable" "Not occurred,Occurred"
textline " "
setclrfld.word 0x00 5. 0x02 5. 0x06 5. " CTROVF_SET/CLR ,Counter equal period status flag" "Not occurred,Occurred"
setclrfld.word 0x00 4. 0x02 4. 0x06 4. " CEVT4_SET/CLR ,Counter overflow status flag" "Not occurred,Occurred"
textline " "
setclrfld.word 0x00 3. 0x02 3. 0x06 3. " CEVT3_SET/CLR ,Capture event 4 status flag" "Not occurred,Occurred"
setclrfld.word 0x00 2. 0x02 2. 0x06 2. " CEVT2_SET/CLR ,Capture event 2 status flag" "Not occurred,Occurred"
textline " "
setclrfld.word 0x00 1. 0x02 1. 0x06 1. " CEVT1_SET/CLR ,Capture event 1 interrupt enable" "Not occurred,Occurred"
setclrfld.word 0x00 0. 0x02 0. 0x06 0. " INT_SET/CLR ,Global interrupt status flag" "Not generated,Generated"
group.word 0x30++0x01
line.word 0x00 "ECFRC,ECAP Interrupt Forcing Register"
bitfld.word 0x00 7. " CTR_CMP ,Force counter equal compare interrupt" "No effect,Forced"
bitfld.word 0x00 6. " CTR_PRD ,Force counter equal period interrupt" "No effect,Forced"
textline " "
bitfld.word 0x00 5. " CTROVF ,Force counter overflow" "No effect,Forced"
bitfld.word 0x00 4. " CEVT4 ,Force capture event 4" "No effect,Forced"
textline " "
bitfld.word 0x00 3. " CEVT3 ,Force capture event 3" "No effect,Forced"
bitfld.word 0x00 2. " CEVT2 ,Force capture event 2" "No effect,Forced"
textline " "
bitfld.word 0x00 1. " CEVT1 ,Force capture event 1" "No effect,Forced"
endif
width 0x0B
tree.end
tree "eCAP 3"
base ad:0xFCF79500
width 11.
group.long 0x00++0x17
line.long 0x00 "TSCTR,Time-Stamp Counter Register"
line.long 0x04 "CTRPHS,Counter Phase Control Register"
line.long 0x08 "CAP1,Capture-1 Register"
line.long 0x0C "CAP2,Capture-2 Register"
line.long 0x10 "CAP3,Capture-3 Register"
line.long 0x14 "CAP4,Capture-4 Register"
sif cpu()=="RM57L843-ZWT"
if (((d.w(ad:0xFCF79500+0x2A))&0x201)==0x200)
group.word 0x2A++0x01
line.word 0x00 "ECCTL2,ECAP Control Register 2"
bitfld.word 0x00 10. " APWMPOL ,APWM output polarity select" "High,Low"
bitfld.word 0x00 9. " CAP_APWM ,CAP/APWM operating mode select" "Capture mode,APWM mode"
textline " "
bitfld.word 0x00 8. " SWSYNC ,Software-forced counter TSCTR synchronizing" "No effect,Forced"
bitfld.word 0x00 6.--7. " SYNCO_SEL ,Sync-Out select" "Pass through,CTR = PRD,Disabled,Disabled"
textline " "
bitfld.word 0x00 5. " SYNCI_EN ,Counter TSCTR Sync-In select mode" "Disabled,Enabled"
bitfld.word 0x00 4. " TSCTRSTOP ,Time stamp TSCTR counter stop control" "Stopped,Free-running"
textline " "
bitfld.word 0x00 3. " REARM ,One-Shot Re-Arming control" "No effect,One-shot sequence"
bitfld.word 0x00 1.--2. " STOP_WRAP ,Wrap value for one-shot mode" "Capture event 1,Capture event 2,Capture event 3,Capture event 4"
textline " "
bitfld.word 0x00 0. " CONT_ONESHT ,Continuous or one-shot mode control" "Continuous,One-shot"
elif (((d.w(ad:0xFCF79500+0x2A))&0x201)==0x201)
group.word 0x2A++0x01
line.word 0x00 "ECCTL2,ECAP Control Register 2"
bitfld.word 0x00 10. " APWMPOL ,APWM output polarity select" "High,Low"
bitfld.word 0x00 9. " CAP_APWM ,CAP/APWM operating mode select" "Capture mode,APWM mode"
textline " "
bitfld.word 0x00 8. " SWSYNC ,Software-forced counter TSCTR synchronizing" "No effect,Forced"
bitfld.word 0x00 6.--7. " SYNCO_SEL ,Sync-Out select" "Pass through,CTR = PRD,Disabled,Disabled"
textline " "
bitfld.word 0x00 5. " SYNCI_EN ,Counter TSCTR Sync-In select mode" "Disabled,Enabled"
bitfld.word 0x00 4. " TSCTRSTOP ,Time stamp TSCTR counter stop control" "Stopped,Free-running"
textline " "
bitfld.word 0x00 3. " REARM ,One-Shot Re-Arming control" "No effect,One-shot sequence"
bitfld.word 0x00 1.--2. " STOP_WRAP ,Stop value for one-shot mode" "Capture event 1,Capture event 2,Capture event 3,Capture event 4"
textline " "
bitfld.word 0x00 0. " CONT_ONESHT ,Continuous or one-shot mode control" "Continuous,One-shot"
elif (((d.w(ad:0xFCF79500+0x2A))&0x201)==0x01)
group.word 0x2A++0x01
line.word 0x00 "ECCTL2,ECAP Control Register 2"
bitfld.word 0x00 9. " CAP_APWM ,CAP/APWM operating mode select" "Capture mode,APWM mode"
textline " "
bitfld.word 0x00 8. " SWSYNC ,Software-forced counter TSCTR synchronizing" "No effect,Forced"
bitfld.word 0x00 6.--7. " SYNCO_SEL ,Sync-Out select" "Pass through,CTR = PRD,Disabled,Disabled"
textline " "
bitfld.word 0x00 5. " SYNCI_EN ,Counter TSCTR Sync-In select mode" "Disabled,Enabled"
bitfld.word 0x00 4. " TSCTRSTOP ,Time stamp TSCTR counter stop control" "Stopped,Free-running"
textline " "
bitfld.word 0x00 3. " REARM ,One-Shot Re-Arming control" "No effect,One-shot sequence"
bitfld.word 0x00 1.--2. " STOP_WRAP ,Stop value for one-shot mode" "Capture event 1,Capture event 2,Capture event 3,Capture event 4"
textline " "
bitfld.word 0x00 0. " CONT_ONESHT ,Continuous or one-shot mode control" "Continuous,One-shot"
else
group.word 0x2A++0x01
line.word 0x00 "ECCTL2,ECAP Control Register 2"
bitfld.word 0x00 9. " CAP_APWM ,CAP/APWM operating mode select" "Capture mode,APWM mode"
textline " "
bitfld.word 0x00 8. " SWSYNC ,Software-forced counter TSCTR synchronizing" "No effect,Forced"
bitfld.word 0x00 6.--7. " SYNCO_SEL ,Sync-Out select" "Pass through,CTR = PRD,Disabled,Disabled"
textline " "
bitfld.word 0x00 5. " SYNCI_EN ,Counter TSCTR Sync-In select mode" "Disabled,Enabled"
bitfld.word 0x00 4. " TSCTRSTOP ,Time stamp TSCTR counter stop control" "Stopped,Free-running"
textline " "
bitfld.word 0x00 3. " REARM ,One-Shot Re-Arming control" "No effect,One-shot sequence"
bitfld.word 0x00 1.--2. " STOP_WRAP ,Wrap value for one-shot mode" "Capture event 1,Capture event 2,Capture event 3,Capture event 4"
textline " "
bitfld.word 0x00 0. " CONT_ONESHT ,Continuous or one-shot mode control" "Continuous,One-shot"
endif
group.word 0x28++0x01
line.word 0x00 "ECCTL1,ECAP Control Regiser 1"
bitfld.word 0x00 14.--15. " FREE/SOFT ,Emulation control" "Stopped immediately,Run until = 0,Run free,Run free"
bitfld.word 0x00 9.--13. " PRESCALE ,Event filter prescale sel" "/1,/2,/4,/6,/8,/10,/12,/14,/16,/18,/20,/22,/24,/26,/28,/30,/32,/34,/36,/38,/40,/42,/44,/46,/48,/50,/52,/54,/56,/58,/60,/62"
textline " "
bitfld.word 0x00 8. " CAPLDEN ,Enable loading of CAP1-4 registers on a capture event" "Disabled,Enabled"
bitfld.word 0x00 7. " CTRRST4 ,Counter reset on capture event 4" "Not reset,Reset"
textline " "
bitfld.word 0x00 6. " CAP4POL ,Capture event 4 polarity select" "RE,FE"
bitfld.word 0x00 5. " CTRRST3 ,Counter reset on capture event 3" "Not reset,Reset"
textline " "
bitfld.word 0x00 4. " CAP3POL ,Capture event 3 polarity select" "RE,FE"
bitfld.word 0x00 3. " CTRRST2 ,Counter reset on capture event 2" "Not reset,Reset"
textline " "
bitfld.word 0x00 2. " CAP2POL ,Capture event 2 polarity select" "RE,FE"
bitfld.word 0x00 1. " CTRRST1 ,Counter reset on capture event 1" "Not reset,Reset"
textline " "
bitfld.word 0x00 0. " CAP1POL ,Capture event 1 polarity select" "RE,FE"
else
if (((d.w(ad:0xFCF79500+0x28))&0x201)==0x200)
group.word 0x28++0x01
line.word 0x00 "ECCTL2,ECAP Control Register 2"
bitfld.word 0x00 10. " APWMPOL ,APWM output polarity select" "High,Low"
bitfld.word 0x00 9. " CAP_APWM ,CAP/APWM operating mode select" "Capture mode,APWM mode"
textline " "
bitfld.word 0x00 8. " SWSYNC ,Software-forced counter TSCTR synchronizing" "No effect,Forced"
bitfld.word 0x00 6.--7. " SYNCO_SEL ,Sync-Out select" "Pass through,CTR = PRD,Disabled,Disabled"
textline " "
bitfld.word 0x00 5. " SYNCI_EN ,Counter TSCTR Sync-In select mode" "Disabled,Enabled"
bitfld.word 0x00 4. " TSCTRSTOP ,Time stamp TSCTR counter stop control" "Stopped,Free-running"
textline " "
bitfld.word 0x00 3. " REARM ,One-Shot Re-Arming control" "No effect,One-shot sequence"
bitfld.word 0x00 1.--2. " STOP_WRAP ,Wrap value for one-shot mode" "Capture event 1,Capture event 2,Capture event 3,Capture event 4"
textline " "
bitfld.word 0x00 0. " CONT_ONESHT ,Continuous or one-shot mode control" "Continuous,One-shot"
elif (((d.w(ad:0xFCF79500+0x28))&0x201)==0x201)
group.word 0x28++0x01
line.word 0x00 "ECCTL2,ECAP Control Register 2"
bitfld.word 0x00 10. " APWMPOL ,APWM output polarity select" "High,Low"
bitfld.word 0x00 9. " CAP_APWM ,CAP/APWM operating mode select" "Capture mode,APWM mode"
textline " "
bitfld.word 0x00 8. " SWSYNC ,Software-forced counter TSCTR synchronizing" "No effect,Forced"
bitfld.word 0x00 6.--7. " SYNCO_SEL ,Sync-Out select" "Pass through,CTR = PRD,Disabled,Disabled"
textline " "
bitfld.word 0x00 5. " SYNCI_EN ,Counter TSCTR Sync-In select mode" "Disabled,Enabled"
bitfld.word 0x00 4. " TSCTRSTOP ,Time stamp TSCTR counter stop control" "Stopped,Free-running"
textline " "
bitfld.word 0x00 3. " REARM ,One-Shot Re-Arming control" "No effect,One-shot sequence"
bitfld.word 0x00 1.--2. " STOP_WRAP ,Stop value for one-shot mode" "Capture event 1,Capture event 2,Capture event 3,Capture event 4"
textline " "
bitfld.word 0x00 0. " CONT_ONESHT ,Continuous or one-shot mode control" "Continuous,One-shot"
elif (((d.w(ad:0xFCF79500+0x28))&0x201)==0x01)
group.word 0x28++0x01
line.word 0x00 "ECCTL2,ECAP Control Register 2"
bitfld.word 0x00 9. " CAP_APWM ,CAP/APWM operating mode select" "Capture mode,APWM mode"
textline " "
bitfld.word 0x00 8. " SWSYNC ,Software-forced counter TSCTR synchronizing" "No effect,Forced"
bitfld.word 0x00 6.--7. " SYNCO_SEL ,Sync-Out select" "Pass through,CTR = PRD,Disabled,Disabled"
textline " "
bitfld.word 0x00 5. " SYNCI_EN ,Counter TSCTR Sync-In select mode" "Disabled,Enabled"
bitfld.word 0x00 4. " TSCTRSTOP ,Time stamp TSCTR counter stop control" "Stopped,Free-running"
textline " "
bitfld.word 0x00 3. " REARM ,One-Shot Re-Arming control" "No effect,One-shot sequence"
bitfld.word 0x00 1.--2. " STOP_WRAP ,Stop value for one-shot mode" "Capture event 1,Capture event 2,Capture event 3,Capture event 4"
textline " "
bitfld.word 0x00 0. " CONT_ONESHT ,Continuous or one-shot mode control" "Continuous,One-shot"
else
group.word 0x28++0x01
line.word 0x00 "ECCTL2,ECAP Control Register 2"
bitfld.word 0x00 9. " CAP_APWM ,CAP/APWM operating mode select" "Capture mode,APWM mode"
textline " "
bitfld.word 0x00 8. " SWSYNC ,Software-forced counter TSCTR synchronizing" "No effect,Forced"
bitfld.word 0x00 6.--7. " SYNCO_SEL ,Sync-Out select" "Pass through,CTR = PRD,Disabled,Disabled"
textline " "
bitfld.word 0x00 5. " SYNCI_EN ,Counter TSCTR Sync-In select mode" "Disabled,Enabled"
bitfld.word 0x00 4. " TSCTRSTOP ,Time stamp TSCTR counter stop control" "Stopped,Free-running"
textline " "
bitfld.word 0x00 3. " REARM ,One-Shot Re-Arming control" "No effect,One-shot sequence"
bitfld.word 0x00 1.--2. " STOP_WRAP ,Wrap value for one-shot mode" "Capture event 1,Capture event 2,Capture event 3,Capture event 4"
textline " "
bitfld.word 0x00 0. " CONT_ONESHT ,Continuous or one-shot mode control" "Continuous,One-shot"
endif
group.word 0x2A++0x01
line.word 0x00 "ECCTL1,ECAP Control Regiser 1"
bitfld.word 0x00 14.--15. " FREE/SOFT ,Emulation control" "Stopped immediately,Run until = 0,Run free,Run free"
bitfld.word 0x00 9.--13. " PRESCALE ,Event filter prescale sel" "/1,/2,/4,/6,/8,/10,/12,/14,/16,/18,/20,/22,/24,/26,/28,/30,/32,/34,/36,/38,/40,/42,/44,/46,/48,/50,/52,/54,/56,/58,/60,/62"
textline " "
bitfld.word 0x00 8. " CAPLDEN ,Enable loading of CAP1-4 registers on a capture event" "Disabled,Enabled"
bitfld.word 0x00 7. " CTRRST4 ,Counter reset on capture event 4" "Not reset,Reset"
textline " "
bitfld.word 0x00 6. " CAP4POL ,Capture event 4 polarity select" "RE,FE"
bitfld.word 0x00 5. " CTRRST3 ,Counter reset on capture event 3" "Not reset,Reset"
textline " "
bitfld.word 0x00 4. " CAP3POL ,Capture event 3 polarity select" "RE,FE"
bitfld.word 0x00 3. " CTRRST2 ,Counter reset on capture event 2" "Not reset,Reset"
textline " "
bitfld.word 0x00 2. " CAP2POL ,Capture event 2 polarity select" "RE,FE"
bitfld.word 0x00 1. " CTRRST1 ,Counter reset on capture event 1" "Not reset,Reset"
textline " "
bitfld.word 0x00 0. " CAP1POL ,Capture event 1 polarity select" "RE,FE"
endif
sif cpu()=="RM57L843-ZWT"
group.word 0x2E++0x01
line.word 0x00 "ECFLG,ECAP Interrupt Flag Register"
setclrfld.word 0x00 7. -0x02 7. 0x02 7. " CTR_CMP_SET/CLR ,Compare equal compare status flag" "Not occurred,Occurred"
setclrfld.word 0x00 6. -0x02 6. 0x02 6. " CTR_PRD_SET/CLR ,Counter equal period interrupt enable" "Not occurred,Occurred"
textline " "
setclrfld.word 0x00 5. -0x02 5. 0x02 5. " CTROVF_SET/CLR ,Counter equal period status flag" "Not occurred,Occurred"
setclrfld.word 0x00 4. -0x02 4. 0x02 4. " CEVT4_SET/CLR ,Counter overflow status flag" "Not occurred,Occurred"
textline " "
setclrfld.word 0x00 3. -0x02 3. 0x02 3. " CEVT3_SET/CLR ,Capture event 4 status flag" "Not occurred,Occurred"
setclrfld.word 0x00 2. -0x02 2. 0x02 2. " CEVT2_SET/CLR ,Capture event 2 status flag" "Not occurred,Occurred"
textline " "
setclrfld.word 0x00 1. -0x02 1. 0x02 1. " CEVT1_SET/CLR ,Capture event 1 interrupt enable" "Not occurred,Occurred"
setclrfld.word 0x00 0. -0x02 0. 0x02 0. " INT_SET/CLR ,Global interrupt status flag" "Not generated,Generated"
group.word 0x32++0x01
line.word 0x00 "ECFRC,ECAP Interrupt Forcing Register"
bitfld.word 0x00 7. " CTR_CMP ,Force counter equal compare interrupt" "No effect,Forced"
bitfld.word 0x00 6. " CTR_PRD ,Force counter equal period interrupt" "No effect,Forced"
textline " "
bitfld.word 0x00 5. " CTROVF ,Force counter overflow" "No effect,Forced"
bitfld.word 0x00 4. " CEVT4 ,Force capture event 4" "No effect,Forced"
textline " "
bitfld.word 0x00 3. " CEVT3 ,Force capture event 3" "No effect,Forced"
bitfld.word 0x00 2. " CEVT2 ,Force capture event 2" "No effect,Forced"
textline " "
bitfld.word 0x00 1. " CEVT1 ,Force capture event 1" "No effect,Forced"
else
group.word 0x2C++0x01
line.word 0x00 "ECFLG,ECAP Interrupt Flag Register"
setclrfld.word 0x00 7. 0x02 7. 0x06 7. " CTR_CMP_SET/CLR ,Compare equal compare status flag" "Not occurred,Occurred"
setclrfld.word 0x00 6. 0x02 6. 0x06 6. " CTR_PRD_SET/CLR ,Counter equal period interrupt enable" "Not occurred,Occurred"
textline " "
setclrfld.word 0x00 5. 0x02 5. 0x06 5. " CTROVF_SET/CLR ,Counter equal period status flag" "Not occurred,Occurred"
setclrfld.word 0x00 4. 0x02 4. 0x06 4. " CEVT4_SET/CLR ,Counter overflow status flag" "Not occurred,Occurred"
textline " "
setclrfld.word 0x00 3. 0x02 3. 0x06 3. " CEVT3_SET/CLR ,Capture event 4 status flag" "Not occurred,Occurred"
setclrfld.word 0x00 2. 0x02 2. 0x06 2. " CEVT2_SET/CLR ,Capture event 2 status flag" "Not occurred,Occurred"
textline " "
setclrfld.word 0x00 1. 0x02 1. 0x06 1. " CEVT1_SET/CLR ,Capture event 1 interrupt enable" "Not occurred,Occurred"
setclrfld.word 0x00 0. 0x02 0. 0x06 0. " INT_SET/CLR ,Global interrupt status flag" "Not generated,Generated"
group.word 0x30++0x01
line.word 0x00 "ECFRC,ECAP Interrupt Forcing Register"
bitfld.word 0x00 7. " CTR_CMP ,Force counter equal compare interrupt" "No effect,Forced"
bitfld.word 0x00 6. " CTR_PRD ,Force counter equal period interrupt" "No effect,Forced"
textline " "
bitfld.word 0x00 5. " CTROVF ,Force counter overflow" "No effect,Forced"
bitfld.word 0x00 4. " CEVT4 ,Force capture event 4" "No effect,Forced"
textline " "
bitfld.word 0x00 3. " CEVT3 ,Force capture event 3" "No effect,Forced"
bitfld.word 0x00 2. " CEVT2 ,Force capture event 2" "No effect,Forced"
textline " "
bitfld.word 0x00 1. " CEVT1 ,Force capture event 1" "No effect,Forced"
endif
width 0x0B
tree.end
tree "eCAP 4"
base ad:0xFCF79600
width 11.
group.long 0x00++0x17
line.long 0x00 "TSCTR,Time-Stamp Counter Register"
line.long 0x04 "CTRPHS,Counter Phase Control Register"
line.long 0x08 "CAP1,Capture-1 Register"
line.long 0x0C "CAP2,Capture-2 Register"
line.long 0x10 "CAP3,Capture-3 Register"
line.long 0x14 "CAP4,Capture-4 Register"
sif cpu()=="RM57L843-ZWT"
if (((d.w(ad:0xFCF79600+0x2A))&0x201)==0x200)
group.word 0x2A++0x01
line.word 0x00 "ECCTL2,ECAP Control Register 2"
bitfld.word 0x00 10. " APWMPOL ,APWM output polarity select" "High,Low"
bitfld.word 0x00 9. " CAP_APWM ,CAP/APWM operating mode select" "Capture mode,APWM mode"
textline " "
bitfld.word 0x00 8. " SWSYNC ,Software-forced counter TSCTR synchronizing" "No effect,Forced"
bitfld.word 0x00 6.--7. " SYNCO_SEL ,Sync-Out select" "Pass through,CTR = PRD,Disabled,Disabled"
textline " "
bitfld.word 0x00 5. " SYNCI_EN ,Counter TSCTR Sync-In select mode" "Disabled,Enabled"
bitfld.word 0x00 4. " TSCTRSTOP ,Time stamp TSCTR counter stop control" "Stopped,Free-running"
textline " "
bitfld.word 0x00 3. " REARM ,One-Shot Re-Arming control" "No effect,One-shot sequence"
bitfld.word 0x00 1.--2. " STOP_WRAP ,Wrap value for one-shot mode" "Capture event 1,Capture event 2,Capture event 3,Capture event 4"
textline " "
bitfld.word 0x00 0. " CONT_ONESHT ,Continuous or one-shot mode control" "Continuous,One-shot"
elif (((d.w(ad:0xFCF79600+0x2A))&0x201)==0x201)
group.word 0x2A++0x01
line.word 0x00 "ECCTL2,ECAP Control Register 2"
bitfld.word 0x00 10. " APWMPOL ,APWM output polarity select" "High,Low"
bitfld.word 0x00 9. " CAP_APWM ,CAP/APWM operating mode select" "Capture mode,APWM mode"
textline " "
bitfld.word 0x00 8. " SWSYNC ,Software-forced counter TSCTR synchronizing" "No effect,Forced"
bitfld.word 0x00 6.--7. " SYNCO_SEL ,Sync-Out select" "Pass through,CTR = PRD,Disabled,Disabled"
textline " "
bitfld.word 0x00 5. " SYNCI_EN ,Counter TSCTR Sync-In select mode" "Disabled,Enabled"
bitfld.word 0x00 4. " TSCTRSTOP ,Time stamp TSCTR counter stop control" "Stopped,Free-running"
textline " "
bitfld.word 0x00 3. " REARM ,One-Shot Re-Arming control" "No effect,One-shot sequence"
bitfld.word 0x00 1.--2. " STOP_WRAP ,Stop value for one-shot mode" "Capture event 1,Capture event 2,Capture event 3,Capture event 4"
textline " "
bitfld.word 0x00 0. " CONT_ONESHT ,Continuous or one-shot mode control" "Continuous,One-shot"
elif (((d.w(ad:0xFCF79600+0x2A))&0x201)==0x01)
group.word 0x2A++0x01
line.word 0x00 "ECCTL2,ECAP Control Register 2"
bitfld.word 0x00 9. " CAP_APWM ,CAP/APWM operating mode select" "Capture mode,APWM mode"
textline " "
bitfld.word 0x00 8. " SWSYNC ,Software-forced counter TSCTR synchronizing" "No effect,Forced"
bitfld.word 0x00 6.--7. " SYNCO_SEL ,Sync-Out select" "Pass through,CTR = PRD,Disabled,Disabled"
textline " "
bitfld.word 0x00 5. " SYNCI_EN ,Counter TSCTR Sync-In select mode" "Disabled,Enabled"
bitfld.word 0x00 4. " TSCTRSTOP ,Time stamp TSCTR counter stop control" "Stopped,Free-running"
textline " "
bitfld.word 0x00 3. " REARM ,One-Shot Re-Arming control" "No effect,One-shot sequence"
bitfld.word 0x00 1.--2. " STOP_WRAP ,Stop value for one-shot mode" "Capture event 1,Capture event 2,Capture event 3,Capture event 4"
textline " "
bitfld.word 0x00 0. " CONT_ONESHT ,Continuous or one-shot mode control" "Continuous,One-shot"
else
group.word 0x2A++0x01
line.word 0x00 "ECCTL2,ECAP Control Register 2"
bitfld.word 0x00 9. " CAP_APWM ,CAP/APWM operating mode select" "Capture mode,APWM mode"
textline " "
bitfld.word 0x00 8. " SWSYNC ,Software-forced counter TSCTR synchronizing" "No effect,Forced"
bitfld.word 0x00 6.--7. " SYNCO_SEL ,Sync-Out select" "Pass through,CTR = PRD,Disabled,Disabled"
textline " "
bitfld.word 0x00 5. " SYNCI_EN ,Counter TSCTR Sync-In select mode" "Disabled,Enabled"
bitfld.word 0x00 4. " TSCTRSTOP ,Time stamp TSCTR counter stop control" "Stopped,Free-running"
textline " "
bitfld.word 0x00 3. " REARM ,One-Shot Re-Arming control" "No effect,One-shot sequence"
bitfld.word 0x00 1.--2. " STOP_WRAP ,Wrap value for one-shot mode" "Capture event 1,Capture event 2,Capture event 3,Capture event 4"
textline " "
bitfld.word 0x00 0. " CONT_ONESHT ,Continuous or one-shot mode control" "Continuous,One-shot"
endif
group.word 0x28++0x01
line.word 0x00 "ECCTL1,ECAP Control Regiser 1"
bitfld.word 0x00 14.--15. " FREE/SOFT ,Emulation control" "Stopped immediately,Run until = 0,Run free,Run free"
bitfld.word 0x00 9.--13. " PRESCALE ,Event filter prescale sel" "/1,/2,/4,/6,/8,/10,/12,/14,/16,/18,/20,/22,/24,/26,/28,/30,/32,/34,/36,/38,/40,/42,/44,/46,/48,/50,/52,/54,/56,/58,/60,/62"
textline " "
bitfld.word 0x00 8. " CAPLDEN ,Enable loading of CAP1-4 registers on a capture event" "Disabled,Enabled"
bitfld.word 0x00 7. " CTRRST4 ,Counter reset on capture event 4" "Not reset,Reset"
textline " "
bitfld.word 0x00 6. " CAP4POL ,Capture event 4 polarity select" "RE,FE"
bitfld.word 0x00 5. " CTRRST3 ,Counter reset on capture event 3" "Not reset,Reset"
textline " "
bitfld.word 0x00 4. " CAP3POL ,Capture event 3 polarity select" "RE,FE"
bitfld.word 0x00 3. " CTRRST2 ,Counter reset on capture event 2" "Not reset,Reset"
textline " "
bitfld.word 0x00 2. " CAP2POL ,Capture event 2 polarity select" "RE,FE"
bitfld.word 0x00 1. " CTRRST1 ,Counter reset on capture event 1" "Not reset,Reset"
textline " "
bitfld.word 0x00 0. " CAP1POL ,Capture event 1 polarity select" "RE,FE"
else
if (((d.w(ad:0xFCF79600+0x28))&0x201)==0x200)
group.word 0x28++0x01
line.word 0x00 "ECCTL2,ECAP Control Register 2"
bitfld.word 0x00 10. " APWMPOL ,APWM output polarity select" "High,Low"
bitfld.word 0x00 9. " CAP_APWM ,CAP/APWM operating mode select" "Capture mode,APWM mode"
textline " "
bitfld.word 0x00 8. " SWSYNC ,Software-forced counter TSCTR synchronizing" "No effect,Forced"
bitfld.word 0x00 6.--7. " SYNCO_SEL ,Sync-Out select" "Pass through,CTR = PRD,Disabled,Disabled"
textline " "
bitfld.word 0x00 5. " SYNCI_EN ,Counter TSCTR Sync-In select mode" "Disabled,Enabled"
bitfld.word 0x00 4. " TSCTRSTOP ,Time stamp TSCTR counter stop control" "Stopped,Free-running"
textline " "
bitfld.word 0x00 3. " REARM ,One-Shot Re-Arming control" "No effect,One-shot sequence"
bitfld.word 0x00 1.--2. " STOP_WRAP ,Wrap value for one-shot mode" "Capture event 1,Capture event 2,Capture event 3,Capture event 4"
textline " "
bitfld.word 0x00 0. " CONT_ONESHT ,Continuous or one-shot mode control" "Continuous,One-shot"
elif (((d.w(ad:0xFCF79600+0x28))&0x201)==0x201)
group.word 0x28++0x01
line.word 0x00 "ECCTL2,ECAP Control Register 2"
bitfld.word 0x00 10. " APWMPOL ,APWM output polarity select" "High,Low"
bitfld.word 0x00 9. " CAP_APWM ,CAP/APWM operating mode select" "Capture mode,APWM mode"
textline " "
bitfld.word 0x00 8. " SWSYNC ,Software-forced counter TSCTR synchronizing" "No effect,Forced"
bitfld.word 0x00 6.--7. " SYNCO_SEL ,Sync-Out select" "Pass through,CTR = PRD,Disabled,Disabled"
textline " "
bitfld.word 0x00 5. " SYNCI_EN ,Counter TSCTR Sync-In select mode" "Disabled,Enabled"
bitfld.word 0x00 4. " TSCTRSTOP ,Time stamp TSCTR counter stop control" "Stopped,Free-running"
textline " "
bitfld.word 0x00 3. " REARM ,One-Shot Re-Arming control" "No effect,One-shot sequence"
bitfld.word 0x00 1.--2. " STOP_WRAP ,Stop value for one-shot mode" "Capture event 1,Capture event 2,Capture event 3,Capture event 4"
textline " "
bitfld.word 0x00 0. " CONT_ONESHT ,Continuous or one-shot mode control" "Continuous,One-shot"
elif (((d.w(ad:0xFCF79600+0x28))&0x201)==0x01)
group.word 0x28++0x01
line.word 0x00 "ECCTL2,ECAP Control Register 2"
bitfld.word 0x00 9. " CAP_APWM ,CAP/APWM operating mode select" "Capture mode,APWM mode"
textline " "
bitfld.word 0x00 8. " SWSYNC ,Software-forced counter TSCTR synchronizing" "No effect,Forced"
bitfld.word 0x00 6.--7. " SYNCO_SEL ,Sync-Out select" "Pass through,CTR = PRD,Disabled,Disabled"
textline " "
bitfld.word 0x00 5. " SYNCI_EN ,Counter TSCTR Sync-In select mode" "Disabled,Enabled"
bitfld.word 0x00 4. " TSCTRSTOP ,Time stamp TSCTR counter stop control" "Stopped,Free-running"
textline " "
bitfld.word 0x00 3. " REARM ,One-Shot Re-Arming control" "No effect,One-shot sequence"
bitfld.word 0x00 1.--2. " STOP_WRAP ,Stop value for one-shot mode" "Capture event 1,Capture event 2,Capture event 3,Capture event 4"
textline " "
bitfld.word 0x00 0. " CONT_ONESHT ,Continuous or one-shot mode control" "Continuous,One-shot"
else
group.word 0x28++0x01
line.word 0x00 "ECCTL2,ECAP Control Register 2"
bitfld.word 0x00 9. " CAP_APWM ,CAP/APWM operating mode select" "Capture mode,APWM mode"
textline " "
bitfld.word 0x00 8. " SWSYNC ,Software-forced counter TSCTR synchronizing" "No effect,Forced"
bitfld.word 0x00 6.--7. " SYNCO_SEL ,Sync-Out select" "Pass through,CTR = PRD,Disabled,Disabled"
textline " "
bitfld.word 0x00 5. " SYNCI_EN ,Counter TSCTR Sync-In select mode" "Disabled,Enabled"
bitfld.word 0x00 4. " TSCTRSTOP ,Time stamp TSCTR counter stop control" "Stopped,Free-running"
textline " "
bitfld.word 0x00 3. " REARM ,One-Shot Re-Arming control" "No effect,One-shot sequence"
bitfld.word 0x00 1.--2. " STOP_WRAP ,Wrap value for one-shot mode" "Capture event 1,Capture event 2,Capture event 3,Capture event 4"
textline " "
bitfld.word 0x00 0. " CONT_ONESHT ,Continuous or one-shot mode control" "Continuous,One-shot"
endif
group.word 0x2A++0x01
line.word 0x00 "ECCTL1,ECAP Control Regiser 1"
bitfld.word 0x00 14.--15. " FREE/SOFT ,Emulation control" "Stopped immediately,Run until = 0,Run free,Run free"
bitfld.word 0x00 9.--13. " PRESCALE ,Event filter prescale sel" "/1,/2,/4,/6,/8,/10,/12,/14,/16,/18,/20,/22,/24,/26,/28,/30,/32,/34,/36,/38,/40,/42,/44,/46,/48,/50,/52,/54,/56,/58,/60,/62"
textline " "
bitfld.word 0x00 8. " CAPLDEN ,Enable loading of CAP1-4 registers on a capture event" "Disabled,Enabled"
bitfld.word 0x00 7. " CTRRST4 ,Counter reset on capture event 4" "Not reset,Reset"
textline " "
bitfld.word 0x00 6. " CAP4POL ,Capture event 4 polarity select" "RE,FE"
bitfld.word 0x00 5. " CTRRST3 ,Counter reset on capture event 3" "Not reset,Reset"
textline " "
bitfld.word 0x00 4. " CAP3POL ,Capture event 3 polarity select" "RE,FE"
bitfld.word 0x00 3. " CTRRST2 ,Counter reset on capture event 2" "Not reset,Reset"
textline " "
bitfld.word 0x00 2. " CAP2POL ,Capture event 2 polarity select" "RE,FE"
bitfld.word 0x00 1. " CTRRST1 ,Counter reset on capture event 1" "Not reset,Reset"
textline " "
bitfld.word 0x00 0. " CAP1POL ,Capture event 1 polarity select" "RE,FE"
endif
sif cpu()=="RM57L843-ZWT"
group.word 0x2E++0x01
line.word 0x00 "ECFLG,ECAP Interrupt Flag Register"
setclrfld.word 0x00 7. -0x02 7. 0x02 7. " CTR_CMP_SET/CLR ,Compare equal compare status flag" "Not occurred,Occurred"
setclrfld.word 0x00 6. -0x02 6. 0x02 6. " CTR_PRD_SET/CLR ,Counter equal period interrupt enable" "Not occurred,Occurred"
textline " "
setclrfld.word 0x00 5. -0x02 5. 0x02 5. " CTROVF_SET/CLR ,Counter equal period status flag" "Not occurred,Occurred"
setclrfld.word 0x00 4. -0x02 4. 0x02 4. " CEVT4_SET/CLR ,Counter overflow status flag" "Not occurred,Occurred"
textline " "
setclrfld.word 0x00 3. -0x02 3. 0x02 3. " CEVT3_SET/CLR ,Capture event 4 status flag" "Not occurred,Occurred"
setclrfld.word 0x00 2. -0x02 2. 0x02 2. " CEVT2_SET/CLR ,Capture event 2 status flag" "Not occurred,Occurred"
textline " "
setclrfld.word 0x00 1. -0x02 1. 0x02 1. " CEVT1_SET/CLR ,Capture event 1 interrupt enable" "Not occurred,Occurred"
setclrfld.word 0x00 0. -0x02 0. 0x02 0. " INT_SET/CLR ,Global interrupt status flag" "Not generated,Generated"
group.word 0x32++0x01
line.word 0x00 "ECFRC,ECAP Interrupt Forcing Register"
bitfld.word 0x00 7. " CTR_CMP ,Force counter equal compare interrupt" "No effect,Forced"
bitfld.word 0x00 6. " CTR_PRD ,Force counter equal period interrupt" "No effect,Forced"
textline " "
bitfld.word 0x00 5. " CTROVF ,Force counter overflow" "No effect,Forced"
bitfld.word 0x00 4. " CEVT4 ,Force capture event 4" "No effect,Forced"
textline " "
bitfld.word 0x00 3. " CEVT3 ,Force capture event 3" "No effect,Forced"
bitfld.word 0x00 2. " CEVT2 ,Force capture event 2" "No effect,Forced"
textline " "
bitfld.word 0x00 1. " CEVT1 ,Force capture event 1" "No effect,Forced"
else
group.word 0x2C++0x01
line.word 0x00 "ECFLG,ECAP Interrupt Flag Register"
setclrfld.word 0x00 7. 0x02 7. 0x06 7. " CTR_CMP_SET/CLR ,Compare equal compare status flag" "Not occurred,Occurred"
setclrfld.word 0x00 6. 0x02 6. 0x06 6. " CTR_PRD_SET/CLR ,Counter equal period interrupt enable" "Not occurred,Occurred"
textline " "
setclrfld.word 0x00 5. 0x02 5. 0x06 5. " CTROVF_SET/CLR ,Counter equal period status flag" "Not occurred,Occurred"
setclrfld.word 0x00 4. 0x02 4. 0x06 4. " CEVT4_SET/CLR ,Counter overflow status flag" "Not occurred,Occurred"
textline " "
setclrfld.word 0x00 3. 0x02 3. 0x06 3. " CEVT3_SET/CLR ,Capture event 4 status flag" "Not occurred,Occurred"
setclrfld.word 0x00 2. 0x02 2. 0x06 2. " CEVT2_SET/CLR ,Capture event 2 status flag" "Not occurred,Occurred"
textline " "
setclrfld.word 0x00 1. 0x02 1. 0x06 1. " CEVT1_SET/CLR ,Capture event 1 interrupt enable" "Not occurred,Occurred"
setclrfld.word 0x00 0. 0x02 0. 0x06 0. " INT_SET/CLR ,Global interrupt status flag" "Not generated,Generated"
group.word 0x30++0x01
line.word 0x00 "ECFRC,ECAP Interrupt Forcing Register"
bitfld.word 0x00 7. " CTR_CMP ,Force counter equal compare interrupt" "No effect,Forced"
bitfld.word 0x00 6. " CTR_PRD ,Force counter equal period interrupt" "No effect,Forced"
textline " "
bitfld.word 0x00 5. " CTROVF ,Force counter overflow" "No effect,Forced"
bitfld.word 0x00 4. " CEVT4 ,Force capture event 4" "No effect,Forced"
textline " "
bitfld.word 0x00 3. " CEVT3 ,Force capture event 3" "No effect,Forced"
bitfld.word 0x00 2. " CEVT2 ,Force capture event 2" "No effect,Forced"
textline " "
bitfld.word 0x00 1. " CEVT1 ,Force capture event 1" "No effect,Forced"
endif
width 0x0B
tree.end
tree "eCAP 5"
base ad:0xFCF79700
width 11.
group.long 0x00++0x17
line.long 0x00 "TSCTR,Time-Stamp Counter Register"
line.long 0x04 "CTRPHS,Counter Phase Control Register"
line.long 0x08 "CAP1,Capture-1 Register"
line.long 0x0C "CAP2,Capture-2 Register"
line.long 0x10 "CAP3,Capture-3 Register"
line.long 0x14 "CAP4,Capture-4 Register"
sif cpu()=="RM57L843-ZWT"
if (((d.w(ad:0xFCF79700+0x2A))&0x201)==0x200)
group.word 0x2A++0x01
line.word 0x00 "ECCTL2,ECAP Control Register 2"
bitfld.word 0x00 10. " APWMPOL ,APWM output polarity select" "High,Low"
bitfld.word 0x00 9. " CAP_APWM ,CAP/APWM operating mode select" "Capture mode,APWM mode"
textline " "
bitfld.word 0x00 8. " SWSYNC ,Software-forced counter TSCTR synchronizing" "No effect,Forced"
bitfld.word 0x00 6.--7. " SYNCO_SEL ,Sync-Out select" "Pass through,CTR = PRD,Disabled,Disabled"
textline " "
bitfld.word 0x00 5. " SYNCI_EN ,Counter TSCTR Sync-In select mode" "Disabled,Enabled"
bitfld.word 0x00 4. " TSCTRSTOP ,Time stamp TSCTR counter stop control" "Stopped,Free-running"
textline " "
bitfld.word 0x00 3. " REARM ,One-Shot Re-Arming control" "No effect,One-shot sequence"
bitfld.word 0x00 1.--2. " STOP_WRAP ,Wrap value for one-shot mode" "Capture event 1,Capture event 2,Capture event 3,Capture event 4"
textline " "
bitfld.word 0x00 0. " CONT_ONESHT ,Continuous or one-shot mode control" "Continuous,One-shot"
elif (((d.w(ad:0xFCF79700+0x2A))&0x201)==0x201)
group.word 0x2A++0x01
line.word 0x00 "ECCTL2,ECAP Control Register 2"
bitfld.word 0x00 10. " APWMPOL ,APWM output polarity select" "High,Low"
bitfld.word 0x00 9. " CAP_APWM ,CAP/APWM operating mode select" "Capture mode,APWM mode"
textline " "
bitfld.word 0x00 8. " SWSYNC ,Software-forced counter TSCTR synchronizing" "No effect,Forced"
bitfld.word 0x00 6.--7. " SYNCO_SEL ,Sync-Out select" "Pass through,CTR = PRD,Disabled,Disabled"
textline " "
bitfld.word 0x00 5. " SYNCI_EN ,Counter TSCTR Sync-In select mode" "Disabled,Enabled"
bitfld.word 0x00 4. " TSCTRSTOP ,Time stamp TSCTR counter stop control" "Stopped,Free-running"
textline " "
bitfld.word 0x00 3. " REARM ,One-Shot Re-Arming control" "No effect,One-shot sequence"
bitfld.word 0x00 1.--2. " STOP_WRAP ,Stop value for one-shot mode" "Capture event 1,Capture event 2,Capture event 3,Capture event 4"
textline " "
bitfld.word 0x00 0. " CONT_ONESHT ,Continuous or one-shot mode control" "Continuous,One-shot"
elif (((d.w(ad:0xFCF79700+0x2A))&0x201)==0x01)
group.word 0x2A++0x01
line.word 0x00 "ECCTL2,ECAP Control Register 2"
bitfld.word 0x00 9. " CAP_APWM ,CAP/APWM operating mode select" "Capture mode,APWM mode"
textline " "
bitfld.word 0x00 8. " SWSYNC ,Software-forced counter TSCTR synchronizing" "No effect,Forced"
bitfld.word 0x00 6.--7. " SYNCO_SEL ,Sync-Out select" "Pass through,CTR = PRD,Disabled,Disabled"
textline " "
bitfld.word 0x00 5. " SYNCI_EN ,Counter TSCTR Sync-In select mode" "Disabled,Enabled"
bitfld.word 0x00 4. " TSCTRSTOP ,Time stamp TSCTR counter stop control" "Stopped,Free-running"
textline " "
bitfld.word 0x00 3. " REARM ,One-Shot Re-Arming control" "No effect,One-shot sequence"
bitfld.word 0x00 1.--2. " STOP_WRAP ,Stop value for one-shot mode" "Capture event 1,Capture event 2,Capture event 3,Capture event 4"
textline " "
bitfld.word 0x00 0. " CONT_ONESHT ,Continuous or one-shot mode control" "Continuous,One-shot"
else
group.word 0x2A++0x01
line.word 0x00 "ECCTL2,ECAP Control Register 2"
bitfld.word 0x00 9. " CAP_APWM ,CAP/APWM operating mode select" "Capture mode,APWM mode"
textline " "
bitfld.word 0x00 8. " SWSYNC ,Software-forced counter TSCTR synchronizing" "No effect,Forced"
bitfld.word 0x00 6.--7. " SYNCO_SEL ,Sync-Out select" "Pass through,CTR = PRD,Disabled,Disabled"
textline " "
bitfld.word 0x00 5. " SYNCI_EN ,Counter TSCTR Sync-In select mode" "Disabled,Enabled"
bitfld.word 0x00 4. " TSCTRSTOP ,Time stamp TSCTR counter stop control" "Stopped,Free-running"
textline " "
bitfld.word 0x00 3. " REARM ,One-Shot Re-Arming control" "No effect,One-shot sequence"
bitfld.word 0x00 1.--2. " STOP_WRAP ,Wrap value for one-shot mode" "Capture event 1,Capture event 2,Capture event 3,Capture event 4"
textline " "
bitfld.word 0x00 0. " CONT_ONESHT ,Continuous or one-shot mode control" "Continuous,One-shot"
endif
group.word 0x28++0x01
line.word 0x00 "ECCTL1,ECAP Control Regiser 1"
bitfld.word 0x00 14.--15. " FREE/SOFT ,Emulation control" "Stopped immediately,Run until = 0,Run free,Run free"
bitfld.word 0x00 9.--13. " PRESCALE ,Event filter prescale sel" "/1,/2,/4,/6,/8,/10,/12,/14,/16,/18,/20,/22,/24,/26,/28,/30,/32,/34,/36,/38,/40,/42,/44,/46,/48,/50,/52,/54,/56,/58,/60,/62"
textline " "
bitfld.word 0x00 8. " CAPLDEN ,Enable loading of CAP1-4 registers on a capture event" "Disabled,Enabled"
bitfld.word 0x00 7. " CTRRST4 ,Counter reset on capture event 4" "Not reset,Reset"
textline " "
bitfld.word 0x00 6. " CAP4POL ,Capture event 4 polarity select" "RE,FE"
bitfld.word 0x00 5. " CTRRST3 ,Counter reset on capture event 3" "Not reset,Reset"
textline " "
bitfld.word 0x00 4. " CAP3POL ,Capture event 3 polarity select" "RE,FE"
bitfld.word 0x00 3. " CTRRST2 ,Counter reset on capture event 2" "Not reset,Reset"
textline " "
bitfld.word 0x00 2. " CAP2POL ,Capture event 2 polarity select" "RE,FE"
bitfld.word 0x00 1. " CTRRST1 ,Counter reset on capture event 1" "Not reset,Reset"
textline " "
bitfld.word 0x00 0. " CAP1POL ,Capture event 1 polarity select" "RE,FE"
else
if (((d.w(ad:0xFCF79700+0x28))&0x201)==0x200)
group.word 0x28++0x01
line.word 0x00 "ECCTL2,ECAP Control Register 2"
bitfld.word 0x00 10. " APWMPOL ,APWM output polarity select" "High,Low"
bitfld.word 0x00 9. " CAP_APWM ,CAP/APWM operating mode select" "Capture mode,APWM mode"
textline " "
bitfld.word 0x00 8. " SWSYNC ,Software-forced counter TSCTR synchronizing" "No effect,Forced"
bitfld.word 0x00 6.--7. " SYNCO_SEL ,Sync-Out select" "Pass through,CTR = PRD,Disabled,Disabled"
textline " "
bitfld.word 0x00 5. " SYNCI_EN ,Counter TSCTR Sync-In select mode" "Disabled,Enabled"
bitfld.word 0x00 4. " TSCTRSTOP ,Time stamp TSCTR counter stop control" "Stopped,Free-running"
textline " "
bitfld.word 0x00 3. " REARM ,One-Shot Re-Arming control" "No effect,One-shot sequence"
bitfld.word 0x00 1.--2. " STOP_WRAP ,Wrap value for one-shot mode" "Capture event 1,Capture event 2,Capture event 3,Capture event 4"
textline " "
bitfld.word 0x00 0. " CONT_ONESHT ,Continuous or one-shot mode control" "Continuous,One-shot"
elif (((d.w(ad:0xFCF79700+0x28))&0x201)==0x201)
group.word 0x28++0x01
line.word 0x00 "ECCTL2,ECAP Control Register 2"
bitfld.word 0x00 10. " APWMPOL ,APWM output polarity select" "High,Low"
bitfld.word 0x00 9. " CAP_APWM ,CAP/APWM operating mode select" "Capture mode,APWM mode"
textline " "
bitfld.word 0x00 8. " SWSYNC ,Software-forced counter TSCTR synchronizing" "No effect,Forced"
bitfld.word 0x00 6.--7. " SYNCO_SEL ,Sync-Out select" "Pass through,CTR = PRD,Disabled,Disabled"
textline " "
bitfld.word 0x00 5. " SYNCI_EN ,Counter TSCTR Sync-In select mode" "Disabled,Enabled"
bitfld.word 0x00 4. " TSCTRSTOP ,Time stamp TSCTR counter stop control" "Stopped,Free-running"
textline " "
bitfld.word 0x00 3. " REARM ,One-Shot Re-Arming control" "No effect,One-shot sequence"
bitfld.word 0x00 1.--2. " STOP_WRAP ,Stop value for one-shot mode" "Capture event 1,Capture event 2,Capture event 3,Capture event 4"
textline " "
bitfld.word 0x00 0. " CONT_ONESHT ,Continuous or one-shot mode control" "Continuous,One-shot"
elif (((d.w(ad:0xFCF79700+0x28))&0x201)==0x01)
group.word 0x28++0x01
line.word 0x00 "ECCTL2,ECAP Control Register 2"
bitfld.word 0x00 9. " CAP_APWM ,CAP/APWM operating mode select" "Capture mode,APWM mode"
textline " "
bitfld.word 0x00 8. " SWSYNC ,Software-forced counter TSCTR synchronizing" "No effect,Forced"
bitfld.word 0x00 6.--7. " SYNCO_SEL ,Sync-Out select" "Pass through,CTR = PRD,Disabled,Disabled"
textline " "
bitfld.word 0x00 5. " SYNCI_EN ,Counter TSCTR Sync-In select mode" "Disabled,Enabled"
bitfld.word 0x00 4. " TSCTRSTOP ,Time stamp TSCTR counter stop control" "Stopped,Free-running"
textline " "
bitfld.word 0x00 3. " REARM ,One-Shot Re-Arming control" "No effect,One-shot sequence"
bitfld.word 0x00 1.--2. " STOP_WRAP ,Stop value for one-shot mode" "Capture event 1,Capture event 2,Capture event 3,Capture event 4"
textline " "
bitfld.word 0x00 0. " CONT_ONESHT ,Continuous or one-shot mode control" "Continuous,One-shot"
else
group.word 0x28++0x01
line.word 0x00 "ECCTL2,ECAP Control Register 2"
bitfld.word 0x00 9. " CAP_APWM ,CAP/APWM operating mode select" "Capture mode,APWM mode"
textline " "
bitfld.word 0x00 8. " SWSYNC ,Software-forced counter TSCTR synchronizing" "No effect,Forced"
bitfld.word 0x00 6.--7. " SYNCO_SEL ,Sync-Out select" "Pass through,CTR = PRD,Disabled,Disabled"
textline " "
bitfld.word 0x00 5. " SYNCI_EN ,Counter TSCTR Sync-In select mode" "Disabled,Enabled"
bitfld.word 0x00 4. " TSCTRSTOP ,Time stamp TSCTR counter stop control" "Stopped,Free-running"
textline " "
bitfld.word 0x00 3. " REARM ,One-Shot Re-Arming control" "No effect,One-shot sequence"
bitfld.word 0x00 1.--2. " STOP_WRAP ,Wrap value for one-shot mode" "Capture event 1,Capture event 2,Capture event 3,Capture event 4"
textline " "
bitfld.word 0x00 0. " CONT_ONESHT ,Continuous or one-shot mode control" "Continuous,One-shot"
endif
group.word 0x2A++0x01
line.word 0x00 "ECCTL1,ECAP Control Regiser 1"
bitfld.word 0x00 14.--15. " FREE/SOFT ,Emulation control" "Stopped immediately,Run until = 0,Run free,Run free"
bitfld.word 0x00 9.--13. " PRESCALE ,Event filter prescale sel" "/1,/2,/4,/6,/8,/10,/12,/14,/16,/18,/20,/22,/24,/26,/28,/30,/32,/34,/36,/38,/40,/42,/44,/46,/48,/50,/52,/54,/56,/58,/60,/62"
textline " "
bitfld.word 0x00 8. " CAPLDEN ,Enable loading of CAP1-4 registers on a capture event" "Disabled,Enabled"
bitfld.word 0x00 7. " CTRRST4 ,Counter reset on capture event 4" "Not reset,Reset"
textline " "
bitfld.word 0x00 6. " CAP4POL ,Capture event 4 polarity select" "RE,FE"
bitfld.word 0x00 5. " CTRRST3 ,Counter reset on capture event 3" "Not reset,Reset"
textline " "
bitfld.word 0x00 4. " CAP3POL ,Capture event 3 polarity select" "RE,FE"
bitfld.word 0x00 3. " CTRRST2 ,Counter reset on capture event 2" "Not reset,Reset"
textline " "
bitfld.word 0x00 2. " CAP2POL ,Capture event 2 polarity select" "RE,FE"
bitfld.word 0x00 1. " CTRRST1 ,Counter reset on capture event 1" "Not reset,Reset"
textline " "
bitfld.word 0x00 0. " CAP1POL ,Capture event 1 polarity select" "RE,FE"
endif
sif cpu()=="RM57L843-ZWT"
group.word 0x2E++0x01
line.word 0x00 "ECFLG,ECAP Interrupt Flag Register"
setclrfld.word 0x00 7. -0x02 7. 0x02 7. " CTR_CMP_SET/CLR ,Compare equal compare status flag" "Not occurred,Occurred"
setclrfld.word 0x00 6. -0x02 6. 0x02 6. " CTR_PRD_SET/CLR ,Counter equal period interrupt enable" "Not occurred,Occurred"
textline " "
setclrfld.word 0x00 5. -0x02 5. 0x02 5. " CTROVF_SET/CLR ,Counter equal period status flag" "Not occurred,Occurred"
setclrfld.word 0x00 4. -0x02 4. 0x02 4. " CEVT4_SET/CLR ,Counter overflow status flag" "Not occurred,Occurred"
textline " "
setclrfld.word 0x00 3. -0x02 3. 0x02 3. " CEVT3_SET/CLR ,Capture event 4 status flag" "Not occurred,Occurred"
setclrfld.word 0x00 2. -0x02 2. 0x02 2. " CEVT2_SET/CLR ,Capture event 2 status flag" "Not occurred,Occurred"
textline " "
setclrfld.word 0x00 1. -0x02 1. 0x02 1. " CEVT1_SET/CLR ,Capture event 1 interrupt enable" "Not occurred,Occurred"
setclrfld.word 0x00 0. -0x02 0. 0x02 0. " INT_SET/CLR ,Global interrupt status flag" "Not generated,Generated"
group.word 0x32++0x01
line.word 0x00 "ECFRC,ECAP Interrupt Forcing Register"
bitfld.word 0x00 7. " CTR_CMP ,Force counter equal compare interrupt" "No effect,Forced"
bitfld.word 0x00 6. " CTR_PRD ,Force counter equal period interrupt" "No effect,Forced"
textline " "
bitfld.word 0x00 5. " CTROVF ,Force counter overflow" "No effect,Forced"
bitfld.word 0x00 4. " CEVT4 ,Force capture event 4" "No effect,Forced"
textline " "
bitfld.word 0x00 3. " CEVT3 ,Force capture event 3" "No effect,Forced"
bitfld.word 0x00 2. " CEVT2 ,Force capture event 2" "No effect,Forced"
textline " "
bitfld.word 0x00 1. " CEVT1 ,Force capture event 1" "No effect,Forced"
else
group.word 0x2C++0x01
line.word 0x00 "ECFLG,ECAP Interrupt Flag Register"
setclrfld.word 0x00 7. 0x02 7. 0x06 7. " CTR_CMP_SET/CLR ,Compare equal compare status flag" "Not occurred,Occurred"
setclrfld.word 0x00 6. 0x02 6. 0x06 6. " CTR_PRD_SET/CLR ,Counter equal period interrupt enable" "Not occurred,Occurred"
textline " "
setclrfld.word 0x00 5. 0x02 5. 0x06 5. " CTROVF_SET/CLR ,Counter equal period status flag" "Not occurred,Occurred"
setclrfld.word 0x00 4. 0x02 4. 0x06 4. " CEVT4_SET/CLR ,Counter overflow status flag" "Not occurred,Occurred"
textline " "
setclrfld.word 0x00 3. 0x02 3. 0x06 3. " CEVT3_SET/CLR ,Capture event 4 status flag" "Not occurred,Occurred"
setclrfld.word 0x00 2. 0x02 2. 0x06 2. " CEVT2_SET/CLR ,Capture event 2 status flag" "Not occurred,Occurred"
textline " "
setclrfld.word 0x00 1. 0x02 1. 0x06 1. " CEVT1_SET/CLR ,Capture event 1 interrupt enable" "Not occurred,Occurred"
setclrfld.word 0x00 0. 0x02 0. 0x06 0. " INT_SET/CLR ,Global interrupt status flag" "Not generated,Generated"
group.word 0x30++0x01
line.word 0x00 "ECFRC,ECAP Interrupt Forcing Register"
bitfld.word 0x00 7. " CTR_CMP ,Force counter equal compare interrupt" "No effect,Forced"
bitfld.word 0x00 6. " CTR_PRD ,Force counter equal period interrupt" "No effect,Forced"
textline " "
bitfld.word 0x00 5. " CTROVF ,Force counter overflow" "No effect,Forced"
bitfld.word 0x00 4. " CEVT4 ,Force capture event 4" "No effect,Forced"
textline " "
bitfld.word 0x00 3. " CEVT3 ,Force capture event 3" "No effect,Forced"
bitfld.word 0x00 2. " CEVT2 ,Force capture event 2" "No effect,Forced"
textline " "
bitfld.word 0x00 1. " CEVT1 ,Force capture event 1" "No effect,Forced"
endif
width 0x0B
tree.end
tree "eCAP 6"
base ad:0xFCF79800
width 11.
group.long 0x00++0x17
line.long 0x00 "TSCTR,Time-Stamp Counter Register"
line.long 0x04 "CTRPHS,Counter Phase Control Register"
line.long 0x08 "CAP1,Capture-1 Register"
line.long 0x0C "CAP2,Capture-2 Register"
line.long 0x10 "CAP3,Capture-3 Register"
line.long 0x14 "CAP4,Capture-4 Register"
sif cpu()=="RM57L843-ZWT"
if (((d.w(ad:0xFCF79800+0x2A))&0x201)==0x200)
group.word 0x2A++0x01
line.word 0x00 "ECCTL2,ECAP Control Register 2"
bitfld.word 0x00 10. " APWMPOL ,APWM output polarity select" "High,Low"
bitfld.word 0x00 9. " CAP_APWM ,CAP/APWM operating mode select" "Capture mode,APWM mode"
textline " "
bitfld.word 0x00 8. " SWSYNC ,Software-forced counter TSCTR synchronizing" "No effect,Forced"
bitfld.word 0x00 6.--7. " SYNCO_SEL ,Sync-Out select" "Pass through,CTR = PRD,Disabled,Disabled"
textline " "
bitfld.word 0x00 5. " SYNCI_EN ,Counter TSCTR Sync-In select mode" "Disabled,Enabled"
bitfld.word 0x00 4. " TSCTRSTOP ,Time stamp TSCTR counter stop control" "Stopped,Free-running"
textline " "
bitfld.word 0x00 3. " REARM ,One-Shot Re-Arming control" "No effect,One-shot sequence"
bitfld.word 0x00 1.--2. " STOP_WRAP ,Wrap value for one-shot mode" "Capture event 1,Capture event 2,Capture event 3,Capture event 4"
textline " "
bitfld.word 0x00 0. " CONT_ONESHT ,Continuous or one-shot mode control" "Continuous,One-shot"
elif (((d.w(ad:0xFCF79800+0x2A))&0x201)==0x201)
group.word 0x2A++0x01
line.word 0x00 "ECCTL2,ECAP Control Register 2"
bitfld.word 0x00 10. " APWMPOL ,APWM output polarity select" "High,Low"
bitfld.word 0x00 9. " CAP_APWM ,CAP/APWM operating mode select" "Capture mode,APWM mode"
textline " "
bitfld.word 0x00 8. " SWSYNC ,Software-forced counter TSCTR synchronizing" "No effect,Forced"
bitfld.word 0x00 6.--7. " SYNCO_SEL ,Sync-Out select" "Pass through,CTR = PRD,Disabled,Disabled"
textline " "
bitfld.word 0x00 5. " SYNCI_EN ,Counter TSCTR Sync-In select mode" "Disabled,Enabled"
bitfld.word 0x00 4. " TSCTRSTOP ,Time stamp TSCTR counter stop control" "Stopped,Free-running"
textline " "
bitfld.word 0x00 3. " REARM ,One-Shot Re-Arming control" "No effect,One-shot sequence"
bitfld.word 0x00 1.--2. " STOP_WRAP ,Stop value for one-shot mode" "Capture event 1,Capture event 2,Capture event 3,Capture event 4"
textline " "
bitfld.word 0x00 0. " CONT_ONESHT ,Continuous or one-shot mode control" "Continuous,One-shot"
elif (((d.w(ad:0xFCF79800+0x2A))&0x201)==0x01)
group.word 0x2A++0x01
line.word 0x00 "ECCTL2,ECAP Control Register 2"
bitfld.word 0x00 9. " CAP_APWM ,CAP/APWM operating mode select" "Capture mode,APWM mode"
textline " "
bitfld.word 0x00 8. " SWSYNC ,Software-forced counter TSCTR synchronizing" "No effect,Forced"
bitfld.word 0x00 6.--7. " SYNCO_SEL ,Sync-Out select" "Pass through,CTR = PRD,Disabled,Disabled"
textline " "
bitfld.word 0x00 5. " SYNCI_EN ,Counter TSCTR Sync-In select mode" "Disabled,Enabled"
bitfld.word 0x00 4. " TSCTRSTOP ,Time stamp TSCTR counter stop control" "Stopped,Free-running"
textline " "
bitfld.word 0x00 3. " REARM ,One-Shot Re-Arming control" "No effect,One-shot sequence"
bitfld.word 0x00 1.--2. " STOP_WRAP ,Stop value for one-shot mode" "Capture event 1,Capture event 2,Capture event 3,Capture event 4"
textline " "
bitfld.word 0x00 0. " CONT_ONESHT ,Continuous or one-shot mode control" "Continuous,One-shot"
else
group.word 0x2A++0x01
line.word 0x00 "ECCTL2,ECAP Control Register 2"
bitfld.word 0x00 9. " CAP_APWM ,CAP/APWM operating mode select" "Capture mode,APWM mode"
textline " "
bitfld.word 0x00 8. " SWSYNC ,Software-forced counter TSCTR synchronizing" "No effect,Forced"
bitfld.word 0x00 6.--7. " SYNCO_SEL ,Sync-Out select" "Pass through,CTR = PRD,Disabled,Disabled"
textline " "
bitfld.word 0x00 5. " SYNCI_EN ,Counter TSCTR Sync-In select mode" "Disabled,Enabled"
bitfld.word 0x00 4. " TSCTRSTOP ,Time stamp TSCTR counter stop control" "Stopped,Free-running"
textline " "
bitfld.word 0x00 3. " REARM ,One-Shot Re-Arming control" "No effect,One-shot sequence"
bitfld.word 0x00 1.--2. " STOP_WRAP ,Wrap value for one-shot mode" "Capture event 1,Capture event 2,Capture event 3,Capture event 4"
textline " "
bitfld.word 0x00 0. " CONT_ONESHT ,Continuous or one-shot mode control" "Continuous,One-shot"
endif
group.word 0x28++0x01
line.word 0x00 "ECCTL1,ECAP Control Regiser 1"
bitfld.word 0x00 14.--15. " FREE/SOFT ,Emulation control" "Stopped immediately,Run until = 0,Run free,Run free"
bitfld.word 0x00 9.--13. " PRESCALE ,Event filter prescale sel" "/1,/2,/4,/6,/8,/10,/12,/14,/16,/18,/20,/22,/24,/26,/28,/30,/32,/34,/36,/38,/40,/42,/44,/46,/48,/50,/52,/54,/56,/58,/60,/62"
textline " "
bitfld.word 0x00 8. " CAPLDEN ,Enable loading of CAP1-4 registers on a capture event" "Disabled,Enabled"
bitfld.word 0x00 7. " CTRRST4 ,Counter reset on capture event 4" "Not reset,Reset"
textline " "
bitfld.word 0x00 6. " CAP4POL ,Capture event 4 polarity select" "RE,FE"
bitfld.word 0x00 5. " CTRRST3 ,Counter reset on capture event 3" "Not reset,Reset"
textline " "
bitfld.word 0x00 4. " CAP3POL ,Capture event 3 polarity select" "RE,FE"
bitfld.word 0x00 3. " CTRRST2 ,Counter reset on capture event 2" "Not reset,Reset"
textline " "
bitfld.word 0x00 2. " CAP2POL ,Capture event 2 polarity select" "RE,FE"
bitfld.word 0x00 1. " CTRRST1 ,Counter reset on capture event 1" "Not reset,Reset"
textline " "
bitfld.word 0x00 0. " CAP1POL ,Capture event 1 polarity select" "RE,FE"
else
if (((d.w(ad:0xFCF79800+0x28))&0x201)==0x200)
group.word 0x28++0x01
line.word 0x00 "ECCTL2,ECAP Control Register 2"
bitfld.word 0x00 10. " APWMPOL ,APWM output polarity select" "High,Low"
bitfld.word 0x00 9. " CAP_APWM ,CAP/APWM operating mode select" "Capture mode,APWM mode"
textline " "
bitfld.word 0x00 8. " SWSYNC ,Software-forced counter TSCTR synchronizing" "No effect,Forced"
bitfld.word 0x00 6.--7. " SYNCO_SEL ,Sync-Out select" "Pass through,CTR = PRD,Disabled,Disabled"
textline " "
bitfld.word 0x00 5. " SYNCI_EN ,Counter TSCTR Sync-In select mode" "Disabled,Enabled"
bitfld.word 0x00 4. " TSCTRSTOP ,Time stamp TSCTR counter stop control" "Stopped,Free-running"
textline " "
bitfld.word 0x00 3. " REARM ,One-Shot Re-Arming control" "No effect,One-shot sequence"
bitfld.word 0x00 1.--2. " STOP_WRAP ,Wrap value for one-shot mode" "Capture event 1,Capture event 2,Capture event 3,Capture event 4"
textline " "
bitfld.word 0x00 0. " CONT_ONESHT ,Continuous or one-shot mode control" "Continuous,One-shot"
elif (((d.w(ad:0xFCF79800+0x28))&0x201)==0x201)
group.word 0x28++0x01
line.word 0x00 "ECCTL2,ECAP Control Register 2"
bitfld.word 0x00 10. " APWMPOL ,APWM output polarity select" "High,Low"
bitfld.word 0x00 9. " CAP_APWM ,CAP/APWM operating mode select" "Capture mode,APWM mode"
textline " "
bitfld.word 0x00 8. " SWSYNC ,Software-forced counter TSCTR synchronizing" "No effect,Forced"
bitfld.word 0x00 6.--7. " SYNCO_SEL ,Sync-Out select" "Pass through,CTR = PRD,Disabled,Disabled"
textline " "
bitfld.word 0x00 5. " SYNCI_EN ,Counter TSCTR Sync-In select mode" "Disabled,Enabled"
bitfld.word 0x00 4. " TSCTRSTOP ,Time stamp TSCTR counter stop control" "Stopped,Free-running"
textline " "
bitfld.word 0x00 3. " REARM ,One-Shot Re-Arming control" "No effect,One-shot sequence"
bitfld.word 0x00 1.--2. " STOP_WRAP ,Stop value for one-shot mode" "Capture event 1,Capture event 2,Capture event 3,Capture event 4"
textline " "
bitfld.word 0x00 0. " CONT_ONESHT ,Continuous or one-shot mode control" "Continuous,One-shot"
elif (((d.w(ad:0xFCF79800+0x28))&0x201)==0x01)
group.word 0x28++0x01
line.word 0x00 "ECCTL2,ECAP Control Register 2"
bitfld.word 0x00 9. " CAP_APWM ,CAP/APWM operating mode select" "Capture mode,APWM mode"
textline " "
bitfld.word 0x00 8. " SWSYNC ,Software-forced counter TSCTR synchronizing" "No effect,Forced"
bitfld.word 0x00 6.--7. " SYNCO_SEL ,Sync-Out select" "Pass through,CTR = PRD,Disabled,Disabled"
textline " "
bitfld.word 0x00 5. " SYNCI_EN ,Counter TSCTR Sync-In select mode" "Disabled,Enabled"
bitfld.word 0x00 4. " TSCTRSTOP ,Time stamp TSCTR counter stop control" "Stopped,Free-running"
textline " "
bitfld.word 0x00 3. " REARM ,One-Shot Re-Arming control" "No effect,One-shot sequence"
bitfld.word 0x00 1.--2. " STOP_WRAP ,Stop value for one-shot mode" "Capture event 1,Capture event 2,Capture event 3,Capture event 4"
textline " "
bitfld.word 0x00 0. " CONT_ONESHT ,Continuous or one-shot mode control" "Continuous,One-shot"
else
group.word 0x28++0x01
line.word 0x00 "ECCTL2,ECAP Control Register 2"
bitfld.word 0x00 9. " CAP_APWM ,CAP/APWM operating mode select" "Capture mode,APWM mode"
textline " "
bitfld.word 0x00 8. " SWSYNC ,Software-forced counter TSCTR synchronizing" "No effect,Forced"
bitfld.word 0x00 6.--7. " SYNCO_SEL ,Sync-Out select" "Pass through,CTR = PRD,Disabled,Disabled"
textline " "
bitfld.word 0x00 5. " SYNCI_EN ,Counter TSCTR Sync-In select mode" "Disabled,Enabled"
bitfld.word 0x00 4. " TSCTRSTOP ,Time stamp TSCTR counter stop control" "Stopped,Free-running"
textline " "
bitfld.word 0x00 3. " REARM ,One-Shot Re-Arming control" "No effect,One-shot sequence"
bitfld.word 0x00 1.--2. " STOP_WRAP ,Wrap value for one-shot mode" "Capture event 1,Capture event 2,Capture event 3,Capture event 4"
textline " "
bitfld.word 0x00 0. " CONT_ONESHT ,Continuous or one-shot mode control" "Continuous,One-shot"
endif
group.word 0x2A++0x01
line.word 0x00 "ECCTL1,ECAP Control Regiser 1"
bitfld.word 0x00 14.--15. " FREE/SOFT ,Emulation control" "Stopped immediately,Run until = 0,Run free,Run free"
bitfld.word 0x00 9.--13. " PRESCALE ,Event filter prescale sel" "/1,/2,/4,/6,/8,/10,/12,/14,/16,/18,/20,/22,/24,/26,/28,/30,/32,/34,/36,/38,/40,/42,/44,/46,/48,/50,/52,/54,/56,/58,/60,/62"
textline " "
bitfld.word 0x00 8. " CAPLDEN ,Enable loading of CAP1-4 registers on a capture event" "Disabled,Enabled"
bitfld.word 0x00 7. " CTRRST4 ,Counter reset on capture event 4" "Not reset,Reset"
textline " "
bitfld.word 0x00 6. " CAP4POL ,Capture event 4 polarity select" "RE,FE"
bitfld.word 0x00 5. " CTRRST3 ,Counter reset on capture event 3" "Not reset,Reset"
textline " "
bitfld.word 0x00 4. " CAP3POL ,Capture event 3 polarity select" "RE,FE"
bitfld.word 0x00 3. " CTRRST2 ,Counter reset on capture event 2" "Not reset,Reset"
textline " "
bitfld.word 0x00 2. " CAP2POL ,Capture event 2 polarity select" "RE,FE"
bitfld.word 0x00 1. " CTRRST1 ,Counter reset on capture event 1" "Not reset,Reset"
textline " "
bitfld.word 0x00 0. " CAP1POL ,Capture event 1 polarity select" "RE,FE"
endif
sif cpu()=="RM57L843-ZWT"
group.word 0x2E++0x01
line.word 0x00 "ECFLG,ECAP Interrupt Flag Register"
setclrfld.word 0x00 7. -0x02 7. 0x02 7. " CTR_CMP_SET/CLR ,Compare equal compare status flag" "Not occurred,Occurred"
setclrfld.word 0x00 6. -0x02 6. 0x02 6. " CTR_PRD_SET/CLR ,Counter equal period interrupt enable" "Not occurred,Occurred"
textline " "
setclrfld.word 0x00 5. -0x02 5. 0x02 5. " CTROVF_SET/CLR ,Counter equal period status flag" "Not occurred,Occurred"
setclrfld.word 0x00 4. -0x02 4. 0x02 4. " CEVT4_SET/CLR ,Counter overflow status flag" "Not occurred,Occurred"
textline " "
setclrfld.word 0x00 3. -0x02 3. 0x02 3. " CEVT3_SET/CLR ,Capture event 4 status flag" "Not occurred,Occurred"
setclrfld.word 0x00 2. -0x02 2. 0x02 2. " CEVT2_SET/CLR ,Capture event 2 status flag" "Not occurred,Occurred"
textline " "
setclrfld.word 0x00 1. -0x02 1. 0x02 1. " CEVT1_SET/CLR ,Capture event 1 interrupt enable" "Not occurred,Occurred"
setclrfld.word 0x00 0. -0x02 0. 0x02 0. " INT_SET/CLR ,Global interrupt status flag" "Not generated,Generated"
group.word 0x32++0x01
line.word 0x00 "ECFRC,ECAP Interrupt Forcing Register"
bitfld.word 0x00 7. " CTR_CMP ,Force counter equal compare interrupt" "No effect,Forced"
bitfld.word 0x00 6. " CTR_PRD ,Force counter equal period interrupt" "No effect,Forced"
textline " "
bitfld.word 0x00 5. " CTROVF ,Force counter overflow" "No effect,Forced"
bitfld.word 0x00 4. " CEVT4 ,Force capture event 4" "No effect,Forced"
textline " "
bitfld.word 0x00 3. " CEVT3 ,Force capture event 3" "No effect,Forced"
bitfld.word 0x00 2. " CEVT2 ,Force capture event 2" "No effect,Forced"
textline " "
bitfld.word 0x00 1. " CEVT1 ,Force capture event 1" "No effect,Forced"
else
group.word 0x2C++0x01
line.word 0x00 "ECFLG,ECAP Interrupt Flag Register"
setclrfld.word 0x00 7. 0x02 7. 0x06 7. " CTR_CMP_SET/CLR ,Compare equal compare status flag" "Not occurred,Occurred"
setclrfld.word 0x00 6. 0x02 6. 0x06 6. " CTR_PRD_SET/CLR ,Counter equal period interrupt enable" "Not occurred,Occurred"
textline " "
setclrfld.word 0x00 5. 0x02 5. 0x06 5. " CTROVF_SET/CLR ,Counter equal period status flag" "Not occurred,Occurred"
setclrfld.word 0x00 4. 0x02 4. 0x06 4. " CEVT4_SET/CLR ,Counter overflow status flag" "Not occurred,Occurred"
textline " "
setclrfld.word 0x00 3. 0x02 3. 0x06 3. " CEVT3_SET/CLR ,Capture event 4 status flag" "Not occurred,Occurred"
setclrfld.word 0x00 2. 0x02 2. 0x06 2. " CEVT2_SET/CLR ,Capture event 2 status flag" "Not occurred,Occurred"
textline " "
setclrfld.word 0x00 1. 0x02 1. 0x06 1. " CEVT1_SET/CLR ,Capture event 1 interrupt enable" "Not occurred,Occurred"
setclrfld.word 0x00 0. 0x02 0. 0x06 0. " INT_SET/CLR ,Global interrupt status flag" "Not generated,Generated"
group.word 0x30++0x01
line.word 0x00 "ECFRC,ECAP Interrupt Forcing Register"
bitfld.word 0x00 7. " CTR_CMP ,Force counter equal compare interrupt" "No effect,Forced"
bitfld.word 0x00 6. " CTR_PRD ,Force counter equal period interrupt" "No effect,Forced"
textline " "
bitfld.word 0x00 5. " CTROVF ,Force counter overflow" "No effect,Forced"
bitfld.word 0x00 4. " CEVT4 ,Force capture event 4" "No effect,Forced"
textline " "
bitfld.word 0x00 3. " CEVT3 ,Force capture event 3" "No effect,Forced"
bitfld.word 0x00 2. " CEVT2 ,Force capture event 2" "No effect,Forced"
textline " "
bitfld.word 0x00 1. " CEVT1 ,Force capture event 1" "No effect,Forced"
endif
width 0x0B
tree.end
tree.end
tree.open "eQEP (Enhanced QEP Module)"
tree "eQEP 1"
base ad:0xFCF79900
sif cpuis("TMS570LS0232")||cpuis("TMS570LS0714*")||cpuis("TMS570LS0914*")
endian.be
endif
width 10.
group.long 0x00++0x0F
line.long 0x00 "QPOSCNT,EQEP Position Counter Register"
line.long 0x04 "QPOSINIT,EQEP Position Counter Initialization Register"
line.long 0x08 "QPOSMAX,EQEP Maximum Position Count Register"
line.long 0x0C "QPOSCMP,EQEP Position-Compare Register"
rgroup.long 0x10++0x0B
line.long 0x00 "QPOSILAT,EQEP Index Position Latch Register"
line.long 0x04 "QPOSSLAT,EQEP Strobe Position Latch Register"
line.long 0x08 "QPOSLAT,EQEP Position Counter Latch Register"
group.long 0x1C++0x07
line.long 0x00 "QUTMR,EQEP Unit Timer Register"
line.long 0x04 "QUPRD,EQEP Register Unit Period Register"
newline
group.word 0x24++0x03
line.word 0x00 "QWDPRD,EQEP Watchdog Period Register"
line.word 0x02 "QWDTMR,EQEP Watchdog Timer Register"
sif cpu()=="RM57L843-ZWT"
group.word 0x28++0x07
line.word 0x00 "QDECCTL,EQEP Decoder Control Register"
bitfld.word 0x00 14.--15. " QSRC ,Position-counter source selection" "Quadrature count,Direction-count,UP count,DOWN count"
bitfld.word 0x00 13. " SOEN ,Sync output-enable" "Disabled,Enabled"
newline
bitfld.word 0x00 12. " SPSEL ,Sync output pin selection" "Index pin,Strobe pin"
bitfld.word 0x00 11. " XCR ,External clock rate" "2x resolution,1x resolution"
newline
bitfld.word 0x00 10. " SWAP ,Swap quadrature clock inputs" "Not swapped,Swapped"
bitfld.word 0x00 9. " IGATE ,Index pulse gating option" "Disable gating of index pulse,Gate the index pin with strobe"
newline
bitfld.word 0x00 8. " QAP ,QEPA input polarity" "No effect,Negates QEPA"
bitfld.word 0x00 7. " QBP ,QEPB input polarity" "No effect,Negates QEPB"
newline
bitfld.word 0x00 6. " QIP ,QEPI input polarity" "No effect,Negates QEPI"
bitfld.word 0x00 5. " QSP ,QEPS input polarity" "No effect,Negates QEPS"
line.word 0x02 "QEPCTL,EQEP Control Register"
bitfld.word 0x02 14.--15. " FREE/SOFT ,Emulation control bits" "Stopped,Continued,Unaffected,Unaffected"
bitfld.word 0x02 12.--13. " PCRM ,Position counter reset mode" "Index event,Maximum position,First index event,Unit time event"
newline
bitfld.word 0x02 10.--11. " SEI ,Strobe event initialization of position counter" "Disabled,Disabled,Rising edge,Clockwise direction"
bitfld.word 0x02 8.--9. " IEI ,Index event initialization of position counter" "Disabled,Disabled,Rising edge,Falling edge"
newline
bitfld.word 0x02 7. " SWI ,Software initialization of position counter" "Disabled,Enabled"
bitfld.word 0x02 6. " SEL ,Strobe event latch of position counter" "Rising edge,Rising/faling edge"
newline
bitfld.word 0x02 4.--5. " IEL ,Index event latch of position counter" ",Rising edge,Faling edge,Software index marker"
bitfld.word 0x02 3. " QPEN ,Quadrature position counter enable/software reset" "Reset,Enabled"
newline
bitfld.word 0x02 2. " QCLM ,EQEP capture latch mode" "Position counter read by CPU,Unit time out"
bitfld.word 0x02 1. " UTE ,EQEP unit timer enable" "Disabled,Enabled"
newline
bitfld.word 0x02 0. " WDE ,EQEP watchdog enable" "Disabled,Enabled"
line.word 0x04 "QCAPCTL,EQEP Capture Control Register"
bitfld.word 0x04 15. " CEN ,Enable EQEP capture" "Disabled,Enabled"
bitfld.word 0x04 4.--6. " CCPS ,EQEP capture timer clock prescaler" "VCLK/1,VCLK/2,VCLK/4,VCLK/8,VCLK/16,VCLK/32,VCLK/64,VCLK/128"
newline
bitfld.word 0x04 0.--3. " UPPS ,Unit position event prescaler" "QCLK/1,QCLK/2,QCLK/4,QCLK/8,QCLK/16,QCLK/32,QCLK/64,QCLK/128,QCLK/256,QCLK/512,QCLK/1024,QCLK/2048,?..."
line.word 0x06 "QPOSCTL,EQEP Position-Compare Control Register"
bitfld.word 0x06 15. " PCSHDW ,Position-compare shadow enable" "Disabled,Enabled"
bitfld.word 0x06 14. " PCLOAD ,Position-compare shadow load mode" "QPOSCNT = 0,QPOSCNT = QPOSCMP"
newline
bitfld.word 0x06 13. " PCPOL ,Polarity of sync output" "High,Low"
bitfld.word 0x06 12. " PCE ,Position-compare enable/disable" "Disabled,Enabled"
newline
hexmask.word 0x06 0.--11. 1. " PCSPW ,Select-position-compare sync output pulse width"
else
group.word 0x28++0x07
line.word 0x00 "QEPCTL,EQEP Control Register"
bitfld.word 0x00 14.--15. " FREE/SOFT ,Emulation control bits" "Stopped,Continued,Unaffected,Unaffected"
bitfld.word 0x00 12.--13. " PCRM ,Position counter reset mode" "Index event,Maximum position,First index event,Unit time event"
newline
bitfld.word 0x00 10.--11. " SEI ,Strobe event initialization of position counter" "Disabled,Disabled,Rising edge,Clockwise direction"
bitfld.word 0x00 8.--9. " IEI ,Index event initialization of position counter" "Disabled,Disabled,Rising edge,Falling edge"
newline
bitfld.word 0x00 7. " SWI ,Software initialization of position counter" "Disabled,Enabled"
bitfld.word 0x00 6. " SEL ,Strobe event latch of position counter" "Rising edge,Falling edge"
newline
bitfld.word 0x00 4.--5. " IEL ,Index event latch of position counter" ",Rising edge,Falling edge,Software index marker"
bitfld.word 0x00 3. " QPEN ,Quadrature position counter enable/software reset" "Reset,Enabled"
newline
bitfld.word 0x00 2. " QCLM ,EQEP capture latch mode" "Read by CPU,Unit time out"
bitfld.word 0x00 1. " UTE ,EQEP unit timer enable" "Disabled,Enabled"
newline
bitfld.word 0x00 0. " WDE ,EQEP watchdog enable" "Disabled,Enabled"
line.word 0x02 "QDECCTL,EQEP Decoder Control Register"
bitfld.word 0x02 14.--15. " QSRC ,Position-counter source selection" "Quadrature,Direction,UP,DOWN"
bitfld.word 0x02 13. " SOEN ,Sync output-enable" "Disabled,Enabled"
newline
bitfld.word 0x02 12. " SPSEL ,Sync output pin selection" "Index,Strobe"
bitfld.word 0x02 11. " XCR ,External clock rate" "2x resolution,1x resolution"
newline
bitfld.word 0x02 10. " SWAP ,Swap quadrature clock inputs" "Not swapped,Swapped"
bitfld.word 0x02 9. " IGATE ,Index pulse gating option enable" "Disable,Enabled"
newline
bitfld.word 0x02 8. " QAP ,QEPA input polarity" "No effect,Negates QEPA"
bitfld.word 0x02 7. " QBP ,QEPB input polarity" "No effect,Negates QEPB"
newline
bitfld.word 0x02 6. " QIP ,QEPI input polarity" "No effect,Negates QEPI"
bitfld.word 0x02 5. " QSP ,QEPS input polarity" "No effect,Negates QEPS"
line.word 0x04 "QPOSCTL,EQEP Position-Compare Control Register"
bitfld.word 0x04 15. " PCSHDW ,Position-compare shadow enable" "Disabled,Enabled"
bitfld.word 0x04 14. " PCLOAD ,Position-compare shadow load mode" "QPOSCNT = 0,QPOSCNT = QPOSCMP"
newline
bitfld.word 0x04 13. " PCPOL ,Polarity of sync output" "High,Low"
bitfld.word 0x04 12. " PCE ,Position-compare enable/disable" "Disabled,Enabled"
newline
hexmask.word 0x04 0.--11. 1. " PCSPW ,Select-position-compare sync output pulse width"
line.word 0x06 "QCAPCTL,EQEP Capture Control Register"
bitfld.word 0x06 15. " CEN ,Enable EQEP capture" "Disabled,Enabled"
bitfld.word 0x06 4.--6. " CCPS ,EQEP capture timer clock prescaler" "VCLK/1,VCLK/2,VCLK/4,VCLK/8,VCLK/16,VCLK/32,VCLK/64,VCLK/128"
newline
bitfld.word 0x06 0.--3. " UPPS ,Unit position event prescaler" "QCLK/1,QCLK/2,QCLK/4,QCLK/8,QCLK/16,QCLK/32,QCLK/64,QCLK/128,QCLK/256,QCLK/512,QCLK/1024,QCLK/2048,?..."
endif
newline
sif cpu()=="RM57L843-ZWT"
rgroup.word 0x32++0x01
line.word 0x00 "QFLG,EQEP Interrupt Flag Register"
bitfld.word 0x00 11. " UTO ,Unit time out interrupt" "Not generated,Generated"
bitfld.word 0x00 10. " IEL ,Index event latch interrupt" "Not generated,Generated"
bitfld.word 0x00 9. " SEL ,Strobe event latch interrupt" "Not generated,Generated"
bitfld.word 0x00 8. " PCM ,Position-compare match interrupt" "Not generated,Generated"
newline
bitfld.word 0x00 7. " PCR ,Position-compare ready interrupt" "Not generated,Generated"
bitfld.word 0x00 6. " PCO ,Position counter overflow interrupt" "Not generated,Generated"
bitfld.word 0x00 5. " PCU ,Position counter underflow interrupt" "Not generated,Generated"
bitfld.word 0x00 4. " WTO ,Watchdog time out interrupt" "Not generated,Generated"
newline
bitfld.word 0x00 3. " QDC ,Quadrature direction change interrupt" "Not generated,Generated"
bitfld.word 0x00 2. " PHE ,Quadrature phase error interrupt" "Not generated,Generated"
bitfld.word 0x00 1. " PCE ,Position counter error interrupt" "Not generated,Generated"
bitfld.word 0x00 0. " INT ,Global interrupt status flag" "Not generated,Generated"
group.word 0x30++0x01
line.word 0x00 "QEINT,EQEP Interrupt Enable Register"
bitfld.word 0x00 11. " UTO ,Unit time out interrupt enable" "Disabled,Enable"
bitfld.word 0x00 10. " IEL ,Index event latch interrupt enable" "Disabled,Enable"
bitfld.word 0x00 9. " SEL ,Strobe event latch interrupt enable" "Disabled,Enable"
bitfld.word 0x00 8. " PCM ,Position-compare match interrupt enable" "Disabled,Enable"
newline
bitfld.word 0x00 7. " PCR ,Position-compare ready interrupt enable" "Disabled,Enable"
bitfld.word 0x00 6. " PCO ,Position counter overflow interrupt enable" "Disabled,Enable"
bitfld.word 0x00 5. " PCU ,Position counter underflow interrupt enable" "Disabled,Enable"
bitfld.word 0x00 4. " WTO ,Watchdog time out interrupt enable" "Disabled,Enable"
newline
bitfld.word 0x00 3. " QDC ,Quadrature direction change interrupt enable" "Disabled,Enable"
bitfld.word 0x00 2. " QPE ,Quadrature phase error interrupt enable" "Disabled,Enable"
bitfld.word 0x00 1. " PCE ,Position counter error interrupt enable" "Disabled,Enable"
group.word 0x36++0x01
line.word 0x00 "QFRC,EQEP Interrupt Force Register"
bitfld.word 0x00 11. " UTO ,Force unit time out interrupt" "No effect,Forced"
bitfld.word 0x00 10. " IEL ,Force index event latch interrupt" "No effect,Forced"
bitfld.word 0x00 9. " SEL ,Force strobe event latch interrupt" "No effect,Forced"
bitfld.word 0x00 8. " PCM ,Force position-compare match interrupt" "No effect,Forced"
newline
bitfld.word 0x00 7. " PCR ,Force position-compare ready interrupt" "No effect,Forced"
bitfld.word 0x00 6. " PCO ,Force position counter overflow interrupt" "No effect,Forced"
bitfld.word 0x00 5. " PCU ,Force position counter underflow interrupt" "No effect,Forced"
bitfld.word 0x00 4. " WTO ,Force watchdog time out interrupt" "No effect,Forced"
newline
bitfld.word 0x00 3. " QDC ,Force quadrature direction change interrupt" "No effect,Forced"
bitfld.word 0x00 2. " PHE ,Force quadrature phase error interrupt" "No effect,Forced"
bitfld.word 0x00 1. " PCE ,Force position counter error interrupt" "No effect,Forced"
group.word 0x34++0x01
line.word 0x00 "QCLR,EQEP Interrupt Clear Register"
bitfld.word 0x00 11. " UTO ,Clear unit time out interrupt flag" "No effect,Clears flag"
bitfld.word 0x00 10. " IEL ,Clear index event latch interrupt flag" "No effect,Clears flag"
bitfld.word 0x00 9. " SEL ,Clear strobe event latch interrupt flag" "No effect,Clears flag"
bitfld.word 0x00 8. " PCM ,Clear EQEP compare match event interrupt flag" "No effect,Clears flag"
newline
bitfld.word 0x00 7. " PCR ,Clear position-compare ready interrupt flag" "No effect,Clears flag"
bitfld.word 0x00 6. " PCO ,Clear position counter overflow interrupt flag" "No effect,Clears flag"
bitfld.word 0x00 5. " PCU ,Clear position counter underflow interrupt flag" "No effect,Clears flag"
bitfld.word 0x00 4. " WTO ,Clear watchdog timeout interrupt flag" "No effect,Clears flag"
newline
bitfld.word 0x00 3. " QDC ,Clear quadrature direction change interrupt flag" "No effect,Clears flag"
bitfld.word 0x00 2. " PHE ,Clear quadrature phase error interrupt flag" "No effect,Clears flag"
bitfld.word 0x00 1. " PCE ,Clear position counter error interrupt flag" "No effect,Clears flag"
bitfld.word 0x00 0. " INT ,Global interrupt clear flag" "No effect,Clears flag"
group.word 0x3A++0x01
line.word 0x00 "QCTMR,EQEP Capture Timer Register"
group.word 0x38++0x01
line.word 0x00 "QEPSTS,EQEP Status Register"
eventfld.word 0x00 7. " UPEVNT ,Unit position event flag" "Not detected,Detected"
rbitfld.word 0x00 6. " FIDF ,Direction on the first index marker" "Counter-clockwise rotation,Clockwise rotation"
newline
rbitfld.word 0x00 5. " QDF ,Quadrature direction flag" "Counter-clockwise rotation,Clockwise rotation"
rbitfld.word 0x00 4. " QDLF ,EQEP direction latch flag" "Counter-clockwise rotation,Clockwise rotation"
newline
eventfld.word 0x00 3. " COEF ,Capture overflow error flag" "Not occurred,Occurred"
eventfld.word 0x00 2. " CDEF ,Capture direction error flag" "Not occurred,Occurred"
newline
eventfld.word 0x00 1. " FIMF ,First index marker flag" "Not occurred,Occurred"
rbitfld.word 0x00 0. " PCEF ,Position counter error flag" "No error,Error"
rgroup.word 0x3E++0x01
line.word 0x00 "QCTMRLAT,EQEP Capture Timer Latch Register"
group.word 0x3C++0x03
line.word 0x00 "QCPRD,EQEP Capture Period Register"
line.word 0x02 "QCPRDLAT,EQEP Capture Period Latch Register"
else
rgroup.word 0x30++0x01
line.word 0x00 "QFLG,EQEP Interrupt Flag Register"
bitfld.word 0x00 11. " UTO ,Unit time out interrupt" "Not generated,Generated"
bitfld.word 0x00 10. " IEL ,Index event latch interrupt" "Not generated,Generated"
bitfld.word 0x00 9. " SEL ,Strobe event latch interrupt" "Not generated,Generated"
bitfld.word 0x00 8. " PCM ,Position-compare match interrupt" "Not generated,Generated"
newline
bitfld.word 0x00 7. " PCR ,Position-compare ready interrupt" "Not generated,Generated"
bitfld.word 0x00 6. " PCO ,Position counter overflow interrupt" "Not generated,Generated"
bitfld.word 0x00 5. " PCU ,Position counter underflow interrupt" "Not generated,Generated"
bitfld.word 0x00 4. " WTO ,Watchdog time out interrupt" "Not generated,Generated"
newline
bitfld.word 0x00 3. " QDC ,Quadrature direction change interrupt" "Not generated,Generated"
bitfld.word 0x00 2. " PHE ,Quadrature phase error interrupt" "Not generated,Generated"
bitfld.word 0x00 1. " PCE ,Position counter error interrupt" "Not generated,Generated"
bitfld.word 0x00 0. " INT ,Global interrupt status flag" "Not generated,Generated"
group.word 0x32++0x0D
line.word 0x00 "QEINT,EQEP Interrupt Enable Register"
bitfld.word 0x00 11. " UTO ,Unit time out interrupt enable" "Disabled,Enable"
bitfld.word 0x00 10. " IEL ,Index event latch interrupt enable" "Disabled,Enable"
bitfld.word 0x00 9. " SEL ,Strobe event latch interrupt enable" "Disabled,Enable"
bitfld.word 0x00 8. " PCM ,Position-compare match interrupt enable" "Disabled,Enable"
newline
bitfld.word 0x00 7. " PCR ,Position-compare ready interrupt enable" "Disabled,Enable"
bitfld.word 0x00 6. " PCO ,Position counter overflow interrupt enable" "Disabled,Enable"
bitfld.word 0x00 5. " PCU ,Position counter underflow interrupt enable" "Disabled,Enable"
bitfld.word 0x00 4. " WTO ,Watchdog time out interrupt enable" "Disabled,Enable"
newline
bitfld.word 0x00 3. " QDC ,Quadrature direction change interrupt enable" "Disabled,Enable"
bitfld.word 0x00 2. " QPE ,Quadrature phase error interrupt enable" "Disabled,Enable"
bitfld.word 0x00 1. " PCE ,Position counter error interrupt enable" "Disabled,Enable"
line.word 0x02 "QFRC,EQEP Interrupt Force Register"
bitfld.word 0x02 11. " UTO ,Force unit time out interrupt" "No effect,Forced"
bitfld.word 0x02 10. " IEL ,Force index event latch interrupt" "No effect,Forced"
bitfld.word 0x02 9. " SEL ,Force strobe event latch interrupt" "No effect,Forced"
bitfld.word 0x02 8. " PCM ,Force position-compare match interrupt" "No effect,Forced"
newline
bitfld.word 0x02 7. " PCR ,Force position-compare ready interrupt" "No effect,Forced"
bitfld.word 0x02 6. " PCO ,Force position counter overflow interrupt" "No effect,Forced"
bitfld.word 0x02 5. " PCU ,Force position counter underflow interrupt" "No effect,Forced"
bitfld.word 0x02 4. " WTO ,Force watchdog time out interrupt" "No effect,Forced"
newline
bitfld.word 0x02 3. " QDC ,Force quadrature direction change interrupt" "No effect,Forced"
bitfld.word 0x02 2. " PHE ,Force quadrature phase error interrupt" "No effect,Forced"
bitfld.word 0x02 1. " PCE ,Force position counter error interrupt" "No effect,Forced"
line.word 0x04 "QCLR,EQEP Interrupt Clear Register"
bitfld.word 0x04 11. " UTO ,Clear unit time out interrupt flag" "No effect,Clears flag"
bitfld.word 0x04 10. " IEL ,Clear index event latch interrupt flag" "No effect,Clears flag"
bitfld.word 0x04 9. " SEL ,Clear strobe event latch interrupt flag" "No effect,Clears flag"
bitfld.word 0x04 8. " PCM ,Clear EQEP compare match event interrupt flag" "No effect,Clears flag"
newline
bitfld.word 0x04 7. " PCR ,Clear position-compare ready interrupt flag" "No effect,Clears flag"
bitfld.word 0x04 6. " PCO ,Clear position counter overflow interrupt flag" "No effect,Clears flag"
bitfld.word 0x04 5. " PCU ,Clear position counter underflow interrupt flag" "No effect,Clears flag"
bitfld.word 0x04 4. " WTO ,Clear watchdog timeout interrupt flag" "No effect,Clears flag"
newline
bitfld.word 0x04 3. " QDC ,Clear quadrature direction change interrupt flag" "No effect,Clears flag"
bitfld.word 0x04 2. " PHE ,Clear quadrature phase error interrupt flag" "No effect,Clears flag"
bitfld.word 0x04 1. " PCE ,Clear position counter error interrupt flag" "No effect,Clears flag"
bitfld.word 0x04 0. " INT ,Global interrupt clear flag" "No effect,Clears flag"
line.word 0x06 "QCTMR,EQEP Capture Timer Register"
line.word 0x08 "QEPSTS,EQEP Status Register"
eventfld.word 0x08 7. " UPEVNT ,Unit position event flag" "Not detected,Detected"
rbitfld.word 0x08 6. " FIDF ,Direction on the first index marker" "Counter-clockwise rotation,Clockwise rotation"
newline
rbitfld.word 0x08 5. " QDF ,Quadrature direction flag" "Counter-clockwise rotation,Clockwise rotation"
rbitfld.word 0x08 4. " QDLF ,EQEP direction latch flag" "Counter-clockwise rotation,Clockwise rotation"
newline
eventfld.word 0x08 3. " COEF ,Capture overflow error flag" "Not occurred,Occurred"
eventfld.word 0x08 2. " CDEF ,Capture direction error flag" "Not occurred,Occurred"
newline
eventfld.word 0x08 1. " FIMF ,First index marker flag" "Not occurred,Occurred"
rbitfld.word 0x08 0. " PCEF ,Position counter error flag" "No error,Error"
line.word 0x0A "QCTMRLAT,EQEP Capture Timer Latch Register"
line.word 0x0C "QCPRD,EQEP Capture Period Register"
group.word 0x42++0x01
line.word 0x00 "QCPRDLAT,EQEP Capture Period Latch Register"
endif
sif cpuis("TMS570LS0232")||cpuis("TMS570LS0714*")||cpuis("TMS570LS0914*")
endian.le
endif
width 0x0B
tree.end
tree "eQEP 2"
base ad:0xFCF79A00
sif cpuis("TMS570LS0232")||cpuis("TMS570LS0714*")||cpuis("TMS570LS0914*")
endian.be
endif
width 10.
group.long 0x00++0x0F
line.long 0x00 "QPOSCNT,EQEP Position Counter Register"
line.long 0x04 "QPOSINIT,EQEP Position Counter Initialization Register"
line.long 0x08 "QPOSMAX,EQEP Maximum Position Count Register"
line.long 0x0C "QPOSCMP,EQEP Position-Compare Register"
rgroup.long 0x10++0x0B
line.long 0x00 "QPOSILAT,EQEP Index Position Latch Register"
line.long 0x04 "QPOSSLAT,EQEP Strobe Position Latch Register"
line.long 0x08 "QPOSLAT,EQEP Position Counter Latch Register"
group.long 0x1C++0x07
line.long 0x00 "QUTMR,EQEP Unit Timer Register"
line.long 0x04 "QUPRD,EQEP Register Unit Period Register"
newline
group.word 0x24++0x03
line.word 0x00 "QWDPRD,EQEP Watchdog Period Register"
line.word 0x02 "QWDTMR,EQEP Watchdog Timer Register"
sif cpu()=="RM57L843-ZWT"
group.word 0x28++0x07
line.word 0x00 "QDECCTL,EQEP Decoder Control Register"
bitfld.word 0x00 14.--15. " QSRC ,Position-counter source selection" "Quadrature count,Direction-count,UP count,DOWN count"
bitfld.word 0x00 13. " SOEN ,Sync output-enable" "Disabled,Enabled"
newline
bitfld.word 0x00 12. " SPSEL ,Sync output pin selection" "Index pin,Strobe pin"
bitfld.word 0x00 11. " XCR ,External clock rate" "2x resolution,1x resolution"
newline
bitfld.word 0x00 10. " SWAP ,Swap quadrature clock inputs" "Not swapped,Swapped"
bitfld.word 0x00 9. " IGATE ,Index pulse gating option" "Disable gating of index pulse,Gate the index pin with strobe"
newline
bitfld.word 0x00 8. " QAP ,QEPA input polarity" "No effect,Negates QEPA"
bitfld.word 0x00 7. " QBP ,QEPB input polarity" "No effect,Negates QEPB"
newline
bitfld.word 0x00 6. " QIP ,QEPI input polarity" "No effect,Negates QEPI"
bitfld.word 0x00 5. " QSP ,QEPS input polarity" "No effect,Negates QEPS"
line.word 0x02 "QEPCTL,EQEP Control Register"
bitfld.word 0x02 14.--15. " FREE/SOFT ,Emulation control bits" "Stopped,Continued,Unaffected,Unaffected"
bitfld.word 0x02 12.--13. " PCRM ,Position counter reset mode" "Index event,Maximum position,First index event,Unit time event"
newline
bitfld.word 0x02 10.--11. " SEI ,Strobe event initialization of position counter" "Disabled,Disabled,Rising edge,Clockwise direction"
bitfld.word 0x02 8.--9. " IEI ,Index event initialization of position counter" "Disabled,Disabled,Rising edge,Falling edge"
newline
bitfld.word 0x02 7. " SWI ,Software initialization of position counter" "Disabled,Enabled"
bitfld.word 0x02 6. " SEL ,Strobe event latch of position counter" "Rising edge,Rising/faling edge"
newline
bitfld.word 0x02 4.--5. " IEL ,Index event latch of position counter" ",Rising edge,Faling edge,Software index marker"
bitfld.word 0x02 3. " QPEN ,Quadrature position counter enable/software reset" "Reset,Enabled"
newline
bitfld.word 0x02 2. " QCLM ,EQEP capture latch mode" "Position counter read by CPU,Unit time out"
bitfld.word 0x02 1. " UTE ,EQEP unit timer enable" "Disabled,Enabled"
newline
bitfld.word 0x02 0. " WDE ,EQEP watchdog enable" "Disabled,Enabled"
line.word 0x04 "QCAPCTL,EQEP Capture Control Register"
bitfld.word 0x04 15. " CEN ,Enable EQEP capture" "Disabled,Enabled"
bitfld.word 0x04 4.--6. " CCPS ,EQEP capture timer clock prescaler" "VCLK/1,VCLK/2,VCLK/4,VCLK/8,VCLK/16,VCLK/32,VCLK/64,VCLK/128"
newline
bitfld.word 0x04 0.--3. " UPPS ,Unit position event prescaler" "QCLK/1,QCLK/2,QCLK/4,QCLK/8,QCLK/16,QCLK/32,QCLK/64,QCLK/128,QCLK/256,QCLK/512,QCLK/1024,QCLK/2048,?..."
line.word 0x06 "QPOSCTL,EQEP Position-Compare Control Register"
bitfld.word 0x06 15. " PCSHDW ,Position-compare shadow enable" "Disabled,Enabled"
bitfld.word 0x06 14. " PCLOAD ,Position-compare shadow load mode" "QPOSCNT = 0,QPOSCNT = QPOSCMP"
newline
bitfld.word 0x06 13. " PCPOL ,Polarity of sync output" "High,Low"
bitfld.word 0x06 12. " PCE ,Position-compare enable/disable" "Disabled,Enabled"
newline
hexmask.word 0x06 0.--11. 1. " PCSPW ,Select-position-compare sync output pulse width"
else
group.word 0x28++0x07
line.word 0x00 "QEPCTL,EQEP Control Register"
bitfld.word 0x00 14.--15. " FREE/SOFT ,Emulation control bits" "Stopped,Continued,Unaffected,Unaffected"
bitfld.word 0x00 12.--13. " PCRM ,Position counter reset mode" "Index event,Maximum position,First index event,Unit time event"
newline
bitfld.word 0x00 10.--11. " SEI ,Strobe event initialization of position counter" "Disabled,Disabled,Rising edge,Clockwise direction"
bitfld.word 0x00 8.--9. " IEI ,Index event initialization of position counter" "Disabled,Disabled,Rising edge,Falling edge"
newline
bitfld.word 0x00 7. " SWI ,Software initialization of position counter" "Disabled,Enabled"
bitfld.word 0x00 6. " SEL ,Strobe event latch of position counter" "Rising edge,Falling edge"
newline
bitfld.word 0x00 4.--5. " IEL ,Index event latch of position counter" ",Rising edge,Falling edge,Software index marker"
bitfld.word 0x00 3. " QPEN ,Quadrature position counter enable/software reset" "Reset,Enabled"
newline
bitfld.word 0x00 2. " QCLM ,EQEP capture latch mode" "Read by CPU,Unit time out"
bitfld.word 0x00 1. " UTE ,EQEP unit timer enable" "Disabled,Enabled"
newline
bitfld.word 0x00 0. " WDE ,EQEP watchdog enable" "Disabled,Enabled"
line.word 0x02 "QDECCTL,EQEP Decoder Control Register"
bitfld.word 0x02 14.--15. " QSRC ,Position-counter source selection" "Quadrature,Direction,UP,DOWN"
bitfld.word 0x02 13. " SOEN ,Sync output-enable" "Disabled,Enabled"
newline
bitfld.word 0x02 12. " SPSEL ,Sync output pin selection" "Index,Strobe"
bitfld.word 0x02 11. " XCR ,External clock rate" "2x resolution,1x resolution"
newline
bitfld.word 0x02 10. " SWAP ,Swap quadrature clock inputs" "Not swapped,Swapped"
bitfld.word 0x02 9. " IGATE ,Index pulse gating option enable" "Disable,Enabled"
newline
bitfld.word 0x02 8. " QAP ,QEPA input polarity" "No effect,Negates QEPA"
bitfld.word 0x02 7. " QBP ,QEPB input polarity" "No effect,Negates QEPB"
newline
bitfld.word 0x02 6. " QIP ,QEPI input polarity" "No effect,Negates QEPI"
bitfld.word 0x02 5. " QSP ,QEPS input polarity" "No effect,Negates QEPS"
line.word 0x04 "QPOSCTL,EQEP Position-Compare Control Register"
bitfld.word 0x04 15. " PCSHDW ,Position-compare shadow enable" "Disabled,Enabled"
bitfld.word 0x04 14. " PCLOAD ,Position-compare shadow load mode" "QPOSCNT = 0,QPOSCNT = QPOSCMP"
newline
bitfld.word 0x04 13. " PCPOL ,Polarity of sync output" "High,Low"
bitfld.word 0x04 12. " PCE ,Position-compare enable/disable" "Disabled,Enabled"
newline
hexmask.word 0x04 0.--11. 1. " PCSPW ,Select-position-compare sync output pulse width"
line.word 0x06 "QCAPCTL,EQEP Capture Control Register"
bitfld.word 0x06 15. " CEN ,Enable EQEP capture" "Disabled,Enabled"
bitfld.word 0x06 4.--6. " CCPS ,EQEP capture timer clock prescaler" "VCLK/1,VCLK/2,VCLK/4,VCLK/8,VCLK/16,VCLK/32,VCLK/64,VCLK/128"
newline
bitfld.word 0x06 0.--3. " UPPS ,Unit position event prescaler" "QCLK/1,QCLK/2,QCLK/4,QCLK/8,QCLK/16,QCLK/32,QCLK/64,QCLK/128,QCLK/256,QCLK/512,QCLK/1024,QCLK/2048,?..."
endif
newline
sif cpu()=="RM57L843-ZWT"
rgroup.word 0x32++0x01
line.word 0x00 "QFLG,EQEP Interrupt Flag Register"
bitfld.word 0x00 11. " UTO ,Unit time out interrupt" "Not generated,Generated"
bitfld.word 0x00 10. " IEL ,Index event latch interrupt" "Not generated,Generated"
bitfld.word 0x00 9. " SEL ,Strobe event latch interrupt" "Not generated,Generated"
bitfld.word 0x00 8. " PCM ,Position-compare match interrupt" "Not generated,Generated"
newline
bitfld.word 0x00 7. " PCR ,Position-compare ready interrupt" "Not generated,Generated"
bitfld.word 0x00 6. " PCO ,Position counter overflow interrupt" "Not generated,Generated"
bitfld.word 0x00 5. " PCU ,Position counter underflow interrupt" "Not generated,Generated"
bitfld.word 0x00 4. " WTO ,Watchdog time out interrupt" "Not generated,Generated"
newline
bitfld.word 0x00 3. " QDC ,Quadrature direction change interrupt" "Not generated,Generated"
bitfld.word 0x00 2. " PHE ,Quadrature phase error interrupt" "Not generated,Generated"
bitfld.word 0x00 1. " PCE ,Position counter error interrupt" "Not generated,Generated"
bitfld.word 0x00 0. " INT ,Global interrupt status flag" "Not generated,Generated"
group.word 0x30++0x01
line.word 0x00 "QEINT,EQEP Interrupt Enable Register"
bitfld.word 0x00 11. " UTO ,Unit time out interrupt enable" "Disabled,Enable"
bitfld.word 0x00 10. " IEL ,Index event latch interrupt enable" "Disabled,Enable"
bitfld.word 0x00 9. " SEL ,Strobe event latch interrupt enable" "Disabled,Enable"
bitfld.word 0x00 8. " PCM ,Position-compare match interrupt enable" "Disabled,Enable"
newline
bitfld.word 0x00 7. " PCR ,Position-compare ready interrupt enable" "Disabled,Enable"
bitfld.word 0x00 6. " PCO ,Position counter overflow interrupt enable" "Disabled,Enable"
bitfld.word 0x00 5. " PCU ,Position counter underflow interrupt enable" "Disabled,Enable"
bitfld.word 0x00 4. " WTO ,Watchdog time out interrupt enable" "Disabled,Enable"
newline
bitfld.word 0x00 3. " QDC ,Quadrature direction change interrupt enable" "Disabled,Enable"
bitfld.word 0x00 2. " QPE ,Quadrature phase error interrupt enable" "Disabled,Enable"
bitfld.word 0x00 1. " PCE ,Position counter error interrupt enable" "Disabled,Enable"
group.word 0x36++0x01
line.word 0x00 "QFRC,EQEP Interrupt Force Register"
bitfld.word 0x00 11. " UTO ,Force unit time out interrupt" "No effect,Forced"
bitfld.word 0x00 10. " IEL ,Force index event latch interrupt" "No effect,Forced"
bitfld.word 0x00 9. " SEL ,Force strobe event latch interrupt" "No effect,Forced"
bitfld.word 0x00 8. " PCM ,Force position-compare match interrupt" "No effect,Forced"
newline
bitfld.word 0x00 7. " PCR ,Force position-compare ready interrupt" "No effect,Forced"
bitfld.word 0x00 6. " PCO ,Force position counter overflow interrupt" "No effect,Forced"
bitfld.word 0x00 5. " PCU ,Force position counter underflow interrupt" "No effect,Forced"
bitfld.word 0x00 4. " WTO ,Force watchdog time out interrupt" "No effect,Forced"
newline
bitfld.word 0x00 3. " QDC ,Force quadrature direction change interrupt" "No effect,Forced"
bitfld.word 0x00 2. " PHE ,Force quadrature phase error interrupt" "No effect,Forced"
bitfld.word 0x00 1. " PCE ,Force position counter error interrupt" "No effect,Forced"
group.word 0x34++0x01
line.word 0x00 "QCLR,EQEP Interrupt Clear Register"
bitfld.word 0x00 11. " UTO ,Clear unit time out interrupt flag" "No effect,Clears flag"
bitfld.word 0x00 10. " IEL ,Clear index event latch interrupt flag" "No effect,Clears flag"
bitfld.word 0x00 9. " SEL ,Clear strobe event latch interrupt flag" "No effect,Clears flag"
bitfld.word 0x00 8. " PCM ,Clear EQEP compare match event interrupt flag" "No effect,Clears flag"
newline
bitfld.word 0x00 7. " PCR ,Clear position-compare ready interrupt flag" "No effect,Clears flag"
bitfld.word 0x00 6. " PCO ,Clear position counter overflow interrupt flag" "No effect,Clears flag"
bitfld.word 0x00 5. " PCU ,Clear position counter underflow interrupt flag" "No effect,Clears flag"
bitfld.word 0x00 4. " WTO ,Clear watchdog timeout interrupt flag" "No effect,Clears flag"
newline
bitfld.word 0x00 3. " QDC ,Clear quadrature direction change interrupt flag" "No effect,Clears flag"
bitfld.word 0x00 2. " PHE ,Clear quadrature phase error interrupt flag" "No effect,Clears flag"
bitfld.word 0x00 1. " PCE ,Clear position counter error interrupt flag" "No effect,Clears flag"
bitfld.word 0x00 0. " INT ,Global interrupt clear flag" "No effect,Clears flag"
group.word 0x3A++0x01
line.word 0x00 "QCTMR,EQEP Capture Timer Register"
group.word 0x38++0x01
line.word 0x00 "QEPSTS,EQEP Status Register"
eventfld.word 0x00 7. " UPEVNT ,Unit position event flag" "Not detected,Detected"
rbitfld.word 0x00 6. " FIDF ,Direction on the first index marker" "Counter-clockwise rotation,Clockwise rotation"
newline
rbitfld.word 0x00 5. " QDF ,Quadrature direction flag" "Counter-clockwise rotation,Clockwise rotation"
rbitfld.word 0x00 4. " QDLF ,EQEP direction latch flag" "Counter-clockwise rotation,Clockwise rotation"
newline
eventfld.word 0x00 3. " COEF ,Capture overflow error flag" "Not occurred,Occurred"
eventfld.word 0x00 2. " CDEF ,Capture direction error flag" "Not occurred,Occurred"
newline
eventfld.word 0x00 1. " FIMF ,First index marker flag" "Not occurred,Occurred"
rbitfld.word 0x00 0. " PCEF ,Position counter error flag" "No error,Error"
rgroup.word 0x3E++0x01
line.word 0x00 "QCTMRLAT,EQEP Capture Timer Latch Register"
group.word 0x3C++0x03
line.word 0x00 "QCPRD,EQEP Capture Period Register"
line.word 0x02 "QCPRDLAT,EQEP Capture Period Latch Register"
else
rgroup.word 0x30++0x01
line.word 0x00 "QFLG,EQEP Interrupt Flag Register"
bitfld.word 0x00 11. " UTO ,Unit time out interrupt" "Not generated,Generated"
bitfld.word 0x00 10. " IEL ,Index event latch interrupt" "Not generated,Generated"
bitfld.word 0x00 9. " SEL ,Strobe event latch interrupt" "Not generated,Generated"
bitfld.word 0x00 8. " PCM ,Position-compare match interrupt" "Not generated,Generated"
newline
bitfld.word 0x00 7. " PCR ,Position-compare ready interrupt" "Not generated,Generated"
bitfld.word 0x00 6. " PCO ,Position counter overflow interrupt" "Not generated,Generated"
bitfld.word 0x00 5. " PCU ,Position counter underflow interrupt" "Not generated,Generated"
bitfld.word 0x00 4. " WTO ,Watchdog time out interrupt" "Not generated,Generated"
newline
bitfld.word 0x00 3. " QDC ,Quadrature direction change interrupt" "Not generated,Generated"
bitfld.word 0x00 2. " PHE ,Quadrature phase error interrupt" "Not generated,Generated"
bitfld.word 0x00 1. " PCE ,Position counter error interrupt" "Not generated,Generated"
bitfld.word 0x00 0. " INT ,Global interrupt status flag" "Not generated,Generated"
group.word 0x32++0x0D
line.word 0x00 "QEINT,EQEP Interrupt Enable Register"
bitfld.word 0x00 11. " UTO ,Unit time out interrupt enable" "Disabled,Enable"
bitfld.word 0x00 10. " IEL ,Index event latch interrupt enable" "Disabled,Enable"
bitfld.word 0x00 9. " SEL ,Strobe event latch interrupt enable" "Disabled,Enable"
bitfld.word 0x00 8. " PCM ,Position-compare match interrupt enable" "Disabled,Enable"
newline
bitfld.word 0x00 7. " PCR ,Position-compare ready interrupt enable" "Disabled,Enable"
bitfld.word 0x00 6. " PCO ,Position counter overflow interrupt enable" "Disabled,Enable"
bitfld.word 0x00 5. " PCU ,Position counter underflow interrupt enable" "Disabled,Enable"
bitfld.word 0x00 4. " WTO ,Watchdog time out interrupt enable" "Disabled,Enable"
newline
bitfld.word 0x00 3. " QDC ,Quadrature direction change interrupt enable" "Disabled,Enable"
bitfld.word 0x00 2. " QPE ,Quadrature phase error interrupt enable" "Disabled,Enable"
bitfld.word 0x00 1. " PCE ,Position counter error interrupt enable" "Disabled,Enable"
line.word 0x02 "QFRC,EQEP Interrupt Force Register"
bitfld.word 0x02 11. " UTO ,Force unit time out interrupt" "No effect,Forced"
bitfld.word 0x02 10. " IEL ,Force index event latch interrupt" "No effect,Forced"
bitfld.word 0x02 9. " SEL ,Force strobe event latch interrupt" "No effect,Forced"
bitfld.word 0x02 8. " PCM ,Force position-compare match interrupt" "No effect,Forced"
newline
bitfld.word 0x02 7. " PCR ,Force position-compare ready interrupt" "No effect,Forced"
bitfld.word 0x02 6. " PCO ,Force position counter overflow interrupt" "No effect,Forced"
bitfld.word 0x02 5. " PCU ,Force position counter underflow interrupt" "No effect,Forced"
bitfld.word 0x02 4. " WTO ,Force watchdog time out interrupt" "No effect,Forced"
newline
bitfld.word 0x02 3. " QDC ,Force quadrature direction change interrupt" "No effect,Forced"
bitfld.word 0x02 2. " PHE ,Force quadrature phase error interrupt" "No effect,Forced"
bitfld.word 0x02 1. " PCE ,Force position counter error interrupt" "No effect,Forced"
line.word 0x04 "QCLR,EQEP Interrupt Clear Register"
bitfld.word 0x04 11. " UTO ,Clear unit time out interrupt flag" "No effect,Clears flag"
bitfld.word 0x04 10. " IEL ,Clear index event latch interrupt flag" "No effect,Clears flag"
bitfld.word 0x04 9. " SEL ,Clear strobe event latch interrupt flag" "No effect,Clears flag"
bitfld.word 0x04 8. " PCM ,Clear EQEP compare match event interrupt flag" "No effect,Clears flag"
newline
bitfld.word 0x04 7. " PCR ,Clear position-compare ready interrupt flag" "No effect,Clears flag"
bitfld.word 0x04 6. " PCO ,Clear position counter overflow interrupt flag" "No effect,Clears flag"
bitfld.word 0x04 5. " PCU ,Clear position counter underflow interrupt flag" "No effect,Clears flag"
bitfld.word 0x04 4. " WTO ,Clear watchdog timeout interrupt flag" "No effect,Clears flag"
newline
bitfld.word 0x04 3. " QDC ,Clear quadrature direction change interrupt flag" "No effect,Clears flag"
bitfld.word 0x04 2. " PHE ,Clear quadrature phase error interrupt flag" "No effect,Clears flag"
bitfld.word 0x04 1. " PCE ,Clear position counter error interrupt flag" "No effect,Clears flag"
bitfld.word 0x04 0. " INT ,Global interrupt clear flag" "No effect,Clears flag"
line.word 0x06 "QCTMR,EQEP Capture Timer Register"
line.word 0x08 "QEPSTS,EQEP Status Register"
eventfld.word 0x08 7. " UPEVNT ,Unit position event flag" "Not detected,Detected"
rbitfld.word 0x08 6. " FIDF ,Direction on the first index marker" "Counter-clockwise rotation,Clockwise rotation"
newline
rbitfld.word 0x08 5. " QDF ,Quadrature direction flag" "Counter-clockwise rotation,Clockwise rotation"
rbitfld.word 0x08 4. " QDLF ,EQEP direction latch flag" "Counter-clockwise rotation,Clockwise rotation"
newline
eventfld.word 0x08 3. " COEF ,Capture overflow error flag" "Not occurred,Occurred"
eventfld.word 0x08 2. " CDEF ,Capture direction error flag" "Not occurred,Occurred"
newline
eventfld.word 0x08 1. " FIMF ,First index marker flag" "Not occurred,Occurred"
rbitfld.word 0x08 0. " PCEF ,Position counter error flag" "No error,Error"
line.word 0x0A "QCTMRLAT,EQEP Capture Timer Latch Register"
line.word 0x0C "QCPRD,EQEP Capture Period Register"
group.word 0x42++0x01
line.word 0x00 "QCPRDLAT,EQEP Capture Period Latch Register"
endif
sif cpuis("TMS570LS0232")||cpuis("TMS570LS0714*")||cpuis("TMS570LS0914*")
endian.le
endif
width 0x0B
tree.end
tree.end
tree.open "ePWM (Enhanced Pulse Width Modulator)"
tree "eTPWM1"
base ad:0xFCF78C00
width 11.
tree "Time-Base Submodule Registers"
group.word 0x00++0x01
line.word 0x00 "TBSTS,Time-Base Status Register"
eventfld.word 0x00 2. " CTRMAX ,Time-Base Counter Max Latched Status Bit time-base counter maximum value" "Not reached,Reached"
eventfld.word 0x00 1. " SYNCI ,Input Synchronization Latched Status Bit external synchronization event" "Not occurred,Occurred"
rbitfld.word 0x00 0. " CTRDIR ,Time-Base Counter Direction Status Bit" "Down,Up"
if (((d.w(ad:0xFCF78C00+0x02))&0x30)==0x00)
group.word 0x02++0x03
line.word 0x00 "TBCTL,Time-Base Control Register"
bitfld.word 0x00 14.--15. " FREE/SOFT ,Emulation Mode Bits" "Stop after timer INC or DEC,Stop after whole cycle,Free run,Free run"
bitfld.word 0x00 13. " PHSDIR ,Phase Direction Bit" "Count down,Count up"
bitfld.word 0x00 10.--12. " CLKDIV ,Time-base Clock Prescale Bits" "/1,/2,/4,/8,/16,/32,/64,/128"
bitfld.word 0x00 7.--9. " HSPCLKDIV ,High Speed Time-base Clock Prescale Bits" "/1,/2,/4,/8,/8,/10,/12,/14"
textline " "
bitfld.word 0x00 6. " SWFSYNC ,Software Forced Synchronization Pulse" "No effect,Generated"
bitfld.word 0x00 4.--5. " SYNCOSEL ,Synchronization Output Select" "EPWMxSYNC,CTR = zero,CTR = CMPB,Disabled EPWMxSYNCO"
bitfld.word 0x00 3. " PRDLD ,Active Period Register Load From Shadow Register Select" "Not selected,Selected"
bitfld.word 0x00 2. " PHSEN ,Counter Register Load From Phase Register Enable" "Disabled,Enabled"
textline " "
bitfld.word 0x00 0.--1. " CTRMODE ,Counter Mode" "Up-count,Down-count,Up-down-count,Stop-freeze counter operation"
line.word 0x02 "TBPHS,Time-Base Phase Register"
else
group.word 0x02++0x03
line.word 0x00 "TBCTL,Time-Base Control Register"
bitfld.word 0x00 14.--15. " FREE/SOFT ,Emulation Mode Bits" "Stop after timer INC or DEC,Stop after whole cycle,Free run,Free run"
bitfld.word 0x00 13. " PHSDIR ,Phase Direction Bit" "Count down,Count up"
bitfld.word 0x00 10.--12. " CLKDIV ,Time-base Clock Prescale Bits" "/1,/2,/4,/8,/16,/32,/64,/128"
bitfld.word 0x00 7.--9. " HSPCLKDIV ,High Speed Time-base Clock Prescale Bits" "/1,/2,/4,/8,/8,/10,/12,/14"
textline " "
bitfld.word 0x00 6. " SWFSYNC ,Software Forced Synchronization Pulse" "No effect,Generated"
bitfld.word 0x00 3. " PRDLD ,Active Period Register Load From Shadow Register Select" "Not selected,Selected"
bitfld.word 0x00 2. " PHSEN ,Counter Register Load From Phase Register Enable" "Disabled,Enabled"
bitfld.word 0x00 0.--1. " CTRMODE ,Counter Mode" "Up-count,Down-count,Up-down-count,Stop-freeze counter operation"
line.word 0x02 "TBPHS, Time-Base Phase Register"
endif
group.word 0x08++0x03
line.word 0x00 "TBPRD,Time-Base Period Register"
line.word 0x02 "TBCTR,Time-Base Counter Register"
tree.end
tree "Counter-Compare Submodule Registers"
width 8.
group.word 0x0C++0x01
line.word 0x00 "CMPCTL,Counter-Compare Control Register"
rbitfld.word 0x00 9. " SHDWBFULL ,Counter-compare B CMPB Shadow Register Full Status Flag" "Not full,Full"
rbitfld.word 0x00 8. " SHDWAFULL ,Counter-compare A CMPA Shadow Register Full Status Flag" "Not full,Full"
bitfld.word 0x00 6. " SHDWBMODE ,Counter-compare B" "Shadow mode,Immediate mode"
textline " "
bitfld.word 0x00 4. " SHDWAMODE ,Counter-compare A CMPA Register Operating Mode" "Shadow mode,Immediate mode"
bitfld.word 0x00 2.--3. " LOADBMODE ,Active Counter-Compare B CMPB Load From Shadow Select Mode" "CTR=0,CTR=PRD,CTR=0/CTR=PRD,Freeze"
bitfld.word 0x00 0.--1. " LOADAMODE ,Active Counter-Compare A CMPA Load From Shadow Select Mode" "CTR=0,CTR=PRD,CTR=0/CTR=PRD,Freeze"
group.word 0x10++0x01
line.word 0x00 "CMPA,Counter-Compare A Register"
group.word 0x16++0x01
line.word 0x00 "CMPB,Counter-Compare B Register"
tree.end
tree "Action-Qualifier Submodule Registers"
width 9.
group.word 0x14++0x01
line.word 0x00 "AQCTLA,Action-Qualifier Control Register for Output A (EPWMxA)"
bitfld.word 0x00 10.--11. " CBD ,Action when the time-base counter equals the active CMPB register and the counter is decrementing" "Disabled,Cleared,Set,Toggled"
bitfld.word 0x00 8.--9. " CBU ,Action when the counter equals the active CMPB register and the counter is incrementing" "Disabled,Cleared,Set,Toggled"
bitfld.word 0x00 6.--7. " CAD ,Action when the counter equals the active CMPA register and the counter is decrementing" "Disabled,Cleared,Set,Toggled"
textline " "
bitfld.word 0x00 4.--5. " CAU ,Action when the counter equals the active CMPA register and the counter is incrementing" "Disabled,Cleared,Set,Toggled"
bitfld.word 0x00 2.--3. " PRD ,Action when the counter equals the period" "Disabled,Cleared,Set,Toggled"
bitfld.word 0x00 0.--1. " ZRO ,Action when counter equals zero" "Disabled,Cleared,Set,Toggled"
group.word 0x18++0x01
line.word 0x00 "AQSFRC,Action-Qualifier Software Force Register"
bitfld.word 0x00 6.--7. " RLDCSF ,AQCSFRC Active Register Reload From Shadow Options" "Zero,Period,Zero or Period,Immediately"
bitfld.word 0x00 5. " OTSFB ,One-Time Software Forced Event on Output B" "No effect,Forced"
bitfld.word 0x00 3.--4. " ACTSFB ,Action when One-Time Software Force B Is invoked" "Disabled,Cleared,Set,Toggled"
textline " "
bitfld.word 0x00 2. " OTSFA ,One-Time Software Forced Event on Output A" "No effect,Forced"
bitfld.word 0x00 0.--1. " ACTSFA ,Action When One-Time Software Force A Is Invoked" "Disabled,Cleared,Set,Toggled"
group.word 0x1A++0x01
line.word 0x00 "AQCTLB,Action-Qualifier Control Register for Output B (EPWMxB)"
bitfld.word 0x00 10.--11. " CBD ,Action when the time-base counter equals the active CMPB register and the counter is decrementing" "Disabled,Cleared,Set,Toggled"
bitfld.word 0x00 8.--9. " CBU ,Action when the counter equals the active CMPB register and the counter is incrementing" "Disabled,Cleared,Set,Toggled"
bitfld.word 0x00 6.--7. " CAD ,Action when the counter equals the active CMPA register and the counter is decrementing" "Disabled,Cleared,Set,Toggled"
textline " "
bitfld.word 0x00 4.--5. " CAU ,Action when the counter equals the active CMPA register and the counter is incrementing" "Disabled,Cleared,Set,Toggled"
bitfld.word 0x00 2.--3. " PRD ,Action when the counter equals the period" "Disabled,Cleared,Set,Toggled"
bitfld.word 0x00 0.--1. " ZRO ,Action when counter equals zero" "Disabled,Cleared,Set,Toggled"
group.word 0x1E++0x01
line.word 0x00 "AQCSFRC,Action-Qualifier Continuous S/W Force Register Set"
bitfld.word 0x00 2.--3. " CSFB ,Continuous Software Force on Output B" "Forced disabled,Continued low,Continued high,Soft forced disabled"
bitfld.word 0x00 0.--1. " CSFA ,Continuous Software Force on Output A" "Forced disabled,Continued low,Continued high,Soft forced disabled"
tree.end
tree "Dead-Band Generator Submodule Registers"
width 7.
group.word 0x1C++0x01
line.word 0x00 "DBCTL,Dead-Band Generator Control Register"
bitfld.word 0x00 15. " HALFCYCLE ,Half Cycle Clocking Enable Bit" "Disabled,Enabled"
bitfld.word 0x00 4.--5. " IN_MODE ,Dead Band Input Mode Control" "EPWMxA Faling&rising,EPWMxB rising / EPWMxA falling,EPWMxA rising / EPWMxB falling,EPWMxB rising&falling"
bitfld.word 0x00 2.--3. " POLSEL ,Polarity Select Control" "AH,ALC,AHC,AL"
bitfld.word 0x00 0.--1. " OUT_MODE ,Dead-band Output Mode Control" "Dead-band generation bypassed,Disabled rising-edge delay,Rising-edge delayed signal on EPWMxA,Dead-band fully enabled"
group.word 0x20++0x03
line.word 0x00 "DBFED,Dead-Band Generator Falling Edge Delay Count Register"
hexmask.word 0x00 0.--9. 1. " DEL ,Falling Edge Delay Count"
line.word 0x02 "DBRED,Dead-Band Generator Rising Edge Delay Count Register"
hexmask.word 0x02 0.--9. 1. " DEL ,Rising Edge Delay Count"
tree.end
tree "Trip-Zone Submodule Registers"
group.word 0x24++0x03
line.word 0x00 "TZDCSEL,Trip Zone Digital Compare Event Select Register"
bitfld.word 0x00 9.--11. " DCBEVT2 ,Digital Compare Output B Event 2 Selection (DCBH/DCBL)" "Disabled,Low / Don't care,High / Don't care,Don't care / Low,Don't care / High,Low / High,?..."
bitfld.word 0x00 6.--8. " DCBEVT1 ,Digital Compare Output B Event 1 Selection (DCBH/DCBL)" "Disabled,Low / Don't care,High / Don't care,Don't care / Low,Don't care / High,Low / High,?..."
textline " "
bitfld.word 0x00 3.--5. " DCAEVT2 ,Digital Compare Output A Event 2 Selection (DCAH/DCAL)" "Disabled,Low / Don't care,High / Don't care,Don't care / Low,Don't care / High,Low / High,?..."
bitfld.word 0x00 0.--2. " DCAEVT1 ,Digital Compare Output A Event 1 Selection (DCAH/DCAL)" "Disabled,Low / Don't care,High / Don't care,Don't care / Low,Don't care / High,Low / High,?..."
line.word 0x02 "TZSEL,Trip-Zone Select Register"
rbitfld.word 0x02 15. " DCBEVT1 ,Digital Compare Output B Event 1 Select" "Disabled,Enabled"
rbitfld.word 0x02 14. " DCAEVT1 ,Digital Compare Output A Event 1 Select" "Disabled,Enabled"
bitfld.word 0x02 13. " OSHT6 ,Trip-zone 6 (/TZ6) Select" "Disabled,Enabled"
textline " "
bitfld.word 0x02 12. " OSHT5 ,Trip-zone 5 (/TZ5) Select" "Disabled,Enabled"
bitfld.word 0x02 11. " OSHT4 ,Trip-zone 4 (/TZ4) Select" "Disabled,Enabled"
bitfld.word 0x02 10. " OSHT3 ,Trip-zone 3 (/TZ3) Select" "Disabled,Enabled"
textline " "
bitfld.word 0x02 9. " OSHT2 ,Trip-zone 2 (/TZ2) Select" "Disabled,Enabled"
bitfld.word 0x02 8. " OSHT1 ,Trip-zone 1 (/TZ1) Select" "Disabled,Enabled"
rbitfld.word 0x02 7. " DCBEVT2 ,Digital Compare Output B Event 2 Select" "Disabled,Enabled"
textline " "
rbitfld.word 0x02 6. " DCAEVT2 ,Digital Compare Output A Event 2 Select" "Disabled,Enabled"
bitfld.word 0x02 5. " CBC6 ,Trip-zone 6 (/TZ6) Select" "Disabled,Enabled"
bitfld.word 0x02 4. " CBC5 ,Trip-zone 5 (/TZ5) Select" "Disabled,Enabled"
textline " "
bitfld.word 0x02 3. " CBC4 ,Trip-zone 4 (/TZ4) Select" "Disabled,Enabled"
bitfld.word 0x02 2. " CBC3 ,Trip-zone 3 (/TZ3) Select" "Disabled,Enabled"
bitfld.word 0x02 1. " CBC2 ,Trip-zone 2 (/TZ2) Select" "Disabled,Enabled"
textline " "
bitfld.word 0x02 0. " CBC1 ,Trip-zone 1 (/TZ1) Select" "Disabled,Enabled"
group.word 0x28++0x01
line.word 0x00 "TZEINT,Trip-Zone Enable Interrupt Register"
bitfld.word 0x00 6. " DCBEVT2 ,Digital Comparator Output B Event 2 Interrupt Enable" "Disabled,Enabled"
bitfld.word 0x00 5. " DCBEVT1 ,Digital Comparator Output B Event 1 Interrupt Enable" "Disabled,Enabled"
bitfld.word 0x00 4. " DCAEVT2 ,Digital Comparator Output A Event 2 Interrupt Enable" "Disabled,Enabled"
textline " "
bitfld.word 0x00 3. " DCAEVT1 ,Digital Comparator Output A Event 1 Interrupt Enable" "Disabled,Enabled"
bitfld.word 0x00 2. " OST ,Trip-zone One-Shot Interrupt Enable" "Disabled,Enabled"
bitfld.word 0x00 1. " CBC ,Trip-zone Cycle-by-Cycle Interrupt Enable" "Disabled,Enabled"
group.word 0x2A++0x01
line.word 0x00 "TZCTL,Trip-Zone Control Register"
bitfld.word 0x00 10.--11. " DCBEVT2 ,Digital Compare Output B Event 2 Action On EPWMxB" "High-impedance,Forced high state,Forced low state,Disabled"
bitfld.word 0x00 8.--9. " DCBEVT1 ,Digital Compare Output B Event 1 Action On EPWMxB" "High-impedance,Forced high state,Forced low state,Disabled"
textline " "
bitfld.word 0x00 6.--7. " DCAEVT2 ,Digital Compare Output A Event 2 Action On EPWMxA" "High-impedance,Forced high state,Forced low state,Disabled"
bitfld.word 0x00 4.--5. " DCAEVT1 ,Digital Compare Output A Event 1 Action On EPWMxA" "High-impedance,Forced high state,Forced low state,Disabled"
textline " "
bitfld.word 0x00 2.--3. " TZB ,When a trip event occurs the following action is taken on output EPWMxB" "High-impedance,Forced high state,Forced low state,Disabled"
bitfld.word 0x00 0.--1. " TZA ,When a trip event occurs the following action is taken on output EPWMxA" "High-impedance,Forced high state,Forced low state,Disabled"
textline " "
group.word 0x2E++0x01
line.word 0x00 "TZFLG,Trip-Zone Flag Register"
setclrfld.word 0x00 6. 0x04 6. -0x02 6. " DCBEVT2_set/clr ,Digital Comparator Output B Event 2 Interrupt" "Not occurred,Occurred"
setclrfld.word 0x00 5. 0x04 5. -0x02 5. " DCBEVT1_set/clr ,Digital Comparator Output B Event 1 Interrupt" "Not occurred,Occurred"
textline " "
setclrfld.word 0x00 4. 0x04 4. -0x02 4. " DCAEVT2_set/clr ,Digital Comparator Output A Event 2 Interrupt" "Not occurred,Occurred"
setclrfld.word 0x00 3. 0x04 3. -0x02 3. " DCAEVT1_set/clr ,Digital Comparator Output A Event 1 Interrupt" "Not occurred,Occurred"
textline " "
setclrfld.word 0x00 2. 0x04 2. -0x02 2. " OST_set/clr ,Trip-zone One-Shot Interrupt" "Not occurred,Occurred"
setclrfld.word 0x00 1. 0x04 1. -0x02 1. " CBC_set/clr ,Trip-zone Cycle-by-Cycle Interrupt" "Not occurred,Occurred"
textline " "
setclrfld.word 0x00 0. 0x04 0. -0x02 0. " INT_set/clr ,Latched Trip Interrupt Status Flag" "Not generated,Generated"
tree.end
tree "Event-Trigger Submodule Registers"
width 7.
group.word 0x30++0x01
line.word 0x00 "ETSEL,Event-Trigger Selection Register"
bitfld.word 0x00 15. " SOCBEN ,Enable the ADC Start of Conversion B EPWMxSOCB Pulse" "Disabled,Enabled"
bitfld.word 0x00 12.--14. " SOCBSEL ,EPWMxSOCB Selection Options" "DCBEVT1_soc,TB CNT equal to zero,TB CNT equal to period,TB CNT equal to zero or period,TB CNT equal to CMPA - Timer INC,TB CNT equal to CMPA - Timer DEC,TB CNT equal to CMPB - Timer INC,TB CNT equal to CMPB - Timer DEC"
bitfld.word 0x00 11. " SOCAEN ,Enable the ADC Start of Conversion A EPWMxSOCA Pulse" "Disabled,Enabled"
textline " "
bitfld.word 0x00 8.--10. " SOCASEL ,EPWMxSOCA Selection Options" "DCAEVT1_soc,TB CNT equal to zero,TB CNT equal to period,TB CNT equal to zero or period,TB CNT equal to CMPA - Timer INC,TB CNT equal to CMPA - Timer DEC,TB CNT equal to CMPB - Timer INC,TB CNT equal to CMPB - Timer DEC"
bitfld.word 0x00 3. " INTEN ,Enable ePWM Interrupt EPWMx_INT Generation" "Disabled,Enabled"
bitfld.word 0x00 0.--2. " INTSEL ,ePWM Interrupt EPWMx_INT Selection Options" ",TB CNT equal to zero,TB CNT equal to period,TB CNT equal to zero or period,TB CNT equal to CMPA - Timer INC,TB CNT equal to CMPA - Timer DEC,TB CNT equal to CMPB - Timer INC,TB CNT equal to CMPB - Timer DEC"
rgroup.word 0x34++0x01
line.word 0x00 "ETFLG,Event-Trigger Flag Register"
bitfld.word 0x00 3. " SOCB ,Latched ePWM ADC Start-of-Conversion B EPWMxSOCB Status Flag" "Not occurred,Occurred"
bitfld.word 0x00 2. " SOCA ,Latched ePWM ADC Start-of-Conversion A EPWMxSOCA Status Flag" "Not occurred,Occurred"
bitfld.word 0x00 0. " INT ,Latched ePWM Interrupt EPWMx_INT Status Flag" "Not occurred,Occurred"
group.word 0x36++0x01
line.word 0x00 "ETPS,Event-Trigger Pre-Scale Register"
rbitfld.word 0x00 14.--15. " SOCBCNT ,ePWM ADC Start-of-Conversion B Event EPWMxSOCB Counter Register" "No events,1 event,2 events,3 events"
bitfld.word 0x00 12.--13. " SOCBPRD ,ePWM ADC Start-of-Conversion B Event EPWMxSOCB Period Select" "Disabled,1st event,2nd event,3th event"
rbitfld.word 0x00 10.--11. " SOCACNT ,ePWM ADC Start-of-Conversion A Event EPWMxSOCA Counter Register" "No events,1 event,2 events,3 events"
textline " "
bitfld.word 0x00 8.--9. " SOCAPRD ,ePWM ADC Start-of-Conversion A Event EPWMxSOCA Period Select" "Disabled,1st event,2nd event,th event"
rbitfld.word 0x00 2.--3. " INTCNT ,ePWM Interrupt Event EPWMx_INT Counter Register" "No events,1 event,2 events,3 events"
bitfld.word 0x00 0.--1. " INTPRD ,ePWM Interrupt EPWMx_INT Period Select" "Disabled,1st event,2nd event,3th event"
group.word 0x38++0x01
line.word 0x00 "ETFRC,Event-Trigger Force Register"
bitfld.word 0x00 3. " SOCB ,SOCB Force Bit" "No effect,Forced"
bitfld.word 0x00 2. " SOCA ,SOCA Force Bit" "No effect,Forced"
bitfld.word 0x00 0. " INT ,INT Force Bit" "No effect,Forced"
group.word 0x3A++0x01
line.word 0x00 "ETCLR,Event-Trigger Clear Register"
bitfld.word 0x00 3. " SOCB ,ePWM ADC Start-of-Conversion B EPWMxSOCB Flag Clear Bit" "No effect,Cleared"
bitfld.word 0x00 2. " SOCA ,ePWM ADC Start-of-Conversion A EPWMxSOCB Flag Clear Bit" "No effect,Cleared"
bitfld.word 0x00 0. " INT ,ePWM Interrupt EPWMx_INT Flag Clear Bit" "No effect,Cleared"
tree.end
tree "PWM-Chopper Submodule Registers"
width 7.
group.word 0x3E++0x01
line.word 0x00 "PCCTL,PWM-Chopper Control Register"
bitfld.word 0x00 8.--10. " CHPDUTY ,Chopping Clock Duty Cycle" "1/8,2/8,3/8,4/8,5/8,6/8,7/8,?..."
bitfld.word 0x00 5.--7. " CHPFREQ ,Chopping Clock Frequency" "/1,/2,/3,/4,/5,/6,/7,/8"
bitfld.word 0x00 1.--4. " OSHTWTH ,One-Shot Pulse Width" "1 x VCLK3 / 8 wide,2 x VCLK3 / 8 wide,3 x VCLK3 / 8 wide,4 x VCLK3 / 8 wide,5 x VCLK3 / 8 wide,6 x VCLK3 / 8 wide,7 x VCLK3 / 8 wide,8 x VCLK3 / 8 wide,9 x VCLK3 / 8 wide,10 x VCLK3 / 8 wide,11 x VCLK3 / 8 wide,12 x VCLK3 / 8 wide,13 x VCLK3 / 8 wide,14 x VCLK3 / 8 wide,15 x VCLK3 / 8 wide,16 x VCLK3 / 8 wide"
textline " "
bitfld.word 0x00 0. " CHPEN ,PWM-chopping Enable" "Disabled,Enabled"
tree.end
tree "Digital Compare Event Registers"
width 14.
group.word 0x60++0x07
line.word 0x00 "DCACTL,Digital Compare A Control Register"
bitfld.word 0x00 9. " EVT2FRC_SYNCSEL ,DCAEVT2 Force Synchronization Signal Select" "Synchronous,Asynchronous"
bitfld.word 0x00 8. " EVT2SRCSEL ,DCAEVT2 Source Signal Select" "DCAEVT2,DCEVTFILT"
bitfld.word 0x00 3. " EVT1SYNCE ,DCAEVT1 SYNC Generation" "Disabled,Enabled"
textline " "
bitfld.word 0x00 2. " EVT1SOCE ,DCAEVT1 SOC Generation" "Disabled,Enabled"
bitfld.word 0x00 1. " EVT1FRC_SYNCSEL ,DCAEVT1 Force Synchronization Signal Select" "Synchronous,Asynchronous"
bitfld.word 0x00 0. " EVT1SRCSEL ,DCAEVT1 Source Signal Select" "DCAEVT,DCEVTFILT"
line.word 0x02 "DCTRIPSEL,Digital Compare Trip Select Register"
bitfld.word 0x02 12.--15. " DCBLCOMPSEL ,Digital Compare B Low Input Select" "TZ1 input,TZ2 input,TZ3 input,?..."
bitfld.word 0x02 8.--11. " DCBHCOMPSEL ,Digital Compare B High Input Select" "TZ1 input,TZ2 input,TZ3 input,?..."
bitfld.word 0x02 4.--7. " DCALCOMPSEL ,Digital Compare A Low Input Select" "TZ1 input,TZ2 input,TZ3 input,?..."
textline " "
bitfld.word 0x02 0.--3. " DCAHCOMPSEL ,Digital Compare A High Input Select" "TZ1 input,TZ2 input,TZ3 input,?..."
line.word 0x04 "DCFCTL,Digital Compare Filter Control Register"
bitfld.word 0x04 4.--5. " PULSESEL ,Pulse Select For Blanking & Capture Alignment" "TB CNT Equal to period,TB CNT Equal to zero,?..."
bitfld.word 0x04 3. " BLANKINV ,Blanking Window Inversion" "Not inverted,Inverted"
bitfld.word 0x04 2. " BLANKE ,Blanking Window Enable/Disable" "Disabled,Enabled"
textline " "
bitfld.word 0x04 0.--1. " SRCSEL ,Filter Block Signal Source Select" "DCAEVT1,DCAEVT2,DCBEVT1,DCBEVT2"
line.word 0x06 "DCBCTL,Digital Compare B Control Register"
bitfld.word 0x06 9. " EVT2FRC_SYNCSEL ,DCBEVT2 Force Synchronization Signal Select" "Synchronous,Asynchronous"
bitfld.word 0x06 8. " EVT2SRCSEL ,DCBEVT2 Source Signal Select" "DCBEVT2,DCEVTFILT"
bitfld.word 0x06 3. " EVT1SYNCE ,DCBEVT1 SYNC Generation" "Disabled,Enabled"
textline " "
bitfld.word 0x06 2. " EVT1SOCE ,DCBEVT1 SOC Generation" "Disabled,Enabled"
bitfld.word 0x06 1. " EVT1FRC_SYNCSEL ,DCBEVT1 Force Synchronization Signal Select" "Synchronous,Asynchronous"
bitfld.word 0x06 0. " EVT1SRCSEL ,DCBEVT1 Source Signal Select" "DCBEVT,DCEVTFILT"
rgroup.word 0x68++0x01
line.word 0x00 "DCOFFSET,Digital Compare Filter Offset Register"
group.word 0x6A++0x03
line.word 0x00 "DCCAPCTL,Digital Compare Capture Control Register"
bitfld.word 0x00 1. " SHDWMODE ,TBCTR Counter Capture Shadow Select Mode" "Shadow mode,Active Mode"
bitfld.word 0x00 0. " CAPE ,TBCTR Counter Capture Enable/Disable" "Disabled,Enabled"
line.word 0x02 "DCFWINDOW,Digital Compare Filter Window Register"
hexmask.word.byte 0x02 0.--7. 1. " WINDOW ,Blanking Window Width"
rgroup.word 0x6C++0x07
line.word 0x02 "DCOFFSETCNT, Digital Compare Filter Offset Counter Register"
line.word 0x04 "DCCAP, Digital Compare Counter Capture Register"
line.word 0x06 "DCFWINDOWCNT, Digital Compare Filter Window Counter Register"
hexmask.word.byte 0x06 0.--7. 1. " WINDOWCNT ,Digital Compare Filter Window Counter Register"
tree.end
width 0xB
tree.end
tree "eTPWM2"
base ad:0xFCF78D00
width 11.
tree "Time-Base Submodule Registers"
group.word 0x00++0x01
line.word 0x00 "TBSTS,Time-Base Status Register"
eventfld.word 0x00 2. " CTRMAX ,Time-Base Counter Max Latched Status Bit time-base counter maximum value" "Not reached,Reached"
eventfld.word 0x00 1. " SYNCI ,Input Synchronization Latched Status Bit external synchronization event" "Not occurred,Occurred"
rbitfld.word 0x00 0. " CTRDIR ,Time-Base Counter Direction Status Bit" "Down,Up"
if (((d.w(ad:0xFCF78D00+0x02))&0x30)==0x00)
group.word 0x02++0x03
line.word 0x00 "TBCTL,Time-Base Control Register"
bitfld.word 0x00 14.--15. " FREE/SOFT ,Emulation Mode Bits" "Stop after timer INC or DEC,Stop after whole cycle,Free run,Free run"
bitfld.word 0x00 13. " PHSDIR ,Phase Direction Bit" "Count down,Count up"
bitfld.word 0x00 10.--12. " CLKDIV ,Time-base Clock Prescale Bits" "/1,/2,/4,/8,/16,/32,/64,/128"
bitfld.word 0x00 7.--9. " HSPCLKDIV ,High Speed Time-base Clock Prescale Bits" "/1,/2,/4,/8,/8,/10,/12,/14"
textline " "
bitfld.word 0x00 6. " SWFSYNC ,Software Forced Synchronization Pulse" "No effect,Generated"
bitfld.word 0x00 4.--5. " SYNCOSEL ,Synchronization Output Select" "EPWMxSYNC,CTR = zero,CTR = CMPB,Disabled EPWMxSYNCO"
bitfld.word 0x00 3. " PRDLD ,Active Period Register Load From Shadow Register Select" "Not selected,Selected"
bitfld.word 0x00 2. " PHSEN ,Counter Register Load From Phase Register Enable" "Disabled,Enabled"
textline " "
bitfld.word 0x00 0.--1. " CTRMODE ,Counter Mode" "Up-count,Down-count,Up-down-count,Stop-freeze counter operation"
line.word 0x02 "TBPHS,Time-Base Phase Register"
else
group.word 0x02++0x03
line.word 0x00 "TBCTL,Time-Base Control Register"
bitfld.word 0x00 14.--15. " FREE/SOFT ,Emulation Mode Bits" "Stop after timer INC or DEC,Stop after whole cycle,Free run,Free run"
bitfld.word 0x00 13. " PHSDIR ,Phase Direction Bit" "Count down,Count up"
bitfld.word 0x00 10.--12. " CLKDIV ,Time-base Clock Prescale Bits" "/1,/2,/4,/8,/16,/32,/64,/128"
bitfld.word 0x00 7.--9. " HSPCLKDIV ,High Speed Time-base Clock Prescale Bits" "/1,/2,/4,/8,/8,/10,/12,/14"
textline " "
bitfld.word 0x00 6. " SWFSYNC ,Software Forced Synchronization Pulse" "No effect,Generated"
bitfld.word 0x00 3. " PRDLD ,Active Period Register Load From Shadow Register Select" "Not selected,Selected"
bitfld.word 0x00 2. " PHSEN ,Counter Register Load From Phase Register Enable" "Disabled,Enabled"
bitfld.word 0x00 0.--1. " CTRMODE ,Counter Mode" "Up-count,Down-count,Up-down-count,Stop-freeze counter operation"
line.word 0x02 "TBPHS, Time-Base Phase Register"
endif
group.word 0x08++0x03
line.word 0x00 "TBPRD,Time-Base Period Register"
line.word 0x02 "TBCTR,Time-Base Counter Register"
tree.end
tree "Counter-Compare Submodule Registers"
width 8.
group.word 0x0C++0x01
line.word 0x00 "CMPCTL,Counter-Compare Control Register"
rbitfld.word 0x00 9. " SHDWBFULL ,Counter-compare B CMPB Shadow Register Full Status Flag" "Not full,Full"
rbitfld.word 0x00 8. " SHDWAFULL ,Counter-compare A CMPA Shadow Register Full Status Flag" "Not full,Full"
bitfld.word 0x00 6. " SHDWBMODE ,Counter-compare B" "Shadow mode,Immediate mode"
textline " "
bitfld.word 0x00 4. " SHDWAMODE ,Counter-compare A CMPA Register Operating Mode" "Shadow mode,Immediate mode"
bitfld.word 0x00 2.--3. " LOADBMODE ,Active Counter-Compare B CMPB Load From Shadow Select Mode" "CTR=0,CTR=PRD,CTR=0/CTR=PRD,Freeze"
bitfld.word 0x00 0.--1. " LOADAMODE ,Active Counter-Compare A CMPA Load From Shadow Select Mode" "CTR=0,CTR=PRD,CTR=0/CTR=PRD,Freeze"
group.word 0x10++0x01
line.word 0x00 "CMPA,Counter-Compare A Register"
group.word 0x16++0x01
line.word 0x00 "CMPB,Counter-Compare B Register"
tree.end
tree "Action-Qualifier Submodule Registers"
width 9.
group.word 0x14++0x01
line.word 0x00 "AQCTLA,Action-Qualifier Control Register for Output A (EPWMxA)"
bitfld.word 0x00 10.--11. " CBD ,Action when the time-base counter equals the active CMPB register and the counter is decrementing" "Disabled,Cleared,Set,Toggled"
bitfld.word 0x00 8.--9. " CBU ,Action when the counter equals the active CMPB register and the counter is incrementing" "Disabled,Cleared,Set,Toggled"
bitfld.word 0x00 6.--7. " CAD ,Action when the counter equals the active CMPA register and the counter is decrementing" "Disabled,Cleared,Set,Toggled"
textline " "
bitfld.word 0x00 4.--5. " CAU ,Action when the counter equals the active CMPA register and the counter is incrementing" "Disabled,Cleared,Set,Toggled"
bitfld.word 0x00 2.--3. " PRD ,Action when the counter equals the period" "Disabled,Cleared,Set,Toggled"
bitfld.word 0x00 0.--1. " ZRO ,Action when counter equals zero" "Disabled,Cleared,Set,Toggled"
group.word 0x18++0x01
line.word 0x00 "AQSFRC,Action-Qualifier Software Force Register"
bitfld.word 0x00 6.--7. " RLDCSF ,AQCSFRC Active Register Reload From Shadow Options" "Zero,Period,Zero or Period,Immediately"
bitfld.word 0x00 5. " OTSFB ,One-Time Software Forced Event on Output B" "No effect,Forced"
bitfld.word 0x00 3.--4. " ACTSFB ,Action when One-Time Software Force B Is invoked" "Disabled,Cleared,Set,Toggled"
textline " "
bitfld.word 0x00 2. " OTSFA ,One-Time Software Forced Event on Output A" "No effect,Forced"
bitfld.word 0x00 0.--1. " ACTSFA ,Action When One-Time Software Force A Is Invoked" "Disabled,Cleared,Set,Toggled"
group.word 0x1A++0x01
line.word 0x00 "AQCTLB,Action-Qualifier Control Register for Output B (EPWMxB)"
bitfld.word 0x00 10.--11. " CBD ,Action when the time-base counter equals the active CMPB register and the counter is decrementing" "Disabled,Cleared,Set,Toggled"
bitfld.word 0x00 8.--9. " CBU ,Action when the counter equals the active CMPB register and the counter is incrementing" "Disabled,Cleared,Set,Toggled"
bitfld.word 0x00 6.--7. " CAD ,Action when the counter equals the active CMPA register and the counter is decrementing" "Disabled,Cleared,Set,Toggled"
textline " "
bitfld.word 0x00 4.--5. " CAU ,Action when the counter equals the active CMPA register and the counter is incrementing" "Disabled,Cleared,Set,Toggled"
bitfld.word 0x00 2.--3. " PRD ,Action when the counter equals the period" "Disabled,Cleared,Set,Toggled"
bitfld.word 0x00 0.--1. " ZRO ,Action when counter equals zero" "Disabled,Cleared,Set,Toggled"
group.word 0x1E++0x01
line.word 0x00 "AQCSFRC,Action-Qualifier Continuous S/W Force Register Set"
bitfld.word 0x00 2.--3. " CSFB ,Continuous Software Force on Output B" "Forced disabled,Continued low,Continued high,Soft forced disabled"
bitfld.word 0x00 0.--1. " CSFA ,Continuous Software Force on Output A" "Forced disabled,Continued low,Continued high,Soft forced disabled"
tree.end
tree "Dead-Band Generator Submodule Registers"
width 7.
group.word 0x1C++0x01
line.word 0x00 "DBCTL,Dead-Band Generator Control Register"
bitfld.word 0x00 15. " HALFCYCLE ,Half Cycle Clocking Enable Bit" "Disabled,Enabled"
bitfld.word 0x00 4.--5. " IN_MODE ,Dead Band Input Mode Control" "EPWMxA Faling&rising,EPWMxB rising / EPWMxA falling,EPWMxA rising / EPWMxB falling,EPWMxB rising&falling"
bitfld.word 0x00 2.--3. " POLSEL ,Polarity Select Control" "AH,ALC,AHC,AL"
bitfld.word 0x00 0.--1. " OUT_MODE ,Dead-band Output Mode Control" "Dead-band generation bypassed,Disabled rising-edge delay,Rising-edge delayed signal on EPWMxA,Dead-band fully enabled"
group.word 0x20++0x03
line.word 0x00 "DBFED,Dead-Band Generator Falling Edge Delay Count Register"
hexmask.word 0x00 0.--9. 1. " DEL ,Falling Edge Delay Count"
line.word 0x02 "DBRED,Dead-Band Generator Rising Edge Delay Count Register"
hexmask.word 0x02 0.--9. 1. " DEL ,Rising Edge Delay Count"
tree.end
tree "Trip-Zone Submodule Registers"
group.word 0x24++0x03
line.word 0x00 "TZDCSEL,Trip Zone Digital Compare Event Select Register"
bitfld.word 0x00 9.--11. " DCBEVT2 ,Digital Compare Output B Event 2 Selection (DCBH/DCBL)" "Disabled,Low / Don't care,High / Don't care,Don't care / Low,Don't care / High,Low / High,?..."
bitfld.word 0x00 6.--8. " DCBEVT1 ,Digital Compare Output B Event 1 Selection (DCBH/DCBL)" "Disabled,Low / Don't care,High / Don't care,Don't care / Low,Don't care / High,Low / High,?..."
textline " "
bitfld.word 0x00 3.--5. " DCAEVT2 ,Digital Compare Output A Event 2 Selection (DCAH/DCAL)" "Disabled,Low / Don't care,High / Don't care,Don't care / Low,Don't care / High,Low / High,?..."
bitfld.word 0x00 0.--2. " DCAEVT1 ,Digital Compare Output A Event 1 Selection (DCAH/DCAL)" "Disabled,Low / Don't care,High / Don't care,Don't care / Low,Don't care / High,Low / High,?..."
line.word 0x02 "TZSEL,Trip-Zone Select Register"
rbitfld.word 0x02 15. " DCBEVT1 ,Digital Compare Output B Event 1 Select" "Disabled,Enabled"
rbitfld.word 0x02 14. " DCAEVT1 ,Digital Compare Output A Event 1 Select" "Disabled,Enabled"
bitfld.word 0x02 13. " OSHT6 ,Trip-zone 6 (/TZ6) Select" "Disabled,Enabled"
textline " "
bitfld.word 0x02 12. " OSHT5 ,Trip-zone 5 (/TZ5) Select" "Disabled,Enabled"
bitfld.word 0x02 11. " OSHT4 ,Trip-zone 4 (/TZ4) Select" "Disabled,Enabled"
bitfld.word 0x02 10. " OSHT3 ,Trip-zone 3 (/TZ3) Select" "Disabled,Enabled"
textline " "
bitfld.word 0x02 9. " OSHT2 ,Trip-zone 2 (/TZ2) Select" "Disabled,Enabled"
bitfld.word 0x02 8. " OSHT1 ,Trip-zone 1 (/TZ1) Select" "Disabled,Enabled"
rbitfld.word 0x02 7. " DCBEVT2 ,Digital Compare Output B Event 2 Select" "Disabled,Enabled"
textline " "
rbitfld.word 0x02 6. " DCAEVT2 ,Digital Compare Output A Event 2 Select" "Disabled,Enabled"
bitfld.word 0x02 5. " CBC6 ,Trip-zone 6 (/TZ6) Select" "Disabled,Enabled"
bitfld.word 0x02 4. " CBC5 ,Trip-zone 5 (/TZ5) Select" "Disabled,Enabled"
textline " "
bitfld.word 0x02 3. " CBC4 ,Trip-zone 4 (/TZ4) Select" "Disabled,Enabled"
bitfld.word 0x02 2. " CBC3 ,Trip-zone 3 (/TZ3) Select" "Disabled,Enabled"
bitfld.word 0x02 1. " CBC2 ,Trip-zone 2 (/TZ2) Select" "Disabled,Enabled"
textline " "
bitfld.word 0x02 0. " CBC1 ,Trip-zone 1 (/TZ1) Select" "Disabled,Enabled"
group.word 0x28++0x01
line.word 0x00 "TZEINT,Trip-Zone Enable Interrupt Register"
bitfld.word 0x00 6. " DCBEVT2 ,Digital Comparator Output B Event 2 Interrupt Enable" "Disabled,Enabled"
bitfld.word 0x00 5. " DCBEVT1 ,Digital Comparator Output B Event 1 Interrupt Enable" "Disabled,Enabled"
bitfld.word 0x00 4. " DCAEVT2 ,Digital Comparator Output A Event 2 Interrupt Enable" "Disabled,Enabled"
textline " "
bitfld.word 0x00 3. " DCAEVT1 ,Digital Comparator Output A Event 1 Interrupt Enable" "Disabled,Enabled"
bitfld.word 0x00 2. " OST ,Trip-zone One-Shot Interrupt Enable" "Disabled,Enabled"
bitfld.word 0x00 1. " CBC ,Trip-zone Cycle-by-Cycle Interrupt Enable" "Disabled,Enabled"
group.word 0x2A++0x01
line.word 0x00 "TZCTL,Trip-Zone Control Register"
bitfld.word 0x00 10.--11. " DCBEVT2 ,Digital Compare Output B Event 2 Action On EPWMxB" "High-impedance,Forced high state,Forced low state,Disabled"
bitfld.word 0x00 8.--9. " DCBEVT1 ,Digital Compare Output B Event 1 Action On EPWMxB" "High-impedance,Forced high state,Forced low state,Disabled"
textline " "
bitfld.word 0x00 6.--7. " DCAEVT2 ,Digital Compare Output A Event 2 Action On EPWMxA" "High-impedance,Forced high state,Forced low state,Disabled"
bitfld.word 0x00 4.--5. " DCAEVT1 ,Digital Compare Output A Event 1 Action On EPWMxA" "High-impedance,Forced high state,Forced low state,Disabled"
textline " "
bitfld.word 0x00 2.--3. " TZB ,When a trip event occurs the following action is taken on output EPWMxB" "High-impedance,Forced high state,Forced low state,Disabled"
bitfld.word 0x00 0.--1. " TZA ,When a trip event occurs the following action is taken on output EPWMxA" "High-impedance,Forced high state,Forced low state,Disabled"
textline " "
group.word 0x2E++0x01
line.word 0x00 "TZFLG,Trip-Zone Flag Register"
setclrfld.word 0x00 6. 0x04 6. -0x02 6. " DCBEVT2_set/clr ,Digital Comparator Output B Event 2 Interrupt" "Not occurred,Occurred"
setclrfld.word 0x00 5. 0x04 5. -0x02 5. " DCBEVT1_set/clr ,Digital Comparator Output B Event 1 Interrupt" "Not occurred,Occurred"
textline " "
setclrfld.word 0x00 4. 0x04 4. -0x02 4. " DCAEVT2_set/clr ,Digital Comparator Output A Event 2 Interrupt" "Not occurred,Occurred"
setclrfld.word 0x00 3. 0x04 3. -0x02 3. " DCAEVT1_set/clr ,Digital Comparator Output A Event 1 Interrupt" "Not occurred,Occurred"
textline " "
setclrfld.word 0x00 2. 0x04 2. -0x02 2. " OST_set/clr ,Trip-zone One-Shot Interrupt" "Not occurred,Occurred"
setclrfld.word 0x00 1. 0x04 1. -0x02 1. " CBC_set/clr ,Trip-zone Cycle-by-Cycle Interrupt" "Not occurred,Occurred"
textline " "
setclrfld.word 0x00 0. 0x04 0. -0x02 0. " INT_set/clr ,Latched Trip Interrupt Status Flag" "Not generated,Generated"
tree.end
tree "Event-Trigger Submodule Registers"
width 7.
group.word 0x30++0x01
line.word 0x00 "ETSEL,Event-Trigger Selection Register"
bitfld.word 0x00 15. " SOCBEN ,Enable the ADC Start of Conversion B EPWMxSOCB Pulse" "Disabled,Enabled"
bitfld.word 0x00 12.--14. " SOCBSEL ,EPWMxSOCB Selection Options" "DCBEVT1_soc,TB CNT equal to zero,TB CNT equal to period,TB CNT equal to zero or period,TB CNT equal to CMPA - Timer INC,TB CNT equal to CMPA - Timer DEC,TB CNT equal to CMPB - Timer INC,TB CNT equal to CMPB - Timer DEC"
bitfld.word 0x00 11. " SOCAEN ,Enable the ADC Start of Conversion A EPWMxSOCA Pulse" "Disabled,Enabled"
textline " "
bitfld.word 0x00 8.--10. " SOCASEL ,EPWMxSOCA Selection Options" "DCAEVT1_soc,TB CNT equal to zero,TB CNT equal to period,TB CNT equal to zero or period,TB CNT equal to CMPA - Timer INC,TB CNT equal to CMPA - Timer DEC,TB CNT equal to CMPB - Timer INC,TB CNT equal to CMPB - Timer DEC"
bitfld.word 0x00 3. " INTEN ,Enable ePWM Interrupt EPWMx_INT Generation" "Disabled,Enabled"
bitfld.word 0x00 0.--2. " INTSEL ,ePWM Interrupt EPWMx_INT Selection Options" ",TB CNT equal to zero,TB CNT equal to period,TB CNT equal to zero or period,TB CNT equal to CMPA - Timer INC,TB CNT equal to CMPA - Timer DEC,TB CNT equal to CMPB - Timer INC,TB CNT equal to CMPB - Timer DEC"
rgroup.word 0x34++0x01
line.word 0x00 "ETFLG,Event-Trigger Flag Register"
bitfld.word 0x00 3. " SOCB ,Latched ePWM ADC Start-of-Conversion B EPWMxSOCB Status Flag" "Not occurred,Occurred"
bitfld.word 0x00 2. " SOCA ,Latched ePWM ADC Start-of-Conversion A EPWMxSOCA Status Flag" "Not occurred,Occurred"
bitfld.word 0x00 0. " INT ,Latched ePWM Interrupt EPWMx_INT Status Flag" "Not occurred,Occurred"
group.word 0x36++0x01
line.word 0x00 "ETPS,Event-Trigger Pre-Scale Register"
rbitfld.word 0x00 14.--15. " SOCBCNT ,ePWM ADC Start-of-Conversion B Event EPWMxSOCB Counter Register" "No events,1 event,2 events,3 events"
bitfld.word 0x00 12.--13. " SOCBPRD ,ePWM ADC Start-of-Conversion B Event EPWMxSOCB Period Select" "Disabled,1st event,2nd event,3th event"
rbitfld.word 0x00 10.--11. " SOCACNT ,ePWM ADC Start-of-Conversion A Event EPWMxSOCA Counter Register" "No events,1 event,2 events,3 events"
textline " "
bitfld.word 0x00 8.--9. " SOCAPRD ,ePWM ADC Start-of-Conversion A Event EPWMxSOCA Period Select" "Disabled,1st event,2nd event,th event"
rbitfld.word 0x00 2.--3. " INTCNT ,ePWM Interrupt Event EPWMx_INT Counter Register" "No events,1 event,2 events,3 events"
bitfld.word 0x00 0.--1. " INTPRD ,ePWM Interrupt EPWMx_INT Period Select" "Disabled,1st event,2nd event,3th event"
group.word 0x38++0x01
line.word 0x00 "ETFRC,Event-Trigger Force Register"
bitfld.word 0x00 3. " SOCB ,SOCB Force Bit" "No effect,Forced"
bitfld.word 0x00 2. " SOCA ,SOCA Force Bit" "No effect,Forced"
bitfld.word 0x00 0. " INT ,INT Force Bit" "No effect,Forced"
group.word 0x3A++0x01
line.word 0x00 "ETCLR,Event-Trigger Clear Register"
bitfld.word 0x00 3. " SOCB ,ePWM ADC Start-of-Conversion B EPWMxSOCB Flag Clear Bit" "No effect,Cleared"
bitfld.word 0x00 2. " SOCA ,ePWM ADC Start-of-Conversion A EPWMxSOCB Flag Clear Bit" "No effect,Cleared"
bitfld.word 0x00 0. " INT ,ePWM Interrupt EPWMx_INT Flag Clear Bit" "No effect,Cleared"
tree.end
tree "PWM-Chopper Submodule Registers"
width 7.
group.word 0x3E++0x01
line.word 0x00 "PCCTL,PWM-Chopper Control Register"
bitfld.word 0x00 8.--10. " CHPDUTY ,Chopping Clock Duty Cycle" "1/8,2/8,3/8,4/8,5/8,6/8,7/8,?..."
bitfld.word 0x00 5.--7. " CHPFREQ ,Chopping Clock Frequency" "/1,/2,/3,/4,/5,/6,/7,/8"
bitfld.word 0x00 1.--4. " OSHTWTH ,One-Shot Pulse Width" "1 x VCLK3 / 8 wide,2 x VCLK3 / 8 wide,3 x VCLK3 / 8 wide,4 x VCLK3 / 8 wide,5 x VCLK3 / 8 wide,6 x VCLK3 / 8 wide,7 x VCLK3 / 8 wide,8 x VCLK3 / 8 wide,9 x VCLK3 / 8 wide,10 x VCLK3 / 8 wide,11 x VCLK3 / 8 wide,12 x VCLK3 / 8 wide,13 x VCLK3 / 8 wide,14 x VCLK3 / 8 wide,15 x VCLK3 / 8 wide,16 x VCLK3 / 8 wide"
textline " "
bitfld.word 0x00 0. " CHPEN ,PWM-chopping Enable" "Disabled,Enabled"
tree.end
tree "Digital Compare Event Registers"
width 14.
group.word 0x60++0x07
line.word 0x00 "DCACTL,Digital Compare A Control Register"
bitfld.word 0x00 9. " EVT2FRC_SYNCSEL ,DCAEVT2 Force Synchronization Signal Select" "Synchronous,Asynchronous"
bitfld.word 0x00 8. " EVT2SRCSEL ,DCAEVT2 Source Signal Select" "DCAEVT2,DCEVTFILT"
bitfld.word 0x00 3. " EVT1SYNCE ,DCAEVT1 SYNC Generation" "Disabled,Enabled"
textline " "
bitfld.word 0x00 2. " EVT1SOCE ,DCAEVT1 SOC Generation" "Disabled,Enabled"
bitfld.word 0x00 1. " EVT1FRC_SYNCSEL ,DCAEVT1 Force Synchronization Signal Select" "Synchronous,Asynchronous"
bitfld.word 0x00 0. " EVT1SRCSEL ,DCAEVT1 Source Signal Select" "DCAEVT,DCEVTFILT"
line.word 0x02 "DCTRIPSEL,Digital Compare Trip Select Register"
bitfld.word 0x02 12.--15. " DCBLCOMPSEL ,Digital Compare B Low Input Select" "TZ1 input,TZ2 input,TZ3 input,?..."
bitfld.word 0x02 8.--11. " DCBHCOMPSEL ,Digital Compare B High Input Select" "TZ1 input,TZ2 input,TZ3 input,?..."
bitfld.word 0x02 4.--7. " DCALCOMPSEL ,Digital Compare A Low Input Select" "TZ1 input,TZ2 input,TZ3 input,?..."
textline " "
bitfld.word 0x02 0.--3. " DCAHCOMPSEL ,Digital Compare A High Input Select" "TZ1 input,TZ2 input,TZ3 input,?..."
line.word 0x04 "DCFCTL,Digital Compare Filter Control Register"
bitfld.word 0x04 4.--5. " PULSESEL ,Pulse Select For Blanking & Capture Alignment" "TB CNT Equal to period,TB CNT Equal to zero,?..."
bitfld.word 0x04 3. " BLANKINV ,Blanking Window Inversion" "Not inverted,Inverted"
bitfld.word 0x04 2. " BLANKE ,Blanking Window Enable/Disable" "Disabled,Enabled"
textline " "
bitfld.word 0x04 0.--1. " SRCSEL ,Filter Block Signal Source Select" "DCAEVT1,DCAEVT2,DCBEVT1,DCBEVT2"
line.word 0x06 "DCBCTL,Digital Compare B Control Register"
bitfld.word 0x06 9. " EVT2FRC_SYNCSEL ,DCBEVT2 Force Synchronization Signal Select" "Synchronous,Asynchronous"
bitfld.word 0x06 8. " EVT2SRCSEL ,DCBEVT2 Source Signal Select" "DCBEVT2,DCEVTFILT"
bitfld.word 0x06 3. " EVT1SYNCE ,DCBEVT1 SYNC Generation" "Disabled,Enabled"
textline " "
bitfld.word 0x06 2. " EVT1SOCE ,DCBEVT1 SOC Generation" "Disabled,Enabled"
bitfld.word 0x06 1. " EVT1FRC_SYNCSEL ,DCBEVT1 Force Synchronization Signal Select" "Synchronous,Asynchronous"
bitfld.word 0x06 0. " EVT1SRCSEL ,DCBEVT1 Source Signal Select" "DCBEVT,DCEVTFILT"
rgroup.word 0x68++0x01
line.word 0x00 "DCOFFSET,Digital Compare Filter Offset Register"
group.word 0x6A++0x03
line.word 0x00 "DCCAPCTL,Digital Compare Capture Control Register"
bitfld.word 0x00 1. " SHDWMODE ,TBCTR Counter Capture Shadow Select Mode" "Shadow mode,Active Mode"
bitfld.word 0x00 0. " CAPE ,TBCTR Counter Capture Enable/Disable" "Disabled,Enabled"
line.word 0x02 "DCFWINDOW,Digital Compare Filter Window Register"
hexmask.word.byte 0x02 0.--7. 1. " WINDOW ,Blanking Window Width"
rgroup.word 0x6C++0x07
line.word 0x02 "DCOFFSETCNT, Digital Compare Filter Offset Counter Register"
line.word 0x04 "DCCAP, Digital Compare Counter Capture Register"
line.word 0x06 "DCFWINDOWCNT, Digital Compare Filter Window Counter Register"
hexmask.word.byte 0x06 0.--7. 1. " WINDOWCNT ,Digital Compare Filter Window Counter Register"
tree.end
width 0xB
tree.end
tree "eTPWM3"
base ad:0xFCF78E00
width 11.
tree "Time-Base Submodule Registers"
group.word 0x00++0x01
line.word 0x00 "TBSTS,Time-Base Status Register"
eventfld.word 0x00 2. " CTRMAX ,Time-Base Counter Max Latched Status Bit time-base counter maximum value" "Not reached,Reached"
eventfld.word 0x00 1. " SYNCI ,Input Synchronization Latched Status Bit external synchronization event" "Not occurred,Occurred"
rbitfld.word 0x00 0. " CTRDIR ,Time-Base Counter Direction Status Bit" "Down,Up"
if (((d.w(ad:0xFCF78E00+0x02))&0x30)==0x00)
group.word 0x02++0x03
line.word 0x00 "TBCTL,Time-Base Control Register"
bitfld.word 0x00 14.--15. " FREE/SOFT ,Emulation Mode Bits" "Stop after timer INC or DEC,Stop after whole cycle,Free run,Free run"
bitfld.word 0x00 13. " PHSDIR ,Phase Direction Bit" "Count down,Count up"
bitfld.word 0x00 10.--12. " CLKDIV ,Time-base Clock Prescale Bits" "/1,/2,/4,/8,/16,/32,/64,/128"
bitfld.word 0x00 7.--9. " HSPCLKDIV ,High Speed Time-base Clock Prescale Bits" "/1,/2,/4,/8,/8,/10,/12,/14"
textline " "
bitfld.word 0x00 6. " SWFSYNC ,Software Forced Synchronization Pulse" "No effect,Generated"
bitfld.word 0x00 4.--5. " SYNCOSEL ,Synchronization Output Select" "EPWMxSYNC,CTR = zero,CTR = CMPB,Disabled EPWMxSYNCO"
bitfld.word 0x00 3. " PRDLD ,Active Period Register Load From Shadow Register Select" "Not selected,Selected"
bitfld.word 0x00 2. " PHSEN ,Counter Register Load From Phase Register Enable" "Disabled,Enabled"
textline " "
bitfld.word 0x00 0.--1. " CTRMODE ,Counter Mode" "Up-count,Down-count,Up-down-count,Stop-freeze counter operation"
line.word 0x02 "TBPHS,Time-Base Phase Register"
else
group.word 0x02++0x03
line.word 0x00 "TBCTL,Time-Base Control Register"
bitfld.word 0x00 14.--15. " FREE/SOFT ,Emulation Mode Bits" "Stop after timer INC or DEC,Stop after whole cycle,Free run,Free run"
bitfld.word 0x00 13. " PHSDIR ,Phase Direction Bit" "Count down,Count up"
bitfld.word 0x00 10.--12. " CLKDIV ,Time-base Clock Prescale Bits" "/1,/2,/4,/8,/16,/32,/64,/128"
bitfld.word 0x00 7.--9. " HSPCLKDIV ,High Speed Time-base Clock Prescale Bits" "/1,/2,/4,/8,/8,/10,/12,/14"
textline " "
bitfld.word 0x00 6. " SWFSYNC ,Software Forced Synchronization Pulse" "No effect,Generated"
bitfld.word 0x00 3. " PRDLD ,Active Period Register Load From Shadow Register Select" "Not selected,Selected"
bitfld.word 0x00 2. " PHSEN ,Counter Register Load From Phase Register Enable" "Disabled,Enabled"
bitfld.word 0x00 0.--1. " CTRMODE ,Counter Mode" "Up-count,Down-count,Up-down-count,Stop-freeze counter operation"
line.word 0x02 "TBPHS, Time-Base Phase Register"
endif
group.word 0x08++0x03
line.word 0x00 "TBPRD,Time-Base Period Register"
line.word 0x02 "TBCTR,Time-Base Counter Register"
tree.end
tree "Counter-Compare Submodule Registers"
width 8.
group.word 0x0C++0x01
line.word 0x00 "CMPCTL,Counter-Compare Control Register"
rbitfld.word 0x00 9. " SHDWBFULL ,Counter-compare B CMPB Shadow Register Full Status Flag" "Not full,Full"
rbitfld.word 0x00 8. " SHDWAFULL ,Counter-compare A CMPA Shadow Register Full Status Flag" "Not full,Full"
bitfld.word 0x00 6. " SHDWBMODE ,Counter-compare B" "Shadow mode,Immediate mode"
textline " "
bitfld.word 0x00 4. " SHDWAMODE ,Counter-compare A CMPA Register Operating Mode" "Shadow mode,Immediate mode"
bitfld.word 0x00 2.--3. " LOADBMODE ,Active Counter-Compare B CMPB Load From Shadow Select Mode" "CTR=0,CTR=PRD,CTR=0/CTR=PRD,Freeze"
bitfld.word 0x00 0.--1. " LOADAMODE ,Active Counter-Compare A CMPA Load From Shadow Select Mode" "CTR=0,CTR=PRD,CTR=0/CTR=PRD,Freeze"
group.word 0x10++0x01
line.word 0x00 "CMPA,Counter-Compare A Register"
group.word 0x16++0x01
line.word 0x00 "CMPB,Counter-Compare B Register"
tree.end
tree "Action-Qualifier Submodule Registers"
width 9.
group.word 0x14++0x01
line.word 0x00 "AQCTLA,Action-Qualifier Control Register for Output A (EPWMxA)"
bitfld.word 0x00 10.--11. " CBD ,Action when the time-base counter equals the active CMPB register and the counter is decrementing" "Disabled,Cleared,Set,Toggled"
bitfld.word 0x00 8.--9. " CBU ,Action when the counter equals the active CMPB register and the counter is incrementing" "Disabled,Cleared,Set,Toggled"
bitfld.word 0x00 6.--7. " CAD ,Action when the counter equals the active CMPA register and the counter is decrementing" "Disabled,Cleared,Set,Toggled"
textline " "
bitfld.word 0x00 4.--5. " CAU ,Action when the counter equals the active CMPA register and the counter is incrementing" "Disabled,Cleared,Set,Toggled"
bitfld.word 0x00 2.--3. " PRD ,Action when the counter equals the period" "Disabled,Cleared,Set,Toggled"
bitfld.word 0x00 0.--1. " ZRO ,Action when counter equals zero" "Disabled,Cleared,Set,Toggled"
group.word 0x18++0x01
line.word 0x00 "AQSFRC,Action-Qualifier Software Force Register"
bitfld.word 0x00 6.--7. " RLDCSF ,AQCSFRC Active Register Reload From Shadow Options" "Zero,Period,Zero or Period,Immediately"
bitfld.word 0x00 5. " OTSFB ,One-Time Software Forced Event on Output B" "No effect,Forced"
bitfld.word 0x00 3.--4. " ACTSFB ,Action when One-Time Software Force B Is invoked" "Disabled,Cleared,Set,Toggled"
textline " "
bitfld.word 0x00 2. " OTSFA ,One-Time Software Forced Event on Output A" "No effect,Forced"
bitfld.word 0x00 0.--1. " ACTSFA ,Action When One-Time Software Force A Is Invoked" "Disabled,Cleared,Set,Toggled"
group.word 0x1A++0x01
line.word 0x00 "AQCTLB,Action-Qualifier Control Register for Output B (EPWMxB)"
bitfld.word 0x00 10.--11. " CBD ,Action when the time-base counter equals the active CMPB register and the counter is decrementing" "Disabled,Cleared,Set,Toggled"
bitfld.word 0x00 8.--9. " CBU ,Action when the counter equals the active CMPB register and the counter is incrementing" "Disabled,Cleared,Set,Toggled"
bitfld.word 0x00 6.--7. " CAD ,Action when the counter equals the active CMPA register and the counter is decrementing" "Disabled,Cleared,Set,Toggled"
textline " "
bitfld.word 0x00 4.--5. " CAU ,Action when the counter equals the active CMPA register and the counter is incrementing" "Disabled,Cleared,Set,Toggled"
bitfld.word 0x00 2.--3. " PRD ,Action when the counter equals the period" "Disabled,Cleared,Set,Toggled"
bitfld.word 0x00 0.--1. " ZRO ,Action when counter equals zero" "Disabled,Cleared,Set,Toggled"
group.word 0x1E++0x01
line.word 0x00 "AQCSFRC,Action-Qualifier Continuous S/W Force Register Set"
bitfld.word 0x00 2.--3. " CSFB ,Continuous Software Force on Output B" "Forced disabled,Continued low,Continued high,Soft forced disabled"
bitfld.word 0x00 0.--1. " CSFA ,Continuous Software Force on Output A" "Forced disabled,Continued low,Continued high,Soft forced disabled"
tree.end
tree "Dead-Band Generator Submodule Registers"
width 7.
group.word 0x1C++0x01
line.word 0x00 "DBCTL,Dead-Band Generator Control Register"
bitfld.word 0x00 15. " HALFCYCLE ,Half Cycle Clocking Enable Bit" "Disabled,Enabled"
bitfld.word 0x00 4.--5. " IN_MODE ,Dead Band Input Mode Control" "EPWMxA Faling&rising,EPWMxB rising / EPWMxA falling,EPWMxA rising / EPWMxB falling,EPWMxB rising&falling"
bitfld.word 0x00 2.--3. " POLSEL ,Polarity Select Control" "AH,ALC,AHC,AL"
bitfld.word 0x00 0.--1. " OUT_MODE ,Dead-band Output Mode Control" "Dead-band generation bypassed,Disabled rising-edge delay,Rising-edge delayed signal on EPWMxA,Dead-band fully enabled"
group.word 0x20++0x03
line.word 0x00 "DBFED,Dead-Band Generator Falling Edge Delay Count Register"
hexmask.word 0x00 0.--9. 1. " DEL ,Falling Edge Delay Count"
line.word 0x02 "DBRED,Dead-Band Generator Rising Edge Delay Count Register"
hexmask.word 0x02 0.--9. 1. " DEL ,Rising Edge Delay Count"
tree.end
tree "Trip-Zone Submodule Registers"
group.word 0x24++0x03
line.word 0x00 "TZDCSEL,Trip Zone Digital Compare Event Select Register"
bitfld.word 0x00 9.--11. " DCBEVT2 ,Digital Compare Output B Event 2 Selection (DCBH/DCBL)" "Disabled,Low / Don't care,High / Don't care,Don't care / Low,Don't care / High,Low / High,?..."
bitfld.word 0x00 6.--8. " DCBEVT1 ,Digital Compare Output B Event 1 Selection (DCBH/DCBL)" "Disabled,Low / Don't care,High / Don't care,Don't care / Low,Don't care / High,Low / High,?..."
textline " "
bitfld.word 0x00 3.--5. " DCAEVT2 ,Digital Compare Output A Event 2 Selection (DCAH/DCAL)" "Disabled,Low / Don't care,High / Don't care,Don't care / Low,Don't care / High,Low / High,?..."
bitfld.word 0x00 0.--2. " DCAEVT1 ,Digital Compare Output A Event 1 Selection (DCAH/DCAL)" "Disabled,Low / Don't care,High / Don't care,Don't care / Low,Don't care / High,Low / High,?..."
line.word 0x02 "TZSEL,Trip-Zone Select Register"
rbitfld.word 0x02 15. " DCBEVT1 ,Digital Compare Output B Event 1 Select" "Disabled,Enabled"
rbitfld.word 0x02 14. " DCAEVT1 ,Digital Compare Output A Event 1 Select" "Disabled,Enabled"
bitfld.word 0x02 13. " OSHT6 ,Trip-zone 6 (/TZ6) Select" "Disabled,Enabled"
textline " "
bitfld.word 0x02 12. " OSHT5 ,Trip-zone 5 (/TZ5) Select" "Disabled,Enabled"
bitfld.word 0x02 11. " OSHT4 ,Trip-zone 4 (/TZ4) Select" "Disabled,Enabled"
bitfld.word 0x02 10. " OSHT3 ,Trip-zone 3 (/TZ3) Select" "Disabled,Enabled"
textline " "
bitfld.word 0x02 9. " OSHT2 ,Trip-zone 2 (/TZ2) Select" "Disabled,Enabled"
bitfld.word 0x02 8. " OSHT1 ,Trip-zone 1 (/TZ1) Select" "Disabled,Enabled"
rbitfld.word 0x02 7. " DCBEVT2 ,Digital Compare Output B Event 2 Select" "Disabled,Enabled"
textline " "
rbitfld.word 0x02 6. " DCAEVT2 ,Digital Compare Output A Event 2 Select" "Disabled,Enabled"
bitfld.word 0x02 5. " CBC6 ,Trip-zone 6 (/TZ6) Select" "Disabled,Enabled"
bitfld.word 0x02 4. " CBC5 ,Trip-zone 5 (/TZ5) Select" "Disabled,Enabled"
textline " "
bitfld.word 0x02 3. " CBC4 ,Trip-zone 4 (/TZ4) Select" "Disabled,Enabled"
bitfld.word 0x02 2. " CBC3 ,Trip-zone 3 (/TZ3) Select" "Disabled,Enabled"
bitfld.word 0x02 1. " CBC2 ,Trip-zone 2 (/TZ2) Select" "Disabled,Enabled"
textline " "
bitfld.word 0x02 0. " CBC1 ,Trip-zone 1 (/TZ1) Select" "Disabled,Enabled"
group.word 0x28++0x01
line.word 0x00 "TZEINT,Trip-Zone Enable Interrupt Register"
bitfld.word 0x00 6. " DCBEVT2 ,Digital Comparator Output B Event 2 Interrupt Enable" "Disabled,Enabled"
bitfld.word 0x00 5. " DCBEVT1 ,Digital Comparator Output B Event 1 Interrupt Enable" "Disabled,Enabled"
bitfld.word 0x00 4. " DCAEVT2 ,Digital Comparator Output A Event 2 Interrupt Enable" "Disabled,Enabled"
textline " "
bitfld.word 0x00 3. " DCAEVT1 ,Digital Comparator Output A Event 1 Interrupt Enable" "Disabled,Enabled"
bitfld.word 0x00 2. " OST ,Trip-zone One-Shot Interrupt Enable" "Disabled,Enabled"
bitfld.word 0x00 1. " CBC ,Trip-zone Cycle-by-Cycle Interrupt Enable" "Disabled,Enabled"
group.word 0x2A++0x01
line.word 0x00 "TZCTL,Trip-Zone Control Register"
bitfld.word 0x00 10.--11. " DCBEVT2 ,Digital Compare Output B Event 2 Action On EPWMxB" "High-impedance,Forced high state,Forced low state,Disabled"
bitfld.word 0x00 8.--9. " DCBEVT1 ,Digital Compare Output B Event 1 Action On EPWMxB" "High-impedance,Forced high state,Forced low state,Disabled"
textline " "
bitfld.word 0x00 6.--7. " DCAEVT2 ,Digital Compare Output A Event 2 Action On EPWMxA" "High-impedance,Forced high state,Forced low state,Disabled"
bitfld.word 0x00 4.--5. " DCAEVT1 ,Digital Compare Output A Event 1 Action On EPWMxA" "High-impedance,Forced high state,Forced low state,Disabled"
textline " "
bitfld.word 0x00 2.--3. " TZB ,When a trip event occurs the following action is taken on output EPWMxB" "High-impedance,Forced high state,Forced low state,Disabled"
bitfld.word 0x00 0.--1. " TZA ,When a trip event occurs the following action is taken on output EPWMxA" "High-impedance,Forced high state,Forced low state,Disabled"
textline " "
group.word 0x2E++0x01
line.word 0x00 "TZFLG,Trip-Zone Flag Register"
setclrfld.word 0x00 6. 0x04 6. -0x02 6. " DCBEVT2_set/clr ,Digital Comparator Output B Event 2 Interrupt" "Not occurred,Occurred"
setclrfld.word 0x00 5. 0x04 5. -0x02 5. " DCBEVT1_set/clr ,Digital Comparator Output B Event 1 Interrupt" "Not occurred,Occurred"
textline " "
setclrfld.word 0x00 4. 0x04 4. -0x02 4. " DCAEVT2_set/clr ,Digital Comparator Output A Event 2 Interrupt" "Not occurred,Occurred"
setclrfld.word 0x00 3. 0x04 3. -0x02 3. " DCAEVT1_set/clr ,Digital Comparator Output A Event 1 Interrupt" "Not occurred,Occurred"
textline " "
setclrfld.word 0x00 2. 0x04 2. -0x02 2. " OST_set/clr ,Trip-zone One-Shot Interrupt" "Not occurred,Occurred"
setclrfld.word 0x00 1. 0x04 1. -0x02 1. " CBC_set/clr ,Trip-zone Cycle-by-Cycle Interrupt" "Not occurred,Occurred"
textline " "
setclrfld.word 0x00 0. 0x04 0. -0x02 0. " INT_set/clr ,Latched Trip Interrupt Status Flag" "Not generated,Generated"
tree.end
tree "Event-Trigger Submodule Registers"
width 7.
group.word 0x30++0x01
line.word 0x00 "ETSEL,Event-Trigger Selection Register"
bitfld.word 0x00 15. " SOCBEN ,Enable the ADC Start of Conversion B EPWMxSOCB Pulse" "Disabled,Enabled"
bitfld.word 0x00 12.--14. " SOCBSEL ,EPWMxSOCB Selection Options" "DCBEVT1_soc,TB CNT equal to zero,TB CNT equal to period,TB CNT equal to zero or period,TB CNT equal to CMPA - Timer INC,TB CNT equal to CMPA - Timer DEC,TB CNT equal to CMPB - Timer INC,TB CNT equal to CMPB - Timer DEC"
bitfld.word 0x00 11. " SOCAEN ,Enable the ADC Start of Conversion A EPWMxSOCA Pulse" "Disabled,Enabled"
textline " "
bitfld.word 0x00 8.--10. " SOCASEL ,EPWMxSOCA Selection Options" "DCAEVT1_soc,TB CNT equal to zero,TB CNT equal to period,TB CNT equal to zero or period,TB CNT equal to CMPA - Timer INC,TB CNT equal to CMPA - Timer DEC,TB CNT equal to CMPB - Timer INC,TB CNT equal to CMPB - Timer DEC"
bitfld.word 0x00 3. " INTEN ,Enable ePWM Interrupt EPWMx_INT Generation" "Disabled,Enabled"
bitfld.word 0x00 0.--2. " INTSEL ,ePWM Interrupt EPWMx_INT Selection Options" ",TB CNT equal to zero,TB CNT equal to period,TB CNT equal to zero or period,TB CNT equal to CMPA - Timer INC,TB CNT equal to CMPA - Timer DEC,TB CNT equal to CMPB - Timer INC,TB CNT equal to CMPB - Timer DEC"
rgroup.word 0x34++0x01
line.word 0x00 "ETFLG,Event-Trigger Flag Register"
bitfld.word 0x00 3. " SOCB ,Latched ePWM ADC Start-of-Conversion B EPWMxSOCB Status Flag" "Not occurred,Occurred"
bitfld.word 0x00 2. " SOCA ,Latched ePWM ADC Start-of-Conversion A EPWMxSOCA Status Flag" "Not occurred,Occurred"
bitfld.word 0x00 0. " INT ,Latched ePWM Interrupt EPWMx_INT Status Flag" "Not occurred,Occurred"
group.word 0x36++0x01
line.word 0x00 "ETPS,Event-Trigger Pre-Scale Register"
rbitfld.word 0x00 14.--15. " SOCBCNT ,ePWM ADC Start-of-Conversion B Event EPWMxSOCB Counter Register" "No events,1 event,2 events,3 events"
bitfld.word 0x00 12.--13. " SOCBPRD ,ePWM ADC Start-of-Conversion B Event EPWMxSOCB Period Select" "Disabled,1st event,2nd event,3th event"
rbitfld.word 0x00 10.--11. " SOCACNT ,ePWM ADC Start-of-Conversion A Event EPWMxSOCA Counter Register" "No events,1 event,2 events,3 events"
textline " "
bitfld.word 0x00 8.--9. " SOCAPRD ,ePWM ADC Start-of-Conversion A Event EPWMxSOCA Period Select" "Disabled,1st event,2nd event,th event"
rbitfld.word 0x00 2.--3. " INTCNT ,ePWM Interrupt Event EPWMx_INT Counter Register" "No events,1 event,2 events,3 events"
bitfld.word 0x00 0.--1. " INTPRD ,ePWM Interrupt EPWMx_INT Period Select" "Disabled,1st event,2nd event,3th event"
group.word 0x38++0x01
line.word 0x00 "ETFRC,Event-Trigger Force Register"
bitfld.word 0x00 3. " SOCB ,SOCB Force Bit" "No effect,Forced"
bitfld.word 0x00 2. " SOCA ,SOCA Force Bit" "No effect,Forced"
bitfld.word 0x00 0. " INT ,INT Force Bit" "No effect,Forced"
group.word 0x3A++0x01
line.word 0x00 "ETCLR,Event-Trigger Clear Register"
bitfld.word 0x00 3. " SOCB ,ePWM ADC Start-of-Conversion B EPWMxSOCB Flag Clear Bit" "No effect,Cleared"
bitfld.word 0x00 2. " SOCA ,ePWM ADC Start-of-Conversion A EPWMxSOCB Flag Clear Bit" "No effect,Cleared"
bitfld.word 0x00 0. " INT ,ePWM Interrupt EPWMx_INT Flag Clear Bit" "No effect,Cleared"
tree.end
tree "PWM-Chopper Submodule Registers"
width 7.
group.word 0x3E++0x01
line.word 0x00 "PCCTL,PWM-Chopper Control Register"
bitfld.word 0x00 8.--10. " CHPDUTY ,Chopping Clock Duty Cycle" "1/8,2/8,3/8,4/8,5/8,6/8,7/8,?..."
bitfld.word 0x00 5.--7. " CHPFREQ ,Chopping Clock Frequency" "/1,/2,/3,/4,/5,/6,/7,/8"
bitfld.word 0x00 1.--4. " OSHTWTH ,One-Shot Pulse Width" "1 x VCLK3 / 8 wide,2 x VCLK3 / 8 wide,3 x VCLK3 / 8 wide,4 x VCLK3 / 8 wide,5 x VCLK3 / 8 wide,6 x VCLK3 / 8 wide,7 x VCLK3 / 8 wide,8 x VCLK3 / 8 wide,9 x VCLK3 / 8 wide,10 x VCLK3 / 8 wide,11 x VCLK3 / 8 wide,12 x VCLK3 / 8 wide,13 x VCLK3 / 8 wide,14 x VCLK3 / 8 wide,15 x VCLK3 / 8 wide,16 x VCLK3 / 8 wide"
textline " "
bitfld.word 0x00 0. " CHPEN ,PWM-chopping Enable" "Disabled,Enabled"
tree.end
tree "Digital Compare Event Registers"
width 14.
group.word 0x60++0x07
line.word 0x00 "DCACTL,Digital Compare A Control Register"
bitfld.word 0x00 9. " EVT2FRC_SYNCSEL ,DCAEVT2 Force Synchronization Signal Select" "Synchronous,Asynchronous"
bitfld.word 0x00 8. " EVT2SRCSEL ,DCAEVT2 Source Signal Select" "DCAEVT2,DCEVTFILT"
bitfld.word 0x00 3. " EVT1SYNCE ,DCAEVT1 SYNC Generation" "Disabled,Enabled"
textline " "
bitfld.word 0x00 2. " EVT1SOCE ,DCAEVT1 SOC Generation" "Disabled,Enabled"
bitfld.word 0x00 1. " EVT1FRC_SYNCSEL ,DCAEVT1 Force Synchronization Signal Select" "Synchronous,Asynchronous"
bitfld.word 0x00 0. " EVT1SRCSEL ,DCAEVT1 Source Signal Select" "DCAEVT,DCEVTFILT"
line.word 0x02 "DCTRIPSEL,Digital Compare Trip Select Register"
bitfld.word 0x02 12.--15. " DCBLCOMPSEL ,Digital Compare B Low Input Select" "TZ1 input,TZ2 input,TZ3 input,?..."
bitfld.word 0x02 8.--11. " DCBHCOMPSEL ,Digital Compare B High Input Select" "TZ1 input,TZ2 input,TZ3 input,?..."
bitfld.word 0x02 4.--7. " DCALCOMPSEL ,Digital Compare A Low Input Select" "TZ1 input,TZ2 input,TZ3 input,?..."
textline " "
bitfld.word 0x02 0.--3. " DCAHCOMPSEL ,Digital Compare A High Input Select" "TZ1 input,TZ2 input,TZ3 input,?..."
line.word 0x04 "DCFCTL,Digital Compare Filter Control Register"
bitfld.word 0x04 4.--5. " PULSESEL ,Pulse Select For Blanking & Capture Alignment" "TB CNT Equal to period,TB CNT Equal to zero,?..."
bitfld.word 0x04 3. " BLANKINV ,Blanking Window Inversion" "Not inverted,Inverted"
bitfld.word 0x04 2. " BLANKE ,Blanking Window Enable/Disable" "Disabled,Enabled"
textline " "
bitfld.word 0x04 0.--1. " SRCSEL ,Filter Block Signal Source Select" "DCAEVT1,DCAEVT2,DCBEVT1,DCBEVT2"
line.word 0x06 "DCBCTL,Digital Compare B Control Register"
bitfld.word 0x06 9. " EVT2FRC_SYNCSEL ,DCBEVT2 Force Synchronization Signal Select" "Synchronous,Asynchronous"
bitfld.word 0x06 8. " EVT2SRCSEL ,DCBEVT2 Source Signal Select" "DCBEVT2,DCEVTFILT"
bitfld.word 0x06 3. " EVT1SYNCE ,DCBEVT1 SYNC Generation" "Disabled,Enabled"
textline " "
bitfld.word 0x06 2. " EVT1SOCE ,DCBEVT1 SOC Generation" "Disabled,Enabled"
bitfld.word 0x06 1. " EVT1FRC_SYNCSEL ,DCBEVT1 Force Synchronization Signal Select" "Synchronous,Asynchronous"
bitfld.word 0x06 0. " EVT1SRCSEL ,DCBEVT1 Source Signal Select" "DCBEVT,DCEVTFILT"
rgroup.word 0x68++0x01
line.word 0x00 "DCOFFSET,Digital Compare Filter Offset Register"
group.word 0x6A++0x03
line.word 0x00 "DCCAPCTL,Digital Compare Capture Control Register"
bitfld.word 0x00 1. " SHDWMODE ,TBCTR Counter Capture Shadow Select Mode" "Shadow mode,Active Mode"
bitfld.word 0x00 0. " CAPE ,TBCTR Counter Capture Enable/Disable" "Disabled,Enabled"
line.word 0x02 "DCFWINDOW,Digital Compare Filter Window Register"
hexmask.word.byte 0x02 0.--7. 1. " WINDOW ,Blanking Window Width"
rgroup.word 0x6C++0x07
line.word 0x02 "DCOFFSETCNT, Digital Compare Filter Offset Counter Register"
line.word 0x04 "DCCAP, Digital Compare Counter Capture Register"
line.word 0x06 "DCFWINDOWCNT, Digital Compare Filter Window Counter Register"
hexmask.word.byte 0x06 0.--7. 1. " WINDOWCNT ,Digital Compare Filter Window Counter Register"
tree.end
width 0xB
tree.end
tree "eTPWM4"
base ad:0xFCF78F00
width 11.
tree "Time-Base Submodule Registers"
group.word 0x00++0x01
line.word 0x00 "TBSTS,Time-Base Status Register"
eventfld.word 0x00 2. " CTRMAX ,Time-Base Counter Max Latched Status Bit time-base counter maximum value" "Not reached,Reached"
eventfld.word 0x00 1. " SYNCI ,Input Synchronization Latched Status Bit external synchronization event" "Not occurred,Occurred"
rbitfld.word 0x00 0. " CTRDIR ,Time-Base Counter Direction Status Bit" "Down,Up"
if (((d.w(ad:0xFCF78F00+0x02))&0x30)==0x00)
group.word 0x02++0x03
line.word 0x00 "TBCTL,Time-Base Control Register"
bitfld.word 0x00 14.--15. " FREE/SOFT ,Emulation Mode Bits" "Stop after timer INC or DEC,Stop after whole cycle,Free run,Free run"
bitfld.word 0x00 13. " PHSDIR ,Phase Direction Bit" "Count down,Count up"
bitfld.word 0x00 10.--12. " CLKDIV ,Time-base Clock Prescale Bits" "/1,/2,/4,/8,/16,/32,/64,/128"
bitfld.word 0x00 7.--9. " HSPCLKDIV ,High Speed Time-base Clock Prescale Bits" "/1,/2,/4,/8,/8,/10,/12,/14"
textline " "
bitfld.word 0x00 6. " SWFSYNC ,Software Forced Synchronization Pulse" "No effect,Generated"
bitfld.word 0x00 4.--5. " SYNCOSEL ,Synchronization Output Select" "EPWMxSYNC,CTR = zero,CTR = CMPB,Disabled EPWMxSYNCO"
bitfld.word 0x00 3. " PRDLD ,Active Period Register Load From Shadow Register Select" "Not selected,Selected"
bitfld.word 0x00 2. " PHSEN ,Counter Register Load From Phase Register Enable" "Disabled,Enabled"
textline " "
bitfld.word 0x00 0.--1. " CTRMODE ,Counter Mode" "Up-count,Down-count,Up-down-count,Stop-freeze counter operation"
line.word 0x02 "TBPHS,Time-Base Phase Register"
else
group.word 0x02++0x03
line.word 0x00 "TBCTL,Time-Base Control Register"
bitfld.word 0x00 14.--15. " FREE/SOFT ,Emulation Mode Bits" "Stop after timer INC or DEC,Stop after whole cycle,Free run,Free run"
bitfld.word 0x00 13. " PHSDIR ,Phase Direction Bit" "Count down,Count up"
bitfld.word 0x00 10.--12. " CLKDIV ,Time-base Clock Prescale Bits" "/1,/2,/4,/8,/16,/32,/64,/128"
bitfld.word 0x00 7.--9. " HSPCLKDIV ,High Speed Time-base Clock Prescale Bits" "/1,/2,/4,/8,/8,/10,/12,/14"
textline " "
bitfld.word 0x00 6. " SWFSYNC ,Software Forced Synchronization Pulse" "No effect,Generated"
bitfld.word 0x00 3. " PRDLD ,Active Period Register Load From Shadow Register Select" "Not selected,Selected"
bitfld.word 0x00 2. " PHSEN ,Counter Register Load From Phase Register Enable" "Disabled,Enabled"
bitfld.word 0x00 0.--1. " CTRMODE ,Counter Mode" "Up-count,Down-count,Up-down-count,Stop-freeze counter operation"
line.word 0x02 "TBPHS, Time-Base Phase Register"
endif
group.word 0x08++0x03
line.word 0x00 "TBPRD,Time-Base Period Register"
line.word 0x02 "TBCTR,Time-Base Counter Register"
tree.end
tree "Counter-Compare Submodule Registers"
width 8.
group.word 0x0C++0x01
line.word 0x00 "CMPCTL,Counter-Compare Control Register"
rbitfld.word 0x00 9. " SHDWBFULL ,Counter-compare B CMPB Shadow Register Full Status Flag" "Not full,Full"
rbitfld.word 0x00 8. " SHDWAFULL ,Counter-compare A CMPA Shadow Register Full Status Flag" "Not full,Full"
bitfld.word 0x00 6. " SHDWBMODE ,Counter-compare B" "Shadow mode,Immediate mode"
textline " "
bitfld.word 0x00 4. " SHDWAMODE ,Counter-compare A CMPA Register Operating Mode" "Shadow mode,Immediate mode"
bitfld.word 0x00 2.--3. " LOADBMODE ,Active Counter-Compare B CMPB Load From Shadow Select Mode" "CTR=0,CTR=PRD,CTR=0/CTR=PRD,Freeze"
bitfld.word 0x00 0.--1. " LOADAMODE ,Active Counter-Compare A CMPA Load From Shadow Select Mode" "CTR=0,CTR=PRD,CTR=0/CTR=PRD,Freeze"
group.word 0x10++0x01
line.word 0x00 "CMPA,Counter-Compare A Register"
group.word 0x16++0x01
line.word 0x00 "CMPB,Counter-Compare B Register"
tree.end
tree "Action-Qualifier Submodule Registers"
width 9.
group.word 0x14++0x01
line.word 0x00 "AQCTLA,Action-Qualifier Control Register for Output A (EPWMxA)"
bitfld.word 0x00 10.--11. " CBD ,Action when the time-base counter equals the active CMPB register and the counter is decrementing" "Disabled,Cleared,Set,Toggled"
bitfld.word 0x00 8.--9. " CBU ,Action when the counter equals the active CMPB register and the counter is incrementing" "Disabled,Cleared,Set,Toggled"
bitfld.word 0x00 6.--7. " CAD ,Action when the counter equals the active CMPA register and the counter is decrementing" "Disabled,Cleared,Set,Toggled"
textline " "
bitfld.word 0x00 4.--5. " CAU ,Action when the counter equals the active CMPA register and the counter is incrementing" "Disabled,Cleared,Set,Toggled"
bitfld.word 0x00 2.--3. " PRD ,Action when the counter equals the period" "Disabled,Cleared,Set,Toggled"
bitfld.word 0x00 0.--1. " ZRO ,Action when counter equals zero" "Disabled,Cleared,Set,Toggled"
group.word 0x18++0x01
line.word 0x00 "AQSFRC,Action-Qualifier Software Force Register"
bitfld.word 0x00 6.--7. " RLDCSF ,AQCSFRC Active Register Reload From Shadow Options" "Zero,Period,Zero or Period,Immediately"
bitfld.word 0x00 5. " OTSFB ,One-Time Software Forced Event on Output B" "No effect,Forced"
bitfld.word 0x00 3.--4. " ACTSFB ,Action when One-Time Software Force B Is invoked" "Disabled,Cleared,Set,Toggled"
textline " "
bitfld.word 0x00 2. " OTSFA ,One-Time Software Forced Event on Output A" "No effect,Forced"
bitfld.word 0x00 0.--1. " ACTSFA ,Action When One-Time Software Force A Is Invoked" "Disabled,Cleared,Set,Toggled"
group.word 0x1A++0x01
line.word 0x00 "AQCTLB,Action-Qualifier Control Register for Output B (EPWMxB)"
bitfld.word 0x00 10.--11. " CBD ,Action when the time-base counter equals the active CMPB register and the counter is decrementing" "Disabled,Cleared,Set,Toggled"
bitfld.word 0x00 8.--9. " CBU ,Action when the counter equals the active CMPB register and the counter is incrementing" "Disabled,Cleared,Set,Toggled"
bitfld.word 0x00 6.--7. " CAD ,Action when the counter equals the active CMPA register and the counter is decrementing" "Disabled,Cleared,Set,Toggled"
textline " "
bitfld.word 0x00 4.--5. " CAU ,Action when the counter equals the active CMPA register and the counter is incrementing" "Disabled,Cleared,Set,Toggled"
bitfld.word 0x00 2.--3. " PRD ,Action when the counter equals the period" "Disabled,Cleared,Set,Toggled"
bitfld.word 0x00 0.--1. " ZRO ,Action when counter equals zero" "Disabled,Cleared,Set,Toggled"
group.word 0x1E++0x01
line.word 0x00 "AQCSFRC,Action-Qualifier Continuous S/W Force Register Set"
bitfld.word 0x00 2.--3. " CSFB ,Continuous Software Force on Output B" "Forced disabled,Continued low,Continued high,Soft forced disabled"
bitfld.word 0x00 0.--1. " CSFA ,Continuous Software Force on Output A" "Forced disabled,Continued low,Continued high,Soft forced disabled"
tree.end
tree "Dead-Band Generator Submodule Registers"
width 7.
group.word 0x1C++0x01
line.word 0x00 "DBCTL,Dead-Band Generator Control Register"
bitfld.word 0x00 15. " HALFCYCLE ,Half Cycle Clocking Enable Bit" "Disabled,Enabled"
bitfld.word 0x00 4.--5. " IN_MODE ,Dead Band Input Mode Control" "EPWMxA Faling&rising,EPWMxB rising / EPWMxA falling,EPWMxA rising / EPWMxB falling,EPWMxB rising&falling"
bitfld.word 0x00 2.--3. " POLSEL ,Polarity Select Control" "AH,ALC,AHC,AL"
bitfld.word 0x00 0.--1. " OUT_MODE ,Dead-band Output Mode Control" "Dead-band generation bypassed,Disabled rising-edge delay,Rising-edge delayed signal on EPWMxA,Dead-band fully enabled"
group.word 0x20++0x03
line.word 0x00 "DBFED,Dead-Band Generator Falling Edge Delay Count Register"
hexmask.word 0x00 0.--9. 1. " DEL ,Falling Edge Delay Count"
line.word 0x02 "DBRED,Dead-Band Generator Rising Edge Delay Count Register"
hexmask.word 0x02 0.--9. 1. " DEL ,Rising Edge Delay Count"
tree.end
tree "Trip-Zone Submodule Registers"
group.word 0x24++0x03
line.word 0x00 "TZDCSEL,Trip Zone Digital Compare Event Select Register"
bitfld.word 0x00 9.--11. " DCBEVT2 ,Digital Compare Output B Event 2 Selection (DCBH/DCBL)" "Disabled,Low / Don't care,High / Don't care,Don't care / Low,Don't care / High,Low / High,?..."
bitfld.word 0x00 6.--8. " DCBEVT1 ,Digital Compare Output B Event 1 Selection (DCBH/DCBL)" "Disabled,Low / Don't care,High / Don't care,Don't care / Low,Don't care / High,Low / High,?..."
textline " "
bitfld.word 0x00 3.--5. " DCAEVT2 ,Digital Compare Output A Event 2 Selection (DCAH/DCAL)" "Disabled,Low / Don't care,High / Don't care,Don't care / Low,Don't care / High,Low / High,?..."
bitfld.word 0x00 0.--2. " DCAEVT1 ,Digital Compare Output A Event 1 Selection (DCAH/DCAL)" "Disabled,Low / Don't care,High / Don't care,Don't care / Low,Don't care / High,Low / High,?..."
line.word 0x02 "TZSEL,Trip-Zone Select Register"
rbitfld.word 0x02 15. " DCBEVT1 ,Digital Compare Output B Event 1 Select" "Disabled,Enabled"
rbitfld.word 0x02 14. " DCAEVT1 ,Digital Compare Output A Event 1 Select" "Disabled,Enabled"
bitfld.word 0x02 13. " OSHT6 ,Trip-zone 6 (/TZ6) Select" "Disabled,Enabled"
textline " "
bitfld.word 0x02 12. " OSHT5 ,Trip-zone 5 (/TZ5) Select" "Disabled,Enabled"
bitfld.word 0x02 11. " OSHT4 ,Trip-zone 4 (/TZ4) Select" "Disabled,Enabled"
bitfld.word 0x02 10. " OSHT3 ,Trip-zone 3 (/TZ3) Select" "Disabled,Enabled"
textline " "
bitfld.word 0x02 9. " OSHT2 ,Trip-zone 2 (/TZ2) Select" "Disabled,Enabled"
bitfld.word 0x02 8. " OSHT1 ,Trip-zone 1 (/TZ1) Select" "Disabled,Enabled"
rbitfld.word 0x02 7. " DCBEVT2 ,Digital Compare Output B Event 2 Select" "Disabled,Enabled"
textline " "
rbitfld.word 0x02 6. " DCAEVT2 ,Digital Compare Output A Event 2 Select" "Disabled,Enabled"
bitfld.word 0x02 5. " CBC6 ,Trip-zone 6 (/TZ6) Select" "Disabled,Enabled"
bitfld.word 0x02 4. " CBC5 ,Trip-zone 5 (/TZ5) Select" "Disabled,Enabled"
textline " "
bitfld.word 0x02 3. " CBC4 ,Trip-zone 4 (/TZ4) Select" "Disabled,Enabled"
bitfld.word 0x02 2. " CBC3 ,Trip-zone 3 (/TZ3) Select" "Disabled,Enabled"
bitfld.word 0x02 1. " CBC2 ,Trip-zone 2 (/TZ2) Select" "Disabled,Enabled"
textline " "
bitfld.word 0x02 0. " CBC1 ,Trip-zone 1 (/TZ1) Select" "Disabled,Enabled"
group.word 0x28++0x01
line.word 0x00 "TZEINT,Trip-Zone Enable Interrupt Register"
bitfld.word 0x00 6. " DCBEVT2 ,Digital Comparator Output B Event 2 Interrupt Enable" "Disabled,Enabled"
bitfld.word 0x00 5. " DCBEVT1 ,Digital Comparator Output B Event 1 Interrupt Enable" "Disabled,Enabled"
bitfld.word 0x00 4. " DCAEVT2 ,Digital Comparator Output A Event 2 Interrupt Enable" "Disabled,Enabled"
textline " "
bitfld.word 0x00 3. " DCAEVT1 ,Digital Comparator Output A Event 1 Interrupt Enable" "Disabled,Enabled"
bitfld.word 0x00 2. " OST ,Trip-zone One-Shot Interrupt Enable" "Disabled,Enabled"
bitfld.word 0x00 1. " CBC ,Trip-zone Cycle-by-Cycle Interrupt Enable" "Disabled,Enabled"
group.word 0x2A++0x01
line.word 0x00 "TZCTL,Trip-Zone Control Register"
bitfld.word 0x00 10.--11. " DCBEVT2 ,Digital Compare Output B Event 2 Action On EPWMxB" "High-impedance,Forced high state,Forced low state,Disabled"
bitfld.word 0x00 8.--9. " DCBEVT1 ,Digital Compare Output B Event 1 Action On EPWMxB" "High-impedance,Forced high state,Forced low state,Disabled"
textline " "
bitfld.word 0x00 6.--7. " DCAEVT2 ,Digital Compare Output A Event 2 Action On EPWMxA" "High-impedance,Forced high state,Forced low state,Disabled"
bitfld.word 0x00 4.--5. " DCAEVT1 ,Digital Compare Output A Event 1 Action On EPWMxA" "High-impedance,Forced high state,Forced low state,Disabled"
textline " "
bitfld.word 0x00 2.--3. " TZB ,When a trip event occurs the following action is taken on output EPWMxB" "High-impedance,Forced high state,Forced low state,Disabled"
bitfld.word 0x00 0.--1. " TZA ,When a trip event occurs the following action is taken on output EPWMxA" "High-impedance,Forced high state,Forced low state,Disabled"
textline " "
group.word 0x2E++0x01
line.word 0x00 "TZFLG,Trip-Zone Flag Register"
setclrfld.word 0x00 6. 0x04 6. -0x02 6. " DCBEVT2_set/clr ,Digital Comparator Output B Event 2 Interrupt" "Not occurred,Occurred"
setclrfld.word 0x00 5. 0x04 5. -0x02 5. " DCBEVT1_set/clr ,Digital Comparator Output B Event 1 Interrupt" "Not occurred,Occurred"
textline " "
setclrfld.word 0x00 4. 0x04 4. -0x02 4. " DCAEVT2_set/clr ,Digital Comparator Output A Event 2 Interrupt" "Not occurred,Occurred"
setclrfld.word 0x00 3. 0x04 3. -0x02 3. " DCAEVT1_set/clr ,Digital Comparator Output A Event 1 Interrupt" "Not occurred,Occurred"
textline " "
setclrfld.word 0x00 2. 0x04 2. -0x02 2. " OST_set/clr ,Trip-zone One-Shot Interrupt" "Not occurred,Occurred"
setclrfld.word 0x00 1. 0x04 1. -0x02 1. " CBC_set/clr ,Trip-zone Cycle-by-Cycle Interrupt" "Not occurred,Occurred"
textline " "
setclrfld.word 0x00 0. 0x04 0. -0x02 0. " INT_set/clr ,Latched Trip Interrupt Status Flag" "Not generated,Generated"
tree.end
tree "Event-Trigger Submodule Registers"
width 7.
group.word 0x30++0x01
line.word 0x00 "ETSEL,Event-Trigger Selection Register"
bitfld.word 0x00 15. " SOCBEN ,Enable the ADC Start of Conversion B EPWMxSOCB Pulse" "Disabled,Enabled"
bitfld.word 0x00 12.--14. " SOCBSEL ,EPWMxSOCB Selection Options" "DCBEVT1_soc,TB CNT equal to zero,TB CNT equal to period,TB CNT equal to zero or period,TB CNT equal to CMPA - Timer INC,TB CNT equal to CMPA - Timer DEC,TB CNT equal to CMPB - Timer INC,TB CNT equal to CMPB - Timer DEC"
bitfld.word 0x00 11. " SOCAEN ,Enable the ADC Start of Conversion A EPWMxSOCA Pulse" "Disabled,Enabled"
textline " "
bitfld.word 0x00 8.--10. " SOCASEL ,EPWMxSOCA Selection Options" "DCAEVT1_soc,TB CNT equal to zero,TB CNT equal to period,TB CNT equal to zero or period,TB CNT equal to CMPA - Timer INC,TB CNT equal to CMPA - Timer DEC,TB CNT equal to CMPB - Timer INC,TB CNT equal to CMPB - Timer DEC"
bitfld.word 0x00 3. " INTEN ,Enable ePWM Interrupt EPWMx_INT Generation" "Disabled,Enabled"
bitfld.word 0x00 0.--2. " INTSEL ,ePWM Interrupt EPWMx_INT Selection Options" ",TB CNT equal to zero,TB CNT equal to period,TB CNT equal to zero or period,TB CNT equal to CMPA - Timer INC,TB CNT equal to CMPA - Timer DEC,TB CNT equal to CMPB - Timer INC,TB CNT equal to CMPB - Timer DEC"
rgroup.word 0x34++0x01
line.word 0x00 "ETFLG,Event-Trigger Flag Register"
bitfld.word 0x00 3. " SOCB ,Latched ePWM ADC Start-of-Conversion B EPWMxSOCB Status Flag" "Not occurred,Occurred"
bitfld.word 0x00 2. " SOCA ,Latched ePWM ADC Start-of-Conversion A EPWMxSOCA Status Flag" "Not occurred,Occurred"
bitfld.word 0x00 0. " INT ,Latched ePWM Interrupt EPWMx_INT Status Flag" "Not occurred,Occurred"
group.word 0x36++0x01
line.word 0x00 "ETPS,Event-Trigger Pre-Scale Register"
rbitfld.word 0x00 14.--15. " SOCBCNT ,ePWM ADC Start-of-Conversion B Event EPWMxSOCB Counter Register" "No events,1 event,2 events,3 events"
bitfld.word 0x00 12.--13. " SOCBPRD ,ePWM ADC Start-of-Conversion B Event EPWMxSOCB Period Select" "Disabled,1st event,2nd event,3th event"
rbitfld.word 0x00 10.--11. " SOCACNT ,ePWM ADC Start-of-Conversion A Event EPWMxSOCA Counter Register" "No events,1 event,2 events,3 events"
textline " "
bitfld.word 0x00 8.--9. " SOCAPRD ,ePWM ADC Start-of-Conversion A Event EPWMxSOCA Period Select" "Disabled,1st event,2nd event,th event"
rbitfld.word 0x00 2.--3. " INTCNT ,ePWM Interrupt Event EPWMx_INT Counter Register" "No events,1 event,2 events,3 events"
bitfld.word 0x00 0.--1. " INTPRD ,ePWM Interrupt EPWMx_INT Period Select" "Disabled,1st event,2nd event,3th event"
group.word 0x38++0x01
line.word 0x00 "ETFRC,Event-Trigger Force Register"
bitfld.word 0x00 3. " SOCB ,SOCB Force Bit" "No effect,Forced"
bitfld.word 0x00 2. " SOCA ,SOCA Force Bit" "No effect,Forced"
bitfld.word 0x00 0. " INT ,INT Force Bit" "No effect,Forced"
group.word 0x3A++0x01
line.word 0x00 "ETCLR,Event-Trigger Clear Register"
bitfld.word 0x00 3. " SOCB ,ePWM ADC Start-of-Conversion B EPWMxSOCB Flag Clear Bit" "No effect,Cleared"
bitfld.word 0x00 2. " SOCA ,ePWM ADC Start-of-Conversion A EPWMxSOCB Flag Clear Bit" "No effect,Cleared"
bitfld.word 0x00 0. " INT ,ePWM Interrupt EPWMx_INT Flag Clear Bit" "No effect,Cleared"
tree.end
tree "PWM-Chopper Submodule Registers"
width 7.
group.word 0x3E++0x01
line.word 0x00 "PCCTL,PWM-Chopper Control Register"
bitfld.word 0x00 8.--10. " CHPDUTY ,Chopping Clock Duty Cycle" "1/8,2/8,3/8,4/8,5/8,6/8,7/8,?..."
bitfld.word 0x00 5.--7. " CHPFREQ ,Chopping Clock Frequency" "/1,/2,/3,/4,/5,/6,/7,/8"
bitfld.word 0x00 1.--4. " OSHTWTH ,One-Shot Pulse Width" "1 x VCLK3 / 8 wide,2 x VCLK3 / 8 wide,3 x VCLK3 / 8 wide,4 x VCLK3 / 8 wide,5 x VCLK3 / 8 wide,6 x VCLK3 / 8 wide,7 x VCLK3 / 8 wide,8 x VCLK3 / 8 wide,9 x VCLK3 / 8 wide,10 x VCLK3 / 8 wide,11 x VCLK3 / 8 wide,12 x VCLK3 / 8 wide,13 x VCLK3 / 8 wide,14 x VCLK3 / 8 wide,15 x VCLK3 / 8 wide,16 x VCLK3 / 8 wide"
textline " "
bitfld.word 0x00 0. " CHPEN ,PWM-chopping Enable" "Disabled,Enabled"
tree.end
tree "Digital Compare Event Registers"
width 14.
group.word 0x60++0x07
line.word 0x00 "DCACTL,Digital Compare A Control Register"
bitfld.word 0x00 9. " EVT2FRC_SYNCSEL ,DCAEVT2 Force Synchronization Signal Select" "Synchronous,Asynchronous"
bitfld.word 0x00 8. " EVT2SRCSEL ,DCAEVT2 Source Signal Select" "DCAEVT2,DCEVTFILT"
bitfld.word 0x00 3. " EVT1SYNCE ,DCAEVT1 SYNC Generation" "Disabled,Enabled"
textline " "
bitfld.word 0x00 2. " EVT1SOCE ,DCAEVT1 SOC Generation" "Disabled,Enabled"
bitfld.word 0x00 1. " EVT1FRC_SYNCSEL ,DCAEVT1 Force Synchronization Signal Select" "Synchronous,Asynchronous"
bitfld.word 0x00 0. " EVT1SRCSEL ,DCAEVT1 Source Signal Select" "DCAEVT,DCEVTFILT"
line.word 0x02 "DCTRIPSEL,Digital Compare Trip Select Register"
bitfld.word 0x02 12.--15. " DCBLCOMPSEL ,Digital Compare B Low Input Select" "TZ1 input,TZ2 input,TZ3 input,?..."
bitfld.word 0x02 8.--11. " DCBHCOMPSEL ,Digital Compare B High Input Select" "TZ1 input,TZ2 input,TZ3 input,?..."
bitfld.word 0x02 4.--7. " DCALCOMPSEL ,Digital Compare A Low Input Select" "TZ1 input,TZ2 input,TZ3 input,?..."
textline " "
bitfld.word 0x02 0.--3. " DCAHCOMPSEL ,Digital Compare A High Input Select" "TZ1 input,TZ2 input,TZ3 input,?..."
line.word 0x04 "DCFCTL,Digital Compare Filter Control Register"
bitfld.word 0x04 4.--5. " PULSESEL ,Pulse Select For Blanking & Capture Alignment" "TB CNT Equal to period,TB CNT Equal to zero,?..."
bitfld.word 0x04 3. " BLANKINV ,Blanking Window Inversion" "Not inverted,Inverted"
bitfld.word 0x04 2. " BLANKE ,Blanking Window Enable/Disable" "Disabled,Enabled"
textline " "
bitfld.word 0x04 0.--1. " SRCSEL ,Filter Block Signal Source Select" "DCAEVT1,DCAEVT2,DCBEVT1,DCBEVT2"
line.word 0x06 "DCBCTL,Digital Compare B Control Register"
bitfld.word 0x06 9. " EVT2FRC_SYNCSEL ,DCBEVT2 Force Synchronization Signal Select" "Synchronous,Asynchronous"
bitfld.word 0x06 8. " EVT2SRCSEL ,DCBEVT2 Source Signal Select" "DCBEVT2,DCEVTFILT"
bitfld.word 0x06 3. " EVT1SYNCE ,DCBEVT1 SYNC Generation" "Disabled,Enabled"
textline " "
bitfld.word 0x06 2. " EVT1SOCE ,DCBEVT1 SOC Generation" "Disabled,Enabled"
bitfld.word 0x06 1. " EVT1FRC_SYNCSEL ,DCBEVT1 Force Synchronization Signal Select" "Synchronous,Asynchronous"
bitfld.word 0x06 0. " EVT1SRCSEL ,DCBEVT1 Source Signal Select" "DCBEVT,DCEVTFILT"
rgroup.word 0x68++0x01
line.word 0x00 "DCOFFSET,Digital Compare Filter Offset Register"
group.word 0x6A++0x03
line.word 0x00 "DCCAPCTL,Digital Compare Capture Control Register"
bitfld.word 0x00 1. " SHDWMODE ,TBCTR Counter Capture Shadow Select Mode" "Shadow mode,Active Mode"
bitfld.word 0x00 0. " CAPE ,TBCTR Counter Capture Enable/Disable" "Disabled,Enabled"
line.word 0x02 "DCFWINDOW,Digital Compare Filter Window Register"
hexmask.word.byte 0x02 0.--7. 1. " WINDOW ,Blanking Window Width"
rgroup.word 0x6C++0x07
line.word 0x02 "DCOFFSETCNT, Digital Compare Filter Offset Counter Register"
line.word 0x04 "DCCAP, Digital Compare Counter Capture Register"
line.word 0x06 "DCFWINDOWCNT, Digital Compare Filter Window Counter Register"
hexmask.word.byte 0x06 0.--7. 1. " WINDOWCNT ,Digital Compare Filter Window Counter Register"
tree.end
width 0xB
tree.end
tree "eTPWM5"
base ad:0xFCF79000
width 11.
tree "Time-Base Submodule Registers"
group.word 0x00++0x01
line.word 0x00 "TBSTS,Time-Base Status Register"
eventfld.word 0x00 2. " CTRMAX ,Time-Base Counter Max Latched Status Bit time-base counter maximum value" "Not reached,Reached"
eventfld.word 0x00 1. " SYNCI ,Input Synchronization Latched Status Bit external synchronization event" "Not occurred,Occurred"
rbitfld.word 0x00 0. " CTRDIR ,Time-Base Counter Direction Status Bit" "Down,Up"
if (((d.w(ad:0xFCF79000+0x02))&0x30)==0x00)
group.word 0x02++0x03
line.word 0x00 "TBCTL,Time-Base Control Register"
bitfld.word 0x00 14.--15. " FREE/SOFT ,Emulation Mode Bits" "Stop after timer INC or DEC,Stop after whole cycle,Free run,Free run"
bitfld.word 0x00 13. " PHSDIR ,Phase Direction Bit" "Count down,Count up"
bitfld.word 0x00 10.--12. " CLKDIV ,Time-base Clock Prescale Bits" "/1,/2,/4,/8,/16,/32,/64,/128"
bitfld.word 0x00 7.--9. " HSPCLKDIV ,High Speed Time-base Clock Prescale Bits" "/1,/2,/4,/8,/8,/10,/12,/14"
textline " "
bitfld.word 0x00 6. " SWFSYNC ,Software Forced Synchronization Pulse" "No effect,Generated"
bitfld.word 0x00 4.--5. " SYNCOSEL ,Synchronization Output Select" "EPWMxSYNC,CTR = zero,CTR = CMPB,Disabled EPWMxSYNCO"
bitfld.word 0x00 3. " PRDLD ,Active Period Register Load From Shadow Register Select" "Not selected,Selected"
bitfld.word 0x00 2. " PHSEN ,Counter Register Load From Phase Register Enable" "Disabled,Enabled"
textline " "
bitfld.word 0x00 0.--1. " CTRMODE ,Counter Mode" "Up-count,Down-count,Up-down-count,Stop-freeze counter operation"
line.word 0x02 "TBPHS,Time-Base Phase Register"
else
group.word 0x02++0x03
line.word 0x00 "TBCTL,Time-Base Control Register"
bitfld.word 0x00 14.--15. " FREE/SOFT ,Emulation Mode Bits" "Stop after timer INC or DEC,Stop after whole cycle,Free run,Free run"
bitfld.word 0x00 13. " PHSDIR ,Phase Direction Bit" "Count down,Count up"
bitfld.word 0x00 10.--12. " CLKDIV ,Time-base Clock Prescale Bits" "/1,/2,/4,/8,/16,/32,/64,/128"
bitfld.word 0x00 7.--9. " HSPCLKDIV ,High Speed Time-base Clock Prescale Bits" "/1,/2,/4,/8,/8,/10,/12,/14"
textline " "
bitfld.word 0x00 6. " SWFSYNC ,Software Forced Synchronization Pulse" "No effect,Generated"
bitfld.word 0x00 3. " PRDLD ,Active Period Register Load From Shadow Register Select" "Not selected,Selected"
bitfld.word 0x00 2. " PHSEN ,Counter Register Load From Phase Register Enable" "Disabled,Enabled"
bitfld.word 0x00 0.--1. " CTRMODE ,Counter Mode" "Up-count,Down-count,Up-down-count,Stop-freeze counter operation"
line.word 0x02 "TBPHS, Time-Base Phase Register"
endif
group.word 0x08++0x03
line.word 0x00 "TBPRD,Time-Base Period Register"
line.word 0x02 "TBCTR,Time-Base Counter Register"
tree.end
tree "Counter-Compare Submodule Registers"
width 8.
group.word 0x0C++0x01
line.word 0x00 "CMPCTL,Counter-Compare Control Register"
rbitfld.word 0x00 9. " SHDWBFULL ,Counter-compare B CMPB Shadow Register Full Status Flag" "Not full,Full"
rbitfld.word 0x00 8. " SHDWAFULL ,Counter-compare A CMPA Shadow Register Full Status Flag" "Not full,Full"
bitfld.word 0x00 6. " SHDWBMODE ,Counter-compare B" "Shadow mode,Immediate mode"
textline " "
bitfld.word 0x00 4. " SHDWAMODE ,Counter-compare A CMPA Register Operating Mode" "Shadow mode,Immediate mode"
bitfld.word 0x00 2.--3. " LOADBMODE ,Active Counter-Compare B CMPB Load From Shadow Select Mode" "CTR=0,CTR=PRD,CTR=0/CTR=PRD,Freeze"
bitfld.word 0x00 0.--1. " LOADAMODE ,Active Counter-Compare A CMPA Load From Shadow Select Mode" "CTR=0,CTR=PRD,CTR=0/CTR=PRD,Freeze"
group.word 0x10++0x01
line.word 0x00 "CMPA,Counter-Compare A Register"
group.word 0x16++0x01
line.word 0x00 "CMPB,Counter-Compare B Register"
tree.end
tree "Action-Qualifier Submodule Registers"
width 9.
group.word 0x14++0x01
line.word 0x00 "AQCTLA,Action-Qualifier Control Register for Output A (EPWMxA)"
bitfld.word 0x00 10.--11. " CBD ,Action when the time-base counter equals the active CMPB register and the counter is decrementing" "Disabled,Cleared,Set,Toggled"
bitfld.word 0x00 8.--9. " CBU ,Action when the counter equals the active CMPB register and the counter is incrementing" "Disabled,Cleared,Set,Toggled"
bitfld.word 0x00 6.--7. " CAD ,Action when the counter equals the active CMPA register and the counter is decrementing" "Disabled,Cleared,Set,Toggled"
textline " "
bitfld.word 0x00 4.--5. " CAU ,Action when the counter equals the active CMPA register and the counter is incrementing" "Disabled,Cleared,Set,Toggled"
bitfld.word 0x00 2.--3. " PRD ,Action when the counter equals the period" "Disabled,Cleared,Set,Toggled"
bitfld.word 0x00 0.--1. " ZRO ,Action when counter equals zero" "Disabled,Cleared,Set,Toggled"
group.word 0x18++0x01
line.word 0x00 "AQSFRC,Action-Qualifier Software Force Register"
bitfld.word 0x00 6.--7. " RLDCSF ,AQCSFRC Active Register Reload From Shadow Options" "Zero,Period,Zero or Period,Immediately"
bitfld.word 0x00 5. " OTSFB ,One-Time Software Forced Event on Output B" "No effect,Forced"
bitfld.word 0x00 3.--4. " ACTSFB ,Action when One-Time Software Force B Is invoked" "Disabled,Cleared,Set,Toggled"
textline " "
bitfld.word 0x00 2. " OTSFA ,One-Time Software Forced Event on Output A" "No effect,Forced"
bitfld.word 0x00 0.--1. " ACTSFA ,Action When One-Time Software Force A Is Invoked" "Disabled,Cleared,Set,Toggled"
group.word 0x1A++0x01
line.word 0x00 "AQCTLB,Action-Qualifier Control Register for Output B (EPWMxB)"
bitfld.word 0x00 10.--11. " CBD ,Action when the time-base counter equals the active CMPB register and the counter is decrementing" "Disabled,Cleared,Set,Toggled"
bitfld.word 0x00 8.--9. " CBU ,Action when the counter equals the active CMPB register and the counter is incrementing" "Disabled,Cleared,Set,Toggled"
bitfld.word 0x00 6.--7. " CAD ,Action when the counter equals the active CMPA register and the counter is decrementing" "Disabled,Cleared,Set,Toggled"
textline " "
bitfld.word 0x00 4.--5. " CAU ,Action when the counter equals the active CMPA register and the counter is incrementing" "Disabled,Cleared,Set,Toggled"
bitfld.word 0x00 2.--3. " PRD ,Action when the counter equals the period" "Disabled,Cleared,Set,Toggled"
bitfld.word 0x00 0.--1. " ZRO ,Action when counter equals zero" "Disabled,Cleared,Set,Toggled"
group.word 0x1E++0x01
line.word 0x00 "AQCSFRC,Action-Qualifier Continuous S/W Force Register Set"
bitfld.word 0x00 2.--3. " CSFB ,Continuous Software Force on Output B" "Forced disabled,Continued low,Continued high,Soft forced disabled"
bitfld.word 0x00 0.--1. " CSFA ,Continuous Software Force on Output A" "Forced disabled,Continued low,Continued high,Soft forced disabled"
tree.end
tree "Dead-Band Generator Submodule Registers"
width 7.
group.word 0x1C++0x01
line.word 0x00 "DBCTL,Dead-Band Generator Control Register"
bitfld.word 0x00 15. " HALFCYCLE ,Half Cycle Clocking Enable Bit" "Disabled,Enabled"
bitfld.word 0x00 4.--5. " IN_MODE ,Dead Band Input Mode Control" "EPWMxA Faling&rising,EPWMxB rising / EPWMxA falling,EPWMxA rising / EPWMxB falling,EPWMxB rising&falling"
bitfld.word 0x00 2.--3. " POLSEL ,Polarity Select Control" "AH,ALC,AHC,AL"
bitfld.word 0x00 0.--1. " OUT_MODE ,Dead-band Output Mode Control" "Dead-band generation bypassed,Disabled rising-edge delay,Rising-edge delayed signal on EPWMxA,Dead-band fully enabled"
group.word 0x20++0x03
line.word 0x00 "DBFED,Dead-Band Generator Falling Edge Delay Count Register"
hexmask.word 0x00 0.--9. 1. " DEL ,Falling Edge Delay Count"
line.word 0x02 "DBRED,Dead-Band Generator Rising Edge Delay Count Register"
hexmask.word 0x02 0.--9. 1. " DEL ,Rising Edge Delay Count"
tree.end
tree "Trip-Zone Submodule Registers"
group.word 0x24++0x03
line.word 0x00 "TZDCSEL,Trip Zone Digital Compare Event Select Register"
bitfld.word 0x00 9.--11. " DCBEVT2 ,Digital Compare Output B Event 2 Selection (DCBH/DCBL)" "Disabled,Low / Don't care,High / Don't care,Don't care / Low,Don't care / High,Low / High,?..."
bitfld.word 0x00 6.--8. " DCBEVT1 ,Digital Compare Output B Event 1 Selection (DCBH/DCBL)" "Disabled,Low / Don't care,High / Don't care,Don't care / Low,Don't care / High,Low / High,?..."
textline " "
bitfld.word 0x00 3.--5. " DCAEVT2 ,Digital Compare Output A Event 2 Selection (DCAH/DCAL)" "Disabled,Low / Don't care,High / Don't care,Don't care / Low,Don't care / High,Low / High,?..."
bitfld.word 0x00 0.--2. " DCAEVT1 ,Digital Compare Output A Event 1 Selection (DCAH/DCAL)" "Disabled,Low / Don't care,High / Don't care,Don't care / Low,Don't care / High,Low / High,?..."
line.word 0x02 "TZSEL,Trip-Zone Select Register"
rbitfld.word 0x02 15. " DCBEVT1 ,Digital Compare Output B Event 1 Select" "Disabled,Enabled"
rbitfld.word 0x02 14. " DCAEVT1 ,Digital Compare Output A Event 1 Select" "Disabled,Enabled"
bitfld.word 0x02 13. " OSHT6 ,Trip-zone 6 (/TZ6) Select" "Disabled,Enabled"
textline " "
bitfld.word 0x02 12. " OSHT5 ,Trip-zone 5 (/TZ5) Select" "Disabled,Enabled"
bitfld.word 0x02 11. " OSHT4 ,Trip-zone 4 (/TZ4) Select" "Disabled,Enabled"
bitfld.word 0x02 10. " OSHT3 ,Trip-zone 3 (/TZ3) Select" "Disabled,Enabled"
textline " "
bitfld.word 0x02 9. " OSHT2 ,Trip-zone 2 (/TZ2) Select" "Disabled,Enabled"
bitfld.word 0x02 8. " OSHT1 ,Trip-zone 1 (/TZ1) Select" "Disabled,Enabled"
rbitfld.word 0x02 7. " DCBEVT2 ,Digital Compare Output B Event 2 Select" "Disabled,Enabled"
textline " "
rbitfld.word 0x02 6. " DCAEVT2 ,Digital Compare Output A Event 2 Select" "Disabled,Enabled"
bitfld.word 0x02 5. " CBC6 ,Trip-zone 6 (/TZ6) Select" "Disabled,Enabled"
bitfld.word 0x02 4. " CBC5 ,Trip-zone 5 (/TZ5) Select" "Disabled,Enabled"
textline " "
bitfld.word 0x02 3. " CBC4 ,Trip-zone 4 (/TZ4) Select" "Disabled,Enabled"
bitfld.word 0x02 2. " CBC3 ,Trip-zone 3 (/TZ3) Select" "Disabled,Enabled"
bitfld.word 0x02 1. " CBC2 ,Trip-zone 2 (/TZ2) Select" "Disabled,Enabled"
textline " "
bitfld.word 0x02 0. " CBC1 ,Trip-zone 1 (/TZ1) Select" "Disabled,Enabled"
group.word 0x28++0x01
line.word 0x00 "TZEINT,Trip-Zone Enable Interrupt Register"
bitfld.word 0x00 6. " DCBEVT2 ,Digital Comparator Output B Event 2 Interrupt Enable" "Disabled,Enabled"
bitfld.word 0x00 5. " DCBEVT1 ,Digital Comparator Output B Event 1 Interrupt Enable" "Disabled,Enabled"
bitfld.word 0x00 4. " DCAEVT2 ,Digital Comparator Output A Event 2 Interrupt Enable" "Disabled,Enabled"
textline " "
bitfld.word 0x00 3. " DCAEVT1 ,Digital Comparator Output A Event 1 Interrupt Enable" "Disabled,Enabled"
bitfld.word 0x00 2. " OST ,Trip-zone One-Shot Interrupt Enable" "Disabled,Enabled"
bitfld.word 0x00 1. " CBC ,Trip-zone Cycle-by-Cycle Interrupt Enable" "Disabled,Enabled"
group.word 0x2A++0x01
line.word 0x00 "TZCTL,Trip-Zone Control Register"
bitfld.word 0x00 10.--11. " DCBEVT2 ,Digital Compare Output B Event 2 Action On EPWMxB" "High-impedance,Forced high state,Forced low state,Disabled"
bitfld.word 0x00 8.--9. " DCBEVT1 ,Digital Compare Output B Event 1 Action On EPWMxB" "High-impedance,Forced high state,Forced low state,Disabled"
textline " "
bitfld.word 0x00 6.--7. " DCAEVT2 ,Digital Compare Output A Event 2 Action On EPWMxA" "High-impedance,Forced high state,Forced low state,Disabled"
bitfld.word 0x00 4.--5. " DCAEVT1 ,Digital Compare Output A Event 1 Action On EPWMxA" "High-impedance,Forced high state,Forced low state,Disabled"
textline " "
bitfld.word 0x00 2.--3. " TZB ,When a trip event occurs the following action is taken on output EPWMxB" "High-impedance,Forced high state,Forced low state,Disabled"
bitfld.word 0x00 0.--1. " TZA ,When a trip event occurs the following action is taken on output EPWMxA" "High-impedance,Forced high state,Forced low state,Disabled"
textline " "
group.word 0x2E++0x01
line.word 0x00 "TZFLG,Trip-Zone Flag Register"
setclrfld.word 0x00 6. 0x04 6. -0x02 6. " DCBEVT2_set/clr ,Digital Comparator Output B Event 2 Interrupt" "Not occurred,Occurred"
setclrfld.word 0x00 5. 0x04 5. -0x02 5. " DCBEVT1_set/clr ,Digital Comparator Output B Event 1 Interrupt" "Not occurred,Occurred"
textline " "
setclrfld.word 0x00 4. 0x04 4. -0x02 4. " DCAEVT2_set/clr ,Digital Comparator Output A Event 2 Interrupt" "Not occurred,Occurred"
setclrfld.word 0x00 3. 0x04 3. -0x02 3. " DCAEVT1_set/clr ,Digital Comparator Output A Event 1 Interrupt" "Not occurred,Occurred"
textline " "
setclrfld.word 0x00 2. 0x04 2. -0x02 2. " OST_set/clr ,Trip-zone One-Shot Interrupt" "Not occurred,Occurred"
setclrfld.word 0x00 1. 0x04 1. -0x02 1. " CBC_set/clr ,Trip-zone Cycle-by-Cycle Interrupt" "Not occurred,Occurred"
textline " "
setclrfld.word 0x00 0. 0x04 0. -0x02 0. " INT_set/clr ,Latched Trip Interrupt Status Flag" "Not generated,Generated"
tree.end
tree "Event-Trigger Submodule Registers"
width 7.
group.word 0x30++0x01
line.word 0x00 "ETSEL,Event-Trigger Selection Register"
bitfld.word 0x00 15. " SOCBEN ,Enable the ADC Start of Conversion B EPWMxSOCB Pulse" "Disabled,Enabled"
bitfld.word 0x00 12.--14. " SOCBSEL ,EPWMxSOCB Selection Options" "DCBEVT1_soc,TB CNT equal to zero,TB CNT equal to period,TB CNT equal to zero or period,TB CNT equal to CMPA - Timer INC,TB CNT equal to CMPA - Timer DEC,TB CNT equal to CMPB - Timer INC,TB CNT equal to CMPB - Timer DEC"
bitfld.word 0x00 11. " SOCAEN ,Enable the ADC Start of Conversion A EPWMxSOCA Pulse" "Disabled,Enabled"
textline " "
bitfld.word 0x00 8.--10. " SOCASEL ,EPWMxSOCA Selection Options" "DCAEVT1_soc,TB CNT equal to zero,TB CNT equal to period,TB CNT equal to zero or period,TB CNT equal to CMPA - Timer INC,TB CNT equal to CMPA - Timer DEC,TB CNT equal to CMPB - Timer INC,TB CNT equal to CMPB - Timer DEC"
bitfld.word 0x00 3. " INTEN ,Enable ePWM Interrupt EPWMx_INT Generation" "Disabled,Enabled"
bitfld.word 0x00 0.--2. " INTSEL ,ePWM Interrupt EPWMx_INT Selection Options" ",TB CNT equal to zero,TB CNT equal to period,TB CNT equal to zero or period,TB CNT equal to CMPA - Timer INC,TB CNT equal to CMPA - Timer DEC,TB CNT equal to CMPB - Timer INC,TB CNT equal to CMPB - Timer DEC"
rgroup.word 0x34++0x01
line.word 0x00 "ETFLG,Event-Trigger Flag Register"
bitfld.word 0x00 3. " SOCB ,Latched ePWM ADC Start-of-Conversion B EPWMxSOCB Status Flag" "Not occurred,Occurred"
bitfld.word 0x00 2. " SOCA ,Latched ePWM ADC Start-of-Conversion A EPWMxSOCA Status Flag" "Not occurred,Occurred"
bitfld.word 0x00 0. " INT ,Latched ePWM Interrupt EPWMx_INT Status Flag" "Not occurred,Occurred"
group.word 0x36++0x01
line.word 0x00 "ETPS,Event-Trigger Pre-Scale Register"
rbitfld.word 0x00 14.--15. " SOCBCNT ,ePWM ADC Start-of-Conversion B Event EPWMxSOCB Counter Register" "No events,1 event,2 events,3 events"
bitfld.word 0x00 12.--13. " SOCBPRD ,ePWM ADC Start-of-Conversion B Event EPWMxSOCB Period Select" "Disabled,1st event,2nd event,3th event"
rbitfld.word 0x00 10.--11. " SOCACNT ,ePWM ADC Start-of-Conversion A Event EPWMxSOCA Counter Register" "No events,1 event,2 events,3 events"
textline " "
bitfld.word 0x00 8.--9. " SOCAPRD ,ePWM ADC Start-of-Conversion A Event EPWMxSOCA Period Select" "Disabled,1st event,2nd event,th event"
rbitfld.word 0x00 2.--3. " INTCNT ,ePWM Interrupt Event EPWMx_INT Counter Register" "No events,1 event,2 events,3 events"
bitfld.word 0x00 0.--1. " INTPRD ,ePWM Interrupt EPWMx_INT Period Select" "Disabled,1st event,2nd event,3th event"
group.word 0x38++0x01
line.word 0x00 "ETFRC,Event-Trigger Force Register"
bitfld.word 0x00 3. " SOCB ,SOCB Force Bit" "No effect,Forced"
bitfld.word 0x00 2. " SOCA ,SOCA Force Bit" "No effect,Forced"
bitfld.word 0x00 0. " INT ,INT Force Bit" "No effect,Forced"
group.word 0x3A++0x01
line.word 0x00 "ETCLR,Event-Trigger Clear Register"
bitfld.word 0x00 3. " SOCB ,ePWM ADC Start-of-Conversion B EPWMxSOCB Flag Clear Bit" "No effect,Cleared"
bitfld.word 0x00 2. " SOCA ,ePWM ADC Start-of-Conversion A EPWMxSOCB Flag Clear Bit" "No effect,Cleared"
bitfld.word 0x00 0. " INT ,ePWM Interrupt EPWMx_INT Flag Clear Bit" "No effect,Cleared"
tree.end
tree "PWM-Chopper Submodule Registers"
width 7.
group.word 0x3E++0x01
line.word 0x00 "PCCTL,PWM-Chopper Control Register"
bitfld.word 0x00 8.--10. " CHPDUTY ,Chopping Clock Duty Cycle" "1/8,2/8,3/8,4/8,5/8,6/8,7/8,?..."
bitfld.word 0x00 5.--7. " CHPFREQ ,Chopping Clock Frequency" "/1,/2,/3,/4,/5,/6,/7,/8"
bitfld.word 0x00 1.--4. " OSHTWTH ,One-Shot Pulse Width" "1 x VCLK3 / 8 wide,2 x VCLK3 / 8 wide,3 x VCLK3 / 8 wide,4 x VCLK3 / 8 wide,5 x VCLK3 / 8 wide,6 x VCLK3 / 8 wide,7 x VCLK3 / 8 wide,8 x VCLK3 / 8 wide,9 x VCLK3 / 8 wide,10 x VCLK3 / 8 wide,11 x VCLK3 / 8 wide,12 x VCLK3 / 8 wide,13 x VCLK3 / 8 wide,14 x VCLK3 / 8 wide,15 x VCLK3 / 8 wide,16 x VCLK3 / 8 wide"
textline " "
bitfld.word 0x00 0. " CHPEN ,PWM-chopping Enable" "Disabled,Enabled"
tree.end
tree "Digital Compare Event Registers"
width 14.
group.word 0x60++0x07
line.word 0x00 "DCACTL,Digital Compare A Control Register"
bitfld.word 0x00 9. " EVT2FRC_SYNCSEL ,DCAEVT2 Force Synchronization Signal Select" "Synchronous,Asynchronous"
bitfld.word 0x00 8. " EVT2SRCSEL ,DCAEVT2 Source Signal Select" "DCAEVT2,DCEVTFILT"
bitfld.word 0x00 3. " EVT1SYNCE ,DCAEVT1 SYNC Generation" "Disabled,Enabled"
textline " "
bitfld.word 0x00 2. " EVT1SOCE ,DCAEVT1 SOC Generation" "Disabled,Enabled"
bitfld.word 0x00 1. " EVT1FRC_SYNCSEL ,DCAEVT1 Force Synchronization Signal Select" "Synchronous,Asynchronous"
bitfld.word 0x00 0. " EVT1SRCSEL ,DCAEVT1 Source Signal Select" "DCAEVT,DCEVTFILT"
line.word 0x02 "DCTRIPSEL,Digital Compare Trip Select Register"
bitfld.word 0x02 12.--15. " DCBLCOMPSEL ,Digital Compare B Low Input Select" "TZ1 input,TZ2 input,TZ3 input,?..."
bitfld.word 0x02 8.--11. " DCBHCOMPSEL ,Digital Compare B High Input Select" "TZ1 input,TZ2 input,TZ3 input,?..."
bitfld.word 0x02 4.--7. " DCALCOMPSEL ,Digital Compare A Low Input Select" "TZ1 input,TZ2 input,TZ3 input,?..."
textline " "
bitfld.word 0x02 0.--3. " DCAHCOMPSEL ,Digital Compare A High Input Select" "TZ1 input,TZ2 input,TZ3 input,?..."
line.word 0x04 "DCFCTL,Digital Compare Filter Control Register"
bitfld.word 0x04 4.--5. " PULSESEL ,Pulse Select For Blanking & Capture Alignment" "TB CNT Equal to period,TB CNT Equal to zero,?..."
bitfld.word 0x04 3. " BLANKINV ,Blanking Window Inversion" "Not inverted,Inverted"
bitfld.word 0x04 2. " BLANKE ,Blanking Window Enable/Disable" "Disabled,Enabled"
textline " "
bitfld.word 0x04 0.--1. " SRCSEL ,Filter Block Signal Source Select" "DCAEVT1,DCAEVT2,DCBEVT1,DCBEVT2"
line.word 0x06 "DCBCTL,Digital Compare B Control Register"
bitfld.word 0x06 9. " EVT2FRC_SYNCSEL ,DCBEVT2 Force Synchronization Signal Select" "Synchronous,Asynchronous"
bitfld.word 0x06 8. " EVT2SRCSEL ,DCBEVT2 Source Signal Select" "DCBEVT2,DCEVTFILT"
bitfld.word 0x06 3. " EVT1SYNCE ,DCBEVT1 SYNC Generation" "Disabled,Enabled"
textline " "
bitfld.word 0x06 2. " EVT1SOCE ,DCBEVT1 SOC Generation" "Disabled,Enabled"
bitfld.word 0x06 1. " EVT1FRC_SYNCSEL ,DCBEVT1 Force Synchronization Signal Select" "Synchronous,Asynchronous"
bitfld.word 0x06 0. " EVT1SRCSEL ,DCBEVT1 Source Signal Select" "DCBEVT,DCEVTFILT"
rgroup.word 0x68++0x01
line.word 0x00 "DCOFFSET,Digital Compare Filter Offset Register"
group.word 0x6A++0x03
line.word 0x00 "DCCAPCTL,Digital Compare Capture Control Register"
bitfld.word 0x00 1. " SHDWMODE ,TBCTR Counter Capture Shadow Select Mode" "Shadow mode,Active Mode"
bitfld.word 0x00 0. " CAPE ,TBCTR Counter Capture Enable/Disable" "Disabled,Enabled"
line.word 0x02 "DCFWINDOW,Digital Compare Filter Window Register"
hexmask.word.byte 0x02 0.--7. 1. " WINDOW ,Blanking Window Width"
rgroup.word 0x6C++0x07
line.word 0x02 "DCOFFSETCNT, Digital Compare Filter Offset Counter Register"
line.word 0x04 "DCCAP, Digital Compare Counter Capture Register"
line.word 0x06 "DCFWINDOWCNT, Digital Compare Filter Window Counter Register"
hexmask.word.byte 0x06 0.--7. 1. " WINDOWCNT ,Digital Compare Filter Window Counter Register"
tree.end
width 0xB
tree.end
tree "eTPWM6"
base ad:0xFCF79100
width 11.
tree "Time-Base Submodule Registers"
group.word 0x00++0x01
line.word 0x00 "TBSTS,Time-Base Status Register"
eventfld.word 0x00 2. " CTRMAX ,Time-Base Counter Max Latched Status Bit time-base counter maximum value" "Not reached,Reached"
eventfld.word 0x00 1. " SYNCI ,Input Synchronization Latched Status Bit external synchronization event" "Not occurred,Occurred"
rbitfld.word 0x00 0. " CTRDIR ,Time-Base Counter Direction Status Bit" "Down,Up"
if (((d.w(ad:0xFCF79100+0x02))&0x30)==0x00)
group.word 0x02++0x03
line.word 0x00 "TBCTL,Time-Base Control Register"
bitfld.word 0x00 14.--15. " FREE/SOFT ,Emulation Mode Bits" "Stop after timer INC or DEC,Stop after whole cycle,Free run,Free run"
bitfld.word 0x00 13. " PHSDIR ,Phase Direction Bit" "Count down,Count up"
bitfld.word 0x00 10.--12. " CLKDIV ,Time-base Clock Prescale Bits" "/1,/2,/4,/8,/16,/32,/64,/128"
bitfld.word 0x00 7.--9. " HSPCLKDIV ,High Speed Time-base Clock Prescale Bits" "/1,/2,/4,/8,/8,/10,/12,/14"
textline " "
bitfld.word 0x00 6. " SWFSYNC ,Software Forced Synchronization Pulse" "No effect,Generated"
bitfld.word 0x00 4.--5. " SYNCOSEL ,Synchronization Output Select" "EPWMxSYNC,CTR = zero,CTR = CMPB,Disabled EPWMxSYNCO"
bitfld.word 0x00 3. " PRDLD ,Active Period Register Load From Shadow Register Select" "Not selected,Selected"
bitfld.word 0x00 2. " PHSEN ,Counter Register Load From Phase Register Enable" "Disabled,Enabled"
textline " "
bitfld.word 0x00 0.--1. " CTRMODE ,Counter Mode" "Up-count,Down-count,Up-down-count,Stop-freeze counter operation"
line.word 0x02 "TBPHS,Time-Base Phase Register"
else
group.word 0x02++0x03
line.word 0x00 "TBCTL,Time-Base Control Register"
bitfld.word 0x00 14.--15. " FREE/SOFT ,Emulation Mode Bits" "Stop after timer INC or DEC,Stop after whole cycle,Free run,Free run"
bitfld.word 0x00 13. " PHSDIR ,Phase Direction Bit" "Count down,Count up"
bitfld.word 0x00 10.--12. " CLKDIV ,Time-base Clock Prescale Bits" "/1,/2,/4,/8,/16,/32,/64,/128"
bitfld.word 0x00 7.--9. " HSPCLKDIV ,High Speed Time-base Clock Prescale Bits" "/1,/2,/4,/8,/8,/10,/12,/14"
textline " "
bitfld.word 0x00 6. " SWFSYNC ,Software Forced Synchronization Pulse" "No effect,Generated"
bitfld.word 0x00 3. " PRDLD ,Active Period Register Load From Shadow Register Select" "Not selected,Selected"
bitfld.word 0x00 2. " PHSEN ,Counter Register Load From Phase Register Enable" "Disabled,Enabled"
bitfld.word 0x00 0.--1. " CTRMODE ,Counter Mode" "Up-count,Down-count,Up-down-count,Stop-freeze counter operation"
line.word 0x02 "TBPHS, Time-Base Phase Register"
endif
group.word 0x08++0x03
line.word 0x00 "TBPRD,Time-Base Period Register"
line.word 0x02 "TBCTR,Time-Base Counter Register"
tree.end
tree "Counter-Compare Submodule Registers"
width 8.
group.word 0x0C++0x01
line.word 0x00 "CMPCTL,Counter-Compare Control Register"
rbitfld.word 0x00 9. " SHDWBFULL ,Counter-compare B CMPB Shadow Register Full Status Flag" "Not full,Full"
rbitfld.word 0x00 8. " SHDWAFULL ,Counter-compare A CMPA Shadow Register Full Status Flag" "Not full,Full"
bitfld.word 0x00 6. " SHDWBMODE ,Counter-compare B" "Shadow mode,Immediate mode"
textline " "
bitfld.word 0x00 4. " SHDWAMODE ,Counter-compare A CMPA Register Operating Mode" "Shadow mode,Immediate mode"
bitfld.word 0x00 2.--3. " LOADBMODE ,Active Counter-Compare B CMPB Load From Shadow Select Mode" "CTR=0,CTR=PRD,CTR=0/CTR=PRD,Freeze"
bitfld.word 0x00 0.--1. " LOADAMODE ,Active Counter-Compare A CMPA Load From Shadow Select Mode" "CTR=0,CTR=PRD,CTR=0/CTR=PRD,Freeze"
group.word 0x10++0x01
line.word 0x00 "CMPA,Counter-Compare A Register"
group.word 0x16++0x01
line.word 0x00 "CMPB,Counter-Compare B Register"
tree.end
tree "Action-Qualifier Submodule Registers"
width 9.
group.word 0x14++0x01
line.word 0x00 "AQCTLA,Action-Qualifier Control Register for Output A (EPWMxA)"
bitfld.word 0x00 10.--11. " CBD ,Action when the time-base counter equals the active CMPB register and the counter is decrementing" "Disabled,Cleared,Set,Toggled"
bitfld.word 0x00 8.--9. " CBU ,Action when the counter equals the active CMPB register and the counter is incrementing" "Disabled,Cleared,Set,Toggled"
bitfld.word 0x00 6.--7. " CAD ,Action when the counter equals the active CMPA register and the counter is decrementing" "Disabled,Cleared,Set,Toggled"
textline " "
bitfld.word 0x00 4.--5. " CAU ,Action when the counter equals the active CMPA register and the counter is incrementing" "Disabled,Cleared,Set,Toggled"
bitfld.word 0x00 2.--3. " PRD ,Action when the counter equals the period" "Disabled,Cleared,Set,Toggled"
bitfld.word 0x00 0.--1. " ZRO ,Action when counter equals zero" "Disabled,Cleared,Set,Toggled"
group.word 0x18++0x01
line.word 0x00 "AQSFRC,Action-Qualifier Software Force Register"
bitfld.word 0x00 6.--7. " RLDCSF ,AQCSFRC Active Register Reload From Shadow Options" "Zero,Period,Zero or Period,Immediately"
bitfld.word 0x00 5. " OTSFB ,One-Time Software Forced Event on Output B" "No effect,Forced"
bitfld.word 0x00 3.--4. " ACTSFB ,Action when One-Time Software Force B Is invoked" "Disabled,Cleared,Set,Toggled"
textline " "
bitfld.word 0x00 2. " OTSFA ,One-Time Software Forced Event on Output A" "No effect,Forced"
bitfld.word 0x00 0.--1. " ACTSFA ,Action When One-Time Software Force A Is Invoked" "Disabled,Cleared,Set,Toggled"
group.word 0x1A++0x01
line.word 0x00 "AQCTLB,Action-Qualifier Control Register for Output B (EPWMxB)"
bitfld.word 0x00 10.--11. " CBD ,Action when the time-base counter equals the active CMPB register and the counter is decrementing" "Disabled,Cleared,Set,Toggled"
bitfld.word 0x00 8.--9. " CBU ,Action when the counter equals the active CMPB register and the counter is incrementing" "Disabled,Cleared,Set,Toggled"
bitfld.word 0x00 6.--7. " CAD ,Action when the counter equals the active CMPA register and the counter is decrementing" "Disabled,Cleared,Set,Toggled"
textline " "
bitfld.word 0x00 4.--5. " CAU ,Action when the counter equals the active CMPA register and the counter is incrementing" "Disabled,Cleared,Set,Toggled"
bitfld.word 0x00 2.--3. " PRD ,Action when the counter equals the period" "Disabled,Cleared,Set,Toggled"
bitfld.word 0x00 0.--1. " ZRO ,Action when counter equals zero" "Disabled,Cleared,Set,Toggled"
group.word 0x1E++0x01
line.word 0x00 "AQCSFRC,Action-Qualifier Continuous S/W Force Register Set"
bitfld.word 0x00 2.--3. " CSFB ,Continuous Software Force on Output B" "Forced disabled,Continued low,Continued high,Soft forced disabled"
bitfld.word 0x00 0.--1. " CSFA ,Continuous Software Force on Output A" "Forced disabled,Continued low,Continued high,Soft forced disabled"
tree.end
tree "Dead-Band Generator Submodule Registers"
width 7.
group.word 0x1C++0x01
line.word 0x00 "DBCTL,Dead-Band Generator Control Register"
bitfld.word 0x00 15. " HALFCYCLE ,Half Cycle Clocking Enable Bit" "Disabled,Enabled"
bitfld.word 0x00 4.--5. " IN_MODE ,Dead Band Input Mode Control" "EPWMxA Faling&rising,EPWMxB rising / EPWMxA falling,EPWMxA rising / EPWMxB falling,EPWMxB rising&falling"
bitfld.word 0x00 2.--3. " POLSEL ,Polarity Select Control" "AH,ALC,AHC,AL"
bitfld.word 0x00 0.--1. " OUT_MODE ,Dead-band Output Mode Control" "Dead-band generation bypassed,Disabled rising-edge delay,Rising-edge delayed signal on EPWMxA,Dead-band fully enabled"
group.word 0x20++0x03
line.word 0x00 "DBFED,Dead-Band Generator Falling Edge Delay Count Register"
hexmask.word 0x00 0.--9. 1. " DEL ,Falling Edge Delay Count"
line.word 0x02 "DBRED,Dead-Band Generator Rising Edge Delay Count Register"
hexmask.word 0x02 0.--9. 1. " DEL ,Rising Edge Delay Count"
tree.end
tree "Trip-Zone Submodule Registers"
group.word 0x24++0x03
line.word 0x00 "TZDCSEL,Trip Zone Digital Compare Event Select Register"
bitfld.word 0x00 9.--11. " DCBEVT2 ,Digital Compare Output B Event 2 Selection (DCBH/DCBL)" "Disabled,Low / Don't care,High / Don't care,Don't care / Low,Don't care / High,Low / High,?..."
bitfld.word 0x00 6.--8. " DCBEVT1 ,Digital Compare Output B Event 1 Selection (DCBH/DCBL)" "Disabled,Low / Don't care,High / Don't care,Don't care / Low,Don't care / High,Low / High,?..."
textline " "
bitfld.word 0x00 3.--5. " DCAEVT2 ,Digital Compare Output A Event 2 Selection (DCAH/DCAL)" "Disabled,Low / Don't care,High / Don't care,Don't care / Low,Don't care / High,Low / High,?..."
bitfld.word 0x00 0.--2. " DCAEVT1 ,Digital Compare Output A Event 1 Selection (DCAH/DCAL)" "Disabled,Low / Don't care,High / Don't care,Don't care / Low,Don't care / High,Low / High,?..."
line.word 0x02 "TZSEL,Trip-Zone Select Register"
rbitfld.word 0x02 15. " DCBEVT1 ,Digital Compare Output B Event 1 Select" "Disabled,Enabled"
rbitfld.word 0x02 14. " DCAEVT1 ,Digital Compare Output A Event 1 Select" "Disabled,Enabled"
bitfld.word 0x02 13. " OSHT6 ,Trip-zone 6 (/TZ6) Select" "Disabled,Enabled"
textline " "
bitfld.word 0x02 12. " OSHT5 ,Trip-zone 5 (/TZ5) Select" "Disabled,Enabled"
bitfld.word 0x02 11. " OSHT4 ,Trip-zone 4 (/TZ4) Select" "Disabled,Enabled"
bitfld.word 0x02 10. " OSHT3 ,Trip-zone 3 (/TZ3) Select" "Disabled,Enabled"
textline " "
bitfld.word 0x02 9. " OSHT2 ,Trip-zone 2 (/TZ2) Select" "Disabled,Enabled"
bitfld.word 0x02 8. " OSHT1 ,Trip-zone 1 (/TZ1) Select" "Disabled,Enabled"
rbitfld.word 0x02 7. " DCBEVT2 ,Digital Compare Output B Event 2 Select" "Disabled,Enabled"
textline " "
rbitfld.word 0x02 6. " DCAEVT2 ,Digital Compare Output A Event 2 Select" "Disabled,Enabled"
bitfld.word 0x02 5. " CBC6 ,Trip-zone 6 (/TZ6) Select" "Disabled,Enabled"
bitfld.word 0x02 4. " CBC5 ,Trip-zone 5 (/TZ5) Select" "Disabled,Enabled"
textline " "
bitfld.word 0x02 3. " CBC4 ,Trip-zone 4 (/TZ4) Select" "Disabled,Enabled"
bitfld.word 0x02 2. " CBC3 ,Trip-zone 3 (/TZ3) Select" "Disabled,Enabled"
bitfld.word 0x02 1. " CBC2 ,Trip-zone 2 (/TZ2) Select" "Disabled,Enabled"
textline " "
bitfld.word 0x02 0. " CBC1 ,Trip-zone 1 (/TZ1) Select" "Disabled,Enabled"
group.word 0x28++0x01
line.word 0x00 "TZEINT,Trip-Zone Enable Interrupt Register"
bitfld.word 0x00 6. " DCBEVT2 ,Digital Comparator Output B Event 2 Interrupt Enable" "Disabled,Enabled"
bitfld.word 0x00 5. " DCBEVT1 ,Digital Comparator Output B Event 1 Interrupt Enable" "Disabled,Enabled"
bitfld.word 0x00 4. " DCAEVT2 ,Digital Comparator Output A Event 2 Interrupt Enable" "Disabled,Enabled"
textline " "
bitfld.word 0x00 3. " DCAEVT1 ,Digital Comparator Output A Event 1 Interrupt Enable" "Disabled,Enabled"
bitfld.word 0x00 2. " OST ,Trip-zone One-Shot Interrupt Enable" "Disabled,Enabled"
bitfld.word 0x00 1. " CBC ,Trip-zone Cycle-by-Cycle Interrupt Enable" "Disabled,Enabled"
group.word 0x2A++0x01
line.word 0x00 "TZCTL,Trip-Zone Control Register"
bitfld.word 0x00 10.--11. " DCBEVT2 ,Digital Compare Output B Event 2 Action On EPWMxB" "High-impedance,Forced high state,Forced low state,Disabled"
bitfld.word 0x00 8.--9. " DCBEVT1 ,Digital Compare Output B Event 1 Action On EPWMxB" "High-impedance,Forced high state,Forced low state,Disabled"
textline " "
bitfld.word 0x00 6.--7. " DCAEVT2 ,Digital Compare Output A Event 2 Action On EPWMxA" "High-impedance,Forced high state,Forced low state,Disabled"
bitfld.word 0x00 4.--5. " DCAEVT1 ,Digital Compare Output A Event 1 Action On EPWMxA" "High-impedance,Forced high state,Forced low state,Disabled"
textline " "
bitfld.word 0x00 2.--3. " TZB ,When a trip event occurs the following action is taken on output EPWMxB" "High-impedance,Forced high state,Forced low state,Disabled"
bitfld.word 0x00 0.--1. " TZA ,When a trip event occurs the following action is taken on output EPWMxA" "High-impedance,Forced high state,Forced low state,Disabled"
textline " "
group.word 0x2E++0x01
line.word 0x00 "TZFLG,Trip-Zone Flag Register"
setclrfld.word 0x00 6. 0x04 6. -0x02 6. " DCBEVT2_set/clr ,Digital Comparator Output B Event 2 Interrupt" "Not occurred,Occurred"
setclrfld.word 0x00 5. 0x04 5. -0x02 5. " DCBEVT1_set/clr ,Digital Comparator Output B Event 1 Interrupt" "Not occurred,Occurred"
textline " "
setclrfld.word 0x00 4. 0x04 4. -0x02 4. " DCAEVT2_set/clr ,Digital Comparator Output A Event 2 Interrupt" "Not occurred,Occurred"
setclrfld.word 0x00 3. 0x04 3. -0x02 3. " DCAEVT1_set/clr ,Digital Comparator Output A Event 1 Interrupt" "Not occurred,Occurred"
textline " "
setclrfld.word 0x00 2. 0x04 2. -0x02 2. " OST_set/clr ,Trip-zone One-Shot Interrupt" "Not occurred,Occurred"
setclrfld.word 0x00 1. 0x04 1. -0x02 1. " CBC_set/clr ,Trip-zone Cycle-by-Cycle Interrupt" "Not occurred,Occurred"
textline " "
setclrfld.word 0x00 0. 0x04 0. -0x02 0. " INT_set/clr ,Latched Trip Interrupt Status Flag" "Not generated,Generated"
tree.end
tree "Event-Trigger Submodule Registers"
width 7.
group.word 0x30++0x01
line.word 0x00 "ETSEL,Event-Trigger Selection Register"
bitfld.word 0x00 15. " SOCBEN ,Enable the ADC Start of Conversion B EPWMxSOCB Pulse" "Disabled,Enabled"
bitfld.word 0x00 12.--14. " SOCBSEL ,EPWMxSOCB Selection Options" "DCBEVT1_soc,TB CNT equal to zero,TB CNT equal to period,TB CNT equal to zero or period,TB CNT equal to CMPA - Timer INC,TB CNT equal to CMPA - Timer DEC,TB CNT equal to CMPB - Timer INC,TB CNT equal to CMPB - Timer DEC"
bitfld.word 0x00 11. " SOCAEN ,Enable the ADC Start of Conversion A EPWMxSOCA Pulse" "Disabled,Enabled"
textline " "
bitfld.word 0x00 8.--10. " SOCASEL ,EPWMxSOCA Selection Options" "DCAEVT1_soc,TB CNT equal to zero,TB CNT equal to period,TB CNT equal to zero or period,TB CNT equal to CMPA - Timer INC,TB CNT equal to CMPA - Timer DEC,TB CNT equal to CMPB - Timer INC,TB CNT equal to CMPB - Timer DEC"
bitfld.word 0x00 3. " INTEN ,Enable ePWM Interrupt EPWMx_INT Generation" "Disabled,Enabled"
bitfld.word 0x00 0.--2. " INTSEL ,ePWM Interrupt EPWMx_INT Selection Options" ",TB CNT equal to zero,TB CNT equal to period,TB CNT equal to zero or period,TB CNT equal to CMPA - Timer INC,TB CNT equal to CMPA - Timer DEC,TB CNT equal to CMPB - Timer INC,TB CNT equal to CMPB - Timer DEC"
rgroup.word 0x34++0x01
line.word 0x00 "ETFLG,Event-Trigger Flag Register"
bitfld.word 0x00 3. " SOCB ,Latched ePWM ADC Start-of-Conversion B EPWMxSOCB Status Flag" "Not occurred,Occurred"
bitfld.word 0x00 2. " SOCA ,Latched ePWM ADC Start-of-Conversion A EPWMxSOCA Status Flag" "Not occurred,Occurred"
bitfld.word 0x00 0. " INT ,Latched ePWM Interrupt EPWMx_INT Status Flag" "Not occurred,Occurred"
group.word 0x36++0x01
line.word 0x00 "ETPS,Event-Trigger Pre-Scale Register"
rbitfld.word 0x00 14.--15. " SOCBCNT ,ePWM ADC Start-of-Conversion B Event EPWMxSOCB Counter Register" "No events,1 event,2 events,3 events"
bitfld.word 0x00 12.--13. " SOCBPRD ,ePWM ADC Start-of-Conversion B Event EPWMxSOCB Period Select" "Disabled,1st event,2nd event,3th event"
rbitfld.word 0x00 10.--11. " SOCACNT ,ePWM ADC Start-of-Conversion A Event EPWMxSOCA Counter Register" "No events,1 event,2 events,3 events"
textline " "
bitfld.word 0x00 8.--9. " SOCAPRD ,ePWM ADC Start-of-Conversion A Event EPWMxSOCA Period Select" "Disabled,1st event,2nd event,th event"
rbitfld.word 0x00 2.--3. " INTCNT ,ePWM Interrupt Event EPWMx_INT Counter Register" "No events,1 event,2 events,3 events"
bitfld.word 0x00 0.--1. " INTPRD ,ePWM Interrupt EPWMx_INT Period Select" "Disabled,1st event,2nd event,3th event"
group.word 0x38++0x01
line.word 0x00 "ETFRC,Event-Trigger Force Register"
bitfld.word 0x00 3. " SOCB ,SOCB Force Bit" "No effect,Forced"
bitfld.word 0x00 2. " SOCA ,SOCA Force Bit" "No effect,Forced"
bitfld.word 0x00 0. " INT ,INT Force Bit" "No effect,Forced"
group.word 0x3A++0x01
line.word 0x00 "ETCLR,Event-Trigger Clear Register"
bitfld.word 0x00 3. " SOCB ,ePWM ADC Start-of-Conversion B EPWMxSOCB Flag Clear Bit" "No effect,Cleared"
bitfld.word 0x00 2. " SOCA ,ePWM ADC Start-of-Conversion A EPWMxSOCB Flag Clear Bit" "No effect,Cleared"
bitfld.word 0x00 0. " INT ,ePWM Interrupt EPWMx_INT Flag Clear Bit" "No effect,Cleared"
tree.end
tree "PWM-Chopper Submodule Registers"
width 7.
group.word 0x3E++0x01
line.word 0x00 "PCCTL,PWM-Chopper Control Register"
bitfld.word 0x00 8.--10. " CHPDUTY ,Chopping Clock Duty Cycle" "1/8,2/8,3/8,4/8,5/8,6/8,7/8,?..."
bitfld.word 0x00 5.--7. " CHPFREQ ,Chopping Clock Frequency" "/1,/2,/3,/4,/5,/6,/7,/8"
bitfld.word 0x00 1.--4. " OSHTWTH ,One-Shot Pulse Width" "1 x VCLK3 / 8 wide,2 x VCLK3 / 8 wide,3 x VCLK3 / 8 wide,4 x VCLK3 / 8 wide,5 x VCLK3 / 8 wide,6 x VCLK3 / 8 wide,7 x VCLK3 / 8 wide,8 x VCLK3 / 8 wide,9 x VCLK3 / 8 wide,10 x VCLK3 / 8 wide,11 x VCLK3 / 8 wide,12 x VCLK3 / 8 wide,13 x VCLK3 / 8 wide,14 x VCLK3 / 8 wide,15 x VCLK3 / 8 wide,16 x VCLK3 / 8 wide"
textline " "
bitfld.word 0x00 0. " CHPEN ,PWM-chopping Enable" "Disabled,Enabled"
tree.end
tree "Digital Compare Event Registers"
width 14.
group.word 0x60++0x07
line.word 0x00 "DCACTL,Digital Compare A Control Register"
bitfld.word 0x00 9. " EVT2FRC_SYNCSEL ,DCAEVT2 Force Synchronization Signal Select" "Synchronous,Asynchronous"
bitfld.word 0x00 8. " EVT2SRCSEL ,DCAEVT2 Source Signal Select" "DCAEVT2,DCEVTFILT"
bitfld.word 0x00 3. " EVT1SYNCE ,DCAEVT1 SYNC Generation" "Disabled,Enabled"
textline " "
bitfld.word 0x00 2. " EVT1SOCE ,DCAEVT1 SOC Generation" "Disabled,Enabled"
bitfld.word 0x00 1. " EVT1FRC_SYNCSEL ,DCAEVT1 Force Synchronization Signal Select" "Synchronous,Asynchronous"
bitfld.word 0x00 0. " EVT1SRCSEL ,DCAEVT1 Source Signal Select" "DCAEVT,DCEVTFILT"
line.word 0x02 "DCTRIPSEL,Digital Compare Trip Select Register"
bitfld.word 0x02 12.--15. " DCBLCOMPSEL ,Digital Compare B Low Input Select" "TZ1 input,TZ2 input,TZ3 input,?..."
bitfld.word 0x02 8.--11. " DCBHCOMPSEL ,Digital Compare B High Input Select" "TZ1 input,TZ2 input,TZ3 input,?..."
bitfld.word 0x02 4.--7. " DCALCOMPSEL ,Digital Compare A Low Input Select" "TZ1 input,TZ2 input,TZ3 input,?..."
textline " "
bitfld.word 0x02 0.--3. " DCAHCOMPSEL ,Digital Compare A High Input Select" "TZ1 input,TZ2 input,TZ3 input,?..."
line.word 0x04 "DCFCTL,Digital Compare Filter Control Register"
bitfld.word 0x04 4.--5. " PULSESEL ,Pulse Select For Blanking & Capture Alignment" "TB CNT Equal to period,TB CNT Equal to zero,?..."
bitfld.word 0x04 3. " BLANKINV ,Blanking Window Inversion" "Not inverted,Inverted"
bitfld.word 0x04 2. " BLANKE ,Blanking Window Enable/Disable" "Disabled,Enabled"
textline " "
bitfld.word 0x04 0.--1. " SRCSEL ,Filter Block Signal Source Select" "DCAEVT1,DCAEVT2,DCBEVT1,DCBEVT2"
line.word 0x06 "DCBCTL,Digital Compare B Control Register"
bitfld.word 0x06 9. " EVT2FRC_SYNCSEL ,DCBEVT2 Force Synchronization Signal Select" "Synchronous,Asynchronous"
bitfld.word 0x06 8. " EVT2SRCSEL ,DCBEVT2 Source Signal Select" "DCBEVT2,DCEVTFILT"
bitfld.word 0x06 3. " EVT1SYNCE ,DCBEVT1 SYNC Generation" "Disabled,Enabled"
textline " "
bitfld.word 0x06 2. " EVT1SOCE ,DCBEVT1 SOC Generation" "Disabled,Enabled"
bitfld.word 0x06 1. " EVT1FRC_SYNCSEL ,DCBEVT1 Force Synchronization Signal Select" "Synchronous,Asynchronous"
bitfld.word 0x06 0. " EVT1SRCSEL ,DCBEVT1 Source Signal Select" "DCBEVT,DCEVTFILT"
rgroup.word 0x68++0x01
line.word 0x00 "DCOFFSET,Digital Compare Filter Offset Register"
group.word 0x6A++0x03
line.word 0x00 "DCCAPCTL,Digital Compare Capture Control Register"
bitfld.word 0x00 1. " SHDWMODE ,TBCTR Counter Capture Shadow Select Mode" "Shadow mode,Active Mode"
bitfld.word 0x00 0. " CAPE ,TBCTR Counter Capture Enable/Disable" "Disabled,Enabled"
line.word 0x02 "DCFWINDOW,Digital Compare Filter Window Register"
hexmask.word.byte 0x02 0.--7. 1. " WINDOW ,Blanking Window Width"
rgroup.word 0x6C++0x07
line.word 0x02 "DCOFFSETCNT, Digital Compare Filter Offset Counter Register"
line.word 0x04 "DCCAP, Digital Compare Counter Capture Register"
line.word 0x06 "DCFWINDOWCNT, Digital Compare Filter Window Counter Register"
hexmask.word.byte 0x06 0.--7. 1. " WINDOWCNT ,Digital Compare Filter Window Counter Register"
tree.end
width 0xB
tree.end
tree "eTPWM7"
base ad:0xFCF79200
width 11.
tree "Time-Base Submodule Registers"
group.word 0x00++0x01
line.word 0x00 "TBSTS,Time-Base Status Register"
eventfld.word 0x00 2. " CTRMAX ,Time-Base Counter Max Latched Status Bit time-base counter maximum value" "Not reached,Reached"
eventfld.word 0x00 1. " SYNCI ,Input Synchronization Latched Status Bit external synchronization event" "Not occurred,Occurred"
rbitfld.word 0x00 0. " CTRDIR ,Time-Base Counter Direction Status Bit" "Down,Up"
if (((d.w(ad:0xFCF79200+0x02))&0x30)==0x00)
group.word 0x02++0x03
line.word 0x00 "TBCTL,Time-Base Control Register"
bitfld.word 0x00 14.--15. " FREE/SOFT ,Emulation Mode Bits" "Stop after timer INC or DEC,Stop after whole cycle,Free run,Free run"
bitfld.word 0x00 13. " PHSDIR ,Phase Direction Bit" "Count down,Count up"
bitfld.word 0x00 10.--12. " CLKDIV ,Time-base Clock Prescale Bits" "/1,/2,/4,/8,/16,/32,/64,/128"
bitfld.word 0x00 7.--9. " HSPCLKDIV ,High Speed Time-base Clock Prescale Bits" "/1,/2,/4,/8,/8,/10,/12,/14"
textline " "
bitfld.word 0x00 6. " SWFSYNC ,Software Forced Synchronization Pulse" "No effect,Generated"
bitfld.word 0x00 4.--5. " SYNCOSEL ,Synchronization Output Select" "EPWMxSYNC,CTR = zero,CTR = CMPB,Disabled EPWMxSYNCO"
bitfld.word 0x00 3. " PRDLD ,Active Period Register Load From Shadow Register Select" "Not selected,Selected"
bitfld.word 0x00 2. " PHSEN ,Counter Register Load From Phase Register Enable" "Disabled,Enabled"
textline " "
bitfld.word 0x00 0.--1. " CTRMODE ,Counter Mode" "Up-count,Down-count,Up-down-count,Stop-freeze counter operation"
line.word 0x02 "TBPHS,Time-Base Phase Register"
else
group.word 0x02++0x03
line.word 0x00 "TBCTL,Time-Base Control Register"
bitfld.word 0x00 14.--15. " FREE/SOFT ,Emulation Mode Bits" "Stop after timer INC or DEC,Stop after whole cycle,Free run,Free run"
bitfld.word 0x00 13. " PHSDIR ,Phase Direction Bit" "Count down,Count up"
bitfld.word 0x00 10.--12. " CLKDIV ,Time-base Clock Prescale Bits" "/1,/2,/4,/8,/16,/32,/64,/128"
bitfld.word 0x00 7.--9. " HSPCLKDIV ,High Speed Time-base Clock Prescale Bits" "/1,/2,/4,/8,/8,/10,/12,/14"
textline " "
bitfld.word 0x00 6. " SWFSYNC ,Software Forced Synchronization Pulse" "No effect,Generated"
bitfld.word 0x00 3. " PRDLD ,Active Period Register Load From Shadow Register Select" "Not selected,Selected"
bitfld.word 0x00 2. " PHSEN ,Counter Register Load From Phase Register Enable" "Disabled,Enabled"
bitfld.word 0x00 0.--1. " CTRMODE ,Counter Mode" "Up-count,Down-count,Up-down-count,Stop-freeze counter operation"
line.word 0x02 "TBPHS, Time-Base Phase Register"
endif
group.word 0x08++0x03
line.word 0x00 "TBPRD,Time-Base Period Register"
line.word 0x02 "TBCTR,Time-Base Counter Register"
tree.end
tree "Counter-Compare Submodule Registers"
width 8.
group.word 0x0C++0x01
line.word 0x00 "CMPCTL,Counter-Compare Control Register"
rbitfld.word 0x00 9. " SHDWBFULL ,Counter-compare B CMPB Shadow Register Full Status Flag" "Not full,Full"
rbitfld.word 0x00 8. " SHDWAFULL ,Counter-compare A CMPA Shadow Register Full Status Flag" "Not full,Full"
bitfld.word 0x00 6. " SHDWBMODE ,Counter-compare B" "Shadow mode,Immediate mode"
textline " "
bitfld.word 0x00 4. " SHDWAMODE ,Counter-compare A CMPA Register Operating Mode" "Shadow mode,Immediate mode"
bitfld.word 0x00 2.--3. " LOADBMODE ,Active Counter-Compare B CMPB Load From Shadow Select Mode" "CTR=0,CTR=PRD,CTR=0/CTR=PRD,Freeze"
bitfld.word 0x00 0.--1. " LOADAMODE ,Active Counter-Compare A CMPA Load From Shadow Select Mode" "CTR=0,CTR=PRD,CTR=0/CTR=PRD,Freeze"
group.word 0x10++0x01
line.word 0x00 "CMPA,Counter-Compare A Register"
group.word 0x16++0x01
line.word 0x00 "CMPB,Counter-Compare B Register"
tree.end
tree "Action-Qualifier Submodule Registers"
width 9.
group.word 0x14++0x01
line.word 0x00 "AQCTLA,Action-Qualifier Control Register for Output A (EPWMxA)"
bitfld.word 0x00 10.--11. " CBD ,Action when the time-base counter equals the active CMPB register and the counter is decrementing" "Disabled,Cleared,Set,Toggled"
bitfld.word 0x00 8.--9. " CBU ,Action when the counter equals the active CMPB register and the counter is incrementing" "Disabled,Cleared,Set,Toggled"
bitfld.word 0x00 6.--7. " CAD ,Action when the counter equals the active CMPA register and the counter is decrementing" "Disabled,Cleared,Set,Toggled"
textline " "
bitfld.word 0x00 4.--5. " CAU ,Action when the counter equals the active CMPA register and the counter is incrementing" "Disabled,Cleared,Set,Toggled"
bitfld.word 0x00 2.--3. " PRD ,Action when the counter equals the period" "Disabled,Cleared,Set,Toggled"
bitfld.word 0x00 0.--1. " ZRO ,Action when counter equals zero" "Disabled,Cleared,Set,Toggled"
group.word 0x18++0x01
line.word 0x00 "AQSFRC,Action-Qualifier Software Force Register"
bitfld.word 0x00 6.--7. " RLDCSF ,AQCSFRC Active Register Reload From Shadow Options" "Zero,Period,Zero or Period,Immediately"
bitfld.word 0x00 5. " OTSFB ,One-Time Software Forced Event on Output B" "No effect,Forced"
bitfld.word 0x00 3.--4. " ACTSFB ,Action when One-Time Software Force B Is invoked" "Disabled,Cleared,Set,Toggled"
textline " "
bitfld.word 0x00 2. " OTSFA ,One-Time Software Forced Event on Output A" "No effect,Forced"
bitfld.word 0x00 0.--1. " ACTSFA ,Action When One-Time Software Force A Is Invoked" "Disabled,Cleared,Set,Toggled"
group.word 0x1A++0x01
line.word 0x00 "AQCTLB,Action-Qualifier Control Register for Output B (EPWMxB)"
bitfld.word 0x00 10.--11. " CBD ,Action when the time-base counter equals the active CMPB register and the counter is decrementing" "Disabled,Cleared,Set,Toggled"
bitfld.word 0x00 8.--9. " CBU ,Action when the counter equals the active CMPB register and the counter is incrementing" "Disabled,Cleared,Set,Toggled"
bitfld.word 0x00 6.--7. " CAD ,Action when the counter equals the active CMPA register and the counter is decrementing" "Disabled,Cleared,Set,Toggled"
textline " "
bitfld.word 0x00 4.--5. " CAU ,Action when the counter equals the active CMPA register and the counter is incrementing" "Disabled,Cleared,Set,Toggled"
bitfld.word 0x00 2.--3. " PRD ,Action when the counter equals the period" "Disabled,Cleared,Set,Toggled"
bitfld.word 0x00 0.--1. " ZRO ,Action when counter equals zero" "Disabled,Cleared,Set,Toggled"
group.word 0x1E++0x01
line.word 0x00 "AQCSFRC,Action-Qualifier Continuous S/W Force Register Set"
bitfld.word 0x00 2.--3. " CSFB ,Continuous Software Force on Output B" "Forced disabled,Continued low,Continued high,Soft forced disabled"
bitfld.word 0x00 0.--1. " CSFA ,Continuous Software Force on Output A" "Forced disabled,Continued low,Continued high,Soft forced disabled"
tree.end
tree "Dead-Band Generator Submodule Registers"
width 7.
group.word 0x1C++0x01
line.word 0x00 "DBCTL,Dead-Band Generator Control Register"
bitfld.word 0x00 15. " HALFCYCLE ,Half Cycle Clocking Enable Bit" "Disabled,Enabled"
bitfld.word 0x00 4.--5. " IN_MODE ,Dead Band Input Mode Control" "EPWMxA Faling&rising,EPWMxB rising / EPWMxA falling,EPWMxA rising / EPWMxB falling,EPWMxB rising&falling"
bitfld.word 0x00 2.--3. " POLSEL ,Polarity Select Control" "AH,ALC,AHC,AL"
bitfld.word 0x00 0.--1. " OUT_MODE ,Dead-band Output Mode Control" "Dead-band generation bypassed,Disabled rising-edge delay,Rising-edge delayed signal on EPWMxA,Dead-band fully enabled"
group.word 0x20++0x03
line.word 0x00 "DBFED,Dead-Band Generator Falling Edge Delay Count Register"
hexmask.word 0x00 0.--9. 1. " DEL ,Falling Edge Delay Count"
line.word 0x02 "DBRED,Dead-Band Generator Rising Edge Delay Count Register"
hexmask.word 0x02 0.--9. 1. " DEL ,Rising Edge Delay Count"
tree.end
tree "Trip-Zone Submodule Registers"
group.word 0x24++0x03
line.word 0x00 "TZDCSEL,Trip Zone Digital Compare Event Select Register"
bitfld.word 0x00 9.--11. " DCBEVT2 ,Digital Compare Output B Event 2 Selection (DCBH/DCBL)" "Disabled,Low / Don't care,High / Don't care,Don't care / Low,Don't care / High,Low / High,?..."
bitfld.word 0x00 6.--8. " DCBEVT1 ,Digital Compare Output B Event 1 Selection (DCBH/DCBL)" "Disabled,Low / Don't care,High / Don't care,Don't care / Low,Don't care / High,Low / High,?..."
textline " "
bitfld.word 0x00 3.--5. " DCAEVT2 ,Digital Compare Output A Event 2 Selection (DCAH/DCAL)" "Disabled,Low / Don't care,High / Don't care,Don't care / Low,Don't care / High,Low / High,?..."
bitfld.word 0x00 0.--2. " DCAEVT1 ,Digital Compare Output A Event 1 Selection (DCAH/DCAL)" "Disabled,Low / Don't care,High / Don't care,Don't care / Low,Don't care / High,Low / High,?..."
line.word 0x02 "TZSEL,Trip-Zone Select Register"
rbitfld.word 0x02 15. " DCBEVT1 ,Digital Compare Output B Event 1 Select" "Disabled,Enabled"
rbitfld.word 0x02 14. " DCAEVT1 ,Digital Compare Output A Event 1 Select" "Disabled,Enabled"
bitfld.word 0x02 13. " OSHT6 ,Trip-zone 6 (/TZ6) Select" "Disabled,Enabled"
textline " "
bitfld.word 0x02 12. " OSHT5 ,Trip-zone 5 (/TZ5) Select" "Disabled,Enabled"
bitfld.word 0x02 11. " OSHT4 ,Trip-zone 4 (/TZ4) Select" "Disabled,Enabled"
bitfld.word 0x02 10. " OSHT3 ,Trip-zone 3 (/TZ3) Select" "Disabled,Enabled"
textline " "
bitfld.word 0x02 9. " OSHT2 ,Trip-zone 2 (/TZ2) Select" "Disabled,Enabled"
bitfld.word 0x02 8. " OSHT1 ,Trip-zone 1 (/TZ1) Select" "Disabled,Enabled"
rbitfld.word 0x02 7. " DCBEVT2 ,Digital Compare Output B Event 2 Select" "Disabled,Enabled"
textline " "
rbitfld.word 0x02 6. " DCAEVT2 ,Digital Compare Output A Event 2 Select" "Disabled,Enabled"
bitfld.word 0x02 5. " CBC6 ,Trip-zone 6 (/TZ6) Select" "Disabled,Enabled"
bitfld.word 0x02 4. " CBC5 ,Trip-zone 5 (/TZ5) Select" "Disabled,Enabled"
textline " "
bitfld.word 0x02 3. " CBC4 ,Trip-zone 4 (/TZ4) Select" "Disabled,Enabled"
bitfld.word 0x02 2. " CBC3 ,Trip-zone 3 (/TZ3) Select" "Disabled,Enabled"
bitfld.word 0x02 1. " CBC2 ,Trip-zone 2 (/TZ2) Select" "Disabled,Enabled"
textline " "
bitfld.word 0x02 0. " CBC1 ,Trip-zone 1 (/TZ1) Select" "Disabled,Enabled"
group.word 0x28++0x01
line.word 0x00 "TZEINT,Trip-Zone Enable Interrupt Register"
bitfld.word 0x00 6. " DCBEVT2 ,Digital Comparator Output B Event 2 Interrupt Enable" "Disabled,Enabled"
bitfld.word 0x00 5. " DCBEVT1 ,Digital Comparator Output B Event 1 Interrupt Enable" "Disabled,Enabled"
bitfld.word 0x00 4. " DCAEVT2 ,Digital Comparator Output A Event 2 Interrupt Enable" "Disabled,Enabled"
textline " "
bitfld.word 0x00 3. " DCAEVT1 ,Digital Comparator Output A Event 1 Interrupt Enable" "Disabled,Enabled"
bitfld.word 0x00 2. " OST ,Trip-zone One-Shot Interrupt Enable" "Disabled,Enabled"
bitfld.word 0x00 1. " CBC ,Trip-zone Cycle-by-Cycle Interrupt Enable" "Disabled,Enabled"
group.word 0x2A++0x01
line.word 0x00 "TZCTL,Trip-Zone Control Register"
bitfld.word 0x00 10.--11. " DCBEVT2 ,Digital Compare Output B Event 2 Action On EPWMxB" "High-impedance,Forced high state,Forced low state,Disabled"
bitfld.word 0x00 8.--9. " DCBEVT1 ,Digital Compare Output B Event 1 Action On EPWMxB" "High-impedance,Forced high state,Forced low state,Disabled"
textline " "
bitfld.word 0x00 6.--7. " DCAEVT2 ,Digital Compare Output A Event 2 Action On EPWMxA" "High-impedance,Forced high state,Forced low state,Disabled"
bitfld.word 0x00 4.--5. " DCAEVT1 ,Digital Compare Output A Event 1 Action On EPWMxA" "High-impedance,Forced high state,Forced low state,Disabled"
textline " "
bitfld.word 0x00 2.--3. " TZB ,When a trip event occurs the following action is taken on output EPWMxB" "High-impedance,Forced high state,Forced low state,Disabled"
bitfld.word 0x00 0.--1. " TZA ,When a trip event occurs the following action is taken on output EPWMxA" "High-impedance,Forced high state,Forced low state,Disabled"
textline " "
group.word 0x2E++0x01
line.word 0x00 "TZFLG,Trip-Zone Flag Register"
setclrfld.word 0x00 6. 0x04 6. -0x02 6. " DCBEVT2_set/clr ,Digital Comparator Output B Event 2 Interrupt" "Not occurred,Occurred"
setclrfld.word 0x00 5. 0x04 5. -0x02 5. " DCBEVT1_set/clr ,Digital Comparator Output B Event 1 Interrupt" "Not occurred,Occurred"
textline " "
setclrfld.word 0x00 4. 0x04 4. -0x02 4. " DCAEVT2_set/clr ,Digital Comparator Output A Event 2 Interrupt" "Not occurred,Occurred"
setclrfld.word 0x00 3. 0x04 3. -0x02 3. " DCAEVT1_set/clr ,Digital Comparator Output A Event 1 Interrupt" "Not occurred,Occurred"
textline " "
setclrfld.word 0x00 2. 0x04 2. -0x02 2. " OST_set/clr ,Trip-zone One-Shot Interrupt" "Not occurred,Occurred"
setclrfld.word 0x00 1. 0x04 1. -0x02 1. " CBC_set/clr ,Trip-zone Cycle-by-Cycle Interrupt" "Not occurred,Occurred"
textline " "
setclrfld.word 0x00 0. 0x04 0. -0x02 0. " INT_set/clr ,Latched Trip Interrupt Status Flag" "Not generated,Generated"
tree.end
tree "Event-Trigger Submodule Registers"
width 7.
group.word 0x30++0x01
line.word 0x00 "ETSEL,Event-Trigger Selection Register"
bitfld.word 0x00 15. " SOCBEN ,Enable the ADC Start of Conversion B EPWMxSOCB Pulse" "Disabled,Enabled"
bitfld.word 0x00 12.--14. " SOCBSEL ,EPWMxSOCB Selection Options" "DCBEVT1_soc,TB CNT equal to zero,TB CNT equal to period,TB CNT equal to zero or period,TB CNT equal to CMPA - Timer INC,TB CNT equal to CMPA - Timer DEC,TB CNT equal to CMPB - Timer INC,TB CNT equal to CMPB - Timer DEC"
bitfld.word 0x00 11. " SOCAEN ,Enable the ADC Start of Conversion A EPWMxSOCA Pulse" "Disabled,Enabled"
textline " "
bitfld.word 0x00 8.--10. " SOCASEL ,EPWMxSOCA Selection Options" "DCAEVT1_soc,TB CNT equal to zero,TB CNT equal to period,TB CNT equal to zero or period,TB CNT equal to CMPA - Timer INC,TB CNT equal to CMPA - Timer DEC,TB CNT equal to CMPB - Timer INC,TB CNT equal to CMPB - Timer DEC"
bitfld.word 0x00 3. " INTEN ,Enable ePWM Interrupt EPWMx_INT Generation" "Disabled,Enabled"
bitfld.word 0x00 0.--2. " INTSEL ,ePWM Interrupt EPWMx_INT Selection Options" ",TB CNT equal to zero,TB CNT equal to period,TB CNT equal to zero or period,TB CNT equal to CMPA - Timer INC,TB CNT equal to CMPA - Timer DEC,TB CNT equal to CMPB - Timer INC,TB CNT equal to CMPB - Timer DEC"
rgroup.word 0x34++0x01
line.word 0x00 "ETFLG,Event-Trigger Flag Register"
bitfld.word 0x00 3. " SOCB ,Latched ePWM ADC Start-of-Conversion B EPWMxSOCB Status Flag" "Not occurred,Occurred"
bitfld.word 0x00 2. " SOCA ,Latched ePWM ADC Start-of-Conversion A EPWMxSOCA Status Flag" "Not occurred,Occurred"
bitfld.word 0x00 0. " INT ,Latched ePWM Interrupt EPWMx_INT Status Flag" "Not occurred,Occurred"
group.word 0x36++0x01
line.word 0x00 "ETPS,Event-Trigger Pre-Scale Register"
rbitfld.word 0x00 14.--15. " SOCBCNT ,ePWM ADC Start-of-Conversion B Event EPWMxSOCB Counter Register" "No events,1 event,2 events,3 events"
bitfld.word 0x00 12.--13. " SOCBPRD ,ePWM ADC Start-of-Conversion B Event EPWMxSOCB Period Select" "Disabled,1st event,2nd event,3th event"
rbitfld.word 0x00 10.--11. " SOCACNT ,ePWM ADC Start-of-Conversion A Event EPWMxSOCA Counter Register" "No events,1 event,2 events,3 events"
textline " "
bitfld.word 0x00 8.--9. " SOCAPRD ,ePWM ADC Start-of-Conversion A Event EPWMxSOCA Period Select" "Disabled,1st event,2nd event,th event"
rbitfld.word 0x00 2.--3. " INTCNT ,ePWM Interrupt Event EPWMx_INT Counter Register" "No events,1 event,2 events,3 events"
bitfld.word 0x00 0.--1. " INTPRD ,ePWM Interrupt EPWMx_INT Period Select" "Disabled,1st event,2nd event,3th event"
group.word 0x38++0x01
line.word 0x00 "ETFRC,Event-Trigger Force Register"
bitfld.word 0x00 3. " SOCB ,SOCB Force Bit" "No effect,Forced"
bitfld.word 0x00 2. " SOCA ,SOCA Force Bit" "No effect,Forced"
bitfld.word 0x00 0. " INT ,INT Force Bit" "No effect,Forced"
group.word 0x3A++0x01
line.word 0x00 "ETCLR,Event-Trigger Clear Register"
bitfld.word 0x00 3. " SOCB ,ePWM ADC Start-of-Conversion B EPWMxSOCB Flag Clear Bit" "No effect,Cleared"
bitfld.word 0x00 2. " SOCA ,ePWM ADC Start-of-Conversion A EPWMxSOCB Flag Clear Bit" "No effect,Cleared"
bitfld.word 0x00 0. " INT ,ePWM Interrupt EPWMx_INT Flag Clear Bit" "No effect,Cleared"
tree.end
tree "PWM-Chopper Submodule Registers"
width 7.
group.word 0x3E++0x01
line.word 0x00 "PCCTL,PWM-Chopper Control Register"
bitfld.word 0x00 8.--10. " CHPDUTY ,Chopping Clock Duty Cycle" "1/8,2/8,3/8,4/8,5/8,6/8,7/8,?..."
bitfld.word 0x00 5.--7. " CHPFREQ ,Chopping Clock Frequency" "/1,/2,/3,/4,/5,/6,/7,/8"
bitfld.word 0x00 1.--4. " OSHTWTH ,One-Shot Pulse Width" "1 x VCLK3 / 8 wide,2 x VCLK3 / 8 wide,3 x VCLK3 / 8 wide,4 x VCLK3 / 8 wide,5 x VCLK3 / 8 wide,6 x VCLK3 / 8 wide,7 x VCLK3 / 8 wide,8 x VCLK3 / 8 wide,9 x VCLK3 / 8 wide,10 x VCLK3 / 8 wide,11 x VCLK3 / 8 wide,12 x VCLK3 / 8 wide,13 x VCLK3 / 8 wide,14 x VCLK3 / 8 wide,15 x VCLK3 / 8 wide,16 x VCLK3 / 8 wide"
textline " "
bitfld.word 0x00 0. " CHPEN ,PWM-chopping Enable" "Disabled,Enabled"
tree.end
tree "Digital Compare Event Registers"
width 14.
group.word 0x60++0x07
line.word 0x00 "DCACTL,Digital Compare A Control Register"
bitfld.word 0x00 9. " EVT2FRC_SYNCSEL ,DCAEVT2 Force Synchronization Signal Select" "Synchronous,Asynchronous"
bitfld.word 0x00 8. " EVT2SRCSEL ,DCAEVT2 Source Signal Select" "DCAEVT2,DCEVTFILT"
bitfld.word 0x00 3. " EVT1SYNCE ,DCAEVT1 SYNC Generation" "Disabled,Enabled"
textline " "
bitfld.word 0x00 2. " EVT1SOCE ,DCAEVT1 SOC Generation" "Disabled,Enabled"
bitfld.word 0x00 1. " EVT1FRC_SYNCSEL ,DCAEVT1 Force Synchronization Signal Select" "Synchronous,Asynchronous"
bitfld.word 0x00 0. " EVT1SRCSEL ,DCAEVT1 Source Signal Select" "DCAEVT,DCEVTFILT"
line.word 0x02 "DCTRIPSEL,Digital Compare Trip Select Register"
bitfld.word 0x02 12.--15. " DCBLCOMPSEL ,Digital Compare B Low Input Select" "TZ1 input,TZ2 input,TZ3 input,?..."
bitfld.word 0x02 8.--11. " DCBHCOMPSEL ,Digital Compare B High Input Select" "TZ1 input,TZ2 input,TZ3 input,?..."
bitfld.word 0x02 4.--7. " DCALCOMPSEL ,Digital Compare A Low Input Select" "TZ1 input,TZ2 input,TZ3 input,?..."
textline " "
bitfld.word 0x02 0.--3. " DCAHCOMPSEL ,Digital Compare A High Input Select" "TZ1 input,TZ2 input,TZ3 input,?..."
line.word 0x04 "DCFCTL,Digital Compare Filter Control Register"
bitfld.word 0x04 4.--5. " PULSESEL ,Pulse Select For Blanking & Capture Alignment" "TB CNT Equal to period,TB CNT Equal to zero,?..."
bitfld.word 0x04 3. " BLANKINV ,Blanking Window Inversion" "Not inverted,Inverted"
bitfld.word 0x04 2. " BLANKE ,Blanking Window Enable/Disable" "Disabled,Enabled"
textline " "
bitfld.word 0x04 0.--1. " SRCSEL ,Filter Block Signal Source Select" "DCAEVT1,DCAEVT2,DCBEVT1,DCBEVT2"
line.word 0x06 "DCBCTL,Digital Compare B Control Register"
bitfld.word 0x06 9. " EVT2FRC_SYNCSEL ,DCBEVT2 Force Synchronization Signal Select" "Synchronous,Asynchronous"
bitfld.word 0x06 8. " EVT2SRCSEL ,DCBEVT2 Source Signal Select" "DCBEVT2,DCEVTFILT"
bitfld.word 0x06 3. " EVT1SYNCE ,DCBEVT1 SYNC Generation" "Disabled,Enabled"
textline " "
bitfld.word 0x06 2. " EVT1SOCE ,DCBEVT1 SOC Generation" "Disabled,Enabled"
bitfld.word 0x06 1. " EVT1FRC_SYNCSEL ,DCBEVT1 Force Synchronization Signal Select" "Synchronous,Asynchronous"
bitfld.word 0x06 0. " EVT1SRCSEL ,DCBEVT1 Source Signal Select" "DCBEVT,DCEVTFILT"
rgroup.word 0x68++0x01
line.word 0x00 "DCOFFSET,Digital Compare Filter Offset Register"
group.word 0x6A++0x03
line.word 0x00 "DCCAPCTL,Digital Compare Capture Control Register"
bitfld.word 0x00 1. " SHDWMODE ,TBCTR Counter Capture Shadow Select Mode" "Shadow mode,Active Mode"
bitfld.word 0x00 0. " CAPE ,TBCTR Counter Capture Enable/Disable" "Disabled,Enabled"
line.word 0x02 "DCFWINDOW,Digital Compare Filter Window Register"
hexmask.word.byte 0x02 0.--7. 1. " WINDOW ,Blanking Window Width"
rgroup.word 0x6C++0x07
line.word 0x02 "DCOFFSETCNT, Digital Compare Filter Offset Counter Register"
line.word 0x04 "DCCAP, Digital Compare Counter Capture Register"
line.word 0x06 "DCFWINDOWCNT, Digital Compare Filter Window Counter Register"
hexmask.word.byte 0x06 0.--7. 1. " WINDOWCNT ,Digital Compare Filter Window Counter Register"
tree.end
width 0xB
tree.end
tree.end
tree "DMM (Data Modification Module)"
base ad:0xFFFFF700
width 12.
group.long 0x00++0x03
line.long 0x00 "GLBCTRL,Global Control Register"
rbitfld.long 0x00 24. " BUSY ,Busy" "Not received,Received"
bitfld.long 0x00 18. " CONTCLK ,Continous RTPCLK output" "Suspended,Continue"
bitfld.long 0x00 17. " COS ,Continue on suspend" "Suspended,Continue"
textline " "
bitfld.long 0x00 16. " RESET ,Reset" "No reset,Reset"
bitfld.long 0x00 9.--10. " DDM_WIDTH ,Packet width in direct data mode" "8 bits,16 bits,32 bits,?..."
bitfld.long 0x00 8. " TM_DMM ,Packet format" "Trace mode,Direct mode"
textline " "
bitfld.long 0x00 0.--3. " ON/OFF ,DMM module receives data enable" "Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Enabled,Disabled,Disabled,Disabled,Disabled,Disabled"
textline " "
if (((d.l(ad:0xFFFFF700))&0x100)==0x100)
group.long 0x04++0x03
line.long 0x00 "INTSET,Interrupt Set Register"
setclrfld.long 0x00 17. 0x00 17. 0x04 17. " PROG_BUFF_SET/CLR ,Programmable buffer interrupt" "No interrupt,Interrupt"
setclrfld.long 0x00 16. 0x00 16. 0x04 16. " EO_BUFF_SET/CLR ,End of buffer interrupt" "No interrupt,Interrupt"
textline " "
setclrfld.long 0x00 7. 0x00 7. 0x04 7. " BUSERROR_SET/CLR ,BMM bus error response" "No interrupt,Interrupt"
setclrfld.long 0x00 6. 0x00 6. 0x04 6. " BUFF_OVF_SET/CLR ,Write buffer overflow interrupt" "No interrupt,Interrupt"
textline " "
setclrfld.long 0x00 5. 0x00 5. 0x04 5. " SRC_OVF_SET/CLR ,Source overflow interrupt" "No interrupt,Interrupt"
setclrfld.long 0x00 4. 0x00 4. 0x04 4. " DEST3_ERRENA_SET/CLR ,Destination 3 error interrupt" "No interrupt,Interrupt"
textline " "
setclrfld.long 0x00 3. 0x00 3. 0x04 3. " DEST2_ERRENA_SET/CLR ,Destination 2 error interrupt" "No interrupt,Interrupt"
setclrfld.long 0x00 2. 0x00 2. 0x04 2. " DEST1_ERRENA_SET/CLR ,Destination 1 error interrupt" "No interrupt,Interrupt"
textline " "
setclrfld.long 0x00 1. 0x00 1. 0x04 1. " DEST0_ERRENA_SET/CLR ,Destination 0 error interrupt" "No interrupt,Interrupt"
setclrfld.long 0x00 0. 0x00 0. 0x04 0. " PACKET_ERR_INT_SET/CLR ,Packet error interrupt" "No interrupt,Interrupt"
textline " "
else
group.long 0x04++0x03
line.long 0x00 "INTSET,Interrupt Set Register"
setclrfld.long 0x00 15. 0x00 15. 0x04 15. " DEST3REG2_SET/CLR ,Destination 3 region 2 interrupt" "No interrupt,Interrupt"
setclrfld.long 0x00 14. 0x00 14. 0x04 14. " DEST3REG1_SET/CLR ,Destination 3 region 1 interrupt" "No interrupt,Interrupt"
textline " "
setclrfld.long 0x00 13. 0x00 13. 0x04 13. " DEST2REG2_SET/CLR ,Destination 2 region 2 interrupt" "No interrupt,Interrupt"
setclrfld.long 0x00 12. 0x00 12. 0x04 12. " DEST2REG1_SET/CLR ,Destination 2 region 1 interrupt" "No interrupt,Interrupt"
textline " "
setclrfld.long 0x00 11. 0x00 11. 0x04 11. " DEST1REG2_SET/CLR ,Destination 1 region 2 interrupt" "No interrupt,Interrupt"
setclrfld.long 0x00 10. 0x00 10. 0x04 10. " DEST1REG1_SET/CLR ,Destination 1 region 1 interrupt" "No interrupt,Interrupt"
textline " "
setclrfld.long 0x00 9. 0x00 9. 0x04 9. " DEST0REG2_SET/CLR ,Destination 0 region 2 interrupt" "No interrupt,Interrupt"
setclrfld.long 0x00 8. 0x00 8. 0x04 8. " DEST0REG1_SET/CLR ,Destination 0 region 1 interrupt" "No interrupt,Interrupt"
textline " "
setclrfld.long 0x00 7. 0x00 7. 0x04 7. " BUSERROR_SET/CLR ,BMM bus error response" "No interrupt,Interrupt"
setclrfld.long 0x00 6. 0x00 6. 0x04 6. " BUFF_OVF_SET/CLR ,Write buffer overflow interrupt" "No interrupt,Interrupt"
textline " "
setclrfld.long 0x00 5. 0x00 5. 0x04 5. " SRC_OVF_SET/CLR ,Source overflow interrupt" "No interrupt,Interrupt"
setclrfld.long 0x00 4. 0x00 4. 0x04 4. " DEST3_ERRENA_SET/CLR ,Destination 3 error interrupt" "No interrupt,Interrupt"
textline " "
setclrfld.long 0x00 3. 0x00 3. 0x04 3. " DEST2_ERRENA_SET/CLR ,Destination 2 error interrupt" "No interrupt,Interrupt"
setclrfld.long 0x00 2. 0x00 2. 0x04 2. " DEST1_ERRENA_SET/CLR ,Destination 1 error interrupt" "No interrupt,Interrupt"
textline " "
setclrfld.long 0x00 1. 0x00 1. 0x04 1. " DEST0_ERRENA_SET/CLR ,Destination 0 error interrupt" "No interrupt,Interrupt"
setclrfld.long 0x00 0. 0x00 0. 0x04 0. " PACKET_ERR_INT_SET/CLR ,Packet error interrupt" "No interrupt,Interrupt"
textline " "
endif
group.long 0x0C++0x03
line.long 0x00 "INTLVL,Interrupt Level Register"
bitfld.long 0x00 17. " PROG_BUFF ,Programmable buffer interrupt level" "Level 0,Level 1"
bitfld.long 0x00 16. " EO_BUFF ,End of buffer interrupt level" "Level 0,Level 1"
bitfld.long 0x00 15. " DEST3REG2 ,Destination 3 region 2 interrupt level" "Level 0,Level 1"
textline " "
bitfld.long 0x00 14. " DEST3REG1 ,Destination 3 region 1 interrupt level" "Level 0,Level 1"
bitfld.long 0x00 13. " DEST2REG2 ,Destination 2 region 2 interrupt level" "Level 0,Level 1"
bitfld.long 0x00 12. " DEST2REG1 ,Destination 2 region 1 interrupt level" "Level 0,Level 1"
textline " "
bitfld.long 0x00 11. " DEST1REG2 ,Destination 1 region 2 interrupt level" "Level 0,Level 1"
bitfld.long 0x00 10. " DEST1REG1 ,Destination 1 region 1 interrupt level" "Level 0,Level 1"
bitfld.long 0x00 9. " DEST0REG2 ,Destination 0 region 2 interrupt level" "Level 0,Level 1"
textline " "
bitfld.long 0x00 8. " DEST0REG1 ,Destination 0 region 1 interrupt level" "Level 0,Level 1"
bitfld.long 0x00 7. " BUSERROR ,BMM bus error response" "Level 0,Level 1"
bitfld.long 0x00 6. " BUFF_OVF ,Write buffer overflow interrupt level" "Level 0,Level 1"
textline " "
bitfld.long 0x00 5. " SRC_OVF ,Source overflow interrupt level" "Level 0,Level 1"
bitfld.long 0x00 4. " DEST3_ERRENA ,Destination 3 error interrupt level" "Level 0,Level 1"
bitfld.long 0x00 3. " DEST2_ERRENA ,Destination 2 error interrupt level" "Level 0,Level 1"
textline " "
bitfld.long 0x00 2. " DEST1_ERRENA ,Destination 1 error interrupt level" "Level 0,Level 1"
bitfld.long 0x00 1. " DEST0_ERRENA ,Destination 0 error interrupt level" "Level 0,Level 1"
bitfld.long 0x00 0. " PACKET_ERR_INT ,Packet error interrupt level" "Level 0,Level 1"
textline " "
group.long 0x10++0x03
line.long 0x00 "INTFLAG,Interrupt Flag Register"
eventfld.long 0x00 17. " PROG_BUFF ,Programmable buffer interrupt flag" "No interrupt,Interrupt"
eventfld.long 0x00 16. " EO_BUFF ,End of buffer interrupt flag" "No interrupt,Interrupt"
eventfld.long 0x00 15. " DEST3REG2 ,Destination 3 region 2 interrupt flag" "No interrupt,Interrupt"
eventfld.long 0x00 14. " DEST3REG1 ,Destination 3 region 1 interrupt flag" "No interrupt,Interrupt"
textline " "
eventfld.long 0x00 13. " DEST2REG2 ,Destination 2 region 2 interrupt flag" "No interrupt,Interrupt"
eventfld.long 0x00 12. " DEST2REG1 ,Destination 2 region 1 interrupt flag" "No interrupt,Interrupt"
eventfld.long 0x00 11. " DEST1REG2 ,Destination 1 region 2 interrupt flag" "No interrupt,Interrupt"
eventfld.long 0x00 10. " DEST1REG1 ,Destination 1 region 1 interrupt flag" "No interrupt,Interrupt"
textline " "
eventfld.long 0x00 9. " DEST0REG2 ,Destination 0 region 2 interrupt flag" "No interrupt,Interrupt"
eventfld.long 0x00 8. " DEST0REG1 ,Destination 0 region 1 interrupt flag" "No interrupt,Interrupt"
eventfld.long 0x00 7. " BUSERROR ,BMM bus error response" "No interrupt,Interrupt"
eventfld.long 0x00 6. " BUFF_OVF ,Write buffer overflow interrupt flag" "No interrupt,Interrupt"
textline " "
eventfld.long 0x00 5. " SRC_OVF ,Source overflow interrupt flag" "No interrupt,Interrupt"
eventfld.long 0x00 4. " DEST3_ERRENA ,Destination 3 error interrupt flag" "No interrupt,Interrupt"
eventfld.long 0x00 3. " DEST2_ERRENA ,Destination 2 error interrupt flag" "No interrupt,Interrupt"
eventfld.long 0x00 2. " DEST1_ERRENA ,Destination 1 error interrupt flag" "No interrupt,Interrupt"
textline " "
eventfld.long 0x00 1. " DEST0_ERRENA ,Destination 0 error interrupt flag" "No interrupt,Interrupt"
eventfld.long 0x00 0. " PACKET_ERR_INT ,Packet error interrupt flag" "No interrupt,Interrupt"
textline " "
width 11.
hgroup.long 0x14++0x03
hide.long 0x00 "OFF1,Interrupt Offset 1 Register"
in
hgroup.long 0x18++0x03
hide.long 0x00 "OFF2,Interrupt Offset 2 Register"
in
group.long 0x1C++0x03
line.long 0x00 "DDMDEST,Direct Data Mode Destination Register"
group.long 0x20++0x03
line.long 0x00 "DDMBL,Direct Data Mode Blocksize Register"
bitfld.long 0x00 0.--3. " BLOCKSIZE ,Block size" "0 B,32 B,64 B,128 B,256 B,512 B,1 kb,2 kb,4 kb,8 kb,16 kb,32 kb,?..."
rgroup.long 0x24++0x03
line.long 0x00 "DDMPT,Direct Data Mode Pointer Register"
hexmask.long.word 0x00 0.--14. 1. " POINTER ,Pointer"
group.long 0x28++0x03
line.long 0x00 "INTPT,Direct Data Mode Interrupt Pointer Register"
hexmask.long.word 0x00 0.--14. 1. " INTPT ,Interrupt pointer"
group.long 0x2C++0x03
line.long 0x00 "DEST0REG1,Destination 0 Region 1"
hexmask.long.word 0x00 18.--31. 0x04 " BASEADDR ,Base address"
hexmask.long.tbyte 0x00 0.--17. 1. " BLOCKADDR ,Block address"
group.long 0x30++0x03
line.long 0x00 "DEST0BL1,Destination 0 Blocksize 1"
bitfld.long 0x00 0.--3. " BLOCKSIZE ,Block size" "0 kb,1 kb,2 kb,4 kb,8 kb,16 kb,32 kb,64 kb,128 kb,256 kb,?..."
group.long 0x34++0x03
line.long 0x00 "DEST0REG2,Destination 0 Region 2"
hexmask.long.word 0x00 18.--31. 0x04 " BASEADDR ,Base address"
hexmask.long.tbyte 0x00 0.--17. 1. " BLOCKADDR ,Block address"
group.long 0x38++0x03
line.long 0x00 "DEST0BL2,Destination 0 Blocksize 2"
bitfld.long 0x00 0.--3. " BLOCKSIZE ,Block size" "0 kb,1 kb,2 kb,4 kb,8 kb,16 kb,32 kb,64 kb,128 kb,256 kb,?..."
group.long 0x3C++0x03
line.long 0x00 "DEST1REG1,Destination 1 Region 1"
hexmask.long.word 0x00 18.--31. 0x04 " BASEADDR ,Base address"
hexmask.long.tbyte 0x00 0.--17. 1. " BLOCKADDR ,Block address"
group.long 0x40++0x03
line.long 0x00 "DEST1BL1,Destination 1 Blocksize 1"
bitfld.long 0x00 0.--3. " BLOCKSIZE ,Block size" "0 kb,1 kb,2 kb,4 kb,8 kb,16 kb,32 kb,64 kb,128 kb,256 kb,?..."
group.long 0x44++0x03
line.long 0x00 "DEST1REG2,Destination 1 Region 2"
hexmask.long.word 0x00 18.--31. 0x04 " BASEADDR ,Base address"
hexmask.long.tbyte 0x00 0.--17. 1. " BLOCKADDR ,Block address"
group.long 0x48++0x03
line.long 0x00 "DEST1BL2,Destination 1 Blocksize 2"
bitfld.long 0x00 0.--3. " BLOCKSIZE ,Block size" "0 kb,1 kb,2 kb,4 kb,8 kb,16 kb,32 kb,64 kb,128 kb,256 kb,?..."
group.long 0x4C++0x03
line.long 0x00 "DEST2REG1,Destination 2 Region 1"
hexmask.long.word 0x00 18.--31. 0x04 " BASEADDR ,Base address"
hexmask.long.tbyte 0x00 0.--17. 1. " BLOCKADDR ,Block address"
group.long 0x50++0x03
line.long 0x00 "DEST2BL1,Destination 2 Blocksize 1"
bitfld.long 0x00 0.--3. " BLOCKSIZE ,Block size" "0 kb,1 kb,2 kb,4 kb,8 kb,16 kb,32 kb,64 kb,128 kb,256 kb,?..."
group.long 0x54++0x03
line.long 0x00 "DEST2REG2,Destination 2 Region 2"
hexmask.long.word 0x00 18.--31. 0x04 " BASEADDR ,Base address"
hexmask.long.tbyte 0x00 0.--17. 1. " BLOCKADDR ,Block address"
group.long 0x58++0x03
line.long 0x00 "DEST2BL2,Destination 2 Blocksize 2"
bitfld.long 0x00 0.--3. " BLOCKSIZE ,Block size" "0 kb,1 kb,2 kb,4 kb,8 kb,16 kb,32 kb,64 kb,128 kb,256 kb,?..."
group.long 0x5C++0x03
line.long 0x00 "DEST3REG1,Destination 3 Region 1"
hexmask.long.word 0x00 18.--31. 0x04 " BASEADDR ,Base address"
hexmask.long.tbyte 0x00 0.--17. 1. " BLOCKADDR ,Block address"
group.long 0x60++0x03
line.long 0x00 "DEST3BL1,Destination 3 Blocksize 1"
bitfld.long 0x00 0.--3. " BLOCKSIZE ,Block size" "0 kb,1 kb,2 kb,4 kb,8 kb,16 kb,32 kb,64 kb,128 kb,256 kb,?..."
group.long 0x64++0x03
line.long 0x00 "DEST3REG2,Destination 3 Region 2"
hexmask.long.word 0x00 18.--31. 0x04 " BASEADDR ,Base address"
hexmask.long.tbyte 0x00 0.--17. 1. " BLOCKADDR ,Block address"
group.long 0x68++0x03
line.long 0x00 "DEST3BL2,Destination 3 Blocksize 2"
bitfld.long 0x00 0.--3. " BLOCKSIZE ,Block size" "0 kb,1 kb,2 kb,4 kb,8 kb,16 kb,32 kb,64 kb,128 kb,256 kb,?..."
textline " "
if (((d.l(ad:0xFFFFF700))&0x100000F)==0x0A)
group.long 0x6C++0x03
line.long 0x00 "PC0(FUNC),Pin Control 0"
bitfld.long 0x00 18. " ENAFUNC ,Functional mode of /DMMENA pin" "GIO mode,Functional mode"
bitfld.long 0x00 17. " DATA15FUNC ,Functional mode of DMMDATA[15] pin" "GIO mode,Functional mode"
bitfld.long 0x00 16. " DATA14FUNC ,Functional mode of DMMDATA[14] pin" "GIO mode,Functional mode"
bitfld.long 0x00 15. " DATA13FUNC ,Functional mode of DMMDATA[13] pin" "GIO mode,Functional mode"
textline " "
bitfld.long 0x00 14. " DATA12FUNC ,Functional mode of DMMDATA[12] pin" "GIO mode,Functional mode"
bitfld.long 0x00 13. " DATA11FUNC ,Functional mode of DMMDATA[11] pin" "GIO mode,Functional mode"
bitfld.long 0x00 12. " DATA10FUNC ,Functional mode of DMMDATA[10] pin" "GIO mode,Functional mode"
bitfld.long 0x00 11. " DATA9FUNC ,Functional mode of DMMDATA[9] pin" "GIO mode,Functional mode"
textline " "
bitfld.long 0x00 10. " DATA8FUNC ,Functional mode of DMMDATA[8] pin" "GIO mode,Functional mode"
bitfld.long 0x00 9. " DATA7FUNC ,Functional mode of DMMDATA[7] pin" "GIO mode,Functional mode"
bitfld.long 0x00 8. " DATA6FUNC ,Functional mode of DMMDATA[6] pin" "GIO mode,Functional mode"
bitfld.long 0x00 7. " DATA5FUNC ,Functional mode of DMMDATA[5] pin" "GIO mode,Functional mode"
textline " "
bitfld.long 0x00 6. " DATA4FUNC ,Functional mode of DMMDATA[4] pin" "GIO mode,Functional mode"
bitfld.long 0x00 5. " DATA3FUNC ,Functional mode of DMMDATA[3] pin" "GIO mode,Functional mode"
bitfld.long 0x00 4. " DATA2FUNC ,Functional mode of DMMDATA[2] pin" "GIO mode,Functional mode"
bitfld.long 0x00 3. " DATA1FUNC ,Functional mode of DMMDATA[1] pin" "GIO mode,Functional mode"
textline " "
bitfld.long 0x00 2. " DATA0FUNC ,Functional mode of DMMDATA[0] pin" "GIO mode,Functional mode"
bitfld.long 0x00 1. " CLKFUNC ,Functional mode of DMMCLK pin" "GIO mode,Functional mode"
bitfld.long 0x00 0. " SYNCFUNC ,Functional mode of DMMSYNC pin" "GIO mode,Functional mode"
textline " "
else
rgroup.long 0x6C++0x03
line.long 0x00 "PC0(FUNC),Pin Control 0"
bitfld.long 0x00 18. " ENAFUNC ,Functional mode of /DMMENA pin" "GIO mode,Functional mode"
bitfld.long 0x00 17. " DATA15FUNC ,Functional mode of DMMDATA[15] pin" "GIO mode,Functional mode"
bitfld.long 0x00 16. " DATA14FUNC ,Functional mode of DMMDATA[14] pin" "GIO mode,Functional mode"
bitfld.long 0x00 15. " DATA13FUNC ,Functional mode of DMMDATA[13] pin" "GIO mode,Functional mode"
textline " "
bitfld.long 0x00 14. " DATA12FUNC ,Functional mode of DMMDATA[12] pin" "GIO mode,Functional mode"
bitfld.long 0x00 13. " DATA11FUNC ,Functional mode of DMMDATA[11] pin" "GIO mode,Functional mode"
bitfld.long 0x00 12. " DATA10FUNC ,Functional mode of DMMDATA[10] pin" "GIO mode,Functional mode"
bitfld.long 0x00 11. " DATA9FUNC ,Functional mode of DMMDATA[9] pin" "GIO mode,Functional mode"
textline " "
bitfld.long 0x00 10. " DATA8FUNC ,Functional mode of DMMDATA[8] pin" "GIO mode,Functional mode"
bitfld.long 0x00 9. " DATA7FUNC ,Functional mode of DMMDATA[7] pin" "GIO mode,Functional mode"
bitfld.long 0x00 8. " DATA6FUNC ,Functional mode of DMMDATA[6] pin" "GIO mode,Functional mode"
bitfld.long 0x00 7. " DATA5FUNC ,Functional mode of DMMDATA[5] pin" "GIO mode,Functional mode"
textline " "
bitfld.long 0x00 6. " DATA4FUNC ,Functional mode of DMMDATA[4] pin" "GIO mode,Functional mode"
bitfld.long 0x00 5. " DATA3FUNC ,Functional mode of DMMDATA[3] pin" "GIO mode,Functional mode"
bitfld.long 0x00 4. " DATA2FUNC ,Functional mode of DMMDATA[2] pin" "GIO mode,Functional mode"
bitfld.long 0x00 3. " DATA1FUNC ,Functional mode of DMMDATA[1] pin" "GIO mode,Functional mode"
textline " "
bitfld.long 0x00 2. " DATA0FUNC ,Functional mode of DMMDATA[0] pin" "GIO mode,Functional mode"
bitfld.long 0x00 1. " CLKFUNC ,Functional mode of DMMCLK pin" "GIO mode,Functional mode"
bitfld.long 0x00 0. " SYNCFUNC ,Functional mode of DMMSYNC pin" "GIO mode,Functional mode"
textline " "
endif
group.long 0x70++0x03
line.long 0x00 "PC1(DIR),Pin Control 1"
bitfld.long 0x00 18. " ENADIR ,Direction of /DMMENA pin (Gio mode)" "Input,Output"
bitfld.long 0x00 17. " DATA15DIR ,Direction of DMMDATA[15] pin (Gio mode)" "Input,Output"
bitfld.long 0x00 16. " DATA14DIR ,Direction of DMMDATA[14] pin (Gio mode)" "Input,Output"
textline " "
bitfld.long 0x00 15. " DATA13DIR ,Direction of DMMDATA[13] pin (Gio mode)" "Input,Output"
bitfld.long 0x00 14. " DATA12DIR ,Direction of DMMDATA[12] pin (Gio mode)" "Input,Output"
bitfld.long 0x00 13. " DATA11DIR ,Direction of DMMDATA[11] pin (Gio mode)" "Input,Output"
textline " "
bitfld.long 0x00 12. " DATA10DIR ,Direction of DMMDATA[10] pin (Gio mode)" "Input,Output"
bitfld.long 0x00 11. " DATA9DIR ,Direction of DMMDATA[9] pin (Gio mode)" "Input,Output"
bitfld.long 0x00 10. " DATA8DIR ,Direction of DMMDATA[8] pin (Gio mode)" "Input,Output"
textline " "
bitfld.long 0x00 9. " DATA7DIR ,Direction of DMMDATA[7] pin (Gio mode)" "Input,Output"
bitfld.long 0x00 8. " DATA6DIR ,Direction of DMMDATA[6] pin (Gio mode)" "Input,Output"
bitfld.long 0x00 7. " DATA5DIR ,Direction of DMMDATA[5] pin (Gio mode)" "Input,Output"
textline " "
bitfld.long 0x00 6. " DATA4DIR ,Direction of DMMDATA[4] pin (Gio mode)" "Input,Output"
bitfld.long 0x00 5. " DATA3DIR ,Direction of DMMDATA[3] pin (Gio mode)" "Input,Output"
bitfld.long 0x00 4. " DATA2DIR ,Direction of DMMDATA[2] pin (Gio mode)" "Input,Output"
textline " "
bitfld.long 0x00 3. " DATA1DIR ,Direction of DMMDATA[1] pin (Gio mode)" "Input,Output"
bitfld.long 0x00 2. " DATA0DIR ,Direction of DMMDATA[0] pin (Gio mode)" "Input,Output"
bitfld.long 0x00 1. " CLKDIR ,Direction of DMMCLK pin (Gio mode)" "Input,Output"
textline " "
bitfld.long 0x00 0. " SYNCDIR ,Direction of DMMSYNC pin (Gio mode)" "Input,Output"
textline " "
rgroup.long 0x74++0x03
line.long 0x00 "PC2(DIN),Pin Control 2"
bitfld.long 0x00 18. " ENAIN ,DMMENA input" "Low,High"
bitfld.long 0x00 17. " DATA15IN ,DMMDATA[15] input" "Low,High"
bitfld.long 0x00 16. " DATA14IN ,DMMDATA[14] input" "Low,High"
bitfld.long 0x00 15. " DATA13IN ,DMMDATA[13] input" "Low,High"
textline " "
bitfld.long 0x00 14. " DATA12IN ,DMMDATA[12] input" "Low,High"
bitfld.long 0x00 13. " DATA11IN ,DMMDATA[11] input" "Low,High"
bitfld.long 0x00 12. " DATA10IN ,DMMDATA[10] input" "Low,High"
bitfld.long 0x00 11. " DATA9IN ,DMMDATA[9] input" "Low,High"
textline " "
bitfld.long 0x00 10. " DATA8IN ,DMMDATA[8] input" "Low,High"
bitfld.long 0x00 9. " DATA7IN ,DMMDATA[7] input" "Low,High"
bitfld.long 0x00 8. " DATA6IN ,DMMDATA[6] input" "Low,High"
bitfld.long 0x00 7. " DATA5IN ,DMMDATA[5] input" "Low,High"
textline " "
bitfld.long 0x00 6. " DATA4IN ,DMMDATA[4] input" "Low,High"
bitfld.long 0x00 5. " DATA3IN ,DMMDATA[3] input" "Low,High"
bitfld.long 0x00 4. " DATA2IN ,DMMDATA[2] input" "Low,High"
bitfld.long 0x00 3. " DATA1IN ,DMMDATA[1] input" "Low,High"
textline " "
bitfld.long 0x00 2. " DATA0IN ,DMMDATA[0] input" "Low,High"
bitfld.long 0x00 1. " CLKIN ,DMMCLK input" "Low,High"
bitfld.long 0x00 0. " SYNCIN ,DMMSYNC input" "Low,High"
textline " "
group.long 0x78++0x03
line.long 0x00 "PC3(OUT),Pin Control 3"
setclrfld.long 0x00 18. 0x04 18. 0x08 18. " ENAOUT_SET/CLR ,Output state of /DMMENA pin" "Low,High"
setclrfld.long 0x00 17. 0x04 17. 0x08 17. " DATA15OUT_SET/CLR ,Output state of DMMDATA[15] pin" "Low,High"
textline " "
setclrfld.long 0x00 16. 0x04 16. 0x08 16. " DATA14OUT_SET/CLR ,Output state of DMMDATA[14] pin" "Low,High"
setclrfld.long 0x00 15. 0x04 15. 0x08 15. " DATA13OUT_SET/CLR ,Output state of DMMDATA[13] pin" "Low,High"
textline " "
setclrfld.long 0x00 14. 0x04 14. 0x08 14. " DATA12OUT_SET/CLR ,Output state of DMMDATA[12] pin" "Low,High"
setclrfld.long 0x00 13. 0x04 13. 0x08 13. " DATA11OUT_SET/CLR ,Output state of DMMDATA[11] pin" "Low,High"
textline " "
setclrfld.long 0x00 12. 0x04 12. 0x08 12. " DATA10OUT_SET/CLR ,Output state of DMMDATA[10] pin" "Low,High"
setclrfld.long 0x00 11. 0x04 11. 0x08 11. " DATA9OUT_SET/CLR ,Output state of DMMDATA[9] pin" "Low,High"
textline " "
setclrfld.long 0x00 10. 0x04 10. 0x08 10. " DATA8OUT_SET/CLR ,Output state of DMMDATA[8] pin" "Low,High"
setclrfld.long 0x00 9. 0x04 9. 0x08 9. " DATA7OUT_SET/CLR ,Output state of DMMDATA[7] pin" "Low,High"
textline " "
setclrfld.long 0x00 8. 0x04 8. 0x08 8. " DATA6OUT_SET/CLR ,Output state of DMMDATA[6] pin" "Low,High"
setclrfld.long 0x00 7. 0x04 7. 0x08 7. " DATA5OUT_SET/CLR ,Output state of DMMDATA[5] pin" "Low,High"
textline " "
setclrfld.long 0x00 6. 0x04 6. 0x08 6. " DATA4OUT_SET/CLR ,Output state of DMMDATA[4] pin" "Low,High"
setclrfld.long 0x00 5. 0x04 5. 0x08 5. " DATA3OUT_SET/CLR ,Output state of DMMDATA[3] pin" "Low,High"
textline " "
setclrfld.long 0x00 4. 0x04 4. 0x08 4. " DATA2OUT_SET/CLR ,Output state of DMMDATA[2] pin" "Low,High"
setclrfld.long 0x00 3. 0x04 3. 0x08 3. " DATA1OUT_SET/CLR ,Output state of DMMDATA[1] pin" "Low,High"
textline " "
setclrfld.long 0x00 2. 0x04 2. 0x08 2. " DATA0OUT_SET/CLR ,Output state of DMMDATA[0] pin" "Low,High"
setclrfld.long 0x00 1. 0x04 1. 0x08 1. " CLKOUT_SET/CLR ,Output state of DMMCLK pin" "Low,High"
textline " "
setclrfld.long 0x00 0. 0x04 0. 0x08 0. " SYNCOUT_SET/CLR ,Output state of DMMSYNC pin" "Low,High"
textline " "
group.long 0x84++0x03
line.long 0x00 "PC6(PDR),Pin Control 6"
bitfld.long 0x00 18. " ENAPDR ,ENAPDR open drain enable" "Disabled,Enabled"
bitfld.long 0x00 17. " DATA15PDR ,Open drain enable 15" "Disabled,Enabled"
bitfld.long 0x00 16. " DATA14PDR ,Open drain enable 14" "Disabled,Enabled"
textline " "
bitfld.long 0x00 15. " DATA13PDR ,Open drain enable 13" "Disabled,Enabled"
bitfld.long 0x00 14. " DATA12PDR ,Open drain enable 12" "Disabled,Enabled"
bitfld.long 0x00 13. " DATA11PDR ,Open drain enable 11" "Disabled,Enabled"
textline " "
bitfld.long 0x00 12. " DATA10PDR ,Open drain enable 10" "Disabled,Enabled"
bitfld.long 0x00 11. " DATA9PDR ,Open drain enable 9" "Disabled,Enabled"
bitfld.long 0x00 10. " DATA8PDR ,Open drain enable 8" "Disabled,Enabled"
textline " "
bitfld.long 0x00 9. " DATA7PDR ,Open drain enable 7" "Disabled,Enabled"
bitfld.long 0x00 8. " DATA6PDR ,Open drain enable 6" "Disabled,Enabled"
bitfld.long 0x00 7. " DATA5PDR ,Open drain enable 5" "Disabled,Enabled"
textline " "
bitfld.long 0x00 6. " DATA4PDR ,Open drain enable 4" "Disabled,Enabled"
bitfld.long 0x00 5. " DATA3PDR ,Open drain enable 3" "Disabled,Enabled"
bitfld.long 0x00 4. " DATA2PDR ,Open drain enable 2" "Disabled,Enabled"
textline " "
bitfld.long 0x00 3. " DATA1PDR ,Open drain enable 1" "Disabled,Enabled"
bitfld.long 0x00 2. " DATA0PDR ,Open drain enable 0" "Disabled,Enabled"
bitfld.long 0x00 1. " CLKPDR ,CLKPDR open drain enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 0. " SYNCPDR ,SYNCPDR open drain enable" "Disabled,Enabled"
textline " "
group.long 0x88++0x03
line.long 0x00 "PC7(PDIS),Pin Control 7"
bitfld.long 0x00 18. " ENAPDIS ,ENAPDIS pull disable" "No,Yes"
bitfld.long 0x00 17. " DATA15PDIS ,Pull disable 15" "No,Yes"
bitfld.long 0x00 16. " DATA14PDIS ,Pull disable 14" "No,Yes"
bitfld.long 0x00 15. " DATA13PDIS ,Pull disable 13" "No,Yes"
textline " "
bitfld.long 0x00 14. " DATA12PDIS ,Pull disable 12" "No,Yes"
bitfld.long 0x00 13. " DATA11PDIS ,Pull disable 11" "No,Yes"
bitfld.long 0x00 12. " DATA10PDIS ,Pull disable 10" "No,Yes"
bitfld.long 0x00 11. " DATA9PDIS ,Pull disable 9" "No,Yes"
textline " "
bitfld.long 0x00 10. " DATA8PDIS ,Pull disable 8" "No,Yes"
bitfld.long 0x00 9. " DATA7PDIS ,Pull disable 7" "No,Yes"
bitfld.long 0x00 8. " DATA6PDIS ,Pull disable 6" "No,Yes"
bitfld.long 0x00 7. " DATA5PDIS ,Pull disable 5" "No,Yes"
textline " "
bitfld.long 0x00 6. " DATA4PDIS ,Pull disable 4" "No,Yes"
bitfld.long 0x00 5. " DATA3PDIS ,Pull disable 3" "No,Yes"
bitfld.long 0x00 4. " DATA2PDIS ,Pull disable 2" "No,Yes"
bitfld.long 0x00 3. " DATA1PDIS ,Pull disable 1" "No,Yes"
textline " "
bitfld.long 0x00 2. " DATA0PDIS ,Pull disable 0" "No,Yes"
bitfld.long 0x00 1. " CLKPDIS ,CLKPDIS pull disable" "No,Yes"
bitfld.long 0x00 0. " SYNCPDIS ,SYNCPDIS pull disable" "No,Yes"
textline " "
group.long 0x8C++0x03
line.long 0x00 "PC8(PSEL),Pin Control 8"
bitfld.long 0x00 18. " ENAPSEL ,ENAPSEL pull select" "Pull down,Pull up"
bitfld.long 0x00 17. " DATA15PSEL ,Pull select 15" "Pull down,Pull up"
bitfld.long 0x00 16. " DATA14PSEL ,Pull select 14" "Pull down,Pull up"
textline " "
bitfld.long 0x00 15. " DATA13PSEL ,Pull select 13" "Pull down,Pull up"
bitfld.long 0x00 14. " DATA12PSEL ,Pull select 12" "Pull down,Pull up"
bitfld.long 0x00 13. " DATA11PSEL ,Pull select 11" "Pull down,Pull up"
textline " "
bitfld.long 0x00 12. " DATA10PSEL ,Pull select 10" "Pull down,Pull up"
bitfld.long 0x00 11. " DATA9PSEL ,Pull select 9" "Pull down,Pull up"
bitfld.long 0x00 10. " DATA8PSEL ,Pull select 8" "Pull down,Pull up"
textline " "
bitfld.long 0x00 9. " DATA7PSEL ,Pull select 7" "Pull down,Pull up"
bitfld.long 0x00 8. " DATA6PSEL ,Pull select 6" "Pull down,Pull up"
bitfld.long 0x00 7. " DATA5PSEL ,Pull select 5" "Pull down,Pull up"
textline " "
bitfld.long 0x00 6. " DATA4PSEL ,Pull select 4" "Pull down,Pull up"
bitfld.long 0x00 5. " DATA3PSEL ,Pull select 3" "Pull down,Pull up"
bitfld.long 0x00 4. " DATA2PSEL ,Pull select 2" "Pull down,Pull up"
textline " "
bitfld.long 0x00 3. " DATA1PSEL ,Pull select 1" "Pull down,Pull up"
bitfld.long 0x00 2. " DATA0PSEL ,Pull select 0" "Pull down,Pull up"
bitfld.long 0x00 1. " CLKPDSEL ,CLKPDSEL pull select" "Pull down,Pull up"
textline " "
bitfld.long 0x00 0. " SYNCPSEL ,SYNCPSEL pull select" "Pull down,Pull up"
width 0x0B
tree.end
tree "RTP (RAM Trace Port)"
sif COMP.AVAILABLE("RTP")
base CONVert.ADDRESSTODUALPORT(COMPonent.BASE("RTP",-1))
width 14.
group.long 0x00++0x07
line.long 0x00 "RTPGLBCTRL,RTP Global Control Register"
sif (cpu()=="TMS570LC4357"||cpu()=="RM57L843-ZWT"||cpu()=="TMS570PSFC61"||cpuis("TMS570LS20216*")||cpu()=="TMS570LS31XX"||cpu()=="TMS570LS21XX"||cpu()=="TMS570LS10XX"||cpu()=="M48L"||cpu()=="TMS570PSFC66")
bitfld.long 0x00 24. " TEST ,FIFO RAM test enable" "Disabled,Enabled"
textline " "
endif
bitfld.long 0x00 16.--18. " PRESCALER ,Rtpclk=1/prescaler" "/1,/2,/3,/4,/5,/6,/7,/8"
bitfld.long 0x00 12.--13. " DDM_WIDTH[1:0] ,Word size in DDM" "8 bit,16 bit,32 bit,?..."
bitfld.long 0x00 11. " DDM_RW ,Direct data mode read/write" "Read,Write"
bitfld.long 0x00 10. " TM_DDM ,Trace mode or direct data mode" "Trace mode,Direct data mode"
textline " "
bitfld.long 0x00 8.--9. " PW[1:0] ,Port width" "2 pins,4 pins,8 pins,16 pins"
bitfld.long 0x00 7. " RESET ,Reset of RTP module" "No reset,Reset"
bitfld.long 0x00 6. " CONTCLK ,Continuous RTPCLK enable" "Disabled,Enabled"
bitfld.long 0x00 5. " HOVF ,Halt on overflow" "Disabled,Enabled"
textline " "
sif (cpu()=="TMS570LC4357"||cpu()=="RM57L843-ZWT"||cpu()=="TMS570PSFC66")
bitfld.long 0x00 4. " INV_RGN ,Invers trace regions" "Inside,Outside"
else
bitfld.long 0x00 4. " INVERSE ,Invers trace regions" "Inside,Outside"
endif
bitfld.long 0x00 0.--3. " ON/OFF ,RTP on or off" "Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Enabled,Disabled,Disabled,Disabled,Disabled,Disabled"
line.long 0x04 "RTPTRENA,RTP Trace Enable Register"
bitfld.long 0x04 24. " ENA4 ,FIFO4 enable" "Disabled,Enabled"
sif (cpu()!=("TMS570LS10106-PGE")&&cpu()!=("TMS570LS10116-PGE")&&cpu()!=("TMS570LS10206-PGE")&&cpu()!=("TMS570LS10216-PGE")&&cpu()!=("TMS570LS20206-PGE")&&cpu()!=("TMS570LS20216-PGE")&&cpu()!=("TMS570LS10106-ZWT")&&cpu()!=("TMS570LS10116-ZWT")&&cpu()!=("TMS570LS10206-ZWT")&&cpu()!=("TMS570LS10216-ZWT")&&cpu()!=("TMS570LS20206-ZWT")&&cpu()!=("TMS570LS20216-ZWT")&&cpu()!=("TMS570LS2126")&&cpu()!=("TMS570LS2127")&&cpu()!=("TMS570LS2136")&&cpu()!=("TMS570LS2137")&&cpu()!=("TMS570LS2125-PGE")&&cpu()!=("TMS570LS2125-ZWT")&&cpu()!=("TMS570LS2135-PGE")&&cpu()!=("TMS570LS2135-ZWT")&&cpu()!=("TMS570LS2124-PGE")&&cpu()!=("TMS570LS2124-ZWT")&&cpu()!=("TMS570LS2134-PGE")&&cpu()!=("TMS570LS2134-ZWT")&&cpu()!=("TMS570LS3134-PGE")&&cpu()!=("TMS570LS3134-ZWT")&&cpu()!=("TMS570LS3135-PGE")&&cpu()!=("TMS570LS3135-ZWT")&&cpu()!=("TMS570LS3136")&&cpu()!=("TMS570LS3137-ZWT")&&cpu()!="RM48L952-PGE"&&cpu()!="RM48L952-ZWT"&&cpu()!="RM48L950-PGE"&&cpu()!="RM48L950-ZWT"&&cpu()!="RM48L940-ZWT"&&cpu()!="RM48L940-PGE"&&cpu()!="RM48L930-ZWT"&&cpu()!="RM48L930-PGE"&&cpu()!="RM48L750-ZWT"&&cpu()!="RM48L750-PGE"&&cpu()!="RM48L740-ZWT"&&cpu()!="RM48L740-PGE"&&cpu()!="RM48L730-ZWT"&&cpu()!="RM48L730-PGE"&&cpu()!="RM48L550-PGE"&&cpu()!="RM48L540-ZWT"&&cpu()!="RM48L540-PGE"&&cpu()!="RM48L530-ZWT"&&cpu()!="RM48L530-PGE")
bitfld.long 0x04 16. " ENA3 ,FIFO3 enable" "Disabled,Enabled"
endif
bitfld.long 0x04 8. " ENA2 ,FIFO2 enable" "Disabled,Enabled"
bitfld.long 0x04 0. " ENA1 ,FIFO1 enable" "Disabled,Enabled"
sif (cpu()=="TMS570LC4357"||cpu()=="RM57L843-ZWT")
group.long 0x08++0x03
line.long 0x00 "RTPGSR,RTP Global Status Register"
rbitfld.long 0x00 12. " EMPTYSER ,Serializer empty" "Not empty,Empty"
rbitfld.long 0x00 11. " EMPTYPER2 ,Peripheral FIFO empty" "Not empty,Empty"
rbitfld.long 0x00 10. " EMPTYPER1 ,Peripheral FIFO empty" "Not empty,Empty"
rbitfld.long 0x00 9. " EMPTY2 ,FIFO2 empty" "Not empty,Empty"
textline " "
rbitfld.long 0x00 8. " EMPTY1 ,FIFO1 empty" "Not empty,Empty"
eventfld.long 0x00 3. " OVFPER ,Overflow peripheral FIFO" "No overflow,Overflow"
eventfld.long 0x00 1. " OVF2 ,Overflow FIFO2" "No overflow,Overflow"
eventfld.long 0x00 0. " OVF1 ,Overflow FIFO1" "No overflow,Overflow"
else
rgroup.long 0x08++0x03
line.long 0x00 "RTPGSR,RTP Global Status Register"
bitfld.long 0x00 12. " EMPTYSER ,Serializer empty" "Not empty,Empty"
sif (cpu()=="TMS570PSFC66")
sif (cpu()!=("TMS570LS10106-PGE")&&cpu()!=("TMS570LS10116-PGE")&&cpu()!=("TMS570LS10206-PGE")&&cpu()!=("TMS570LS10216-PGE")&&cpu()!=("TMS570LS20206-PGE")&&cpu()!=("TMS570LS20216-PGE")&&cpu()!=("TMS570LS10106-ZWT")&&cpu()!=("TMS570LS10116-ZWT")&&cpu()!=("TMS570LS10206-ZWT")&&cpu()!=("TMS570LS10216-ZWT")&&cpu()!=("TMS570LS20206-ZWT")&&cpu()!=("TMS570LS20216-ZWT")&&cpu()!=("TMS570LS10106-ZWT")&&cpu()!=("TMS570LS10116-ZWT")&&cpu()!=("TMS570LS10206-ZWT")&&cpu()!=("TMS570LS10216-ZWT")&&cpu()!=("TMS570LS20206-ZWT")&&cpu()!=("TMS570LS20216-ZWT")&&cpu()!=("TMS570LS2126")&&cpu()!=("TMS570LS2127")&&cpu()!=("TMS570LS2136")&&cpu()!=("TMS570LS2137")&&cpu()!=("TMS570LS2125-PGE")&&cpu()!=("TMS570LS2125-ZWT")&&cpu()!=("TMS570LS2135-PGE")&&cpu()!=("TMS570LS2135-ZWT")&&cpu()!=("TMS570LS2124-PGE")&&cpu()!=("TMS570LS2124-ZWT")&&cpu()!=("TMS570LS2134-PGE")&&cpu()!=("TMS570LS2134-ZWT")&&cpu()!=("TMS570LS3134-PGE")&&cpu()!=("TMS570LS3134-ZWT")&&cpu()!=("TMS570LS3135-PGE")&&cpu()!=("TMS570LS3135-ZWT")&&cpu()!=("TMS570LS3136")&&cpu()!=("TMS570LS3137-ZWT")&&cpu()!="RM48L952-PGE"&&cpu()!="RM48L952-ZWT"&&cpu()!="RM48L950-PGE"&&cpu()!="RM48L950-ZWT"&&cpu()!="RM48L940-ZWT"&&cpu()!="RM48L940-PGE"&&cpu()!="RM48L930-ZWT"&&cpu()!="RM48L930-PGE"&&cpu()!="RM48L750-ZWT"&&cpu()!="RM48L750-PGE"&&cpu()!="RM48L740-ZWT"&&cpu()!="RM48L740-PGE"&&cpu()!="RM48L730-ZWT"&&cpu()!="RM48L730-PGE"&&cpu()!="RM48L550-PGE"&&cpu()!="RM48L540-ZWT"&&cpu()!="RM48L540-PGE"&&cpu()!="RM48L530-ZWT"&&cpu()!="RM48L530-PGE")
bitfld.long 0x00 10. " EMPTY3 ,FIFO 3 Empty" "Not empty,Empty"
endif
else
bitfld.long 0x00 11. " EMPTYPER2 ,Peripheral FIFO empty" "Not empty,Empty"
bitfld.long 0x00 10. " EMPTYPER1 ,Peripheral FIFO empty" "Not empty,Empty"
endif
bitfld.long 0x00 9. " EMPTY2 ,FIFO2 empty" "Not empty,Empty"
bitfld.long 0x00 8. " EMPTY1 ,FIFO1 empty" "Not empty,Empty"
textline " "
bitfld.long 0x00 3. " OVFPER ,Overflow peripheral FIFO" "No overflow,Overflow"
sif (cpu()!=("TMS570LS10106-PGE")&&cpu()!=("TMS570LS10116-PGE")&&cpu()!=("TMS570LS10206-PGE")&&cpu()!=("TMS570LS10216-PGE")&&cpu()!=("TMS570LS20206-PGE")&&cpu()!=("TMS570LS20216-PGE")&&cpu()!=("TMS570LS10106-ZWT")&&cpu()!=("TMS570LS10116-ZWT")&&cpu()!=("TMS570LS10206-ZWT")&&cpu()!=("TMS570LS10216-ZWT")&&cpu()!=("TMS570LS20206-ZWT")&&cpu()!=("TMS570LS20216-ZWT")&&cpu()!=("TMS570LS10106-ZWT")&&cpu()!=("TMS570LS10116-ZWT")&&cpu()!=("TMS570LS10206-ZWT")&&cpu()!=("TMS570LS10216-ZWT")&&cpu()!=("TMS570LS20206-ZWT")&&cpu()!=("TMS570LS20216-ZWT")&&cpu()!=("TMS570LS2126")&&cpu()!=("TMS570LS2127")&&cpu()!=("TMS570LS2136")&&cpu()!=("TMS570LS2137")&&cpu()!=("TMS570LS2125-PGE")&&cpu()!=("TMS570LS2125-ZWT")&&cpu()!=("TMS570LS2135-PGE")&&cpu()!=("TMS570LS2135-ZWT")&&cpu()!=("TMS570LS2124-PGE")&&cpu()!=("TMS570LS2124-ZWT")&&cpu()!=("TMS570LS2134-PGE")&&cpu()!=("TMS570LS2134-ZWT")&&cpu()!=("TMS570LS3134-PGE")&&cpu()!=("TMS570LS3134-ZWT")&&cpu()!=("TMS570LS3135-PGE")&&cpu()!=("TMS570LS3135-ZWT")&&cpu()!=("TMS570LS3136")&&cpu()!=("TMS570LS3137-ZWT")&&cpu()!="RM48L952-PGE"&&cpu()!="RM48L952-ZWT"&&cpu()!="RM48L950-PGE"&&cpu()!="RM48L950-ZWT"&&cpu()!="RM48L940-ZWT"&&cpu()!="RM48L940-PGE"&&cpu()!="RM48L930-ZWT"&&cpu()!="RM48L930-PGE"&&cpu()!="RM48L750-ZWT"&&cpu()!="RM48L750-PGE"&&cpu()!="RM48L740-ZWT"&&cpu()!="RM48L740-PGE"&&cpu()!="RM48L730-ZWT"&&cpu()!="RM48L730-PGE"&&cpu()!="RM48L550-PGE"&&cpu()!="RM48L540-ZWT"&&cpu()!="RM48L540-PGE"&&cpu()!="RM48L530-ZWT"&&cpu()!="RM48L530-PGE")
bitfld.long 0x00 2. " OVFPE3 ,Overflow FIFO3" "No overflow,Overflow"
endif
bitfld.long 0x00 1. " OVFPE2 ,Overflow FIFO2" "No overflow,Overflow"
bitfld.long 0x00 0. " OVFPE1 ,Overflow FIFO1" "No overflow,Overflow"
endif
group.long 0x0C++0x23
line.long 0x00 "RTPRAM1REG1,RTP RAM 1 Trace Region 1 Register"
bitfld.long 0x00 29.--30. " CPU_DMA ,CPU and/or DMA access" "Any,CPU,DMA,?..."
bitfld.long 0x00 28. " RW ,Read/write" "Read,Write"
bitfld.long 0x00 24.--27. " BLOCKSIZE ,Blocksize" "0,256 B,512 B,1k B,2k B,4k B,8k B,16k B,32k B,64k B,128k B,256k B,?..."
hexmask.long.tbyte 0x00 0.--17. 1. " STARTADDR ,Start address"
line.long 0x04 "RTPRAM1REG2,RTP RAM 1 Trace Region 2 Register"
bitfld.long 0x04 29.--30. " CPU_DMA ,CPU and/or DMA access" "Any,CPU,DMA,?..."
bitfld.long 0x04 28. " RW ,Read/write" "Read,Write"
bitfld.long 0x04 24.--27. " BLOCKSIZE ,Blocksize" "0,256 B,512 B,1k B,2k B,4k B,8k B,16k B,32k B,64k B,128k B,256k B,?..."
hexmask.long.tbyte 0x04 0.--17. 1. " STARTADDR ,Start address"
line.long 0x08 "RTPRAM2REG1,RTP RAM 2 Trace Region 1 Register"
bitfld.long 0x08 29.--30. " CPU_DMA ,CPU and/or DMA access" "Any,CPU,DMA,?..."
bitfld.long 0x08 28. " RW ,Read/write" "Read,Write"
bitfld.long 0x08 24.--27. " BLOCKSIZE ,Blocksize" "0,256 B,512 B,1k B,2k B,4k B,8k B,16k B,32k B,64k B,128k B,256k B,?..."
hexmask.long.tbyte 0x08 0.--17. 1. " STARTADDR ,Start address"
line.long 0x0C "RTPRAM2REG2,RTP RAM 2 Trace Region 2 Register"
bitfld.long 0x0C 29.--30. " CPU_DMA ,CPU and/or DMA access" "Any,CPU,DMA,?..."
bitfld.long 0x0C 28. " RW ,Read/write" "Read,Write"
bitfld.long 0x0C 24.--27. " BLOCKSIZE ,Blocksize" "0,256 B,512 B,1k B,2k B,4k B,8k B,16k B,32k B,64k B,128k B,256k B,?..."
hexmask.long.tbyte 0x0C 0.--17. 1. " STARTADDR ,Start address"
sif (cpu()!=("TMS570LS10106-PGE")&&cpu()!=("TMS570LS10116-PGE")&&cpu()!=("TMS570LS10206-PGE")&&cpu()!=("TMS570LS10216-PGE")&&cpu()!=("TMS570LS20206-PGE")&&cpu()!=("TMS570LS20216-PGE")&&cpu()!=("TMS570LS10106-ZWT")&&cpu()!=("TMS570LS10116-ZWT")&&cpu()!=("TMS570LS10206-ZWT")&&cpu()!=("TMS570LS10216-ZWT")&&cpu()!=("TMS570LS20206-ZWT")&&cpu()!=("TMS570LS20216-ZWT")&&cpu()!="RM48L952-PGE"&&cpu()!="RM48L952-ZWT"&&cpu()!="RM48L950-PGE"&&cpu()!="RM48L950-ZWT"&&cpu()!="RM48L940-ZWT"&&cpu()!="RM48L940-PGE"&&cpu()!="RM48L930-ZWT"&&cpu()!="RM48L930-PGE"&&cpu()!="RM48L750-ZWT"&&cpu()!="RM48L750-PGE"&&cpu()!="RM48L740-ZWT"&&cpu()!="RM48L740-PGE"&&cpu()!="RM48L730-ZWT"&&cpu()!="RM48L730-PGE"&&cpu()!="RM48L550-PGE"&&cpu()!="RM48L540-ZWT"&&cpu()!="RM48L540-PGE"&&cpu()!="RM48L530-ZWT"&&cpu()!="RM48L530-PGE")
line.long 0x10 "RTPRAM3REG1,RTP RAM 3 Trace Region 1 Register"
bitfld.long 0x10 29.--30. " CPU_DMA ,CPU and/or DMA access" "Any,CPU,DMA,?..."
bitfld.long 0x10 28. " RW ,Read/write" "Read,Write"
bitfld.long 0x10 24.--27. " BLOCKSIZE ,Blocksize" "0,256 B,512 B,1k B,2k B,4k B,8k B,16k B,32k B,64k B,128k B,256k B,?..."
hexmask.long.tbyte 0x10 0.--17. 1. " STARTADDR ,Start address"
line.long 0x14 "RTPRAM3REG2,RTP RAM 3 Trace Region 2 Register"
bitfld.long 0x14 29.--30. " CPU_DMA ,CPU and/or DMA access" "Any,CPU,DMA,?..."
bitfld.long 0x14 28. " RW ,Read/write" "Read,Write"
bitfld.long 0x14 24.--27. " BLOCKSIZE ,Blocksize" "0,256 B,512 B,1k B,2k B,4k B,8k B,16k B,32k B,64k B,128k B,256k B,?..."
hexmask.long.tbyte 0x14 0.--17. 1. " STARTADDR ,Start address"
endif
line.long 0x18 "RTPPERREG1,RTP Peripheral Trace Region 1 Register"
bitfld.long 0x18 29.--30. " CPU_DMA ,CPU and/or DMA access" "Any,CPU,DMA,?..."
bitfld.long 0x18 28. " RW ,Read/write" "Read,Write"
sif (cpu()==("TMS570LS10106-PGE")||cpu()==("TMS570LS10116-PGE")||cpu()==("TMS570LS10206-PGE")||cpu()==("TMS570LS10216-PGE")||cpu()==("TMS570LS20206-PGE")||cpu()==("TMS570LS20216-PGE")||cpu()==("TMS570LS10106-ZWT")||cpu()==("TMS570LS10116-ZWT")||cpu()==("TMS570LS10206-ZWT")||cpu()==("TMS570LS10216-ZWT")||cpu()==("TMS570LS20206-ZWT")||cpu()==("TMS570LS20216-ZWT")||cpu()=="RM48L952-PGE"||cpu()=="RM48L952-ZWT"||cpu()=="RM48L950-PGE"||cpu()=="RM48L950-ZWT"||cpu()=="RM48L940-ZWT"||cpu()=="RM48L940-PGE"||cpu()=="RM48L930-ZWT"||cpu()=="RM48L930-PGE"||cpu()=="RM48L750-ZWT"||cpu()=="RM48L750-PGE"||cpu()=="RM48L740-ZWT"||cpu()=="RM48L740-PGE"||cpu()=="RM48L730-ZWT"||cpu()=="RM48L730-PGE"||cpu()=="RM48L550-PGE"||cpu()=="RM48L540-ZWT"||cpu()=="RM48L540-PGE"||cpu()=="RM48L530-ZWT"||cpu()=="RM48L530-PGE")
bitfld.long 0x00 24.--27. " BLOCKSIZE ,Trace Region Length" "0 kB,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,?..."
else
bitfld.long 0x18 24.--27. " BLOCKSIZE ,Blocksize" "0,256 B,512 B,1k B,2k B,4k B,8k B,16k B,32k B,64k B,128k B,256k B,?..."
endif
hexmask.long.tbyte 0x18 0.--23. 1. " STARTADDR ,Start address"
line.long 0x1C "RTPPERREG2,RTP Peripheral Trace Region 2 Register"
bitfld.long 0x1C 29.--30. " CPU_DMA ,CPU and/or DMA access" "Any,CPU,DMA,?..."
bitfld.long 0x1C 28. " RW ,Read/write" "Read,Write"
sif (cpu()==("TMS570LS10106-PGE")||cpu()==("TMS570LS10116-PGE")||cpu()==("TMS570LS10206-PGE")||cpu()==("TMS570LS10216-PGE")||cpu()==("TMS570LS20206-PGE")||cpu()==("TMS570LS20216-PGE")||cpu()==("TMS570LS10106-ZWT")||cpu()==("TMS570LS10116-ZWT")||cpu()==("TMS570LS10206-ZWT")||cpu()==("TMS570LS10216-ZWT")||cpu()==("TMS570LS20206-ZWT")||cpu()==("TMS570LS20216-ZWT")||cpu()=="RM48L952-PGE"||cpu()=="RM48L952-ZWT"||cpu()=="RM48L950-PGE"||cpu()=="RM48L950-ZWT"||cpu()=="RM48L940-ZWT"||cpu()=="RM48L940-PGE"||cpu()=="RM48L930-ZWT"||cpu()=="RM48L930-PGE"||cpu()=="RM48L750-ZWT"||cpu()=="RM48L750-PGE"||cpu()=="RM48L740-ZWT"||cpu()=="RM48L740-PGE"||cpu()=="RM48L730-ZWT"||cpu()=="RM48L730-PGE"||cpu()=="RM48L550-PGE"||cpu()=="RM48L540-ZWT"||cpu()=="RM48L540-PGE"||cpu()=="RM48L530-ZWT"||cpu()=="RM48L530-PGE")
bitfld.long 0x00 24.--27. " BLOCKSIZE ,Trace Region Length" "0 kB,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,?..."
else
bitfld.long 0x1C 24.--27. " BLOCKSIZE ,Blocksize" "0,256 B,512 B,1k B,2k B,4k B,8k B,16k B,32k B,64k B,128k B,256k B,?..."
endif
hexmask.long.tbyte 0x1C 0.--23. 1. " STARTADDR ,Start address"
line.long 0x20 "RTPDDMW,RTP Direct Data Mode Write Register"
group.long 0x34++0x07
line.long 0x00 "RTPPC0,RTP Pin Control 0"
bitfld.long 0x00 18. " ENAFUNC ,Functional mode of RTPENA pin" "GIO mode,Functional mode"
bitfld.long 0x00 17. " CLKFUNC ,Functional mode of RTPCLK pin" "GIO mode,Functional mode"
bitfld.long 0x00 16. " SYNCFUNC ,Functional mode of RTPSYNC pin" "GIO mode,Functional mode"
textline " "
bitfld.long 0x00 15. " DATAFUNC ,Output state of RTPDATA pin 15" "GIO,Functional"
bitfld.long 0x00 14. " DATAFUNC ,Output state of RTPDATA pin 14" "GIO,Functional"
bitfld.long 0x00 13. " DATAFUNC ,Output state of RTPDATA pin 13" "GIO,Functional"
textline " "
bitfld.long 0x00 12. " DATAFUNC ,Output state of RTPDATA pin 12" "GIO,Functional"
bitfld.long 0x00 11. " DATAFUNC ,Output state of RTPDATA pin 11" "GIO,Functional"
bitfld.long 0x00 10. " DATAFUNC ,Output state of RTPDATA pin 10" "GIO,Functional"
textline " "
bitfld.long 0x00 9. " DATAFUNC ,Output state of RTPDATA pin 9" "GIO,Functional"
bitfld.long 0x00 8. " DATAFUNC ,Output state of RTPDATA pin 8" "GIO,Functional"
bitfld.long 0x00 7. " DATAFUNC ,Output state of RTPDATA pin 7" "GIO,Functional"
textline " "
bitfld.long 0x00 6. " DATAFUNC ,Output state of RTPDATA pin 6" "GIO,Functional"
bitfld.long 0x00 5. " DATAFUNC ,Output state of RTPDATA pin 5" "GIO,Functional"
bitfld.long 0x00 4. " DATAFUNC ,Output state of RTPDATA pin 4" "GIO,Functional"
textline " "
bitfld.long 0x00 3. " DATAFUNC ,Output state of RTPDATA pin 3" "GIO,Functional"
bitfld.long 0x00 2. " DATAFUNC ,Output state of RTPDATA pin 2" "GIO,Functional"
bitfld.long 0x00 1. " DATAFUNC ,Output state of RTPDATA pin 1" "GIO,Functional"
textline " "
bitfld.long 0x00 0. " DATAFUNC ,Output state of RTPDATA pin 0" "GIO,Functional"
line.long 0x04 "RTPPC1,RTP Pin Control 1"
bitfld.long 0x04 18. " ENADIR ,Direction of RTPENA pin" "Input,Output"
bitfld.long 0x04 17. " CLKDIR ,Direction of RTPCLK pin" "Input,Output"
bitfld.long 0x04 16. " SYNCDIR ,Direction of RTPSYNC pin" "Input,Output"
textline " "
bitfld.long 0x04 15. " DATADIR ,Output state of RTPDATA pin 15" "Input,Output"
bitfld.long 0x04 14. " DATADIR ,Output state of RTPDATA pin 14" "Input,Output"
bitfld.long 0x04 13. " DATADIR ,Output state of RTPDATA pin 13" "Input,Output"
textline " "
bitfld.long 0x04 12. " DATADIR ,Output state of RTPDATA pin 12" "Input,Output"
bitfld.long 0x04 11. " DATADIR ,Output state of RTPDATA pin 11" "Input,Output"
bitfld.long 0x04 10. " DATADIR ,Output state of RTPDATA pin 10" "Input,Output"
textline " "
bitfld.long 0x04 9. " DATADIR ,Output state of RTPDATA pin 9" "Input,Output"
bitfld.long 0x04 8. " DATADIR ,Output state of RTPDATA pin 8" "Input,Output"
bitfld.long 0x04 7. " DATADIR ,Output state of RTPDATA pin 7" "Input,Output"
textline " "
bitfld.long 0x04 6. " DATADIR ,Output state of RTPDATA pin 6" "Input,Output"
bitfld.long 0x04 5. " DATADIR ,Output state of RTPDATA pin 5" "Input,Output"
bitfld.long 0x04 4. " DATADIR ,Output state of RTPDATA pin 4" "Input,Output"
textline " "
bitfld.long 0x04 3. " DATADIR ,Output state of RTPDATA pin 3" "Input,Output"
bitfld.long 0x04 2. " DATADIR ,Output state of RTPDATA pin 2" "Input,Output"
bitfld.long 0x04 1. " DATADIR ,Output state of RTPDATA pin 1" "Input,Output"
textline " "
bitfld.long 0x04 0. " DATADIR ,Output state of RTPDATA pin 0" "Input,Output"
rgroup.long 0x3C++0x03
line.long 0x00 "RTPPC2,RTP Pin Control 2"
bitfld.long 0x00 18. " ENAIN ,State of RTPENA pin" "Low,High"
bitfld.long 0x00 17. " CLKIN ,State of RTPCLK pin" "Low,High"
bitfld.long 0x00 16. " SYNCIN ,State of RTPSYNC pin" "Low,High"
textline " "
bitfld.long 0x00 15. " DATAIN ,Output state of RTPDATA pin 15" "Low,High"
bitfld.long 0x00 14. " DATAIN ,Output state of RTPDATA pin 14" "Low,High"
bitfld.long 0x00 13. " DATAIN ,Output state of RTPDATA pin 13" "Low,High"
textline " "
bitfld.long 0x00 12. " DATAIN ,Output state of RTPDATA pin 12" "Low,High"
bitfld.long 0x00 11. " DATAIN ,Output state of RTPDATA pin 11" "Low,High"
bitfld.long 0x00 10. " DATAIN ,Output state of RTPDATA pin 10" "Low,High"
textline " "
bitfld.long 0x00 9. " DATAIN ,Output state of RTPDATA pin 9" "Low,High"
bitfld.long 0x00 8. " DATAIN ,Output state of RTPDATA pin 8" "Low,High"
bitfld.long 0x00 7. " DATAIN ,Output state of RTPDATA pin 7" "Low,High"
textline " "
bitfld.long 0x00 6. " DATAIN ,Output state of RTPDATA pin 6" "Low,High"
bitfld.long 0x00 5. " DATAIN ,Output state of RTPDATA pin 5" "Low,High"
bitfld.long 0x00 4. " DATAIN ,Output state of RTPDATA pin 4" "Low,High"
textline " "
bitfld.long 0x00 3. " DATAIN ,Output state of RTPDATA pin 3" "Low,High"
bitfld.long 0x00 2. " DATAIN ,Output state of RTPDATA pin 2" "Low,High"
bitfld.long 0x00 1. " DATAIN ,Output state of RTPDATA pin 1" "Low,High"
textline " "
bitfld.long 0x00 0. " DATAIN ,Output state of RTPDATA pin 0" "Low,High"
group.long 0x40++0x17
line.long 0x00 "RTPPC3,RTP Pin Control 3"
bitfld.long 0x00 18. " ENAOUT ,Output state of RTPENA pin" "Low,High"
bitfld.long 0x00 17. " CLKOUT ,Output state of RTPCLK pin" "Low,High"
sif (cpu()=="TMS570LC4357"||cpu()=="RM57L843-ZWT"||cpu()=="TMS570PSFC66")
bitfld.long 0x00 16. " SYNCOUT ,Output state of RTPSYNC pins" "Low,High"
else
bitfld.long 0x00 16. " DATAOUT ,Output state of RTPDATA pins" "Low,High"
endif
textline " "
bitfld.long 0x00 15. " DATAOUT ,Output state of RTPDATA pin 15" "Push/pull,Open drain"
bitfld.long 0x00 14. " DATAOUT ,Output state of RTPDATA pin 14" "Push/pull,Open drain"
bitfld.long 0x00 13. " DATAOUT ,Output state of RTPDATA pin 13" "Push/pull,Open drain"
textline " "
bitfld.long 0x00 12. " DATAOUT ,Output state of RTPDATA pin 12" "Push/pull,Open drain"
bitfld.long 0x00 11. " DATAOUT ,Output state of RTPDATA pin 11" "Push/pull,Open drain"
bitfld.long 0x00 10. " DATAOUT ,Output state of RTPDATA pin 10" "Push/pull,Open drain"
textline " "
bitfld.long 0x00 9. " DATAOUT ,Output state of RTPDATA pin 9" "Push/pull,Open drain"
bitfld.long 0x00 8. " DATAOUT ,Output state of RTPDATA pin 8" "Push/pull,Open drain"
bitfld.long 0x00 7. " DATAOUT ,Output state of RTPDATA pin 7" "Push/pull,Open drain"
textline " "
bitfld.long 0x00 6. " DATAOUT ,Output state of RTPDATA pin 6" "Push/pull,Open drain"
bitfld.long 0x00 5. " DATAOUT ,Output state of RTPDATA pin 5" "Push/pull,Open drain"
bitfld.long 0x00 4. " DATAOUT ,Output state of RTPDATA pin 4" "Push/pull,Open drain"
textline " "
bitfld.long 0x00 3. " DATAOUT ,Output state of RTPDATA pin 3" "Push/pull,Open drain"
bitfld.long 0x00 2. " DATAOUT ,Output state of RTPDATA pin 2" "Push/pull,Open drain"
bitfld.long 0x00 1. " DATAOUT ,Output state of RTPDATA pin 1" "Push/pull,Open drain"
textline " "
bitfld.long 0x00 0. " DATAOUT ,Output state of RTPDATA pin 0" "Push/pull,Open drain"
line.long 0x04 "RTPPC4,RTP Pin Control 4"
bitfld.long 0x04 18. " ENASET ,Set output state of RTPENA pin to logic high" "No change,Set high"
bitfld.long 0x04 17. " CLKSET ,Set output state of RTPCLK pin to logic high" "No change,Set high"
bitfld.long 0x04 16. " SYNCSET ,Set output state of RTPSYNC pin to logic high" "No change,Set high"
textline " "
bitfld.long 0x04 15. " DATASET ,Output state of RTPDATA pin 15" "Low,High"
bitfld.long 0x04 14. " DATASET ,Output state of RTPDATA pin 14" "Low,High"
bitfld.long 0x04 13. " DATASET ,Output state of RTPDATA pin 13" "Low,High"
textline " "
bitfld.long 0x04 12. " DATASET ,Output state of RTPDATA pin 12" "Low,High"
bitfld.long 0x04 11. " DATASET ,Output state of RTPDATA pin 11" "Low,High"
bitfld.long 0x04 10. " DATASET ,Output state of RTPDATA pin 10" "Low,High"
textline " "
bitfld.long 0x04 9. " DATASET ,Output state of RTPDATA pin 9" "Low,High"
bitfld.long 0x04 8. " DATASET ,Output state of RTPDATA pin 8" "Low,High"
bitfld.long 0x04 7. " DATASET ,Output state of RTPDATA pin 7" "Low,High"
textline " "
bitfld.long 0x04 6. " DATASET ,Output state of RTPDATA pin 6" "Low,High"
bitfld.long 0x04 5. " DATASET ,Output state of RTPDATA pin 5" "Low,High"
bitfld.long 0x04 4. " DATASET ,Output state of RTPDATA pin 4" "Low,High"
textline " "
bitfld.long 0x04 3. " DATASET ,Output state of RTPDATA pin 3" "Low,High"
bitfld.long 0x04 2. " DATASET ,Output state of RTPDATA pin 2" "Low,High"
bitfld.long 0x04 1. " DATASET ,Output state of RTPDATA pin 1" "Low,High"
textline " "
bitfld.long 0x04 0. " DATASET ,Output state of RTPDATA pin 0" "Low,High"
line.long 0x08 "RTPPC5,RTP Pin Control 5"
bitfld.long 0x08 18. " ENACLR ,Set output state of RTPENA pin to logic low" "No change,Set low"
bitfld.long 0x08 17. " CLKCLR ,Set output state of RTPCLK pin to logic low" "No change,Set low"
bitfld.long 0x08 16. " SYNCCLR ,Set output state of RTPSYNC pin to logic low" "No change,Set low"
textline " "
bitfld.long 0x08 15. " DATACLR ,Output state of RTPDATA pin 15" "Low,High"
bitfld.long 0x08 14. " DATACLR ,Output state of RTPDATA pin 14" "Low,High"
bitfld.long 0x08 13. " DATACLR ,Output state of RTPDATA pin 13" "Low,High"
textline " "
bitfld.long 0x08 12. " DATACLR ,Output state of RTPDATA pin 12" "Low,High"
bitfld.long 0x08 11. " DATACLR ,Output state of RTPDATA pin 11" "Low,High"
bitfld.long 0x08 10. " DATACLR ,Output state of RTPDATA pin 10" "Low,High"
textline " "
bitfld.long 0x08 9. " DATACLR ,Output state of RTPDATA pin 9" "Low,High"
bitfld.long 0x08 8. " DATACLR ,Output state of RTPDATA pin 8" "Low,High"
bitfld.long 0x08 7. " DATACLR ,Output state of RTPDATA pin 7" "Low,High"
textline " "
bitfld.long 0x08 6. " DATACLR ,Output state of RTPDATA pin 6" "Low,High"
bitfld.long 0x08 5. " DATACLR ,Output state of RTPDATA pin 5" "Low,High"
bitfld.long 0x08 4. " DATACLR ,Output state of RTPDATA pin 4" "Low,High"
textline " "
bitfld.long 0x08 3. " DATACLR ,Output state of RTPDATA pin 3" "Low,High"
bitfld.long 0x08 2. " DATACLR ,Output state of RTPDATA pin 2" "Low,High"
bitfld.long 0x08 1. " DATACLR ,Output state of RTPDATA pin 1" "Low,High"
textline " "
bitfld.long 0x08 0. " DATACLR ,Output state of RTPDATA pin 0" "Low,High"
line.long 0x0C "RTPPC6,RTP Pin Control 6"
bitfld.long 0x0C 18. " ENAPDR ,Open drain enable of RTPENA pin" "Normal mode,Open drain"
bitfld.long 0x0C 17. " CLKPDR ,Open drain enable of RTPCLK pin" "Normal mode,Open drain"
bitfld.long 0x0C 16. " SYNCPDR ,Open drain enable of RTPSYNC pin" "Normal mode,Open drain"
textline " "
bitfld.long 0x0C 15. " DATAPDR ,Output state of RTPDATA pin 15" "Push/pull,Open drain"
bitfld.long 0x0C 14. " DATAPDR ,Output state of RTPDATA pin 14" "Push/pull,Open drain"
bitfld.long 0x0C 13. " DATAPDR ,Output state of RTPDATA pin 13" "Push/pull,Open drain"
textline " "
bitfld.long 0x0C 12. " DATAPDR ,Output state of RTPDATA pin 12" "Push/pull,Open drain"
bitfld.long 0x0C 11. " DATAPDR ,Output state of RTPDATA pin 11" "Push/pull,Open drain"
bitfld.long 0x0C 10. " DATAPDR ,Output state of RTPDATA pin 10" "Push/pull,Open drain"
textline " "
bitfld.long 0x0C 9. " DATAPDR ,Output state of RTPDATA pin 9" "Push/pull,Open drain"
bitfld.long 0x0C 8. " DATAPDR ,Output state of RTPDATA pin 8" "Push/pull,Open drain"
bitfld.long 0x0C 7. " DATAPDR ,Output state of RTPDATA pin 7" "Push/pull,Open drain"
textline " "
bitfld.long 0x0C 6. " DATAPDR ,Output state of RTPDATA pin 6" "Push/pull,Open drain"
bitfld.long 0x0C 5. " DATAPDR ,Output state of RTPDATA pin 5" "Push/pull,Open drain"
bitfld.long 0x0C 4. " DATAPDR ,Output state of RTPDATA pin 4" "Push/pull,Open drain"
textline " "
bitfld.long 0x0C 3. " DATAPDR ,Output state of RTPDATA pin 3" "Push/pull,Open drain"
bitfld.long 0x0C 2. " DATAPDR ,Output state of RTPDATA pin 2" "Push/pull,Open drain"
bitfld.long 0x0C 1. " DATAPDR ,Output state of RTPDATA pin 1" "Push/pull,Open drain"
textline " "
bitfld.long 0x0C 0. " DATAPDR ,Output state of RTPDATA pin 0" "Push/pull,Open drain"
line.long 0x10 "RTPPC7,RTP Pin Control 7"
sif (cpu()=="TMS570LC4357"||cpu()=="RM57L843-ZWT")
bitfld.long 0x10 18. " ENADIS ,Pull-up/pull-down functionality of RTPENA pin disabled" "No,Yes"
bitfld.long 0x10 17. " CLKDIS ,Pull-up/pull-down functionality of RTPCLK pin disabled" "No,Yes"
bitfld.long 0x10 16. " SYNCDIS ,Pull-up/pull-down functionality of RTPSYNC pin disabled" "No,Yes"
else
bitfld.long 0x10 18. " ENAPDIS ,Pull-up/pull-down functionality of RTPENA pin disabled" "No,Yes"
bitfld.long 0x10 17. " CLKPDIS ,Pull-up/pull-down functionality of RTPCLK pin disabled" "No,Yes"
bitfld.long 0x10 16. " SYNCPDIS ,Pull-up/pull-down functionality of RTPSYNC pin disabled" "No,Yes"
endif
textline " "
bitfld.long 0x10 15. " DATADIS ,Output state of RTPDATA pin 15" "Enabled,Disabled"
bitfld.long 0x10 14. " DATADIS ,Output state of RTPDATA pin 14" "Enabled,Disabled"
bitfld.long 0x10 13. " DATADIS ,Output state of RTPDATA pin 13" "Enabled,Disabled"
textline " "
bitfld.long 0x10 12. " DATADIS ,Output state of RTPDATA pin 12" "Enabled,Disabled"
bitfld.long 0x10 11. " DATADIS ,Output state of RTPDATA pin 11" "Enabled,Disabled"
bitfld.long 0x10 10. " DATADIS ,Output state of RTPDATA pin 10" "Enabled,Disabled"
textline " "
bitfld.long 0x10 9. " DATADIS ,Output state of RTPDATA pin 9" "Enabled,Disabled"
bitfld.long 0x10 8. " DATADIS ,Output state of RTPDATA pin 8" "Enabled,Disabled"
bitfld.long 0x10 7. " DATADIS ,Output state of RTPDATA pin 7" "Enabled,Disabled"
textline " "
bitfld.long 0x10 6. " DATADIS ,Output state of RTPDATA pin 6" "Enabled,Disabled"
bitfld.long 0x10 5. " DATADIS ,Output state of RTPDATA pin 5" "Enabled,Disabled"
bitfld.long 0x10 4. " DATADIS ,Output state of RTPDATA pin 4" "Enabled,Disabled"
textline " "
bitfld.long 0x10 3. " DATADIS ,Output state of RTPDATA pin 3" "Enabled,Disabled"
bitfld.long 0x10 2. " DATADIS ,Output state of RTPDATA pin 2" "Enabled,Disabled"
bitfld.long 0x10 1. " DATADIS ,Output state of RTPDATA pin 1" "Enabled,Disabled"
textline " "
bitfld.long 0x10 0. " DATADIS ,Output state of RTPDATA pin 0" "Enabled,Disabled"
line.long 0x14 "RTPPC8,RTP Pin Control 8"
bitfld.long 0x14 18. " ENAPSEL ,Pull select of RTPENA pin" "Pull-down,Pull-up"
bitfld.long 0x14 17. " CLKPSEL ,Pull select of RTPCLK pin" "Pull-down,Pull-up"
bitfld.long 0x14 16. " SYNCPSEL ,Pull select of RTPSYNC pin" "Pull-down,Pull-up"
textline " "
bitfld.long 0x14 15. " DATAPSEL ,Output state of RTPDATA pin 15" "Pull-down,Pull-up"
bitfld.long 0x14 14. " DATAPSEL ,Output state of RTPDATA pin 14" "Pull-down,Pull-up"
bitfld.long 0x14 13. " DATAPSEL ,Output state of RTPDATA pin 13" "Pull-down,Pull-up"
textline " "
bitfld.long 0x14 12. " DATAPSEL ,Output state of RTPDATA pin 12" "Pull-down,Pull-up"
bitfld.long 0x14 11. " DATAPSEL ,Output state of RTPDATA pin 11" "Pull-down,Pull-up"
bitfld.long 0x14 10. " DATAPSEL ,Output state of RTPDATA pin 10" "Pull-down,Pull-up"
textline " "
bitfld.long 0x14 9. " DATAPSEL ,Output state of RTPDATA pin 9" "Pull-down,Pull-up"
bitfld.long 0x14 8. " DATAPSEL ,Output state of RTPDATA pin 8" "Pull-down,Pull-up"
bitfld.long 0x14 7. " DATAPSEL ,Output state of RTPDATA pin 7" "Pull-down,Pull-up"
textline " "
bitfld.long 0x14 6. " DATAPSEL ,Output state of RTPDATA pin 6" "Pull-down,Pull-up"
bitfld.long 0x14 5. " DATAPSEL ,Output state of RTPDATA pin 5" "Pull-down,Pull-up"
bitfld.long 0x14 4. " DATAPSEL ,Output state of RTPDATA pin 4" "Pull-down,Pull-up"
textline " "
bitfld.long 0x14 3. " DATAPSEL ,Output state of RTPDATA pin 3" "Pull-down,Pull-up"
bitfld.long 0x14 2. " DATAPSEL ,Output state of RTPDATA pin 2" "Pull-down,Pull-up"
bitfld.long 0x14 1. " DATAPSEL ,Output state of RTPDATA pin 1" "Pull-down,Pull-up"
textline " "
bitfld.long 0x14 0. " DATAPSEL ,Output state of RTPDATA pin 0" "Pull-down,Pull-up"
sif (cpu()!="TMS570LC4357"&&cpu()!="RM57L843-ZWT")
group.long 0x58++0x03
line.long 0x00 "RTPIODFTCTRL,RTP IODFT Control"
hexmask.long.byte 0x00 8.--11. 1. " IODFTENA ,IO DFT enable"
bitfld.long 0x00 1. " LBENA ,Loop back enable" "Analog,Digital"
endif
endif
width 0x0B
tree.end
tree "eFuse (Enhanced Fuse Controller)"
base ad:0xFFF8C000
sif cpuis("TMS570LS0232")||cpuis("TMS570LS0714*")||cpuis("TMS570LS0914*")
endian.be
endif
width 14.
group.long 0x1C++0x03
line.long 0x00 "EFCBOUND,EFC Boundary Control Register"
bitfld.long 0x00 21. " EFC_SELF_TEST_ERROR ,Self error test (If(self_test_error_oe is high))" "Low,High"
bitfld.long 0x00 20. " EFC_SINGLE_ERROR ,Single bit error (If(single_error_oe is high))" "Low,High"
bitfld.long 0x00 19. " EFC_INSTRUCTION_ERROR ,Instruction error (If(instruction_error_oe is high))" "Low,High"
newline
bitfld.long 0x00 18. " EFC_AUTOLOAD_ERROR ,Autoload error (If(autoload_error_oe is high))" "Low,High"
bitfld.long 0x00 17. " SELF_TEST_ERROR_OE ,Self test error output enable" "Efuse controller,Boundary register"
bitfld.long 0x00 16. " SINGLE_ERROR_OE ,Single bit error output enable" "Efuse controller,Boundary register"
newline
bitfld.long 0x00 15. " INSTRUCTION_ERROR_OE ,Instruction error output enable" "Efuse controller,Boundary register"
bitfld.long 0x00 14. " AUTOLOAD_ERROR_OE ,Autoload error output enable" "Efuse controller,Boundary register"
bitfld.long 0x00 13. " EFC_ECC_SELFTEST_ENABLE ,Starts the selftest of the ECC logic (If EFCBOUND = 0xf)" "No action,Start ECC selftest"
newline
bitfld.long 0x00 0.--3. " EFCBOUND[3:0] ,Input enable" "Not started,Not started,Not started,Not started,Not started,Not started,Not started,Not started,Not started,Not started,Not started,Not started,Not started,Not started,Not started,Started"
rgroup.long 0x2C++0x03
line.long 0x00 "EFCPINS,EFC Pins Register"
bitfld.long 0x00 15. " EFC_SELFTEST_DONE ,Determine EFC ECC selftest complete" "Not done,Done"
bitfld.long 0x00 14. " EFC_SELFTEST_ERROR ,Determine EFC ECC selftest pass/fail" "No error,Error"
bitfld.long 0x00 12. " EFC_SINGLE_BIT_ERROR ,Determine single bit error" "No error,Error detected/corrected"
newline
bitfld.long 0x00 11. " EFC_INSTRUCTION_ERROR ,Error during factory test/program operation" "No error,Error"
bitfld.long 0x00 10. " EFC_AUTOLOAD_ERROR ,Non-Correctable error" "No error,Errors"
group.long 0x3C++0x03
line.long 0x00 "EFC_ERR_STAT,EFC Error Status Register"
bitfld.long 0x00 5. " INSTRUC_DONE ,Instruction done" "Not done,Done"
bitfld.long 0x00 0.--4. " ERROR_CODE ,Error status" "No error,,,,,Uncorrectable error,,,,,,,,,,,,,,,,Single bit error,,,Signature fail,?..."
group.long 0x48++0x07
line.long 0x00 "EFC_ST_CY,EFC Self Test Cycles Register"
line.long 0x04 "EFC_ST_SIG,EFC Self Test Signature Register"
sif cpuis("TMS570LS0232")||cpuis("TMS570LS0714*")||cpuis("TMS570LS0914*")
endian.le
endif
width 0x0B
tree.end
textline ""
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